diff --git a/.clang-format b/.clang-format index 30fa661f1..e85c367d7 100644 --- a/.clang-format +++ b/.clang-format @@ -1,18 +1,47 @@ -# Tested with Ubuntu clang-format version 14.0.0-1ubuntu1.1 - -BreakBeforeBinaryOperators: All - -ColumnLimit: 120 - +# Language conformance: C11 +# Using Cpp as a language is ok here, since there is no separate C formatter. +# It is common to use Cpp for C code formatting in clang-format. +Language: Cpp +Standard: Cpp11 BasedOnStyle: Google +# --- BRACE STYLE --- +# "Functions... opening brace on new line" +# "if, for, while... opening brace on the same line" BreakBeforeBraces: Stroustrup +# --- INDENTATION & WIDTH --- +ColumnLimit: 103 + +# "You shall indent the code with 4 spaces" IndentWidth: 4 +TabWidth: 4 +UseTab: Never +ContinuationIndentWidth: 4 +# --- POINTERS --- +# Google defaults to Left, but guidelines show Right (void *p) PointerAlignment: Right +DerivePointerAlignment: false + +# --- SPECIFIC TROPIC SQUARE RULES --- +# "You shall place braces around the single statement" +# Valid since Clang-Format 15 +InsertBraces: true + +# "You shall put spaces after... if, switch..." +SpaceBeforeParens: ControlStatements +# "You shall not add spaces around (inside) parenthesized expressions" +SpacesInParentheses: false + +# "Space on each side of most binary and ternary operators" +# Note: "SpacesInBinaryOperators" is implicit in Google style, no key needed. +SpaceBeforeAssignmentOperators: true -# # Insert New line at EOF if missing -#InsertNewlineAtEOF: true -# # Set EOL to LF unconditionally -#LineEnding: LF \ No newline at end of file +# Misc Cleanup +SortIncludes: true +IndentCaseLabels: true +# Keep operators at the end of the line +BreakBeforeBinaryOperators: None +# Make breaking at '=' very expensive so it forces breaks inside arguments instead +PenaltyBreakAssignment: 100 \ No newline at end of file diff --git a/.github/workflows/clang_format_check.yml b/.github/workflows/clang_format_check.yml index f45d3aab2..6924da1b4 100644 --- a/.github/workflows/clang_format_check.yml +++ b/.github/workflows/clang_format_check.yml @@ -6,11 +6,15 @@ on: - develop paths: - '**.c' + - '**.cpp' - '**.h' + - '**.hpp' pull_request: paths: - '**.c' + - '**.cpp' - '**.h' + - '**.hpp' jobs: check-format: @@ -21,7 +25,9 @@ jobs: uses: actions/checkout@v4 - name: Install clang-format - run: sudo apt install -y clang-format + run: | + sudo apt-get update + sudo apt-get install -y clang-format - name: Get files and check format run: | @@ -31,7 +37,7 @@ jobs: echo "Formatting issue in $f" exit_code=1 fi - done < <(find . -type f \( -name '*.c' -o -name '*.h' \) ! -path './vendor/*' ! -path './vendor/**' ! -path '*Vendor/*' ! -path '*_deps/*' ! -path './.git/*' -print0) + done < <(find . -type f \( -name '*.c' -o -name '*.cpp' -o -name '*.h' -o -name '*.hpp' \) ! -path './vendor/*' ! -path './vendor/**' ! -path '*Vendor/*' ! -path '*_deps/*' ! -path './.git/*' -print0) if [ $exit_code -ne 0 ]; then echo "Clang-format check failed." diff --git a/.github/workflows/coverage.yml b/.github/workflows/coverage.yml index de5715fcd..8e7bfdbf2 100644 --- a/.github/workflows/coverage.yml +++ b/.github/workflows/coverage.yml @@ -42,6 +42,7 @@ jobs: - name: Install dependencies run: | + sudo apt-get update sudo apt-get install cmake build-essential ninja-build ./tests/functional/model/download_deps.sh ./scripts/tropic01_model/install_linux.sh diff --git a/.github/workflows/functional_mock_tests.yml b/.github/workflows/functional_mock_tests.yml index 90d83095b..3178470d0 100644 --- a/.github/workflows/functional_mock_tests.yml +++ b/.github/workflows/functional_mock_tests.yml @@ -26,6 +26,7 @@ jobs: - name: Install dependencies run: | + sudo apt-get update sudo apt-get install cmake build-essential ninja-build pip install jsonschema jinja2 @@ -58,6 +59,7 @@ jobs: - name: Install dependencies run: | + sudo apt-get update sudo apt-get install cmake build-essential valgrind ninja-build pip install jsonschema jinja2 diff --git a/.github/workflows/integration_tests.yml b/.github/workflows/integration_tests.yml index 1880d1d1a..180c36b78 100644 --- a/.github/workflows/integration_tests.yml +++ b/.github/workflows/integration_tests.yml @@ -26,6 +26,7 @@ jobs: - name: Install dependencies run: | + sudo apt-get update sudo apt-get install cmake build-essential ninja-build ./tests/functional/model/download_deps.sh ./scripts/tropic01_model/install_linux.sh @@ -69,6 +70,7 @@ jobs: - name: Install dependencies run: | + sudo apt-get update sudo apt-get install cmake build-essential valgrind ninja-build ./tests/functional/model/download_deps.sh ./scripts/tropic01_model/install_linux.sh diff --git a/.github/workflows/linux_build_examples.yml b/.github/workflows/linux_build_examples.yml index 5c5310d0f..14da2e3ee 100644 --- a/.github/workflows/linux_build_examples.yml +++ b/.github/workflows/linux_build_examples.yml @@ -24,6 +24,7 @@ jobs: - name: Install dependencies run: | + sudo apt-get update sudo apt-get install cmake build-essential ninja-build pip3 install jsonschema @@ -41,6 +42,10 @@ jobs: cmake ./ -B build -G Ninja cd build && ninja + cd ../../full_chain_verification + cmake ./ -B build -G Ninja + cd build && ninja + - name: Build USB Devkit examples run: | cd examples/linux/usb_devkit/hello_world diff --git a/.github/workflows/model_run_examples.yml b/.github/workflows/model_run_examples.yml index 31ef443ab..3686d8f70 100644 --- a/.github/workflows/model_run_examples.yml +++ b/.github/workflows/model_run_examples.yml @@ -24,6 +24,7 @@ jobs: - name: Install dependencies run: | + sudo apt-get update sudo apt-get install cmake build-essential valgrind ninja-build ./tests/functional/model/download_deps.sh ./scripts/tropic01_model/install_linux.sh diff --git a/.github/workflows/release_new_version.yml b/.github/workflows/release_new_version.yml index cf757318a..44cb1c239 100644 --- a/.github/workflows/release_new_version.yml +++ b/.github/workflows/release_new_version.yml @@ -72,6 +72,7 @@ jobs: - name: Install dependencies run: | + sudo apt-get update sudo apt-get install doxygen graphviz pip install -r docs/requirements.txt diff --git a/.github/workflows/static_analysis.yml b/.github/workflows/static_analysis.yml index a9af75f81..96e6671fe 100644 --- a/.github/workflows/static_analysis.yml +++ b/.github/workflows/static_analysis.yml @@ -17,6 +17,7 @@ jobs: steps: - name: Install dependencies run: | + sudo apt-get update sudo apt-get install cmake build-essential cppcheck - name: Checkout Repository diff --git a/.github/workflows/stm32_build_examples.yml b/.github/workflows/stm32_build_examples.yml index 224f8d715..3c5285b1c 100644 --- a/.github/workflows/stm32_build_examples.yml +++ b/.github/workflows/stm32_build_examples.yml @@ -24,6 +24,7 @@ jobs: - name: Install dependencies run: | + sudo apt-get update sudo apt-get install cmake build-essential ninja-build gcc-arm-none-eabi pip3 install jsonschema diff --git a/CHANGELOG.md b/CHANGELOG.md index 4e9f64f9a..e430a38c4 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -5,6 +5,25 @@ All notable changes to this project will be documented in this file. The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.1.0/), and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). +## [3.2.0] + +### Changed +- Renamed `lt_secure_memzero.h` to `libtropic_secure_memzero.h` and moved it to `include/`, so it is available in HAL. + +### Added +- Examples: Added full certificate chain verification example for Linux SPI. +- HAL: HAL for STM32U5xx series +- Documentation: new tutorial for the TROPIC01 model - **Understanding Libtropic**. + +### Fixed +- Size of `l3_chunk` member of `lt_l2_encrypted_cmd_req_t` and `lt_l2_encrypted_cmd_rsp_t` structs to `TR01_L2_CHUNK_MAX_DATA_SIZE`. +- `hal/`: don't include `libtropic_port.h` in HAL headers if not used. +- `lt_init()` is successful even if TROPIC01 has invalid Application FW, so Libtropic can be used in Start-up Mode. +- STM32: securely wipe secrets when generating random numbers. +- STM32: change type of `baudrate_prescaler` (inside `lt_dev_stm32_nucleo_f439zi_t` and `lt_dev_stm32_nucleo_l432kc_t`) to `uint32_t`. + +### Removed + ## [3.1.0] ### Changed diff --git a/CMakeLists.txt b/CMakeLists.txt index 27d14a671..3dbc817ce 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -113,7 +113,7 @@ get_directory_property(HAS_PARENT_SCOPE PARENT_DIRECTORY) ########################################################################### project(libtropic_SDK - VERSION 3.1.0 + VERSION 3.2.0 DESCRIPTION "TROPIC01 software development kit" HOMEPAGE_URL "https://tropicsquare.github.io/libtropic/latest/" LANGUAGES C) @@ -134,7 +134,7 @@ set(SDK_SRCS ${SDK_SRCS} ${CMAKE_CURRENT_SOURCE_DIR}/src/lt_asn1_der.c ${CMAKE_CURRENT_SOURCE_DIR}/src/libtropic_default_sh0_keys.c ${CMAKE_CURRENT_SOURCE_DIR}/src/lt_tr01_attrs.c - ${CMAKE_CURRENT_SOURCE_DIR}/src/lt_secure_memzero.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/libtropic_secure_memzero.c ) set(SDK_INCS ${SDK_INCS} @@ -143,6 +143,7 @@ set(SDK_INCS ${SDK_INCS} ${CMAKE_CURRENT_SOURCE_DIR}/include/libtropic_port.h ${CMAKE_CURRENT_SOURCE_DIR}/include/libtropic_l2.h ${CMAKE_CURRENT_SOURCE_DIR}/include/libtropic_l3.h + ${CMAKE_CURRENT_SOURCE_DIR}/include/libtropic_secure_memzero.h ${CMAKE_CURRENT_SOURCE_DIR}/src/lt_crc16.h ${CMAKE_CURRENT_SOURCE_DIR}/src/lt_port_wrap.h ${CMAKE_CURRENT_SOURCE_DIR}/src/lt_l1.h diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index fcbeb0e76..65580d58c 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -5,7 +5,7 @@ We love contributions! To make contributing simple for both sides, please: - Create a branch from the develop branch and do the changes: - Make sure to follow specifics in our [Coding Style](#coding-style). - Make sure to use [Code Formatter](#code-formatter), otherwise the PR check will fail and cannot be merged. - - Make sure the branch passes [Tests](https://tropicsquare.github.io/libtropic/latest/for_contributors/functional_tests/) against model -- otherwise, the PR check will fail. + - Make sure the branch passes [functional tests](https://tropicsquare.github.io/libtropic/latest/for_contributors/tests/functional_tests/) against TROPIC01 Model and [functional mock tests](https://tropicsquare.github.io/libtropic/latest/for_contributors/tests/functional_mock_tests/), otherwise, the PR check will fail. - Make sure to run [Static Analysis](#static-analysis). - Make sure your [Commit Messages](#commit-messages) follow our guidelines. - Create pull request. diff --git a/README.md b/README.md index c9e77f137..90a5d1e8a 100644 --- a/README.md +++ b/README.md @@ -2,59 +2,46 @@ ![](https://github.com/tropicsquare/libtropic/actions/workflows/integration_tests.yml/badge.svg) ![](https://github.com/tropicsquare/libtropic/actions/workflows/build_docs_master.yml/badge.svg) -TROPIC01's SDK written in C. Contributors, please follow [guidelines](https://github.com/tropicsquare/libtropic/blob/master/CONTRIBUTING.md). +**Libtropic** is the official C SDK for TROPIC01, **the open and auditable secure element by [Tropic Square](https://tropicsquare.com/)**. -For more information about TROPIC01 chip and its **datasheet** or **User API**, check out developers resources in the [TROPIC01](https://github.com/tropicsquare/tropic01) repository. +The repository provides the library and integration examples for practical evaluation of the chip. For information about particular TROPIC01 part number or for general insights into TROPIC01 design, please follow the link to [TROPIC01](https://github.com/tropicsquare/tropic01) product page. -## Documentation -We recommend using the [Libtropic documentation](https://tropicsquare.github.io/libtropic/latest/) as the source of truth for getting information about Libtropic. +## Getting started -The documentation is generated only for the releases and the version can be switched via the version selector at the top of the page. +Want to learn **TROPIC01** the easy way? See our [Tutorials](https://tropicsquare.github.io/libtropic/latest/tutorials/) and start today! -## Compatibility with TROPIC01 firmware versions +## Firmware compatibility -For the Libtropic library to function correctly with the TROPIC01 secure element, the versions of four key components must be compatible: +For correct operation, these four versions must be compatible: -1. **Libtropic SDK**: The version of this library. -2. **Bootloader FW**: Bootloader firmware running on the TROPIC01's RISC-V CPU after power-up. It cannot be updated. -2. **Application FW**: Application firmware running on the TROPIC01's RISC-V CPU. It can be updated. -3. **SPECT FW**: Firmware running on the TROPIC01's SPECT co-processor. It can be updated. +1. **Libtropic SDK**: Version of this library. +2. **Bootloader FW**: Firmware running on TROPIC01 RISC-V CPU after power-up (cannot be updated). +3. **Application FW**: Firmware running on TROPIC01 RISC-V CPU (can be updated). +4. **SPECT FW**: Firmware running on the TROPIC01 SPECT co-processor (can be updated). -For more information about each of these, refer to the [TROPIC01](https://github.com/tropicsquare/tropic01) repository. +For details, see particular part number in [TROPIC01](https://github.com/tropicsquare/tropic01). -The following table outlines the tested and supported compatibility between released versions: - -| Libtropic | Application FW | SPECT FW | Bootloader FW | Tests | +| Libtropic | Application FW | SPECT FW | Bootloader FW | Tests | |:---------:|:--------------:|:--------:|:-------------:|:------------------:| | 1.0.0 | 1.0.0 | 1.0.0 | 1.0.1-2.0.1 | :white_check_mark: | | 2.0.0 | 1.0.0–1.0.1 | 1.0.0 | 2.0.1 | :white_check_mark: | | 2.0.1 | 1.0.0–1.0.1 | 1.0.0 | 2.0.1 | :white_check_mark: | | 3.0.0 | 1.0.0–2.0.0 | 1.0.0 | 2.0.1 | :white_check_mark: | | 3.1.0 | 1.0.0–2.0.0 | 1.0.0 | 2.0.1 | :white_check_mark: | +| 3.2.0 | 1.0.0–2.0.0 | 1.0.0 | 2.0.1 | :white_check_mark: | > [!WARNING] -> Using mismatched versions of the components may result in unpredictable behavior or errors. It is strongly advised to use the latest compatible versions of all components to ensure proper functionality. - -For retrieving firmware versions from TROPIC01 and updating its firmware, refer to the [Tutorials](https://tropicsquare.github.io/libtropic/latest/tutorials/) and select your platform. Follow the instructions for **Chip Identification** and **Firmware Update** example. - -## Repository structure -* `CMakeLists.txt` Root CMake project file -* `cmake/` CMake related files -* `cal/` Implementation of Crypto Abstraction Layers (CAL) for supported Cryptographic Functionality Providers (CFP) -* `docs/` [MkDocs](https://www.mkdocs.org/) Documentation deployed [here](https://tropicsquare.github.io/libtropic/latest/) -* `examples/` Example projects for each supported platform -* `hal/` Implementation of Hardware Abstraction Layers (HAL) for supported host platforms -* `include/` Public API header files -* `scripts/` Build and config scripts -* `src/` Library's source files -* `tests/` Functional tests -* `TROPIC01_fw_update_files/` Files used for updating TROPIC01's firmware -* `vendor/` Third party libraries and tools +> Mismatched component versions may cause errors or unpredictable behavior. Use the latest compatible versions whenever possible. + +To read firmware versions and update firmware, use the [Tutorials](https://tropicsquare.github.io/libtropic/latest/tutorials/) and follow **Chip Identification** and **Firmware Update**. ## FAQ -We provide the [FAQ](https://tropicsquare.github.io/libtropic/latest/faq/) section in our documentation with frequently asked questions and troubleshooting tips. + +See the [FAQ](https://tropicsquare.github.io/libtropic/latest/faq/) for common questions and troubleshooting. ## License -See the [LICENSE.md](LICENSE.md) file in the root of this repository or consult license information at [Tropic Square website](http:/tropicsquare.com/license). +See [LICENSE.md](LICENSE.md) in the repository root, or check the [Tropic Square website](https://tropicsquare.com/license). + + diff --git a/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_1_0_0/fw_CPU.h b/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_1_0_0/fw_CPU.h index e93849f76..54b170e20 100644 --- a/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_1_0_0/fw_CPU.h +++ b/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_1_0_0/fw_CPU.h @@ -5,1233 +5,1463 @@ /** * @brief CPU firmware version fw_v1.0.0_signed.bin for bootloader v1.0.1 */ -const uint8_t fw_CPU[] - = {0xa1, 0xc5, 0x90, 0x6f, 0xeb, 0x05, 0xe3, 0x91, 0xf0, 0x7c, 0x2f, 0x4a, 0x0f, 0x89, 0x75, 0xc1, 0x4b, 0xa1, 0xa4, - 0x44, 0x0e, 0x9c, 0xb0, 0x1d, 0xc1, 0x05, 0x80, 0xed, 0x88, 0x38, 0xfd, 0xe0, 0xf2, 0x28, 0xd3, 0x91, 0x32, 0xbd, - 0x6a, 0x95, 0xf0, 0x6f, 0x8e, 0xba, 0x29, 0x56, 0x64, 0xa9, 0x20, 0xc0, 0xcb, 0xdb, 0xd4, 0x50, 0x5e, 0xee, 0xb6, - 0x57, 0x6f, 0xa7, 0xf5, 0xba, 0x97, 0x06, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x2c, 0x57, 0x00, 0x00, 0xbe, 0x52, 0xea, 0x0a, 0xec, 0x8f, 0xcf, 0xa2, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x6f, 0x30, - 0x00, 0x43, 0x6f, 0x30, 0x20, 0x3d, 0x6f, 0x30, 0xe0, 0x3c, 0x6f, 0x30, 0xa0, 0x3c, 0x6f, 0x30, 0x60, 0x3c, 0x6f, - 0x30, 0x20, 0x3c, 0x6f, 0x30, 0xe0, 0x3b, 0x6f, 0x50, 0x60, 0x04, 0x6f, 0x30, 0x60, 0x3b, 0x6f, 0x30, 0x20, 0x3b, - 0x6f, 0x30, 0xe0, 0x3a, 0x6f, 0x30, 0xa0, 0x7f, 0x6f, 0x30, 0x60, 0x3a, 0x6f, 0x30, 0x20, 0x3a, 0x6f, 0x30, 0xe0, - 0x39, 0x6f, 0x30, 0xa0, 0x39, 0x6f, 0x40, 0xf0, 0x72, 0x6f, 0x30, 0x20, 0x26, 0x6f, 0x30, 0x50, 0x20, 0x6f, 0x40, - 0x30, 0x22, 0x6f, 0x40, 0xf0, 0x21, 0x6f, 0x40, 0xb0, 0x21, 0x6f, 0x30, 0xa0, 0x4c, 0x6f, 0x30, 0xa0, 0x4d, 0x6f, - 0x30, 0xf0, 0x42, 0x6f, 0x40, 0x50, 0x56, 0x6f, 0x30, 0x20, 0x4e, 0x6f, 0x20, 0x30, 0x1f, 0x6f, 0x40, 0x70, 0x0a, - 0x6f, 0x30, 0xa0, 0x4e, 0x6f, 0x30, 0x00, 0x5b, 0x6f, 0x30, 0x00, 0x3f, 0x93, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, - 0x00, 0x93, 0x01, 0x00, 0x00, 0x13, 0x02, 0x00, 0x00, 0x93, 0x02, 0x00, 0x00, 0x13, 0x03, 0x00, 0x00, 0x93, 0x03, - 0x00, 0x00, 0x13, 0x04, 0x00, 0x00, 0x93, 0x04, 0x00, 0x00, 0x13, 0x05, 0x00, 0x00, 0x93, 0x05, 0x00, 0x00, 0x13, - 0x06, 0x00, 0x00, 0x93, 0x06, 0x00, 0x00, 0x13, 0x07, 0x00, 0x00, 0x93, 0x07, 0x00, 0x00, 0x13, 0x08, 0x00, 0x00, - 0x93, 0x08, 0x00, 0x00, 0x13, 0x09, 0x00, 0x00, 0x93, 0x09, 0x00, 0x00, 0x13, 0x0a, 0x00, 0x00, 0x93, 0x0a, 0x00, - 0x00, 0x13, 0x0b, 0x00, 0x00, 0x93, 0x0b, 0x00, 0x00, 0x13, 0x0c, 0x00, 0x00, 0x93, 0x0c, 0x00, 0x00, 0x13, 0x0d, - 0x00, 0x00, 0x93, 0x0d, 0x00, 0x00, 0x13, 0x0e, 0x00, 0x00, 0x93, 0x0e, 0x00, 0x00, 0x13, 0x0f, 0x00, 0x00, 0x93, - 0x0f, 0x00, 0x00, 0x97, 0x00, 0x00, 0x00, 0x93, 0x80, 0x40, 0xf0, 0x73, 0x90, 0x50, 0x30, 0x93, 0x00, 0x00, 0x00, - 0x17, 0x41, 0x10, 0x00, 0x13, 0x01, 0x41, 0xcf, 0x33, 0x04, 0x01, 0x00, 0x17, 0x0d, 0x10, 0x00, 0x13, 0x0d, 0x8d, - 0xee, 0x97, 0x4d, 0x10, 0x00, 0x93, 0x8d, 0x0d, 0xce, 0x63, 0x57, 0xbd, 0x01, 0x23, 0x20, 0x0d, 0x00, 0x11, 0x0d, - 0xe3, 0x4d, 0xbd, 0xff, 0xef, 0x00, 0xf0, 0x60, 0x73, 0x00, 0x50, 0x10, 0xf5, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x23, - 0xa6, 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0x07, 0xf2, - 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0x07, 0xf2, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x88, 0x07, 0xf2, 0x82, 0x80, 0x18, - 0x41, 0xfd, 0x57, 0x63, 0x02, 0xf7, 0x06, 0x13, 0x07, 0x45, 0x00, 0x81, 0x47, 0x13, 0x06, 0xf0, 0x07, 0x14, 0x43, - 0x81, 0xea, 0x85, 0x07, 0x11, 0x07, 0xe3, 0x9c, 0xc7, 0xfe, 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x01, 0x47, 0x93, - 0x05, 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, 0x05, 0x8a, 0x19, 0xca, 0x93, 0x05, 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, - 0x05, 0x8a, 0x15, 0xc6, 0x05, 0x07, 0xe3, 0x1b, 0xb7, 0xfe, 0x21, 0xa0, 0x05, 0x07, 0xe3, 0x11, 0xb7, 0xfe, 0x89, - 0x07, 0x93, 0x06, 0x00, 0x08, 0x7d, 0x56, 0xe3, 0x85, 0xd7, 0xfc, 0x85, 0x07, 0x13, 0x97, 0x27, 0x00, 0x2a, 0x97, - 0x03, 0x27, 0xc7, 0xff, 0xe3, 0x08, 0xc7, 0xfe, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x05, 0x67, 0xaa, 0x87, 0x01, - 0x17, 0x01, 0x45, 0x94, 0x43, 0x99, 0xe6, 0x13, 0x05, 0x05, 0x02, 0x91, 0x07, 0xe3, 0x1b, 0xe5, 0xfe, 0x82, 0x80, - 0x81, 0x47, 0x13, 0x06, 0x00, 0x02, 0x33, 0xd7, 0xf6, 0x00, 0x05, 0x8b, 0x09, 0xe7, 0x85, 0x07, 0x05, 0x05, 0xe3, - 0x9a, 0xc7, 0xfe, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x14, 0x20, 0x00, 0x13, 0x04, 0x04, 0x00, 0x83, 0x46, - 0x94, 0x07, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, 0x64, 0x13, - 0x06, 0x06, 0x3d, 0x93, 0x85, 0xc5, 0x3d, 0x06, 0xc6, 0xef, 0x10, 0x30, 0x4c, 0x03, 0x45, 0x94, 0x07, 0xb2, 0x40, - 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x40, 0x90, 0x0b, 0xef, 0x20, 0xc0, 0x58, 0x93, - 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x00, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x40, 0x50, 0x0c, 0xb2, 0x40, 0x41, 0x01, - 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x05, 0x05, 0x10, 0x2a, 0x84, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, - 0x3e, 0x06, 0xc6, 0xef, 0x10, 0x30, 0x4f, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf5, 0x14, 0x43, 0x85, 0x47, - 0xb3, 0x97, 0x87, 0x00, 0xb2, 0x40, 0x22, 0x44, 0x93, 0xc7, 0xf7, 0xff, 0xf5, 0x8f, 0x1c, 0xc3, 0x41, 0x01, 0x82, - 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x2a, 0x84, 0x93, 0x04, 0xa0, 0x0a, 0xef, 0x20, 0x10, 0x76, - 0x63, 0x19, 0x95, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x22, - 0x85, 0xef, 0x20, 0x90, 0x78, 0x22, 0x85, 0xef, 0x20, 0x30, 0x74, 0xe3, 0x03, 0x95, 0xfe, 0x37, 0x55, 0x10, 0x00, - 0x13, 0x05, 0x45, 0x3e, 0x85, 0x45, 0xef, 0x10, 0x10, 0x49, 0x13, 0x05, 0x50, 0x05, 0xd1, 0xbf, 0x01, 0x11, 0x22, - 0xcc, 0x2a, 0x84, 0x37, 0x35, 0x00, 0x08, 0x06, 0xce, 0x2e, 0xc6, 0xef, 0x30, 0x10, 0x0a, 0x32, 0x46, 0xa2, 0x85, - 0x37, 0x35, 0x00, 0x08, 0xef, 0x30, 0x50, 0x0e, 0x62, 0x44, 0xf2, 0x40, 0x37, 0x35, 0x00, 0x08, 0x05, 0x61, 0x6f, - 0x30, 0xb0, 0x0b, 0x6d, 0x71, 0x23, 0x24, 0x81, 0x10, 0x2a, 0x84, 0x0a, 0x85, 0x23, 0x26, 0x11, 0x10, 0xef, 0x10, - 0x50, 0x63, 0x0a, 0x85, 0x23, 0x00, 0x81, 0x00, 0xef, 0x20, 0xc0, 0x3e, 0x83, 0x20, 0xc1, 0x10, 0x03, 0x24, 0x81, - 0x10, 0x51, 0x61, 0x82, 0x80, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0x2e, 0xc4, 0xef, 0x20, 0xd0, 0x1a, 0xa2, 0x45, - 0x32, 0x45, 0xef, 0x20, 0xd0, 0x32, 0x2a, 0xc4, 0xef, 0x20, 0x90, 0x1b, 0xf2, 0x40, 0x22, 0x45, 0x05, 0x61, 0x82, - 0x80, 0x13, 0x01, 0x01, 0xde, 0x23, 0x2c, 0x81, 0x20, 0x2e, 0x84, 0xaa, 0x05, 0x23, 0x28, 0x21, 0x21, 0x93, 0x85, - 0x05, 0x20, 0x2a, 0x89, 0x08, 0x08, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x2a, 0x91, 0x20, 0x7d, 0x3f, 0x93, 0x07, 0xa0, - 0x0a, 0x63, 0x12, 0xf5, 0x04, 0xaa, 0x84, 0x08, 0x08, 0xcd, 0x33, 0x63, 0x00, 0x95, 0x02, 0x22, 0x85, 0xd1, 0x3d, - 0x09, 0x45, 0x83, 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, 0x41, 0x21, 0x03, 0x29, 0x01, 0x21, 0x13, - 0x01, 0x01, 0x22, 0x82, 0x80, 0x42, 0x44, 0x48, 0x08, 0x22, 0xc6, 0x25, 0x35, 0x09, 0x8c, 0x11, 0x46, 0x6c, 0x00, - 0x4a, 0x85, 0x22, 0xc6, 0xef, 0x40, 0x70, 0x7c, 0x05, 0x45, 0xc9, 0xbf, 0x01, 0x45, 0xf9, 0xb7, 0x41, 0x11, 0x4a, - 0xc0, 0x03, 0xa9, 0x05, 0x00, 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0x2e, 0x84, 0xaa, 0x84, 0xef, 0x20, 0x10, 0x67, - 0xca, 0x85, 0x26, 0x85, 0xef, 0x20, 0x70, 0x1e, 0xa6, 0x85, 0x22, 0x85, 0xef, 0x20, 0xb0, 0x28, 0x93, 0x07, 0xa0, - 0x0a, 0x63, 0x16, 0xf5, 0x02, 0x1c, 0x40, 0x63, 0x93, 0x27, 0x03, 0x93, 0x07, 0x44, 0x00, 0x7d, 0x57, 0x13, 0x04, - 0x04, 0x20, 0x94, 0x43, 0x63, 0x9b, 0xe6, 0x00, 0x91, 0x07, 0xe3, 0x9c, 0x87, 0xfe, 0xb2, 0x40, 0x22, 0x44, 0x92, - 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0xc5, 0xbf, 0x13, 0x01, 0x01, 0xde, 0x23, 0x26, - 0x31, 0x21, 0x93, 0x19, 0xa5, 0x00, 0x23, 0x2a, 0x91, 0x20, 0x93, 0x84, 0x09, 0x20, 0x23, 0x2c, 0x81, 0x20, 0xa6, - 0x85, 0x2a, 0x84, 0x0a, 0x85, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x28, 0x21, 0x21, 0xfd, 0x35, 0x93, 0x07, 0xa0, 0x0a, - 0x63, 0x00, 0xf5, 0x02, 0x01, 0x45, 0x83, 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, 0x41, 0x21, 0x03, - 0x29, 0x01, 0x21, 0x83, 0x29, 0xc1, 0x20, 0x13, 0x01, 0x01, 0x22, 0x82, 0x80, 0x2a, 0x89, 0x0a, 0x85, 0xdd, 0x39, - 0x63, 0x06, 0x25, 0x01, 0x22, 0x85, 0xe5, 0x33, 0x09, 0x45, 0xd9, 0xbf, 0x02, 0x44, 0x48, 0x00, 0x89, 0x3b, 0xaa, - 0x87, 0x33, 0x06, 0xa4, 0x40, 0x0d, 0x45, 0xe3, 0x03, 0xf4, 0xfc, 0x09, 0x45, 0xe3, 0x60, 0xc4, 0xfc, 0x5c, 0x00, - 0x01, 0x44, 0x13, 0x08, 0x00, 0x02, 0x13, 0x05, 0xf0, 0x07, 0x8c, 0x43, 0x89, 0xc9, 0x81, 0x46, 0x33, 0xd7, 0xd5, - 0x00, 0x05, 0x8b, 0x05, 0xeb, 0x85, 0x06, 0xe3, 0x9b, 0x06, 0xff, 0x05, 0x04, 0x91, 0x07, 0xe3, 0x14, 0xa4, 0xfe, - 0x7d, 0x16, 0x8a, 0x85, 0x13, 0x85, 0x09, 0x40, 0x32, 0xc0, 0xf5, 0x3d, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x11, 0xf5, - 0xf8, 0x8a, 0x85, 0x26, 0x85, 0xfd, 0x35, 0x13, 0x05, 0x65, 0xf5, 0x1d, 0xa8, 0x05, 0x47, 0x33, 0x17, 0xd7, 0x00, - 0x13, 0x47, 0xf7, 0xff, 0x6d, 0x8f, 0x98, 0xc3, 0xef, 0x20, 0xc0, 0x7f, 0x18, 0x04, 0x93, 0x17, 0x24, 0x00, 0xba, - 0x97, 0x83, 0xa5, 0x47, 0xe0, 0x13, 0x05, 0x14, 0x00, 0x0a, 0x05, 0x26, 0x95, 0xef, 0x20, 0x50, 0x10, 0x2a, 0x84, - 0xef, 0x20, 0x80, 0x7f, 0x13, 0x05, 0x64, 0xf5, 0x13, 0x35, 0x15, 0x00, 0x35, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x06, - 0xc6, 0x93, 0x07, 0x30, 0x0c, 0x2a, 0x84, 0x63, 0x04, 0xf5, 0x00, 0xef, 0x20, 0xc0, 0x4b, 0xb7, 0x07, 0x20, 0x00, - 0x93, 0x87, 0x07, 0x00, 0x05, 0x67, 0x23, 0x80, 0x87, 0x00, 0xba, 0x97, 0xf8, 0x5b, 0x19, 0xe3, 0x05, 0x47, 0xf8, - 0xdb, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x66, 0x37, 0x05, 0x20, 0x00, 0x41, 0x11, 0x13, 0x06, - 0xc6, 0x07, 0x81, 0x45, 0x13, 0x05, 0x05, 0x00, 0x06, 0xc6, 0xef, 0x40, 0xb0, 0x65, 0xef, 0x20, 0x80, 0x41, 0xef, - 0x40, 0x80, 0x39, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x20, 0x00, 0x38, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x20, 0x00, 0x55, - 0xef, 0x20, 0x90, 0x7f, 0xef, 0x40, 0xa0, 0x0c, 0xef, 0x40, 0x00, 0x65, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x30, 0xe0, - 0x15, 0x69, 0x71, 0x08, 0x08, 0x23, 0x22, 0x91, 0x12, 0x23, 0x20, 0x21, 0x13, 0x23, 0x2c, 0x41, 0x11, 0x23, 0x26, - 0x11, 0x12, 0x23, 0x24, 0x81, 0x12, 0x23, 0x2e, 0x31, 0x11, 0x23, 0x2a, 0x51, 0x11, 0xef, 0x10, 0xf0, 0x39, 0x91, - 0x47, 0x37, 0x39, 0x20, 0x00, 0x23, 0x08, 0xf1, 0x00, 0x83, 0x27, 0xc9, 0xf4, 0x37, 0x1a, 0x20, 0x00, 0xb7, 0x34, - 0x20, 0x00, 0x13, 0x09, 0xc9, 0xf4, 0x13, 0x0a, 0x0a, 0x00, 0x93, 0x84, 0x84, 0xf4, 0xc5, 0xe7, 0x83, 0x27, 0x4a, - 0x07, 0x09, 0x46, 0x6c, 0x00, 0x23, 0x20, 0xf9, 0x00, 0x13, 0x05, 0x21, 0x01, 0xc1, 0x17, 0x3e, 0xc6, 0x23, 0xa0, - 0x04, 0x00, 0xef, 0x40, 0xf0, 0x58, 0x89, 0x47, 0xa3, 0x08, 0xf1, 0x00, 0x13, 0x04, 0xe0, 0x07, 0x93, 0x09, 0x41, - 0x01, 0x03, 0x27, 0x09, 0x00, 0x94, 0x40, 0xb3, 0x07, 0xd7, 0x40, 0x63, 0xf3, 0x87, 0x00, 0x3e, 0x84, 0x37, 0x56, - 0x10, 0x00, 0xb7, 0x5a, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0xa2, 0x87, 0x93, 0x85, 0xca, 0x3f, 0x13, 0x06, 0xc6, - 0x3e, 0x13, 0x05, 0x45, 0x40, 0xef, 0x10, 0x50, 0x0c, 0x8c, 0x40, 0x83, 0x27, 0x4a, 0x07, 0x33, 0x07, 0xb4, 0x00, - 0x63, 0xf7, 0xe7, 0x04, 0x8d, 0x45, 0x13, 0x85, 0xca, 0x3f, 0xef, 0x10, 0x30, 0x12, 0x13, 0x04, 0x50, 0x05, 0xc5, - 0x3c, 0xef, 0x40, 0x60, 0x2a, 0xef, 0x20, 0xa0, 0x32, 0xef, 0x20, 0xa0, 0x29, 0x29, 0x3f, 0x83, 0x20, 0xc1, 0x12, - 0x22, 0x85, 0x03, 0x24, 0x81, 0x12, 0x83, 0x24, 0x41, 0x12, 0x03, 0x29, 0x01, 0x12, 0x83, 0x29, 0xc1, 0x11, 0x03, - 0x2a, 0x81, 0x11, 0x83, 0x2a, 0x41, 0x11, 0x55, 0x61, 0x82, 0x80, 0x13, 0x04, 0x00, 0x08, 0x93, 0x09, 0x21, 0x01, - 0xb5, 0xbf, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x22, 0x86, 0xbe, 0x95, 0x4e, 0x85, 0xef, 0x40, 0x90, - 0x4e, 0x83, 0x47, 0x11, 0x01, 0x98, 0x40, 0x22, 0x97, 0x3e, 0x94, 0x83, 0x27, 0x09, 0x00, 0xa3, 0x08, 0x81, 0x00, - 0x98, 0xc0, 0x13, 0x04, 0x50, 0x05, 0x63, 0x17, 0xf7, 0x00, 0x89, 0x47, 0x23, 0x08, 0xf1, 0x00, 0x13, 0x04, 0xa0, - 0x0a, 0x08, 0x08, 0xef, 0x20, 0xe0, 0x04, 0x59, 0xbf, 0x41, 0x11, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, - 0x06, 0xc6, 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x20, 0xe0, 0x26, 0x85, 0x3d, 0xb9, 0x3c, 0xef, 0x30, 0x20, 0x07, 0x41, - 0x3d, 0xb2, 0x40, 0x1d, 0x65, 0x13, 0x05, 0x05, 0x6c, 0x41, 0x01, 0x6f, 0x30, 0x00, 0x0f, 0x41, 0x11, 0x26, 0xc2, - 0xae, 0x84, 0xb6, 0x85, 0x06, 0xc6, 0x22, 0xc4, 0x4a, 0xc0, 0x36, 0x84, 0x32, 0x89, 0xef, 0x40, 0x40, 0x4f, 0x22, - 0x86, 0xca, 0x85, 0x13, 0x05, 0x00, 0x02, 0xef, 0x40, 0x00, 0x58, 0xef, 0x40, 0x60, 0x4c, 0xef, 0x40, 0xe0, 0x67, - 0x93, 0x07, 0xa0, 0x0a, 0x13, 0x04, 0x50, 0x05, 0x63, 0x1a, 0xf5, 0x00, 0x2a, 0x84, 0x13, 0x06, 0x00, 0x02, 0x93, - 0x05, 0x00, 0x02, 0x26, 0x85, 0xef, 0x40, 0xe0, 0x50, 0xb2, 0x40, 0x22, 0x85, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, - 0x41, 0x01, 0x82, 0x80, 0x85, 0x67, 0xc1, 0x07, 0x63, 0xee, 0xb7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, - 0xc6, 0xae, 0x84, 0x37, 0x04, 0x20, 0x00, 0x19, 0xc5, 0x2e, 0x86, 0xaa, 0x85, 0x13, 0x05, 0x04, 0x00, 0xef, 0x40, - 0xd0, 0x42, 0x13, 0x04, 0x04, 0x00, 0x93, 0x07, 0x30, 0xfc, 0x23, 0x00, 0xf4, 0x00, 0x85, 0x67, 0x3e, 0x94, 0x64, - 0xd8, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x82, 0x80, 0x13, 0x01, 0x01, 0xdd, 0x23, 0x24, - 0x81, 0x22, 0x23, 0x22, 0x91, 0x22, 0x23, 0x20, 0x21, 0x23, 0x23, 0x2e, 0x31, 0x21, 0x23, 0x2c, 0x41, 0x21, 0x23, - 0x2a, 0x51, 0x21, 0x23, 0x28, 0x61, 0x21, 0x23, 0x26, 0x71, 0x21, 0x23, 0x24, 0x81, 0x21, 0x23, 0x26, 0x11, 0x22, - 0x13, 0x04, 0x00, 0x20, 0x01, 0x49, 0x93, 0x04, 0xa0, 0x0a, 0x37, 0x3a, 0x20, 0x00, 0x85, 0x4a, 0x37, 0x5b, 0x10, - 0x00, 0xb7, 0x5b, 0x10, 0x00, 0x37, 0x5c, 0x10, 0x00, 0xc1, 0x49, 0xa2, 0x85, 0x0a, 0x85, 0xb1, 0x3e, 0x63, 0x16, - 0x95, 0x02, 0x0a, 0x85, 0x59, 0x32, 0x63, 0x1e, 0x95, 0x04, 0x13, 0x07, 0x4a, 0xf5, 0x14, 0x43, 0xb3, 0x97, 0x2a, - 0x01, 0x13, 0x06, 0x8b, 0x40, 0xd5, 0x8f, 0x93, 0x85, 0x4b, 0x3e, 0xca, 0x86, 0x13, 0x05, 0x4c, 0x64, 0x1c, 0xc3, - 0xef, 0x10, 0xe0, 0x6e, 0x05, 0x09, 0x13, 0x04, 0x04, 0x40, 0xe3, 0x14, 0x39, 0xfd, 0x83, 0x20, 0xc1, 0x22, 0x03, - 0x24, 0x81, 0x22, 0x83, 0x24, 0x41, 0x22, 0x03, 0x29, 0x01, 0x22, 0x83, 0x29, 0xc1, 0x21, 0x03, 0x2a, 0x81, 0x21, - 0x83, 0x2a, 0x41, 0x21, 0x03, 0x2b, 0x01, 0x21, 0x83, 0x2b, 0xc1, 0x20, 0x03, 0x2c, 0x81, 0x20, 0x13, 0x01, 0x01, - 0x23, 0x82, 0x80, 0x93, 0x05, 0x04, 0x20, 0x0a, 0x85, 0xc5, 0x3c, 0xe3, 0x10, 0x95, 0xfc, 0x0a, 0x85, 0xef, 0xf0, - 0xbf, 0x91, 0xe3, 0x1b, 0x95, 0xfa, 0x22, 0x85, 0xef, 0x20, 0x10, 0x1f, 0x8a, 0x85, 0x22, 0x85, 0xef, 0x20, 0x70, - 0x06, 0xa2, 0x85, 0x0a, 0x85, 0xf9, 0x34, 0xe3, 0x1f, 0x95, 0xf8, 0x0a, 0x85, 0xef, 0xf0, 0x9f, 0x8f, 0xe3, 0x0a, - 0x95, 0xf6, 0x41, 0xbf, 0xb7, 0x05, 0x00, 0x80, 0x37, 0x55, 0x10, 0x00, 0x86, 0x87, 0x6d, 0x71, 0xbe, 0x95, 0x13, - 0x05, 0x45, 0x41, 0x23, 0x26, 0x11, 0x10, 0xef, 0x10, 0x80, 0x6d, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x87, 0xf2, - 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x1e, 0xf7, 0x02, 0x37, 0x15, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x9a, 0xef, 0x10, 0xf0, - 0x5f, 0x13, 0x05, 0xc0, 0x0f, 0xef, 0x10, 0xa0, 0x5a, 0x0a, 0x85, 0xef, 0x10, 0x70, 0x09, 0x93, 0x07, 0xf0, 0x07, - 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x00, 0x23, 0x00, 0xf1, 0x00, 0xef, 0x10, 0x00, 0x54, 0xa3, 0x00, 0xa1, - 0x00, 0x0a, 0x85, 0xef, 0x10, 0x70, 0x60, 0x05, 0x45, 0xef, 0x40, 0x00, 0x67, 0xef, 0x40, 0x00, 0x66, 0xd5, 0x33, - 0xef, 0x10, 0x50, 0x2d, 0xf5, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0x40, 0x60, 0x4c, 0x93, 0x07, 0x00, - 0x08, 0x63, 0xf3, 0xa7, 0x00, 0xad, 0x3f, 0x2a, 0x84, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0x50, 0x7e, 0xb7, 0x17, - 0x20, 0x00, 0xb2, 0x40, 0x23, 0xaa, 0x87, 0x06, 0x22, 0x44, 0x13, 0x05, 0x30, 0x0c, 0x41, 0x01, 0x82, 0x80, 0x93, - 0x07, 0xf0, 0x17, 0x63, 0xf5, 0xa7, 0x00, 0x41, 0x11, 0x06, 0xc6, 0xb9, 0x37, 0x6f, 0x10, 0xb0, 0x3e, 0x41, 0x11, - 0x22, 0xc4, 0x26, 0xc2, 0x4a, 0xc0, 0x2e, 0x84, 0x06, 0xc6, 0xaa, 0x84, 0xc5, 0x37, 0x61, 0x8d, 0x13, 0x09, 0x50, - 0x05, 0x19, 0xc1, 0x13, 0x09, 0xa0, 0x0a, 0x26, 0x85, 0xc1, 0x3f, 0x69, 0x8c, 0x13, 0x05, 0xa0, 0x0a, 0x19, 0xe0, - 0x13, 0x05, 0x50, 0x05, 0x63, 0x03, 0x25, 0x01, 0x21, 0x3f, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, - 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x8d, 0x47, 0x63, 0xf3, 0xa7, 0x00, 0x01, 0x37, 0x89, 0x67, 0x93, 0x87, - 0x07, 0xbf, 0x0a, 0x05, 0x3e, 0x95, 0xef, 0x30, 0xe0, 0x02, 0xaa, 0x87, 0x13, 0x07, 0xf0, 0x0f, 0x55, 0x45, 0x63, - 0x89, 0xe7, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x59, 0x45, 0x63, 0x94, 0xe7, 0x00, 0x13, 0x05, 0x30, 0x0c, 0xb2, 0x40, - 0x41, 0x01, 0x82, 0x80, 0x21, 0x71, 0x23, 0x2c, 0x81, 0x1a, 0x2a, 0x84, 0x08, 0x09, 0x23, 0x2e, 0x11, 0x1a, 0x23, - 0x2a, 0x91, 0x1a, 0x23, 0x28, 0x21, 0x1b, 0x23, 0x26, 0x31, 0x1b, 0x23, 0x24, 0x41, 0x1b, 0x23, 0x22, 0x51, 0x1b, - 0x23, 0x20, 0x61, 0x1b, 0x23, 0x2e, 0x71, 0x19, 0x23, 0x2c, 0x81, 0x19, 0x23, 0x2a, 0x91, 0x19, 0xef, 0x10, 0x40, - 0x77, 0x83, 0x47, 0x04, 0x00, 0x05, 0x47, 0x23, 0x18, 0xe1, 0x08, 0xc1, 0x46, 0x63, 0x80, 0xd7, 0x46, 0x63, 0xee, - 0xf6, 0x02, 0x91, 0x46, 0x63, 0x88, 0xd7, 0x34, 0x63, 0xe1, 0xf6, 0x02, 0x63, 0x86, 0xe7, 0x06, 0x09, 0x47, 0x63, - 0x81, 0xe7, 0x0e, 0x93, 0x07, 0xe0, 0x07, 0x23, 0x08, 0xf1, 0x08, 0x08, 0x09, 0xef, 0x10, 0xd0, 0x4c, 0x93, 0x07, - 0x50, 0x05, 0x99, 0xa1, 0x21, 0x47, 0xe3, 0x95, 0xe7, 0xfe, 0x83, 0x47, 0x14, 0x00, 0xd1, 0xeb, 0x4d, 0x31, 0x39, - 0xa9, 0x93, 0x06, 0x20, 0x0a, 0x63, 0x85, 0xd7, 0x4c, 0x93, 0x06, 0x30, 0x0b, 0x63, 0x82, 0xd7, 0x46, 0x93, 0x06, - 0x00, 0x02, 0xe3, 0x94, 0xd7, 0xfc, 0x83, 0x47, 0x14, 0x00, 0x63, 0x99, 0xe7, 0x06, 0x03, 0x47, 0x24, 0x00, 0x95, - 0x47, 0x63, 0x14, 0xf7, 0x06, 0x85, 0x45, 0x61, 0x45, 0xe1, 0x3d, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x09, 0xf5, 0x42, - 0x13, 0x04, 0x80, 0xf8, 0x7d, 0xa0, 0x03, 0x47, 0x14, 0x00, 0x89, 0x47, 0x63, 0x15, 0xf7, 0x04, 0x83, 0x47, 0x24, - 0x00, 0x63, 0x8a, 0xe7, 0x04, 0x63, 0x6b, 0xf7, 0x02, 0xa1, 0xe3, 0x83, 0x45, 0x34, 0x00, 0xf5, 0x47, 0x63, 0xe9, - 0xb7, 0x02, 0x9e, 0x05, 0x13, 0x06, 0x00, 0x08, 0x93, 0x85, 0x05, 0x10, 0x13, 0x05, 0x21, 0x09, 0xef, 0x20, 0x30, - 0x6d, 0x13, 0x04, 0x00, 0x08, 0x08, 0x09, 0xa3, 0x08, 0x81, 0x08, 0xef, 0x10, 0x70, 0x43, 0x93, 0x07, 0xa0, 0x0a, - 0x45, 0xae, 0x13, 0x05, 0x80, 0x1e, 0x63, 0x8d, 0xd7, 0x00, 0x13, 0x04, 0x10, 0xf8, 0xa1, 0xa8, 0x89, 0x65, 0x13, - 0x06, 0x00, 0x08, 0x93, 0x85, 0x05, 0x90, 0xf1, 0xb7, 0x13, 0x05, 0x00, 0x1f, 0xef, 0x10, 0x90, 0x24, 0x2a, 0xc6, - 0x11, 0x46, 0x6c, 0x00, 0x13, 0x05, 0x21, 0x09, 0xef, 0x40, 0x30, 0x0a, 0x11, 0x44, 0x7d, 0xbf, 0x83, 0x44, 0x14, - 0x00, 0xc5, 0x36, 0x93, 0x07, 0x10, 0x02, 0xe3, 0x95, 0xf4, 0xfc, 0xef, 0x10, 0x10, 0x7d, 0xef, 0x20, 0x90, 0x27, - 0xef, 0x30, 0x90, 0x38, 0xef, 0x40, 0x60, 0x07, 0x03, 0x45, 0x24, 0x02, 0xa5, 0x35, 0x93, 0x07, 0x30, 0x0c, 0x63, - 0x0b, 0xf5, 0x02, 0x13, 0x04, 0x70, 0xf8, 0xb3, 0x06, 0x80, 0x40, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, - 0x37, 0x55, 0x10, 0x00, 0x93, 0xf6, 0xf6, 0x0f, 0x13, 0x06, 0x86, 0x42, 0x93, 0x85, 0x45, 0x41, 0x13, 0x05, 0x45, - 0x64, 0x23, 0x08, 0xd1, 0x08, 0xef, 0x10, 0x80, 0x3b, 0xa3, 0x08, 0x01, 0x08, 0xf9, 0xb5, 0x83, 0x44, 0x24, 0x02, - 0x19, 0x34, 0x8d, 0x47, 0xe3, 0xe3, 0x97, 0xfc, 0x13, 0x06, 0x10, 0x08, 0x81, 0x45, 0x68, 0x00, 0xef, 0x40, 0x50, - 0x06, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0x24, 0x00, 0x13, 0x05, 0xd1, 0x00, 0x23, 0x06, 0x91, 0x00, 0xef, 0x40, - 0x50, 0x01, 0xef, 0x40, 0x60, 0x00, 0x37, 0x25, 0x00, 0x08, 0xef, 0x30, 0x80, 0x01, 0x81, 0x46, 0x01, 0x46, 0x93, - 0x05, 0xd1, 0x02, 0x45, 0x45, 0x85, 0x3e, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x13, 0xf5, 0xf8, 0x81, 0x45, 0x68, 0x00, - 0xef, 0x30, 0x50, 0x2f, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0xe3, 0x1a, 0xf5, 0xf6, 0x93, 0x06, 0x00, 0x02, 0x13, - 0x06, 0xd1, 0x00, 0x93, 0x05, 0xd1, 0x04, 0x49, 0x45, 0x99, 0x36, 0xaa, 0x84, 0xe3, 0x1f, 0x25, 0xf5, 0x85, 0x45, - 0x68, 0x00, 0xef, 0x30, 0xd0, 0x2c, 0x2a, 0x89, 0xe3, 0x18, 0x95, 0xf4, 0x83, 0x47, 0xc1, 0x00, 0x85, 0x46, 0x13, - 0x06, 0xb1, 0x00, 0x93, 0x05, 0xd1, 0x04, 0x4d, 0x45, 0xa3, 0x05, 0xf1, 0x00, 0x31, 0x3e, 0xaa, 0x84, 0xe3, 0x1a, - 0x25, 0xf3, 0x89, 0x45, 0x68, 0x00, 0xef, 0x30, 0x30, 0x2a, 0x2a, 0x89, 0xe3, 0x13, 0x95, 0xf2, 0x81, 0x46, 0x01, - 0x46, 0x93, 0x05, 0xd1, 0x04, 0x51, 0x45, 0xf5, 0x3c, 0xaa, 0x84, 0xe3, 0x1a, 0x25, 0xf1, 0x8d, 0x45, 0x68, 0x00, - 0xef, 0x30, 0x30, 0x28, 0x2a, 0x89, 0xe3, 0x13, 0x95, 0xf0, 0x91, 0x45, 0x68, 0x00, 0xef, 0x30, 0x50, 0x27, 0xaa, - 0x84, 0xe3, 0x1c, 0x25, 0xef, 0x95, 0x45, 0x68, 0x00, 0xef, 0x30, 0x70, 0x26, 0xe3, 0x16, 0x95, 0xee, 0xb7, 0x19, - 0x20, 0x00, 0x13, 0x85, 0x09, 0x02, 0xef, 0x30, 0x70, 0x29, 0xb7, 0x14, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, - 0x05, 0xd1, 0x02, 0x13, 0x85, 0x04, 0x03, 0xef, 0x40, 0xa0, 0x73, 0x37, 0x15, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, - 0x93, 0x05, 0xd1, 0x06, 0x13, 0x05, 0x05, 0x05, 0xef, 0x40, 0x60, 0x72, 0x03, 0x49, 0x24, 0x02, 0x8d, 0x47, 0x4e, - 0x84, 0x63, 0xf3, 0x27, 0x01, 0x01, 0x39, 0x37, 0x5c, 0x10, 0x00, 0xef, 0x10, 0x10, 0x49, 0x81, 0x4c, 0x13, 0x0c, - 0x8c, 0x58, 0x8d, 0x49, 0xfd, 0x5a, 0x13, 0x0a, 0x00, 0x0f, 0x41, 0x6b, 0xb7, 0x0b, 0x00, 0x01, 0x03, 0x25, 0x0c, - 0x00, 0x51, 0x81, 0x49, 0x39, 0x03, 0x27, 0x0c, 0x00, 0x93, 0x57, 0x07, 0x01, 0xbd, 0x8b, 0x63, 0xe8, 0xf9, 0x00, - 0x8e, 0x07, 0xb3, 0x97, 0xfa, 0x00, 0x93, 0xc7, 0xf7, 0xff, 0x7d, 0x8d, 0x83, 0x46, 0x1c, 0x00, 0x33, 0x55, 0x25, - 0x01, 0x93, 0x77, 0x15, 0x00, 0x93, 0xf6, 0x06, 0x0f, 0x63, 0x96, 0x46, 0x07, 0x99, 0xc3, 0x93, 0x07, 0xf0, 0x0f, - 0xbd, 0x65, 0xf9, 0x8d, 0x21, 0x83, 0x3d, 0x8b, 0x22, 0x07, 0x4d, 0x8f, 0x83, 0x45, 0x0c, 0x00, 0xc2, 0x07, 0x66, - 0x85, 0xd9, 0x8d, 0xdd, 0x8d, 0xef, 0x10, 0xd0, 0x43, 0x83, 0x47, 0x4c, 0x00, 0x11, 0x0c, 0x85, 0x0c, 0xc5, 0xf3, - 0xef, 0x10, 0x90, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x04, - 0x03, 0x13, 0x05, 0x21, 0x09, 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x40, 0xa0, 0x67, 0x93, 0x05, 0x04, 0x02, 0x41, 0x46, - 0x13, 0x05, 0x21, 0x0b, 0xef, 0x40, 0xc0, 0x66, 0xef, 0x30, 0xf0, 0x6b, 0x13, 0x04, 0x00, 0x03, 0xef, 0xf0, 0x7f, - 0x85, 0xbd, 0xbb, 0x93, 0x76, 0x05, 0x10, 0x99, 0xc2, 0x93, 0xe7, 0x27, 0x00, 0xb3, 0x76, 0x65, 0x01, 0x99, 0xc2, - 0x93, 0xe7, 0x47, 0x00, 0x33, 0x75, 0x75, 0x01, 0x59, 0xd1, 0x93, 0xe7, 0x87, 0x00, 0x41, 0xb7, 0xb7, 0x37, 0x20, - 0x00, 0x03, 0xa7, 0xc7, 0xf3, 0x93, 0x07, 0xa0, 0x0a, 0x83, 0x44, 0x14, 0x00, 0x63, 0x14, 0xf7, 0x0e, 0x91, 0xe4, - 0x13, 0x04, 0x10, 0xf8, 0xef, 0xf0, 0xbf, 0x96, 0x4d, 0xbb, 0xb7, 0x39, 0x20, 0x00, 0x83, 0xa7, 0x89, 0xf3, 0x93, - 0x89, 0x89, 0xf3, 0xad, 0xcb, 0x09, 0x04, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x49, 0xf3, 0x83, 0x26, 0x09, 0x00, - 0x03, 0xa7, 0x09, 0x00, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, - 0x64, 0xa6, 0x96, 0x13, 0x06, 0xc6, 0x41, 0x93, 0x85, 0xc5, 0x3f, 0xef, 0x10, 0x20, 0x15, 0x03, 0x25, 0x09, 0x00, - 0x83, 0xa7, 0x09, 0x00, 0x33, 0x87, 0xa4, 0x00, 0xe3, 0xe6, 0xe7, 0xfa, 0x85, 0x67, 0x93, 0x87, 0x07, 0x02, 0xe3, - 0xe1, 0xe7, 0xfa, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x26, 0x86, 0x3e, 0x95, 0xa2, 0x85, 0xef, 0x40, - 0x40, 0x5b, 0x83, 0x27, 0x09, 0x00, 0xbe, 0x94, 0x83, 0xa7, 0x09, 0x00, 0x23, 0x20, 0x99, 0x00, 0xbd, 0xe3, 0x75, - 0x54, 0x15, 0xbb, 0x89, 0x47, 0xe3, 0xfb, 0x97, 0xf6, 0x03, 0x49, 0x34, 0x00, 0x83, 0x47, 0x24, 0x00, 0xf9, 0x14, - 0x22, 0x09, 0x3e, 0x99, 0x85, 0x67, 0x93, 0x06, 0xf9, 0xff, 0x13, 0x87, 0xf7, 0x00, 0x11, 0x04, 0xe3, 0x6c, 0xd7, - 0xf4, 0x37, 0x0a, 0x20, 0x00, 0x13, 0x0a, 0x0a, 0x00, 0x3e, 0x9a, 0x41, 0x09, 0x93, 0x07, 0xf0, 0x07, 0xa3, 0x0c, - 0xfa, 0x06, 0x23, 0xa0, 0x29, 0x01, 0xef, 0x10, 0x50, 0x4a, 0xef, 0x20, 0xc0, 0x74, 0xef, 0x30, 0xd0, 0x05, 0xb7, - 0x37, 0x20, 0x00, 0x23, 0x28, 0x2a, 0x07, 0x23, 0x2a, 0x0a, 0x06, 0x23, 0xaa, 0x07, 0xf2, 0x2d, 0xbf, 0x13, 0x04, - 0x60, 0xf8, 0x39, 0xbf, 0xe3, 0x9e, 0xf4, 0xf8, 0x01, 0x44, 0xa1, 0xb9, 0x83, 0x47, 0x14, 0x00, 0xe3, 0x95, 0x07, - 0xc6, 0xef, 0x10, 0x30, 0x15, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x0f, 0x05, 0xc4, 0x83, 0x20, 0xc1, 0x1b, 0x03, 0x24, - 0x81, 0x1b, 0x83, 0x24, 0x41, 0x1b, 0x03, 0x29, 0x01, 0x1b, 0x83, 0x29, 0xc1, 0x1a, 0x03, 0x2a, 0x81, 0x1a, 0x83, - 0x2a, 0x41, 0x1a, 0x03, 0x2b, 0x01, 0x1a, 0x83, 0x2b, 0xc1, 0x19, 0x03, 0x2c, 0x81, 0x19, 0x83, 0x2c, 0x41, 0x19, - 0x3e, 0x85, 0x39, 0x61, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa2, 0xa7, 0xf4, 0x7d, 0xb7, 0x83, 0x46, 0x14, - 0x00, 0xe3, 0x9d, 0xe6, 0xc0, 0x83, 0x47, 0x24, 0x00, 0x63, 0x8a, 0xd7, 0x02, 0x0d, 0x47, 0xe3, 0x96, 0xe7, 0xc0, - 0xa1, 0x45, 0x01, 0x45, 0xb5, 0x3c, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0xe3, 0x13, 0xf5, 0xba, 0xb7, 0xb5, 0xb5, - 0x61, 0x93, 0x85, 0x55, 0x49, 0x13, 0x05, 0x80, 0x1f, 0xef, 0x10, 0x40, 0x6b, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa6, - 0x87, 0xf2, 0xbd, 0xb7, 0xb7, 0x15, 0x78, 0x4a, 0x93, 0x85, 0x95, 0x21, 0x13, 0x05, 0x80, 0x1f, 0xef, 0x10, 0xa0, - 0x69, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf2, 0x81, 0xbf, 0xb7, 0x37, 0x20, 0x00, - 0x03, 0xa7, 0x87, 0xf2, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1f, 0xf7, 0xb4, 0x83, 0x47, 0x14, 0x00, 0xe3, 0x96, 0x07, - 0xba, 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x09, 0xef, 0x00, 0x50, 0x6f, 0x2a, 0x84, 0xe3, 0x51, 0x05, 0xb8, - 0xcd, 0xbe, 0x41, 0x11, 0x05, 0x45, 0x06, 0xc6, 0xef, 0x40, 0x20, 0x02, 0xb2, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x13, - 0x07, 0xa0, 0x0a, 0x23, 0xa0, 0xe7, 0xf4, 0x41, 0x01, 0x82, 0x80, 0x31, 0x71, 0x22, 0xdd, 0x37, 0x34, 0x20, 0x00, - 0x93, 0x07, 0x50, 0x05, 0x06, 0xdf, 0x4a, 0xd9, 0x52, 0xd5, 0x56, 0xd3, 0x62, 0xcd, 0x26, 0xdb, 0x4e, 0xd7, 0x5a, - 0xd1, 0x5e, 0xcf, 0x66, 0xcb, 0x6a, 0xc9, 0x6e, 0xc7, 0xb7, 0x3a, 0x20, 0x00, 0x37, 0x3a, 0x20, 0x00, 0x37, 0x39, - 0x20, 0x00, 0x13, 0x04, 0x84, 0xf2, 0x23, 0xa0, 0xfa, 0xf4, 0x23, 0x26, 0xfa, 0xf2, 0x23, 0x22, 0xf9, 0xf4, 0x1c, - 0xc0, 0xef, 0x10, 0x60, 0x3d, 0xef, 0x10, 0xc0, 0x55, 0x13, 0x87, 0x0a, 0xf4, 0x3a, 0xc8, 0x13, 0x07, 0xca, 0xf2, - 0x3a, 0xca, 0x13, 0x07, 0x49, 0xf4, 0x93, 0x07, 0xa0, 0x0a, 0x3a, 0xc6, 0x37, 0x5c, 0x10, 0x00, 0x85, 0x45, 0x63, - 0x0a, 0xf5, 0x00, 0x13, 0x05, 0x4c, 0x41, 0xef, 0x00, 0x90, 0x7b, 0xef, 0x10, 0x80, 0x4f, 0xef, 0xf0, 0x3f, 0x8c, - 0x41, 0x45, 0xef, 0xf0, 0x5f, 0x97, 0x08, 0xc0, 0xb7, 0x07, 0x01, 0x02, 0x80, 0x57, 0x98, 0x5b, 0x29, 0x45, 0x59, - 0x8c, 0x98, 0x5f, 0x59, 0x8c, 0x13, 0x77, 0xf4, 0x87, 0x98, 0xd7, 0x98, 0xdb, 0x98, 0xdf, 0xd8, 0x43, 0x13, 0x67, - 0x87, 0x00, 0xd8, 0xc3, 0xef, 0x10, 0x00, 0x38, 0xef, 0x30, 0x30, 0x22, 0x13, 0x75, 0x05, 0x78, 0x11, 0xc5, 0x13, - 0x05, 0x00, 0x78, 0x81, 0x45, 0xef, 0x30, 0x90, 0x1a, 0xb7, 0x07, 0x01, 0x02, 0x80, 0xd7, 0x80, 0xdb, 0x37, 0x15, - 0x10, 0x00, 0x80, 0xdf, 0x13, 0x05, 0xc5, 0x9a, 0xef, 0x10, 0xa0, 0x69, 0x37, 0x56, 0x10, 0x00, 0x37, 0x59, 0x10, - 0x00, 0x81, 0x47, 0x01, 0x47, 0x85, 0x46, 0x13, 0x06, 0x06, 0x43, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, 0x64, - 0xef, 0x00, 0x50, 0x6c, 0xef, 0x30, 0x50, 0x1e, 0x93, 0x07, 0x50, 0x05, 0x63, 0x1e, 0xf5, 0x00, 0x37, 0x56, 0x10, - 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x46, 0x44, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x45, 0x40, 0xef, 0x00, - 0x10, 0x6a, 0xef, 0x20, 0xa0, 0x2f, 0x51, 0x45, 0xef, 0x10, 0xc0, 0x4b, 0x1d, 0x89, 0xef, 0x20, 0xc0, 0x2f, 0xef, - 0x20, 0xa0, 0x03, 0xef, 0x20, 0x10, 0x03, 0xef, 0x20, 0x30, 0x31, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0xb0, 0x31, - 0x11, 0x46, 0x6c, 0x10, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0xf0, 0x35, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0xb0, - 0x33, 0x32, 0x55, 0xc1, 0x7a, 0x37, 0x0b, 0x01, 0xff, 0xb7, 0x0b, 0x00, 0x01, 0xef, 0x20, 0x70, 0x22, 0x05, 0x64, - 0x01, 0x4a, 0x93, 0x8a, 0xfa, 0x0f, 0x7d, 0x1b, 0xfd, 0x1b, 0x13, 0x0d, 0x00, 0x18, 0x52, 0x85, 0xef, 0xf0, 0x1f, - 0x87, 0xaa, 0x8c, 0x22, 0x85, 0xef, 0x20, 0xd0, 0x0f, 0x93, 0xf9, 0x09, 0xf0, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, - 0x44, 0x00, 0xef, 0x20, 0xd0, 0x0e, 0x22, 0x05, 0xb3, 0xf9, 0x59, 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, 0x84, - 0x00, 0xef, 0x20, 0xb0, 0x0d, 0x42, 0x05, 0xb3, 0xf9, 0x69, 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, 0xc4, 0x00, - 0xef, 0x20, 0x90, 0x0c, 0x62, 0x05, 0xb3, 0xf9, 0x79, 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x93, 0xc7, 0xf9, 0xff, 0x33, - 0xf5, 0x97, 0x01, 0xe3, 0x1b, 0x05, 0xea, 0x11, 0x0a, 0x41, 0x04, 0xe3, 0x12, 0xaa, 0xfb, 0x37, 0x55, 0x10, 0x00, - 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x13, 0x05, 0x85, 0x5e, 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x10, 0xf0, - 0x1a, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x40, 0x05, 0x93, 0x85, 0x45, 0x53, 0x68, 0x10, 0xef, 0x40, 0xc0, 0x24, - 0x60, 0x10, 0x48, 0x40, 0x01, 0xc5, 0xef, 0x20, 0xa0, 0x7f, 0x48, 0xc0, 0x31, 0x04, 0x1c, 0x01, 0xe3, 0x99, 0x87, - 0xfe, 0x37, 0x55, 0x10, 0x00, 0x1d, 0x46, 0x6c, 0x10, 0x13, 0x05, 0xc5, 0x5f, 0xef, 0x20, 0x40, 0x42, 0xef, 0xf0, - 0x0f, 0xe3, 0x05, 0x45, 0xef, 0x10, 0xd0, 0x02, 0xef, 0x30, 0xa0, 0x4e, 0xef, 0x30, 0x50, 0x21, 0x01, 0x45, 0xef, - 0x30, 0xf0, 0x5d, 0xb7, 0x0a, 0x20, 0x00, 0x93, 0x87, 0x0a, 0x00, 0x05, 0x6b, 0xb3, 0x8b, 0x67, 0x01, 0xb7, 0x17, - 0x20, 0x00, 0x13, 0x8a, 0xc7, 0x07, 0xef, 0x10, 0x40, 0x66, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x87, 0xf3, 0x63, - 0x82, 0x07, 0x10, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0x47, 0xf3, 0x63, 0x9c, 0xe7, 0x0e, 0xb7, 0x37, 0x20, 0x00, - 0x03, 0xc7, 0x07, 0xf3, 0x93, 0x87, 0x07, 0xf3, 0x3e, 0xcc, 0xe3, 0x1d, 0x07, 0x36, 0x03, 0xa6, 0x0b, 0x07, 0x93, - 0x07, 0xf0, 0x07, 0xb7, 0x19, 0x20, 0x00, 0xa3, 0x8c, 0xfb, 0x06, 0xc1, 0x4c, 0x13, 0x8d, 0x0a, 0x00, 0x93, 0x89, - 0x09, 0x00, 0x63, 0xfe, 0xcc, 0x0a, 0x13, 0x04, 0x06, 0xff, 0xef, 0x10, 0x60, 0x72, 0x01, 0x45, 0xef, 0x30, 0x60, - 0x4f, 0x22, 0x86, 0x63, 0xf3, 0x8c, 0x00, 0x41, 0x46, 0x93, 0x85, 0x0a, 0x00, 0x68, 0x10, 0xef, 0x30, 0x20, 0x50, - 0xef, 0x10, 0xc0, 0x77, 0xb7, 0x57, 0x10, 0x00, 0x23, 0x8c, 0xa9, 0x06, 0x93, 0x87, 0x87, 0x58, 0x03, 0xc7, 0x07, - 0x00, 0x63, 0x1b, 0x07, 0x12, 0x03, 0xa4, 0x09, 0x07, 0xc1, 0x47, 0xe3, 0xf2, 0x87, 0xda, 0x01, 0x45, 0xef, 0x30, - 0xc0, 0x4b, 0x41, 0x14, 0x22, 0x86, 0x93, 0x85, 0x0a, 0x00, 0x13, 0x85, 0x0a, 0x00, 0xef, 0x30, 0xa0, 0x4c, 0xb7, - 0x1c, 0x20, 0x00, 0x13, 0x85, 0x0c, 0x02, 0xef, 0x30, 0xa0, 0x68, 0xef, 0x30, 0x20, 0x6d, 0x37, 0x56, 0x10, 0x00, - 0xb7, 0x5d, 0x10, 0x00, 0xaa, 0x86, 0x13, 0x06, 0x46, 0x45, 0x93, 0x85, 0xcd, 0x3d, 0x13, 0x05, 0x49, 0x64, 0xef, - 0x00, 0xf0, 0x49, 0x93, 0x85, 0x0c, 0x02, 0x41, 0x46, 0x33, 0x05, 0x8d, 0x00, 0xef, 0x00, 0x30, 0x38, 0xaa, 0x8c, - 0xc1, 0x47, 0x63, 0x09, 0x05, 0x0e, 0x89, 0x45, 0x13, 0x85, 0xcd, 0x3d, 0xef, 0x00, 0x50, 0x4f, 0x37, 0x55, 0x10, - 0x00, 0x93, 0x07, 0xb0, 0x07, 0x91, 0x45, 0x13, 0x05, 0xc5, 0x3f, 0xa3, 0x8c, 0xf9, 0x06, 0xef, 0x00, 0xf0, 0x4d, - 0xef, 0xe0, 0x9f, 0xf7, 0xef, 0xf0, 0xcf, 0x87, 0xef, 0xf0, 0x4f, 0xc3, 0xef, 0x10, 0xa0, 0x53, 0x93, 0x07, 0xa0, - 0x0a, 0x2a, 0x84, 0x63, 0x17, 0xf5, 0x08, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xc7, 0x07, 0xf3, 0xc9, 0xe3, 0xef, 0x10, - 0xa0, 0x02, 0xe3, 0x15, 0x85, 0x20, 0xd2, 0x47, 0x9c, 0x43, 0x63, 0x94, 0xa7, 0x00, 0xef, 0x10, 0xc0, 0x18, 0xb2, - 0x47, 0x98, 0x43, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x13, 0xf7, 0x1e, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0x86, 0x4d, - 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x10, 0x41, 0xef, 0xf0, 0x4f, 0xbe, 0x37, 0x25, 0x00, - 0x08, 0xef, 0x20, 0x70, 0x0d, 0xef, 0xf0, 0x4f, 0xa8, 0xef, 0x20, 0x60, 0x5f, 0xef, 0x10, 0x50, 0x1c, 0xef, 0x20, - 0x30, 0x21, 0xef, 0xe0, 0xff, 0xf3, 0x32, 0x47, 0x37, 0x56, 0x10, 0x00, 0x93, 0x07, 0x50, 0x05, 0x13, 0x06, 0x46, - 0x4e, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, 0x64, 0x1c, 0xc3, 0xef, 0x00, 0x50, 0x3d, 0xef, 0x20, 0x10, 0x21, - 0xef, 0x10, 0x70, 0x48, 0xef, 0x20, 0x20, 0x5f, 0xef, 0x30, 0x90, 0x00, 0xc2, 0x47, 0x98, 0x43, 0x93, 0x07, 0x50, - 0x05, 0xe3, 0x08, 0xf7, 0xe4, 0xad, 0xb9, 0x63, 0x1c, 0xe5, 0x00, 0x83, 0xc7, 0x17, 0x00, 0xbd, 0x8b, 0xe3, 0x82, - 0x07, 0xec, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0xa0, 0x59, 0x65, 0xbd, 0x91, 0x07, 0x75, 0xb5, 0x03, 0xa4, 0x09, - 0x07, 0xe3, 0xe4, 0x87, 0x16, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0xc5, 0x3f, 0xef, 0x00, 0xb0, 0x3f, - 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x3f, 0x95, 0x45, 0xef, 0x00, 0xd0, 0x3e, 0x13, 0x05, 0xf0, 0x07, 0x39, - 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xf5, 0x94, 0x43, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, - 0x13, 0x87, 0x16, 0x00, 0x98, 0xc3, 0x03, 0xc7, 0x89, 0x07, 0xa2, 0x87, 0x13, 0x06, 0x46, 0x46, 0x93, 0x85, 0xc5, - 0x3f, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x30, 0x34, 0xb7, 0x17, 0x20, 0x00, 0x13, 0x85, 0xc7, 0x07, 0x3d, 0x46, - 0x81, 0x45, 0xef, 0x30, 0xd0, 0x7f, 0x83, 0xc7, 0x89, 0x07, 0x13, 0x07, 0x20, 0x04, 0x63, 0x80, 0xe7, 0x56, 0x63, - 0x69, 0xf7, 0x16, 0x13, 0x07, 0x10, 0x02, 0x63, 0x89, 0xe7, 0x3e, 0x63, 0x60, 0xf7, 0x08, 0x45, 0x47, 0x63, 0x82, - 0xe7, 0x30, 0x63, 0x69, 0xf7, 0x02, 0x05, 0x47, 0x63, 0x85, 0xe7, 0x24, 0x41, 0x47, 0x63, 0x8d, 0xe7, 0x26, 0x89, - 0x49, 0x3d, 0xa3, 0x93, 0x87, 0x07, 0xfa, 0x93, 0xf7, 0xf7, 0x0f, 0x45, 0x47, 0xe3, 0x69, 0xf7, 0xfe, 0x37, 0x57, - 0x10, 0x00, 0x8a, 0x07, 0x13, 0x07, 0xc7, 0x4e, 0xba, 0x97, 0x9c, 0x43, 0x82, 0x87, 0x49, 0x47, 0x63, 0x82, 0xe7, - 0x34, 0x13, 0x07, 0x00, 0x02, 0xe3, 0x9a, 0xe7, 0xfc, 0x42, 0x04, 0x41, 0x80, 0xa1, 0x47, 0xe3, 0x13, 0xf4, 0xf4, - 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x81, 0x63, 0x97, 0x07, 0x54, 0x93, - 0x07, 0xf0, 0x1f, 0x63, 0xe3, 0xa7, 0x54, 0x83, 0x25, 0x4d, 0x00, 0xef, 0x10, 0x90, 0x1e, 0x93, 0x07, 0xa0, 0x0a, - 0x63, 0x1b, 0xf5, 0x52, 0xad, 0xa6, 0x13, 0x07, 0x10, 0x03, 0x63, 0x86, 0xe7, 0x3a, 0x63, 0x6f, 0xf7, 0x04, 0x13, - 0x07, 0x20, 0x02, 0x63, 0x87, 0xe7, 0x38, 0x13, 0x07, 0x00, 0x03, 0xe3, 0x91, 0xe7, 0xf8, 0x42, 0x04, 0x41, 0x80, - 0x91, 0x47, 0xe3, 0x1a, 0xf4, 0xee, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x97, 0x07, 0x01, 0x8d, 0x8b, 0x41, - 0x83, 0x63, 0x9e, 0x07, 0x4e, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xea, 0xe7, 0x4e, 0x03, 0x45, 0x3d, 0x00, 0xfd, 0x47, - 0x63, 0xe5, 0xa7, 0x4e, 0x93, 0x15, 0x25, 0x00, 0x0d, 0x81, 0x93, 0xf7, 0xc5, 0x01, 0x3a, 0x95, 0xbd, 0x45, 0xb3, - 0x95, 0xf5, 0x00, 0x0a, 0x05, 0x93, 0xc5, 0xf5, 0xff, 0x5a, 0x95, 0x05, 0xa4, 0x13, 0x07, 0x00, 0x04, 0x63, 0x8f, - 0xe7, 0x3a, 0x13, 0x07, 0x10, 0x04, 0xe3, 0x94, 0xe7, 0xf2, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x1d, 0xf4, - 0xe8, 0x83, 0x26, 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0xa1, 0x82, 0xc2, 0x06, 0xc1, 0x82, 0x63, 0xe1, 0xd7, 0x4a, - 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x86, 0x4b, 0x93, 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, - 0x64, 0xef, 0x00, 0x10, 0x1f, 0xef, 0x10, 0x50, 0x57, 0xef, 0x20, 0x00, 0x75, 0x83, 0x27, 0x0d, 0x00, 0x91, 0x65, - 0x93, 0x85, 0x05, 0x20, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, 0xa6, 0x07, 0x37, 0x15, 0x20, 0x00, 0xbe, 0x95, 0x13, - 0x05, 0x05, 0x08, 0xef, 0x10, 0x30, 0x19, 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x74, 0x93, 0x07, 0xc0, 0x1b, 0xe3, 0xe0, - 0x87, 0xa8, 0x93, 0x05, 0x44, 0x00, 0x29, 0xac, 0x13, 0x07, 0x10, 0x07, 0x63, 0x69, 0xf7, 0x02, 0x13, 0x07, 0xf0, - 0x05, 0xe3, 0x66, 0xf7, 0xea, 0x13, 0x07, 0x00, 0x05, 0xe3, 0x90, 0xe7, 0xea, 0x42, 0x04, 0x41, 0x80, 0x89, 0x47, - 0xe3, 0x19, 0xf4, 0xe0, 0x03, 0x44, 0x1d, 0x00, 0x37, 0x15, 0x20, 0x00, 0x13, 0x05, 0x05, 0x08, 0xa2, 0x85, 0xef, - 0xe0, 0x1f, 0xd7, 0xd9, 0xb7, 0x13, 0x07, 0x20, 0x08, 0x63, 0x8b, 0xe7, 0x6e, 0x63, 0x6d, 0xf7, 0x04, 0x13, 0x07, - 0x00, 0x08, 0x63, 0x82, 0xe7, 0x68, 0x13, 0x07, 0x10, 0x08, 0xe3, 0x93, 0xe7, 0xe6, 0x42, 0x04, 0x41, 0x80, 0x8d, - 0x47, 0xe3, 0x1c, 0xf4, 0xdc, 0x03, 0x45, 0x1d, 0x00, 0x3d, 0x47, 0x81, 0x47, 0x63, 0x6e, 0xa7, 0x00, 0xb7, 0x37, - 0x20, 0x00, 0x03, 0xa7, 0x47, 0xf5, 0x89, 0x47, 0x33, 0x57, 0xa7, 0x00, 0x05, 0x8b, 0x01, 0xc7, 0xef, 0xe0, 0x7f, - 0xe6, 0xaa, 0x87, 0xfd, 0x17, 0x09, 0x47, 0x63, 0x63, 0xf7, 0x3c, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x72, - 0xaa, 0x97, 0x83, 0xc9, 0x07, 0x00, 0x1d, 0xaa, 0x13, 0x07, 0x00, 0x09, 0xe3, 0x9c, 0xe7, 0xe0, 0x93, 0x17, 0x04, - 0x01, 0xc1, 0x83, 0x13, 0x07, 0x30, 0x02, 0xe3, 0x73, 0xf7, 0xd8, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, - 0xbe, 0x86, 0x13, 0x06, 0x06, 0x4c, 0x93, 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0xd0, 0x0e, 0xef, - 0x20, 0xa0, 0x0d, 0xef, 0x20, 0xc0, 0x64, 0xef, 0x20, 0x20, 0x0e, 0x2a, 0x84, 0xef, 0x20, 0x40, 0x0d, 0xef, 0x20, - 0x00, 0x66, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x14, 0xf4, 0x36, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0x00, 0x2c, 0x93, - 0x07, 0x40, 0x02, 0x81, 0xa3, 0x93, 0x19, 0x04, 0x01, 0x93, 0xd9, 0x09, 0x01, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, - 0x10, 0x00, 0xce, 0x86, 0x13, 0x06, 0x06, 0x4a, 0x93, 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0xf0, - 0x09, 0x93, 0x07, 0x1b, 0x00, 0xe3, 0xeb, 0x37, 0xd1, 0xce, 0x85, 0x13, 0x85, 0x0a, 0x00, 0xef, 0xf0, 0x4f, 0x8e, - 0xa9, 0xaa, 0x42, 0x04, 0x41, 0x80, 0x93, 0x07, 0x40, 0x02, 0xe3, 0x1f, 0xf4, 0xce, 0x03, 0x25, 0x0d, 0x00, 0x0d, - 0x44, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0x64, 0xa4, 0x30, 0xef, 0xf0, 0x8f, 0xae, 0xd5, 0x47, 0x63, 0x1f, - 0xf5, 0x2e, 0x83, 0x29, 0x0d, 0x00, 0x93, 0xd9, 0x89, 0x00, 0xc2, 0x09, 0x93, 0xd9, 0x09, 0x01, 0xe3, 0x6c, 0x34, - 0x91, 0x13, 0x84, 0x09, 0x0e, 0x16, 0x04, 0x91, 0x4c, 0x71, 0x14, 0x93, 0x0d, 0x40, 0x02, 0xb3, 0x05, 0x9d, 0x01, - 0x11, 0x46, 0x68, 0x10, 0xef, 0x30, 0x70, 0x4c, 0xb2, 0x55, 0x33, 0x05, 0x94, 0x01, 0x91, 0x0c, 0xef, 0x20, 0x20, - 0x33, 0xe3, 0x94, 0xbc, 0xff, 0x09, 0x65, 0x8a, 0x09, 0xb7, 0xf5, 0xf0, 0xf0, 0x13, 0x05, 0x05, 0xbf, 0x93, 0x85, - 0x05, 0x0f, 0x4e, 0x95, 0xef, 0x20, 0x80, 0x31, 0xc5, 0xa0, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x13, 0xf4, - 0xc8, 0x03, 0x25, 0x0d, 0x00, 0x0d, 0x44, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0x68, 0xa4, 0x28, 0xef, 0xf0, - 0x0f, 0xa7, 0x93, 0x07, 0x30, 0x0c, 0x63, 0x08, 0xf5, 0x00, 0xaa, 0x89, 0x93, 0x07, 0x00, 0x08, 0x63, 0x9a, 0xf9, - 0x20, 0xb1, 0xb9, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, 0xe3, 0x6b, 0xf4, 0x88, 0x93, 0x87, - 0x07, 0x0e, 0x13, 0x94, 0x57, 0x00, 0x93, 0x09, 0x00, 0x02, 0x33, 0x05, 0x94, 0x01, 0xef, 0x20, 0x20, 0x20, 0xb7, - 0x17, 0x20, 0x00, 0x93, 0x87, 0x07, 0x08, 0x2a, 0xd6, 0x11, 0x46, 0x33, 0x85, 0x97, 0x01, 0x6c, 0x10, 0x91, 0x0c, - 0xef, 0x30, 0x30, 0x43, 0xe3, 0x90, 0x3c, 0xff, 0x93, 0x05, 0x40, 0x02, 0x52, 0x85, 0x29, 0xb7, 0x42, 0x04, 0x41, - 0x80, 0x8d, 0x47, 0xe3, 0x17, 0xf4, 0xc0, 0x03, 0x25, 0x0d, 0x00, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0x6d, - 0xa4, 0x20, 0xef, 0xf0, 0xaf, 0x9f, 0xd5, 0x47, 0x63, 0x08, 0xf5, 0x20, 0xd9, 0x47, 0x63, 0x01, 0xf5, 0x04, 0x83, - 0x29, 0x0d, 0x00, 0x93, 0xd9, 0x89, 0x00, 0xc2, 0x09, 0x93, 0xd9, 0x09, 0x01, 0xe3, 0x62, 0x34, 0x83, 0x89, 0x67, - 0x13, 0x95, 0x29, 0x00, 0x93, 0x87, 0x07, 0xbf, 0x81, 0x45, 0x3e, 0x95, 0x93, 0x89, 0x09, 0x0e, 0xef, 0x20, 0xe0, - 0x24, 0x96, 0x09, 0x13, 0x04, 0x00, 0x02, 0x33, 0x85, 0x99, 0x01, 0x81, 0x45, 0x91, 0x0c, 0xef, 0x20, 0xc0, 0x23, - 0xe3, 0x9a, 0x8c, 0xfe, 0x93, 0x09, 0x30, 0x0c, 0xb9, 0xaa, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x11, 0xf4, - 0xba, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x81, 0x63, 0x95, 0x07, 0x1a, - 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe1, 0xa7, 0x1a, 0xef, 0x10, 0x60, 0x5b, 0x23, 0x22, 0xaa, 0x00, 0xa1, 0x45, 0x8d, - 0xb7, 0x42, 0x04, 0x41, 0x80, 0x85, 0x47, 0x01, 0x45, 0xe3, 0x18, 0xf4, 0xb6, 0xef, 0x10, 0x30, 0x24, 0x6d, 0xbf, - 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x10, 0xf4, 0xb6, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x94, 0x07, - 0x01, 0x8d, 0x8b, 0x41, 0x80, 0x63, 0x94, 0x07, 0x16, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe0, 0x87, 0x16, 0x0a, 0x04, - 0x33, 0x05, 0x64, 0x01, 0xef, 0x20, 0xe0, 0x17, 0x93, 0xf4, 0x04, 0xf0, 0xc9, 0x8c, 0x13, 0x05, 0x4b, 0x00, 0x22, - 0x95, 0xef, 0x20, 0xe0, 0x16, 0xc1, 0x77, 0x93, 0x87, 0xf7, 0x0f, 0xfd, 0x8c, 0x22, 0x05, 0xc9, 0x8c, 0x13, 0x05, - 0x8b, 0x00, 0x22, 0x95, 0xef, 0x20, 0x80, 0x15, 0xb7, 0x07, 0x01, 0xff, 0xfd, 0x17, 0x42, 0x05, 0xfd, 0x8c, 0xc9, - 0x8c, 0x13, 0x05, 0xcb, 0x00, 0x22, 0x95, 0xef, 0x20, 0x20, 0x14, 0xa2, 0x04, 0x62, 0x05, 0xa1, 0x80, 0xc9, 0x8c, - 0x23, 0x22, 0x9a, 0x00, 0x95, 0xbf, 0x93, 0x07, 0xb4, 0xff, 0xc2, 0x07, 0xc1, 0x83, 0x13, 0x07, 0xb0, 0x1b, 0xe3, - 0x61, 0xf7, 0xae, 0x83, 0x26, 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0x93, 0x09, 0xc0, 0x03, 0xa1, 0x82, 0xc2, 0x06, - 0xc1, 0x82, 0x63, 0xe0, 0xd7, 0x08, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x06, 0x4b, 0x93, - 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x40, 0x63, 0x03, 0x25, 0x0d, 0x00, 0x91, 0x69, 0x93, 0x89, - 0x09, 0x20, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x26, 0x05, 0x4e, 0x95, 0xef, 0x10, 0x30, 0x13, 0x93, 0x07, 0xa0, - 0x0a, 0xaa, 0x8c, 0x63, 0x12, 0xf5, 0x04, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0xbf, 0x9f, 0xef, 0x20, 0xe0, 0x36, - 0x83, 0x27, 0x0d, 0x00, 0x42, 0x04, 0x41, 0x80, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, 0xa6, 0x07, 0xb7, 0x05, 0x20, - 0x00, 0x13, 0x06, 0xc4, 0xff, 0x33, 0x85, 0x37, 0x01, 0x74, 0x10, 0x93, 0x85, 0x45, 0x00, 0xef, 0x10, 0xf0, 0x02, - 0x2a, 0x84, 0x93, 0x09, 0x30, 0x0c, 0xef, 0x20, 0x00, 0x36, 0x63, 0x03, 0x94, 0x01, 0xc1, 0x49, 0x13, 0xf5, 0xf9, - 0x0f, 0xe5, 0xae, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x10, 0xf4, 0xa4, 0x03, 0x25, 0x0d, 0x00, 0x93, 0x07, - 0xf0, 0x1f, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0xe4, 0xa7, 0x04, 0x91, 0x67, 0x26, 0x05, 0x93, 0x87, 0x07, - 0x20, 0x3e, 0x95, 0x55, 0xbd, 0x42, 0x04, 0x41, 0x80, 0x91, 0x47, 0xe3, 0x1c, 0xf4, 0xa0, 0xc1, 0x45, 0x68, 0x10, - 0xef, 0xe0, 0x1f, 0x98, 0x68, 0x10, 0xef, 0x10, 0x80, 0x7c, 0xef, 0x30, 0xa0, 0x20, 0xef, 0x20, 0xa0, 0x2e, 0x91, - 0x45, 0x13, 0x05, 0x00, 0x06, 0xef, 0x30, 0xc0, 0x42, 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x2f, 0x93, 0x07, 0xa0, 0x0a, - 0xe3, 0x0e, 0xf4, 0xe2, 0x93, 0x09, 0xc0, 0x03, 0x59, 0xbf, 0x42, 0x04, 0x41, 0x80, 0x93, 0x07, 0x00, 0x03, 0xe3, - 0x1c, 0xf4, 0x9c, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0x1f, 0x94, 0x68, 0x10, 0xef, 0x10, 0x80, 0x78, 0xef, 0x30, - 0xa0, 0x1c, 0xef, 0x20, 0xa0, 0x2a, 0x93, 0x05, 0x00, 0x03, 0x13, 0x05, 0x10, 0x06, 0x7d, 0xbf, 0x42, 0x04, 0x41, - 0x80, 0x8d, 0x47, 0xe3, 0x17, 0xf4, 0x9a, 0xef, 0x30, 0xe0, 0x1a, 0xef, 0x20, 0xe0, 0x28, 0x8d, 0x45, 0x13, 0x05, - 0x20, 0x06, 0xef, 0x30, 0x00, 0x3d, 0x2a, 0x84, 0xef, 0x20, 0x00, 0x2a, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x14, 0xf4, - 0xfa, 0xef, 0xe0, 0x7f, 0xf0, 0x05, 0xb3, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x1f, 0xf4, 0x96, 0xef, 0x30, - 0xe0, 0x17, 0x8d, 0x45, 0x13, 0x05, 0x30, 0x06, 0xef, 0x30, 0x40, 0x3a, 0xb1, 0xb4, 0x42, 0x04, 0x41, 0x80, 0x93, - 0x07, 0x00, 0x03, 0xe3, 0x11, 0xf4, 0x96, 0xef, 0x30, 0x20, 0x16, 0xef, 0x20, 0x50, 0x6f, 0xb7, 0x15, 0x20, 0x00, - 0x2a, 0xd6, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, 0xef, 0x30, 0x60, 0x26, 0x11, - 0x46, 0x6c, 0x10, 0x13, 0x05, 0x00, 0x0c, 0xef, 0x30, 0xa0, 0x25, 0xef, 0x20, 0xc0, 0x21, 0x93, 0x05, 0x00, 0x03, - 0x13, 0x05, 0x00, 0x07, 0xef, 0x30, 0xc0, 0x35, 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x22, 0x93, 0x07, 0xa0, 0x0a, 0xe3, - 0x1a, 0xf4, 0xf2, 0xef, 0xe0, 0x3f, 0xe9, 0x75, 0xb1, 0x93, 0x17, 0x04, 0x01, 0xc1, 0x83, 0x3d, 0x47, 0xe3, 0x74, - 0xf7, 0x90, 0xef, 0x30, 0x80, 0x10, 0xef, 0x20, 0xb0, 0x69, 0xaa, 0x8c, 0x01, 0x45, 0xef, 0x20, 0xd0, 0x45, 0x41, - 0x46, 0x93, 0x85, 0x0a, 0x00, 0x01, 0x45, 0xef, 0x20, 0xf0, 0x46, 0xef, 0x20, 0x00, 0x1d, 0xb7, 0x15, 0x20, 0x00, - 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, 0x66, 0xd6, 0xef, 0x30, 0x40, 0x1f, 0x11, - 0x46, 0x6c, 0x10, 0x13, 0x05, 0x00, 0x0c, 0xef, 0x30, 0x80, 0x1e, 0x85, 0x45, 0x13, 0x05, 0x10, 0x04, 0xef, 0x30, - 0x00, 0x2f, 0x93, 0x07, 0xa0, 0x0a, 0xaa, 0x8c, 0x63, 0x19, 0xf5, 0x00, 0x81, 0x45, 0x13, 0x05, 0x20, 0x04, 0xef, - 0x30, 0xc0, 0x2d, 0x63, 0x05, 0x95, 0x01, 0xef, 0x20, 0xa0, 0x1a, 0x5d, 0xbd, 0x42, 0x04, 0x41, 0x80, 0x93, 0x0d, - 0x04, 0xff, 0xef, 0x20, 0xc0, 0x19, 0xee, 0x8c, 0x22, 0x9d, 0x93, 0x07, 0x00, 0x09, 0xb3, 0x05, 0x9d, 0x41, 0x63, - 0xe5, 0x97, 0x09, 0x66, 0x86, 0x01, 0x45, 0xef, 0x20, 0xd0, 0x3f, 0xe6, 0x85, 0x13, 0x05, 0x40, 0x04, 0xef, 0x30, - 0x40, 0x2a, 0x13, 0x07, 0xa0, 0x0a, 0xe3, 0x11, 0xe5, 0xe8, 0x2a, 0xce, 0x81, 0x45, 0x13, 0x05, 0x50, 0x04, 0xef, - 0x30, 0x00, 0x29, 0xf2, 0x47, 0xaa, 0x8c, 0xe3, 0x17, 0xf5, 0xe6, 0x01, 0x45, 0xef, 0x20, 0x30, 0x3b, 0x93, 0x85, - 0x0a, 0x00, 0x41, 0x46, 0x01, 0x45, 0xef, 0x20, 0x50, 0x3c, 0x93, 0x07, 0xf0, 0x03, 0xb7, 0x05, 0x20, 0x00, 0x63, - 0xe1, 0xb7, 0x07, 0x93, 0x85, 0x05, 0x01, 0x01, 0x45, 0x6e, 0x86, 0xef, 0x20, 0xd0, 0x3a, 0xee, 0x85, 0x13, 0x05, - 0x60, 0x04, 0xef, 0x30, 0x40, 0x25, 0xe3, 0x1b, 0x95, 0xe3, 0x81, 0x45, 0x13, 0x05, 0xa0, 0x04, 0xef, 0x30, 0x60, - 0x24, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x12, 0xf5, 0xe2, 0xef, 0x20, 0x10, 0x58, 0x93, 0x07, 0x00, 0x05, 0x23, 0xaa, - 0xf9, 0x06, 0xb1, 0xb1, 0x13, 0x06, 0x00, 0x09, 0x01, 0x45, 0xef, 0x20, 0x50, 0x37, 0x93, 0x05, 0x00, 0x09, 0x13, - 0x05, 0x30, 0x04, 0xef, 0x30, 0xa0, 0x21, 0x13, 0x07, 0xa0, 0x0a, 0xe3, 0x1c, 0xe5, 0xde, 0x93, 0x8c, 0x0c, 0xf7, - 0xb1, 0xb7, 0x93, 0x85, 0x05, 0x01, 0x01, 0x45, 0x13, 0x06, 0x00, 0x04, 0xef, 0x20, 0xd0, 0x34, 0x93, 0x05, 0x00, - 0x04, 0x13, 0x05, 0x70, 0x04, 0xef, 0x30, 0x20, 0x1f, 0xe3, 0x1a, 0x95, 0xdd, 0x13, 0x04, 0x04, 0xfb, 0x93, 0x0c, - 0x00, 0x08, 0x93, 0x0d, 0xa0, 0x0a, 0xb3, 0x05, 0x8d, 0x40, 0x63, 0xe0, 0x8c, 0x02, 0x22, 0x86, 0x01, 0x45, 0xef, - 0x20, 0x10, 0x32, 0xa2, 0x85, 0x13, 0x05, 0x90, 0x04, 0xef, 0x30, 0x80, 0x1c, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x13, - 0xf5, 0xda, 0x85, 0xbf, 0x01, 0x45, 0x13, 0x06, 0x00, 0x08, 0xef, 0x20, 0x30, 0x30, 0x93, 0x05, 0x00, 0x08, 0x13, - 0x05, 0x80, 0x04, 0xef, 0x30, 0x80, 0x1a, 0xe3, 0x15, 0xb5, 0xd9, 0x13, 0x04, 0x04, 0xf8, 0x7d, 0xbf, 0x42, 0x04, - 0x41, 0x80, 0xa1, 0x47, 0x63, 0x10, 0xf4, 0xf6, 0x03, 0x44, 0x1d, 0x00, 0xbd, 0x47, 0xe3, 0xe8, 0x87, 0xd6, 0x83, - 0x2c, 0x4d, 0x00, 0xfd, 0x57, 0xe3, 0x83, 0xfc, 0xd6, 0x93, 0x19, 0xa4, 0x00, 0x13, 0x85, 0x09, 0x40, 0xef, 0xe0, - 0x8f, 0xe6, 0x13, 0x07, 0xa0, 0x0a, 0x2a, 0x8d, 0xe3, 0x18, 0xe5, 0xd4, 0x93, 0x89, 0x09, 0x20, 0x4e, 0x85, 0xef, - 0xe0, 0x4f, 0xe5, 0xaa, 0x8d, 0xe3, 0x10, 0xa5, 0xd5, 0xe6, 0x85, 0x4e, 0x85, 0xef, 0x10, 0x60, 0x1b, 0xe3, 0x1a, - 0xb5, 0xd3, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf5, 0x85, 0x47, 0x33, 0x94, 0x87, 0x00, 0x1c, 0x43, 0x5d, - 0x8c, 0x00, 0xc3, 0x91, 0xbe, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0x63, 0x1d, 0xf4, 0xee, 0x83, 0x45, 0x1d, 0x00, - 0xbd, 0x47, 0xe3, 0xe5, 0xb7, 0xd0, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf5, 0xd1, 0x49, 0xb3, 0xd7, 0xb7, - 0x00, 0x85, 0x8b, 0xe3, 0x88, 0x07, 0xc8, 0x37, 0x15, 0x20, 0x00, 0x13, 0x05, 0x05, 0x08, 0xef, 0xe0, 0x6f, 0xeb, - 0x85, 0x47, 0xe3, 0x07, 0xf5, 0xb4, 0x89, 0x47, 0xe3, 0x0c, 0xf5, 0xc6, 0xe9, 0xb9, 0xef, 0x10, 0x90, 0x43, 0xef, - 0xe0, 0x8f, 0xd8, 0x6f, 0xf0, 0xef, 0xe6, 0xef, 0x00, 0xc0, 0x6f, 0x6f, 0xf0, 0xef, 0xe6, 0xef, 0x00, 0x30, 0x4e, - 0x41, 0x14, 0xaa, 0x86, 0x63, 0x0b, 0x05, 0xea, 0x8d, 0x45, 0x13, 0x85, 0xcd, 0x3d, 0x36, 0xce, 0x71, 0x24, 0xf2, - 0x46, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x45, 0x93, 0x85, 0xcd, 0x3d, 0x13, 0x05, 0x49, 0x64, 0x09, 0x24, - 0xf2, 0x46, 0x09, 0x47, 0x85, 0x47, 0x63, 0x83, 0xe6, 0x00, 0x89, 0x47, 0x83, 0xc6, 0x89, 0x07, 0x37, 0x56, 0x10, - 0x00, 0xb7, 0x55, 0x10, 0x00, 0x22, 0x87, 0x13, 0x06, 0xc6, 0x47, 0x93, 0x85, 0xc5, 0x3f, 0x13, 0x05, 0x49, 0x64, - 0xa3, 0x8c, 0xf9, 0x06, 0xd9, 0x2a, 0xef, 0xe0, 0x8f, 0xce, 0xef, 0xe0, 0x8f, 0xff, 0x62, 0x47, 0x85, 0x47, 0x23, - 0x00, 0xf7, 0x00, 0xef, 0x00, 0xe0, 0x5a, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x11, 0xf5, 0xd6, 0x25, 0x29, - 0x63, 0x1e, 0x85, 0xd4, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xf4, 0xb1, 0xeb, 0x83, 0xa7, 0x4b, 0x07, 0x13, - 0x07, 0xfb, 0x00, 0xfd, 0x17, 0x63, 0x64, 0xf7, 0x04, 0x05, 0x45, 0xef, 0x20, 0xb0, 0x17, 0x03, 0xa6, 0x4b, 0x07, - 0xb7, 0x09, 0x20, 0x00, 0x93, 0x85, 0x09, 0x00, 0x13, 0x85, 0x09, 0x00, 0xef, 0x20, 0xf0, 0x25, 0x37, 0x14, 0x20, - 0x00, 0x13, 0x05, 0x04, 0x02, 0xef, 0x20, 0x50, 0x34, 0x03, 0xa5, 0x4b, 0x07, 0x93, 0x87, 0x09, 0x00, 0x41, 0x46, - 0x3e, 0x95, 0x93, 0x05, 0x04, 0x02, 0xef, 0x30, 0x00, 0x5f, 0x83, 0xa7, 0x4b, 0x07, 0xc1, 0x07, 0x23, 0xaa, 0xfb, - 0x06, 0xef, 0x00, 0xf0, 0x1b, 0x13, 0x04, 0xa0, 0x0a, 0x63, 0x0a, 0x85, 0xce, 0xef, 0xe0, 0x8f, 0xfe, 0x63, 0x16, - 0x85, 0xce, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x06, 0x4d, 0x93, - 0x85, 0xc5, 0x3f, 0x13, 0x05, 0x45, 0x40, 0x25, 0x22, 0xef, 0xe0, 0x2f, 0xb7, 0xef, 0x20, 0x70, 0x32, 0xef, 0x00, - 0xb0, 0x3a, 0xef, 0x00, 0xb0, 0x31, 0xef, 0xe0, 0xaf, 0xf9, 0x6f, 0xf0, 0xaf, 0xcb, 0x2a, 0x87, 0x81, 0x47, 0x01, - 0x45, 0x63, 0x93, 0xc7, 0x00, 0x82, 0x80, 0xb3, 0x06, 0xf7, 0x00, 0x33, 0x88, 0xf5, 0x00, 0x83, 0xc6, 0x06, 0x00, - 0x03, 0x48, 0x08, 0x00, 0x85, 0x07, 0xb3, 0xc6, 0x06, 0x01, 0x55, 0x8d, 0x13, 0x75, 0xf5, 0x0f, 0xf9, 0xbf, 0xb7, - 0x37, 0x20, 0x00, 0x37, 0x37, 0x20, 0x00, 0x03, 0xa8, 0xc7, 0xf5, 0x83, 0x27, 0x87, 0xf5, 0xaa, 0x86, 0x13, 0x07, - 0x87, 0xf5, 0x01, 0x45, 0x63, 0x13, 0xf8, 0x00, 0x82, 0x80, 0x37, 0x26, 0x20, 0x00, 0x13, 0x06, 0xc6, 0x08, 0x93, - 0x08, 0xf0, 0x7f, 0x63, 0x01, 0xb5, 0x02, 0x33, 0x0e, 0xf6, 0x00, 0x03, 0x4e, 0x0e, 0x00, 0x05, 0x05, 0x33, 0x83, - 0xa6, 0x00, 0xa3, 0x0f, 0xc3, 0xff, 0x85, 0x07, 0x63, 0xf3, 0xf8, 0x00, 0x81, 0x47, 0xe3, 0x11, 0xf8, 0xfe, 0x1c, - 0xc3, 0x82, 0x80, 0xb7, 0x36, 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x86, 0xf5, 0x83, 0xa7, 0xc7, 0xf5, - 0x93, 0x86, 0x86, 0xf5, 0x33, 0x87, 0xe7, 0x40, 0x63, 0x56, 0x07, 0x00, 0x05, 0x66, 0x13, 0x06, 0x06, 0x80, 0x32, - 0x97, 0x63, 0x5b, 0xe5, 0x00, 0x33, 0x85, 0xa7, 0x40, 0x85, 0x67, 0x93, 0x87, 0x07, 0x80, 0x63, 0xf3, 0xa7, 0x00, - 0x3e, 0x95, 0x88, 0xc2, 0x82, 0x80, 0xb7, 0x36, 0x20, 0x00, 0x03, 0xa8, 0xc6, 0xf5, 0x13, 0x07, 0xf0, 0x7f, 0x13, - 0x86, 0xc6, 0xf5, 0x93, 0x07, 0x18, 0x00, 0x63, 0x73, 0xf7, 0x00, 0x81, 0x47, 0xb7, 0x36, 0x20, 0x00, 0x83, 0xa8, - 0x86, 0xf5, 0x37, 0x27, 0x20, 0x00, 0x93, 0x85, 0x86, 0xf5, 0x13, 0x07, 0xc7, 0x08, 0x63, 0x9f, 0xf8, 0x00, 0x93, - 0x88, 0x17, 0x80, 0x93, 0x86, 0x17, 0x00, 0x63, 0x93, 0x08, 0x00, 0x81, 0x46, 0x94, 0xc1, 0xba, 0x96, 0x93, 0x05, - 0xa0, 0x02, 0x23, 0x80, 0xb6, 0x00, 0x42, 0x97, 0x23, 0x00, 0xa7, 0x00, 0x1c, 0xc2, 0x82, 0x80, 0x82, 0x80, 0x39, - 0x71, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x06, 0xce, 0x36, 0xd6, 0x3a, 0xd8, 0x3e, 0xda, 0x42, 0xdc, 0x46, 0xde, - 0xaa, 0x84, 0x2e, 0x89, 0x32, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0xdf, 0x96, 0x63, 0x14, 0x09, 0x00, 0xef, 0xe0, 0x5f, - 0x96, 0x19, 0xe0, 0xef, 0xe0, 0xff, 0x95, 0x7c, 0x10, 0x3e, 0xc6, 0xef, 0x30, 0x20, 0x13, 0xaa, 0x85, 0x37, 0x55, - 0x10, 0x00, 0x13, 0x05, 0x85, 0x60, 0xef, 0x30, 0x20, 0x38, 0x37, 0x55, 0x10, 0x00, 0x4a, 0x86, 0xa6, 0x85, 0x13, - 0x05, 0x05, 0x61, 0xef, 0x30, 0x20, 0x37, 0xb2, 0x45, 0x22, 0x85, 0xef, 0x30, 0x80, 0x33, 0x37, 0x55, 0x10, 0x00, - 0x13, 0x05, 0xc5, 0x61, 0xef, 0x30, 0xe0, 0x35, 0xb9, 0x29, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0x21, - 0x61, 0x82, 0x80, 0xae, 0x86, 0x37, 0x56, 0x10, 0x00, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x4b, - 0x13, 0x05, 0x05, 0x62, 0x9d, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, 0x83, - 0xa6, 0x47, 0x10, 0x63, 0x7e, 0xd7, 0x00, 0x0a, 0x07, 0x3e, 0x97, 0x18, 0x43, 0x18, 0xc1, 0x03, 0xa7, 0x07, 0x10, - 0x13, 0x05, 0xa0, 0x0a, 0x05, 0x07, 0x23, 0xa0, 0xe7, 0x10, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, - 0x11, 0x26, 0xca, 0xb7, 0x34, 0x20, 0x00, 0x83, 0xa7, 0x04, 0xf6, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, - 0x52, 0xc4, 0x11, 0x47, 0x63, 0x6f, 0xf7, 0x0c, 0x37, 0x57, 0x10, 0x00, 0x8a, 0x07, 0x13, 0x07, 0x87, 0x64, 0xba, - 0x97, 0x9c, 0x43, 0x2a, 0x84, 0x93, 0x84, 0x04, 0xf6, 0x82, 0x87, 0x81, 0x45, 0xef, 0x30, 0x20, 0x31, 0xb7, 0x37, - 0x20, 0x00, 0x23, 0x92, 0xa7, 0xf6, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x86, 0x87, 0x88, 0xef, 0x20, 0xd0, 0x6f, 0x9c, - 0x40, 0x85, 0x07, 0x81, 0xa8, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0x07, 0xf6, 0x93, 0x07, 0xc0, 0x0f, 0x63, 0xf1, - 0xa7, 0x02, 0x62, 0x44, 0x9d, 0x47, 0xf2, 0x40, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x9c, 0xc0, 0xd2, 0x44, 0x37, - 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x45, 0x62, 0x05, 0x61, 0x2d, 0xbf, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, - 0x49, 0xf6, 0x83, 0x55, 0x09, 0x00, 0xef, 0x30, 0xa0, 0x2b, 0xb7, 0x37, 0x20, 0x00, 0xa3, 0x86, 0x87, 0x88, 0x23, - 0x10, 0xa9, 0x00, 0x8d, 0x47, 0x5d, 0xf4, 0x9c, 0xc0, 0x91, 0xa8, 0x37, 0x39, 0x20, 0x00, 0x03, 0x27, 0x89, 0xf6, - 0x93, 0x07, 0xb0, 0x0f, 0x13, 0x09, 0x89, 0xf6, 0x63, 0xf4, 0xe7, 0x00, 0xef, 0xe0, 0x3f, 0x81, 0x83, 0x27, 0x09, - 0x00, 0x37, 0x3a, 0x20, 0x00, 0x13, 0x0a, 0x4a, 0xf6, 0xb7, 0x39, 0x20, 0x00, 0x93, 0x89, 0xc9, 0x88, 0x83, 0x55, - 0x0a, 0x00, 0xce, 0x97, 0x23, 0x81, 0x87, 0x00, 0x22, 0x85, 0xef, 0x30, 0xa0, 0x26, 0x83, 0x27, 0x09, 0x00, 0x03, - 0xc7, 0x19, 0x00, 0x23, 0x10, 0xaa, 0x00, 0x85, 0x07, 0x23, 0x20, 0xf9, 0x00, 0xe3, 0xfd, 0xe7, 0xf4, 0xf2, 0x40, - 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, - 0x93, 0xa7, 0xf6, 0x3d, 0xbf, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x69, 0xf6, 0x13, 0x14, 0x85, 0x00, 0xb7, 0x39, - 0x20, 0x00, 0x03, 0x55, 0x09, 0x00, 0x93, 0x89, 0x49, 0xf6, 0x83, 0xd7, 0x09, 0x00, 0x49, 0x8c, 0x23, 0x10, 0x89, - 0x00, 0xe3, 0x8d, 0x87, 0xf0, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0x44, 0x62, 0x99, 0x47, 0x89, 0x45, 0x9c, 0xc0, - 0x95, 0x3d, 0x93, 0x05, 0x44, 0x62, 0x62, 0x44, 0x03, 0xd7, 0x09, 0x00, 0x83, 0x56, 0x09, 0x00, 0xf2, 0x40, 0xd2, - 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x86, 0x62, - 0x13, 0x05, 0x45, 0x64, 0x05, 0x61, 0x6f, 0xf0, 0x3f, 0xdd, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0xb7, - 0x25, 0x10, 0x00, 0x37, 0x25, 0x10, 0x00, 0x23, 0xa0, 0x07, 0x10, 0x23, 0xa2, 0x07, 0x10, 0x93, 0x85, 0x05, 0xf8, - 0xb7, 0x37, 0x20, 0x00, 0x13, 0x05, 0x25, 0xfb, 0x23, 0xa0, 0x07, 0xf6, 0x6f, 0x20, 0xb0, 0x52, 0x11, 0xed, 0x01, - 0x11, 0x06, 0xce, 0x2a, 0xc6, 0xef, 0xe0, 0x2f, 0xf2, 0x32, 0x45, 0xf2, 0x40, 0x13, 0x06, 0xe0, 0x0f, 0x81, 0x45, - 0x05, 0x61, 0x6f, 0x30, 0x40, 0x25, 0x13, 0x06, 0xe0, 0x0f, 0x81, 0x45, 0xdd, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x83, - 0xa7, 0x07, 0xf6, 0x13, 0x05, 0xa0, 0x0a, 0x99, 0xc3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, - 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, 0xf6, 0x1c, 0x40, 0x06, 0xc6, 0x15, 0x47, 0x63, 0x98, 0xe7, 0x00, 0x13, - 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x81, 0xe7, 0x13, 0x05, 0x50, 0x05, 0xcd, 0xbf, - 0xef, 0x20, 0x90, 0x50, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x19, 0xf5, 0xfe, 0x01, 0x00, 0x18, 0x40, 0x91, 0x47, 0xe3, - 0xcd, 0xe7, 0xfc, 0x99, 0x47, 0x1c, 0xc0, 0xd9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x20, 0x10, 0x50, 0x93, 0x07, - 0xa0, 0x0a, 0x63, 0x04, 0xf5, 0x00, 0xef, 0x20, 0x70, 0x51, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x95, - 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, - 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x99, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, - 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x9d, 0x47, 0x13, 0x05, 0xa0, 0x0a, - 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x37, 0x35, 0x20, 0x00, 0x13, 0x05, 0xc5, 0x88, 0x82, - 0x80, 0x01, 0x11, 0x26, 0xca, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0xaa, 0x84, 0x19, 0xe1, 0xef, 0xe0, - 0x2f, 0xe3, 0x83, 0xc7, 0x14, 0x00, 0x13, 0x07, 0xc0, 0x0f, 0x13, 0x05, 0x50, 0x05, 0x63, 0x65, 0xf7, 0x06, 0x37, - 0x39, 0x20, 0x00, 0x13, 0x04, 0xc9, 0x98, 0x23, 0x20, 0x04, 0x10, 0x03, 0xc7, 0x04, 0x00, 0xa3, 0x00, 0xf4, 0x00, - 0x03, 0xc6, 0x14, 0x00, 0x23, 0x00, 0xe4, 0x00, 0x93, 0x85, 0x24, 0x00, 0x13, 0x05, 0x24, 0x00, 0xef, 0x30, 0x00, - 0x10, 0x83, 0xc9, 0x14, 0x00, 0x13, 0x05, 0xc9, 0x98, 0x13, 0x09, 0xc9, 0x98, 0x93, 0x84, 0x29, 0x00, 0xa6, 0x85, - 0xef, 0x30, 0x60, 0x08, 0xa2, 0x94, 0x23, 0x80, 0xa4, 0x00, 0x4e, 0x94, 0x21, 0x81, 0x93, 0x87, 0x49, 0x00, 0xa3, - 0x01, 0xa4, 0x00, 0xfd, 0x56, 0x13, 0xf7, 0x37, 0x00, 0x19, 0xef, 0x89, 0x83, 0x23, 0x22, 0xf9, 0x10, 0xef, 0x20, - 0xb0, 0x45, 0x13, 0x05, 0xa0, 0x0a, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, - 0x80, 0x33, 0x07, 0xf9, 0x00, 0x23, 0x00, 0xd7, 0x00, 0x85, 0x07, 0xd1, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, - 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, 0x83, 0xa7, 0x47, 0x10, 0x63, 0x14, 0xf7, 0x00, 0x6f, 0x20, 0x30, 0x3e, 0x13, - 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa0, 0x07, 0xf6, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, - 0x93, 0x07, 0x00, 0x08, 0x73, 0xa0, 0x47, 0x30, 0x93, 0x06, 0x70, 0x3e, 0x09, 0x46, 0x93, 0x05, 0x60, 0x04, 0x37, - 0x05, 0x10, 0x01, 0xef, 0x20, 0x30, 0x52, 0x8d, 0x45, 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, 0x70, 0x52, 0x37, 0x05, - 0x10, 0x01, 0xef, 0x20, 0xf0, 0x4f, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x10, 0x50, 0xfd, 0x56, 0x01, 0x46, 0x93, - 0x05, 0x60, 0x04, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x90, 0x4f, 0xb2, 0x40, 0xb7, 0x07, 0x20, 0x01, 0x23, 0xac, - 0x07, 0x00, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x89, 0x2c, 0xb2, 0x40, 0x41, 0x01, 0x45, 0xb7, 0x41, - 0x11, 0x22, 0xc4, 0xb7, 0x07, 0x20, 0x01, 0x06, 0xc6, 0x23, 0xac, 0x07, 0x00, 0x2a, 0x84, 0x37, 0x05, 0x20, 0x01, - 0xef, 0x20, 0x50, 0x4b, 0x93, 0x07, 0x80, 0x3e, 0x13, 0x05, 0x80, 0x3e, 0x63, 0xe3, 0x87, 0x00, 0x22, 0x85, 0xb7, - 0x07, 0x20, 0x01, 0x98, 0x4f, 0x13, 0x84, 0x87, 0x01, 0xe3, 0x6d, 0xa7, 0xfe, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, - 0xb0, 0x49, 0xb2, 0x40, 0x23, 0x20, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x11, 0xe1, 0x82, 0x80, 0x01, - 0x00, 0x7d, 0x15, 0xe5, 0xbf, 0x6f, 0xf0, 0x9f, 0xb3, 0x39, 0xa4, 0x01, 0x11, 0x26, 0xca, 0xaa, 0x84, 0x37, 0x05, - 0x20, 0x01, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x56, 0xc2, 0x06, 0xce, 0x22, 0xcc, 0x2e, 0x89, 0x93, 0x09, 0xa0, - 0x0a, 0xef, 0x20, 0x50, 0x45, 0x37, 0x0a, 0x20, 0x01, 0x93, 0x0a, 0x80, 0x3e, 0x82, 0x94, 0x2a, 0x84, 0x63, 0x0c, - 0x35, 0x03, 0x83, 0x27, 0x8a, 0x01, 0x63, 0x7a, 0xf9, 0x04, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0xc4, 0x65, 0x85, - 0x45, 0xef, 0xf0, 0x9f, 0xb6, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0x05, 0xc4, 0x65, 0xa6, 0x86, - 0x13, 0x06, 0x06, 0x66, 0x13, 0x05, 0x45, 0x64, 0xef, 0xf0, 0x9f, 0xad, 0x13, 0x04, 0x50, 0x05, 0x37, 0x05, 0x20, - 0x01, 0xef, 0x20, 0x30, 0x41, 0xf2, 0x40, 0x22, 0x85, 0x62, 0x44, 0xb7, 0x07, 0x20, 0x01, 0x23, 0xac, 0x07, 0x00, - 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xe3, 0xf0, 0x2a, 0xfb, 0x41, - 0x22, 0x69, 0xbf, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x87, 0x00, 0x1c, 0xc7, 0x82, 0x80, 0x41, 0x11, - 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, 0xc1, 0xa9, 0x44, 0x03, 0x45, 0x04, - 0x00, 0x11, 0xe5, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xef, 0xf0, 0xdf, 0xa1, 0x83, 0x47, - 0x04, 0x00, 0x63, 0x94, 0x97, 0x00, 0xef, 0xf0, 0x7f, 0xa6, 0x05, 0x04, 0xf9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0x25, - 0x37, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x05, 0xf5, 0x00, 0xef, 0xe0, 0xaf, 0xbd, 0x01, 0xa0, 0xb2, 0x40, 0x41, 0x01, - 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x44, 0x20, 0x00, 0x13, 0x06, 0xc0, 0x1f, 0x81, 0x45, 0x13, 0x05, 0x04, - 0xe0, 0x06, 0xc6, 0x26, 0xc2, 0xef, 0x20, 0xb0, 0x6f, 0x13, 0x05, 0x04, 0xe0, 0x93, 0x05, 0xc0, 0x1f, 0xef, 0x20, - 0xb0, 0x67, 0x93, 0x04, 0x04, 0xe0, 0xb2, 0x40, 0x22, 0x44, 0x23, 0xae, 0xa4, 0x1e, 0x92, 0x44, 0x41, 0x01, 0x82, - 0x80, 0x41, 0x11, 0x37, 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, 0xc0, 0x1f, 0x13, 0x04, 0x05, 0xe0, 0x13, 0x05, - 0x05, 0xe0, 0x06, 0xc6, 0xef, 0x20, 0xf0, 0x64, 0x03, 0x27, 0xc4, 0x1f, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xa7, - 0x00, 0x93, 0x07, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x3e, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, - 0xaa, 0x87, 0x63, 0x6e, 0xa7, 0x00, 0x13, 0x77, 0x35, 0x00, 0x01, 0x45, 0x11, 0xeb, 0x37, 0x45, 0x20, 0x00, 0x13, - 0x05, 0x05, 0xe0, 0xf1, 0x9b, 0xaa, 0x97, 0x88, 0x43, 0x82, 0x80, 0x01, 0x45, 0x82, 0x80, 0x93, 0x07, 0xb0, 0x1f, - 0x63, 0xec, 0xa7, 0x00, 0x93, 0x77, 0x35, 0x00, 0x81, 0xeb, 0xb7, 0x47, 0x20, 0x00, 0x71, 0x99, 0x93, 0x87, 0x07, - 0xe0, 0x3e, 0x95, 0x0c, 0xc1, 0x82, 0x80, 0x41, 0x11, 0x37, 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, 0xc0, 0x1f, - 0x13, 0x04, 0x05, 0xe0, 0x13, 0x05, 0x05, 0xe0, 0x06, 0xc6, 0xef, 0x20, 0x70, 0x5d, 0xb2, 0x40, 0x23, 0x2e, 0xa4, - 0x1e, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, 0x63, 0x61, 0xa7, 0x02, 0x93, 0x77, 0x35, 0x00, - 0x13, 0x07, 0x50, 0x05, 0x89, 0xef, 0x41, 0x11, 0x06, 0xc6, 0x5d, 0x37, 0xc9, 0x37, 0xb2, 0x40, 0x13, 0x07, 0xa0, - 0x0a, 0x3a, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0x50, 0x05, 0x3a, 0x85, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, - 0xef, 0x00, 0x10, 0x71, 0xb2, 0x40, 0xb7, 0x07, 0x00, 0x02, 0x0d, 0x47, 0xf8, 0xcb, 0x13, 0x05, 0xa0, 0x0a, 0x41, - 0x01, 0x82, 0x80, 0x73, 0x00, 0x50, 0x10, 0x82, 0x80, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, - 0x52, 0xcc, 0x06, 0xd6, 0x2a, 0x84, 0xae, 0x84, 0x32, 0x89, 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x07, 0x39, 0x41, 0x33, - 0x05, 0x34, 0x01, 0x63, 0x6c, 0xfa, 0x02, 0x71, 0x56, 0x93, 0x57, 0x29, 0x00, 0xb3, 0x87, 0xc7, 0x02, 0x93, 0x75, - 0xc9, 0xff, 0x33, 0x05, 0xb4, 0x00, 0xae, 0x94, 0x33, 0x86, 0x27, 0x01, 0x11, 0xc6, 0x9c, 0x40, 0x6c, 0x00, 0x3e, - 0xc6, 0xef, 0x20, 0xd0, 0x56, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, - 0x82, 0x80, 0xb3, 0x87, 0x34, 0x01, 0x9c, 0x43, 0x11, 0x46, 0x6c, 0x00, 0x3e, 0xc6, 0x91, 0x09, 0xef, 0x20, 0xb0, - 0x54, 0x7d, 0xb7, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x52, 0xcc, 0x06, 0xd6, 0x2a, 0x84, - 0xae, 0x84, 0x32, 0x89, 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x07, 0x39, 0x41, 0xb3, 0x85, 0x34, 0x01, 0x63, 0x6d, 0xfa, - 0x02, 0x71, 0x56, 0x93, 0x57, 0x29, 0x00, 0xb3, 0x87, 0xc7, 0x02, 0x93, 0x75, 0xc9, 0xff, 0x2e, 0x94, 0xa6, 0x95, - 0x33, 0x86, 0x27, 0x01, 0x01, 0xca, 0x1c, 0x40, 0x68, 0x00, 0x3e, 0xc6, 0xef, 0x20, 0x30, 0x50, 0xb2, 0x47, 0x1c, - 0xc0, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0x11, 0x46, - 0x68, 0x00, 0xef, 0x20, 0x70, 0x4e, 0x32, 0x47, 0xb3, 0x07, 0x34, 0x01, 0x91, 0x09, 0x98, 0xc3, 0x75, 0xb7, 0x41, - 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x6f, 0x9c, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, - 0x50, 0x05, 0x23, 0xa6, 0xe7, 0xf6, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa8, 0x87, 0xf6, 0x22, 0x44, 0xb2, 0x40, 0xb7, - 0x37, 0x20, 0x00, 0x23, 0x8a, 0x07, 0xa8, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xa4, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, - 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, 0x99, 0x37, 0x35, 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0xa2, 0x85, 0x13, - 0x06, 0xe0, 0x0f, 0x13, 0x05, 0x45, 0xa9, 0x23, 0x8a, 0x07, 0xb8, 0xef, 0x20, 0xf0, 0x47, 0x22, 0x85, 0x22, 0x44, - 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xb2, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x19, - 0xe1, 0xef, 0xe0, 0xcf, 0x95, 0xb7, 0x34, 0x20, 0x00, 0x83, 0xc7, 0x44, 0xb9, 0x99, 0xcb, 0x37, 0x35, 0x20, 0x00, - 0x13, 0x06, 0xe0, 0x0f, 0x93, 0x85, 0x44, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0xef, 0x20, 0x50, 0x44, 0xa2, 0x85, 0x13, - 0x85, 0x44, 0xb9, 0x13, 0x06, 0xe0, 0x0f, 0xef, 0x20, 0x70, 0x43, 0x22, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x92, 0x44, - 0x41, 0x01, 0x6f, 0xf0, 0x1f, 0xae, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0xc7, 0xf6, 0x82, 0x80, 0x41, 0x11, 0x22, - 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0xc4, 0xf6, 0x26, 0xc2, 0x04, 0x40, 0x06, 0xc6, 0x93, 0x07, 0xa0, 0x0a, - 0x63, 0x89, 0xf4, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x37, - 0x35, 0x20, 0x00, 0x13, 0x05, 0x45, 0xb9, 0xef, 0xf0, 0x3f, 0xaa, 0xe3, 0x13, 0x95, 0xfe, 0x93, 0x07, 0x50, 0x05, - 0x1c, 0xc0, 0xc5, 0xb7, 0x37, 0x35, 0x20, 0x00, 0x83, 0x47, 0x45, 0xa9, 0x85, 0xc3, 0xb7, 0x37, 0x20, 0x00, 0x83, - 0xc7, 0x47, 0xb9, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf6, 0x13, 0x05, - 0x45, 0xa9, 0x6f, 0xf0, 0xff, 0xa6, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xdf, - 0x99, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xf5, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, - 0x6d, 0x71, 0x23, 0x26, 0x11, 0x10, 0x23, 0x24, 0x81, 0x10, 0x23, 0x22, 0x91, 0x10, 0xef, 0xf0, 0xdf, 0x98, 0x93, - 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x04, 0x2a, 0x84, 0xef, 0xf0, 0x5f, 0x9c, 0x63, 0x1b, 0x85, 0x06, 0xef, 0xf0, - 0xdf, 0xa1, 0x83, 0x46, 0x05, 0x00, 0x93, 0x07, 0x20, 0x0a, 0x2a, 0x84, 0x63, 0x80, 0xf6, 0x02, 0x37, 0x56, 0x10, - 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x66, 0x93, 0x85, 0xc5, 0x67, 0x13, 0x05, - 0x45, 0x64, 0xef, 0xf0, 0x6f, 0xeb, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xf7, 0x22, 0x85, 0x82, 0x97, 0xef, - 0xf0, 0xff, 0xaa, 0xef, 0xf0, 0xdf, 0xa8, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x14, 0xf5, 0x08, 0xef, 0xf0, - 0x7f, 0x91, 0x63, 0x10, 0x85, 0x08, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xf6, 0x63, 0x94, 0xa7, 0x04, 0x03, - 0x24, 0x81, 0x10, 0x83, 0x20, 0xc1, 0x10, 0x83, 0x24, 0x41, 0x10, 0x51, 0x61, 0x6f, 0xf0, 0x7f, 0xee, 0xef, 0xf0, - 0xbf, 0x97, 0x81, 0x44, 0x63, 0x14, 0x85, 0x00, 0x93, 0x04, 0xc0, 0x07, 0xef, 0xf0, 0x5f, 0x98, 0x93, 0x07, 0xa0, - 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0xdd, 0xd4, 0x0a, 0x85, 0x23, 0x00, 0x91, 0x00, 0xa3, 0x00, 0x01, 0x00, 0xef, 0xf0, - 0x5f, 0xe3, 0x79, 0xbf, 0x93, 0x04, 0xc0, 0x07, 0xf5, 0xb7, 0xb7, 0x35, 0x20, 0x00, 0x83, 0xc7, 0x45, 0xb9, 0x95, - 0xc3, 0x03, 0x24, 0x81, 0x10, 0x83, 0x20, 0xc1, 0x10, 0x83, 0x24, 0x41, 0x10, 0x37, 0x35, 0x20, 0x00, 0x13, 0x06, - 0xe0, 0x0f, 0x93, 0x85, 0x45, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0x51, 0x61, 0x6f, 0x20, 0x30, 0x2a, 0x83, 0x20, 0xc1, - 0x10, 0x03, 0x24, 0x81, 0x10, 0x83, 0x24, 0x41, 0x10, 0x51, 0x61, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x23, 0xa2, - 0x07, 0x00, 0x21, 0x65, 0x6f, 0x20, 0xc0, 0x1c, 0x41, 0x11, 0x21, 0x65, 0x06, 0xc6, 0xef, 0x20, 0x60, 0x1b, 0xb2, - 0x40, 0xb7, 0x07, 0x01, 0x04, 0x05, 0x47, 0xd8, 0xc3, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, - 0x06, 0xc6, 0x93, 0x07, 0x70, 0x02, 0x2a, 0x84, 0xae, 0x84, 0x63, 0xf4, 0xa7, 0x00, 0xef, 0xd0, 0xff, 0xf4, 0x37, - 0x05, 0x01, 0x04, 0x0a, 0x04, 0x13, 0x05, 0x05, 0x10, 0x2a, 0x94, 0x04, 0xc0, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, - 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x13, 0x87, 0x07, 0x10, 0x93, 0x87, 0x07, 0x1a, 0x23, 0x20, 0x07, - 0x00, 0x11, 0x07, 0xe3, 0x1d, 0xf7, 0xfe, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0xc8, 0xcb, 0x82, 0x80, 0x42, 0x05, - 0xb7, 0x07, 0x01, 0x04, 0xc8, 0xcb, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x88, 0x4b, 0x13, 0x75, 0xf5, 0x0f, 0x82, - 0x80, 0x89, 0x67, 0x37, 0x07, 0x01, 0x04, 0x8d, 0x07, 0x1c, 0xc7, 0x23, 0x2a, 0x07, 0x00, 0x82, 0x80, 0x41, 0x11, - 0x06, 0xc6, 0x22, 0xc4, 0x2a, 0x84, 0xad, 0x37, 0xb7, 0x07, 0x01, 0x04, 0x80, 0xcf, 0xc5, 0x37, 0x65, 0x37, 0x22, - 0x44, 0xb2, 0x40, 0x41, 0x01, 0xa9, 0xb7, 0xb7, 0x06, 0x01, 0x04, 0x9c, 0x46, 0x05, 0x45, 0x13, 0xf7, 0x17, 0x00, - 0x1d, 0xc7, 0x13, 0xf7, 0x07, 0x40, 0x0d, 0x45, 0x1d, 0xe3, 0x98, 0x4a, 0x13, 0x77, 0xf7, 0x0f, 0x19, 0xcf, 0x13, - 0xf7, 0x27, 0x20, 0x09, 0x45, 0x19, 0xeb, 0x13, 0xd7, 0xb7, 0x00, 0x05, 0x8b, 0x11, 0x45, 0x11, 0xe7, 0x13, 0xd5, - 0x87, 0x00, 0x13, 0x45, 0x15, 0x00, 0x05, 0x89, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x88, 0xcf, 0x82, 0x80, 0x01, - 0x11, 0x22, 0xcc, 0x06, 0xce, 0x33, 0x07, 0xb6, 0x00, 0x93, 0x07, 0x00, 0x09, 0x2e, 0x84, 0x63, 0xf8, 0xe7, 0x00, - 0x32, 0xc6, 0x2a, 0xc4, 0xef, 0xd0, 0x5f, 0xe7, 0x32, 0x46, 0x22, 0x45, 0xb7, 0x15, 0x01, 0x04, 0xa2, 0x95, 0xef, - 0xf0, 0xdf, 0xbb, 0xf2, 0x40, 0x62, 0x44, 0x13, 0x05, 0xa0, 0x0a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, - 0x26, 0xca, 0x06, 0xce, 0x33, 0x07, 0xb6, 0x00, 0x93, 0x07, 0x00, 0x08, 0xaa, 0x84, 0x2e, 0x84, 0x63, 0xf6, 0xe7, - 0x00, 0x32, 0xc6, 0xef, 0xd0, 0xdf, 0xe3, 0x32, 0x46, 0x37, 0x25, 0x01, 0x04, 0x13, 0x05, 0x05, 0x80, 0x22, 0x95, - 0x62, 0x44, 0xf2, 0x40, 0xa6, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x6f, 0xf0, 0x5f, 0xbe, 0x39, 0x71, 0x2a, 0xd6, 0x2e, - 0xd4, 0x32, 0xd2, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x06, 0x68, - 0x93, 0x85, 0x05, 0x69, 0x13, 0x05, 0x45, 0x69, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x36, 0xd0, 0x3a, - 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xf0, 0xcf, 0xc5, - 0xef, 0xe0, 0xcf, 0xc8, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, - 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, - 0x73, 0x00, 0x20, 0x30, 0x09, 0x65, 0x6f, 0x10, 0x70, 0x7f, 0x09, 0x65, 0x6f, 0x10, 0xd0, 0x7f, 0x41, 0x11, 0x22, - 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xd0, 0x1f, 0xda, 0xdd, 0x37, 0xb7, 0x07, 0x00, 0x07, 0x83, 0x46, - 0x14, 0x00, 0xd8, 0x43, 0x83, 0x47, 0x04, 0x00, 0xa2, 0x06, 0xdd, 0x8e, 0x83, 0x47, 0x24, 0x00, 0xc2, 0x07, 0xdd, - 0x8e, 0x83, 0x47, 0x34, 0x00, 0xe2, 0x07, 0xd5, 0x8f, 0x93, 0x06, 0xf0, 0x0f, 0x63, 0x85, 0xd7, 0x00, 0x61, 0x9b, - 0x9d, 0x8b, 0x5d, 0x8f, 0x93, 0x77, 0x77, 0xff, 0x03, 0x47, 0x44, 0x00, 0x83, 0x46, 0x94, 0x00, 0xb2, 0x40, 0x0e, - 0x07, 0x21, 0x8b, 0x5d, 0x8f, 0xfd, 0x77, 0xbd, 0x07, 0x7d, 0x8f, 0x83, 0x47, 0x54, 0x00, 0x92, 0x07, 0x5d, 0x8f, - 0xb7, 0x17, 0x80, 0xff, 0xfd, 0x17, 0x7d, 0x8f, 0x83, 0x47, 0xa4, 0x00, 0xa2, 0x07, 0xd5, 0x8f, 0xb2, 0x07, 0xb7, - 0xf6, 0x7f, 0x00, 0xf5, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x80, 0xf8, 0x7d, 0x17, 0xf9, 0x8f, 0x03, 0x47, 0x74, 0x00, - 0xb7, 0x06, 0x80, 0x07, 0x5e, 0x07, 0x75, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x00, 0x88, 0x7d, 0x17, 0xf9, 0x8f, 0x03, - 0x47, 0x64, 0x00, 0xb7, 0x06, 0x00, 0x78, 0x22, 0x44, 0x6e, 0x07, 0x75, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x00, 0x07, - 0x5c, 0xc3, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x87, 0xf7, 0x82, 0x80, 0xb7, 0x07, 0x08, - 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, - 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x13, 0x05, 0xa0, 0x0a, 0x89, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, - 0x05, 0x82, 0x80, 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x65, 0xba, 0x6f, 0xf0, - 0xbf, 0x8c, 0x41, 0x11, 0xb7, 0x07, 0x08, 0x05, 0x22, 0xc4, 0x03, 0xa4, 0xc7, 0x20, 0x37, 0x07, 0x00, 0x04, 0x06, - 0xc6, 0x26, 0xc2, 0xb3, 0x76, 0xe4, 0x00, 0x91, 0xca, 0x37, 0x55, 0x10, 0x00, 0x23, 0xa6, 0xe7, 0x20, 0xa5, 0x45, - 0x13, 0x05, 0x85, 0x69, 0xef, 0xf0, 0x4f, 0xb7, 0xb7, 0x07, 0x80, 0x6b, 0xe1, 0x8f, 0x95, 0xcb, 0x37, 0x07, 0x08, - 0x05, 0x23, 0x26, 0xf7, 0x20, 0xb7, 0x07, 0x00, 0x68, 0x7d, 0x8c, 0x93, 0x04, 0x50, 0x05, 0x11, 0xc8, 0x37, 0x55, - 0x10, 0x00, 0x9d, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xf0, 0xaf, 0xb4, 0xef, 0xd0, 0x9f, 0xc5, 0xb2, 0x40, 0x22, - 0x44, 0x26, 0x85, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0xf7, 0x84, 0x43, - 0x13, 0x07, 0xa0, 0x0a, 0x63, 0x96, 0xe4, 0x00, 0x13, 0x07, 0x50, 0x05, 0x98, 0xc3, 0xe1, 0xbf, 0x93, 0x04, 0xa0, - 0x0a, 0xd9, 0xbf, 0x81, 0x47, 0xb7, 0x05, 0x08, 0x05, 0x13, 0x07, 0x00, 0x20, 0xb3, 0x86, 0xb7, 0x00, 0x90, 0x42, - 0xb3, 0x06, 0xf5, 0x00, 0x91, 0x07, 0x90, 0xc2, 0xe3, 0x99, 0xe7, 0xfe, 0x6f, 0xf0, 0xff, 0xf5, 0x41, 0x11, 0x06, - 0xc6, 0x22, 0xc4, 0x2a, 0x84, 0xef, 0xf0, 0x1f, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, - 0xe7, 0xf6, 0x8d, 0x47, 0x33, 0x95, 0x87, 0x00, 0xb7, 0xb7, 0xaa, 0x02, 0x93, 0x87, 0xa7, 0xaa, 0x3d, 0x8d, 0xb7, - 0x07, 0x08, 0x05, 0x23, 0xa4, 0xa7, 0x20, 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, - 0x65, 0xb8, 0xef, 0xf0, 0x2f, 0xfe, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0xf1, 0x41, 0x11, 0x06, - 0xc6, 0xef, 0xf0, 0x9f, 0xef, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf7, 0x37, 0x07, 0x08, 0x05, 0x13, 0x05, - 0x00, 0x20, 0xf9, 0x9b, 0x23, 0x22, 0xf7, 0x20, 0xef, 0x10, 0xd0, 0x5e, 0xb2, 0x40, 0x39, 0x45, 0x41, 0x01, 0x6f, - 0x10, 0xf0, 0x5f, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf7, 0x1c, 0x43, 0x93, 0xf7, 0xf7, 0xfd, 0x1c, 0xc3, - 0x37, 0x07, 0x08, 0x05, 0x23, 0x22, 0xf7, 0x20, 0x82, 0x80, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf7, 0x1c, - 0x43, 0x93, 0xe7, 0x07, 0x02, 0x1c, 0xc3, 0x37, 0x07, 0x08, 0x05, 0x23, 0x22, 0xf7, 0x20, 0x82, 0x80, 0x33, 0x87, - 0xc5, 0x00, 0xb7, 0x07, 0x08, 0x00, 0x63, 0x7c, 0xf7, 0x06, 0x01, 0x11, 0x22, 0xcc, 0x26, 0xca, 0x4e, 0xc6, 0x06, - 0xce, 0x4a, 0xc8, 0x93, 0xf4, 0x35, 0x00, 0xaa, 0x89, 0x2e, 0x84, 0x13, 0x05, 0x50, 0x05, 0x9d, 0xec, 0x32, 0x89, - 0xef, 0xf0, 0x5f, 0xe7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x47, 0xf7, 0xb7, 0x06, 0x08, 0x05, 0xb7, 0x05, 0x00, - 0x05, 0x13, 0x67, 0x27, 0x00, 0x23, 0xa2, 0xe6, 0x20, 0x93, 0x87, 0x47, 0xf7, 0x0d, 0x47, 0x2e, 0x94, 0xb3, 0x06, - 0x99, 0x40, 0x63, 0x60, 0xd7, 0x02, 0x98, 0x43, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x05, 0xa0, 0x0a, 0x23, 0xa2, 0xe7, - 0x20, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, 0xb3, 0x06, 0x94, 0x00, - 0x90, 0x42, 0xb3, 0x86, 0x99, 0x00, 0x91, 0x04, 0x90, 0xc2, 0xf9, 0xb7, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, - 0x11, 0xaa, 0x85, 0x11, 0x46, 0x68, 0x00, 0x06, 0xce, 0xef, 0xf0, 0x1f, 0xf7, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, - 0xf5, 0x00, 0x32, 0x45, 0xf2, 0x40, 0x05, 0x61, 0x82, 0x80, 0x01, 0x45, 0xe5, 0xbf, 0xb7, 0x07, 0x08, 0x00, 0x63, - 0xef, 0xa7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x8d, 0xe3, - 0xae, 0x84, 0xef, 0xf0, 0xbf, 0xdd, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x22, 0x44, 0xb2, 0x40, 0x23, - 0xaa, 0x97, 0x20, 0x92, 0x44, 0x01, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x9f, 0xe7, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, - 0x41, 0x01, 0x82, 0x80, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xaa, 0x84, 0x2e, 0x84, 0x45, - 0x3f, 0x26, 0x85, 0xef, 0xf0, 0xbf, 0xf8, 0x63, 0x09, 0x85, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, - 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xcd, 0xbf, 0x01, 0x11, 0x22, 0xcc, 0x2e, 0xc6, 0x06, - 0xce, 0x2a, 0x84, 0xef, 0xf0, 0x5f, 0xf6, 0xb2, 0x45, 0x63, 0x03, 0xb5, 0x02, 0xfd, 0x57, 0x63, 0x1a, 0xf5, 0x00, - 0x63, 0x8e, 0xa5, 0x00, 0x22, 0x85, 0x62, 0x44, 0xf2, 0x40, 0x05, 0x61, 0x6f, 0xf0, 0xff, 0xfa, 0x13, 0x05, 0x50, - 0x05, 0xf2, 0x40, 0x62, 0x44, 0x05, 0x61, 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xd5, 0xbf, 0xb7, 0x07, 0x08, 0x00, - 0x63, 0xe0, 0xb7, 0x04, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0xf7, 0xf5, 0x1f, 0xaa, 0x84, 0x2e, - 0x84, 0x13, 0x05, 0x50, 0x05, 0x99, 0xef, 0xef, 0xf0, 0xbf, 0xd2, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, - 0x39, 0x45, 0xef, 0xf0, 0x5f, 0xdd, 0x26, 0x85, 0xef, 0xf0, 0xff, 0xda, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, - 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, - 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xfb, 0xb7, 0x00, 0x81, 0x44, 0xf2, 0x40, 0x62, - 0x44, 0x42, 0x49, 0xb2, 0x49, 0x26, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x82, 0x80, 0x93, 0xf4, 0xf5, 0x1f, 0x2e, 0x84, - 0xe5, 0xf4, 0x2a, 0x89, 0xef, 0xf0, 0xff, 0xcc, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x41, 0x45, 0xef, - 0xf0, 0x9f, 0xd7, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x17, 0xf5, 0xfc, 0x37, 0x34, 0x20, 0x00, 0x13, 0x05, 0x44, 0xc9, - 0xef, 0xf0, 0x5f, 0xd4, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x87, 0x07, 0x20, 0x23, 0xa0, 0x07, 0x00, 0x91, 0x07, 0xe3, - 0x9d, 0xe7, 0xfe, 0x93, 0x09, 0x44, 0xc9, 0x03, 0xd6, 0xc9, 0x1f, 0x93, 0x07, 0xc0, 0x1d, 0x63, 0xfa, 0xc7, 0x00, - 0x37, 0x55, 0x10, 0x00, 0x99, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xf0, 0xaf, 0x82, 0x41, 0xbf, 0x93, 0x05, 0x44, - 0xc9, 0x4a, 0x85, 0xef, 0x20, 0x60, 0x43, 0x83, 0xd4, 0xc9, 0x1f, 0x41, 0xb7, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe7, - 0xa7, 0x04, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x13, 0x05, 0x50, - 0x05, 0x9d, 0xe7, 0xef, 0xf0, 0xbf, 0xc4, 0x85, 0x67, 0xb7, 0x04, 0x08, 0x05, 0x93, 0x87, 0x97, 0x82, 0x23, 0xa2, - 0xf4, 0x20, 0x23, 0xac, 0x84, 0x20, 0x39, 0x45, 0xef, 0xf0, 0xbf, 0xce, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, - 0xf7, 0x13, 0x05, 0xa0, 0x0a, 0x23, 0xa2, 0xf4, 0x20, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, - 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x0d, 0x65, 0x01, 0x11, 0x13, 0x05, 0x05, 0x20, 0x06, 0xce, 0x22, 0xcc, 0x26, - 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xef, 0x10, 0xf0, 0x2f, 0x39, 0x45, 0xef, 0x10, 0x50, 0x31, 0x13, 0x05, 0x80, 0x07, - 0x37, 0x39, 0x20, 0x00, 0xef, 0xf0, 0x6f, 0xb9, 0x93, 0x09, 0x49, 0xf7, 0x83, 0xa7, 0x09, 0x00, 0x37, 0x04, 0x08, - 0x05, 0x93, 0x04, 0x04, 0x20, 0xdc, 0xc0, 0xb7, 0x07, 0x46, 0x00, 0x85, 0x07, 0xdc, 0xcc, 0x85, 0x67, 0x93, 0x87, - 0x57, 0x86, 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, 0xdc, 0xc0, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x05, 0xb9, 0xef, - 0xf0, 0xef, 0xc8, 0xb7, 0x07, 0x40, 0x08, 0x9c, 0xc8, 0xdc, 0x40, 0x01, 0x45, 0x13, 0x09, 0x49, 0xf7, 0x93, 0xe7, - 0x07, 0x18, 0x23, 0xa0, 0xf9, 0x00, 0xef, 0xf0, 0x7f, 0xf3, 0x93, 0x07, 0x04, 0x10, 0x98, 0x43, 0xb7, 0x67, 0xa5, - 0xf0, 0x93, 0x87, 0xf7, 0xa0, 0x63, 0x05, 0xf7, 0x02, 0x37, 0x55, 0x10, 0x00, 0x95, 0x45, 0x13, 0x05, 0x85, 0x69, - 0xef, 0xe0, 0xbf, 0xf2, 0x41, 0x67, 0x7d, 0x17, 0x93, 0x07, 0x04, 0x18, 0xb8, 0xd3, 0xf8, 0xd3, 0xb8, 0xd7, 0xf8, - 0xd7, 0xb8, 0xdb, 0xf8, 0xdb, 0xb8, 0xdf, 0xf8, 0xdf, 0x51, 0x45, 0xef, 0xf0, 0x7f, 0xc1, 0xb7, 0x07, 0x08, 0x05, - 0x83, 0xa7, 0xc7, 0x20, 0x91, 0x8b, 0x91, 0xeb, 0x37, 0x55, 0x10, 0x00, 0x91, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, - 0xe0, 0x3f, 0xef, 0xef, 0xd0, 0x1f, 0x80, 0xb7, 0x07, 0x08, 0x05, 0x37, 0x07, 0x40, 0x00, 0x23, 0xa6, 0xe7, 0x20, - 0x03, 0x27, 0x09, 0x00, 0xf2, 0x40, 0x62, 0x44, 0x23, 0xa2, 0xe7, 0x20, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, - 0x61, 0x82, 0x80, 0x85, 0x67, 0x37, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0x86, 0x23, 0x2a, 0xf7, 0xf6, 0x37, 0x37, - 0x20, 0x00, 0x93, 0x07, 0x50, 0x05, 0x23, 0x2c, 0xf7, 0xf6, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2e, 0xf7, 0xf6, 0x6f, - 0xf0, 0xbf, 0xee, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe0, 0xa7, 0x06, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, - 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x13, 0x05, 0x50, 0x05, 0xa1, 0xe3, 0xae, 0x84, 0xef, 0xf0, 0x7f, 0xad, 0xb7, - 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x01, 0x47, 0x93, 0x06, 0x00, 0x20, 0xb3, 0x85, 0xe4, 0x00, 0x8c, 0x41, - 0x33, 0x06, 0xf7, 0x00, 0x11, 0x07, 0x0c, 0xc2, 0xe3, 0x19, 0xd7, 0xfe, 0x7d, 0x57, 0x93, 0x87, 0x07, 0x20, 0xf8, - 0xc3, 0xb8, 0xc7, 0xf8, 0xc7, 0xb8, 0xcb, 0x29, 0x45, 0xef, 0xf0, 0xbf, 0xb5, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, - 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xaa, 0x85, 0x37, 0x05, 0x08, - 0x05, 0x41, 0x46, 0x13, 0x05, 0x05, 0x26, 0x6f, 0xf0, 0x0f, 0xd0, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xef, 0xa7, 0x0a, - 0x01, 0x11, 0x26, 0xca, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x56, - 0xc2, 0xaa, 0x84, 0x13, 0x05, 0x50, 0x05, 0xd9, 0xe7, 0x93, 0x07, 0xc0, 0x1d, 0x32, 0x89, 0x63, 0xe3, 0xc7, 0x08, - 0xb6, 0x89, 0x37, 0x34, 0x20, 0x00, 0x2e, 0x8a, 0xef, 0xf0, 0x5f, 0xa4, 0x13, 0x06, 0x00, 0x20, 0x81, 0x45, 0x13, - 0x05, 0x44, 0xc9, 0xef, 0x20, 0x80, 0x23, 0x4a, 0x86, 0xd2, 0x85, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x00, 0x1f, - 0x4e, 0x85, 0xef, 0xf0, 0xbf, 0xf9, 0x93, 0x0a, 0x44, 0xc9, 0xb7, 0x07, 0x08, 0x05, 0x23, 0x9e, 0x2a, 0x1f, 0x13, - 0x07, 0x44, 0xc9, 0x93, 0x86, 0x07, 0x20, 0x10, 0x43, 0x11, 0x07, 0x90, 0xc3, 0x91, 0x07, 0xe3, 0x9c, 0xd7, 0xfe, - 0x13, 0x06, 0x00, 0x20, 0x81, 0x45, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x80, 0x1f, 0xb7, 0x07, 0x08, 0x05, 0x23, - 0xac, 0x97, 0x20, 0x31, 0x45, 0xef, 0xf0, 0x1f, 0xaa, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0x37, 0x55, - 0x10, 0x00, 0x13, 0x05, 0x85, 0x69, 0x8d, 0x45, 0xef, 0xe0, 0x1f, 0xd8, 0x13, 0x05, 0x50, 0x05, 0xf2, 0x40, 0x62, - 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, - 0x82, 0x80, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xeb, 0xa7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0xf5, - 0x1f, 0x2a, 0x84, 0x89, 0xef, 0xef, 0xf0, 0xdf, 0x99, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x22, 0x44, - 0xb2, 0x40, 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x1f, 0xa4, 0xb2, 0x40, 0x22, 0x44, 0x13, 0x05, 0x50, 0x05, 0x41, - 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x37, 0x04, 0x08, 0x05, - 0x23, 0x2c, 0xa4, 0x20, 0xef, 0xf0, 0x5f, 0x96, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, - 0xf6, 0xb7, 0xb7, 0xaa, 0x02, 0x93, 0x87, 0x67, 0xaa, 0xb2, 0x40, 0x23, 0x24, 0xf4, 0x20, 0x22, 0x44, 0x41, 0x01, - 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xdf, 0x93, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, - 0xac, 0xe7, 0xf6, 0xb2, 0x40, 0xb7, 0xb7, 0xa6, 0x02, 0x37, 0x07, 0x08, 0x05, 0x93, 0x87, 0xa7, 0xaa, 0x23, 0x24, - 0xf7, 0x20, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x3e, 0xcc, 0xb7, 0x07, 0x08, 0x05, 0x3a, 0xce, 0x03, 0xa7, 0xc7, - 0x20, 0x36, 0xd0, 0xb7, 0x06, 0x40, 0x00, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, - 0x32, 0xd2, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0x75, 0x8f, 0x05, 0xcf, 0x23, - 0xa6, 0xd7, 0x20, 0x13, 0x07, 0xa0, 0x0a, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0xe7, 0xf6, 0xf2, 0x50, 0xe2, 0x52, - 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, - 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x03, 0xa7, 0xc7, 0x20, - 0xb7, 0x06, 0x00, 0x08, 0x37, 0x55, 0x10, 0x00, 0x75, 0x8f, 0x0d, 0xc3, 0x23, 0xa6, 0xd7, 0x20, 0x85, 0x45, 0x13, - 0x05, 0x85, 0x69, 0xef, 0xe0, 0x3f, 0xc4, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xae, 0xe7, 0xf6, - 0xef, 0xd0, 0x1f, 0xbf, 0x75, 0xb7, 0x89, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, 0x7f, 0xc2, 0xb7, 0x07, 0x02, - 0x00, 0x73, 0xb0, 0x47, 0x30, 0xe5, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa0, 0xe7, 0xf8, - 0x82, 0x80, 0x99, 0x47, 0x63, 0x05, 0xf5, 0x02, 0x9d, 0x47, 0x63, 0x0b, 0xf5, 0x00, 0x95, 0x47, 0x63, 0x15, 0xf5, - 0x02, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xf7, 0xf7, 0xf7, 0x29, 0xa8, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, - 0xa0, 0x0a, 0x23, 0xa0, 0xe7, 0xf8, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xe7, 0x07, 0x08, 0x7c, - 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf8, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, 0xf7, 0x00, - 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xe7, 0x07, 0x08, 0x7c, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, - 0xa7, 0x07, 0xf8, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, 0xf7, 0x00, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xf7, - 0xf7, 0xf7, 0x7c, 0xc3, 0x82, 0x80, 0x39, 0x71, 0x2a, 0xd6, 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, 0x13, 0x05, 0xc5, - 0x69, 0x85, 0x45, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, - 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0x9f, 0xb6, 0xef, 0xd0, 0x3f, - 0xb2, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, - 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, - 0x30, 0x39, 0x71, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, - 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xf3, 0x25, 0x20, - 0x34, 0xc1, 0x67, 0x37, 0x55, 0x10, 0x00, 0xdd, 0x8d, 0x13, 0x05, 0xc5, 0x69, 0xef, 0xe0, 0x9f, 0xb0, 0xef, 0xd0, - 0x3f, 0xac, 0x01, 0xa0, 0x39, 0x71, 0x2a, 0xd6, 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, 0x13, 0x05, 0xc5, 0x69, 0x89, - 0x45, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, - 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0x3f, 0xad, 0xef, 0xd0, 0xdf, 0xa8, 0xf2, - 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, - 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, - 0x07, 0x01, 0x01, 0xb7, 0x07, 0x00, 0x01, 0x13, 0x07, 0x17, 0x10, 0x98, 0xd3, 0x37, 0x07, 0x03, 0x04, 0x09, 0x07, - 0xd8, 0xd3, 0x13, 0x07, 0x50, 0x60, 0x98, 0xd7, 0x37, 0x17, 0x09, 0x00, 0x13, 0x07, 0x77, 0x80, 0xd8, 0xd7, 0x37, - 0x17, 0x0b, 0x0b, 0x13, 0x07, 0xa7, 0xa0, 0x98, 0xdb, 0x37, 0x17, 0x0c, 0x00, 0x13, 0x07, 0xb7, 0xc0, 0xd8, 0xdb, - 0x37, 0x17, 0x0f, 0x00, 0x13, 0x07, 0xd7, 0xe0, 0x98, 0xdf, 0x05, 0x67, 0xd8, 0xdf, 0xb7, 0x17, 0xff, 0x7f, 0x93, - 0x87, 0x07, 0x80, 0x73, 0xa0, 0x47, 0x30, 0xa1, 0x47, 0x73, 0xa0, 0x07, 0x30, 0x82, 0x80, 0x41, 0x11, 0x3e, 0xc6, - 0xb7, 0x07, 0x40, 0x00, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x3e, - 0xc6, 0xb7, 0x07, 0x80, 0x00, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, - 0x3e, 0xc6, 0xb7, 0x07, 0x00, 0x04, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, - 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x00, 0x20, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, - 0x05, 0x65, 0x6f, 0x10, 0xa0, 0x54, 0x05, 0x65, 0x6f, 0x10, 0x00, 0x55, 0x01, 0x11, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, - 0xc6, 0x06, 0xce, 0x26, 0xca, 0x52, 0xc4, 0x56, 0xc2, 0x9d, 0x47, 0x2a, 0x84, 0xae, 0x89, 0x32, 0x89, 0x63, 0xd4, - 0xc7, 0x00, 0xef, 0xd0, 0x2f, 0xae, 0xef, 0xf0, 0x5f, 0xfd, 0xb7, 0x07, 0x01, 0x07, 0x18, 0x40, 0xdc, 0x43, 0x93, - 0x06, 0xf0, 0x0f, 0x63, 0x05, 0xd7, 0x00, 0xf1, 0x9b, 0x0d, 0x8b, 0xd9, 0x8f, 0x13, 0xf7, 0xb7, 0xff, 0x83, 0x47, - 0x44, 0x00, 0x81, 0x44, 0x31, 0x4a, 0x8a, 0x07, 0x91, 0x8b, 0xd9, 0x8f, 0x37, 0x07, 0x01, 0x07, 0x5c, 0xc3, 0xb7, - 0x1a, 0x01, 0x07, 0x63, 0xcf, 0x24, 0x03, 0x14, 0x40, 0x05, 0x47, 0xad, 0x47, 0x63, 0x9e, 0xe6, 0x00, 0x83, 0x46, - 0x44, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0xbd, 0x47, 0x63, 0x97, 0xe6, 0x00, 0x14, 0x44, 0x37, 0x37, 0x20, 0x00, 0x23, - 0x22, 0xd7, 0xf8, 0xf2, 0x40, 0x62, 0x44, 0x37, 0x07, 0x01, 0x07, 0x5c, 0xc7, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, - 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xb3, 0x85, 0x44, 0x03, 0x13, 0x95, 0x44, 0x00, 0x31, 0x46, 0x56, - 0x95, 0x85, 0x04, 0xce, 0x95, 0xef, 0xf0, 0xcf, 0x81, 0x7d, 0xb7, 0x1d, 0x71, 0x3e, 0xda, 0xb7, 0x07, 0x01, 0x07, - 0xa2, 0xc6, 0x80, 0x47, 0x86, 0xce, 0x96, 0xcc, 0x9a, 0xca, 0x9e, 0xc8, 0xaa, 0xc4, 0xae, 0xc2, 0xb2, 0xc0, 0x36, - 0xde, 0x3a, 0xdc, 0x42, 0xd8, 0x46, 0xd6, 0x72, 0xd4, 0x76, 0xd2, 0x7a, 0xd0, 0x7e, 0xce, 0x93, 0x77, 0xb4, 0x00, - 0x95, 0xc7, 0xb7, 0x07, 0x00, 0x40, 0x73, 0xb0, 0x47, 0x30, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, - 0x55, 0x10, 0x00, 0xa2, 0x86, 0x13, 0x06, 0x06, 0x6a, 0x93, 0x85, 0x85, 0x6a, 0x13, 0x05, 0x45, 0x64, 0xef, 0xe0, - 0xbf, 0x87, 0xef, 0xd0, 0xbf, 0x8a, 0x93, 0x77, 0x44, 0x00, 0x99, 0xcf, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, - 0xf8, 0x91, 0xcb, 0x6c, 0x00, 0x28, 0x00, 0x82, 0x97, 0x22, 0x47, 0xb7, 0x07, 0x01, 0x07, 0x98, 0xcb, 0x32, 0x47, - 0xd8, 0xcb, 0xb7, 0x07, 0x01, 0x07, 0x80, 0xc7, 0x36, 0x44, 0xf6, 0x40, 0xe6, 0x42, 0x56, 0x43, 0xc6, 0x43, 0x26, - 0x45, 0x96, 0x45, 0x06, 0x46, 0xf2, 0x56, 0x62, 0x57, 0xd2, 0x57, 0x42, 0x58, 0xb2, 0x58, 0x22, 0x5e, 0x92, 0x5e, - 0x02, 0x5f, 0xf2, 0x4f, 0x25, 0x61, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x07, 0x02, 0x04, 0xdc, 0x47, 0x13, 0x05, 0xa0, - 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x13, 0x05, 0x00, 0x08, 0x6f, 0x10, 0x40, 0x3d, - 0x13, 0x05, 0x00, 0x08, 0x6f, 0x10, 0x80, 0x3d, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x07, 0xd0, - 0x79, 0x37, 0x04, 0x02, 0x04, 0x5c, 0xc4, 0x85, 0x44, 0x95, 0x65, 0x37, 0x35, 0x10, 0x00, 0x04, 0xc4, 0x93, 0x85, - 0x05, 0xe2, 0x13, 0x05, 0x25, 0x6d, 0xef, 0xe0, 0x7f, 0xca, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x13, 0xf5, 0x02, 0x54, - 0x44, 0x63, 0x82, 0x96, 0x02, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, - 0xc6, 0x6a, 0x93, 0x85, 0x45, 0x6b, 0x13, 0x05, 0x05, 0x62, 0xef, 0xe0, 0x0f, 0xfb, 0x13, 0x05, 0x50, 0x05, 0xb2, - 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xdf, 0xf8, 0xb2, 0x40, - 0xb7, 0x07, 0x02, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x05, 0x45, 0x22, 0xc4, 0x26, - 0xc2, 0x06, 0xc6, 0xef, 0xe0, 0x3f, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa4, 0xe7, 0xf8, - 0x89, 0x46, 0x37, 0x07, 0x02, 0x02, 0x54, 0xc7, 0x13, 0x84, 0x87, 0xf8, 0x93, 0x04, 0x50, 0x05, 0xef, 0xe0, 0x9f, - 0xc2, 0x1c, 0x40, 0xe3, 0x9d, 0x97, 0xfe, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, - 0x02, 0x02, 0xc8, 0xcb, 0x05, 0x47, 0xd8, 0xc7, 0xd8, 0x53, 0x69, 0x8f, 0x63, 0x1e, 0xa7, 0x00, 0xd4, 0x57, 0x7d, - 0x55, 0xf9, 0x8e, 0x91, 0xea, 0x94, 0x57, 0x75, 0x8f, 0x19, 0xe7, 0x88, 0x47, 0x05, 0x89, 0x33, 0x05, 0xa0, 0x40, - 0x82, 0x80, 0x7d, 0x55, 0x82, 0x80, 0x41, 0x45, 0x6f, 0x10, 0x00, 0x2f, 0x41, 0x45, 0x6f, 0x10, 0xe0, 0x2d, 0x01, - 0x11, 0x06, 0xce, 0x22, 0xcc, 0x2a, 0xc6, 0xef, 0xf0, 0x3f, 0xff, 0x13, 0x07, 0x50, 0x05, 0xb7, 0x37, 0x20, 0x00, - 0x23, 0xa4, 0xe7, 0xf8, 0x37, 0x04, 0x02, 0x02, 0xa1, 0x47, 0x5c, 0xc4, 0x32, 0x45, 0x85, 0x47, 0x1c, 0xc8, 0x93, - 0x07, 0x10, 0x40, 0x5c, 0xc0, 0xef, 0xf0, 0xbf, 0xf9, 0xef, 0xf0, 0x9f, 0xf5, 0x23, 0x22, 0x04, 0x00, 0x62, 0x44, - 0xf2, 0x40, 0x05, 0x61, 0x6f, 0xf0, 0x7f, 0xfb, 0x41, 0x11, 0x3a, 0xc6, 0x37, 0x07, 0x02, 0x02, 0x3e, 0xc4, 0x1c, - 0x47, 0x1c, 0xc7, 0x85, 0x8b, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa4, 0xe7, 0xf8, - 0x32, 0x47, 0xa2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0xc7, 0xf8, 0x82, - 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xd0, 0x6f, 0x81, - 0x89, 0x67, 0x63, 0x64, 0xf4, 0x00, 0xef, 0xd0, 0xcf, 0x80, 0x37, 0x27, 0x00, 0x06, 0x85, 0x46, 0x09, 0x46, 0x1c, - 0x47, 0x9d, 0x8b, 0x63, 0x86, 0xd7, 0x00, 0x1c, 0x47, 0x9d, 0x8b, 0xe3, 0x9a, 0xc7, 0xfe, 0x37, 0x05, 0x00, 0x06, - 0x2a, 0x94, 0x08, 0x40, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x65, 0xb7, 0x37, 0x20, 0x00, 0x13, - 0x07, 0x50, 0x05, 0x41, 0x11, 0x13, 0x05, 0x05, 0x80, 0x23, 0xa6, 0xe7, 0xf8, 0x06, 0xc6, 0xef, 0x10, 0xc0, 0x20, - 0xb7, 0x27, 0x00, 0x06, 0x9c, 0x47, 0x05, 0x47, 0x9d, 0x8b, 0xfd, 0x17, 0x63, 0x7b, 0xf7, 0x00, 0x37, 0x55, 0x10, - 0x00, 0x89, 0x45, 0x13, 0x05, 0x85, 0x6b, 0xef, 0xe0, 0xaf, 0xe9, 0xef, 0xc0, 0x9f, 0xfa, 0xb7, 0x07, 0x46, 0x00, - 0xb2, 0x40, 0x37, 0x27, 0x00, 0x06, 0x85, 0x07, 0x5c, 0xcf, 0x85, 0x47, 0x5c, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x37, - 0x27, 0x00, 0x06, 0x1c, 0x47, 0x85, 0x46, 0x9d, 0x8b, 0x63, 0x8a, 0xd7, 0x00, 0x14, 0xcb, 0xb7, 0x26, 0x00, 0x06, - 0x05, 0x47, 0x9c, 0x46, 0x9d, 0x8b, 0xe3, 0x9e, 0xe7, 0xfe, 0xb7, 0x27, 0x00, 0x06, 0x09, 0x47, 0x05, 0x65, 0x98, - 0xcb, 0x13, 0x05, 0x05, 0x80, 0x6f, 0x10, 0x00, 0x1b, 0x05, 0x65, 0x41, 0x11, 0x13, 0x05, 0x05, 0x80, 0x06, 0xc6, - 0xef, 0x10, 0x60, 0x19, 0xb2, 0x40, 0xb7, 0x27, 0x00, 0x06, 0x21, 0x47, 0x98, 0xcb, 0x41, 0x01, 0x82, 0x80, 0x41, - 0x11, 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0xaa, 0x84, 0xef, 0xf0, 0x5f, 0xf1, 0x2a, 0x84, 0x49, 0x22, 0x13, 0x75, - 0xf5, 0x0f, 0xef, 0xe0, 0x1f, 0xa6, 0x26, 0x85, 0xef, 0xf0, 0x3f, 0xf0, 0x63, 0x05, 0xa4, 0x00, 0xef, 0xc0, 0xff, - 0xf1, 0x01, 0x45, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, - 0x4a, 0xd0, 0x4e, 0xce, 0x06, 0xd6, 0x52, 0xcc, 0xaa, 0x89, 0x2e, 0x89, 0x93, 0x74, 0xc6, 0xff, 0x01, 0x44, 0x33, - 0x8a, 0x89, 0x00, 0x33, 0x05, 0x89, 0x00, 0x63, 0x1a, 0x94, 0x00, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, - 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0xef, 0xf0, 0x9f, 0xf9, 0x2a, 0xc6, 0x11, 0x46, 0x6c, 0x00, 0x52, - 0x85, 0xef, 0x10, 0x50, 0x1d, 0x11, 0x04, 0xc9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x1f, 0xf8, 0x2a, 0x87, - 0x85, 0x46, 0x01, 0x45, 0x89, 0x45, 0x01, 0xe7, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x93, 0x77, 0xf7, 0x00, 0x01, - 0x46, 0x81, 0xef, 0x63, 0xd3, 0xc5, 0x00, 0xb6, 0x87, 0x5d, 0x8d, 0x86, 0x06, 0x13, 0x75, 0xf5, 0x0f, 0x93, 0xf6, - 0xf6, 0x0f, 0x11, 0x83, 0xf1, 0xbf, 0x13, 0xf8, 0x17, 0x00, 0x85, 0x83, 0x42, 0x96, 0x93, 0xf7, 0xf7, 0x0f, 0xf1, - 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0xae, 0x84, 0x99, 0xc3, - 0xef, 0xc0, 0x1f, 0xe7, 0x89, 0x67, 0x63, 0x64, 0xf4, 0x00, 0xef, 0xc0, 0x7f, 0xe6, 0xb7, 0x37, 0x20, 0x00, 0x13, - 0x07, 0x50, 0x05, 0x23, 0xa6, 0xe7, 0xf8, 0xb7, 0x27, 0x00, 0x06, 0x84, 0xcf, 0xc0, 0xcb, 0x22, 0x44, 0xb2, 0x40, - 0x92, 0x44, 0x11, 0x47, 0x98, 0xcb, 0x89, 0x65, 0x37, 0x45, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0xe5, - 0x84, 0x41, 0x01, 0x6f, 0xe0, 0xdf, 0xa4, 0x39, 0x71, 0x3a, 0xce, 0x37, 0x27, 0x00, 0x06, 0x3e, 0xcc, 0x1c, 0x47, - 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, - 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xa1, 0x8b, 0x85, 0xcf, 0xa1, 0x47, 0x1c, 0xc7, 0xb7, 0x37, - 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf8, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, - 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, - 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x85, - 0x6b, 0xef, 0xe0, 0x2f, 0xcb, 0xef, 0xd0, 0xcf, 0xc6, 0xe1, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa8, 0xa7, 0xf8, - 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xf9, 0x88, 0x43, 0x37, 0x67, 0x19, 0x00, 0x13, 0x07, 0xd7, - 0x60, 0x33, 0x05, 0xe5, 0x02, 0x37, 0xf7, 0x6e, 0x3c, 0x13, 0x07, 0xf7, 0x35, 0x3a, 0x95, 0x88, 0xc3, 0x82, 0x80, - 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf9, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0x87, 0xf9, 0x9c, 0x4f, 0x13, - 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0xc7, 0xf9, 0x63, 0x84, 0xe7, 0x00, 0x13, 0x05, - 0x50, 0x05, 0x82, 0x80, 0xfd, 0x77, 0xfd, 0x17, 0xe9, 0x8f, 0xb7, 0x26, 0x00, 0x08, 0x2e, 0x87, 0xb2, 0x85, 0x63, - 0x94, 0xd7, 0x02, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0xa7, 0xf8, 0xb7, 0x37, 0x20, 0x00, 0x37, 0x45, 0x10, 0x00, - 0x23, 0xae, 0xe7, 0xf8, 0x13, 0x05, 0x05, 0xaf, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0xe7, 0xf8, 0x6f, 0xe0, 0x5f, - 0x87, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0xa7, 0xf8, 0xb7, 0x37, 0x20, 0x00, - 0x37, 0x45, 0x10, 0x00, 0x23, 0xae, 0x07, 0xf8, 0x13, 0x07, 0x00, 0x10, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x05, 0x80, - 0x3e, 0x13, 0x05, 0x05, 0xaf, 0x23, 0xac, 0xe7, 0xf8, 0x6f, 0xe0, 0x3f, 0x84, 0x37, 0x07, 0x01, 0x02, 0x5c, 0x43, - 0xb7, 0x06, 0x05, 0x00, 0xd5, 0x8f, 0x5c, 0xc3, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0xb7, - 0x27, 0x00, 0x08, 0x37, 0x05, 0x08, 0x00, 0x63, 0x14, 0xf4, 0x00, 0x37, 0x05, 0x04, 0x00, 0xef, 0x00, 0x50, 0x71, - 0x5c, 0x5c, 0x22, 0x85, 0xb2, 0x40, 0x93, 0xe7, 0x37, 0x00, 0x5c, 0xdc, 0x23, 0x2c, 0x04, 0x00, 0x22, 0x44, 0x41, - 0x01, 0x6f, 0xf0, 0x5f, 0xf9, 0x58, 0x5d, 0xaa, 0x87, 0x75, 0x9b, 0x58, 0xdd, 0x37, 0x27, 0x00, 0x08, 0x37, 0x05, - 0x04, 0x00, 0x63, 0x84, 0xe7, 0x00, 0x37, 0x05, 0x08, 0x00, 0x6f, 0x00, 0xd0, 0x6e, 0x79, 0x71, 0x22, 0xd4, 0x26, - 0xd2, 0x4a, 0xd0, 0x06, 0xd6, 0x4e, 0xce, 0x52, 0xcc, 0x56, 0xca, 0x2a, 0x89, 0xae, 0x84, 0x32, 0x84, 0x99, 0xe1, - 0xef, 0xc0, 0x3f, 0xc8, 0x13, 0x0a, 0xa0, 0x0a, 0x91, 0x4a, 0x05, 0xe4, 0x83, 0x27, 0x89, 0x01, 0x37, 0x07, 0x11, - 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x99, 0xc3, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, - 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0xd2, 0x4a, 0x45, 0x61, 0x82, 0x80, 0x13, 0x06, 0x80, 0x3e, 0x85, 0x45, 0x4a, - 0x85, 0xef, 0xf0, 0x7f, 0xee, 0xe3, 0x1f, 0x45, 0xfd, 0x83, 0x27, 0x49, 0x02, 0xa2, 0x89, 0x3e, 0xc6, 0x63, 0xf3, - 0x8a, 0x00, 0x91, 0x49, 0x26, 0x85, 0x4e, 0x86, 0x6c, 0x00, 0xef, 0x10, 0x20, 0x73, 0xce, 0x94, 0x33, 0x04, 0x34, - 0x41, 0x6d, 0xb7, 0x41, 0x11, 0x37, 0x05, 0x02, 0x00, 0x06, 0xc6, 0xef, 0x00, 0xb0, 0x65, 0xb2, 0x40, 0xb7, 0x17, - 0x00, 0x08, 0x37, 0x07, 0x07, 0x00, 0x98, 0xd3, 0x13, 0x05, 0x40, 0x1f, 0x41, 0x01, 0x6f, 0xe0, 0xef, 0xee, 0xb7, - 0x17, 0x00, 0x08, 0x23, 0xa0, 0x07, 0x02, 0x37, 0x05, 0x02, 0x00, 0x6f, 0x00, 0x10, 0x64, 0x39, 0x71, 0x3e, 0xcc, - 0xb7, 0x17, 0x00, 0x08, 0x3a, 0xce, 0x98, 0x57, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, - 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0x05, 0x8b, - 0x05, 0xcb, 0x98, 0x57, 0x13, 0x67, 0x17, 0x00, 0x98, 0xd7, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, - 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, - 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x98, 0x57, 0x09, 0x8b, 0x09, 0xc7, 0x98, 0x57, 0x13, - 0x67, 0x27, 0x00, 0xf1, 0xb7, 0x98, 0x57, 0x11, 0x8b, 0x09, 0xc7, 0x98, 0x57, 0x13, 0x67, 0x47, 0x00, 0x7d, 0xbf, - 0xb7, 0x07, 0x00, 0x01, 0x73, 0xb0, 0x47, 0x30, 0xef, 0xd0, 0xcf, 0xa1, 0x4d, 0xbf, 0x37, 0x07, 0x00, 0x02, 0x5c, - 0x4f, 0xb7, 0x36, 0x20, 0x00, 0x13, 0xf6, 0x77, 0x00, 0xe1, 0x9b, 0x23, 0xa0, 0xc6, 0xfa, 0x93, 0xe7, 0x47, 0x00, - 0x5c, 0xcf, 0x1c, 0x4f, 0xf9, 0x9b, 0x1c, 0xcf, 0x82, 0x80, 0x41, 0x11, 0x26, 0xc2, 0xb7, 0x04, 0x00, 0x02, 0x22, - 0xc4, 0xc0, 0x4c, 0x9c, 0x4c, 0x06, 0xc6, 0x13, 0x05, 0x80, 0x07, 0x93, 0xe7, 0x17, 0x00, 0x9c, 0xcc, 0xef, 0xe0, - 0xaf, 0xe1, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xfa, 0x61, 0x98, 0xb2, 0x40, 0x5d, 0x8c, 0xc0, 0xcc, 0x22, - 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x17, 0x05, 0x01, 0x93, 0x17, 0x85, 0x01, 0xba, 0x97, 0x13, 0x17, - 0x85, 0x00, 0xba, 0x97, 0x3e, 0x95, 0xb7, 0x07, 0x00, 0x04, 0x88, 0xd3, 0xc8, 0xd3, 0x88, 0xd7, 0xc8, 0xd7, 0x88, - 0xdb, 0xc8, 0xdb, 0x88, 0xdf, 0xc8, 0xdf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x00, 0x08, 0x98, 0xd3, - 0x23, 0xa2, 0x07, 0x02, 0x0e, 0x05, 0x23, 0xa4, 0x07, 0x02, 0x42, 0x05, 0x23, 0xa6, 0x07, 0x02, 0x41, 0x81, 0x23, - 0xa8, 0x07, 0x02, 0x13, 0x17, 0x85, 0x00, 0xb7, 0x06, 0xff, 0x00, 0x23, 0xaa, 0x07, 0x02, 0x75, 0x8f, 0x62, 0x05, - 0x23, 0xac, 0x07, 0x02, 0x3a, 0x95, 0xc8, 0xdf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x00, 0x08, 0x98, - 0xd3, 0x23, 0xa2, 0x07, 0x02, 0x23, 0xa4, 0x07, 0x02, 0x23, 0xa6, 0x07, 0x02, 0x23, 0xa8, 0x07, 0x02, 0x23, 0xaa, - 0x07, 0x02, 0x23, 0xac, 0x07, 0x02, 0x23, 0xae, 0x07, 0x02, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x47, - 0xea, 0x82, 0x80, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0x6f, 0xe0, - 0x3f, 0x83, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa2, 0xe7, 0xea, 0xb7, 0x07, 0x00, 0x04, 0xc8, - 0xc3, 0x13, 0x07, 0x90, 0x02, 0x85, 0x65, 0x37, 0x45, 0x10, 0x00, 0x98, 0xc7, 0x93, 0x85, 0x85, 0x38, 0x13, 0x05, - 0x45, 0xdf, 0x6f, 0xe0, 0xaf, 0xd8, 0x41, 0x11, 0x22, 0xc4, 0x01, 0x45, 0x37, 0x34, 0x20, 0x00, 0x06, 0xc6, 0x13, - 0x04, 0x44, 0xe9, 0xef, 0xf0, 0x1f, 0xf2, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0xfb, - 0x48, 0x44, 0xb7, 0x07, 0x02, 0x00, 0x95, 0x07, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0xbf, 0xfa, 0x48, 0x44, 0x7e, - 0x05, 0x13, 0x65, 0x05, 0x05, 0xef, 0xf0, 0xff, 0xf9, 0x48, 0x44, 0xb7, 0x07, 0x00, 0x10, 0x99, 0x07, 0x7e, 0x05, - 0x5d, 0x8d, 0xef, 0xf0, 0xff, 0xf8, 0x48, 0x44, 0xb7, 0x07, 0x01, 0x10, 0x99, 0x07, 0x7e, 0x05, 0x5d, 0x8d, 0xef, - 0xf0, 0xff, 0xf7, 0x22, 0x44, 0xb2, 0x40, 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0xf7, 0x7d, 0x47, 0x63, 0x7e, - 0xb7, 0x04, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0x6f, 0xe0, 0x8f, - 0xf8, 0xb3, 0x06, 0xf5, 0x00, 0x83, 0xc6, 0x06, 0x00, 0x33, 0x07, 0xf1, 0x00, 0x85, 0x07, 0x23, 0x00, 0xd7, 0x00, - 0xe3, 0x97, 0xf5, 0xfe, 0x18, 0x10, 0x93, 0x87, 0x15, 0x00, 0xba, 0x95, 0x13, 0x07, 0x00, 0xf8, 0x23, 0x80, 0xe5, - 0xfe, 0x13, 0x07, 0x00, 0x02, 0x63, 0x92, 0xe7, 0x02, 0x37, 0x05, 0x00, 0x04, 0x8a, 0x85, 0x13, 0x06, 0x00, 0x02, - 0x13, 0x05, 0x05, 0x02, 0xef, 0xe0, 0x8f, 0xf4, 0xb2, 0x50, 0x45, 0x61, 0x82, 0x80, 0x79, 0x71, 0x06, 0xd6, 0x81, - 0x47, 0xd9, 0xb7, 0xb3, 0x06, 0xf1, 0x00, 0x23, 0x80, 0x06, 0x00, 0x85, 0x07, 0xc9, 0xbf, 0x37, 0x55, 0x10, 0x00, - 0x01, 0x11, 0x13, 0x05, 0x45, 0x6c, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x37, - 0x34, 0x20, 0x00, 0xef, 0xf0, 0x1f, 0xed, 0x93, 0x07, 0x44, 0xe9, 0xc8, 0x47, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, - 0xef, 0xf0, 0x3f, 0xed, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x10, 0xf5, 0x2e, 0xaa, 0x84, 0x13, 0x05, 0x00, 0x02, 0xef, - 0xf0, 0x3f, 0xe4, 0x13, 0x04, 0x44, 0xe9, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x1f, 0xeb, - 0xaa, 0x89, 0x63, 0x10, 0x95, 0x2c, 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, - 0xf0, 0xbf, 0xe9, 0xaa, 0x84, 0x63, 0x15, 0x35, 0x2b, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, - 0x9f, 0xe8, 0xaa, 0x89, 0x63, 0x1c, 0x95, 0x28, 0x1c, 0x40, 0x48, 0x44, 0x37, 0x0a, 0x00, 0x04, 0x83, 0xc7, 0x07, - 0x00, 0x7e, 0x05, 0x13, 0x65, 0x15, 0x00, 0x93, 0xe7, 0x07, 0x20, 0x23, 0x2c, 0xfa, 0x00, 0xef, 0xf0, 0x5f, 0xe6, - 0xaa, 0x84, 0x63, 0x1a, 0x35, 0x27, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x3f, 0xe5, 0x2a, - 0x89, 0x63, 0x11, 0x95, 0x26, 0xef, 0xf0, 0x5f, 0xe0, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, - 0xdf, 0xe3, 0xaa, 0x84, 0x63, 0x16, 0x25, 0x25, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x1f, 0xdb, 0x48, 0x44, 0x23, - 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xff, 0xe1, 0x2a, 0x89, 0x63, 0x17, 0x95, 0x22, - 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xdf, 0xe0, 0xaa, 0x84, 0x63, 0x1e, 0x25, 0x21, 0x48, - 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xbf, 0xdf, 0x63, 0x16, 0x95, 0x20, 0x48, 0x44, 0x93, 0x07, - 0x00, 0x10, 0x23, 0x2c, 0xfa, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x15, 0x00, 0xef, 0xf0, 0x3f, 0xde, 0x93, 0x07, 0xa0, - 0x0a, 0xaa, 0x84, 0x63, 0x17, 0xf5, 0x1e, 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, - 0xef, 0xf0, 0x9f, 0xdc, 0xaa, 0x89, 0x63, 0x1c, 0x95, 0x1c, 0xef, 0xf0, 0xbf, 0xd7, 0x48, 0x44, 0x7e, 0x05, 0x13, - 0x65, 0x05, 0x07, 0xef, 0xf0, 0x3f, 0xdb, 0xaa, 0x84, 0x63, 0x11, 0x35, 0x1d, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, - 0x7f, 0xd2, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x5f, 0xd9, 0xaa, - 0x89, 0x63, 0x12, 0x95, 0x1a, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x3f, 0xd8, 0xaa, 0x84, - 0x63, 0x19, 0x35, 0x19, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x1f, 0xd7, 0xaa, 0x89, 0x63, - 0x10, 0x95, 0x18, 0x08, 0x40, 0x05, 0x05, 0xef, 0xf0, 0x1f, 0xd5, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, - 0xef, 0xf0, 0x7f, 0xd5, 0xaa, 0x84, 0x63, 0x13, 0x35, 0x17, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, - 0xf0, 0x5f, 0xd4, 0x2a, 0x89, 0x63, 0x1a, 0x95, 0x14, 0xef, 0xf0, 0x7f, 0xcf, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, - 0x05, 0x07, 0xef, 0xf0, 0xff, 0xd2, 0xaa, 0x84, 0x63, 0x1f, 0x25, 0x13, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x3f, - 0xca, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x1f, 0xd1, 0x63, 0x11, - 0x95, 0x12, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x1f, 0xd0, 0x93, 0x07, 0xa0, 0x0a, 0x2a, - 0x89, 0x63, 0x16, 0xf5, 0x10, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xbf, 0xce, 0xaa, 0x84, - 0x63, 0x1d, 0x25, 0x0f, 0x13, 0x05, 0x10, 0x02, 0xef, 0xf0, 0xff, 0xc5, 0x1c, 0x40, 0x48, 0x44, 0x21, 0x67, 0x83, - 0xc7, 0x07, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xd9, 0x8f, 0x23, 0x20, 0xfa, 0x02, 0xef, 0xf0, 0x3f, 0xcc, - 0xaa, 0x89, 0x63, 0x19, 0x95, 0x0c, 0x48, 0x44, 0x89, 0x64, 0x8d, 0x04, 0x7e, 0x05, 0x45, 0x8d, 0xef, 0xf0, 0xff, - 0xca, 0x2a, 0x89, 0x63, 0x1f, 0x35, 0x0b, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xdf, 0xc9, - 0xaa, 0x89, 0x63, 0x16, 0x25, 0x0b, 0x08, 0x40, 0x13, 0x05, 0x15, 0x02, 0xef, 0xf0, 0xbf, 0xc7, 0x48, 0x44, 0x7e, - 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x1f, 0xc8, 0x2a, 0x89, 0x63, 0x18, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, - 0x45, 0x8d, 0xef, 0xf0, 0x1f, 0xc7, 0xaa, 0x84, 0x63, 0x10, 0x25, 0x09, 0xef, 0xf0, 0x3f, 0xc2, 0x48, 0x44, 0x7e, - 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0xc5, 0x2a, 0x89, 0x63, 0x15, 0x95, 0x06, 0x13, 0x05, 0x00, 0x04, - 0xef, 0xf0, 0xff, 0xbc, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, - 0xc3, 0xaa, 0x84, 0x63, 0x16, 0x25, 0x05, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xbf, 0xc2, - 0x63, 0x1e, 0x95, 0x02, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x52, 0xef, 0xf0, 0xbf, 0xc1, 0x93, 0x07, 0xa0, - 0x0a, 0x63, 0x14, 0xf5, 0x02, 0x08, 0x40, 0x62, 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, - 0xb7, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x06, 0x13, 0x05, 0x15, 0x06, 0x05, 0x61, 0x6f, - 0xe0, 0x0f, 0xbb, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, - 0x01, 0x11, 0x4e, 0xc6, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x52, 0xc4, 0x93, 0x09, 0x00, 0x04, 0x63, - 0xeb, 0xb9, 0x08, 0x37, 0x3a, 0x20, 0x00, 0xaa, 0x84, 0x2e, 0x84, 0x13, 0x09, 0x4a, 0xe9, 0xef, 0xf0, 0xbf, 0xc4, - 0x03, 0x25, 0xc9, 0x00, 0x13, 0x0a, 0x4a, 0xe9, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x7f, 0xba, 0x13, - 0x85, 0x04, 0x02, 0x63, 0x19, 0x34, 0x03, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x05, 0x05, 0x02, 0x13, 0x06, - 0x00, 0x02, 0xef, 0xe0, 0xaf, 0xbb, 0x03, 0x25, 0xc9, 0x00, 0x62, 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, - 0x49, 0x22, 0x4a, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0x05, 0x61, 0x6f, 0xf0, 0x1f, 0xb7, 0xfd, 0x47, 0x63, 0xf8, - 0x87, 0x02, 0x93, 0x05, 0x04, 0xfe, 0xef, 0xf0, 0x5f, 0xbf, 0x13, 0x04, 0x04, 0x04, 0x0e, 0x04, 0x42, 0x04, 0x41, - 0x80, 0x93, 0x17, 0x84, 0x00, 0x37, 0x07, 0xff, 0x00, 0xf9, 0x8f, 0x62, 0x04, 0x3e, 0x94, 0xb7, 0x07, 0x00, 0x04, - 0x03, 0x25, 0xca, 0x00, 0xc0, 0xdf, 0x65, 0xbf, 0x01, 0x45, 0xef, 0xf0, 0x3f, 0xa9, 0xd9, 0xbf, 0xf2, 0x40, 0x62, - 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, 0x37, 0x34, - 0x20, 0x00, 0x93, 0x07, 0x44, 0xe9, 0x52, 0xc4, 0x2a, 0x8a, 0xc8, 0x47, 0x56, 0xc2, 0x06, 0xce, 0x7e, 0x05, 0x13, - 0x65, 0x05, 0x30, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xae, 0x8a, 0xef, 0xf0, 0xff, 0xaf, 0x93, 0x07, 0xa0, 0x0a, - 0x63, 0x11, 0xf5, 0x12, 0xaa, 0x84, 0x13, 0x05, 0x60, 0x03, 0xef, 0xf0, 0x7f, 0xa4, 0x13, 0x04, 0x44, 0xe9, 0x48, - 0x44, 0x7e, 0x05, 0x13, 0x65, 0x45, 0x00, 0xef, 0xf0, 0xdf, 0xad, 0x2a, 0x89, 0x63, 0x11, 0x95, 0x10, 0x48, 0x44, - 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xbf, 0xac, 0xaa, 0x84, 0x63, 0x18, 0x25, 0x0f, 0x48, 0x44, 0x09, - 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x5f, 0xab, 0xaa, 0x89, 0x63, 0x1d, 0x95, 0x0c, - 0xd6, 0x85, 0x52, 0x85, 0xef, 0xf0, 0xdf, 0xec, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xbf, - 0xa9, 0xaa, 0x84, 0x63, 0x10, 0x35, 0x0d, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x03, 0xef, 0xf0, 0x9f, 0xa8, - 0xaa, 0x89, 0x63, 0x17, 0x95, 0x0a, 0x13, 0x05, 0xc0, 0x05, 0xef, 0xf0, 0x5f, 0x9d, 0x48, 0x44, 0x7e, 0x05, 0x13, - 0x65, 0x45, 0x00, 0xef, 0xf0, 0xff, 0xa6, 0xaa, 0x84, 0x63, 0x1a, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, - 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xa5, 0xaa, 0x89, 0x63, 0x11, 0x95, 0x08, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, - 0x32, 0xef, 0xf0, 0xbf, 0xa4, 0xaa, 0x84, 0x63, 0x18, 0x35, 0x07, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, - 0xef, 0xf0, 0x9f, 0xa3, 0x63, 0x10, 0x95, 0x06, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x03, 0xef, 0xf0, 0x9f, - 0xa2, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0x63, 0x15, 0xf5, 0x04, 0x13, 0x05, 0x00, 0x06, 0xef, 0xf0, 0x9f, 0x99, - 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xbf, 0xa0, 0xaa, 0x84, 0x63, 0x18, 0x25, 0x03, 0x48, - 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x9f, 0x9f, 0x63, 0x10, 0x95, 0x02, 0x48, 0x44, 0x62, 0x44, - 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0x05, - 0x61, 0x6f, 0xf0, 0x9f, 0x9d, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, - 0x05, 0x61, 0x82, 0x80, 0x39, 0x71, 0x22, 0xdc, 0x37, 0x34, 0x20, 0x00, 0x06, 0xde, 0x4a, 0xd8, 0x26, 0xda, 0x32, - 0x89, 0x13, 0x04, 0x44, 0xe9, 0xef, 0xf0, 0xdf, 0xe8, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x40, 0xef, 0xf0, - 0x3f, 0x9a, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x0a, 0xaa, 0x84, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, - 0x05, 0xc5, 0x6b, 0xef, 0xf0, 0x9f, 0xe6, 0x85, 0x47, 0x63, 0x07, 0xf9, 0x08, 0x48, 0x44, 0x85, 0x67, 0x93, 0x87, - 0x07, 0x80, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0x5f, 0x97, 0x2a, 0x89, 0x63, 0x1c, 0x95, 0x06, 0xb7, 0x05, 0x00, - 0x04, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x04, 0x68, 0x00, 0xef, 0xe0, 0xef, 0x91, 0x48, 0x44, 0x89, 0x47, - 0x23, 0x06, 0xf1, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x20, 0xef, 0xf0, 0xbf, 0x94, 0xaa, 0x84, 0x63, 0x17, 0x25, - 0x05, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0x9f, 0x93, 0x2a, 0x89, 0x63, 0x1e, 0x95, 0x02, - 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x42, 0xef, 0xf0, 0x7f, 0x92, 0xaa, 0x84, 0x63, 0x15, 0x25, 0x03, 0x68, - 0x00, 0x93, 0x05, 0x10, 0x02, 0xef, 0xf0, 0x5f, 0xdf, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x10, 0xef, 0xf0, - 0xbf, 0x90, 0x63, 0x18, 0x95, 0x00, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xbf, 0x8f, 0xf2, - 0x50, 0x62, 0x54, 0xd2, 0x54, 0x42, 0x59, 0x21, 0x61, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, - 0x13, 0x04, 0x44, 0xe9, 0x08, 0x40, 0x09, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x06, 0xc6, 0xef, - 0xf0, 0xff, 0xf0, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x71, 0xef, 0xf0, 0x5f, 0x8c, 0x48, 0x44, 0x22, 0x44, - 0xb2, 0x40, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0x8b, 0xb7, 0x37, 0x20, 0x00, 0x03, - 0xa5, 0x47, 0xe9, 0x05, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x6f, 0xf0, 0xbf, 0xed, 0x41, 0x11, - 0xb7, 0x55, 0x10, 0x00, 0x37, 0x05, 0x00, 0x04, 0x22, 0xc4, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x45, 0x6c, 0x13, - 0x05, 0x05, 0x02, 0x37, 0x34, 0x20, 0x00, 0x06, 0xc6, 0x13, 0x04, 0x44, 0xe9, 0xef, 0xe0, 0x4f, 0x8a, 0x48, 0x44, - 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0x86, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x1d, 0xf5, 0x00, 0x08, - 0x40, 0x22, 0x44, 0xb2, 0x40, 0x05, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x41, 0x01, 0x6f, 0xf0, - 0xbf, 0xe8, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, - 0x04, 0x44, 0xe9, 0x48, 0x44, 0x06, 0xc6, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xbf, 0x82, 0x08, 0x40, - 0x13, 0x06, 0x00, 0x02, 0x81, 0x45, 0x13, 0x05, 0x15, 0x04, 0xef, 0x00, 0x90, 0x5c, 0x08, 0x40, 0x09, 0x46, 0x81, - 0x45, 0x13, 0x05, 0x15, 0x04, 0xef, 0xf0, 0xbf, 0xe4, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x60, 0xef, 0xf0, - 0x1f, 0x80, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x71, 0xef, 0xf0, 0x4f, 0xff, 0x01, 0x45, 0xef, 0xf0, 0x8f, - 0xf4, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x2f, 0xfe, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, - 0x05, 0x17, 0xef, 0xf0, 0x6f, 0xfd, 0xb2, 0x40, 0x22, 0x44, 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, 0x98, 0xc7, 0x41, - 0x01, 0x82, 0x80, 0x11, 0x65, 0xad, 0xa9, 0x37, 0x35, 0x20, 0x00, 0x41, 0x11, 0x51, 0x46, 0x81, 0x45, 0x13, 0x05, - 0x45, 0xe9, 0x06, 0xc6, 0xef, 0x00, 0xd0, 0x55, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x1d, 0x65, 0x23, - 0xa2, 0xe7, 0xfa, 0xa9, 0x21, 0xb2, 0x40, 0xb7, 0x07, 0x00, 0x04, 0x05, 0x47, 0x98, 0xcb, 0x41, 0x01, 0x6f, 0xf0, - 0xdf, 0xfc, 0x11, 0x65, 0x1d, 0xa9, 0x95, 0x47, 0x63, 0xec, 0xb7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, - 0x00, 0x13, 0x04, 0x44, 0xe9, 0x85, 0x47, 0x5c, 0xc0, 0xb7, 0x57, 0x10, 0x00, 0x0c, 0xc4, 0x93, 0x87, 0x87, 0x6e, - 0x8a, 0x05, 0xbe, 0x95, 0x9c, 0x41, 0x06, 0xc6, 0x08, 0xc0, 0x82, 0x97, 0x08, 0x48, 0xb2, 0x40, 0x23, 0x22, 0x04, - 0x00, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x05, 0x00, 0x04, 0x41, 0x46, - 0x93, 0x85, 0x05, 0x08, 0x6f, 0xd0, 0xff, 0xef, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xe9, 0x89, 0x47, 0x5c, - 0xc3, 0x5c, 0x47, 0x46, 0x05, 0xfe, 0x07, 0xc9, 0x8f, 0x21, 0x65, 0x15, 0x05, 0x5d, 0x8d, 0x6f, 0xf0, 0xef, 0xf1, - 0x39, 0x71, 0x4e, 0xd6, 0x5e, 0xce, 0x62, 0xcc, 0xb7, 0x0b, 0x00, 0x04, 0xb7, 0x39, 0x20, 0x00, 0x05, 0x6c, 0x22, - 0xdc, 0x26, 0xda, 0x4a, 0xd8, 0x56, 0xd2, 0x5a, 0xd0, 0x66, 0xca, 0x6a, 0xc8, 0x06, 0xde, 0x52, 0xd4, 0x2a, 0x84, - 0x2e, 0x8b, 0xb2, 0x8a, 0x81, 0x44, 0x01, 0x49, 0xc1, 0x4c, 0x93, 0x8b, 0x0b, 0x02, 0x93, 0x89, 0x49, 0xe9, 0x09, - 0x0c, 0x37, 0x3d, 0x20, 0x00, 0xb3, 0x05, 0x9b, 0x00, 0x63, 0xe0, 0x54, 0x03, 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, - 0x42, 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, 0xd2, 0x4c, 0x42, 0x4d, 0x21, - 0x61, 0x82, 0x80, 0x33, 0x8a, 0x9a, 0x40, 0x63, 0xd3, 0x4c, 0x01, 0x41, 0x4a, 0x4a, 0x85, 0x2e, 0xc6, 0xef, 0xe0, - 0xcf, 0x9f, 0xb2, 0x45, 0x13, 0x06, 0x3a, 0x00, 0x71, 0x9a, 0x5e, 0x85, 0xef, 0xd0, 0xbf, 0xec, 0x03, 0xa5, 0xc9, - 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xef, 0xe8, 0x03, 0xa5, 0xc9, 0x00, 0x93, 0x17, 0x8a, 0x01, - 0x7e, 0x05, 0x5d, 0x8d, 0x13, 0x65, 0x75, 0x00, 0xef, 0xf0, 0xaf, 0xe7, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x33, - 0x65, 0x85, 0x01, 0xef, 0xf0, 0xcf, 0xe6, 0x03, 0x27, 0x4d, 0xfa, 0x93, 0x07, 0x50, 0x05, 0x63, 0x19, 0xf7, 0x00, - 0x19, 0xc4, 0x22, 0x85, 0x52, 0x86, 0xca, 0x85, 0xef, 0xe0, 0x4f, 0xa3, 0x41, 0x04, 0x93, 0x07, 0x00, 0x07, 0x63, - 0xe3, 0x27, 0x01, 0x41, 0x09, 0xc1, 0x04, 0x9d, 0xb7, 0x39, 0x71, 0x4e, 0xd6, 0x5a, 0xd0, 0x5e, 0xce, 0xb7, 0x39, - 0x20, 0x00, 0x37, 0x0b, 0x02, 0x00, 0x85, 0x6b, 0x26, 0xda, 0x4a, 0xd8, 0x52, 0xd4, 0x56, 0xd2, 0x62, 0xcc, 0x6a, - 0xc8, 0x6e, 0xc6, 0x06, 0xde, 0x22, 0xdc, 0x66, 0xca, 0xaa, 0x8a, 0xae, 0x84, 0x32, 0x8a, 0x01, 0x49, 0x81, 0x4d, - 0x37, 0x3c, 0x20, 0x00, 0x41, 0x4d, 0x93, 0x89, 0x49, 0xe9, 0x1d, 0x0b, 0x93, 0x8b, 0x0b, 0x82, 0xb3, 0x8c, 0x2a, - 0x01, 0x93, 0x07, 0x4c, 0xfa, 0x63, 0x64, 0x49, 0x03, 0xf2, 0x50, 0x62, 0x54, 0x13, 0x07, 0x50, 0x05, 0x98, 0xc3, - 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, 0xd2, 0x4c, 0x42, - 0x4d, 0xb2, 0x4d, 0x21, 0x61, 0x82, 0x80, 0x33, 0x04, 0x2a, 0x41, 0x63, 0x73, 0x8d, 0x00, 0x41, 0x44, 0x6e, 0x85, - 0xef, 0xe0, 0xef, 0x91, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0xfa, 0x98, 0x43, 0x93, 0x07, 0x50, 0x05, 0x63, - 0x19, 0xf7, 0x00, 0x99, 0xc4, 0x26, 0x85, 0x22, 0x86, 0xee, 0x85, 0xef, 0xe0, 0xcf, 0x9b, 0xc1, 0x04, 0x03, 0xa5, - 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x25, 0x00, 0xef, 0xf0, 0x6f, 0xd9, 0x03, 0xa5, 0xc9, 0x00, 0x93, 0x17, 0x84, - 0x01, 0x0d, 0x04, 0x7e, 0x05, 0x5d, 0x8d, 0x33, 0x65, 0x65, 0x01, 0xef, 0xf0, 0x0f, 0xd8, 0x03, 0xa5, 0xc9, 0x00, - 0x7e, 0x05, 0x33, 0x65, 0x75, 0x01, 0xef, 0xf0, 0x2f, 0xd7, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x76, 0xc4, 0xff, 0x93, - 0x85, 0x05, 0x04, 0x66, 0x85, 0xef, 0xd0, 0x3f, 0xd2, 0x93, 0x07, 0x00, 0x06, 0x63, 0xe3, 0xb7, 0x01, 0xc1, 0x0d, - 0x41, 0x09, 0x81, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x2a, 0x84, 0x21, 0x45, 0x06, 0xc6, 0xef, 0xf0, 0x4f, 0xd4, 0x93, - 0x07, 0xa0, 0x0a, 0x63, 0x19, 0xf5, 0x00, 0x22, 0x85, 0xef, 0xf0, 0x1f, 0xdf, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, - 0x07, 0xe8, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa2, 0xa7, 0xfa, 0x82, - 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x60, 0x02, 0x98, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, - 0x98, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0xc8, 0x4b, 0x82, 0x80, 0x39, 0x71, 0x36, 0xd0, 0x3a, 0xce, 0x3e, - 0xcc, 0x05, 0x47, 0xb7, 0x07, 0x00, 0x04, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, - 0x32, 0xd2, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xd8, 0xc7, 0xb7, 0x37, 0x20, - 0x00, 0x93, 0x87, 0x47, 0xe9, 0xd8, 0x43, 0x89, 0x46, 0x7d, 0x17, 0x63, 0xfe, 0xe6, 0x02, 0x37, 0x55, 0x10, 0x00, - 0x85, 0x45, 0x13, 0x05, 0x05, 0x6c, 0xef, 0xd0, 0xef, 0xe0, 0xef, 0xc0, 0x8f, 0xdc, 0xf2, 0x50, 0xe2, 0x52, 0x52, - 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, - 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x13, 0x07, 0xa0, 0x0a, 0x98, - 0xcb, 0xd1, 0xbf, 0xb7, 0x07, 0x01, 0x02, 0x88, 0xd7, 0xcc, 0xd7, 0x88, 0xdb, 0xcc, 0xdb, 0x88, 0xdf, 0xcc, 0xdf, - 0x82, 0x80, 0x01, 0x11, 0x26, 0xca, 0xb7, 0x04, 0x01, 0x02, 0x22, 0xcc, 0xc0, 0x40, 0xf5, 0x77, 0x93, 0x87, 0xf7, - 0xa5, 0x7d, 0x8c, 0x89, 0x67, 0x93, 0x87, 0x07, 0x1a, 0x06, 0xce, 0x4a, 0xc8, 0x4e, 0xc6, 0xc1, 0x8f, 0xaa, 0x89, - 0xdc, 0xc0, 0x05, 0x45, 0x2e, 0x89, 0xef, 0xd0, 0xbf, 0x99, 0x93, 0x67, 0x04, 0x40, 0xdc, 0xc0, 0x05, 0x45, 0xef, - 0xd0, 0xff, 0x98, 0x85, 0x67, 0x93, 0x87, 0x07, 0x40, 0x5d, 0x8c, 0xc0, 0xc0, 0xb7, 0x47, 0x00, 0x08, 0x23, 0xa4, - 0x07, 0x00, 0xb7, 0x57, 0x00, 0x08, 0x23, 0xa4, 0x07, 0x00, 0xf2, 0x40, 0x62, 0x44, 0x23, 0xa0, 0x34, 0x03, 0x23, - 0xa2, 0x24, 0x03, 0xb2, 0x49, 0xd2, 0x44, 0x42, 0x49, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x02, 0x88, 0x53, - 0xcc, 0x53, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x02, 0x88, 0x47, 0x21, 0x81, 0x13, 0x75, 0xf5, 0x0f, 0x82, 0x80, 0x41, - 0x11, 0x01, 0x45, 0x81, 0x45, 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0xef, 0xf0, 0x1f, 0xf6, 0xef, 0xf0, 0x9f, 0xfd, - 0xaa, 0x84, 0x2e, 0x84, 0x2a, 0x87, 0xae, 0x86, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, - 0x00, 0x93, 0x85, 0x85, 0x71, 0x13, 0x05, 0x45, 0x64, 0x13, 0x06, 0x06, 0x70, 0xef, 0xd0, 0xaf, 0xc9, 0xa2, 0x85, - 0x22, 0x44, 0xb2, 0x40, 0x26, 0x85, 0x92, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xf3, 0x39, 0x71, 0x06, 0xde, 0x16, - 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, - 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xf0, 0x7f, 0xf9, 0xef, 0xc0, 0x4f, 0xc9, 0xf2, - 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, - 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, - 0x07, 0x00, 0x02, 0x5c, 0x47, 0xc9, 0x8f, 0x5c, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0xd8, 0x47, 0x13, 0x45, - 0xf5, 0xff, 0x79, 0x8d, 0xc8, 0xc7, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x4f, 0xc9, 0x8f, 0x1c, 0xcf, 0x82, - 0x80, 0xb7, 0x07, 0x00, 0x02, 0x98, 0x4f, 0x13, 0x45, 0xf5, 0xff, 0x79, 0x8d, 0x88, 0xcf, 0x82, 0x80, 0xb7, 0x07, - 0x00, 0x02, 0xc8, 0xcb, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x47, 0x00, 0x1c, 0xc7, 0xb7, - 0x07, 0x00, 0x03, 0x94, 0x4b, 0x37, 0x37, 0x20, 0x00, 0x23, 0x24, 0xd7, 0xfa, 0x23, 0xa8, 0x07, 0x00, 0x82, 0x80, - 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0xb7, 0x06, 0x00, 0x03, 0xf9, 0x9b, 0x1c, 0xc7, 0x37, 0x07, 0x08, 0x00, 0x9c, - 0x46, 0xf9, 0x8f, 0xf5, 0xff, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x17, 0x00, 0x1c, 0xc7, - 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x87, 0xfa, 0xb7, 0x07, 0x00, 0x03, 0x98, 0xcb, 0x82, 0x80, 0xb7, 0x37, 0x20, - 0x00, 0x03, 0xa5, 0xc7, 0xfa, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0xb7, 0x27, 0x03, 0x04, 0x9c, 0x47, - 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x13, 0x05, 0x00, 0x10, 0x6f, - 0xf0, 0x3f, 0xf4, 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0x41, 0x11, 0x37, 0x37, - 0x20, 0x00, 0x23, 0x28, 0xf7, 0xfa, 0x06, 0xc6, 0xef, 0xf0, 0x1f, 0xfe, 0xb7, 0x27, 0x03, 0x04, 0x09, 0x47, 0xd8, - 0xc3, 0x37, 0x17, 0x03, 0x04, 0xb7, 0x07, 0x03, 0x04, 0x13, 0x07, 0x07, 0x80, 0x23, 0xa0, 0x07, 0x00, 0x91, 0x07, - 0xe3, 0x9d, 0xe7, 0xfe, 0xb7, 0x27, 0x03, 0x04, 0x0d, 0x47, 0xd8, 0xc7, 0x98, 0x47, 0x85, 0x47, 0x13, 0x05, 0xa0, - 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x00, 0x10, - 0x6f, 0xf0, 0xff, 0xee, 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0x37, 0x37, 0x20, - 0x00, 0x23, 0x28, 0xf7, 0xfa, 0xb7, 0x27, 0x03, 0x04, 0x05, 0x47, 0xd8, 0xc3, 0x82, 0x80, 0xc2, 0x05, 0xc9, 0x8d, - 0x93, 0xe5, 0x05, 0x10, 0xb7, 0x07, 0x03, 0x04, 0x23, 0xa0, 0xb7, 0x10, 0x82, 0x80, 0xc2, 0x05, 0xc9, 0x8d, 0x11, - 0x65, 0x13, 0x05, 0x05, 0x50, 0xc9, 0x8d, 0xb7, 0x07, 0x03, 0x04, 0x23, 0xa0, 0xb7, 0x10, 0x82, 0x80, 0x41, 0x11, - 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xb0, 0x9f, 0xc4, 0x37, 0x15, 0x03, - 0x04, 0x2a, 0x94, 0x08, 0x40, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x79, 0x71, 0x26, 0xd2, 0x4a, 0xd0, - 0x4e, 0xce, 0x06, 0xd6, 0x22, 0xd4, 0xaa, 0x84, 0x2e, 0x89, 0xb2, 0x89, 0x19, 0xe1, 0xef, 0xb0, 0x1f, 0xc2, 0x93, - 0x77, 0x39, 0x00, 0x99, 0xc3, 0xef, 0xb0, 0x7f, 0xc1, 0x01, 0x44, 0x63, 0x69, 0x34, 0x01, 0xb2, 0x50, 0x22, 0x54, - 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x45, 0x61, 0x82, 0x80, 0x33, 0x05, 0x24, 0x01, 0xef, 0xf0, 0x5f, 0xfa, 0x2a, - 0xc6, 0x11, 0x46, 0x33, 0x85, 0x84, 0x00, 0x6c, 0x00, 0xcd, 0x2d, 0x11, 0x04, 0xe1, 0xbf, 0x79, 0x71, 0x22, 0xd4, - 0x4a, 0xd0, 0x4e, 0xce, 0x56, 0xca, 0x06, 0xd6, 0x26, 0xd2, 0x52, 0xcc, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0xae, - 0x89, 0x32, 0x89, 0x93, 0x7a, 0xc6, 0xff, 0x99, 0xc3, 0xef, 0xb0, 0x7f, 0xbc, 0x37, 0x0a, 0x03, 0x04, 0x81, 0x44, - 0x22, 0x9a, 0x63, 0xe9, 0x54, 0x03, 0x13, 0x76, 0x39, 0x00, 0x01, 0xce, 0xb3, 0x85, 0x99, 0x00, 0x68, 0x00, 0x02, - 0xc6, 0x7d, 0x25, 0xb2, 0x47, 0x37, 0x05, 0x03, 0x04, 0x2a, 0x94, 0x26, 0x94, 0x1c, 0xc0, 0xb2, 0x50, 0x22, 0x54, - 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0xd2, 0x4a, 0x45, 0x61, 0x82, 0x80, 0x63, 0x94, 0x09, 0x00, 0xef, - 0xb0, 0x5f, 0xb8, 0xb3, 0x85, 0x99, 0x00, 0x11, 0x46, 0x68, 0x00, 0xbd, 0x2d, 0x32, 0x47, 0xb3, 0x07, 0x9a, 0x00, - 0x91, 0x04, 0x98, 0xc3, 0x4d, 0xbf, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x41, 0x11, 0x13, 0x05, 0x45, 0xb5, 0x06, - 0xc6, 0x22, 0xc4, 0xef, 0xd0, 0xef, 0xe9, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0f, 0xf5, 0x00, 0x37, 0x55, 0x10, 0x00, - 0x85, 0x45, 0x13, 0x05, 0x05, 0x72, 0xef, 0xd0, 0x2f, 0xa3, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x41, - 0x01, 0x82, 0x80, 0xb7, 0x17, 0x03, 0x04, 0x83, 0xa7, 0x07, 0x10, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, 0xfb, - 0x93, 0xf7, 0xf7, 0x0f, 0x81, 0xe7, 0x1c, 0x40, 0x63, 0x9d, 0xa7, 0x00, 0x37, 0x55, 0x10, 0x00, 0x8d, 0x45, 0x13, - 0x05, 0x05, 0x72, 0xef, 0xd0, 0xcf, 0x9f, 0x93, 0x07, 0xa0, 0x0a, 0x1c, 0xc0, 0xd1, 0xb7, 0xb7, 0x37, 0x20, 0x00, - 0x03, 0xa7, 0xc7, 0xfa, 0x13, 0x84, 0xc7, 0xfa, 0x63, 0x09, 0xa7, 0x00, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, 0x13, - 0x05, 0x05, 0x72, 0xef, 0xd0, 0x6f, 0x9d, 0x08, 0x40, 0x5d, 0xb7, 0x37, 0x95, 0x04, 0x00, 0x13, 0x05, 0x05, 0x3e, - 0x6f, 0xf0, 0xff, 0xf6, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x5f, 0xe6, 0xef, 0xf0, 0x1f, 0xe3, 0xb2, 0x40, 0x41, - 0x01, 0x6f, 0xf0, 0x5f, 0xfe, 0xb7, 0x17, 0x03, 0x04, 0x03, 0xa5, 0x07, 0x10, 0x41, 0x81, 0x82, 0x80, 0x41, 0x11, - 0x3a, 0xc4, 0x37, 0x27, 0x03, 0x04, 0x3e, 0xc2, 0x1c, 0x47, 0x36, 0xc6, 0x93, 0xf6, 0x27, 0x00, 0x89, 0xca, 0x89, - 0x46, 0x14, 0xc7, 0x37, 0x37, 0x20, 0x00, 0x93, 0x06, 0xa0, 0x0a, 0x23, 0x26, 0xd7, 0xfa, 0x91, 0x8b, 0x99, 0xcf, - 0xb7, 0x27, 0x03, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x93, 0x07, 0xa0, 0x0a, 0x37, 0x37, 0x20, 0x00, 0x23, 0x28, 0xf7, - 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0xb2, 0x46, 0x22, 0x47, 0x92, 0x47, 0x41, 0x01, 0x73, 0x00, - 0x20, 0x30, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x04, 0x00, 0x03, 0x1c, 0x48, 0x06, 0xc6, 0xdd, 0x9b, 0x1c, 0xc8, 0xef, - 0xe0, 0x0f, 0xd9, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x02, 0x5c, 0xcc, 0xb2, 0x40, 0x22, 0x44, 0xb7, 0x37, - 0x20, 0x00, 0x23, 0x8c, 0x07, 0xfa, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x2a, 0x84, 0x21, 0x45, 0x06, - 0xc6, 0xef, 0xf0, 0x7f, 0xca, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x7f, 0xc6, 0x22, 0x04, 0x13, 0x64, 0x04, 0x03, - 0x37, 0x07, 0x00, 0x03, 0x40, 0xc3, 0xb2, 0x40, 0x22, 0x44, 0xc1, 0x67, 0x93, 0x87, 0xa7, 0xfa, 0x1c, 0xcf, 0x41, - 0x01, 0x82, 0x80, 0x41, 0x11, 0x26, 0xc2, 0xaa, 0x84, 0x09, 0x45, 0x22, 0xc4, 0x06, 0xc6, 0x2e, 0x84, 0xef, 0xf0, - 0x1f, 0xfc, 0x37, 0x07, 0x20, 0x00, 0xb7, 0x07, 0x00, 0x03, 0x13, 0x07, 0x07, 0x02, 0xd8, 0xcf, 0x37, 0x37, 0x20, - 0x00, 0x23, 0x2a, 0x97, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2e, 0x87, 0xfa, 0xb2, 0x40, 0x22, 0x44, 0x05, 0x47, - 0x98, 0xcb, 0x37, 0x07, 0x08, 0x00, 0x98, 0xc7, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x03, 0x9c, - 0x47, 0x37, 0x07, 0x04, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, - 0x37, 0x07, 0x00, 0x03, 0x5c, 0x53, 0x13, 0x05, 0x50, 0x05, 0x93, 0x96, 0x07, 0x01, 0xc1, 0x82, 0xc1, 0x83, 0x63, - 0x97, 0xf6, 0x00, 0x1c, 0x47, 0x91, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, - 0xef, 0xf0, 0xff, 0xf1, 0x37, 0x07, 0x00, 0x03, 0x5c, 0x47, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc7, 0x5c, 0x47, 0x85, - 0x8b, 0xf5, 0xff, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xfb, 0x95, 0xc3, - 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x5f, 0xef, 0xb7, 0x07, 0x00, 0x03, 0x98, 0x4b, 0xb2, 0x40, 0x13, 0x67, 0x87, - 0x00, 0x98, 0xcb, 0x37, 0x07, 0x08, 0x00, 0x98, 0xc7, 0x41, 0x01, 0x6f, 0xe0, 0xcf, 0xc5, 0x82, 0x80, 0x37, 0x07, - 0x00, 0x03, 0x1c, 0x4b, 0xf9, 0x9b, 0x1c, 0xcb, 0x82, 0x80, 0xb7, 0x06, 0x00, 0x03, 0xdc, 0x42, 0x7d, 0x77, 0x13, - 0x07, 0xf7, 0x0f, 0xf9, 0x8f, 0x05, 0x67, 0x22, 0x05, 0x13, 0x07, 0x07, 0xf0, 0x79, 0x8d, 0x5d, 0x8d, 0xc8, 0xc2, - 0x82, 0x80, 0x1d, 0x71, 0x3a, 0xda, 0x37, 0x07, 0x00, 0x03, 0x3e, 0xd8, 0x1c, 0x47, 0x86, 0xce, 0x96, 0xcc, 0x9a, - 0xca, 0x9e, 0xc8, 0xa2, 0xc6, 0xa6, 0xc4, 0xaa, 0xc2, 0xae, 0xc0, 0x32, 0xde, 0x36, 0xdc, 0x42, 0xd6, 0x46, 0xd4, - 0x4a, 0xd2, 0x4e, 0xd0, 0x72, 0xce, 0x76, 0xcc, 0x7a, 0xca, 0x7e, 0xc8, 0x85, 0x8b, 0xa1, 0xc7, 0x04, 0x57, 0x11, - 0x44, 0x37, 0x39, 0x20, 0x00, 0x83, 0x27, 0x49, 0xfb, 0x13, 0xf5, 0xf4, 0x0f, 0x7d, 0x14, 0x82, 0x97, 0xa1, 0x80, - 0x6d, 0xf8, 0x36, 0x44, 0xf6, 0x40, 0xe6, 0x42, 0x56, 0x43, 0xc6, 0x43, 0xa6, 0x44, 0x16, 0x45, 0x86, 0x45, 0x72, - 0x56, 0xe2, 0x56, 0x52, 0x57, 0xc2, 0x57, 0x32, 0x58, 0xa2, 0x58, 0x12, 0x59, 0x82, 0x59, 0x72, 0x4e, 0xe2, 0x4e, - 0x52, 0x4f, 0xc2, 0x4f, 0x25, 0x61, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xc7, 0x87, 0xfb, 0x13, - 0x84, 0x87, 0xfb, 0x05, 0xeb, 0xb7, 0x04, 0x00, 0x03, 0x37, 0x39, 0x20, 0x00, 0x93, 0x09, 0xa0, 0x0a, 0x9c, 0x44, - 0x91, 0x8b, 0xd5, 0xfb, 0x83, 0x27, 0xc9, 0xfb, 0x68, 0x00, 0x82, 0x97, 0x63, 0x0d, 0x35, 0x01, 0x85, 0x47, 0x23, - 0x00, 0xf4, 0x00, 0xc1, 0x67, 0x93, 0x87, 0x07, 0x02, 0xdc, 0xcc, 0x61, 0xbf, 0xef, 0xf0, 0x5f, 0xdf, 0x49, 0xbf, - 0xb2, 0x47, 0x9c, 0xd8, 0xd1, 0xbf, 0x5c, 0x41, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc1, 0x82, 0x80, 0x5c, 0x41, 0xf9, - 0x9b, 0x5c, 0xc1, 0x82, 0x80, 0x5c, 0x41, 0xf5, 0x9b, 0xd1, 0x8f, 0x5c, 0xc1, 0x14, 0xc9, 0x4c, 0xc9, 0x82, 0x80, - 0x5c, 0x45, 0xcd, 0x8f, 0x5c, 0xc5, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x07, 0xfc, 0x82, 0x80, 0x39, - 0x71, 0x3a, 0xce, 0x37, 0x07, 0x10, 0x01, 0x3e, 0xcc, 0x1c, 0x47, 0x58, 0x47, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, - 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, - 0xc2, 0x7e, 0xc0, 0xf9, 0x8f, 0x91, 0xcf, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xfc, 0x98, 0x43, 0x05, 0x07, - 0x98, 0xc3, 0xb7, 0x07, 0x10, 0x01, 0x98, 0x47, 0x0d, 0x8b, 0x98, 0xc7, 0x19, 0xa8, 0xb7, 0x07, 0x20, 0x01, 0x98, - 0x47, 0xdc, 0x47, 0x7d, 0x8f, 0xb7, 0x07, 0x20, 0x01, 0x6d, 0xf7, 0xef, 0xb0, 0xff, 0xe6, 0xf2, 0x50, 0xe2, 0x52, - 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, - 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x1c, 0x41, 0x63, 0xf7, - 0xb7, 0x00, 0x23, 0x80, 0xc7, 0x00, 0x1c, 0x41, 0x85, 0x07, 0x1c, 0xc1, 0x82, 0x80, 0x1d, 0x71, 0xa2, 0xcc, 0xa6, - 0xca, 0xca, 0xc8, 0x86, 0xce, 0xce, 0xc6, 0xd2, 0xc4, 0xd6, 0xc2, 0xda, 0xc0, 0x5e, 0xde, 0x62, 0xdc, 0x66, 0xda, - 0x6a, 0xd8, 0x6e, 0xd6, 0x2a, 0xc6, 0x2e, 0x84, 0x32, 0x89, 0xb6, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x0f, 0xf6, 0x63, - 0x14, 0x09, 0x00, 0xef, 0xb0, 0x8f, 0xf5, 0x01, 0x45, 0x05, 0xc4, 0xb2, 0x4a, 0x7d, 0x14, 0x25, 0x4a, 0x56, 0x94, - 0x93, 0x0c, 0xc0, 0x06, 0x13, 0x0b, 0x30, 0x07, 0xa9, 0x4b, 0x1d, 0x4d, 0x03, 0x46, 0x09, 0x00, 0x15, 0xe6, 0xb2, - 0x47, 0x23, 0x80, 0x07, 0x00, 0x32, 0x45, 0x33, 0x05, 0x55, 0x41, 0xf6, 0x40, 0x66, 0x44, 0xd6, 0x44, 0x46, 0x49, - 0xb6, 0x49, 0x26, 0x4a, 0x96, 0x4a, 0x06, 0x4b, 0xf2, 0x5b, 0x62, 0x5c, 0xd2, 0x5c, 0x42, 0x5d, 0xb2, 0x5d, 0x25, - 0x61, 0x82, 0x80, 0x93, 0x07, 0x50, 0x02, 0x63, 0x1f, 0xf6, 0x02, 0x93, 0x07, 0x19, 0x00, 0x83, 0xc6, 0x07, 0x00, - 0x3e, 0x89, 0x85, 0x07, 0x13, 0x87, 0x06, 0xfd, 0x13, 0x77, 0xf7, 0x0f, 0xe3, 0x78, 0xea, 0xfe, 0x63, 0x93, 0x96, - 0x01, 0x3e, 0x89, 0x03, 0x46, 0x09, 0x00, 0x63, 0x06, 0x66, 0x0d, 0x63, 0x60, 0xcb, 0x02, 0x93, 0x07, 0x30, 0x06, - 0x63, 0x05, 0xf6, 0x06, 0x93, 0x07, 0x40, 0x06, 0x63, 0x0c, 0xf6, 0x06, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, - 0xf2, 0xa6, 0x89, 0x95, 0xa0, 0x93, 0x07, 0x50, 0x07, 0x63, 0x02, 0xf6, 0x06, 0x93, 0x07, 0x80, 0x07, 0xe3, 0x14, - 0xf6, 0xfe, 0x98, 0x40, 0x93, 0x89, 0x44, 0x00, 0x81, 0x46, 0x37, 0x06, 0x00, 0xf0, 0xb3, 0x75, 0xc7, 0x00, 0xba, - 0x84, 0x36, 0x8c, 0x12, 0x07, 0x85, 0x06, 0x89, 0xe5, 0xe3, 0x99, 0xa6, 0xff, 0x1d, 0x4c, 0xba, 0x84, 0xa1, 0x4d, - 0x13, 0xd7, 0xc4, 0x01, 0x63, 0x74, 0xea, 0x08, 0x13, 0x06, 0x77, 0x05, 0xa2, 0x85, 0x68, 0x00, 0x05, 0x0c, 0xef, - 0xf0, 0x1f, 0xee, 0x92, 0x04, 0xe3, 0x14, 0xbc, 0xff, 0x09, 0xa8, 0x03, 0xc6, 0x04, 0x00, 0xa2, 0x85, 0x68, 0x00, - 0x93, 0x89, 0x44, 0x00, 0xef, 0xf0, 0x9f, 0xec, 0x05, 0x09, 0xce, 0x84, 0x31, 0xbf, 0x5c, 0x08, 0x98, 0x40, 0x93, - 0x89, 0x44, 0x00, 0x3e, 0x8c, 0x81, 0x44, 0xb3, 0x76, 0x77, 0x03, 0x85, 0x04, 0x85, 0x07, 0x93, 0x86, 0x06, 0x03, - 0xa3, 0x8f, 0xd7, 0xfe, 0xba, 0x86, 0x33, 0x57, 0x77, 0x03, 0xe3, 0x65, 0xda, 0xfe, 0xfd, 0x5d, 0xfd, 0x14, 0xe3, - 0x88, 0xb4, 0xfd, 0xb3, 0x07, 0x9c, 0x00, 0x03, 0xc6, 0x07, 0x00, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0x5f, 0xe8, - 0xed, 0xb7, 0x93, 0x89, 0x44, 0x00, 0x84, 0x40, 0x03, 0xc6, 0x04, 0x00, 0x45, 0xda, 0xa2, 0x85, 0x68, 0x00, 0xef, - 0xf0, 0xff, 0xe6, 0x85, 0x04, 0xc5, 0xbf, 0x13, 0x06, 0x07, 0x03, 0xb5, 0xbf, 0x41, 0x11, 0x26, 0xc2, 0xb7, 0x34, - 0x20, 0x00, 0x2a, 0x86, 0xae, 0x86, 0x13, 0x85, 0x84, 0xea, 0x93, 0x05, 0x00, 0x08, 0x06, 0xc6, 0x22, 0xc4, 0xef, - 0xf0, 0xbf, 0xe5, 0x2a, 0x84, 0x13, 0x85, 0x84, 0xea, 0xef, 0xd0, 0x8f, 0x9b, 0xb2, 0x40, 0x22, 0x85, 0x22, 0x44, - 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x26, 0xca, 0xb7, 0x34, 0x20, 0x00, 0x2e, 0xd2, 0x32, 0xd4, 0x36, - 0xd6, 0x2a, 0x86, 0x54, 0x10, 0x93, 0x05, 0x00, 0x08, 0x13, 0x85, 0x84, 0xea, 0x06, 0xce, 0x22, 0xcc, 0x3a, 0xd8, - 0x3e, 0xda, 0x42, 0xdc, 0x46, 0xde, 0x36, 0xc6, 0xef, 0xf0, 0x9f, 0xe1, 0x2a, 0x84, 0x13, 0x85, 0x84, 0xea, 0xef, - 0xd0, 0x6f, 0x97, 0xf2, 0x40, 0x22, 0x85, 0x62, 0x44, 0xd2, 0x44, 0x21, 0x61, 0x82, 0x80, 0x22, 0x05, 0x61, 0x77, - 0x2d, 0x8d, 0xa1, 0x47, 0x15, 0x07, 0x93, 0x16, 0x05, 0x01, 0x06, 0x05, 0x42, 0x05, 0xc1, 0x86, 0x41, 0x81, 0x63, - 0xd5, 0x06, 0x00, 0x39, 0x8d, 0x42, 0x05, 0x41, 0x81, 0xfd, 0x17, 0xe5, 0xf7, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, - 0x26, 0xc2, 0x2a, 0x84, 0xb3, 0x04, 0xb5, 0x00, 0x06, 0xc6, 0x01, 0x45, 0x63, 0x97, 0x84, 0x00, 0xb2, 0x40, 0x22, - 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x04, 0xaa, 0x85, 0x03, 0x45, 0xf4, 0xff, 0xef, 0xf0, 0x5f, 0xfb, - 0xdd, 0xb7, 0xb7, 0x86, 0xb8, 0xed, 0x01, 0x47, 0xfd, 0x57, 0x93, 0x86, 0x06, 0x32, 0x63, 0x15, 0xb7, 0x00, 0x13, - 0xc5, 0xf7, 0xff, 0x82, 0x80, 0x33, 0x06, 0xe5, 0x00, 0x03, 0x46, 0x06, 0x00, 0xb1, 0x8f, 0x21, 0x46, 0x13, 0xd8, - 0x17, 0x00, 0x85, 0x8b, 0x91, 0xc3, 0xb6, 0x87, 0x7d, 0x16, 0xb3, 0x47, 0xf8, 0x00, 0x65, 0xfa, 0x05, 0x07, 0xd9, - 0xbf, 0x2a, 0x83, 0x09, 0xca, 0x83, 0x83, 0x05, 0x00, 0x23, 0x00, 0x73, 0x00, 0x7d, 0x16, 0x05, 0x03, 0x85, 0x05, - 0x6d, 0xfa, 0x82, 0x80, 0x15, 0xc2, 0x2a, 0x83, 0x85, 0x46, 0x63, 0x67, 0xb5, 0x00, 0xfd, 0x56, 0x13, 0x07, 0xf6, - 0xff, 0x3a, 0x93, 0xba, 0x95, 0x83, 0x83, 0x05, 0x00, 0x23, 0x00, 0x73, 0x00, 0x7d, 0x16, 0x36, 0x93, 0xb6, 0x95, - 0x6d, 0xfa, 0x82, 0x80, 0x2a, 0x83, 0x11, 0xc6, 0x23, 0x00, 0xb3, 0x00, 0x7d, 0x16, 0x05, 0x03, 0x65, 0xfe, 0x82, - 0x80, 0x00, 0x00, 0x63, 0x6f, 0x64, 0x65, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, 0x53, 0x45, 0x43, 0x43, - 0x48, 0x4e, 0x4c, 0x00, 0x4d, 0x43, 0x4e, 0x54, 0x00, 0x00, 0x00, 0x00, 0x54, 0x58, 0x3a, 0x20, 0x25, 0x64, 0x2f, - 0x25, 0x64, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x43, 0x4d, 0x44, 0x33, 0x00, 0x00, 0x00, 0x00, 0x49, 0x00, - 0x00, 0x00, 0x65, 0x6e, 0x61, 0x62, 0x6c, 0x65, 0x64, 0x20, 0x25, 0x64, 0x00, 0x00, 0x4d, 0x41, 0x49, 0x4e, 0x00, - 0x00, 0x00, 0x00, 0x6c, 0x65, 0x6e, 0x20, 0x25, 0x64, 0x2f, 0x25, 0x64, 0x00, 0x00, 0x00, 0x72, 0x73, 0x70, 0x3d, - 0x25, 0x78, 0x00, 0x00, 0x73, 0x74, 0x61, 0x72, 0x74, 0x2c, 0x20, 0x76, 0x25, 0x75, 0x2e, 0x25, 0x75, 0x2e, 0x25, - 0x75, 0x00, 0x00, 0x00, 0x00, 0x50, 0x52, 0x4f, 0x56, 0x49, 0x53, 0x49, 0x4f, 0x4e, 0x20, 0x4f, 0x4b, 0x00, 0x00, - 0x00, 0x00, 0x4e, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x43, 0x50, 0x42, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x4c, - 0x33, 0x20, 0x63, 0x6d, 0x64, 0x20, 0x25, 0x64, 0x3a, 0x20, 0x25, 0x78, 0x2c, 0x20, 0x6c, 0x65, 0x6e, 0x3a, 0x20, - 0x25, 0x64, 0x00, 0x00, 0x4c, 0x33, 0x20, 0x61, 0x63, 0x63, 0x65, 0x73, 0x73, 0x20, 0x66, 0x61, 0x69, 0x6c, 0x65, - 0x64, 0x2c, 0x20, 0x63, 0x6d, 0x64, 0x3a, 0x20, 0x25, 0x64, 0x2c, 0x20, 0x6c, 0x65, 0x6e, 0x3a, 0x20, 0x25, 0x64, - 0x20, 0x00, 0x70, 0x69, 0x6e, 0x67, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x00, 0x4c, 0x33, 0x00, 0x00, 0x57, - 0x52, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x00, 0x52, 0x44, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x00, 0x6d, 0x61, 0x63, 0x61, - 0x6e, 0x64, 0x64, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x00, 0x00, 0x73, 0x65, 0x6e, 0x74, 0x00, 0x00, 0x00, - 0x00, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x20, 0x73, 0x6c, 0x65, 0x65, 0x70, 0x00, 0x77, 0x61, 0x6b, 0x65, 0x75, 0x70, - 0x00, 0x00, 0x56, 0x19, 0x10, 0x00, 0x94, 0x19, 0x10, 0x00, 0xc0, 0x19, 0x10, 0x00, 0xf0, 0x19, 0x10, 0x00, 0xf8, - 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, - 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, - 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0x0a, 0x1a, 0x10, 0x00, 0x64, 0x1a, 0x10, 0x00, 0x00, 0x00, - 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 0x00, 0x06, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0xa0, - 0x1f, 0x00, 0x06, 0x02, 0x00, 0x05, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x06, 0x03, 0x10, 0x08, 0x00, - 0x00, 0x18, 0x00, 0x00, 0x40, 0x1f, 0x00, 0x06, 0x06, 0x10, 0x08, 0x00, 0x04, 0x18, 0x00, 0x00, 0x60, 0x1f, 0x00, - 0x06, 0x04, 0x00, 0x09, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x06, 0x05, 0x05, 0x7f, 0x07, 0x01, 0x08, 0x18, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xf0, 0x01, 0x10, 0x10, 0x00, 0x04, 0x02, 0x11, 0x00, 0x44, 0x02, 0x12, - 0x00, 0x84, 0x02, 0x20, 0x90, 0x01, 0x03, 0x21, 0x80, 0x42, 0x03, 0x22, 0xf0, 0x01, 0x03, 0x30, 0x80, 0x02, 0x04, - 0x31, 0x80, 0x42, 0x04, 0x40, 0x70, 0x04, 0x11, 0x41, 0x70, 0x44, 0x11, 0x42, 0x70, 0x84, 0x11, 0x50, 0xf0, 0x01, - 0x12, 0x60, 0x32, 0x04, 0x13, 0x61, 0x32, 0x44, 0x13, 0x62, 0x32, 0x84, 0x13, 0x63, 0x32, 0xc4, 0x13, 0x70, 0x32, - 0x04, 0x14, 0x71, 0x32, 0x44, 0x14, 0x80, 0x20, 0x04, 0x15, 0x81, 0x20, 0x84, 0x15, 0x82, 0x20, 0x44, 0x15, 0x90, - 0x51, 0x04, 0x16, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x14, 0x04, 0x04, 0x00, 0x08, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x23, 0x20, 0x25, 0x6c, 0x75, 0x20, 0x00, 0x00, 0x25, 0x73, 0x28, 0x25, 0x73, 0x29, 0x3a, 0x20, 0x00, 0x00, - 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x45, 0x00, 0x00, 0x00, 0x4d, 0x53, 0x47, 0x00, 0x43, 0x52, 0x43, 0x20, 0x72, - 0x78, 0x3a, 0x20, 0x25, 0x30, 0x34, 0x78, 0x2c, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x3a, 0x20, 0x25, 0x30, 0x34, 0x78, - 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0xe4, 0x1f, 0x10, 0x00, 0x04, 0x20, 0x10, 0x00, 0x56, 0x20, 0x10, - 0x00, 0xb8, 0x20, 0x10, 0x00, 0xc2, 0x20, 0x10, 0x00, 0x4f, 0x53, 0x00, 0x00, 0x63, 0x6f, 0x6e, 0x64, 0x3a, 0x20, - 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, 0x52, 0x58, 0x3a, 0x20, 0x63, 0x6d, 0x64, 0x3d, 0x30, 0x78, 0x25, 0x30, 0x32, - 0x78, 0x00, 0x00, 0x55, 0x49, 0x00, 0x00, 0x43, 0x50, 0x42, 0x20, 0x49, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, - 0x74, 0x20, 0x21, 0x00, 0x43, 0x50, 0x42, 0x00, 0x57, 0x00, 0x00, 0x00, 0x46, 0x53, 0x53, 0x00, 0x49, 0x52, 0x51, - 0x00, 0x53, 0x54, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x4b, 0x44, 0x42, 0x00, 0x73, 0x74, 0x3a, 0x20, 0x25, 0x78, - 0x00, 0x00, 0x4d, 0x41, 0x44, 0x00, 0x4f, 0x54, 0x50, 0x00, 0x01, 0x00, 0x00, 0x00, 0x53, 0x43, 0x42, 0x00, 0x4e, - 0x6f, 0x69, 0x73, 0x65, 0x5f, 0x4b, 0x4b, 0x31, 0x5f, 0x32, 0x35, 0x35, 0x31, 0x39, 0x5f, 0x41, 0x45, 0x53, 0x47, - 0x43, 0x4d, 0x5f, 0x53, 0x48, 0x41, 0x32, 0x35, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x3f, 0x10, - 0x00, 0x78, 0x45, 0x10, 0x00, 0x62, 0x45, 0x10, 0x00, 0x26, 0x45, 0x10, 0x00, 0x3a, 0x3e, 0x10, 0x00, 0xd0, 0x45, - 0x10, 0x00, 0x41, 0x4c, 0x41, 0x52, 0x4d, 0x20, 0x43, 0x48, 0x41, 0x4e, 0x4e, 0x45, 0x4c, 0x53, 0x3a, 0x20, 0x25, - 0x78, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x53, 0x43, 0x4e, 0x54, 0x52, 0x00, 0x00, 0x00, 0x53, 0x50, 0x45, 0x43, - 0x54, 0x00, 0x00, 0x00, 0xc3, 0x14, 0x13, 0x00}; \ No newline at end of file +const uint8_t fw_CPU[] = { + 0xa1, 0xc5, 0x90, 0x6f, 0xeb, 0x05, 0xe3, 0x91, 0xf0, 0x7c, 0x2f, 0x4a, 0x0f, 0x89, 0x75, 0xc1, + 0x4b, 0xa1, 0xa4, 0x44, 0x0e, 0x9c, 0xb0, 0x1d, 0xc1, 0x05, 0x80, 0xed, 0x88, 0x38, 0xfd, 0xe0, + 0xf2, 0x28, 0xd3, 0x91, 0x32, 0xbd, 0x6a, 0x95, 0xf0, 0x6f, 0x8e, 0xba, 0x29, 0x56, 0x64, 0xa9, + 0x20, 0xc0, 0xcb, 0xdb, 0xd4, 0x50, 0x5e, 0xee, 0xb6, 0x57, 0x6f, 0xa7, 0xf5, 0xba, 0x97, 0x06, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x2c, 0x57, 0x00, 0x00, 0xbe, 0x52, 0xea, 0x0a, + 0xec, 0x8f, 0xcf, 0xa2, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x6f, 0x30, 0x00, 0x43, 0x6f, 0x30, 0x20, 0x3d, 0x6f, 0x30, 0xe0, 0x3c, 0x6f, 0x30, 0xa0, 0x3c, + 0x6f, 0x30, 0x60, 0x3c, 0x6f, 0x30, 0x20, 0x3c, 0x6f, 0x30, 0xe0, 0x3b, 0x6f, 0x50, 0x60, 0x04, + 0x6f, 0x30, 0x60, 0x3b, 0x6f, 0x30, 0x20, 0x3b, 0x6f, 0x30, 0xe0, 0x3a, 0x6f, 0x30, 0xa0, 0x7f, + 0x6f, 0x30, 0x60, 0x3a, 0x6f, 0x30, 0x20, 0x3a, 0x6f, 0x30, 0xe0, 0x39, 0x6f, 0x30, 0xa0, 0x39, + 0x6f, 0x40, 0xf0, 0x72, 0x6f, 0x30, 0x20, 0x26, 0x6f, 0x30, 0x50, 0x20, 0x6f, 0x40, 0x30, 0x22, + 0x6f, 0x40, 0xf0, 0x21, 0x6f, 0x40, 0xb0, 0x21, 0x6f, 0x30, 0xa0, 0x4c, 0x6f, 0x30, 0xa0, 0x4d, + 0x6f, 0x30, 0xf0, 0x42, 0x6f, 0x40, 0x50, 0x56, 0x6f, 0x30, 0x20, 0x4e, 0x6f, 0x20, 0x30, 0x1f, + 0x6f, 0x40, 0x70, 0x0a, 0x6f, 0x30, 0xa0, 0x4e, 0x6f, 0x30, 0x00, 0x5b, 0x6f, 0x30, 0x00, 0x3f, + 0x93, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x93, 0x01, 0x00, 0x00, 0x13, 0x02, 0x00, 0x00, + 0x93, 0x02, 0x00, 0x00, 0x13, 0x03, 0x00, 0x00, 0x93, 0x03, 0x00, 0x00, 0x13, 0x04, 0x00, 0x00, + 0x93, 0x04, 0x00, 0x00, 0x13, 0x05, 0x00, 0x00, 0x93, 0x05, 0x00, 0x00, 0x13, 0x06, 0x00, 0x00, + 0x93, 0x06, 0x00, 0x00, 0x13, 0x07, 0x00, 0x00, 0x93, 0x07, 0x00, 0x00, 0x13, 0x08, 0x00, 0x00, + 0x93, 0x08, 0x00, 0x00, 0x13, 0x09, 0x00, 0x00, 0x93, 0x09, 0x00, 0x00, 0x13, 0x0a, 0x00, 0x00, + 0x93, 0x0a, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x93, 0x0b, 0x00, 0x00, 0x13, 0x0c, 0x00, 0x00, + 0x93, 0x0c, 0x00, 0x00, 0x13, 0x0d, 0x00, 0x00, 0x93, 0x0d, 0x00, 0x00, 0x13, 0x0e, 0x00, 0x00, + 0x93, 0x0e, 0x00, 0x00, 0x13, 0x0f, 0x00, 0x00, 0x93, 0x0f, 0x00, 0x00, 0x97, 0x00, 0x00, 0x00, + 0x93, 0x80, 0x40, 0xf0, 0x73, 0x90, 0x50, 0x30, 0x93, 0x00, 0x00, 0x00, 0x17, 0x41, 0x10, 0x00, + 0x13, 0x01, 0x41, 0xcf, 0x33, 0x04, 0x01, 0x00, 0x17, 0x0d, 0x10, 0x00, 0x13, 0x0d, 0x8d, 0xee, + 0x97, 0x4d, 0x10, 0x00, 0x93, 0x8d, 0x0d, 0xce, 0x63, 0x57, 0xbd, 0x01, 0x23, 0x20, 0x0d, 0x00, + 0x11, 0x0d, 0xe3, 0x4d, 0xbd, 0xff, 0xef, 0x00, 0xf0, 0x60, 0x73, 0x00, 0x50, 0x10, 0xf5, 0xbf, + 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa6, 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0x07, 0xf4, + 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0x07, 0xf2, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0x07, 0xf2, + 0xb7, 0x37, 0x20, 0x00, 0x23, 0x88, 0x07, 0xf2, 0x82, 0x80, 0x18, 0x41, 0xfd, 0x57, 0x63, 0x02, + 0xf7, 0x06, 0x13, 0x07, 0x45, 0x00, 0x81, 0x47, 0x13, 0x06, 0xf0, 0x07, 0x14, 0x43, 0x81, 0xea, + 0x85, 0x07, 0x11, 0x07, 0xe3, 0x9c, 0xc7, 0xfe, 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x01, 0x47, + 0x93, 0x05, 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, 0x05, 0x8a, 0x19, 0xca, 0x93, 0x05, 0x00, 0x02, + 0x33, 0xd6, 0xe6, 0x00, 0x05, 0x8a, 0x15, 0xc6, 0x05, 0x07, 0xe3, 0x1b, 0xb7, 0xfe, 0x21, 0xa0, + 0x05, 0x07, 0xe3, 0x11, 0xb7, 0xfe, 0x89, 0x07, 0x93, 0x06, 0x00, 0x08, 0x7d, 0x56, 0xe3, 0x85, + 0xd7, 0xfc, 0x85, 0x07, 0x13, 0x97, 0x27, 0x00, 0x2a, 0x97, 0x03, 0x27, 0xc7, 0xff, 0xe3, 0x08, + 0xc7, 0xfe, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x05, 0x67, 0xaa, 0x87, 0x01, 0x17, 0x01, 0x45, + 0x94, 0x43, 0x99, 0xe6, 0x13, 0x05, 0x05, 0x02, 0x91, 0x07, 0xe3, 0x1b, 0xe5, 0xfe, 0x82, 0x80, + 0x81, 0x47, 0x13, 0x06, 0x00, 0x02, 0x33, 0xd7, 0xf6, 0x00, 0x05, 0x8b, 0x09, 0xe7, 0x85, 0x07, + 0x05, 0x05, 0xe3, 0x9a, 0xc7, 0xfe, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x14, 0x20, 0x00, + 0x13, 0x04, 0x04, 0x00, 0x83, 0x46, 0x94, 0x07, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, + 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, 0x64, 0x13, 0x06, 0x06, 0x3d, 0x93, 0x85, 0xc5, 0x3d, + 0x06, 0xc6, 0xef, 0x10, 0x30, 0x4c, 0x03, 0x45, 0x94, 0x07, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, + 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x40, 0x90, 0x0b, 0xef, 0x20, 0xc0, 0x58, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x00, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x40, 0x50, 0x0c, 0xb2, 0x40, + 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x05, 0x05, 0x10, 0x2a, 0x84, 0x37, 0x55, + 0x10, 0x00, 0x13, 0x05, 0x45, 0x3e, 0x06, 0xc6, 0xef, 0x10, 0x30, 0x4f, 0x37, 0x37, 0x20, 0x00, + 0x13, 0x07, 0x47, 0xf5, 0x14, 0x43, 0x85, 0x47, 0xb3, 0x97, 0x87, 0x00, 0xb2, 0x40, 0x22, 0x44, + 0x93, 0xc7, 0xf7, 0xff, 0xf5, 0x8f, 0x1c, 0xc3, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, + 0x26, 0xc2, 0x06, 0xc6, 0x2a, 0x84, 0x93, 0x04, 0xa0, 0x0a, 0xef, 0x20, 0x10, 0x76, 0x63, 0x19, + 0x95, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, + 0x22, 0x85, 0xef, 0x20, 0x90, 0x78, 0x22, 0x85, 0xef, 0x20, 0x30, 0x74, 0xe3, 0x03, 0x95, 0xfe, + 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, 0x3e, 0x85, 0x45, 0xef, 0x10, 0x10, 0x49, 0x13, 0x05, + 0x50, 0x05, 0xd1, 0xbf, 0x01, 0x11, 0x22, 0xcc, 0x2a, 0x84, 0x37, 0x35, 0x00, 0x08, 0x06, 0xce, + 0x2e, 0xc6, 0xef, 0x30, 0x10, 0x0a, 0x32, 0x46, 0xa2, 0x85, 0x37, 0x35, 0x00, 0x08, 0xef, 0x30, + 0x50, 0x0e, 0x62, 0x44, 0xf2, 0x40, 0x37, 0x35, 0x00, 0x08, 0x05, 0x61, 0x6f, 0x30, 0xb0, 0x0b, + 0x6d, 0x71, 0x23, 0x24, 0x81, 0x10, 0x2a, 0x84, 0x0a, 0x85, 0x23, 0x26, 0x11, 0x10, 0xef, 0x10, + 0x50, 0x63, 0x0a, 0x85, 0x23, 0x00, 0x81, 0x00, 0xef, 0x20, 0xc0, 0x3e, 0x83, 0x20, 0xc1, 0x10, + 0x03, 0x24, 0x81, 0x10, 0x51, 0x61, 0x82, 0x80, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0x2e, 0xc4, + 0xef, 0x20, 0xd0, 0x1a, 0xa2, 0x45, 0x32, 0x45, 0xef, 0x20, 0xd0, 0x32, 0x2a, 0xc4, 0xef, 0x20, + 0x90, 0x1b, 0xf2, 0x40, 0x22, 0x45, 0x05, 0x61, 0x82, 0x80, 0x13, 0x01, 0x01, 0xde, 0x23, 0x2c, + 0x81, 0x20, 0x2e, 0x84, 0xaa, 0x05, 0x23, 0x28, 0x21, 0x21, 0x93, 0x85, 0x05, 0x20, 0x2a, 0x89, + 0x08, 0x08, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x2a, 0x91, 0x20, 0x7d, 0x3f, 0x93, 0x07, 0xa0, 0x0a, + 0x63, 0x12, 0xf5, 0x04, 0xaa, 0x84, 0x08, 0x08, 0xcd, 0x33, 0x63, 0x00, 0x95, 0x02, 0x22, 0x85, + 0xd1, 0x3d, 0x09, 0x45, 0x83, 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, 0x41, 0x21, + 0x03, 0x29, 0x01, 0x21, 0x13, 0x01, 0x01, 0x22, 0x82, 0x80, 0x42, 0x44, 0x48, 0x08, 0x22, 0xc6, + 0x25, 0x35, 0x09, 0x8c, 0x11, 0x46, 0x6c, 0x00, 0x4a, 0x85, 0x22, 0xc6, 0xef, 0x40, 0x70, 0x7c, + 0x05, 0x45, 0xc9, 0xbf, 0x01, 0x45, 0xf9, 0xb7, 0x41, 0x11, 0x4a, 0xc0, 0x03, 0xa9, 0x05, 0x00, + 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0x2e, 0x84, 0xaa, 0x84, 0xef, 0x20, 0x10, 0x67, 0xca, 0x85, + 0x26, 0x85, 0xef, 0x20, 0x70, 0x1e, 0xa6, 0x85, 0x22, 0x85, 0xef, 0x20, 0xb0, 0x28, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x02, 0x1c, 0x40, 0x63, 0x93, 0x27, 0x03, 0x93, 0x07, 0x44, 0x00, + 0x7d, 0x57, 0x13, 0x04, 0x04, 0x20, 0x94, 0x43, 0x63, 0x9b, 0xe6, 0x00, 0x91, 0x07, 0xe3, 0x9c, + 0x87, 0xfe, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, + 0x50, 0x05, 0xc5, 0xbf, 0x13, 0x01, 0x01, 0xde, 0x23, 0x26, 0x31, 0x21, 0x93, 0x19, 0xa5, 0x00, + 0x23, 0x2a, 0x91, 0x20, 0x93, 0x84, 0x09, 0x20, 0x23, 0x2c, 0x81, 0x20, 0xa6, 0x85, 0x2a, 0x84, + 0x0a, 0x85, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x28, 0x21, 0x21, 0xfd, 0x35, 0x93, 0x07, 0xa0, 0x0a, + 0x63, 0x00, 0xf5, 0x02, 0x01, 0x45, 0x83, 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, + 0x41, 0x21, 0x03, 0x29, 0x01, 0x21, 0x83, 0x29, 0xc1, 0x20, 0x13, 0x01, 0x01, 0x22, 0x82, 0x80, + 0x2a, 0x89, 0x0a, 0x85, 0xdd, 0x39, 0x63, 0x06, 0x25, 0x01, 0x22, 0x85, 0xe5, 0x33, 0x09, 0x45, + 0xd9, 0xbf, 0x02, 0x44, 0x48, 0x00, 0x89, 0x3b, 0xaa, 0x87, 0x33, 0x06, 0xa4, 0x40, 0x0d, 0x45, + 0xe3, 0x03, 0xf4, 0xfc, 0x09, 0x45, 0xe3, 0x60, 0xc4, 0xfc, 0x5c, 0x00, 0x01, 0x44, 0x13, 0x08, + 0x00, 0x02, 0x13, 0x05, 0xf0, 0x07, 0x8c, 0x43, 0x89, 0xc9, 0x81, 0x46, 0x33, 0xd7, 0xd5, 0x00, + 0x05, 0x8b, 0x05, 0xeb, 0x85, 0x06, 0xe3, 0x9b, 0x06, 0xff, 0x05, 0x04, 0x91, 0x07, 0xe3, 0x14, + 0xa4, 0xfe, 0x7d, 0x16, 0x8a, 0x85, 0x13, 0x85, 0x09, 0x40, 0x32, 0xc0, 0xf5, 0x3d, 0x93, 0x07, + 0xa0, 0x0a, 0xe3, 0x11, 0xf5, 0xf8, 0x8a, 0x85, 0x26, 0x85, 0xfd, 0x35, 0x13, 0x05, 0x65, 0xf5, + 0x1d, 0xa8, 0x05, 0x47, 0x33, 0x17, 0xd7, 0x00, 0x13, 0x47, 0xf7, 0xff, 0x6d, 0x8f, 0x98, 0xc3, + 0xef, 0x20, 0xc0, 0x7f, 0x18, 0x04, 0x93, 0x17, 0x24, 0x00, 0xba, 0x97, 0x83, 0xa5, 0x47, 0xe0, + 0x13, 0x05, 0x14, 0x00, 0x0a, 0x05, 0x26, 0x95, 0xef, 0x20, 0x50, 0x10, 0x2a, 0x84, 0xef, 0x20, + 0x80, 0x7f, 0x13, 0x05, 0x64, 0xf5, 0x13, 0x35, 0x15, 0x00, 0x35, 0xbf, 0x41, 0x11, 0x22, 0xc4, + 0x06, 0xc6, 0x93, 0x07, 0x30, 0x0c, 0x2a, 0x84, 0x63, 0x04, 0xf5, 0x00, 0xef, 0x20, 0xc0, 0x4b, + 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x05, 0x67, 0x23, 0x80, 0x87, 0x00, 0xba, 0x97, + 0xf8, 0x5b, 0x19, 0xe3, 0x05, 0x47, 0xf8, 0xdb, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, + 0x05, 0x66, 0x37, 0x05, 0x20, 0x00, 0x41, 0x11, 0x13, 0x06, 0xc6, 0x07, 0x81, 0x45, 0x13, 0x05, + 0x05, 0x00, 0x06, 0xc6, 0xef, 0x40, 0xb0, 0x65, 0xef, 0x20, 0x80, 0x41, 0xef, 0x40, 0x80, 0x39, + 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x20, 0x00, 0x38, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x20, 0x00, 0x55, + 0xef, 0x20, 0x90, 0x7f, 0xef, 0x40, 0xa0, 0x0c, 0xef, 0x40, 0x00, 0x65, 0xb2, 0x40, 0x41, 0x01, + 0x6f, 0x30, 0xe0, 0x15, 0x69, 0x71, 0x08, 0x08, 0x23, 0x22, 0x91, 0x12, 0x23, 0x20, 0x21, 0x13, + 0x23, 0x2c, 0x41, 0x11, 0x23, 0x26, 0x11, 0x12, 0x23, 0x24, 0x81, 0x12, 0x23, 0x2e, 0x31, 0x11, + 0x23, 0x2a, 0x51, 0x11, 0xef, 0x10, 0xf0, 0x39, 0x91, 0x47, 0x37, 0x39, 0x20, 0x00, 0x23, 0x08, + 0xf1, 0x00, 0x83, 0x27, 0xc9, 0xf4, 0x37, 0x1a, 0x20, 0x00, 0xb7, 0x34, 0x20, 0x00, 0x13, 0x09, + 0xc9, 0xf4, 0x13, 0x0a, 0x0a, 0x00, 0x93, 0x84, 0x84, 0xf4, 0xc5, 0xe7, 0x83, 0x27, 0x4a, 0x07, + 0x09, 0x46, 0x6c, 0x00, 0x23, 0x20, 0xf9, 0x00, 0x13, 0x05, 0x21, 0x01, 0xc1, 0x17, 0x3e, 0xc6, + 0x23, 0xa0, 0x04, 0x00, 0xef, 0x40, 0xf0, 0x58, 0x89, 0x47, 0xa3, 0x08, 0xf1, 0x00, 0x13, 0x04, + 0xe0, 0x07, 0x93, 0x09, 0x41, 0x01, 0x03, 0x27, 0x09, 0x00, 0x94, 0x40, 0xb3, 0x07, 0xd7, 0x40, + 0x63, 0xf3, 0x87, 0x00, 0x3e, 0x84, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x5a, 0x10, 0x00, 0x37, 0x55, + 0x10, 0x00, 0xa2, 0x87, 0x93, 0x85, 0xca, 0x3f, 0x13, 0x06, 0xc6, 0x3e, 0x13, 0x05, 0x45, 0x40, + 0xef, 0x10, 0x50, 0x0c, 0x8c, 0x40, 0x83, 0x27, 0x4a, 0x07, 0x33, 0x07, 0xb4, 0x00, 0x63, 0xf7, + 0xe7, 0x04, 0x8d, 0x45, 0x13, 0x85, 0xca, 0x3f, 0xef, 0x10, 0x30, 0x12, 0x13, 0x04, 0x50, 0x05, + 0xc5, 0x3c, 0xef, 0x40, 0x60, 0x2a, 0xef, 0x20, 0xa0, 0x32, 0xef, 0x20, 0xa0, 0x29, 0x29, 0x3f, + 0x83, 0x20, 0xc1, 0x12, 0x22, 0x85, 0x03, 0x24, 0x81, 0x12, 0x83, 0x24, 0x41, 0x12, 0x03, 0x29, + 0x01, 0x12, 0x83, 0x29, 0xc1, 0x11, 0x03, 0x2a, 0x81, 0x11, 0x83, 0x2a, 0x41, 0x11, 0x55, 0x61, + 0x82, 0x80, 0x13, 0x04, 0x00, 0x08, 0x93, 0x09, 0x21, 0x01, 0xb5, 0xbf, 0xb7, 0x07, 0x20, 0x00, + 0x93, 0x87, 0x07, 0x00, 0x22, 0x86, 0xbe, 0x95, 0x4e, 0x85, 0xef, 0x40, 0x90, 0x4e, 0x83, 0x47, + 0x11, 0x01, 0x98, 0x40, 0x22, 0x97, 0x3e, 0x94, 0x83, 0x27, 0x09, 0x00, 0xa3, 0x08, 0x81, 0x00, + 0x98, 0xc0, 0x13, 0x04, 0x50, 0x05, 0x63, 0x17, 0xf7, 0x00, 0x89, 0x47, 0x23, 0x08, 0xf1, 0x00, + 0x13, 0x04, 0xa0, 0x0a, 0x08, 0x08, 0xef, 0x20, 0xe0, 0x04, 0x59, 0xbf, 0x41, 0x11, 0xb7, 0x37, + 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x06, 0xc6, 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x20, 0xe0, 0x26, + 0x85, 0x3d, 0xb9, 0x3c, 0xef, 0x30, 0x20, 0x07, 0x41, 0x3d, 0xb2, 0x40, 0x1d, 0x65, 0x13, 0x05, + 0x05, 0x6c, 0x41, 0x01, 0x6f, 0x30, 0x00, 0x0f, 0x41, 0x11, 0x26, 0xc2, 0xae, 0x84, 0xb6, 0x85, + 0x06, 0xc6, 0x22, 0xc4, 0x4a, 0xc0, 0x36, 0x84, 0x32, 0x89, 0xef, 0x40, 0x40, 0x4f, 0x22, 0x86, + 0xca, 0x85, 0x13, 0x05, 0x00, 0x02, 0xef, 0x40, 0x00, 0x58, 0xef, 0x40, 0x60, 0x4c, 0xef, 0x40, + 0xe0, 0x67, 0x93, 0x07, 0xa0, 0x0a, 0x13, 0x04, 0x50, 0x05, 0x63, 0x1a, 0xf5, 0x00, 0x2a, 0x84, + 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0x00, 0x02, 0x26, 0x85, 0xef, 0x40, 0xe0, 0x50, 0xb2, 0x40, + 0x22, 0x85, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x85, 0x67, 0xc1, 0x07, + 0x63, 0xee, 0xb7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xae, 0x84, 0x37, 0x04, + 0x20, 0x00, 0x19, 0xc5, 0x2e, 0x86, 0xaa, 0x85, 0x13, 0x05, 0x04, 0x00, 0xef, 0x40, 0xd0, 0x42, + 0x13, 0x04, 0x04, 0x00, 0x93, 0x07, 0x30, 0xfc, 0x23, 0x00, 0xf4, 0x00, 0x85, 0x67, 0x3e, 0x94, + 0x64, 0xd8, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x82, 0x80, 0x13, 0x01, + 0x01, 0xdd, 0x23, 0x24, 0x81, 0x22, 0x23, 0x22, 0x91, 0x22, 0x23, 0x20, 0x21, 0x23, 0x23, 0x2e, + 0x31, 0x21, 0x23, 0x2c, 0x41, 0x21, 0x23, 0x2a, 0x51, 0x21, 0x23, 0x28, 0x61, 0x21, 0x23, 0x26, + 0x71, 0x21, 0x23, 0x24, 0x81, 0x21, 0x23, 0x26, 0x11, 0x22, 0x13, 0x04, 0x00, 0x20, 0x01, 0x49, + 0x93, 0x04, 0xa0, 0x0a, 0x37, 0x3a, 0x20, 0x00, 0x85, 0x4a, 0x37, 0x5b, 0x10, 0x00, 0xb7, 0x5b, + 0x10, 0x00, 0x37, 0x5c, 0x10, 0x00, 0xc1, 0x49, 0xa2, 0x85, 0x0a, 0x85, 0xb1, 0x3e, 0x63, 0x16, + 0x95, 0x02, 0x0a, 0x85, 0x59, 0x32, 0x63, 0x1e, 0x95, 0x04, 0x13, 0x07, 0x4a, 0xf5, 0x14, 0x43, + 0xb3, 0x97, 0x2a, 0x01, 0x13, 0x06, 0x8b, 0x40, 0xd5, 0x8f, 0x93, 0x85, 0x4b, 0x3e, 0xca, 0x86, + 0x13, 0x05, 0x4c, 0x64, 0x1c, 0xc3, 0xef, 0x10, 0xe0, 0x6e, 0x05, 0x09, 0x13, 0x04, 0x04, 0x40, + 0xe3, 0x14, 0x39, 0xfd, 0x83, 0x20, 0xc1, 0x22, 0x03, 0x24, 0x81, 0x22, 0x83, 0x24, 0x41, 0x22, + 0x03, 0x29, 0x01, 0x22, 0x83, 0x29, 0xc1, 0x21, 0x03, 0x2a, 0x81, 0x21, 0x83, 0x2a, 0x41, 0x21, + 0x03, 0x2b, 0x01, 0x21, 0x83, 0x2b, 0xc1, 0x20, 0x03, 0x2c, 0x81, 0x20, 0x13, 0x01, 0x01, 0x23, + 0x82, 0x80, 0x93, 0x05, 0x04, 0x20, 0x0a, 0x85, 0xc5, 0x3c, 0xe3, 0x10, 0x95, 0xfc, 0x0a, 0x85, + 0xef, 0xf0, 0xbf, 0x91, 0xe3, 0x1b, 0x95, 0xfa, 0x22, 0x85, 0xef, 0x20, 0x10, 0x1f, 0x8a, 0x85, + 0x22, 0x85, 0xef, 0x20, 0x70, 0x06, 0xa2, 0x85, 0x0a, 0x85, 0xf9, 0x34, 0xe3, 0x1f, 0x95, 0xf8, + 0x0a, 0x85, 0xef, 0xf0, 0x9f, 0x8f, 0xe3, 0x0a, 0x95, 0xf6, 0x41, 0xbf, 0xb7, 0x05, 0x00, 0x80, + 0x37, 0x55, 0x10, 0x00, 0x86, 0x87, 0x6d, 0x71, 0xbe, 0x95, 0x13, 0x05, 0x45, 0x41, 0x23, 0x26, + 0x11, 0x10, 0xef, 0x10, 0x80, 0x6d, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x87, 0xf2, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x1e, 0xf7, 0x02, 0x37, 0x15, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x9a, 0xef, 0x10, + 0xf0, 0x5f, 0x13, 0x05, 0xc0, 0x0f, 0xef, 0x10, 0xa0, 0x5a, 0x0a, 0x85, 0xef, 0x10, 0x70, 0x09, + 0x93, 0x07, 0xf0, 0x07, 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x00, 0x23, 0x00, 0xf1, 0x00, + 0xef, 0x10, 0x00, 0x54, 0xa3, 0x00, 0xa1, 0x00, 0x0a, 0x85, 0xef, 0x10, 0x70, 0x60, 0x05, 0x45, + 0xef, 0x40, 0x00, 0x67, 0xef, 0x40, 0x00, 0x66, 0xd5, 0x33, 0xef, 0x10, 0x50, 0x2d, 0xf5, 0xbf, + 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0x40, 0x60, 0x4c, 0x93, 0x07, 0x00, 0x08, 0x63, 0xf3, + 0xa7, 0x00, 0xad, 0x3f, 0x2a, 0x84, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0x50, 0x7e, 0xb7, 0x17, + 0x20, 0x00, 0xb2, 0x40, 0x23, 0xaa, 0x87, 0x06, 0x22, 0x44, 0x13, 0x05, 0x30, 0x0c, 0x41, 0x01, + 0x82, 0x80, 0x93, 0x07, 0xf0, 0x17, 0x63, 0xf5, 0xa7, 0x00, 0x41, 0x11, 0x06, 0xc6, 0xb9, 0x37, + 0x6f, 0x10, 0xb0, 0x3e, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x4a, 0xc0, 0x2e, 0x84, 0x06, 0xc6, + 0xaa, 0x84, 0xc5, 0x37, 0x61, 0x8d, 0x13, 0x09, 0x50, 0x05, 0x19, 0xc1, 0x13, 0x09, 0xa0, 0x0a, + 0x26, 0x85, 0xc1, 0x3f, 0x69, 0x8c, 0x13, 0x05, 0xa0, 0x0a, 0x19, 0xe0, 0x13, 0x05, 0x50, 0x05, + 0x63, 0x03, 0x25, 0x01, 0x21, 0x3f, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, + 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x8d, 0x47, 0x63, 0xf3, 0xa7, 0x00, 0x01, 0x37, 0x89, 0x67, + 0x93, 0x87, 0x07, 0xbf, 0x0a, 0x05, 0x3e, 0x95, 0xef, 0x30, 0xe0, 0x02, 0xaa, 0x87, 0x13, 0x07, + 0xf0, 0x0f, 0x55, 0x45, 0x63, 0x89, 0xe7, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x59, 0x45, 0x63, 0x94, + 0xe7, 0x00, 0x13, 0x05, 0x30, 0x0c, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x21, 0x71, 0x23, 0x2c, + 0x81, 0x1a, 0x2a, 0x84, 0x08, 0x09, 0x23, 0x2e, 0x11, 0x1a, 0x23, 0x2a, 0x91, 0x1a, 0x23, 0x28, + 0x21, 0x1b, 0x23, 0x26, 0x31, 0x1b, 0x23, 0x24, 0x41, 0x1b, 0x23, 0x22, 0x51, 0x1b, 0x23, 0x20, + 0x61, 0x1b, 0x23, 0x2e, 0x71, 0x19, 0x23, 0x2c, 0x81, 0x19, 0x23, 0x2a, 0x91, 0x19, 0xef, 0x10, + 0x40, 0x77, 0x83, 0x47, 0x04, 0x00, 0x05, 0x47, 0x23, 0x18, 0xe1, 0x08, 0xc1, 0x46, 0x63, 0x80, + 0xd7, 0x46, 0x63, 0xee, 0xf6, 0x02, 0x91, 0x46, 0x63, 0x88, 0xd7, 0x34, 0x63, 0xe1, 0xf6, 0x02, + 0x63, 0x86, 0xe7, 0x06, 0x09, 0x47, 0x63, 0x81, 0xe7, 0x0e, 0x93, 0x07, 0xe0, 0x07, 0x23, 0x08, + 0xf1, 0x08, 0x08, 0x09, 0xef, 0x10, 0xd0, 0x4c, 0x93, 0x07, 0x50, 0x05, 0x99, 0xa1, 0x21, 0x47, + 0xe3, 0x95, 0xe7, 0xfe, 0x83, 0x47, 0x14, 0x00, 0xd1, 0xeb, 0x4d, 0x31, 0x39, 0xa9, 0x93, 0x06, + 0x20, 0x0a, 0x63, 0x85, 0xd7, 0x4c, 0x93, 0x06, 0x30, 0x0b, 0x63, 0x82, 0xd7, 0x46, 0x93, 0x06, + 0x00, 0x02, 0xe3, 0x94, 0xd7, 0xfc, 0x83, 0x47, 0x14, 0x00, 0x63, 0x99, 0xe7, 0x06, 0x03, 0x47, + 0x24, 0x00, 0x95, 0x47, 0x63, 0x14, 0xf7, 0x06, 0x85, 0x45, 0x61, 0x45, 0xe1, 0x3d, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x09, 0xf5, 0x42, 0x13, 0x04, 0x80, 0xf8, 0x7d, 0xa0, 0x03, 0x47, 0x14, 0x00, + 0x89, 0x47, 0x63, 0x15, 0xf7, 0x04, 0x83, 0x47, 0x24, 0x00, 0x63, 0x8a, 0xe7, 0x04, 0x63, 0x6b, + 0xf7, 0x02, 0xa1, 0xe3, 0x83, 0x45, 0x34, 0x00, 0xf5, 0x47, 0x63, 0xe9, 0xb7, 0x02, 0x9e, 0x05, + 0x13, 0x06, 0x00, 0x08, 0x93, 0x85, 0x05, 0x10, 0x13, 0x05, 0x21, 0x09, 0xef, 0x20, 0x30, 0x6d, + 0x13, 0x04, 0x00, 0x08, 0x08, 0x09, 0xa3, 0x08, 0x81, 0x08, 0xef, 0x10, 0x70, 0x43, 0x93, 0x07, + 0xa0, 0x0a, 0x45, 0xae, 0x13, 0x05, 0x80, 0x1e, 0x63, 0x8d, 0xd7, 0x00, 0x13, 0x04, 0x10, 0xf8, + 0xa1, 0xa8, 0x89, 0x65, 0x13, 0x06, 0x00, 0x08, 0x93, 0x85, 0x05, 0x90, 0xf1, 0xb7, 0x13, 0x05, + 0x00, 0x1f, 0xef, 0x10, 0x90, 0x24, 0x2a, 0xc6, 0x11, 0x46, 0x6c, 0x00, 0x13, 0x05, 0x21, 0x09, + 0xef, 0x40, 0x30, 0x0a, 0x11, 0x44, 0x7d, 0xbf, 0x83, 0x44, 0x14, 0x00, 0xc5, 0x36, 0x93, 0x07, + 0x10, 0x02, 0xe3, 0x95, 0xf4, 0xfc, 0xef, 0x10, 0x10, 0x7d, 0xef, 0x20, 0x90, 0x27, 0xef, 0x30, + 0x90, 0x38, 0xef, 0x40, 0x60, 0x07, 0x03, 0x45, 0x24, 0x02, 0xa5, 0x35, 0x93, 0x07, 0x30, 0x0c, + 0x63, 0x0b, 0xf5, 0x02, 0x13, 0x04, 0x70, 0xf8, 0xb3, 0x06, 0x80, 0x40, 0x37, 0x56, 0x10, 0x00, + 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0xf6, 0xf6, 0x0f, 0x13, 0x06, 0x86, 0x42, + 0x93, 0x85, 0x45, 0x41, 0x13, 0x05, 0x45, 0x64, 0x23, 0x08, 0xd1, 0x08, 0xef, 0x10, 0x80, 0x3b, + 0xa3, 0x08, 0x01, 0x08, 0xf9, 0xb5, 0x83, 0x44, 0x24, 0x02, 0x19, 0x34, 0x8d, 0x47, 0xe3, 0xe3, + 0x97, 0xfc, 0x13, 0x06, 0x10, 0x08, 0x81, 0x45, 0x68, 0x00, 0xef, 0x40, 0x50, 0x06, 0x13, 0x06, + 0x00, 0x02, 0x93, 0x05, 0x24, 0x00, 0x13, 0x05, 0xd1, 0x00, 0x23, 0x06, 0x91, 0x00, 0xef, 0x40, + 0x50, 0x01, 0xef, 0x40, 0x60, 0x00, 0x37, 0x25, 0x00, 0x08, 0xef, 0x30, 0x80, 0x01, 0x81, 0x46, + 0x01, 0x46, 0x93, 0x05, 0xd1, 0x02, 0x45, 0x45, 0x85, 0x3e, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x13, + 0xf5, 0xf8, 0x81, 0x45, 0x68, 0x00, 0xef, 0x30, 0x50, 0x2f, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, + 0xe3, 0x1a, 0xf5, 0xf6, 0x93, 0x06, 0x00, 0x02, 0x13, 0x06, 0xd1, 0x00, 0x93, 0x05, 0xd1, 0x04, + 0x49, 0x45, 0x99, 0x36, 0xaa, 0x84, 0xe3, 0x1f, 0x25, 0xf5, 0x85, 0x45, 0x68, 0x00, 0xef, 0x30, + 0xd0, 0x2c, 0x2a, 0x89, 0xe3, 0x18, 0x95, 0xf4, 0x83, 0x47, 0xc1, 0x00, 0x85, 0x46, 0x13, 0x06, + 0xb1, 0x00, 0x93, 0x05, 0xd1, 0x04, 0x4d, 0x45, 0xa3, 0x05, 0xf1, 0x00, 0x31, 0x3e, 0xaa, 0x84, + 0xe3, 0x1a, 0x25, 0xf3, 0x89, 0x45, 0x68, 0x00, 0xef, 0x30, 0x30, 0x2a, 0x2a, 0x89, 0xe3, 0x13, + 0x95, 0xf2, 0x81, 0x46, 0x01, 0x46, 0x93, 0x05, 0xd1, 0x04, 0x51, 0x45, 0xf5, 0x3c, 0xaa, 0x84, + 0xe3, 0x1a, 0x25, 0xf1, 0x8d, 0x45, 0x68, 0x00, 0xef, 0x30, 0x30, 0x28, 0x2a, 0x89, 0xe3, 0x13, + 0x95, 0xf0, 0x91, 0x45, 0x68, 0x00, 0xef, 0x30, 0x50, 0x27, 0xaa, 0x84, 0xe3, 0x1c, 0x25, 0xef, + 0x95, 0x45, 0x68, 0x00, 0xef, 0x30, 0x70, 0x26, 0xe3, 0x16, 0x95, 0xee, 0xb7, 0x19, 0x20, 0x00, + 0x13, 0x85, 0x09, 0x02, 0xef, 0x30, 0x70, 0x29, 0xb7, 0x14, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, + 0x93, 0x05, 0xd1, 0x02, 0x13, 0x85, 0x04, 0x03, 0xef, 0x40, 0xa0, 0x73, 0x37, 0x15, 0x20, 0x00, + 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0xd1, 0x06, 0x13, 0x05, 0x05, 0x05, 0xef, 0x40, 0x60, 0x72, + 0x03, 0x49, 0x24, 0x02, 0x8d, 0x47, 0x4e, 0x84, 0x63, 0xf3, 0x27, 0x01, 0x01, 0x39, 0x37, 0x5c, + 0x10, 0x00, 0xef, 0x10, 0x10, 0x49, 0x81, 0x4c, 0x13, 0x0c, 0x8c, 0x58, 0x8d, 0x49, 0xfd, 0x5a, + 0x13, 0x0a, 0x00, 0x0f, 0x41, 0x6b, 0xb7, 0x0b, 0x00, 0x01, 0x03, 0x25, 0x0c, 0x00, 0x51, 0x81, + 0x49, 0x39, 0x03, 0x27, 0x0c, 0x00, 0x93, 0x57, 0x07, 0x01, 0xbd, 0x8b, 0x63, 0xe8, 0xf9, 0x00, + 0x8e, 0x07, 0xb3, 0x97, 0xfa, 0x00, 0x93, 0xc7, 0xf7, 0xff, 0x7d, 0x8d, 0x83, 0x46, 0x1c, 0x00, + 0x33, 0x55, 0x25, 0x01, 0x93, 0x77, 0x15, 0x00, 0x93, 0xf6, 0x06, 0x0f, 0x63, 0x96, 0x46, 0x07, + 0x99, 0xc3, 0x93, 0x07, 0xf0, 0x0f, 0xbd, 0x65, 0xf9, 0x8d, 0x21, 0x83, 0x3d, 0x8b, 0x22, 0x07, + 0x4d, 0x8f, 0x83, 0x45, 0x0c, 0x00, 0xc2, 0x07, 0x66, 0x85, 0xd9, 0x8d, 0xdd, 0x8d, 0xef, 0x10, + 0xd0, 0x43, 0x83, 0x47, 0x4c, 0x00, 0x11, 0x0c, 0x85, 0x0c, 0xc5, 0xf3, 0xef, 0x10, 0x90, 0x40, + 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x04, 0x03, + 0x13, 0x05, 0x21, 0x09, 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x40, 0xa0, 0x67, 0x93, 0x05, 0x04, 0x02, + 0x41, 0x46, 0x13, 0x05, 0x21, 0x0b, 0xef, 0x40, 0xc0, 0x66, 0xef, 0x30, 0xf0, 0x6b, 0x13, 0x04, + 0x00, 0x03, 0xef, 0xf0, 0x7f, 0x85, 0xbd, 0xbb, 0x93, 0x76, 0x05, 0x10, 0x99, 0xc2, 0x93, 0xe7, + 0x27, 0x00, 0xb3, 0x76, 0x65, 0x01, 0x99, 0xc2, 0x93, 0xe7, 0x47, 0x00, 0x33, 0x75, 0x75, 0x01, + 0x59, 0xd1, 0x93, 0xe7, 0x87, 0x00, 0x41, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0xc7, 0xf3, + 0x93, 0x07, 0xa0, 0x0a, 0x83, 0x44, 0x14, 0x00, 0x63, 0x14, 0xf7, 0x0e, 0x91, 0xe4, 0x13, 0x04, + 0x10, 0xf8, 0xef, 0xf0, 0xbf, 0x96, 0x4d, 0xbb, 0xb7, 0x39, 0x20, 0x00, 0x83, 0xa7, 0x89, 0xf3, + 0x93, 0x89, 0x89, 0xf3, 0xad, 0xcb, 0x09, 0x04, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x49, 0xf3, + 0x83, 0x26, 0x09, 0x00, 0x03, 0xa7, 0x09, 0x00, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, + 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, 0x64, 0xa6, 0x96, 0x13, 0x06, 0xc6, 0x41, 0x93, 0x85, + 0xc5, 0x3f, 0xef, 0x10, 0x20, 0x15, 0x03, 0x25, 0x09, 0x00, 0x83, 0xa7, 0x09, 0x00, 0x33, 0x87, + 0xa4, 0x00, 0xe3, 0xe6, 0xe7, 0xfa, 0x85, 0x67, 0x93, 0x87, 0x07, 0x02, 0xe3, 0xe1, 0xe7, 0xfa, + 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x26, 0x86, 0x3e, 0x95, 0xa2, 0x85, 0xef, 0x40, + 0x40, 0x5b, 0x83, 0x27, 0x09, 0x00, 0xbe, 0x94, 0x83, 0xa7, 0x09, 0x00, 0x23, 0x20, 0x99, 0x00, + 0xbd, 0xe3, 0x75, 0x54, 0x15, 0xbb, 0x89, 0x47, 0xe3, 0xfb, 0x97, 0xf6, 0x03, 0x49, 0x34, 0x00, + 0x83, 0x47, 0x24, 0x00, 0xf9, 0x14, 0x22, 0x09, 0x3e, 0x99, 0x85, 0x67, 0x93, 0x06, 0xf9, 0xff, + 0x13, 0x87, 0xf7, 0x00, 0x11, 0x04, 0xe3, 0x6c, 0xd7, 0xf4, 0x37, 0x0a, 0x20, 0x00, 0x13, 0x0a, + 0x0a, 0x00, 0x3e, 0x9a, 0x41, 0x09, 0x93, 0x07, 0xf0, 0x07, 0xa3, 0x0c, 0xfa, 0x06, 0x23, 0xa0, + 0x29, 0x01, 0xef, 0x10, 0x50, 0x4a, 0xef, 0x20, 0xc0, 0x74, 0xef, 0x30, 0xd0, 0x05, 0xb7, 0x37, + 0x20, 0x00, 0x23, 0x28, 0x2a, 0x07, 0x23, 0x2a, 0x0a, 0x06, 0x23, 0xaa, 0x07, 0xf2, 0x2d, 0xbf, + 0x13, 0x04, 0x60, 0xf8, 0x39, 0xbf, 0xe3, 0x9e, 0xf4, 0xf8, 0x01, 0x44, 0xa1, 0xb9, 0x83, 0x47, + 0x14, 0x00, 0xe3, 0x95, 0x07, 0xc6, 0xef, 0x10, 0x30, 0x15, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x0f, + 0x05, 0xc4, 0x83, 0x20, 0xc1, 0x1b, 0x03, 0x24, 0x81, 0x1b, 0x83, 0x24, 0x41, 0x1b, 0x03, 0x29, + 0x01, 0x1b, 0x83, 0x29, 0xc1, 0x1a, 0x03, 0x2a, 0x81, 0x1a, 0x83, 0x2a, 0x41, 0x1a, 0x03, 0x2b, + 0x01, 0x1a, 0x83, 0x2b, 0xc1, 0x19, 0x03, 0x2c, 0x81, 0x19, 0x83, 0x2c, 0x41, 0x19, 0x3e, 0x85, + 0x39, 0x61, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa2, 0xa7, 0xf4, 0x7d, 0xb7, 0x83, 0x46, + 0x14, 0x00, 0xe3, 0x9d, 0xe6, 0xc0, 0x83, 0x47, 0x24, 0x00, 0x63, 0x8a, 0xd7, 0x02, 0x0d, 0x47, + 0xe3, 0x96, 0xe7, 0xc0, 0xa1, 0x45, 0x01, 0x45, 0xb5, 0x3c, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, + 0xe3, 0x13, 0xf5, 0xba, 0xb7, 0xb5, 0xb5, 0x61, 0x93, 0x85, 0x55, 0x49, 0x13, 0x05, 0x80, 0x1f, + 0xef, 0x10, 0x40, 0x6b, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa6, 0x87, 0xf2, 0xbd, 0xb7, 0xb7, 0x15, + 0x78, 0x4a, 0x93, 0x85, 0x95, 0x21, 0x13, 0x05, 0x80, 0x1f, 0xef, 0x10, 0xa0, 0x69, 0xb7, 0x37, + 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf2, 0x81, 0xbf, 0xb7, 0x37, 0x20, 0x00, + 0x03, 0xa7, 0x87, 0xf2, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1f, 0xf7, 0xb4, 0x83, 0x47, 0x14, 0x00, + 0xe3, 0x96, 0x07, 0xba, 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x09, 0xef, 0x00, 0x50, 0x6f, + 0x2a, 0x84, 0xe3, 0x51, 0x05, 0xb8, 0xcd, 0xbe, 0x41, 0x11, 0x05, 0x45, 0x06, 0xc6, 0xef, 0x40, + 0x20, 0x02, 0xb2, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa0, 0xe7, 0xf4, + 0x41, 0x01, 0x82, 0x80, 0x31, 0x71, 0x22, 0xdd, 0x37, 0x34, 0x20, 0x00, 0x93, 0x07, 0x50, 0x05, + 0x06, 0xdf, 0x4a, 0xd9, 0x52, 0xd5, 0x56, 0xd3, 0x62, 0xcd, 0x26, 0xdb, 0x4e, 0xd7, 0x5a, 0xd1, + 0x5e, 0xcf, 0x66, 0xcb, 0x6a, 0xc9, 0x6e, 0xc7, 0xb7, 0x3a, 0x20, 0x00, 0x37, 0x3a, 0x20, 0x00, + 0x37, 0x39, 0x20, 0x00, 0x13, 0x04, 0x84, 0xf2, 0x23, 0xa0, 0xfa, 0xf4, 0x23, 0x26, 0xfa, 0xf2, + 0x23, 0x22, 0xf9, 0xf4, 0x1c, 0xc0, 0xef, 0x10, 0x60, 0x3d, 0xef, 0x10, 0xc0, 0x55, 0x13, 0x87, + 0x0a, 0xf4, 0x3a, 0xc8, 0x13, 0x07, 0xca, 0xf2, 0x3a, 0xca, 0x13, 0x07, 0x49, 0xf4, 0x93, 0x07, + 0xa0, 0x0a, 0x3a, 0xc6, 0x37, 0x5c, 0x10, 0x00, 0x85, 0x45, 0x63, 0x0a, 0xf5, 0x00, 0x13, 0x05, + 0x4c, 0x41, 0xef, 0x00, 0x90, 0x7b, 0xef, 0x10, 0x80, 0x4f, 0xef, 0xf0, 0x3f, 0x8c, 0x41, 0x45, + 0xef, 0xf0, 0x5f, 0x97, 0x08, 0xc0, 0xb7, 0x07, 0x01, 0x02, 0x80, 0x57, 0x98, 0x5b, 0x29, 0x45, + 0x59, 0x8c, 0x98, 0x5f, 0x59, 0x8c, 0x13, 0x77, 0xf4, 0x87, 0x98, 0xd7, 0x98, 0xdb, 0x98, 0xdf, + 0xd8, 0x43, 0x13, 0x67, 0x87, 0x00, 0xd8, 0xc3, 0xef, 0x10, 0x00, 0x38, 0xef, 0x30, 0x30, 0x22, + 0x13, 0x75, 0x05, 0x78, 0x11, 0xc5, 0x13, 0x05, 0x00, 0x78, 0x81, 0x45, 0xef, 0x30, 0x90, 0x1a, + 0xb7, 0x07, 0x01, 0x02, 0x80, 0xd7, 0x80, 0xdb, 0x37, 0x15, 0x10, 0x00, 0x80, 0xdf, 0x13, 0x05, + 0xc5, 0x9a, 0xef, 0x10, 0xa0, 0x69, 0x37, 0x56, 0x10, 0x00, 0x37, 0x59, 0x10, 0x00, 0x81, 0x47, + 0x01, 0x47, 0x85, 0x46, 0x13, 0x06, 0x06, 0x43, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, 0x64, + 0xef, 0x00, 0x50, 0x6c, 0xef, 0x30, 0x50, 0x1e, 0x93, 0x07, 0x50, 0x05, 0x63, 0x1e, 0xf5, 0x00, + 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x46, 0x44, 0x93, 0x05, 0x4c, 0x41, + 0x13, 0x05, 0x45, 0x40, 0xef, 0x00, 0x10, 0x6a, 0xef, 0x20, 0xa0, 0x2f, 0x51, 0x45, 0xef, 0x10, + 0xc0, 0x4b, 0x1d, 0x89, 0xef, 0x20, 0xc0, 0x2f, 0xef, 0x20, 0xa0, 0x03, 0xef, 0x20, 0x10, 0x03, + 0xef, 0x20, 0x30, 0x31, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0xb0, 0x31, 0x11, 0x46, 0x6c, 0x10, + 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0xf0, 0x35, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0xb0, 0x33, + 0x32, 0x55, 0xc1, 0x7a, 0x37, 0x0b, 0x01, 0xff, 0xb7, 0x0b, 0x00, 0x01, 0xef, 0x20, 0x70, 0x22, + 0x05, 0x64, 0x01, 0x4a, 0x93, 0x8a, 0xfa, 0x0f, 0x7d, 0x1b, 0xfd, 0x1b, 0x13, 0x0d, 0x00, 0x18, + 0x52, 0x85, 0xef, 0xf0, 0x1f, 0x87, 0xaa, 0x8c, 0x22, 0x85, 0xef, 0x20, 0xd0, 0x0f, 0x93, 0xf9, + 0x09, 0xf0, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, 0x44, 0x00, 0xef, 0x20, 0xd0, 0x0e, 0x22, 0x05, + 0xb3, 0xf9, 0x59, 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, 0x84, 0x00, 0xef, 0x20, 0xb0, 0x0d, + 0x42, 0x05, 0xb3, 0xf9, 0x69, 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, 0xc4, 0x00, 0xef, 0x20, + 0x90, 0x0c, 0x62, 0x05, 0xb3, 0xf9, 0x79, 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x93, 0xc7, 0xf9, 0xff, + 0x33, 0xf5, 0x97, 0x01, 0xe3, 0x1b, 0x05, 0xea, 0x11, 0x0a, 0x41, 0x04, 0xe3, 0x12, 0xaa, 0xfb, + 0x37, 0x55, 0x10, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x13, 0x05, 0x85, 0x5e, + 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x10, 0xf0, 0x1a, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x40, 0x05, + 0x93, 0x85, 0x45, 0x53, 0x68, 0x10, 0xef, 0x40, 0xc0, 0x24, 0x60, 0x10, 0x48, 0x40, 0x01, 0xc5, + 0xef, 0x20, 0xa0, 0x7f, 0x48, 0xc0, 0x31, 0x04, 0x1c, 0x01, 0xe3, 0x99, 0x87, 0xfe, 0x37, 0x55, + 0x10, 0x00, 0x1d, 0x46, 0x6c, 0x10, 0x13, 0x05, 0xc5, 0x5f, 0xef, 0x20, 0x40, 0x42, 0xef, 0xf0, + 0x0f, 0xe3, 0x05, 0x45, 0xef, 0x10, 0xd0, 0x02, 0xef, 0x30, 0xa0, 0x4e, 0xef, 0x30, 0x50, 0x21, + 0x01, 0x45, 0xef, 0x30, 0xf0, 0x5d, 0xb7, 0x0a, 0x20, 0x00, 0x93, 0x87, 0x0a, 0x00, 0x05, 0x6b, + 0xb3, 0x8b, 0x67, 0x01, 0xb7, 0x17, 0x20, 0x00, 0x13, 0x8a, 0xc7, 0x07, 0xef, 0x10, 0x40, 0x66, + 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x87, 0xf3, 0x63, 0x82, 0x07, 0x10, 0x37, 0x37, 0x20, 0x00, + 0x03, 0x27, 0x47, 0xf3, 0x63, 0x9c, 0xe7, 0x0e, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xc7, 0x07, 0xf3, + 0x93, 0x87, 0x07, 0xf3, 0x3e, 0xcc, 0xe3, 0x1d, 0x07, 0x36, 0x03, 0xa6, 0x0b, 0x07, 0x93, 0x07, + 0xf0, 0x07, 0xb7, 0x19, 0x20, 0x00, 0xa3, 0x8c, 0xfb, 0x06, 0xc1, 0x4c, 0x13, 0x8d, 0x0a, 0x00, + 0x93, 0x89, 0x09, 0x00, 0x63, 0xfe, 0xcc, 0x0a, 0x13, 0x04, 0x06, 0xff, 0xef, 0x10, 0x60, 0x72, + 0x01, 0x45, 0xef, 0x30, 0x60, 0x4f, 0x22, 0x86, 0x63, 0xf3, 0x8c, 0x00, 0x41, 0x46, 0x93, 0x85, + 0x0a, 0x00, 0x68, 0x10, 0xef, 0x30, 0x20, 0x50, 0xef, 0x10, 0xc0, 0x77, 0xb7, 0x57, 0x10, 0x00, + 0x23, 0x8c, 0xa9, 0x06, 0x93, 0x87, 0x87, 0x58, 0x03, 0xc7, 0x07, 0x00, 0x63, 0x1b, 0x07, 0x12, + 0x03, 0xa4, 0x09, 0x07, 0xc1, 0x47, 0xe3, 0xf2, 0x87, 0xda, 0x01, 0x45, 0xef, 0x30, 0xc0, 0x4b, + 0x41, 0x14, 0x22, 0x86, 0x93, 0x85, 0x0a, 0x00, 0x13, 0x85, 0x0a, 0x00, 0xef, 0x30, 0xa0, 0x4c, + 0xb7, 0x1c, 0x20, 0x00, 0x13, 0x85, 0x0c, 0x02, 0xef, 0x30, 0xa0, 0x68, 0xef, 0x30, 0x20, 0x6d, + 0x37, 0x56, 0x10, 0x00, 0xb7, 0x5d, 0x10, 0x00, 0xaa, 0x86, 0x13, 0x06, 0x46, 0x45, 0x93, 0x85, + 0xcd, 0x3d, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0xf0, 0x49, 0x93, 0x85, 0x0c, 0x02, 0x41, 0x46, + 0x33, 0x05, 0x8d, 0x00, 0xef, 0x00, 0x30, 0x38, 0xaa, 0x8c, 0xc1, 0x47, 0x63, 0x09, 0x05, 0x0e, + 0x89, 0x45, 0x13, 0x85, 0xcd, 0x3d, 0xef, 0x00, 0x50, 0x4f, 0x37, 0x55, 0x10, 0x00, 0x93, 0x07, + 0xb0, 0x07, 0x91, 0x45, 0x13, 0x05, 0xc5, 0x3f, 0xa3, 0x8c, 0xf9, 0x06, 0xef, 0x00, 0xf0, 0x4d, + 0xef, 0xe0, 0x9f, 0xf7, 0xef, 0xf0, 0xcf, 0x87, 0xef, 0xf0, 0x4f, 0xc3, 0xef, 0x10, 0xa0, 0x53, + 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x17, 0xf5, 0x08, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xc7, + 0x07, 0xf3, 0xc9, 0xe3, 0xef, 0x10, 0xa0, 0x02, 0xe3, 0x15, 0x85, 0x20, 0xd2, 0x47, 0x9c, 0x43, + 0x63, 0x94, 0xa7, 0x00, 0xef, 0x10, 0xc0, 0x18, 0xb2, 0x47, 0x98, 0x43, 0x93, 0x07, 0xa0, 0x0a, + 0xe3, 0x13, 0xf7, 0x1e, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0x86, 0x4d, 0x93, 0x05, 0x4c, 0x41, + 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x10, 0x41, 0xef, 0xf0, 0x4f, 0xbe, 0x37, 0x25, 0x00, 0x08, + 0xef, 0x20, 0x70, 0x0d, 0xef, 0xf0, 0x4f, 0xa8, 0xef, 0x20, 0x60, 0x5f, 0xef, 0x10, 0x50, 0x1c, + 0xef, 0x20, 0x30, 0x21, 0xef, 0xe0, 0xff, 0xf3, 0x32, 0x47, 0x37, 0x56, 0x10, 0x00, 0x93, 0x07, + 0x50, 0x05, 0x13, 0x06, 0x46, 0x4e, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, 0x64, 0x1c, 0xc3, + 0xef, 0x00, 0x50, 0x3d, 0xef, 0x20, 0x10, 0x21, 0xef, 0x10, 0x70, 0x48, 0xef, 0x20, 0x20, 0x5f, + 0xef, 0x30, 0x90, 0x00, 0xc2, 0x47, 0x98, 0x43, 0x93, 0x07, 0x50, 0x05, 0xe3, 0x08, 0xf7, 0xe4, + 0xad, 0xb9, 0x63, 0x1c, 0xe5, 0x00, 0x83, 0xc7, 0x17, 0x00, 0xbd, 0x8b, 0xe3, 0x82, 0x07, 0xec, + 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0xa0, 0x59, 0x65, 0xbd, 0x91, 0x07, 0x75, 0xb5, 0x03, 0xa4, + 0x09, 0x07, 0xe3, 0xe4, 0x87, 0x16, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0xc5, 0x3f, + 0xef, 0x00, 0xb0, 0x3f, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x3f, 0x95, 0x45, 0xef, 0x00, + 0xd0, 0x3e, 0x13, 0x05, 0xf0, 0x07, 0x39, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xf5, + 0x94, 0x43, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x87, 0x16, 0x00, 0x98, 0xc3, + 0x03, 0xc7, 0x89, 0x07, 0xa2, 0x87, 0x13, 0x06, 0x46, 0x46, 0x93, 0x85, 0xc5, 0x3f, 0x13, 0x05, + 0x49, 0x64, 0xef, 0x00, 0x30, 0x34, 0xb7, 0x17, 0x20, 0x00, 0x13, 0x85, 0xc7, 0x07, 0x3d, 0x46, + 0x81, 0x45, 0xef, 0x30, 0xd0, 0x7f, 0x83, 0xc7, 0x89, 0x07, 0x13, 0x07, 0x20, 0x04, 0x63, 0x80, + 0xe7, 0x56, 0x63, 0x69, 0xf7, 0x16, 0x13, 0x07, 0x10, 0x02, 0x63, 0x89, 0xe7, 0x3e, 0x63, 0x60, + 0xf7, 0x08, 0x45, 0x47, 0x63, 0x82, 0xe7, 0x30, 0x63, 0x69, 0xf7, 0x02, 0x05, 0x47, 0x63, 0x85, + 0xe7, 0x24, 0x41, 0x47, 0x63, 0x8d, 0xe7, 0x26, 0x89, 0x49, 0x3d, 0xa3, 0x93, 0x87, 0x07, 0xfa, + 0x93, 0xf7, 0xf7, 0x0f, 0x45, 0x47, 0xe3, 0x69, 0xf7, 0xfe, 0x37, 0x57, 0x10, 0x00, 0x8a, 0x07, + 0x13, 0x07, 0xc7, 0x4e, 0xba, 0x97, 0x9c, 0x43, 0x82, 0x87, 0x49, 0x47, 0x63, 0x82, 0xe7, 0x34, + 0x13, 0x07, 0x00, 0x02, 0xe3, 0x9a, 0xe7, 0xfc, 0x42, 0x04, 0x41, 0x80, 0xa1, 0x47, 0xe3, 0x13, + 0xf4, 0xf4, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x81, + 0x63, 0x97, 0x07, 0x54, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe3, 0xa7, 0x54, 0x83, 0x25, 0x4d, 0x00, + 0xef, 0x10, 0x90, 0x1e, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x1b, 0xf5, 0x52, 0xad, 0xa6, 0x13, 0x07, + 0x10, 0x03, 0x63, 0x86, 0xe7, 0x3a, 0x63, 0x6f, 0xf7, 0x04, 0x13, 0x07, 0x20, 0x02, 0x63, 0x87, + 0xe7, 0x38, 0x13, 0x07, 0x00, 0x03, 0xe3, 0x91, 0xe7, 0xf8, 0x42, 0x04, 0x41, 0x80, 0x91, 0x47, + 0xe3, 0x1a, 0xf4, 0xee, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x97, 0x07, 0x01, 0x8d, 0x8b, + 0x41, 0x83, 0x63, 0x9e, 0x07, 0x4e, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xea, 0xe7, 0x4e, 0x03, 0x45, + 0x3d, 0x00, 0xfd, 0x47, 0x63, 0xe5, 0xa7, 0x4e, 0x93, 0x15, 0x25, 0x00, 0x0d, 0x81, 0x93, 0xf7, + 0xc5, 0x01, 0x3a, 0x95, 0xbd, 0x45, 0xb3, 0x95, 0xf5, 0x00, 0x0a, 0x05, 0x93, 0xc5, 0xf5, 0xff, + 0x5a, 0x95, 0x05, 0xa4, 0x13, 0x07, 0x00, 0x04, 0x63, 0x8f, 0xe7, 0x3a, 0x13, 0x07, 0x10, 0x04, + 0xe3, 0x94, 0xe7, 0xf2, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x1d, 0xf4, 0xe8, 0x83, 0x26, + 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0xa1, 0x82, 0xc2, 0x06, 0xc1, 0x82, 0x63, 0xe1, 0xd7, 0x4a, + 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x86, 0x4b, 0x93, 0x85, 0xc5, 0x4a, + 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x10, 0x1f, 0xef, 0x10, 0x50, 0x57, 0xef, 0x20, 0x00, 0x75, + 0x83, 0x27, 0x0d, 0x00, 0x91, 0x65, 0x93, 0x85, 0x05, 0x20, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, + 0xa6, 0x07, 0x37, 0x15, 0x20, 0x00, 0xbe, 0x95, 0x13, 0x05, 0x05, 0x08, 0xef, 0x10, 0x30, 0x19, + 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x74, 0x93, 0x07, 0xc0, 0x1b, 0xe3, 0xe0, 0x87, 0xa8, 0x93, 0x05, + 0x44, 0x00, 0x29, 0xac, 0x13, 0x07, 0x10, 0x07, 0x63, 0x69, 0xf7, 0x02, 0x13, 0x07, 0xf0, 0x05, + 0xe3, 0x66, 0xf7, 0xea, 0x13, 0x07, 0x00, 0x05, 0xe3, 0x90, 0xe7, 0xea, 0x42, 0x04, 0x41, 0x80, + 0x89, 0x47, 0xe3, 0x19, 0xf4, 0xe0, 0x03, 0x44, 0x1d, 0x00, 0x37, 0x15, 0x20, 0x00, 0x13, 0x05, + 0x05, 0x08, 0xa2, 0x85, 0xef, 0xe0, 0x1f, 0xd7, 0xd9, 0xb7, 0x13, 0x07, 0x20, 0x08, 0x63, 0x8b, + 0xe7, 0x6e, 0x63, 0x6d, 0xf7, 0x04, 0x13, 0x07, 0x00, 0x08, 0x63, 0x82, 0xe7, 0x68, 0x13, 0x07, + 0x10, 0x08, 0xe3, 0x93, 0xe7, 0xe6, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x1c, 0xf4, 0xdc, + 0x03, 0x45, 0x1d, 0x00, 0x3d, 0x47, 0x81, 0x47, 0x63, 0x6e, 0xa7, 0x00, 0xb7, 0x37, 0x20, 0x00, + 0x03, 0xa7, 0x47, 0xf5, 0x89, 0x47, 0x33, 0x57, 0xa7, 0x00, 0x05, 0x8b, 0x01, 0xc7, 0xef, 0xe0, + 0x7f, 0xe6, 0xaa, 0x87, 0xfd, 0x17, 0x09, 0x47, 0x63, 0x63, 0xf7, 0x3c, 0x37, 0x55, 0x10, 0x00, + 0x13, 0x05, 0x85, 0x72, 0xaa, 0x97, 0x83, 0xc9, 0x07, 0x00, 0x1d, 0xaa, 0x13, 0x07, 0x00, 0x09, + 0xe3, 0x9c, 0xe7, 0xe0, 0x93, 0x17, 0x04, 0x01, 0xc1, 0x83, 0x13, 0x07, 0x30, 0x02, 0xe3, 0x73, + 0xf7, 0xd8, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0xbe, 0x86, 0x13, 0x06, 0x06, 0x4c, + 0x93, 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0xd0, 0x0e, 0xef, 0x20, 0xa0, 0x0d, + 0xef, 0x20, 0xc0, 0x64, 0xef, 0x20, 0x20, 0x0e, 0x2a, 0x84, 0xef, 0x20, 0x40, 0x0d, 0xef, 0x20, + 0x00, 0x66, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x14, 0xf4, 0x36, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, + 0x00, 0x2c, 0x93, 0x07, 0x40, 0x02, 0x81, 0xa3, 0x93, 0x19, 0x04, 0x01, 0x93, 0xd9, 0x09, 0x01, + 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0xce, 0x86, 0x13, 0x06, 0x06, 0x4a, 0x93, 0x85, + 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0xf0, 0x09, 0x93, 0x07, 0x1b, 0x00, 0xe3, 0xeb, + 0x37, 0xd1, 0xce, 0x85, 0x13, 0x85, 0x0a, 0x00, 0xef, 0xf0, 0x4f, 0x8e, 0xa9, 0xaa, 0x42, 0x04, + 0x41, 0x80, 0x93, 0x07, 0x40, 0x02, 0xe3, 0x1f, 0xf4, 0xce, 0x03, 0x25, 0x0d, 0x00, 0x0d, 0x44, + 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0x64, 0xa4, 0x30, 0xef, 0xf0, 0x8f, 0xae, 0xd5, 0x47, + 0x63, 0x1f, 0xf5, 0x2e, 0x83, 0x29, 0x0d, 0x00, 0x93, 0xd9, 0x89, 0x00, 0xc2, 0x09, 0x93, 0xd9, + 0x09, 0x01, 0xe3, 0x6c, 0x34, 0x91, 0x13, 0x84, 0x09, 0x0e, 0x16, 0x04, 0x91, 0x4c, 0x71, 0x14, + 0x93, 0x0d, 0x40, 0x02, 0xb3, 0x05, 0x9d, 0x01, 0x11, 0x46, 0x68, 0x10, 0xef, 0x30, 0x70, 0x4c, + 0xb2, 0x55, 0x33, 0x05, 0x94, 0x01, 0x91, 0x0c, 0xef, 0x20, 0x20, 0x33, 0xe3, 0x94, 0xbc, 0xff, + 0x09, 0x65, 0x8a, 0x09, 0xb7, 0xf5, 0xf0, 0xf0, 0x13, 0x05, 0x05, 0xbf, 0x93, 0x85, 0x05, 0x0f, + 0x4e, 0x95, 0xef, 0x20, 0x80, 0x31, 0xc5, 0xa0, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x13, + 0xf4, 0xc8, 0x03, 0x25, 0x0d, 0x00, 0x0d, 0x44, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0x68, + 0xa4, 0x28, 0xef, 0xf0, 0x0f, 0xa7, 0x93, 0x07, 0x30, 0x0c, 0x63, 0x08, 0xf5, 0x00, 0xaa, 0x89, + 0x93, 0x07, 0x00, 0x08, 0x63, 0x9a, 0xf9, 0x20, 0xb1, 0xb9, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, + 0xc2, 0x07, 0xc1, 0x83, 0xe3, 0x6b, 0xf4, 0x88, 0x93, 0x87, 0x07, 0x0e, 0x13, 0x94, 0x57, 0x00, + 0x93, 0x09, 0x00, 0x02, 0x33, 0x05, 0x94, 0x01, 0xef, 0x20, 0x20, 0x20, 0xb7, 0x17, 0x20, 0x00, + 0x93, 0x87, 0x07, 0x08, 0x2a, 0xd6, 0x11, 0x46, 0x33, 0x85, 0x97, 0x01, 0x6c, 0x10, 0x91, 0x0c, + 0xef, 0x30, 0x30, 0x43, 0xe3, 0x90, 0x3c, 0xff, 0x93, 0x05, 0x40, 0x02, 0x52, 0x85, 0x29, 0xb7, + 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x17, 0xf4, 0xc0, 0x03, 0x25, 0x0d, 0x00, 0x21, 0x81, + 0x42, 0x05, 0x41, 0x81, 0x63, 0x6d, 0xa4, 0x20, 0xef, 0xf0, 0xaf, 0x9f, 0xd5, 0x47, 0x63, 0x08, + 0xf5, 0x20, 0xd9, 0x47, 0x63, 0x01, 0xf5, 0x04, 0x83, 0x29, 0x0d, 0x00, 0x93, 0xd9, 0x89, 0x00, + 0xc2, 0x09, 0x93, 0xd9, 0x09, 0x01, 0xe3, 0x62, 0x34, 0x83, 0x89, 0x67, 0x13, 0x95, 0x29, 0x00, + 0x93, 0x87, 0x07, 0xbf, 0x81, 0x45, 0x3e, 0x95, 0x93, 0x89, 0x09, 0x0e, 0xef, 0x20, 0xe0, 0x24, + 0x96, 0x09, 0x13, 0x04, 0x00, 0x02, 0x33, 0x85, 0x99, 0x01, 0x81, 0x45, 0x91, 0x0c, 0xef, 0x20, + 0xc0, 0x23, 0xe3, 0x9a, 0x8c, 0xfe, 0x93, 0x09, 0x30, 0x0c, 0xb9, 0xaa, 0x42, 0x04, 0x41, 0x80, + 0x8d, 0x47, 0xe3, 0x11, 0xf4, 0xba, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, 0x07, 0x01, + 0x8d, 0x8b, 0x41, 0x81, 0x63, 0x95, 0x07, 0x1a, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe1, 0xa7, 0x1a, + 0xef, 0x10, 0x60, 0x5b, 0x23, 0x22, 0xaa, 0x00, 0xa1, 0x45, 0x8d, 0xb7, 0x42, 0x04, 0x41, 0x80, + 0x85, 0x47, 0x01, 0x45, 0xe3, 0x18, 0xf4, 0xb6, 0xef, 0x10, 0x30, 0x24, 0x6d, 0xbf, 0x42, 0x04, + 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x10, 0xf4, 0xb6, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x94, + 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x80, 0x63, 0x94, 0x07, 0x16, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe0, + 0x87, 0x16, 0x0a, 0x04, 0x33, 0x05, 0x64, 0x01, 0xef, 0x20, 0xe0, 0x17, 0x93, 0xf4, 0x04, 0xf0, + 0xc9, 0x8c, 0x13, 0x05, 0x4b, 0x00, 0x22, 0x95, 0xef, 0x20, 0xe0, 0x16, 0xc1, 0x77, 0x93, 0x87, + 0xf7, 0x0f, 0xfd, 0x8c, 0x22, 0x05, 0xc9, 0x8c, 0x13, 0x05, 0x8b, 0x00, 0x22, 0x95, 0xef, 0x20, + 0x80, 0x15, 0xb7, 0x07, 0x01, 0xff, 0xfd, 0x17, 0x42, 0x05, 0xfd, 0x8c, 0xc9, 0x8c, 0x13, 0x05, + 0xcb, 0x00, 0x22, 0x95, 0xef, 0x20, 0x20, 0x14, 0xa2, 0x04, 0x62, 0x05, 0xa1, 0x80, 0xc9, 0x8c, + 0x23, 0x22, 0x9a, 0x00, 0x95, 0xbf, 0x93, 0x07, 0xb4, 0xff, 0xc2, 0x07, 0xc1, 0x83, 0x13, 0x07, + 0xb0, 0x1b, 0xe3, 0x61, 0xf7, 0xae, 0x83, 0x26, 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0x93, 0x09, + 0xc0, 0x03, 0xa1, 0x82, 0xc2, 0x06, 0xc1, 0x82, 0x63, 0xe0, 0xd7, 0x08, 0x37, 0x56, 0x10, 0x00, + 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x06, 0x4b, 0x93, 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, + 0xef, 0x00, 0x40, 0x63, 0x03, 0x25, 0x0d, 0x00, 0x91, 0x69, 0x93, 0x89, 0x09, 0x20, 0x21, 0x81, + 0x42, 0x05, 0x41, 0x81, 0x26, 0x05, 0x4e, 0x95, 0xef, 0x10, 0x30, 0x13, 0x93, 0x07, 0xa0, 0x0a, + 0xaa, 0x8c, 0x63, 0x12, 0xf5, 0x04, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0xbf, 0x9f, 0xef, 0x20, + 0xe0, 0x36, 0x83, 0x27, 0x0d, 0x00, 0x42, 0x04, 0x41, 0x80, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, + 0xa6, 0x07, 0xb7, 0x05, 0x20, 0x00, 0x13, 0x06, 0xc4, 0xff, 0x33, 0x85, 0x37, 0x01, 0x74, 0x10, + 0x93, 0x85, 0x45, 0x00, 0xef, 0x10, 0xf0, 0x02, 0x2a, 0x84, 0x93, 0x09, 0x30, 0x0c, 0xef, 0x20, + 0x00, 0x36, 0x63, 0x03, 0x94, 0x01, 0xc1, 0x49, 0x13, 0xf5, 0xf9, 0x0f, 0xe5, 0xae, 0x42, 0x04, + 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x10, 0xf4, 0xa4, 0x03, 0x25, 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, + 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0xe4, 0xa7, 0x04, 0x91, 0x67, 0x26, 0x05, 0x93, 0x87, + 0x07, 0x20, 0x3e, 0x95, 0x55, 0xbd, 0x42, 0x04, 0x41, 0x80, 0x91, 0x47, 0xe3, 0x1c, 0xf4, 0xa0, + 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0x1f, 0x98, 0x68, 0x10, 0xef, 0x10, 0x80, 0x7c, 0xef, 0x30, + 0xa0, 0x20, 0xef, 0x20, 0xa0, 0x2e, 0x91, 0x45, 0x13, 0x05, 0x00, 0x06, 0xef, 0x30, 0xc0, 0x42, + 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x2f, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x0e, 0xf4, 0xe2, 0x93, 0x09, + 0xc0, 0x03, 0x59, 0xbf, 0x42, 0x04, 0x41, 0x80, 0x93, 0x07, 0x00, 0x03, 0xe3, 0x1c, 0xf4, 0x9c, + 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0x1f, 0x94, 0x68, 0x10, 0xef, 0x10, 0x80, 0x78, 0xef, 0x30, + 0xa0, 0x1c, 0xef, 0x20, 0xa0, 0x2a, 0x93, 0x05, 0x00, 0x03, 0x13, 0x05, 0x10, 0x06, 0x7d, 0xbf, + 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x17, 0xf4, 0x9a, 0xef, 0x30, 0xe0, 0x1a, 0xef, 0x20, + 0xe0, 0x28, 0x8d, 0x45, 0x13, 0x05, 0x20, 0x06, 0xef, 0x30, 0x00, 0x3d, 0x2a, 0x84, 0xef, 0x20, + 0x00, 0x2a, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x14, 0xf4, 0xfa, 0xef, 0xe0, 0x7f, 0xf0, 0x05, 0xb3, + 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x1f, 0xf4, 0x96, 0xef, 0x30, 0xe0, 0x17, 0x8d, 0x45, + 0x13, 0x05, 0x30, 0x06, 0xef, 0x30, 0x40, 0x3a, 0xb1, 0xb4, 0x42, 0x04, 0x41, 0x80, 0x93, 0x07, + 0x00, 0x03, 0xe3, 0x11, 0xf4, 0x96, 0xef, 0x30, 0x20, 0x16, 0xef, 0x20, 0x50, 0x6f, 0xb7, 0x15, + 0x20, 0x00, 0x2a, 0xd6, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, + 0xef, 0x30, 0x60, 0x26, 0x11, 0x46, 0x6c, 0x10, 0x13, 0x05, 0x00, 0x0c, 0xef, 0x30, 0xa0, 0x25, + 0xef, 0x20, 0xc0, 0x21, 0x93, 0x05, 0x00, 0x03, 0x13, 0x05, 0x00, 0x07, 0xef, 0x30, 0xc0, 0x35, + 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x22, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1a, 0xf4, 0xf2, 0xef, 0xe0, + 0x3f, 0xe9, 0x75, 0xb1, 0x93, 0x17, 0x04, 0x01, 0xc1, 0x83, 0x3d, 0x47, 0xe3, 0x74, 0xf7, 0x90, + 0xef, 0x30, 0x80, 0x10, 0xef, 0x20, 0xb0, 0x69, 0xaa, 0x8c, 0x01, 0x45, 0xef, 0x20, 0xd0, 0x45, + 0x41, 0x46, 0x93, 0x85, 0x0a, 0x00, 0x01, 0x45, 0xef, 0x20, 0xf0, 0x46, 0xef, 0x20, 0x00, 0x1d, + 0xb7, 0x15, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, + 0x66, 0xd6, 0xef, 0x30, 0x40, 0x1f, 0x11, 0x46, 0x6c, 0x10, 0x13, 0x05, 0x00, 0x0c, 0xef, 0x30, + 0x80, 0x1e, 0x85, 0x45, 0x13, 0x05, 0x10, 0x04, 0xef, 0x30, 0x00, 0x2f, 0x93, 0x07, 0xa0, 0x0a, + 0xaa, 0x8c, 0x63, 0x19, 0xf5, 0x00, 0x81, 0x45, 0x13, 0x05, 0x20, 0x04, 0xef, 0x30, 0xc0, 0x2d, + 0x63, 0x05, 0x95, 0x01, 0xef, 0x20, 0xa0, 0x1a, 0x5d, 0xbd, 0x42, 0x04, 0x41, 0x80, 0x93, 0x0d, + 0x04, 0xff, 0xef, 0x20, 0xc0, 0x19, 0xee, 0x8c, 0x22, 0x9d, 0x93, 0x07, 0x00, 0x09, 0xb3, 0x05, + 0x9d, 0x41, 0x63, 0xe5, 0x97, 0x09, 0x66, 0x86, 0x01, 0x45, 0xef, 0x20, 0xd0, 0x3f, 0xe6, 0x85, + 0x13, 0x05, 0x40, 0x04, 0xef, 0x30, 0x40, 0x2a, 0x13, 0x07, 0xa0, 0x0a, 0xe3, 0x11, 0xe5, 0xe8, + 0x2a, 0xce, 0x81, 0x45, 0x13, 0x05, 0x50, 0x04, 0xef, 0x30, 0x00, 0x29, 0xf2, 0x47, 0xaa, 0x8c, + 0xe3, 0x17, 0xf5, 0xe6, 0x01, 0x45, 0xef, 0x20, 0x30, 0x3b, 0x93, 0x85, 0x0a, 0x00, 0x41, 0x46, + 0x01, 0x45, 0xef, 0x20, 0x50, 0x3c, 0x93, 0x07, 0xf0, 0x03, 0xb7, 0x05, 0x20, 0x00, 0x63, 0xe1, + 0xb7, 0x07, 0x93, 0x85, 0x05, 0x01, 0x01, 0x45, 0x6e, 0x86, 0xef, 0x20, 0xd0, 0x3a, 0xee, 0x85, + 0x13, 0x05, 0x60, 0x04, 0xef, 0x30, 0x40, 0x25, 0xe3, 0x1b, 0x95, 0xe3, 0x81, 0x45, 0x13, 0x05, + 0xa0, 0x04, 0xef, 0x30, 0x60, 0x24, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x12, 0xf5, 0xe2, 0xef, 0x20, + 0x10, 0x58, 0x93, 0x07, 0x00, 0x05, 0x23, 0xaa, 0xf9, 0x06, 0xb1, 0xb1, 0x13, 0x06, 0x00, 0x09, + 0x01, 0x45, 0xef, 0x20, 0x50, 0x37, 0x93, 0x05, 0x00, 0x09, 0x13, 0x05, 0x30, 0x04, 0xef, 0x30, + 0xa0, 0x21, 0x13, 0x07, 0xa0, 0x0a, 0xe3, 0x1c, 0xe5, 0xde, 0x93, 0x8c, 0x0c, 0xf7, 0xb1, 0xb7, + 0x93, 0x85, 0x05, 0x01, 0x01, 0x45, 0x13, 0x06, 0x00, 0x04, 0xef, 0x20, 0xd0, 0x34, 0x93, 0x05, + 0x00, 0x04, 0x13, 0x05, 0x70, 0x04, 0xef, 0x30, 0x20, 0x1f, 0xe3, 0x1a, 0x95, 0xdd, 0x13, 0x04, + 0x04, 0xfb, 0x93, 0x0c, 0x00, 0x08, 0x93, 0x0d, 0xa0, 0x0a, 0xb3, 0x05, 0x8d, 0x40, 0x63, 0xe0, + 0x8c, 0x02, 0x22, 0x86, 0x01, 0x45, 0xef, 0x20, 0x10, 0x32, 0xa2, 0x85, 0x13, 0x05, 0x90, 0x04, + 0xef, 0x30, 0x80, 0x1c, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x13, 0xf5, 0xda, 0x85, 0xbf, 0x01, 0x45, + 0x13, 0x06, 0x00, 0x08, 0xef, 0x20, 0x30, 0x30, 0x93, 0x05, 0x00, 0x08, 0x13, 0x05, 0x80, 0x04, + 0xef, 0x30, 0x80, 0x1a, 0xe3, 0x15, 0xb5, 0xd9, 0x13, 0x04, 0x04, 0xf8, 0x7d, 0xbf, 0x42, 0x04, + 0x41, 0x80, 0xa1, 0x47, 0x63, 0x10, 0xf4, 0xf6, 0x03, 0x44, 0x1d, 0x00, 0xbd, 0x47, 0xe3, 0xe8, + 0x87, 0xd6, 0x83, 0x2c, 0x4d, 0x00, 0xfd, 0x57, 0xe3, 0x83, 0xfc, 0xd6, 0x93, 0x19, 0xa4, 0x00, + 0x13, 0x85, 0x09, 0x40, 0xef, 0xe0, 0x8f, 0xe6, 0x13, 0x07, 0xa0, 0x0a, 0x2a, 0x8d, 0xe3, 0x18, + 0xe5, 0xd4, 0x93, 0x89, 0x09, 0x20, 0x4e, 0x85, 0xef, 0xe0, 0x4f, 0xe5, 0xaa, 0x8d, 0xe3, 0x10, + 0xa5, 0xd5, 0xe6, 0x85, 0x4e, 0x85, 0xef, 0x10, 0x60, 0x1b, 0xe3, 0x1a, 0xb5, 0xd3, 0x37, 0x37, + 0x20, 0x00, 0x13, 0x07, 0x47, 0xf5, 0x85, 0x47, 0x33, 0x94, 0x87, 0x00, 0x1c, 0x43, 0x5d, 0x8c, + 0x00, 0xc3, 0x91, 0xbe, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0x63, 0x1d, 0xf4, 0xee, 0x83, 0x45, + 0x1d, 0x00, 0xbd, 0x47, 0xe3, 0xe5, 0xb7, 0xd0, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf5, + 0xd1, 0x49, 0xb3, 0xd7, 0xb7, 0x00, 0x85, 0x8b, 0xe3, 0x88, 0x07, 0xc8, 0x37, 0x15, 0x20, 0x00, + 0x13, 0x05, 0x05, 0x08, 0xef, 0xe0, 0x6f, 0xeb, 0x85, 0x47, 0xe3, 0x07, 0xf5, 0xb4, 0x89, 0x47, + 0xe3, 0x0c, 0xf5, 0xc6, 0xe9, 0xb9, 0xef, 0x10, 0x90, 0x43, 0xef, 0xe0, 0x8f, 0xd8, 0x6f, 0xf0, + 0xef, 0xe6, 0xef, 0x00, 0xc0, 0x6f, 0x6f, 0xf0, 0xef, 0xe6, 0xef, 0x00, 0x30, 0x4e, 0x41, 0x14, + 0xaa, 0x86, 0x63, 0x0b, 0x05, 0xea, 0x8d, 0x45, 0x13, 0x85, 0xcd, 0x3d, 0x36, 0xce, 0x71, 0x24, + 0xf2, 0x46, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x45, 0x93, 0x85, 0xcd, 0x3d, 0x13, 0x05, + 0x49, 0x64, 0x09, 0x24, 0xf2, 0x46, 0x09, 0x47, 0x85, 0x47, 0x63, 0x83, 0xe6, 0x00, 0x89, 0x47, + 0x83, 0xc6, 0x89, 0x07, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x22, 0x87, 0x13, 0x06, + 0xc6, 0x47, 0x93, 0x85, 0xc5, 0x3f, 0x13, 0x05, 0x49, 0x64, 0xa3, 0x8c, 0xf9, 0x06, 0xd9, 0x2a, + 0xef, 0xe0, 0x8f, 0xce, 0xef, 0xe0, 0x8f, 0xff, 0x62, 0x47, 0x85, 0x47, 0x23, 0x00, 0xf7, 0x00, + 0xef, 0x00, 0xe0, 0x5a, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x11, 0xf5, 0xd6, 0x25, 0x29, + 0x63, 0x1e, 0x85, 0xd4, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xf4, 0xb1, 0xeb, 0x83, 0xa7, + 0x4b, 0x07, 0x13, 0x07, 0xfb, 0x00, 0xfd, 0x17, 0x63, 0x64, 0xf7, 0x04, 0x05, 0x45, 0xef, 0x20, + 0xb0, 0x17, 0x03, 0xa6, 0x4b, 0x07, 0xb7, 0x09, 0x20, 0x00, 0x93, 0x85, 0x09, 0x00, 0x13, 0x85, + 0x09, 0x00, 0xef, 0x20, 0xf0, 0x25, 0x37, 0x14, 0x20, 0x00, 0x13, 0x05, 0x04, 0x02, 0xef, 0x20, + 0x50, 0x34, 0x03, 0xa5, 0x4b, 0x07, 0x93, 0x87, 0x09, 0x00, 0x41, 0x46, 0x3e, 0x95, 0x93, 0x05, + 0x04, 0x02, 0xef, 0x30, 0x00, 0x5f, 0x83, 0xa7, 0x4b, 0x07, 0xc1, 0x07, 0x23, 0xaa, 0xfb, 0x06, + 0xef, 0x00, 0xf0, 0x1b, 0x13, 0x04, 0xa0, 0x0a, 0x63, 0x0a, 0x85, 0xce, 0xef, 0xe0, 0x8f, 0xfe, + 0x63, 0x16, 0x85, 0xce, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, + 0x13, 0x06, 0x06, 0x4d, 0x93, 0x85, 0xc5, 0x3f, 0x13, 0x05, 0x45, 0x40, 0x25, 0x22, 0xef, 0xe0, + 0x2f, 0xb7, 0xef, 0x20, 0x70, 0x32, 0xef, 0x00, 0xb0, 0x3a, 0xef, 0x00, 0xb0, 0x31, 0xef, 0xe0, + 0xaf, 0xf9, 0x6f, 0xf0, 0xaf, 0xcb, 0x2a, 0x87, 0x81, 0x47, 0x01, 0x45, 0x63, 0x93, 0xc7, 0x00, + 0x82, 0x80, 0xb3, 0x06, 0xf7, 0x00, 0x33, 0x88, 0xf5, 0x00, 0x83, 0xc6, 0x06, 0x00, 0x03, 0x48, + 0x08, 0x00, 0x85, 0x07, 0xb3, 0xc6, 0x06, 0x01, 0x55, 0x8d, 0x13, 0x75, 0xf5, 0x0f, 0xf9, 0xbf, + 0xb7, 0x37, 0x20, 0x00, 0x37, 0x37, 0x20, 0x00, 0x03, 0xa8, 0xc7, 0xf5, 0x83, 0x27, 0x87, 0xf5, + 0xaa, 0x86, 0x13, 0x07, 0x87, 0xf5, 0x01, 0x45, 0x63, 0x13, 0xf8, 0x00, 0x82, 0x80, 0x37, 0x26, + 0x20, 0x00, 0x13, 0x06, 0xc6, 0x08, 0x93, 0x08, 0xf0, 0x7f, 0x63, 0x01, 0xb5, 0x02, 0x33, 0x0e, + 0xf6, 0x00, 0x03, 0x4e, 0x0e, 0x00, 0x05, 0x05, 0x33, 0x83, 0xa6, 0x00, 0xa3, 0x0f, 0xc3, 0xff, + 0x85, 0x07, 0x63, 0xf3, 0xf8, 0x00, 0x81, 0x47, 0xe3, 0x11, 0xf8, 0xfe, 0x1c, 0xc3, 0x82, 0x80, + 0xb7, 0x36, 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x86, 0xf5, 0x83, 0xa7, 0xc7, 0xf5, + 0x93, 0x86, 0x86, 0xf5, 0x33, 0x87, 0xe7, 0x40, 0x63, 0x56, 0x07, 0x00, 0x05, 0x66, 0x13, 0x06, + 0x06, 0x80, 0x32, 0x97, 0x63, 0x5b, 0xe5, 0x00, 0x33, 0x85, 0xa7, 0x40, 0x85, 0x67, 0x93, 0x87, + 0x07, 0x80, 0x63, 0xf3, 0xa7, 0x00, 0x3e, 0x95, 0x88, 0xc2, 0x82, 0x80, 0xb7, 0x36, 0x20, 0x00, + 0x03, 0xa8, 0xc6, 0xf5, 0x13, 0x07, 0xf0, 0x7f, 0x13, 0x86, 0xc6, 0xf5, 0x93, 0x07, 0x18, 0x00, + 0x63, 0x73, 0xf7, 0x00, 0x81, 0x47, 0xb7, 0x36, 0x20, 0x00, 0x83, 0xa8, 0x86, 0xf5, 0x37, 0x27, + 0x20, 0x00, 0x93, 0x85, 0x86, 0xf5, 0x13, 0x07, 0xc7, 0x08, 0x63, 0x9f, 0xf8, 0x00, 0x93, 0x88, + 0x17, 0x80, 0x93, 0x86, 0x17, 0x00, 0x63, 0x93, 0x08, 0x00, 0x81, 0x46, 0x94, 0xc1, 0xba, 0x96, + 0x93, 0x05, 0xa0, 0x02, 0x23, 0x80, 0xb6, 0x00, 0x42, 0x97, 0x23, 0x00, 0xa7, 0x00, 0x1c, 0xc2, + 0x82, 0x80, 0x82, 0x80, 0x39, 0x71, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x06, 0xce, 0x36, 0xd6, + 0x3a, 0xd8, 0x3e, 0xda, 0x42, 0xdc, 0x46, 0xde, 0xaa, 0x84, 0x2e, 0x89, 0x32, 0x84, 0x19, 0xe1, + 0xef, 0xe0, 0xdf, 0x96, 0x63, 0x14, 0x09, 0x00, 0xef, 0xe0, 0x5f, 0x96, 0x19, 0xe0, 0xef, 0xe0, + 0xff, 0x95, 0x7c, 0x10, 0x3e, 0xc6, 0xef, 0x30, 0x20, 0x13, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, + 0x13, 0x05, 0x85, 0x60, 0xef, 0x30, 0x20, 0x38, 0x37, 0x55, 0x10, 0x00, 0x4a, 0x86, 0xa6, 0x85, + 0x13, 0x05, 0x05, 0x61, 0xef, 0x30, 0x20, 0x37, 0xb2, 0x45, 0x22, 0x85, 0xef, 0x30, 0x80, 0x33, + 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x61, 0xef, 0x30, 0xe0, 0x35, 0xb9, 0x29, 0xf2, 0x40, + 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0x21, 0x61, 0x82, 0x80, 0xae, 0x86, 0x37, 0x56, 0x10, 0x00, + 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x4b, 0x13, 0x05, 0x05, 0x62, 0x9d, 0xbf, + 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, 0x83, 0xa6, 0x47, 0x10, + 0x63, 0x7e, 0xd7, 0x00, 0x0a, 0x07, 0x3e, 0x97, 0x18, 0x43, 0x18, 0xc1, 0x03, 0xa7, 0x07, 0x10, + 0x13, 0x05, 0xa0, 0x0a, 0x05, 0x07, 0x23, 0xa0, 0xe7, 0x10, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, + 0x82, 0x80, 0x01, 0x11, 0x26, 0xca, 0xb7, 0x34, 0x20, 0x00, 0x83, 0xa7, 0x04, 0xf6, 0x06, 0xce, + 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x11, 0x47, 0x63, 0x6f, 0xf7, 0x0c, 0x37, 0x57, + 0x10, 0x00, 0x8a, 0x07, 0x13, 0x07, 0x87, 0x64, 0xba, 0x97, 0x9c, 0x43, 0x2a, 0x84, 0x93, 0x84, + 0x04, 0xf6, 0x82, 0x87, 0x81, 0x45, 0xef, 0x30, 0x20, 0x31, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x92, + 0xa7, 0xf6, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x86, 0x87, 0x88, 0xef, 0x20, 0xd0, 0x6f, 0x9c, 0x40, + 0x85, 0x07, 0x81, 0xa8, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0x07, 0xf6, 0x93, 0x07, 0xc0, 0x0f, + 0x63, 0xf1, 0xa7, 0x02, 0x62, 0x44, 0x9d, 0x47, 0xf2, 0x40, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, + 0x9c, 0xc0, 0xd2, 0x44, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x45, 0x62, 0x05, 0x61, + 0x2d, 0xbf, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x49, 0xf6, 0x83, 0x55, 0x09, 0x00, 0xef, 0x30, + 0xa0, 0x2b, 0xb7, 0x37, 0x20, 0x00, 0xa3, 0x86, 0x87, 0x88, 0x23, 0x10, 0xa9, 0x00, 0x8d, 0x47, + 0x5d, 0xf4, 0x9c, 0xc0, 0x91, 0xa8, 0x37, 0x39, 0x20, 0x00, 0x03, 0x27, 0x89, 0xf6, 0x93, 0x07, + 0xb0, 0x0f, 0x13, 0x09, 0x89, 0xf6, 0x63, 0xf4, 0xe7, 0x00, 0xef, 0xe0, 0x3f, 0x81, 0x83, 0x27, + 0x09, 0x00, 0x37, 0x3a, 0x20, 0x00, 0x13, 0x0a, 0x4a, 0xf6, 0xb7, 0x39, 0x20, 0x00, 0x93, 0x89, + 0xc9, 0x88, 0x83, 0x55, 0x0a, 0x00, 0xce, 0x97, 0x23, 0x81, 0x87, 0x00, 0x22, 0x85, 0xef, 0x30, + 0xa0, 0x26, 0x83, 0x27, 0x09, 0x00, 0x03, 0xc7, 0x19, 0x00, 0x23, 0x10, 0xaa, 0x00, 0x85, 0x07, + 0x23, 0x20, 0xf9, 0x00, 0xe3, 0xfd, 0xe7, 0xf4, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, + 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x93, 0xa7, 0xf6, + 0x3d, 0xbf, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x69, 0xf6, 0x13, 0x14, 0x85, 0x00, 0xb7, 0x39, + 0x20, 0x00, 0x03, 0x55, 0x09, 0x00, 0x93, 0x89, 0x49, 0xf6, 0x83, 0xd7, 0x09, 0x00, 0x49, 0x8c, + 0x23, 0x10, 0x89, 0x00, 0xe3, 0x8d, 0x87, 0xf0, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0x44, 0x62, + 0x99, 0x47, 0x89, 0x45, 0x9c, 0xc0, 0x95, 0x3d, 0x93, 0x05, 0x44, 0x62, 0x62, 0x44, 0x03, 0xd7, + 0x09, 0x00, 0x83, 0x56, 0x09, 0x00, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, + 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x86, 0x62, 0x13, 0x05, 0x45, 0x64, + 0x05, 0x61, 0x6f, 0xf0, 0x3f, 0xdd, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0xb7, 0x25, + 0x10, 0x00, 0x37, 0x25, 0x10, 0x00, 0x23, 0xa0, 0x07, 0x10, 0x23, 0xa2, 0x07, 0x10, 0x93, 0x85, + 0x05, 0xf8, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x05, 0x25, 0xfb, 0x23, 0xa0, 0x07, 0xf6, 0x6f, 0x20, + 0xb0, 0x52, 0x11, 0xed, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0xef, 0xe0, 0x2f, 0xf2, 0x32, 0x45, + 0xf2, 0x40, 0x13, 0x06, 0xe0, 0x0f, 0x81, 0x45, 0x05, 0x61, 0x6f, 0x30, 0x40, 0x25, 0x13, 0x06, + 0xe0, 0x0f, 0x81, 0x45, 0xdd, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xf6, 0x13, 0x05, + 0xa0, 0x0a, 0x99, 0xc3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, + 0x20, 0x00, 0x13, 0x04, 0x04, 0xf6, 0x1c, 0x40, 0x06, 0xc6, 0x15, 0x47, 0x63, 0x98, 0xe7, 0x00, + 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x81, 0xe7, 0x13, 0x05, + 0x50, 0x05, 0xcd, 0xbf, 0xef, 0x20, 0x90, 0x50, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x19, 0xf5, 0xfe, + 0x01, 0x00, 0x18, 0x40, 0x91, 0x47, 0xe3, 0xcd, 0xe7, 0xfc, 0x99, 0x47, 0x1c, 0xc0, 0xd9, 0xbf, + 0x41, 0x11, 0x06, 0xc6, 0xef, 0x20, 0x10, 0x50, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xf5, 0x00, + 0xef, 0x20, 0x70, 0x51, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x95, 0x47, 0x13, 0x05, + 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, + 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x99, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, + 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, + 0x9d, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, + 0x37, 0x35, 0x20, 0x00, 0x13, 0x05, 0xc5, 0x88, 0x82, 0x80, 0x01, 0x11, 0x26, 0xca, 0x06, 0xce, + 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0xaa, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, 0xe3, 0x83, 0xc7, + 0x14, 0x00, 0x13, 0x07, 0xc0, 0x0f, 0x13, 0x05, 0x50, 0x05, 0x63, 0x65, 0xf7, 0x06, 0x37, 0x39, + 0x20, 0x00, 0x13, 0x04, 0xc9, 0x98, 0x23, 0x20, 0x04, 0x10, 0x03, 0xc7, 0x04, 0x00, 0xa3, 0x00, + 0xf4, 0x00, 0x03, 0xc6, 0x14, 0x00, 0x23, 0x00, 0xe4, 0x00, 0x93, 0x85, 0x24, 0x00, 0x13, 0x05, + 0x24, 0x00, 0xef, 0x30, 0x00, 0x10, 0x83, 0xc9, 0x14, 0x00, 0x13, 0x05, 0xc9, 0x98, 0x13, 0x09, + 0xc9, 0x98, 0x93, 0x84, 0x29, 0x00, 0xa6, 0x85, 0xef, 0x30, 0x60, 0x08, 0xa2, 0x94, 0x23, 0x80, + 0xa4, 0x00, 0x4e, 0x94, 0x21, 0x81, 0x93, 0x87, 0x49, 0x00, 0xa3, 0x01, 0xa4, 0x00, 0xfd, 0x56, + 0x13, 0xf7, 0x37, 0x00, 0x19, 0xef, 0x89, 0x83, 0x23, 0x22, 0xf9, 0x10, 0xef, 0x20, 0xb0, 0x45, + 0x13, 0x05, 0xa0, 0x0a, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, + 0x82, 0x80, 0x33, 0x07, 0xf9, 0x00, 0x23, 0x00, 0xd7, 0x00, 0x85, 0x07, 0xd1, 0xbf, 0xb7, 0x37, + 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, 0x83, 0xa7, 0x47, 0x10, 0x63, 0x14, + 0xf7, 0x00, 0x6f, 0x20, 0x30, 0x3e, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, + 0x23, 0xa0, 0x07, 0xf6, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x93, 0x07, 0x00, 0x08, 0x73, 0xa0, + 0x47, 0x30, 0x93, 0x06, 0x70, 0x3e, 0x09, 0x46, 0x93, 0x05, 0x60, 0x04, 0x37, 0x05, 0x10, 0x01, + 0xef, 0x20, 0x30, 0x52, 0x8d, 0x45, 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, 0x70, 0x52, 0x37, 0x05, + 0x10, 0x01, 0xef, 0x20, 0xf0, 0x4f, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x10, 0x50, 0xfd, 0x56, + 0x01, 0x46, 0x93, 0x05, 0x60, 0x04, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x90, 0x4f, 0xb2, 0x40, + 0xb7, 0x07, 0x20, 0x01, 0x23, 0xac, 0x07, 0x00, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, + 0x89, 0x2c, 0xb2, 0x40, 0x41, 0x01, 0x45, 0xb7, 0x41, 0x11, 0x22, 0xc4, 0xb7, 0x07, 0x20, 0x01, + 0x06, 0xc6, 0x23, 0xac, 0x07, 0x00, 0x2a, 0x84, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x50, 0x4b, + 0x93, 0x07, 0x80, 0x3e, 0x13, 0x05, 0x80, 0x3e, 0x63, 0xe3, 0x87, 0x00, 0x22, 0x85, 0xb7, 0x07, + 0x20, 0x01, 0x98, 0x4f, 0x13, 0x84, 0x87, 0x01, 0xe3, 0x6d, 0xa7, 0xfe, 0x37, 0x05, 0x20, 0x01, + 0xef, 0x20, 0xb0, 0x49, 0xb2, 0x40, 0x23, 0x20, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, + 0x11, 0xe1, 0x82, 0x80, 0x01, 0x00, 0x7d, 0x15, 0xe5, 0xbf, 0x6f, 0xf0, 0x9f, 0xb3, 0x39, 0xa4, + 0x01, 0x11, 0x26, 0xca, 0xaa, 0x84, 0x37, 0x05, 0x20, 0x01, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, + 0x56, 0xc2, 0x06, 0xce, 0x22, 0xcc, 0x2e, 0x89, 0x93, 0x09, 0xa0, 0x0a, 0xef, 0x20, 0x50, 0x45, + 0x37, 0x0a, 0x20, 0x01, 0x93, 0x0a, 0x80, 0x3e, 0x82, 0x94, 0x2a, 0x84, 0x63, 0x0c, 0x35, 0x03, + 0x83, 0x27, 0x8a, 0x01, 0x63, 0x7a, 0xf9, 0x04, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0xc4, 0x65, + 0x85, 0x45, 0xef, 0xf0, 0x9f, 0xb6, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0x05, + 0xc4, 0x65, 0xa6, 0x86, 0x13, 0x06, 0x06, 0x66, 0x13, 0x05, 0x45, 0x64, 0xef, 0xf0, 0x9f, 0xad, + 0x13, 0x04, 0x50, 0x05, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x30, 0x41, 0xf2, 0x40, 0x22, 0x85, + 0x62, 0x44, 0xb7, 0x07, 0x20, 0x01, 0x23, 0xac, 0x07, 0x00, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, + 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xe3, 0xf0, 0x2a, 0xfb, 0x41, 0x22, 0x69, 0xbf, + 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x87, 0x00, 0x1c, 0xc7, 0x82, 0x80, 0x41, 0x11, + 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, 0xc1, 0xa9, 0x44, + 0x03, 0x45, 0x04, 0x00, 0x11, 0xe5, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, + 0xef, 0xf0, 0xdf, 0xa1, 0x83, 0x47, 0x04, 0x00, 0x63, 0x94, 0x97, 0x00, 0xef, 0xf0, 0x7f, 0xa6, + 0x05, 0x04, 0xf9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0x25, 0x37, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x05, + 0xf5, 0x00, 0xef, 0xe0, 0xaf, 0xbd, 0x01, 0xa0, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, + 0x22, 0xc4, 0x37, 0x44, 0x20, 0x00, 0x13, 0x06, 0xc0, 0x1f, 0x81, 0x45, 0x13, 0x05, 0x04, 0xe0, + 0x06, 0xc6, 0x26, 0xc2, 0xef, 0x20, 0xb0, 0x6f, 0x13, 0x05, 0x04, 0xe0, 0x93, 0x05, 0xc0, 0x1f, + 0xef, 0x20, 0xb0, 0x67, 0x93, 0x04, 0x04, 0xe0, 0xb2, 0x40, 0x22, 0x44, 0x23, 0xae, 0xa4, 0x1e, + 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x37, 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, + 0xc0, 0x1f, 0x13, 0x04, 0x05, 0xe0, 0x13, 0x05, 0x05, 0xe0, 0x06, 0xc6, 0xef, 0x20, 0xf0, 0x64, + 0x03, 0x27, 0xc4, 0x1f, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xa7, 0x00, 0x93, 0x07, 0x50, 0x05, + 0xb2, 0x40, 0x22, 0x44, 0x3e, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, 0xaa, 0x87, + 0x63, 0x6e, 0xa7, 0x00, 0x13, 0x77, 0x35, 0x00, 0x01, 0x45, 0x11, 0xeb, 0x37, 0x45, 0x20, 0x00, + 0x13, 0x05, 0x05, 0xe0, 0xf1, 0x9b, 0xaa, 0x97, 0x88, 0x43, 0x82, 0x80, 0x01, 0x45, 0x82, 0x80, + 0x93, 0x07, 0xb0, 0x1f, 0x63, 0xec, 0xa7, 0x00, 0x93, 0x77, 0x35, 0x00, 0x81, 0xeb, 0xb7, 0x47, + 0x20, 0x00, 0x71, 0x99, 0x93, 0x87, 0x07, 0xe0, 0x3e, 0x95, 0x0c, 0xc1, 0x82, 0x80, 0x41, 0x11, + 0x37, 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, 0xc0, 0x1f, 0x13, 0x04, 0x05, 0xe0, 0x13, 0x05, + 0x05, 0xe0, 0x06, 0xc6, 0xef, 0x20, 0x70, 0x5d, 0xb2, 0x40, 0x23, 0x2e, 0xa4, 0x1e, 0x22, 0x44, + 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, 0x63, 0x61, 0xa7, 0x02, 0x93, 0x77, 0x35, 0x00, + 0x13, 0x07, 0x50, 0x05, 0x89, 0xef, 0x41, 0x11, 0x06, 0xc6, 0x5d, 0x37, 0xc9, 0x37, 0xb2, 0x40, + 0x13, 0x07, 0xa0, 0x0a, 0x3a, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0x50, 0x05, 0x3a, 0x85, + 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x00, 0x10, 0x71, 0xb2, 0x40, 0xb7, 0x07, 0x00, 0x02, + 0x0d, 0x47, 0xf8, 0xcb, 0x13, 0x05, 0xa0, 0x0a, 0x41, 0x01, 0x82, 0x80, 0x73, 0x00, 0x50, 0x10, + 0x82, 0x80, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x52, 0xcc, 0x06, 0xd6, + 0x2a, 0x84, 0xae, 0x84, 0x32, 0x89, 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x07, 0x39, 0x41, 0x33, 0x05, + 0x34, 0x01, 0x63, 0x6c, 0xfa, 0x02, 0x71, 0x56, 0x93, 0x57, 0x29, 0x00, 0xb3, 0x87, 0xc7, 0x02, + 0x93, 0x75, 0xc9, 0xff, 0x33, 0x05, 0xb4, 0x00, 0xae, 0x94, 0x33, 0x86, 0x27, 0x01, 0x11, 0xc6, + 0x9c, 0x40, 0x6c, 0x00, 0x3e, 0xc6, 0xef, 0x20, 0xd0, 0x56, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, + 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0xb3, 0x87, 0x34, 0x01, 0x9c, 0x43, + 0x11, 0x46, 0x6c, 0x00, 0x3e, 0xc6, 0x91, 0x09, 0xef, 0x20, 0xb0, 0x54, 0x7d, 0xb7, 0x79, 0x71, + 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x52, 0xcc, 0x06, 0xd6, 0x2a, 0x84, 0xae, 0x84, + 0x32, 0x89, 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x07, 0x39, 0x41, 0xb3, 0x85, 0x34, 0x01, 0x63, 0x6d, + 0xfa, 0x02, 0x71, 0x56, 0x93, 0x57, 0x29, 0x00, 0xb3, 0x87, 0xc7, 0x02, 0x93, 0x75, 0xc9, 0xff, + 0x2e, 0x94, 0xa6, 0x95, 0x33, 0x86, 0x27, 0x01, 0x01, 0xca, 0x1c, 0x40, 0x68, 0x00, 0x3e, 0xc6, + 0xef, 0x20, 0x30, 0x50, 0xb2, 0x47, 0x1c, 0xc0, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, + 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0x11, 0x46, 0x68, 0x00, 0xef, 0x20, 0x70, 0x4e, + 0x32, 0x47, 0xb3, 0x07, 0x34, 0x01, 0x91, 0x09, 0x98, 0xc3, 0x75, 0xb7, 0x41, 0x11, 0x22, 0xc4, + 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x6f, 0x9c, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, + 0x50, 0x05, 0x23, 0xa6, 0xe7, 0xf6, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa8, 0x87, 0xf6, 0x22, 0x44, + 0xb2, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x8a, 0x07, 0xa8, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xa4, + 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, 0x99, 0x37, 0x35, + 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0xa2, 0x85, 0x13, 0x06, 0xe0, 0x0f, 0x13, 0x05, 0x45, 0xa9, + 0x23, 0x8a, 0x07, 0xb8, 0xef, 0x20, 0xf0, 0x47, 0x22, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, + 0x6f, 0xf0, 0xbf, 0xb2, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x19, 0xe1, + 0xef, 0xe0, 0xcf, 0x95, 0xb7, 0x34, 0x20, 0x00, 0x83, 0xc7, 0x44, 0xb9, 0x99, 0xcb, 0x37, 0x35, + 0x20, 0x00, 0x13, 0x06, 0xe0, 0x0f, 0x93, 0x85, 0x44, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0xef, 0x20, + 0x50, 0x44, 0xa2, 0x85, 0x13, 0x85, 0x44, 0xb9, 0x13, 0x06, 0xe0, 0x0f, 0xef, 0x20, 0x70, 0x43, + 0x22, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x92, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0x1f, 0xae, 0xb7, 0x37, + 0x20, 0x00, 0x03, 0xa5, 0xc7, 0xf6, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, + 0x13, 0x04, 0xc4, 0xf6, 0x26, 0xc2, 0x04, 0x40, 0x06, 0xc6, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x89, + 0xf4, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, + 0x37, 0x35, 0x20, 0x00, 0x13, 0x05, 0x45, 0xb9, 0xef, 0xf0, 0x3f, 0xaa, 0xe3, 0x13, 0x95, 0xfe, + 0x93, 0x07, 0x50, 0x05, 0x1c, 0xc0, 0xc5, 0xb7, 0x37, 0x35, 0x20, 0x00, 0x83, 0x47, 0x45, 0xa9, + 0x85, 0xc3, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xc7, 0x47, 0xb9, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, + 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf6, 0x13, 0x05, 0x45, 0xa9, 0x6f, 0xf0, 0xff, 0xa6, + 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xdf, 0x99, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x04, 0xf5, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, + 0x6d, 0x71, 0x23, 0x26, 0x11, 0x10, 0x23, 0x24, 0x81, 0x10, 0x23, 0x22, 0x91, 0x10, 0xef, 0xf0, + 0xdf, 0x98, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x04, 0x2a, 0x84, 0xef, 0xf0, 0x5f, 0x9c, + 0x63, 0x1b, 0x85, 0x06, 0xef, 0xf0, 0xdf, 0xa1, 0x83, 0x46, 0x05, 0x00, 0x93, 0x07, 0x20, 0x0a, + 0x2a, 0x84, 0x63, 0x80, 0xf6, 0x02, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, + 0x10, 0x00, 0x13, 0x06, 0xc6, 0x66, 0x93, 0x85, 0xc5, 0x67, 0x13, 0x05, 0x45, 0x64, 0xef, 0xf0, + 0x6f, 0xeb, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xf7, 0x22, 0x85, 0x82, 0x97, 0xef, 0xf0, + 0xff, 0xaa, 0xef, 0xf0, 0xdf, 0xa8, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x14, 0xf5, 0x08, + 0xef, 0xf0, 0x7f, 0x91, 0x63, 0x10, 0x85, 0x08, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xf6, + 0x63, 0x94, 0xa7, 0x04, 0x03, 0x24, 0x81, 0x10, 0x83, 0x20, 0xc1, 0x10, 0x83, 0x24, 0x41, 0x10, + 0x51, 0x61, 0x6f, 0xf0, 0x7f, 0xee, 0xef, 0xf0, 0xbf, 0x97, 0x81, 0x44, 0x63, 0x14, 0x85, 0x00, + 0x93, 0x04, 0xc0, 0x07, 0xef, 0xf0, 0x5f, 0x98, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, + 0xdd, 0xd4, 0x0a, 0x85, 0x23, 0x00, 0x91, 0x00, 0xa3, 0x00, 0x01, 0x00, 0xef, 0xf0, 0x5f, 0xe3, + 0x79, 0xbf, 0x93, 0x04, 0xc0, 0x07, 0xf5, 0xb7, 0xb7, 0x35, 0x20, 0x00, 0x83, 0xc7, 0x45, 0xb9, + 0x95, 0xc3, 0x03, 0x24, 0x81, 0x10, 0x83, 0x20, 0xc1, 0x10, 0x83, 0x24, 0x41, 0x10, 0x37, 0x35, + 0x20, 0x00, 0x13, 0x06, 0xe0, 0x0f, 0x93, 0x85, 0x45, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0x51, 0x61, + 0x6f, 0x20, 0x30, 0x2a, 0x83, 0x20, 0xc1, 0x10, 0x03, 0x24, 0x81, 0x10, 0x83, 0x24, 0x41, 0x10, + 0x51, 0x61, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x23, 0xa2, 0x07, 0x00, 0x21, 0x65, 0x6f, 0x20, + 0xc0, 0x1c, 0x41, 0x11, 0x21, 0x65, 0x06, 0xc6, 0xef, 0x20, 0x60, 0x1b, 0xb2, 0x40, 0xb7, 0x07, + 0x01, 0x04, 0x05, 0x47, 0xd8, 0xc3, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, + 0x06, 0xc6, 0x93, 0x07, 0x70, 0x02, 0x2a, 0x84, 0xae, 0x84, 0x63, 0xf4, 0xa7, 0x00, 0xef, 0xd0, + 0xff, 0xf4, 0x37, 0x05, 0x01, 0x04, 0x0a, 0x04, 0x13, 0x05, 0x05, 0x10, 0x2a, 0x94, 0x04, 0xc0, + 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x13, 0x87, + 0x07, 0x10, 0x93, 0x87, 0x07, 0x1a, 0x23, 0x20, 0x07, 0x00, 0x11, 0x07, 0xe3, 0x1d, 0xf7, 0xfe, + 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0xc8, 0xcb, 0x82, 0x80, 0x42, 0x05, 0xb7, 0x07, 0x01, 0x04, + 0xc8, 0xcb, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x88, 0x4b, 0x13, 0x75, 0xf5, 0x0f, 0x82, 0x80, + 0x89, 0x67, 0x37, 0x07, 0x01, 0x04, 0x8d, 0x07, 0x1c, 0xc7, 0x23, 0x2a, 0x07, 0x00, 0x82, 0x80, + 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0x2a, 0x84, 0xad, 0x37, 0xb7, 0x07, 0x01, 0x04, 0x80, 0xcf, + 0xc5, 0x37, 0x65, 0x37, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0xa9, 0xb7, 0xb7, 0x06, 0x01, 0x04, + 0x9c, 0x46, 0x05, 0x45, 0x13, 0xf7, 0x17, 0x00, 0x1d, 0xc7, 0x13, 0xf7, 0x07, 0x40, 0x0d, 0x45, + 0x1d, 0xe3, 0x98, 0x4a, 0x13, 0x77, 0xf7, 0x0f, 0x19, 0xcf, 0x13, 0xf7, 0x27, 0x20, 0x09, 0x45, + 0x19, 0xeb, 0x13, 0xd7, 0xb7, 0x00, 0x05, 0x8b, 0x11, 0x45, 0x11, 0xe7, 0x13, 0xd5, 0x87, 0x00, + 0x13, 0x45, 0x15, 0x00, 0x05, 0x89, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x88, 0xcf, 0x82, 0x80, + 0x01, 0x11, 0x22, 0xcc, 0x06, 0xce, 0x33, 0x07, 0xb6, 0x00, 0x93, 0x07, 0x00, 0x09, 0x2e, 0x84, + 0x63, 0xf8, 0xe7, 0x00, 0x32, 0xc6, 0x2a, 0xc4, 0xef, 0xd0, 0x5f, 0xe7, 0x32, 0x46, 0x22, 0x45, + 0xb7, 0x15, 0x01, 0x04, 0xa2, 0x95, 0xef, 0xf0, 0xdf, 0xbb, 0xf2, 0x40, 0x62, 0x44, 0x13, 0x05, + 0xa0, 0x0a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, 0x26, 0xca, 0x06, 0xce, 0x33, 0x07, + 0xb6, 0x00, 0x93, 0x07, 0x00, 0x08, 0xaa, 0x84, 0x2e, 0x84, 0x63, 0xf6, 0xe7, 0x00, 0x32, 0xc6, + 0xef, 0xd0, 0xdf, 0xe3, 0x32, 0x46, 0x37, 0x25, 0x01, 0x04, 0x13, 0x05, 0x05, 0x80, 0x22, 0x95, + 0x62, 0x44, 0xf2, 0x40, 0xa6, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x6f, 0xf0, 0x5f, 0xbe, 0x39, 0x71, + 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, + 0x10, 0x00, 0x13, 0x06, 0x06, 0x68, 0x93, 0x85, 0x05, 0x69, 0x13, 0x05, 0x45, 0x69, 0x06, 0xde, + 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, + 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xf0, 0xcf, 0xc5, 0xef, 0xe0, 0xcf, 0xc8, + 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, + 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, + 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x09, 0x65, 0x6f, 0x10, 0x70, 0x7f, 0x09, 0x65, 0x6f, 0x10, + 0xd0, 0x7f, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xd0, 0x1f, 0xda, + 0xdd, 0x37, 0xb7, 0x07, 0x00, 0x07, 0x83, 0x46, 0x14, 0x00, 0xd8, 0x43, 0x83, 0x47, 0x04, 0x00, + 0xa2, 0x06, 0xdd, 0x8e, 0x83, 0x47, 0x24, 0x00, 0xc2, 0x07, 0xdd, 0x8e, 0x83, 0x47, 0x34, 0x00, + 0xe2, 0x07, 0xd5, 0x8f, 0x93, 0x06, 0xf0, 0x0f, 0x63, 0x85, 0xd7, 0x00, 0x61, 0x9b, 0x9d, 0x8b, + 0x5d, 0x8f, 0x93, 0x77, 0x77, 0xff, 0x03, 0x47, 0x44, 0x00, 0x83, 0x46, 0x94, 0x00, 0xb2, 0x40, + 0x0e, 0x07, 0x21, 0x8b, 0x5d, 0x8f, 0xfd, 0x77, 0xbd, 0x07, 0x7d, 0x8f, 0x83, 0x47, 0x54, 0x00, + 0x92, 0x07, 0x5d, 0x8f, 0xb7, 0x17, 0x80, 0xff, 0xfd, 0x17, 0x7d, 0x8f, 0x83, 0x47, 0xa4, 0x00, + 0xa2, 0x07, 0xd5, 0x8f, 0xb2, 0x07, 0xb7, 0xf6, 0x7f, 0x00, 0xf5, 0x8f, 0xd9, 0x8f, 0x37, 0x07, + 0x80, 0xf8, 0x7d, 0x17, 0xf9, 0x8f, 0x03, 0x47, 0x74, 0x00, 0xb7, 0x06, 0x80, 0x07, 0x5e, 0x07, + 0x75, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x00, 0x88, 0x7d, 0x17, 0xf9, 0x8f, 0x03, 0x47, 0x64, 0x00, + 0xb7, 0x06, 0x00, 0x78, 0x22, 0x44, 0x6e, 0x07, 0x75, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x00, 0x07, + 0x5c, 0xc3, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x87, 0xf7, 0x82, 0x80, + 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, + 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x13, 0x05, + 0xa0, 0x0a, 0x89, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x89, 0x65, 0x37, 0x35, + 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x65, 0xba, 0x6f, 0xf0, 0xbf, 0x8c, 0x41, 0x11, + 0xb7, 0x07, 0x08, 0x05, 0x22, 0xc4, 0x03, 0xa4, 0xc7, 0x20, 0x37, 0x07, 0x00, 0x04, 0x06, 0xc6, + 0x26, 0xc2, 0xb3, 0x76, 0xe4, 0x00, 0x91, 0xca, 0x37, 0x55, 0x10, 0x00, 0x23, 0xa6, 0xe7, 0x20, + 0xa5, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xf0, 0x4f, 0xb7, 0xb7, 0x07, 0x80, 0x6b, 0xe1, 0x8f, + 0x95, 0xcb, 0x37, 0x07, 0x08, 0x05, 0x23, 0x26, 0xf7, 0x20, 0xb7, 0x07, 0x00, 0x68, 0x7d, 0x8c, + 0x93, 0x04, 0x50, 0x05, 0x11, 0xc8, 0x37, 0x55, 0x10, 0x00, 0x9d, 0x45, 0x13, 0x05, 0x85, 0x69, + 0xef, 0xf0, 0xaf, 0xb4, 0xef, 0xd0, 0x9f, 0xc5, 0xb2, 0x40, 0x22, 0x44, 0x26, 0x85, 0x92, 0x44, + 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0xf7, 0x84, 0x43, 0x13, 0x07, + 0xa0, 0x0a, 0x63, 0x96, 0xe4, 0x00, 0x13, 0x07, 0x50, 0x05, 0x98, 0xc3, 0xe1, 0xbf, 0x93, 0x04, + 0xa0, 0x0a, 0xd9, 0xbf, 0x81, 0x47, 0xb7, 0x05, 0x08, 0x05, 0x13, 0x07, 0x00, 0x20, 0xb3, 0x86, + 0xb7, 0x00, 0x90, 0x42, 0xb3, 0x06, 0xf5, 0x00, 0x91, 0x07, 0x90, 0xc2, 0xe3, 0x99, 0xe7, 0xfe, + 0x6f, 0xf0, 0xff, 0xf5, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0x2a, 0x84, 0xef, 0xf0, 0x1f, 0xf4, + 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf6, 0x8d, 0x47, 0x33, 0x95, + 0x87, 0x00, 0xb7, 0xb7, 0xaa, 0x02, 0x93, 0x87, 0xa7, 0xaa, 0x3d, 0x8d, 0xb7, 0x07, 0x08, 0x05, + 0x23, 0xa4, 0xa7, 0x20, 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, + 0x65, 0xb8, 0xef, 0xf0, 0x2f, 0xfe, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0xf1, + 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x9f, 0xef, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf7, + 0x37, 0x07, 0x08, 0x05, 0x13, 0x05, 0x00, 0x20, 0xf9, 0x9b, 0x23, 0x22, 0xf7, 0x20, 0xef, 0x10, + 0xd0, 0x5e, 0xb2, 0x40, 0x39, 0x45, 0x41, 0x01, 0x6f, 0x10, 0xf0, 0x5f, 0x37, 0x37, 0x20, 0x00, + 0x13, 0x07, 0x47, 0xf7, 0x1c, 0x43, 0x93, 0xf7, 0xf7, 0xfd, 0x1c, 0xc3, 0x37, 0x07, 0x08, 0x05, + 0x23, 0x22, 0xf7, 0x20, 0x82, 0x80, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf7, 0x1c, 0x43, + 0x93, 0xe7, 0x07, 0x02, 0x1c, 0xc3, 0x37, 0x07, 0x08, 0x05, 0x23, 0x22, 0xf7, 0x20, 0x82, 0x80, + 0x33, 0x87, 0xc5, 0x00, 0xb7, 0x07, 0x08, 0x00, 0x63, 0x7c, 0xf7, 0x06, 0x01, 0x11, 0x22, 0xcc, + 0x26, 0xca, 0x4e, 0xc6, 0x06, 0xce, 0x4a, 0xc8, 0x93, 0xf4, 0x35, 0x00, 0xaa, 0x89, 0x2e, 0x84, + 0x13, 0x05, 0x50, 0x05, 0x9d, 0xec, 0x32, 0x89, 0xef, 0xf0, 0x5f, 0xe7, 0xb7, 0x37, 0x20, 0x00, + 0x03, 0xa7, 0x47, 0xf7, 0xb7, 0x06, 0x08, 0x05, 0xb7, 0x05, 0x00, 0x05, 0x13, 0x67, 0x27, 0x00, + 0x23, 0xa2, 0xe6, 0x20, 0x93, 0x87, 0x47, 0xf7, 0x0d, 0x47, 0x2e, 0x94, 0xb3, 0x06, 0x99, 0x40, + 0x63, 0x60, 0xd7, 0x02, 0x98, 0x43, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x05, 0xa0, 0x0a, 0x23, 0xa2, + 0xe7, 0x20, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, + 0xb3, 0x06, 0x94, 0x00, 0x90, 0x42, 0xb3, 0x86, 0x99, 0x00, 0x91, 0x04, 0x90, 0xc2, 0xf9, 0xb7, + 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, 0xaa, 0x85, 0x11, 0x46, 0x68, 0x00, 0x06, 0xce, + 0xef, 0xf0, 0x1f, 0xf7, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x00, 0x32, 0x45, 0xf2, 0x40, + 0x05, 0x61, 0x82, 0x80, 0x01, 0x45, 0xe5, 0xbf, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xef, 0xa7, 0x02, + 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x8d, 0xe3, + 0xae, 0x84, 0xef, 0xf0, 0xbf, 0xdd, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x22, 0x44, + 0xb2, 0x40, 0x23, 0xaa, 0x97, 0x20, 0x92, 0x44, 0x01, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x9f, 0xe7, + 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, + 0x26, 0xc2, 0x06, 0xc6, 0xaa, 0x84, 0x2e, 0x84, 0x45, 0x3f, 0x26, 0x85, 0xef, 0xf0, 0xbf, 0xf8, + 0x63, 0x09, 0x85, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, + 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xcd, 0xbf, 0x01, 0x11, 0x22, 0xcc, 0x2e, 0xc6, 0x06, 0xce, + 0x2a, 0x84, 0xef, 0xf0, 0x5f, 0xf6, 0xb2, 0x45, 0x63, 0x03, 0xb5, 0x02, 0xfd, 0x57, 0x63, 0x1a, + 0xf5, 0x00, 0x63, 0x8e, 0xa5, 0x00, 0x22, 0x85, 0x62, 0x44, 0xf2, 0x40, 0x05, 0x61, 0x6f, 0xf0, + 0xff, 0xfa, 0x13, 0x05, 0x50, 0x05, 0xf2, 0x40, 0x62, 0x44, 0x05, 0x61, 0x82, 0x80, 0x13, 0x05, + 0xa0, 0x0a, 0xd5, 0xbf, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe0, 0xb7, 0x04, 0x41, 0x11, 0x22, 0xc4, + 0x26, 0xc2, 0x06, 0xc6, 0x93, 0xf7, 0xf5, 0x1f, 0xaa, 0x84, 0x2e, 0x84, 0x13, 0x05, 0x50, 0x05, + 0x99, 0xef, 0xef, 0xf0, 0xbf, 0xd2, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x39, 0x45, + 0xef, 0xf0, 0x5f, 0xdd, 0x26, 0x85, 0xef, 0xf0, 0xff, 0xda, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, + 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, + 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xfb, + 0xb7, 0x00, 0x81, 0x44, 0xf2, 0x40, 0x62, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x26, 0x85, 0xd2, 0x44, + 0x05, 0x61, 0x82, 0x80, 0x93, 0xf4, 0xf5, 0x1f, 0x2e, 0x84, 0xe5, 0xf4, 0x2a, 0x89, 0xef, 0xf0, + 0xff, 0xcc, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x41, 0x45, 0xef, 0xf0, 0x9f, 0xd7, + 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x17, 0xf5, 0xfc, 0x37, 0x34, 0x20, 0x00, 0x13, 0x05, 0x44, 0xc9, + 0xef, 0xf0, 0x5f, 0xd4, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x87, 0x07, 0x20, 0x23, 0xa0, 0x07, 0x00, + 0x91, 0x07, 0xe3, 0x9d, 0xe7, 0xfe, 0x93, 0x09, 0x44, 0xc9, 0x03, 0xd6, 0xc9, 0x1f, 0x93, 0x07, + 0xc0, 0x1d, 0x63, 0xfa, 0xc7, 0x00, 0x37, 0x55, 0x10, 0x00, 0x99, 0x45, 0x13, 0x05, 0x85, 0x69, + 0xef, 0xf0, 0xaf, 0x82, 0x41, 0xbf, 0x93, 0x05, 0x44, 0xc9, 0x4a, 0x85, 0xef, 0x20, 0x60, 0x43, + 0x83, 0xd4, 0xc9, 0x1f, 0x41, 0xb7, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe7, 0xa7, 0x04, 0x41, 0x11, + 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x13, 0x05, 0x50, 0x05, + 0x9d, 0xe7, 0xef, 0xf0, 0xbf, 0xc4, 0x85, 0x67, 0xb7, 0x04, 0x08, 0x05, 0x93, 0x87, 0x97, 0x82, + 0x23, 0xa2, 0xf4, 0x20, 0x23, 0xac, 0x84, 0x20, 0x39, 0x45, 0xef, 0xf0, 0xbf, 0xce, 0xb7, 0x37, + 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf7, 0x13, 0x05, 0xa0, 0x0a, 0x23, 0xa2, 0xf4, 0x20, 0xb2, 0x40, + 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x0d, 0x65, + 0x01, 0x11, 0x13, 0x05, 0x05, 0x20, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, + 0xef, 0x10, 0xf0, 0x2f, 0x39, 0x45, 0xef, 0x10, 0x50, 0x31, 0x13, 0x05, 0x80, 0x07, 0x37, 0x39, + 0x20, 0x00, 0xef, 0xf0, 0x6f, 0xb9, 0x93, 0x09, 0x49, 0xf7, 0x83, 0xa7, 0x09, 0x00, 0x37, 0x04, + 0x08, 0x05, 0x93, 0x04, 0x04, 0x20, 0xdc, 0xc0, 0xb7, 0x07, 0x46, 0x00, 0x85, 0x07, 0xdc, 0xcc, + 0x85, 0x67, 0x93, 0x87, 0x57, 0x86, 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, 0xdc, 0xc0, 0x93, 0x85, + 0x05, 0x71, 0x13, 0x05, 0x05, 0xb9, 0xef, 0xf0, 0xef, 0xc8, 0xb7, 0x07, 0x40, 0x08, 0x9c, 0xc8, + 0xdc, 0x40, 0x01, 0x45, 0x13, 0x09, 0x49, 0xf7, 0x93, 0xe7, 0x07, 0x18, 0x23, 0xa0, 0xf9, 0x00, + 0xef, 0xf0, 0x7f, 0xf3, 0x93, 0x07, 0x04, 0x10, 0x98, 0x43, 0xb7, 0x67, 0xa5, 0xf0, 0x93, 0x87, + 0xf7, 0xa0, 0x63, 0x05, 0xf7, 0x02, 0x37, 0x55, 0x10, 0x00, 0x95, 0x45, 0x13, 0x05, 0x85, 0x69, + 0xef, 0xe0, 0xbf, 0xf2, 0x41, 0x67, 0x7d, 0x17, 0x93, 0x07, 0x04, 0x18, 0xb8, 0xd3, 0xf8, 0xd3, + 0xb8, 0xd7, 0xf8, 0xd7, 0xb8, 0xdb, 0xf8, 0xdb, 0xb8, 0xdf, 0xf8, 0xdf, 0x51, 0x45, 0xef, 0xf0, + 0x7f, 0xc1, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x91, 0x8b, 0x91, 0xeb, 0x37, 0x55, + 0x10, 0x00, 0x91, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, 0x3f, 0xef, 0xef, 0xd0, 0x1f, 0x80, + 0xb7, 0x07, 0x08, 0x05, 0x37, 0x07, 0x40, 0x00, 0x23, 0xa6, 0xe7, 0x20, 0x03, 0x27, 0x09, 0x00, + 0xf2, 0x40, 0x62, 0x44, 0x23, 0xa2, 0xe7, 0x20, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, + 0x82, 0x80, 0x85, 0x67, 0x37, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0x86, 0x23, 0x2a, 0xf7, 0xf6, + 0x37, 0x37, 0x20, 0x00, 0x93, 0x07, 0x50, 0x05, 0x23, 0x2c, 0xf7, 0xf6, 0x37, 0x37, 0x20, 0x00, + 0x23, 0x2e, 0xf7, 0xf6, 0x6f, 0xf0, 0xbf, 0xee, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe0, 0xa7, 0x06, + 0x41, 0x11, 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x13, 0x05, + 0x50, 0x05, 0xa1, 0xe3, 0xae, 0x84, 0xef, 0xf0, 0x7f, 0xad, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, + 0x87, 0x20, 0x01, 0x47, 0x93, 0x06, 0x00, 0x20, 0xb3, 0x85, 0xe4, 0x00, 0x8c, 0x41, 0x33, 0x06, + 0xf7, 0x00, 0x11, 0x07, 0x0c, 0xc2, 0xe3, 0x19, 0xd7, 0xfe, 0x7d, 0x57, 0x93, 0x87, 0x07, 0x20, + 0xf8, 0xc3, 0xb8, 0xc7, 0xf8, 0xc7, 0xb8, 0xcb, 0x29, 0x45, 0xef, 0xf0, 0xbf, 0xb5, 0x13, 0x05, + 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, + 0x82, 0x80, 0xaa, 0x85, 0x37, 0x05, 0x08, 0x05, 0x41, 0x46, 0x13, 0x05, 0x05, 0x26, 0x6f, 0xf0, + 0x0f, 0xd0, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xef, 0xa7, 0x0a, 0x01, 0x11, 0x26, 0xca, 0x93, 0x77, + 0xf5, 0x1f, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x56, 0xc2, 0xaa, 0x84, + 0x13, 0x05, 0x50, 0x05, 0xd9, 0xe7, 0x93, 0x07, 0xc0, 0x1d, 0x32, 0x89, 0x63, 0xe3, 0xc7, 0x08, + 0xb6, 0x89, 0x37, 0x34, 0x20, 0x00, 0x2e, 0x8a, 0xef, 0xf0, 0x5f, 0xa4, 0x13, 0x06, 0x00, 0x20, + 0x81, 0x45, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x80, 0x23, 0x4a, 0x86, 0xd2, 0x85, 0x13, 0x05, + 0x44, 0xc9, 0xef, 0x20, 0x00, 0x1f, 0x4e, 0x85, 0xef, 0xf0, 0xbf, 0xf9, 0x93, 0x0a, 0x44, 0xc9, + 0xb7, 0x07, 0x08, 0x05, 0x23, 0x9e, 0x2a, 0x1f, 0x13, 0x07, 0x44, 0xc9, 0x93, 0x86, 0x07, 0x20, + 0x10, 0x43, 0x11, 0x07, 0x90, 0xc3, 0x91, 0x07, 0xe3, 0x9c, 0xd7, 0xfe, 0x13, 0x06, 0x00, 0x20, + 0x81, 0x45, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x80, 0x1f, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, + 0x97, 0x20, 0x31, 0x45, 0xef, 0xf0, 0x1f, 0xaa, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, + 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x69, 0x8d, 0x45, 0xef, 0xe0, 0x1f, 0xd8, 0x13, 0x05, + 0x50, 0x05, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, + 0x05, 0x61, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xeb, + 0xa7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0xf5, 0x1f, 0x2a, 0x84, 0x89, 0xef, + 0xef, 0xf0, 0xdf, 0x99, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x22, 0x44, 0xb2, 0x40, + 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x1f, 0xa4, 0xb2, 0x40, 0x22, 0x44, 0x13, 0x05, 0x50, 0x05, + 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, + 0x37, 0x04, 0x08, 0x05, 0x23, 0x2c, 0xa4, 0x20, 0xef, 0xf0, 0x5f, 0x96, 0xb7, 0x37, 0x20, 0x00, + 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf6, 0xb7, 0xb7, 0xaa, 0x02, 0x93, 0x87, 0x67, 0xaa, + 0xb2, 0x40, 0x23, 0x24, 0xf4, 0x20, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, + 0xef, 0xf0, 0xdf, 0x93, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf6, + 0xb2, 0x40, 0xb7, 0xb7, 0xa6, 0x02, 0x37, 0x07, 0x08, 0x05, 0x93, 0x87, 0xa7, 0xaa, 0x23, 0x24, + 0xf7, 0x20, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x3e, 0xcc, 0xb7, 0x07, 0x08, 0x05, 0x3a, 0xce, + 0x03, 0xa7, 0xc7, 0x20, 0x36, 0xd0, 0xb7, 0x06, 0x40, 0x00, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, + 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, + 0x7a, 0xc2, 0x7e, 0xc0, 0x75, 0x8f, 0x05, 0xcf, 0x23, 0xa6, 0xd7, 0x20, 0x13, 0x07, 0xa0, 0x0a, + 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0xe7, 0xf6, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, + 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, + 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x03, 0xa7, + 0xc7, 0x20, 0xb7, 0x06, 0x00, 0x08, 0x37, 0x55, 0x10, 0x00, 0x75, 0x8f, 0x0d, 0xc3, 0x23, 0xa6, + 0xd7, 0x20, 0x85, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, 0x3f, 0xc4, 0xb7, 0x37, 0x20, 0x00, + 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xae, 0xe7, 0xf6, 0xef, 0xd0, 0x1f, 0xbf, 0x75, 0xb7, 0x89, 0x45, + 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, 0x7f, 0xc2, 0xb7, 0x07, 0x02, 0x00, 0x73, 0xb0, 0x47, 0x30, + 0xe5, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa0, 0xe7, 0xf8, 0x82, 0x80, + 0x99, 0x47, 0x63, 0x05, 0xf5, 0x02, 0x9d, 0x47, 0x63, 0x0b, 0xf5, 0x00, 0x95, 0x47, 0x63, 0x15, + 0xf5, 0x02, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xf7, 0xf7, 0xf7, 0x29, 0xa8, 0xb7, 0x37, + 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa0, 0xe7, 0xf8, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, + 0x7c, 0x43, 0x93, 0xe7, 0x07, 0x08, 0x7c, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, + 0x07, 0xf8, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, 0xf7, 0x00, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, + 0x93, 0xe7, 0x07, 0x08, 0x7c, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf8, + 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, 0xf7, 0x00, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xf7, + 0xf7, 0xf7, 0x7c, 0xc3, 0x82, 0x80, 0x39, 0x71, 0x2a, 0xd6, 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, + 0x13, 0x05, 0xc5, 0x69, 0x85, 0x45, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, + 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, + 0x7e, 0xc0, 0xef, 0xe0, 0x9f, 0xb6, 0xef, 0xd0, 0x3f, 0xb2, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, + 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, + 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, + 0x39, 0x71, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, + 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, + 0x7e, 0xc0, 0xf3, 0x25, 0x20, 0x34, 0xc1, 0x67, 0x37, 0x55, 0x10, 0x00, 0xdd, 0x8d, 0x13, 0x05, + 0xc5, 0x69, 0xef, 0xe0, 0x9f, 0xb0, 0xef, 0xd0, 0x3f, 0xac, 0x01, 0xa0, 0x39, 0x71, 0x2a, 0xd6, + 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, 0x13, 0x05, 0xc5, 0x69, 0x89, 0x45, 0x06, 0xde, 0x16, 0xdc, + 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, + 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0x3f, 0xad, 0xef, 0xd0, 0xdf, 0xa8, + 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, + 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, + 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x07, 0x01, 0x01, 0xb7, 0x07, 0x00, 0x01, 0x13, 0x07, + 0x17, 0x10, 0x98, 0xd3, 0x37, 0x07, 0x03, 0x04, 0x09, 0x07, 0xd8, 0xd3, 0x13, 0x07, 0x50, 0x60, + 0x98, 0xd7, 0x37, 0x17, 0x09, 0x00, 0x13, 0x07, 0x77, 0x80, 0xd8, 0xd7, 0x37, 0x17, 0x0b, 0x0b, + 0x13, 0x07, 0xa7, 0xa0, 0x98, 0xdb, 0x37, 0x17, 0x0c, 0x00, 0x13, 0x07, 0xb7, 0xc0, 0xd8, 0xdb, + 0x37, 0x17, 0x0f, 0x00, 0x13, 0x07, 0xd7, 0xe0, 0x98, 0xdf, 0x05, 0x67, 0xd8, 0xdf, 0xb7, 0x17, + 0xff, 0x7f, 0x93, 0x87, 0x07, 0x80, 0x73, 0xa0, 0x47, 0x30, 0xa1, 0x47, 0x73, 0xa0, 0x07, 0x30, + 0x82, 0x80, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x40, 0x00, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, + 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x80, 0x00, 0x73, 0xb0, + 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, + 0x00, 0x04, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, + 0x3e, 0xc6, 0xb7, 0x07, 0x00, 0x20, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, + 0x20, 0x30, 0x05, 0x65, 0x6f, 0x10, 0xa0, 0x54, 0x05, 0x65, 0x6f, 0x10, 0x00, 0x55, 0x01, 0x11, + 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x06, 0xce, 0x26, 0xca, 0x52, 0xc4, 0x56, 0xc2, 0x9d, 0x47, + 0x2a, 0x84, 0xae, 0x89, 0x32, 0x89, 0x63, 0xd4, 0xc7, 0x00, 0xef, 0xd0, 0x2f, 0xae, 0xef, 0xf0, + 0x5f, 0xfd, 0xb7, 0x07, 0x01, 0x07, 0x18, 0x40, 0xdc, 0x43, 0x93, 0x06, 0xf0, 0x0f, 0x63, 0x05, + 0xd7, 0x00, 0xf1, 0x9b, 0x0d, 0x8b, 0xd9, 0x8f, 0x13, 0xf7, 0xb7, 0xff, 0x83, 0x47, 0x44, 0x00, + 0x81, 0x44, 0x31, 0x4a, 0x8a, 0x07, 0x91, 0x8b, 0xd9, 0x8f, 0x37, 0x07, 0x01, 0x07, 0x5c, 0xc3, + 0xb7, 0x1a, 0x01, 0x07, 0x63, 0xcf, 0x24, 0x03, 0x14, 0x40, 0x05, 0x47, 0xad, 0x47, 0x63, 0x9e, + 0xe6, 0x00, 0x83, 0x46, 0x44, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0xbd, 0x47, 0x63, 0x97, 0xe6, 0x00, + 0x14, 0x44, 0x37, 0x37, 0x20, 0x00, 0x23, 0x22, 0xd7, 0xf8, 0xf2, 0x40, 0x62, 0x44, 0x37, 0x07, + 0x01, 0x07, 0x5c, 0xc7, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, + 0x82, 0x80, 0xb3, 0x85, 0x44, 0x03, 0x13, 0x95, 0x44, 0x00, 0x31, 0x46, 0x56, 0x95, 0x85, 0x04, + 0xce, 0x95, 0xef, 0xf0, 0xcf, 0x81, 0x7d, 0xb7, 0x1d, 0x71, 0x3e, 0xda, 0xb7, 0x07, 0x01, 0x07, + 0xa2, 0xc6, 0x80, 0x47, 0x86, 0xce, 0x96, 0xcc, 0x9a, 0xca, 0x9e, 0xc8, 0xaa, 0xc4, 0xae, 0xc2, + 0xb2, 0xc0, 0x36, 0xde, 0x3a, 0xdc, 0x42, 0xd8, 0x46, 0xd6, 0x72, 0xd4, 0x76, 0xd2, 0x7a, 0xd0, + 0x7e, 0xce, 0x93, 0x77, 0xb4, 0x00, 0x95, 0xc7, 0xb7, 0x07, 0x00, 0x40, 0x73, 0xb0, 0x47, 0x30, + 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0xa2, 0x86, 0x13, 0x06, + 0x06, 0x6a, 0x93, 0x85, 0x85, 0x6a, 0x13, 0x05, 0x45, 0x64, 0xef, 0xe0, 0xbf, 0x87, 0xef, 0xd0, + 0xbf, 0x8a, 0x93, 0x77, 0x44, 0x00, 0x99, 0xcf, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf8, + 0x91, 0xcb, 0x6c, 0x00, 0x28, 0x00, 0x82, 0x97, 0x22, 0x47, 0xb7, 0x07, 0x01, 0x07, 0x98, 0xcb, + 0x32, 0x47, 0xd8, 0xcb, 0xb7, 0x07, 0x01, 0x07, 0x80, 0xc7, 0x36, 0x44, 0xf6, 0x40, 0xe6, 0x42, + 0x56, 0x43, 0xc6, 0x43, 0x26, 0x45, 0x96, 0x45, 0x06, 0x46, 0xf2, 0x56, 0x62, 0x57, 0xd2, 0x57, + 0x42, 0x58, 0xb2, 0x58, 0x22, 0x5e, 0x92, 0x5e, 0x02, 0x5f, 0xf2, 0x4f, 0x25, 0x61, 0x73, 0x00, + 0x20, 0x30, 0xb7, 0x07, 0x02, 0x04, 0xdc, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, + 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x13, 0x05, 0x00, 0x08, 0x6f, 0x10, 0x40, 0x3d, 0x13, 0x05, + 0x00, 0x08, 0x6f, 0x10, 0x80, 0x3d, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x07, + 0xd0, 0x79, 0x37, 0x04, 0x02, 0x04, 0x5c, 0xc4, 0x85, 0x44, 0x95, 0x65, 0x37, 0x35, 0x10, 0x00, + 0x04, 0xc4, 0x93, 0x85, 0x05, 0xe2, 0x13, 0x05, 0x25, 0x6d, 0xef, 0xe0, 0x7f, 0xca, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x13, 0xf5, 0x02, 0x54, 0x44, 0x63, 0x82, 0x96, 0x02, 0x37, 0x56, 0x10, 0x00, + 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x6a, 0x93, 0x85, 0x45, 0x6b, + 0x13, 0x05, 0x05, 0x62, 0xef, 0xe0, 0x0f, 0xfb, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, + 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xdf, 0xf8, 0xb2, 0x40, + 0xb7, 0x07, 0x02, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x05, 0x45, + 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xef, 0xe0, 0x3f, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, + 0xa0, 0x0a, 0x23, 0xa4, 0xe7, 0xf8, 0x89, 0x46, 0x37, 0x07, 0x02, 0x02, 0x54, 0xc7, 0x13, 0x84, + 0x87, 0xf8, 0x93, 0x04, 0x50, 0x05, 0xef, 0xe0, 0x9f, 0xc2, 0x1c, 0x40, 0xe3, 0x9d, 0x97, 0xfe, + 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x02, 0x02, 0xc8, 0xcb, + 0x05, 0x47, 0xd8, 0xc7, 0xd8, 0x53, 0x69, 0x8f, 0x63, 0x1e, 0xa7, 0x00, 0xd4, 0x57, 0x7d, 0x55, + 0xf9, 0x8e, 0x91, 0xea, 0x94, 0x57, 0x75, 0x8f, 0x19, 0xe7, 0x88, 0x47, 0x05, 0x89, 0x33, 0x05, + 0xa0, 0x40, 0x82, 0x80, 0x7d, 0x55, 0x82, 0x80, 0x41, 0x45, 0x6f, 0x10, 0x00, 0x2f, 0x41, 0x45, + 0x6f, 0x10, 0xe0, 0x2d, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, 0x2a, 0xc6, 0xef, 0xf0, 0x3f, 0xff, + 0x13, 0x07, 0x50, 0x05, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0xe7, 0xf8, 0x37, 0x04, 0x02, 0x02, + 0xa1, 0x47, 0x5c, 0xc4, 0x32, 0x45, 0x85, 0x47, 0x1c, 0xc8, 0x93, 0x07, 0x10, 0x40, 0x5c, 0xc0, + 0xef, 0xf0, 0xbf, 0xf9, 0xef, 0xf0, 0x9f, 0xf5, 0x23, 0x22, 0x04, 0x00, 0x62, 0x44, 0xf2, 0x40, + 0x05, 0x61, 0x6f, 0xf0, 0x7f, 0xfb, 0x41, 0x11, 0x3a, 0xc6, 0x37, 0x07, 0x02, 0x02, 0x3e, 0xc4, + 0x1c, 0x47, 0x1c, 0xc7, 0x85, 0x8b, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, + 0x23, 0xa4, 0xe7, 0xf8, 0x32, 0x47, 0xa2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x37, + 0x20, 0x00, 0x03, 0xa5, 0xc7, 0xf8, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, + 0x35, 0x00, 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xd0, 0x6f, 0x81, 0x89, 0x67, 0x63, 0x64, 0xf4, 0x00, + 0xef, 0xd0, 0xcf, 0x80, 0x37, 0x27, 0x00, 0x06, 0x85, 0x46, 0x09, 0x46, 0x1c, 0x47, 0x9d, 0x8b, + 0x63, 0x86, 0xd7, 0x00, 0x1c, 0x47, 0x9d, 0x8b, 0xe3, 0x9a, 0xc7, 0xfe, 0x37, 0x05, 0x00, 0x06, + 0x2a, 0x94, 0x08, 0x40, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x65, 0xb7, 0x37, + 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x41, 0x11, 0x13, 0x05, 0x05, 0x80, 0x23, 0xa6, 0xe7, 0xf8, + 0x06, 0xc6, 0xef, 0x10, 0xc0, 0x20, 0xb7, 0x27, 0x00, 0x06, 0x9c, 0x47, 0x05, 0x47, 0x9d, 0x8b, + 0xfd, 0x17, 0x63, 0x7b, 0xf7, 0x00, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0x85, 0x6b, + 0xef, 0xe0, 0xaf, 0xe9, 0xef, 0xc0, 0x9f, 0xfa, 0xb7, 0x07, 0x46, 0x00, 0xb2, 0x40, 0x37, 0x27, + 0x00, 0x06, 0x85, 0x07, 0x5c, 0xcf, 0x85, 0x47, 0x5c, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x37, 0x27, + 0x00, 0x06, 0x1c, 0x47, 0x85, 0x46, 0x9d, 0x8b, 0x63, 0x8a, 0xd7, 0x00, 0x14, 0xcb, 0xb7, 0x26, + 0x00, 0x06, 0x05, 0x47, 0x9c, 0x46, 0x9d, 0x8b, 0xe3, 0x9e, 0xe7, 0xfe, 0xb7, 0x27, 0x00, 0x06, + 0x09, 0x47, 0x05, 0x65, 0x98, 0xcb, 0x13, 0x05, 0x05, 0x80, 0x6f, 0x10, 0x00, 0x1b, 0x05, 0x65, + 0x41, 0x11, 0x13, 0x05, 0x05, 0x80, 0x06, 0xc6, 0xef, 0x10, 0x60, 0x19, 0xb2, 0x40, 0xb7, 0x27, + 0x00, 0x06, 0x21, 0x47, 0x98, 0xcb, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, + 0x26, 0xc2, 0xaa, 0x84, 0xef, 0xf0, 0x5f, 0xf1, 0x2a, 0x84, 0x49, 0x22, 0x13, 0x75, 0xf5, 0x0f, + 0xef, 0xe0, 0x1f, 0xa6, 0x26, 0x85, 0xef, 0xf0, 0x3f, 0xf0, 0x63, 0x05, 0xa4, 0x00, 0xef, 0xc0, + 0xff, 0xf1, 0x01, 0x45, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x79, 0x71, + 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x06, 0xd6, 0x52, 0xcc, 0xaa, 0x89, 0x2e, 0x89, + 0x93, 0x74, 0xc6, 0xff, 0x01, 0x44, 0x33, 0x8a, 0x89, 0x00, 0x33, 0x05, 0x89, 0x00, 0x63, 0x1a, + 0x94, 0x00, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, + 0x82, 0x80, 0xef, 0xf0, 0x9f, 0xf9, 0x2a, 0xc6, 0x11, 0x46, 0x6c, 0x00, 0x52, 0x85, 0xef, 0x10, + 0x50, 0x1d, 0x11, 0x04, 0xc9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x1f, 0xf8, 0x2a, 0x87, + 0x85, 0x46, 0x01, 0x45, 0x89, 0x45, 0x01, 0xe7, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x93, 0x77, + 0xf7, 0x00, 0x01, 0x46, 0x81, 0xef, 0x63, 0xd3, 0xc5, 0x00, 0xb6, 0x87, 0x5d, 0x8d, 0x86, 0x06, + 0x13, 0x75, 0xf5, 0x0f, 0x93, 0xf6, 0xf6, 0x0f, 0x11, 0x83, 0xf1, 0xbf, 0x13, 0xf8, 0x17, 0x00, + 0x85, 0x83, 0x42, 0x96, 0x93, 0xf7, 0xf7, 0x0f, 0xf1, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, + 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0xae, 0x84, 0x99, 0xc3, 0xef, 0xc0, 0x1f, 0xe7, + 0x89, 0x67, 0x63, 0x64, 0xf4, 0x00, 0xef, 0xc0, 0x7f, 0xe6, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, + 0x50, 0x05, 0x23, 0xa6, 0xe7, 0xf8, 0xb7, 0x27, 0x00, 0x06, 0x84, 0xcf, 0xc0, 0xcb, 0x22, 0x44, + 0xb2, 0x40, 0x92, 0x44, 0x11, 0x47, 0x98, 0xcb, 0x89, 0x65, 0x37, 0x45, 0x10, 0x00, 0x93, 0x85, + 0x05, 0x71, 0x13, 0x05, 0xe5, 0x84, 0x41, 0x01, 0x6f, 0xe0, 0xdf, 0xa4, 0x39, 0x71, 0x3a, 0xce, + 0x37, 0x27, 0x00, 0x06, 0x3e, 0xcc, 0x1c, 0x47, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, + 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, + 0x7a, 0xc2, 0x7e, 0xc0, 0xa1, 0x8b, 0x85, 0xcf, 0xa1, 0x47, 0x1c, 0xc7, 0xb7, 0x37, 0x20, 0x00, + 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf8, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, + 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, + 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x55, + 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x85, 0x6b, 0xef, 0xe0, 0x2f, 0xcb, 0xef, 0xd0, 0xcf, 0xc6, + 0xe1, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa8, 0xa7, 0xf8, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, + 0x93, 0x87, 0x07, 0xf9, 0x88, 0x43, 0x37, 0x67, 0x19, 0x00, 0x13, 0x07, 0xd7, 0x60, 0x33, 0x05, + 0xe5, 0x02, 0x37, 0xf7, 0x6e, 0x3c, 0x13, 0x07, 0xf7, 0x35, 0x3a, 0x95, 0x88, 0xc3, 0x82, 0x80, + 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf9, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0x87, 0xf9, + 0x9c, 0x4f, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0xc7, 0xf9, + 0x63, 0x84, 0xe7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xfd, 0x77, 0xfd, 0x17, 0xe9, 0x8f, + 0xb7, 0x26, 0x00, 0x08, 0x2e, 0x87, 0xb2, 0x85, 0x63, 0x94, 0xd7, 0x02, 0xb7, 0x37, 0x20, 0x00, + 0x23, 0xaa, 0xa7, 0xf8, 0xb7, 0x37, 0x20, 0x00, 0x37, 0x45, 0x10, 0x00, 0x23, 0xae, 0xe7, 0xf8, + 0x13, 0x05, 0x05, 0xaf, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0xe7, 0xf8, 0x6f, 0xe0, 0x5f, 0x87, + 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0xa7, 0xf8, 0xb7, 0x37, + 0x20, 0x00, 0x37, 0x45, 0x10, 0x00, 0x23, 0xae, 0x07, 0xf8, 0x13, 0x07, 0x00, 0x10, 0xb7, 0x37, + 0x20, 0x00, 0x93, 0x05, 0x80, 0x3e, 0x13, 0x05, 0x05, 0xaf, 0x23, 0xac, 0xe7, 0xf8, 0x6f, 0xe0, + 0x3f, 0x84, 0x37, 0x07, 0x01, 0x02, 0x5c, 0x43, 0xb7, 0x06, 0x05, 0x00, 0xd5, 0x8f, 0x5c, 0xc3, + 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0xb7, 0x27, 0x00, 0x08, 0x37, 0x05, + 0x08, 0x00, 0x63, 0x14, 0xf4, 0x00, 0x37, 0x05, 0x04, 0x00, 0xef, 0x00, 0x50, 0x71, 0x5c, 0x5c, + 0x22, 0x85, 0xb2, 0x40, 0x93, 0xe7, 0x37, 0x00, 0x5c, 0xdc, 0x23, 0x2c, 0x04, 0x00, 0x22, 0x44, + 0x41, 0x01, 0x6f, 0xf0, 0x5f, 0xf9, 0x58, 0x5d, 0xaa, 0x87, 0x75, 0x9b, 0x58, 0xdd, 0x37, 0x27, + 0x00, 0x08, 0x37, 0x05, 0x04, 0x00, 0x63, 0x84, 0xe7, 0x00, 0x37, 0x05, 0x08, 0x00, 0x6f, 0x00, + 0xd0, 0x6e, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x06, 0xd6, 0x4e, 0xce, 0x52, 0xcc, + 0x56, 0xca, 0x2a, 0x89, 0xae, 0x84, 0x32, 0x84, 0x99, 0xe1, 0xef, 0xc0, 0x3f, 0xc8, 0x13, 0x0a, + 0xa0, 0x0a, 0x91, 0x4a, 0x05, 0xe4, 0x83, 0x27, 0x89, 0x01, 0x37, 0x07, 0x11, 0x00, 0x13, 0x05, + 0xa0, 0x0a, 0xf9, 0x8f, 0x99, 0xc3, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, + 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0xd2, 0x4a, 0x45, 0x61, 0x82, 0x80, 0x13, 0x06, 0x80, 0x3e, + 0x85, 0x45, 0x4a, 0x85, 0xef, 0xf0, 0x7f, 0xee, 0xe3, 0x1f, 0x45, 0xfd, 0x83, 0x27, 0x49, 0x02, + 0xa2, 0x89, 0x3e, 0xc6, 0x63, 0xf3, 0x8a, 0x00, 0x91, 0x49, 0x26, 0x85, 0x4e, 0x86, 0x6c, 0x00, + 0xef, 0x10, 0x20, 0x73, 0xce, 0x94, 0x33, 0x04, 0x34, 0x41, 0x6d, 0xb7, 0x41, 0x11, 0x37, 0x05, + 0x02, 0x00, 0x06, 0xc6, 0xef, 0x00, 0xb0, 0x65, 0xb2, 0x40, 0xb7, 0x17, 0x00, 0x08, 0x37, 0x07, + 0x07, 0x00, 0x98, 0xd3, 0x13, 0x05, 0x40, 0x1f, 0x41, 0x01, 0x6f, 0xe0, 0xef, 0xee, 0xb7, 0x17, + 0x00, 0x08, 0x23, 0xa0, 0x07, 0x02, 0x37, 0x05, 0x02, 0x00, 0x6f, 0x00, 0x10, 0x64, 0x39, 0x71, + 0x3e, 0xcc, 0xb7, 0x17, 0x00, 0x08, 0x3a, 0xce, 0x98, 0x57, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, + 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, + 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0x05, 0x8b, 0x05, 0xcb, 0x98, 0x57, 0x13, 0x67, 0x17, 0x00, + 0x98, 0xd7, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, + 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, + 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x98, 0x57, 0x09, 0x8b, 0x09, 0xc7, 0x98, 0x57, + 0x13, 0x67, 0x27, 0x00, 0xf1, 0xb7, 0x98, 0x57, 0x11, 0x8b, 0x09, 0xc7, 0x98, 0x57, 0x13, 0x67, + 0x47, 0x00, 0x7d, 0xbf, 0xb7, 0x07, 0x00, 0x01, 0x73, 0xb0, 0x47, 0x30, 0xef, 0xd0, 0xcf, 0xa1, + 0x4d, 0xbf, 0x37, 0x07, 0x00, 0x02, 0x5c, 0x4f, 0xb7, 0x36, 0x20, 0x00, 0x13, 0xf6, 0x77, 0x00, + 0xe1, 0x9b, 0x23, 0xa0, 0xc6, 0xfa, 0x93, 0xe7, 0x47, 0x00, 0x5c, 0xcf, 0x1c, 0x4f, 0xf9, 0x9b, + 0x1c, 0xcf, 0x82, 0x80, 0x41, 0x11, 0x26, 0xc2, 0xb7, 0x04, 0x00, 0x02, 0x22, 0xc4, 0xc0, 0x4c, + 0x9c, 0x4c, 0x06, 0xc6, 0x13, 0x05, 0x80, 0x07, 0x93, 0xe7, 0x17, 0x00, 0x9c, 0xcc, 0xef, 0xe0, + 0xaf, 0xe1, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xfa, 0x61, 0x98, 0xb2, 0x40, 0x5d, 0x8c, + 0xc0, 0xcc, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x17, 0x05, 0x01, 0x93, 0x17, + 0x85, 0x01, 0xba, 0x97, 0x13, 0x17, 0x85, 0x00, 0xba, 0x97, 0x3e, 0x95, 0xb7, 0x07, 0x00, 0x04, + 0x88, 0xd3, 0xc8, 0xd3, 0x88, 0xd7, 0xc8, 0xd7, 0x88, 0xdb, 0xc8, 0xdb, 0x88, 0xdf, 0xc8, 0xdf, + 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x00, 0x08, 0x98, 0xd3, 0x23, 0xa2, 0x07, 0x02, + 0x0e, 0x05, 0x23, 0xa4, 0x07, 0x02, 0x42, 0x05, 0x23, 0xa6, 0x07, 0x02, 0x41, 0x81, 0x23, 0xa8, + 0x07, 0x02, 0x13, 0x17, 0x85, 0x00, 0xb7, 0x06, 0xff, 0x00, 0x23, 0xaa, 0x07, 0x02, 0x75, 0x8f, + 0x62, 0x05, 0x23, 0xac, 0x07, 0x02, 0x3a, 0x95, 0xc8, 0xdf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, + 0x13, 0x07, 0x00, 0x08, 0x98, 0xd3, 0x23, 0xa2, 0x07, 0x02, 0x23, 0xa4, 0x07, 0x02, 0x23, 0xa6, + 0x07, 0x02, 0x23, 0xa8, 0x07, 0x02, 0x23, 0xaa, 0x07, 0x02, 0x23, 0xac, 0x07, 0x02, 0x23, 0xae, + 0x07, 0x02, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x47, 0xea, 0x82, 0x80, 0xaa, 0x85, + 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0x6f, 0xe0, 0x3f, 0x83, + 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa2, 0xe7, 0xea, 0xb7, 0x07, 0x00, 0x04, + 0xc8, 0xc3, 0x13, 0x07, 0x90, 0x02, 0x85, 0x65, 0x37, 0x45, 0x10, 0x00, 0x98, 0xc7, 0x93, 0x85, + 0x85, 0x38, 0x13, 0x05, 0x45, 0xdf, 0x6f, 0xe0, 0xaf, 0xd8, 0x41, 0x11, 0x22, 0xc4, 0x01, 0x45, + 0x37, 0x34, 0x20, 0x00, 0x06, 0xc6, 0x13, 0x04, 0x44, 0xe9, 0xef, 0xf0, 0x1f, 0xf2, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0xfb, 0x48, 0x44, 0xb7, 0x07, 0x02, 0x00, + 0x95, 0x07, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0xbf, 0xfa, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x05, 0xef, 0xf0, 0xff, 0xf9, 0x48, 0x44, 0xb7, 0x07, 0x00, 0x10, 0x99, 0x07, 0x7e, 0x05, + 0x5d, 0x8d, 0xef, 0xf0, 0xff, 0xf8, 0x48, 0x44, 0xb7, 0x07, 0x01, 0x10, 0x99, 0x07, 0x7e, 0x05, + 0x5d, 0x8d, 0xef, 0xf0, 0xff, 0xf7, 0x22, 0x44, 0xb2, 0x40, 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, + 0x3f, 0xf7, 0x7d, 0x47, 0x63, 0x7e, 0xb7, 0x04, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, + 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0x6f, 0xe0, 0x8f, 0xf8, 0xb3, 0x06, 0xf5, 0x00, 0x83, 0xc6, + 0x06, 0x00, 0x33, 0x07, 0xf1, 0x00, 0x85, 0x07, 0x23, 0x00, 0xd7, 0x00, 0xe3, 0x97, 0xf5, 0xfe, + 0x18, 0x10, 0x93, 0x87, 0x15, 0x00, 0xba, 0x95, 0x13, 0x07, 0x00, 0xf8, 0x23, 0x80, 0xe5, 0xfe, + 0x13, 0x07, 0x00, 0x02, 0x63, 0x92, 0xe7, 0x02, 0x37, 0x05, 0x00, 0x04, 0x8a, 0x85, 0x13, 0x06, + 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0xef, 0xe0, 0x8f, 0xf4, 0xb2, 0x50, 0x45, 0x61, 0x82, 0x80, + 0x79, 0x71, 0x06, 0xd6, 0x81, 0x47, 0xd9, 0xb7, 0xb3, 0x06, 0xf1, 0x00, 0x23, 0x80, 0x06, 0x00, + 0x85, 0x07, 0xc9, 0xbf, 0x37, 0x55, 0x10, 0x00, 0x01, 0x11, 0x13, 0x05, 0x45, 0x6c, 0x06, 0xce, + 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x37, 0x34, 0x20, 0x00, 0xef, 0xf0, + 0x1f, 0xed, 0x93, 0x07, 0x44, 0xe9, 0xc8, 0x47, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, + 0x3f, 0xed, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x10, 0xf5, 0x2e, 0xaa, 0x84, 0x13, 0x05, 0x00, 0x02, + 0xef, 0xf0, 0x3f, 0xe4, 0x13, 0x04, 0x44, 0xe9, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, + 0xef, 0xf0, 0x1f, 0xeb, 0xaa, 0x89, 0x63, 0x10, 0x95, 0x2c, 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, + 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0xbf, 0xe9, 0xaa, 0x84, 0x63, 0x15, 0x35, 0x2b, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x9f, 0xe8, 0xaa, 0x89, 0x63, 0x1c, + 0x95, 0x28, 0x1c, 0x40, 0x48, 0x44, 0x37, 0x0a, 0x00, 0x04, 0x83, 0xc7, 0x07, 0x00, 0x7e, 0x05, + 0x13, 0x65, 0x15, 0x00, 0x93, 0xe7, 0x07, 0x20, 0x23, 0x2c, 0xfa, 0x00, 0xef, 0xf0, 0x5f, 0xe6, + 0xaa, 0x84, 0x63, 0x1a, 0x35, 0x27, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, + 0x3f, 0xe5, 0x2a, 0x89, 0x63, 0x11, 0x95, 0x26, 0xef, 0xf0, 0x5f, 0xe0, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xdf, 0xe3, 0xaa, 0x84, 0x63, 0x16, 0x25, 0x25, 0x13, 0x05, + 0x00, 0x04, 0xef, 0xf0, 0x1f, 0xdb, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x17, 0xef, 0xf0, 0xff, 0xe1, 0x2a, 0x89, 0x63, 0x17, 0x95, 0x22, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xdf, 0xe0, 0xaa, 0x84, 0x63, 0x1e, 0x25, 0x21, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xbf, 0xdf, 0x63, 0x16, 0x95, 0x20, 0x48, 0x44, + 0x93, 0x07, 0x00, 0x10, 0x23, 0x2c, 0xfa, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x15, 0x00, 0xef, 0xf0, + 0x3f, 0xde, 0x93, 0x07, 0xa0, 0x0a, 0xaa, 0x84, 0x63, 0x17, 0xf5, 0x1e, 0x48, 0x44, 0x09, 0x69, + 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x9f, 0xdc, 0xaa, 0x89, 0x63, 0x1c, + 0x95, 0x1c, 0xef, 0xf0, 0xbf, 0xd7, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, + 0x3f, 0xdb, 0xaa, 0x84, 0x63, 0x11, 0x35, 0x1d, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x7f, 0xd2, + 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x5f, 0xd9, + 0xaa, 0x89, 0x63, 0x12, 0x95, 0x1a, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, + 0x3f, 0xd8, 0xaa, 0x84, 0x63, 0x19, 0x35, 0x19, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, + 0xef, 0xf0, 0x1f, 0xd7, 0xaa, 0x89, 0x63, 0x10, 0x95, 0x18, 0x08, 0x40, 0x05, 0x05, 0xef, 0xf0, + 0x1f, 0xd5, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x7f, 0xd5, 0xaa, 0x84, + 0x63, 0x13, 0x35, 0x17, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x5f, 0xd4, + 0x2a, 0x89, 0x63, 0x1a, 0x95, 0x14, 0xef, 0xf0, 0x7f, 0xcf, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x07, 0xef, 0xf0, 0xff, 0xd2, 0xaa, 0x84, 0x63, 0x1f, 0x25, 0x13, 0x13, 0x05, 0x00, 0x04, + 0xef, 0xf0, 0x3f, 0xca, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, + 0xef, 0xf0, 0x1f, 0xd1, 0x63, 0x11, 0x95, 0x12, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, + 0xef, 0xf0, 0x1f, 0xd0, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0x63, 0x16, 0xf5, 0x10, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xbf, 0xce, 0xaa, 0x84, 0x63, 0x1d, 0x25, 0x0f, + 0x13, 0x05, 0x10, 0x02, 0xef, 0xf0, 0xff, 0xc5, 0x1c, 0x40, 0x48, 0x44, 0x21, 0x67, 0x83, 0xc7, + 0x07, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xd9, 0x8f, 0x23, 0x20, 0xfa, 0x02, 0xef, 0xf0, + 0x3f, 0xcc, 0xaa, 0x89, 0x63, 0x19, 0x95, 0x0c, 0x48, 0x44, 0x89, 0x64, 0x8d, 0x04, 0x7e, 0x05, + 0x45, 0x8d, 0xef, 0xf0, 0xff, 0xca, 0x2a, 0x89, 0x63, 0x1f, 0x35, 0x0b, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xdf, 0xc9, 0xaa, 0x89, 0x63, 0x16, 0x25, 0x0b, 0x08, 0x40, + 0x13, 0x05, 0x15, 0x02, 0xef, 0xf0, 0xbf, 0xc7, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, + 0xef, 0xf0, 0x1f, 0xc8, 0x2a, 0x89, 0x63, 0x18, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, 0x45, 0x8d, + 0xef, 0xf0, 0x1f, 0xc7, 0xaa, 0x84, 0x63, 0x10, 0x25, 0x09, 0xef, 0xf0, 0x3f, 0xc2, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0xc5, 0x2a, 0x89, 0x63, 0x15, 0x95, 0x06, + 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0xff, 0xbc, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xc3, 0xaa, 0x84, 0x63, 0x16, 0x25, 0x05, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xbf, 0xc2, 0x63, 0x1e, 0x95, 0x02, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x52, 0xef, 0xf0, 0xbf, 0xc1, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x14, + 0xf5, 0x02, 0x08, 0x40, 0x62, 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, + 0xb7, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x06, 0x13, 0x05, 0x15, 0x06, + 0x05, 0x61, 0x6f, 0xe0, 0x0f, 0xbb, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, + 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x4e, 0xc6, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, + 0x4a, 0xc8, 0x52, 0xc4, 0x93, 0x09, 0x00, 0x04, 0x63, 0xeb, 0xb9, 0x08, 0x37, 0x3a, 0x20, 0x00, + 0xaa, 0x84, 0x2e, 0x84, 0x13, 0x09, 0x4a, 0xe9, 0xef, 0xf0, 0xbf, 0xc4, 0x03, 0x25, 0xc9, 0x00, + 0x13, 0x0a, 0x4a, 0xe9, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x7f, 0xba, 0x13, 0x85, + 0x04, 0x02, 0x63, 0x19, 0x34, 0x03, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x05, 0x05, 0x02, + 0x13, 0x06, 0x00, 0x02, 0xef, 0xe0, 0xaf, 0xbb, 0x03, 0x25, 0xc9, 0x00, 0x62, 0x44, 0xf2, 0x40, + 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0x05, 0x61, + 0x6f, 0xf0, 0x1f, 0xb7, 0xfd, 0x47, 0x63, 0xf8, 0x87, 0x02, 0x93, 0x05, 0x04, 0xfe, 0xef, 0xf0, + 0x5f, 0xbf, 0x13, 0x04, 0x04, 0x04, 0x0e, 0x04, 0x42, 0x04, 0x41, 0x80, 0x93, 0x17, 0x84, 0x00, + 0x37, 0x07, 0xff, 0x00, 0xf9, 0x8f, 0x62, 0x04, 0x3e, 0x94, 0xb7, 0x07, 0x00, 0x04, 0x03, 0x25, + 0xca, 0x00, 0xc0, 0xdf, 0x65, 0xbf, 0x01, 0x45, 0xef, 0xf0, 0x3f, 0xa9, 0xd9, 0xbf, 0xf2, 0x40, + 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, + 0x22, 0xcc, 0x37, 0x34, 0x20, 0x00, 0x93, 0x07, 0x44, 0xe9, 0x52, 0xc4, 0x2a, 0x8a, 0xc8, 0x47, + 0x56, 0xc2, 0x06, 0xce, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x30, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, + 0xae, 0x8a, 0xef, 0xf0, 0xff, 0xaf, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x11, 0xf5, 0x12, 0xaa, 0x84, + 0x13, 0x05, 0x60, 0x03, 0xef, 0xf0, 0x7f, 0xa4, 0x13, 0x04, 0x44, 0xe9, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x45, 0x00, 0xef, 0xf0, 0xdf, 0xad, 0x2a, 0x89, 0x63, 0x11, 0x95, 0x10, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xbf, 0xac, 0xaa, 0x84, 0x63, 0x18, 0x25, 0x0f, + 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x5f, 0xab, + 0xaa, 0x89, 0x63, 0x1d, 0x95, 0x0c, 0xd6, 0x85, 0x52, 0x85, 0xef, 0xf0, 0xdf, 0xec, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xbf, 0xa9, 0xaa, 0x84, 0x63, 0x10, 0x35, 0x0d, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x03, 0xef, 0xf0, 0x9f, 0xa8, 0xaa, 0x89, 0x63, 0x17, + 0x95, 0x0a, 0x13, 0x05, 0xc0, 0x05, 0xef, 0xf0, 0x5f, 0x9d, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x45, 0x00, 0xef, 0xf0, 0xff, 0xa6, 0xaa, 0x84, 0x63, 0x1a, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xa5, 0xaa, 0x89, 0x63, 0x11, 0x95, 0x08, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x32, 0xef, 0xf0, 0xbf, 0xa4, 0xaa, 0x84, 0x63, 0x18, 0x35, 0x07, + 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x9f, 0xa3, 0x63, 0x10, 0x95, 0x06, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x03, 0xef, 0xf0, 0x9f, 0xa2, 0x93, 0x07, 0xa0, 0x0a, + 0x2a, 0x89, 0x63, 0x15, 0xf5, 0x04, 0x13, 0x05, 0x00, 0x06, 0xef, 0xf0, 0x9f, 0x99, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xbf, 0xa0, 0xaa, 0x84, 0x63, 0x18, 0x25, 0x03, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x9f, 0x9f, 0x63, 0x10, 0x95, 0x02, + 0x48, 0x44, 0x62, 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0x05, 0x61, 0x6f, 0xf0, 0x9f, 0x9d, 0xf2, 0x40, 0x62, 0x44, + 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x39, 0x71, + 0x22, 0xdc, 0x37, 0x34, 0x20, 0x00, 0x06, 0xde, 0x4a, 0xd8, 0x26, 0xda, 0x32, 0x89, 0x13, 0x04, + 0x44, 0xe9, 0xef, 0xf0, 0xdf, 0xe8, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x40, 0xef, 0xf0, + 0x3f, 0x9a, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x0a, 0xaa, 0x84, 0x37, 0x55, 0x10, 0x00, + 0x85, 0x45, 0x13, 0x05, 0xc5, 0x6b, 0xef, 0xf0, 0x9f, 0xe6, 0x85, 0x47, 0x63, 0x07, 0xf9, 0x08, + 0x48, 0x44, 0x85, 0x67, 0x93, 0x87, 0x07, 0x80, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0x5f, 0x97, + 0x2a, 0x89, 0x63, 0x1c, 0x95, 0x06, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, + 0x05, 0x04, 0x68, 0x00, 0xef, 0xe0, 0xef, 0x91, 0x48, 0x44, 0x89, 0x47, 0x23, 0x06, 0xf1, 0x02, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x20, 0xef, 0xf0, 0xbf, 0x94, 0xaa, 0x84, 0x63, 0x17, 0x25, 0x05, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0x9f, 0x93, 0x2a, 0x89, 0x63, 0x1e, + 0x95, 0x02, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x42, 0xef, 0xf0, 0x7f, 0x92, 0xaa, 0x84, + 0x63, 0x15, 0x25, 0x03, 0x68, 0x00, 0x93, 0x05, 0x10, 0x02, 0xef, 0xf0, 0x5f, 0xdf, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x10, 0xef, 0xf0, 0xbf, 0x90, 0x63, 0x18, 0x95, 0x00, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xbf, 0x8f, 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, + 0x42, 0x59, 0x21, 0x61, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, + 0x44, 0xe9, 0x08, 0x40, 0x09, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x06, 0xc6, + 0xef, 0xf0, 0xff, 0xf0, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x71, 0xef, 0xf0, 0x5f, 0x8c, + 0x48, 0x44, 0x22, 0x44, 0xb2, 0x40, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x40, 0x41, 0x01, 0x6f, 0xf0, + 0x3f, 0x8b, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x47, 0xe9, 0x05, 0x46, 0x93, 0x05, 0x00, 0x02, + 0x13, 0x05, 0x15, 0x04, 0x6f, 0xf0, 0xbf, 0xed, 0x41, 0x11, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x05, + 0x00, 0x04, 0x22, 0xc4, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x45, 0x6c, 0x13, 0x05, 0x05, 0x02, + 0x37, 0x34, 0x20, 0x00, 0x06, 0xc6, 0x13, 0x04, 0x44, 0xe9, 0xef, 0xe0, 0x4f, 0x8a, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0x86, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x1d, + 0xf5, 0x00, 0x08, 0x40, 0x22, 0x44, 0xb2, 0x40, 0x05, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, + 0x15, 0x04, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xe8, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, + 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x44, 0xe9, 0x48, 0x44, 0x06, 0xc6, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xbf, 0x82, 0x08, 0x40, 0x13, 0x06, 0x00, 0x02, + 0x81, 0x45, 0x13, 0x05, 0x15, 0x04, 0xef, 0x00, 0x90, 0x5c, 0x08, 0x40, 0x09, 0x46, 0x81, 0x45, + 0x13, 0x05, 0x15, 0x04, 0xef, 0xf0, 0xbf, 0xe4, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x60, + 0xef, 0xf0, 0x1f, 0x80, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x71, 0xef, 0xf0, 0x4f, 0xff, + 0x01, 0x45, 0xef, 0xf0, 0x8f, 0xf4, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, + 0x2f, 0xfe, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x6f, 0xfd, 0xb2, 0x40, + 0x22, 0x44, 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, 0x98, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x11, 0x65, + 0xad, 0xa9, 0x37, 0x35, 0x20, 0x00, 0x41, 0x11, 0x51, 0x46, 0x81, 0x45, 0x13, 0x05, 0x45, 0xe9, + 0x06, 0xc6, 0xef, 0x00, 0xd0, 0x55, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x1d, 0x65, + 0x23, 0xa2, 0xe7, 0xfa, 0xa9, 0x21, 0xb2, 0x40, 0xb7, 0x07, 0x00, 0x04, 0x05, 0x47, 0x98, 0xcb, + 0x41, 0x01, 0x6f, 0xf0, 0xdf, 0xfc, 0x11, 0x65, 0x1d, 0xa9, 0x95, 0x47, 0x63, 0xec, 0xb7, 0x02, + 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x44, 0xe9, 0x85, 0x47, 0x5c, 0xc0, + 0xb7, 0x57, 0x10, 0x00, 0x0c, 0xc4, 0x93, 0x87, 0x87, 0x6e, 0x8a, 0x05, 0xbe, 0x95, 0x9c, 0x41, + 0x06, 0xc6, 0x08, 0xc0, 0x82, 0x97, 0x08, 0x48, 0xb2, 0x40, 0x23, 0x22, 0x04, 0x00, 0x22, 0x44, + 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x05, 0x00, 0x04, 0x41, 0x46, + 0x93, 0x85, 0x05, 0x08, 0x6f, 0xd0, 0xff, 0xef, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xe9, + 0x89, 0x47, 0x5c, 0xc3, 0x5c, 0x47, 0x46, 0x05, 0xfe, 0x07, 0xc9, 0x8f, 0x21, 0x65, 0x15, 0x05, + 0x5d, 0x8d, 0x6f, 0xf0, 0xef, 0xf1, 0x39, 0x71, 0x4e, 0xd6, 0x5e, 0xce, 0x62, 0xcc, 0xb7, 0x0b, + 0x00, 0x04, 0xb7, 0x39, 0x20, 0x00, 0x05, 0x6c, 0x22, 0xdc, 0x26, 0xda, 0x4a, 0xd8, 0x56, 0xd2, + 0x5a, 0xd0, 0x66, 0xca, 0x6a, 0xc8, 0x06, 0xde, 0x52, 0xd4, 0x2a, 0x84, 0x2e, 0x8b, 0xb2, 0x8a, + 0x81, 0x44, 0x01, 0x49, 0xc1, 0x4c, 0x93, 0x8b, 0x0b, 0x02, 0x93, 0x89, 0x49, 0xe9, 0x09, 0x0c, + 0x37, 0x3d, 0x20, 0x00, 0xb3, 0x05, 0x9b, 0x00, 0x63, 0xe0, 0x54, 0x03, 0xf2, 0x50, 0x62, 0x54, + 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, + 0xd2, 0x4c, 0x42, 0x4d, 0x21, 0x61, 0x82, 0x80, 0x33, 0x8a, 0x9a, 0x40, 0x63, 0xd3, 0x4c, 0x01, + 0x41, 0x4a, 0x4a, 0x85, 0x2e, 0xc6, 0xef, 0xe0, 0xcf, 0x9f, 0xb2, 0x45, 0x13, 0x06, 0x3a, 0x00, + 0x71, 0x9a, 0x5e, 0x85, 0xef, 0xd0, 0xbf, 0xec, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x07, 0xef, 0xf0, 0xef, 0xe8, 0x03, 0xa5, 0xc9, 0x00, 0x93, 0x17, 0x8a, 0x01, 0x7e, 0x05, + 0x5d, 0x8d, 0x13, 0x65, 0x75, 0x00, 0xef, 0xf0, 0xaf, 0xe7, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, + 0x33, 0x65, 0x85, 0x01, 0xef, 0xf0, 0xcf, 0xe6, 0x03, 0x27, 0x4d, 0xfa, 0x93, 0x07, 0x50, 0x05, + 0x63, 0x19, 0xf7, 0x00, 0x19, 0xc4, 0x22, 0x85, 0x52, 0x86, 0xca, 0x85, 0xef, 0xe0, 0x4f, 0xa3, + 0x41, 0x04, 0x93, 0x07, 0x00, 0x07, 0x63, 0xe3, 0x27, 0x01, 0x41, 0x09, 0xc1, 0x04, 0x9d, 0xb7, + 0x39, 0x71, 0x4e, 0xd6, 0x5a, 0xd0, 0x5e, 0xce, 0xb7, 0x39, 0x20, 0x00, 0x37, 0x0b, 0x02, 0x00, + 0x85, 0x6b, 0x26, 0xda, 0x4a, 0xd8, 0x52, 0xd4, 0x56, 0xd2, 0x62, 0xcc, 0x6a, 0xc8, 0x6e, 0xc6, + 0x06, 0xde, 0x22, 0xdc, 0x66, 0xca, 0xaa, 0x8a, 0xae, 0x84, 0x32, 0x8a, 0x01, 0x49, 0x81, 0x4d, + 0x37, 0x3c, 0x20, 0x00, 0x41, 0x4d, 0x93, 0x89, 0x49, 0xe9, 0x1d, 0x0b, 0x93, 0x8b, 0x0b, 0x82, + 0xb3, 0x8c, 0x2a, 0x01, 0x93, 0x07, 0x4c, 0xfa, 0x63, 0x64, 0x49, 0x03, 0xf2, 0x50, 0x62, 0x54, + 0x13, 0x07, 0x50, 0x05, 0x98, 0xc3, 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, 0x5a, + 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, 0xd2, 0x4c, 0x42, 0x4d, 0xb2, 0x4d, 0x21, 0x61, 0x82, 0x80, + 0x33, 0x04, 0x2a, 0x41, 0x63, 0x73, 0x8d, 0x00, 0x41, 0x44, 0x6e, 0x85, 0xef, 0xe0, 0xef, 0x91, + 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0xfa, 0x98, 0x43, 0x93, 0x07, 0x50, 0x05, 0x63, 0x19, + 0xf7, 0x00, 0x99, 0xc4, 0x26, 0x85, 0x22, 0x86, 0xee, 0x85, 0xef, 0xe0, 0xcf, 0x9b, 0xc1, 0x04, + 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x25, 0x00, 0xef, 0xf0, 0x6f, 0xd9, 0x03, 0xa5, + 0xc9, 0x00, 0x93, 0x17, 0x84, 0x01, 0x0d, 0x04, 0x7e, 0x05, 0x5d, 0x8d, 0x33, 0x65, 0x65, 0x01, + 0xef, 0xf0, 0x0f, 0xd8, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x33, 0x65, 0x75, 0x01, 0xef, 0xf0, + 0x2f, 0xd7, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x76, 0xc4, 0xff, 0x93, 0x85, 0x05, 0x04, 0x66, 0x85, + 0xef, 0xd0, 0x3f, 0xd2, 0x93, 0x07, 0x00, 0x06, 0x63, 0xe3, 0xb7, 0x01, 0xc1, 0x0d, 0x41, 0x09, + 0x81, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x2a, 0x84, 0x21, 0x45, 0x06, 0xc6, 0xef, 0xf0, 0x4f, 0xd4, + 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x19, 0xf5, 0x00, 0x22, 0x85, 0xef, 0xf0, 0x1f, 0xdf, 0xb7, 0x37, + 0x20, 0x00, 0x23, 0xac, 0x07, 0xe8, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, + 0x20, 0x00, 0x23, 0xa2, 0xa7, 0xfa, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x60, 0x02, + 0x98, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, 0x98, 0xc7, 0x82, 0x80, 0xb7, 0x07, + 0x00, 0x04, 0xc8, 0x4b, 0x82, 0x80, 0x39, 0x71, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x05, 0x47, + 0xb7, 0x07, 0x00, 0x04, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, + 0x32, 0xd2, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xd8, 0xc7, + 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0xe9, 0xd8, 0x43, 0x89, 0x46, 0x7d, 0x17, 0x63, 0xfe, + 0xe6, 0x02, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x05, 0x6c, 0xef, 0xd0, 0xef, 0xe0, + 0xef, 0xc0, 0x8f, 0xdc, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, + 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, + 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x13, 0x07, 0xa0, 0x0a, 0x98, 0xcb, + 0xd1, 0xbf, 0xb7, 0x07, 0x01, 0x02, 0x88, 0xd7, 0xcc, 0xd7, 0x88, 0xdb, 0xcc, 0xdb, 0x88, 0xdf, + 0xcc, 0xdf, 0x82, 0x80, 0x01, 0x11, 0x26, 0xca, 0xb7, 0x04, 0x01, 0x02, 0x22, 0xcc, 0xc0, 0x40, + 0xf5, 0x77, 0x93, 0x87, 0xf7, 0xa5, 0x7d, 0x8c, 0x89, 0x67, 0x93, 0x87, 0x07, 0x1a, 0x06, 0xce, + 0x4a, 0xc8, 0x4e, 0xc6, 0xc1, 0x8f, 0xaa, 0x89, 0xdc, 0xc0, 0x05, 0x45, 0x2e, 0x89, 0xef, 0xd0, + 0xbf, 0x99, 0x93, 0x67, 0x04, 0x40, 0xdc, 0xc0, 0x05, 0x45, 0xef, 0xd0, 0xff, 0x98, 0x85, 0x67, + 0x93, 0x87, 0x07, 0x40, 0x5d, 0x8c, 0xc0, 0xc0, 0xb7, 0x47, 0x00, 0x08, 0x23, 0xa4, 0x07, 0x00, + 0xb7, 0x57, 0x00, 0x08, 0x23, 0xa4, 0x07, 0x00, 0xf2, 0x40, 0x62, 0x44, 0x23, 0xa0, 0x34, 0x03, + 0x23, 0xa2, 0x24, 0x03, 0xb2, 0x49, 0xd2, 0x44, 0x42, 0x49, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x07, + 0x01, 0x02, 0x88, 0x53, 0xcc, 0x53, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x02, 0x88, 0x47, 0x21, 0x81, + 0x13, 0x75, 0xf5, 0x0f, 0x82, 0x80, 0x41, 0x11, 0x01, 0x45, 0x81, 0x45, 0x06, 0xc6, 0x22, 0xc4, + 0x26, 0xc2, 0xef, 0xf0, 0x1f, 0xf6, 0xef, 0xf0, 0x9f, 0xfd, 0xaa, 0x84, 0x2e, 0x84, 0x2a, 0x87, + 0xae, 0x86, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0x85, + 0x85, 0x71, 0x13, 0x05, 0x45, 0x64, 0x13, 0x06, 0x06, 0x70, 0xef, 0xd0, 0xaf, 0xc9, 0xa2, 0x85, + 0x22, 0x44, 0xb2, 0x40, 0x26, 0x85, 0x92, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xf3, 0x39, 0x71, + 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, + 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, + 0xef, 0xf0, 0x7f, 0xf9, 0xef, 0xc0, 0x4f, 0xc9, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, + 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, + 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x07, + 0x00, 0x02, 0x5c, 0x47, 0xc9, 0x8f, 0x5c, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0xd8, 0x47, + 0x13, 0x45, 0xf5, 0xff, 0x79, 0x8d, 0xc8, 0xc7, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x4f, + 0xc9, 0x8f, 0x1c, 0xcf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0x98, 0x4f, 0x13, 0x45, 0xf5, 0xff, + 0x79, 0x8d, 0x88, 0xcf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0xc8, 0xcb, 0x82, 0x80, 0x37, 0x07, + 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x47, 0x00, 0x1c, 0xc7, 0xb7, 0x07, 0x00, 0x03, 0x94, 0x4b, + 0x37, 0x37, 0x20, 0x00, 0x23, 0x24, 0xd7, 0xfa, 0x23, 0xa8, 0x07, 0x00, 0x82, 0x80, 0x37, 0x07, + 0x00, 0x02, 0x1c, 0x47, 0xb7, 0x06, 0x00, 0x03, 0xf9, 0x9b, 0x1c, 0xc7, 0x37, 0x07, 0x08, 0x00, + 0x9c, 0x46, 0xf9, 0x8f, 0xf5, 0xff, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, + 0x17, 0x00, 0x1c, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x87, 0xfa, 0xb7, 0x07, 0x00, 0x03, + 0x98, 0xcb, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0xc7, 0xfa, 0x93, 0x07, 0xa0, 0x0a, + 0x63, 0x0b, 0xf5, 0x00, 0xb7, 0x27, 0x03, 0x04, 0x9c, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, + 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x13, 0x05, 0x00, 0x10, 0x6f, 0xf0, 0x3f, 0xf4, + 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0x41, 0x11, 0x37, 0x37, + 0x20, 0x00, 0x23, 0x28, 0xf7, 0xfa, 0x06, 0xc6, 0xef, 0xf0, 0x1f, 0xfe, 0xb7, 0x27, 0x03, 0x04, + 0x09, 0x47, 0xd8, 0xc3, 0x37, 0x17, 0x03, 0x04, 0xb7, 0x07, 0x03, 0x04, 0x13, 0x07, 0x07, 0x80, + 0x23, 0xa0, 0x07, 0x00, 0x91, 0x07, 0xe3, 0x9d, 0xe7, 0xfe, 0xb7, 0x27, 0x03, 0x04, 0x0d, 0x47, + 0xd8, 0xc7, 0x98, 0x47, 0x85, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, + 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x00, 0x10, 0x6f, 0xf0, 0xff, 0xee, + 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0x37, 0x37, 0x20, 0x00, + 0x23, 0x28, 0xf7, 0xfa, 0xb7, 0x27, 0x03, 0x04, 0x05, 0x47, 0xd8, 0xc3, 0x82, 0x80, 0xc2, 0x05, + 0xc9, 0x8d, 0x93, 0xe5, 0x05, 0x10, 0xb7, 0x07, 0x03, 0x04, 0x23, 0xa0, 0xb7, 0x10, 0x82, 0x80, + 0xc2, 0x05, 0xc9, 0x8d, 0x11, 0x65, 0x13, 0x05, 0x05, 0x50, 0xc9, 0x8d, 0xb7, 0x07, 0x03, 0x04, + 0x23, 0xa0, 0xb7, 0x10, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, + 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xb0, 0x9f, 0xc4, 0x37, 0x15, 0x03, 0x04, 0x2a, 0x94, 0x08, 0x40, + 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x79, 0x71, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, + 0x06, 0xd6, 0x22, 0xd4, 0xaa, 0x84, 0x2e, 0x89, 0xb2, 0x89, 0x19, 0xe1, 0xef, 0xb0, 0x1f, 0xc2, + 0x93, 0x77, 0x39, 0x00, 0x99, 0xc3, 0xef, 0xb0, 0x7f, 0xc1, 0x01, 0x44, 0x63, 0x69, 0x34, 0x01, + 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x45, 0x61, 0x82, 0x80, 0x33, 0x05, + 0x24, 0x01, 0xef, 0xf0, 0x5f, 0xfa, 0x2a, 0xc6, 0x11, 0x46, 0x33, 0x85, 0x84, 0x00, 0x6c, 0x00, + 0xcd, 0x2d, 0x11, 0x04, 0xe1, 0xbf, 0x79, 0x71, 0x22, 0xd4, 0x4a, 0xd0, 0x4e, 0xce, 0x56, 0xca, + 0x06, 0xd6, 0x26, 0xd2, 0x52, 0xcc, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0xae, 0x89, 0x32, 0x89, + 0x93, 0x7a, 0xc6, 0xff, 0x99, 0xc3, 0xef, 0xb0, 0x7f, 0xbc, 0x37, 0x0a, 0x03, 0x04, 0x81, 0x44, + 0x22, 0x9a, 0x63, 0xe9, 0x54, 0x03, 0x13, 0x76, 0x39, 0x00, 0x01, 0xce, 0xb3, 0x85, 0x99, 0x00, + 0x68, 0x00, 0x02, 0xc6, 0x7d, 0x25, 0xb2, 0x47, 0x37, 0x05, 0x03, 0x04, 0x2a, 0x94, 0x26, 0x94, + 0x1c, 0xc0, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0xd2, 0x4a, + 0x45, 0x61, 0x82, 0x80, 0x63, 0x94, 0x09, 0x00, 0xef, 0xb0, 0x5f, 0xb8, 0xb3, 0x85, 0x99, 0x00, + 0x11, 0x46, 0x68, 0x00, 0xbd, 0x2d, 0x32, 0x47, 0xb3, 0x07, 0x9a, 0x00, 0x91, 0x04, 0x98, 0xc3, + 0x4d, 0xbf, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x41, 0x11, 0x13, 0x05, 0x45, 0xb5, 0x06, 0xc6, + 0x22, 0xc4, 0xef, 0xd0, 0xef, 0xe9, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0f, 0xf5, 0x00, 0x37, 0x55, + 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x05, 0x72, 0xef, 0xd0, 0x2f, 0xa3, 0x13, 0x05, 0x50, 0x05, + 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x17, 0x03, 0x04, 0x83, 0xa7, 0x07, 0x10, + 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, 0xfb, 0x93, 0xf7, 0xf7, 0x0f, 0x81, 0xe7, 0x1c, 0x40, + 0x63, 0x9d, 0xa7, 0x00, 0x37, 0x55, 0x10, 0x00, 0x8d, 0x45, 0x13, 0x05, 0x05, 0x72, 0xef, 0xd0, + 0xcf, 0x9f, 0x93, 0x07, 0xa0, 0x0a, 0x1c, 0xc0, 0xd1, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, + 0xc7, 0xfa, 0x13, 0x84, 0xc7, 0xfa, 0x63, 0x09, 0xa7, 0x00, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, + 0x13, 0x05, 0x05, 0x72, 0xef, 0xd0, 0x6f, 0x9d, 0x08, 0x40, 0x5d, 0xb7, 0x37, 0x95, 0x04, 0x00, + 0x13, 0x05, 0x05, 0x3e, 0x6f, 0xf0, 0xff, 0xf6, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x5f, 0xe6, + 0xef, 0xf0, 0x1f, 0xe3, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x5f, 0xfe, 0xb7, 0x17, 0x03, 0x04, + 0x03, 0xa5, 0x07, 0x10, 0x41, 0x81, 0x82, 0x80, 0x41, 0x11, 0x3a, 0xc4, 0x37, 0x27, 0x03, 0x04, + 0x3e, 0xc2, 0x1c, 0x47, 0x36, 0xc6, 0x93, 0xf6, 0x27, 0x00, 0x89, 0xca, 0x89, 0x46, 0x14, 0xc7, + 0x37, 0x37, 0x20, 0x00, 0x93, 0x06, 0xa0, 0x0a, 0x23, 0x26, 0xd7, 0xfa, 0x91, 0x8b, 0x99, 0xcf, + 0xb7, 0x27, 0x03, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x93, 0x07, 0xa0, 0x0a, 0x37, 0x37, 0x20, 0x00, + 0x23, 0x28, 0xf7, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0xb2, 0x46, 0x22, 0x47, + 0x92, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x04, 0x00, 0x03, + 0x1c, 0x48, 0x06, 0xc6, 0xdd, 0x9b, 0x1c, 0xc8, 0xef, 0xe0, 0x0f, 0xd9, 0xb7, 0x07, 0x20, 0x00, + 0x93, 0x87, 0x07, 0x02, 0x5c, 0xcc, 0xb2, 0x40, 0x22, 0x44, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x8c, + 0x07, 0xfa, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x2a, 0x84, 0x21, 0x45, 0x06, 0xc6, + 0xef, 0xf0, 0x7f, 0xca, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x7f, 0xc6, 0x22, 0x04, 0x13, 0x64, + 0x04, 0x03, 0x37, 0x07, 0x00, 0x03, 0x40, 0xc3, 0xb2, 0x40, 0x22, 0x44, 0xc1, 0x67, 0x93, 0x87, + 0xa7, 0xfa, 0x1c, 0xcf, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x26, 0xc2, 0xaa, 0x84, 0x09, 0x45, + 0x22, 0xc4, 0x06, 0xc6, 0x2e, 0x84, 0xef, 0xf0, 0x1f, 0xfc, 0x37, 0x07, 0x20, 0x00, 0xb7, 0x07, + 0x00, 0x03, 0x13, 0x07, 0x07, 0x02, 0xd8, 0xcf, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2a, 0x97, 0xfa, + 0x37, 0x37, 0x20, 0x00, 0x23, 0x2e, 0x87, 0xfa, 0xb2, 0x40, 0x22, 0x44, 0x05, 0x47, 0x98, 0xcb, + 0x37, 0x07, 0x08, 0x00, 0x98, 0xc7, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x03, + 0x9c, 0x47, 0x37, 0x07, 0x04, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x99, 0xe3, 0x13, 0x05, + 0x50, 0x05, 0x82, 0x80, 0x37, 0x07, 0x00, 0x03, 0x5c, 0x53, 0x13, 0x05, 0x50, 0x05, 0x93, 0x96, + 0x07, 0x01, 0xc1, 0x82, 0xc1, 0x83, 0x63, 0x97, 0xf6, 0x00, 0x1c, 0x47, 0x91, 0x8b, 0x99, 0xe3, + 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xff, 0xf1, 0x37, 0x07, + 0x00, 0x03, 0x5c, 0x47, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc7, 0x5c, 0x47, 0x85, 0x8b, 0xf5, 0xff, + 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xfb, 0x95, 0xc3, + 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x5f, 0xef, 0xb7, 0x07, 0x00, 0x03, 0x98, 0x4b, 0xb2, 0x40, + 0x13, 0x67, 0x87, 0x00, 0x98, 0xcb, 0x37, 0x07, 0x08, 0x00, 0x98, 0xc7, 0x41, 0x01, 0x6f, 0xe0, + 0xcf, 0xc5, 0x82, 0x80, 0x37, 0x07, 0x00, 0x03, 0x1c, 0x4b, 0xf9, 0x9b, 0x1c, 0xcb, 0x82, 0x80, + 0xb7, 0x06, 0x00, 0x03, 0xdc, 0x42, 0x7d, 0x77, 0x13, 0x07, 0xf7, 0x0f, 0xf9, 0x8f, 0x05, 0x67, + 0x22, 0x05, 0x13, 0x07, 0x07, 0xf0, 0x79, 0x8d, 0x5d, 0x8d, 0xc8, 0xc2, 0x82, 0x80, 0x1d, 0x71, + 0x3a, 0xda, 0x37, 0x07, 0x00, 0x03, 0x3e, 0xd8, 0x1c, 0x47, 0x86, 0xce, 0x96, 0xcc, 0x9a, 0xca, + 0x9e, 0xc8, 0xa2, 0xc6, 0xa6, 0xc4, 0xaa, 0xc2, 0xae, 0xc0, 0x32, 0xde, 0x36, 0xdc, 0x42, 0xd6, + 0x46, 0xd4, 0x4a, 0xd2, 0x4e, 0xd0, 0x72, 0xce, 0x76, 0xcc, 0x7a, 0xca, 0x7e, 0xc8, 0x85, 0x8b, + 0xa1, 0xc7, 0x04, 0x57, 0x11, 0x44, 0x37, 0x39, 0x20, 0x00, 0x83, 0x27, 0x49, 0xfb, 0x13, 0xf5, + 0xf4, 0x0f, 0x7d, 0x14, 0x82, 0x97, 0xa1, 0x80, 0x6d, 0xf8, 0x36, 0x44, 0xf6, 0x40, 0xe6, 0x42, + 0x56, 0x43, 0xc6, 0x43, 0xa6, 0x44, 0x16, 0x45, 0x86, 0x45, 0x72, 0x56, 0xe2, 0x56, 0x52, 0x57, + 0xc2, 0x57, 0x32, 0x58, 0xa2, 0x58, 0x12, 0x59, 0x82, 0x59, 0x72, 0x4e, 0xe2, 0x4e, 0x52, 0x4f, + 0xc2, 0x4f, 0x25, 0x61, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xc7, 0x87, 0xfb, + 0x13, 0x84, 0x87, 0xfb, 0x05, 0xeb, 0xb7, 0x04, 0x00, 0x03, 0x37, 0x39, 0x20, 0x00, 0x93, 0x09, + 0xa0, 0x0a, 0x9c, 0x44, 0x91, 0x8b, 0xd5, 0xfb, 0x83, 0x27, 0xc9, 0xfb, 0x68, 0x00, 0x82, 0x97, + 0x63, 0x0d, 0x35, 0x01, 0x85, 0x47, 0x23, 0x00, 0xf4, 0x00, 0xc1, 0x67, 0x93, 0x87, 0x07, 0x02, + 0xdc, 0xcc, 0x61, 0xbf, 0xef, 0xf0, 0x5f, 0xdf, 0x49, 0xbf, 0xb2, 0x47, 0x9c, 0xd8, 0xd1, 0xbf, + 0x5c, 0x41, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc1, 0x82, 0x80, 0x5c, 0x41, 0xf9, 0x9b, 0x5c, 0xc1, + 0x82, 0x80, 0x5c, 0x41, 0xf5, 0x9b, 0xd1, 0x8f, 0x5c, 0xc1, 0x14, 0xc9, 0x4c, 0xc9, 0x82, 0x80, + 0x5c, 0x45, 0xcd, 0x8f, 0x5c, 0xc5, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x07, 0xfc, + 0x82, 0x80, 0x39, 0x71, 0x3a, 0xce, 0x37, 0x07, 0x10, 0x01, 0x3e, 0xcc, 0x1c, 0x47, 0x58, 0x47, + 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, + 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xf9, 0x8f, 0x91, 0xcf, + 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xfc, 0x98, 0x43, 0x05, 0x07, 0x98, 0xc3, 0xb7, 0x07, + 0x10, 0x01, 0x98, 0x47, 0x0d, 0x8b, 0x98, 0xc7, 0x19, 0xa8, 0xb7, 0x07, 0x20, 0x01, 0x98, 0x47, + 0xdc, 0x47, 0x7d, 0x8f, 0xb7, 0x07, 0x20, 0x01, 0x6d, 0xf7, 0xef, 0xb0, 0xff, 0xe6, 0xf2, 0x50, + 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, + 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, + 0x73, 0x00, 0x20, 0x30, 0x1c, 0x41, 0x63, 0xf7, 0xb7, 0x00, 0x23, 0x80, 0xc7, 0x00, 0x1c, 0x41, + 0x85, 0x07, 0x1c, 0xc1, 0x82, 0x80, 0x1d, 0x71, 0xa2, 0xcc, 0xa6, 0xca, 0xca, 0xc8, 0x86, 0xce, + 0xce, 0xc6, 0xd2, 0xc4, 0xd6, 0xc2, 0xda, 0xc0, 0x5e, 0xde, 0x62, 0xdc, 0x66, 0xda, 0x6a, 0xd8, + 0x6e, 0xd6, 0x2a, 0xc6, 0x2e, 0x84, 0x32, 0x89, 0xb6, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x0f, 0xf6, + 0x63, 0x14, 0x09, 0x00, 0xef, 0xb0, 0x8f, 0xf5, 0x01, 0x45, 0x05, 0xc4, 0xb2, 0x4a, 0x7d, 0x14, + 0x25, 0x4a, 0x56, 0x94, 0x93, 0x0c, 0xc0, 0x06, 0x13, 0x0b, 0x30, 0x07, 0xa9, 0x4b, 0x1d, 0x4d, + 0x03, 0x46, 0x09, 0x00, 0x15, 0xe6, 0xb2, 0x47, 0x23, 0x80, 0x07, 0x00, 0x32, 0x45, 0x33, 0x05, + 0x55, 0x41, 0xf6, 0x40, 0x66, 0x44, 0xd6, 0x44, 0x46, 0x49, 0xb6, 0x49, 0x26, 0x4a, 0x96, 0x4a, + 0x06, 0x4b, 0xf2, 0x5b, 0x62, 0x5c, 0xd2, 0x5c, 0x42, 0x5d, 0xb2, 0x5d, 0x25, 0x61, 0x82, 0x80, + 0x93, 0x07, 0x50, 0x02, 0x63, 0x1f, 0xf6, 0x02, 0x93, 0x07, 0x19, 0x00, 0x83, 0xc6, 0x07, 0x00, + 0x3e, 0x89, 0x85, 0x07, 0x13, 0x87, 0x06, 0xfd, 0x13, 0x77, 0xf7, 0x0f, 0xe3, 0x78, 0xea, 0xfe, + 0x63, 0x93, 0x96, 0x01, 0x3e, 0x89, 0x03, 0x46, 0x09, 0x00, 0x63, 0x06, 0x66, 0x0d, 0x63, 0x60, + 0xcb, 0x02, 0x93, 0x07, 0x30, 0x06, 0x63, 0x05, 0xf6, 0x06, 0x93, 0x07, 0x40, 0x06, 0x63, 0x0c, + 0xf6, 0x06, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, 0xf2, 0xa6, 0x89, 0x95, 0xa0, 0x93, 0x07, + 0x50, 0x07, 0x63, 0x02, 0xf6, 0x06, 0x93, 0x07, 0x80, 0x07, 0xe3, 0x14, 0xf6, 0xfe, 0x98, 0x40, + 0x93, 0x89, 0x44, 0x00, 0x81, 0x46, 0x37, 0x06, 0x00, 0xf0, 0xb3, 0x75, 0xc7, 0x00, 0xba, 0x84, + 0x36, 0x8c, 0x12, 0x07, 0x85, 0x06, 0x89, 0xe5, 0xe3, 0x99, 0xa6, 0xff, 0x1d, 0x4c, 0xba, 0x84, + 0xa1, 0x4d, 0x13, 0xd7, 0xc4, 0x01, 0x63, 0x74, 0xea, 0x08, 0x13, 0x06, 0x77, 0x05, 0xa2, 0x85, + 0x68, 0x00, 0x05, 0x0c, 0xef, 0xf0, 0x1f, 0xee, 0x92, 0x04, 0xe3, 0x14, 0xbc, 0xff, 0x09, 0xa8, + 0x03, 0xc6, 0x04, 0x00, 0xa2, 0x85, 0x68, 0x00, 0x93, 0x89, 0x44, 0x00, 0xef, 0xf0, 0x9f, 0xec, + 0x05, 0x09, 0xce, 0x84, 0x31, 0xbf, 0x5c, 0x08, 0x98, 0x40, 0x93, 0x89, 0x44, 0x00, 0x3e, 0x8c, + 0x81, 0x44, 0xb3, 0x76, 0x77, 0x03, 0x85, 0x04, 0x85, 0x07, 0x93, 0x86, 0x06, 0x03, 0xa3, 0x8f, + 0xd7, 0xfe, 0xba, 0x86, 0x33, 0x57, 0x77, 0x03, 0xe3, 0x65, 0xda, 0xfe, 0xfd, 0x5d, 0xfd, 0x14, + 0xe3, 0x88, 0xb4, 0xfd, 0xb3, 0x07, 0x9c, 0x00, 0x03, 0xc6, 0x07, 0x00, 0xa2, 0x85, 0x68, 0x00, + 0xef, 0xf0, 0x5f, 0xe8, 0xed, 0xb7, 0x93, 0x89, 0x44, 0x00, 0x84, 0x40, 0x03, 0xc6, 0x04, 0x00, + 0x45, 0xda, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, 0xe6, 0x85, 0x04, 0xc5, 0xbf, 0x13, 0x06, + 0x07, 0x03, 0xb5, 0xbf, 0x41, 0x11, 0x26, 0xc2, 0xb7, 0x34, 0x20, 0x00, 0x2a, 0x86, 0xae, 0x86, + 0x13, 0x85, 0x84, 0xea, 0x93, 0x05, 0x00, 0x08, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0xf0, 0xbf, 0xe5, + 0x2a, 0x84, 0x13, 0x85, 0x84, 0xea, 0xef, 0xd0, 0x8f, 0x9b, 0xb2, 0x40, 0x22, 0x85, 0x22, 0x44, + 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x26, 0xca, 0xb7, 0x34, 0x20, 0x00, 0x2e, 0xd2, + 0x32, 0xd4, 0x36, 0xd6, 0x2a, 0x86, 0x54, 0x10, 0x93, 0x05, 0x00, 0x08, 0x13, 0x85, 0x84, 0xea, + 0x06, 0xce, 0x22, 0xcc, 0x3a, 0xd8, 0x3e, 0xda, 0x42, 0xdc, 0x46, 0xde, 0x36, 0xc6, 0xef, 0xf0, + 0x9f, 0xe1, 0x2a, 0x84, 0x13, 0x85, 0x84, 0xea, 0xef, 0xd0, 0x6f, 0x97, 0xf2, 0x40, 0x22, 0x85, + 0x62, 0x44, 0xd2, 0x44, 0x21, 0x61, 0x82, 0x80, 0x22, 0x05, 0x61, 0x77, 0x2d, 0x8d, 0xa1, 0x47, + 0x15, 0x07, 0x93, 0x16, 0x05, 0x01, 0x06, 0x05, 0x42, 0x05, 0xc1, 0x86, 0x41, 0x81, 0x63, 0xd5, + 0x06, 0x00, 0x39, 0x8d, 0x42, 0x05, 0x41, 0x81, 0xfd, 0x17, 0xe5, 0xf7, 0x82, 0x80, 0x41, 0x11, + 0x22, 0xc4, 0x26, 0xc2, 0x2a, 0x84, 0xb3, 0x04, 0xb5, 0x00, 0x06, 0xc6, 0x01, 0x45, 0x63, 0x97, + 0x84, 0x00, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x04, 0xaa, 0x85, + 0x03, 0x45, 0xf4, 0xff, 0xef, 0xf0, 0x5f, 0xfb, 0xdd, 0xb7, 0xb7, 0x86, 0xb8, 0xed, 0x01, 0x47, + 0xfd, 0x57, 0x93, 0x86, 0x06, 0x32, 0x63, 0x15, 0xb7, 0x00, 0x13, 0xc5, 0xf7, 0xff, 0x82, 0x80, + 0x33, 0x06, 0xe5, 0x00, 0x03, 0x46, 0x06, 0x00, 0xb1, 0x8f, 0x21, 0x46, 0x13, 0xd8, 0x17, 0x00, + 0x85, 0x8b, 0x91, 0xc3, 0xb6, 0x87, 0x7d, 0x16, 0xb3, 0x47, 0xf8, 0x00, 0x65, 0xfa, 0x05, 0x07, + 0xd9, 0xbf, 0x2a, 0x83, 0x09, 0xca, 0x83, 0x83, 0x05, 0x00, 0x23, 0x00, 0x73, 0x00, 0x7d, 0x16, + 0x05, 0x03, 0x85, 0x05, 0x6d, 0xfa, 0x82, 0x80, 0x15, 0xc2, 0x2a, 0x83, 0x85, 0x46, 0x63, 0x67, + 0xb5, 0x00, 0xfd, 0x56, 0x13, 0x07, 0xf6, 0xff, 0x3a, 0x93, 0xba, 0x95, 0x83, 0x83, 0x05, 0x00, + 0x23, 0x00, 0x73, 0x00, 0x7d, 0x16, 0x36, 0x93, 0xb6, 0x95, 0x6d, 0xfa, 0x82, 0x80, 0x2a, 0x83, + 0x11, 0xc6, 0x23, 0x00, 0xb3, 0x00, 0x7d, 0x16, 0x05, 0x03, 0x65, 0xfe, 0x82, 0x80, 0x00, 0x00, + 0x63, 0x6f, 0x64, 0x65, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, 0x53, 0x45, 0x43, 0x43, + 0x48, 0x4e, 0x4c, 0x00, 0x4d, 0x43, 0x4e, 0x54, 0x00, 0x00, 0x00, 0x00, 0x54, 0x58, 0x3a, 0x20, + 0x25, 0x64, 0x2f, 0x25, 0x64, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x43, 0x4d, 0x44, 0x33, + 0x00, 0x00, 0x00, 0x00, 0x49, 0x00, 0x00, 0x00, 0x65, 0x6e, 0x61, 0x62, 0x6c, 0x65, 0x64, 0x20, + 0x25, 0x64, 0x00, 0x00, 0x4d, 0x41, 0x49, 0x4e, 0x00, 0x00, 0x00, 0x00, 0x6c, 0x65, 0x6e, 0x20, + 0x25, 0x64, 0x2f, 0x25, 0x64, 0x00, 0x00, 0x00, 0x72, 0x73, 0x70, 0x3d, 0x25, 0x78, 0x00, 0x00, + 0x73, 0x74, 0x61, 0x72, 0x74, 0x2c, 0x20, 0x76, 0x25, 0x75, 0x2e, 0x25, 0x75, 0x2e, 0x25, 0x75, + 0x00, 0x00, 0x00, 0x00, 0x50, 0x52, 0x4f, 0x56, 0x49, 0x53, 0x49, 0x4f, 0x4e, 0x20, 0x4f, 0x4b, + 0x00, 0x00, 0x00, 0x00, 0x4e, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x43, 0x50, 0x42, 0x3a, + 0x20, 0x25, 0x64, 0x00, 0x4c, 0x33, 0x20, 0x63, 0x6d, 0x64, 0x20, 0x25, 0x64, 0x3a, 0x20, 0x25, + 0x78, 0x2c, 0x20, 0x6c, 0x65, 0x6e, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x00, 0x4c, 0x33, 0x20, 0x61, + 0x63, 0x63, 0x65, 0x73, 0x73, 0x20, 0x66, 0x61, 0x69, 0x6c, 0x65, 0x64, 0x2c, 0x20, 0x63, 0x6d, + 0x64, 0x3a, 0x20, 0x25, 0x64, 0x2c, 0x20, 0x6c, 0x65, 0x6e, 0x3a, 0x20, 0x25, 0x64, 0x20, 0x00, + 0x70, 0x69, 0x6e, 0x67, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x00, 0x4c, 0x33, 0x00, 0x00, + 0x57, 0x52, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x00, 0x52, 0x44, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x00, + 0x6d, 0x61, 0x63, 0x61, 0x6e, 0x64, 0x64, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x00, 0x00, + 0x73, 0x65, 0x6e, 0x74, 0x00, 0x00, 0x00, 0x00, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x20, 0x73, 0x6c, + 0x65, 0x65, 0x70, 0x00, 0x77, 0x61, 0x6b, 0x65, 0x75, 0x70, 0x00, 0x00, 0x56, 0x19, 0x10, 0x00, + 0x94, 0x19, 0x10, 0x00, 0xc0, 0x19, 0x10, 0x00, 0xf0, 0x19, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, + 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, + 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, + 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0x0a, 0x1a, 0x10, 0x00, + 0x64, 0x1a, 0x10, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 0x00, 0x06, + 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x1f, 0x00, 0x06, 0x02, 0x00, 0x05, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x06, 0x03, 0x10, 0x08, 0x00, 0x00, 0x18, 0x00, 0x00, + 0x40, 0x1f, 0x00, 0x06, 0x06, 0x10, 0x08, 0x00, 0x04, 0x18, 0x00, 0x00, 0x60, 0x1f, 0x00, 0x06, + 0x04, 0x00, 0x09, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x06, 0x05, 0x05, 0x7f, 0x07, 0x01, + 0x08, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xf0, 0x01, 0x10, 0x10, 0x00, 0x04, 0x02, + 0x11, 0x00, 0x44, 0x02, 0x12, 0x00, 0x84, 0x02, 0x20, 0x90, 0x01, 0x03, 0x21, 0x80, 0x42, 0x03, + 0x22, 0xf0, 0x01, 0x03, 0x30, 0x80, 0x02, 0x04, 0x31, 0x80, 0x42, 0x04, 0x40, 0x70, 0x04, 0x11, + 0x41, 0x70, 0x44, 0x11, 0x42, 0x70, 0x84, 0x11, 0x50, 0xf0, 0x01, 0x12, 0x60, 0x32, 0x04, 0x13, + 0x61, 0x32, 0x44, 0x13, 0x62, 0x32, 0x84, 0x13, 0x63, 0x32, 0xc4, 0x13, 0x70, 0x32, 0x04, 0x14, + 0x71, 0x32, 0x44, 0x14, 0x80, 0x20, 0x04, 0x15, 0x81, 0x20, 0x84, 0x15, 0x82, 0x20, 0x44, 0x15, + 0x90, 0x51, 0x04, 0x16, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x14, 0x04, 0x04, + 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x20, 0x25, 0x6c, 0x75, 0x20, 0x00, 0x00, + 0x25, 0x73, 0x28, 0x25, 0x73, 0x29, 0x3a, 0x20, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, + 0x45, 0x00, 0x00, 0x00, 0x4d, 0x53, 0x47, 0x00, 0x43, 0x52, 0x43, 0x20, 0x72, 0x78, 0x3a, 0x20, + 0x25, 0x30, 0x34, 0x78, 0x2c, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x3a, 0x20, 0x25, 0x30, 0x34, 0x78, + 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0xe4, 0x1f, 0x10, 0x00, 0x04, 0x20, 0x10, 0x00, + 0x56, 0x20, 0x10, 0x00, 0xb8, 0x20, 0x10, 0x00, 0xc2, 0x20, 0x10, 0x00, 0x4f, 0x53, 0x00, 0x00, + 0x63, 0x6f, 0x6e, 0x64, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, 0x52, 0x58, 0x3a, 0x20, + 0x63, 0x6d, 0x64, 0x3d, 0x30, 0x78, 0x25, 0x30, 0x32, 0x78, 0x00, 0x00, 0x55, 0x49, 0x00, 0x00, + 0x43, 0x50, 0x42, 0x20, 0x49, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x20, 0x21, 0x00, + 0x43, 0x50, 0x42, 0x00, 0x57, 0x00, 0x00, 0x00, 0x46, 0x53, 0x53, 0x00, 0x49, 0x52, 0x51, 0x00, + 0x53, 0x54, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x4b, 0x44, 0x42, 0x00, 0x73, 0x74, 0x3a, 0x20, + 0x25, 0x78, 0x00, 0x00, 0x4d, 0x41, 0x44, 0x00, 0x4f, 0x54, 0x50, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x53, 0x43, 0x42, 0x00, 0x4e, 0x6f, 0x69, 0x73, 0x65, 0x5f, 0x4b, 0x4b, 0x31, 0x5f, 0x32, 0x35, + 0x35, 0x31, 0x39, 0x5f, 0x41, 0x45, 0x53, 0x47, 0x43, 0x4d, 0x5f, 0x53, 0x48, 0x41, 0x32, 0x35, + 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x3f, 0x10, 0x00, 0x78, 0x45, 0x10, 0x00, + 0x62, 0x45, 0x10, 0x00, 0x26, 0x45, 0x10, 0x00, 0x3a, 0x3e, 0x10, 0x00, 0xd0, 0x45, 0x10, 0x00, + 0x41, 0x4c, 0x41, 0x52, 0x4d, 0x20, 0x43, 0x48, 0x41, 0x4e, 0x4e, 0x45, 0x4c, 0x53, 0x3a, 0x20, + 0x25, 0x78, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x53, 0x43, 0x4e, 0x54, 0x52, 0x00, 0x00, 0x00, + 0x53, 0x50, 0x45, 0x43, 0x54, 0x00, 0x00, 0x00, 0xc3, 0x14, 0x13, 0x00}; \ No newline at end of file diff --git a/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_1_0_0/fw_SPECT.h b/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_1_0_0/fw_SPECT.h index b12a33d5f..6193db5c8 100644 --- a/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_1_0_0/fw_SPECT.h +++ b/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_1_0_0/fw_SPECT.h @@ -5,552 +5,655 @@ /** * @brief SPECT firmware version spect_app-v1.0.0_signed.bin for bootloader v1.0.1 */ -const uint8_t fw_SPECT[] - = {0x6b, 0xc1, 0x97, 0x12, 0x62, 0xd1, 0x74, 0x61, 0x11, 0xc6, 0x82, 0x39, 0x3d, 0xb0, 0x9f, 0xb7, 0xde, 0xb2, 0x09, - 0x47, 0x40, 0x54, 0xca, 0xc2, 0x3c, 0x86, 0x9f, 0x05, 0xdb, 0x0e, 0xd7, 0x70, 0xe8, 0x6a, 0x1d, 0xd0, 0x6d, 0xa3, - 0xf7, 0xea, 0x18, 0x4e, 0xda, 0x94, 0x1c, 0x24, 0xaf, 0x8d, 0x1b, 0x24, 0x34, 0x9c, 0x18, 0x17, 0x38, 0x15, 0x37, - 0xf6, 0xc8, 0x61, 0x81, 0x81, 0x7b, 0x05, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x02, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa8, 0x24, 0x00, 0x00, 0xd4, 0x7d, 0x50, 0x04, 0xb7, 0xcf, 0xe1, 0x1e, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, - 0x7e, 0xa3, 0xe4, 0xa3, 0x00, 0x82, 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, 0x40, 0xa2, 0xff, 0x00, 0x48, 0xa3, 0x00, - 0x02, 0x82, 0x62, 0xf0, 0x10, 0x88, 0xa2, 0x20, 0x33, 0x4a, 0xc5, 0x00, 0x10, 0x40, 0x28, 0x2c, 0xa3, 0x00, 0x08, - 0x60, 0x40, 0x40, 0x28, 0x4c, 0x80, 0x00, 0x88, 0x10, 0x40, 0x40, 0xa8, 0x84, 0x80, 0x00, 0x08, 0x40, 0x40, 0x40, - 0xa8, 0xb8, 0x80, 0x00, 0x08, 0x70, 0x40, 0x40, 0xa8, 0x20, 0x81, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0x04, 0xa4, - 0x00, 0x82, 0xf4, 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x60, 0x10, 0x40, 0x28, 0x1c, - 0x9f, 0x00, 0x08, 0x61, 0x10, 0x40, 0xa8, 0x1c, 0x9f, 0x00, 0x08, 0x62, 0x10, 0x40, 0xa8, 0xa4, 0x9f, 0x00, 0x08, - 0x63, 0x10, 0x40, 0x28, 0xb0, 0xa0, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0xf3, 0x50, 0x8a, - 0xa4, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x11, 0x10, 0x40, 0x28, 0x60, 0xa2, 0x00, 0x08, 0x12, 0x10, - 0x40, 0x28, 0x9c, 0xa2, 0x00, 0x08, 0x13, 0x10, 0x40, 0xa8, 0xbc, 0xa2, 0x00, 0x88, 0x14, 0x10, 0x40, 0x28, 0xe0, - 0xa2, 0x00, 0x88, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x04, 0xa4, 0x00, 0x82, 0xf2, 0x50, 0x8a, 0x24, - 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x41, 0x10, 0x40, 0x28, 0x94, 0x8f, 0x00, 0x88, 0x42, 0x10, 0x40, - 0x28, 0xac, 0x90, 0x00, 0x88, 0x43, 0x10, 0x40, 0xa8, 0xd4, 0x90, 0x00, 0x88, 0x44, 0x10, 0x40, 0x28, 0x04, 0x91, - 0x00, 0x88, 0x45, 0x10, 0x40, 0xa8, 0xfc, 0x91, 0x00, 0x08, 0x46, 0x10, 0x40, 0xa8, 0xa0, 0x92, 0x00, 0x08, 0x47, - 0x10, 0x40, 0x28, 0xf4, 0x92, 0x00, 0x88, 0x48, 0x10, 0x40, 0x28, 0x30, 0x93, 0x00, 0x88, 0x49, 0x10, 0x40, 0xa8, - 0x48, 0x93, 0x00, 0x88, 0x4a, 0x10, 0x40, 0xa8, 0x18, 0x94, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, - 0x18, 0x04, 0xa4, 0x00, 0x82, 0xf1, 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x70, 0x10, - 0x40, 0xa8, 0x1c, 0xa1, 0x00, 0x88, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x02, 0x00, 0x44, 0x23, 0x64, - 0x81, 0x00, 0x02, 0x00, 0x00, 0x44, 0x69, 0x00, 0x00, 0x42, 0xa3, 0xf3, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, - 0x40, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x84, 0x50, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, - 0xf3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, 0x00, 0xf5, 0x00, 0x00, 0x00, 0xf5, 0xff, 0x00, - 0x42, 0xa3, 0x00, 0x10, 0x02, 0xf3, 0xff, 0x10, 0x82, 0xa4, 0x80, 0x00, 0x80, 0xe2, 0x00, 0x00, 0x00, 0x84, 0xa8, - 0xa4, 0x00, 0x18, 0x00, 0x10, 0x02, 0xf3, 0x00, 0x10, 0x02, 0xf3, 0x80, 0x00, 0x40, 0xe2, 0x00, 0x11, 0x40, 0x49, - 0x00, 0x00, 0xc0, 0x93, 0x80, 0x10, 0x84, 0xff, 0x80, 0x20, 0x86, 0x7f, 0x80, 0x31, 0x88, 0xff, 0x00, 0x42, 0x88, - 0xff, 0x80, 0x41, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, - 0x88, 0xff, 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x06, 0x00, 0x7c, 0x23, 0x00, - 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0xdc, 0x81, 0x00, 0x8a, - 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x0f, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, - 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0xfc, 0x81, 0x00, 0x0a, 0x80, 0x42, 0x8c, 0xff, 0x00, 0x63, - 0x88, 0xff, 0x3f, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, - 0xe0, 0x7d, 0xa4, 0x1c, 0x82, 0x00, 0x8a, 0x00, 0x43, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, - 0x1e, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, - 0xa4, 0x40, 0x82, 0x00, 0x8a, 0x00, 0x43, 0x88, 0x7f, 0x40, 0x30, 0x4a, 0xc5, 0x80, 0x00, 0x7c, 0xa3, 0x00, 0x42, - 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x50, 0x0a, 0x63, 0x80, 0x82, 0x00, 0x8c, 0x00, 0x50, 0x0a, 0x63, 0x94, - 0x82, 0x00, 0x0e, 0x80, 0x40, 0x88, 0xff, 0x94, 0x82, 0x00, 0x98, 0x00, 0x50, 0x0a, 0x63, 0x90, 0x82, 0x00, 0x0c, - 0x00, 0x41, 0x88, 0xff, 0x94, 0x82, 0x00, 0x98, 0x80, 0x41, 0x88, 0x7f, 0x02, 0xe0, 0x7d, 0x24, 0x60, 0x82, 0x00, - 0x0a, 0x00, 0x40, 0x42, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x86, 0xef, 0x80, 0x30, 0x88, 0xef, 0x00, 0x42, - 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, - 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x31, 0x86, 0x6f, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, - 0x00, 0x32, 0x8a, 0x6f, 0x80, 0x52, 0x86, 0xef, 0x09, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x01, 0xe0, 0x7d, - 0x24, 0xe0, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x86, 0xef, 0x0a, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, - 0x86, 0xef, 0x02, 0xe0, 0x7d, 0x24, 0xf4, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x8a, 0xef, 0x80, 0x52, 0x86, 0xef, 0x80, - 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x1e, 0x00, 0x7c, 0x23, - 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, 0x20, 0x83, 0x00, - 0x0a, 0x80, 0x30, 0x86, 0x6f, 0x80, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, - 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x04, 0xe0, 0x7d, 0x24, 0x3c, 0x83, 0x00, 0x8a, 0x00, 0x31, 0x86, 0x6f, 0x20, - 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, - 0x04, 0xe0, 0x7d, 0x24, 0x5c, 0x83, 0x00, 0x8a, 0x00, 0x31, 0x86, 0x6f, 0x1e, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, - 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, 0x7c, 0x83, 0x00, 0x0a, 0x80, 0x32, - 0x86, 0xef, 0x00, 0x00, 0x00, 0x84, 0xa4, 0x82, 0x00, 0x02, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, - 0x30, 0x82, 0xef, 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x84, 0xe7, 0x80, 0x20, 0x88, 0xe7, 0x00, 0x42, 0x86, 0x67, - 0x80, 0x31, 0x86, 0x67, 0x80, 0x41, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, - 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x07, 0x00, 0x7c, 0xa3, 0x80, 0x31, - 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xdc, 0x83, 0x00, 0x0a, 0x80, 0x21, 0x8a, 0xe7, 0x80, 0x52, 0x86, 0x67, 0x0f, - 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xf4, 0x83, 0x00, 0x0a, 0x80, 0x51, 0x84, 0xe7, - 0x00, 0x21, 0x86, 0x67, 0x0f, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x0c, 0x84, 0x00, - 0x0a, 0x80, 0x51, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x22, 0x8a, 0x67, 0x80, 0x52, - 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x30, 0x84, 0x00, 0x0a, 0x80, - 0x51, 0x84, 0xe7, 0x00, 0x21, 0x86, 0x67, 0x63, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, - 0x48, 0x84, 0x00, 0x0a, 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, - 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x60, 0x84, 0x00, 0x0a, 0x80, 0x32, 0x84, 0xe7, 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, - 0x00, 0x02, 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x30, 0x86, 0xe7, 0x80, 0x31, 0x86, 0x67, 0x80, - 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x00, 0x32, 0x82, 0x67, 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, 0x00, 0x02, - 0x00, 0x21, 0x80, 0x67, 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, - 0xe7, 0x00, 0x00, 0x80, 0x67, 0x00, 0x21, 0x84, 0xe7, 0x80, 0x20, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x32, - 0x48, 0x45, 0x00, 0x22, 0x86, 0x67, 0x00, 0x21, 0x88, 0xe7, 0x80, 0x40, 0x88, 0xe8, 0xdc, 0x84, 0x00, 0x8a, 0x00, - 0x20, 0x42, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x30, 0x42, 0x63, 0x00, 0x00, 0x00, 0x84, 0x00, 0x90, 0x42, 0x63, - 0x74, 0x84, 0x00, 0x82, 0x80, 0x70, 0x8e, 0xe7, 0x80, 0x80, 0x90, 0xe7, 0x01, 0x00, 0x42, 0x23, 0x80, 0x70, 0x8e, - 0xe2, 0x00, 0x80, 0x10, 0xeb, 0x80, 0x83, 0x90, 0xe4, 0x00, 0x80, 0x10, 0xed, 0x00, 0x80, 0x10, 0xf9, 0x00, 0x00, - 0x00, 0x84, 0x00, 0xc0, 0x60, 0x63, 0x00, 0x00, 0x21, 0x63, 0x24, 0x85, 0x00, 0x8c, 0x00, 0x00, 0x6c, 0xa3, 0x2c, - 0x85, 0x00, 0x18, 0x01, 0x00, 0x6c, 0x23, 0x2c, 0x85, 0x00, 0x18, 0x00, 0x00, 0x21, 0x65, 0x00, 0x00, 0x59, 0x63, - 0x00, 0x08, 0xa1, 0xe7, 0x01, 0x00, 0x42, 0x23, 0x80, 0x00, 0xa9, 0xfd, 0x00, 0x03, 0xa1, 0x67, 0x80, 0x00, 0xab, - 0x7b, 0x80, 0x5a, 0xa5, 0x67, 0x80, 0x2a, 0xa5, 0xe7, 0x00, 0x2a, 0xa7, 0xe7, 0x00, 0x29, 0xa5, 0x67, 0x80, 0x2a, - 0xa5, 0xe7, 0x00, 0x2a, 0x83, 0xe7, 0x00, 0x10, 0x60, 0xe3, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0xa4, 0x67, 0x00, - 0x29, 0xa5, 0x67, 0x00, 0x28, 0xa5, 0xe7, 0x80, 0x29, 0xa5, 0xe7, 0x00, 0x29, 0xa1, 0xe7, 0x80, 0x0a, 0xa1, 0xe7, - 0x00, 0x32, 0x42, 0x45, 0x80, 0x20, 0xa3, 0xe7, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x0a, 0xbd, 0xe8, 0x9c, 0x85, 0x00, - 0x8a, 0x00, 0x20, 0x41, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x7c, 0x23, 0x00, 0xea, 0xa9, 0xfd, 0x00, 0x0a, - 0xbd, 0xe8, 0xb4, 0x85, 0x00, 0x8a, 0x00, 0x10, 0x41, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x10, 0x40, 0x28, 0x10, - 0x86, 0x00, 0x88, 0x00, 0x00, 0x42, 0xa3, 0x00, 0xe0, 0xbd, 0x68, 0xcc, 0x85, 0x00, 0x8a, 0x01, 0x10, 0x82, 0x24, - 0x01, 0x60, 0x41, 0xa8, 0xd8, 0x85, 0x00, 0x8a, 0x02, 0x10, 0x82, 0x24, 0x03, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, - 0x88, 0x00, 0x00, 0x46, 0x23, 0x00, 0x30, 0x86, 0xfd, 0x01, 0x00, 0x7c, 0xa3, 0x00, 0x0f, 0x82, 0xe2, 0x00, 0x1b, - 0x40, 0x68, 0x00, 0x86, 0x00, 0x8a, 0x00, 0x00, 0x56, 0x63, 0x08, 0x86, 0x00, 0x18, 0x00, 0x30, 0x56, 0x63, 0x08, - 0x86, 0x00, 0x18, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x00, 0x84, 0xff, 0x0f, 0x42, 0xa3, 0x00, 0x00, 0x00, 0x84, - 0x80, 0x83, 0x80, 0xfd, 0x80, 0xc5, 0x82, 0xfd, 0x80, 0x00, 0x80, 0xe7, 0x80, 0x83, 0x82, 0x7b, 0x80, 0xc5, 0x84, - 0xfb, 0x00, 0x11, 0x82, 0xe7, 0x00, 0xa7, 0x84, 0x67, 0x00, 0x23, 0x84, 0x67, 0x00, 0x21, 0x84, 0x7b, 0x80, 0x96, - 0x86, 0xe7, 0x80, 0x31, 0x86, 0xfb, 0x00, 0x10, 0x88, 0xfd, 0x00, 0x10, 0x80, 0x7b, 0x00, 0x31, 0x82, 0xfd, 0x00, - 0x31, 0x84, 0xfb, 0x80, 0x40, 0x96, 0xe7, 0x00, 0x40, 0x9c, 0x67, 0x00, 0x20, 0x98, 0xe7, 0x80, 0x20, 0x9a, 0xe7, - 0x00, 0x00, 0x00, 0x84, 0x80, 0x73, 0x80, 0x67, 0x00, 0x84, 0x82, 0xe7, 0x80, 0x94, 0x84, 0xe7, 0x00, 0x21, 0x84, - 0x7b, 0x80, 0x00, 0x86, 0x7b, 0x00, 0x74, 0x88, 0x7b, 0x00, 0x42, 0x88, 0xe7, 0x00, 0x32, 0x88, 0xfd, 0x80, 0x00, - 0x80, 0x7d, 0x00, 0x20, 0x82, 0xfb, 0x80, 0x40, 0x8e, 0xe7, 0x80, 0x00, 0x92, 0xe7, 0x80, 0x01, 0x90, 0xe7, 0x80, - 0x41, 0x94, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x4e, 0xa3, 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, 0xa3, - 0x00, 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, - 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, - 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0xb8, - 0x86, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x56, 0xc9, 0x20, 0x05, 0x58, 0xc9, 0x40, 0x05, 0x5a, 0x49, - 0x00, 0x00, 0x4e, 0xa3, 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, - 0xa3, 0x00, 0x00, 0xde, 0xf3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, - 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, - 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, - 0x14, 0x87, 0x00, 0x0a, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xb0, 0x4e, - 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, 0x68, 0x86, - 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x01, - 0xe0, 0x7d, 0x24, 0x50, 0x87, 0x00, 0x0a, 0x00, 0x00, 0x7c, 0x23, 0x80, 0xe3, 0x8f, 0xfd, 0x00, 0xe5, 0x95, 0xfd, - 0x18, 0x86, 0x00, 0x02, 0x80, 0xe3, 0x8f, 0xfd, 0x00, 0xe5, 0x95, 0xfd, 0x00, 0x05, 0x40, 0x45, 0x20, 0x05, 0x42, - 0x45, 0x40, 0x05, 0x44, 0x45, 0x80, 0x06, 0x80, 0xe7, 0x80, 0x16, 0x82, 0xe7, 0x00, 0xb1, 0x96, 0xe7, 0x00, 0xc1, - 0x98, 0xe7, 0x80, 0x05, 0xbc, 0xe8, 0xd4, 0x87, 0x00, 0x0a, 0x00, 0x16, 0xbc, 0xe8, 0xd4, 0x87, 0x00, 0x0a, 0x00, - 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x40, 0x31, 0x7e, 0xc5, - 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xae, 0x24, 0x80, 0x5b, 0xab, - 0x67, 0x00, 0x5b, 0xb1, 0x67, 0x80, 0x6b, 0xad, 0x67, 0x98, 0x96, 0x00, 0x02, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x00, - 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0x02, 0x56, 0x49, 0x20, - 0x02, 0x58, 0x49, 0x40, 0x02, 0x5a, 0xc9, 0x60, 0x02, 0x5c, 0x49, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, - 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0x02, 0x56, 0x45, 0x20, 0x02, 0x58, - 0x45, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, 0x45, 0x00, 0x02, 0x4e, 0x49, 0x20, 0x02, 0x50, 0xc9, 0x40, 0x02, - 0x52, 0x49, 0x60, 0x02, 0x54, 0xc9, 0x00, 0x50, 0x4f, 0xe3, 0x00, 0x60, 0x51, 0xe3, 0x00, 0x70, 0x53, 0xe3, 0x00, - 0x80, 0x55, 0xe3, 0x00, 0x00, 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, 0x00, 0x07, 0x9c, 0xfd, 0x18, 0x86, 0x00, 0x02, - 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, - 0xc5, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, - 0x00, 0x0a, 0x00, 0x02, 0x56, 0x45, 0x20, 0x02, 0x58, 0x45, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, 0x45, 0x18, - 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0x00, 0xe0, 0x54, 0x63, - 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, 0x74, 0x84, 0x00, 0x82, 0x80, 0xb0, 0xaa, - 0xe7, 0x80, 0xc0, 0xac, 0x67, 0x80, 0x5a, 0x83, 0xe7, 0x00, 0x6b, 0x85, 0xe7, 0x80, 0x20, 0x86, 0xfd, 0x00, 0x11, - 0x88, 0xe7, 0x00, 0x43, 0x88, 0x67, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x40, 0x88, 0xfb, 0x00, 0x32, 0x80, 0xe8, 0x08, - 0x89, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, - 0x80, 0x73, 0x80, 0x67, 0x00, 0x84, 0x82, 0xe7, 0x80, 0x94, 0x84, 0xe7, 0x00, 0x10, 0x86, 0x7d, 0x00, 0x31, 0x86, - 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x03, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x01, 0x80, 0x7b, 0x00, 0x30, - 0x86, 0x68, 0x48, 0x89, 0x00, 0x8a, 0x00, 0x74, 0x80, 0x67, 0x00, 0x95, 0x86, 0x67, 0x00, 0x30, 0x86, 0x68, 0x00, - 0x00, 0x00, 0x84, 0x00, 0x96, 0x80, 0xef, 0x80, 0xa6, 0x82, 0xef, 0x00, 0xb7, 0x84, 0x6f, 0x00, 0x95, 0x86, 0xfb, - 0x80, 0xc6, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x6f, 0x80, 0x00, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x7d, 0x80, 0xa5, 0x88, - 0xfb, 0x00, 0xd7, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xef, 0x00, 0x11, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xfd, 0x80, 0x95, - 0x8a, 0x7b, 0x00, 0xc7, 0x8c, 0x7b, 0x00, 0x53, 0x8a, 0xef, 0x00, 0x01, 0x8c, 0x7b, 0x00, 0x53, 0x8c, 0xfd, 0x00, - 0x81, 0x8e, 0x6f, 0x80, 0x63, 0x8a, 0x7d, 0x80, 0x52, 0x8e, 0x7b, 0x80, 0x53, 0x8a, 0x7b, 0x80, 0x12, 0x8e, 0xfd, - 0x80, 0x12, 0x8a, 0x7b, 0x00, 0x83, 0x8c, 0x6f, 0x00, 0x21, 0x82, 0x7b, 0x00, 0x11, 0x84, 0x7b, 0x00, 0x61, 0x8c, - 0x7d, 0x00, 0x60, 0x8c, 0xfd, 0x00, 0x63, 0x82, 0x7b, 0x00, 0x13, 0x8c, 0x7b, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, - 0x80, 0x7b, 0x00, 0x01, 0x80, 0x7d, 0x00, 0x43, 0x82, 0xef, 0x00, 0x03, 0x84, 0x6f, 0x80, 0x53, 0x8c, 0x6f, 0x00, - 0x61, 0x9a, 0xfb, 0x80, 0x32, 0x8a, 0xef, 0x80, 0x50, 0x98, 0x7d, 0x80, 0x43, 0x8e, 0x6f, 0x00, 0x30, 0x82, 0x6f, - 0x80, 0x70, 0x9c, 0x7b, 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0xef, 0x00, 0xa5, 0x82, 0x6f, 0x80, 0xb5, 0x84, - 0x6f, 0x00, 0x95, 0x86, 0xef, 0x80, 0x31, 0x86, 0xfb, 0x80, 0x95, 0x8e, 0xef, 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x81, - 0x8c, 0xef, 0x80, 0x63, 0x8c, 0x7d, 0x00, 0x63, 0x8a, 0xfb, 0x00, 0x53, 0x8c, 0xfb, 0x00, 0x13, 0x8a, 0x7d, 0x00, - 0x13, 0x8c, 0x7b, 0x00, 0x53, 0x8c, 0xef, 0x80, 0x51, 0x8a, 0xef, 0x00, 0x21, 0x86, 0xfb, 0x80, 0x21, 0x84, 0xfb, - 0x80, 0x83, 0x8e, 0x6f, 0x00, 0x71, 0x8e, 0x7d, 0x00, 0x70, 0x8e, 0xfd, 0x80, 0x73, 0x86, 0xfb, 0x80, 0x71, 0x8e, - 0xfb, 0x00, 0x00, 0x86, 0xfb, 0x00, 0x30, 0x80, 0xfb, 0x00, 0x01, 0x80, 0x7d, 0x80, 0x03, 0x80, 0x6f, 0x00, 0x60, - 0x8c, 0xfb, 0x80, 0xa5, 0x80, 0x6f, 0x00, 0x00, 0x80, 0xfb, 0x80, 0x03, 0x8e, 0xef, 0x80, 0x53, 0x8a, 0x7d, 0x80, - 0x00, 0x8e, 0xef, 0x80, 0x73, 0x8e, 0x7b, 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x50, 0x52, 0xe3, 0x00, 0x60, 0x54, 0xe3, - 0x00, 0x70, 0x56, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, 0x00, 0x56, - 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, - 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, - 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xa8, 0x8a, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, - 0x00, 0x05, 0x58, 0x49, 0x20, 0x05, 0x5a, 0x49, 0x40, 0x05, 0x5c, 0x49, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, - 0xa3, 0x00, 0x00, 0x56, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xde, 0xf3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xd0, - 0x3b, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, - 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, - 0xf8, 0x8a, 0x00, 0x0a, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, - 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, - 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x2c, 0x8b, 0x00, 0x8a, 0x00, - 0x00, 0x7c, 0x23, 0x00, 0xe5, 0x95, 0xfd, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe5, 0x95, 0xfd, 0x00, 0x05, 0x40, 0x45, - 0x20, 0x05, 0x42, 0x45, 0x40, 0x05, 0x44, 0x45, 0x00, 0x07, 0x80, 0x6f, 0x00, 0x17, 0x82, 0x6f, 0x00, 0xc1, 0x98, - 0x6f, 0x00, 0xd1, 0x9a, 0x6f, 0x00, 0x06, 0xbc, 0x68, 0xa0, 0x8b, 0x00, 0x0a, 0x80, 0x16, 0xbc, 0x68, 0xa0, 0x8b, - 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, - 0x30, 0x7e, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xb0, 0x24, - 0x00, 0x6c, 0xad, 0xef, 0x00, 0x7c, 0xaf, 0xef, 0xc8, 0x97, 0x00, 0x82, 0x00, 0x10, 0x53, 0xe3, 0x00, 0x20, 0x55, - 0xe3, 0x00, 0x30, 0x57, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, - 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0x80, 0x30, 0x50, 0x45, 0x00, 0x10, 0x59, 0xe3, 0x00, - 0x20, 0x5b, 0x63, 0x00, 0x30, 0x5d, 0xe3, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x94, 0x8c, 0x00, 0x0a, - 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0x00, 0x80, 0x68, 0x00, 0x60, 0x53, 0x6f, 0x00, 0x70, 0x55, - 0xef, 0x00, 0x80, 0x57, 0x6f, 0x00, 0x10, 0x59, 0xe3, 0x00, 0x20, 0x5b, 0x63, 0x00, 0x30, 0x5d, 0xe3, 0x80, 0x06, - 0x9a, 0xfd, 0x4c, 0x89, 0x00, 0x82, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x00, - 0x30, 0x7e, 0xc5, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x94, 0x8c, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, - 0x94, 0x8c, 0x00, 0x0a, 0x00, 0x60, 0x59, 0x63, 0x00, 0x70, 0x5b, 0x63, 0x00, 0x80, 0x5d, 0x63, 0x4c, 0x89, 0x00, - 0x82, 0x00, 0xc0, 0x52, 0xe3, 0x00, 0xd0, 0x54, 0x63, 0x00, 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, - 0x00, 0x0a, 0x00, 0xe0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0xc0, 0xac, 0xef, 0x80, 0xd0, 0xae, 0xef, 0x00, - 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x30, 0x40, 0x45, - 0x80, 0x30, 0x42, 0x45, 0x00, 0xa5, 0x86, 0xef, 0x80, 0x35, 0x86, 0x6f, 0x80, 0x94, 0x84, 0x6f, 0x80, 0x24, 0x84, - 0xef, 0x80, 0xb5, 0x88, 0x6f, 0x80, 0x45, 0x8a, 0xef, 0x80, 0x04, 0x80, 0xef, 0x00, 0x02, 0x80, 0x6f, 0x80, 0x12, - 0x82, 0xef, 0x80, 0x00, 0x80, 0x7b, 0x00, 0x01, 0x80, 0x7b, 0x80, 0x01, 0x80, 0x68, 0x00, 0x00, 0x00, 0x84, 0x60, - 0x32, 0x40, 0xc5, 0x00, 0x08, 0x80, 0xe7, 0x00, 0x08, 0x83, 0xe7, 0x00, 0x10, 0x82, 0xfb, 0x01, 0x00, 0x40, 0xa3, - 0x00, 0x10, 0x82, 0xfb, 0x00, 0x18, 0x82, 0xe7, 0x98, 0x84, 0x00, 0x02, 0x00, 0x10, 0x62, 0x63, 0x01, 0x00, 0x44, - 0x23, 0x00, 0x20, 0x84, 0x70, 0x00, 0x01, 0x84, 0x62, 0x00, 0x00, 0x00, 0x84, 0xc0, 0x32, 0x68, 0xc5, 0xe0, 0x32, - 0x6a, 0xc5, 0xa0, 0x32, 0x6c, 0x45, 0x00, 0x64, 0x8b, 0x67, 0x80, 0x53, 0x8a, 0x7b, 0x00, 0x66, 0x8d, 0xe7, 0x80, - 0x65, 0x8c, 0x7b, 0x00, 0x53, 0x80, 0x67, 0x80, 0x96, 0x82, 0x67, 0x00, 0x86, 0x84, 0x67, 0x80, 0x54, 0x86, 0xfb, - 0x80, 0x66, 0x88, 0xfb, 0x00, 0x32, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x7d, 0x00, 0x54, 0x88, - 0xfb, 0x00, 0x66, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0x67, 0x00, 0x01, 0x8a, 0x7b, 0x80, 0x42, 0x88, 0xfd, 0x00, 0x94, - 0x8a, 0x7b, 0x00, 0xd6, 0x96, 0xfb, 0x80, 0x55, 0x8a, 0xe7, 0x00, 0x11, 0x96, 0x7b, 0x80, 0x55, 0x8a, 0x7d, 0x00, - 0x42, 0x99, 0xe7, 0x00, 0x51, 0x97, 0xe7, 0x00, 0xb6, 0x98, 0x7b, 0x00, 0x16, 0x96, 0xfd, 0x00, 0x16, 0x98, 0x7b, - 0x00, 0xb6, 0x9a, 0x67, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x82, 0xfb, 0x00, 0x41, 0x85, 0x67, 0x00, 0x52, 0x89, - 0xe7, 0x00, 0x11, 0x82, 0x7b, 0x00, 0x01, 0x84, 0xfd, 0x00, 0x41, 0x85, 0x67, 0x00, 0x41, 0x88, 0x7b, 0x00, 0x12, - 0x80, 0x67, 0x00, 0xd0, 0x9a, 0xfb, 0x00, 0x52, 0x80, 0xe7, 0x80, 0x35, 0x96, 0x67, 0x00, 0xb0, 0x96, 0xfd, 0x80, - 0x30, 0x80, 0xe7, 0x00, 0x56, 0x98, 0x67, 0x00, 0xc0, 0x98, 0xfb, 0x00, 0x66, 0xad, 0x67, 0x00, 0xbb, 0x96, 0x7d, - 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0x67, 0x00, 0x04, 0x80, 0xe7, 0x60, 0x32, 0x42, 0x45, 0x80, 0x13, 0x82, - 0xe7, 0x00, 0x14, 0x82, 0x7b, 0x00, 0x14, 0x82, 0xe7, 0x80, 0x73, 0x84, 0xe7, 0x00, 0x11, 0x82, 0x7b, 0x80, 0x13, - 0x82, 0xe7, 0x80, 0x00, 0x80, 0xe8, 0x00, 0x00, 0x00, 0x84, 0x00, 0x74, 0x80, 0xfb, 0x00, 0x95, 0x82, 0x7d, 0x00, - 0x10, 0x82, 0x67, 0x00, 0x74, 0x80, 0xfd, 0x00, 0x95, 0x84, 0x7b, 0x00, 0x20, 0x84, 0x67, 0x00, 0x11, 0x86, 0xfb, - 0x80, 0x31, 0x86, 0x67, 0x00, 0x11, 0x88, 0x7d, 0x00, 0x42, 0x88, 0xe7, 0x00, 0x36, 0x92, 0x67, 0x00, 0xb2, 0x94, - 0x67, 0x00, 0x00, 0x00, 0x84, 0x00, 0x74, 0x82, 0x7b, 0x80, 0x10, 0x82, 0xe7, 0x00, 0x74, 0x84, 0x7d, 0x00, 0x21, - 0x84, 0xe7, 0x00, 0x11, 0x8e, 0xe7, 0x00, 0x11, 0x82, 0x7d, 0x80, 0x60, 0x86, 0xe7, 0x00, 0x31, 0x86, 0x7b, 0x80, - 0x11, 0x90, 0x67, 0x00, 0x00, 0x00, 0x84, 0x80, 0x32, 0x4c, 0x45, 0x00, 0xb0, 0x52, 0x63, 0x00, 0xc0, 0x54, 0xe3, - 0x01, 0x00, 0x4e, 0x23, 0x00, 0x00, 0x50, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xf6, 0xf3, 0x00, 0xb0, 0x37, - 0xeb, 0x00, 0xd0, 0x3b, 0xeb, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, - 0x00, 0x02, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x78, 0x8e, 0x00, 0x0a, 0x00, - 0x01, 0x7c, 0xa3, 0x00, 0xb0, 0x37, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, - 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, 0x00, 0x02, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, - 0x24, 0xa4, 0x8e, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x76, 0x80, 0xe7, 0x00, 0xb4, 0x82, 0xe7, 0x00, 0x86, - 0x84, 0x67, 0x60, 0x32, 0x4c, 0xc5, 0x00, 0x63, 0x86, 0xfb, 0x00, 0x31, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, 0x80, - 0x41, 0x88, 0xfb, 0x80, 0xb3, 0x8a, 0x67, 0x00, 0x51, 0x8a, 0x7b, 0x80, 0x42, 0x88, 0x67, 0x00, 0x31, 0x86, 0xe7, - 0x80, 0x41, 0x88, 0xfd, 0x00, 0x45, 0x88, 0x67, 0x80, 0x00, 0x82, 0xfd, 0x80, 0x10, 0x82, 0xe7, 0x80, 0x14, 0x82, - 0x67, 0x80, 0x40, 0x92, 0xfd, 0x80, 0xd6, 0x86, 0xfb, 0x00, 0x34, 0x86, 0xe7, 0x00, 0x35, 0x86, 0x67, 0x00, 0x30, - 0x8e, 0xe7, 0x00, 0x31, 0x90, 0x67, 0x00, 0x00, 0x00, 0x84, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, - 0x00, 0x42, 0xa3, 0x00, 0xe0, 0x45, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x47, 0xe5, 0x20, 0xe0, 0x7d, 0x22, - 0x00, 0xe0, 0x49, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4b, 0xe5, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4d, - 0xe5, 0x00, 0x20, 0x04, 0xf9, 0x00, 0x30, 0x06, 0xf9, 0x00, 0x40, 0x08, 0xf9, 0x00, 0x50, 0x0a, 0xf9, 0x00, 0x60, - 0x0c, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x11, 0x02, 0xfd, 0x80, 0x21, 0x04, 0x7d, 0x00, 0x32, 0x06, 0xfd, 0x80, - 0x42, 0x08, 0x7d, 0x00, 0x53, 0x0a, 0x7d, 0x00, 0x60, 0x0c, 0xf3, 0x00, 0x00, 0x00, 0x84, 0x58, 0x81, 0x00, 0x02, - 0x00, 0x00, 0x48, 0x22, 0x00, 0x40, 0x44, 0xe5, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x20, 0x2c, 0x63, 0x01, 0x60, 0x6b, - 0x22, 0x00, 0x00, 0x42, 0xa3, 0x04, 0x54, 0xe1, 0x35, 0x88, 0x90, 0x00, 0x9c, 0xff, 0x00, 0x40, 0x23, 0x00, 0x00, - 0xa3, 0xe2, 0x02, 0x10, 0x41, 0x28, 0x94, 0x90, 0x00, 0x8a, 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0x21, 0xf5, 0x00, - 0x00, 0x21, 0xf5, 0x00, 0x00, 0xa3, 0xe2, 0x00, 0x20, 0x84, 0x62, 0x00, 0x11, 0x41, 0xe8, 0xa0, 0x90, 0x00, 0x0a, - 0x05, 0x54, 0xf3, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x00, 0x03, 0x72, 0xc9, 0x05, 0x54, 0xc1, 0x39, 0x88, 0x90, 0x00, - 0x9c, 0x00, 0x60, 0x6b, 0xe3, 0x00, 0x54, 0xf5, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x01, 0x54, 0xef, 0xb5, 0x88, 0x90, - 0x00, 0x9c, 0x02, 0x54, 0xfb, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x03, 0x54, 0xfd, 0x35, 0x88, 0x90, 0x00, 0x9c, 0x05, - 0x54, 0xc1, 0x39, 0x88, 0x90, 0x00, 0x9c, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, - 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, 0x00, 0xd0, 0xbb, 0xfb, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x71, 0xaf, - 0xe8, 0x00, 0xe1, 0xbd, 0xe8, 0x00, 0x7f, 0xa9, 0x68, 0xe0, 0x03, 0x74, 0x49, 0x00, 0x04, 0x7a, 0xc9, 0xa0, 0x00, - 0x60, 0xc5, 0x00, 0x00, 0x21, 0xf9, 0xc0, 0x00, 0x62, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, - 0x81, 0x00, 0x98, 0x05, 0x54, 0xc1, 0x39, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x12, 0x00, 0x44, 0xa3, - 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x00, 0x84, 0x6c, 0x90, 0x00, 0x82, 0xf2, 0x00, 0x40, - 0xa3, 0x94, 0x81, 0x00, 0x98, 0x6c, 0x90, 0x00, 0x82, 0xf4, 0x00, 0x40, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x6c, 0x90, - 0x00, 0x82, 0xf6, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x00, 0x00, 0xce, 0x73, 0x00, 0x00, 0xd0, 0x73, 0x00, - 0x00, 0xd2, 0xf3, 0x00, 0x00, 0xd4, 0xf3, 0x00, 0x70, 0xc0, 0xe3, 0x0c, 0x40, 0xc1, 0xa5, 0x4c, 0xa3, 0x00, 0x02, - 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x30, 0x8f, 0x00, 0x02, 0x08, 0x00, 0x56, - 0x23, 0x12, 0x00, 0x58, 0x23, 0x78, 0x8f, 0x00, 0x02, 0x01, 0xc0, 0x58, 0x24, 0xe0, 0x90, 0x00, 0x8a, 0x00, 0x10, - 0xc0, 0xe9, 0x01, 0xb0, 0x56, 0x24, 0xdc, 0x90, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, - 0x81, 0x00, 0x98, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, 0x30, 0x8f, 0x00, 0x02, 0x80, 0x00, 0x5e, 0xa3, - 0x00, 0xf0, 0x1e, 0xf3, 0x00, 0xf0, 0x1e, 0xf3, 0x00, 0xf0, 0x1e, 0xf3, 0x12, 0xb0, 0x56, 0xa4, 0x80, 0xb7, 0xa0, - 0x62, 0x44, 0x91, 0x00, 0x8a, 0x12, 0x00, 0x58, 0x23, 0x78, 0x8f, 0x00, 0x02, 0x01, 0xc0, 0x58, 0x24, 0x30, 0x91, - 0x00, 0x8a, 0x00, 0x10, 0xc0, 0xe9, 0x20, 0x91, 0x00, 0x18, 0x12, 0xb0, 0x56, 0xa2, 0x88, 0x91, 0x00, 0x08, 0x12, - 0x00, 0x58, 0x23, 0x80, 0xc5, 0x58, 0xe4, 0x78, 0x8f, 0x00, 0x02, 0x01, 0xb0, 0x56, 0x24, 0x54, 0x91, 0x00, 0x0a, - 0x01, 0xc0, 0x40, 0x28, 0x9c, 0x91, 0x00, 0x08, 0x04, 0x00, 0x44, 0x23, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x11, 0x02, - 0xfd, 0x00, 0x20, 0x04, 0xf3, 0x01, 0xc0, 0x58, 0x24, 0x70, 0x91, 0x00, 0x0a, 0x80, 0x10, 0x82, 0x24, 0xac, 0x91, - 0x00, 0x98, 0x00, 0x00, 0x42, 0xa3, 0x8a, 0x00, 0x46, 0xa3, 0x80, 0x11, 0xc2, 0xe2, 0x80, 0x10, 0x82, 0x24, 0xac, - 0x91, 0x00, 0x98, 0x84, 0x00, 0x44, 0xa3, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x11, 0x02, 0xfd, 0xac, 0x91, 0x00, 0x98, - 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf6, 0x71, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x70, 0xce, 0xeb, 0x00, 0x70, 0xd2, - 0x6b, 0x00, 0x70, 0xc0, 0xe3, 0x0c, 0xb0, 0xc1, 0xa5, 0x04, 0x00, 0x42, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x10, - 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xd0, 0x91, 0x00, 0x0a, 0x80, 0x10, 0x82, 0x24, 0x00, 0x10, 0xc0, 0xe9, 0x00, - 0x00, 0xf8, 0xf1, 0x60, 0x31, 0x7e, 0x45, 0x80, 0xcd, 0xb7, 0xf9, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, - 0x94, 0x81, 0x00, 0x98, 0x40, 0x31, 0x7e, 0xc5, 0xc0, 0x31, 0x6a, 0x45, 0xe0, 0x31, 0x6c, 0xc5, 0xdc, 0x87, 0x00, - 0x02, 0x01, 0x00, 0x42, 0x23, 0x80, 0x50, 0xab, 0xe2, 0x00, 0x50, 0x2b, 0xed, 0x80, 0x6a, 0xad, 0xe4, 0x00, 0x60, - 0x2d, 0xf9, 0x20, 0x03, 0x6c, 0x49, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x58, 0x81, 0x00, 0x02, 0x00, - 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x6b, 0x65, 0x00, 0x50, 0x2b, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x69, 0xe5, - 0x00, 0x40, 0x29, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x67, 0x65, 0x00, 0x30, 0x27, 0xf9, 0x20, 0xe0, 0x7d, - 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x20, 0x25, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x4c, 0x23, 0x00, 0x60, - 0x8a, 0x70, 0x60, 0xb0, 0x92, 0x22, 0x1f, 0xb0, 0x90, 0x22, 0x20, 0x00, 0x4e, 0x23, 0x00, 0x74, 0x50, 0xe4, 0x00, - 0x80, 0x4e, 0xe3, 0x00, 0x70, 0x0e, 0x63, 0x00, 0x70, 0x0e, 0x63, 0x00, 0x70, 0x0e, 0x63, 0x01, 0x70, 0x4e, 0x24, - 0x00, 0x53, 0x0a, 0x7d, 0x01, 0x80, 0x50, 0x24, 0x90, 0x92, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, 0x70, 0x81, 0x00, - 0x02, 0x00, 0x00, 0x56, 0x63, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x67, 0x65, 0x20, 0xe0, - 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x20, 0x25, 0xf9, 0x00, 0x03, 0x68, 0x45, 0x20, - 0x03, 0x6a, 0x45, 0x40, 0xb0, 0x7a, 0xa2, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, - 0x00, 0x00, 0xc0, 0x2d, 0x64, 0x92, 0x00, 0x82, 0x20, 0x90, 0x40, 0x28, 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, - 0xe3, 0xac, 0x93, 0x00, 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x67, 0x65, 0x20, 0xe0, - 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x20, 0x25, 0xf9, 0x00, 0x03, 0x68, 0x45, 0x20, - 0x03, 0x6a, 0x45, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x20, 0xe1, 0x6b, 0x80, 0x00, 0x7a, 0xa3, 0x00, 0x00, 0x40, 0x23, - 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x2c, 0x92, 0x00, 0x82, 0x00, 0x20, 0xe1, 0x6b, 0x80, 0xd0, 0x7b, - 0x22, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, - 0x56, 0x63, 0x80, 0xd5, 0x7b, 0xe2, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x2c, - 0x92, 0x00, 0x82, 0x80, 0xb0, 0x40, 0xa8, 0xdc, 0x93, 0x00, 0x08, 0x64, 0x92, 0x00, 0x82, 0x60, 0x90, 0x40, 0xa8, - 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, 0xe3, 0x40, 0x90, 0x40, 0x28, 0xac, 0x93, 0x00, 0x88, 0x00, 0x00, 0x66, - 0xa3, 0x20, 0x90, 0x40, 0x28, 0xa0, 0x93, 0x00, 0x88, 0x00, 0x00, 0x68, 0x23, 0x80, 0x52, 0xab, 0x62, 0x80, 0x53, - 0xeb, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x42, 0xa9, 0x62, 0x80, 0x43, 0xe9, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, - 0x32, 0xa7, 0x62, 0x80, 0x33, 0xe7, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x22, 0xa5, 0x62, 0x80, 0x23, 0xe5, 0x62, - 0x10, 0xb0, 0x90, 0x22, 0xd0, 0x93, 0x00, 0x8a, 0x80, 0x2e, 0xa5, 0x64, 0xf8, 0x93, 0x00, 0x98, 0x00, 0x20, 0xe1, - 0x6b, 0x00, 0x00, 0x6a, 0xa3, 0xec, 0x93, 0x00, 0x98, 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x6a, 0xa3, 0xff, 0x00, - 0x4e, 0xa3, 0x80, 0x53, 0xeb, 0x62, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x66, 0xa3, 0x00, 0xd0, 0x65, 0xe3, 0x60, - 0x31, 0x7e, 0x45, 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x21, 0xf9, 0x00, 0x10, 0x23, 0xf9, 0x80, 0x08, 0xb3, 0x79, - 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x60, 0x31, 0x7e, 0x45, 0xe0, 0x03, 0x74, - 0x45, 0x00, 0x04, 0x44, 0x45, 0x80, 0xac, 0x83, 0xff, 0x80, 0x2c, 0x84, 0xff, 0x80, 0xb0, 0x87, 0x7b, 0x00, 0x31, - 0x86, 0x7b, 0x40, 0x03, 0x46, 0xc9, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0x03, 0x58, 0x45, 0x00, - 0xc0, 0x18, 0xf9, 0x10, 0x85, 0x00, 0x82, 0x00, 0x10, 0xbc, 0x28, 0x10, 0x95, 0x00, 0x8a, 0x01, 0x00, 0x5a, 0x23, - 0x00, 0xb6, 0x9c, 0x67, 0x00, 0x90, 0x79, 0xe3, 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x4e, 0xc9, 0x80, 0x03, 0x50, - 0x49, 0xa0, 0x03, 0x52, 0x49, 0xc0, 0x03, 0x54, 0x49, 0x40, 0x03, 0x78, 0x45, 0xc0, 0x31, 0x56, 0x45, 0xe0, 0x31, - 0x58, 0x45, 0x01, 0x00, 0x5a, 0x23, 0x00, 0xb6, 0x9c, 0x67, 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x56, 0xc5, 0x80, - 0x03, 0x58, 0xc5, 0xa0, 0x03, 0x5a, 0xc5, 0xc0, 0x03, 0x5c, 0xc5, 0x00, 0x00, 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, - 0x00, 0x07, 0x9c, 0xfd, 0x18, 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, - 0x63, 0xe4, 0x84, 0x00, 0x82, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x20, 0x03, 0x48, 0x45, 0xff, 0x0f, - 0x7e, 0xa3, 0x00, 0xf0, 0x41, 0x28, 0x00, 0x82, 0x84, 0xe8, 0x18, 0x95, 0x00, 0x0a, 0x00, 0xf0, 0x41, 0x28, 0x00, - 0x82, 0x84, 0xe8, 0x18, 0x95, 0x00, 0x0a, 0xc3, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x10, 0x00, 0x7c, 0x22, - 0x40, 0x03, 0x4a, 0xc5, 0x00, 0x40, 0x08, 0xf9, 0x00, 0xe0, 0x49, 0x69, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4b, - 0xe9, 0x00, 0x00, 0x40, 0x23, 0x50, 0x00, 0x42, 0xa3, 0x2c, 0x95, 0x00, 0x98, 0x36, 0x00, 0x40, 0x23, 0x1c, 0x95, - 0x00, 0x98, 0x36, 0x00, 0x40, 0x23, 0x3c, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, 0x42, 0x23, 0x2c, - 0x95, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x94, 0x81, 0x00, 0x98, 0x00, 0x00, 0x8c, 0x67, - 0x00, 0x63, 0x8c, 0xfb, 0x01, 0x00, 0x7c, 0xa3, 0x00, 0x6f, 0x8e, 0x7b, 0x00, 0x70, 0xbc, 0x28, 0x6c, 0x96, 0x00, - 0x88, 0x60, 0x32, 0x50, 0x45, 0x00, 0x00, 0x7c, 0x23, 0x00, 0xe4, 0x93, 0x7d, 0x00, 0x83, 0x90, 0x67, 0x80, 0x73, - 0x94, 0x67, 0x80, 0xa3, 0x96, 0x67, 0x80, 0x84, 0x90, 0x67, 0x00, 0x85, 0x90, 0xfb, 0x80, 0x84, 0x90, 0x67, 0x80, - 0xb5, 0x98, 0x67, 0x00, 0xc6, 0x94, 0x67, 0x80, 0xc5, 0x98, 0xe7, 0x00, 0xc4, 0x98, 0xe7, 0x00, 0xa6, 0x94, 0x67, - 0x00, 0xa0, 0x42, 0x63, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x25, 0x9a, - 0x67, 0x00, 0xd6, 0x9a, 0x67, 0x00, 0x32, 0x7c, 0xc5, 0x00, 0xdf, 0x9c, 0x67, 0x80, 0xd6, 0x94, 0x67, 0x80, 0xa5, - 0x94, 0xe7, 0x00, 0xa4, 0x88, 0x68, 0xc0, 0x95, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, 0xc8, 0x95, 0x00, 0x98, 0x00, - 0xe0, 0x42, 0xe3, 0xc8, 0x95, 0x00, 0x98, 0x00, 0x93, 0x84, 0xe7, 0x00, 0xd0, 0x86, 0xe7, 0x01, 0xe0, 0x89, 0xa4, - 0x00, 0x32, 0x86, 0xe7, 0x00, 0x3f, 0x88, 0xe7, 0x00, 0x83, 0x8c, 0xe7, 0x80, 0x31, 0x94, 0x67, 0x80, 0xa5, 0x94, - 0xe7, 0x00, 0xa3, 0xbc, 0xfd, 0x00, 0xe0, 0xbd, 0xa8, 0xfc, 0x95, 0x00, 0x0a, 0x00, 0x30, 0x40, 0xe3, 0x04, 0x96, - 0x00, 0x98, 0x00, 0x40, 0x40, 0x63, 0x04, 0x96, 0x00, 0x98, 0x80, 0x10, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, - 0xa4, 0xbc, 0x7d, 0x00, 0xe0, 0xbd, 0xa8, 0x20, 0x96, 0x00, 0x8a, 0x00, 0x90, 0x46, 0xe3, 0x28, 0x96, 0x00, 0x18, - 0x00, 0x20, 0x46, 0x63, 0x28, 0x96, 0x00, 0x18, 0x38, 0x96, 0x00, 0x8a, 0x00, 0x10, 0x44, 0xe3, 0x01, 0x00, 0x7c, - 0xa3, 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, 0x44, 0x63, 0x00, 0x00, 0x7c, 0x23, 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, - 0x40, 0x23, 0x00, 0x01, 0x82, 0xfd, 0x01, 0x00, 0x50, 0x23, 0x00, 0x24, 0x8c, 0x62, 0x00, 0xe3, 0xbd, 0x68, 0x64, - 0x96, 0x00, 0x08, 0x00, 0x10, 0x56, 0xe3, 0x6c, 0x96, 0x00, 0x18, 0x00, 0x20, 0x56, 0xe3, 0x6c, 0x96, 0x00, 0x18, - 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, - 0x02, 0x00, 0x70, 0xbc, 0x28, 0x70, 0x96, 0x00, 0x08, 0x80, 0xb3, 0x9a, 0xe7, 0x00, 0x30, 0x56, 0x63, 0x00, 0x70, - 0x58, 0x63, 0x00, 0x00, 0x00, 0x84, 0x40, 0x31, 0x7e, 0xc5, 0x00, 0x05, 0x42, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0xb4, - 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, 0x02, 0x00, 0x70, 0xbc, 0x28, 0x98, 0x96, 0x00, 0x08, 0x00, 0x33, 0x7c, 0x45, - 0x00, 0x3f, 0x94, 0x67, 0x80, 0x75, 0x9a, 0xe7, 0x80, 0x33, 0x98, 0x7d, 0x80, 0x33, 0x9c, 0xfb, 0x00, 0xd7, 0x80, - 0x67, 0x00, 0x00, 0xbc, 0xa8, 0x98, 0x96, 0x00, 0x08, 0x00, 0xa7, 0x96, 0x67, 0x80, 0xc6, 0x98, 0xe7, 0x00, 0xb6, - 0x9c, 0x67, 0x00, 0xb0, 0x96, 0x67, 0x00, 0xc0, 0x98, 0x67, 0x00, 0x00, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x00, - 0x08, 0x8d, 0xef, 0x00, 0x06, 0x8f, 0xef, 0x80, 0x63, 0x8c, 0x6f, 0x00, 0x60, 0x42, 0x63, 0xa4, 0x82, 0x00, 0x02, - 0x00, 0x30, 0x52, 0xe3, 0x80, 0x93, 0x92, 0x6f, 0x00, 0x31, 0x40, 0xc5, 0x00, 0x90, 0x94, 0xef, 0x80, 0x94, 0x90, - 0x6f, 0x00, 0x88, 0x90, 0x6f, 0x00, 0x86, 0x80, 0xe8, 0x00, 0x90, 0x54, 0xef, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, - 0x68, 0xe3, 0x20, 0x31, 0x40, 0x45, 0x60, 0x30, 0x42, 0xc5, 0x80, 0x30, 0x44, 0x45, 0x00, 0x4a, 0x97, 0x6f, 0x80, - 0x05, 0x96, 0xef, 0x80, 0xb5, 0x98, 0xef, 0x80, 0xc5, 0x98, 0x7b, 0x01, 0x00, 0x48, 0x23, 0x00, 0xc2, 0x9a, 0xfb, - 0x80, 0x26, 0x9a, 0x6f, 0x00, 0x00, 0x48, 0xa3, 0x00, 0x46, 0x9c, 0xfd, 0x00, 0xc0, 0x80, 0xa8, 0x00, 0xe0, 0x40, - 0x6f, 0x00, 0x17, 0x9c, 0x6f, 0x80, 0xd6, 0x98, 0xef, 0x00, 0xe7, 0xa0, 0x6f, 0x00, 0x18, 0x9e, 0xef, 0x80, 0xc7, - 0x98, 0xfb, 0x80, 0xc6, 0x98, 0x6f, 0x00, 0x07, 0xa1, 0x6f, 0x00, 0x28, 0x9e, 0xef, 0x80, 0xc7, 0x98, 0xfb, 0x80, - 0xb6, 0xa2, 0xef, 0xf0, 0x96, 0x00, 0x82, 0x00, 0xba, 0xa4, 0x6f, 0x00, 0x25, 0xa5, 0xef, 0x00, 0xd0, 0x62, 0x6f, - 0x00, 0xa0, 0x64, 0xef, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x19, 0x82, 0xfd, 0x00, 0x49, 0x81, 0x68, 0x01, 0x00, 0x44, - 0x23, 0x00, 0x01, 0x80, 0xe2, 0x00, 0x10, 0x64, 0x6f, 0x00, 0x10, 0x64, 0x63, 0x00, 0x27, 0xa5, 0x6f, 0x00, 0xe0, - 0x66, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x42, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0xb4, 0xa3, 0x00, 0x82, 0x28, - 0x97, 0x00, 0x02, 0x00, 0x30, 0xbd, 0x28, 0xc8, 0x97, 0x00, 0x88, 0x00, 0x00, 0x00, 0x84, 0x20, 0x30, 0x7e, 0x45, - 0x60, 0x10, 0x40, 0x28, 0x18, 0x98, 0x00, 0x08, 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x66, 0xe5, 0x00, 0x30, 0x27, - 0xf9, 0x00, 0x00, 0x68, 0x23, 0x80, 0x49, 0xb9, 0x79, 0x80, 0xc9, 0x83, 0xe8, 0xb4, 0x99, 0x00, 0x0a, 0x00, 0xc0, - 0x83, 0xa8, 0xb4, 0x99, 0x00, 0x88, 0x2c, 0x98, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, 0x00, 0x00, 0xe8, 0xf3, 0x80, - 0x49, 0xb9, 0x79, 0x00, 0xc0, 0x83, 0xa8, 0xb4, 0x99, 0x00, 0x88, 0x00, 0x00, 0xc0, 0xf3, 0x00, 0x00, 0xc2, 0x73, - 0x00, 0x00, 0xc4, 0x73, 0x00, 0x00, 0xc6, 0xf3, 0x00, 0x00, 0xc0, 0x63, 0x0a, 0xc0, 0xc1, 0x25, 0x04, 0x00, 0x44, - 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x04, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x4c, 0x98, 0x00, 0x0a, 0x80, 0x20, - 0x84, 0x24, 0x00, 0x20, 0xc0, 0xe9, 0x00, 0x00, 0xfa, 0x71, 0x20, 0x01, 0x78, 0xc9, 0x40, 0x01, 0x7a, 0x49, 0x20, - 0x30, 0x7e, 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xcf, 0xf9, 0xff, 0x00, 0x30, 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, - 0xc0, 0x30, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, - 0x82, 0x01, 0x00, 0x9c, 0xa4, 0x00, 0xc7, 0x98, 0x6f, 0x00, 0xd7, 0x9a, 0x6f, 0x00, 0xc0, 0x52, 0xe3, 0x00, 0xd0, - 0x54, 0x63, 0x00, 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0xc0, 0x99, 0x00, 0x0a, 0x80, 0x30, 0x50, 0x45, 0xd8, - 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0xc0, 0x99, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0xc0, 0x99, 0x00, 0x0a, - 0x00, 0xb0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0x90, 0x92, 0x6f, 0x80, 0xa0, 0x94, 0x6f, 0x00, 0x90, 0x19, - 0x6d, 0x00, 0xc0, 0x18, 0xf3, 0xaa, 0xc0, 0x98, 0xa4, 0x00, 0xc0, 0x18, 0xf3, 0x00, 0x01, 0x40, 0xc5, 0xff, 0x00, - 0x48, 0xa3, 0x00, 0x02, 0xa8, 0xe2, 0x60, 0x40, 0x41, 0xa8, 0x08, 0x99, 0x00, 0x08, 0x02, 0xc0, 0x98, 0x24, 0x0c, - 0x99, 0x00, 0x18, 0x01, 0xc0, 0x98, 0x24, 0x00, 0xc0, 0x18, 0xf3, 0x01, 0xc0, 0x98, 0x24, 0x04, 0xa4, 0xd9, 0x37, - 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xd3, 0xb7, 0xb4, 0x99, 0x00, 0x9c, 0x06, 0xa4, 0xd5, 0xb7, 0xb4, 0x99, 0x00, - 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, 0x00, 0x9c, 0x20, 0x01, - 0x78, 0xc5, 0x40, 0x01, 0x7a, 0x45, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, - 0xa3, 0x00, 0x82, 0x00, 0xc0, 0xb9, 0xfd, 0x00, 0x00, 0xc4, 0x73, 0x00, 0xd1, 0xbb, 0xe8, 0x00, 0x90, 0x75, 0xe3, - 0xff, 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, 0x80, 0xc4, 0x94, 0x68, 0x00, 0xa4, 0xf9, - 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0x37, 0xb4, 0x99, - 0x00, 0x9c, 0x03, 0xa4, 0xc5, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x04, 0xa4, 0xd5, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x02, - 0xa4, 0xc1, 0xb9, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, - 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, - 0x39, 0x41, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x10, 0x40, 0x28, 0xe0, 0x99, 0x00, 0x08, 0x10, 0x00, - 0x48, 0xa2, 0x00, 0x40, 0x66, 0xe5, 0xe4, 0x99, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, 0x01, 0x00, 0x64, 0xa3, 0x00, - 0x20, 0x25, 0xed, 0x00, 0x00, 0x62, 0x23, 0x00, 0x01, 0x60, 0x23, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x00, 0xc0, 0x2d, - 0x00, 0x00, 0xf9, 0xeb, 0x00, 0xd0, 0x3b, 0xf9, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, - 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x0e, 0xba, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0xd0, 0xfb, 0x62, 0x00, 0xc0, - 0x39, 0xf9, 0x20, 0x01, 0x7a, 0x49, 0x40, 0x01, 0x78, 0xc9, 0x00, 0x00, 0xfc, 0xf3, 0x60, 0x31, 0x7e, 0x45, 0x00, - 0xdf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xc0, 0x31, 0x56, 0x45, 0xe0, 0x31, 0x58, 0x45, 0x00, 0x00, 0xc4, 0x73, - 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x9a, 0xa4, 0x80, 0xb6, 0x96, 0xe7, 0x00, 0xb6, 0x9c, - 0x67, 0x80, 0xc6, 0x98, 0xe7, 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, - 0x52, 0x63, 0x00, 0xe0, 0x54, 0x63, 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, 0xf0, 0x86, 0x00, 0x02, 0x00, - 0x00, 0x40, 0xa8, 0x70, 0x9b, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, 0xe4, 0x84, 0x00, 0x82, - 0x00, 0x90, 0x15, 0x6d, 0x00, 0xa0, 0x14, 0xf3, 0xaa, 0xa0, 0x94, 0xa4, 0x00, 0xa0, 0x14, 0xf3, 0x00, 0x01, 0x40, - 0xc5, 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0x92, 0xe2, 0x60, 0x90, 0x40, 0xa8, 0xc0, 0x9a, 0x00, 0x88, 0x02, 0xa0, - 0x94, 0x24, 0xc4, 0x9a, 0x00, 0x98, 0x01, 0xa0, 0x94, 0x24, 0x00, 0xa0, 0x14, 0xf3, 0x02, 0xa0, 0x94, 0x24, 0x04, - 0xa4, 0xd5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xd1, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, - 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0x9b, 0x00, 0x9c, 0x20, 0x01, 0x78, 0xc5, 0x40, 0x01, 0x7a, - 0x45, 0x00, 0x00, 0x40, 0x23, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x0e, 0xbc, 0xf9, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, - 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x80, 0x24, 0x00, 0xe0, 0xb9, 0x7d, 0x00, 0x00, 0xc4, 0x73, 0x00, - 0xd1, 0xbb, 0xe8, 0x00, 0x90, 0x75, 0xe3, 0xff, 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, - 0x80, 0xa4, 0x94, 0x68, 0x00, 0xa4, 0xf9, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, 0x7c, 0x9b, 0x00, - 0x9c, 0x02, 0xa4, 0xc1, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x03, 0xa4, 0xc5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x04, 0xa4, - 0xd5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0x7c, - 0x9b, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0x41, 0x00, 0x46, 0x23, - 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xc6, - 0xf3, 0x00, 0x00, 0xc8, 0x73, 0x00, 0x00, 0xca, 0xf3, 0x00, 0x00, 0xcc, 0xf3, 0x00, 0x30, 0xc0, 0x63, 0x0b, 0x40, - 0xc1, 0x25, 0x4c, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x43, 0x63, 0x80, - 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xb0, 0x9b, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, - 0x0e, 0x00, 0x7c, 0xa3, 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xc8, 0x9b, 0x00, - 0x0a, 0x04, 0x00, 0x7c, 0xa3, 0x00, 0x00, 0x42, 0xa3, 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, - 0x7d, 0x24, 0xe0, 0x9b, 0x00, 0x0a, 0x1a, 0x00, 0x7c, 0xa3, 0x00, 0x0f, 0xc0, 0xe2, 0x80, 0x00, 0x80, 0x24, 0x00, - 0x00, 0xc0, 0x69, 0x00, 0x00, 0xf6, 0x71, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x30, 0xc6, 0xeb, 0x00, 0x30, 0xca, 0xeb, - 0x00, 0x30, 0xc0, 0x63, 0x0b, 0xb0, 0xc1, 0x25, 0x04, 0x00, 0x42, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x10, 0x02, - 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x20, 0x9c, 0x00, 0x8a, 0x80, 0x10, 0x82, 0x24, 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, - 0xf8, 0xf1, 0x20, 0x01, 0x64, 0x49, 0x20, 0x30, 0x7e, 0x45, 0x80, 0xcd, 0xb7, 0xf9, 0x00, 0xb0, 0x81, 0xa8, 0xdc, - 0x9d, 0x00, 0x88, 0xa0, 0x30, 0x6c, 0xc5, 0xc0, 0x30, 0x6e, 0x45, 0xa8, 0x8b, 0x00, 0x02, 0x00, 0x00, 0x46, 0xe3, - 0x00, 0x00, 0x40, 0xa8, 0xfc, 0x9d, 0x00, 0x8a, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x0b, 0xac, - 0x79, 0x00, 0x60, 0x81, 0x28, 0xe4, 0x9d, 0x00, 0x08, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, - 0x00, 0x82, 0x00, 0x00, 0x72, 0x63, 0x01, 0x90, 0xb3, 0x24, 0x80, 0x9d, 0x83, 0x7f, 0xa8, 0x81, 0x00, 0x02, 0x20, - 0x01, 0x64, 0x45, 0x80, 0x2c, 0x95, 0xff, 0x80, 0x6c, 0x97, 0xff, 0x80, 0xa5, 0x99, 0x7f, 0x80, 0x55, 0x9b, 0xff, - 0x80, 0xc6, 0x96, 0xfb, 0x80, 0xa5, 0x94, 0x7b, 0x00, 0x15, 0x94, 0xff, 0x00, 0xa0, 0x80, 0xa8, 0xec, 0x9d, 0x00, - 0x88, 0x40, 0x01, 0x54, 0x49, 0x00, 0xa0, 0x42, 0x63, 0xa8, 0x81, 0x00, 0x02, 0x80, 0x20, 0xb9, 0x7f, 0x80, 0x60, - 0xb7, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, 0xc0, 0x30, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x94, - 0x8a, 0x00, 0x82, 0x00, 0x90, 0x5e, 0xe3, 0x00, 0xa0, 0x60, 0x63, 0x00, 0xb0, 0x62, 0x63, 0x60, 0x01, 0x58, 0xc5, - 0x80, 0x01, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0xb0, 0x79, 0x63, 0x94, 0x8a, 0x00, 0x82, 0x80, 0xf5, 0x84, - 0xef, 0x80, 0x98, 0x86, 0xef, 0x80, 0x21, 0x80, 0xe8, 0x38, 0x9d, 0x00, 0x0a, 0x80, 0x05, 0x85, 0x6f, 0x80, 0xa8, - 0x86, 0xef, 0x80, 0x21, 0x80, 0xe8, 0xf4, 0x9d, 0x00, 0x0a, 0xfc, 0x89, 0x00, 0x02, 0x00, 0x90, 0x58, 0xe3, 0x00, - 0xa0, 0x5a, 0x63, 0x00, 0xb0, 0x5c, 0xe3, 0x48, 0x9d, 0x00, 0x98, 0x00, 0xf0, 0x58, 0xe3, 0x00, 0x00, 0x5b, 0xe3, - 0x00, 0x10, 0x5d, 0x63, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0xc0, 0x98, - 0x6f, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x06, 0x98, 0x79, 0x00, 0x00, 0x7e, 0xa3, 0x00, 0xf0, - 0x41, 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, 0x9d, 0x00, 0x0a, 0x00, 0xf0, 0x41, 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, - 0x9d, 0x00, 0x0a, 0x00, 0x00, 0x46, 0x23, 0xc3, 0x00, 0x44, 0xa3, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, - 0x00, 0xe0, 0x45, 0x69, 0x00, 0x30, 0x40, 0xa8, 0x01, 0x00, 0x42, 0x23, 0xbc, 0x9d, 0x00, 0x0a, 0x50, 0x00, 0x42, - 0xa3, 0x10, 0x00, 0x7c, 0x22, 0x00, 0x60, 0x2d, 0xf9, 0x00, 0xe0, 0x6d, 0x69, 0x20, 0xe0, 0x7d, 0x22, 0x40, 0x01, - 0x54, 0x45, 0x00, 0xa0, 0x14, 0xf9, 0x00, 0xe0, 0x55, 0xe9, 0x00, 0x30, 0x40, 0xe3, 0x00, 0x00, 0x68, 0x23, 0x00, - 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x76, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, - 0x94, 0x81, 0x00, 0x98, 0x21, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, 0x22, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, - 0x98, 0x23, 0x00, 0x46, 0xa3, 0xfc, 0x9d, 0x00, 0x98, 0x24, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, 0x3c, 0x00, - 0x44, 0xa3, 0x01, 0x00, 0x42, 0x23, 0x84, 0x9d, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x40, 0x31, 0x7e, 0xc5, 0x00, - 0x00, 0x40, 0x23, 0x00, 0x08, 0x80, 0xf9, 0x00, 0x08, 0x80, 0xe8, 0xdc, 0x9e, 0x00, 0x0a, 0xd8, 0x8c, 0x00, 0x02, - 0xdc, 0x9e, 0x00, 0x0a, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xa4, - 0x24, 0x00, 0x09, 0xa1, 0x67, 0x00, 0x19, 0xa3, 0x67, 0x00, 0x00, 0xfc, 0xf3, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x3f, - 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, 0x70, 0x96, 0x00, 0x02, 0x5c, 0x8e, 0x00, 0x82, 0xd0, 0x8e, 0x00, 0x02, 0x00, - 0x70, 0x6e, 0x63, 0x00, 0x80, 0x70, 0x63, 0x00, 0x90, 0x72, 0x63, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, - 0x00, 0x00, 0x4f, 0xe3, 0x00, 0x20, 0x51, 0x63, 0x00, 0x10, 0x53, 0xe3, 0x0c, 0x8d, 0x00, 0x82, 0x00, 0x00, 0xfc, - 0xf3, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x3f, 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, 0x5c, 0x8e, 0x00, 0x82, 0xd0, 0x8e, - 0x00, 0x02, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x80, 0x04, 0x92, 0xfd, 0x00, - 0x70, 0x57, 0x63, 0x00, 0x80, 0x59, 0xe3, 0x00, 0x90, 0x5b, 0xe3, 0x0c, 0x8d, 0x00, 0x82, 0x00, 0xc0, 0x42, 0x63, - 0x74, 0x84, 0x00, 0x82, 0x80, 0xb0, 0x96, 0xe7, 0x80, 0xd0, 0x9a, 0xe7, 0x01, 0x00, 0x58, 0xa3, 0xd4, 0x8d, 0x00, - 0x82, 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x12, 0x00, 0x40, 0x23, 0x00, 0x00, - 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0xa8, 0xa4, 0x00, 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, - 0x00, 0x48, 0x22, 0x00, 0x40, 0x48, 0xe5, 0xff, 0x00, 0x44, 0xa3, 0x00, 0x41, 0x82, 0xe2, 0x00, 0x40, 0x32, 0xf5, - 0x00, 0x90, 0x09, 0xf5, 0x00, 0x40, 0x08, 0xf5, 0x00, 0x91, 0xb3, 0xe2, 0x00, 0x41, 0x88, 0xe2, 0x00, 0x00, 0x00, - 0x84, 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x33, 0x63, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x01, 0x90, - 0x75, 0x22, 0x04, 0xa4, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x02, 0x40, 0x40, 0xa8, 0x54, 0x9f, 0x00, 0x08, 0x01, - 0x40, 0x40, 0xa8, 0x70, 0x9f, 0x00, 0x08, 0xf4, 0x00, 0x46, 0xa3, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, - 0xcc, 0x99, 0x00, 0x82, 0x00, 0x30, 0x40, 0xa8, 0x68, 0x9f, 0x00, 0x08, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, - 0x98, 0xc3, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xe4, 0x97, 0x00, 0x02, 0x00, 0x30, 0x40, 0xa8, 0x84, 0x9f, - 0x00, 0x88, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xc3, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0x64, - 0x81, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa2, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x44, 0x69, 0x00, 0x30, 0x40, 0xe3, - 0x00, 0xa1, 0x00, 0x98, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x68, 0xe3, 0x00, 0x40, 0x6b, 0x22, 0xf0, 0x9e, 0x00, - 0x02, 0x00, 0x90, 0x35, 0x63, 0x01, 0xa0, 0x75, 0x22, 0xf2, 0x00, 0x46, 0xa3, 0x04, 0xa4, 0xc1, 0xb9, 0x70, 0xa0, - 0x00, 0x9e, 0x04, 0xa4, 0xc5, 0x35, 0x7c, 0xa0, 0x00, 0x1c, 0xf6, 0x00, 0x46, 0x23, 0xff, 0x00, 0x7c, 0x23, 0x00, - 0x20, 0x4a, 0x63, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0x01, 0x40, 0x40, 0xa8, 0xf4, 0x9f, 0x00, 0x08, - 0x02, 0x40, 0x40, 0xa8, 0x70, 0xa0, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0xaa, 0x40, 0x40, - 0x28, 0x70, 0xa0, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0x80, 0x4c, 0x40, 0x68, 0x70, 0xa0, - 0x00, 0x8a, 0xf4, 0x00, 0x46, 0xa3, 0x00, 0xe1, 0xbd, 0xe2, 0x02, 0xe0, 0x41, 0x28, 0x44, 0xa0, 0x00, 0x88, 0x01, - 0xe0, 0x41, 0x28, 0x70, 0xa0, 0x00, 0x8a, 0x50, 0x00, 0x42, 0xa3, 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, 0x00, 0x1c, - 0x06, 0xa4, 0xe3, 0x35, 0x7c, 0xa0, 0x00, 0x1c, 0x50, 0xa0, 0x00, 0x18, 0x30, 0x00, 0x42, 0xa3, 0x05, 0xa4, 0xe1, - 0xb5, 0x7c, 0xa0, 0x00, 0x1c, 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0xff, 0x0f, 0x4a, 0x23, 0x80, 0x22, - 0x84, 0x62, 0x00, 0x20, 0x04, 0xf3, 0xc3, 0x20, 0x84, 0xa4, 0x00, 0x00, 0x40, 0x23, 0x8c, 0xa0, 0x00, 0x98, 0x12, - 0x00, 0x44, 0xa3, 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, 0x00, 0x98, 0x3c, 0x00, 0x44, 0xa3, 0xf2, 0x00, 0x46, 0xa3, - 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, 0x00, 0x98, 0x00, 0x50, 0x45, 0xe9, 0x10, 0x40, 0x6d, 0xa2, 0x00, 0x00, 0x21, - 0xf9, 0x00, 0x60, 0x61, 0xe9, 0x20, 0x60, 0x6d, 0x22, 0x00, 0x10, 0x23, 0xf9, 0x00, 0x60, 0x63, 0x69, 0x00, 0x00, - 0x40, 0x23, 0x00, 0xa1, 0x00, 0x98, 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x33, 0x63, 0x64, 0x81, 0x00, 0x02, 0x00, - 0x00, 0x6a, 0x22, 0x03, 0x94, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, - 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, 0x73, 0x22, 0x03, 0x94, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0x04, 0x94, 0xc1, - 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x05, 0x94, 0xc1, 0x39, 0xc3, 0x00, 0x44, 0xa3, 0x00, 0x50, 0x45, 0xe9, 0x01, 0x00, - 0x42, 0x23, 0x00, 0x00, 0x40, 0x23, 0x00, 0xa1, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x00, - 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x44, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x94, 0x81, 0x00, 0x98, - 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, 0x22, 0x00, 0x40, 0x48, 0xe5, 0x00, 0x40, 0x04, 0xf5, 0xff, 0x00, 0x4c, - 0x23, 0x00, 0x23, 0x84, 0x62, 0x00, 0x20, 0x32, 0x63, 0x01, 0x90, 0xb3, 0x24, 0x04, 0x94, 0xcb, 0xb5, 0x0c, 0xa2, - 0x00, 0x1c, 0xff, 0x00, 0x4c, 0x23, 0x00, 0x53, 0x8e, 0xe2, 0x01, 0x70, 0x40, 0xa8, 0x00, 0xa2, 0x00, 0x8a, 0x00, - 0x50, 0x0a, 0xf5, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x53, 0x8e, 0xe2, 0x00, 0x71, 0x40, 0x68, - 0xf4, 0xa1, 0x00, 0x0a, 0x05, 0x94, 0xcb, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x60, 0x01, 0x4a, 0xc9, 0x06, 0x94, 0xcb, - 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x80, 0x01, 0x4a, 0x49, 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, 0x73, 0x24, 0x00, 0x94, - 0xf5, 0xb5, 0x0c, 0xa2, 0x00, 0x1c, 0x01, 0x94, 0xed, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x02, 0x94, 0xeb, 0x35, 0x0c, - 0xa2, 0x00, 0x1c, 0x03, 0x94, 0xef, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x05, 0x94, 0xc1, 0x39, 0x10, 0x00, 0x48, 0xa2, - 0x00, 0x40, 0x64, 0x65, 0x00, 0x20, 0x25, 0xf9, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, - 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, 0x00, 0x50, 0xab, 0xfb, 0x00, 0x00, 0xd4, 0xf3, 0x00, 0x65, - 0xad, 0x68, 0x00, 0x75, 0xaf, 0x68, 0x80, 0x6b, 0xa9, 0xe8, 0xa0, 0x00, 0x60, 0xc5, 0x00, 0x00, 0x21, 0xf9, 0xc0, - 0x00, 0x62, 0x45, 0x88, 0x9b, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf6, 0x00, 0x46, 0x23, 0x14, 0xa2, 0x00, 0x98, - 0x05, 0x94, 0xc1, 0x39, 0xf4, 0x00, 0x46, 0xa3, 0x14, 0xa2, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf2, 0x00, 0x46, - 0xa3, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x05, 0x94, 0xc1, 0x39, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, - 0x7c, 0xa2, 0x12, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x00, 0x30, 0x40, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, - 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x6e, 0x23, - 0x94, 0x81, 0x00, 0x98, 0x20, 0x00, 0x42, 0x23, 0x94, 0x81, 0x00, 0x98, 0xf2, 0x00, 0x40, 0xa3, 0x50, 0xa2, 0x00, - 0x98, 0x00, 0x00, 0xe6, 0x73, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, - 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0x30, 0xe7, 0x62, 0x40, 0x00, 0x66, 0x49, 0x09, - 0x00, 0x60, 0xa3, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, - 0x50, 0xa2, 0x00, 0x98, 0x40, 0x00, 0x66, 0x45, 0x20, 0x00, 0x60, 0x45, 0x60, 0x00, 0x60, 0xc9, 0x0c, 0x9e, 0x00, - 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x20, 0x00, - 0x42, 0x45, 0x00, 0x12, 0xe0, 0xb5, 0x58, 0xa2, 0x00, 0x9c, 0x40, 0x00, 0x66, 0x45, 0x0c, 0x9e, 0x00, 0x02, 0x00, - 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x60, 0x00, 0x60, 0xc5, - 0x00, 0x00, 0x42, 0xa3, 0x00, 0x10, 0xe6, 0x35, 0x58, 0xa2, 0x00, 0x9c, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, - 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0x30, - 0xe7, 0x62, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x00, - 0x00, 0x66, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x50, 0xa2, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, - 0xd0, 0xa3, 0x00, 0x02, 0xe4, 0xa3, 0x00, 0x82, 0x04, 0xa4, 0x00, 0x82, 0x24, 0xa4, 0x00, 0x02, 0x00, 0x00, 0xc0, - 0x2d, 0x00, 0x00, 0xc0, 0x63, 0x94, 0x81, 0x00, 0x98, 0x1c, 0x00, 0x7c, 0xa3, 0x00, 0x10, 0x23, 0xf9, 0x00, 0x00, - 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, 0xfd, 0x80, 0x08, 0x21, 0x7d, 0x00, 0x10, 0x23, 0xf3, 0x01, - 0xe0, 0x7d, 0x24, 0x5c, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, 0xfd, - 0x00, 0x00, 0x21, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x78, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, 0x00, 0x00, 0x00, - 0x84, 0x54, 0x00, 0x46, 0xa3, 0x00, 0x30, 0x06, 0xf3, 0x53, 0x30, 0x86, 0xa4, 0x00, 0x30, 0x06, 0xf3, 0x01, 0x30, - 0x86, 0x24, 0x00, 0x30, 0x06, 0xf3, 0x80, 0x30, 0x86, 0x24, 0x00, 0x30, 0x06, 0xf5, 0x00, 0x00, 0x00, 0x84, 0x90, - 0xa3, 0x00, 0x82, 0x01, 0x06, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xed, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xc0, 0xeb, - 0x00, 0x10, 0x80, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x08, 0x4c, 0xa3, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x60, 0x7e, - 0x69, 0xd4, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x02, 0x4c, 0xa3, 0x10, 0x00, 0x44, 0x23, 0x00, 0x20, - 0x04, 0xf3, 0x00, 0x61, 0x86, 0xe4, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0xf0, 0xa3, 0x00, 0x0a, 0x00, - 0x00, 0x00, 0x84, 0x80, 0x00, 0x4c, 0xa3, 0x50, 0x00, 0x44, 0xa3, 0x00, 0x20, 0x04, 0xf3, 0x00, 0x61, 0x86, 0xe4, - 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0x10, 0xa4, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x40, - 0x23, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x44, 0xa3, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x48, 0xa3, 0x00, 0x00, - 0x4a, 0x23, 0x00, 0x00, 0x4c, 0x23, 0x00, 0x00, 0x4e, 0xa3, 0x00, 0x00, 0x50, 0xa3, 0x00, 0x00, 0x52, 0x23, 0x00, - 0x00, 0x54, 0x23, 0x00, 0x00, 0x56, 0xa3, 0x00, 0x00, 0x58, 0x23, 0x00, 0x00, 0x5a, 0xa3, 0x00, 0x00, 0x5c, 0xa3, - 0x00, 0x00, 0x5e, 0x23, 0x00, 0x00, 0x60, 0xa3, 0x00, 0x00, 0x62, 0x23, 0x00, 0x00, 0x64, 0x23, 0x00, 0x00, 0x66, - 0xa3, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, 0x00, 0x00, 0x6e, 0x23, 0x00, 0x00, - 0x70, 0x23, 0x00, 0x00, 0x72, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x76, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x00, - 0x00, 0x7a, 0x23, 0x00, 0x00, 0x7c, 0x23, 0x00, 0x00, 0x7e, 0xa3, 0x00, 0x00, 0x00, 0x84}; \ No newline at end of file +const uint8_t fw_SPECT[] = { + 0x6b, 0xc1, 0x97, 0x12, 0x62, 0xd1, 0x74, 0x61, 0x11, 0xc6, 0x82, 0x39, 0x3d, 0xb0, 0x9f, 0xb7, + 0xde, 0xb2, 0x09, 0x47, 0x40, 0x54, 0xca, 0xc2, 0x3c, 0x86, 0x9f, 0x05, 0xdb, 0x0e, 0xd7, 0x70, + 0xe8, 0x6a, 0x1d, 0xd0, 0x6d, 0xa3, 0xf7, 0xea, 0x18, 0x4e, 0xda, 0x94, 0x1c, 0x24, 0xaf, 0x8d, + 0x1b, 0x24, 0x34, 0x9c, 0x18, 0x17, 0x38, 0x15, 0x37, 0xf6, 0xc8, 0x61, 0x81, 0x81, 0x7b, 0x05, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa8, 0x24, 0x00, 0x00, 0xd4, 0x7d, 0x50, 0x04, + 0xb7, 0xcf, 0xe1, 0x1e, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x00, 0x7e, 0xa3, 0xe4, 0xa3, 0x00, 0x82, 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, 0x40, 0xa2, + 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0x82, 0x62, 0xf0, 0x10, 0x88, 0xa2, 0x20, 0x33, 0x4a, 0xc5, + 0x00, 0x10, 0x40, 0x28, 0x2c, 0xa3, 0x00, 0x08, 0x60, 0x40, 0x40, 0x28, 0x4c, 0x80, 0x00, 0x88, + 0x10, 0x40, 0x40, 0xa8, 0x84, 0x80, 0x00, 0x08, 0x40, 0x40, 0x40, 0xa8, 0xb8, 0x80, 0x00, 0x08, + 0x70, 0x40, 0x40, 0xa8, 0x20, 0x81, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0x04, 0xa4, 0x00, 0x82, + 0xf4, 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x60, 0x10, 0x40, 0x28, + 0x1c, 0x9f, 0x00, 0x08, 0x61, 0x10, 0x40, 0xa8, 0x1c, 0x9f, 0x00, 0x08, 0x62, 0x10, 0x40, 0xa8, + 0xa4, 0x9f, 0x00, 0x08, 0x63, 0x10, 0x40, 0x28, 0xb0, 0xa0, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, + 0xa8, 0xa4, 0x00, 0x18, 0xf3, 0x50, 0x8a, 0xa4, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, + 0x11, 0x10, 0x40, 0x28, 0x60, 0xa2, 0x00, 0x08, 0x12, 0x10, 0x40, 0x28, 0x9c, 0xa2, 0x00, 0x08, + 0x13, 0x10, 0x40, 0xa8, 0xbc, 0xa2, 0x00, 0x88, 0x14, 0x10, 0x40, 0x28, 0xe0, 0xa2, 0x00, 0x88, + 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x04, 0xa4, 0x00, 0x82, 0xf2, 0x50, 0x8a, 0x24, + 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x41, 0x10, 0x40, 0x28, 0x94, 0x8f, 0x00, 0x88, + 0x42, 0x10, 0x40, 0x28, 0xac, 0x90, 0x00, 0x88, 0x43, 0x10, 0x40, 0xa8, 0xd4, 0x90, 0x00, 0x88, + 0x44, 0x10, 0x40, 0x28, 0x04, 0x91, 0x00, 0x88, 0x45, 0x10, 0x40, 0xa8, 0xfc, 0x91, 0x00, 0x08, + 0x46, 0x10, 0x40, 0xa8, 0xa0, 0x92, 0x00, 0x08, 0x47, 0x10, 0x40, 0x28, 0xf4, 0x92, 0x00, 0x88, + 0x48, 0x10, 0x40, 0x28, 0x30, 0x93, 0x00, 0x88, 0x49, 0x10, 0x40, 0xa8, 0x48, 0x93, 0x00, 0x88, + 0x4a, 0x10, 0x40, 0xa8, 0x18, 0x94, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, + 0x04, 0xa4, 0x00, 0x82, 0xf1, 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, + 0x70, 0x10, 0x40, 0xa8, 0x1c, 0xa1, 0x00, 0x88, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, + 0x02, 0x00, 0x44, 0x23, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x44, 0x69, 0x00, 0x00, 0x42, 0xa3, + 0xf3, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x40, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xf3, + 0x00, 0x00, 0x00, 0x84, 0x50, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, 0x00, 0xf5, 0x00, 0x00, 0x00, 0xf5, 0xff, 0x00, 0x42, 0xa3, + 0x00, 0x10, 0x02, 0xf3, 0xff, 0x10, 0x82, 0xa4, 0x80, 0x00, 0x80, 0xe2, 0x00, 0x00, 0x00, 0x84, + 0xa8, 0xa4, 0x00, 0x18, 0x00, 0x10, 0x02, 0xf3, 0x00, 0x10, 0x02, 0xf3, 0x80, 0x00, 0x40, 0xe2, + 0x00, 0x11, 0x40, 0x49, 0x00, 0x00, 0xc0, 0x93, 0x80, 0x10, 0x84, 0xff, 0x80, 0x20, 0x86, 0x7f, + 0x80, 0x31, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x80, 0x41, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, + 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x80, 0x42, 0x8a, 0xff, + 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x06, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, + 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0xdc, 0x81, 0x00, 0x8a, + 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x0f, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, + 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0xfc, 0x81, 0x00, 0x0a, + 0x80, 0x42, 0x8c, 0xff, 0x00, 0x63, 0x88, 0xff, 0x3f, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, + 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0x1c, 0x82, 0x00, 0x8a, + 0x00, 0x43, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x1e, 0x00, 0x7c, 0x23, + 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, + 0x40, 0x82, 0x00, 0x8a, 0x00, 0x43, 0x88, 0x7f, 0x40, 0x30, 0x4a, 0xc5, 0x80, 0x00, 0x7c, 0xa3, + 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x50, 0x0a, 0x63, 0x80, 0x82, 0x00, 0x8c, + 0x00, 0x50, 0x0a, 0x63, 0x94, 0x82, 0x00, 0x0e, 0x80, 0x40, 0x88, 0xff, 0x94, 0x82, 0x00, 0x98, + 0x00, 0x50, 0x0a, 0x63, 0x90, 0x82, 0x00, 0x0c, 0x00, 0x41, 0x88, 0xff, 0x94, 0x82, 0x00, 0x98, + 0x80, 0x41, 0x88, 0x7f, 0x02, 0xe0, 0x7d, 0x24, 0x60, 0x82, 0x00, 0x0a, 0x00, 0x40, 0x42, 0xe3, + 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x86, 0xef, 0x80, 0x30, 0x88, 0xef, 0x00, 0x42, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x31, 0x86, 0x6f, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x8a, 0x6f, 0x80, 0x52, 0x86, 0xef, 0x09, 0x00, 0x7c, 0x23, + 0x80, 0x31, 0x86, 0xef, 0x01, 0xe0, 0x7d, 0x24, 0xe0, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x86, 0xef, + 0x0a, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x02, 0xe0, 0x7d, 0x24, + 0xf4, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x8a, 0xef, 0x80, 0x52, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, + 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x1e, 0x00, 0x7c, 0x23, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, + 0x20, 0x83, 0x00, 0x0a, 0x80, 0x30, 0x86, 0x6f, 0x80, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x04, 0xe0, 0x7d, 0x24, + 0x3c, 0x83, 0x00, 0x8a, 0x00, 0x31, 0x86, 0x6f, 0x20, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x04, 0xe0, 0x7d, 0x24, + 0x5c, 0x83, 0x00, 0x8a, 0x00, 0x31, 0x86, 0x6f, 0x1e, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, 0x7c, 0x83, 0x00, 0x0a, + 0x80, 0x32, 0x86, 0xef, 0x00, 0x00, 0x00, 0x84, 0xa4, 0x82, 0x00, 0x02, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x30, 0x82, 0xef, 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x84, 0xe7, + 0x80, 0x20, 0x88, 0xe7, 0x00, 0x42, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x41, 0x84, 0x67, + 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, + 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x07, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0x67, + 0x01, 0xe0, 0x7d, 0x24, 0xdc, 0x83, 0x00, 0x0a, 0x80, 0x21, 0x8a, 0xe7, 0x80, 0x52, 0x86, 0x67, + 0x0f, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xf4, 0x83, 0x00, 0x0a, + 0x80, 0x51, 0x84, 0xe7, 0x00, 0x21, 0x86, 0x67, 0x0f, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, + 0x01, 0xe0, 0x7d, 0x24, 0x0c, 0x84, 0x00, 0x0a, 0x80, 0x51, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, + 0x00, 0x21, 0x84, 0xe7, 0x00, 0x22, 0x8a, 0x67, 0x80, 0x52, 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, + 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x30, 0x84, 0x00, 0x0a, 0x80, 0x51, 0x84, 0xe7, + 0x00, 0x21, 0x86, 0x67, 0x63, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, + 0x48, 0x84, 0x00, 0x0a, 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, + 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x60, 0x84, 0x00, 0x0a, 0x80, 0x32, 0x84, 0xe7, + 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, + 0x80, 0x30, 0x86, 0xe7, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, + 0x00, 0x32, 0x82, 0x67, 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0x80, 0x67, + 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, + 0x00, 0x00, 0x80, 0x67, 0x00, 0x21, 0x84, 0xe7, 0x80, 0x20, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, + 0x00, 0x32, 0x48, 0x45, 0x00, 0x22, 0x86, 0x67, 0x00, 0x21, 0x88, 0xe7, 0x80, 0x40, 0x88, 0xe8, + 0xdc, 0x84, 0x00, 0x8a, 0x00, 0x20, 0x42, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x30, 0x42, 0x63, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x90, 0x42, 0x63, 0x74, 0x84, 0x00, 0x82, 0x80, 0x70, 0x8e, 0xe7, + 0x80, 0x80, 0x90, 0xe7, 0x01, 0x00, 0x42, 0x23, 0x80, 0x70, 0x8e, 0xe2, 0x00, 0x80, 0x10, 0xeb, + 0x80, 0x83, 0x90, 0xe4, 0x00, 0x80, 0x10, 0xed, 0x00, 0x80, 0x10, 0xf9, 0x00, 0x00, 0x00, 0x84, + 0x00, 0xc0, 0x60, 0x63, 0x00, 0x00, 0x21, 0x63, 0x24, 0x85, 0x00, 0x8c, 0x00, 0x00, 0x6c, 0xa3, + 0x2c, 0x85, 0x00, 0x18, 0x01, 0x00, 0x6c, 0x23, 0x2c, 0x85, 0x00, 0x18, 0x00, 0x00, 0x21, 0x65, + 0x00, 0x00, 0x59, 0x63, 0x00, 0x08, 0xa1, 0xe7, 0x01, 0x00, 0x42, 0x23, 0x80, 0x00, 0xa9, 0xfd, + 0x00, 0x03, 0xa1, 0x67, 0x80, 0x00, 0xab, 0x7b, 0x80, 0x5a, 0xa5, 0x67, 0x80, 0x2a, 0xa5, 0xe7, + 0x00, 0x2a, 0xa7, 0xe7, 0x00, 0x29, 0xa5, 0x67, 0x80, 0x2a, 0xa5, 0xe7, 0x00, 0x2a, 0x83, 0xe7, + 0x00, 0x10, 0x60, 0xe3, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0xa4, 0x67, 0x00, 0x29, 0xa5, 0x67, + 0x00, 0x28, 0xa5, 0xe7, 0x80, 0x29, 0xa5, 0xe7, 0x00, 0x29, 0xa1, 0xe7, 0x80, 0x0a, 0xa1, 0xe7, + 0x00, 0x32, 0x42, 0x45, 0x80, 0x20, 0xa3, 0xe7, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x0a, 0xbd, 0xe8, + 0x9c, 0x85, 0x00, 0x8a, 0x00, 0x20, 0x41, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x7c, 0x23, + 0x00, 0xea, 0xa9, 0xfd, 0x00, 0x0a, 0xbd, 0xe8, 0xb4, 0x85, 0x00, 0x8a, 0x00, 0x10, 0x41, 0xe3, + 0x01, 0x00, 0x42, 0x23, 0x00, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, 0x88, 0x00, 0x00, 0x42, 0xa3, + 0x00, 0xe0, 0xbd, 0x68, 0xcc, 0x85, 0x00, 0x8a, 0x01, 0x10, 0x82, 0x24, 0x01, 0x60, 0x41, 0xa8, + 0xd8, 0x85, 0x00, 0x8a, 0x02, 0x10, 0x82, 0x24, 0x03, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, 0x88, + 0x00, 0x00, 0x46, 0x23, 0x00, 0x30, 0x86, 0xfd, 0x01, 0x00, 0x7c, 0xa3, 0x00, 0x0f, 0x82, 0xe2, + 0x00, 0x1b, 0x40, 0x68, 0x00, 0x86, 0x00, 0x8a, 0x00, 0x00, 0x56, 0x63, 0x08, 0x86, 0x00, 0x18, + 0x00, 0x30, 0x56, 0x63, 0x08, 0x86, 0x00, 0x18, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x00, 0x84, + 0xff, 0x0f, 0x42, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x80, 0x83, 0x80, 0xfd, 0x80, 0xc5, 0x82, 0xfd, + 0x80, 0x00, 0x80, 0xe7, 0x80, 0x83, 0x82, 0x7b, 0x80, 0xc5, 0x84, 0xfb, 0x00, 0x11, 0x82, 0xe7, + 0x00, 0xa7, 0x84, 0x67, 0x00, 0x23, 0x84, 0x67, 0x00, 0x21, 0x84, 0x7b, 0x80, 0x96, 0x86, 0xe7, + 0x80, 0x31, 0x86, 0xfb, 0x00, 0x10, 0x88, 0xfd, 0x00, 0x10, 0x80, 0x7b, 0x00, 0x31, 0x82, 0xfd, + 0x00, 0x31, 0x84, 0xfb, 0x80, 0x40, 0x96, 0xe7, 0x00, 0x40, 0x9c, 0x67, 0x00, 0x20, 0x98, 0xe7, + 0x80, 0x20, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x80, 0x73, 0x80, 0x67, 0x00, 0x84, 0x82, 0xe7, + 0x80, 0x94, 0x84, 0xe7, 0x00, 0x21, 0x84, 0x7b, 0x80, 0x00, 0x86, 0x7b, 0x00, 0x74, 0x88, 0x7b, + 0x00, 0x42, 0x88, 0xe7, 0x00, 0x32, 0x88, 0xfd, 0x80, 0x00, 0x80, 0x7d, 0x00, 0x20, 0x82, 0xfb, + 0x80, 0x40, 0x8e, 0xe7, 0x80, 0x00, 0x92, 0xe7, 0x80, 0x01, 0x90, 0xe7, 0x80, 0x41, 0x94, 0xe7, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x4e, 0xa3, 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, 0xa3, + 0x00, 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xb0, 0x4e, 0x67, + 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, + 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, + 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0xb8, 0x86, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x05, 0x56, 0xc9, 0x20, 0x05, 0x58, 0xc9, 0x40, 0x05, 0x5a, 0x49, 0x00, 0x00, 0x4e, 0xa3, + 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, 0xa3, + 0x00, 0x00, 0xde, 0xf3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, 0x00, 0xb0, 0x4e, 0x67, + 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, + 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, + 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x14, 0x87, 0x00, 0x0a, 0x00, 0x01, 0x7c, 0xa3, + 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, + 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, + 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, + 0x01, 0xe0, 0x7d, 0x24, 0x50, 0x87, 0x00, 0x0a, 0x00, 0x00, 0x7c, 0x23, 0x80, 0xe3, 0x8f, 0xfd, + 0x00, 0xe5, 0x95, 0xfd, 0x18, 0x86, 0x00, 0x02, 0x80, 0xe3, 0x8f, 0xfd, 0x00, 0xe5, 0x95, 0xfd, + 0x00, 0x05, 0x40, 0x45, 0x20, 0x05, 0x42, 0x45, 0x40, 0x05, 0x44, 0x45, 0x80, 0x06, 0x80, 0xe7, + 0x80, 0x16, 0x82, 0xe7, 0x00, 0xb1, 0x96, 0xe7, 0x00, 0xc1, 0x98, 0xe7, 0x80, 0x05, 0xbc, 0xe8, + 0xd4, 0x87, 0x00, 0x0a, 0x00, 0x16, 0xbc, 0xe8, 0xd4, 0x87, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, + 0x00, 0x00, 0x00, 0x84, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x40, 0x31, 0x7e, 0xc5, + 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xae, 0x24, + 0x80, 0x5b, 0xab, 0x67, 0x00, 0x5b, 0xb1, 0x67, 0x80, 0x6b, 0xad, 0x67, 0x98, 0x96, 0x00, 0x02, + 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, + 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0x02, 0x56, 0x49, 0x20, 0x02, 0x58, 0x49, 0x40, 0x02, 0x5a, 0xc9, + 0x60, 0x02, 0x5c, 0x49, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x08, 0x89, 0x00, 0x0a, + 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0x02, 0x56, 0x45, 0x20, 0x02, 0x58, 0x45, + 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, 0x45, 0x00, 0x02, 0x4e, 0x49, 0x20, 0x02, 0x50, 0xc9, + 0x40, 0x02, 0x52, 0x49, 0x60, 0x02, 0x54, 0xc9, 0x00, 0x50, 0x4f, 0xe3, 0x00, 0x60, 0x51, 0xe3, + 0x00, 0x70, 0x53, 0xe3, 0x00, 0x80, 0x55, 0xe3, 0x00, 0x00, 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, + 0x00, 0x07, 0x9c, 0xfd, 0x18, 0x86, 0x00, 0x02, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xfc, 0xf3, + 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, 0xf0, 0x86, 0x00, 0x02, + 0x00, 0x00, 0x40, 0xa8, 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, + 0x00, 0x02, 0x56, 0x45, 0x20, 0x02, 0x58, 0x45, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, 0x45, + 0x18, 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, + 0x00, 0xe0, 0x54, 0x63, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, + 0x74, 0x84, 0x00, 0x82, 0x80, 0xb0, 0xaa, 0xe7, 0x80, 0xc0, 0xac, 0x67, 0x80, 0x5a, 0x83, 0xe7, + 0x00, 0x6b, 0x85, 0xe7, 0x80, 0x20, 0x86, 0xfd, 0x00, 0x11, 0x88, 0xe7, 0x00, 0x43, 0x88, 0x67, + 0x01, 0x00, 0x40, 0xa3, 0x00, 0x40, 0x88, 0xfb, 0x00, 0x32, 0x80, 0xe8, 0x08, 0x89, 0x00, 0x0a, + 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, + 0x80, 0x73, 0x80, 0x67, 0x00, 0x84, 0x82, 0xe7, 0x80, 0x94, 0x84, 0xe7, 0x00, 0x10, 0x86, 0x7d, + 0x00, 0x31, 0x86, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x03, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, + 0x00, 0x01, 0x80, 0x7b, 0x00, 0x30, 0x86, 0x68, 0x48, 0x89, 0x00, 0x8a, 0x00, 0x74, 0x80, 0x67, + 0x00, 0x95, 0x86, 0x67, 0x00, 0x30, 0x86, 0x68, 0x00, 0x00, 0x00, 0x84, 0x00, 0x96, 0x80, 0xef, + 0x80, 0xa6, 0x82, 0xef, 0x00, 0xb7, 0x84, 0x6f, 0x00, 0x95, 0x86, 0xfb, 0x80, 0xc6, 0x88, 0xfb, + 0x00, 0x32, 0x86, 0x6f, 0x80, 0x00, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x7d, 0x80, 0xa5, 0x88, 0xfb, + 0x00, 0xd7, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xef, 0x00, 0x11, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xfd, + 0x80, 0x95, 0x8a, 0x7b, 0x00, 0xc7, 0x8c, 0x7b, 0x00, 0x53, 0x8a, 0xef, 0x00, 0x01, 0x8c, 0x7b, + 0x00, 0x53, 0x8c, 0xfd, 0x00, 0x81, 0x8e, 0x6f, 0x80, 0x63, 0x8a, 0x7d, 0x80, 0x52, 0x8e, 0x7b, + 0x80, 0x53, 0x8a, 0x7b, 0x80, 0x12, 0x8e, 0xfd, 0x80, 0x12, 0x8a, 0x7b, 0x00, 0x83, 0x8c, 0x6f, + 0x00, 0x21, 0x82, 0x7b, 0x00, 0x11, 0x84, 0x7b, 0x00, 0x61, 0x8c, 0x7d, 0x00, 0x60, 0x8c, 0xfd, + 0x00, 0x63, 0x82, 0x7b, 0x00, 0x13, 0x8c, 0x7b, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x80, 0x7b, + 0x00, 0x01, 0x80, 0x7d, 0x00, 0x43, 0x82, 0xef, 0x00, 0x03, 0x84, 0x6f, 0x80, 0x53, 0x8c, 0x6f, + 0x00, 0x61, 0x9a, 0xfb, 0x80, 0x32, 0x8a, 0xef, 0x80, 0x50, 0x98, 0x7d, 0x80, 0x43, 0x8e, 0x6f, + 0x00, 0x30, 0x82, 0x6f, 0x80, 0x70, 0x9c, 0x7b, 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0xef, + 0x00, 0xa5, 0x82, 0x6f, 0x80, 0xb5, 0x84, 0x6f, 0x00, 0x95, 0x86, 0xef, 0x80, 0x31, 0x86, 0xfb, + 0x80, 0x95, 0x8e, 0xef, 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x81, 0x8c, 0xef, 0x80, 0x63, 0x8c, 0x7d, + 0x00, 0x63, 0x8a, 0xfb, 0x00, 0x53, 0x8c, 0xfb, 0x00, 0x13, 0x8a, 0x7d, 0x00, 0x13, 0x8c, 0x7b, + 0x00, 0x53, 0x8c, 0xef, 0x80, 0x51, 0x8a, 0xef, 0x00, 0x21, 0x86, 0xfb, 0x80, 0x21, 0x84, 0xfb, + 0x80, 0x83, 0x8e, 0x6f, 0x00, 0x71, 0x8e, 0x7d, 0x00, 0x70, 0x8e, 0xfd, 0x80, 0x73, 0x86, 0xfb, + 0x80, 0x71, 0x8e, 0xfb, 0x00, 0x00, 0x86, 0xfb, 0x00, 0x30, 0x80, 0xfb, 0x00, 0x01, 0x80, 0x7d, + 0x80, 0x03, 0x80, 0x6f, 0x00, 0x60, 0x8c, 0xfb, 0x80, 0xa5, 0x80, 0x6f, 0x00, 0x00, 0x80, 0xfb, + 0x80, 0x03, 0x8e, 0xef, 0x80, 0x53, 0x8a, 0x7d, 0x80, 0x00, 0x8e, 0xef, 0x80, 0x73, 0x8e, 0x7b, + 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x50, 0x52, 0xe3, 0x00, 0x60, 0x54, 0xe3, 0x00, 0x70, 0x56, 0xe3, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, 0x00, 0x56, 0xa3, + 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, 0x67, + 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, + 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, + 0xa8, 0x8a, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x58, 0x49, 0x20, 0x05, 0x5a, 0x49, + 0x40, 0x05, 0x5c, 0x49, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, 0x00, 0x56, 0xa3, + 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xde, 0xf3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, + 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, + 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, + 0x01, 0xe0, 0x7d, 0x24, 0xf8, 0x8a, 0x00, 0x0a, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xf0, 0x1e, 0xeb, + 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, + 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, + 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x2c, 0x8b, 0x00, 0x8a, 0x00, 0x00, 0x7c, 0x23, + 0x00, 0xe5, 0x95, 0xfd, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe5, 0x95, 0xfd, 0x00, 0x05, 0x40, 0x45, + 0x20, 0x05, 0x42, 0x45, 0x40, 0x05, 0x44, 0x45, 0x00, 0x07, 0x80, 0x6f, 0x00, 0x17, 0x82, 0x6f, + 0x00, 0xc1, 0x98, 0x6f, 0x00, 0xd1, 0x9a, 0x6f, 0x00, 0x06, 0xbc, 0x68, 0xa0, 0x8b, 0x00, 0x0a, + 0x80, 0x16, 0xbc, 0x68, 0xa0, 0x8b, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, + 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x30, 0x7e, 0xc5, 0x00, 0x00, 0xc4, 0x73, + 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xb0, 0x24, 0x00, 0x6c, 0xad, 0xef, + 0x00, 0x7c, 0xaf, 0xef, 0xc8, 0x97, 0x00, 0x82, 0x00, 0x10, 0x53, 0xe3, 0x00, 0x20, 0x55, 0xe3, + 0x00, 0x30, 0x57, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x20, 0x30, 0x7e, 0x45, + 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0x80, 0x30, 0x50, 0x45, + 0x00, 0x10, 0x59, 0xe3, 0x00, 0x20, 0x5b, 0x63, 0x00, 0x30, 0x5d, 0xe3, 0xd8, 0x8a, 0x00, 0x02, + 0x00, 0x00, 0x40, 0xa8, 0x94, 0x8c, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, + 0x00, 0x00, 0x80, 0x68, 0x00, 0x60, 0x53, 0x6f, 0x00, 0x70, 0x55, 0xef, 0x00, 0x80, 0x57, 0x6f, + 0x00, 0x10, 0x59, 0xe3, 0x00, 0x20, 0x5b, 0x63, 0x00, 0x30, 0x5d, 0xe3, 0x80, 0x06, 0x9a, 0xfd, + 0x4c, 0x89, 0x00, 0x82, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, + 0x00, 0x30, 0x7e, 0xc5, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x94, 0x8c, 0x00, 0x0a, + 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0x60, 0x59, 0x63, 0x00, 0x70, 0x5b, 0x63, + 0x00, 0x80, 0x5d, 0x63, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xc0, 0x52, 0xe3, 0x00, 0xd0, 0x54, 0x63, + 0x00, 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0xe0, 0x42, 0xe3, + 0x98, 0x83, 0x00, 0x82, 0x80, 0xc0, 0xac, 0xef, 0x80, 0xd0, 0xae, 0xef, 0x00, 0x00, 0x40, 0x23, + 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x30, 0x40, 0x45, + 0x80, 0x30, 0x42, 0x45, 0x00, 0xa5, 0x86, 0xef, 0x80, 0x35, 0x86, 0x6f, 0x80, 0x94, 0x84, 0x6f, + 0x80, 0x24, 0x84, 0xef, 0x80, 0xb5, 0x88, 0x6f, 0x80, 0x45, 0x8a, 0xef, 0x80, 0x04, 0x80, 0xef, + 0x00, 0x02, 0x80, 0x6f, 0x80, 0x12, 0x82, 0xef, 0x80, 0x00, 0x80, 0x7b, 0x00, 0x01, 0x80, 0x7b, + 0x80, 0x01, 0x80, 0x68, 0x00, 0x00, 0x00, 0x84, 0x60, 0x32, 0x40, 0xc5, 0x00, 0x08, 0x80, 0xe7, + 0x00, 0x08, 0x83, 0xe7, 0x00, 0x10, 0x82, 0xfb, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x10, 0x82, 0xfb, + 0x00, 0x18, 0x82, 0xe7, 0x98, 0x84, 0x00, 0x02, 0x00, 0x10, 0x62, 0x63, 0x01, 0x00, 0x44, 0x23, + 0x00, 0x20, 0x84, 0x70, 0x00, 0x01, 0x84, 0x62, 0x00, 0x00, 0x00, 0x84, 0xc0, 0x32, 0x68, 0xc5, + 0xe0, 0x32, 0x6a, 0xc5, 0xa0, 0x32, 0x6c, 0x45, 0x00, 0x64, 0x8b, 0x67, 0x80, 0x53, 0x8a, 0x7b, + 0x00, 0x66, 0x8d, 0xe7, 0x80, 0x65, 0x8c, 0x7b, 0x00, 0x53, 0x80, 0x67, 0x80, 0x96, 0x82, 0x67, + 0x00, 0x86, 0x84, 0x67, 0x80, 0x54, 0x86, 0xfb, 0x80, 0x66, 0x88, 0xfb, 0x00, 0x32, 0x86, 0xe7, + 0x80, 0x00, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x7d, 0x00, 0x54, 0x88, 0xfb, 0x00, 0x66, 0x8a, 0xfb, + 0x80, 0x42, 0x88, 0x67, 0x00, 0x01, 0x8a, 0x7b, 0x80, 0x42, 0x88, 0xfd, 0x00, 0x94, 0x8a, 0x7b, + 0x00, 0xd6, 0x96, 0xfb, 0x80, 0x55, 0x8a, 0xe7, 0x00, 0x11, 0x96, 0x7b, 0x80, 0x55, 0x8a, 0x7d, + 0x00, 0x42, 0x99, 0xe7, 0x00, 0x51, 0x97, 0xe7, 0x00, 0xb6, 0x98, 0x7b, 0x00, 0x16, 0x96, 0xfd, + 0x00, 0x16, 0x98, 0x7b, 0x00, 0xb6, 0x9a, 0x67, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x82, 0xfb, + 0x00, 0x41, 0x85, 0x67, 0x00, 0x52, 0x89, 0xe7, 0x00, 0x11, 0x82, 0x7b, 0x00, 0x01, 0x84, 0xfd, + 0x00, 0x41, 0x85, 0x67, 0x00, 0x41, 0x88, 0x7b, 0x00, 0x12, 0x80, 0x67, 0x00, 0xd0, 0x9a, 0xfb, + 0x00, 0x52, 0x80, 0xe7, 0x80, 0x35, 0x96, 0x67, 0x00, 0xb0, 0x96, 0xfd, 0x80, 0x30, 0x80, 0xe7, + 0x00, 0x56, 0x98, 0x67, 0x00, 0xc0, 0x98, 0xfb, 0x00, 0x66, 0xad, 0x67, 0x00, 0xbb, 0x96, 0x7d, + 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0x67, 0x00, 0x04, 0x80, 0xe7, 0x60, 0x32, 0x42, 0x45, + 0x80, 0x13, 0x82, 0xe7, 0x00, 0x14, 0x82, 0x7b, 0x00, 0x14, 0x82, 0xe7, 0x80, 0x73, 0x84, 0xe7, + 0x00, 0x11, 0x82, 0x7b, 0x80, 0x13, 0x82, 0xe7, 0x80, 0x00, 0x80, 0xe8, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x74, 0x80, 0xfb, 0x00, 0x95, 0x82, 0x7d, 0x00, 0x10, 0x82, 0x67, 0x00, 0x74, 0x80, 0xfd, + 0x00, 0x95, 0x84, 0x7b, 0x00, 0x20, 0x84, 0x67, 0x00, 0x11, 0x86, 0xfb, 0x80, 0x31, 0x86, 0x67, + 0x00, 0x11, 0x88, 0x7d, 0x00, 0x42, 0x88, 0xe7, 0x00, 0x36, 0x92, 0x67, 0x00, 0xb2, 0x94, 0x67, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x74, 0x82, 0x7b, 0x80, 0x10, 0x82, 0xe7, 0x00, 0x74, 0x84, 0x7d, + 0x00, 0x21, 0x84, 0xe7, 0x00, 0x11, 0x8e, 0xe7, 0x00, 0x11, 0x82, 0x7d, 0x80, 0x60, 0x86, 0xe7, + 0x00, 0x31, 0x86, 0x7b, 0x80, 0x11, 0x90, 0x67, 0x00, 0x00, 0x00, 0x84, 0x80, 0x32, 0x4c, 0x45, + 0x00, 0xb0, 0x52, 0x63, 0x00, 0xc0, 0x54, 0xe3, 0x01, 0x00, 0x4e, 0x23, 0x00, 0x00, 0x50, 0xa3, + 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xf6, 0xf3, 0x00, 0xb0, 0x37, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, + 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, 0x00, 0x02, + 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x78, 0x8e, 0x00, 0x0a, + 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xb0, 0x37, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0x90, 0x4e, 0xe7, + 0x00, 0xa0, 0x50, 0xe7, 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, 0x00, 0x02, 0x00, 0x90, 0x4e, 0xe7, + 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0xa4, 0x8e, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x76, 0x80, 0xe7, 0x00, 0xb4, 0x82, 0xe7, 0x00, 0x86, 0x84, 0x67, 0x60, 0x32, 0x4c, 0xc5, + 0x00, 0x63, 0x86, 0xfb, 0x00, 0x31, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, 0x80, 0x41, 0x88, 0xfb, + 0x80, 0xb3, 0x8a, 0x67, 0x00, 0x51, 0x8a, 0x7b, 0x80, 0x42, 0x88, 0x67, 0x00, 0x31, 0x86, 0xe7, + 0x80, 0x41, 0x88, 0xfd, 0x00, 0x45, 0x88, 0x67, 0x80, 0x00, 0x82, 0xfd, 0x80, 0x10, 0x82, 0xe7, + 0x80, 0x14, 0x82, 0x67, 0x80, 0x40, 0x92, 0xfd, 0x80, 0xd6, 0x86, 0xfb, 0x00, 0x34, 0x86, 0xe7, + 0x00, 0x35, 0x86, 0x67, 0x00, 0x30, 0x8e, 0xe7, 0x00, 0x31, 0x90, 0x67, 0x00, 0x00, 0x00, 0x84, + 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0x00, 0x42, 0xa3, 0x00, 0xe0, 0x45, 0x65, + 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x47, 0xe5, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x49, 0x65, + 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4b, 0xe5, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4d, 0xe5, + 0x00, 0x20, 0x04, 0xf9, 0x00, 0x30, 0x06, 0xf9, 0x00, 0x40, 0x08, 0xf9, 0x00, 0x50, 0x0a, 0xf9, + 0x00, 0x60, 0x0c, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x11, 0x02, 0xfd, 0x80, 0x21, 0x04, 0x7d, + 0x00, 0x32, 0x06, 0xfd, 0x80, 0x42, 0x08, 0x7d, 0x00, 0x53, 0x0a, 0x7d, 0x00, 0x60, 0x0c, 0xf3, + 0x00, 0x00, 0x00, 0x84, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, 0x22, 0x00, 0x40, 0x44, 0xe5, + 0x00, 0x20, 0x04, 0xf5, 0x00, 0x20, 0x2c, 0x63, 0x01, 0x60, 0x6b, 0x22, 0x00, 0x00, 0x42, 0xa3, + 0x04, 0x54, 0xe1, 0x35, 0x88, 0x90, 0x00, 0x9c, 0xff, 0x00, 0x40, 0x23, 0x00, 0x00, 0xa3, 0xe2, + 0x02, 0x10, 0x41, 0x28, 0x94, 0x90, 0x00, 0x8a, 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0x21, 0xf5, + 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0xa3, 0xe2, 0x00, 0x20, 0x84, 0x62, 0x00, 0x11, 0x41, 0xe8, + 0xa0, 0x90, 0x00, 0x0a, 0x05, 0x54, 0xf3, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x00, 0x03, 0x72, 0xc9, + 0x05, 0x54, 0xc1, 0x39, 0x88, 0x90, 0x00, 0x9c, 0x00, 0x60, 0x6b, 0xe3, 0x00, 0x54, 0xf5, 0xb5, + 0x88, 0x90, 0x00, 0x9c, 0x01, 0x54, 0xef, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x02, 0x54, 0xfb, 0xb5, + 0x88, 0x90, 0x00, 0x9c, 0x03, 0x54, 0xfd, 0x35, 0x88, 0x90, 0x00, 0x9c, 0x05, 0x54, 0xc1, 0x39, + 0x88, 0x90, 0x00, 0x9c, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, + 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, 0x00, 0xd0, 0xbb, 0xfb, 0x00, 0x00, 0xc4, 0x73, + 0x00, 0x71, 0xaf, 0xe8, 0x00, 0xe1, 0xbd, 0xe8, 0x00, 0x7f, 0xa9, 0x68, 0xe0, 0x03, 0x74, 0x49, + 0x00, 0x04, 0x7a, 0xc9, 0xa0, 0x00, 0x60, 0xc5, 0x00, 0x00, 0x21, 0xf9, 0xc0, 0x00, 0x62, 0x45, + 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x05, 0x54, 0xc1, 0x39, + 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x12, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, + 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x00, 0x84, 0x6c, 0x90, 0x00, 0x82, 0xf2, 0x00, 0x40, 0xa3, + 0x94, 0x81, 0x00, 0x98, 0x6c, 0x90, 0x00, 0x82, 0xf4, 0x00, 0x40, 0xa3, 0x94, 0x81, 0x00, 0x98, + 0x6c, 0x90, 0x00, 0x82, 0xf6, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x00, 0x00, 0xce, 0x73, + 0x00, 0x00, 0xd0, 0x73, 0x00, 0x00, 0xd2, 0xf3, 0x00, 0x00, 0xd4, 0xf3, 0x00, 0x70, 0xc0, 0xe3, + 0x0c, 0x40, 0xc1, 0xa5, 0x4c, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x40, 0x23, + 0x94, 0x81, 0x00, 0x98, 0x30, 0x8f, 0x00, 0x02, 0x08, 0x00, 0x56, 0x23, 0x12, 0x00, 0x58, 0x23, + 0x78, 0x8f, 0x00, 0x02, 0x01, 0xc0, 0x58, 0x24, 0xe0, 0x90, 0x00, 0x8a, 0x00, 0x10, 0xc0, 0xe9, + 0x01, 0xb0, 0x56, 0x24, 0xdc, 0x90, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, + 0x94, 0x81, 0x00, 0x98, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, 0x30, 0x8f, 0x00, 0x02, + 0x80, 0x00, 0x5e, 0xa3, 0x00, 0xf0, 0x1e, 0xf3, 0x00, 0xf0, 0x1e, 0xf3, 0x00, 0xf0, 0x1e, 0xf3, + 0x12, 0xb0, 0x56, 0xa4, 0x80, 0xb7, 0xa0, 0x62, 0x44, 0x91, 0x00, 0x8a, 0x12, 0x00, 0x58, 0x23, + 0x78, 0x8f, 0x00, 0x02, 0x01, 0xc0, 0x58, 0x24, 0x30, 0x91, 0x00, 0x8a, 0x00, 0x10, 0xc0, 0xe9, + 0x20, 0x91, 0x00, 0x18, 0x12, 0xb0, 0x56, 0xa2, 0x88, 0x91, 0x00, 0x08, 0x12, 0x00, 0x58, 0x23, + 0x80, 0xc5, 0x58, 0xe4, 0x78, 0x8f, 0x00, 0x02, 0x01, 0xb0, 0x56, 0x24, 0x54, 0x91, 0x00, 0x0a, + 0x01, 0xc0, 0x40, 0x28, 0x9c, 0x91, 0x00, 0x08, 0x04, 0x00, 0x44, 0x23, 0x00, 0x20, 0x04, 0xf5, + 0x00, 0x11, 0x02, 0xfd, 0x00, 0x20, 0x04, 0xf3, 0x01, 0xc0, 0x58, 0x24, 0x70, 0x91, 0x00, 0x0a, + 0x80, 0x10, 0x82, 0x24, 0xac, 0x91, 0x00, 0x98, 0x00, 0x00, 0x42, 0xa3, 0x8a, 0x00, 0x46, 0xa3, + 0x80, 0x11, 0xc2, 0xe2, 0x80, 0x10, 0x82, 0x24, 0xac, 0x91, 0x00, 0x98, 0x84, 0x00, 0x44, 0xa3, + 0x00, 0x20, 0x04, 0xf5, 0x00, 0x11, 0x02, 0xfd, 0xac, 0x91, 0x00, 0x98, 0x00, 0x10, 0xc0, 0xe9, + 0x00, 0x00, 0xf6, 0x71, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x70, 0xce, 0xeb, 0x00, 0x70, 0xd2, 0x6b, + 0x00, 0x70, 0xc0, 0xe3, 0x0c, 0xb0, 0xc1, 0xa5, 0x04, 0x00, 0x42, 0x23, 0x11, 0x00, 0x7c, 0x23, + 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xd0, 0x91, 0x00, 0x0a, 0x80, 0x10, 0x82, 0x24, + 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf8, 0xf1, 0x60, 0x31, 0x7e, 0x45, 0x80, 0xcd, 0xb7, 0xf9, + 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x40, 0x31, 0x7e, 0xc5, + 0xc0, 0x31, 0x6a, 0x45, 0xe0, 0x31, 0x6c, 0xc5, 0xdc, 0x87, 0x00, 0x02, 0x01, 0x00, 0x42, 0x23, + 0x80, 0x50, 0xab, 0xe2, 0x00, 0x50, 0x2b, 0xed, 0x80, 0x6a, 0xad, 0xe4, 0x00, 0x60, 0x2d, 0xf9, + 0x20, 0x03, 0x6c, 0x49, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x58, 0x81, 0x00, 0x02, + 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x6b, 0x65, 0x00, 0x50, 0x2b, 0xf9, 0x20, 0xe0, 0x7d, 0x22, + 0x00, 0xe0, 0x69, 0xe5, 0x00, 0x40, 0x29, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x67, 0x65, + 0x00, 0x30, 0x27, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x20, 0x25, 0xf9, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x4c, 0x23, 0x00, 0x60, 0x8a, 0x70, 0x60, 0xb0, 0x92, 0x22, + 0x1f, 0xb0, 0x90, 0x22, 0x20, 0x00, 0x4e, 0x23, 0x00, 0x74, 0x50, 0xe4, 0x00, 0x80, 0x4e, 0xe3, + 0x00, 0x70, 0x0e, 0x63, 0x00, 0x70, 0x0e, 0x63, 0x00, 0x70, 0x0e, 0x63, 0x01, 0x70, 0x4e, 0x24, + 0x00, 0x53, 0x0a, 0x7d, 0x01, 0x80, 0x50, 0x24, 0x90, 0x92, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, + 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, + 0x00, 0xe0, 0x67, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, + 0x00, 0x20, 0x25, 0xf9, 0x00, 0x03, 0x68, 0x45, 0x20, 0x03, 0x6a, 0x45, 0x40, 0xb0, 0x7a, 0xa2, + 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0x00, 0xc0, 0x2d, + 0x64, 0x92, 0x00, 0x82, 0x20, 0x90, 0x40, 0x28, 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, 0xe3, + 0xac, 0x93, 0x00, 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x67, 0x65, + 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x20, 0x25, 0xf9, + 0x00, 0x03, 0x68, 0x45, 0x20, 0x03, 0x6a, 0x45, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x20, 0xe1, 0x6b, + 0x80, 0x00, 0x7a, 0xa3, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, + 0x2c, 0x92, 0x00, 0x82, 0x00, 0x20, 0xe1, 0x6b, 0x80, 0xd0, 0x7b, 0x22, 0x00, 0x00, 0x40, 0x23, + 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, + 0x80, 0xd5, 0x7b, 0xe2, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, + 0x2c, 0x92, 0x00, 0x82, 0x80, 0xb0, 0x40, 0xa8, 0xdc, 0x93, 0x00, 0x08, 0x64, 0x92, 0x00, 0x82, + 0x60, 0x90, 0x40, 0xa8, 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, 0xe3, 0x40, 0x90, 0x40, 0x28, + 0xac, 0x93, 0x00, 0x88, 0x00, 0x00, 0x66, 0xa3, 0x20, 0x90, 0x40, 0x28, 0xa0, 0x93, 0x00, 0x88, + 0x00, 0x00, 0x68, 0x23, 0x80, 0x52, 0xab, 0x62, 0x80, 0x53, 0xeb, 0x62, 0xf8, 0x93, 0x00, 0x98, + 0x80, 0x42, 0xa9, 0x62, 0x80, 0x43, 0xe9, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x32, 0xa7, 0x62, + 0x80, 0x33, 0xe7, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x22, 0xa5, 0x62, 0x80, 0x23, 0xe5, 0x62, + 0x10, 0xb0, 0x90, 0x22, 0xd0, 0x93, 0x00, 0x8a, 0x80, 0x2e, 0xa5, 0x64, 0xf8, 0x93, 0x00, 0x98, + 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x6a, 0xa3, 0xec, 0x93, 0x00, 0x98, 0x00, 0x20, 0xe1, 0x6b, + 0x00, 0x00, 0x6a, 0xa3, 0xff, 0x00, 0x4e, 0xa3, 0x80, 0x53, 0xeb, 0x62, 0x00, 0x00, 0x68, 0x23, + 0x00, 0x00, 0x66, 0xa3, 0x00, 0xd0, 0x65, 0xe3, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x20, 0xe1, 0x6b, + 0x00, 0x00, 0x21, 0xf9, 0x00, 0x10, 0x23, 0xf9, 0x80, 0x08, 0xb3, 0x79, 0x00, 0x00, 0x40, 0x23, + 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x60, 0x31, 0x7e, 0x45, 0xe0, 0x03, 0x74, 0x45, + 0x00, 0x04, 0x44, 0x45, 0x80, 0xac, 0x83, 0xff, 0x80, 0x2c, 0x84, 0xff, 0x80, 0xb0, 0x87, 0x7b, + 0x00, 0x31, 0x86, 0x7b, 0x40, 0x03, 0x46, 0xc9, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, + 0x00, 0x03, 0x58, 0x45, 0x00, 0xc0, 0x18, 0xf9, 0x10, 0x85, 0x00, 0x82, 0x00, 0x10, 0xbc, 0x28, + 0x10, 0x95, 0x00, 0x8a, 0x01, 0x00, 0x5a, 0x23, 0x00, 0xb6, 0x9c, 0x67, 0x00, 0x90, 0x79, 0xe3, + 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x4e, 0xc9, 0x80, 0x03, 0x50, 0x49, 0xa0, 0x03, 0x52, 0x49, + 0xc0, 0x03, 0x54, 0x49, 0x40, 0x03, 0x78, 0x45, 0xc0, 0x31, 0x56, 0x45, 0xe0, 0x31, 0x58, 0x45, + 0x01, 0x00, 0x5a, 0x23, 0x00, 0xb6, 0x9c, 0x67, 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x56, 0xc5, + 0x80, 0x03, 0x58, 0xc5, 0xa0, 0x03, 0x5a, 0xc5, 0xc0, 0x03, 0x5c, 0xc5, 0x00, 0x00, 0x40, 0x23, + 0x80, 0x05, 0x96, 0xfd, 0x00, 0x07, 0x9c, 0xfd, 0x18, 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, 0xe3, + 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0xe4, 0x84, 0x00, 0x82, 0x64, 0x81, 0x00, 0x02, + 0x00, 0x00, 0x7c, 0xa2, 0x20, 0x03, 0x48, 0x45, 0xff, 0x0f, 0x7e, 0xa3, 0x00, 0xf0, 0x41, 0x28, + 0x00, 0x82, 0x84, 0xe8, 0x18, 0x95, 0x00, 0x0a, 0x00, 0xf0, 0x41, 0x28, 0x00, 0x82, 0x84, 0xe8, + 0x18, 0x95, 0x00, 0x0a, 0xc3, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x10, 0x00, 0x7c, 0x22, + 0x40, 0x03, 0x4a, 0xc5, 0x00, 0x40, 0x08, 0xf9, 0x00, 0xe0, 0x49, 0x69, 0x20, 0xe0, 0x7d, 0x22, + 0x00, 0xe0, 0x4b, 0xe9, 0x00, 0x00, 0x40, 0x23, 0x50, 0x00, 0x42, 0xa3, 0x2c, 0x95, 0x00, 0x98, + 0x36, 0x00, 0x40, 0x23, 0x1c, 0x95, 0x00, 0x98, 0x36, 0x00, 0x40, 0x23, 0x3c, 0x00, 0x44, 0xa3, + 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, 0x42, 0x23, 0x2c, 0x95, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, + 0xd0, 0xa3, 0x00, 0x02, 0x94, 0x81, 0x00, 0x98, 0x00, 0x00, 0x8c, 0x67, 0x00, 0x63, 0x8c, 0xfb, + 0x01, 0x00, 0x7c, 0xa3, 0x00, 0x6f, 0x8e, 0x7b, 0x00, 0x70, 0xbc, 0x28, 0x6c, 0x96, 0x00, 0x88, + 0x60, 0x32, 0x50, 0x45, 0x00, 0x00, 0x7c, 0x23, 0x00, 0xe4, 0x93, 0x7d, 0x00, 0x83, 0x90, 0x67, + 0x80, 0x73, 0x94, 0x67, 0x80, 0xa3, 0x96, 0x67, 0x80, 0x84, 0x90, 0x67, 0x00, 0x85, 0x90, 0xfb, + 0x80, 0x84, 0x90, 0x67, 0x80, 0xb5, 0x98, 0x67, 0x00, 0xc6, 0x94, 0x67, 0x80, 0xc5, 0x98, 0xe7, + 0x00, 0xc4, 0x98, 0xe7, 0x00, 0xa6, 0x94, 0x67, 0x00, 0xa0, 0x42, 0x63, 0xac, 0x83, 0x00, 0x02, + 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x25, 0x9a, 0x67, 0x00, 0xd6, 0x9a, 0x67, + 0x00, 0x32, 0x7c, 0xc5, 0x00, 0xdf, 0x9c, 0x67, 0x80, 0xd6, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, + 0x00, 0xa4, 0x88, 0x68, 0xc0, 0x95, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, 0xc8, 0x95, 0x00, 0x98, + 0x00, 0xe0, 0x42, 0xe3, 0xc8, 0x95, 0x00, 0x98, 0x00, 0x93, 0x84, 0xe7, 0x00, 0xd0, 0x86, 0xe7, + 0x01, 0xe0, 0x89, 0xa4, 0x00, 0x32, 0x86, 0xe7, 0x00, 0x3f, 0x88, 0xe7, 0x00, 0x83, 0x8c, 0xe7, + 0x80, 0x31, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa3, 0xbc, 0xfd, 0x00, 0xe0, 0xbd, 0xa8, + 0xfc, 0x95, 0x00, 0x0a, 0x00, 0x30, 0x40, 0xe3, 0x04, 0x96, 0x00, 0x98, 0x00, 0x40, 0x40, 0x63, + 0x04, 0x96, 0x00, 0x98, 0x80, 0x10, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa4, 0xbc, 0x7d, + 0x00, 0xe0, 0xbd, 0xa8, 0x20, 0x96, 0x00, 0x8a, 0x00, 0x90, 0x46, 0xe3, 0x28, 0x96, 0x00, 0x18, + 0x00, 0x20, 0x46, 0x63, 0x28, 0x96, 0x00, 0x18, 0x38, 0x96, 0x00, 0x8a, 0x00, 0x10, 0x44, 0xe3, + 0x01, 0x00, 0x7c, 0xa3, 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, 0x44, 0x63, 0x00, 0x00, 0x7c, 0x23, + 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, 0x40, 0x23, 0x00, 0x01, 0x82, 0xfd, 0x01, 0x00, 0x50, 0x23, + 0x00, 0x24, 0x8c, 0x62, 0x00, 0xe3, 0xbd, 0x68, 0x64, 0x96, 0x00, 0x08, 0x00, 0x10, 0x56, 0xe3, + 0x6c, 0x96, 0x00, 0x18, 0x00, 0x20, 0x56, 0xe3, 0x6c, 0x96, 0x00, 0x18, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, 0x02, + 0x00, 0x70, 0xbc, 0x28, 0x70, 0x96, 0x00, 0x08, 0x80, 0xb3, 0x9a, 0xe7, 0x00, 0x30, 0x56, 0x63, + 0x00, 0x70, 0x58, 0x63, 0x00, 0x00, 0x00, 0x84, 0x40, 0x31, 0x7e, 0xc5, 0x00, 0x05, 0x42, 0xc5, + 0x00, 0x00, 0xc4, 0x73, 0xb4, 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, 0x02, 0x00, 0x70, 0xbc, 0x28, + 0x98, 0x96, 0x00, 0x08, 0x00, 0x33, 0x7c, 0x45, 0x00, 0x3f, 0x94, 0x67, 0x80, 0x75, 0x9a, 0xe7, + 0x80, 0x33, 0x98, 0x7d, 0x80, 0x33, 0x9c, 0xfb, 0x00, 0xd7, 0x80, 0x67, 0x00, 0x00, 0xbc, 0xa8, + 0x98, 0x96, 0x00, 0x08, 0x00, 0xa7, 0x96, 0x67, 0x80, 0xc6, 0x98, 0xe7, 0x00, 0xb6, 0x9c, 0x67, + 0x00, 0xb0, 0x96, 0x67, 0x00, 0xc0, 0x98, 0x67, 0x00, 0x00, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x08, 0x8d, 0xef, 0x00, 0x06, 0x8f, 0xef, 0x80, 0x63, 0x8c, 0x6f, 0x00, 0x60, 0x42, 0x63, + 0xa4, 0x82, 0x00, 0x02, 0x00, 0x30, 0x52, 0xe3, 0x80, 0x93, 0x92, 0x6f, 0x00, 0x31, 0x40, 0xc5, + 0x00, 0x90, 0x94, 0xef, 0x80, 0x94, 0x90, 0x6f, 0x00, 0x88, 0x90, 0x6f, 0x00, 0x86, 0x80, 0xe8, + 0x00, 0x90, 0x54, 0xef, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x68, 0xe3, 0x20, 0x31, 0x40, 0x45, + 0x60, 0x30, 0x42, 0xc5, 0x80, 0x30, 0x44, 0x45, 0x00, 0x4a, 0x97, 0x6f, 0x80, 0x05, 0x96, 0xef, + 0x80, 0xb5, 0x98, 0xef, 0x80, 0xc5, 0x98, 0x7b, 0x01, 0x00, 0x48, 0x23, 0x00, 0xc2, 0x9a, 0xfb, + 0x80, 0x26, 0x9a, 0x6f, 0x00, 0x00, 0x48, 0xa3, 0x00, 0x46, 0x9c, 0xfd, 0x00, 0xc0, 0x80, 0xa8, + 0x00, 0xe0, 0x40, 0x6f, 0x00, 0x17, 0x9c, 0x6f, 0x80, 0xd6, 0x98, 0xef, 0x00, 0xe7, 0xa0, 0x6f, + 0x00, 0x18, 0x9e, 0xef, 0x80, 0xc7, 0x98, 0xfb, 0x80, 0xc6, 0x98, 0x6f, 0x00, 0x07, 0xa1, 0x6f, + 0x00, 0x28, 0x9e, 0xef, 0x80, 0xc7, 0x98, 0xfb, 0x80, 0xb6, 0xa2, 0xef, 0xf0, 0x96, 0x00, 0x82, + 0x00, 0xba, 0xa4, 0x6f, 0x00, 0x25, 0xa5, 0xef, 0x00, 0xd0, 0x62, 0x6f, 0x00, 0xa0, 0x64, 0xef, + 0x00, 0x00, 0x42, 0xa3, 0x00, 0x19, 0x82, 0xfd, 0x00, 0x49, 0x81, 0x68, 0x01, 0x00, 0x44, 0x23, + 0x00, 0x01, 0x80, 0xe2, 0x00, 0x10, 0x64, 0x6f, 0x00, 0x10, 0x64, 0x63, 0x00, 0x27, 0xa5, 0x6f, + 0x00, 0xe0, 0x66, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x42, 0xc5, 0x00, 0x00, 0xc4, 0x73, + 0xb4, 0xa3, 0x00, 0x82, 0x28, 0x97, 0x00, 0x02, 0x00, 0x30, 0xbd, 0x28, 0xc8, 0x97, 0x00, 0x88, + 0x00, 0x00, 0x00, 0x84, 0x20, 0x30, 0x7e, 0x45, 0x60, 0x10, 0x40, 0x28, 0x18, 0x98, 0x00, 0x08, + 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x66, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x00, 0x68, 0x23, + 0x80, 0x49, 0xb9, 0x79, 0x80, 0xc9, 0x83, 0xe8, 0xb4, 0x99, 0x00, 0x0a, 0x00, 0xc0, 0x83, 0xa8, + 0xb4, 0x99, 0x00, 0x88, 0x2c, 0x98, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, 0x00, 0x00, 0xe8, 0xf3, + 0x80, 0x49, 0xb9, 0x79, 0x00, 0xc0, 0x83, 0xa8, 0xb4, 0x99, 0x00, 0x88, 0x00, 0x00, 0xc0, 0xf3, + 0x00, 0x00, 0xc2, 0x73, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x00, 0xc6, 0xf3, 0x00, 0x00, 0xc0, 0x63, + 0x0a, 0xc0, 0xc1, 0x25, 0x04, 0x00, 0x44, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x04, 0xf3, + 0x01, 0xe0, 0x7d, 0x24, 0x4c, 0x98, 0x00, 0x0a, 0x80, 0x20, 0x84, 0x24, 0x00, 0x20, 0xc0, 0xe9, + 0x00, 0x00, 0xfa, 0x71, 0x20, 0x01, 0x78, 0xc9, 0x40, 0x01, 0x7a, 0x49, 0x20, 0x30, 0x7e, 0x45, + 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xcf, 0xf9, 0xff, 0x00, 0x30, 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, + 0xc0, 0x30, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, + 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x9c, 0xa4, 0x00, 0xc7, 0x98, 0x6f, 0x00, 0xd7, 0x9a, 0x6f, + 0x00, 0xc0, 0x52, 0xe3, 0x00, 0xd0, 0x54, 0x63, 0x00, 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, + 0xc0, 0x99, 0x00, 0x0a, 0x80, 0x30, 0x50, 0x45, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, + 0xc0, 0x99, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0xc0, 0x99, 0x00, 0x0a, 0x00, 0xb0, 0x42, 0xe3, + 0x98, 0x83, 0x00, 0x82, 0x80, 0x90, 0x92, 0x6f, 0x80, 0xa0, 0x94, 0x6f, 0x00, 0x90, 0x19, 0x6d, + 0x00, 0xc0, 0x18, 0xf3, 0xaa, 0xc0, 0x98, 0xa4, 0x00, 0xc0, 0x18, 0xf3, 0x00, 0x01, 0x40, 0xc5, + 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0xa8, 0xe2, 0x60, 0x40, 0x41, 0xa8, 0x08, 0x99, 0x00, 0x08, + 0x02, 0xc0, 0x98, 0x24, 0x0c, 0x99, 0x00, 0x18, 0x01, 0xc0, 0x98, 0x24, 0x00, 0xc0, 0x18, 0xf3, + 0x01, 0xc0, 0x98, 0x24, 0x04, 0xa4, 0xd9, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xd3, 0xb7, + 0xb4, 0x99, 0x00, 0x9c, 0x06, 0xa4, 0xd5, 0xb7, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, + 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, 0x00, 0x9c, 0x20, 0x01, 0x78, 0xc5, + 0x40, 0x01, 0x7a, 0x45, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, + 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xc0, 0xb9, 0xfd, 0x00, 0x00, 0xc4, 0x73, 0x00, 0xd1, 0xbb, 0xe8, + 0x00, 0x90, 0x75, 0xe3, 0xff, 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, + 0x80, 0xc4, 0x94, 0x68, 0x00, 0xa4, 0xf9, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, + 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x03, 0xa4, 0xc5, 0x37, + 0xb4, 0x99, 0x00, 0x9c, 0x04, 0xa4, 0xd5, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, + 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, + 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, + 0x05, 0xa4, 0xc1, 0x39, 0x41, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x10, 0x40, 0x28, + 0xe0, 0x99, 0x00, 0x08, 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x66, 0xe5, 0xe4, 0x99, 0x00, 0x18, + 0x00, 0x00, 0xe6, 0x73, 0x01, 0x00, 0x64, 0xa3, 0x00, 0x20, 0x25, 0xed, 0x00, 0x00, 0x62, 0x23, + 0x00, 0x01, 0x60, 0x23, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xf9, 0xeb, + 0x00, 0xd0, 0x3b, 0xf9, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, + 0x00, 0x00, 0x80, 0x70, 0x80, 0x0e, 0xba, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0xd0, 0xfb, 0x62, + 0x00, 0xc0, 0x39, 0xf9, 0x20, 0x01, 0x7a, 0x49, 0x40, 0x01, 0x78, 0xc9, 0x00, 0x00, 0xfc, 0xf3, + 0x60, 0x31, 0x7e, 0x45, 0x00, 0xdf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xc0, 0x31, 0x56, 0x45, + 0xe0, 0x31, 0x58, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, + 0x01, 0x00, 0x9a, 0xa4, 0x80, 0xb6, 0x96, 0xe7, 0x00, 0xb6, 0x9c, 0x67, 0x80, 0xc6, 0x98, 0xe7, + 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, + 0x00, 0xe0, 0x54, 0x63, 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, 0xf0, 0x86, 0x00, 0x02, + 0x00, 0x00, 0x40, 0xa8, 0x70, 0x9b, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, + 0xe4, 0x84, 0x00, 0x82, 0x00, 0x90, 0x15, 0x6d, 0x00, 0xa0, 0x14, 0xf3, 0xaa, 0xa0, 0x94, 0xa4, + 0x00, 0xa0, 0x14, 0xf3, 0x00, 0x01, 0x40, 0xc5, 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0x92, 0xe2, + 0x60, 0x90, 0x40, 0xa8, 0xc0, 0x9a, 0x00, 0x88, 0x02, 0xa0, 0x94, 0x24, 0xc4, 0x9a, 0x00, 0x98, + 0x01, 0xa0, 0x94, 0x24, 0x00, 0xa0, 0x14, 0xf3, 0x02, 0xa0, 0x94, 0x24, 0x04, 0xa4, 0xd5, 0x37, + 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xd1, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, + 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0x9b, 0x00, 0x9c, 0x20, 0x01, 0x78, 0xc5, + 0x40, 0x01, 0x7a, 0x45, 0x00, 0x00, 0x40, 0x23, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x0e, 0xbc, 0xf9, + 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x80, 0x24, + 0x00, 0xe0, 0xb9, 0x7d, 0x00, 0x00, 0xc4, 0x73, 0x00, 0xd1, 0xbb, 0xe8, 0x00, 0x90, 0x75, 0xe3, + 0xff, 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, 0x80, 0xa4, 0x94, 0x68, + 0x00, 0xa4, 0xf9, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, 0x7c, 0x9b, 0x00, 0x9c, + 0x02, 0xa4, 0xc1, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x03, 0xa4, 0xc5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, + 0x04, 0xa4, 0xd5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0x7c, 0x9b, 0x00, 0x9c, + 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0x9b, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, + 0x05, 0xa4, 0xc1, 0x39, 0x41, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, + 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xc6, 0xf3, 0x00, 0x00, 0xc8, 0x73, + 0x00, 0x00, 0xca, 0xf3, 0x00, 0x00, 0xcc, 0xf3, 0x00, 0x30, 0xc0, 0x63, 0x0b, 0x40, 0xc1, 0x25, + 0x4c, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x43, 0x63, + 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xb0, 0x9b, 0x00, 0x0a, + 0x00, 0x00, 0xc0, 0x69, 0x0e, 0x00, 0x7c, 0xa3, 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, + 0x01, 0xe0, 0x7d, 0x24, 0xc8, 0x9b, 0x00, 0x0a, 0x04, 0x00, 0x7c, 0xa3, 0x00, 0x00, 0x42, 0xa3, + 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xe0, 0x9b, 0x00, 0x0a, + 0x1a, 0x00, 0x7c, 0xa3, 0x00, 0x0f, 0xc0, 0xe2, 0x80, 0x00, 0x80, 0x24, 0x00, 0x00, 0xc0, 0x69, + 0x00, 0x00, 0xf6, 0x71, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x30, 0xc6, 0xeb, 0x00, 0x30, 0xca, 0xeb, + 0x00, 0x30, 0xc0, 0x63, 0x0b, 0xb0, 0xc1, 0x25, 0x04, 0x00, 0x42, 0x23, 0x11, 0x00, 0x7c, 0x23, + 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x20, 0x9c, 0x00, 0x8a, 0x80, 0x10, 0x82, 0x24, + 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf8, 0xf1, 0x20, 0x01, 0x64, 0x49, 0x20, 0x30, 0x7e, 0x45, + 0x80, 0xcd, 0xb7, 0xf9, 0x00, 0xb0, 0x81, 0xa8, 0xdc, 0x9d, 0x00, 0x88, 0xa0, 0x30, 0x6c, 0xc5, + 0xc0, 0x30, 0x6e, 0x45, 0xa8, 0x8b, 0x00, 0x02, 0x00, 0x00, 0x46, 0xe3, 0x00, 0x00, 0x40, 0xa8, + 0xfc, 0x9d, 0x00, 0x8a, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x0b, 0xac, 0x79, + 0x00, 0x60, 0x81, 0x28, 0xe4, 0x9d, 0x00, 0x08, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, + 0xb4, 0xa3, 0x00, 0x82, 0x00, 0x00, 0x72, 0x63, 0x01, 0x90, 0xb3, 0x24, 0x80, 0x9d, 0x83, 0x7f, + 0xa8, 0x81, 0x00, 0x02, 0x20, 0x01, 0x64, 0x45, 0x80, 0x2c, 0x95, 0xff, 0x80, 0x6c, 0x97, 0xff, + 0x80, 0xa5, 0x99, 0x7f, 0x80, 0x55, 0x9b, 0xff, 0x80, 0xc6, 0x96, 0xfb, 0x80, 0xa5, 0x94, 0x7b, + 0x00, 0x15, 0x94, 0xff, 0x00, 0xa0, 0x80, 0xa8, 0xec, 0x9d, 0x00, 0x88, 0x40, 0x01, 0x54, 0x49, + 0x00, 0xa0, 0x42, 0x63, 0xa8, 0x81, 0x00, 0x02, 0x80, 0x20, 0xb9, 0x7f, 0x80, 0x60, 0xb7, 0x7f, + 0x00, 0x30, 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, 0xc0, 0x30, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, + 0x94, 0x8a, 0x00, 0x82, 0x00, 0x90, 0x5e, 0xe3, 0x00, 0xa0, 0x60, 0x63, 0x00, 0xb0, 0x62, 0x63, + 0x60, 0x01, 0x58, 0xc5, 0x80, 0x01, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0xb0, 0x79, 0x63, + 0x94, 0x8a, 0x00, 0x82, 0x80, 0xf5, 0x84, 0xef, 0x80, 0x98, 0x86, 0xef, 0x80, 0x21, 0x80, 0xe8, + 0x38, 0x9d, 0x00, 0x0a, 0x80, 0x05, 0x85, 0x6f, 0x80, 0xa8, 0x86, 0xef, 0x80, 0x21, 0x80, 0xe8, + 0xf4, 0x9d, 0x00, 0x0a, 0xfc, 0x89, 0x00, 0x02, 0x00, 0x90, 0x58, 0xe3, 0x00, 0xa0, 0x5a, 0x63, + 0x00, 0xb0, 0x5c, 0xe3, 0x48, 0x9d, 0x00, 0x98, 0x00, 0xf0, 0x58, 0xe3, 0x00, 0x00, 0x5b, 0xe3, + 0x00, 0x10, 0x5d, 0x63, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, + 0x80, 0xc0, 0x98, 0x6f, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x06, 0x98, 0x79, + 0x00, 0x00, 0x7e, 0xa3, 0x00, 0xf0, 0x41, 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, 0x9d, 0x00, 0x0a, + 0x00, 0xf0, 0x41, 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, 0x9d, 0x00, 0x0a, 0x00, 0x00, 0x46, 0x23, + 0xc3, 0x00, 0x44, 0xa3, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x45, 0x69, + 0x00, 0x30, 0x40, 0xa8, 0x01, 0x00, 0x42, 0x23, 0xbc, 0x9d, 0x00, 0x0a, 0x50, 0x00, 0x42, 0xa3, + 0x10, 0x00, 0x7c, 0x22, 0x00, 0x60, 0x2d, 0xf9, 0x00, 0xe0, 0x6d, 0x69, 0x20, 0xe0, 0x7d, 0x22, + 0x40, 0x01, 0x54, 0x45, 0x00, 0xa0, 0x14, 0xf9, 0x00, 0xe0, 0x55, 0xe9, 0x00, 0x30, 0x40, 0xe3, + 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x76, 0x23, + 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x94, 0x81, 0x00, 0x98, 0x21, 0x00, 0x46, 0x23, + 0xfc, 0x9d, 0x00, 0x98, 0x22, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, 0x23, 0x00, 0x46, 0xa3, + 0xfc, 0x9d, 0x00, 0x98, 0x24, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, 0x3c, 0x00, 0x44, 0xa3, + 0x01, 0x00, 0x42, 0x23, 0x84, 0x9d, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x40, 0x31, 0x7e, 0xc5, + 0x00, 0x00, 0x40, 0x23, 0x00, 0x08, 0x80, 0xf9, 0x00, 0x08, 0x80, 0xe8, 0xdc, 0x9e, 0x00, 0x0a, + 0xd8, 0x8c, 0x00, 0x02, 0xdc, 0x9e, 0x00, 0x0a, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, + 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xa4, 0x24, 0x00, 0x09, 0xa1, 0x67, 0x00, 0x19, 0xa3, 0x67, + 0x00, 0x00, 0xfc, 0xf3, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x3f, 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, + 0x70, 0x96, 0x00, 0x02, 0x5c, 0x8e, 0x00, 0x82, 0xd0, 0x8e, 0x00, 0x02, 0x00, 0x70, 0x6e, 0x63, + 0x00, 0x80, 0x70, 0x63, 0x00, 0x90, 0x72, 0x63, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, + 0x00, 0x00, 0x4f, 0xe3, 0x00, 0x20, 0x51, 0x63, 0x00, 0x10, 0x53, 0xe3, 0x0c, 0x8d, 0x00, 0x82, + 0x00, 0x00, 0xfc, 0xf3, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x3f, 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, + 0x5c, 0x8e, 0x00, 0x82, 0xd0, 0x8e, 0x00, 0x02, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, + 0x00, 0x00, 0x40, 0x23, 0x80, 0x04, 0x92, 0xfd, 0x00, 0x70, 0x57, 0x63, 0x00, 0x80, 0x59, 0xe3, + 0x00, 0x90, 0x5b, 0xe3, 0x0c, 0x8d, 0x00, 0x82, 0x00, 0xc0, 0x42, 0x63, 0x74, 0x84, 0x00, 0x82, + 0x80, 0xb0, 0x96, 0xe7, 0x80, 0xd0, 0x9a, 0xe7, 0x01, 0x00, 0x58, 0xa3, 0xd4, 0x8d, 0x00, 0x82, + 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x12, 0x00, 0x40, 0x23, + 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0xa8, 0xa4, 0x00, 0x18, + 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, 0x22, 0x00, 0x40, 0x48, 0xe5, 0xff, 0x00, 0x44, 0xa3, + 0x00, 0x41, 0x82, 0xe2, 0x00, 0x40, 0x32, 0xf5, 0x00, 0x90, 0x09, 0xf5, 0x00, 0x40, 0x08, 0xf5, + 0x00, 0x91, 0xb3, 0xe2, 0x00, 0x41, 0x88, 0xe2, 0x00, 0x00, 0x00, 0x84, 0xf0, 0x9e, 0x00, 0x02, + 0x00, 0x90, 0x33, 0x63, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x01, 0x90, 0x75, 0x22, + 0x04, 0xa4, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x02, 0x40, 0x40, 0xa8, 0x54, 0x9f, 0x00, 0x08, + 0x01, 0x40, 0x40, 0xa8, 0x70, 0x9f, 0x00, 0x08, 0xf4, 0x00, 0x46, 0xa3, 0x3c, 0x00, 0x44, 0xa3, + 0x8c, 0x9f, 0x00, 0x98, 0xcc, 0x99, 0x00, 0x82, 0x00, 0x30, 0x40, 0xa8, 0x68, 0x9f, 0x00, 0x08, + 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xc3, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, + 0xe4, 0x97, 0x00, 0x02, 0x00, 0x30, 0x40, 0xa8, 0x84, 0x9f, 0x00, 0x88, 0x3c, 0x00, 0x44, 0xa3, + 0x8c, 0x9f, 0x00, 0x98, 0xc3, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0x64, 0x81, 0x00, 0x02, + 0x00, 0x00, 0x40, 0xa2, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x44, 0x69, 0x00, 0x30, 0x40, 0xe3, + 0x00, 0xa1, 0x00, 0x98, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x68, 0xe3, 0x00, 0x40, 0x6b, 0x22, + 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x35, 0x63, 0x01, 0xa0, 0x75, 0x22, 0xf2, 0x00, 0x46, 0xa3, + 0x04, 0xa4, 0xc1, 0xb9, 0x70, 0xa0, 0x00, 0x9e, 0x04, 0xa4, 0xc5, 0x35, 0x7c, 0xa0, 0x00, 0x1c, + 0xf6, 0x00, 0x46, 0x23, 0xff, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x4a, 0x63, 0x00, 0x50, 0x0a, 0xf5, + 0x00, 0x5f, 0x88, 0xe2, 0x01, 0x40, 0x40, 0xa8, 0xf4, 0x9f, 0x00, 0x08, 0x02, 0x40, 0x40, 0xa8, + 0x70, 0xa0, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0xaa, 0x40, 0x40, 0x28, + 0x70, 0xa0, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0x80, 0x4c, 0x40, 0x68, + 0x70, 0xa0, 0x00, 0x8a, 0xf4, 0x00, 0x46, 0xa3, 0x00, 0xe1, 0xbd, 0xe2, 0x02, 0xe0, 0x41, 0x28, + 0x44, 0xa0, 0x00, 0x88, 0x01, 0xe0, 0x41, 0x28, 0x70, 0xa0, 0x00, 0x8a, 0x50, 0x00, 0x42, 0xa3, + 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, 0x00, 0x1c, 0x06, 0xa4, 0xe3, 0x35, 0x7c, 0xa0, 0x00, 0x1c, + 0x50, 0xa0, 0x00, 0x18, 0x30, 0x00, 0x42, 0xa3, 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, 0x00, 0x1c, + 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0xff, 0x0f, 0x4a, 0x23, 0x80, 0x22, 0x84, 0x62, + 0x00, 0x20, 0x04, 0xf3, 0xc3, 0x20, 0x84, 0xa4, 0x00, 0x00, 0x40, 0x23, 0x8c, 0xa0, 0x00, 0x98, + 0x12, 0x00, 0x44, 0xa3, 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, 0x00, 0x98, 0x3c, 0x00, 0x44, 0xa3, + 0xf2, 0x00, 0x46, 0xa3, 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, 0x00, 0x98, 0x00, 0x50, 0x45, 0xe9, + 0x10, 0x40, 0x6d, 0xa2, 0x00, 0x00, 0x21, 0xf9, 0x00, 0x60, 0x61, 0xe9, 0x20, 0x60, 0x6d, 0x22, + 0x00, 0x10, 0x23, 0xf9, 0x00, 0x60, 0x63, 0x69, 0x00, 0x00, 0x40, 0x23, 0x00, 0xa1, 0x00, 0x98, + 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x33, 0x63, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x6a, 0x22, + 0x03, 0x94, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, + 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, 0x73, 0x22, 0x03, 0x94, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, + 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x05, 0x94, 0xc1, 0x39, 0xc3, 0x00, 0x44, 0xa3, + 0x00, 0x50, 0x45, 0xe9, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x40, 0x23, 0x00, 0xa1, 0x00, 0x98, + 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, + 0x00, 0x00, 0x44, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x94, 0x81, 0x00, 0x98, 0x58, 0x81, 0x00, 0x02, + 0x00, 0x00, 0x48, 0x22, 0x00, 0x40, 0x48, 0xe5, 0x00, 0x40, 0x04, 0xf5, 0xff, 0x00, 0x4c, 0x23, + 0x00, 0x23, 0x84, 0x62, 0x00, 0x20, 0x32, 0x63, 0x01, 0x90, 0xb3, 0x24, 0x04, 0x94, 0xcb, 0xb5, + 0x0c, 0xa2, 0x00, 0x1c, 0xff, 0x00, 0x4c, 0x23, 0x00, 0x53, 0x8e, 0xe2, 0x01, 0x70, 0x40, 0xa8, + 0x00, 0xa2, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x50, 0x0a, 0xf5, + 0x00, 0x53, 0x8e, 0xe2, 0x00, 0x71, 0x40, 0x68, 0xf4, 0xa1, 0x00, 0x0a, 0x05, 0x94, 0xcb, 0x35, + 0x0c, 0xa2, 0x00, 0x1c, 0x60, 0x01, 0x4a, 0xc9, 0x06, 0x94, 0xcb, 0x35, 0x0c, 0xa2, 0x00, 0x1c, + 0x80, 0x01, 0x4a, 0x49, 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, 0x73, 0x24, 0x00, 0x94, 0xf5, 0xb5, + 0x0c, 0xa2, 0x00, 0x1c, 0x01, 0x94, 0xed, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x02, 0x94, 0xeb, 0x35, + 0x0c, 0xa2, 0x00, 0x1c, 0x03, 0x94, 0xef, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x05, 0x94, 0xc1, 0x39, + 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x64, 0x65, 0x00, 0x20, 0x25, 0xf9, 0x20, 0x30, 0x7e, 0x45, + 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, + 0x00, 0x50, 0xab, 0xfb, 0x00, 0x00, 0xd4, 0xf3, 0x00, 0x65, 0xad, 0x68, 0x00, 0x75, 0xaf, 0x68, + 0x80, 0x6b, 0xa9, 0xe8, 0xa0, 0x00, 0x60, 0xc5, 0x00, 0x00, 0x21, 0xf9, 0xc0, 0x00, 0x62, 0x45, + 0x88, 0x9b, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf6, 0x00, 0x46, 0x23, 0x14, 0xa2, 0x00, 0x98, + 0x05, 0x94, 0xc1, 0x39, 0xf4, 0x00, 0x46, 0xa3, 0x14, 0xa2, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, + 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x05, 0x94, 0xc1, 0x39, + 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x12, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, + 0x00, 0x30, 0x40, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, + 0x00, 0x00, 0x6c, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x6e, 0x23, 0x94, 0x81, 0x00, 0x98, + 0x20, 0x00, 0x42, 0x23, 0x94, 0x81, 0x00, 0x98, 0xf2, 0x00, 0x40, 0xa3, 0x50, 0xa2, 0x00, 0x98, + 0x00, 0x00, 0xe6, 0x73, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, + 0x00, 0x00, 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0x30, 0xe7, 0x62, + 0x40, 0x00, 0x66, 0x49, 0x09, 0x00, 0x60, 0xa3, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, + 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x40, 0x00, 0x66, 0x45, + 0x20, 0x00, 0x60, 0x45, 0x60, 0x00, 0x60, 0xc9, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, + 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x20, 0x00, 0x42, 0x45, + 0x00, 0x12, 0xe0, 0xb5, 0x58, 0xa2, 0x00, 0x9c, 0x40, 0x00, 0x66, 0x45, 0x0c, 0x9e, 0x00, 0x02, + 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, + 0x60, 0x00, 0x60, 0xc5, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x10, 0xe6, 0x35, 0x58, 0xa2, 0x00, 0x9c, + 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, + 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0x30, 0xe7, 0x62, 0x0c, 0x9e, 0x00, 0x02, + 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x00, 0x00, 0x66, 0xa3, + 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x50, 0xa2, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, + 0xd0, 0xa3, 0x00, 0x02, 0xe4, 0xa3, 0x00, 0x82, 0x04, 0xa4, 0x00, 0x82, 0x24, 0xa4, 0x00, 0x02, + 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xc0, 0x63, 0x94, 0x81, 0x00, 0x98, 0x1c, 0x00, 0x7c, 0xa3, + 0x00, 0x10, 0x23, 0xf9, 0x00, 0x00, 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, 0xfd, + 0x80, 0x08, 0x21, 0x7d, 0x00, 0x10, 0x23, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x5c, 0xa3, 0x00, 0x0a, + 0x00, 0x00, 0xc0, 0x69, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, 0xfd, 0x00, 0x00, 0x21, 0xf3, + 0x01, 0xe0, 0x7d, 0x24, 0x78, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, 0x00, 0x00, 0x00, 0x84, + 0x54, 0x00, 0x46, 0xa3, 0x00, 0x30, 0x06, 0xf3, 0x53, 0x30, 0x86, 0xa4, 0x00, 0x30, 0x06, 0xf3, + 0x01, 0x30, 0x86, 0x24, 0x00, 0x30, 0x06, 0xf3, 0x80, 0x30, 0x86, 0x24, 0x00, 0x30, 0x06, 0xf5, + 0x00, 0x00, 0x00, 0x84, 0x90, 0xa3, 0x00, 0x82, 0x01, 0x06, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xed, + 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xc0, 0xeb, 0x00, 0x10, 0x80, 0xf9, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x08, 0x4c, 0xa3, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x60, 0x7e, 0x69, 0xd4, 0xa3, 0x00, 0x0a, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x02, 0x4c, 0xa3, 0x10, 0x00, 0x44, 0x23, 0x00, 0x20, 0x04, 0xf3, + 0x00, 0x61, 0x86, 0xe4, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0xf0, 0xa3, 0x00, 0x0a, + 0x00, 0x00, 0x00, 0x84, 0x80, 0x00, 0x4c, 0xa3, 0x50, 0x00, 0x44, 0xa3, 0x00, 0x20, 0x04, 0xf3, + 0x00, 0x61, 0x86, 0xe4, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0x10, 0xa4, 0x00, 0x0a, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x44, 0xa3, + 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x48, 0xa3, 0x00, 0x00, 0x4a, 0x23, 0x00, 0x00, 0x4c, 0x23, + 0x00, 0x00, 0x4e, 0xa3, 0x00, 0x00, 0x50, 0xa3, 0x00, 0x00, 0x52, 0x23, 0x00, 0x00, 0x54, 0x23, + 0x00, 0x00, 0x56, 0xa3, 0x00, 0x00, 0x58, 0x23, 0x00, 0x00, 0x5a, 0xa3, 0x00, 0x00, 0x5c, 0xa3, + 0x00, 0x00, 0x5e, 0x23, 0x00, 0x00, 0x60, 0xa3, 0x00, 0x00, 0x62, 0x23, 0x00, 0x00, 0x64, 0x23, + 0x00, 0x00, 0x66, 0xa3, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, + 0x00, 0x00, 0x6e, 0x23, 0x00, 0x00, 0x70, 0x23, 0x00, 0x00, 0x72, 0xa3, 0x00, 0x00, 0x74, 0xa3, + 0x00, 0x00, 0x76, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x7c, 0x23, + 0x00, 0x00, 0x7e, 0xa3, 0x00, 0x00, 0x00, 0x84}; \ No newline at end of file diff --git a/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_1_0_1/fw_CPU.h b/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_1_0_1/fw_CPU.h index 7e2a7858c..88ddd444b 100644 --- a/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_1_0_1/fw_CPU.h +++ b/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_1_0_1/fw_CPU.h @@ -5,1233 +5,1463 @@ /** * @brief CPU firmware version fw_v1.0.1_signed.bin for bootloader v1.0.1 */ -const uint8_t fw_CPU[] - = {0x5f, 0x3c, 0xc7, 0xed, 0xef, 0x9d, 0x5f, 0x8c, 0x74, 0x18, 0xbe, 0x71, 0xe6, 0x29, 0xcb, 0x5b, 0x8d, 0x93, 0xd7, - 0xf7, 0x9c, 0x5c, 0xc4, 0x88, 0x50, 0x0a, 0x63, 0x0e, 0xa1, 0xf9, 0xc8, 0x72, 0x16, 0x8b, 0x99, 0x77, 0x0f, 0x5e, - 0xd6, 0xc1, 0x64, 0x19, 0x2f, 0x48, 0xa6, 0x72, 0x68, 0x40, 0xb0, 0x9b, 0x5d, 0xe3, 0x0f, 0xe4, 0x15, 0x2c, 0x61, - 0xf4, 0xa9, 0x80, 0x6d, 0x8b, 0x6d, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, - 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x2c, 0x57, 0x00, 0x00, 0x02, 0x41, 0xc9, 0x04, 0xec, 0x8f, 0xcf, 0xa2, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x6f, 0x30, - 0x00, 0x43, 0x6f, 0x30, 0x20, 0x3d, 0x6f, 0x30, 0xe0, 0x3c, 0x6f, 0x30, 0xa0, 0x3c, 0x6f, 0x30, 0x60, 0x3c, 0x6f, - 0x30, 0x20, 0x3c, 0x6f, 0x30, 0xe0, 0x3b, 0x6f, 0x50, 0x60, 0x04, 0x6f, 0x30, 0x60, 0x3b, 0x6f, 0x30, 0x20, 0x3b, - 0x6f, 0x30, 0xe0, 0x3a, 0x6f, 0x30, 0xa0, 0x7f, 0x6f, 0x30, 0x60, 0x3a, 0x6f, 0x30, 0x20, 0x3a, 0x6f, 0x30, 0xe0, - 0x39, 0x6f, 0x30, 0xa0, 0x39, 0x6f, 0x40, 0xf0, 0x72, 0x6f, 0x30, 0x20, 0x26, 0x6f, 0x30, 0x50, 0x20, 0x6f, 0x40, - 0x30, 0x22, 0x6f, 0x40, 0xf0, 0x21, 0x6f, 0x40, 0xb0, 0x21, 0x6f, 0x30, 0xa0, 0x4c, 0x6f, 0x30, 0xa0, 0x4d, 0x6f, - 0x30, 0xf0, 0x42, 0x6f, 0x40, 0x50, 0x56, 0x6f, 0x30, 0x20, 0x4e, 0x6f, 0x20, 0x30, 0x1f, 0x6f, 0x40, 0x70, 0x0a, - 0x6f, 0x30, 0xa0, 0x4e, 0x6f, 0x30, 0x00, 0x5b, 0x6f, 0x30, 0x00, 0x3f, 0x93, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, - 0x00, 0x93, 0x01, 0x00, 0x00, 0x13, 0x02, 0x00, 0x00, 0x93, 0x02, 0x00, 0x00, 0x13, 0x03, 0x00, 0x00, 0x93, 0x03, - 0x00, 0x00, 0x13, 0x04, 0x00, 0x00, 0x93, 0x04, 0x00, 0x00, 0x13, 0x05, 0x00, 0x00, 0x93, 0x05, 0x00, 0x00, 0x13, - 0x06, 0x00, 0x00, 0x93, 0x06, 0x00, 0x00, 0x13, 0x07, 0x00, 0x00, 0x93, 0x07, 0x00, 0x00, 0x13, 0x08, 0x00, 0x00, - 0x93, 0x08, 0x00, 0x00, 0x13, 0x09, 0x00, 0x00, 0x93, 0x09, 0x00, 0x00, 0x13, 0x0a, 0x00, 0x00, 0x93, 0x0a, 0x00, - 0x00, 0x13, 0x0b, 0x00, 0x00, 0x93, 0x0b, 0x00, 0x00, 0x13, 0x0c, 0x00, 0x00, 0x93, 0x0c, 0x00, 0x00, 0x13, 0x0d, - 0x00, 0x00, 0x93, 0x0d, 0x00, 0x00, 0x13, 0x0e, 0x00, 0x00, 0x93, 0x0e, 0x00, 0x00, 0x13, 0x0f, 0x00, 0x00, 0x93, - 0x0f, 0x00, 0x00, 0x97, 0x00, 0x00, 0x00, 0x93, 0x80, 0x40, 0xf0, 0x73, 0x90, 0x50, 0x30, 0x93, 0x00, 0x00, 0x00, - 0x17, 0x41, 0x10, 0x00, 0x13, 0x01, 0x41, 0xcf, 0x33, 0x04, 0x01, 0x00, 0x17, 0x0d, 0x10, 0x00, 0x13, 0x0d, 0x8d, - 0xee, 0x97, 0x4d, 0x10, 0x00, 0x93, 0x8d, 0x0d, 0xce, 0x63, 0x57, 0xbd, 0x01, 0x23, 0x20, 0x0d, 0x00, 0x11, 0x0d, - 0xe3, 0x4d, 0xbd, 0xff, 0xef, 0x00, 0xf0, 0x60, 0x73, 0x00, 0x50, 0x10, 0xf5, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x23, - 0xa6, 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0x07, 0xf2, - 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0x07, 0xf2, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x88, 0x07, 0xf2, 0x82, 0x80, 0x18, - 0x41, 0xfd, 0x57, 0x63, 0x02, 0xf7, 0x06, 0x13, 0x07, 0x45, 0x00, 0x81, 0x47, 0x13, 0x06, 0xf0, 0x07, 0x14, 0x43, - 0x81, 0xea, 0x85, 0x07, 0x11, 0x07, 0xe3, 0x9c, 0xc7, 0xfe, 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x01, 0x47, 0x93, - 0x05, 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, 0x05, 0x8a, 0x19, 0xca, 0x93, 0x05, 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, - 0x05, 0x8a, 0x15, 0xc6, 0x05, 0x07, 0xe3, 0x1b, 0xb7, 0xfe, 0x21, 0xa0, 0x05, 0x07, 0xe3, 0x11, 0xb7, 0xfe, 0x89, - 0x07, 0x93, 0x06, 0x00, 0x08, 0x7d, 0x56, 0xe3, 0x85, 0xd7, 0xfc, 0x85, 0x07, 0x13, 0x97, 0x27, 0x00, 0x2a, 0x97, - 0x03, 0x27, 0xc7, 0xff, 0xe3, 0x08, 0xc7, 0xfe, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x05, 0x67, 0xaa, 0x87, 0x01, - 0x17, 0x01, 0x45, 0x94, 0x43, 0x99, 0xe6, 0x13, 0x05, 0x05, 0x02, 0x91, 0x07, 0xe3, 0x1b, 0xe5, 0xfe, 0x82, 0x80, - 0x81, 0x47, 0x13, 0x06, 0x00, 0x02, 0x33, 0xd7, 0xf6, 0x00, 0x05, 0x8b, 0x09, 0xe7, 0x85, 0x07, 0x05, 0x05, 0xe3, - 0x9a, 0xc7, 0xfe, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x14, 0x20, 0x00, 0x13, 0x04, 0x04, 0x00, 0x83, 0x46, - 0x94, 0x07, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, 0x64, 0x13, - 0x06, 0x06, 0x3d, 0x93, 0x85, 0xc5, 0x3d, 0x06, 0xc6, 0xef, 0x10, 0x30, 0x4c, 0x03, 0x45, 0x94, 0x07, 0xb2, 0x40, - 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x40, 0x90, 0x0b, 0xef, 0x20, 0xc0, 0x58, 0x93, - 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x00, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x40, 0x50, 0x0c, 0xb2, 0x40, 0x41, 0x01, - 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x05, 0x05, 0x10, 0x2a, 0x84, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, - 0x3e, 0x06, 0xc6, 0xef, 0x10, 0x30, 0x4f, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf5, 0x14, 0x43, 0x85, 0x47, - 0xb3, 0x97, 0x87, 0x00, 0xb2, 0x40, 0x22, 0x44, 0x93, 0xc7, 0xf7, 0xff, 0xf5, 0x8f, 0x1c, 0xc3, 0x41, 0x01, 0x82, - 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x2a, 0x84, 0x93, 0x04, 0xa0, 0x0a, 0xef, 0x20, 0x10, 0x76, - 0x63, 0x19, 0x95, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x22, - 0x85, 0xef, 0x20, 0x90, 0x78, 0x22, 0x85, 0xef, 0x20, 0x30, 0x74, 0xe3, 0x03, 0x95, 0xfe, 0x37, 0x55, 0x10, 0x00, - 0x13, 0x05, 0x45, 0x3e, 0x85, 0x45, 0xef, 0x10, 0x10, 0x49, 0x13, 0x05, 0x50, 0x05, 0xd1, 0xbf, 0x01, 0x11, 0x22, - 0xcc, 0x2a, 0x84, 0x37, 0x35, 0x00, 0x08, 0x06, 0xce, 0x2e, 0xc6, 0xef, 0x30, 0x10, 0x0a, 0x32, 0x46, 0xa2, 0x85, - 0x37, 0x35, 0x00, 0x08, 0xef, 0x30, 0x50, 0x0e, 0x62, 0x44, 0xf2, 0x40, 0x37, 0x35, 0x00, 0x08, 0x05, 0x61, 0x6f, - 0x30, 0xb0, 0x0b, 0x6d, 0x71, 0x23, 0x24, 0x81, 0x10, 0x2a, 0x84, 0x0a, 0x85, 0x23, 0x26, 0x11, 0x10, 0xef, 0x10, - 0x50, 0x63, 0x0a, 0x85, 0x23, 0x00, 0x81, 0x00, 0xef, 0x20, 0xc0, 0x3e, 0x83, 0x20, 0xc1, 0x10, 0x03, 0x24, 0x81, - 0x10, 0x51, 0x61, 0x82, 0x80, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0x2e, 0xc4, 0xef, 0x20, 0xd0, 0x1a, 0xa2, 0x45, - 0x32, 0x45, 0xef, 0x20, 0xd0, 0x32, 0x2a, 0xc4, 0xef, 0x20, 0x90, 0x1b, 0xf2, 0x40, 0x22, 0x45, 0x05, 0x61, 0x82, - 0x80, 0x13, 0x01, 0x01, 0xde, 0x23, 0x2c, 0x81, 0x20, 0x2e, 0x84, 0xaa, 0x05, 0x23, 0x28, 0x21, 0x21, 0x93, 0x85, - 0x05, 0x20, 0x2a, 0x89, 0x08, 0x08, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x2a, 0x91, 0x20, 0x7d, 0x3f, 0x93, 0x07, 0xa0, - 0x0a, 0x63, 0x12, 0xf5, 0x04, 0xaa, 0x84, 0x08, 0x08, 0xcd, 0x33, 0x63, 0x00, 0x95, 0x02, 0x22, 0x85, 0xd1, 0x3d, - 0x09, 0x45, 0x83, 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, 0x41, 0x21, 0x03, 0x29, 0x01, 0x21, 0x13, - 0x01, 0x01, 0x22, 0x82, 0x80, 0x42, 0x44, 0x48, 0x08, 0x22, 0xc6, 0x25, 0x35, 0x09, 0x8c, 0x11, 0x46, 0x6c, 0x00, - 0x4a, 0x85, 0x22, 0xc6, 0xef, 0x40, 0x70, 0x7c, 0x05, 0x45, 0xc9, 0xbf, 0x01, 0x45, 0xf9, 0xb7, 0x41, 0x11, 0x4a, - 0xc0, 0x03, 0xa9, 0x05, 0x00, 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0x2e, 0x84, 0xaa, 0x84, 0xef, 0x20, 0x10, 0x67, - 0xca, 0x85, 0x26, 0x85, 0xef, 0x20, 0x70, 0x1e, 0xa6, 0x85, 0x22, 0x85, 0xef, 0x20, 0xb0, 0x28, 0x93, 0x07, 0xa0, - 0x0a, 0x63, 0x16, 0xf5, 0x02, 0x1c, 0x40, 0x63, 0x93, 0x27, 0x03, 0x93, 0x07, 0x44, 0x00, 0x7d, 0x57, 0x13, 0x04, - 0x04, 0x20, 0x94, 0x43, 0x63, 0x9b, 0xe6, 0x00, 0x91, 0x07, 0xe3, 0x9c, 0x87, 0xfe, 0xb2, 0x40, 0x22, 0x44, 0x92, - 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0xc5, 0xbf, 0x13, 0x01, 0x01, 0xde, 0x23, 0x26, - 0x31, 0x21, 0x93, 0x19, 0xa5, 0x00, 0x23, 0x2a, 0x91, 0x20, 0x93, 0x84, 0x09, 0x20, 0x23, 0x2c, 0x81, 0x20, 0xa6, - 0x85, 0x2a, 0x84, 0x0a, 0x85, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x28, 0x21, 0x21, 0xfd, 0x35, 0x93, 0x07, 0xa0, 0x0a, - 0x63, 0x00, 0xf5, 0x02, 0x01, 0x45, 0x83, 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, 0x41, 0x21, 0x03, - 0x29, 0x01, 0x21, 0x83, 0x29, 0xc1, 0x20, 0x13, 0x01, 0x01, 0x22, 0x82, 0x80, 0x2a, 0x89, 0x0a, 0x85, 0xdd, 0x39, - 0x63, 0x06, 0x25, 0x01, 0x22, 0x85, 0xe5, 0x33, 0x09, 0x45, 0xd9, 0xbf, 0x02, 0x44, 0x48, 0x00, 0x89, 0x3b, 0xaa, - 0x87, 0x33, 0x06, 0xa4, 0x40, 0x0d, 0x45, 0xe3, 0x03, 0xf4, 0xfc, 0x09, 0x45, 0xe3, 0x60, 0xc4, 0xfc, 0x5c, 0x00, - 0x01, 0x44, 0x13, 0x08, 0x00, 0x02, 0x13, 0x05, 0xf0, 0x07, 0x8c, 0x43, 0x89, 0xc9, 0x81, 0x46, 0x33, 0xd7, 0xd5, - 0x00, 0x05, 0x8b, 0x05, 0xeb, 0x85, 0x06, 0xe3, 0x9b, 0x06, 0xff, 0x05, 0x04, 0x91, 0x07, 0xe3, 0x14, 0xa4, 0xfe, - 0x7d, 0x16, 0x8a, 0x85, 0x13, 0x85, 0x09, 0x40, 0x32, 0xc0, 0xf5, 0x3d, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x11, 0xf5, - 0xf8, 0x8a, 0x85, 0x26, 0x85, 0xfd, 0x35, 0x13, 0x05, 0x65, 0xf5, 0x1d, 0xa8, 0x05, 0x47, 0x33, 0x17, 0xd7, 0x00, - 0x13, 0x47, 0xf7, 0xff, 0x6d, 0x8f, 0x98, 0xc3, 0xef, 0x20, 0xc0, 0x7f, 0x18, 0x04, 0x93, 0x17, 0x24, 0x00, 0xba, - 0x97, 0x83, 0xa5, 0x47, 0xe0, 0x13, 0x05, 0x14, 0x00, 0x0a, 0x05, 0x26, 0x95, 0xef, 0x20, 0x50, 0x10, 0x2a, 0x84, - 0xef, 0x20, 0x80, 0x7f, 0x13, 0x05, 0x64, 0xf5, 0x13, 0x35, 0x15, 0x00, 0x35, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x06, - 0xc6, 0x93, 0x07, 0x30, 0x0c, 0x2a, 0x84, 0x63, 0x04, 0xf5, 0x00, 0xef, 0x20, 0xc0, 0x4b, 0xb7, 0x07, 0x20, 0x00, - 0x93, 0x87, 0x07, 0x00, 0x05, 0x67, 0x23, 0x80, 0x87, 0x00, 0xba, 0x97, 0xf8, 0x5b, 0x19, 0xe3, 0x05, 0x47, 0xf8, - 0xdb, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x66, 0x37, 0x05, 0x20, 0x00, 0x41, 0x11, 0x13, 0x06, - 0xc6, 0x07, 0x81, 0x45, 0x13, 0x05, 0x05, 0x00, 0x06, 0xc6, 0xef, 0x40, 0xb0, 0x65, 0xef, 0x20, 0x80, 0x41, 0xef, - 0x40, 0x80, 0x39, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x20, 0x00, 0x38, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x20, 0x00, 0x55, - 0xef, 0x20, 0x90, 0x7f, 0xef, 0x40, 0xa0, 0x0c, 0xef, 0x40, 0x00, 0x65, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x30, 0xe0, - 0x15, 0x69, 0x71, 0x08, 0x08, 0x23, 0x22, 0x91, 0x12, 0x23, 0x20, 0x21, 0x13, 0x23, 0x2c, 0x41, 0x11, 0x23, 0x26, - 0x11, 0x12, 0x23, 0x24, 0x81, 0x12, 0x23, 0x2e, 0x31, 0x11, 0x23, 0x2a, 0x51, 0x11, 0xef, 0x10, 0xf0, 0x39, 0x91, - 0x47, 0x37, 0x39, 0x20, 0x00, 0x23, 0x08, 0xf1, 0x00, 0x83, 0x27, 0xc9, 0xf4, 0x37, 0x1a, 0x20, 0x00, 0xb7, 0x34, - 0x20, 0x00, 0x13, 0x09, 0xc9, 0xf4, 0x13, 0x0a, 0x0a, 0x00, 0x93, 0x84, 0x84, 0xf4, 0xc5, 0xe7, 0x83, 0x27, 0x4a, - 0x07, 0x09, 0x46, 0x6c, 0x00, 0x23, 0x20, 0xf9, 0x00, 0x13, 0x05, 0x21, 0x01, 0xc1, 0x17, 0x3e, 0xc6, 0x23, 0xa0, - 0x04, 0x00, 0xef, 0x40, 0xf0, 0x58, 0x89, 0x47, 0xa3, 0x08, 0xf1, 0x00, 0x13, 0x04, 0xe0, 0x07, 0x93, 0x09, 0x41, - 0x01, 0x03, 0x27, 0x09, 0x00, 0x94, 0x40, 0xb3, 0x07, 0xd7, 0x40, 0x63, 0xf3, 0x87, 0x00, 0x3e, 0x84, 0x37, 0x56, - 0x10, 0x00, 0xb7, 0x5a, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0xa2, 0x87, 0x93, 0x85, 0xca, 0x3f, 0x13, 0x06, 0xc6, - 0x3e, 0x13, 0x05, 0x45, 0x40, 0xef, 0x10, 0x50, 0x0c, 0x8c, 0x40, 0x83, 0x27, 0x4a, 0x07, 0x33, 0x07, 0xb4, 0x00, - 0x63, 0xf7, 0xe7, 0x04, 0x8d, 0x45, 0x13, 0x85, 0xca, 0x3f, 0xef, 0x10, 0x30, 0x12, 0x13, 0x04, 0x50, 0x05, 0xc5, - 0x3c, 0xef, 0x40, 0x60, 0x2a, 0xef, 0x20, 0xa0, 0x32, 0xef, 0x20, 0xa0, 0x29, 0x29, 0x3f, 0x83, 0x20, 0xc1, 0x12, - 0x22, 0x85, 0x03, 0x24, 0x81, 0x12, 0x83, 0x24, 0x41, 0x12, 0x03, 0x29, 0x01, 0x12, 0x83, 0x29, 0xc1, 0x11, 0x03, - 0x2a, 0x81, 0x11, 0x83, 0x2a, 0x41, 0x11, 0x55, 0x61, 0x82, 0x80, 0x13, 0x04, 0x00, 0x08, 0x93, 0x09, 0x21, 0x01, - 0xb5, 0xbf, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x22, 0x86, 0xbe, 0x95, 0x4e, 0x85, 0xef, 0x40, 0x90, - 0x4e, 0x83, 0x47, 0x11, 0x01, 0x98, 0x40, 0x22, 0x97, 0x3e, 0x94, 0x83, 0x27, 0x09, 0x00, 0xa3, 0x08, 0x81, 0x00, - 0x98, 0xc0, 0x13, 0x04, 0x50, 0x05, 0x63, 0x17, 0xf7, 0x00, 0x89, 0x47, 0x23, 0x08, 0xf1, 0x00, 0x13, 0x04, 0xa0, - 0x0a, 0x08, 0x08, 0xef, 0x20, 0xe0, 0x04, 0x59, 0xbf, 0x41, 0x11, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, - 0x06, 0xc6, 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x20, 0xe0, 0x26, 0x85, 0x3d, 0xb9, 0x3c, 0xef, 0x30, 0x20, 0x07, 0x41, - 0x3d, 0xb2, 0x40, 0x1d, 0x65, 0x13, 0x05, 0x05, 0x6c, 0x41, 0x01, 0x6f, 0x30, 0x00, 0x0f, 0x41, 0x11, 0x26, 0xc2, - 0xae, 0x84, 0xb6, 0x85, 0x06, 0xc6, 0x22, 0xc4, 0x4a, 0xc0, 0x36, 0x84, 0x32, 0x89, 0xef, 0x40, 0x40, 0x4f, 0x22, - 0x86, 0xca, 0x85, 0x13, 0x05, 0x00, 0x02, 0xef, 0x40, 0x00, 0x58, 0xef, 0x40, 0x60, 0x4c, 0xef, 0x40, 0xe0, 0x67, - 0x93, 0x07, 0xa0, 0x0a, 0x13, 0x04, 0x50, 0x05, 0x63, 0x1a, 0xf5, 0x00, 0x2a, 0x84, 0x13, 0x06, 0x00, 0x02, 0x93, - 0x05, 0x00, 0x02, 0x26, 0x85, 0xef, 0x40, 0xe0, 0x50, 0xb2, 0x40, 0x22, 0x85, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, - 0x41, 0x01, 0x82, 0x80, 0x85, 0x67, 0xc1, 0x07, 0x63, 0xee, 0xb7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, - 0xc6, 0xae, 0x84, 0x37, 0x04, 0x20, 0x00, 0x19, 0xc5, 0x2e, 0x86, 0xaa, 0x85, 0x13, 0x05, 0x04, 0x00, 0xef, 0x40, - 0xd0, 0x42, 0x13, 0x04, 0x04, 0x00, 0x93, 0x07, 0x30, 0xfc, 0x23, 0x00, 0xf4, 0x00, 0x85, 0x67, 0x3e, 0x94, 0x64, - 0xd8, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x82, 0x80, 0x13, 0x01, 0x01, 0xdd, 0x23, 0x24, - 0x81, 0x22, 0x23, 0x22, 0x91, 0x22, 0x23, 0x20, 0x21, 0x23, 0x23, 0x2e, 0x31, 0x21, 0x23, 0x2c, 0x41, 0x21, 0x23, - 0x2a, 0x51, 0x21, 0x23, 0x28, 0x61, 0x21, 0x23, 0x26, 0x71, 0x21, 0x23, 0x24, 0x81, 0x21, 0x23, 0x26, 0x11, 0x22, - 0x13, 0x04, 0x00, 0x20, 0x01, 0x49, 0x93, 0x04, 0xa0, 0x0a, 0x37, 0x3a, 0x20, 0x00, 0x85, 0x4a, 0x37, 0x5b, 0x10, - 0x00, 0xb7, 0x5b, 0x10, 0x00, 0x37, 0x5c, 0x10, 0x00, 0xc1, 0x49, 0xa2, 0x85, 0x0a, 0x85, 0xb1, 0x3e, 0x63, 0x16, - 0x95, 0x02, 0x0a, 0x85, 0x59, 0x32, 0x63, 0x1e, 0x95, 0x04, 0x13, 0x07, 0x4a, 0xf5, 0x14, 0x43, 0xb3, 0x97, 0x2a, - 0x01, 0x13, 0x06, 0x8b, 0x40, 0xd5, 0x8f, 0x93, 0x85, 0x4b, 0x3e, 0xca, 0x86, 0x13, 0x05, 0x4c, 0x64, 0x1c, 0xc3, - 0xef, 0x10, 0xe0, 0x6e, 0x05, 0x09, 0x13, 0x04, 0x04, 0x40, 0xe3, 0x14, 0x39, 0xfd, 0x83, 0x20, 0xc1, 0x22, 0x03, - 0x24, 0x81, 0x22, 0x83, 0x24, 0x41, 0x22, 0x03, 0x29, 0x01, 0x22, 0x83, 0x29, 0xc1, 0x21, 0x03, 0x2a, 0x81, 0x21, - 0x83, 0x2a, 0x41, 0x21, 0x03, 0x2b, 0x01, 0x21, 0x83, 0x2b, 0xc1, 0x20, 0x03, 0x2c, 0x81, 0x20, 0x13, 0x01, 0x01, - 0x23, 0x82, 0x80, 0x93, 0x05, 0x04, 0x20, 0x0a, 0x85, 0xc5, 0x3c, 0xe3, 0x10, 0x95, 0xfc, 0x0a, 0x85, 0xef, 0xf0, - 0xbf, 0x91, 0xe3, 0x1b, 0x95, 0xfa, 0x22, 0x85, 0xef, 0x20, 0x10, 0x1f, 0x8a, 0x85, 0x22, 0x85, 0xef, 0x20, 0x70, - 0x06, 0xa2, 0x85, 0x0a, 0x85, 0xf9, 0x34, 0xe3, 0x1f, 0x95, 0xf8, 0x0a, 0x85, 0xef, 0xf0, 0x9f, 0x8f, 0xe3, 0x0a, - 0x95, 0xf6, 0x41, 0xbf, 0xb7, 0x05, 0x00, 0x80, 0x37, 0x55, 0x10, 0x00, 0x86, 0x87, 0x6d, 0x71, 0xbe, 0x95, 0x13, - 0x05, 0x45, 0x41, 0x23, 0x26, 0x11, 0x10, 0xef, 0x10, 0x80, 0x6d, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x87, 0xf2, - 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x1e, 0xf7, 0x02, 0x37, 0x15, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x9a, 0xef, 0x10, 0xf0, - 0x5f, 0x13, 0x05, 0xc0, 0x0f, 0xef, 0x10, 0xa0, 0x5a, 0x0a, 0x85, 0xef, 0x10, 0x70, 0x09, 0x93, 0x07, 0xf0, 0x07, - 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x00, 0x23, 0x00, 0xf1, 0x00, 0xef, 0x10, 0x00, 0x54, 0xa3, 0x00, 0xa1, - 0x00, 0x0a, 0x85, 0xef, 0x10, 0x70, 0x60, 0x05, 0x45, 0xef, 0x40, 0x00, 0x67, 0xef, 0x40, 0x00, 0x66, 0xd5, 0x33, - 0xef, 0x10, 0x50, 0x2d, 0xf5, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0x40, 0x60, 0x4c, 0x93, 0x07, 0x00, - 0x08, 0x63, 0xf3, 0xa7, 0x00, 0xad, 0x3f, 0x2a, 0x84, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0x50, 0x7e, 0xb7, 0x17, - 0x20, 0x00, 0xb2, 0x40, 0x23, 0xaa, 0x87, 0x06, 0x22, 0x44, 0x13, 0x05, 0x30, 0x0c, 0x41, 0x01, 0x82, 0x80, 0x93, - 0x07, 0xf0, 0x17, 0x63, 0xf5, 0xa7, 0x00, 0x41, 0x11, 0x06, 0xc6, 0xb9, 0x37, 0x6f, 0x10, 0xb0, 0x3e, 0x41, 0x11, - 0x22, 0xc4, 0x26, 0xc2, 0x4a, 0xc0, 0x2e, 0x84, 0x06, 0xc6, 0xaa, 0x84, 0xc5, 0x37, 0x61, 0x8d, 0x13, 0x09, 0x50, - 0x05, 0x19, 0xc1, 0x13, 0x09, 0xa0, 0x0a, 0x26, 0x85, 0xc1, 0x3f, 0x69, 0x8c, 0x13, 0x05, 0xa0, 0x0a, 0x19, 0xe0, - 0x13, 0x05, 0x50, 0x05, 0x63, 0x03, 0x25, 0x01, 0x21, 0x3f, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, - 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x8d, 0x47, 0x63, 0xf3, 0xa7, 0x00, 0x01, 0x37, 0x89, 0x67, 0x93, 0x87, - 0x07, 0xbf, 0x0a, 0x05, 0x3e, 0x95, 0xef, 0x30, 0xe0, 0x02, 0xaa, 0x87, 0x13, 0x07, 0xf0, 0x0f, 0x55, 0x45, 0x63, - 0x89, 0xe7, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x59, 0x45, 0x63, 0x94, 0xe7, 0x00, 0x13, 0x05, 0x30, 0x0c, 0xb2, 0x40, - 0x41, 0x01, 0x82, 0x80, 0x21, 0x71, 0x23, 0x2c, 0x81, 0x1a, 0x2a, 0x84, 0x08, 0x09, 0x23, 0x2e, 0x11, 0x1a, 0x23, - 0x2a, 0x91, 0x1a, 0x23, 0x28, 0x21, 0x1b, 0x23, 0x26, 0x31, 0x1b, 0x23, 0x24, 0x41, 0x1b, 0x23, 0x22, 0x51, 0x1b, - 0x23, 0x20, 0x61, 0x1b, 0x23, 0x2e, 0x71, 0x19, 0x23, 0x2c, 0x81, 0x19, 0x23, 0x2a, 0x91, 0x19, 0xef, 0x10, 0x40, - 0x77, 0x83, 0x47, 0x04, 0x00, 0x05, 0x47, 0x23, 0x18, 0xe1, 0x08, 0xc1, 0x46, 0x63, 0x80, 0xd7, 0x46, 0x63, 0xee, - 0xf6, 0x02, 0x91, 0x46, 0x63, 0x88, 0xd7, 0x34, 0x63, 0xe1, 0xf6, 0x02, 0x63, 0x86, 0xe7, 0x06, 0x09, 0x47, 0x63, - 0x81, 0xe7, 0x0e, 0x93, 0x07, 0xe0, 0x07, 0x23, 0x08, 0xf1, 0x08, 0x08, 0x09, 0xef, 0x10, 0xd0, 0x4c, 0x93, 0x07, - 0x50, 0x05, 0x99, 0xa1, 0x21, 0x47, 0xe3, 0x95, 0xe7, 0xfe, 0x83, 0x47, 0x14, 0x00, 0xd1, 0xeb, 0x4d, 0x31, 0x39, - 0xa9, 0x93, 0x06, 0x20, 0x0a, 0x63, 0x85, 0xd7, 0x4c, 0x93, 0x06, 0x30, 0x0b, 0x63, 0x82, 0xd7, 0x46, 0x93, 0x06, - 0x00, 0x02, 0xe3, 0x94, 0xd7, 0xfc, 0x83, 0x47, 0x14, 0x00, 0x63, 0x99, 0xe7, 0x06, 0x03, 0x47, 0x24, 0x00, 0x95, - 0x47, 0x63, 0x14, 0xf7, 0x06, 0x85, 0x45, 0x61, 0x45, 0xe1, 0x3d, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x09, 0xf5, 0x42, - 0x13, 0x04, 0x80, 0xf8, 0x7d, 0xa0, 0x03, 0x47, 0x14, 0x00, 0x89, 0x47, 0x63, 0x15, 0xf7, 0x04, 0x83, 0x47, 0x24, - 0x00, 0x63, 0x8a, 0xe7, 0x04, 0x63, 0x6b, 0xf7, 0x02, 0xa1, 0xe3, 0x83, 0x45, 0x34, 0x00, 0xf5, 0x47, 0x63, 0xe9, - 0xb7, 0x02, 0x9e, 0x05, 0x13, 0x06, 0x00, 0x08, 0x93, 0x85, 0x05, 0x10, 0x13, 0x05, 0x21, 0x09, 0xef, 0x20, 0x30, - 0x6d, 0x13, 0x04, 0x00, 0x08, 0x08, 0x09, 0xa3, 0x08, 0x81, 0x08, 0xef, 0x10, 0x70, 0x43, 0x93, 0x07, 0xa0, 0x0a, - 0x45, 0xae, 0x13, 0x05, 0x80, 0x1e, 0x63, 0x8d, 0xd7, 0x00, 0x13, 0x04, 0x10, 0xf8, 0xa1, 0xa8, 0x89, 0x65, 0x13, - 0x06, 0x00, 0x08, 0x93, 0x85, 0x05, 0x90, 0xf1, 0xb7, 0x13, 0x05, 0x00, 0x1f, 0xef, 0x10, 0x90, 0x24, 0x2a, 0xc6, - 0x11, 0x46, 0x6c, 0x00, 0x13, 0x05, 0x21, 0x09, 0xef, 0x40, 0x30, 0x0a, 0x11, 0x44, 0x7d, 0xbf, 0x83, 0x44, 0x14, - 0x00, 0xc5, 0x36, 0x93, 0x07, 0x10, 0x02, 0xe3, 0x95, 0xf4, 0xfc, 0xef, 0x10, 0x10, 0x7d, 0xef, 0x20, 0x90, 0x27, - 0xef, 0x30, 0x90, 0x38, 0xef, 0x40, 0x60, 0x07, 0x03, 0x45, 0x24, 0x02, 0xa5, 0x35, 0x93, 0x07, 0x30, 0x0c, 0x63, - 0x0b, 0xf5, 0x02, 0x13, 0x04, 0x70, 0xf8, 0xb3, 0x06, 0x80, 0x40, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, - 0x37, 0x55, 0x10, 0x00, 0x93, 0xf6, 0xf6, 0x0f, 0x13, 0x06, 0x86, 0x42, 0x93, 0x85, 0x45, 0x41, 0x13, 0x05, 0x45, - 0x64, 0x23, 0x08, 0xd1, 0x08, 0xef, 0x10, 0x80, 0x3b, 0xa3, 0x08, 0x01, 0x08, 0xf9, 0xb5, 0x83, 0x44, 0x24, 0x02, - 0x19, 0x34, 0x8d, 0x47, 0xe3, 0xe3, 0x97, 0xfc, 0x13, 0x06, 0x10, 0x08, 0x81, 0x45, 0x68, 0x00, 0xef, 0x40, 0x50, - 0x06, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0x24, 0x00, 0x13, 0x05, 0xd1, 0x00, 0x23, 0x06, 0x91, 0x00, 0xef, 0x40, - 0x50, 0x01, 0xef, 0x40, 0x60, 0x00, 0x37, 0x25, 0x00, 0x08, 0xef, 0x30, 0x80, 0x01, 0x81, 0x46, 0x01, 0x46, 0x93, - 0x05, 0xd1, 0x02, 0x45, 0x45, 0x85, 0x3e, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x13, 0xf5, 0xf8, 0x81, 0x45, 0x68, 0x00, - 0xef, 0x30, 0x50, 0x2f, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0xe3, 0x1a, 0xf5, 0xf6, 0x93, 0x06, 0x00, 0x02, 0x13, - 0x06, 0xd1, 0x00, 0x93, 0x05, 0xd1, 0x04, 0x49, 0x45, 0x99, 0x36, 0xaa, 0x84, 0xe3, 0x1f, 0x25, 0xf5, 0x85, 0x45, - 0x68, 0x00, 0xef, 0x30, 0xd0, 0x2c, 0x2a, 0x89, 0xe3, 0x18, 0x95, 0xf4, 0x83, 0x47, 0xc1, 0x00, 0x85, 0x46, 0x13, - 0x06, 0xb1, 0x00, 0x93, 0x05, 0xd1, 0x04, 0x4d, 0x45, 0xa3, 0x05, 0xf1, 0x00, 0x31, 0x3e, 0xaa, 0x84, 0xe3, 0x1a, - 0x25, 0xf3, 0x89, 0x45, 0x68, 0x00, 0xef, 0x30, 0x30, 0x2a, 0x2a, 0x89, 0xe3, 0x13, 0x95, 0xf2, 0x81, 0x46, 0x01, - 0x46, 0x93, 0x05, 0xd1, 0x04, 0x51, 0x45, 0xf5, 0x3c, 0xaa, 0x84, 0xe3, 0x1a, 0x25, 0xf1, 0x8d, 0x45, 0x68, 0x00, - 0xef, 0x30, 0x30, 0x28, 0x2a, 0x89, 0xe3, 0x13, 0x95, 0xf0, 0x91, 0x45, 0x68, 0x00, 0xef, 0x30, 0x50, 0x27, 0xaa, - 0x84, 0xe3, 0x1c, 0x25, 0xef, 0x95, 0x45, 0x68, 0x00, 0xef, 0x30, 0x70, 0x26, 0xe3, 0x16, 0x95, 0xee, 0xb7, 0x19, - 0x20, 0x00, 0x13, 0x85, 0x09, 0x02, 0xef, 0x30, 0x70, 0x29, 0xb7, 0x14, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, - 0x05, 0xd1, 0x02, 0x13, 0x85, 0x04, 0x03, 0xef, 0x40, 0xa0, 0x73, 0x37, 0x15, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, - 0x93, 0x05, 0xd1, 0x06, 0x13, 0x05, 0x05, 0x05, 0xef, 0x40, 0x60, 0x72, 0x03, 0x49, 0x24, 0x02, 0x8d, 0x47, 0x4e, - 0x84, 0x63, 0xf3, 0x27, 0x01, 0x01, 0x39, 0x37, 0x5c, 0x10, 0x00, 0xef, 0x10, 0x10, 0x49, 0x81, 0x4c, 0x13, 0x0c, - 0x8c, 0x58, 0x8d, 0x49, 0xfd, 0x5a, 0x13, 0x0a, 0x00, 0x0f, 0x41, 0x6b, 0xb7, 0x0b, 0x00, 0x01, 0x03, 0x25, 0x0c, - 0x00, 0x51, 0x81, 0x49, 0x39, 0x03, 0x27, 0x0c, 0x00, 0x93, 0x57, 0x07, 0x01, 0xbd, 0x8b, 0x63, 0xe8, 0xf9, 0x00, - 0x8e, 0x07, 0xb3, 0x97, 0xfa, 0x00, 0x93, 0xc7, 0xf7, 0xff, 0x7d, 0x8d, 0x83, 0x46, 0x1c, 0x00, 0x33, 0x55, 0x25, - 0x01, 0x93, 0x77, 0x15, 0x00, 0x93, 0xf6, 0x06, 0x0f, 0x63, 0x96, 0x46, 0x07, 0x99, 0xc3, 0x93, 0x07, 0xf0, 0x0f, - 0xbd, 0x65, 0xf9, 0x8d, 0x21, 0x83, 0x3d, 0x8b, 0x22, 0x07, 0x4d, 0x8f, 0x83, 0x45, 0x0c, 0x00, 0xc2, 0x07, 0x66, - 0x85, 0xd9, 0x8d, 0xdd, 0x8d, 0xef, 0x10, 0xd0, 0x43, 0x83, 0x47, 0x4c, 0x00, 0x11, 0x0c, 0x85, 0x0c, 0xc5, 0xf3, - 0xef, 0x10, 0x90, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x04, - 0x03, 0x13, 0x05, 0x21, 0x09, 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x40, 0xa0, 0x67, 0x93, 0x05, 0x04, 0x02, 0x41, 0x46, - 0x13, 0x05, 0x21, 0x0b, 0xef, 0x40, 0xc0, 0x66, 0xef, 0x30, 0xf0, 0x6b, 0x13, 0x04, 0x00, 0x03, 0xef, 0xf0, 0x7f, - 0x85, 0xbd, 0xbb, 0x93, 0x76, 0x05, 0x10, 0x99, 0xc2, 0x93, 0xe7, 0x27, 0x00, 0xb3, 0x76, 0x65, 0x01, 0x99, 0xc2, - 0x93, 0xe7, 0x47, 0x00, 0x33, 0x75, 0x75, 0x01, 0x59, 0xd1, 0x93, 0xe7, 0x87, 0x00, 0x41, 0xb7, 0xb7, 0x37, 0x20, - 0x00, 0x03, 0xa7, 0xc7, 0xf3, 0x93, 0x07, 0xa0, 0x0a, 0x83, 0x44, 0x14, 0x00, 0x63, 0x14, 0xf7, 0x0e, 0x91, 0xe4, - 0x13, 0x04, 0x10, 0xf8, 0xef, 0xf0, 0xbf, 0x96, 0x4d, 0xbb, 0xb7, 0x39, 0x20, 0x00, 0x83, 0xa7, 0x89, 0xf3, 0x93, - 0x89, 0x89, 0xf3, 0xad, 0xcb, 0x09, 0x04, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x49, 0xf3, 0x83, 0x26, 0x09, 0x00, - 0x03, 0xa7, 0x09, 0x00, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, - 0x64, 0xa6, 0x96, 0x13, 0x06, 0xc6, 0x41, 0x93, 0x85, 0xc5, 0x3f, 0xef, 0x10, 0x20, 0x15, 0x03, 0x25, 0x09, 0x00, - 0x83, 0xa7, 0x09, 0x00, 0x33, 0x87, 0xa4, 0x00, 0xe3, 0xe6, 0xe7, 0xfa, 0x85, 0x67, 0x93, 0x87, 0x07, 0x02, 0xe3, - 0xe1, 0xe7, 0xfa, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x26, 0x86, 0x3e, 0x95, 0xa2, 0x85, 0xef, 0x40, - 0x40, 0x5b, 0x83, 0x27, 0x09, 0x00, 0xbe, 0x94, 0x83, 0xa7, 0x09, 0x00, 0x23, 0x20, 0x99, 0x00, 0xbd, 0xe3, 0x75, - 0x54, 0x15, 0xbb, 0x89, 0x47, 0xe3, 0xfb, 0x97, 0xf6, 0x03, 0x49, 0x34, 0x00, 0x83, 0x47, 0x24, 0x00, 0xf9, 0x14, - 0x22, 0x09, 0x3e, 0x99, 0x85, 0x67, 0x93, 0x06, 0xf9, 0xff, 0x13, 0x87, 0xf7, 0x00, 0x11, 0x04, 0xe3, 0x6c, 0xd7, - 0xf4, 0x37, 0x0a, 0x20, 0x00, 0x13, 0x0a, 0x0a, 0x00, 0x3e, 0x9a, 0x41, 0x09, 0x93, 0x07, 0xf0, 0x07, 0xa3, 0x0c, - 0xfa, 0x06, 0x23, 0xa0, 0x29, 0x01, 0xef, 0x10, 0x50, 0x4a, 0xef, 0x20, 0xc0, 0x74, 0xef, 0x30, 0xd0, 0x05, 0xb7, - 0x37, 0x20, 0x00, 0x23, 0x28, 0x2a, 0x07, 0x23, 0x2a, 0x0a, 0x06, 0x23, 0xaa, 0x07, 0xf2, 0x2d, 0xbf, 0x13, 0x04, - 0x60, 0xf8, 0x39, 0xbf, 0xe3, 0x9e, 0xf4, 0xf8, 0x01, 0x44, 0xa1, 0xb9, 0x83, 0x47, 0x14, 0x00, 0xe3, 0x95, 0x07, - 0xc6, 0xef, 0x10, 0x30, 0x15, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x0f, 0x05, 0xc4, 0x83, 0x20, 0xc1, 0x1b, 0x03, 0x24, - 0x81, 0x1b, 0x83, 0x24, 0x41, 0x1b, 0x03, 0x29, 0x01, 0x1b, 0x83, 0x29, 0xc1, 0x1a, 0x03, 0x2a, 0x81, 0x1a, 0x83, - 0x2a, 0x41, 0x1a, 0x03, 0x2b, 0x01, 0x1a, 0x83, 0x2b, 0xc1, 0x19, 0x03, 0x2c, 0x81, 0x19, 0x83, 0x2c, 0x41, 0x19, - 0x3e, 0x85, 0x39, 0x61, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa2, 0xa7, 0xf4, 0x7d, 0xb7, 0x83, 0x46, 0x14, - 0x00, 0xe3, 0x9d, 0xe6, 0xc0, 0x83, 0x47, 0x24, 0x00, 0x63, 0x8a, 0xd7, 0x02, 0x0d, 0x47, 0xe3, 0x96, 0xe7, 0xc0, - 0xa1, 0x45, 0x01, 0x45, 0xb5, 0x3c, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0xe3, 0x13, 0xf5, 0xba, 0xb7, 0xb5, 0xb5, - 0x61, 0x93, 0x85, 0x55, 0x49, 0x13, 0x05, 0x80, 0x1f, 0xef, 0x10, 0x40, 0x6b, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa6, - 0x87, 0xf2, 0xbd, 0xb7, 0xb7, 0x15, 0x78, 0x4a, 0x93, 0x85, 0x95, 0x21, 0x13, 0x05, 0x80, 0x1f, 0xef, 0x10, 0xa0, - 0x69, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf2, 0x81, 0xbf, 0xb7, 0x37, 0x20, 0x00, - 0x03, 0xa7, 0x87, 0xf2, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1f, 0xf7, 0xb4, 0x83, 0x47, 0x14, 0x00, 0xe3, 0x96, 0x07, - 0xba, 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x09, 0xef, 0x00, 0x50, 0x6f, 0x2a, 0x84, 0xe3, 0x51, 0x05, 0xb8, - 0xcd, 0xbe, 0x41, 0x11, 0x05, 0x45, 0x06, 0xc6, 0xef, 0x40, 0x20, 0x02, 0xb2, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x13, - 0x07, 0xa0, 0x0a, 0x23, 0xa0, 0xe7, 0xf4, 0x41, 0x01, 0x82, 0x80, 0x31, 0x71, 0x22, 0xdd, 0x37, 0x34, 0x20, 0x00, - 0x93, 0x07, 0x50, 0x05, 0x06, 0xdf, 0x4a, 0xd9, 0x52, 0xd5, 0x56, 0xd3, 0x62, 0xcd, 0x26, 0xdb, 0x4e, 0xd7, 0x5a, - 0xd1, 0x5e, 0xcf, 0x66, 0xcb, 0x6a, 0xc9, 0x6e, 0xc7, 0xb7, 0x3a, 0x20, 0x00, 0x37, 0x3a, 0x20, 0x00, 0x37, 0x39, - 0x20, 0x00, 0x13, 0x04, 0x84, 0xf2, 0x23, 0xa0, 0xfa, 0xf4, 0x23, 0x26, 0xfa, 0xf2, 0x23, 0x22, 0xf9, 0xf4, 0x1c, - 0xc0, 0xef, 0x10, 0x60, 0x3d, 0xef, 0x10, 0xc0, 0x55, 0x13, 0x87, 0x0a, 0xf4, 0x3a, 0xc8, 0x13, 0x07, 0xca, 0xf2, - 0x3a, 0xca, 0x13, 0x07, 0x49, 0xf4, 0x93, 0x07, 0xa0, 0x0a, 0x3a, 0xc6, 0x37, 0x5c, 0x10, 0x00, 0x85, 0x45, 0x63, - 0x0a, 0xf5, 0x00, 0x13, 0x05, 0x4c, 0x41, 0xef, 0x00, 0x90, 0x7b, 0xef, 0x10, 0x80, 0x4f, 0xef, 0xf0, 0x3f, 0x8c, - 0x41, 0x45, 0xef, 0xf0, 0x5f, 0x97, 0x08, 0xc0, 0xb7, 0x07, 0x01, 0x02, 0x80, 0x57, 0x98, 0x5b, 0x29, 0x45, 0x59, - 0x8c, 0x98, 0x5f, 0x59, 0x8c, 0x13, 0x77, 0xf4, 0x87, 0x98, 0xd7, 0x98, 0xdb, 0x98, 0xdf, 0xd8, 0x43, 0x13, 0x67, - 0x87, 0x00, 0xd8, 0xc3, 0xef, 0x10, 0x00, 0x38, 0xef, 0x30, 0x30, 0x22, 0x13, 0x75, 0x05, 0x78, 0x11, 0xc5, 0x13, - 0x05, 0x00, 0x78, 0x81, 0x45, 0xef, 0x30, 0x90, 0x1a, 0xb7, 0x07, 0x01, 0x02, 0x80, 0xd7, 0x80, 0xdb, 0x37, 0x15, - 0x10, 0x00, 0x80, 0xdf, 0x13, 0x05, 0xc5, 0x9a, 0xef, 0x10, 0xa0, 0x69, 0x37, 0x56, 0x10, 0x00, 0x37, 0x59, 0x10, - 0x00, 0x81, 0x47, 0x01, 0x47, 0x85, 0x46, 0x13, 0x06, 0x06, 0x43, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, 0x64, - 0xef, 0x00, 0x50, 0x6c, 0xef, 0x30, 0x50, 0x1e, 0x93, 0x07, 0x50, 0x05, 0x63, 0x1e, 0xf5, 0x00, 0x37, 0x56, 0x10, - 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x46, 0x44, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x45, 0x40, 0xef, 0x00, - 0x10, 0x6a, 0xef, 0x20, 0xa0, 0x2f, 0x51, 0x45, 0xef, 0x10, 0xc0, 0x4b, 0x1d, 0x89, 0xef, 0x20, 0xc0, 0x2f, 0xef, - 0x20, 0xa0, 0x03, 0xef, 0x20, 0x10, 0x03, 0xef, 0x20, 0x30, 0x31, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0xb0, 0x31, - 0x11, 0x46, 0x6c, 0x10, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0xf0, 0x35, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0xb0, - 0x33, 0x32, 0x55, 0xc1, 0x7a, 0x37, 0x0b, 0x01, 0xff, 0xb7, 0x0b, 0x00, 0x01, 0xef, 0x20, 0x70, 0x22, 0x05, 0x64, - 0x01, 0x4a, 0x93, 0x8a, 0xfa, 0x0f, 0x7d, 0x1b, 0xfd, 0x1b, 0x13, 0x0d, 0x00, 0x18, 0x52, 0x85, 0xef, 0xf0, 0x1f, - 0x87, 0xaa, 0x8c, 0x22, 0x85, 0xef, 0x20, 0xd0, 0x0f, 0x93, 0xf9, 0x09, 0xf0, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, - 0x44, 0x00, 0xef, 0x20, 0xd0, 0x0e, 0x22, 0x05, 0xb3, 0xf9, 0x59, 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, 0x84, - 0x00, 0xef, 0x20, 0xb0, 0x0d, 0x42, 0x05, 0xb3, 0xf9, 0x69, 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, 0xc4, 0x00, - 0xef, 0x20, 0x90, 0x0c, 0x62, 0x05, 0xb3, 0xf9, 0x79, 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x93, 0xc7, 0xf9, 0xff, 0x33, - 0xf5, 0x97, 0x01, 0xe3, 0x1b, 0x05, 0xea, 0x11, 0x0a, 0x41, 0x04, 0xe3, 0x12, 0xaa, 0xfb, 0x37, 0x55, 0x10, 0x00, - 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x13, 0x05, 0x85, 0x5e, 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x10, 0xf0, - 0x1a, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x40, 0x05, 0x93, 0x85, 0x45, 0x53, 0x68, 0x10, 0xef, 0x40, 0xc0, 0x24, - 0x60, 0x10, 0x48, 0x40, 0x01, 0xc5, 0xef, 0x20, 0xa0, 0x7f, 0x48, 0xc0, 0x31, 0x04, 0x1c, 0x01, 0xe3, 0x99, 0x87, - 0xfe, 0x37, 0x55, 0x10, 0x00, 0x1d, 0x46, 0x6c, 0x10, 0x13, 0x05, 0xc5, 0x5f, 0xef, 0x20, 0x40, 0x42, 0xef, 0xf0, - 0x0f, 0xe3, 0x05, 0x45, 0xef, 0x10, 0xd0, 0x02, 0xef, 0x30, 0xa0, 0x4e, 0xef, 0x30, 0x50, 0x21, 0x01, 0x45, 0xef, - 0x30, 0xf0, 0x5d, 0xb7, 0x0a, 0x20, 0x00, 0x93, 0x87, 0x0a, 0x00, 0x05, 0x6b, 0xb3, 0x8b, 0x67, 0x01, 0xb7, 0x17, - 0x20, 0x00, 0x13, 0x8a, 0xc7, 0x07, 0xef, 0x10, 0x40, 0x66, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x87, 0xf3, 0x63, - 0x82, 0x07, 0x10, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0x47, 0xf3, 0x63, 0x9c, 0xe7, 0x0e, 0xb7, 0x37, 0x20, 0x00, - 0x03, 0xc7, 0x07, 0xf3, 0x93, 0x87, 0x07, 0xf3, 0x3e, 0xcc, 0xe3, 0x1d, 0x07, 0x36, 0x03, 0xa6, 0x0b, 0x07, 0x93, - 0x07, 0xf0, 0x07, 0xb7, 0x19, 0x20, 0x00, 0xa3, 0x8c, 0xfb, 0x06, 0xc1, 0x4c, 0x13, 0x8d, 0x0a, 0x00, 0x93, 0x89, - 0x09, 0x00, 0x63, 0xfe, 0xcc, 0x0a, 0x13, 0x04, 0x06, 0xff, 0xef, 0x10, 0x60, 0x72, 0x01, 0x45, 0xef, 0x30, 0x60, - 0x4f, 0x22, 0x86, 0x63, 0xf3, 0x8c, 0x00, 0x41, 0x46, 0x93, 0x85, 0x0a, 0x00, 0x68, 0x10, 0xef, 0x30, 0x20, 0x50, - 0xef, 0x10, 0xc0, 0x77, 0xb7, 0x57, 0x10, 0x00, 0x23, 0x8c, 0xa9, 0x06, 0x93, 0x87, 0x87, 0x58, 0x03, 0xc7, 0x07, - 0x00, 0x63, 0x1b, 0x07, 0x12, 0x03, 0xa4, 0x09, 0x07, 0xc1, 0x47, 0xe3, 0xf2, 0x87, 0xda, 0x01, 0x45, 0xef, 0x30, - 0xc0, 0x4b, 0x41, 0x14, 0x22, 0x86, 0x93, 0x85, 0x0a, 0x00, 0x13, 0x85, 0x0a, 0x00, 0xef, 0x30, 0xa0, 0x4c, 0xb7, - 0x1c, 0x20, 0x00, 0x13, 0x85, 0x0c, 0x02, 0xef, 0x30, 0xa0, 0x68, 0xef, 0x30, 0x20, 0x6d, 0x37, 0x56, 0x10, 0x00, - 0xb7, 0x5d, 0x10, 0x00, 0xaa, 0x86, 0x13, 0x06, 0x46, 0x45, 0x93, 0x85, 0xcd, 0x3d, 0x13, 0x05, 0x49, 0x64, 0xef, - 0x00, 0xf0, 0x49, 0x93, 0x85, 0x0c, 0x02, 0x41, 0x46, 0x33, 0x05, 0x8d, 0x00, 0xef, 0x00, 0x30, 0x38, 0xaa, 0x8c, - 0xc1, 0x47, 0x63, 0x09, 0x05, 0x0e, 0x89, 0x45, 0x13, 0x85, 0xcd, 0x3d, 0xef, 0x00, 0x50, 0x4f, 0x37, 0x55, 0x10, - 0x00, 0x93, 0x07, 0xb0, 0x07, 0x91, 0x45, 0x13, 0x05, 0xc5, 0x3f, 0xa3, 0x8c, 0xf9, 0x06, 0xef, 0x00, 0xf0, 0x4d, - 0xef, 0xe0, 0x9f, 0xf7, 0xef, 0xf0, 0xcf, 0x87, 0xef, 0xf0, 0x4f, 0xc3, 0xef, 0x10, 0xa0, 0x53, 0x93, 0x07, 0xa0, - 0x0a, 0x2a, 0x84, 0x63, 0x17, 0xf5, 0x08, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xc7, 0x07, 0xf3, 0xc9, 0xe3, 0xef, 0x10, - 0xa0, 0x02, 0xe3, 0x15, 0x85, 0x20, 0xd2, 0x47, 0x9c, 0x43, 0x63, 0x94, 0xa7, 0x00, 0xef, 0x10, 0xc0, 0x18, 0xb2, - 0x47, 0x98, 0x43, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x13, 0xf7, 0x1e, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0x86, 0x4d, - 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x10, 0x41, 0xef, 0xf0, 0x4f, 0xbe, 0x37, 0x25, 0x00, - 0x08, 0xef, 0x20, 0x70, 0x0d, 0xef, 0xf0, 0x4f, 0xa8, 0xef, 0x20, 0x60, 0x5f, 0xef, 0x10, 0x50, 0x1c, 0xef, 0x20, - 0x30, 0x21, 0xef, 0xe0, 0xff, 0xf3, 0x32, 0x47, 0x37, 0x56, 0x10, 0x00, 0x93, 0x07, 0x50, 0x05, 0x13, 0x06, 0x46, - 0x4e, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, 0x64, 0x1c, 0xc3, 0xef, 0x00, 0x50, 0x3d, 0xef, 0x20, 0x10, 0x21, - 0xef, 0x10, 0x70, 0x48, 0xef, 0x20, 0x20, 0x5f, 0xef, 0x30, 0x90, 0x00, 0xc2, 0x47, 0x98, 0x43, 0x93, 0x07, 0x50, - 0x05, 0xe3, 0x08, 0xf7, 0xe4, 0xad, 0xb9, 0x63, 0x1c, 0xe5, 0x00, 0x83, 0xc7, 0x17, 0x00, 0xbd, 0x8b, 0xe3, 0x82, - 0x07, 0xec, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0xa0, 0x59, 0x65, 0xbd, 0x91, 0x07, 0x75, 0xb5, 0x03, 0xa4, 0x09, - 0x07, 0xe3, 0xe4, 0x87, 0x16, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0xc5, 0x3f, 0xef, 0x00, 0xb0, 0x3f, - 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x3f, 0x95, 0x45, 0xef, 0x00, 0xd0, 0x3e, 0x13, 0x05, 0xf0, 0x07, 0x39, - 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xf5, 0x94, 0x43, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, - 0x13, 0x87, 0x16, 0x00, 0x98, 0xc3, 0x03, 0xc7, 0x89, 0x07, 0xa2, 0x87, 0x13, 0x06, 0x46, 0x46, 0x93, 0x85, 0xc5, - 0x3f, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x30, 0x34, 0xb7, 0x17, 0x20, 0x00, 0x13, 0x85, 0xc7, 0x07, 0x3d, 0x46, - 0x81, 0x45, 0xef, 0x30, 0xd0, 0x7f, 0x83, 0xc7, 0x89, 0x07, 0x13, 0x07, 0x20, 0x04, 0x63, 0x80, 0xe7, 0x56, 0x63, - 0x69, 0xf7, 0x16, 0x13, 0x07, 0x10, 0x02, 0x63, 0x89, 0xe7, 0x3e, 0x63, 0x60, 0xf7, 0x08, 0x45, 0x47, 0x63, 0x82, - 0xe7, 0x30, 0x63, 0x69, 0xf7, 0x02, 0x05, 0x47, 0x63, 0x85, 0xe7, 0x24, 0x41, 0x47, 0x63, 0x8d, 0xe7, 0x26, 0x89, - 0x49, 0x3d, 0xa3, 0x93, 0x87, 0x07, 0xfa, 0x93, 0xf7, 0xf7, 0x0f, 0x45, 0x47, 0xe3, 0x69, 0xf7, 0xfe, 0x37, 0x57, - 0x10, 0x00, 0x8a, 0x07, 0x13, 0x07, 0xc7, 0x4e, 0xba, 0x97, 0x9c, 0x43, 0x82, 0x87, 0x49, 0x47, 0x63, 0x82, 0xe7, - 0x34, 0x13, 0x07, 0x00, 0x02, 0xe3, 0x9a, 0xe7, 0xfc, 0x42, 0x04, 0x41, 0x80, 0xa1, 0x47, 0xe3, 0x13, 0xf4, 0xf4, - 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x81, 0x63, 0x97, 0x07, 0x54, 0x93, - 0x07, 0xf0, 0x1f, 0x63, 0xe3, 0xa7, 0x54, 0x83, 0x25, 0x4d, 0x00, 0xef, 0x10, 0x90, 0x1e, 0x93, 0x07, 0xa0, 0x0a, - 0x63, 0x1b, 0xf5, 0x52, 0xad, 0xa6, 0x13, 0x07, 0x10, 0x03, 0x63, 0x86, 0xe7, 0x3a, 0x63, 0x6f, 0xf7, 0x04, 0x13, - 0x07, 0x20, 0x02, 0x63, 0x87, 0xe7, 0x38, 0x13, 0x07, 0x00, 0x03, 0xe3, 0x91, 0xe7, 0xf8, 0x42, 0x04, 0x41, 0x80, - 0x91, 0x47, 0xe3, 0x1a, 0xf4, 0xee, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x97, 0x07, 0x01, 0x8d, 0x8b, 0x41, - 0x83, 0x63, 0x9e, 0x07, 0x4e, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xea, 0xe7, 0x4e, 0x03, 0x45, 0x3d, 0x00, 0xfd, 0x47, - 0x63, 0xe5, 0xa7, 0x4e, 0x93, 0x15, 0x25, 0x00, 0x0d, 0x81, 0x93, 0xf7, 0xc5, 0x01, 0x3a, 0x95, 0xbd, 0x45, 0xb3, - 0x95, 0xf5, 0x00, 0x0a, 0x05, 0x93, 0xc5, 0xf5, 0xff, 0x5a, 0x95, 0x05, 0xa4, 0x13, 0x07, 0x00, 0x04, 0x63, 0x8f, - 0xe7, 0x3a, 0x13, 0x07, 0x10, 0x04, 0xe3, 0x94, 0xe7, 0xf2, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x1d, 0xf4, - 0xe8, 0x83, 0x26, 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0xa1, 0x82, 0xc2, 0x06, 0xc1, 0x82, 0x63, 0xe1, 0xd7, 0x4a, - 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x86, 0x4b, 0x93, 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, - 0x64, 0xef, 0x00, 0x10, 0x1f, 0xef, 0x10, 0x50, 0x57, 0xef, 0x20, 0x00, 0x75, 0x83, 0x27, 0x0d, 0x00, 0x91, 0x65, - 0x93, 0x85, 0x05, 0x20, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, 0xa6, 0x07, 0x37, 0x15, 0x20, 0x00, 0xbe, 0x95, 0x13, - 0x05, 0x05, 0x08, 0xef, 0x10, 0x30, 0x19, 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x74, 0x93, 0x07, 0xc0, 0x1b, 0xe3, 0xe0, - 0x87, 0xa8, 0x93, 0x05, 0x44, 0x00, 0x29, 0xac, 0x13, 0x07, 0x10, 0x07, 0x63, 0x69, 0xf7, 0x02, 0x13, 0x07, 0xf0, - 0x05, 0xe3, 0x66, 0xf7, 0xea, 0x13, 0x07, 0x00, 0x05, 0xe3, 0x90, 0xe7, 0xea, 0x42, 0x04, 0x41, 0x80, 0x89, 0x47, - 0xe3, 0x19, 0xf4, 0xe0, 0x03, 0x44, 0x1d, 0x00, 0x37, 0x15, 0x20, 0x00, 0x13, 0x05, 0x05, 0x08, 0xa2, 0x85, 0xef, - 0xe0, 0x1f, 0xd7, 0xd9, 0xb7, 0x13, 0x07, 0x20, 0x08, 0x63, 0x8b, 0xe7, 0x6e, 0x63, 0x6d, 0xf7, 0x04, 0x13, 0x07, - 0x00, 0x08, 0x63, 0x82, 0xe7, 0x68, 0x13, 0x07, 0x10, 0x08, 0xe3, 0x93, 0xe7, 0xe6, 0x42, 0x04, 0x41, 0x80, 0x8d, - 0x47, 0xe3, 0x1c, 0xf4, 0xdc, 0x03, 0x45, 0x1d, 0x00, 0x3d, 0x47, 0x81, 0x47, 0x63, 0x6e, 0xa7, 0x00, 0xb7, 0x37, - 0x20, 0x00, 0x03, 0xa7, 0x47, 0xf5, 0x89, 0x47, 0x33, 0x57, 0xa7, 0x00, 0x05, 0x8b, 0x01, 0xc7, 0xef, 0xe0, 0x7f, - 0xe6, 0xaa, 0x87, 0xfd, 0x17, 0x09, 0x47, 0x63, 0x63, 0xf7, 0x3c, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x72, - 0xaa, 0x97, 0x83, 0xc9, 0x07, 0x00, 0x1d, 0xaa, 0x13, 0x07, 0x00, 0x09, 0xe3, 0x9c, 0xe7, 0xe0, 0x93, 0x17, 0x04, - 0x01, 0xc1, 0x83, 0x13, 0x07, 0x30, 0x02, 0xe3, 0x73, 0xf7, 0xd8, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, - 0xbe, 0x86, 0x13, 0x06, 0x06, 0x4c, 0x93, 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0xd0, 0x0e, 0xef, - 0x20, 0xa0, 0x0d, 0xef, 0x20, 0xc0, 0x64, 0xef, 0x20, 0x20, 0x0e, 0x2a, 0x84, 0xef, 0x20, 0x40, 0x0d, 0xef, 0x20, - 0x00, 0x66, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x14, 0xf4, 0x36, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0x00, 0x2c, 0x93, - 0x07, 0x40, 0x02, 0x81, 0xa3, 0x93, 0x19, 0x04, 0x01, 0x93, 0xd9, 0x09, 0x01, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, - 0x10, 0x00, 0xce, 0x86, 0x13, 0x06, 0x06, 0x4a, 0x93, 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0xf0, - 0x09, 0x93, 0x07, 0x1b, 0x00, 0xe3, 0xeb, 0x37, 0xd1, 0xce, 0x85, 0x13, 0x85, 0x0a, 0x00, 0xef, 0xf0, 0x4f, 0x8e, - 0xa9, 0xaa, 0x42, 0x04, 0x41, 0x80, 0x93, 0x07, 0x40, 0x02, 0xe3, 0x1f, 0xf4, 0xce, 0x03, 0x25, 0x0d, 0x00, 0x0d, - 0x44, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0x64, 0xa4, 0x30, 0xef, 0xf0, 0x8f, 0xae, 0xd5, 0x47, 0x63, 0x1f, - 0xf5, 0x2e, 0x83, 0x29, 0x0d, 0x00, 0x93, 0xd9, 0x89, 0x00, 0xc2, 0x09, 0x93, 0xd9, 0x09, 0x01, 0xe3, 0x6c, 0x34, - 0x91, 0x13, 0x84, 0x09, 0x0e, 0x16, 0x04, 0x91, 0x4c, 0x71, 0x14, 0x93, 0x0d, 0x40, 0x02, 0xb3, 0x05, 0x9d, 0x01, - 0x11, 0x46, 0x68, 0x10, 0xef, 0x30, 0x70, 0x4c, 0xb2, 0x55, 0x33, 0x05, 0x94, 0x01, 0x91, 0x0c, 0xef, 0x20, 0x20, - 0x33, 0xe3, 0x94, 0xbc, 0xff, 0x09, 0x65, 0x8a, 0x09, 0xb7, 0xf5, 0xf0, 0xf0, 0x13, 0x05, 0x05, 0xbf, 0x93, 0x85, - 0x05, 0x0f, 0x4e, 0x95, 0xef, 0x20, 0x80, 0x31, 0xc5, 0xa0, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x13, 0xf4, - 0xc8, 0x03, 0x25, 0x0d, 0x00, 0x0d, 0x44, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0x68, 0xa4, 0x28, 0xef, 0xf0, - 0x0f, 0xa7, 0x93, 0x07, 0x30, 0x0c, 0x63, 0x08, 0xf5, 0x00, 0xaa, 0x89, 0x93, 0x07, 0x00, 0x08, 0x63, 0x9a, 0xf9, - 0x20, 0xb1, 0xb9, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, 0xe3, 0x6b, 0xf4, 0x88, 0x93, 0x87, - 0x07, 0x0e, 0x13, 0x94, 0x57, 0x00, 0x93, 0x09, 0x00, 0x02, 0x33, 0x05, 0x94, 0x01, 0xef, 0x20, 0x20, 0x20, 0xb7, - 0x17, 0x20, 0x00, 0x93, 0x87, 0x07, 0x08, 0x2a, 0xd6, 0x11, 0x46, 0x33, 0x85, 0x97, 0x01, 0x6c, 0x10, 0x91, 0x0c, - 0xef, 0x30, 0x30, 0x43, 0xe3, 0x90, 0x3c, 0xff, 0x93, 0x05, 0x40, 0x02, 0x52, 0x85, 0x29, 0xb7, 0x42, 0x04, 0x41, - 0x80, 0x8d, 0x47, 0xe3, 0x17, 0xf4, 0xc0, 0x03, 0x25, 0x0d, 0x00, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0x6d, - 0xa4, 0x20, 0xef, 0xf0, 0xaf, 0x9f, 0xd5, 0x47, 0x63, 0x08, 0xf5, 0x20, 0xd9, 0x47, 0x63, 0x01, 0xf5, 0x04, 0x83, - 0x29, 0x0d, 0x00, 0x93, 0xd9, 0x89, 0x00, 0xc2, 0x09, 0x93, 0xd9, 0x09, 0x01, 0xe3, 0x62, 0x34, 0x83, 0x89, 0x67, - 0x13, 0x95, 0x29, 0x00, 0x93, 0x87, 0x07, 0xbf, 0x81, 0x45, 0x3e, 0x95, 0x93, 0x89, 0x09, 0x0e, 0xef, 0x20, 0xe0, - 0x24, 0x96, 0x09, 0x13, 0x04, 0x00, 0x02, 0x33, 0x85, 0x99, 0x01, 0x81, 0x45, 0x91, 0x0c, 0xef, 0x20, 0xc0, 0x23, - 0xe3, 0x9a, 0x8c, 0xfe, 0x93, 0x09, 0x30, 0x0c, 0xb9, 0xaa, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x11, 0xf4, - 0xba, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x81, 0x63, 0x95, 0x07, 0x1a, - 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe1, 0xa7, 0x1a, 0xef, 0x10, 0x60, 0x5b, 0x23, 0x22, 0xaa, 0x00, 0xa1, 0x45, 0x8d, - 0xb7, 0x42, 0x04, 0x41, 0x80, 0x85, 0x47, 0x01, 0x45, 0xe3, 0x18, 0xf4, 0xb6, 0xef, 0x10, 0x30, 0x24, 0x6d, 0xbf, - 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x10, 0xf4, 0xb6, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x94, 0x07, - 0x01, 0x8d, 0x8b, 0x41, 0x80, 0x63, 0x94, 0x07, 0x16, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe0, 0x87, 0x16, 0x0a, 0x04, - 0x33, 0x05, 0x64, 0x01, 0xef, 0x20, 0xe0, 0x17, 0x93, 0xf4, 0x04, 0xf0, 0xc9, 0x8c, 0x13, 0x05, 0x4b, 0x00, 0x22, - 0x95, 0xef, 0x20, 0xe0, 0x16, 0xc1, 0x77, 0x93, 0x87, 0xf7, 0x0f, 0xfd, 0x8c, 0x22, 0x05, 0xc9, 0x8c, 0x13, 0x05, - 0x8b, 0x00, 0x22, 0x95, 0xef, 0x20, 0x80, 0x15, 0xb7, 0x07, 0x01, 0xff, 0xfd, 0x17, 0x42, 0x05, 0xfd, 0x8c, 0xc9, - 0x8c, 0x13, 0x05, 0xcb, 0x00, 0x22, 0x95, 0xef, 0x20, 0x20, 0x14, 0xa2, 0x04, 0x62, 0x05, 0xa1, 0x80, 0xc9, 0x8c, - 0x23, 0x22, 0x9a, 0x00, 0x95, 0xbf, 0x93, 0x07, 0xb4, 0xff, 0xc2, 0x07, 0xc1, 0x83, 0x13, 0x07, 0xb0, 0x1b, 0xe3, - 0x61, 0xf7, 0xae, 0x83, 0x26, 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0x93, 0x09, 0xc0, 0x03, 0xa1, 0x82, 0xc2, 0x06, - 0xc1, 0x82, 0x63, 0xe0, 0xd7, 0x08, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x06, 0x4b, 0x93, - 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x40, 0x63, 0x03, 0x25, 0x0d, 0x00, 0x91, 0x69, 0x93, 0x89, - 0x09, 0x20, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x26, 0x05, 0x4e, 0x95, 0xef, 0x10, 0x30, 0x13, 0x93, 0x07, 0xa0, - 0x0a, 0xaa, 0x8c, 0x63, 0x12, 0xf5, 0x04, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0xbf, 0x9f, 0xef, 0x20, 0xe0, 0x36, - 0x83, 0x27, 0x0d, 0x00, 0x42, 0x04, 0x41, 0x80, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, 0xa6, 0x07, 0xb7, 0x05, 0x20, - 0x00, 0x13, 0x06, 0xc4, 0xff, 0x33, 0x85, 0x37, 0x01, 0x74, 0x10, 0x93, 0x85, 0x45, 0x00, 0xef, 0x10, 0xf0, 0x02, - 0x2a, 0x84, 0x93, 0x09, 0x30, 0x0c, 0xef, 0x20, 0x00, 0x36, 0x63, 0x03, 0x94, 0x01, 0xc1, 0x49, 0x13, 0xf5, 0xf9, - 0x0f, 0xe5, 0xae, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x10, 0xf4, 0xa4, 0x03, 0x25, 0x0d, 0x00, 0x93, 0x07, - 0xf0, 0x1f, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0xe4, 0xa7, 0x04, 0x91, 0x67, 0x26, 0x05, 0x93, 0x87, 0x07, - 0x20, 0x3e, 0x95, 0x55, 0xbd, 0x42, 0x04, 0x41, 0x80, 0x91, 0x47, 0xe3, 0x1c, 0xf4, 0xa0, 0xc1, 0x45, 0x68, 0x10, - 0xef, 0xe0, 0x1f, 0x98, 0x68, 0x10, 0xef, 0x10, 0x80, 0x7c, 0xef, 0x30, 0xa0, 0x20, 0xef, 0x20, 0xa0, 0x2e, 0x91, - 0x45, 0x13, 0x05, 0x00, 0x06, 0xef, 0x30, 0xc0, 0x42, 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x2f, 0x93, 0x07, 0xa0, 0x0a, - 0xe3, 0x0e, 0xf4, 0xe2, 0x93, 0x09, 0xc0, 0x03, 0x59, 0xbf, 0x42, 0x04, 0x41, 0x80, 0x93, 0x07, 0x00, 0x03, 0xe3, - 0x1c, 0xf4, 0x9c, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0x1f, 0x94, 0x68, 0x10, 0xef, 0x10, 0x80, 0x78, 0xef, 0x30, - 0xa0, 0x1c, 0xef, 0x20, 0xa0, 0x2a, 0x93, 0x05, 0x00, 0x03, 0x13, 0x05, 0x10, 0x06, 0x7d, 0xbf, 0x42, 0x04, 0x41, - 0x80, 0x8d, 0x47, 0xe3, 0x17, 0xf4, 0x9a, 0xef, 0x30, 0xe0, 0x1a, 0xef, 0x20, 0xe0, 0x28, 0x8d, 0x45, 0x13, 0x05, - 0x20, 0x06, 0xef, 0x30, 0x00, 0x3d, 0x2a, 0x84, 0xef, 0x20, 0x00, 0x2a, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x14, 0xf4, - 0xfa, 0xef, 0xe0, 0x7f, 0xf0, 0x05, 0xb3, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x1f, 0xf4, 0x96, 0xef, 0x30, - 0xe0, 0x17, 0x8d, 0x45, 0x13, 0x05, 0x30, 0x06, 0xef, 0x30, 0x40, 0x3a, 0xb1, 0xb4, 0x42, 0x04, 0x41, 0x80, 0x93, - 0x07, 0x00, 0x03, 0xe3, 0x11, 0xf4, 0x96, 0xef, 0x30, 0x20, 0x16, 0xef, 0x20, 0x50, 0x6f, 0xb7, 0x15, 0x20, 0x00, - 0x2a, 0xd6, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, 0xef, 0x30, 0x60, 0x26, 0x11, - 0x46, 0x6c, 0x10, 0x13, 0x05, 0x00, 0x0c, 0xef, 0x30, 0xa0, 0x25, 0xef, 0x20, 0xc0, 0x21, 0x93, 0x05, 0x00, 0x03, - 0x13, 0x05, 0x00, 0x07, 0xef, 0x30, 0xc0, 0x35, 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x22, 0x93, 0x07, 0xa0, 0x0a, 0xe3, - 0x1a, 0xf4, 0xf2, 0xef, 0xe0, 0x3f, 0xe9, 0x75, 0xb1, 0x93, 0x17, 0x04, 0x01, 0xc1, 0x83, 0x3d, 0x47, 0xe3, 0x74, - 0xf7, 0x90, 0xef, 0x30, 0x80, 0x10, 0xef, 0x20, 0xb0, 0x69, 0xaa, 0x8c, 0x01, 0x45, 0xef, 0x20, 0xd0, 0x45, 0x41, - 0x46, 0x93, 0x85, 0x0a, 0x00, 0x01, 0x45, 0xef, 0x20, 0xf0, 0x46, 0xef, 0x20, 0x00, 0x1d, 0xb7, 0x15, 0x20, 0x00, - 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, 0x66, 0xd6, 0xef, 0x30, 0x40, 0x1f, 0x11, - 0x46, 0x6c, 0x10, 0x13, 0x05, 0x00, 0x0c, 0xef, 0x30, 0x80, 0x1e, 0x85, 0x45, 0x13, 0x05, 0x10, 0x04, 0xef, 0x30, - 0x00, 0x2f, 0x93, 0x07, 0xa0, 0x0a, 0xaa, 0x8c, 0x63, 0x19, 0xf5, 0x00, 0x81, 0x45, 0x13, 0x05, 0x20, 0x04, 0xef, - 0x30, 0xc0, 0x2d, 0x63, 0x05, 0x95, 0x01, 0xef, 0x20, 0xa0, 0x1a, 0x5d, 0xbd, 0x42, 0x04, 0x41, 0x80, 0x93, 0x0d, - 0x04, 0xff, 0xef, 0x20, 0xc0, 0x19, 0xee, 0x8c, 0x22, 0x9d, 0x93, 0x07, 0x00, 0x09, 0xb3, 0x05, 0x9d, 0x41, 0x63, - 0xe5, 0x97, 0x09, 0x66, 0x86, 0x01, 0x45, 0xef, 0x20, 0xd0, 0x3f, 0xe6, 0x85, 0x13, 0x05, 0x40, 0x04, 0xef, 0x30, - 0x40, 0x2a, 0x13, 0x07, 0xa0, 0x0a, 0xe3, 0x11, 0xe5, 0xe8, 0x2a, 0xce, 0x81, 0x45, 0x13, 0x05, 0x50, 0x04, 0xef, - 0x30, 0x00, 0x29, 0xf2, 0x47, 0xaa, 0x8c, 0xe3, 0x17, 0xf5, 0xe6, 0x01, 0x45, 0xef, 0x20, 0x30, 0x3b, 0x93, 0x85, - 0x0a, 0x00, 0x41, 0x46, 0x01, 0x45, 0xef, 0x20, 0x50, 0x3c, 0x93, 0x07, 0xf0, 0x03, 0xb7, 0x05, 0x20, 0x00, 0x63, - 0xe1, 0xb7, 0x07, 0x93, 0x85, 0x05, 0x01, 0x01, 0x45, 0x6e, 0x86, 0xef, 0x20, 0xd0, 0x3a, 0xee, 0x85, 0x13, 0x05, - 0x60, 0x04, 0xef, 0x30, 0x40, 0x25, 0xe3, 0x1b, 0x95, 0xe3, 0x81, 0x45, 0x13, 0x05, 0xa0, 0x04, 0xef, 0x30, 0x60, - 0x24, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x12, 0xf5, 0xe2, 0xef, 0x20, 0x10, 0x58, 0x93, 0x07, 0x00, 0x05, 0x23, 0xaa, - 0xf9, 0x06, 0xb1, 0xb1, 0x13, 0x06, 0x00, 0x09, 0x01, 0x45, 0xef, 0x20, 0x50, 0x37, 0x93, 0x05, 0x00, 0x09, 0x13, - 0x05, 0x30, 0x04, 0xef, 0x30, 0xa0, 0x21, 0x13, 0x07, 0xa0, 0x0a, 0xe3, 0x1c, 0xe5, 0xde, 0x93, 0x8c, 0x0c, 0xf7, - 0xb1, 0xb7, 0x93, 0x85, 0x05, 0x01, 0x01, 0x45, 0x13, 0x06, 0x00, 0x04, 0xef, 0x20, 0xd0, 0x34, 0x93, 0x05, 0x00, - 0x04, 0x13, 0x05, 0x70, 0x04, 0xef, 0x30, 0x20, 0x1f, 0xe3, 0x1a, 0x95, 0xdd, 0x13, 0x04, 0x04, 0xfb, 0x93, 0x0c, - 0x00, 0x08, 0x93, 0x0d, 0xa0, 0x0a, 0xb3, 0x05, 0x8d, 0x40, 0x63, 0xe0, 0x8c, 0x02, 0x22, 0x86, 0x01, 0x45, 0xef, - 0x20, 0x10, 0x32, 0xa2, 0x85, 0x13, 0x05, 0x90, 0x04, 0xef, 0x30, 0x80, 0x1c, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x13, - 0xf5, 0xda, 0x85, 0xbf, 0x01, 0x45, 0x13, 0x06, 0x00, 0x08, 0xef, 0x20, 0x30, 0x30, 0x93, 0x05, 0x00, 0x08, 0x13, - 0x05, 0x80, 0x04, 0xef, 0x30, 0x80, 0x1a, 0xe3, 0x15, 0xb5, 0xd9, 0x13, 0x04, 0x04, 0xf8, 0x7d, 0xbf, 0x42, 0x04, - 0x41, 0x80, 0xa1, 0x47, 0x63, 0x10, 0xf4, 0xf6, 0x03, 0x44, 0x1d, 0x00, 0xbd, 0x47, 0xe3, 0xe8, 0x87, 0xd6, 0x83, - 0x2c, 0x4d, 0x00, 0xfd, 0x57, 0xe3, 0x83, 0xfc, 0xd6, 0x93, 0x19, 0xa4, 0x00, 0x13, 0x85, 0x09, 0x40, 0xef, 0xe0, - 0x8f, 0xe6, 0x13, 0x07, 0xa0, 0x0a, 0x2a, 0x8d, 0xe3, 0x18, 0xe5, 0xd4, 0x93, 0x89, 0x09, 0x20, 0x4e, 0x85, 0xef, - 0xe0, 0x4f, 0xe5, 0xaa, 0x8d, 0xe3, 0x10, 0xa5, 0xd5, 0xe6, 0x85, 0x4e, 0x85, 0xef, 0x10, 0x60, 0x1b, 0xe3, 0x1a, - 0xb5, 0xd3, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf5, 0x85, 0x47, 0x33, 0x94, 0x87, 0x00, 0x1c, 0x43, 0x5d, - 0x8c, 0x00, 0xc3, 0x91, 0xbe, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0x63, 0x1d, 0xf4, 0xee, 0x83, 0x45, 0x1d, 0x00, - 0xbd, 0x47, 0xe3, 0xe5, 0xb7, 0xd0, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf5, 0xd1, 0x49, 0xb3, 0xd7, 0xb7, - 0x00, 0x85, 0x8b, 0xe3, 0x88, 0x07, 0xc8, 0x37, 0x15, 0x20, 0x00, 0x13, 0x05, 0x05, 0x08, 0xef, 0xe0, 0x6f, 0xeb, - 0x85, 0x47, 0xe3, 0x07, 0xf5, 0xb4, 0x89, 0x47, 0xe3, 0x0c, 0xf5, 0xc6, 0xe9, 0xb9, 0xef, 0x10, 0x90, 0x43, 0xef, - 0xe0, 0x8f, 0xd8, 0x6f, 0xf0, 0xef, 0xe6, 0xef, 0x00, 0xc0, 0x6f, 0x6f, 0xf0, 0xef, 0xe6, 0xef, 0x00, 0x30, 0x4e, - 0x41, 0x14, 0xaa, 0x86, 0x63, 0x0b, 0x05, 0xea, 0x8d, 0x45, 0x13, 0x85, 0xcd, 0x3d, 0x36, 0xce, 0x71, 0x24, 0xf2, - 0x46, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x45, 0x93, 0x85, 0xcd, 0x3d, 0x13, 0x05, 0x49, 0x64, 0x09, 0x24, - 0xf2, 0x46, 0x09, 0x47, 0x85, 0x47, 0x63, 0x83, 0xe6, 0x00, 0x89, 0x47, 0x83, 0xc6, 0x89, 0x07, 0x37, 0x56, 0x10, - 0x00, 0xb7, 0x55, 0x10, 0x00, 0x22, 0x87, 0x13, 0x06, 0xc6, 0x47, 0x93, 0x85, 0xc5, 0x3f, 0x13, 0x05, 0x49, 0x64, - 0xa3, 0x8c, 0xf9, 0x06, 0xd9, 0x2a, 0xef, 0xe0, 0x8f, 0xce, 0xef, 0xe0, 0x8f, 0xff, 0x62, 0x47, 0x85, 0x47, 0x23, - 0x00, 0xf7, 0x00, 0xef, 0x00, 0xe0, 0x5a, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x11, 0xf5, 0xd6, 0x25, 0x29, - 0x63, 0x1e, 0x85, 0xd4, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xf4, 0xb1, 0xeb, 0x83, 0xa7, 0x4b, 0x07, 0x13, - 0x07, 0xfb, 0x00, 0xfd, 0x17, 0x63, 0x64, 0xf7, 0x04, 0x05, 0x45, 0xef, 0x20, 0xb0, 0x17, 0x03, 0xa6, 0x4b, 0x07, - 0xb7, 0x09, 0x20, 0x00, 0x93, 0x85, 0x09, 0x00, 0x13, 0x85, 0x09, 0x00, 0xef, 0x20, 0xf0, 0x25, 0x37, 0x14, 0x20, - 0x00, 0x13, 0x05, 0x04, 0x02, 0xef, 0x20, 0x50, 0x34, 0x03, 0xa5, 0x4b, 0x07, 0x93, 0x87, 0x09, 0x00, 0x41, 0x46, - 0x3e, 0x95, 0x93, 0x05, 0x04, 0x02, 0xef, 0x30, 0x00, 0x5f, 0x83, 0xa7, 0x4b, 0x07, 0xc1, 0x07, 0x23, 0xaa, 0xfb, - 0x06, 0xef, 0x00, 0xf0, 0x1b, 0x13, 0x04, 0xa0, 0x0a, 0x63, 0x0a, 0x85, 0xce, 0xef, 0xe0, 0x8f, 0xfe, 0x63, 0x16, - 0x85, 0xce, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x06, 0x4d, 0x93, - 0x85, 0xc5, 0x3f, 0x13, 0x05, 0x45, 0x40, 0x25, 0x22, 0xef, 0xe0, 0x2f, 0xb7, 0xef, 0x20, 0x70, 0x32, 0xef, 0x00, - 0xb0, 0x3a, 0xef, 0x00, 0xb0, 0x31, 0xef, 0xe0, 0xaf, 0xf9, 0x6f, 0xf0, 0xaf, 0xcb, 0x2a, 0x87, 0x81, 0x47, 0x01, - 0x45, 0x63, 0x93, 0xc7, 0x00, 0x82, 0x80, 0xb3, 0x06, 0xf7, 0x00, 0x33, 0x88, 0xf5, 0x00, 0x83, 0xc6, 0x06, 0x00, - 0x03, 0x48, 0x08, 0x00, 0x85, 0x07, 0xb3, 0xc6, 0x06, 0x01, 0x55, 0x8d, 0x13, 0x75, 0xf5, 0x0f, 0xf9, 0xbf, 0xb7, - 0x37, 0x20, 0x00, 0x37, 0x37, 0x20, 0x00, 0x03, 0xa8, 0xc7, 0xf5, 0x83, 0x27, 0x87, 0xf5, 0xaa, 0x86, 0x13, 0x07, - 0x87, 0xf5, 0x01, 0x45, 0x63, 0x13, 0xf8, 0x00, 0x82, 0x80, 0x37, 0x26, 0x20, 0x00, 0x13, 0x06, 0xc6, 0x08, 0x93, - 0x08, 0xf0, 0x7f, 0x63, 0x01, 0xb5, 0x02, 0x33, 0x0e, 0xf6, 0x00, 0x03, 0x4e, 0x0e, 0x00, 0x05, 0x05, 0x33, 0x83, - 0xa6, 0x00, 0xa3, 0x0f, 0xc3, 0xff, 0x85, 0x07, 0x63, 0xf3, 0xf8, 0x00, 0x81, 0x47, 0xe3, 0x11, 0xf8, 0xfe, 0x1c, - 0xc3, 0x82, 0x80, 0xb7, 0x36, 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x86, 0xf5, 0x83, 0xa7, 0xc7, 0xf5, - 0x93, 0x86, 0x86, 0xf5, 0x33, 0x87, 0xe7, 0x40, 0x63, 0x56, 0x07, 0x00, 0x05, 0x66, 0x13, 0x06, 0x06, 0x80, 0x32, - 0x97, 0x63, 0x5b, 0xe5, 0x00, 0x33, 0x85, 0xa7, 0x40, 0x85, 0x67, 0x93, 0x87, 0x07, 0x80, 0x63, 0xf3, 0xa7, 0x00, - 0x3e, 0x95, 0x88, 0xc2, 0x82, 0x80, 0xb7, 0x36, 0x20, 0x00, 0x03, 0xa8, 0xc6, 0xf5, 0x13, 0x07, 0xf0, 0x7f, 0x13, - 0x86, 0xc6, 0xf5, 0x93, 0x07, 0x18, 0x00, 0x63, 0x73, 0xf7, 0x00, 0x81, 0x47, 0xb7, 0x36, 0x20, 0x00, 0x83, 0xa8, - 0x86, 0xf5, 0x37, 0x27, 0x20, 0x00, 0x93, 0x85, 0x86, 0xf5, 0x13, 0x07, 0xc7, 0x08, 0x63, 0x9f, 0xf8, 0x00, 0x93, - 0x88, 0x17, 0x80, 0x93, 0x86, 0x17, 0x00, 0x63, 0x93, 0x08, 0x00, 0x81, 0x46, 0x94, 0xc1, 0xba, 0x96, 0x93, 0x05, - 0xa0, 0x02, 0x23, 0x80, 0xb6, 0x00, 0x42, 0x97, 0x23, 0x00, 0xa7, 0x00, 0x1c, 0xc2, 0x82, 0x80, 0x82, 0x80, 0x39, - 0x71, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x06, 0xce, 0x36, 0xd6, 0x3a, 0xd8, 0x3e, 0xda, 0x42, 0xdc, 0x46, 0xde, - 0xaa, 0x84, 0x2e, 0x89, 0x32, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0xdf, 0x96, 0x63, 0x14, 0x09, 0x00, 0xef, 0xe0, 0x5f, - 0x96, 0x19, 0xe0, 0xef, 0xe0, 0xff, 0x95, 0x7c, 0x10, 0x3e, 0xc6, 0xef, 0x30, 0x20, 0x13, 0xaa, 0x85, 0x37, 0x55, - 0x10, 0x00, 0x13, 0x05, 0x85, 0x60, 0xef, 0x30, 0x20, 0x38, 0x37, 0x55, 0x10, 0x00, 0x4a, 0x86, 0xa6, 0x85, 0x13, - 0x05, 0x05, 0x61, 0xef, 0x30, 0x20, 0x37, 0xb2, 0x45, 0x22, 0x85, 0xef, 0x30, 0x80, 0x33, 0x37, 0x55, 0x10, 0x00, - 0x13, 0x05, 0xc5, 0x61, 0xef, 0x30, 0xe0, 0x35, 0xb9, 0x29, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0x21, - 0x61, 0x82, 0x80, 0xae, 0x86, 0x37, 0x56, 0x10, 0x00, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x4b, - 0x13, 0x05, 0x05, 0x62, 0x9d, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, 0x83, - 0xa6, 0x47, 0x10, 0x63, 0x7e, 0xd7, 0x00, 0x0a, 0x07, 0x3e, 0x97, 0x18, 0x43, 0x18, 0xc1, 0x03, 0xa7, 0x07, 0x10, - 0x13, 0x05, 0xa0, 0x0a, 0x05, 0x07, 0x23, 0xa0, 0xe7, 0x10, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, - 0x11, 0x26, 0xca, 0xb7, 0x34, 0x20, 0x00, 0x83, 0xa7, 0x04, 0xf6, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, - 0x52, 0xc4, 0x11, 0x47, 0x63, 0x6f, 0xf7, 0x0c, 0x37, 0x57, 0x10, 0x00, 0x8a, 0x07, 0x13, 0x07, 0x87, 0x64, 0xba, - 0x97, 0x9c, 0x43, 0x2a, 0x84, 0x93, 0x84, 0x04, 0xf6, 0x82, 0x87, 0x81, 0x45, 0xef, 0x30, 0x20, 0x31, 0xb7, 0x37, - 0x20, 0x00, 0x23, 0x92, 0xa7, 0xf6, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x86, 0x87, 0x88, 0xef, 0x20, 0xd0, 0x6f, 0x9c, - 0x40, 0x85, 0x07, 0x81, 0xa8, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0x07, 0xf6, 0x93, 0x07, 0xc0, 0x0f, 0x63, 0xf1, - 0xa7, 0x02, 0x62, 0x44, 0x9d, 0x47, 0xf2, 0x40, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x9c, 0xc0, 0xd2, 0x44, 0x37, - 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x45, 0x62, 0x05, 0x61, 0x2d, 0xbf, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, - 0x49, 0xf6, 0x83, 0x55, 0x09, 0x00, 0xef, 0x30, 0xa0, 0x2b, 0xb7, 0x37, 0x20, 0x00, 0xa3, 0x86, 0x87, 0x88, 0x23, - 0x10, 0xa9, 0x00, 0x8d, 0x47, 0x5d, 0xf4, 0x9c, 0xc0, 0x91, 0xa8, 0x37, 0x39, 0x20, 0x00, 0x03, 0x27, 0x89, 0xf6, - 0x93, 0x07, 0xb0, 0x0f, 0x13, 0x09, 0x89, 0xf6, 0x63, 0xf4, 0xe7, 0x00, 0xef, 0xe0, 0x3f, 0x81, 0x83, 0x27, 0x09, - 0x00, 0x37, 0x3a, 0x20, 0x00, 0x13, 0x0a, 0x4a, 0xf6, 0xb7, 0x39, 0x20, 0x00, 0x93, 0x89, 0xc9, 0x88, 0x83, 0x55, - 0x0a, 0x00, 0xce, 0x97, 0x23, 0x81, 0x87, 0x00, 0x22, 0x85, 0xef, 0x30, 0xa0, 0x26, 0x83, 0x27, 0x09, 0x00, 0x03, - 0xc7, 0x19, 0x00, 0x23, 0x10, 0xaa, 0x00, 0x85, 0x07, 0x23, 0x20, 0xf9, 0x00, 0xe3, 0xfd, 0xe7, 0xf4, 0xf2, 0x40, - 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, - 0x93, 0xa7, 0xf6, 0x3d, 0xbf, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x69, 0xf6, 0x13, 0x14, 0x85, 0x00, 0xb7, 0x39, - 0x20, 0x00, 0x03, 0x55, 0x09, 0x00, 0x93, 0x89, 0x49, 0xf6, 0x83, 0xd7, 0x09, 0x00, 0x49, 0x8c, 0x23, 0x10, 0x89, - 0x00, 0xe3, 0x8d, 0x87, 0xf0, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0x44, 0x62, 0x99, 0x47, 0x89, 0x45, 0x9c, 0xc0, - 0x95, 0x3d, 0x93, 0x05, 0x44, 0x62, 0x62, 0x44, 0x03, 0xd7, 0x09, 0x00, 0x83, 0x56, 0x09, 0x00, 0xf2, 0x40, 0xd2, - 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x86, 0x62, - 0x13, 0x05, 0x45, 0x64, 0x05, 0x61, 0x6f, 0xf0, 0x3f, 0xdd, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0xb7, - 0x25, 0x10, 0x00, 0x37, 0x25, 0x10, 0x00, 0x23, 0xa0, 0x07, 0x10, 0x23, 0xa2, 0x07, 0x10, 0x93, 0x85, 0x05, 0xf8, - 0xb7, 0x37, 0x20, 0x00, 0x13, 0x05, 0x25, 0xfb, 0x23, 0xa0, 0x07, 0xf6, 0x6f, 0x20, 0xb0, 0x52, 0x11, 0xed, 0x01, - 0x11, 0x06, 0xce, 0x2a, 0xc6, 0xef, 0xe0, 0x2f, 0xf2, 0x32, 0x45, 0xf2, 0x40, 0x13, 0x06, 0xe0, 0x0f, 0x81, 0x45, - 0x05, 0x61, 0x6f, 0x30, 0x40, 0x25, 0x13, 0x06, 0xe0, 0x0f, 0x81, 0x45, 0xdd, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x83, - 0xa7, 0x07, 0xf6, 0x13, 0x05, 0xa0, 0x0a, 0x99, 0xc3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, - 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, 0xf6, 0x1c, 0x40, 0x06, 0xc6, 0x15, 0x47, 0x63, 0x98, 0xe7, 0x00, 0x13, - 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x81, 0xe7, 0x13, 0x05, 0x50, 0x05, 0xcd, 0xbf, - 0xef, 0x20, 0x90, 0x50, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x19, 0xf5, 0xfe, 0x01, 0x00, 0x18, 0x40, 0x91, 0x47, 0xe3, - 0xcd, 0xe7, 0xfc, 0x99, 0x47, 0x1c, 0xc0, 0xd9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x20, 0x10, 0x50, 0x93, 0x07, - 0xa0, 0x0a, 0x63, 0x04, 0xf5, 0x00, 0xef, 0x20, 0x70, 0x51, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x95, - 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, - 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x99, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, - 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x9d, 0x47, 0x13, 0x05, 0xa0, 0x0a, - 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x37, 0x35, 0x20, 0x00, 0x13, 0x05, 0xc5, 0x88, 0x82, - 0x80, 0x01, 0x11, 0x26, 0xca, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0xaa, 0x84, 0x19, 0xe1, 0xef, 0xe0, - 0x2f, 0xe3, 0x83, 0xc7, 0x14, 0x00, 0x13, 0x07, 0xc0, 0x0f, 0x13, 0x05, 0x50, 0x05, 0x63, 0x65, 0xf7, 0x06, 0x37, - 0x39, 0x20, 0x00, 0x13, 0x04, 0xc9, 0x98, 0x23, 0x20, 0x04, 0x10, 0x03, 0xc7, 0x04, 0x00, 0xa3, 0x00, 0xf4, 0x00, - 0x03, 0xc6, 0x14, 0x00, 0x23, 0x00, 0xe4, 0x00, 0x93, 0x85, 0x24, 0x00, 0x13, 0x05, 0x24, 0x00, 0xef, 0x30, 0x00, - 0x10, 0x83, 0xc9, 0x14, 0x00, 0x13, 0x05, 0xc9, 0x98, 0x13, 0x09, 0xc9, 0x98, 0x93, 0x84, 0x29, 0x00, 0xa6, 0x85, - 0xef, 0x30, 0x60, 0x08, 0xa2, 0x94, 0x23, 0x80, 0xa4, 0x00, 0x4e, 0x94, 0x21, 0x81, 0x93, 0x87, 0x49, 0x00, 0xa3, - 0x01, 0xa4, 0x00, 0xfd, 0x56, 0x13, 0xf7, 0x37, 0x00, 0x19, 0xef, 0x89, 0x83, 0x23, 0x22, 0xf9, 0x10, 0xef, 0x20, - 0xb0, 0x45, 0x13, 0x05, 0xa0, 0x0a, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, - 0x80, 0x33, 0x07, 0xf9, 0x00, 0x23, 0x00, 0xd7, 0x00, 0x85, 0x07, 0xd1, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, - 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, 0x83, 0xa7, 0x47, 0x10, 0x63, 0x14, 0xf7, 0x00, 0x6f, 0x20, 0x30, 0x3e, 0x13, - 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa0, 0x07, 0xf6, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, - 0x93, 0x07, 0x00, 0x08, 0x73, 0xa0, 0x47, 0x30, 0x93, 0x06, 0x70, 0x3e, 0x09, 0x46, 0x93, 0x05, 0x60, 0x04, 0x37, - 0x05, 0x10, 0x01, 0xef, 0x20, 0x30, 0x52, 0x8d, 0x45, 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, 0x70, 0x52, 0x37, 0x05, - 0x10, 0x01, 0xef, 0x20, 0xf0, 0x4f, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x10, 0x50, 0xfd, 0x56, 0x01, 0x46, 0x93, - 0x05, 0x60, 0x04, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x90, 0x4f, 0xb2, 0x40, 0xb7, 0x07, 0x20, 0x01, 0x23, 0xac, - 0x07, 0x00, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x89, 0x2c, 0xb2, 0x40, 0x41, 0x01, 0x45, 0xb7, 0x41, - 0x11, 0x22, 0xc4, 0xb7, 0x07, 0x20, 0x01, 0x06, 0xc6, 0x23, 0xac, 0x07, 0x00, 0x2a, 0x84, 0x37, 0x05, 0x20, 0x01, - 0xef, 0x20, 0x50, 0x4b, 0x93, 0x07, 0x80, 0x3e, 0x13, 0x05, 0x80, 0x3e, 0x63, 0xe3, 0x87, 0x00, 0x22, 0x85, 0xb7, - 0x07, 0x20, 0x01, 0x98, 0x4f, 0x13, 0x84, 0x87, 0x01, 0xe3, 0x6d, 0xa7, 0xfe, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, - 0xb0, 0x49, 0xb2, 0x40, 0x23, 0x20, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x11, 0xe1, 0x82, 0x80, 0x01, - 0x00, 0x7d, 0x15, 0xe5, 0xbf, 0x6f, 0xf0, 0x9f, 0xb3, 0x39, 0xa4, 0x01, 0x11, 0x26, 0xca, 0xaa, 0x84, 0x37, 0x05, - 0x20, 0x01, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x56, 0xc2, 0x06, 0xce, 0x22, 0xcc, 0x2e, 0x89, 0x93, 0x09, 0xa0, - 0x0a, 0xef, 0x20, 0x50, 0x45, 0x37, 0x0a, 0x20, 0x01, 0x93, 0x0a, 0x80, 0x3e, 0x82, 0x94, 0x2a, 0x84, 0x63, 0x0c, - 0x35, 0x03, 0x83, 0x27, 0x8a, 0x01, 0x63, 0x7a, 0xf9, 0x04, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0xc4, 0x65, 0x85, - 0x45, 0xef, 0xf0, 0x9f, 0xb6, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0x05, 0xc4, 0x65, 0xa6, 0x86, - 0x13, 0x06, 0x06, 0x66, 0x13, 0x05, 0x45, 0x64, 0xef, 0xf0, 0x9f, 0xad, 0x13, 0x04, 0x50, 0x05, 0x37, 0x05, 0x20, - 0x01, 0xef, 0x20, 0x30, 0x41, 0xf2, 0x40, 0x22, 0x85, 0x62, 0x44, 0xb7, 0x07, 0x20, 0x01, 0x23, 0xac, 0x07, 0x00, - 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xe3, 0xf0, 0x2a, 0xfb, 0x41, - 0x22, 0x69, 0xbf, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x87, 0x00, 0x1c, 0xc7, 0x82, 0x80, 0x41, 0x11, - 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, 0xc1, 0xa9, 0x44, 0x03, 0x45, 0x04, - 0x00, 0x11, 0xe5, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xef, 0xf0, 0xdf, 0xa1, 0x83, 0x47, - 0x04, 0x00, 0x63, 0x94, 0x97, 0x00, 0xef, 0xf0, 0x7f, 0xa6, 0x05, 0x04, 0xf9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0x25, - 0x37, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x05, 0xf5, 0x00, 0xef, 0xe0, 0xaf, 0xbd, 0x01, 0xa0, 0xb2, 0x40, 0x41, 0x01, - 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x44, 0x20, 0x00, 0x13, 0x06, 0xc0, 0x1f, 0x81, 0x45, 0x13, 0x05, 0x04, - 0xe0, 0x06, 0xc6, 0x26, 0xc2, 0xef, 0x20, 0xb0, 0x6f, 0x13, 0x05, 0x04, 0xe0, 0x93, 0x05, 0xc0, 0x1f, 0xef, 0x20, - 0xb0, 0x67, 0x93, 0x04, 0x04, 0xe0, 0xb2, 0x40, 0x22, 0x44, 0x23, 0xae, 0xa4, 0x1e, 0x92, 0x44, 0x41, 0x01, 0x82, - 0x80, 0x41, 0x11, 0x37, 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, 0xc0, 0x1f, 0x13, 0x04, 0x05, 0xe0, 0x13, 0x05, - 0x05, 0xe0, 0x06, 0xc6, 0xef, 0x20, 0xf0, 0x64, 0x03, 0x27, 0xc4, 0x1f, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xa7, - 0x00, 0x93, 0x07, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x3e, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, - 0xaa, 0x87, 0x63, 0x6e, 0xa7, 0x00, 0x13, 0x77, 0x35, 0x00, 0x01, 0x45, 0x11, 0xeb, 0x37, 0x45, 0x20, 0x00, 0x13, - 0x05, 0x05, 0xe0, 0xf1, 0x9b, 0xaa, 0x97, 0x88, 0x43, 0x82, 0x80, 0x01, 0x45, 0x82, 0x80, 0x93, 0x07, 0xb0, 0x1f, - 0x63, 0xec, 0xa7, 0x00, 0x93, 0x77, 0x35, 0x00, 0x81, 0xeb, 0xb7, 0x47, 0x20, 0x00, 0x71, 0x99, 0x93, 0x87, 0x07, - 0xe0, 0x3e, 0x95, 0x0c, 0xc1, 0x82, 0x80, 0x41, 0x11, 0x37, 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, 0xc0, 0x1f, - 0x13, 0x04, 0x05, 0xe0, 0x13, 0x05, 0x05, 0xe0, 0x06, 0xc6, 0xef, 0x20, 0x70, 0x5d, 0xb2, 0x40, 0x23, 0x2e, 0xa4, - 0x1e, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, 0x63, 0x61, 0xa7, 0x02, 0x93, 0x77, 0x35, 0x00, - 0x13, 0x07, 0x50, 0x05, 0x89, 0xef, 0x41, 0x11, 0x06, 0xc6, 0x5d, 0x37, 0xc9, 0x37, 0xb2, 0x40, 0x13, 0x07, 0xa0, - 0x0a, 0x3a, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0x50, 0x05, 0x3a, 0x85, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, - 0xef, 0x00, 0x10, 0x71, 0xb2, 0x40, 0xb7, 0x07, 0x00, 0x02, 0x0d, 0x47, 0xf8, 0xcb, 0x13, 0x05, 0xa0, 0x0a, 0x41, - 0x01, 0x82, 0x80, 0x73, 0x00, 0x50, 0x10, 0x82, 0x80, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, - 0x52, 0xcc, 0x06, 0xd6, 0x2a, 0x84, 0xae, 0x84, 0x32, 0x89, 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x07, 0x39, 0x41, 0x33, - 0x05, 0x34, 0x01, 0x63, 0x6c, 0xfa, 0x02, 0x71, 0x56, 0x93, 0x57, 0x29, 0x00, 0xb3, 0x87, 0xc7, 0x02, 0x93, 0x75, - 0xc9, 0xff, 0x33, 0x05, 0xb4, 0x00, 0xae, 0x94, 0x33, 0x86, 0x27, 0x01, 0x11, 0xc6, 0x9c, 0x40, 0x6c, 0x00, 0x3e, - 0xc6, 0xef, 0x20, 0xd0, 0x56, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, - 0x82, 0x80, 0xb3, 0x87, 0x34, 0x01, 0x9c, 0x43, 0x11, 0x46, 0x6c, 0x00, 0x3e, 0xc6, 0x91, 0x09, 0xef, 0x20, 0xb0, - 0x54, 0x7d, 0xb7, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x52, 0xcc, 0x06, 0xd6, 0x2a, 0x84, - 0xae, 0x84, 0x32, 0x89, 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x07, 0x39, 0x41, 0xb3, 0x85, 0x34, 0x01, 0x63, 0x6d, 0xfa, - 0x02, 0x71, 0x56, 0x93, 0x57, 0x29, 0x00, 0xb3, 0x87, 0xc7, 0x02, 0x93, 0x75, 0xc9, 0xff, 0x2e, 0x94, 0xa6, 0x95, - 0x33, 0x86, 0x27, 0x01, 0x01, 0xca, 0x1c, 0x40, 0x68, 0x00, 0x3e, 0xc6, 0xef, 0x20, 0x30, 0x50, 0xb2, 0x47, 0x1c, - 0xc0, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0x11, 0x46, - 0x68, 0x00, 0xef, 0x20, 0x70, 0x4e, 0x32, 0x47, 0xb3, 0x07, 0x34, 0x01, 0x91, 0x09, 0x98, 0xc3, 0x75, 0xb7, 0x41, - 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x6f, 0x9c, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, - 0x50, 0x05, 0x23, 0xa6, 0xe7, 0xf6, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa8, 0x87, 0xf6, 0x22, 0x44, 0xb2, 0x40, 0xb7, - 0x37, 0x20, 0x00, 0x23, 0x8a, 0x07, 0xa8, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xa4, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, - 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, 0x99, 0x37, 0x35, 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0xa2, 0x85, 0x13, - 0x06, 0xe0, 0x0f, 0x13, 0x05, 0x45, 0xa9, 0x23, 0x8a, 0x07, 0xb8, 0xef, 0x20, 0xf0, 0x47, 0x22, 0x85, 0x22, 0x44, - 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xb2, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x19, - 0xe1, 0xef, 0xe0, 0xcf, 0x95, 0xb7, 0x34, 0x20, 0x00, 0x83, 0xc7, 0x44, 0xb9, 0x99, 0xcb, 0x37, 0x35, 0x20, 0x00, - 0x13, 0x06, 0xe0, 0x0f, 0x93, 0x85, 0x44, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0xef, 0x20, 0x50, 0x44, 0xa2, 0x85, 0x13, - 0x85, 0x44, 0xb9, 0x13, 0x06, 0xe0, 0x0f, 0xef, 0x20, 0x70, 0x43, 0x22, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x92, 0x44, - 0x41, 0x01, 0x6f, 0xf0, 0x1f, 0xae, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0xc7, 0xf6, 0x82, 0x80, 0x41, 0x11, 0x22, - 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0xc4, 0xf6, 0x26, 0xc2, 0x04, 0x40, 0x06, 0xc6, 0x93, 0x07, 0xa0, 0x0a, - 0x63, 0x89, 0xf4, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x37, - 0x35, 0x20, 0x00, 0x13, 0x05, 0x45, 0xb9, 0xef, 0xf0, 0x3f, 0xaa, 0xe3, 0x13, 0x95, 0xfe, 0x93, 0x07, 0x50, 0x05, - 0x1c, 0xc0, 0xc5, 0xb7, 0x37, 0x35, 0x20, 0x00, 0x83, 0x47, 0x45, 0xa9, 0x85, 0xc3, 0xb7, 0x37, 0x20, 0x00, 0x83, - 0xc7, 0x47, 0xb9, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf6, 0x13, 0x05, - 0x45, 0xa9, 0x6f, 0xf0, 0xff, 0xa6, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xdf, - 0x99, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xf5, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, - 0x6d, 0x71, 0x23, 0x26, 0x11, 0x10, 0x23, 0x24, 0x81, 0x10, 0x23, 0x22, 0x91, 0x10, 0xef, 0xf0, 0xdf, 0x98, 0x93, - 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x04, 0x2a, 0x84, 0xef, 0xf0, 0x5f, 0x9c, 0x63, 0x1b, 0x85, 0x06, 0xef, 0xf0, - 0xdf, 0xa1, 0x83, 0x46, 0x05, 0x00, 0x93, 0x07, 0x20, 0x0a, 0x2a, 0x84, 0x63, 0x80, 0xf6, 0x02, 0x37, 0x56, 0x10, - 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x66, 0x93, 0x85, 0xc5, 0x67, 0x13, 0x05, - 0x45, 0x64, 0xef, 0xf0, 0x6f, 0xeb, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xf7, 0x22, 0x85, 0x82, 0x97, 0xef, - 0xf0, 0xff, 0xaa, 0xef, 0xf0, 0xdf, 0xa8, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x14, 0xf5, 0x08, 0xef, 0xf0, - 0x7f, 0x91, 0x63, 0x10, 0x85, 0x08, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xf6, 0x63, 0x94, 0xa7, 0x04, 0x03, - 0x24, 0x81, 0x10, 0x83, 0x20, 0xc1, 0x10, 0x83, 0x24, 0x41, 0x10, 0x51, 0x61, 0x6f, 0xf0, 0x7f, 0xee, 0xef, 0xf0, - 0xbf, 0x97, 0x81, 0x44, 0x63, 0x14, 0x85, 0x00, 0x93, 0x04, 0xc0, 0x07, 0xef, 0xf0, 0x5f, 0x98, 0x93, 0x07, 0xa0, - 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0xdd, 0xd4, 0x0a, 0x85, 0x23, 0x00, 0x91, 0x00, 0xa3, 0x00, 0x01, 0x00, 0xef, 0xf0, - 0x5f, 0xe3, 0x79, 0xbf, 0x93, 0x04, 0xc0, 0x07, 0xf5, 0xb7, 0xb7, 0x35, 0x20, 0x00, 0x83, 0xc7, 0x45, 0xb9, 0x95, - 0xc3, 0x03, 0x24, 0x81, 0x10, 0x83, 0x20, 0xc1, 0x10, 0x83, 0x24, 0x41, 0x10, 0x37, 0x35, 0x20, 0x00, 0x13, 0x06, - 0xe0, 0x0f, 0x93, 0x85, 0x45, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0x51, 0x61, 0x6f, 0x20, 0x30, 0x2a, 0x83, 0x20, 0xc1, - 0x10, 0x03, 0x24, 0x81, 0x10, 0x83, 0x24, 0x41, 0x10, 0x51, 0x61, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x23, 0xa2, - 0x07, 0x00, 0x21, 0x65, 0x6f, 0x20, 0xc0, 0x1c, 0x41, 0x11, 0x21, 0x65, 0x06, 0xc6, 0xef, 0x20, 0x60, 0x1b, 0xb2, - 0x40, 0xb7, 0x07, 0x01, 0x04, 0x05, 0x47, 0xd8, 0xc3, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, - 0x06, 0xc6, 0x93, 0x07, 0x70, 0x02, 0x2a, 0x84, 0xae, 0x84, 0x63, 0xf4, 0xa7, 0x00, 0xef, 0xd0, 0xff, 0xf4, 0x37, - 0x05, 0x01, 0x04, 0x0a, 0x04, 0x13, 0x05, 0x05, 0x10, 0x2a, 0x94, 0x04, 0xc0, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, - 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x13, 0x87, 0x07, 0x10, 0x93, 0x87, 0x07, 0x1a, 0x23, 0x20, 0x07, - 0x00, 0x11, 0x07, 0xe3, 0x1d, 0xf7, 0xfe, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0xc8, 0xcb, 0x82, 0x80, 0x42, 0x05, - 0xb7, 0x07, 0x01, 0x04, 0xc8, 0xcb, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x88, 0x4b, 0x13, 0x75, 0xf5, 0x0f, 0x82, - 0x80, 0x89, 0x67, 0x37, 0x07, 0x01, 0x04, 0x8d, 0x07, 0x1c, 0xc7, 0x23, 0x2a, 0x07, 0x00, 0x82, 0x80, 0x41, 0x11, - 0x06, 0xc6, 0x22, 0xc4, 0x2a, 0x84, 0xad, 0x37, 0xb7, 0x07, 0x01, 0x04, 0x80, 0xcf, 0xc5, 0x37, 0x65, 0x37, 0x22, - 0x44, 0xb2, 0x40, 0x41, 0x01, 0xa9, 0xb7, 0xb7, 0x06, 0x01, 0x04, 0x9c, 0x46, 0x05, 0x45, 0x13, 0xf7, 0x17, 0x00, - 0x1d, 0xc7, 0x13, 0xf7, 0x07, 0x40, 0x0d, 0x45, 0x1d, 0xe3, 0x98, 0x4a, 0x13, 0x77, 0xf7, 0x0f, 0x19, 0xcf, 0x13, - 0xf7, 0x27, 0x20, 0x09, 0x45, 0x19, 0xeb, 0x13, 0xd7, 0xb7, 0x00, 0x05, 0x8b, 0x11, 0x45, 0x11, 0xe7, 0x13, 0xd5, - 0x87, 0x00, 0x13, 0x45, 0x15, 0x00, 0x05, 0x89, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x88, 0xcf, 0x82, 0x80, 0x01, - 0x11, 0x22, 0xcc, 0x06, 0xce, 0x33, 0x07, 0xb6, 0x00, 0x93, 0x07, 0x00, 0x09, 0x2e, 0x84, 0x63, 0xf8, 0xe7, 0x00, - 0x32, 0xc6, 0x2a, 0xc4, 0xef, 0xd0, 0x5f, 0xe7, 0x32, 0x46, 0x22, 0x45, 0xb7, 0x15, 0x01, 0x04, 0xa2, 0x95, 0xef, - 0xf0, 0xdf, 0xbb, 0xf2, 0x40, 0x62, 0x44, 0x13, 0x05, 0xa0, 0x0a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, - 0x26, 0xca, 0x06, 0xce, 0x33, 0x07, 0xb6, 0x00, 0x93, 0x07, 0x00, 0x08, 0xaa, 0x84, 0x2e, 0x84, 0x63, 0xf6, 0xe7, - 0x00, 0x32, 0xc6, 0xef, 0xd0, 0xdf, 0xe3, 0x32, 0x46, 0x37, 0x25, 0x01, 0x04, 0x13, 0x05, 0x05, 0x80, 0x22, 0x95, - 0x62, 0x44, 0xf2, 0x40, 0xa6, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x6f, 0xf0, 0x5f, 0xbe, 0x39, 0x71, 0x2a, 0xd6, 0x2e, - 0xd4, 0x32, 0xd2, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x06, 0x68, - 0x93, 0x85, 0x05, 0x69, 0x13, 0x05, 0x45, 0x69, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x36, 0xd0, 0x3a, - 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xf0, 0xcf, 0xc5, - 0xef, 0xe0, 0xcf, 0xc8, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, - 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, - 0x73, 0x00, 0x20, 0x30, 0x09, 0x65, 0x6f, 0x10, 0x70, 0x7f, 0x09, 0x65, 0x6f, 0x10, 0xd0, 0x7f, 0x41, 0x11, 0x22, - 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xd0, 0x1f, 0xda, 0xdd, 0x37, 0xb7, 0x07, 0x00, 0x07, 0x83, 0x46, - 0x14, 0x00, 0xd8, 0x43, 0x83, 0x47, 0x04, 0x00, 0xa2, 0x06, 0xdd, 0x8e, 0x83, 0x47, 0x24, 0x00, 0xc2, 0x07, 0xdd, - 0x8e, 0x83, 0x47, 0x34, 0x00, 0xe2, 0x07, 0xd5, 0x8f, 0x93, 0x06, 0xf0, 0x0f, 0x63, 0x85, 0xd7, 0x00, 0x61, 0x9b, - 0x9d, 0x8b, 0x5d, 0x8f, 0x93, 0x77, 0x77, 0xff, 0x03, 0x47, 0x44, 0x00, 0x83, 0x46, 0x94, 0x00, 0xb2, 0x40, 0x0e, - 0x07, 0x21, 0x8b, 0x5d, 0x8f, 0xfd, 0x77, 0xbd, 0x07, 0x7d, 0x8f, 0x83, 0x47, 0x54, 0x00, 0x92, 0x07, 0x5d, 0x8f, - 0xb7, 0x17, 0x80, 0xff, 0xfd, 0x17, 0x7d, 0x8f, 0x83, 0x47, 0xa4, 0x00, 0xa2, 0x07, 0xd5, 0x8f, 0xb2, 0x07, 0xb7, - 0xf6, 0x7f, 0x00, 0xf5, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x80, 0xf8, 0x7d, 0x17, 0xf9, 0x8f, 0x03, 0x47, 0x74, 0x00, - 0xb7, 0x06, 0x80, 0x07, 0x5e, 0x07, 0x75, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x00, 0x88, 0x7d, 0x17, 0xf9, 0x8f, 0x03, - 0x47, 0x64, 0x00, 0xb7, 0x06, 0x00, 0x78, 0x22, 0x44, 0x6e, 0x07, 0x75, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x00, 0x07, - 0x5c, 0xc3, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x87, 0xf7, 0x82, 0x80, 0xb7, 0x07, 0x08, - 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, - 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x13, 0x05, 0xa0, 0x0a, 0x89, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, - 0x05, 0x82, 0x80, 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x65, 0xba, 0x6f, 0xf0, - 0xbf, 0x8c, 0x41, 0x11, 0xb7, 0x07, 0x08, 0x05, 0x22, 0xc4, 0x03, 0xa4, 0xc7, 0x20, 0x37, 0x07, 0x00, 0x04, 0x06, - 0xc6, 0x26, 0xc2, 0xb3, 0x76, 0xe4, 0x00, 0x91, 0xca, 0x37, 0x55, 0x10, 0x00, 0x23, 0xa6, 0xe7, 0x20, 0xa5, 0x45, - 0x13, 0x05, 0x85, 0x69, 0xef, 0xf0, 0x4f, 0xb7, 0xb7, 0x07, 0x80, 0x6b, 0xe1, 0x8f, 0x95, 0xcb, 0x37, 0x07, 0x08, - 0x05, 0x23, 0x26, 0xf7, 0x20, 0xb7, 0x07, 0x00, 0x68, 0x7d, 0x8c, 0x93, 0x04, 0x50, 0x05, 0x11, 0xc8, 0x37, 0x55, - 0x10, 0x00, 0x9d, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xf0, 0xaf, 0xb4, 0xef, 0xd0, 0x9f, 0xc5, 0xb2, 0x40, 0x22, - 0x44, 0x26, 0x85, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0xf7, 0x84, 0x43, - 0x13, 0x07, 0xa0, 0x0a, 0x63, 0x96, 0xe4, 0x00, 0x13, 0x07, 0x50, 0x05, 0x98, 0xc3, 0xe1, 0xbf, 0x93, 0x04, 0xa0, - 0x0a, 0xd9, 0xbf, 0x81, 0x47, 0xb7, 0x05, 0x08, 0x05, 0x13, 0x07, 0x00, 0x20, 0xb3, 0x86, 0xb7, 0x00, 0x90, 0x42, - 0xb3, 0x06, 0xf5, 0x00, 0x91, 0x07, 0x90, 0xc2, 0xe3, 0x99, 0xe7, 0xfe, 0x6f, 0xf0, 0xff, 0xf5, 0x41, 0x11, 0x06, - 0xc6, 0x22, 0xc4, 0x2a, 0x84, 0xef, 0xf0, 0x1f, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, - 0xe7, 0xf6, 0x8d, 0x47, 0x33, 0x95, 0x87, 0x00, 0xb7, 0xb7, 0xaa, 0x02, 0x93, 0x87, 0xa7, 0xaa, 0x3d, 0x8d, 0xb7, - 0x07, 0x08, 0x05, 0x23, 0xa4, 0xa7, 0x20, 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, - 0x65, 0xb8, 0xef, 0xf0, 0x2f, 0xfe, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0xf1, 0x41, 0x11, 0x06, - 0xc6, 0xef, 0xf0, 0x9f, 0xef, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf7, 0x37, 0x07, 0x08, 0x05, 0x13, 0x05, - 0x00, 0x20, 0xf9, 0x9b, 0x23, 0x22, 0xf7, 0x20, 0xef, 0x10, 0xd0, 0x5e, 0xb2, 0x40, 0x39, 0x45, 0x41, 0x01, 0x6f, - 0x10, 0xf0, 0x5f, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf7, 0x1c, 0x43, 0x93, 0xf7, 0xf7, 0xfd, 0x1c, 0xc3, - 0x37, 0x07, 0x08, 0x05, 0x23, 0x22, 0xf7, 0x20, 0x82, 0x80, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf7, 0x1c, - 0x43, 0x93, 0xe7, 0x07, 0x02, 0x1c, 0xc3, 0x37, 0x07, 0x08, 0x05, 0x23, 0x22, 0xf7, 0x20, 0x82, 0x80, 0x33, 0x87, - 0xc5, 0x00, 0xb7, 0x07, 0x08, 0x00, 0x63, 0x7c, 0xf7, 0x06, 0x01, 0x11, 0x22, 0xcc, 0x26, 0xca, 0x4e, 0xc6, 0x06, - 0xce, 0x4a, 0xc8, 0x93, 0xf4, 0x35, 0x00, 0xaa, 0x89, 0x2e, 0x84, 0x13, 0x05, 0x50, 0x05, 0x9d, 0xec, 0x32, 0x89, - 0xef, 0xf0, 0x5f, 0xe7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x47, 0xf7, 0xb7, 0x06, 0x08, 0x05, 0xb7, 0x05, 0x00, - 0x05, 0x13, 0x67, 0x27, 0x00, 0x23, 0xa2, 0xe6, 0x20, 0x93, 0x87, 0x47, 0xf7, 0x0d, 0x47, 0x2e, 0x94, 0xb3, 0x06, - 0x99, 0x40, 0x63, 0x60, 0xd7, 0x02, 0x98, 0x43, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x05, 0xa0, 0x0a, 0x23, 0xa2, 0xe7, - 0x20, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, 0xb3, 0x06, 0x94, 0x00, - 0x90, 0x42, 0xb3, 0x86, 0x99, 0x00, 0x91, 0x04, 0x90, 0xc2, 0xf9, 0xb7, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, - 0x11, 0xaa, 0x85, 0x11, 0x46, 0x68, 0x00, 0x06, 0xce, 0xef, 0xf0, 0x1f, 0xf7, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, - 0xf5, 0x00, 0x32, 0x45, 0xf2, 0x40, 0x05, 0x61, 0x82, 0x80, 0x01, 0x45, 0xe5, 0xbf, 0xb7, 0x07, 0x08, 0x00, 0x63, - 0xef, 0xa7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x8d, 0xe3, - 0xae, 0x84, 0xef, 0xf0, 0xbf, 0xdd, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x22, 0x44, 0xb2, 0x40, 0x23, - 0xaa, 0x97, 0x20, 0x92, 0x44, 0x01, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x9f, 0xe7, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, - 0x41, 0x01, 0x82, 0x80, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xaa, 0x84, 0x2e, 0x84, 0x45, - 0x3f, 0x26, 0x85, 0xef, 0xf0, 0xbf, 0xf8, 0x63, 0x09, 0x85, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, - 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xcd, 0xbf, 0x01, 0x11, 0x22, 0xcc, 0x2e, 0xc6, 0x06, - 0xce, 0x2a, 0x84, 0xef, 0xf0, 0x5f, 0xf6, 0xb2, 0x45, 0x63, 0x03, 0xb5, 0x02, 0xfd, 0x57, 0x63, 0x1a, 0xf5, 0x00, - 0x63, 0x8e, 0xa5, 0x00, 0x22, 0x85, 0x62, 0x44, 0xf2, 0x40, 0x05, 0x61, 0x6f, 0xf0, 0xff, 0xfa, 0x13, 0x05, 0x50, - 0x05, 0xf2, 0x40, 0x62, 0x44, 0x05, 0x61, 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xd5, 0xbf, 0xb7, 0x07, 0x08, 0x00, - 0x63, 0xe0, 0xb7, 0x04, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0xf7, 0xf5, 0x1f, 0xaa, 0x84, 0x2e, - 0x84, 0x13, 0x05, 0x50, 0x05, 0x99, 0xef, 0xef, 0xf0, 0xbf, 0xd2, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, - 0x39, 0x45, 0xef, 0xf0, 0x5f, 0xdd, 0x26, 0x85, 0xef, 0xf0, 0xff, 0xda, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, - 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, - 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xfb, 0xb7, 0x00, 0x81, 0x44, 0xf2, 0x40, 0x62, - 0x44, 0x42, 0x49, 0xb2, 0x49, 0x26, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x82, 0x80, 0x93, 0xf4, 0xf5, 0x1f, 0x2e, 0x84, - 0xe5, 0xf4, 0x2a, 0x89, 0xef, 0xf0, 0xff, 0xcc, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x41, 0x45, 0xef, - 0xf0, 0x9f, 0xd7, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x17, 0xf5, 0xfc, 0x37, 0x34, 0x20, 0x00, 0x13, 0x05, 0x44, 0xc9, - 0xef, 0xf0, 0x5f, 0xd4, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x87, 0x07, 0x20, 0x23, 0xa0, 0x07, 0x00, 0x91, 0x07, 0xe3, - 0x9d, 0xe7, 0xfe, 0x93, 0x09, 0x44, 0xc9, 0x03, 0xd6, 0xc9, 0x1f, 0x93, 0x07, 0xc0, 0x1d, 0x63, 0xfa, 0xc7, 0x00, - 0x37, 0x55, 0x10, 0x00, 0x99, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xf0, 0xaf, 0x82, 0x41, 0xbf, 0x93, 0x05, 0x44, - 0xc9, 0x4a, 0x85, 0xef, 0x20, 0x60, 0x43, 0x83, 0xd4, 0xc9, 0x1f, 0x41, 0xb7, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe7, - 0xa7, 0x04, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x13, 0x05, 0x50, - 0x05, 0x9d, 0xe7, 0xef, 0xf0, 0xbf, 0xc4, 0x85, 0x67, 0xb7, 0x04, 0x08, 0x05, 0x93, 0x87, 0x97, 0x82, 0x23, 0xa2, - 0xf4, 0x20, 0x23, 0xac, 0x84, 0x20, 0x39, 0x45, 0xef, 0xf0, 0xbf, 0xce, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, - 0xf7, 0x13, 0x05, 0xa0, 0x0a, 0x23, 0xa2, 0xf4, 0x20, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, - 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x0d, 0x65, 0x01, 0x11, 0x13, 0x05, 0x05, 0x20, 0x06, 0xce, 0x22, 0xcc, 0x26, - 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xef, 0x10, 0xf0, 0x2f, 0x39, 0x45, 0xef, 0x10, 0x50, 0x31, 0x13, 0x05, 0x80, 0x07, - 0x37, 0x39, 0x20, 0x00, 0xef, 0xf0, 0x6f, 0xb9, 0x93, 0x09, 0x49, 0xf7, 0x83, 0xa7, 0x09, 0x00, 0x37, 0x04, 0x08, - 0x05, 0x93, 0x04, 0x04, 0x20, 0xdc, 0xc0, 0xb7, 0x07, 0x46, 0x00, 0x85, 0x07, 0xdc, 0xcc, 0x85, 0x67, 0x93, 0x87, - 0x57, 0x86, 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, 0xdc, 0xc0, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x05, 0xb9, 0xef, - 0xf0, 0xef, 0xc8, 0xb7, 0x07, 0x40, 0x08, 0x9c, 0xc8, 0xdc, 0x40, 0x01, 0x45, 0x13, 0x09, 0x49, 0xf7, 0x93, 0xe7, - 0x07, 0x18, 0x23, 0xa0, 0xf9, 0x00, 0xef, 0xf0, 0x7f, 0xf3, 0x93, 0x07, 0x04, 0x10, 0x98, 0x43, 0xb7, 0x67, 0xa5, - 0xf0, 0x93, 0x87, 0xf7, 0xa0, 0x63, 0x05, 0xf7, 0x02, 0x37, 0x55, 0x10, 0x00, 0x95, 0x45, 0x13, 0x05, 0x85, 0x69, - 0xef, 0xe0, 0xbf, 0xf2, 0x41, 0x67, 0x7d, 0x17, 0x93, 0x07, 0x04, 0x18, 0xb8, 0xd3, 0xf8, 0xd3, 0xb8, 0xd7, 0xf8, - 0xd7, 0xb8, 0xdb, 0xf8, 0xdb, 0xb8, 0xdf, 0xf8, 0xdf, 0x51, 0x45, 0xef, 0xf0, 0x7f, 0xc1, 0xb7, 0x07, 0x08, 0x05, - 0x83, 0xa7, 0xc7, 0x20, 0x91, 0x8b, 0x91, 0xeb, 0x37, 0x55, 0x10, 0x00, 0x91, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, - 0xe0, 0x3f, 0xef, 0xef, 0xd0, 0x1f, 0x80, 0xb7, 0x07, 0x08, 0x05, 0x37, 0x07, 0x40, 0x00, 0x23, 0xa6, 0xe7, 0x20, - 0x03, 0x27, 0x09, 0x00, 0xf2, 0x40, 0x62, 0x44, 0x23, 0xa2, 0xe7, 0x20, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, - 0x61, 0x82, 0x80, 0x85, 0x67, 0x37, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0x86, 0x23, 0x2a, 0xf7, 0xf6, 0x37, 0x37, - 0x20, 0x00, 0x93, 0x07, 0x50, 0x05, 0x23, 0x2c, 0xf7, 0xf6, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2e, 0xf7, 0xf6, 0x6f, - 0xf0, 0xbf, 0xee, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe0, 0xa7, 0x06, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, - 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x13, 0x05, 0x50, 0x05, 0xa1, 0xe3, 0xae, 0x84, 0xef, 0xf0, 0x7f, 0xad, 0xb7, - 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x01, 0x47, 0x93, 0x06, 0x00, 0x20, 0xb3, 0x85, 0xe4, 0x00, 0x8c, 0x41, - 0x33, 0x06, 0xf7, 0x00, 0x11, 0x07, 0x0c, 0xc2, 0xe3, 0x19, 0xd7, 0xfe, 0x7d, 0x57, 0x93, 0x87, 0x07, 0x20, 0xf8, - 0xc3, 0xb8, 0xc7, 0xf8, 0xc7, 0xb8, 0xcb, 0x29, 0x45, 0xef, 0xf0, 0xbf, 0xb5, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, - 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xaa, 0x85, 0x37, 0x05, 0x08, - 0x05, 0x41, 0x46, 0x13, 0x05, 0x05, 0x26, 0x6f, 0xf0, 0x0f, 0xd0, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xef, 0xa7, 0x0a, - 0x01, 0x11, 0x26, 0xca, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x56, - 0xc2, 0xaa, 0x84, 0x13, 0x05, 0x50, 0x05, 0xd9, 0xe7, 0x93, 0x07, 0xc0, 0x1d, 0x32, 0x89, 0x63, 0xe3, 0xc7, 0x08, - 0xb6, 0x89, 0x37, 0x34, 0x20, 0x00, 0x2e, 0x8a, 0xef, 0xf0, 0x5f, 0xa4, 0x13, 0x06, 0x00, 0x20, 0x81, 0x45, 0x13, - 0x05, 0x44, 0xc9, 0xef, 0x20, 0x80, 0x23, 0x4a, 0x86, 0xd2, 0x85, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x00, 0x1f, - 0x4e, 0x85, 0xef, 0xf0, 0xbf, 0xf9, 0x93, 0x0a, 0x44, 0xc9, 0xb7, 0x07, 0x08, 0x05, 0x23, 0x9e, 0x2a, 0x1f, 0x13, - 0x07, 0x44, 0xc9, 0x93, 0x86, 0x07, 0x20, 0x10, 0x43, 0x11, 0x07, 0x90, 0xc3, 0x91, 0x07, 0xe3, 0x9c, 0xd7, 0xfe, - 0x13, 0x06, 0x00, 0x20, 0x81, 0x45, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x80, 0x1f, 0xb7, 0x07, 0x08, 0x05, 0x23, - 0xac, 0x97, 0x20, 0x31, 0x45, 0xef, 0xf0, 0x1f, 0xaa, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0x37, 0x55, - 0x10, 0x00, 0x13, 0x05, 0x85, 0x69, 0x8d, 0x45, 0xef, 0xe0, 0x1f, 0xd8, 0x13, 0x05, 0x50, 0x05, 0xf2, 0x40, 0x62, - 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, - 0x82, 0x80, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xeb, 0xa7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0xf5, - 0x1f, 0x2a, 0x84, 0x89, 0xef, 0xef, 0xf0, 0xdf, 0x99, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x22, 0x44, - 0xb2, 0x40, 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x1f, 0xa4, 0xb2, 0x40, 0x22, 0x44, 0x13, 0x05, 0x50, 0x05, 0x41, - 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x37, 0x04, 0x08, 0x05, - 0x23, 0x2c, 0xa4, 0x20, 0xef, 0xf0, 0x5f, 0x96, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, - 0xf6, 0xb7, 0xb7, 0xaa, 0x02, 0x93, 0x87, 0x67, 0xaa, 0xb2, 0x40, 0x23, 0x24, 0xf4, 0x20, 0x22, 0x44, 0x41, 0x01, - 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xdf, 0x93, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, - 0xac, 0xe7, 0xf6, 0xb2, 0x40, 0xb7, 0xb7, 0xa6, 0x02, 0x37, 0x07, 0x08, 0x05, 0x93, 0x87, 0xa7, 0xaa, 0x23, 0x24, - 0xf7, 0x20, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x3e, 0xcc, 0xb7, 0x07, 0x08, 0x05, 0x3a, 0xce, 0x03, 0xa7, 0xc7, - 0x20, 0x36, 0xd0, 0xb7, 0x06, 0x40, 0x00, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, - 0x32, 0xd2, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0x75, 0x8f, 0x05, 0xcf, 0x23, - 0xa6, 0xd7, 0x20, 0x13, 0x07, 0xa0, 0x0a, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0xe7, 0xf6, 0xf2, 0x50, 0xe2, 0x52, - 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, - 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x03, 0xa7, 0xc7, 0x20, - 0xb7, 0x06, 0x00, 0x08, 0x37, 0x55, 0x10, 0x00, 0x75, 0x8f, 0x0d, 0xc3, 0x23, 0xa6, 0xd7, 0x20, 0x85, 0x45, 0x13, - 0x05, 0x85, 0x69, 0xef, 0xe0, 0x3f, 0xc4, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xae, 0xe7, 0xf6, - 0xef, 0xd0, 0x1f, 0xbf, 0x75, 0xb7, 0x89, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, 0x7f, 0xc2, 0xb7, 0x07, 0x02, - 0x00, 0x73, 0xb0, 0x47, 0x30, 0xe5, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa0, 0xe7, 0xf8, - 0x82, 0x80, 0x99, 0x47, 0x63, 0x05, 0xf5, 0x02, 0x9d, 0x47, 0x63, 0x0b, 0xf5, 0x00, 0x95, 0x47, 0x63, 0x15, 0xf5, - 0x02, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xf7, 0xf7, 0xf7, 0x29, 0xa8, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, - 0xa0, 0x0a, 0x23, 0xa0, 0xe7, 0xf8, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xe7, 0x07, 0x08, 0x7c, - 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf8, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, 0xf7, 0x00, - 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xe7, 0x07, 0x08, 0x7c, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, - 0xa7, 0x07, 0xf8, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, 0xf7, 0x00, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xf7, - 0xf7, 0xf7, 0x7c, 0xc3, 0x82, 0x80, 0x39, 0x71, 0x2a, 0xd6, 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, 0x13, 0x05, 0xc5, - 0x69, 0x85, 0x45, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, - 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0x9f, 0xb6, 0xef, 0xd0, 0x3f, - 0xb2, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, - 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, - 0x30, 0x39, 0x71, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, - 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xf3, 0x25, 0x20, - 0x34, 0xc1, 0x67, 0x37, 0x55, 0x10, 0x00, 0xdd, 0x8d, 0x13, 0x05, 0xc5, 0x69, 0xef, 0xe0, 0x9f, 0xb0, 0xef, 0xd0, - 0x3f, 0xac, 0x01, 0xa0, 0x39, 0x71, 0x2a, 0xd6, 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, 0x13, 0x05, 0xc5, 0x69, 0x89, - 0x45, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, - 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0x3f, 0xad, 0xef, 0xd0, 0xdf, 0xa8, 0xf2, - 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, - 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, - 0x07, 0x01, 0x01, 0xb7, 0x07, 0x00, 0x01, 0x13, 0x07, 0x17, 0x10, 0x98, 0xd3, 0x37, 0x07, 0x03, 0x04, 0x09, 0x07, - 0xd8, 0xd3, 0x13, 0x07, 0x50, 0x60, 0x98, 0xd7, 0x37, 0x17, 0x09, 0x00, 0x13, 0x07, 0x77, 0x80, 0xd8, 0xd7, 0x37, - 0x17, 0x0b, 0x0b, 0x13, 0x07, 0xa7, 0xa0, 0x98, 0xdb, 0x37, 0x17, 0x0c, 0x00, 0x13, 0x07, 0xb7, 0xc0, 0xd8, 0xdb, - 0x37, 0x17, 0x0f, 0x00, 0x13, 0x07, 0xd7, 0xe0, 0x98, 0xdf, 0x05, 0x67, 0xd8, 0xdf, 0xb7, 0x17, 0xff, 0x7f, 0x93, - 0x87, 0x07, 0x80, 0x73, 0xa0, 0x47, 0x30, 0xa1, 0x47, 0x73, 0xa0, 0x07, 0x30, 0x82, 0x80, 0x41, 0x11, 0x3e, 0xc6, - 0xb7, 0x07, 0x40, 0x00, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x3e, - 0xc6, 0xb7, 0x07, 0x80, 0x00, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, - 0x3e, 0xc6, 0xb7, 0x07, 0x00, 0x04, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, - 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x00, 0x20, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, - 0x05, 0x65, 0x6f, 0x10, 0xa0, 0x54, 0x05, 0x65, 0x6f, 0x10, 0x00, 0x55, 0x01, 0x11, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, - 0xc6, 0x06, 0xce, 0x26, 0xca, 0x52, 0xc4, 0x56, 0xc2, 0x9d, 0x47, 0x2a, 0x84, 0xae, 0x89, 0x32, 0x89, 0x63, 0xd4, - 0xc7, 0x00, 0xef, 0xd0, 0x2f, 0xae, 0xef, 0xf0, 0x5f, 0xfd, 0xb7, 0x07, 0x01, 0x07, 0x18, 0x40, 0xdc, 0x43, 0x93, - 0x06, 0xf0, 0x0f, 0x63, 0x05, 0xd7, 0x00, 0xf1, 0x9b, 0x0d, 0x8b, 0xd9, 0x8f, 0x13, 0xf7, 0xb7, 0xff, 0x83, 0x47, - 0x44, 0x00, 0x81, 0x44, 0x31, 0x4a, 0x8a, 0x07, 0x91, 0x8b, 0xd9, 0x8f, 0x37, 0x07, 0x01, 0x07, 0x5c, 0xc3, 0xb7, - 0x1a, 0x01, 0x07, 0x63, 0xcf, 0x24, 0x03, 0x14, 0x40, 0x05, 0x47, 0xad, 0x47, 0x63, 0x9e, 0xe6, 0x00, 0x83, 0x46, - 0x44, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0xbd, 0x47, 0x63, 0x97, 0xe6, 0x00, 0x14, 0x44, 0x37, 0x37, 0x20, 0x00, 0x23, - 0x22, 0xd7, 0xf8, 0xf2, 0x40, 0x62, 0x44, 0x37, 0x07, 0x01, 0x07, 0x5c, 0xc7, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, - 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xb3, 0x85, 0x44, 0x03, 0x13, 0x95, 0x44, 0x00, 0x31, 0x46, 0x56, - 0x95, 0x85, 0x04, 0xce, 0x95, 0xef, 0xf0, 0xcf, 0x81, 0x7d, 0xb7, 0x1d, 0x71, 0x3e, 0xda, 0xb7, 0x07, 0x01, 0x07, - 0xa2, 0xc6, 0x80, 0x47, 0x86, 0xce, 0x96, 0xcc, 0x9a, 0xca, 0x9e, 0xc8, 0xaa, 0xc4, 0xae, 0xc2, 0xb2, 0xc0, 0x36, - 0xde, 0x3a, 0xdc, 0x42, 0xd8, 0x46, 0xd6, 0x72, 0xd4, 0x76, 0xd2, 0x7a, 0xd0, 0x7e, 0xce, 0x93, 0x77, 0xb4, 0x00, - 0x95, 0xc7, 0xb7, 0x07, 0x00, 0x40, 0x73, 0xb0, 0x47, 0x30, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, - 0x55, 0x10, 0x00, 0xa2, 0x86, 0x13, 0x06, 0x06, 0x6a, 0x93, 0x85, 0x85, 0x6a, 0x13, 0x05, 0x45, 0x64, 0xef, 0xe0, - 0xbf, 0x87, 0xef, 0xd0, 0xbf, 0x8a, 0x93, 0x77, 0x44, 0x00, 0x99, 0xcf, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, - 0xf8, 0x91, 0xcb, 0x6c, 0x00, 0x28, 0x00, 0x82, 0x97, 0x22, 0x47, 0xb7, 0x07, 0x01, 0x07, 0x98, 0xcb, 0x32, 0x47, - 0xd8, 0xcb, 0xb7, 0x07, 0x01, 0x07, 0x80, 0xc7, 0x36, 0x44, 0xf6, 0x40, 0xe6, 0x42, 0x56, 0x43, 0xc6, 0x43, 0x26, - 0x45, 0x96, 0x45, 0x06, 0x46, 0xf2, 0x56, 0x62, 0x57, 0xd2, 0x57, 0x42, 0x58, 0xb2, 0x58, 0x22, 0x5e, 0x92, 0x5e, - 0x02, 0x5f, 0xf2, 0x4f, 0x25, 0x61, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x07, 0x02, 0x04, 0xdc, 0x47, 0x13, 0x05, 0xa0, - 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x13, 0x05, 0x00, 0x08, 0x6f, 0x10, 0x40, 0x3d, - 0x13, 0x05, 0x00, 0x08, 0x6f, 0x10, 0x80, 0x3d, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x07, 0xd0, - 0x79, 0x37, 0x04, 0x02, 0x04, 0x5c, 0xc4, 0x85, 0x44, 0x95, 0x65, 0x37, 0x35, 0x10, 0x00, 0x04, 0xc4, 0x93, 0x85, - 0x05, 0xe2, 0x13, 0x05, 0x25, 0x6d, 0xef, 0xe0, 0x7f, 0xca, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x13, 0xf5, 0x02, 0x54, - 0x44, 0x63, 0x82, 0x96, 0x02, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, - 0xc6, 0x6a, 0x93, 0x85, 0x45, 0x6b, 0x13, 0x05, 0x05, 0x62, 0xef, 0xe0, 0x0f, 0xfb, 0x13, 0x05, 0x50, 0x05, 0xb2, - 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xdf, 0xf8, 0xb2, 0x40, - 0xb7, 0x07, 0x02, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x05, 0x45, 0x22, 0xc4, 0x26, - 0xc2, 0x06, 0xc6, 0xef, 0xe0, 0x3f, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa4, 0xe7, 0xf8, - 0x89, 0x46, 0x37, 0x07, 0x02, 0x02, 0x54, 0xc7, 0x13, 0x84, 0x87, 0xf8, 0x93, 0x04, 0x50, 0x05, 0xef, 0xe0, 0x9f, - 0xc2, 0x1c, 0x40, 0xe3, 0x9d, 0x97, 0xfe, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, - 0x02, 0x02, 0xc8, 0xcb, 0x05, 0x47, 0xd8, 0xc7, 0xd8, 0x53, 0x69, 0x8f, 0x63, 0x1e, 0xa7, 0x00, 0xd4, 0x57, 0x7d, - 0x55, 0xf9, 0x8e, 0x91, 0xea, 0x94, 0x57, 0x75, 0x8f, 0x19, 0xe7, 0x88, 0x47, 0x05, 0x89, 0x33, 0x05, 0xa0, 0x40, - 0x82, 0x80, 0x7d, 0x55, 0x82, 0x80, 0x41, 0x45, 0x6f, 0x10, 0x00, 0x2f, 0x41, 0x45, 0x6f, 0x10, 0xe0, 0x2d, 0x01, - 0x11, 0x06, 0xce, 0x22, 0xcc, 0x2a, 0xc6, 0xef, 0xf0, 0x3f, 0xff, 0x13, 0x07, 0x50, 0x05, 0xb7, 0x37, 0x20, 0x00, - 0x23, 0xa4, 0xe7, 0xf8, 0x37, 0x04, 0x02, 0x02, 0xa1, 0x47, 0x5c, 0xc4, 0x32, 0x45, 0x85, 0x47, 0x1c, 0xc8, 0x93, - 0x07, 0x10, 0x40, 0x5c, 0xc0, 0xef, 0xf0, 0xbf, 0xf9, 0xef, 0xf0, 0x9f, 0xf5, 0x23, 0x22, 0x04, 0x00, 0x62, 0x44, - 0xf2, 0x40, 0x05, 0x61, 0x6f, 0xf0, 0x7f, 0xfb, 0x41, 0x11, 0x3a, 0xc6, 0x37, 0x07, 0x02, 0x02, 0x3e, 0xc4, 0x1c, - 0x47, 0x1c, 0xc7, 0x85, 0x8b, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa4, 0xe7, 0xf8, - 0x32, 0x47, 0xa2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0xc7, 0xf8, 0x82, - 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xd0, 0x6f, 0x81, - 0x89, 0x67, 0x63, 0x64, 0xf4, 0x00, 0xef, 0xd0, 0xcf, 0x80, 0x37, 0x27, 0x00, 0x06, 0x85, 0x46, 0x09, 0x46, 0x1c, - 0x47, 0x9d, 0x8b, 0x63, 0x86, 0xd7, 0x00, 0x1c, 0x47, 0x9d, 0x8b, 0xe3, 0x9a, 0xc7, 0xfe, 0x37, 0x05, 0x00, 0x06, - 0x2a, 0x94, 0x08, 0x40, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x65, 0xb7, 0x37, 0x20, 0x00, 0x13, - 0x07, 0x50, 0x05, 0x41, 0x11, 0x13, 0x05, 0x05, 0x80, 0x23, 0xa6, 0xe7, 0xf8, 0x06, 0xc6, 0xef, 0x10, 0xc0, 0x20, - 0xb7, 0x27, 0x00, 0x06, 0x9c, 0x47, 0x05, 0x47, 0x9d, 0x8b, 0xfd, 0x17, 0x63, 0x7b, 0xf7, 0x00, 0x37, 0x55, 0x10, - 0x00, 0x89, 0x45, 0x13, 0x05, 0x85, 0x6b, 0xef, 0xe0, 0xaf, 0xe9, 0xef, 0xc0, 0x9f, 0xfa, 0xb7, 0x07, 0x46, 0x00, - 0xb2, 0x40, 0x37, 0x27, 0x00, 0x06, 0x85, 0x07, 0x5c, 0xcf, 0x85, 0x47, 0x5c, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x37, - 0x27, 0x00, 0x06, 0x1c, 0x47, 0x85, 0x46, 0x9d, 0x8b, 0x63, 0x8a, 0xd7, 0x00, 0x14, 0xcb, 0xb7, 0x26, 0x00, 0x06, - 0x05, 0x47, 0x9c, 0x46, 0x9d, 0x8b, 0xe3, 0x9e, 0xe7, 0xfe, 0xb7, 0x27, 0x00, 0x06, 0x09, 0x47, 0x05, 0x65, 0x98, - 0xcb, 0x13, 0x05, 0x05, 0x80, 0x6f, 0x10, 0x00, 0x1b, 0x05, 0x65, 0x41, 0x11, 0x13, 0x05, 0x05, 0x80, 0x06, 0xc6, - 0xef, 0x10, 0x60, 0x19, 0xb2, 0x40, 0xb7, 0x27, 0x00, 0x06, 0x21, 0x47, 0x98, 0xcb, 0x41, 0x01, 0x82, 0x80, 0x41, - 0x11, 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0xaa, 0x84, 0xef, 0xf0, 0x5f, 0xf1, 0x2a, 0x84, 0x49, 0x22, 0x13, 0x75, - 0xf5, 0x0f, 0xef, 0xe0, 0x1f, 0xa6, 0x26, 0x85, 0xef, 0xf0, 0x3f, 0xf0, 0x63, 0x05, 0xa4, 0x00, 0xef, 0xc0, 0xff, - 0xf1, 0x01, 0x45, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, - 0x4a, 0xd0, 0x4e, 0xce, 0x06, 0xd6, 0x52, 0xcc, 0xaa, 0x89, 0x2e, 0x89, 0x93, 0x74, 0xc6, 0xff, 0x01, 0x44, 0x33, - 0x8a, 0x89, 0x00, 0x33, 0x05, 0x89, 0x00, 0x63, 0x1a, 0x94, 0x00, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, - 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0xef, 0xf0, 0x9f, 0xf9, 0x2a, 0xc6, 0x11, 0x46, 0x6c, 0x00, 0x52, - 0x85, 0xef, 0x10, 0x50, 0x1d, 0x11, 0x04, 0xc9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x1f, 0xf8, 0x2a, 0x87, - 0x85, 0x46, 0x01, 0x45, 0x89, 0x45, 0x01, 0xe7, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x93, 0x77, 0xf7, 0x00, 0x01, - 0x46, 0x81, 0xef, 0x63, 0xd3, 0xc5, 0x00, 0xb6, 0x87, 0x5d, 0x8d, 0x86, 0x06, 0x13, 0x75, 0xf5, 0x0f, 0x93, 0xf6, - 0xf6, 0x0f, 0x11, 0x83, 0xf1, 0xbf, 0x13, 0xf8, 0x17, 0x00, 0x85, 0x83, 0x42, 0x96, 0x93, 0xf7, 0xf7, 0x0f, 0xf1, - 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0xae, 0x84, 0x99, 0xc3, - 0xef, 0xc0, 0x1f, 0xe7, 0x89, 0x67, 0x63, 0x64, 0xf4, 0x00, 0xef, 0xc0, 0x7f, 0xe6, 0xb7, 0x37, 0x20, 0x00, 0x13, - 0x07, 0x50, 0x05, 0x23, 0xa6, 0xe7, 0xf8, 0xb7, 0x27, 0x00, 0x06, 0x84, 0xcf, 0xc0, 0xcb, 0x22, 0x44, 0xb2, 0x40, - 0x92, 0x44, 0x11, 0x47, 0x98, 0xcb, 0x89, 0x65, 0x37, 0x45, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0xe5, - 0x84, 0x41, 0x01, 0x6f, 0xe0, 0xdf, 0xa4, 0x39, 0x71, 0x3a, 0xce, 0x37, 0x27, 0x00, 0x06, 0x3e, 0xcc, 0x1c, 0x47, - 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, - 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xa1, 0x8b, 0x85, 0xcf, 0xa1, 0x47, 0x1c, 0xc7, 0xb7, 0x37, - 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf8, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, - 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, - 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x85, - 0x6b, 0xef, 0xe0, 0x2f, 0xcb, 0xef, 0xd0, 0xcf, 0xc6, 0xe1, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa8, 0xa7, 0xf8, - 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xf9, 0x88, 0x43, 0x37, 0x67, 0x19, 0x00, 0x13, 0x07, 0xd7, - 0x60, 0x33, 0x05, 0xe5, 0x02, 0x37, 0xf7, 0x6e, 0x3c, 0x13, 0x07, 0xf7, 0x35, 0x3a, 0x95, 0x88, 0xc3, 0x82, 0x80, - 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf9, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0x87, 0xf9, 0x9c, 0x4f, 0x13, - 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0xc7, 0xf9, 0x63, 0x84, 0xe7, 0x00, 0x13, 0x05, - 0x50, 0x05, 0x82, 0x80, 0xfd, 0x77, 0xfd, 0x17, 0xe9, 0x8f, 0xb7, 0x26, 0x00, 0x08, 0x2e, 0x87, 0xb2, 0x85, 0x63, - 0x94, 0xd7, 0x02, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0xa7, 0xf8, 0xb7, 0x37, 0x20, 0x00, 0x37, 0x45, 0x10, 0x00, - 0x23, 0xae, 0xe7, 0xf8, 0x13, 0x05, 0x05, 0xaf, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0xe7, 0xf8, 0x6f, 0xe0, 0x5f, - 0x87, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0xa7, 0xf8, 0xb7, 0x37, 0x20, 0x00, - 0x37, 0x45, 0x10, 0x00, 0x23, 0xae, 0x07, 0xf8, 0x13, 0x07, 0x00, 0x10, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x05, 0x80, - 0x3e, 0x13, 0x05, 0x05, 0xaf, 0x23, 0xac, 0xe7, 0xf8, 0x6f, 0xe0, 0x3f, 0x84, 0x37, 0x07, 0x01, 0x02, 0x5c, 0x43, - 0xb7, 0x06, 0x05, 0x00, 0xd5, 0x8f, 0x5c, 0xc3, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0xb7, - 0x27, 0x00, 0x08, 0x37, 0x05, 0x08, 0x00, 0x63, 0x14, 0xf4, 0x00, 0x37, 0x05, 0x04, 0x00, 0xef, 0x00, 0x50, 0x71, - 0x5c, 0x5c, 0x22, 0x85, 0xb2, 0x40, 0x93, 0xe7, 0x37, 0x00, 0x5c, 0xdc, 0x23, 0x2c, 0x04, 0x00, 0x22, 0x44, 0x41, - 0x01, 0x6f, 0xf0, 0x5f, 0xf9, 0x58, 0x5d, 0xaa, 0x87, 0x75, 0x9b, 0x58, 0xdd, 0x37, 0x27, 0x00, 0x08, 0x37, 0x05, - 0x04, 0x00, 0x63, 0x84, 0xe7, 0x00, 0x37, 0x05, 0x08, 0x00, 0x6f, 0x00, 0xd0, 0x6e, 0x79, 0x71, 0x22, 0xd4, 0x26, - 0xd2, 0x4a, 0xd0, 0x06, 0xd6, 0x4e, 0xce, 0x52, 0xcc, 0x56, 0xca, 0x2a, 0x89, 0xae, 0x84, 0x32, 0x84, 0x99, 0xe1, - 0xef, 0xc0, 0x3f, 0xc8, 0x13, 0x0a, 0xa0, 0x0a, 0x91, 0x4a, 0x05, 0xe4, 0x83, 0x27, 0x89, 0x01, 0x37, 0x07, 0x11, - 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x99, 0xc3, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, - 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0xd2, 0x4a, 0x45, 0x61, 0x82, 0x80, 0x13, 0x06, 0x80, 0x3e, 0x85, 0x45, 0x4a, - 0x85, 0xef, 0xf0, 0x7f, 0xee, 0xe3, 0x1f, 0x45, 0xfd, 0x83, 0x27, 0x49, 0x02, 0xa2, 0x89, 0x3e, 0xc6, 0x63, 0xf3, - 0x8a, 0x00, 0x91, 0x49, 0x26, 0x85, 0x4e, 0x86, 0x6c, 0x00, 0xef, 0x10, 0x20, 0x73, 0xce, 0x94, 0x33, 0x04, 0x34, - 0x41, 0x6d, 0xb7, 0x41, 0x11, 0x37, 0x05, 0x02, 0x00, 0x06, 0xc6, 0xef, 0x00, 0xb0, 0x65, 0xb2, 0x40, 0xb7, 0x17, - 0x00, 0x08, 0x37, 0x07, 0x07, 0x00, 0x98, 0xd3, 0x13, 0x05, 0x40, 0x1f, 0x41, 0x01, 0x6f, 0xe0, 0xef, 0xee, 0xb7, - 0x17, 0x00, 0x08, 0x23, 0xa0, 0x07, 0x02, 0x37, 0x05, 0x02, 0x00, 0x6f, 0x00, 0x10, 0x64, 0x39, 0x71, 0x3e, 0xcc, - 0xb7, 0x17, 0x00, 0x08, 0x3a, 0xce, 0x98, 0x57, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, - 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0x05, 0x8b, - 0x05, 0xcb, 0x98, 0x57, 0x13, 0x67, 0x17, 0x00, 0x98, 0xd7, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, - 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, - 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x98, 0x57, 0x09, 0x8b, 0x09, 0xc7, 0x98, 0x57, 0x13, - 0x67, 0x27, 0x00, 0xf1, 0xb7, 0x98, 0x57, 0x11, 0x8b, 0x09, 0xc7, 0x98, 0x57, 0x13, 0x67, 0x47, 0x00, 0x7d, 0xbf, - 0xb7, 0x07, 0x00, 0x01, 0x73, 0xb0, 0x47, 0x30, 0xef, 0xd0, 0xcf, 0xa1, 0x4d, 0xbf, 0x37, 0x07, 0x00, 0x02, 0x5c, - 0x4f, 0xb7, 0x36, 0x20, 0x00, 0x13, 0xf6, 0x77, 0x00, 0xe1, 0x9b, 0x23, 0xa0, 0xc6, 0xfa, 0x93, 0xe7, 0x47, 0x00, - 0x5c, 0xcf, 0x1c, 0x4f, 0xf9, 0x9b, 0x1c, 0xcf, 0x82, 0x80, 0x41, 0x11, 0x26, 0xc2, 0xb7, 0x04, 0x00, 0x02, 0x22, - 0xc4, 0xc0, 0x4c, 0x9c, 0x4c, 0x06, 0xc6, 0x13, 0x05, 0x80, 0x07, 0x93, 0xe7, 0x17, 0x00, 0x9c, 0xcc, 0xef, 0xe0, - 0xaf, 0xe1, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xfa, 0x61, 0x98, 0xb2, 0x40, 0x5d, 0x8c, 0xc0, 0xcc, 0x22, - 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x17, 0x05, 0x01, 0x93, 0x17, 0x85, 0x01, 0xba, 0x97, 0x13, 0x17, - 0x85, 0x00, 0xba, 0x97, 0x3e, 0x95, 0xb7, 0x07, 0x00, 0x04, 0x88, 0xd3, 0xc8, 0xd3, 0x88, 0xd7, 0xc8, 0xd7, 0x88, - 0xdb, 0xc8, 0xdb, 0x88, 0xdf, 0xc8, 0xdf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x00, 0x08, 0x98, 0xd3, - 0x23, 0xa2, 0x07, 0x02, 0x0e, 0x05, 0x23, 0xa4, 0x07, 0x02, 0x42, 0x05, 0x23, 0xa6, 0x07, 0x02, 0x41, 0x81, 0x23, - 0xa8, 0x07, 0x02, 0x13, 0x17, 0x85, 0x00, 0xb7, 0x06, 0xff, 0x00, 0x23, 0xaa, 0x07, 0x02, 0x75, 0x8f, 0x62, 0x05, - 0x23, 0xac, 0x07, 0x02, 0x3a, 0x95, 0xc8, 0xdf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x00, 0x08, 0x98, - 0xd3, 0x23, 0xa2, 0x07, 0x02, 0x23, 0xa4, 0x07, 0x02, 0x23, 0xa6, 0x07, 0x02, 0x23, 0xa8, 0x07, 0x02, 0x23, 0xaa, - 0x07, 0x02, 0x23, 0xac, 0x07, 0x02, 0x23, 0xae, 0x07, 0x02, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x47, - 0xea, 0x82, 0x80, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0x6f, 0xe0, - 0x3f, 0x83, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa2, 0xe7, 0xea, 0xb7, 0x07, 0x00, 0x04, 0xc8, - 0xc3, 0x13, 0x07, 0x90, 0x02, 0x85, 0x65, 0x37, 0x45, 0x10, 0x00, 0x98, 0xc7, 0x93, 0x85, 0x85, 0x38, 0x13, 0x05, - 0x45, 0xdf, 0x6f, 0xe0, 0xaf, 0xd8, 0x41, 0x11, 0x22, 0xc4, 0x01, 0x45, 0x37, 0x34, 0x20, 0x00, 0x06, 0xc6, 0x13, - 0x04, 0x44, 0xe9, 0xef, 0xf0, 0x1f, 0xf2, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0xfb, - 0x48, 0x44, 0xb7, 0x07, 0x02, 0x00, 0x95, 0x07, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0xbf, 0xfa, 0x48, 0x44, 0x7e, - 0x05, 0x13, 0x65, 0x05, 0x05, 0xef, 0xf0, 0xff, 0xf9, 0x48, 0x44, 0xb7, 0x07, 0x00, 0x10, 0x99, 0x07, 0x7e, 0x05, - 0x5d, 0x8d, 0xef, 0xf0, 0xff, 0xf8, 0x48, 0x44, 0xb7, 0x07, 0x01, 0x10, 0x99, 0x07, 0x7e, 0x05, 0x5d, 0x8d, 0xef, - 0xf0, 0xff, 0xf7, 0x22, 0x44, 0xb2, 0x40, 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0xf7, 0x7d, 0x47, 0x63, 0x7e, - 0xb7, 0x04, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0x6f, 0xe0, 0x8f, - 0xf8, 0xb3, 0x06, 0xf5, 0x00, 0x83, 0xc6, 0x06, 0x00, 0x33, 0x07, 0xf1, 0x00, 0x85, 0x07, 0x23, 0x00, 0xd7, 0x00, - 0xe3, 0x97, 0xf5, 0xfe, 0x18, 0x10, 0x93, 0x87, 0x15, 0x00, 0xba, 0x95, 0x13, 0x07, 0x00, 0xf8, 0x23, 0x80, 0xe5, - 0xfe, 0x13, 0x07, 0x00, 0x02, 0x63, 0x92, 0xe7, 0x02, 0x37, 0x05, 0x00, 0x04, 0x8a, 0x85, 0x13, 0x06, 0x00, 0x02, - 0x13, 0x05, 0x05, 0x02, 0xef, 0xe0, 0x8f, 0xf4, 0xb2, 0x50, 0x45, 0x61, 0x82, 0x80, 0x79, 0x71, 0x06, 0xd6, 0x81, - 0x47, 0xd9, 0xb7, 0xb3, 0x06, 0xf1, 0x00, 0x23, 0x80, 0x06, 0x00, 0x85, 0x07, 0xc9, 0xbf, 0x37, 0x55, 0x10, 0x00, - 0x01, 0x11, 0x13, 0x05, 0x45, 0x6c, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x37, - 0x34, 0x20, 0x00, 0xef, 0xf0, 0x1f, 0xed, 0x93, 0x07, 0x44, 0xe9, 0xc8, 0x47, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, - 0xef, 0xf0, 0x3f, 0xed, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x10, 0xf5, 0x2e, 0xaa, 0x84, 0x13, 0x05, 0x00, 0x02, 0xef, - 0xf0, 0x3f, 0xe4, 0x13, 0x04, 0x44, 0xe9, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x1f, 0xeb, - 0xaa, 0x89, 0x63, 0x10, 0x95, 0x2c, 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, - 0xf0, 0xbf, 0xe9, 0xaa, 0x84, 0x63, 0x15, 0x35, 0x2b, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, - 0x9f, 0xe8, 0xaa, 0x89, 0x63, 0x1c, 0x95, 0x28, 0x1c, 0x40, 0x48, 0x44, 0x37, 0x0a, 0x00, 0x04, 0x83, 0xc7, 0x07, - 0x00, 0x7e, 0x05, 0x13, 0x65, 0x15, 0x00, 0x93, 0xe7, 0x07, 0x20, 0x23, 0x2c, 0xfa, 0x00, 0xef, 0xf0, 0x5f, 0xe6, - 0xaa, 0x84, 0x63, 0x1a, 0x35, 0x27, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x3f, 0xe5, 0x2a, - 0x89, 0x63, 0x11, 0x95, 0x26, 0xef, 0xf0, 0x5f, 0xe0, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, - 0xdf, 0xe3, 0xaa, 0x84, 0x63, 0x16, 0x25, 0x25, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x1f, 0xdb, 0x48, 0x44, 0x23, - 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xff, 0xe1, 0x2a, 0x89, 0x63, 0x17, 0x95, 0x22, - 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xdf, 0xe0, 0xaa, 0x84, 0x63, 0x1e, 0x25, 0x21, 0x48, - 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xbf, 0xdf, 0x63, 0x16, 0x95, 0x20, 0x48, 0x44, 0x93, 0x07, - 0x00, 0x10, 0x23, 0x2c, 0xfa, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x15, 0x00, 0xef, 0xf0, 0x3f, 0xde, 0x93, 0x07, 0xa0, - 0x0a, 0xaa, 0x84, 0x63, 0x17, 0xf5, 0x1e, 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, - 0xef, 0xf0, 0x9f, 0xdc, 0xaa, 0x89, 0x63, 0x1c, 0x95, 0x1c, 0xef, 0xf0, 0xbf, 0xd7, 0x48, 0x44, 0x7e, 0x05, 0x13, - 0x65, 0x05, 0x07, 0xef, 0xf0, 0x3f, 0xdb, 0xaa, 0x84, 0x63, 0x11, 0x35, 0x1d, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, - 0x7f, 0xd2, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x5f, 0xd9, 0xaa, - 0x89, 0x63, 0x12, 0x95, 0x1a, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x3f, 0xd8, 0xaa, 0x84, - 0x63, 0x19, 0x35, 0x19, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x1f, 0xd7, 0xaa, 0x89, 0x63, - 0x10, 0x95, 0x18, 0x08, 0x40, 0x05, 0x05, 0xef, 0xf0, 0x1f, 0xd5, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, - 0xef, 0xf0, 0x7f, 0xd5, 0xaa, 0x84, 0x63, 0x13, 0x35, 0x17, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, - 0xf0, 0x5f, 0xd4, 0x2a, 0x89, 0x63, 0x1a, 0x95, 0x14, 0xef, 0xf0, 0x7f, 0xcf, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, - 0x05, 0x07, 0xef, 0xf0, 0xff, 0xd2, 0xaa, 0x84, 0x63, 0x1f, 0x25, 0x13, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x3f, - 0xca, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x1f, 0xd1, 0x63, 0x11, - 0x95, 0x12, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x1f, 0xd0, 0x93, 0x07, 0xa0, 0x0a, 0x2a, - 0x89, 0x63, 0x16, 0xf5, 0x10, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xbf, 0xce, 0xaa, 0x84, - 0x63, 0x1d, 0x25, 0x0f, 0x13, 0x05, 0x10, 0x02, 0xef, 0xf0, 0xff, 0xc5, 0x1c, 0x40, 0x48, 0x44, 0x21, 0x67, 0x83, - 0xc7, 0x07, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xd9, 0x8f, 0x23, 0x20, 0xfa, 0x02, 0xef, 0xf0, 0x3f, 0xcc, - 0xaa, 0x89, 0x63, 0x19, 0x95, 0x0c, 0x48, 0x44, 0x89, 0x64, 0x8d, 0x04, 0x7e, 0x05, 0x45, 0x8d, 0xef, 0xf0, 0xff, - 0xca, 0x2a, 0x89, 0x63, 0x1f, 0x35, 0x0b, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xdf, 0xc9, - 0xaa, 0x89, 0x63, 0x16, 0x25, 0x0b, 0x08, 0x40, 0x13, 0x05, 0x15, 0x02, 0xef, 0xf0, 0xbf, 0xc7, 0x48, 0x44, 0x7e, - 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x1f, 0xc8, 0x2a, 0x89, 0x63, 0x18, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, - 0x45, 0x8d, 0xef, 0xf0, 0x1f, 0xc7, 0xaa, 0x84, 0x63, 0x10, 0x25, 0x09, 0xef, 0xf0, 0x3f, 0xc2, 0x48, 0x44, 0x7e, - 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0xc5, 0x2a, 0x89, 0x63, 0x15, 0x95, 0x06, 0x13, 0x05, 0x00, 0x04, - 0xef, 0xf0, 0xff, 0xbc, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, - 0xc3, 0xaa, 0x84, 0x63, 0x16, 0x25, 0x05, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xbf, 0xc2, - 0x63, 0x1e, 0x95, 0x02, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x52, 0xef, 0xf0, 0xbf, 0xc1, 0x93, 0x07, 0xa0, - 0x0a, 0x63, 0x14, 0xf5, 0x02, 0x08, 0x40, 0x62, 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, - 0xb7, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x06, 0x13, 0x05, 0x15, 0x06, 0x05, 0x61, 0x6f, - 0xe0, 0x0f, 0xbb, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, - 0x01, 0x11, 0x4e, 0xc6, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x52, 0xc4, 0x93, 0x09, 0x00, 0x04, 0x63, - 0xeb, 0xb9, 0x08, 0x37, 0x3a, 0x20, 0x00, 0xaa, 0x84, 0x2e, 0x84, 0x13, 0x09, 0x4a, 0xe9, 0xef, 0xf0, 0xbf, 0xc4, - 0x03, 0x25, 0xc9, 0x00, 0x13, 0x0a, 0x4a, 0xe9, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x7f, 0xba, 0x13, - 0x85, 0x04, 0x02, 0x63, 0x19, 0x34, 0x03, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x05, 0x05, 0x02, 0x13, 0x06, - 0x00, 0x02, 0xef, 0xe0, 0xaf, 0xbb, 0x03, 0x25, 0xc9, 0x00, 0x62, 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, - 0x49, 0x22, 0x4a, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0x05, 0x61, 0x6f, 0xf0, 0x1f, 0xb7, 0xfd, 0x47, 0x63, 0xf8, - 0x87, 0x02, 0x93, 0x05, 0x04, 0xfe, 0xef, 0xf0, 0x5f, 0xbf, 0x13, 0x04, 0x04, 0x04, 0x0e, 0x04, 0x42, 0x04, 0x41, - 0x80, 0x93, 0x17, 0x84, 0x00, 0x37, 0x07, 0xff, 0x00, 0xf9, 0x8f, 0x62, 0x04, 0x3e, 0x94, 0xb7, 0x07, 0x00, 0x04, - 0x03, 0x25, 0xca, 0x00, 0xc0, 0xdf, 0x65, 0xbf, 0x01, 0x45, 0xef, 0xf0, 0x3f, 0xa9, 0xd9, 0xbf, 0xf2, 0x40, 0x62, - 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, 0x37, 0x34, - 0x20, 0x00, 0x93, 0x07, 0x44, 0xe9, 0x52, 0xc4, 0x2a, 0x8a, 0xc8, 0x47, 0x56, 0xc2, 0x06, 0xce, 0x7e, 0x05, 0x13, - 0x65, 0x05, 0x30, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xae, 0x8a, 0xef, 0xf0, 0xff, 0xaf, 0x93, 0x07, 0xa0, 0x0a, - 0x63, 0x11, 0xf5, 0x12, 0xaa, 0x84, 0x13, 0x05, 0x60, 0x03, 0xef, 0xf0, 0x7f, 0xa4, 0x13, 0x04, 0x44, 0xe9, 0x48, - 0x44, 0x7e, 0x05, 0x13, 0x65, 0x45, 0x00, 0xef, 0xf0, 0xdf, 0xad, 0x2a, 0x89, 0x63, 0x11, 0x95, 0x10, 0x48, 0x44, - 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xbf, 0xac, 0xaa, 0x84, 0x63, 0x18, 0x25, 0x0f, 0x48, 0x44, 0x09, - 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x5f, 0xab, 0xaa, 0x89, 0x63, 0x1d, 0x95, 0x0c, - 0xd6, 0x85, 0x52, 0x85, 0xef, 0xf0, 0xdf, 0xec, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xbf, - 0xa9, 0xaa, 0x84, 0x63, 0x10, 0x35, 0x0d, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x03, 0xef, 0xf0, 0x9f, 0xa8, - 0xaa, 0x89, 0x63, 0x17, 0x95, 0x0a, 0x13, 0x05, 0xc0, 0x05, 0xef, 0xf0, 0x5f, 0x9d, 0x48, 0x44, 0x7e, 0x05, 0x13, - 0x65, 0x45, 0x00, 0xef, 0xf0, 0xff, 0xa6, 0xaa, 0x84, 0x63, 0x1a, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, - 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xa5, 0xaa, 0x89, 0x63, 0x11, 0x95, 0x08, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, - 0x32, 0xef, 0xf0, 0xbf, 0xa4, 0xaa, 0x84, 0x63, 0x18, 0x35, 0x07, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, - 0xef, 0xf0, 0x9f, 0xa3, 0x63, 0x10, 0x95, 0x06, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x03, 0xef, 0xf0, 0x9f, - 0xa2, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0x63, 0x15, 0xf5, 0x04, 0x13, 0x05, 0x00, 0x06, 0xef, 0xf0, 0x9f, 0x99, - 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xbf, 0xa0, 0xaa, 0x84, 0x63, 0x18, 0x25, 0x03, 0x48, - 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x9f, 0x9f, 0x63, 0x10, 0x95, 0x02, 0x48, 0x44, 0x62, 0x44, - 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0x05, - 0x61, 0x6f, 0xf0, 0x9f, 0x9d, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, - 0x05, 0x61, 0x82, 0x80, 0x39, 0x71, 0x22, 0xdc, 0x37, 0x34, 0x20, 0x00, 0x06, 0xde, 0x4a, 0xd8, 0x26, 0xda, 0x32, - 0x89, 0x13, 0x04, 0x44, 0xe9, 0xef, 0xf0, 0xdf, 0xe8, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x40, 0xef, 0xf0, - 0x3f, 0x9a, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x0a, 0xaa, 0x84, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, - 0x05, 0xc5, 0x6b, 0xef, 0xf0, 0x9f, 0xe6, 0x85, 0x47, 0x63, 0x07, 0xf9, 0x08, 0x48, 0x44, 0x85, 0x67, 0x93, 0x87, - 0x07, 0x80, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0x5f, 0x97, 0x2a, 0x89, 0x63, 0x1c, 0x95, 0x06, 0xb7, 0x05, 0x00, - 0x04, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x04, 0x68, 0x00, 0xef, 0xe0, 0xef, 0x91, 0x48, 0x44, 0x89, 0x47, - 0x23, 0x06, 0xf1, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x20, 0xef, 0xf0, 0xbf, 0x94, 0xaa, 0x84, 0x63, 0x17, 0x25, - 0x05, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0x9f, 0x93, 0x2a, 0x89, 0x63, 0x1e, 0x95, 0x02, - 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x42, 0xef, 0xf0, 0x7f, 0x92, 0xaa, 0x84, 0x63, 0x15, 0x25, 0x03, 0x68, - 0x00, 0x93, 0x05, 0x10, 0x02, 0xef, 0xf0, 0x5f, 0xdf, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x10, 0xef, 0xf0, - 0xbf, 0x90, 0x63, 0x18, 0x95, 0x00, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xbf, 0x8f, 0xf2, - 0x50, 0x62, 0x54, 0xd2, 0x54, 0x42, 0x59, 0x21, 0x61, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, - 0x13, 0x04, 0x44, 0xe9, 0x08, 0x40, 0x09, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x06, 0xc6, 0xef, - 0xf0, 0xff, 0xf0, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x71, 0xef, 0xf0, 0x5f, 0x8c, 0x48, 0x44, 0x22, 0x44, - 0xb2, 0x40, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0x8b, 0xb7, 0x37, 0x20, 0x00, 0x03, - 0xa5, 0x47, 0xe9, 0x05, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x6f, 0xf0, 0xbf, 0xed, 0x41, 0x11, - 0xb7, 0x55, 0x10, 0x00, 0x37, 0x05, 0x00, 0x04, 0x22, 0xc4, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x45, 0x6c, 0x13, - 0x05, 0x05, 0x02, 0x37, 0x34, 0x20, 0x00, 0x06, 0xc6, 0x13, 0x04, 0x44, 0xe9, 0xef, 0xe0, 0x4f, 0x8a, 0x48, 0x44, - 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0x86, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x1d, 0xf5, 0x00, 0x08, - 0x40, 0x22, 0x44, 0xb2, 0x40, 0x05, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x41, 0x01, 0x6f, 0xf0, - 0xbf, 0xe8, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, - 0x04, 0x44, 0xe9, 0x48, 0x44, 0x06, 0xc6, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xbf, 0x82, 0x08, 0x40, - 0x13, 0x06, 0x00, 0x02, 0x81, 0x45, 0x13, 0x05, 0x15, 0x04, 0xef, 0x00, 0x90, 0x5c, 0x08, 0x40, 0x09, 0x46, 0x81, - 0x45, 0x13, 0x05, 0x15, 0x04, 0xef, 0xf0, 0xbf, 0xe4, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x60, 0xef, 0xf0, - 0x1f, 0x80, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x71, 0xef, 0xf0, 0x4f, 0xff, 0x01, 0x45, 0xef, 0xf0, 0x8f, - 0xf4, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x2f, 0xfe, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, - 0x05, 0x17, 0xef, 0xf0, 0x6f, 0xfd, 0xb2, 0x40, 0x22, 0x44, 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, 0x98, 0xc7, 0x41, - 0x01, 0x82, 0x80, 0x11, 0x65, 0xad, 0xa9, 0x37, 0x35, 0x20, 0x00, 0x41, 0x11, 0x51, 0x46, 0x81, 0x45, 0x13, 0x05, - 0x45, 0xe9, 0x06, 0xc6, 0xef, 0x00, 0xd0, 0x55, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x1d, 0x65, 0x23, - 0xa2, 0xe7, 0xfa, 0xa9, 0x21, 0xb2, 0x40, 0xb7, 0x07, 0x00, 0x04, 0x05, 0x47, 0x98, 0xcb, 0x41, 0x01, 0x6f, 0xf0, - 0xdf, 0xfc, 0x11, 0x65, 0x1d, 0xa9, 0x95, 0x47, 0x63, 0xec, 0xb7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, - 0x00, 0x13, 0x04, 0x44, 0xe9, 0x85, 0x47, 0x5c, 0xc0, 0xb7, 0x57, 0x10, 0x00, 0x0c, 0xc4, 0x93, 0x87, 0x87, 0x6e, - 0x8a, 0x05, 0xbe, 0x95, 0x9c, 0x41, 0x06, 0xc6, 0x08, 0xc0, 0x82, 0x97, 0x08, 0x48, 0xb2, 0x40, 0x23, 0x22, 0x04, - 0x00, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x05, 0x00, 0x04, 0x41, 0x46, - 0x93, 0x85, 0x05, 0x08, 0x6f, 0xd0, 0xff, 0xef, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xe9, 0x89, 0x47, 0x5c, - 0xc3, 0x5c, 0x47, 0x46, 0x05, 0xfe, 0x07, 0xc9, 0x8f, 0x21, 0x65, 0x15, 0x05, 0x5d, 0x8d, 0x6f, 0xf0, 0xef, 0xf1, - 0x39, 0x71, 0x4e, 0xd6, 0x5e, 0xce, 0x62, 0xcc, 0xb7, 0x0b, 0x00, 0x04, 0xb7, 0x39, 0x20, 0x00, 0x05, 0x6c, 0x22, - 0xdc, 0x26, 0xda, 0x4a, 0xd8, 0x56, 0xd2, 0x5a, 0xd0, 0x66, 0xca, 0x6a, 0xc8, 0x06, 0xde, 0x52, 0xd4, 0x2a, 0x84, - 0x2e, 0x8b, 0xb2, 0x8a, 0x81, 0x44, 0x01, 0x49, 0xc1, 0x4c, 0x93, 0x8b, 0x0b, 0x02, 0x93, 0x89, 0x49, 0xe9, 0x09, - 0x0c, 0x37, 0x3d, 0x20, 0x00, 0xb3, 0x05, 0x9b, 0x00, 0x63, 0xe0, 0x54, 0x03, 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, - 0x42, 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, 0xd2, 0x4c, 0x42, 0x4d, 0x21, - 0x61, 0x82, 0x80, 0x33, 0x8a, 0x9a, 0x40, 0x63, 0xd3, 0x4c, 0x01, 0x41, 0x4a, 0x4a, 0x85, 0x2e, 0xc6, 0xef, 0xe0, - 0xcf, 0x9f, 0xb2, 0x45, 0x13, 0x06, 0x3a, 0x00, 0x71, 0x9a, 0x5e, 0x85, 0xef, 0xd0, 0xbf, 0xec, 0x03, 0xa5, 0xc9, - 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xef, 0xe8, 0x03, 0xa5, 0xc9, 0x00, 0x93, 0x17, 0x8a, 0x01, - 0x7e, 0x05, 0x5d, 0x8d, 0x13, 0x65, 0x75, 0x00, 0xef, 0xf0, 0xaf, 0xe7, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x33, - 0x65, 0x85, 0x01, 0xef, 0xf0, 0xcf, 0xe6, 0x03, 0x27, 0x4d, 0xfa, 0x93, 0x07, 0x50, 0x05, 0x63, 0x19, 0xf7, 0x00, - 0x19, 0xc4, 0x22, 0x85, 0x52, 0x86, 0xca, 0x85, 0xef, 0xe0, 0x4f, 0xa3, 0x41, 0x04, 0x93, 0x07, 0x00, 0x07, 0x63, - 0xe3, 0x27, 0x01, 0x41, 0x09, 0xc1, 0x04, 0x9d, 0xb7, 0x39, 0x71, 0x4e, 0xd6, 0x5a, 0xd0, 0x5e, 0xce, 0xb7, 0x39, - 0x20, 0x00, 0x37, 0x0b, 0x02, 0x00, 0x85, 0x6b, 0x26, 0xda, 0x4a, 0xd8, 0x52, 0xd4, 0x56, 0xd2, 0x62, 0xcc, 0x6a, - 0xc8, 0x6e, 0xc6, 0x06, 0xde, 0x22, 0xdc, 0x66, 0xca, 0xaa, 0x8a, 0xae, 0x84, 0x32, 0x8a, 0x01, 0x49, 0x81, 0x4d, - 0x37, 0x3c, 0x20, 0x00, 0x41, 0x4d, 0x93, 0x89, 0x49, 0xe9, 0x1d, 0x0b, 0x93, 0x8b, 0x0b, 0x82, 0xb3, 0x8c, 0x2a, - 0x01, 0x93, 0x07, 0x4c, 0xfa, 0x63, 0x64, 0x49, 0x03, 0xf2, 0x50, 0x62, 0x54, 0x13, 0x07, 0x50, 0x05, 0x98, 0xc3, - 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, 0xd2, 0x4c, 0x42, - 0x4d, 0xb2, 0x4d, 0x21, 0x61, 0x82, 0x80, 0x33, 0x04, 0x2a, 0x41, 0x63, 0x73, 0x8d, 0x00, 0x41, 0x44, 0x6e, 0x85, - 0xef, 0xe0, 0xef, 0x91, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0xfa, 0x98, 0x43, 0x93, 0x07, 0x50, 0x05, 0x63, - 0x19, 0xf7, 0x00, 0x99, 0xc4, 0x26, 0x85, 0x22, 0x86, 0xee, 0x85, 0xef, 0xe0, 0xcf, 0x9b, 0xc1, 0x04, 0x03, 0xa5, - 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x25, 0x00, 0xef, 0xf0, 0x6f, 0xd9, 0x03, 0xa5, 0xc9, 0x00, 0x93, 0x17, 0x84, - 0x01, 0x0d, 0x04, 0x7e, 0x05, 0x5d, 0x8d, 0x33, 0x65, 0x65, 0x01, 0xef, 0xf0, 0x0f, 0xd8, 0x03, 0xa5, 0xc9, 0x00, - 0x7e, 0x05, 0x33, 0x65, 0x75, 0x01, 0xef, 0xf0, 0x2f, 0xd7, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x76, 0xc4, 0xff, 0x93, - 0x85, 0x05, 0x04, 0x66, 0x85, 0xef, 0xd0, 0x3f, 0xd2, 0x93, 0x07, 0x00, 0x06, 0x63, 0xe3, 0xb7, 0x01, 0xc1, 0x0d, - 0x41, 0x09, 0x81, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x2a, 0x84, 0x21, 0x45, 0x06, 0xc6, 0xef, 0xf0, 0x4f, 0xd4, 0x93, - 0x07, 0xa0, 0x0a, 0x63, 0x19, 0xf5, 0x00, 0x22, 0x85, 0xef, 0xf0, 0x1f, 0xdf, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, - 0x07, 0xe8, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa2, 0xa7, 0xfa, 0x82, - 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x60, 0x02, 0x98, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, - 0x98, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0xc8, 0x4b, 0x82, 0x80, 0x39, 0x71, 0x36, 0xd0, 0x3a, 0xce, 0x3e, - 0xcc, 0x05, 0x47, 0xb7, 0x07, 0x00, 0x04, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, - 0x32, 0xd2, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xd8, 0xc7, 0xb7, 0x37, 0x20, - 0x00, 0x93, 0x87, 0x47, 0xe9, 0xd8, 0x43, 0x89, 0x46, 0x7d, 0x17, 0x63, 0xfe, 0xe6, 0x02, 0x37, 0x55, 0x10, 0x00, - 0x85, 0x45, 0x13, 0x05, 0x05, 0x6c, 0xef, 0xd0, 0xef, 0xe0, 0xef, 0xc0, 0x8f, 0xdc, 0xf2, 0x50, 0xe2, 0x52, 0x52, - 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, - 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x13, 0x07, 0xa0, 0x0a, 0x98, - 0xcb, 0xd1, 0xbf, 0xb7, 0x07, 0x01, 0x02, 0x88, 0xd7, 0xcc, 0xd7, 0x88, 0xdb, 0xcc, 0xdb, 0x88, 0xdf, 0xcc, 0xdf, - 0x82, 0x80, 0x01, 0x11, 0x26, 0xca, 0xb7, 0x04, 0x01, 0x02, 0x22, 0xcc, 0xc0, 0x40, 0xf5, 0x77, 0x93, 0x87, 0xf7, - 0xa5, 0x7d, 0x8c, 0x89, 0x67, 0x93, 0x87, 0x07, 0x1a, 0x06, 0xce, 0x4a, 0xc8, 0x4e, 0xc6, 0xc1, 0x8f, 0xaa, 0x89, - 0xdc, 0xc0, 0x05, 0x45, 0x2e, 0x89, 0xef, 0xd0, 0xbf, 0x99, 0x93, 0x67, 0x04, 0x40, 0xdc, 0xc0, 0x05, 0x45, 0xef, - 0xd0, 0xff, 0x98, 0x85, 0x67, 0x93, 0x87, 0x07, 0x40, 0x5d, 0x8c, 0xc0, 0xc0, 0xb7, 0x47, 0x00, 0x08, 0x23, 0xa4, - 0x07, 0x00, 0xb7, 0x57, 0x00, 0x08, 0x23, 0xa4, 0x07, 0x00, 0xf2, 0x40, 0x62, 0x44, 0x23, 0xa0, 0x34, 0x03, 0x23, - 0xa2, 0x24, 0x03, 0xb2, 0x49, 0xd2, 0x44, 0x42, 0x49, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x02, 0x88, 0x53, - 0xcc, 0x53, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x02, 0x88, 0x47, 0x21, 0x81, 0x13, 0x75, 0xf5, 0x0f, 0x82, 0x80, 0x41, - 0x11, 0x01, 0x45, 0x81, 0x45, 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0xef, 0xf0, 0x1f, 0xf6, 0xef, 0xf0, 0x9f, 0xfd, - 0xaa, 0x84, 0x2e, 0x84, 0x2a, 0x87, 0xae, 0x86, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, - 0x00, 0x93, 0x85, 0x85, 0x71, 0x13, 0x05, 0x45, 0x64, 0x13, 0x06, 0x06, 0x70, 0xef, 0xd0, 0xaf, 0xc9, 0xa2, 0x85, - 0x22, 0x44, 0xb2, 0x40, 0x26, 0x85, 0x92, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xf3, 0x39, 0x71, 0x06, 0xde, 0x16, - 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, - 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xf0, 0x7f, 0xf9, 0xef, 0xc0, 0x4f, 0xc9, 0xf2, - 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, - 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, - 0x07, 0x00, 0x02, 0x5c, 0x47, 0xc9, 0x8f, 0x5c, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0xd8, 0x47, 0x13, 0x45, - 0xf5, 0xff, 0x79, 0x8d, 0xc8, 0xc7, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x4f, 0xc9, 0x8f, 0x1c, 0xcf, 0x82, - 0x80, 0xb7, 0x07, 0x00, 0x02, 0x98, 0x4f, 0x13, 0x45, 0xf5, 0xff, 0x79, 0x8d, 0x88, 0xcf, 0x82, 0x80, 0xb7, 0x07, - 0x00, 0x02, 0xc8, 0xcb, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x47, 0x00, 0x1c, 0xc7, 0xb7, - 0x07, 0x00, 0x03, 0x94, 0x4b, 0x37, 0x37, 0x20, 0x00, 0x23, 0x24, 0xd7, 0xfa, 0x23, 0xa8, 0x07, 0x00, 0x82, 0x80, - 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0xb7, 0x06, 0x00, 0x03, 0xf9, 0x9b, 0x1c, 0xc7, 0x37, 0x07, 0x08, 0x00, 0x9c, - 0x46, 0xf9, 0x8f, 0xf5, 0xff, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x17, 0x00, 0x1c, 0xc7, - 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x87, 0xfa, 0xb7, 0x07, 0x00, 0x03, 0x98, 0xcb, 0x82, 0x80, 0xb7, 0x37, 0x20, - 0x00, 0x03, 0xa5, 0xc7, 0xfa, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0xb7, 0x27, 0x03, 0x04, 0x9c, 0x47, - 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x13, 0x05, 0x00, 0x10, 0x6f, - 0xf0, 0x3f, 0xf4, 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0x41, 0x11, 0x37, 0x37, - 0x20, 0x00, 0x23, 0x28, 0xf7, 0xfa, 0x06, 0xc6, 0xef, 0xf0, 0x1f, 0xfe, 0xb7, 0x27, 0x03, 0x04, 0x09, 0x47, 0xd8, - 0xc3, 0x37, 0x17, 0x03, 0x04, 0xb7, 0x07, 0x03, 0x04, 0x13, 0x07, 0x07, 0x80, 0x23, 0xa0, 0x07, 0x00, 0x91, 0x07, - 0xe3, 0x9d, 0xe7, 0xfe, 0xb7, 0x27, 0x03, 0x04, 0x0d, 0x47, 0xd8, 0xc7, 0x98, 0x47, 0x85, 0x47, 0x13, 0x05, 0xa0, - 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x00, 0x10, - 0x6f, 0xf0, 0xff, 0xee, 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0x37, 0x37, 0x20, - 0x00, 0x23, 0x28, 0xf7, 0xfa, 0xb7, 0x27, 0x03, 0x04, 0x05, 0x47, 0xd8, 0xc3, 0x82, 0x80, 0xc2, 0x05, 0xc9, 0x8d, - 0x93, 0xe5, 0x05, 0x10, 0xb7, 0x07, 0x03, 0x04, 0x23, 0xa0, 0xb7, 0x10, 0x82, 0x80, 0xc2, 0x05, 0xc9, 0x8d, 0x11, - 0x65, 0x13, 0x05, 0x05, 0x50, 0xc9, 0x8d, 0xb7, 0x07, 0x03, 0x04, 0x23, 0xa0, 0xb7, 0x10, 0x82, 0x80, 0x41, 0x11, - 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xb0, 0x9f, 0xc4, 0x37, 0x15, 0x03, - 0x04, 0x2a, 0x94, 0x08, 0x40, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x79, 0x71, 0x26, 0xd2, 0x4a, 0xd0, - 0x4e, 0xce, 0x06, 0xd6, 0x22, 0xd4, 0xaa, 0x84, 0x2e, 0x89, 0xb2, 0x89, 0x19, 0xe1, 0xef, 0xb0, 0x1f, 0xc2, 0x93, - 0x77, 0x39, 0x00, 0x99, 0xc3, 0xef, 0xb0, 0x7f, 0xc1, 0x01, 0x44, 0x63, 0x69, 0x34, 0x01, 0xb2, 0x50, 0x22, 0x54, - 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x45, 0x61, 0x82, 0x80, 0x33, 0x05, 0x24, 0x01, 0xef, 0xf0, 0x5f, 0xfa, 0x2a, - 0xc6, 0x11, 0x46, 0x33, 0x85, 0x84, 0x00, 0x6c, 0x00, 0xcd, 0x2d, 0x11, 0x04, 0xe1, 0xbf, 0x79, 0x71, 0x22, 0xd4, - 0x4a, 0xd0, 0x4e, 0xce, 0x56, 0xca, 0x06, 0xd6, 0x26, 0xd2, 0x52, 0xcc, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0xae, - 0x89, 0x32, 0x89, 0x93, 0x7a, 0xc6, 0xff, 0x99, 0xc3, 0xef, 0xb0, 0x7f, 0xbc, 0x37, 0x0a, 0x03, 0x04, 0x81, 0x44, - 0x22, 0x9a, 0x63, 0xe9, 0x54, 0x03, 0x13, 0x76, 0x39, 0x00, 0x01, 0xce, 0xb3, 0x85, 0x99, 0x00, 0x68, 0x00, 0x02, - 0xc6, 0x7d, 0x25, 0xb2, 0x47, 0x37, 0x05, 0x03, 0x04, 0x2a, 0x94, 0x26, 0x94, 0x1c, 0xc0, 0xb2, 0x50, 0x22, 0x54, - 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0xd2, 0x4a, 0x45, 0x61, 0x82, 0x80, 0x63, 0x94, 0x09, 0x00, 0xef, - 0xb0, 0x5f, 0xb8, 0xb3, 0x85, 0x99, 0x00, 0x11, 0x46, 0x68, 0x00, 0xbd, 0x2d, 0x32, 0x47, 0xb3, 0x07, 0x9a, 0x00, - 0x91, 0x04, 0x98, 0xc3, 0x4d, 0xbf, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x41, 0x11, 0x13, 0x05, 0x45, 0xb5, 0x06, - 0xc6, 0x22, 0xc4, 0xef, 0xd0, 0xef, 0xe9, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0f, 0xf5, 0x00, 0x37, 0x55, 0x10, 0x00, - 0x85, 0x45, 0x13, 0x05, 0x05, 0x72, 0xef, 0xd0, 0x2f, 0xa3, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x41, - 0x01, 0x82, 0x80, 0xb7, 0x17, 0x03, 0x04, 0x83, 0xa7, 0x07, 0x10, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, 0xfb, - 0x93, 0xf7, 0xf7, 0x0f, 0x81, 0xe7, 0x1c, 0x40, 0x63, 0x9d, 0xa7, 0x00, 0x37, 0x55, 0x10, 0x00, 0x8d, 0x45, 0x13, - 0x05, 0x05, 0x72, 0xef, 0xd0, 0xcf, 0x9f, 0x93, 0x07, 0xa0, 0x0a, 0x1c, 0xc0, 0xd1, 0xb7, 0xb7, 0x37, 0x20, 0x00, - 0x03, 0xa7, 0xc7, 0xfa, 0x13, 0x84, 0xc7, 0xfa, 0x63, 0x09, 0xa7, 0x00, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, 0x13, - 0x05, 0x05, 0x72, 0xef, 0xd0, 0x6f, 0x9d, 0x08, 0x40, 0x5d, 0xb7, 0x37, 0x95, 0x04, 0x00, 0x13, 0x05, 0x05, 0x3e, - 0x6f, 0xf0, 0xff, 0xf6, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x5f, 0xe6, 0xef, 0xf0, 0x1f, 0xe3, 0xb2, 0x40, 0x41, - 0x01, 0x6f, 0xf0, 0x5f, 0xfe, 0xb7, 0x17, 0x03, 0x04, 0x03, 0xa5, 0x07, 0x10, 0x41, 0x81, 0x82, 0x80, 0x41, 0x11, - 0x3a, 0xc4, 0x37, 0x27, 0x03, 0x04, 0x3e, 0xc2, 0x1c, 0x47, 0x36, 0xc6, 0x93, 0xf6, 0x27, 0x00, 0x89, 0xca, 0x89, - 0x46, 0x14, 0xc7, 0x37, 0x37, 0x20, 0x00, 0x93, 0x06, 0xa0, 0x0a, 0x23, 0x26, 0xd7, 0xfa, 0x91, 0x8b, 0x99, 0xcf, - 0xb7, 0x27, 0x03, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x93, 0x07, 0xa0, 0x0a, 0x37, 0x37, 0x20, 0x00, 0x23, 0x28, 0xf7, - 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0xb2, 0x46, 0x22, 0x47, 0x92, 0x47, 0x41, 0x01, 0x73, 0x00, - 0x20, 0x30, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x04, 0x00, 0x03, 0x1c, 0x48, 0x06, 0xc6, 0xdd, 0x9b, 0x1c, 0xc8, 0xef, - 0xe0, 0x0f, 0xd9, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x02, 0x5c, 0xcc, 0xb2, 0x40, 0x22, 0x44, 0xb7, 0x37, - 0x20, 0x00, 0x23, 0x8c, 0x07, 0xfa, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x2a, 0x84, 0x21, 0x45, 0x06, - 0xc6, 0xef, 0xf0, 0x7f, 0xca, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x7f, 0xc6, 0x22, 0x04, 0x13, 0x64, 0x04, 0x03, - 0x37, 0x07, 0x00, 0x03, 0x40, 0xc3, 0xb2, 0x40, 0x22, 0x44, 0xc1, 0x67, 0x93, 0x87, 0xa7, 0xfa, 0x1c, 0xcf, 0x41, - 0x01, 0x82, 0x80, 0x41, 0x11, 0x26, 0xc2, 0xaa, 0x84, 0x09, 0x45, 0x22, 0xc4, 0x06, 0xc6, 0x2e, 0x84, 0xef, 0xf0, - 0x1f, 0xfc, 0x37, 0x07, 0x20, 0x00, 0xb7, 0x07, 0x00, 0x03, 0x13, 0x07, 0x07, 0x02, 0xd8, 0xcf, 0x37, 0x37, 0x20, - 0x00, 0x23, 0x2a, 0x97, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2e, 0x87, 0xfa, 0xb2, 0x40, 0x22, 0x44, 0x05, 0x47, - 0x98, 0xcb, 0x37, 0x07, 0x08, 0x00, 0x98, 0xc7, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x03, 0x9c, - 0x47, 0x37, 0x07, 0x04, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, - 0x37, 0x07, 0x00, 0x03, 0x5c, 0x53, 0x13, 0x05, 0x50, 0x05, 0x93, 0x96, 0x07, 0x01, 0xc1, 0x82, 0xc1, 0x83, 0x63, - 0x97, 0xf6, 0x00, 0x1c, 0x47, 0x91, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, - 0xef, 0xf0, 0xff, 0xf1, 0x37, 0x07, 0x00, 0x03, 0x5c, 0x47, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc7, 0x5c, 0x47, 0x85, - 0x8b, 0xf5, 0xff, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xfb, 0x95, 0xc3, - 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x5f, 0xef, 0xb7, 0x07, 0x00, 0x03, 0x98, 0x4b, 0xb2, 0x40, 0x13, 0x67, 0x87, - 0x00, 0x98, 0xcb, 0x37, 0x07, 0x08, 0x00, 0x98, 0xc7, 0x41, 0x01, 0x6f, 0xe0, 0xcf, 0xc5, 0x82, 0x80, 0x37, 0x07, - 0x00, 0x03, 0x1c, 0x4b, 0xf9, 0x9b, 0x1c, 0xcb, 0x82, 0x80, 0xb7, 0x06, 0x00, 0x03, 0xdc, 0x42, 0x7d, 0x77, 0x13, - 0x07, 0xf7, 0x0f, 0xf9, 0x8f, 0x05, 0x67, 0x22, 0x05, 0x13, 0x07, 0x07, 0xf0, 0x79, 0x8d, 0x5d, 0x8d, 0xc8, 0xc2, - 0x82, 0x80, 0x1d, 0x71, 0x3a, 0xda, 0x37, 0x07, 0x00, 0x03, 0x3e, 0xd8, 0x1c, 0x47, 0x86, 0xce, 0x96, 0xcc, 0x9a, - 0xca, 0x9e, 0xc8, 0xa2, 0xc6, 0xa6, 0xc4, 0xaa, 0xc2, 0xae, 0xc0, 0x32, 0xde, 0x36, 0xdc, 0x42, 0xd6, 0x46, 0xd4, - 0x4a, 0xd2, 0x4e, 0xd0, 0x72, 0xce, 0x76, 0xcc, 0x7a, 0xca, 0x7e, 0xc8, 0x85, 0x8b, 0xa1, 0xc7, 0x04, 0x57, 0x11, - 0x44, 0x37, 0x39, 0x20, 0x00, 0x83, 0x27, 0x49, 0xfb, 0x13, 0xf5, 0xf4, 0x0f, 0x7d, 0x14, 0x82, 0x97, 0xa1, 0x80, - 0x6d, 0xf8, 0x36, 0x44, 0xf6, 0x40, 0xe6, 0x42, 0x56, 0x43, 0xc6, 0x43, 0xa6, 0x44, 0x16, 0x45, 0x86, 0x45, 0x72, - 0x56, 0xe2, 0x56, 0x52, 0x57, 0xc2, 0x57, 0x32, 0x58, 0xa2, 0x58, 0x12, 0x59, 0x82, 0x59, 0x72, 0x4e, 0xe2, 0x4e, - 0x52, 0x4f, 0xc2, 0x4f, 0x25, 0x61, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xc7, 0x87, 0xfb, 0x13, - 0x84, 0x87, 0xfb, 0x05, 0xeb, 0xb7, 0x04, 0x00, 0x03, 0x37, 0x39, 0x20, 0x00, 0x93, 0x09, 0xa0, 0x0a, 0x9c, 0x44, - 0x91, 0x8b, 0xd5, 0xfb, 0x83, 0x27, 0xc9, 0xfb, 0x68, 0x00, 0x82, 0x97, 0x63, 0x0d, 0x35, 0x01, 0x85, 0x47, 0x23, - 0x00, 0xf4, 0x00, 0xc1, 0x67, 0x93, 0x87, 0x07, 0x02, 0xdc, 0xcc, 0x61, 0xbf, 0xef, 0xf0, 0x5f, 0xdf, 0x49, 0xbf, - 0xb2, 0x47, 0x9c, 0xd8, 0xd1, 0xbf, 0x5c, 0x41, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc1, 0x82, 0x80, 0x5c, 0x41, 0xf9, - 0x9b, 0x5c, 0xc1, 0x82, 0x80, 0x5c, 0x41, 0xf5, 0x9b, 0xd1, 0x8f, 0x5c, 0xc1, 0x14, 0xc9, 0x4c, 0xc9, 0x82, 0x80, - 0x5c, 0x45, 0xcd, 0x8f, 0x5c, 0xc5, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x07, 0xfc, 0x82, 0x80, 0x39, - 0x71, 0x3a, 0xce, 0x37, 0x07, 0x10, 0x01, 0x3e, 0xcc, 0x1c, 0x47, 0x58, 0x47, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, - 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, - 0xc2, 0x7e, 0xc0, 0xf9, 0x8f, 0x91, 0xcf, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xfc, 0x98, 0x43, 0x05, 0x07, - 0x98, 0xc3, 0xb7, 0x07, 0x10, 0x01, 0x98, 0x47, 0x0d, 0x8b, 0x98, 0xc7, 0x19, 0xa8, 0xb7, 0x07, 0x20, 0x01, 0x98, - 0x47, 0xdc, 0x47, 0x7d, 0x8f, 0xb7, 0x07, 0x20, 0x01, 0x6d, 0xf7, 0xef, 0xb0, 0xff, 0xe6, 0xf2, 0x50, 0xe2, 0x52, - 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, - 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x1c, 0x41, 0x63, 0xf7, - 0xb7, 0x00, 0x23, 0x80, 0xc7, 0x00, 0x1c, 0x41, 0x85, 0x07, 0x1c, 0xc1, 0x82, 0x80, 0x1d, 0x71, 0xa2, 0xcc, 0xa6, - 0xca, 0xca, 0xc8, 0x86, 0xce, 0xce, 0xc6, 0xd2, 0xc4, 0xd6, 0xc2, 0xda, 0xc0, 0x5e, 0xde, 0x62, 0xdc, 0x66, 0xda, - 0x6a, 0xd8, 0x6e, 0xd6, 0x2a, 0xc6, 0x2e, 0x84, 0x32, 0x89, 0xb6, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x0f, 0xf6, 0x63, - 0x14, 0x09, 0x00, 0xef, 0xb0, 0x8f, 0xf5, 0x01, 0x45, 0x05, 0xc4, 0xb2, 0x4a, 0x7d, 0x14, 0x25, 0x4a, 0x56, 0x94, - 0x93, 0x0c, 0xc0, 0x06, 0x13, 0x0b, 0x30, 0x07, 0xa9, 0x4b, 0x1d, 0x4d, 0x03, 0x46, 0x09, 0x00, 0x15, 0xe6, 0xb2, - 0x47, 0x23, 0x80, 0x07, 0x00, 0x32, 0x45, 0x33, 0x05, 0x55, 0x41, 0xf6, 0x40, 0x66, 0x44, 0xd6, 0x44, 0x46, 0x49, - 0xb6, 0x49, 0x26, 0x4a, 0x96, 0x4a, 0x06, 0x4b, 0xf2, 0x5b, 0x62, 0x5c, 0xd2, 0x5c, 0x42, 0x5d, 0xb2, 0x5d, 0x25, - 0x61, 0x82, 0x80, 0x93, 0x07, 0x50, 0x02, 0x63, 0x1f, 0xf6, 0x02, 0x93, 0x07, 0x19, 0x00, 0x83, 0xc6, 0x07, 0x00, - 0x3e, 0x89, 0x85, 0x07, 0x13, 0x87, 0x06, 0xfd, 0x13, 0x77, 0xf7, 0x0f, 0xe3, 0x78, 0xea, 0xfe, 0x63, 0x93, 0x96, - 0x01, 0x3e, 0x89, 0x03, 0x46, 0x09, 0x00, 0x63, 0x06, 0x66, 0x0d, 0x63, 0x60, 0xcb, 0x02, 0x93, 0x07, 0x30, 0x06, - 0x63, 0x05, 0xf6, 0x06, 0x93, 0x07, 0x40, 0x06, 0x63, 0x0c, 0xf6, 0x06, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, - 0xf2, 0xa6, 0x89, 0x95, 0xa0, 0x93, 0x07, 0x50, 0x07, 0x63, 0x02, 0xf6, 0x06, 0x93, 0x07, 0x80, 0x07, 0xe3, 0x14, - 0xf6, 0xfe, 0x98, 0x40, 0x93, 0x89, 0x44, 0x00, 0x81, 0x46, 0x37, 0x06, 0x00, 0xf0, 0xb3, 0x75, 0xc7, 0x00, 0xba, - 0x84, 0x36, 0x8c, 0x12, 0x07, 0x85, 0x06, 0x89, 0xe5, 0xe3, 0x99, 0xa6, 0xff, 0x1d, 0x4c, 0xba, 0x84, 0xa1, 0x4d, - 0x13, 0xd7, 0xc4, 0x01, 0x63, 0x74, 0xea, 0x08, 0x13, 0x06, 0x77, 0x05, 0xa2, 0x85, 0x68, 0x00, 0x05, 0x0c, 0xef, - 0xf0, 0x1f, 0xee, 0x92, 0x04, 0xe3, 0x14, 0xbc, 0xff, 0x09, 0xa8, 0x03, 0xc6, 0x04, 0x00, 0xa2, 0x85, 0x68, 0x00, - 0x93, 0x89, 0x44, 0x00, 0xef, 0xf0, 0x9f, 0xec, 0x05, 0x09, 0xce, 0x84, 0x31, 0xbf, 0x5c, 0x08, 0x98, 0x40, 0x93, - 0x89, 0x44, 0x00, 0x3e, 0x8c, 0x81, 0x44, 0xb3, 0x76, 0x77, 0x03, 0x85, 0x04, 0x85, 0x07, 0x93, 0x86, 0x06, 0x03, - 0xa3, 0x8f, 0xd7, 0xfe, 0xba, 0x86, 0x33, 0x57, 0x77, 0x03, 0xe3, 0x65, 0xda, 0xfe, 0xfd, 0x5d, 0xfd, 0x14, 0xe3, - 0x88, 0xb4, 0xfd, 0xb3, 0x07, 0x9c, 0x00, 0x03, 0xc6, 0x07, 0x00, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0x5f, 0xe8, - 0xed, 0xb7, 0x93, 0x89, 0x44, 0x00, 0x84, 0x40, 0x03, 0xc6, 0x04, 0x00, 0x45, 0xda, 0xa2, 0x85, 0x68, 0x00, 0xef, - 0xf0, 0xff, 0xe6, 0x85, 0x04, 0xc5, 0xbf, 0x13, 0x06, 0x07, 0x03, 0xb5, 0xbf, 0x41, 0x11, 0x26, 0xc2, 0xb7, 0x34, - 0x20, 0x00, 0x2a, 0x86, 0xae, 0x86, 0x13, 0x85, 0x84, 0xea, 0x93, 0x05, 0x00, 0x08, 0x06, 0xc6, 0x22, 0xc4, 0xef, - 0xf0, 0xbf, 0xe5, 0x2a, 0x84, 0x13, 0x85, 0x84, 0xea, 0xef, 0xd0, 0x8f, 0x9b, 0xb2, 0x40, 0x22, 0x85, 0x22, 0x44, - 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x26, 0xca, 0xb7, 0x34, 0x20, 0x00, 0x2e, 0xd2, 0x32, 0xd4, 0x36, - 0xd6, 0x2a, 0x86, 0x54, 0x10, 0x93, 0x05, 0x00, 0x08, 0x13, 0x85, 0x84, 0xea, 0x06, 0xce, 0x22, 0xcc, 0x3a, 0xd8, - 0x3e, 0xda, 0x42, 0xdc, 0x46, 0xde, 0x36, 0xc6, 0xef, 0xf0, 0x9f, 0xe1, 0x2a, 0x84, 0x13, 0x85, 0x84, 0xea, 0xef, - 0xd0, 0x6f, 0x97, 0xf2, 0x40, 0x22, 0x85, 0x62, 0x44, 0xd2, 0x44, 0x21, 0x61, 0x82, 0x80, 0x22, 0x05, 0x61, 0x77, - 0x2d, 0x8d, 0xa1, 0x47, 0x15, 0x07, 0x93, 0x16, 0x05, 0x01, 0x06, 0x05, 0x42, 0x05, 0xc1, 0x86, 0x41, 0x81, 0x63, - 0xd5, 0x06, 0x00, 0x39, 0x8d, 0x42, 0x05, 0x41, 0x81, 0xfd, 0x17, 0xe5, 0xf7, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, - 0x26, 0xc2, 0x2a, 0x84, 0xb3, 0x04, 0xb5, 0x00, 0x06, 0xc6, 0x01, 0x45, 0x63, 0x97, 0x84, 0x00, 0xb2, 0x40, 0x22, - 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x04, 0xaa, 0x85, 0x03, 0x45, 0xf4, 0xff, 0xef, 0xf0, 0x5f, 0xfb, - 0xdd, 0xb7, 0xb7, 0x86, 0xb8, 0xed, 0x01, 0x47, 0xfd, 0x57, 0x93, 0x86, 0x06, 0x32, 0x63, 0x15, 0xb7, 0x00, 0x13, - 0xc5, 0xf7, 0xff, 0x82, 0x80, 0x33, 0x06, 0xe5, 0x00, 0x03, 0x46, 0x06, 0x00, 0xb1, 0x8f, 0x21, 0x46, 0x13, 0xd8, - 0x17, 0x00, 0x85, 0x8b, 0x91, 0xc3, 0xb6, 0x87, 0x7d, 0x16, 0xb3, 0x47, 0xf8, 0x00, 0x65, 0xfa, 0x05, 0x07, 0xd9, - 0xbf, 0x2a, 0x83, 0x09, 0xca, 0x83, 0x83, 0x05, 0x00, 0x23, 0x00, 0x73, 0x00, 0x7d, 0x16, 0x05, 0x03, 0x85, 0x05, - 0x6d, 0xfa, 0x82, 0x80, 0x15, 0xc2, 0x2a, 0x83, 0x85, 0x46, 0x63, 0x67, 0xb5, 0x00, 0xfd, 0x56, 0x13, 0x07, 0xf6, - 0xff, 0x3a, 0x93, 0xba, 0x95, 0x83, 0x83, 0x05, 0x00, 0x23, 0x00, 0x73, 0x00, 0x7d, 0x16, 0x36, 0x93, 0xb6, 0x95, - 0x6d, 0xfa, 0x82, 0x80, 0x2a, 0x83, 0x11, 0xc6, 0x23, 0x00, 0xb3, 0x00, 0x7d, 0x16, 0x05, 0x03, 0x65, 0xfe, 0x82, - 0x80, 0x00, 0x00, 0x63, 0x6f, 0x64, 0x65, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, 0x53, 0x45, 0x43, 0x43, - 0x48, 0x4e, 0x4c, 0x00, 0x4d, 0x43, 0x4e, 0x54, 0x00, 0x00, 0x00, 0x00, 0x54, 0x58, 0x3a, 0x20, 0x25, 0x64, 0x2f, - 0x25, 0x64, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x43, 0x4d, 0x44, 0x33, 0x00, 0x00, 0x00, 0x00, 0x49, 0x00, - 0x00, 0x00, 0x65, 0x6e, 0x61, 0x62, 0x6c, 0x65, 0x64, 0x20, 0x25, 0x64, 0x00, 0x00, 0x4d, 0x41, 0x49, 0x4e, 0x00, - 0x00, 0x00, 0x00, 0x6c, 0x65, 0x6e, 0x20, 0x25, 0x64, 0x2f, 0x25, 0x64, 0x00, 0x00, 0x00, 0x72, 0x73, 0x70, 0x3d, - 0x25, 0x78, 0x00, 0x00, 0x73, 0x74, 0x61, 0x72, 0x74, 0x2c, 0x20, 0x76, 0x25, 0x75, 0x2e, 0x25, 0x75, 0x2e, 0x25, - 0x75, 0x00, 0x00, 0x00, 0x00, 0x50, 0x52, 0x4f, 0x56, 0x49, 0x53, 0x49, 0x4f, 0x4e, 0x20, 0x4f, 0x4b, 0x00, 0x00, - 0x00, 0x00, 0x4e, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x43, 0x50, 0x42, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x4c, - 0x33, 0x20, 0x63, 0x6d, 0x64, 0x20, 0x25, 0x64, 0x3a, 0x20, 0x25, 0x78, 0x2c, 0x20, 0x6c, 0x65, 0x6e, 0x3a, 0x20, - 0x25, 0x64, 0x00, 0x00, 0x4c, 0x33, 0x20, 0x61, 0x63, 0x63, 0x65, 0x73, 0x73, 0x20, 0x66, 0x61, 0x69, 0x6c, 0x65, - 0x64, 0x2c, 0x20, 0x63, 0x6d, 0x64, 0x3a, 0x20, 0x25, 0x64, 0x2c, 0x20, 0x6c, 0x65, 0x6e, 0x3a, 0x20, 0x25, 0x64, - 0x20, 0x00, 0x70, 0x69, 0x6e, 0x67, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x00, 0x4c, 0x33, 0x00, 0x00, 0x57, - 0x52, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x00, 0x52, 0x44, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x00, 0x6d, 0x61, 0x63, 0x61, - 0x6e, 0x64, 0x64, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x00, 0x00, 0x73, 0x65, 0x6e, 0x74, 0x00, 0x00, 0x00, - 0x00, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x20, 0x73, 0x6c, 0x65, 0x65, 0x70, 0x00, 0x77, 0x61, 0x6b, 0x65, 0x75, 0x70, - 0x00, 0x00, 0x56, 0x19, 0x10, 0x00, 0x94, 0x19, 0x10, 0x00, 0xc0, 0x19, 0x10, 0x00, 0xf0, 0x19, 0x10, 0x00, 0xf8, - 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, - 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, - 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0x0a, 0x1a, 0x10, 0x00, 0x64, 0x1a, 0x10, 0x00, 0x00, 0x00, - 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 0x00, 0x06, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0xa0, - 0x1f, 0x00, 0x06, 0x02, 0x00, 0x05, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x06, 0x03, 0x10, 0x08, 0x00, - 0x00, 0x18, 0x00, 0x00, 0x40, 0x1f, 0x00, 0x06, 0x06, 0x10, 0x08, 0x00, 0x04, 0x18, 0x00, 0x00, 0x60, 0x1f, 0x00, - 0x06, 0x04, 0x00, 0x09, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x06, 0x05, 0x05, 0x7f, 0x07, 0x01, 0x08, 0x18, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xf0, 0x01, 0x10, 0x10, 0x00, 0x04, 0x02, 0x11, 0x00, 0x44, 0x02, 0x12, - 0x00, 0x84, 0x02, 0x20, 0x90, 0x01, 0x03, 0x21, 0x80, 0x42, 0x03, 0x22, 0xf0, 0x01, 0x03, 0x30, 0x80, 0x02, 0x04, - 0x31, 0x80, 0x42, 0x04, 0x40, 0x70, 0x04, 0x11, 0x41, 0x70, 0x44, 0x11, 0x42, 0x70, 0x84, 0x11, 0x50, 0xf0, 0x01, - 0x12, 0x60, 0x32, 0x04, 0x13, 0x61, 0x32, 0x44, 0x13, 0x62, 0x32, 0x84, 0x13, 0x63, 0x32, 0xc4, 0x13, 0x70, 0x32, - 0x04, 0x14, 0x71, 0x32, 0x44, 0x14, 0x80, 0x20, 0x04, 0x15, 0x81, 0x20, 0x84, 0x15, 0x82, 0x20, 0x44, 0x15, 0x90, - 0x51, 0x04, 0x16, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x14, 0x04, 0x04, 0x00, 0x08, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x23, 0x20, 0x25, 0x6c, 0x75, 0x20, 0x00, 0x00, 0x25, 0x73, 0x28, 0x25, 0x73, 0x29, 0x3a, 0x20, 0x00, 0x00, - 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x45, 0x00, 0x00, 0x00, 0x4d, 0x53, 0x47, 0x00, 0x43, 0x52, 0x43, 0x20, 0x72, - 0x78, 0x3a, 0x20, 0x25, 0x30, 0x34, 0x78, 0x2c, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x3a, 0x20, 0x25, 0x30, 0x34, 0x78, - 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0xe4, 0x1f, 0x10, 0x00, 0x04, 0x20, 0x10, 0x00, 0x56, 0x20, 0x10, - 0x00, 0xb8, 0x20, 0x10, 0x00, 0xc2, 0x20, 0x10, 0x00, 0x4f, 0x53, 0x00, 0x00, 0x63, 0x6f, 0x6e, 0x64, 0x3a, 0x20, - 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, 0x52, 0x58, 0x3a, 0x20, 0x63, 0x6d, 0x64, 0x3d, 0x30, 0x78, 0x25, 0x30, 0x32, - 0x78, 0x00, 0x00, 0x55, 0x49, 0x00, 0x00, 0x43, 0x50, 0x42, 0x20, 0x49, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, - 0x74, 0x20, 0x21, 0x00, 0x43, 0x50, 0x42, 0x00, 0x57, 0x00, 0x00, 0x00, 0x46, 0x53, 0x53, 0x00, 0x49, 0x52, 0x51, - 0x00, 0x53, 0x54, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x4b, 0x44, 0x42, 0x00, 0x73, 0x74, 0x3a, 0x20, 0x25, 0x78, - 0x00, 0x00, 0x4d, 0x41, 0x44, 0x00, 0x4f, 0x54, 0x50, 0x00, 0x01, 0x00, 0x00, 0x00, 0x53, 0x43, 0x42, 0x00, 0x4e, - 0x6f, 0x69, 0x73, 0x65, 0x5f, 0x4b, 0x4b, 0x31, 0x5f, 0x32, 0x35, 0x35, 0x31, 0x39, 0x5f, 0x41, 0x45, 0x53, 0x47, - 0x43, 0x4d, 0x5f, 0x53, 0x48, 0x41, 0x32, 0x35, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x3f, 0x10, - 0x00, 0x78, 0x45, 0x10, 0x00, 0x62, 0x45, 0x10, 0x00, 0x26, 0x45, 0x10, 0x00, 0x3a, 0x3e, 0x10, 0x00, 0xd0, 0x45, - 0x10, 0x00, 0x41, 0x4c, 0x41, 0x52, 0x4d, 0x20, 0x43, 0x48, 0x41, 0x4e, 0x4e, 0x45, 0x4c, 0x53, 0x3a, 0x20, 0x25, - 0x78, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x53, 0x43, 0x4e, 0x54, 0x52, 0x00, 0x00, 0x00, 0x53, 0x50, 0x45, 0x43, - 0x54, 0x00, 0x00, 0x00, 0xc3, 0x14, 0x13, 0x00}; \ No newline at end of file +const uint8_t fw_CPU[] = { + 0x5f, 0x3c, 0xc7, 0xed, 0xef, 0x9d, 0x5f, 0x8c, 0x74, 0x18, 0xbe, 0x71, 0xe6, 0x29, 0xcb, 0x5b, + 0x8d, 0x93, 0xd7, 0xf7, 0x9c, 0x5c, 0xc4, 0x88, 0x50, 0x0a, 0x63, 0x0e, 0xa1, 0xf9, 0xc8, 0x72, + 0x16, 0x8b, 0x99, 0x77, 0x0f, 0x5e, 0xd6, 0xc1, 0x64, 0x19, 0x2f, 0x48, 0xa6, 0x72, 0x68, 0x40, + 0xb0, 0x9b, 0x5d, 0xe3, 0x0f, 0xe4, 0x15, 0x2c, 0x61, 0xf4, 0xa9, 0x80, 0x6d, 0x8b, 0x6d, 0x0f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x2c, 0x57, 0x00, 0x00, 0x02, 0x41, 0xc9, 0x04, + 0xec, 0x8f, 0xcf, 0xa2, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x6f, 0x30, 0x00, 0x43, 0x6f, 0x30, 0x20, 0x3d, 0x6f, 0x30, 0xe0, 0x3c, 0x6f, 0x30, 0xa0, 0x3c, + 0x6f, 0x30, 0x60, 0x3c, 0x6f, 0x30, 0x20, 0x3c, 0x6f, 0x30, 0xe0, 0x3b, 0x6f, 0x50, 0x60, 0x04, + 0x6f, 0x30, 0x60, 0x3b, 0x6f, 0x30, 0x20, 0x3b, 0x6f, 0x30, 0xe0, 0x3a, 0x6f, 0x30, 0xa0, 0x7f, + 0x6f, 0x30, 0x60, 0x3a, 0x6f, 0x30, 0x20, 0x3a, 0x6f, 0x30, 0xe0, 0x39, 0x6f, 0x30, 0xa0, 0x39, + 0x6f, 0x40, 0xf0, 0x72, 0x6f, 0x30, 0x20, 0x26, 0x6f, 0x30, 0x50, 0x20, 0x6f, 0x40, 0x30, 0x22, + 0x6f, 0x40, 0xf0, 0x21, 0x6f, 0x40, 0xb0, 0x21, 0x6f, 0x30, 0xa0, 0x4c, 0x6f, 0x30, 0xa0, 0x4d, + 0x6f, 0x30, 0xf0, 0x42, 0x6f, 0x40, 0x50, 0x56, 0x6f, 0x30, 0x20, 0x4e, 0x6f, 0x20, 0x30, 0x1f, + 0x6f, 0x40, 0x70, 0x0a, 0x6f, 0x30, 0xa0, 0x4e, 0x6f, 0x30, 0x00, 0x5b, 0x6f, 0x30, 0x00, 0x3f, + 0x93, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x93, 0x01, 0x00, 0x00, 0x13, 0x02, 0x00, 0x00, + 0x93, 0x02, 0x00, 0x00, 0x13, 0x03, 0x00, 0x00, 0x93, 0x03, 0x00, 0x00, 0x13, 0x04, 0x00, 0x00, + 0x93, 0x04, 0x00, 0x00, 0x13, 0x05, 0x00, 0x00, 0x93, 0x05, 0x00, 0x00, 0x13, 0x06, 0x00, 0x00, + 0x93, 0x06, 0x00, 0x00, 0x13, 0x07, 0x00, 0x00, 0x93, 0x07, 0x00, 0x00, 0x13, 0x08, 0x00, 0x00, + 0x93, 0x08, 0x00, 0x00, 0x13, 0x09, 0x00, 0x00, 0x93, 0x09, 0x00, 0x00, 0x13, 0x0a, 0x00, 0x00, + 0x93, 0x0a, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x93, 0x0b, 0x00, 0x00, 0x13, 0x0c, 0x00, 0x00, + 0x93, 0x0c, 0x00, 0x00, 0x13, 0x0d, 0x00, 0x00, 0x93, 0x0d, 0x00, 0x00, 0x13, 0x0e, 0x00, 0x00, + 0x93, 0x0e, 0x00, 0x00, 0x13, 0x0f, 0x00, 0x00, 0x93, 0x0f, 0x00, 0x00, 0x97, 0x00, 0x00, 0x00, + 0x93, 0x80, 0x40, 0xf0, 0x73, 0x90, 0x50, 0x30, 0x93, 0x00, 0x00, 0x00, 0x17, 0x41, 0x10, 0x00, + 0x13, 0x01, 0x41, 0xcf, 0x33, 0x04, 0x01, 0x00, 0x17, 0x0d, 0x10, 0x00, 0x13, 0x0d, 0x8d, 0xee, + 0x97, 0x4d, 0x10, 0x00, 0x93, 0x8d, 0x0d, 0xce, 0x63, 0x57, 0xbd, 0x01, 0x23, 0x20, 0x0d, 0x00, + 0x11, 0x0d, 0xe3, 0x4d, 0xbd, 0xff, 0xef, 0x00, 0xf0, 0x60, 0x73, 0x00, 0x50, 0x10, 0xf5, 0xbf, + 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa6, 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0x07, 0xf4, + 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0x07, 0xf2, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0x07, 0xf2, + 0xb7, 0x37, 0x20, 0x00, 0x23, 0x88, 0x07, 0xf2, 0x82, 0x80, 0x18, 0x41, 0xfd, 0x57, 0x63, 0x02, + 0xf7, 0x06, 0x13, 0x07, 0x45, 0x00, 0x81, 0x47, 0x13, 0x06, 0xf0, 0x07, 0x14, 0x43, 0x81, 0xea, + 0x85, 0x07, 0x11, 0x07, 0xe3, 0x9c, 0xc7, 0xfe, 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x01, 0x47, + 0x93, 0x05, 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, 0x05, 0x8a, 0x19, 0xca, 0x93, 0x05, 0x00, 0x02, + 0x33, 0xd6, 0xe6, 0x00, 0x05, 0x8a, 0x15, 0xc6, 0x05, 0x07, 0xe3, 0x1b, 0xb7, 0xfe, 0x21, 0xa0, + 0x05, 0x07, 0xe3, 0x11, 0xb7, 0xfe, 0x89, 0x07, 0x93, 0x06, 0x00, 0x08, 0x7d, 0x56, 0xe3, 0x85, + 0xd7, 0xfc, 0x85, 0x07, 0x13, 0x97, 0x27, 0x00, 0x2a, 0x97, 0x03, 0x27, 0xc7, 0xff, 0xe3, 0x08, + 0xc7, 0xfe, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x05, 0x67, 0xaa, 0x87, 0x01, 0x17, 0x01, 0x45, + 0x94, 0x43, 0x99, 0xe6, 0x13, 0x05, 0x05, 0x02, 0x91, 0x07, 0xe3, 0x1b, 0xe5, 0xfe, 0x82, 0x80, + 0x81, 0x47, 0x13, 0x06, 0x00, 0x02, 0x33, 0xd7, 0xf6, 0x00, 0x05, 0x8b, 0x09, 0xe7, 0x85, 0x07, + 0x05, 0x05, 0xe3, 0x9a, 0xc7, 0xfe, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x14, 0x20, 0x00, + 0x13, 0x04, 0x04, 0x00, 0x83, 0x46, 0x94, 0x07, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, + 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, 0x64, 0x13, 0x06, 0x06, 0x3d, 0x93, 0x85, 0xc5, 0x3d, + 0x06, 0xc6, 0xef, 0x10, 0x30, 0x4c, 0x03, 0x45, 0x94, 0x07, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, + 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x40, 0x90, 0x0b, 0xef, 0x20, 0xc0, 0x58, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x00, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x40, 0x50, 0x0c, 0xb2, 0x40, + 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x05, 0x05, 0x10, 0x2a, 0x84, 0x37, 0x55, + 0x10, 0x00, 0x13, 0x05, 0x45, 0x3e, 0x06, 0xc6, 0xef, 0x10, 0x30, 0x4f, 0x37, 0x37, 0x20, 0x00, + 0x13, 0x07, 0x47, 0xf5, 0x14, 0x43, 0x85, 0x47, 0xb3, 0x97, 0x87, 0x00, 0xb2, 0x40, 0x22, 0x44, + 0x93, 0xc7, 0xf7, 0xff, 0xf5, 0x8f, 0x1c, 0xc3, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, + 0x26, 0xc2, 0x06, 0xc6, 0x2a, 0x84, 0x93, 0x04, 0xa0, 0x0a, 0xef, 0x20, 0x10, 0x76, 0x63, 0x19, + 0x95, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, + 0x22, 0x85, 0xef, 0x20, 0x90, 0x78, 0x22, 0x85, 0xef, 0x20, 0x30, 0x74, 0xe3, 0x03, 0x95, 0xfe, + 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, 0x3e, 0x85, 0x45, 0xef, 0x10, 0x10, 0x49, 0x13, 0x05, + 0x50, 0x05, 0xd1, 0xbf, 0x01, 0x11, 0x22, 0xcc, 0x2a, 0x84, 0x37, 0x35, 0x00, 0x08, 0x06, 0xce, + 0x2e, 0xc6, 0xef, 0x30, 0x10, 0x0a, 0x32, 0x46, 0xa2, 0x85, 0x37, 0x35, 0x00, 0x08, 0xef, 0x30, + 0x50, 0x0e, 0x62, 0x44, 0xf2, 0x40, 0x37, 0x35, 0x00, 0x08, 0x05, 0x61, 0x6f, 0x30, 0xb0, 0x0b, + 0x6d, 0x71, 0x23, 0x24, 0x81, 0x10, 0x2a, 0x84, 0x0a, 0x85, 0x23, 0x26, 0x11, 0x10, 0xef, 0x10, + 0x50, 0x63, 0x0a, 0x85, 0x23, 0x00, 0x81, 0x00, 0xef, 0x20, 0xc0, 0x3e, 0x83, 0x20, 0xc1, 0x10, + 0x03, 0x24, 0x81, 0x10, 0x51, 0x61, 0x82, 0x80, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0x2e, 0xc4, + 0xef, 0x20, 0xd0, 0x1a, 0xa2, 0x45, 0x32, 0x45, 0xef, 0x20, 0xd0, 0x32, 0x2a, 0xc4, 0xef, 0x20, + 0x90, 0x1b, 0xf2, 0x40, 0x22, 0x45, 0x05, 0x61, 0x82, 0x80, 0x13, 0x01, 0x01, 0xde, 0x23, 0x2c, + 0x81, 0x20, 0x2e, 0x84, 0xaa, 0x05, 0x23, 0x28, 0x21, 0x21, 0x93, 0x85, 0x05, 0x20, 0x2a, 0x89, + 0x08, 0x08, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x2a, 0x91, 0x20, 0x7d, 0x3f, 0x93, 0x07, 0xa0, 0x0a, + 0x63, 0x12, 0xf5, 0x04, 0xaa, 0x84, 0x08, 0x08, 0xcd, 0x33, 0x63, 0x00, 0x95, 0x02, 0x22, 0x85, + 0xd1, 0x3d, 0x09, 0x45, 0x83, 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, 0x41, 0x21, + 0x03, 0x29, 0x01, 0x21, 0x13, 0x01, 0x01, 0x22, 0x82, 0x80, 0x42, 0x44, 0x48, 0x08, 0x22, 0xc6, + 0x25, 0x35, 0x09, 0x8c, 0x11, 0x46, 0x6c, 0x00, 0x4a, 0x85, 0x22, 0xc6, 0xef, 0x40, 0x70, 0x7c, + 0x05, 0x45, 0xc9, 0xbf, 0x01, 0x45, 0xf9, 0xb7, 0x41, 0x11, 0x4a, 0xc0, 0x03, 0xa9, 0x05, 0x00, + 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0x2e, 0x84, 0xaa, 0x84, 0xef, 0x20, 0x10, 0x67, 0xca, 0x85, + 0x26, 0x85, 0xef, 0x20, 0x70, 0x1e, 0xa6, 0x85, 0x22, 0x85, 0xef, 0x20, 0xb0, 0x28, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x02, 0x1c, 0x40, 0x63, 0x93, 0x27, 0x03, 0x93, 0x07, 0x44, 0x00, + 0x7d, 0x57, 0x13, 0x04, 0x04, 0x20, 0x94, 0x43, 0x63, 0x9b, 0xe6, 0x00, 0x91, 0x07, 0xe3, 0x9c, + 0x87, 0xfe, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, + 0x50, 0x05, 0xc5, 0xbf, 0x13, 0x01, 0x01, 0xde, 0x23, 0x26, 0x31, 0x21, 0x93, 0x19, 0xa5, 0x00, + 0x23, 0x2a, 0x91, 0x20, 0x93, 0x84, 0x09, 0x20, 0x23, 0x2c, 0x81, 0x20, 0xa6, 0x85, 0x2a, 0x84, + 0x0a, 0x85, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x28, 0x21, 0x21, 0xfd, 0x35, 0x93, 0x07, 0xa0, 0x0a, + 0x63, 0x00, 0xf5, 0x02, 0x01, 0x45, 0x83, 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, + 0x41, 0x21, 0x03, 0x29, 0x01, 0x21, 0x83, 0x29, 0xc1, 0x20, 0x13, 0x01, 0x01, 0x22, 0x82, 0x80, + 0x2a, 0x89, 0x0a, 0x85, 0xdd, 0x39, 0x63, 0x06, 0x25, 0x01, 0x22, 0x85, 0xe5, 0x33, 0x09, 0x45, + 0xd9, 0xbf, 0x02, 0x44, 0x48, 0x00, 0x89, 0x3b, 0xaa, 0x87, 0x33, 0x06, 0xa4, 0x40, 0x0d, 0x45, + 0xe3, 0x03, 0xf4, 0xfc, 0x09, 0x45, 0xe3, 0x60, 0xc4, 0xfc, 0x5c, 0x00, 0x01, 0x44, 0x13, 0x08, + 0x00, 0x02, 0x13, 0x05, 0xf0, 0x07, 0x8c, 0x43, 0x89, 0xc9, 0x81, 0x46, 0x33, 0xd7, 0xd5, 0x00, + 0x05, 0x8b, 0x05, 0xeb, 0x85, 0x06, 0xe3, 0x9b, 0x06, 0xff, 0x05, 0x04, 0x91, 0x07, 0xe3, 0x14, + 0xa4, 0xfe, 0x7d, 0x16, 0x8a, 0x85, 0x13, 0x85, 0x09, 0x40, 0x32, 0xc0, 0xf5, 0x3d, 0x93, 0x07, + 0xa0, 0x0a, 0xe3, 0x11, 0xf5, 0xf8, 0x8a, 0x85, 0x26, 0x85, 0xfd, 0x35, 0x13, 0x05, 0x65, 0xf5, + 0x1d, 0xa8, 0x05, 0x47, 0x33, 0x17, 0xd7, 0x00, 0x13, 0x47, 0xf7, 0xff, 0x6d, 0x8f, 0x98, 0xc3, + 0xef, 0x20, 0xc0, 0x7f, 0x18, 0x04, 0x93, 0x17, 0x24, 0x00, 0xba, 0x97, 0x83, 0xa5, 0x47, 0xe0, + 0x13, 0x05, 0x14, 0x00, 0x0a, 0x05, 0x26, 0x95, 0xef, 0x20, 0x50, 0x10, 0x2a, 0x84, 0xef, 0x20, + 0x80, 0x7f, 0x13, 0x05, 0x64, 0xf5, 0x13, 0x35, 0x15, 0x00, 0x35, 0xbf, 0x41, 0x11, 0x22, 0xc4, + 0x06, 0xc6, 0x93, 0x07, 0x30, 0x0c, 0x2a, 0x84, 0x63, 0x04, 0xf5, 0x00, 0xef, 0x20, 0xc0, 0x4b, + 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x05, 0x67, 0x23, 0x80, 0x87, 0x00, 0xba, 0x97, + 0xf8, 0x5b, 0x19, 0xe3, 0x05, 0x47, 0xf8, 0xdb, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, + 0x05, 0x66, 0x37, 0x05, 0x20, 0x00, 0x41, 0x11, 0x13, 0x06, 0xc6, 0x07, 0x81, 0x45, 0x13, 0x05, + 0x05, 0x00, 0x06, 0xc6, 0xef, 0x40, 0xb0, 0x65, 0xef, 0x20, 0x80, 0x41, 0xef, 0x40, 0x80, 0x39, + 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x20, 0x00, 0x38, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x20, 0x00, 0x55, + 0xef, 0x20, 0x90, 0x7f, 0xef, 0x40, 0xa0, 0x0c, 0xef, 0x40, 0x00, 0x65, 0xb2, 0x40, 0x41, 0x01, + 0x6f, 0x30, 0xe0, 0x15, 0x69, 0x71, 0x08, 0x08, 0x23, 0x22, 0x91, 0x12, 0x23, 0x20, 0x21, 0x13, + 0x23, 0x2c, 0x41, 0x11, 0x23, 0x26, 0x11, 0x12, 0x23, 0x24, 0x81, 0x12, 0x23, 0x2e, 0x31, 0x11, + 0x23, 0x2a, 0x51, 0x11, 0xef, 0x10, 0xf0, 0x39, 0x91, 0x47, 0x37, 0x39, 0x20, 0x00, 0x23, 0x08, + 0xf1, 0x00, 0x83, 0x27, 0xc9, 0xf4, 0x37, 0x1a, 0x20, 0x00, 0xb7, 0x34, 0x20, 0x00, 0x13, 0x09, + 0xc9, 0xf4, 0x13, 0x0a, 0x0a, 0x00, 0x93, 0x84, 0x84, 0xf4, 0xc5, 0xe7, 0x83, 0x27, 0x4a, 0x07, + 0x09, 0x46, 0x6c, 0x00, 0x23, 0x20, 0xf9, 0x00, 0x13, 0x05, 0x21, 0x01, 0xc1, 0x17, 0x3e, 0xc6, + 0x23, 0xa0, 0x04, 0x00, 0xef, 0x40, 0xf0, 0x58, 0x89, 0x47, 0xa3, 0x08, 0xf1, 0x00, 0x13, 0x04, + 0xe0, 0x07, 0x93, 0x09, 0x41, 0x01, 0x03, 0x27, 0x09, 0x00, 0x94, 0x40, 0xb3, 0x07, 0xd7, 0x40, + 0x63, 0xf3, 0x87, 0x00, 0x3e, 0x84, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x5a, 0x10, 0x00, 0x37, 0x55, + 0x10, 0x00, 0xa2, 0x87, 0x93, 0x85, 0xca, 0x3f, 0x13, 0x06, 0xc6, 0x3e, 0x13, 0x05, 0x45, 0x40, + 0xef, 0x10, 0x50, 0x0c, 0x8c, 0x40, 0x83, 0x27, 0x4a, 0x07, 0x33, 0x07, 0xb4, 0x00, 0x63, 0xf7, + 0xe7, 0x04, 0x8d, 0x45, 0x13, 0x85, 0xca, 0x3f, 0xef, 0x10, 0x30, 0x12, 0x13, 0x04, 0x50, 0x05, + 0xc5, 0x3c, 0xef, 0x40, 0x60, 0x2a, 0xef, 0x20, 0xa0, 0x32, 0xef, 0x20, 0xa0, 0x29, 0x29, 0x3f, + 0x83, 0x20, 0xc1, 0x12, 0x22, 0x85, 0x03, 0x24, 0x81, 0x12, 0x83, 0x24, 0x41, 0x12, 0x03, 0x29, + 0x01, 0x12, 0x83, 0x29, 0xc1, 0x11, 0x03, 0x2a, 0x81, 0x11, 0x83, 0x2a, 0x41, 0x11, 0x55, 0x61, + 0x82, 0x80, 0x13, 0x04, 0x00, 0x08, 0x93, 0x09, 0x21, 0x01, 0xb5, 0xbf, 0xb7, 0x07, 0x20, 0x00, + 0x93, 0x87, 0x07, 0x00, 0x22, 0x86, 0xbe, 0x95, 0x4e, 0x85, 0xef, 0x40, 0x90, 0x4e, 0x83, 0x47, + 0x11, 0x01, 0x98, 0x40, 0x22, 0x97, 0x3e, 0x94, 0x83, 0x27, 0x09, 0x00, 0xa3, 0x08, 0x81, 0x00, + 0x98, 0xc0, 0x13, 0x04, 0x50, 0x05, 0x63, 0x17, 0xf7, 0x00, 0x89, 0x47, 0x23, 0x08, 0xf1, 0x00, + 0x13, 0x04, 0xa0, 0x0a, 0x08, 0x08, 0xef, 0x20, 0xe0, 0x04, 0x59, 0xbf, 0x41, 0x11, 0xb7, 0x37, + 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x06, 0xc6, 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x20, 0xe0, 0x26, + 0x85, 0x3d, 0xb9, 0x3c, 0xef, 0x30, 0x20, 0x07, 0x41, 0x3d, 0xb2, 0x40, 0x1d, 0x65, 0x13, 0x05, + 0x05, 0x6c, 0x41, 0x01, 0x6f, 0x30, 0x00, 0x0f, 0x41, 0x11, 0x26, 0xc2, 0xae, 0x84, 0xb6, 0x85, + 0x06, 0xc6, 0x22, 0xc4, 0x4a, 0xc0, 0x36, 0x84, 0x32, 0x89, 0xef, 0x40, 0x40, 0x4f, 0x22, 0x86, + 0xca, 0x85, 0x13, 0x05, 0x00, 0x02, 0xef, 0x40, 0x00, 0x58, 0xef, 0x40, 0x60, 0x4c, 0xef, 0x40, + 0xe0, 0x67, 0x93, 0x07, 0xa0, 0x0a, 0x13, 0x04, 0x50, 0x05, 0x63, 0x1a, 0xf5, 0x00, 0x2a, 0x84, + 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0x00, 0x02, 0x26, 0x85, 0xef, 0x40, 0xe0, 0x50, 0xb2, 0x40, + 0x22, 0x85, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x85, 0x67, 0xc1, 0x07, + 0x63, 0xee, 0xb7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xae, 0x84, 0x37, 0x04, + 0x20, 0x00, 0x19, 0xc5, 0x2e, 0x86, 0xaa, 0x85, 0x13, 0x05, 0x04, 0x00, 0xef, 0x40, 0xd0, 0x42, + 0x13, 0x04, 0x04, 0x00, 0x93, 0x07, 0x30, 0xfc, 0x23, 0x00, 0xf4, 0x00, 0x85, 0x67, 0x3e, 0x94, + 0x64, 0xd8, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x82, 0x80, 0x13, 0x01, + 0x01, 0xdd, 0x23, 0x24, 0x81, 0x22, 0x23, 0x22, 0x91, 0x22, 0x23, 0x20, 0x21, 0x23, 0x23, 0x2e, + 0x31, 0x21, 0x23, 0x2c, 0x41, 0x21, 0x23, 0x2a, 0x51, 0x21, 0x23, 0x28, 0x61, 0x21, 0x23, 0x26, + 0x71, 0x21, 0x23, 0x24, 0x81, 0x21, 0x23, 0x26, 0x11, 0x22, 0x13, 0x04, 0x00, 0x20, 0x01, 0x49, + 0x93, 0x04, 0xa0, 0x0a, 0x37, 0x3a, 0x20, 0x00, 0x85, 0x4a, 0x37, 0x5b, 0x10, 0x00, 0xb7, 0x5b, + 0x10, 0x00, 0x37, 0x5c, 0x10, 0x00, 0xc1, 0x49, 0xa2, 0x85, 0x0a, 0x85, 0xb1, 0x3e, 0x63, 0x16, + 0x95, 0x02, 0x0a, 0x85, 0x59, 0x32, 0x63, 0x1e, 0x95, 0x04, 0x13, 0x07, 0x4a, 0xf5, 0x14, 0x43, + 0xb3, 0x97, 0x2a, 0x01, 0x13, 0x06, 0x8b, 0x40, 0xd5, 0x8f, 0x93, 0x85, 0x4b, 0x3e, 0xca, 0x86, + 0x13, 0x05, 0x4c, 0x64, 0x1c, 0xc3, 0xef, 0x10, 0xe0, 0x6e, 0x05, 0x09, 0x13, 0x04, 0x04, 0x40, + 0xe3, 0x14, 0x39, 0xfd, 0x83, 0x20, 0xc1, 0x22, 0x03, 0x24, 0x81, 0x22, 0x83, 0x24, 0x41, 0x22, + 0x03, 0x29, 0x01, 0x22, 0x83, 0x29, 0xc1, 0x21, 0x03, 0x2a, 0x81, 0x21, 0x83, 0x2a, 0x41, 0x21, + 0x03, 0x2b, 0x01, 0x21, 0x83, 0x2b, 0xc1, 0x20, 0x03, 0x2c, 0x81, 0x20, 0x13, 0x01, 0x01, 0x23, + 0x82, 0x80, 0x93, 0x05, 0x04, 0x20, 0x0a, 0x85, 0xc5, 0x3c, 0xe3, 0x10, 0x95, 0xfc, 0x0a, 0x85, + 0xef, 0xf0, 0xbf, 0x91, 0xe3, 0x1b, 0x95, 0xfa, 0x22, 0x85, 0xef, 0x20, 0x10, 0x1f, 0x8a, 0x85, + 0x22, 0x85, 0xef, 0x20, 0x70, 0x06, 0xa2, 0x85, 0x0a, 0x85, 0xf9, 0x34, 0xe3, 0x1f, 0x95, 0xf8, + 0x0a, 0x85, 0xef, 0xf0, 0x9f, 0x8f, 0xe3, 0x0a, 0x95, 0xf6, 0x41, 0xbf, 0xb7, 0x05, 0x00, 0x80, + 0x37, 0x55, 0x10, 0x00, 0x86, 0x87, 0x6d, 0x71, 0xbe, 0x95, 0x13, 0x05, 0x45, 0x41, 0x23, 0x26, + 0x11, 0x10, 0xef, 0x10, 0x80, 0x6d, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x87, 0xf2, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x1e, 0xf7, 0x02, 0x37, 0x15, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x9a, 0xef, 0x10, + 0xf0, 0x5f, 0x13, 0x05, 0xc0, 0x0f, 0xef, 0x10, 0xa0, 0x5a, 0x0a, 0x85, 0xef, 0x10, 0x70, 0x09, + 0x93, 0x07, 0xf0, 0x07, 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x00, 0x23, 0x00, 0xf1, 0x00, + 0xef, 0x10, 0x00, 0x54, 0xa3, 0x00, 0xa1, 0x00, 0x0a, 0x85, 0xef, 0x10, 0x70, 0x60, 0x05, 0x45, + 0xef, 0x40, 0x00, 0x67, 0xef, 0x40, 0x00, 0x66, 0xd5, 0x33, 0xef, 0x10, 0x50, 0x2d, 0xf5, 0xbf, + 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0x40, 0x60, 0x4c, 0x93, 0x07, 0x00, 0x08, 0x63, 0xf3, + 0xa7, 0x00, 0xad, 0x3f, 0x2a, 0x84, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0x50, 0x7e, 0xb7, 0x17, + 0x20, 0x00, 0xb2, 0x40, 0x23, 0xaa, 0x87, 0x06, 0x22, 0x44, 0x13, 0x05, 0x30, 0x0c, 0x41, 0x01, + 0x82, 0x80, 0x93, 0x07, 0xf0, 0x17, 0x63, 0xf5, 0xa7, 0x00, 0x41, 0x11, 0x06, 0xc6, 0xb9, 0x37, + 0x6f, 0x10, 0xb0, 0x3e, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x4a, 0xc0, 0x2e, 0x84, 0x06, 0xc6, + 0xaa, 0x84, 0xc5, 0x37, 0x61, 0x8d, 0x13, 0x09, 0x50, 0x05, 0x19, 0xc1, 0x13, 0x09, 0xa0, 0x0a, + 0x26, 0x85, 0xc1, 0x3f, 0x69, 0x8c, 0x13, 0x05, 0xa0, 0x0a, 0x19, 0xe0, 0x13, 0x05, 0x50, 0x05, + 0x63, 0x03, 0x25, 0x01, 0x21, 0x3f, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, + 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x8d, 0x47, 0x63, 0xf3, 0xa7, 0x00, 0x01, 0x37, 0x89, 0x67, + 0x93, 0x87, 0x07, 0xbf, 0x0a, 0x05, 0x3e, 0x95, 0xef, 0x30, 0xe0, 0x02, 0xaa, 0x87, 0x13, 0x07, + 0xf0, 0x0f, 0x55, 0x45, 0x63, 0x89, 0xe7, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x59, 0x45, 0x63, 0x94, + 0xe7, 0x00, 0x13, 0x05, 0x30, 0x0c, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x21, 0x71, 0x23, 0x2c, + 0x81, 0x1a, 0x2a, 0x84, 0x08, 0x09, 0x23, 0x2e, 0x11, 0x1a, 0x23, 0x2a, 0x91, 0x1a, 0x23, 0x28, + 0x21, 0x1b, 0x23, 0x26, 0x31, 0x1b, 0x23, 0x24, 0x41, 0x1b, 0x23, 0x22, 0x51, 0x1b, 0x23, 0x20, + 0x61, 0x1b, 0x23, 0x2e, 0x71, 0x19, 0x23, 0x2c, 0x81, 0x19, 0x23, 0x2a, 0x91, 0x19, 0xef, 0x10, + 0x40, 0x77, 0x83, 0x47, 0x04, 0x00, 0x05, 0x47, 0x23, 0x18, 0xe1, 0x08, 0xc1, 0x46, 0x63, 0x80, + 0xd7, 0x46, 0x63, 0xee, 0xf6, 0x02, 0x91, 0x46, 0x63, 0x88, 0xd7, 0x34, 0x63, 0xe1, 0xf6, 0x02, + 0x63, 0x86, 0xe7, 0x06, 0x09, 0x47, 0x63, 0x81, 0xe7, 0x0e, 0x93, 0x07, 0xe0, 0x07, 0x23, 0x08, + 0xf1, 0x08, 0x08, 0x09, 0xef, 0x10, 0xd0, 0x4c, 0x93, 0x07, 0x50, 0x05, 0x99, 0xa1, 0x21, 0x47, + 0xe3, 0x95, 0xe7, 0xfe, 0x83, 0x47, 0x14, 0x00, 0xd1, 0xeb, 0x4d, 0x31, 0x39, 0xa9, 0x93, 0x06, + 0x20, 0x0a, 0x63, 0x85, 0xd7, 0x4c, 0x93, 0x06, 0x30, 0x0b, 0x63, 0x82, 0xd7, 0x46, 0x93, 0x06, + 0x00, 0x02, 0xe3, 0x94, 0xd7, 0xfc, 0x83, 0x47, 0x14, 0x00, 0x63, 0x99, 0xe7, 0x06, 0x03, 0x47, + 0x24, 0x00, 0x95, 0x47, 0x63, 0x14, 0xf7, 0x06, 0x85, 0x45, 0x61, 0x45, 0xe1, 0x3d, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x09, 0xf5, 0x42, 0x13, 0x04, 0x80, 0xf8, 0x7d, 0xa0, 0x03, 0x47, 0x14, 0x00, + 0x89, 0x47, 0x63, 0x15, 0xf7, 0x04, 0x83, 0x47, 0x24, 0x00, 0x63, 0x8a, 0xe7, 0x04, 0x63, 0x6b, + 0xf7, 0x02, 0xa1, 0xe3, 0x83, 0x45, 0x34, 0x00, 0xf5, 0x47, 0x63, 0xe9, 0xb7, 0x02, 0x9e, 0x05, + 0x13, 0x06, 0x00, 0x08, 0x93, 0x85, 0x05, 0x10, 0x13, 0x05, 0x21, 0x09, 0xef, 0x20, 0x30, 0x6d, + 0x13, 0x04, 0x00, 0x08, 0x08, 0x09, 0xa3, 0x08, 0x81, 0x08, 0xef, 0x10, 0x70, 0x43, 0x93, 0x07, + 0xa0, 0x0a, 0x45, 0xae, 0x13, 0x05, 0x80, 0x1e, 0x63, 0x8d, 0xd7, 0x00, 0x13, 0x04, 0x10, 0xf8, + 0xa1, 0xa8, 0x89, 0x65, 0x13, 0x06, 0x00, 0x08, 0x93, 0x85, 0x05, 0x90, 0xf1, 0xb7, 0x13, 0x05, + 0x00, 0x1f, 0xef, 0x10, 0x90, 0x24, 0x2a, 0xc6, 0x11, 0x46, 0x6c, 0x00, 0x13, 0x05, 0x21, 0x09, + 0xef, 0x40, 0x30, 0x0a, 0x11, 0x44, 0x7d, 0xbf, 0x83, 0x44, 0x14, 0x00, 0xc5, 0x36, 0x93, 0x07, + 0x10, 0x02, 0xe3, 0x95, 0xf4, 0xfc, 0xef, 0x10, 0x10, 0x7d, 0xef, 0x20, 0x90, 0x27, 0xef, 0x30, + 0x90, 0x38, 0xef, 0x40, 0x60, 0x07, 0x03, 0x45, 0x24, 0x02, 0xa5, 0x35, 0x93, 0x07, 0x30, 0x0c, + 0x63, 0x0b, 0xf5, 0x02, 0x13, 0x04, 0x70, 0xf8, 0xb3, 0x06, 0x80, 0x40, 0x37, 0x56, 0x10, 0x00, + 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0xf6, 0xf6, 0x0f, 0x13, 0x06, 0x86, 0x42, + 0x93, 0x85, 0x45, 0x41, 0x13, 0x05, 0x45, 0x64, 0x23, 0x08, 0xd1, 0x08, 0xef, 0x10, 0x80, 0x3b, + 0xa3, 0x08, 0x01, 0x08, 0xf9, 0xb5, 0x83, 0x44, 0x24, 0x02, 0x19, 0x34, 0x8d, 0x47, 0xe3, 0xe3, + 0x97, 0xfc, 0x13, 0x06, 0x10, 0x08, 0x81, 0x45, 0x68, 0x00, 0xef, 0x40, 0x50, 0x06, 0x13, 0x06, + 0x00, 0x02, 0x93, 0x05, 0x24, 0x00, 0x13, 0x05, 0xd1, 0x00, 0x23, 0x06, 0x91, 0x00, 0xef, 0x40, + 0x50, 0x01, 0xef, 0x40, 0x60, 0x00, 0x37, 0x25, 0x00, 0x08, 0xef, 0x30, 0x80, 0x01, 0x81, 0x46, + 0x01, 0x46, 0x93, 0x05, 0xd1, 0x02, 0x45, 0x45, 0x85, 0x3e, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x13, + 0xf5, 0xf8, 0x81, 0x45, 0x68, 0x00, 0xef, 0x30, 0x50, 0x2f, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, + 0xe3, 0x1a, 0xf5, 0xf6, 0x93, 0x06, 0x00, 0x02, 0x13, 0x06, 0xd1, 0x00, 0x93, 0x05, 0xd1, 0x04, + 0x49, 0x45, 0x99, 0x36, 0xaa, 0x84, 0xe3, 0x1f, 0x25, 0xf5, 0x85, 0x45, 0x68, 0x00, 0xef, 0x30, + 0xd0, 0x2c, 0x2a, 0x89, 0xe3, 0x18, 0x95, 0xf4, 0x83, 0x47, 0xc1, 0x00, 0x85, 0x46, 0x13, 0x06, + 0xb1, 0x00, 0x93, 0x05, 0xd1, 0x04, 0x4d, 0x45, 0xa3, 0x05, 0xf1, 0x00, 0x31, 0x3e, 0xaa, 0x84, + 0xe3, 0x1a, 0x25, 0xf3, 0x89, 0x45, 0x68, 0x00, 0xef, 0x30, 0x30, 0x2a, 0x2a, 0x89, 0xe3, 0x13, + 0x95, 0xf2, 0x81, 0x46, 0x01, 0x46, 0x93, 0x05, 0xd1, 0x04, 0x51, 0x45, 0xf5, 0x3c, 0xaa, 0x84, + 0xe3, 0x1a, 0x25, 0xf1, 0x8d, 0x45, 0x68, 0x00, 0xef, 0x30, 0x30, 0x28, 0x2a, 0x89, 0xe3, 0x13, + 0x95, 0xf0, 0x91, 0x45, 0x68, 0x00, 0xef, 0x30, 0x50, 0x27, 0xaa, 0x84, 0xe3, 0x1c, 0x25, 0xef, + 0x95, 0x45, 0x68, 0x00, 0xef, 0x30, 0x70, 0x26, 0xe3, 0x16, 0x95, 0xee, 0xb7, 0x19, 0x20, 0x00, + 0x13, 0x85, 0x09, 0x02, 0xef, 0x30, 0x70, 0x29, 0xb7, 0x14, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, + 0x93, 0x05, 0xd1, 0x02, 0x13, 0x85, 0x04, 0x03, 0xef, 0x40, 0xa0, 0x73, 0x37, 0x15, 0x20, 0x00, + 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0xd1, 0x06, 0x13, 0x05, 0x05, 0x05, 0xef, 0x40, 0x60, 0x72, + 0x03, 0x49, 0x24, 0x02, 0x8d, 0x47, 0x4e, 0x84, 0x63, 0xf3, 0x27, 0x01, 0x01, 0x39, 0x37, 0x5c, + 0x10, 0x00, 0xef, 0x10, 0x10, 0x49, 0x81, 0x4c, 0x13, 0x0c, 0x8c, 0x58, 0x8d, 0x49, 0xfd, 0x5a, + 0x13, 0x0a, 0x00, 0x0f, 0x41, 0x6b, 0xb7, 0x0b, 0x00, 0x01, 0x03, 0x25, 0x0c, 0x00, 0x51, 0x81, + 0x49, 0x39, 0x03, 0x27, 0x0c, 0x00, 0x93, 0x57, 0x07, 0x01, 0xbd, 0x8b, 0x63, 0xe8, 0xf9, 0x00, + 0x8e, 0x07, 0xb3, 0x97, 0xfa, 0x00, 0x93, 0xc7, 0xf7, 0xff, 0x7d, 0x8d, 0x83, 0x46, 0x1c, 0x00, + 0x33, 0x55, 0x25, 0x01, 0x93, 0x77, 0x15, 0x00, 0x93, 0xf6, 0x06, 0x0f, 0x63, 0x96, 0x46, 0x07, + 0x99, 0xc3, 0x93, 0x07, 0xf0, 0x0f, 0xbd, 0x65, 0xf9, 0x8d, 0x21, 0x83, 0x3d, 0x8b, 0x22, 0x07, + 0x4d, 0x8f, 0x83, 0x45, 0x0c, 0x00, 0xc2, 0x07, 0x66, 0x85, 0xd9, 0x8d, 0xdd, 0x8d, 0xef, 0x10, + 0xd0, 0x43, 0x83, 0x47, 0x4c, 0x00, 0x11, 0x0c, 0x85, 0x0c, 0xc5, 0xf3, 0xef, 0x10, 0x90, 0x40, + 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x04, 0x03, + 0x13, 0x05, 0x21, 0x09, 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x40, 0xa0, 0x67, 0x93, 0x05, 0x04, 0x02, + 0x41, 0x46, 0x13, 0x05, 0x21, 0x0b, 0xef, 0x40, 0xc0, 0x66, 0xef, 0x30, 0xf0, 0x6b, 0x13, 0x04, + 0x00, 0x03, 0xef, 0xf0, 0x7f, 0x85, 0xbd, 0xbb, 0x93, 0x76, 0x05, 0x10, 0x99, 0xc2, 0x93, 0xe7, + 0x27, 0x00, 0xb3, 0x76, 0x65, 0x01, 0x99, 0xc2, 0x93, 0xe7, 0x47, 0x00, 0x33, 0x75, 0x75, 0x01, + 0x59, 0xd1, 0x93, 0xe7, 0x87, 0x00, 0x41, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0xc7, 0xf3, + 0x93, 0x07, 0xa0, 0x0a, 0x83, 0x44, 0x14, 0x00, 0x63, 0x14, 0xf7, 0x0e, 0x91, 0xe4, 0x13, 0x04, + 0x10, 0xf8, 0xef, 0xf0, 0xbf, 0x96, 0x4d, 0xbb, 0xb7, 0x39, 0x20, 0x00, 0x83, 0xa7, 0x89, 0xf3, + 0x93, 0x89, 0x89, 0xf3, 0xad, 0xcb, 0x09, 0x04, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x49, 0xf3, + 0x83, 0x26, 0x09, 0x00, 0x03, 0xa7, 0x09, 0x00, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, + 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, 0x64, 0xa6, 0x96, 0x13, 0x06, 0xc6, 0x41, 0x93, 0x85, + 0xc5, 0x3f, 0xef, 0x10, 0x20, 0x15, 0x03, 0x25, 0x09, 0x00, 0x83, 0xa7, 0x09, 0x00, 0x33, 0x87, + 0xa4, 0x00, 0xe3, 0xe6, 0xe7, 0xfa, 0x85, 0x67, 0x93, 0x87, 0x07, 0x02, 0xe3, 0xe1, 0xe7, 0xfa, + 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x26, 0x86, 0x3e, 0x95, 0xa2, 0x85, 0xef, 0x40, + 0x40, 0x5b, 0x83, 0x27, 0x09, 0x00, 0xbe, 0x94, 0x83, 0xa7, 0x09, 0x00, 0x23, 0x20, 0x99, 0x00, + 0xbd, 0xe3, 0x75, 0x54, 0x15, 0xbb, 0x89, 0x47, 0xe3, 0xfb, 0x97, 0xf6, 0x03, 0x49, 0x34, 0x00, + 0x83, 0x47, 0x24, 0x00, 0xf9, 0x14, 0x22, 0x09, 0x3e, 0x99, 0x85, 0x67, 0x93, 0x06, 0xf9, 0xff, + 0x13, 0x87, 0xf7, 0x00, 0x11, 0x04, 0xe3, 0x6c, 0xd7, 0xf4, 0x37, 0x0a, 0x20, 0x00, 0x13, 0x0a, + 0x0a, 0x00, 0x3e, 0x9a, 0x41, 0x09, 0x93, 0x07, 0xf0, 0x07, 0xa3, 0x0c, 0xfa, 0x06, 0x23, 0xa0, + 0x29, 0x01, 0xef, 0x10, 0x50, 0x4a, 0xef, 0x20, 0xc0, 0x74, 0xef, 0x30, 0xd0, 0x05, 0xb7, 0x37, + 0x20, 0x00, 0x23, 0x28, 0x2a, 0x07, 0x23, 0x2a, 0x0a, 0x06, 0x23, 0xaa, 0x07, 0xf2, 0x2d, 0xbf, + 0x13, 0x04, 0x60, 0xf8, 0x39, 0xbf, 0xe3, 0x9e, 0xf4, 0xf8, 0x01, 0x44, 0xa1, 0xb9, 0x83, 0x47, + 0x14, 0x00, 0xe3, 0x95, 0x07, 0xc6, 0xef, 0x10, 0x30, 0x15, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x0f, + 0x05, 0xc4, 0x83, 0x20, 0xc1, 0x1b, 0x03, 0x24, 0x81, 0x1b, 0x83, 0x24, 0x41, 0x1b, 0x03, 0x29, + 0x01, 0x1b, 0x83, 0x29, 0xc1, 0x1a, 0x03, 0x2a, 0x81, 0x1a, 0x83, 0x2a, 0x41, 0x1a, 0x03, 0x2b, + 0x01, 0x1a, 0x83, 0x2b, 0xc1, 0x19, 0x03, 0x2c, 0x81, 0x19, 0x83, 0x2c, 0x41, 0x19, 0x3e, 0x85, + 0x39, 0x61, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa2, 0xa7, 0xf4, 0x7d, 0xb7, 0x83, 0x46, + 0x14, 0x00, 0xe3, 0x9d, 0xe6, 0xc0, 0x83, 0x47, 0x24, 0x00, 0x63, 0x8a, 0xd7, 0x02, 0x0d, 0x47, + 0xe3, 0x96, 0xe7, 0xc0, 0xa1, 0x45, 0x01, 0x45, 0xb5, 0x3c, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, + 0xe3, 0x13, 0xf5, 0xba, 0xb7, 0xb5, 0xb5, 0x61, 0x93, 0x85, 0x55, 0x49, 0x13, 0x05, 0x80, 0x1f, + 0xef, 0x10, 0x40, 0x6b, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa6, 0x87, 0xf2, 0xbd, 0xb7, 0xb7, 0x15, + 0x78, 0x4a, 0x93, 0x85, 0x95, 0x21, 0x13, 0x05, 0x80, 0x1f, 0xef, 0x10, 0xa0, 0x69, 0xb7, 0x37, + 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf2, 0x81, 0xbf, 0xb7, 0x37, 0x20, 0x00, + 0x03, 0xa7, 0x87, 0xf2, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1f, 0xf7, 0xb4, 0x83, 0x47, 0x14, 0x00, + 0xe3, 0x96, 0x07, 0xba, 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x09, 0xef, 0x00, 0x50, 0x6f, + 0x2a, 0x84, 0xe3, 0x51, 0x05, 0xb8, 0xcd, 0xbe, 0x41, 0x11, 0x05, 0x45, 0x06, 0xc6, 0xef, 0x40, + 0x20, 0x02, 0xb2, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa0, 0xe7, 0xf4, + 0x41, 0x01, 0x82, 0x80, 0x31, 0x71, 0x22, 0xdd, 0x37, 0x34, 0x20, 0x00, 0x93, 0x07, 0x50, 0x05, + 0x06, 0xdf, 0x4a, 0xd9, 0x52, 0xd5, 0x56, 0xd3, 0x62, 0xcd, 0x26, 0xdb, 0x4e, 0xd7, 0x5a, 0xd1, + 0x5e, 0xcf, 0x66, 0xcb, 0x6a, 0xc9, 0x6e, 0xc7, 0xb7, 0x3a, 0x20, 0x00, 0x37, 0x3a, 0x20, 0x00, + 0x37, 0x39, 0x20, 0x00, 0x13, 0x04, 0x84, 0xf2, 0x23, 0xa0, 0xfa, 0xf4, 0x23, 0x26, 0xfa, 0xf2, + 0x23, 0x22, 0xf9, 0xf4, 0x1c, 0xc0, 0xef, 0x10, 0x60, 0x3d, 0xef, 0x10, 0xc0, 0x55, 0x13, 0x87, + 0x0a, 0xf4, 0x3a, 0xc8, 0x13, 0x07, 0xca, 0xf2, 0x3a, 0xca, 0x13, 0x07, 0x49, 0xf4, 0x93, 0x07, + 0xa0, 0x0a, 0x3a, 0xc6, 0x37, 0x5c, 0x10, 0x00, 0x85, 0x45, 0x63, 0x0a, 0xf5, 0x00, 0x13, 0x05, + 0x4c, 0x41, 0xef, 0x00, 0x90, 0x7b, 0xef, 0x10, 0x80, 0x4f, 0xef, 0xf0, 0x3f, 0x8c, 0x41, 0x45, + 0xef, 0xf0, 0x5f, 0x97, 0x08, 0xc0, 0xb7, 0x07, 0x01, 0x02, 0x80, 0x57, 0x98, 0x5b, 0x29, 0x45, + 0x59, 0x8c, 0x98, 0x5f, 0x59, 0x8c, 0x13, 0x77, 0xf4, 0x87, 0x98, 0xd7, 0x98, 0xdb, 0x98, 0xdf, + 0xd8, 0x43, 0x13, 0x67, 0x87, 0x00, 0xd8, 0xc3, 0xef, 0x10, 0x00, 0x38, 0xef, 0x30, 0x30, 0x22, + 0x13, 0x75, 0x05, 0x78, 0x11, 0xc5, 0x13, 0x05, 0x00, 0x78, 0x81, 0x45, 0xef, 0x30, 0x90, 0x1a, + 0xb7, 0x07, 0x01, 0x02, 0x80, 0xd7, 0x80, 0xdb, 0x37, 0x15, 0x10, 0x00, 0x80, 0xdf, 0x13, 0x05, + 0xc5, 0x9a, 0xef, 0x10, 0xa0, 0x69, 0x37, 0x56, 0x10, 0x00, 0x37, 0x59, 0x10, 0x00, 0x81, 0x47, + 0x01, 0x47, 0x85, 0x46, 0x13, 0x06, 0x06, 0x43, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, 0x64, + 0xef, 0x00, 0x50, 0x6c, 0xef, 0x30, 0x50, 0x1e, 0x93, 0x07, 0x50, 0x05, 0x63, 0x1e, 0xf5, 0x00, + 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x46, 0x44, 0x93, 0x05, 0x4c, 0x41, + 0x13, 0x05, 0x45, 0x40, 0xef, 0x00, 0x10, 0x6a, 0xef, 0x20, 0xa0, 0x2f, 0x51, 0x45, 0xef, 0x10, + 0xc0, 0x4b, 0x1d, 0x89, 0xef, 0x20, 0xc0, 0x2f, 0xef, 0x20, 0xa0, 0x03, 0xef, 0x20, 0x10, 0x03, + 0xef, 0x20, 0x30, 0x31, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0xb0, 0x31, 0x11, 0x46, 0x6c, 0x10, + 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0xf0, 0x35, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0xb0, 0x33, + 0x32, 0x55, 0xc1, 0x7a, 0x37, 0x0b, 0x01, 0xff, 0xb7, 0x0b, 0x00, 0x01, 0xef, 0x20, 0x70, 0x22, + 0x05, 0x64, 0x01, 0x4a, 0x93, 0x8a, 0xfa, 0x0f, 0x7d, 0x1b, 0xfd, 0x1b, 0x13, 0x0d, 0x00, 0x18, + 0x52, 0x85, 0xef, 0xf0, 0x1f, 0x87, 0xaa, 0x8c, 0x22, 0x85, 0xef, 0x20, 0xd0, 0x0f, 0x93, 0xf9, + 0x09, 0xf0, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, 0x44, 0x00, 0xef, 0x20, 0xd0, 0x0e, 0x22, 0x05, + 0xb3, 0xf9, 0x59, 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, 0x84, 0x00, 0xef, 0x20, 0xb0, 0x0d, + 0x42, 0x05, 0xb3, 0xf9, 0x69, 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, 0xc4, 0x00, 0xef, 0x20, + 0x90, 0x0c, 0x62, 0x05, 0xb3, 0xf9, 0x79, 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x93, 0xc7, 0xf9, 0xff, + 0x33, 0xf5, 0x97, 0x01, 0xe3, 0x1b, 0x05, 0xea, 0x11, 0x0a, 0x41, 0x04, 0xe3, 0x12, 0xaa, 0xfb, + 0x37, 0x55, 0x10, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x13, 0x05, 0x85, 0x5e, + 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x10, 0xf0, 0x1a, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x40, 0x05, + 0x93, 0x85, 0x45, 0x53, 0x68, 0x10, 0xef, 0x40, 0xc0, 0x24, 0x60, 0x10, 0x48, 0x40, 0x01, 0xc5, + 0xef, 0x20, 0xa0, 0x7f, 0x48, 0xc0, 0x31, 0x04, 0x1c, 0x01, 0xe3, 0x99, 0x87, 0xfe, 0x37, 0x55, + 0x10, 0x00, 0x1d, 0x46, 0x6c, 0x10, 0x13, 0x05, 0xc5, 0x5f, 0xef, 0x20, 0x40, 0x42, 0xef, 0xf0, + 0x0f, 0xe3, 0x05, 0x45, 0xef, 0x10, 0xd0, 0x02, 0xef, 0x30, 0xa0, 0x4e, 0xef, 0x30, 0x50, 0x21, + 0x01, 0x45, 0xef, 0x30, 0xf0, 0x5d, 0xb7, 0x0a, 0x20, 0x00, 0x93, 0x87, 0x0a, 0x00, 0x05, 0x6b, + 0xb3, 0x8b, 0x67, 0x01, 0xb7, 0x17, 0x20, 0x00, 0x13, 0x8a, 0xc7, 0x07, 0xef, 0x10, 0x40, 0x66, + 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x87, 0xf3, 0x63, 0x82, 0x07, 0x10, 0x37, 0x37, 0x20, 0x00, + 0x03, 0x27, 0x47, 0xf3, 0x63, 0x9c, 0xe7, 0x0e, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xc7, 0x07, 0xf3, + 0x93, 0x87, 0x07, 0xf3, 0x3e, 0xcc, 0xe3, 0x1d, 0x07, 0x36, 0x03, 0xa6, 0x0b, 0x07, 0x93, 0x07, + 0xf0, 0x07, 0xb7, 0x19, 0x20, 0x00, 0xa3, 0x8c, 0xfb, 0x06, 0xc1, 0x4c, 0x13, 0x8d, 0x0a, 0x00, + 0x93, 0x89, 0x09, 0x00, 0x63, 0xfe, 0xcc, 0x0a, 0x13, 0x04, 0x06, 0xff, 0xef, 0x10, 0x60, 0x72, + 0x01, 0x45, 0xef, 0x30, 0x60, 0x4f, 0x22, 0x86, 0x63, 0xf3, 0x8c, 0x00, 0x41, 0x46, 0x93, 0x85, + 0x0a, 0x00, 0x68, 0x10, 0xef, 0x30, 0x20, 0x50, 0xef, 0x10, 0xc0, 0x77, 0xb7, 0x57, 0x10, 0x00, + 0x23, 0x8c, 0xa9, 0x06, 0x93, 0x87, 0x87, 0x58, 0x03, 0xc7, 0x07, 0x00, 0x63, 0x1b, 0x07, 0x12, + 0x03, 0xa4, 0x09, 0x07, 0xc1, 0x47, 0xe3, 0xf2, 0x87, 0xda, 0x01, 0x45, 0xef, 0x30, 0xc0, 0x4b, + 0x41, 0x14, 0x22, 0x86, 0x93, 0x85, 0x0a, 0x00, 0x13, 0x85, 0x0a, 0x00, 0xef, 0x30, 0xa0, 0x4c, + 0xb7, 0x1c, 0x20, 0x00, 0x13, 0x85, 0x0c, 0x02, 0xef, 0x30, 0xa0, 0x68, 0xef, 0x30, 0x20, 0x6d, + 0x37, 0x56, 0x10, 0x00, 0xb7, 0x5d, 0x10, 0x00, 0xaa, 0x86, 0x13, 0x06, 0x46, 0x45, 0x93, 0x85, + 0xcd, 0x3d, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0xf0, 0x49, 0x93, 0x85, 0x0c, 0x02, 0x41, 0x46, + 0x33, 0x05, 0x8d, 0x00, 0xef, 0x00, 0x30, 0x38, 0xaa, 0x8c, 0xc1, 0x47, 0x63, 0x09, 0x05, 0x0e, + 0x89, 0x45, 0x13, 0x85, 0xcd, 0x3d, 0xef, 0x00, 0x50, 0x4f, 0x37, 0x55, 0x10, 0x00, 0x93, 0x07, + 0xb0, 0x07, 0x91, 0x45, 0x13, 0x05, 0xc5, 0x3f, 0xa3, 0x8c, 0xf9, 0x06, 0xef, 0x00, 0xf0, 0x4d, + 0xef, 0xe0, 0x9f, 0xf7, 0xef, 0xf0, 0xcf, 0x87, 0xef, 0xf0, 0x4f, 0xc3, 0xef, 0x10, 0xa0, 0x53, + 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x17, 0xf5, 0x08, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xc7, + 0x07, 0xf3, 0xc9, 0xe3, 0xef, 0x10, 0xa0, 0x02, 0xe3, 0x15, 0x85, 0x20, 0xd2, 0x47, 0x9c, 0x43, + 0x63, 0x94, 0xa7, 0x00, 0xef, 0x10, 0xc0, 0x18, 0xb2, 0x47, 0x98, 0x43, 0x93, 0x07, 0xa0, 0x0a, + 0xe3, 0x13, 0xf7, 0x1e, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0x86, 0x4d, 0x93, 0x05, 0x4c, 0x41, + 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x10, 0x41, 0xef, 0xf0, 0x4f, 0xbe, 0x37, 0x25, 0x00, 0x08, + 0xef, 0x20, 0x70, 0x0d, 0xef, 0xf0, 0x4f, 0xa8, 0xef, 0x20, 0x60, 0x5f, 0xef, 0x10, 0x50, 0x1c, + 0xef, 0x20, 0x30, 0x21, 0xef, 0xe0, 0xff, 0xf3, 0x32, 0x47, 0x37, 0x56, 0x10, 0x00, 0x93, 0x07, + 0x50, 0x05, 0x13, 0x06, 0x46, 0x4e, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, 0x64, 0x1c, 0xc3, + 0xef, 0x00, 0x50, 0x3d, 0xef, 0x20, 0x10, 0x21, 0xef, 0x10, 0x70, 0x48, 0xef, 0x20, 0x20, 0x5f, + 0xef, 0x30, 0x90, 0x00, 0xc2, 0x47, 0x98, 0x43, 0x93, 0x07, 0x50, 0x05, 0xe3, 0x08, 0xf7, 0xe4, + 0xad, 0xb9, 0x63, 0x1c, 0xe5, 0x00, 0x83, 0xc7, 0x17, 0x00, 0xbd, 0x8b, 0xe3, 0x82, 0x07, 0xec, + 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0xa0, 0x59, 0x65, 0xbd, 0x91, 0x07, 0x75, 0xb5, 0x03, 0xa4, + 0x09, 0x07, 0xe3, 0xe4, 0x87, 0x16, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0xc5, 0x3f, + 0xef, 0x00, 0xb0, 0x3f, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x3f, 0x95, 0x45, 0xef, 0x00, + 0xd0, 0x3e, 0x13, 0x05, 0xf0, 0x07, 0x39, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xf5, + 0x94, 0x43, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x87, 0x16, 0x00, 0x98, 0xc3, + 0x03, 0xc7, 0x89, 0x07, 0xa2, 0x87, 0x13, 0x06, 0x46, 0x46, 0x93, 0x85, 0xc5, 0x3f, 0x13, 0x05, + 0x49, 0x64, 0xef, 0x00, 0x30, 0x34, 0xb7, 0x17, 0x20, 0x00, 0x13, 0x85, 0xc7, 0x07, 0x3d, 0x46, + 0x81, 0x45, 0xef, 0x30, 0xd0, 0x7f, 0x83, 0xc7, 0x89, 0x07, 0x13, 0x07, 0x20, 0x04, 0x63, 0x80, + 0xe7, 0x56, 0x63, 0x69, 0xf7, 0x16, 0x13, 0x07, 0x10, 0x02, 0x63, 0x89, 0xe7, 0x3e, 0x63, 0x60, + 0xf7, 0x08, 0x45, 0x47, 0x63, 0x82, 0xe7, 0x30, 0x63, 0x69, 0xf7, 0x02, 0x05, 0x47, 0x63, 0x85, + 0xe7, 0x24, 0x41, 0x47, 0x63, 0x8d, 0xe7, 0x26, 0x89, 0x49, 0x3d, 0xa3, 0x93, 0x87, 0x07, 0xfa, + 0x93, 0xf7, 0xf7, 0x0f, 0x45, 0x47, 0xe3, 0x69, 0xf7, 0xfe, 0x37, 0x57, 0x10, 0x00, 0x8a, 0x07, + 0x13, 0x07, 0xc7, 0x4e, 0xba, 0x97, 0x9c, 0x43, 0x82, 0x87, 0x49, 0x47, 0x63, 0x82, 0xe7, 0x34, + 0x13, 0x07, 0x00, 0x02, 0xe3, 0x9a, 0xe7, 0xfc, 0x42, 0x04, 0x41, 0x80, 0xa1, 0x47, 0xe3, 0x13, + 0xf4, 0xf4, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x81, + 0x63, 0x97, 0x07, 0x54, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe3, 0xa7, 0x54, 0x83, 0x25, 0x4d, 0x00, + 0xef, 0x10, 0x90, 0x1e, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x1b, 0xf5, 0x52, 0xad, 0xa6, 0x13, 0x07, + 0x10, 0x03, 0x63, 0x86, 0xe7, 0x3a, 0x63, 0x6f, 0xf7, 0x04, 0x13, 0x07, 0x20, 0x02, 0x63, 0x87, + 0xe7, 0x38, 0x13, 0x07, 0x00, 0x03, 0xe3, 0x91, 0xe7, 0xf8, 0x42, 0x04, 0x41, 0x80, 0x91, 0x47, + 0xe3, 0x1a, 0xf4, 0xee, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x97, 0x07, 0x01, 0x8d, 0x8b, + 0x41, 0x83, 0x63, 0x9e, 0x07, 0x4e, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xea, 0xe7, 0x4e, 0x03, 0x45, + 0x3d, 0x00, 0xfd, 0x47, 0x63, 0xe5, 0xa7, 0x4e, 0x93, 0x15, 0x25, 0x00, 0x0d, 0x81, 0x93, 0xf7, + 0xc5, 0x01, 0x3a, 0x95, 0xbd, 0x45, 0xb3, 0x95, 0xf5, 0x00, 0x0a, 0x05, 0x93, 0xc5, 0xf5, 0xff, + 0x5a, 0x95, 0x05, 0xa4, 0x13, 0x07, 0x00, 0x04, 0x63, 0x8f, 0xe7, 0x3a, 0x13, 0x07, 0x10, 0x04, + 0xe3, 0x94, 0xe7, 0xf2, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x1d, 0xf4, 0xe8, 0x83, 0x26, + 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0xa1, 0x82, 0xc2, 0x06, 0xc1, 0x82, 0x63, 0xe1, 0xd7, 0x4a, + 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x86, 0x4b, 0x93, 0x85, 0xc5, 0x4a, + 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x10, 0x1f, 0xef, 0x10, 0x50, 0x57, 0xef, 0x20, 0x00, 0x75, + 0x83, 0x27, 0x0d, 0x00, 0x91, 0x65, 0x93, 0x85, 0x05, 0x20, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, + 0xa6, 0x07, 0x37, 0x15, 0x20, 0x00, 0xbe, 0x95, 0x13, 0x05, 0x05, 0x08, 0xef, 0x10, 0x30, 0x19, + 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x74, 0x93, 0x07, 0xc0, 0x1b, 0xe3, 0xe0, 0x87, 0xa8, 0x93, 0x05, + 0x44, 0x00, 0x29, 0xac, 0x13, 0x07, 0x10, 0x07, 0x63, 0x69, 0xf7, 0x02, 0x13, 0x07, 0xf0, 0x05, + 0xe3, 0x66, 0xf7, 0xea, 0x13, 0x07, 0x00, 0x05, 0xe3, 0x90, 0xe7, 0xea, 0x42, 0x04, 0x41, 0x80, + 0x89, 0x47, 0xe3, 0x19, 0xf4, 0xe0, 0x03, 0x44, 0x1d, 0x00, 0x37, 0x15, 0x20, 0x00, 0x13, 0x05, + 0x05, 0x08, 0xa2, 0x85, 0xef, 0xe0, 0x1f, 0xd7, 0xd9, 0xb7, 0x13, 0x07, 0x20, 0x08, 0x63, 0x8b, + 0xe7, 0x6e, 0x63, 0x6d, 0xf7, 0x04, 0x13, 0x07, 0x00, 0x08, 0x63, 0x82, 0xe7, 0x68, 0x13, 0x07, + 0x10, 0x08, 0xe3, 0x93, 0xe7, 0xe6, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x1c, 0xf4, 0xdc, + 0x03, 0x45, 0x1d, 0x00, 0x3d, 0x47, 0x81, 0x47, 0x63, 0x6e, 0xa7, 0x00, 0xb7, 0x37, 0x20, 0x00, + 0x03, 0xa7, 0x47, 0xf5, 0x89, 0x47, 0x33, 0x57, 0xa7, 0x00, 0x05, 0x8b, 0x01, 0xc7, 0xef, 0xe0, + 0x7f, 0xe6, 0xaa, 0x87, 0xfd, 0x17, 0x09, 0x47, 0x63, 0x63, 0xf7, 0x3c, 0x37, 0x55, 0x10, 0x00, + 0x13, 0x05, 0x85, 0x72, 0xaa, 0x97, 0x83, 0xc9, 0x07, 0x00, 0x1d, 0xaa, 0x13, 0x07, 0x00, 0x09, + 0xe3, 0x9c, 0xe7, 0xe0, 0x93, 0x17, 0x04, 0x01, 0xc1, 0x83, 0x13, 0x07, 0x30, 0x02, 0xe3, 0x73, + 0xf7, 0xd8, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0xbe, 0x86, 0x13, 0x06, 0x06, 0x4c, + 0x93, 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0xd0, 0x0e, 0xef, 0x20, 0xa0, 0x0d, + 0xef, 0x20, 0xc0, 0x64, 0xef, 0x20, 0x20, 0x0e, 0x2a, 0x84, 0xef, 0x20, 0x40, 0x0d, 0xef, 0x20, + 0x00, 0x66, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x14, 0xf4, 0x36, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, + 0x00, 0x2c, 0x93, 0x07, 0x40, 0x02, 0x81, 0xa3, 0x93, 0x19, 0x04, 0x01, 0x93, 0xd9, 0x09, 0x01, + 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0xce, 0x86, 0x13, 0x06, 0x06, 0x4a, 0x93, 0x85, + 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0xf0, 0x09, 0x93, 0x07, 0x1b, 0x00, 0xe3, 0xeb, + 0x37, 0xd1, 0xce, 0x85, 0x13, 0x85, 0x0a, 0x00, 0xef, 0xf0, 0x4f, 0x8e, 0xa9, 0xaa, 0x42, 0x04, + 0x41, 0x80, 0x93, 0x07, 0x40, 0x02, 0xe3, 0x1f, 0xf4, 0xce, 0x03, 0x25, 0x0d, 0x00, 0x0d, 0x44, + 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0x64, 0xa4, 0x30, 0xef, 0xf0, 0x8f, 0xae, 0xd5, 0x47, + 0x63, 0x1f, 0xf5, 0x2e, 0x83, 0x29, 0x0d, 0x00, 0x93, 0xd9, 0x89, 0x00, 0xc2, 0x09, 0x93, 0xd9, + 0x09, 0x01, 0xe3, 0x6c, 0x34, 0x91, 0x13, 0x84, 0x09, 0x0e, 0x16, 0x04, 0x91, 0x4c, 0x71, 0x14, + 0x93, 0x0d, 0x40, 0x02, 0xb3, 0x05, 0x9d, 0x01, 0x11, 0x46, 0x68, 0x10, 0xef, 0x30, 0x70, 0x4c, + 0xb2, 0x55, 0x33, 0x05, 0x94, 0x01, 0x91, 0x0c, 0xef, 0x20, 0x20, 0x33, 0xe3, 0x94, 0xbc, 0xff, + 0x09, 0x65, 0x8a, 0x09, 0xb7, 0xf5, 0xf0, 0xf0, 0x13, 0x05, 0x05, 0xbf, 0x93, 0x85, 0x05, 0x0f, + 0x4e, 0x95, 0xef, 0x20, 0x80, 0x31, 0xc5, 0xa0, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x13, + 0xf4, 0xc8, 0x03, 0x25, 0x0d, 0x00, 0x0d, 0x44, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0x68, + 0xa4, 0x28, 0xef, 0xf0, 0x0f, 0xa7, 0x93, 0x07, 0x30, 0x0c, 0x63, 0x08, 0xf5, 0x00, 0xaa, 0x89, + 0x93, 0x07, 0x00, 0x08, 0x63, 0x9a, 0xf9, 0x20, 0xb1, 0xb9, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, + 0xc2, 0x07, 0xc1, 0x83, 0xe3, 0x6b, 0xf4, 0x88, 0x93, 0x87, 0x07, 0x0e, 0x13, 0x94, 0x57, 0x00, + 0x93, 0x09, 0x00, 0x02, 0x33, 0x05, 0x94, 0x01, 0xef, 0x20, 0x20, 0x20, 0xb7, 0x17, 0x20, 0x00, + 0x93, 0x87, 0x07, 0x08, 0x2a, 0xd6, 0x11, 0x46, 0x33, 0x85, 0x97, 0x01, 0x6c, 0x10, 0x91, 0x0c, + 0xef, 0x30, 0x30, 0x43, 0xe3, 0x90, 0x3c, 0xff, 0x93, 0x05, 0x40, 0x02, 0x52, 0x85, 0x29, 0xb7, + 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x17, 0xf4, 0xc0, 0x03, 0x25, 0x0d, 0x00, 0x21, 0x81, + 0x42, 0x05, 0x41, 0x81, 0x63, 0x6d, 0xa4, 0x20, 0xef, 0xf0, 0xaf, 0x9f, 0xd5, 0x47, 0x63, 0x08, + 0xf5, 0x20, 0xd9, 0x47, 0x63, 0x01, 0xf5, 0x04, 0x83, 0x29, 0x0d, 0x00, 0x93, 0xd9, 0x89, 0x00, + 0xc2, 0x09, 0x93, 0xd9, 0x09, 0x01, 0xe3, 0x62, 0x34, 0x83, 0x89, 0x67, 0x13, 0x95, 0x29, 0x00, + 0x93, 0x87, 0x07, 0xbf, 0x81, 0x45, 0x3e, 0x95, 0x93, 0x89, 0x09, 0x0e, 0xef, 0x20, 0xe0, 0x24, + 0x96, 0x09, 0x13, 0x04, 0x00, 0x02, 0x33, 0x85, 0x99, 0x01, 0x81, 0x45, 0x91, 0x0c, 0xef, 0x20, + 0xc0, 0x23, 0xe3, 0x9a, 0x8c, 0xfe, 0x93, 0x09, 0x30, 0x0c, 0xb9, 0xaa, 0x42, 0x04, 0x41, 0x80, + 0x8d, 0x47, 0xe3, 0x11, 0xf4, 0xba, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, 0x07, 0x01, + 0x8d, 0x8b, 0x41, 0x81, 0x63, 0x95, 0x07, 0x1a, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe1, 0xa7, 0x1a, + 0xef, 0x10, 0x60, 0x5b, 0x23, 0x22, 0xaa, 0x00, 0xa1, 0x45, 0x8d, 0xb7, 0x42, 0x04, 0x41, 0x80, + 0x85, 0x47, 0x01, 0x45, 0xe3, 0x18, 0xf4, 0xb6, 0xef, 0x10, 0x30, 0x24, 0x6d, 0xbf, 0x42, 0x04, + 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x10, 0xf4, 0xb6, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x94, + 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x80, 0x63, 0x94, 0x07, 0x16, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe0, + 0x87, 0x16, 0x0a, 0x04, 0x33, 0x05, 0x64, 0x01, 0xef, 0x20, 0xe0, 0x17, 0x93, 0xf4, 0x04, 0xf0, + 0xc9, 0x8c, 0x13, 0x05, 0x4b, 0x00, 0x22, 0x95, 0xef, 0x20, 0xe0, 0x16, 0xc1, 0x77, 0x93, 0x87, + 0xf7, 0x0f, 0xfd, 0x8c, 0x22, 0x05, 0xc9, 0x8c, 0x13, 0x05, 0x8b, 0x00, 0x22, 0x95, 0xef, 0x20, + 0x80, 0x15, 0xb7, 0x07, 0x01, 0xff, 0xfd, 0x17, 0x42, 0x05, 0xfd, 0x8c, 0xc9, 0x8c, 0x13, 0x05, + 0xcb, 0x00, 0x22, 0x95, 0xef, 0x20, 0x20, 0x14, 0xa2, 0x04, 0x62, 0x05, 0xa1, 0x80, 0xc9, 0x8c, + 0x23, 0x22, 0x9a, 0x00, 0x95, 0xbf, 0x93, 0x07, 0xb4, 0xff, 0xc2, 0x07, 0xc1, 0x83, 0x13, 0x07, + 0xb0, 0x1b, 0xe3, 0x61, 0xf7, 0xae, 0x83, 0x26, 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0x93, 0x09, + 0xc0, 0x03, 0xa1, 0x82, 0xc2, 0x06, 0xc1, 0x82, 0x63, 0xe0, 0xd7, 0x08, 0x37, 0x56, 0x10, 0x00, + 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x06, 0x4b, 0x93, 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, + 0xef, 0x00, 0x40, 0x63, 0x03, 0x25, 0x0d, 0x00, 0x91, 0x69, 0x93, 0x89, 0x09, 0x20, 0x21, 0x81, + 0x42, 0x05, 0x41, 0x81, 0x26, 0x05, 0x4e, 0x95, 0xef, 0x10, 0x30, 0x13, 0x93, 0x07, 0xa0, 0x0a, + 0xaa, 0x8c, 0x63, 0x12, 0xf5, 0x04, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0xbf, 0x9f, 0xef, 0x20, + 0xe0, 0x36, 0x83, 0x27, 0x0d, 0x00, 0x42, 0x04, 0x41, 0x80, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, + 0xa6, 0x07, 0xb7, 0x05, 0x20, 0x00, 0x13, 0x06, 0xc4, 0xff, 0x33, 0x85, 0x37, 0x01, 0x74, 0x10, + 0x93, 0x85, 0x45, 0x00, 0xef, 0x10, 0xf0, 0x02, 0x2a, 0x84, 0x93, 0x09, 0x30, 0x0c, 0xef, 0x20, + 0x00, 0x36, 0x63, 0x03, 0x94, 0x01, 0xc1, 0x49, 0x13, 0xf5, 0xf9, 0x0f, 0xe5, 0xae, 0x42, 0x04, + 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x10, 0xf4, 0xa4, 0x03, 0x25, 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, + 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0xe4, 0xa7, 0x04, 0x91, 0x67, 0x26, 0x05, 0x93, 0x87, + 0x07, 0x20, 0x3e, 0x95, 0x55, 0xbd, 0x42, 0x04, 0x41, 0x80, 0x91, 0x47, 0xe3, 0x1c, 0xf4, 0xa0, + 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0x1f, 0x98, 0x68, 0x10, 0xef, 0x10, 0x80, 0x7c, 0xef, 0x30, + 0xa0, 0x20, 0xef, 0x20, 0xa0, 0x2e, 0x91, 0x45, 0x13, 0x05, 0x00, 0x06, 0xef, 0x30, 0xc0, 0x42, + 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x2f, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x0e, 0xf4, 0xe2, 0x93, 0x09, + 0xc0, 0x03, 0x59, 0xbf, 0x42, 0x04, 0x41, 0x80, 0x93, 0x07, 0x00, 0x03, 0xe3, 0x1c, 0xf4, 0x9c, + 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0x1f, 0x94, 0x68, 0x10, 0xef, 0x10, 0x80, 0x78, 0xef, 0x30, + 0xa0, 0x1c, 0xef, 0x20, 0xa0, 0x2a, 0x93, 0x05, 0x00, 0x03, 0x13, 0x05, 0x10, 0x06, 0x7d, 0xbf, + 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x17, 0xf4, 0x9a, 0xef, 0x30, 0xe0, 0x1a, 0xef, 0x20, + 0xe0, 0x28, 0x8d, 0x45, 0x13, 0x05, 0x20, 0x06, 0xef, 0x30, 0x00, 0x3d, 0x2a, 0x84, 0xef, 0x20, + 0x00, 0x2a, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x14, 0xf4, 0xfa, 0xef, 0xe0, 0x7f, 0xf0, 0x05, 0xb3, + 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x1f, 0xf4, 0x96, 0xef, 0x30, 0xe0, 0x17, 0x8d, 0x45, + 0x13, 0x05, 0x30, 0x06, 0xef, 0x30, 0x40, 0x3a, 0xb1, 0xb4, 0x42, 0x04, 0x41, 0x80, 0x93, 0x07, + 0x00, 0x03, 0xe3, 0x11, 0xf4, 0x96, 0xef, 0x30, 0x20, 0x16, 0xef, 0x20, 0x50, 0x6f, 0xb7, 0x15, + 0x20, 0x00, 0x2a, 0xd6, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, + 0xef, 0x30, 0x60, 0x26, 0x11, 0x46, 0x6c, 0x10, 0x13, 0x05, 0x00, 0x0c, 0xef, 0x30, 0xa0, 0x25, + 0xef, 0x20, 0xc0, 0x21, 0x93, 0x05, 0x00, 0x03, 0x13, 0x05, 0x00, 0x07, 0xef, 0x30, 0xc0, 0x35, + 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x22, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1a, 0xf4, 0xf2, 0xef, 0xe0, + 0x3f, 0xe9, 0x75, 0xb1, 0x93, 0x17, 0x04, 0x01, 0xc1, 0x83, 0x3d, 0x47, 0xe3, 0x74, 0xf7, 0x90, + 0xef, 0x30, 0x80, 0x10, 0xef, 0x20, 0xb0, 0x69, 0xaa, 0x8c, 0x01, 0x45, 0xef, 0x20, 0xd0, 0x45, + 0x41, 0x46, 0x93, 0x85, 0x0a, 0x00, 0x01, 0x45, 0xef, 0x20, 0xf0, 0x46, 0xef, 0x20, 0x00, 0x1d, + 0xb7, 0x15, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, + 0x66, 0xd6, 0xef, 0x30, 0x40, 0x1f, 0x11, 0x46, 0x6c, 0x10, 0x13, 0x05, 0x00, 0x0c, 0xef, 0x30, + 0x80, 0x1e, 0x85, 0x45, 0x13, 0x05, 0x10, 0x04, 0xef, 0x30, 0x00, 0x2f, 0x93, 0x07, 0xa0, 0x0a, + 0xaa, 0x8c, 0x63, 0x19, 0xf5, 0x00, 0x81, 0x45, 0x13, 0x05, 0x20, 0x04, 0xef, 0x30, 0xc0, 0x2d, + 0x63, 0x05, 0x95, 0x01, 0xef, 0x20, 0xa0, 0x1a, 0x5d, 0xbd, 0x42, 0x04, 0x41, 0x80, 0x93, 0x0d, + 0x04, 0xff, 0xef, 0x20, 0xc0, 0x19, 0xee, 0x8c, 0x22, 0x9d, 0x93, 0x07, 0x00, 0x09, 0xb3, 0x05, + 0x9d, 0x41, 0x63, 0xe5, 0x97, 0x09, 0x66, 0x86, 0x01, 0x45, 0xef, 0x20, 0xd0, 0x3f, 0xe6, 0x85, + 0x13, 0x05, 0x40, 0x04, 0xef, 0x30, 0x40, 0x2a, 0x13, 0x07, 0xa0, 0x0a, 0xe3, 0x11, 0xe5, 0xe8, + 0x2a, 0xce, 0x81, 0x45, 0x13, 0x05, 0x50, 0x04, 0xef, 0x30, 0x00, 0x29, 0xf2, 0x47, 0xaa, 0x8c, + 0xe3, 0x17, 0xf5, 0xe6, 0x01, 0x45, 0xef, 0x20, 0x30, 0x3b, 0x93, 0x85, 0x0a, 0x00, 0x41, 0x46, + 0x01, 0x45, 0xef, 0x20, 0x50, 0x3c, 0x93, 0x07, 0xf0, 0x03, 0xb7, 0x05, 0x20, 0x00, 0x63, 0xe1, + 0xb7, 0x07, 0x93, 0x85, 0x05, 0x01, 0x01, 0x45, 0x6e, 0x86, 0xef, 0x20, 0xd0, 0x3a, 0xee, 0x85, + 0x13, 0x05, 0x60, 0x04, 0xef, 0x30, 0x40, 0x25, 0xe3, 0x1b, 0x95, 0xe3, 0x81, 0x45, 0x13, 0x05, + 0xa0, 0x04, 0xef, 0x30, 0x60, 0x24, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x12, 0xf5, 0xe2, 0xef, 0x20, + 0x10, 0x58, 0x93, 0x07, 0x00, 0x05, 0x23, 0xaa, 0xf9, 0x06, 0xb1, 0xb1, 0x13, 0x06, 0x00, 0x09, + 0x01, 0x45, 0xef, 0x20, 0x50, 0x37, 0x93, 0x05, 0x00, 0x09, 0x13, 0x05, 0x30, 0x04, 0xef, 0x30, + 0xa0, 0x21, 0x13, 0x07, 0xa0, 0x0a, 0xe3, 0x1c, 0xe5, 0xde, 0x93, 0x8c, 0x0c, 0xf7, 0xb1, 0xb7, + 0x93, 0x85, 0x05, 0x01, 0x01, 0x45, 0x13, 0x06, 0x00, 0x04, 0xef, 0x20, 0xd0, 0x34, 0x93, 0x05, + 0x00, 0x04, 0x13, 0x05, 0x70, 0x04, 0xef, 0x30, 0x20, 0x1f, 0xe3, 0x1a, 0x95, 0xdd, 0x13, 0x04, + 0x04, 0xfb, 0x93, 0x0c, 0x00, 0x08, 0x93, 0x0d, 0xa0, 0x0a, 0xb3, 0x05, 0x8d, 0x40, 0x63, 0xe0, + 0x8c, 0x02, 0x22, 0x86, 0x01, 0x45, 0xef, 0x20, 0x10, 0x32, 0xa2, 0x85, 0x13, 0x05, 0x90, 0x04, + 0xef, 0x30, 0x80, 0x1c, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x13, 0xf5, 0xda, 0x85, 0xbf, 0x01, 0x45, + 0x13, 0x06, 0x00, 0x08, 0xef, 0x20, 0x30, 0x30, 0x93, 0x05, 0x00, 0x08, 0x13, 0x05, 0x80, 0x04, + 0xef, 0x30, 0x80, 0x1a, 0xe3, 0x15, 0xb5, 0xd9, 0x13, 0x04, 0x04, 0xf8, 0x7d, 0xbf, 0x42, 0x04, + 0x41, 0x80, 0xa1, 0x47, 0x63, 0x10, 0xf4, 0xf6, 0x03, 0x44, 0x1d, 0x00, 0xbd, 0x47, 0xe3, 0xe8, + 0x87, 0xd6, 0x83, 0x2c, 0x4d, 0x00, 0xfd, 0x57, 0xe3, 0x83, 0xfc, 0xd6, 0x93, 0x19, 0xa4, 0x00, + 0x13, 0x85, 0x09, 0x40, 0xef, 0xe0, 0x8f, 0xe6, 0x13, 0x07, 0xa0, 0x0a, 0x2a, 0x8d, 0xe3, 0x18, + 0xe5, 0xd4, 0x93, 0x89, 0x09, 0x20, 0x4e, 0x85, 0xef, 0xe0, 0x4f, 0xe5, 0xaa, 0x8d, 0xe3, 0x10, + 0xa5, 0xd5, 0xe6, 0x85, 0x4e, 0x85, 0xef, 0x10, 0x60, 0x1b, 0xe3, 0x1a, 0xb5, 0xd3, 0x37, 0x37, + 0x20, 0x00, 0x13, 0x07, 0x47, 0xf5, 0x85, 0x47, 0x33, 0x94, 0x87, 0x00, 0x1c, 0x43, 0x5d, 0x8c, + 0x00, 0xc3, 0x91, 0xbe, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0x63, 0x1d, 0xf4, 0xee, 0x83, 0x45, + 0x1d, 0x00, 0xbd, 0x47, 0xe3, 0xe5, 0xb7, 0xd0, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf5, + 0xd1, 0x49, 0xb3, 0xd7, 0xb7, 0x00, 0x85, 0x8b, 0xe3, 0x88, 0x07, 0xc8, 0x37, 0x15, 0x20, 0x00, + 0x13, 0x05, 0x05, 0x08, 0xef, 0xe0, 0x6f, 0xeb, 0x85, 0x47, 0xe3, 0x07, 0xf5, 0xb4, 0x89, 0x47, + 0xe3, 0x0c, 0xf5, 0xc6, 0xe9, 0xb9, 0xef, 0x10, 0x90, 0x43, 0xef, 0xe0, 0x8f, 0xd8, 0x6f, 0xf0, + 0xef, 0xe6, 0xef, 0x00, 0xc0, 0x6f, 0x6f, 0xf0, 0xef, 0xe6, 0xef, 0x00, 0x30, 0x4e, 0x41, 0x14, + 0xaa, 0x86, 0x63, 0x0b, 0x05, 0xea, 0x8d, 0x45, 0x13, 0x85, 0xcd, 0x3d, 0x36, 0xce, 0x71, 0x24, + 0xf2, 0x46, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x45, 0x93, 0x85, 0xcd, 0x3d, 0x13, 0x05, + 0x49, 0x64, 0x09, 0x24, 0xf2, 0x46, 0x09, 0x47, 0x85, 0x47, 0x63, 0x83, 0xe6, 0x00, 0x89, 0x47, + 0x83, 0xc6, 0x89, 0x07, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x22, 0x87, 0x13, 0x06, + 0xc6, 0x47, 0x93, 0x85, 0xc5, 0x3f, 0x13, 0x05, 0x49, 0x64, 0xa3, 0x8c, 0xf9, 0x06, 0xd9, 0x2a, + 0xef, 0xe0, 0x8f, 0xce, 0xef, 0xe0, 0x8f, 0xff, 0x62, 0x47, 0x85, 0x47, 0x23, 0x00, 0xf7, 0x00, + 0xef, 0x00, 0xe0, 0x5a, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x11, 0xf5, 0xd6, 0x25, 0x29, + 0x63, 0x1e, 0x85, 0xd4, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xf4, 0xb1, 0xeb, 0x83, 0xa7, + 0x4b, 0x07, 0x13, 0x07, 0xfb, 0x00, 0xfd, 0x17, 0x63, 0x64, 0xf7, 0x04, 0x05, 0x45, 0xef, 0x20, + 0xb0, 0x17, 0x03, 0xa6, 0x4b, 0x07, 0xb7, 0x09, 0x20, 0x00, 0x93, 0x85, 0x09, 0x00, 0x13, 0x85, + 0x09, 0x00, 0xef, 0x20, 0xf0, 0x25, 0x37, 0x14, 0x20, 0x00, 0x13, 0x05, 0x04, 0x02, 0xef, 0x20, + 0x50, 0x34, 0x03, 0xa5, 0x4b, 0x07, 0x93, 0x87, 0x09, 0x00, 0x41, 0x46, 0x3e, 0x95, 0x93, 0x05, + 0x04, 0x02, 0xef, 0x30, 0x00, 0x5f, 0x83, 0xa7, 0x4b, 0x07, 0xc1, 0x07, 0x23, 0xaa, 0xfb, 0x06, + 0xef, 0x00, 0xf0, 0x1b, 0x13, 0x04, 0xa0, 0x0a, 0x63, 0x0a, 0x85, 0xce, 0xef, 0xe0, 0x8f, 0xfe, + 0x63, 0x16, 0x85, 0xce, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, + 0x13, 0x06, 0x06, 0x4d, 0x93, 0x85, 0xc5, 0x3f, 0x13, 0x05, 0x45, 0x40, 0x25, 0x22, 0xef, 0xe0, + 0x2f, 0xb7, 0xef, 0x20, 0x70, 0x32, 0xef, 0x00, 0xb0, 0x3a, 0xef, 0x00, 0xb0, 0x31, 0xef, 0xe0, + 0xaf, 0xf9, 0x6f, 0xf0, 0xaf, 0xcb, 0x2a, 0x87, 0x81, 0x47, 0x01, 0x45, 0x63, 0x93, 0xc7, 0x00, + 0x82, 0x80, 0xb3, 0x06, 0xf7, 0x00, 0x33, 0x88, 0xf5, 0x00, 0x83, 0xc6, 0x06, 0x00, 0x03, 0x48, + 0x08, 0x00, 0x85, 0x07, 0xb3, 0xc6, 0x06, 0x01, 0x55, 0x8d, 0x13, 0x75, 0xf5, 0x0f, 0xf9, 0xbf, + 0xb7, 0x37, 0x20, 0x00, 0x37, 0x37, 0x20, 0x00, 0x03, 0xa8, 0xc7, 0xf5, 0x83, 0x27, 0x87, 0xf5, + 0xaa, 0x86, 0x13, 0x07, 0x87, 0xf5, 0x01, 0x45, 0x63, 0x13, 0xf8, 0x00, 0x82, 0x80, 0x37, 0x26, + 0x20, 0x00, 0x13, 0x06, 0xc6, 0x08, 0x93, 0x08, 0xf0, 0x7f, 0x63, 0x01, 0xb5, 0x02, 0x33, 0x0e, + 0xf6, 0x00, 0x03, 0x4e, 0x0e, 0x00, 0x05, 0x05, 0x33, 0x83, 0xa6, 0x00, 0xa3, 0x0f, 0xc3, 0xff, + 0x85, 0x07, 0x63, 0xf3, 0xf8, 0x00, 0x81, 0x47, 0xe3, 0x11, 0xf8, 0xfe, 0x1c, 0xc3, 0x82, 0x80, + 0xb7, 0x36, 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x86, 0xf5, 0x83, 0xa7, 0xc7, 0xf5, + 0x93, 0x86, 0x86, 0xf5, 0x33, 0x87, 0xe7, 0x40, 0x63, 0x56, 0x07, 0x00, 0x05, 0x66, 0x13, 0x06, + 0x06, 0x80, 0x32, 0x97, 0x63, 0x5b, 0xe5, 0x00, 0x33, 0x85, 0xa7, 0x40, 0x85, 0x67, 0x93, 0x87, + 0x07, 0x80, 0x63, 0xf3, 0xa7, 0x00, 0x3e, 0x95, 0x88, 0xc2, 0x82, 0x80, 0xb7, 0x36, 0x20, 0x00, + 0x03, 0xa8, 0xc6, 0xf5, 0x13, 0x07, 0xf0, 0x7f, 0x13, 0x86, 0xc6, 0xf5, 0x93, 0x07, 0x18, 0x00, + 0x63, 0x73, 0xf7, 0x00, 0x81, 0x47, 0xb7, 0x36, 0x20, 0x00, 0x83, 0xa8, 0x86, 0xf5, 0x37, 0x27, + 0x20, 0x00, 0x93, 0x85, 0x86, 0xf5, 0x13, 0x07, 0xc7, 0x08, 0x63, 0x9f, 0xf8, 0x00, 0x93, 0x88, + 0x17, 0x80, 0x93, 0x86, 0x17, 0x00, 0x63, 0x93, 0x08, 0x00, 0x81, 0x46, 0x94, 0xc1, 0xba, 0x96, + 0x93, 0x05, 0xa0, 0x02, 0x23, 0x80, 0xb6, 0x00, 0x42, 0x97, 0x23, 0x00, 0xa7, 0x00, 0x1c, 0xc2, + 0x82, 0x80, 0x82, 0x80, 0x39, 0x71, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x06, 0xce, 0x36, 0xd6, + 0x3a, 0xd8, 0x3e, 0xda, 0x42, 0xdc, 0x46, 0xde, 0xaa, 0x84, 0x2e, 0x89, 0x32, 0x84, 0x19, 0xe1, + 0xef, 0xe0, 0xdf, 0x96, 0x63, 0x14, 0x09, 0x00, 0xef, 0xe0, 0x5f, 0x96, 0x19, 0xe0, 0xef, 0xe0, + 0xff, 0x95, 0x7c, 0x10, 0x3e, 0xc6, 0xef, 0x30, 0x20, 0x13, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, + 0x13, 0x05, 0x85, 0x60, 0xef, 0x30, 0x20, 0x38, 0x37, 0x55, 0x10, 0x00, 0x4a, 0x86, 0xa6, 0x85, + 0x13, 0x05, 0x05, 0x61, 0xef, 0x30, 0x20, 0x37, 0xb2, 0x45, 0x22, 0x85, 0xef, 0x30, 0x80, 0x33, + 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x61, 0xef, 0x30, 0xe0, 0x35, 0xb9, 0x29, 0xf2, 0x40, + 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0x21, 0x61, 0x82, 0x80, 0xae, 0x86, 0x37, 0x56, 0x10, 0x00, + 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x4b, 0x13, 0x05, 0x05, 0x62, 0x9d, 0xbf, + 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, 0x83, 0xa6, 0x47, 0x10, + 0x63, 0x7e, 0xd7, 0x00, 0x0a, 0x07, 0x3e, 0x97, 0x18, 0x43, 0x18, 0xc1, 0x03, 0xa7, 0x07, 0x10, + 0x13, 0x05, 0xa0, 0x0a, 0x05, 0x07, 0x23, 0xa0, 0xe7, 0x10, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, + 0x82, 0x80, 0x01, 0x11, 0x26, 0xca, 0xb7, 0x34, 0x20, 0x00, 0x83, 0xa7, 0x04, 0xf6, 0x06, 0xce, + 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x11, 0x47, 0x63, 0x6f, 0xf7, 0x0c, 0x37, 0x57, + 0x10, 0x00, 0x8a, 0x07, 0x13, 0x07, 0x87, 0x64, 0xba, 0x97, 0x9c, 0x43, 0x2a, 0x84, 0x93, 0x84, + 0x04, 0xf6, 0x82, 0x87, 0x81, 0x45, 0xef, 0x30, 0x20, 0x31, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x92, + 0xa7, 0xf6, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x86, 0x87, 0x88, 0xef, 0x20, 0xd0, 0x6f, 0x9c, 0x40, + 0x85, 0x07, 0x81, 0xa8, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0x07, 0xf6, 0x93, 0x07, 0xc0, 0x0f, + 0x63, 0xf1, 0xa7, 0x02, 0x62, 0x44, 0x9d, 0x47, 0xf2, 0x40, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, + 0x9c, 0xc0, 0xd2, 0x44, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x45, 0x62, 0x05, 0x61, + 0x2d, 0xbf, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x49, 0xf6, 0x83, 0x55, 0x09, 0x00, 0xef, 0x30, + 0xa0, 0x2b, 0xb7, 0x37, 0x20, 0x00, 0xa3, 0x86, 0x87, 0x88, 0x23, 0x10, 0xa9, 0x00, 0x8d, 0x47, + 0x5d, 0xf4, 0x9c, 0xc0, 0x91, 0xa8, 0x37, 0x39, 0x20, 0x00, 0x03, 0x27, 0x89, 0xf6, 0x93, 0x07, + 0xb0, 0x0f, 0x13, 0x09, 0x89, 0xf6, 0x63, 0xf4, 0xe7, 0x00, 0xef, 0xe0, 0x3f, 0x81, 0x83, 0x27, + 0x09, 0x00, 0x37, 0x3a, 0x20, 0x00, 0x13, 0x0a, 0x4a, 0xf6, 0xb7, 0x39, 0x20, 0x00, 0x93, 0x89, + 0xc9, 0x88, 0x83, 0x55, 0x0a, 0x00, 0xce, 0x97, 0x23, 0x81, 0x87, 0x00, 0x22, 0x85, 0xef, 0x30, + 0xa0, 0x26, 0x83, 0x27, 0x09, 0x00, 0x03, 0xc7, 0x19, 0x00, 0x23, 0x10, 0xaa, 0x00, 0x85, 0x07, + 0x23, 0x20, 0xf9, 0x00, 0xe3, 0xfd, 0xe7, 0xf4, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, + 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x93, 0xa7, 0xf6, + 0x3d, 0xbf, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x69, 0xf6, 0x13, 0x14, 0x85, 0x00, 0xb7, 0x39, + 0x20, 0x00, 0x03, 0x55, 0x09, 0x00, 0x93, 0x89, 0x49, 0xf6, 0x83, 0xd7, 0x09, 0x00, 0x49, 0x8c, + 0x23, 0x10, 0x89, 0x00, 0xe3, 0x8d, 0x87, 0xf0, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0x44, 0x62, + 0x99, 0x47, 0x89, 0x45, 0x9c, 0xc0, 0x95, 0x3d, 0x93, 0x05, 0x44, 0x62, 0x62, 0x44, 0x03, 0xd7, + 0x09, 0x00, 0x83, 0x56, 0x09, 0x00, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, + 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x86, 0x62, 0x13, 0x05, 0x45, 0x64, + 0x05, 0x61, 0x6f, 0xf0, 0x3f, 0xdd, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0xb7, 0x25, + 0x10, 0x00, 0x37, 0x25, 0x10, 0x00, 0x23, 0xa0, 0x07, 0x10, 0x23, 0xa2, 0x07, 0x10, 0x93, 0x85, + 0x05, 0xf8, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x05, 0x25, 0xfb, 0x23, 0xa0, 0x07, 0xf6, 0x6f, 0x20, + 0xb0, 0x52, 0x11, 0xed, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0xef, 0xe0, 0x2f, 0xf2, 0x32, 0x45, + 0xf2, 0x40, 0x13, 0x06, 0xe0, 0x0f, 0x81, 0x45, 0x05, 0x61, 0x6f, 0x30, 0x40, 0x25, 0x13, 0x06, + 0xe0, 0x0f, 0x81, 0x45, 0xdd, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xf6, 0x13, 0x05, + 0xa0, 0x0a, 0x99, 0xc3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, + 0x20, 0x00, 0x13, 0x04, 0x04, 0xf6, 0x1c, 0x40, 0x06, 0xc6, 0x15, 0x47, 0x63, 0x98, 0xe7, 0x00, + 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x81, 0xe7, 0x13, 0x05, + 0x50, 0x05, 0xcd, 0xbf, 0xef, 0x20, 0x90, 0x50, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x19, 0xf5, 0xfe, + 0x01, 0x00, 0x18, 0x40, 0x91, 0x47, 0xe3, 0xcd, 0xe7, 0xfc, 0x99, 0x47, 0x1c, 0xc0, 0xd9, 0xbf, + 0x41, 0x11, 0x06, 0xc6, 0xef, 0x20, 0x10, 0x50, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xf5, 0x00, + 0xef, 0x20, 0x70, 0x51, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x95, 0x47, 0x13, 0x05, + 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, + 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x99, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, + 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, + 0x9d, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, + 0x37, 0x35, 0x20, 0x00, 0x13, 0x05, 0xc5, 0x88, 0x82, 0x80, 0x01, 0x11, 0x26, 0xca, 0x06, 0xce, + 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0xaa, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, 0xe3, 0x83, 0xc7, + 0x14, 0x00, 0x13, 0x07, 0xc0, 0x0f, 0x13, 0x05, 0x50, 0x05, 0x63, 0x65, 0xf7, 0x06, 0x37, 0x39, + 0x20, 0x00, 0x13, 0x04, 0xc9, 0x98, 0x23, 0x20, 0x04, 0x10, 0x03, 0xc7, 0x04, 0x00, 0xa3, 0x00, + 0xf4, 0x00, 0x03, 0xc6, 0x14, 0x00, 0x23, 0x00, 0xe4, 0x00, 0x93, 0x85, 0x24, 0x00, 0x13, 0x05, + 0x24, 0x00, 0xef, 0x30, 0x00, 0x10, 0x83, 0xc9, 0x14, 0x00, 0x13, 0x05, 0xc9, 0x98, 0x13, 0x09, + 0xc9, 0x98, 0x93, 0x84, 0x29, 0x00, 0xa6, 0x85, 0xef, 0x30, 0x60, 0x08, 0xa2, 0x94, 0x23, 0x80, + 0xa4, 0x00, 0x4e, 0x94, 0x21, 0x81, 0x93, 0x87, 0x49, 0x00, 0xa3, 0x01, 0xa4, 0x00, 0xfd, 0x56, + 0x13, 0xf7, 0x37, 0x00, 0x19, 0xef, 0x89, 0x83, 0x23, 0x22, 0xf9, 0x10, 0xef, 0x20, 0xb0, 0x45, + 0x13, 0x05, 0xa0, 0x0a, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, + 0x82, 0x80, 0x33, 0x07, 0xf9, 0x00, 0x23, 0x00, 0xd7, 0x00, 0x85, 0x07, 0xd1, 0xbf, 0xb7, 0x37, + 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, 0x83, 0xa7, 0x47, 0x10, 0x63, 0x14, + 0xf7, 0x00, 0x6f, 0x20, 0x30, 0x3e, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, + 0x23, 0xa0, 0x07, 0xf6, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x93, 0x07, 0x00, 0x08, 0x73, 0xa0, + 0x47, 0x30, 0x93, 0x06, 0x70, 0x3e, 0x09, 0x46, 0x93, 0x05, 0x60, 0x04, 0x37, 0x05, 0x10, 0x01, + 0xef, 0x20, 0x30, 0x52, 0x8d, 0x45, 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, 0x70, 0x52, 0x37, 0x05, + 0x10, 0x01, 0xef, 0x20, 0xf0, 0x4f, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x10, 0x50, 0xfd, 0x56, + 0x01, 0x46, 0x93, 0x05, 0x60, 0x04, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x90, 0x4f, 0xb2, 0x40, + 0xb7, 0x07, 0x20, 0x01, 0x23, 0xac, 0x07, 0x00, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, + 0x89, 0x2c, 0xb2, 0x40, 0x41, 0x01, 0x45, 0xb7, 0x41, 0x11, 0x22, 0xc4, 0xb7, 0x07, 0x20, 0x01, + 0x06, 0xc6, 0x23, 0xac, 0x07, 0x00, 0x2a, 0x84, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x50, 0x4b, + 0x93, 0x07, 0x80, 0x3e, 0x13, 0x05, 0x80, 0x3e, 0x63, 0xe3, 0x87, 0x00, 0x22, 0x85, 0xb7, 0x07, + 0x20, 0x01, 0x98, 0x4f, 0x13, 0x84, 0x87, 0x01, 0xe3, 0x6d, 0xa7, 0xfe, 0x37, 0x05, 0x20, 0x01, + 0xef, 0x20, 0xb0, 0x49, 0xb2, 0x40, 0x23, 0x20, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, + 0x11, 0xe1, 0x82, 0x80, 0x01, 0x00, 0x7d, 0x15, 0xe5, 0xbf, 0x6f, 0xf0, 0x9f, 0xb3, 0x39, 0xa4, + 0x01, 0x11, 0x26, 0xca, 0xaa, 0x84, 0x37, 0x05, 0x20, 0x01, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, + 0x56, 0xc2, 0x06, 0xce, 0x22, 0xcc, 0x2e, 0x89, 0x93, 0x09, 0xa0, 0x0a, 0xef, 0x20, 0x50, 0x45, + 0x37, 0x0a, 0x20, 0x01, 0x93, 0x0a, 0x80, 0x3e, 0x82, 0x94, 0x2a, 0x84, 0x63, 0x0c, 0x35, 0x03, + 0x83, 0x27, 0x8a, 0x01, 0x63, 0x7a, 0xf9, 0x04, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0xc4, 0x65, + 0x85, 0x45, 0xef, 0xf0, 0x9f, 0xb6, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0x05, + 0xc4, 0x65, 0xa6, 0x86, 0x13, 0x06, 0x06, 0x66, 0x13, 0x05, 0x45, 0x64, 0xef, 0xf0, 0x9f, 0xad, + 0x13, 0x04, 0x50, 0x05, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x30, 0x41, 0xf2, 0x40, 0x22, 0x85, + 0x62, 0x44, 0xb7, 0x07, 0x20, 0x01, 0x23, 0xac, 0x07, 0x00, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, + 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xe3, 0xf0, 0x2a, 0xfb, 0x41, 0x22, 0x69, 0xbf, + 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x87, 0x00, 0x1c, 0xc7, 0x82, 0x80, 0x41, 0x11, + 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, 0xc1, 0xa9, 0x44, + 0x03, 0x45, 0x04, 0x00, 0x11, 0xe5, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, + 0xef, 0xf0, 0xdf, 0xa1, 0x83, 0x47, 0x04, 0x00, 0x63, 0x94, 0x97, 0x00, 0xef, 0xf0, 0x7f, 0xa6, + 0x05, 0x04, 0xf9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0x25, 0x37, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x05, + 0xf5, 0x00, 0xef, 0xe0, 0xaf, 0xbd, 0x01, 0xa0, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, + 0x22, 0xc4, 0x37, 0x44, 0x20, 0x00, 0x13, 0x06, 0xc0, 0x1f, 0x81, 0x45, 0x13, 0x05, 0x04, 0xe0, + 0x06, 0xc6, 0x26, 0xc2, 0xef, 0x20, 0xb0, 0x6f, 0x13, 0x05, 0x04, 0xe0, 0x93, 0x05, 0xc0, 0x1f, + 0xef, 0x20, 0xb0, 0x67, 0x93, 0x04, 0x04, 0xe0, 0xb2, 0x40, 0x22, 0x44, 0x23, 0xae, 0xa4, 0x1e, + 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x37, 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, + 0xc0, 0x1f, 0x13, 0x04, 0x05, 0xe0, 0x13, 0x05, 0x05, 0xe0, 0x06, 0xc6, 0xef, 0x20, 0xf0, 0x64, + 0x03, 0x27, 0xc4, 0x1f, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xa7, 0x00, 0x93, 0x07, 0x50, 0x05, + 0xb2, 0x40, 0x22, 0x44, 0x3e, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, 0xaa, 0x87, + 0x63, 0x6e, 0xa7, 0x00, 0x13, 0x77, 0x35, 0x00, 0x01, 0x45, 0x11, 0xeb, 0x37, 0x45, 0x20, 0x00, + 0x13, 0x05, 0x05, 0xe0, 0xf1, 0x9b, 0xaa, 0x97, 0x88, 0x43, 0x82, 0x80, 0x01, 0x45, 0x82, 0x80, + 0x93, 0x07, 0xb0, 0x1f, 0x63, 0xec, 0xa7, 0x00, 0x93, 0x77, 0x35, 0x00, 0x81, 0xeb, 0xb7, 0x47, + 0x20, 0x00, 0x71, 0x99, 0x93, 0x87, 0x07, 0xe0, 0x3e, 0x95, 0x0c, 0xc1, 0x82, 0x80, 0x41, 0x11, + 0x37, 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, 0xc0, 0x1f, 0x13, 0x04, 0x05, 0xe0, 0x13, 0x05, + 0x05, 0xe0, 0x06, 0xc6, 0xef, 0x20, 0x70, 0x5d, 0xb2, 0x40, 0x23, 0x2e, 0xa4, 0x1e, 0x22, 0x44, + 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, 0x63, 0x61, 0xa7, 0x02, 0x93, 0x77, 0x35, 0x00, + 0x13, 0x07, 0x50, 0x05, 0x89, 0xef, 0x41, 0x11, 0x06, 0xc6, 0x5d, 0x37, 0xc9, 0x37, 0xb2, 0x40, + 0x13, 0x07, 0xa0, 0x0a, 0x3a, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0x50, 0x05, 0x3a, 0x85, + 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x00, 0x10, 0x71, 0xb2, 0x40, 0xb7, 0x07, 0x00, 0x02, + 0x0d, 0x47, 0xf8, 0xcb, 0x13, 0x05, 0xa0, 0x0a, 0x41, 0x01, 0x82, 0x80, 0x73, 0x00, 0x50, 0x10, + 0x82, 0x80, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x52, 0xcc, 0x06, 0xd6, + 0x2a, 0x84, 0xae, 0x84, 0x32, 0x89, 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x07, 0x39, 0x41, 0x33, 0x05, + 0x34, 0x01, 0x63, 0x6c, 0xfa, 0x02, 0x71, 0x56, 0x93, 0x57, 0x29, 0x00, 0xb3, 0x87, 0xc7, 0x02, + 0x93, 0x75, 0xc9, 0xff, 0x33, 0x05, 0xb4, 0x00, 0xae, 0x94, 0x33, 0x86, 0x27, 0x01, 0x11, 0xc6, + 0x9c, 0x40, 0x6c, 0x00, 0x3e, 0xc6, 0xef, 0x20, 0xd0, 0x56, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, + 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0xb3, 0x87, 0x34, 0x01, 0x9c, 0x43, + 0x11, 0x46, 0x6c, 0x00, 0x3e, 0xc6, 0x91, 0x09, 0xef, 0x20, 0xb0, 0x54, 0x7d, 0xb7, 0x79, 0x71, + 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x52, 0xcc, 0x06, 0xd6, 0x2a, 0x84, 0xae, 0x84, + 0x32, 0x89, 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x07, 0x39, 0x41, 0xb3, 0x85, 0x34, 0x01, 0x63, 0x6d, + 0xfa, 0x02, 0x71, 0x56, 0x93, 0x57, 0x29, 0x00, 0xb3, 0x87, 0xc7, 0x02, 0x93, 0x75, 0xc9, 0xff, + 0x2e, 0x94, 0xa6, 0x95, 0x33, 0x86, 0x27, 0x01, 0x01, 0xca, 0x1c, 0x40, 0x68, 0x00, 0x3e, 0xc6, + 0xef, 0x20, 0x30, 0x50, 0xb2, 0x47, 0x1c, 0xc0, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, + 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0x11, 0x46, 0x68, 0x00, 0xef, 0x20, 0x70, 0x4e, + 0x32, 0x47, 0xb3, 0x07, 0x34, 0x01, 0x91, 0x09, 0x98, 0xc3, 0x75, 0xb7, 0x41, 0x11, 0x22, 0xc4, + 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x6f, 0x9c, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, + 0x50, 0x05, 0x23, 0xa6, 0xe7, 0xf6, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa8, 0x87, 0xf6, 0x22, 0x44, + 0xb2, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x8a, 0x07, 0xa8, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xa4, + 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, 0x99, 0x37, 0x35, + 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0xa2, 0x85, 0x13, 0x06, 0xe0, 0x0f, 0x13, 0x05, 0x45, 0xa9, + 0x23, 0x8a, 0x07, 0xb8, 0xef, 0x20, 0xf0, 0x47, 0x22, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, + 0x6f, 0xf0, 0xbf, 0xb2, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x19, 0xe1, + 0xef, 0xe0, 0xcf, 0x95, 0xb7, 0x34, 0x20, 0x00, 0x83, 0xc7, 0x44, 0xb9, 0x99, 0xcb, 0x37, 0x35, + 0x20, 0x00, 0x13, 0x06, 0xe0, 0x0f, 0x93, 0x85, 0x44, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0xef, 0x20, + 0x50, 0x44, 0xa2, 0x85, 0x13, 0x85, 0x44, 0xb9, 0x13, 0x06, 0xe0, 0x0f, 0xef, 0x20, 0x70, 0x43, + 0x22, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x92, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0x1f, 0xae, 0xb7, 0x37, + 0x20, 0x00, 0x03, 0xa5, 0xc7, 0xf6, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, + 0x13, 0x04, 0xc4, 0xf6, 0x26, 0xc2, 0x04, 0x40, 0x06, 0xc6, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x89, + 0xf4, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, + 0x37, 0x35, 0x20, 0x00, 0x13, 0x05, 0x45, 0xb9, 0xef, 0xf0, 0x3f, 0xaa, 0xe3, 0x13, 0x95, 0xfe, + 0x93, 0x07, 0x50, 0x05, 0x1c, 0xc0, 0xc5, 0xb7, 0x37, 0x35, 0x20, 0x00, 0x83, 0x47, 0x45, 0xa9, + 0x85, 0xc3, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xc7, 0x47, 0xb9, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, + 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf6, 0x13, 0x05, 0x45, 0xa9, 0x6f, 0xf0, 0xff, 0xa6, + 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xdf, 0x99, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x04, 0xf5, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, + 0x6d, 0x71, 0x23, 0x26, 0x11, 0x10, 0x23, 0x24, 0x81, 0x10, 0x23, 0x22, 0x91, 0x10, 0xef, 0xf0, + 0xdf, 0x98, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x04, 0x2a, 0x84, 0xef, 0xf0, 0x5f, 0x9c, + 0x63, 0x1b, 0x85, 0x06, 0xef, 0xf0, 0xdf, 0xa1, 0x83, 0x46, 0x05, 0x00, 0x93, 0x07, 0x20, 0x0a, + 0x2a, 0x84, 0x63, 0x80, 0xf6, 0x02, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, + 0x10, 0x00, 0x13, 0x06, 0xc6, 0x66, 0x93, 0x85, 0xc5, 0x67, 0x13, 0x05, 0x45, 0x64, 0xef, 0xf0, + 0x6f, 0xeb, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xf7, 0x22, 0x85, 0x82, 0x97, 0xef, 0xf0, + 0xff, 0xaa, 0xef, 0xf0, 0xdf, 0xa8, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x14, 0xf5, 0x08, + 0xef, 0xf0, 0x7f, 0x91, 0x63, 0x10, 0x85, 0x08, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xf6, + 0x63, 0x94, 0xa7, 0x04, 0x03, 0x24, 0x81, 0x10, 0x83, 0x20, 0xc1, 0x10, 0x83, 0x24, 0x41, 0x10, + 0x51, 0x61, 0x6f, 0xf0, 0x7f, 0xee, 0xef, 0xf0, 0xbf, 0x97, 0x81, 0x44, 0x63, 0x14, 0x85, 0x00, + 0x93, 0x04, 0xc0, 0x07, 0xef, 0xf0, 0x5f, 0x98, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, + 0xdd, 0xd4, 0x0a, 0x85, 0x23, 0x00, 0x91, 0x00, 0xa3, 0x00, 0x01, 0x00, 0xef, 0xf0, 0x5f, 0xe3, + 0x79, 0xbf, 0x93, 0x04, 0xc0, 0x07, 0xf5, 0xb7, 0xb7, 0x35, 0x20, 0x00, 0x83, 0xc7, 0x45, 0xb9, + 0x95, 0xc3, 0x03, 0x24, 0x81, 0x10, 0x83, 0x20, 0xc1, 0x10, 0x83, 0x24, 0x41, 0x10, 0x37, 0x35, + 0x20, 0x00, 0x13, 0x06, 0xe0, 0x0f, 0x93, 0x85, 0x45, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0x51, 0x61, + 0x6f, 0x20, 0x30, 0x2a, 0x83, 0x20, 0xc1, 0x10, 0x03, 0x24, 0x81, 0x10, 0x83, 0x24, 0x41, 0x10, + 0x51, 0x61, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x23, 0xa2, 0x07, 0x00, 0x21, 0x65, 0x6f, 0x20, + 0xc0, 0x1c, 0x41, 0x11, 0x21, 0x65, 0x06, 0xc6, 0xef, 0x20, 0x60, 0x1b, 0xb2, 0x40, 0xb7, 0x07, + 0x01, 0x04, 0x05, 0x47, 0xd8, 0xc3, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, + 0x06, 0xc6, 0x93, 0x07, 0x70, 0x02, 0x2a, 0x84, 0xae, 0x84, 0x63, 0xf4, 0xa7, 0x00, 0xef, 0xd0, + 0xff, 0xf4, 0x37, 0x05, 0x01, 0x04, 0x0a, 0x04, 0x13, 0x05, 0x05, 0x10, 0x2a, 0x94, 0x04, 0xc0, + 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x13, 0x87, + 0x07, 0x10, 0x93, 0x87, 0x07, 0x1a, 0x23, 0x20, 0x07, 0x00, 0x11, 0x07, 0xe3, 0x1d, 0xf7, 0xfe, + 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0xc8, 0xcb, 0x82, 0x80, 0x42, 0x05, 0xb7, 0x07, 0x01, 0x04, + 0xc8, 0xcb, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x88, 0x4b, 0x13, 0x75, 0xf5, 0x0f, 0x82, 0x80, + 0x89, 0x67, 0x37, 0x07, 0x01, 0x04, 0x8d, 0x07, 0x1c, 0xc7, 0x23, 0x2a, 0x07, 0x00, 0x82, 0x80, + 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0x2a, 0x84, 0xad, 0x37, 0xb7, 0x07, 0x01, 0x04, 0x80, 0xcf, + 0xc5, 0x37, 0x65, 0x37, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0xa9, 0xb7, 0xb7, 0x06, 0x01, 0x04, + 0x9c, 0x46, 0x05, 0x45, 0x13, 0xf7, 0x17, 0x00, 0x1d, 0xc7, 0x13, 0xf7, 0x07, 0x40, 0x0d, 0x45, + 0x1d, 0xe3, 0x98, 0x4a, 0x13, 0x77, 0xf7, 0x0f, 0x19, 0xcf, 0x13, 0xf7, 0x27, 0x20, 0x09, 0x45, + 0x19, 0xeb, 0x13, 0xd7, 0xb7, 0x00, 0x05, 0x8b, 0x11, 0x45, 0x11, 0xe7, 0x13, 0xd5, 0x87, 0x00, + 0x13, 0x45, 0x15, 0x00, 0x05, 0x89, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x88, 0xcf, 0x82, 0x80, + 0x01, 0x11, 0x22, 0xcc, 0x06, 0xce, 0x33, 0x07, 0xb6, 0x00, 0x93, 0x07, 0x00, 0x09, 0x2e, 0x84, + 0x63, 0xf8, 0xe7, 0x00, 0x32, 0xc6, 0x2a, 0xc4, 0xef, 0xd0, 0x5f, 0xe7, 0x32, 0x46, 0x22, 0x45, + 0xb7, 0x15, 0x01, 0x04, 0xa2, 0x95, 0xef, 0xf0, 0xdf, 0xbb, 0xf2, 0x40, 0x62, 0x44, 0x13, 0x05, + 0xa0, 0x0a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, 0x26, 0xca, 0x06, 0xce, 0x33, 0x07, + 0xb6, 0x00, 0x93, 0x07, 0x00, 0x08, 0xaa, 0x84, 0x2e, 0x84, 0x63, 0xf6, 0xe7, 0x00, 0x32, 0xc6, + 0xef, 0xd0, 0xdf, 0xe3, 0x32, 0x46, 0x37, 0x25, 0x01, 0x04, 0x13, 0x05, 0x05, 0x80, 0x22, 0x95, + 0x62, 0x44, 0xf2, 0x40, 0xa6, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x6f, 0xf0, 0x5f, 0xbe, 0x39, 0x71, + 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, + 0x10, 0x00, 0x13, 0x06, 0x06, 0x68, 0x93, 0x85, 0x05, 0x69, 0x13, 0x05, 0x45, 0x69, 0x06, 0xde, + 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, + 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xf0, 0xcf, 0xc5, 0xef, 0xe0, 0xcf, 0xc8, + 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, + 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, + 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x09, 0x65, 0x6f, 0x10, 0x70, 0x7f, 0x09, 0x65, 0x6f, 0x10, + 0xd0, 0x7f, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xd0, 0x1f, 0xda, + 0xdd, 0x37, 0xb7, 0x07, 0x00, 0x07, 0x83, 0x46, 0x14, 0x00, 0xd8, 0x43, 0x83, 0x47, 0x04, 0x00, + 0xa2, 0x06, 0xdd, 0x8e, 0x83, 0x47, 0x24, 0x00, 0xc2, 0x07, 0xdd, 0x8e, 0x83, 0x47, 0x34, 0x00, + 0xe2, 0x07, 0xd5, 0x8f, 0x93, 0x06, 0xf0, 0x0f, 0x63, 0x85, 0xd7, 0x00, 0x61, 0x9b, 0x9d, 0x8b, + 0x5d, 0x8f, 0x93, 0x77, 0x77, 0xff, 0x03, 0x47, 0x44, 0x00, 0x83, 0x46, 0x94, 0x00, 0xb2, 0x40, + 0x0e, 0x07, 0x21, 0x8b, 0x5d, 0x8f, 0xfd, 0x77, 0xbd, 0x07, 0x7d, 0x8f, 0x83, 0x47, 0x54, 0x00, + 0x92, 0x07, 0x5d, 0x8f, 0xb7, 0x17, 0x80, 0xff, 0xfd, 0x17, 0x7d, 0x8f, 0x83, 0x47, 0xa4, 0x00, + 0xa2, 0x07, 0xd5, 0x8f, 0xb2, 0x07, 0xb7, 0xf6, 0x7f, 0x00, 0xf5, 0x8f, 0xd9, 0x8f, 0x37, 0x07, + 0x80, 0xf8, 0x7d, 0x17, 0xf9, 0x8f, 0x03, 0x47, 0x74, 0x00, 0xb7, 0x06, 0x80, 0x07, 0x5e, 0x07, + 0x75, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x00, 0x88, 0x7d, 0x17, 0xf9, 0x8f, 0x03, 0x47, 0x64, 0x00, + 0xb7, 0x06, 0x00, 0x78, 0x22, 0x44, 0x6e, 0x07, 0x75, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x00, 0x07, + 0x5c, 0xc3, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x87, 0xf7, 0x82, 0x80, + 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, + 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x13, 0x05, + 0xa0, 0x0a, 0x89, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x89, 0x65, 0x37, 0x35, + 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x65, 0xba, 0x6f, 0xf0, 0xbf, 0x8c, 0x41, 0x11, + 0xb7, 0x07, 0x08, 0x05, 0x22, 0xc4, 0x03, 0xa4, 0xc7, 0x20, 0x37, 0x07, 0x00, 0x04, 0x06, 0xc6, + 0x26, 0xc2, 0xb3, 0x76, 0xe4, 0x00, 0x91, 0xca, 0x37, 0x55, 0x10, 0x00, 0x23, 0xa6, 0xe7, 0x20, + 0xa5, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xf0, 0x4f, 0xb7, 0xb7, 0x07, 0x80, 0x6b, 0xe1, 0x8f, + 0x95, 0xcb, 0x37, 0x07, 0x08, 0x05, 0x23, 0x26, 0xf7, 0x20, 0xb7, 0x07, 0x00, 0x68, 0x7d, 0x8c, + 0x93, 0x04, 0x50, 0x05, 0x11, 0xc8, 0x37, 0x55, 0x10, 0x00, 0x9d, 0x45, 0x13, 0x05, 0x85, 0x69, + 0xef, 0xf0, 0xaf, 0xb4, 0xef, 0xd0, 0x9f, 0xc5, 0xb2, 0x40, 0x22, 0x44, 0x26, 0x85, 0x92, 0x44, + 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0xf7, 0x84, 0x43, 0x13, 0x07, + 0xa0, 0x0a, 0x63, 0x96, 0xe4, 0x00, 0x13, 0x07, 0x50, 0x05, 0x98, 0xc3, 0xe1, 0xbf, 0x93, 0x04, + 0xa0, 0x0a, 0xd9, 0xbf, 0x81, 0x47, 0xb7, 0x05, 0x08, 0x05, 0x13, 0x07, 0x00, 0x20, 0xb3, 0x86, + 0xb7, 0x00, 0x90, 0x42, 0xb3, 0x06, 0xf5, 0x00, 0x91, 0x07, 0x90, 0xc2, 0xe3, 0x99, 0xe7, 0xfe, + 0x6f, 0xf0, 0xff, 0xf5, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0x2a, 0x84, 0xef, 0xf0, 0x1f, 0xf4, + 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf6, 0x8d, 0x47, 0x33, 0x95, + 0x87, 0x00, 0xb7, 0xb7, 0xaa, 0x02, 0x93, 0x87, 0xa7, 0xaa, 0x3d, 0x8d, 0xb7, 0x07, 0x08, 0x05, + 0x23, 0xa4, 0xa7, 0x20, 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, + 0x65, 0xb8, 0xef, 0xf0, 0x2f, 0xfe, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0xf1, + 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x9f, 0xef, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf7, + 0x37, 0x07, 0x08, 0x05, 0x13, 0x05, 0x00, 0x20, 0xf9, 0x9b, 0x23, 0x22, 0xf7, 0x20, 0xef, 0x10, + 0xd0, 0x5e, 0xb2, 0x40, 0x39, 0x45, 0x41, 0x01, 0x6f, 0x10, 0xf0, 0x5f, 0x37, 0x37, 0x20, 0x00, + 0x13, 0x07, 0x47, 0xf7, 0x1c, 0x43, 0x93, 0xf7, 0xf7, 0xfd, 0x1c, 0xc3, 0x37, 0x07, 0x08, 0x05, + 0x23, 0x22, 0xf7, 0x20, 0x82, 0x80, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf7, 0x1c, 0x43, + 0x93, 0xe7, 0x07, 0x02, 0x1c, 0xc3, 0x37, 0x07, 0x08, 0x05, 0x23, 0x22, 0xf7, 0x20, 0x82, 0x80, + 0x33, 0x87, 0xc5, 0x00, 0xb7, 0x07, 0x08, 0x00, 0x63, 0x7c, 0xf7, 0x06, 0x01, 0x11, 0x22, 0xcc, + 0x26, 0xca, 0x4e, 0xc6, 0x06, 0xce, 0x4a, 0xc8, 0x93, 0xf4, 0x35, 0x00, 0xaa, 0x89, 0x2e, 0x84, + 0x13, 0x05, 0x50, 0x05, 0x9d, 0xec, 0x32, 0x89, 0xef, 0xf0, 0x5f, 0xe7, 0xb7, 0x37, 0x20, 0x00, + 0x03, 0xa7, 0x47, 0xf7, 0xb7, 0x06, 0x08, 0x05, 0xb7, 0x05, 0x00, 0x05, 0x13, 0x67, 0x27, 0x00, + 0x23, 0xa2, 0xe6, 0x20, 0x93, 0x87, 0x47, 0xf7, 0x0d, 0x47, 0x2e, 0x94, 0xb3, 0x06, 0x99, 0x40, + 0x63, 0x60, 0xd7, 0x02, 0x98, 0x43, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x05, 0xa0, 0x0a, 0x23, 0xa2, + 0xe7, 0x20, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, + 0xb3, 0x06, 0x94, 0x00, 0x90, 0x42, 0xb3, 0x86, 0x99, 0x00, 0x91, 0x04, 0x90, 0xc2, 0xf9, 0xb7, + 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, 0xaa, 0x85, 0x11, 0x46, 0x68, 0x00, 0x06, 0xce, + 0xef, 0xf0, 0x1f, 0xf7, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x00, 0x32, 0x45, 0xf2, 0x40, + 0x05, 0x61, 0x82, 0x80, 0x01, 0x45, 0xe5, 0xbf, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xef, 0xa7, 0x02, + 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x8d, 0xe3, + 0xae, 0x84, 0xef, 0xf0, 0xbf, 0xdd, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x22, 0x44, + 0xb2, 0x40, 0x23, 0xaa, 0x97, 0x20, 0x92, 0x44, 0x01, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x9f, 0xe7, + 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, + 0x26, 0xc2, 0x06, 0xc6, 0xaa, 0x84, 0x2e, 0x84, 0x45, 0x3f, 0x26, 0x85, 0xef, 0xf0, 0xbf, 0xf8, + 0x63, 0x09, 0x85, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, + 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xcd, 0xbf, 0x01, 0x11, 0x22, 0xcc, 0x2e, 0xc6, 0x06, 0xce, + 0x2a, 0x84, 0xef, 0xf0, 0x5f, 0xf6, 0xb2, 0x45, 0x63, 0x03, 0xb5, 0x02, 0xfd, 0x57, 0x63, 0x1a, + 0xf5, 0x00, 0x63, 0x8e, 0xa5, 0x00, 0x22, 0x85, 0x62, 0x44, 0xf2, 0x40, 0x05, 0x61, 0x6f, 0xf0, + 0xff, 0xfa, 0x13, 0x05, 0x50, 0x05, 0xf2, 0x40, 0x62, 0x44, 0x05, 0x61, 0x82, 0x80, 0x13, 0x05, + 0xa0, 0x0a, 0xd5, 0xbf, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe0, 0xb7, 0x04, 0x41, 0x11, 0x22, 0xc4, + 0x26, 0xc2, 0x06, 0xc6, 0x93, 0xf7, 0xf5, 0x1f, 0xaa, 0x84, 0x2e, 0x84, 0x13, 0x05, 0x50, 0x05, + 0x99, 0xef, 0xef, 0xf0, 0xbf, 0xd2, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x39, 0x45, + 0xef, 0xf0, 0x5f, 0xdd, 0x26, 0x85, 0xef, 0xf0, 0xff, 0xda, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, + 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, + 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xfb, + 0xb7, 0x00, 0x81, 0x44, 0xf2, 0x40, 0x62, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x26, 0x85, 0xd2, 0x44, + 0x05, 0x61, 0x82, 0x80, 0x93, 0xf4, 0xf5, 0x1f, 0x2e, 0x84, 0xe5, 0xf4, 0x2a, 0x89, 0xef, 0xf0, + 0xff, 0xcc, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x41, 0x45, 0xef, 0xf0, 0x9f, 0xd7, + 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x17, 0xf5, 0xfc, 0x37, 0x34, 0x20, 0x00, 0x13, 0x05, 0x44, 0xc9, + 0xef, 0xf0, 0x5f, 0xd4, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x87, 0x07, 0x20, 0x23, 0xa0, 0x07, 0x00, + 0x91, 0x07, 0xe3, 0x9d, 0xe7, 0xfe, 0x93, 0x09, 0x44, 0xc9, 0x03, 0xd6, 0xc9, 0x1f, 0x93, 0x07, + 0xc0, 0x1d, 0x63, 0xfa, 0xc7, 0x00, 0x37, 0x55, 0x10, 0x00, 0x99, 0x45, 0x13, 0x05, 0x85, 0x69, + 0xef, 0xf0, 0xaf, 0x82, 0x41, 0xbf, 0x93, 0x05, 0x44, 0xc9, 0x4a, 0x85, 0xef, 0x20, 0x60, 0x43, + 0x83, 0xd4, 0xc9, 0x1f, 0x41, 0xb7, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe7, 0xa7, 0x04, 0x41, 0x11, + 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x13, 0x05, 0x50, 0x05, + 0x9d, 0xe7, 0xef, 0xf0, 0xbf, 0xc4, 0x85, 0x67, 0xb7, 0x04, 0x08, 0x05, 0x93, 0x87, 0x97, 0x82, + 0x23, 0xa2, 0xf4, 0x20, 0x23, 0xac, 0x84, 0x20, 0x39, 0x45, 0xef, 0xf0, 0xbf, 0xce, 0xb7, 0x37, + 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf7, 0x13, 0x05, 0xa0, 0x0a, 0x23, 0xa2, 0xf4, 0x20, 0xb2, 0x40, + 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x0d, 0x65, + 0x01, 0x11, 0x13, 0x05, 0x05, 0x20, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, + 0xef, 0x10, 0xf0, 0x2f, 0x39, 0x45, 0xef, 0x10, 0x50, 0x31, 0x13, 0x05, 0x80, 0x07, 0x37, 0x39, + 0x20, 0x00, 0xef, 0xf0, 0x6f, 0xb9, 0x93, 0x09, 0x49, 0xf7, 0x83, 0xa7, 0x09, 0x00, 0x37, 0x04, + 0x08, 0x05, 0x93, 0x04, 0x04, 0x20, 0xdc, 0xc0, 0xb7, 0x07, 0x46, 0x00, 0x85, 0x07, 0xdc, 0xcc, + 0x85, 0x67, 0x93, 0x87, 0x57, 0x86, 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, 0xdc, 0xc0, 0x93, 0x85, + 0x05, 0x71, 0x13, 0x05, 0x05, 0xb9, 0xef, 0xf0, 0xef, 0xc8, 0xb7, 0x07, 0x40, 0x08, 0x9c, 0xc8, + 0xdc, 0x40, 0x01, 0x45, 0x13, 0x09, 0x49, 0xf7, 0x93, 0xe7, 0x07, 0x18, 0x23, 0xa0, 0xf9, 0x00, + 0xef, 0xf0, 0x7f, 0xf3, 0x93, 0x07, 0x04, 0x10, 0x98, 0x43, 0xb7, 0x67, 0xa5, 0xf0, 0x93, 0x87, + 0xf7, 0xa0, 0x63, 0x05, 0xf7, 0x02, 0x37, 0x55, 0x10, 0x00, 0x95, 0x45, 0x13, 0x05, 0x85, 0x69, + 0xef, 0xe0, 0xbf, 0xf2, 0x41, 0x67, 0x7d, 0x17, 0x93, 0x07, 0x04, 0x18, 0xb8, 0xd3, 0xf8, 0xd3, + 0xb8, 0xd7, 0xf8, 0xd7, 0xb8, 0xdb, 0xf8, 0xdb, 0xb8, 0xdf, 0xf8, 0xdf, 0x51, 0x45, 0xef, 0xf0, + 0x7f, 0xc1, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x91, 0x8b, 0x91, 0xeb, 0x37, 0x55, + 0x10, 0x00, 0x91, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, 0x3f, 0xef, 0xef, 0xd0, 0x1f, 0x80, + 0xb7, 0x07, 0x08, 0x05, 0x37, 0x07, 0x40, 0x00, 0x23, 0xa6, 0xe7, 0x20, 0x03, 0x27, 0x09, 0x00, + 0xf2, 0x40, 0x62, 0x44, 0x23, 0xa2, 0xe7, 0x20, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, + 0x82, 0x80, 0x85, 0x67, 0x37, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0x86, 0x23, 0x2a, 0xf7, 0xf6, + 0x37, 0x37, 0x20, 0x00, 0x93, 0x07, 0x50, 0x05, 0x23, 0x2c, 0xf7, 0xf6, 0x37, 0x37, 0x20, 0x00, + 0x23, 0x2e, 0xf7, 0xf6, 0x6f, 0xf0, 0xbf, 0xee, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe0, 0xa7, 0x06, + 0x41, 0x11, 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x13, 0x05, + 0x50, 0x05, 0xa1, 0xe3, 0xae, 0x84, 0xef, 0xf0, 0x7f, 0xad, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, + 0x87, 0x20, 0x01, 0x47, 0x93, 0x06, 0x00, 0x20, 0xb3, 0x85, 0xe4, 0x00, 0x8c, 0x41, 0x33, 0x06, + 0xf7, 0x00, 0x11, 0x07, 0x0c, 0xc2, 0xe3, 0x19, 0xd7, 0xfe, 0x7d, 0x57, 0x93, 0x87, 0x07, 0x20, + 0xf8, 0xc3, 0xb8, 0xc7, 0xf8, 0xc7, 0xb8, 0xcb, 0x29, 0x45, 0xef, 0xf0, 0xbf, 0xb5, 0x13, 0x05, + 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, + 0x82, 0x80, 0xaa, 0x85, 0x37, 0x05, 0x08, 0x05, 0x41, 0x46, 0x13, 0x05, 0x05, 0x26, 0x6f, 0xf0, + 0x0f, 0xd0, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xef, 0xa7, 0x0a, 0x01, 0x11, 0x26, 0xca, 0x93, 0x77, + 0xf5, 0x1f, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x56, 0xc2, 0xaa, 0x84, + 0x13, 0x05, 0x50, 0x05, 0xd9, 0xe7, 0x93, 0x07, 0xc0, 0x1d, 0x32, 0x89, 0x63, 0xe3, 0xc7, 0x08, + 0xb6, 0x89, 0x37, 0x34, 0x20, 0x00, 0x2e, 0x8a, 0xef, 0xf0, 0x5f, 0xa4, 0x13, 0x06, 0x00, 0x20, + 0x81, 0x45, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x80, 0x23, 0x4a, 0x86, 0xd2, 0x85, 0x13, 0x05, + 0x44, 0xc9, 0xef, 0x20, 0x00, 0x1f, 0x4e, 0x85, 0xef, 0xf0, 0xbf, 0xf9, 0x93, 0x0a, 0x44, 0xc9, + 0xb7, 0x07, 0x08, 0x05, 0x23, 0x9e, 0x2a, 0x1f, 0x13, 0x07, 0x44, 0xc9, 0x93, 0x86, 0x07, 0x20, + 0x10, 0x43, 0x11, 0x07, 0x90, 0xc3, 0x91, 0x07, 0xe3, 0x9c, 0xd7, 0xfe, 0x13, 0x06, 0x00, 0x20, + 0x81, 0x45, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x80, 0x1f, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, + 0x97, 0x20, 0x31, 0x45, 0xef, 0xf0, 0x1f, 0xaa, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, + 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x69, 0x8d, 0x45, 0xef, 0xe0, 0x1f, 0xd8, 0x13, 0x05, + 0x50, 0x05, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, + 0x05, 0x61, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xeb, + 0xa7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0xf5, 0x1f, 0x2a, 0x84, 0x89, 0xef, + 0xef, 0xf0, 0xdf, 0x99, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x22, 0x44, 0xb2, 0x40, + 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x1f, 0xa4, 0xb2, 0x40, 0x22, 0x44, 0x13, 0x05, 0x50, 0x05, + 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, + 0x37, 0x04, 0x08, 0x05, 0x23, 0x2c, 0xa4, 0x20, 0xef, 0xf0, 0x5f, 0x96, 0xb7, 0x37, 0x20, 0x00, + 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf6, 0xb7, 0xb7, 0xaa, 0x02, 0x93, 0x87, 0x67, 0xaa, + 0xb2, 0x40, 0x23, 0x24, 0xf4, 0x20, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, + 0xef, 0xf0, 0xdf, 0x93, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf6, + 0xb2, 0x40, 0xb7, 0xb7, 0xa6, 0x02, 0x37, 0x07, 0x08, 0x05, 0x93, 0x87, 0xa7, 0xaa, 0x23, 0x24, + 0xf7, 0x20, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x3e, 0xcc, 0xb7, 0x07, 0x08, 0x05, 0x3a, 0xce, + 0x03, 0xa7, 0xc7, 0x20, 0x36, 0xd0, 0xb7, 0x06, 0x40, 0x00, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, + 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, + 0x7a, 0xc2, 0x7e, 0xc0, 0x75, 0x8f, 0x05, 0xcf, 0x23, 0xa6, 0xd7, 0x20, 0x13, 0x07, 0xa0, 0x0a, + 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0xe7, 0xf6, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, + 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, + 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x03, 0xa7, + 0xc7, 0x20, 0xb7, 0x06, 0x00, 0x08, 0x37, 0x55, 0x10, 0x00, 0x75, 0x8f, 0x0d, 0xc3, 0x23, 0xa6, + 0xd7, 0x20, 0x85, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, 0x3f, 0xc4, 0xb7, 0x37, 0x20, 0x00, + 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xae, 0xe7, 0xf6, 0xef, 0xd0, 0x1f, 0xbf, 0x75, 0xb7, 0x89, 0x45, + 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, 0x7f, 0xc2, 0xb7, 0x07, 0x02, 0x00, 0x73, 0xb0, 0x47, 0x30, + 0xe5, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa0, 0xe7, 0xf8, 0x82, 0x80, + 0x99, 0x47, 0x63, 0x05, 0xf5, 0x02, 0x9d, 0x47, 0x63, 0x0b, 0xf5, 0x00, 0x95, 0x47, 0x63, 0x15, + 0xf5, 0x02, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xf7, 0xf7, 0xf7, 0x29, 0xa8, 0xb7, 0x37, + 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa0, 0xe7, 0xf8, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, + 0x7c, 0x43, 0x93, 0xe7, 0x07, 0x08, 0x7c, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, + 0x07, 0xf8, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, 0xf7, 0x00, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, + 0x93, 0xe7, 0x07, 0x08, 0x7c, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf8, + 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, 0xf7, 0x00, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xf7, + 0xf7, 0xf7, 0x7c, 0xc3, 0x82, 0x80, 0x39, 0x71, 0x2a, 0xd6, 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, + 0x13, 0x05, 0xc5, 0x69, 0x85, 0x45, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, + 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, + 0x7e, 0xc0, 0xef, 0xe0, 0x9f, 0xb6, 0xef, 0xd0, 0x3f, 0xb2, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, + 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, + 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, + 0x39, 0x71, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, + 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, + 0x7e, 0xc0, 0xf3, 0x25, 0x20, 0x34, 0xc1, 0x67, 0x37, 0x55, 0x10, 0x00, 0xdd, 0x8d, 0x13, 0x05, + 0xc5, 0x69, 0xef, 0xe0, 0x9f, 0xb0, 0xef, 0xd0, 0x3f, 0xac, 0x01, 0xa0, 0x39, 0x71, 0x2a, 0xd6, + 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, 0x13, 0x05, 0xc5, 0x69, 0x89, 0x45, 0x06, 0xde, 0x16, 0xdc, + 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, + 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0x3f, 0xad, 0xef, 0xd0, 0xdf, 0xa8, + 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, + 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, + 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x07, 0x01, 0x01, 0xb7, 0x07, 0x00, 0x01, 0x13, 0x07, + 0x17, 0x10, 0x98, 0xd3, 0x37, 0x07, 0x03, 0x04, 0x09, 0x07, 0xd8, 0xd3, 0x13, 0x07, 0x50, 0x60, + 0x98, 0xd7, 0x37, 0x17, 0x09, 0x00, 0x13, 0x07, 0x77, 0x80, 0xd8, 0xd7, 0x37, 0x17, 0x0b, 0x0b, + 0x13, 0x07, 0xa7, 0xa0, 0x98, 0xdb, 0x37, 0x17, 0x0c, 0x00, 0x13, 0x07, 0xb7, 0xc0, 0xd8, 0xdb, + 0x37, 0x17, 0x0f, 0x00, 0x13, 0x07, 0xd7, 0xe0, 0x98, 0xdf, 0x05, 0x67, 0xd8, 0xdf, 0xb7, 0x17, + 0xff, 0x7f, 0x93, 0x87, 0x07, 0x80, 0x73, 0xa0, 0x47, 0x30, 0xa1, 0x47, 0x73, 0xa0, 0x07, 0x30, + 0x82, 0x80, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x40, 0x00, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, + 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x80, 0x00, 0x73, 0xb0, + 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, + 0x00, 0x04, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, + 0x3e, 0xc6, 0xb7, 0x07, 0x00, 0x20, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, + 0x20, 0x30, 0x05, 0x65, 0x6f, 0x10, 0xa0, 0x54, 0x05, 0x65, 0x6f, 0x10, 0x00, 0x55, 0x01, 0x11, + 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x06, 0xce, 0x26, 0xca, 0x52, 0xc4, 0x56, 0xc2, 0x9d, 0x47, + 0x2a, 0x84, 0xae, 0x89, 0x32, 0x89, 0x63, 0xd4, 0xc7, 0x00, 0xef, 0xd0, 0x2f, 0xae, 0xef, 0xf0, + 0x5f, 0xfd, 0xb7, 0x07, 0x01, 0x07, 0x18, 0x40, 0xdc, 0x43, 0x93, 0x06, 0xf0, 0x0f, 0x63, 0x05, + 0xd7, 0x00, 0xf1, 0x9b, 0x0d, 0x8b, 0xd9, 0x8f, 0x13, 0xf7, 0xb7, 0xff, 0x83, 0x47, 0x44, 0x00, + 0x81, 0x44, 0x31, 0x4a, 0x8a, 0x07, 0x91, 0x8b, 0xd9, 0x8f, 0x37, 0x07, 0x01, 0x07, 0x5c, 0xc3, + 0xb7, 0x1a, 0x01, 0x07, 0x63, 0xcf, 0x24, 0x03, 0x14, 0x40, 0x05, 0x47, 0xad, 0x47, 0x63, 0x9e, + 0xe6, 0x00, 0x83, 0x46, 0x44, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0xbd, 0x47, 0x63, 0x97, 0xe6, 0x00, + 0x14, 0x44, 0x37, 0x37, 0x20, 0x00, 0x23, 0x22, 0xd7, 0xf8, 0xf2, 0x40, 0x62, 0x44, 0x37, 0x07, + 0x01, 0x07, 0x5c, 0xc7, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, + 0x82, 0x80, 0xb3, 0x85, 0x44, 0x03, 0x13, 0x95, 0x44, 0x00, 0x31, 0x46, 0x56, 0x95, 0x85, 0x04, + 0xce, 0x95, 0xef, 0xf0, 0xcf, 0x81, 0x7d, 0xb7, 0x1d, 0x71, 0x3e, 0xda, 0xb7, 0x07, 0x01, 0x07, + 0xa2, 0xc6, 0x80, 0x47, 0x86, 0xce, 0x96, 0xcc, 0x9a, 0xca, 0x9e, 0xc8, 0xaa, 0xc4, 0xae, 0xc2, + 0xb2, 0xc0, 0x36, 0xde, 0x3a, 0xdc, 0x42, 0xd8, 0x46, 0xd6, 0x72, 0xd4, 0x76, 0xd2, 0x7a, 0xd0, + 0x7e, 0xce, 0x93, 0x77, 0xb4, 0x00, 0x95, 0xc7, 0xb7, 0x07, 0x00, 0x40, 0x73, 0xb0, 0x47, 0x30, + 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0xa2, 0x86, 0x13, 0x06, + 0x06, 0x6a, 0x93, 0x85, 0x85, 0x6a, 0x13, 0x05, 0x45, 0x64, 0xef, 0xe0, 0xbf, 0x87, 0xef, 0xd0, + 0xbf, 0x8a, 0x93, 0x77, 0x44, 0x00, 0x99, 0xcf, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf8, + 0x91, 0xcb, 0x6c, 0x00, 0x28, 0x00, 0x82, 0x97, 0x22, 0x47, 0xb7, 0x07, 0x01, 0x07, 0x98, 0xcb, + 0x32, 0x47, 0xd8, 0xcb, 0xb7, 0x07, 0x01, 0x07, 0x80, 0xc7, 0x36, 0x44, 0xf6, 0x40, 0xe6, 0x42, + 0x56, 0x43, 0xc6, 0x43, 0x26, 0x45, 0x96, 0x45, 0x06, 0x46, 0xf2, 0x56, 0x62, 0x57, 0xd2, 0x57, + 0x42, 0x58, 0xb2, 0x58, 0x22, 0x5e, 0x92, 0x5e, 0x02, 0x5f, 0xf2, 0x4f, 0x25, 0x61, 0x73, 0x00, + 0x20, 0x30, 0xb7, 0x07, 0x02, 0x04, 0xdc, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, + 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x13, 0x05, 0x00, 0x08, 0x6f, 0x10, 0x40, 0x3d, 0x13, 0x05, + 0x00, 0x08, 0x6f, 0x10, 0x80, 0x3d, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x07, + 0xd0, 0x79, 0x37, 0x04, 0x02, 0x04, 0x5c, 0xc4, 0x85, 0x44, 0x95, 0x65, 0x37, 0x35, 0x10, 0x00, + 0x04, 0xc4, 0x93, 0x85, 0x05, 0xe2, 0x13, 0x05, 0x25, 0x6d, 0xef, 0xe0, 0x7f, 0xca, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x13, 0xf5, 0x02, 0x54, 0x44, 0x63, 0x82, 0x96, 0x02, 0x37, 0x56, 0x10, 0x00, + 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x6a, 0x93, 0x85, 0x45, 0x6b, + 0x13, 0x05, 0x05, 0x62, 0xef, 0xe0, 0x0f, 0xfb, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, + 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xdf, 0xf8, 0xb2, 0x40, + 0xb7, 0x07, 0x02, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x05, 0x45, + 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xef, 0xe0, 0x3f, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, + 0xa0, 0x0a, 0x23, 0xa4, 0xe7, 0xf8, 0x89, 0x46, 0x37, 0x07, 0x02, 0x02, 0x54, 0xc7, 0x13, 0x84, + 0x87, 0xf8, 0x93, 0x04, 0x50, 0x05, 0xef, 0xe0, 0x9f, 0xc2, 0x1c, 0x40, 0xe3, 0x9d, 0x97, 0xfe, + 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x02, 0x02, 0xc8, 0xcb, + 0x05, 0x47, 0xd8, 0xc7, 0xd8, 0x53, 0x69, 0x8f, 0x63, 0x1e, 0xa7, 0x00, 0xd4, 0x57, 0x7d, 0x55, + 0xf9, 0x8e, 0x91, 0xea, 0x94, 0x57, 0x75, 0x8f, 0x19, 0xe7, 0x88, 0x47, 0x05, 0x89, 0x33, 0x05, + 0xa0, 0x40, 0x82, 0x80, 0x7d, 0x55, 0x82, 0x80, 0x41, 0x45, 0x6f, 0x10, 0x00, 0x2f, 0x41, 0x45, + 0x6f, 0x10, 0xe0, 0x2d, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, 0x2a, 0xc6, 0xef, 0xf0, 0x3f, 0xff, + 0x13, 0x07, 0x50, 0x05, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0xe7, 0xf8, 0x37, 0x04, 0x02, 0x02, + 0xa1, 0x47, 0x5c, 0xc4, 0x32, 0x45, 0x85, 0x47, 0x1c, 0xc8, 0x93, 0x07, 0x10, 0x40, 0x5c, 0xc0, + 0xef, 0xf0, 0xbf, 0xf9, 0xef, 0xf0, 0x9f, 0xf5, 0x23, 0x22, 0x04, 0x00, 0x62, 0x44, 0xf2, 0x40, + 0x05, 0x61, 0x6f, 0xf0, 0x7f, 0xfb, 0x41, 0x11, 0x3a, 0xc6, 0x37, 0x07, 0x02, 0x02, 0x3e, 0xc4, + 0x1c, 0x47, 0x1c, 0xc7, 0x85, 0x8b, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, + 0x23, 0xa4, 0xe7, 0xf8, 0x32, 0x47, 0xa2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x37, + 0x20, 0x00, 0x03, 0xa5, 0xc7, 0xf8, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, + 0x35, 0x00, 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xd0, 0x6f, 0x81, 0x89, 0x67, 0x63, 0x64, 0xf4, 0x00, + 0xef, 0xd0, 0xcf, 0x80, 0x37, 0x27, 0x00, 0x06, 0x85, 0x46, 0x09, 0x46, 0x1c, 0x47, 0x9d, 0x8b, + 0x63, 0x86, 0xd7, 0x00, 0x1c, 0x47, 0x9d, 0x8b, 0xe3, 0x9a, 0xc7, 0xfe, 0x37, 0x05, 0x00, 0x06, + 0x2a, 0x94, 0x08, 0x40, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x65, 0xb7, 0x37, + 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x41, 0x11, 0x13, 0x05, 0x05, 0x80, 0x23, 0xa6, 0xe7, 0xf8, + 0x06, 0xc6, 0xef, 0x10, 0xc0, 0x20, 0xb7, 0x27, 0x00, 0x06, 0x9c, 0x47, 0x05, 0x47, 0x9d, 0x8b, + 0xfd, 0x17, 0x63, 0x7b, 0xf7, 0x00, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0x85, 0x6b, + 0xef, 0xe0, 0xaf, 0xe9, 0xef, 0xc0, 0x9f, 0xfa, 0xb7, 0x07, 0x46, 0x00, 0xb2, 0x40, 0x37, 0x27, + 0x00, 0x06, 0x85, 0x07, 0x5c, 0xcf, 0x85, 0x47, 0x5c, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x37, 0x27, + 0x00, 0x06, 0x1c, 0x47, 0x85, 0x46, 0x9d, 0x8b, 0x63, 0x8a, 0xd7, 0x00, 0x14, 0xcb, 0xb7, 0x26, + 0x00, 0x06, 0x05, 0x47, 0x9c, 0x46, 0x9d, 0x8b, 0xe3, 0x9e, 0xe7, 0xfe, 0xb7, 0x27, 0x00, 0x06, + 0x09, 0x47, 0x05, 0x65, 0x98, 0xcb, 0x13, 0x05, 0x05, 0x80, 0x6f, 0x10, 0x00, 0x1b, 0x05, 0x65, + 0x41, 0x11, 0x13, 0x05, 0x05, 0x80, 0x06, 0xc6, 0xef, 0x10, 0x60, 0x19, 0xb2, 0x40, 0xb7, 0x27, + 0x00, 0x06, 0x21, 0x47, 0x98, 0xcb, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, + 0x26, 0xc2, 0xaa, 0x84, 0xef, 0xf0, 0x5f, 0xf1, 0x2a, 0x84, 0x49, 0x22, 0x13, 0x75, 0xf5, 0x0f, + 0xef, 0xe0, 0x1f, 0xa6, 0x26, 0x85, 0xef, 0xf0, 0x3f, 0xf0, 0x63, 0x05, 0xa4, 0x00, 0xef, 0xc0, + 0xff, 0xf1, 0x01, 0x45, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x79, 0x71, + 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x06, 0xd6, 0x52, 0xcc, 0xaa, 0x89, 0x2e, 0x89, + 0x93, 0x74, 0xc6, 0xff, 0x01, 0x44, 0x33, 0x8a, 0x89, 0x00, 0x33, 0x05, 0x89, 0x00, 0x63, 0x1a, + 0x94, 0x00, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, + 0x82, 0x80, 0xef, 0xf0, 0x9f, 0xf9, 0x2a, 0xc6, 0x11, 0x46, 0x6c, 0x00, 0x52, 0x85, 0xef, 0x10, + 0x50, 0x1d, 0x11, 0x04, 0xc9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x1f, 0xf8, 0x2a, 0x87, + 0x85, 0x46, 0x01, 0x45, 0x89, 0x45, 0x01, 0xe7, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x93, 0x77, + 0xf7, 0x00, 0x01, 0x46, 0x81, 0xef, 0x63, 0xd3, 0xc5, 0x00, 0xb6, 0x87, 0x5d, 0x8d, 0x86, 0x06, + 0x13, 0x75, 0xf5, 0x0f, 0x93, 0xf6, 0xf6, 0x0f, 0x11, 0x83, 0xf1, 0xbf, 0x13, 0xf8, 0x17, 0x00, + 0x85, 0x83, 0x42, 0x96, 0x93, 0xf7, 0xf7, 0x0f, 0xf1, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, + 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0xae, 0x84, 0x99, 0xc3, 0xef, 0xc0, 0x1f, 0xe7, + 0x89, 0x67, 0x63, 0x64, 0xf4, 0x00, 0xef, 0xc0, 0x7f, 0xe6, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, + 0x50, 0x05, 0x23, 0xa6, 0xe7, 0xf8, 0xb7, 0x27, 0x00, 0x06, 0x84, 0xcf, 0xc0, 0xcb, 0x22, 0x44, + 0xb2, 0x40, 0x92, 0x44, 0x11, 0x47, 0x98, 0xcb, 0x89, 0x65, 0x37, 0x45, 0x10, 0x00, 0x93, 0x85, + 0x05, 0x71, 0x13, 0x05, 0xe5, 0x84, 0x41, 0x01, 0x6f, 0xe0, 0xdf, 0xa4, 0x39, 0x71, 0x3a, 0xce, + 0x37, 0x27, 0x00, 0x06, 0x3e, 0xcc, 0x1c, 0x47, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, + 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, + 0x7a, 0xc2, 0x7e, 0xc0, 0xa1, 0x8b, 0x85, 0xcf, 0xa1, 0x47, 0x1c, 0xc7, 0xb7, 0x37, 0x20, 0x00, + 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf8, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, + 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, + 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x55, + 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x85, 0x6b, 0xef, 0xe0, 0x2f, 0xcb, 0xef, 0xd0, 0xcf, 0xc6, + 0xe1, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa8, 0xa7, 0xf8, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, + 0x93, 0x87, 0x07, 0xf9, 0x88, 0x43, 0x37, 0x67, 0x19, 0x00, 0x13, 0x07, 0xd7, 0x60, 0x33, 0x05, + 0xe5, 0x02, 0x37, 0xf7, 0x6e, 0x3c, 0x13, 0x07, 0xf7, 0x35, 0x3a, 0x95, 0x88, 0xc3, 0x82, 0x80, + 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf9, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0x87, 0xf9, + 0x9c, 0x4f, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0xc7, 0xf9, + 0x63, 0x84, 0xe7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xfd, 0x77, 0xfd, 0x17, 0xe9, 0x8f, + 0xb7, 0x26, 0x00, 0x08, 0x2e, 0x87, 0xb2, 0x85, 0x63, 0x94, 0xd7, 0x02, 0xb7, 0x37, 0x20, 0x00, + 0x23, 0xaa, 0xa7, 0xf8, 0xb7, 0x37, 0x20, 0x00, 0x37, 0x45, 0x10, 0x00, 0x23, 0xae, 0xe7, 0xf8, + 0x13, 0x05, 0x05, 0xaf, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0xe7, 0xf8, 0x6f, 0xe0, 0x5f, 0x87, + 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0xa7, 0xf8, 0xb7, 0x37, + 0x20, 0x00, 0x37, 0x45, 0x10, 0x00, 0x23, 0xae, 0x07, 0xf8, 0x13, 0x07, 0x00, 0x10, 0xb7, 0x37, + 0x20, 0x00, 0x93, 0x05, 0x80, 0x3e, 0x13, 0x05, 0x05, 0xaf, 0x23, 0xac, 0xe7, 0xf8, 0x6f, 0xe0, + 0x3f, 0x84, 0x37, 0x07, 0x01, 0x02, 0x5c, 0x43, 0xb7, 0x06, 0x05, 0x00, 0xd5, 0x8f, 0x5c, 0xc3, + 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0xb7, 0x27, 0x00, 0x08, 0x37, 0x05, + 0x08, 0x00, 0x63, 0x14, 0xf4, 0x00, 0x37, 0x05, 0x04, 0x00, 0xef, 0x00, 0x50, 0x71, 0x5c, 0x5c, + 0x22, 0x85, 0xb2, 0x40, 0x93, 0xe7, 0x37, 0x00, 0x5c, 0xdc, 0x23, 0x2c, 0x04, 0x00, 0x22, 0x44, + 0x41, 0x01, 0x6f, 0xf0, 0x5f, 0xf9, 0x58, 0x5d, 0xaa, 0x87, 0x75, 0x9b, 0x58, 0xdd, 0x37, 0x27, + 0x00, 0x08, 0x37, 0x05, 0x04, 0x00, 0x63, 0x84, 0xe7, 0x00, 0x37, 0x05, 0x08, 0x00, 0x6f, 0x00, + 0xd0, 0x6e, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x06, 0xd6, 0x4e, 0xce, 0x52, 0xcc, + 0x56, 0xca, 0x2a, 0x89, 0xae, 0x84, 0x32, 0x84, 0x99, 0xe1, 0xef, 0xc0, 0x3f, 0xc8, 0x13, 0x0a, + 0xa0, 0x0a, 0x91, 0x4a, 0x05, 0xe4, 0x83, 0x27, 0x89, 0x01, 0x37, 0x07, 0x11, 0x00, 0x13, 0x05, + 0xa0, 0x0a, 0xf9, 0x8f, 0x99, 0xc3, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, + 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0xd2, 0x4a, 0x45, 0x61, 0x82, 0x80, 0x13, 0x06, 0x80, 0x3e, + 0x85, 0x45, 0x4a, 0x85, 0xef, 0xf0, 0x7f, 0xee, 0xe3, 0x1f, 0x45, 0xfd, 0x83, 0x27, 0x49, 0x02, + 0xa2, 0x89, 0x3e, 0xc6, 0x63, 0xf3, 0x8a, 0x00, 0x91, 0x49, 0x26, 0x85, 0x4e, 0x86, 0x6c, 0x00, + 0xef, 0x10, 0x20, 0x73, 0xce, 0x94, 0x33, 0x04, 0x34, 0x41, 0x6d, 0xb7, 0x41, 0x11, 0x37, 0x05, + 0x02, 0x00, 0x06, 0xc6, 0xef, 0x00, 0xb0, 0x65, 0xb2, 0x40, 0xb7, 0x17, 0x00, 0x08, 0x37, 0x07, + 0x07, 0x00, 0x98, 0xd3, 0x13, 0x05, 0x40, 0x1f, 0x41, 0x01, 0x6f, 0xe0, 0xef, 0xee, 0xb7, 0x17, + 0x00, 0x08, 0x23, 0xa0, 0x07, 0x02, 0x37, 0x05, 0x02, 0x00, 0x6f, 0x00, 0x10, 0x64, 0x39, 0x71, + 0x3e, 0xcc, 0xb7, 0x17, 0x00, 0x08, 0x3a, 0xce, 0x98, 0x57, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, + 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, + 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0x05, 0x8b, 0x05, 0xcb, 0x98, 0x57, 0x13, 0x67, 0x17, 0x00, + 0x98, 0xd7, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, + 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, + 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x98, 0x57, 0x09, 0x8b, 0x09, 0xc7, 0x98, 0x57, + 0x13, 0x67, 0x27, 0x00, 0xf1, 0xb7, 0x98, 0x57, 0x11, 0x8b, 0x09, 0xc7, 0x98, 0x57, 0x13, 0x67, + 0x47, 0x00, 0x7d, 0xbf, 0xb7, 0x07, 0x00, 0x01, 0x73, 0xb0, 0x47, 0x30, 0xef, 0xd0, 0xcf, 0xa1, + 0x4d, 0xbf, 0x37, 0x07, 0x00, 0x02, 0x5c, 0x4f, 0xb7, 0x36, 0x20, 0x00, 0x13, 0xf6, 0x77, 0x00, + 0xe1, 0x9b, 0x23, 0xa0, 0xc6, 0xfa, 0x93, 0xe7, 0x47, 0x00, 0x5c, 0xcf, 0x1c, 0x4f, 0xf9, 0x9b, + 0x1c, 0xcf, 0x82, 0x80, 0x41, 0x11, 0x26, 0xc2, 0xb7, 0x04, 0x00, 0x02, 0x22, 0xc4, 0xc0, 0x4c, + 0x9c, 0x4c, 0x06, 0xc6, 0x13, 0x05, 0x80, 0x07, 0x93, 0xe7, 0x17, 0x00, 0x9c, 0xcc, 0xef, 0xe0, + 0xaf, 0xe1, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xfa, 0x61, 0x98, 0xb2, 0x40, 0x5d, 0x8c, + 0xc0, 0xcc, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x17, 0x05, 0x01, 0x93, 0x17, + 0x85, 0x01, 0xba, 0x97, 0x13, 0x17, 0x85, 0x00, 0xba, 0x97, 0x3e, 0x95, 0xb7, 0x07, 0x00, 0x04, + 0x88, 0xd3, 0xc8, 0xd3, 0x88, 0xd7, 0xc8, 0xd7, 0x88, 0xdb, 0xc8, 0xdb, 0x88, 0xdf, 0xc8, 0xdf, + 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x00, 0x08, 0x98, 0xd3, 0x23, 0xa2, 0x07, 0x02, + 0x0e, 0x05, 0x23, 0xa4, 0x07, 0x02, 0x42, 0x05, 0x23, 0xa6, 0x07, 0x02, 0x41, 0x81, 0x23, 0xa8, + 0x07, 0x02, 0x13, 0x17, 0x85, 0x00, 0xb7, 0x06, 0xff, 0x00, 0x23, 0xaa, 0x07, 0x02, 0x75, 0x8f, + 0x62, 0x05, 0x23, 0xac, 0x07, 0x02, 0x3a, 0x95, 0xc8, 0xdf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, + 0x13, 0x07, 0x00, 0x08, 0x98, 0xd3, 0x23, 0xa2, 0x07, 0x02, 0x23, 0xa4, 0x07, 0x02, 0x23, 0xa6, + 0x07, 0x02, 0x23, 0xa8, 0x07, 0x02, 0x23, 0xaa, 0x07, 0x02, 0x23, 0xac, 0x07, 0x02, 0x23, 0xae, + 0x07, 0x02, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x47, 0xea, 0x82, 0x80, 0xaa, 0x85, + 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0x6f, 0xe0, 0x3f, 0x83, + 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa2, 0xe7, 0xea, 0xb7, 0x07, 0x00, 0x04, + 0xc8, 0xc3, 0x13, 0x07, 0x90, 0x02, 0x85, 0x65, 0x37, 0x45, 0x10, 0x00, 0x98, 0xc7, 0x93, 0x85, + 0x85, 0x38, 0x13, 0x05, 0x45, 0xdf, 0x6f, 0xe0, 0xaf, 0xd8, 0x41, 0x11, 0x22, 0xc4, 0x01, 0x45, + 0x37, 0x34, 0x20, 0x00, 0x06, 0xc6, 0x13, 0x04, 0x44, 0xe9, 0xef, 0xf0, 0x1f, 0xf2, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0xfb, 0x48, 0x44, 0xb7, 0x07, 0x02, 0x00, + 0x95, 0x07, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0xbf, 0xfa, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x05, 0xef, 0xf0, 0xff, 0xf9, 0x48, 0x44, 0xb7, 0x07, 0x00, 0x10, 0x99, 0x07, 0x7e, 0x05, + 0x5d, 0x8d, 0xef, 0xf0, 0xff, 0xf8, 0x48, 0x44, 0xb7, 0x07, 0x01, 0x10, 0x99, 0x07, 0x7e, 0x05, + 0x5d, 0x8d, 0xef, 0xf0, 0xff, 0xf7, 0x22, 0x44, 0xb2, 0x40, 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, + 0x3f, 0xf7, 0x7d, 0x47, 0x63, 0x7e, 0xb7, 0x04, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, + 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0x6f, 0xe0, 0x8f, 0xf8, 0xb3, 0x06, 0xf5, 0x00, 0x83, 0xc6, + 0x06, 0x00, 0x33, 0x07, 0xf1, 0x00, 0x85, 0x07, 0x23, 0x00, 0xd7, 0x00, 0xe3, 0x97, 0xf5, 0xfe, + 0x18, 0x10, 0x93, 0x87, 0x15, 0x00, 0xba, 0x95, 0x13, 0x07, 0x00, 0xf8, 0x23, 0x80, 0xe5, 0xfe, + 0x13, 0x07, 0x00, 0x02, 0x63, 0x92, 0xe7, 0x02, 0x37, 0x05, 0x00, 0x04, 0x8a, 0x85, 0x13, 0x06, + 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0xef, 0xe0, 0x8f, 0xf4, 0xb2, 0x50, 0x45, 0x61, 0x82, 0x80, + 0x79, 0x71, 0x06, 0xd6, 0x81, 0x47, 0xd9, 0xb7, 0xb3, 0x06, 0xf1, 0x00, 0x23, 0x80, 0x06, 0x00, + 0x85, 0x07, 0xc9, 0xbf, 0x37, 0x55, 0x10, 0x00, 0x01, 0x11, 0x13, 0x05, 0x45, 0x6c, 0x06, 0xce, + 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x37, 0x34, 0x20, 0x00, 0xef, 0xf0, + 0x1f, 0xed, 0x93, 0x07, 0x44, 0xe9, 0xc8, 0x47, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, + 0x3f, 0xed, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x10, 0xf5, 0x2e, 0xaa, 0x84, 0x13, 0x05, 0x00, 0x02, + 0xef, 0xf0, 0x3f, 0xe4, 0x13, 0x04, 0x44, 0xe9, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, + 0xef, 0xf0, 0x1f, 0xeb, 0xaa, 0x89, 0x63, 0x10, 0x95, 0x2c, 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, + 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0xbf, 0xe9, 0xaa, 0x84, 0x63, 0x15, 0x35, 0x2b, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x9f, 0xe8, 0xaa, 0x89, 0x63, 0x1c, + 0x95, 0x28, 0x1c, 0x40, 0x48, 0x44, 0x37, 0x0a, 0x00, 0x04, 0x83, 0xc7, 0x07, 0x00, 0x7e, 0x05, + 0x13, 0x65, 0x15, 0x00, 0x93, 0xe7, 0x07, 0x20, 0x23, 0x2c, 0xfa, 0x00, 0xef, 0xf0, 0x5f, 0xe6, + 0xaa, 0x84, 0x63, 0x1a, 0x35, 0x27, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, + 0x3f, 0xe5, 0x2a, 0x89, 0x63, 0x11, 0x95, 0x26, 0xef, 0xf0, 0x5f, 0xe0, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xdf, 0xe3, 0xaa, 0x84, 0x63, 0x16, 0x25, 0x25, 0x13, 0x05, + 0x00, 0x04, 0xef, 0xf0, 0x1f, 0xdb, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x17, 0xef, 0xf0, 0xff, 0xe1, 0x2a, 0x89, 0x63, 0x17, 0x95, 0x22, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xdf, 0xe0, 0xaa, 0x84, 0x63, 0x1e, 0x25, 0x21, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xbf, 0xdf, 0x63, 0x16, 0x95, 0x20, 0x48, 0x44, + 0x93, 0x07, 0x00, 0x10, 0x23, 0x2c, 0xfa, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x15, 0x00, 0xef, 0xf0, + 0x3f, 0xde, 0x93, 0x07, 0xa0, 0x0a, 0xaa, 0x84, 0x63, 0x17, 0xf5, 0x1e, 0x48, 0x44, 0x09, 0x69, + 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x9f, 0xdc, 0xaa, 0x89, 0x63, 0x1c, + 0x95, 0x1c, 0xef, 0xf0, 0xbf, 0xd7, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, + 0x3f, 0xdb, 0xaa, 0x84, 0x63, 0x11, 0x35, 0x1d, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x7f, 0xd2, + 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x5f, 0xd9, + 0xaa, 0x89, 0x63, 0x12, 0x95, 0x1a, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, + 0x3f, 0xd8, 0xaa, 0x84, 0x63, 0x19, 0x35, 0x19, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, + 0xef, 0xf0, 0x1f, 0xd7, 0xaa, 0x89, 0x63, 0x10, 0x95, 0x18, 0x08, 0x40, 0x05, 0x05, 0xef, 0xf0, + 0x1f, 0xd5, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x7f, 0xd5, 0xaa, 0x84, + 0x63, 0x13, 0x35, 0x17, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x5f, 0xd4, + 0x2a, 0x89, 0x63, 0x1a, 0x95, 0x14, 0xef, 0xf0, 0x7f, 0xcf, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x07, 0xef, 0xf0, 0xff, 0xd2, 0xaa, 0x84, 0x63, 0x1f, 0x25, 0x13, 0x13, 0x05, 0x00, 0x04, + 0xef, 0xf0, 0x3f, 0xca, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, + 0xef, 0xf0, 0x1f, 0xd1, 0x63, 0x11, 0x95, 0x12, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, + 0xef, 0xf0, 0x1f, 0xd0, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0x63, 0x16, 0xf5, 0x10, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xbf, 0xce, 0xaa, 0x84, 0x63, 0x1d, 0x25, 0x0f, + 0x13, 0x05, 0x10, 0x02, 0xef, 0xf0, 0xff, 0xc5, 0x1c, 0x40, 0x48, 0x44, 0x21, 0x67, 0x83, 0xc7, + 0x07, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xd9, 0x8f, 0x23, 0x20, 0xfa, 0x02, 0xef, 0xf0, + 0x3f, 0xcc, 0xaa, 0x89, 0x63, 0x19, 0x95, 0x0c, 0x48, 0x44, 0x89, 0x64, 0x8d, 0x04, 0x7e, 0x05, + 0x45, 0x8d, 0xef, 0xf0, 0xff, 0xca, 0x2a, 0x89, 0x63, 0x1f, 0x35, 0x0b, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xdf, 0xc9, 0xaa, 0x89, 0x63, 0x16, 0x25, 0x0b, 0x08, 0x40, + 0x13, 0x05, 0x15, 0x02, 0xef, 0xf0, 0xbf, 0xc7, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, + 0xef, 0xf0, 0x1f, 0xc8, 0x2a, 0x89, 0x63, 0x18, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, 0x45, 0x8d, + 0xef, 0xf0, 0x1f, 0xc7, 0xaa, 0x84, 0x63, 0x10, 0x25, 0x09, 0xef, 0xf0, 0x3f, 0xc2, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0xc5, 0x2a, 0x89, 0x63, 0x15, 0x95, 0x06, + 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0xff, 0xbc, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xc3, 0xaa, 0x84, 0x63, 0x16, 0x25, 0x05, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xbf, 0xc2, 0x63, 0x1e, 0x95, 0x02, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x52, 0xef, 0xf0, 0xbf, 0xc1, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x14, + 0xf5, 0x02, 0x08, 0x40, 0x62, 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, + 0xb7, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x06, 0x13, 0x05, 0x15, 0x06, + 0x05, 0x61, 0x6f, 0xe0, 0x0f, 0xbb, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, + 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x4e, 0xc6, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, + 0x4a, 0xc8, 0x52, 0xc4, 0x93, 0x09, 0x00, 0x04, 0x63, 0xeb, 0xb9, 0x08, 0x37, 0x3a, 0x20, 0x00, + 0xaa, 0x84, 0x2e, 0x84, 0x13, 0x09, 0x4a, 0xe9, 0xef, 0xf0, 0xbf, 0xc4, 0x03, 0x25, 0xc9, 0x00, + 0x13, 0x0a, 0x4a, 0xe9, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x7f, 0xba, 0x13, 0x85, + 0x04, 0x02, 0x63, 0x19, 0x34, 0x03, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x05, 0x05, 0x02, + 0x13, 0x06, 0x00, 0x02, 0xef, 0xe0, 0xaf, 0xbb, 0x03, 0x25, 0xc9, 0x00, 0x62, 0x44, 0xf2, 0x40, + 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0x05, 0x61, + 0x6f, 0xf0, 0x1f, 0xb7, 0xfd, 0x47, 0x63, 0xf8, 0x87, 0x02, 0x93, 0x05, 0x04, 0xfe, 0xef, 0xf0, + 0x5f, 0xbf, 0x13, 0x04, 0x04, 0x04, 0x0e, 0x04, 0x42, 0x04, 0x41, 0x80, 0x93, 0x17, 0x84, 0x00, + 0x37, 0x07, 0xff, 0x00, 0xf9, 0x8f, 0x62, 0x04, 0x3e, 0x94, 0xb7, 0x07, 0x00, 0x04, 0x03, 0x25, + 0xca, 0x00, 0xc0, 0xdf, 0x65, 0xbf, 0x01, 0x45, 0xef, 0xf0, 0x3f, 0xa9, 0xd9, 0xbf, 0xf2, 0x40, + 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, + 0x22, 0xcc, 0x37, 0x34, 0x20, 0x00, 0x93, 0x07, 0x44, 0xe9, 0x52, 0xc4, 0x2a, 0x8a, 0xc8, 0x47, + 0x56, 0xc2, 0x06, 0xce, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x30, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, + 0xae, 0x8a, 0xef, 0xf0, 0xff, 0xaf, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x11, 0xf5, 0x12, 0xaa, 0x84, + 0x13, 0x05, 0x60, 0x03, 0xef, 0xf0, 0x7f, 0xa4, 0x13, 0x04, 0x44, 0xe9, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x45, 0x00, 0xef, 0xf0, 0xdf, 0xad, 0x2a, 0x89, 0x63, 0x11, 0x95, 0x10, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xbf, 0xac, 0xaa, 0x84, 0x63, 0x18, 0x25, 0x0f, + 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x5f, 0xab, + 0xaa, 0x89, 0x63, 0x1d, 0x95, 0x0c, 0xd6, 0x85, 0x52, 0x85, 0xef, 0xf0, 0xdf, 0xec, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xbf, 0xa9, 0xaa, 0x84, 0x63, 0x10, 0x35, 0x0d, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x03, 0xef, 0xf0, 0x9f, 0xa8, 0xaa, 0x89, 0x63, 0x17, + 0x95, 0x0a, 0x13, 0x05, 0xc0, 0x05, 0xef, 0xf0, 0x5f, 0x9d, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x45, 0x00, 0xef, 0xf0, 0xff, 0xa6, 0xaa, 0x84, 0x63, 0x1a, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xa5, 0xaa, 0x89, 0x63, 0x11, 0x95, 0x08, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x32, 0xef, 0xf0, 0xbf, 0xa4, 0xaa, 0x84, 0x63, 0x18, 0x35, 0x07, + 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x9f, 0xa3, 0x63, 0x10, 0x95, 0x06, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x03, 0xef, 0xf0, 0x9f, 0xa2, 0x93, 0x07, 0xa0, 0x0a, + 0x2a, 0x89, 0x63, 0x15, 0xf5, 0x04, 0x13, 0x05, 0x00, 0x06, 0xef, 0xf0, 0x9f, 0x99, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xbf, 0xa0, 0xaa, 0x84, 0x63, 0x18, 0x25, 0x03, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x9f, 0x9f, 0x63, 0x10, 0x95, 0x02, + 0x48, 0x44, 0x62, 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0x05, 0x61, 0x6f, 0xf0, 0x9f, 0x9d, 0xf2, 0x40, 0x62, 0x44, + 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x39, 0x71, + 0x22, 0xdc, 0x37, 0x34, 0x20, 0x00, 0x06, 0xde, 0x4a, 0xd8, 0x26, 0xda, 0x32, 0x89, 0x13, 0x04, + 0x44, 0xe9, 0xef, 0xf0, 0xdf, 0xe8, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x40, 0xef, 0xf0, + 0x3f, 0x9a, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x0a, 0xaa, 0x84, 0x37, 0x55, 0x10, 0x00, + 0x85, 0x45, 0x13, 0x05, 0xc5, 0x6b, 0xef, 0xf0, 0x9f, 0xe6, 0x85, 0x47, 0x63, 0x07, 0xf9, 0x08, + 0x48, 0x44, 0x85, 0x67, 0x93, 0x87, 0x07, 0x80, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0x5f, 0x97, + 0x2a, 0x89, 0x63, 0x1c, 0x95, 0x06, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, + 0x05, 0x04, 0x68, 0x00, 0xef, 0xe0, 0xef, 0x91, 0x48, 0x44, 0x89, 0x47, 0x23, 0x06, 0xf1, 0x02, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x20, 0xef, 0xf0, 0xbf, 0x94, 0xaa, 0x84, 0x63, 0x17, 0x25, 0x05, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0x9f, 0x93, 0x2a, 0x89, 0x63, 0x1e, + 0x95, 0x02, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x42, 0xef, 0xf0, 0x7f, 0x92, 0xaa, 0x84, + 0x63, 0x15, 0x25, 0x03, 0x68, 0x00, 0x93, 0x05, 0x10, 0x02, 0xef, 0xf0, 0x5f, 0xdf, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x10, 0xef, 0xf0, 0xbf, 0x90, 0x63, 0x18, 0x95, 0x00, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xbf, 0x8f, 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, + 0x42, 0x59, 0x21, 0x61, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, + 0x44, 0xe9, 0x08, 0x40, 0x09, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x06, 0xc6, + 0xef, 0xf0, 0xff, 0xf0, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x71, 0xef, 0xf0, 0x5f, 0x8c, + 0x48, 0x44, 0x22, 0x44, 0xb2, 0x40, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x40, 0x41, 0x01, 0x6f, 0xf0, + 0x3f, 0x8b, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x47, 0xe9, 0x05, 0x46, 0x93, 0x05, 0x00, 0x02, + 0x13, 0x05, 0x15, 0x04, 0x6f, 0xf0, 0xbf, 0xed, 0x41, 0x11, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x05, + 0x00, 0x04, 0x22, 0xc4, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x45, 0x6c, 0x13, 0x05, 0x05, 0x02, + 0x37, 0x34, 0x20, 0x00, 0x06, 0xc6, 0x13, 0x04, 0x44, 0xe9, 0xef, 0xe0, 0x4f, 0x8a, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0x86, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x1d, + 0xf5, 0x00, 0x08, 0x40, 0x22, 0x44, 0xb2, 0x40, 0x05, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, + 0x15, 0x04, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xe8, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, + 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x44, 0xe9, 0x48, 0x44, 0x06, 0xc6, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xbf, 0x82, 0x08, 0x40, 0x13, 0x06, 0x00, 0x02, + 0x81, 0x45, 0x13, 0x05, 0x15, 0x04, 0xef, 0x00, 0x90, 0x5c, 0x08, 0x40, 0x09, 0x46, 0x81, 0x45, + 0x13, 0x05, 0x15, 0x04, 0xef, 0xf0, 0xbf, 0xe4, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x60, + 0xef, 0xf0, 0x1f, 0x80, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x71, 0xef, 0xf0, 0x4f, 0xff, + 0x01, 0x45, 0xef, 0xf0, 0x8f, 0xf4, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, + 0x2f, 0xfe, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x6f, 0xfd, 0xb2, 0x40, + 0x22, 0x44, 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, 0x98, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x11, 0x65, + 0xad, 0xa9, 0x37, 0x35, 0x20, 0x00, 0x41, 0x11, 0x51, 0x46, 0x81, 0x45, 0x13, 0x05, 0x45, 0xe9, + 0x06, 0xc6, 0xef, 0x00, 0xd0, 0x55, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x1d, 0x65, + 0x23, 0xa2, 0xe7, 0xfa, 0xa9, 0x21, 0xb2, 0x40, 0xb7, 0x07, 0x00, 0x04, 0x05, 0x47, 0x98, 0xcb, + 0x41, 0x01, 0x6f, 0xf0, 0xdf, 0xfc, 0x11, 0x65, 0x1d, 0xa9, 0x95, 0x47, 0x63, 0xec, 0xb7, 0x02, + 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x44, 0xe9, 0x85, 0x47, 0x5c, 0xc0, + 0xb7, 0x57, 0x10, 0x00, 0x0c, 0xc4, 0x93, 0x87, 0x87, 0x6e, 0x8a, 0x05, 0xbe, 0x95, 0x9c, 0x41, + 0x06, 0xc6, 0x08, 0xc0, 0x82, 0x97, 0x08, 0x48, 0xb2, 0x40, 0x23, 0x22, 0x04, 0x00, 0x22, 0x44, + 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x05, 0x00, 0x04, 0x41, 0x46, + 0x93, 0x85, 0x05, 0x08, 0x6f, 0xd0, 0xff, 0xef, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xe9, + 0x89, 0x47, 0x5c, 0xc3, 0x5c, 0x47, 0x46, 0x05, 0xfe, 0x07, 0xc9, 0x8f, 0x21, 0x65, 0x15, 0x05, + 0x5d, 0x8d, 0x6f, 0xf0, 0xef, 0xf1, 0x39, 0x71, 0x4e, 0xd6, 0x5e, 0xce, 0x62, 0xcc, 0xb7, 0x0b, + 0x00, 0x04, 0xb7, 0x39, 0x20, 0x00, 0x05, 0x6c, 0x22, 0xdc, 0x26, 0xda, 0x4a, 0xd8, 0x56, 0xd2, + 0x5a, 0xd0, 0x66, 0xca, 0x6a, 0xc8, 0x06, 0xde, 0x52, 0xd4, 0x2a, 0x84, 0x2e, 0x8b, 0xb2, 0x8a, + 0x81, 0x44, 0x01, 0x49, 0xc1, 0x4c, 0x93, 0x8b, 0x0b, 0x02, 0x93, 0x89, 0x49, 0xe9, 0x09, 0x0c, + 0x37, 0x3d, 0x20, 0x00, 0xb3, 0x05, 0x9b, 0x00, 0x63, 0xe0, 0x54, 0x03, 0xf2, 0x50, 0x62, 0x54, + 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, + 0xd2, 0x4c, 0x42, 0x4d, 0x21, 0x61, 0x82, 0x80, 0x33, 0x8a, 0x9a, 0x40, 0x63, 0xd3, 0x4c, 0x01, + 0x41, 0x4a, 0x4a, 0x85, 0x2e, 0xc6, 0xef, 0xe0, 0xcf, 0x9f, 0xb2, 0x45, 0x13, 0x06, 0x3a, 0x00, + 0x71, 0x9a, 0x5e, 0x85, 0xef, 0xd0, 0xbf, 0xec, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x07, 0xef, 0xf0, 0xef, 0xe8, 0x03, 0xa5, 0xc9, 0x00, 0x93, 0x17, 0x8a, 0x01, 0x7e, 0x05, + 0x5d, 0x8d, 0x13, 0x65, 0x75, 0x00, 0xef, 0xf0, 0xaf, 0xe7, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, + 0x33, 0x65, 0x85, 0x01, 0xef, 0xf0, 0xcf, 0xe6, 0x03, 0x27, 0x4d, 0xfa, 0x93, 0x07, 0x50, 0x05, + 0x63, 0x19, 0xf7, 0x00, 0x19, 0xc4, 0x22, 0x85, 0x52, 0x86, 0xca, 0x85, 0xef, 0xe0, 0x4f, 0xa3, + 0x41, 0x04, 0x93, 0x07, 0x00, 0x07, 0x63, 0xe3, 0x27, 0x01, 0x41, 0x09, 0xc1, 0x04, 0x9d, 0xb7, + 0x39, 0x71, 0x4e, 0xd6, 0x5a, 0xd0, 0x5e, 0xce, 0xb7, 0x39, 0x20, 0x00, 0x37, 0x0b, 0x02, 0x00, + 0x85, 0x6b, 0x26, 0xda, 0x4a, 0xd8, 0x52, 0xd4, 0x56, 0xd2, 0x62, 0xcc, 0x6a, 0xc8, 0x6e, 0xc6, + 0x06, 0xde, 0x22, 0xdc, 0x66, 0xca, 0xaa, 0x8a, 0xae, 0x84, 0x32, 0x8a, 0x01, 0x49, 0x81, 0x4d, + 0x37, 0x3c, 0x20, 0x00, 0x41, 0x4d, 0x93, 0x89, 0x49, 0xe9, 0x1d, 0x0b, 0x93, 0x8b, 0x0b, 0x82, + 0xb3, 0x8c, 0x2a, 0x01, 0x93, 0x07, 0x4c, 0xfa, 0x63, 0x64, 0x49, 0x03, 0xf2, 0x50, 0x62, 0x54, + 0x13, 0x07, 0x50, 0x05, 0x98, 0xc3, 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, 0x5a, + 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, 0xd2, 0x4c, 0x42, 0x4d, 0xb2, 0x4d, 0x21, 0x61, 0x82, 0x80, + 0x33, 0x04, 0x2a, 0x41, 0x63, 0x73, 0x8d, 0x00, 0x41, 0x44, 0x6e, 0x85, 0xef, 0xe0, 0xef, 0x91, + 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0xfa, 0x98, 0x43, 0x93, 0x07, 0x50, 0x05, 0x63, 0x19, + 0xf7, 0x00, 0x99, 0xc4, 0x26, 0x85, 0x22, 0x86, 0xee, 0x85, 0xef, 0xe0, 0xcf, 0x9b, 0xc1, 0x04, + 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x25, 0x00, 0xef, 0xf0, 0x6f, 0xd9, 0x03, 0xa5, + 0xc9, 0x00, 0x93, 0x17, 0x84, 0x01, 0x0d, 0x04, 0x7e, 0x05, 0x5d, 0x8d, 0x33, 0x65, 0x65, 0x01, + 0xef, 0xf0, 0x0f, 0xd8, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x33, 0x65, 0x75, 0x01, 0xef, 0xf0, + 0x2f, 0xd7, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x76, 0xc4, 0xff, 0x93, 0x85, 0x05, 0x04, 0x66, 0x85, + 0xef, 0xd0, 0x3f, 0xd2, 0x93, 0x07, 0x00, 0x06, 0x63, 0xe3, 0xb7, 0x01, 0xc1, 0x0d, 0x41, 0x09, + 0x81, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x2a, 0x84, 0x21, 0x45, 0x06, 0xc6, 0xef, 0xf0, 0x4f, 0xd4, + 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x19, 0xf5, 0x00, 0x22, 0x85, 0xef, 0xf0, 0x1f, 0xdf, 0xb7, 0x37, + 0x20, 0x00, 0x23, 0xac, 0x07, 0xe8, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, + 0x20, 0x00, 0x23, 0xa2, 0xa7, 0xfa, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x60, 0x02, + 0x98, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, 0x98, 0xc7, 0x82, 0x80, 0xb7, 0x07, + 0x00, 0x04, 0xc8, 0x4b, 0x82, 0x80, 0x39, 0x71, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x05, 0x47, + 0xb7, 0x07, 0x00, 0x04, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, + 0x32, 0xd2, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xd8, 0xc7, + 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0xe9, 0xd8, 0x43, 0x89, 0x46, 0x7d, 0x17, 0x63, 0xfe, + 0xe6, 0x02, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x05, 0x6c, 0xef, 0xd0, 0xef, 0xe0, + 0xef, 0xc0, 0x8f, 0xdc, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, + 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, + 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x13, 0x07, 0xa0, 0x0a, 0x98, 0xcb, + 0xd1, 0xbf, 0xb7, 0x07, 0x01, 0x02, 0x88, 0xd7, 0xcc, 0xd7, 0x88, 0xdb, 0xcc, 0xdb, 0x88, 0xdf, + 0xcc, 0xdf, 0x82, 0x80, 0x01, 0x11, 0x26, 0xca, 0xb7, 0x04, 0x01, 0x02, 0x22, 0xcc, 0xc0, 0x40, + 0xf5, 0x77, 0x93, 0x87, 0xf7, 0xa5, 0x7d, 0x8c, 0x89, 0x67, 0x93, 0x87, 0x07, 0x1a, 0x06, 0xce, + 0x4a, 0xc8, 0x4e, 0xc6, 0xc1, 0x8f, 0xaa, 0x89, 0xdc, 0xc0, 0x05, 0x45, 0x2e, 0x89, 0xef, 0xd0, + 0xbf, 0x99, 0x93, 0x67, 0x04, 0x40, 0xdc, 0xc0, 0x05, 0x45, 0xef, 0xd0, 0xff, 0x98, 0x85, 0x67, + 0x93, 0x87, 0x07, 0x40, 0x5d, 0x8c, 0xc0, 0xc0, 0xb7, 0x47, 0x00, 0x08, 0x23, 0xa4, 0x07, 0x00, + 0xb7, 0x57, 0x00, 0x08, 0x23, 0xa4, 0x07, 0x00, 0xf2, 0x40, 0x62, 0x44, 0x23, 0xa0, 0x34, 0x03, + 0x23, 0xa2, 0x24, 0x03, 0xb2, 0x49, 0xd2, 0x44, 0x42, 0x49, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x07, + 0x01, 0x02, 0x88, 0x53, 0xcc, 0x53, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x02, 0x88, 0x47, 0x21, 0x81, + 0x13, 0x75, 0xf5, 0x0f, 0x82, 0x80, 0x41, 0x11, 0x01, 0x45, 0x81, 0x45, 0x06, 0xc6, 0x22, 0xc4, + 0x26, 0xc2, 0xef, 0xf0, 0x1f, 0xf6, 0xef, 0xf0, 0x9f, 0xfd, 0xaa, 0x84, 0x2e, 0x84, 0x2a, 0x87, + 0xae, 0x86, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0x85, + 0x85, 0x71, 0x13, 0x05, 0x45, 0x64, 0x13, 0x06, 0x06, 0x70, 0xef, 0xd0, 0xaf, 0xc9, 0xa2, 0x85, + 0x22, 0x44, 0xb2, 0x40, 0x26, 0x85, 0x92, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xf3, 0x39, 0x71, + 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, + 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, + 0xef, 0xf0, 0x7f, 0xf9, 0xef, 0xc0, 0x4f, 0xc9, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, + 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, + 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x07, + 0x00, 0x02, 0x5c, 0x47, 0xc9, 0x8f, 0x5c, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0xd8, 0x47, + 0x13, 0x45, 0xf5, 0xff, 0x79, 0x8d, 0xc8, 0xc7, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x4f, + 0xc9, 0x8f, 0x1c, 0xcf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0x98, 0x4f, 0x13, 0x45, 0xf5, 0xff, + 0x79, 0x8d, 0x88, 0xcf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0xc8, 0xcb, 0x82, 0x80, 0x37, 0x07, + 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x47, 0x00, 0x1c, 0xc7, 0xb7, 0x07, 0x00, 0x03, 0x94, 0x4b, + 0x37, 0x37, 0x20, 0x00, 0x23, 0x24, 0xd7, 0xfa, 0x23, 0xa8, 0x07, 0x00, 0x82, 0x80, 0x37, 0x07, + 0x00, 0x02, 0x1c, 0x47, 0xb7, 0x06, 0x00, 0x03, 0xf9, 0x9b, 0x1c, 0xc7, 0x37, 0x07, 0x08, 0x00, + 0x9c, 0x46, 0xf9, 0x8f, 0xf5, 0xff, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, + 0x17, 0x00, 0x1c, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x87, 0xfa, 0xb7, 0x07, 0x00, 0x03, + 0x98, 0xcb, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0xc7, 0xfa, 0x93, 0x07, 0xa0, 0x0a, + 0x63, 0x0b, 0xf5, 0x00, 0xb7, 0x27, 0x03, 0x04, 0x9c, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, + 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x13, 0x05, 0x00, 0x10, 0x6f, 0xf0, 0x3f, 0xf4, + 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0x41, 0x11, 0x37, 0x37, + 0x20, 0x00, 0x23, 0x28, 0xf7, 0xfa, 0x06, 0xc6, 0xef, 0xf0, 0x1f, 0xfe, 0xb7, 0x27, 0x03, 0x04, + 0x09, 0x47, 0xd8, 0xc3, 0x37, 0x17, 0x03, 0x04, 0xb7, 0x07, 0x03, 0x04, 0x13, 0x07, 0x07, 0x80, + 0x23, 0xa0, 0x07, 0x00, 0x91, 0x07, 0xe3, 0x9d, 0xe7, 0xfe, 0xb7, 0x27, 0x03, 0x04, 0x0d, 0x47, + 0xd8, 0xc7, 0x98, 0x47, 0x85, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, + 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x00, 0x10, 0x6f, 0xf0, 0xff, 0xee, + 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0x37, 0x37, 0x20, 0x00, + 0x23, 0x28, 0xf7, 0xfa, 0xb7, 0x27, 0x03, 0x04, 0x05, 0x47, 0xd8, 0xc3, 0x82, 0x80, 0xc2, 0x05, + 0xc9, 0x8d, 0x93, 0xe5, 0x05, 0x10, 0xb7, 0x07, 0x03, 0x04, 0x23, 0xa0, 0xb7, 0x10, 0x82, 0x80, + 0xc2, 0x05, 0xc9, 0x8d, 0x11, 0x65, 0x13, 0x05, 0x05, 0x50, 0xc9, 0x8d, 0xb7, 0x07, 0x03, 0x04, + 0x23, 0xa0, 0xb7, 0x10, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, + 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xb0, 0x9f, 0xc4, 0x37, 0x15, 0x03, 0x04, 0x2a, 0x94, 0x08, 0x40, + 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x79, 0x71, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, + 0x06, 0xd6, 0x22, 0xd4, 0xaa, 0x84, 0x2e, 0x89, 0xb2, 0x89, 0x19, 0xe1, 0xef, 0xb0, 0x1f, 0xc2, + 0x93, 0x77, 0x39, 0x00, 0x99, 0xc3, 0xef, 0xb0, 0x7f, 0xc1, 0x01, 0x44, 0x63, 0x69, 0x34, 0x01, + 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x45, 0x61, 0x82, 0x80, 0x33, 0x05, + 0x24, 0x01, 0xef, 0xf0, 0x5f, 0xfa, 0x2a, 0xc6, 0x11, 0x46, 0x33, 0x85, 0x84, 0x00, 0x6c, 0x00, + 0xcd, 0x2d, 0x11, 0x04, 0xe1, 0xbf, 0x79, 0x71, 0x22, 0xd4, 0x4a, 0xd0, 0x4e, 0xce, 0x56, 0xca, + 0x06, 0xd6, 0x26, 0xd2, 0x52, 0xcc, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0xae, 0x89, 0x32, 0x89, + 0x93, 0x7a, 0xc6, 0xff, 0x99, 0xc3, 0xef, 0xb0, 0x7f, 0xbc, 0x37, 0x0a, 0x03, 0x04, 0x81, 0x44, + 0x22, 0x9a, 0x63, 0xe9, 0x54, 0x03, 0x13, 0x76, 0x39, 0x00, 0x01, 0xce, 0xb3, 0x85, 0x99, 0x00, + 0x68, 0x00, 0x02, 0xc6, 0x7d, 0x25, 0xb2, 0x47, 0x37, 0x05, 0x03, 0x04, 0x2a, 0x94, 0x26, 0x94, + 0x1c, 0xc0, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0xd2, 0x4a, + 0x45, 0x61, 0x82, 0x80, 0x63, 0x94, 0x09, 0x00, 0xef, 0xb0, 0x5f, 0xb8, 0xb3, 0x85, 0x99, 0x00, + 0x11, 0x46, 0x68, 0x00, 0xbd, 0x2d, 0x32, 0x47, 0xb3, 0x07, 0x9a, 0x00, 0x91, 0x04, 0x98, 0xc3, + 0x4d, 0xbf, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x41, 0x11, 0x13, 0x05, 0x45, 0xb5, 0x06, 0xc6, + 0x22, 0xc4, 0xef, 0xd0, 0xef, 0xe9, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0f, 0xf5, 0x00, 0x37, 0x55, + 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x05, 0x72, 0xef, 0xd0, 0x2f, 0xa3, 0x13, 0x05, 0x50, 0x05, + 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x17, 0x03, 0x04, 0x83, 0xa7, 0x07, 0x10, + 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, 0xfb, 0x93, 0xf7, 0xf7, 0x0f, 0x81, 0xe7, 0x1c, 0x40, + 0x63, 0x9d, 0xa7, 0x00, 0x37, 0x55, 0x10, 0x00, 0x8d, 0x45, 0x13, 0x05, 0x05, 0x72, 0xef, 0xd0, + 0xcf, 0x9f, 0x93, 0x07, 0xa0, 0x0a, 0x1c, 0xc0, 0xd1, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, + 0xc7, 0xfa, 0x13, 0x84, 0xc7, 0xfa, 0x63, 0x09, 0xa7, 0x00, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, + 0x13, 0x05, 0x05, 0x72, 0xef, 0xd0, 0x6f, 0x9d, 0x08, 0x40, 0x5d, 0xb7, 0x37, 0x95, 0x04, 0x00, + 0x13, 0x05, 0x05, 0x3e, 0x6f, 0xf0, 0xff, 0xf6, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x5f, 0xe6, + 0xef, 0xf0, 0x1f, 0xe3, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x5f, 0xfe, 0xb7, 0x17, 0x03, 0x04, + 0x03, 0xa5, 0x07, 0x10, 0x41, 0x81, 0x82, 0x80, 0x41, 0x11, 0x3a, 0xc4, 0x37, 0x27, 0x03, 0x04, + 0x3e, 0xc2, 0x1c, 0x47, 0x36, 0xc6, 0x93, 0xf6, 0x27, 0x00, 0x89, 0xca, 0x89, 0x46, 0x14, 0xc7, + 0x37, 0x37, 0x20, 0x00, 0x93, 0x06, 0xa0, 0x0a, 0x23, 0x26, 0xd7, 0xfa, 0x91, 0x8b, 0x99, 0xcf, + 0xb7, 0x27, 0x03, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x93, 0x07, 0xa0, 0x0a, 0x37, 0x37, 0x20, 0x00, + 0x23, 0x28, 0xf7, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0xb2, 0x46, 0x22, 0x47, + 0x92, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x04, 0x00, 0x03, + 0x1c, 0x48, 0x06, 0xc6, 0xdd, 0x9b, 0x1c, 0xc8, 0xef, 0xe0, 0x0f, 0xd9, 0xb7, 0x07, 0x20, 0x00, + 0x93, 0x87, 0x07, 0x02, 0x5c, 0xcc, 0xb2, 0x40, 0x22, 0x44, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x8c, + 0x07, 0xfa, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x2a, 0x84, 0x21, 0x45, 0x06, 0xc6, + 0xef, 0xf0, 0x7f, 0xca, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x7f, 0xc6, 0x22, 0x04, 0x13, 0x64, + 0x04, 0x03, 0x37, 0x07, 0x00, 0x03, 0x40, 0xc3, 0xb2, 0x40, 0x22, 0x44, 0xc1, 0x67, 0x93, 0x87, + 0xa7, 0xfa, 0x1c, 0xcf, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x26, 0xc2, 0xaa, 0x84, 0x09, 0x45, + 0x22, 0xc4, 0x06, 0xc6, 0x2e, 0x84, 0xef, 0xf0, 0x1f, 0xfc, 0x37, 0x07, 0x20, 0x00, 0xb7, 0x07, + 0x00, 0x03, 0x13, 0x07, 0x07, 0x02, 0xd8, 0xcf, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2a, 0x97, 0xfa, + 0x37, 0x37, 0x20, 0x00, 0x23, 0x2e, 0x87, 0xfa, 0xb2, 0x40, 0x22, 0x44, 0x05, 0x47, 0x98, 0xcb, + 0x37, 0x07, 0x08, 0x00, 0x98, 0xc7, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x03, + 0x9c, 0x47, 0x37, 0x07, 0x04, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x99, 0xe3, 0x13, 0x05, + 0x50, 0x05, 0x82, 0x80, 0x37, 0x07, 0x00, 0x03, 0x5c, 0x53, 0x13, 0x05, 0x50, 0x05, 0x93, 0x96, + 0x07, 0x01, 0xc1, 0x82, 0xc1, 0x83, 0x63, 0x97, 0xf6, 0x00, 0x1c, 0x47, 0x91, 0x8b, 0x99, 0xe3, + 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xff, 0xf1, 0x37, 0x07, + 0x00, 0x03, 0x5c, 0x47, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc7, 0x5c, 0x47, 0x85, 0x8b, 0xf5, 0xff, + 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xfb, 0x95, 0xc3, + 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x5f, 0xef, 0xb7, 0x07, 0x00, 0x03, 0x98, 0x4b, 0xb2, 0x40, + 0x13, 0x67, 0x87, 0x00, 0x98, 0xcb, 0x37, 0x07, 0x08, 0x00, 0x98, 0xc7, 0x41, 0x01, 0x6f, 0xe0, + 0xcf, 0xc5, 0x82, 0x80, 0x37, 0x07, 0x00, 0x03, 0x1c, 0x4b, 0xf9, 0x9b, 0x1c, 0xcb, 0x82, 0x80, + 0xb7, 0x06, 0x00, 0x03, 0xdc, 0x42, 0x7d, 0x77, 0x13, 0x07, 0xf7, 0x0f, 0xf9, 0x8f, 0x05, 0x67, + 0x22, 0x05, 0x13, 0x07, 0x07, 0xf0, 0x79, 0x8d, 0x5d, 0x8d, 0xc8, 0xc2, 0x82, 0x80, 0x1d, 0x71, + 0x3a, 0xda, 0x37, 0x07, 0x00, 0x03, 0x3e, 0xd8, 0x1c, 0x47, 0x86, 0xce, 0x96, 0xcc, 0x9a, 0xca, + 0x9e, 0xc8, 0xa2, 0xc6, 0xa6, 0xc4, 0xaa, 0xc2, 0xae, 0xc0, 0x32, 0xde, 0x36, 0xdc, 0x42, 0xd6, + 0x46, 0xd4, 0x4a, 0xd2, 0x4e, 0xd0, 0x72, 0xce, 0x76, 0xcc, 0x7a, 0xca, 0x7e, 0xc8, 0x85, 0x8b, + 0xa1, 0xc7, 0x04, 0x57, 0x11, 0x44, 0x37, 0x39, 0x20, 0x00, 0x83, 0x27, 0x49, 0xfb, 0x13, 0xf5, + 0xf4, 0x0f, 0x7d, 0x14, 0x82, 0x97, 0xa1, 0x80, 0x6d, 0xf8, 0x36, 0x44, 0xf6, 0x40, 0xe6, 0x42, + 0x56, 0x43, 0xc6, 0x43, 0xa6, 0x44, 0x16, 0x45, 0x86, 0x45, 0x72, 0x56, 0xe2, 0x56, 0x52, 0x57, + 0xc2, 0x57, 0x32, 0x58, 0xa2, 0x58, 0x12, 0x59, 0x82, 0x59, 0x72, 0x4e, 0xe2, 0x4e, 0x52, 0x4f, + 0xc2, 0x4f, 0x25, 0x61, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xc7, 0x87, 0xfb, + 0x13, 0x84, 0x87, 0xfb, 0x05, 0xeb, 0xb7, 0x04, 0x00, 0x03, 0x37, 0x39, 0x20, 0x00, 0x93, 0x09, + 0xa0, 0x0a, 0x9c, 0x44, 0x91, 0x8b, 0xd5, 0xfb, 0x83, 0x27, 0xc9, 0xfb, 0x68, 0x00, 0x82, 0x97, + 0x63, 0x0d, 0x35, 0x01, 0x85, 0x47, 0x23, 0x00, 0xf4, 0x00, 0xc1, 0x67, 0x93, 0x87, 0x07, 0x02, + 0xdc, 0xcc, 0x61, 0xbf, 0xef, 0xf0, 0x5f, 0xdf, 0x49, 0xbf, 0xb2, 0x47, 0x9c, 0xd8, 0xd1, 0xbf, + 0x5c, 0x41, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc1, 0x82, 0x80, 0x5c, 0x41, 0xf9, 0x9b, 0x5c, 0xc1, + 0x82, 0x80, 0x5c, 0x41, 0xf5, 0x9b, 0xd1, 0x8f, 0x5c, 0xc1, 0x14, 0xc9, 0x4c, 0xc9, 0x82, 0x80, + 0x5c, 0x45, 0xcd, 0x8f, 0x5c, 0xc5, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x07, 0xfc, + 0x82, 0x80, 0x39, 0x71, 0x3a, 0xce, 0x37, 0x07, 0x10, 0x01, 0x3e, 0xcc, 0x1c, 0x47, 0x58, 0x47, + 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, + 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xf9, 0x8f, 0x91, 0xcf, + 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xfc, 0x98, 0x43, 0x05, 0x07, 0x98, 0xc3, 0xb7, 0x07, + 0x10, 0x01, 0x98, 0x47, 0x0d, 0x8b, 0x98, 0xc7, 0x19, 0xa8, 0xb7, 0x07, 0x20, 0x01, 0x98, 0x47, + 0xdc, 0x47, 0x7d, 0x8f, 0xb7, 0x07, 0x20, 0x01, 0x6d, 0xf7, 0xef, 0xb0, 0xff, 0xe6, 0xf2, 0x50, + 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, + 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, + 0x73, 0x00, 0x20, 0x30, 0x1c, 0x41, 0x63, 0xf7, 0xb7, 0x00, 0x23, 0x80, 0xc7, 0x00, 0x1c, 0x41, + 0x85, 0x07, 0x1c, 0xc1, 0x82, 0x80, 0x1d, 0x71, 0xa2, 0xcc, 0xa6, 0xca, 0xca, 0xc8, 0x86, 0xce, + 0xce, 0xc6, 0xd2, 0xc4, 0xd6, 0xc2, 0xda, 0xc0, 0x5e, 0xde, 0x62, 0xdc, 0x66, 0xda, 0x6a, 0xd8, + 0x6e, 0xd6, 0x2a, 0xc6, 0x2e, 0x84, 0x32, 0x89, 0xb6, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x0f, 0xf6, + 0x63, 0x14, 0x09, 0x00, 0xef, 0xb0, 0x8f, 0xf5, 0x01, 0x45, 0x05, 0xc4, 0xb2, 0x4a, 0x7d, 0x14, + 0x25, 0x4a, 0x56, 0x94, 0x93, 0x0c, 0xc0, 0x06, 0x13, 0x0b, 0x30, 0x07, 0xa9, 0x4b, 0x1d, 0x4d, + 0x03, 0x46, 0x09, 0x00, 0x15, 0xe6, 0xb2, 0x47, 0x23, 0x80, 0x07, 0x00, 0x32, 0x45, 0x33, 0x05, + 0x55, 0x41, 0xf6, 0x40, 0x66, 0x44, 0xd6, 0x44, 0x46, 0x49, 0xb6, 0x49, 0x26, 0x4a, 0x96, 0x4a, + 0x06, 0x4b, 0xf2, 0x5b, 0x62, 0x5c, 0xd2, 0x5c, 0x42, 0x5d, 0xb2, 0x5d, 0x25, 0x61, 0x82, 0x80, + 0x93, 0x07, 0x50, 0x02, 0x63, 0x1f, 0xf6, 0x02, 0x93, 0x07, 0x19, 0x00, 0x83, 0xc6, 0x07, 0x00, + 0x3e, 0x89, 0x85, 0x07, 0x13, 0x87, 0x06, 0xfd, 0x13, 0x77, 0xf7, 0x0f, 0xe3, 0x78, 0xea, 0xfe, + 0x63, 0x93, 0x96, 0x01, 0x3e, 0x89, 0x03, 0x46, 0x09, 0x00, 0x63, 0x06, 0x66, 0x0d, 0x63, 0x60, + 0xcb, 0x02, 0x93, 0x07, 0x30, 0x06, 0x63, 0x05, 0xf6, 0x06, 0x93, 0x07, 0x40, 0x06, 0x63, 0x0c, + 0xf6, 0x06, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, 0xf2, 0xa6, 0x89, 0x95, 0xa0, 0x93, 0x07, + 0x50, 0x07, 0x63, 0x02, 0xf6, 0x06, 0x93, 0x07, 0x80, 0x07, 0xe3, 0x14, 0xf6, 0xfe, 0x98, 0x40, + 0x93, 0x89, 0x44, 0x00, 0x81, 0x46, 0x37, 0x06, 0x00, 0xf0, 0xb3, 0x75, 0xc7, 0x00, 0xba, 0x84, + 0x36, 0x8c, 0x12, 0x07, 0x85, 0x06, 0x89, 0xe5, 0xe3, 0x99, 0xa6, 0xff, 0x1d, 0x4c, 0xba, 0x84, + 0xa1, 0x4d, 0x13, 0xd7, 0xc4, 0x01, 0x63, 0x74, 0xea, 0x08, 0x13, 0x06, 0x77, 0x05, 0xa2, 0x85, + 0x68, 0x00, 0x05, 0x0c, 0xef, 0xf0, 0x1f, 0xee, 0x92, 0x04, 0xe3, 0x14, 0xbc, 0xff, 0x09, 0xa8, + 0x03, 0xc6, 0x04, 0x00, 0xa2, 0x85, 0x68, 0x00, 0x93, 0x89, 0x44, 0x00, 0xef, 0xf0, 0x9f, 0xec, + 0x05, 0x09, 0xce, 0x84, 0x31, 0xbf, 0x5c, 0x08, 0x98, 0x40, 0x93, 0x89, 0x44, 0x00, 0x3e, 0x8c, + 0x81, 0x44, 0xb3, 0x76, 0x77, 0x03, 0x85, 0x04, 0x85, 0x07, 0x93, 0x86, 0x06, 0x03, 0xa3, 0x8f, + 0xd7, 0xfe, 0xba, 0x86, 0x33, 0x57, 0x77, 0x03, 0xe3, 0x65, 0xda, 0xfe, 0xfd, 0x5d, 0xfd, 0x14, + 0xe3, 0x88, 0xb4, 0xfd, 0xb3, 0x07, 0x9c, 0x00, 0x03, 0xc6, 0x07, 0x00, 0xa2, 0x85, 0x68, 0x00, + 0xef, 0xf0, 0x5f, 0xe8, 0xed, 0xb7, 0x93, 0x89, 0x44, 0x00, 0x84, 0x40, 0x03, 0xc6, 0x04, 0x00, + 0x45, 0xda, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, 0xe6, 0x85, 0x04, 0xc5, 0xbf, 0x13, 0x06, + 0x07, 0x03, 0xb5, 0xbf, 0x41, 0x11, 0x26, 0xc2, 0xb7, 0x34, 0x20, 0x00, 0x2a, 0x86, 0xae, 0x86, + 0x13, 0x85, 0x84, 0xea, 0x93, 0x05, 0x00, 0x08, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0xf0, 0xbf, 0xe5, + 0x2a, 0x84, 0x13, 0x85, 0x84, 0xea, 0xef, 0xd0, 0x8f, 0x9b, 0xb2, 0x40, 0x22, 0x85, 0x22, 0x44, + 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x26, 0xca, 0xb7, 0x34, 0x20, 0x00, 0x2e, 0xd2, + 0x32, 0xd4, 0x36, 0xd6, 0x2a, 0x86, 0x54, 0x10, 0x93, 0x05, 0x00, 0x08, 0x13, 0x85, 0x84, 0xea, + 0x06, 0xce, 0x22, 0xcc, 0x3a, 0xd8, 0x3e, 0xda, 0x42, 0xdc, 0x46, 0xde, 0x36, 0xc6, 0xef, 0xf0, + 0x9f, 0xe1, 0x2a, 0x84, 0x13, 0x85, 0x84, 0xea, 0xef, 0xd0, 0x6f, 0x97, 0xf2, 0x40, 0x22, 0x85, + 0x62, 0x44, 0xd2, 0x44, 0x21, 0x61, 0x82, 0x80, 0x22, 0x05, 0x61, 0x77, 0x2d, 0x8d, 0xa1, 0x47, + 0x15, 0x07, 0x93, 0x16, 0x05, 0x01, 0x06, 0x05, 0x42, 0x05, 0xc1, 0x86, 0x41, 0x81, 0x63, 0xd5, + 0x06, 0x00, 0x39, 0x8d, 0x42, 0x05, 0x41, 0x81, 0xfd, 0x17, 0xe5, 0xf7, 0x82, 0x80, 0x41, 0x11, + 0x22, 0xc4, 0x26, 0xc2, 0x2a, 0x84, 0xb3, 0x04, 0xb5, 0x00, 0x06, 0xc6, 0x01, 0x45, 0x63, 0x97, + 0x84, 0x00, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x04, 0xaa, 0x85, + 0x03, 0x45, 0xf4, 0xff, 0xef, 0xf0, 0x5f, 0xfb, 0xdd, 0xb7, 0xb7, 0x86, 0xb8, 0xed, 0x01, 0x47, + 0xfd, 0x57, 0x93, 0x86, 0x06, 0x32, 0x63, 0x15, 0xb7, 0x00, 0x13, 0xc5, 0xf7, 0xff, 0x82, 0x80, + 0x33, 0x06, 0xe5, 0x00, 0x03, 0x46, 0x06, 0x00, 0xb1, 0x8f, 0x21, 0x46, 0x13, 0xd8, 0x17, 0x00, + 0x85, 0x8b, 0x91, 0xc3, 0xb6, 0x87, 0x7d, 0x16, 0xb3, 0x47, 0xf8, 0x00, 0x65, 0xfa, 0x05, 0x07, + 0xd9, 0xbf, 0x2a, 0x83, 0x09, 0xca, 0x83, 0x83, 0x05, 0x00, 0x23, 0x00, 0x73, 0x00, 0x7d, 0x16, + 0x05, 0x03, 0x85, 0x05, 0x6d, 0xfa, 0x82, 0x80, 0x15, 0xc2, 0x2a, 0x83, 0x85, 0x46, 0x63, 0x67, + 0xb5, 0x00, 0xfd, 0x56, 0x13, 0x07, 0xf6, 0xff, 0x3a, 0x93, 0xba, 0x95, 0x83, 0x83, 0x05, 0x00, + 0x23, 0x00, 0x73, 0x00, 0x7d, 0x16, 0x36, 0x93, 0xb6, 0x95, 0x6d, 0xfa, 0x82, 0x80, 0x2a, 0x83, + 0x11, 0xc6, 0x23, 0x00, 0xb3, 0x00, 0x7d, 0x16, 0x05, 0x03, 0x65, 0xfe, 0x82, 0x80, 0x00, 0x00, + 0x63, 0x6f, 0x64, 0x65, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, 0x53, 0x45, 0x43, 0x43, + 0x48, 0x4e, 0x4c, 0x00, 0x4d, 0x43, 0x4e, 0x54, 0x00, 0x00, 0x00, 0x00, 0x54, 0x58, 0x3a, 0x20, + 0x25, 0x64, 0x2f, 0x25, 0x64, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x43, 0x4d, 0x44, 0x33, + 0x00, 0x00, 0x00, 0x00, 0x49, 0x00, 0x00, 0x00, 0x65, 0x6e, 0x61, 0x62, 0x6c, 0x65, 0x64, 0x20, + 0x25, 0x64, 0x00, 0x00, 0x4d, 0x41, 0x49, 0x4e, 0x00, 0x00, 0x00, 0x00, 0x6c, 0x65, 0x6e, 0x20, + 0x25, 0x64, 0x2f, 0x25, 0x64, 0x00, 0x00, 0x00, 0x72, 0x73, 0x70, 0x3d, 0x25, 0x78, 0x00, 0x00, + 0x73, 0x74, 0x61, 0x72, 0x74, 0x2c, 0x20, 0x76, 0x25, 0x75, 0x2e, 0x25, 0x75, 0x2e, 0x25, 0x75, + 0x00, 0x00, 0x00, 0x00, 0x50, 0x52, 0x4f, 0x56, 0x49, 0x53, 0x49, 0x4f, 0x4e, 0x20, 0x4f, 0x4b, + 0x00, 0x00, 0x00, 0x00, 0x4e, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x43, 0x50, 0x42, 0x3a, + 0x20, 0x25, 0x64, 0x00, 0x4c, 0x33, 0x20, 0x63, 0x6d, 0x64, 0x20, 0x25, 0x64, 0x3a, 0x20, 0x25, + 0x78, 0x2c, 0x20, 0x6c, 0x65, 0x6e, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x00, 0x4c, 0x33, 0x20, 0x61, + 0x63, 0x63, 0x65, 0x73, 0x73, 0x20, 0x66, 0x61, 0x69, 0x6c, 0x65, 0x64, 0x2c, 0x20, 0x63, 0x6d, + 0x64, 0x3a, 0x20, 0x25, 0x64, 0x2c, 0x20, 0x6c, 0x65, 0x6e, 0x3a, 0x20, 0x25, 0x64, 0x20, 0x00, + 0x70, 0x69, 0x6e, 0x67, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x00, 0x4c, 0x33, 0x00, 0x00, + 0x57, 0x52, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x00, 0x52, 0x44, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x00, + 0x6d, 0x61, 0x63, 0x61, 0x6e, 0x64, 0x64, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x00, 0x00, + 0x73, 0x65, 0x6e, 0x74, 0x00, 0x00, 0x00, 0x00, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x20, 0x73, 0x6c, + 0x65, 0x65, 0x70, 0x00, 0x77, 0x61, 0x6b, 0x65, 0x75, 0x70, 0x00, 0x00, 0x56, 0x19, 0x10, 0x00, + 0x94, 0x19, 0x10, 0x00, 0xc0, 0x19, 0x10, 0x00, 0xf0, 0x19, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, + 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, + 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, + 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0x0a, 0x1a, 0x10, 0x00, + 0x64, 0x1a, 0x10, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 0x00, 0x06, + 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x1f, 0x00, 0x06, 0x02, 0x00, 0x05, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x06, 0x03, 0x10, 0x08, 0x00, 0x00, 0x18, 0x00, 0x00, + 0x40, 0x1f, 0x00, 0x06, 0x06, 0x10, 0x08, 0x00, 0x04, 0x18, 0x00, 0x00, 0x60, 0x1f, 0x00, 0x06, + 0x04, 0x00, 0x09, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x06, 0x05, 0x05, 0x7f, 0x07, 0x01, + 0x08, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xf0, 0x01, 0x10, 0x10, 0x00, 0x04, 0x02, + 0x11, 0x00, 0x44, 0x02, 0x12, 0x00, 0x84, 0x02, 0x20, 0x90, 0x01, 0x03, 0x21, 0x80, 0x42, 0x03, + 0x22, 0xf0, 0x01, 0x03, 0x30, 0x80, 0x02, 0x04, 0x31, 0x80, 0x42, 0x04, 0x40, 0x70, 0x04, 0x11, + 0x41, 0x70, 0x44, 0x11, 0x42, 0x70, 0x84, 0x11, 0x50, 0xf0, 0x01, 0x12, 0x60, 0x32, 0x04, 0x13, + 0x61, 0x32, 0x44, 0x13, 0x62, 0x32, 0x84, 0x13, 0x63, 0x32, 0xc4, 0x13, 0x70, 0x32, 0x04, 0x14, + 0x71, 0x32, 0x44, 0x14, 0x80, 0x20, 0x04, 0x15, 0x81, 0x20, 0x84, 0x15, 0x82, 0x20, 0x44, 0x15, + 0x90, 0x51, 0x04, 0x16, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x14, 0x04, 0x04, + 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x20, 0x25, 0x6c, 0x75, 0x20, 0x00, 0x00, + 0x25, 0x73, 0x28, 0x25, 0x73, 0x29, 0x3a, 0x20, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, + 0x45, 0x00, 0x00, 0x00, 0x4d, 0x53, 0x47, 0x00, 0x43, 0x52, 0x43, 0x20, 0x72, 0x78, 0x3a, 0x20, + 0x25, 0x30, 0x34, 0x78, 0x2c, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x3a, 0x20, 0x25, 0x30, 0x34, 0x78, + 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0xe4, 0x1f, 0x10, 0x00, 0x04, 0x20, 0x10, 0x00, + 0x56, 0x20, 0x10, 0x00, 0xb8, 0x20, 0x10, 0x00, 0xc2, 0x20, 0x10, 0x00, 0x4f, 0x53, 0x00, 0x00, + 0x63, 0x6f, 0x6e, 0x64, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, 0x52, 0x58, 0x3a, 0x20, + 0x63, 0x6d, 0x64, 0x3d, 0x30, 0x78, 0x25, 0x30, 0x32, 0x78, 0x00, 0x00, 0x55, 0x49, 0x00, 0x00, + 0x43, 0x50, 0x42, 0x20, 0x49, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x20, 0x21, 0x00, + 0x43, 0x50, 0x42, 0x00, 0x57, 0x00, 0x00, 0x00, 0x46, 0x53, 0x53, 0x00, 0x49, 0x52, 0x51, 0x00, + 0x53, 0x54, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x4b, 0x44, 0x42, 0x00, 0x73, 0x74, 0x3a, 0x20, + 0x25, 0x78, 0x00, 0x00, 0x4d, 0x41, 0x44, 0x00, 0x4f, 0x54, 0x50, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x53, 0x43, 0x42, 0x00, 0x4e, 0x6f, 0x69, 0x73, 0x65, 0x5f, 0x4b, 0x4b, 0x31, 0x5f, 0x32, 0x35, + 0x35, 0x31, 0x39, 0x5f, 0x41, 0x45, 0x53, 0x47, 0x43, 0x4d, 0x5f, 0x53, 0x48, 0x41, 0x32, 0x35, + 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x3f, 0x10, 0x00, 0x78, 0x45, 0x10, 0x00, + 0x62, 0x45, 0x10, 0x00, 0x26, 0x45, 0x10, 0x00, 0x3a, 0x3e, 0x10, 0x00, 0xd0, 0x45, 0x10, 0x00, + 0x41, 0x4c, 0x41, 0x52, 0x4d, 0x20, 0x43, 0x48, 0x41, 0x4e, 0x4e, 0x45, 0x4c, 0x53, 0x3a, 0x20, + 0x25, 0x78, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x53, 0x43, 0x4e, 0x54, 0x52, 0x00, 0x00, 0x00, + 0x53, 0x50, 0x45, 0x43, 0x54, 0x00, 0x00, 0x00, 0xc3, 0x14, 0x13, 0x00}; \ No newline at end of file diff --git a/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_1_0_1/fw_SPECT.h b/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_1_0_1/fw_SPECT.h index b12a33d5f..6193db5c8 100644 --- a/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_1_0_1/fw_SPECT.h +++ b/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_1_0_1/fw_SPECT.h @@ -5,552 +5,655 @@ /** * @brief SPECT firmware version spect_app-v1.0.0_signed.bin for bootloader v1.0.1 */ -const uint8_t fw_SPECT[] - = {0x6b, 0xc1, 0x97, 0x12, 0x62, 0xd1, 0x74, 0x61, 0x11, 0xc6, 0x82, 0x39, 0x3d, 0xb0, 0x9f, 0xb7, 0xde, 0xb2, 0x09, - 0x47, 0x40, 0x54, 0xca, 0xc2, 0x3c, 0x86, 0x9f, 0x05, 0xdb, 0x0e, 0xd7, 0x70, 0xe8, 0x6a, 0x1d, 0xd0, 0x6d, 0xa3, - 0xf7, 0xea, 0x18, 0x4e, 0xda, 0x94, 0x1c, 0x24, 0xaf, 0x8d, 0x1b, 0x24, 0x34, 0x9c, 0x18, 0x17, 0x38, 0x15, 0x37, - 0xf6, 0xc8, 0x61, 0x81, 0x81, 0x7b, 0x05, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x02, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa8, 0x24, 0x00, 0x00, 0xd4, 0x7d, 0x50, 0x04, 0xb7, 0xcf, 0xe1, 0x1e, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, - 0x7e, 0xa3, 0xe4, 0xa3, 0x00, 0x82, 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, 0x40, 0xa2, 0xff, 0x00, 0x48, 0xa3, 0x00, - 0x02, 0x82, 0x62, 0xf0, 0x10, 0x88, 0xa2, 0x20, 0x33, 0x4a, 0xc5, 0x00, 0x10, 0x40, 0x28, 0x2c, 0xa3, 0x00, 0x08, - 0x60, 0x40, 0x40, 0x28, 0x4c, 0x80, 0x00, 0x88, 0x10, 0x40, 0x40, 0xa8, 0x84, 0x80, 0x00, 0x08, 0x40, 0x40, 0x40, - 0xa8, 0xb8, 0x80, 0x00, 0x08, 0x70, 0x40, 0x40, 0xa8, 0x20, 0x81, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0x04, 0xa4, - 0x00, 0x82, 0xf4, 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x60, 0x10, 0x40, 0x28, 0x1c, - 0x9f, 0x00, 0x08, 0x61, 0x10, 0x40, 0xa8, 0x1c, 0x9f, 0x00, 0x08, 0x62, 0x10, 0x40, 0xa8, 0xa4, 0x9f, 0x00, 0x08, - 0x63, 0x10, 0x40, 0x28, 0xb0, 0xa0, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0xf3, 0x50, 0x8a, - 0xa4, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x11, 0x10, 0x40, 0x28, 0x60, 0xa2, 0x00, 0x08, 0x12, 0x10, - 0x40, 0x28, 0x9c, 0xa2, 0x00, 0x08, 0x13, 0x10, 0x40, 0xa8, 0xbc, 0xa2, 0x00, 0x88, 0x14, 0x10, 0x40, 0x28, 0xe0, - 0xa2, 0x00, 0x88, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x04, 0xa4, 0x00, 0x82, 0xf2, 0x50, 0x8a, 0x24, - 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x41, 0x10, 0x40, 0x28, 0x94, 0x8f, 0x00, 0x88, 0x42, 0x10, 0x40, - 0x28, 0xac, 0x90, 0x00, 0x88, 0x43, 0x10, 0x40, 0xa8, 0xd4, 0x90, 0x00, 0x88, 0x44, 0x10, 0x40, 0x28, 0x04, 0x91, - 0x00, 0x88, 0x45, 0x10, 0x40, 0xa8, 0xfc, 0x91, 0x00, 0x08, 0x46, 0x10, 0x40, 0xa8, 0xa0, 0x92, 0x00, 0x08, 0x47, - 0x10, 0x40, 0x28, 0xf4, 0x92, 0x00, 0x88, 0x48, 0x10, 0x40, 0x28, 0x30, 0x93, 0x00, 0x88, 0x49, 0x10, 0x40, 0xa8, - 0x48, 0x93, 0x00, 0x88, 0x4a, 0x10, 0x40, 0xa8, 0x18, 0x94, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, - 0x18, 0x04, 0xa4, 0x00, 0x82, 0xf1, 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x70, 0x10, - 0x40, 0xa8, 0x1c, 0xa1, 0x00, 0x88, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x02, 0x00, 0x44, 0x23, 0x64, - 0x81, 0x00, 0x02, 0x00, 0x00, 0x44, 0x69, 0x00, 0x00, 0x42, 0xa3, 0xf3, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, - 0x40, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x84, 0x50, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, - 0xf3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, 0x00, 0xf5, 0x00, 0x00, 0x00, 0xf5, 0xff, 0x00, - 0x42, 0xa3, 0x00, 0x10, 0x02, 0xf3, 0xff, 0x10, 0x82, 0xa4, 0x80, 0x00, 0x80, 0xe2, 0x00, 0x00, 0x00, 0x84, 0xa8, - 0xa4, 0x00, 0x18, 0x00, 0x10, 0x02, 0xf3, 0x00, 0x10, 0x02, 0xf3, 0x80, 0x00, 0x40, 0xe2, 0x00, 0x11, 0x40, 0x49, - 0x00, 0x00, 0xc0, 0x93, 0x80, 0x10, 0x84, 0xff, 0x80, 0x20, 0x86, 0x7f, 0x80, 0x31, 0x88, 0xff, 0x00, 0x42, 0x88, - 0xff, 0x80, 0x41, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, - 0x88, 0xff, 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x06, 0x00, 0x7c, 0x23, 0x00, - 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0xdc, 0x81, 0x00, 0x8a, - 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x0f, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, - 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0xfc, 0x81, 0x00, 0x0a, 0x80, 0x42, 0x8c, 0xff, 0x00, 0x63, - 0x88, 0xff, 0x3f, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, - 0xe0, 0x7d, 0xa4, 0x1c, 0x82, 0x00, 0x8a, 0x00, 0x43, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, - 0x1e, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, - 0xa4, 0x40, 0x82, 0x00, 0x8a, 0x00, 0x43, 0x88, 0x7f, 0x40, 0x30, 0x4a, 0xc5, 0x80, 0x00, 0x7c, 0xa3, 0x00, 0x42, - 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x50, 0x0a, 0x63, 0x80, 0x82, 0x00, 0x8c, 0x00, 0x50, 0x0a, 0x63, 0x94, - 0x82, 0x00, 0x0e, 0x80, 0x40, 0x88, 0xff, 0x94, 0x82, 0x00, 0x98, 0x00, 0x50, 0x0a, 0x63, 0x90, 0x82, 0x00, 0x0c, - 0x00, 0x41, 0x88, 0xff, 0x94, 0x82, 0x00, 0x98, 0x80, 0x41, 0x88, 0x7f, 0x02, 0xe0, 0x7d, 0x24, 0x60, 0x82, 0x00, - 0x0a, 0x00, 0x40, 0x42, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x86, 0xef, 0x80, 0x30, 0x88, 0xef, 0x00, 0x42, - 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, - 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x31, 0x86, 0x6f, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, - 0x00, 0x32, 0x8a, 0x6f, 0x80, 0x52, 0x86, 0xef, 0x09, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x01, 0xe0, 0x7d, - 0x24, 0xe0, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x86, 0xef, 0x0a, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, - 0x86, 0xef, 0x02, 0xe0, 0x7d, 0x24, 0xf4, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x8a, 0xef, 0x80, 0x52, 0x86, 0xef, 0x80, - 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x1e, 0x00, 0x7c, 0x23, - 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, 0x20, 0x83, 0x00, - 0x0a, 0x80, 0x30, 0x86, 0x6f, 0x80, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, - 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x04, 0xe0, 0x7d, 0x24, 0x3c, 0x83, 0x00, 0x8a, 0x00, 0x31, 0x86, 0x6f, 0x20, - 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, - 0x04, 0xe0, 0x7d, 0x24, 0x5c, 0x83, 0x00, 0x8a, 0x00, 0x31, 0x86, 0x6f, 0x1e, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, - 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, 0x7c, 0x83, 0x00, 0x0a, 0x80, 0x32, - 0x86, 0xef, 0x00, 0x00, 0x00, 0x84, 0xa4, 0x82, 0x00, 0x02, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, - 0x30, 0x82, 0xef, 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x84, 0xe7, 0x80, 0x20, 0x88, 0xe7, 0x00, 0x42, 0x86, 0x67, - 0x80, 0x31, 0x86, 0x67, 0x80, 0x41, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, - 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x07, 0x00, 0x7c, 0xa3, 0x80, 0x31, - 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xdc, 0x83, 0x00, 0x0a, 0x80, 0x21, 0x8a, 0xe7, 0x80, 0x52, 0x86, 0x67, 0x0f, - 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xf4, 0x83, 0x00, 0x0a, 0x80, 0x51, 0x84, 0xe7, - 0x00, 0x21, 0x86, 0x67, 0x0f, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x0c, 0x84, 0x00, - 0x0a, 0x80, 0x51, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x22, 0x8a, 0x67, 0x80, 0x52, - 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x30, 0x84, 0x00, 0x0a, 0x80, - 0x51, 0x84, 0xe7, 0x00, 0x21, 0x86, 0x67, 0x63, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, - 0x48, 0x84, 0x00, 0x0a, 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, - 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x60, 0x84, 0x00, 0x0a, 0x80, 0x32, 0x84, 0xe7, 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, - 0x00, 0x02, 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x30, 0x86, 0xe7, 0x80, 0x31, 0x86, 0x67, 0x80, - 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x00, 0x32, 0x82, 0x67, 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, 0x00, 0x02, - 0x00, 0x21, 0x80, 0x67, 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, - 0xe7, 0x00, 0x00, 0x80, 0x67, 0x00, 0x21, 0x84, 0xe7, 0x80, 0x20, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x32, - 0x48, 0x45, 0x00, 0x22, 0x86, 0x67, 0x00, 0x21, 0x88, 0xe7, 0x80, 0x40, 0x88, 0xe8, 0xdc, 0x84, 0x00, 0x8a, 0x00, - 0x20, 0x42, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x30, 0x42, 0x63, 0x00, 0x00, 0x00, 0x84, 0x00, 0x90, 0x42, 0x63, - 0x74, 0x84, 0x00, 0x82, 0x80, 0x70, 0x8e, 0xe7, 0x80, 0x80, 0x90, 0xe7, 0x01, 0x00, 0x42, 0x23, 0x80, 0x70, 0x8e, - 0xe2, 0x00, 0x80, 0x10, 0xeb, 0x80, 0x83, 0x90, 0xe4, 0x00, 0x80, 0x10, 0xed, 0x00, 0x80, 0x10, 0xf9, 0x00, 0x00, - 0x00, 0x84, 0x00, 0xc0, 0x60, 0x63, 0x00, 0x00, 0x21, 0x63, 0x24, 0x85, 0x00, 0x8c, 0x00, 0x00, 0x6c, 0xa3, 0x2c, - 0x85, 0x00, 0x18, 0x01, 0x00, 0x6c, 0x23, 0x2c, 0x85, 0x00, 0x18, 0x00, 0x00, 0x21, 0x65, 0x00, 0x00, 0x59, 0x63, - 0x00, 0x08, 0xa1, 0xe7, 0x01, 0x00, 0x42, 0x23, 0x80, 0x00, 0xa9, 0xfd, 0x00, 0x03, 0xa1, 0x67, 0x80, 0x00, 0xab, - 0x7b, 0x80, 0x5a, 0xa5, 0x67, 0x80, 0x2a, 0xa5, 0xe7, 0x00, 0x2a, 0xa7, 0xe7, 0x00, 0x29, 0xa5, 0x67, 0x80, 0x2a, - 0xa5, 0xe7, 0x00, 0x2a, 0x83, 0xe7, 0x00, 0x10, 0x60, 0xe3, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0xa4, 0x67, 0x00, - 0x29, 0xa5, 0x67, 0x00, 0x28, 0xa5, 0xe7, 0x80, 0x29, 0xa5, 0xe7, 0x00, 0x29, 0xa1, 0xe7, 0x80, 0x0a, 0xa1, 0xe7, - 0x00, 0x32, 0x42, 0x45, 0x80, 0x20, 0xa3, 0xe7, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x0a, 0xbd, 0xe8, 0x9c, 0x85, 0x00, - 0x8a, 0x00, 0x20, 0x41, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x7c, 0x23, 0x00, 0xea, 0xa9, 0xfd, 0x00, 0x0a, - 0xbd, 0xe8, 0xb4, 0x85, 0x00, 0x8a, 0x00, 0x10, 0x41, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x10, 0x40, 0x28, 0x10, - 0x86, 0x00, 0x88, 0x00, 0x00, 0x42, 0xa3, 0x00, 0xe0, 0xbd, 0x68, 0xcc, 0x85, 0x00, 0x8a, 0x01, 0x10, 0x82, 0x24, - 0x01, 0x60, 0x41, 0xa8, 0xd8, 0x85, 0x00, 0x8a, 0x02, 0x10, 0x82, 0x24, 0x03, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, - 0x88, 0x00, 0x00, 0x46, 0x23, 0x00, 0x30, 0x86, 0xfd, 0x01, 0x00, 0x7c, 0xa3, 0x00, 0x0f, 0x82, 0xe2, 0x00, 0x1b, - 0x40, 0x68, 0x00, 0x86, 0x00, 0x8a, 0x00, 0x00, 0x56, 0x63, 0x08, 0x86, 0x00, 0x18, 0x00, 0x30, 0x56, 0x63, 0x08, - 0x86, 0x00, 0x18, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x00, 0x84, 0xff, 0x0f, 0x42, 0xa3, 0x00, 0x00, 0x00, 0x84, - 0x80, 0x83, 0x80, 0xfd, 0x80, 0xc5, 0x82, 0xfd, 0x80, 0x00, 0x80, 0xe7, 0x80, 0x83, 0x82, 0x7b, 0x80, 0xc5, 0x84, - 0xfb, 0x00, 0x11, 0x82, 0xe7, 0x00, 0xa7, 0x84, 0x67, 0x00, 0x23, 0x84, 0x67, 0x00, 0x21, 0x84, 0x7b, 0x80, 0x96, - 0x86, 0xe7, 0x80, 0x31, 0x86, 0xfb, 0x00, 0x10, 0x88, 0xfd, 0x00, 0x10, 0x80, 0x7b, 0x00, 0x31, 0x82, 0xfd, 0x00, - 0x31, 0x84, 0xfb, 0x80, 0x40, 0x96, 0xe7, 0x00, 0x40, 0x9c, 0x67, 0x00, 0x20, 0x98, 0xe7, 0x80, 0x20, 0x9a, 0xe7, - 0x00, 0x00, 0x00, 0x84, 0x80, 0x73, 0x80, 0x67, 0x00, 0x84, 0x82, 0xe7, 0x80, 0x94, 0x84, 0xe7, 0x00, 0x21, 0x84, - 0x7b, 0x80, 0x00, 0x86, 0x7b, 0x00, 0x74, 0x88, 0x7b, 0x00, 0x42, 0x88, 0xe7, 0x00, 0x32, 0x88, 0xfd, 0x80, 0x00, - 0x80, 0x7d, 0x00, 0x20, 0x82, 0xfb, 0x80, 0x40, 0x8e, 0xe7, 0x80, 0x00, 0x92, 0xe7, 0x80, 0x01, 0x90, 0xe7, 0x80, - 0x41, 0x94, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x4e, 0xa3, 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, 0xa3, - 0x00, 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, - 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, - 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0xb8, - 0x86, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x56, 0xc9, 0x20, 0x05, 0x58, 0xc9, 0x40, 0x05, 0x5a, 0x49, - 0x00, 0x00, 0x4e, 0xa3, 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, - 0xa3, 0x00, 0x00, 0xde, 0xf3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, - 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, - 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, - 0x14, 0x87, 0x00, 0x0a, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xb0, 0x4e, - 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, 0x68, 0x86, - 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x01, - 0xe0, 0x7d, 0x24, 0x50, 0x87, 0x00, 0x0a, 0x00, 0x00, 0x7c, 0x23, 0x80, 0xe3, 0x8f, 0xfd, 0x00, 0xe5, 0x95, 0xfd, - 0x18, 0x86, 0x00, 0x02, 0x80, 0xe3, 0x8f, 0xfd, 0x00, 0xe5, 0x95, 0xfd, 0x00, 0x05, 0x40, 0x45, 0x20, 0x05, 0x42, - 0x45, 0x40, 0x05, 0x44, 0x45, 0x80, 0x06, 0x80, 0xe7, 0x80, 0x16, 0x82, 0xe7, 0x00, 0xb1, 0x96, 0xe7, 0x00, 0xc1, - 0x98, 0xe7, 0x80, 0x05, 0xbc, 0xe8, 0xd4, 0x87, 0x00, 0x0a, 0x00, 0x16, 0xbc, 0xe8, 0xd4, 0x87, 0x00, 0x0a, 0x00, - 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x40, 0x31, 0x7e, 0xc5, - 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xae, 0x24, 0x80, 0x5b, 0xab, - 0x67, 0x00, 0x5b, 0xb1, 0x67, 0x80, 0x6b, 0xad, 0x67, 0x98, 0x96, 0x00, 0x02, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x00, - 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0x02, 0x56, 0x49, 0x20, - 0x02, 0x58, 0x49, 0x40, 0x02, 0x5a, 0xc9, 0x60, 0x02, 0x5c, 0x49, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, - 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0x02, 0x56, 0x45, 0x20, 0x02, 0x58, - 0x45, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, 0x45, 0x00, 0x02, 0x4e, 0x49, 0x20, 0x02, 0x50, 0xc9, 0x40, 0x02, - 0x52, 0x49, 0x60, 0x02, 0x54, 0xc9, 0x00, 0x50, 0x4f, 0xe3, 0x00, 0x60, 0x51, 0xe3, 0x00, 0x70, 0x53, 0xe3, 0x00, - 0x80, 0x55, 0xe3, 0x00, 0x00, 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, 0x00, 0x07, 0x9c, 0xfd, 0x18, 0x86, 0x00, 0x02, - 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, - 0xc5, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, - 0x00, 0x0a, 0x00, 0x02, 0x56, 0x45, 0x20, 0x02, 0x58, 0x45, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, 0x45, 0x18, - 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0x00, 0xe0, 0x54, 0x63, - 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, 0x74, 0x84, 0x00, 0x82, 0x80, 0xb0, 0xaa, - 0xe7, 0x80, 0xc0, 0xac, 0x67, 0x80, 0x5a, 0x83, 0xe7, 0x00, 0x6b, 0x85, 0xe7, 0x80, 0x20, 0x86, 0xfd, 0x00, 0x11, - 0x88, 0xe7, 0x00, 0x43, 0x88, 0x67, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x40, 0x88, 0xfb, 0x00, 0x32, 0x80, 0xe8, 0x08, - 0x89, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, - 0x80, 0x73, 0x80, 0x67, 0x00, 0x84, 0x82, 0xe7, 0x80, 0x94, 0x84, 0xe7, 0x00, 0x10, 0x86, 0x7d, 0x00, 0x31, 0x86, - 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x03, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x01, 0x80, 0x7b, 0x00, 0x30, - 0x86, 0x68, 0x48, 0x89, 0x00, 0x8a, 0x00, 0x74, 0x80, 0x67, 0x00, 0x95, 0x86, 0x67, 0x00, 0x30, 0x86, 0x68, 0x00, - 0x00, 0x00, 0x84, 0x00, 0x96, 0x80, 0xef, 0x80, 0xa6, 0x82, 0xef, 0x00, 0xb7, 0x84, 0x6f, 0x00, 0x95, 0x86, 0xfb, - 0x80, 0xc6, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x6f, 0x80, 0x00, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x7d, 0x80, 0xa5, 0x88, - 0xfb, 0x00, 0xd7, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xef, 0x00, 0x11, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xfd, 0x80, 0x95, - 0x8a, 0x7b, 0x00, 0xc7, 0x8c, 0x7b, 0x00, 0x53, 0x8a, 0xef, 0x00, 0x01, 0x8c, 0x7b, 0x00, 0x53, 0x8c, 0xfd, 0x00, - 0x81, 0x8e, 0x6f, 0x80, 0x63, 0x8a, 0x7d, 0x80, 0x52, 0x8e, 0x7b, 0x80, 0x53, 0x8a, 0x7b, 0x80, 0x12, 0x8e, 0xfd, - 0x80, 0x12, 0x8a, 0x7b, 0x00, 0x83, 0x8c, 0x6f, 0x00, 0x21, 0x82, 0x7b, 0x00, 0x11, 0x84, 0x7b, 0x00, 0x61, 0x8c, - 0x7d, 0x00, 0x60, 0x8c, 0xfd, 0x00, 0x63, 0x82, 0x7b, 0x00, 0x13, 0x8c, 0x7b, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, - 0x80, 0x7b, 0x00, 0x01, 0x80, 0x7d, 0x00, 0x43, 0x82, 0xef, 0x00, 0x03, 0x84, 0x6f, 0x80, 0x53, 0x8c, 0x6f, 0x00, - 0x61, 0x9a, 0xfb, 0x80, 0x32, 0x8a, 0xef, 0x80, 0x50, 0x98, 0x7d, 0x80, 0x43, 0x8e, 0x6f, 0x00, 0x30, 0x82, 0x6f, - 0x80, 0x70, 0x9c, 0x7b, 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0xef, 0x00, 0xa5, 0x82, 0x6f, 0x80, 0xb5, 0x84, - 0x6f, 0x00, 0x95, 0x86, 0xef, 0x80, 0x31, 0x86, 0xfb, 0x80, 0x95, 0x8e, 0xef, 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x81, - 0x8c, 0xef, 0x80, 0x63, 0x8c, 0x7d, 0x00, 0x63, 0x8a, 0xfb, 0x00, 0x53, 0x8c, 0xfb, 0x00, 0x13, 0x8a, 0x7d, 0x00, - 0x13, 0x8c, 0x7b, 0x00, 0x53, 0x8c, 0xef, 0x80, 0x51, 0x8a, 0xef, 0x00, 0x21, 0x86, 0xfb, 0x80, 0x21, 0x84, 0xfb, - 0x80, 0x83, 0x8e, 0x6f, 0x00, 0x71, 0x8e, 0x7d, 0x00, 0x70, 0x8e, 0xfd, 0x80, 0x73, 0x86, 0xfb, 0x80, 0x71, 0x8e, - 0xfb, 0x00, 0x00, 0x86, 0xfb, 0x00, 0x30, 0x80, 0xfb, 0x00, 0x01, 0x80, 0x7d, 0x80, 0x03, 0x80, 0x6f, 0x00, 0x60, - 0x8c, 0xfb, 0x80, 0xa5, 0x80, 0x6f, 0x00, 0x00, 0x80, 0xfb, 0x80, 0x03, 0x8e, 0xef, 0x80, 0x53, 0x8a, 0x7d, 0x80, - 0x00, 0x8e, 0xef, 0x80, 0x73, 0x8e, 0x7b, 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x50, 0x52, 0xe3, 0x00, 0x60, 0x54, 0xe3, - 0x00, 0x70, 0x56, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, 0x00, 0x56, - 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, - 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, - 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xa8, 0x8a, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, - 0x00, 0x05, 0x58, 0x49, 0x20, 0x05, 0x5a, 0x49, 0x40, 0x05, 0x5c, 0x49, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, - 0xa3, 0x00, 0x00, 0x56, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xde, 0xf3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xd0, - 0x3b, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, - 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, - 0xf8, 0x8a, 0x00, 0x0a, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, - 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, - 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x2c, 0x8b, 0x00, 0x8a, 0x00, - 0x00, 0x7c, 0x23, 0x00, 0xe5, 0x95, 0xfd, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe5, 0x95, 0xfd, 0x00, 0x05, 0x40, 0x45, - 0x20, 0x05, 0x42, 0x45, 0x40, 0x05, 0x44, 0x45, 0x00, 0x07, 0x80, 0x6f, 0x00, 0x17, 0x82, 0x6f, 0x00, 0xc1, 0x98, - 0x6f, 0x00, 0xd1, 0x9a, 0x6f, 0x00, 0x06, 0xbc, 0x68, 0xa0, 0x8b, 0x00, 0x0a, 0x80, 0x16, 0xbc, 0x68, 0xa0, 0x8b, - 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, - 0x30, 0x7e, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xb0, 0x24, - 0x00, 0x6c, 0xad, 0xef, 0x00, 0x7c, 0xaf, 0xef, 0xc8, 0x97, 0x00, 0x82, 0x00, 0x10, 0x53, 0xe3, 0x00, 0x20, 0x55, - 0xe3, 0x00, 0x30, 0x57, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, - 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0x80, 0x30, 0x50, 0x45, 0x00, 0x10, 0x59, 0xe3, 0x00, - 0x20, 0x5b, 0x63, 0x00, 0x30, 0x5d, 0xe3, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x94, 0x8c, 0x00, 0x0a, - 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0x00, 0x80, 0x68, 0x00, 0x60, 0x53, 0x6f, 0x00, 0x70, 0x55, - 0xef, 0x00, 0x80, 0x57, 0x6f, 0x00, 0x10, 0x59, 0xe3, 0x00, 0x20, 0x5b, 0x63, 0x00, 0x30, 0x5d, 0xe3, 0x80, 0x06, - 0x9a, 0xfd, 0x4c, 0x89, 0x00, 0x82, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x00, - 0x30, 0x7e, 0xc5, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x94, 0x8c, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, - 0x94, 0x8c, 0x00, 0x0a, 0x00, 0x60, 0x59, 0x63, 0x00, 0x70, 0x5b, 0x63, 0x00, 0x80, 0x5d, 0x63, 0x4c, 0x89, 0x00, - 0x82, 0x00, 0xc0, 0x52, 0xe3, 0x00, 0xd0, 0x54, 0x63, 0x00, 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, - 0x00, 0x0a, 0x00, 0xe0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0xc0, 0xac, 0xef, 0x80, 0xd0, 0xae, 0xef, 0x00, - 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x30, 0x40, 0x45, - 0x80, 0x30, 0x42, 0x45, 0x00, 0xa5, 0x86, 0xef, 0x80, 0x35, 0x86, 0x6f, 0x80, 0x94, 0x84, 0x6f, 0x80, 0x24, 0x84, - 0xef, 0x80, 0xb5, 0x88, 0x6f, 0x80, 0x45, 0x8a, 0xef, 0x80, 0x04, 0x80, 0xef, 0x00, 0x02, 0x80, 0x6f, 0x80, 0x12, - 0x82, 0xef, 0x80, 0x00, 0x80, 0x7b, 0x00, 0x01, 0x80, 0x7b, 0x80, 0x01, 0x80, 0x68, 0x00, 0x00, 0x00, 0x84, 0x60, - 0x32, 0x40, 0xc5, 0x00, 0x08, 0x80, 0xe7, 0x00, 0x08, 0x83, 0xe7, 0x00, 0x10, 0x82, 0xfb, 0x01, 0x00, 0x40, 0xa3, - 0x00, 0x10, 0x82, 0xfb, 0x00, 0x18, 0x82, 0xe7, 0x98, 0x84, 0x00, 0x02, 0x00, 0x10, 0x62, 0x63, 0x01, 0x00, 0x44, - 0x23, 0x00, 0x20, 0x84, 0x70, 0x00, 0x01, 0x84, 0x62, 0x00, 0x00, 0x00, 0x84, 0xc0, 0x32, 0x68, 0xc5, 0xe0, 0x32, - 0x6a, 0xc5, 0xa0, 0x32, 0x6c, 0x45, 0x00, 0x64, 0x8b, 0x67, 0x80, 0x53, 0x8a, 0x7b, 0x00, 0x66, 0x8d, 0xe7, 0x80, - 0x65, 0x8c, 0x7b, 0x00, 0x53, 0x80, 0x67, 0x80, 0x96, 0x82, 0x67, 0x00, 0x86, 0x84, 0x67, 0x80, 0x54, 0x86, 0xfb, - 0x80, 0x66, 0x88, 0xfb, 0x00, 0x32, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x7d, 0x00, 0x54, 0x88, - 0xfb, 0x00, 0x66, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0x67, 0x00, 0x01, 0x8a, 0x7b, 0x80, 0x42, 0x88, 0xfd, 0x00, 0x94, - 0x8a, 0x7b, 0x00, 0xd6, 0x96, 0xfb, 0x80, 0x55, 0x8a, 0xe7, 0x00, 0x11, 0x96, 0x7b, 0x80, 0x55, 0x8a, 0x7d, 0x00, - 0x42, 0x99, 0xe7, 0x00, 0x51, 0x97, 0xe7, 0x00, 0xb6, 0x98, 0x7b, 0x00, 0x16, 0x96, 0xfd, 0x00, 0x16, 0x98, 0x7b, - 0x00, 0xb6, 0x9a, 0x67, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x82, 0xfb, 0x00, 0x41, 0x85, 0x67, 0x00, 0x52, 0x89, - 0xe7, 0x00, 0x11, 0x82, 0x7b, 0x00, 0x01, 0x84, 0xfd, 0x00, 0x41, 0x85, 0x67, 0x00, 0x41, 0x88, 0x7b, 0x00, 0x12, - 0x80, 0x67, 0x00, 0xd0, 0x9a, 0xfb, 0x00, 0x52, 0x80, 0xe7, 0x80, 0x35, 0x96, 0x67, 0x00, 0xb0, 0x96, 0xfd, 0x80, - 0x30, 0x80, 0xe7, 0x00, 0x56, 0x98, 0x67, 0x00, 0xc0, 0x98, 0xfb, 0x00, 0x66, 0xad, 0x67, 0x00, 0xbb, 0x96, 0x7d, - 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0x67, 0x00, 0x04, 0x80, 0xe7, 0x60, 0x32, 0x42, 0x45, 0x80, 0x13, 0x82, - 0xe7, 0x00, 0x14, 0x82, 0x7b, 0x00, 0x14, 0x82, 0xe7, 0x80, 0x73, 0x84, 0xe7, 0x00, 0x11, 0x82, 0x7b, 0x80, 0x13, - 0x82, 0xe7, 0x80, 0x00, 0x80, 0xe8, 0x00, 0x00, 0x00, 0x84, 0x00, 0x74, 0x80, 0xfb, 0x00, 0x95, 0x82, 0x7d, 0x00, - 0x10, 0x82, 0x67, 0x00, 0x74, 0x80, 0xfd, 0x00, 0x95, 0x84, 0x7b, 0x00, 0x20, 0x84, 0x67, 0x00, 0x11, 0x86, 0xfb, - 0x80, 0x31, 0x86, 0x67, 0x00, 0x11, 0x88, 0x7d, 0x00, 0x42, 0x88, 0xe7, 0x00, 0x36, 0x92, 0x67, 0x00, 0xb2, 0x94, - 0x67, 0x00, 0x00, 0x00, 0x84, 0x00, 0x74, 0x82, 0x7b, 0x80, 0x10, 0x82, 0xe7, 0x00, 0x74, 0x84, 0x7d, 0x00, 0x21, - 0x84, 0xe7, 0x00, 0x11, 0x8e, 0xe7, 0x00, 0x11, 0x82, 0x7d, 0x80, 0x60, 0x86, 0xe7, 0x00, 0x31, 0x86, 0x7b, 0x80, - 0x11, 0x90, 0x67, 0x00, 0x00, 0x00, 0x84, 0x80, 0x32, 0x4c, 0x45, 0x00, 0xb0, 0x52, 0x63, 0x00, 0xc0, 0x54, 0xe3, - 0x01, 0x00, 0x4e, 0x23, 0x00, 0x00, 0x50, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xf6, 0xf3, 0x00, 0xb0, 0x37, - 0xeb, 0x00, 0xd0, 0x3b, 0xeb, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, - 0x00, 0x02, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x78, 0x8e, 0x00, 0x0a, 0x00, - 0x01, 0x7c, 0xa3, 0x00, 0xb0, 0x37, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, - 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, 0x00, 0x02, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, - 0x24, 0xa4, 0x8e, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x76, 0x80, 0xe7, 0x00, 0xb4, 0x82, 0xe7, 0x00, 0x86, - 0x84, 0x67, 0x60, 0x32, 0x4c, 0xc5, 0x00, 0x63, 0x86, 0xfb, 0x00, 0x31, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, 0x80, - 0x41, 0x88, 0xfb, 0x80, 0xb3, 0x8a, 0x67, 0x00, 0x51, 0x8a, 0x7b, 0x80, 0x42, 0x88, 0x67, 0x00, 0x31, 0x86, 0xe7, - 0x80, 0x41, 0x88, 0xfd, 0x00, 0x45, 0x88, 0x67, 0x80, 0x00, 0x82, 0xfd, 0x80, 0x10, 0x82, 0xe7, 0x80, 0x14, 0x82, - 0x67, 0x80, 0x40, 0x92, 0xfd, 0x80, 0xd6, 0x86, 0xfb, 0x00, 0x34, 0x86, 0xe7, 0x00, 0x35, 0x86, 0x67, 0x00, 0x30, - 0x8e, 0xe7, 0x00, 0x31, 0x90, 0x67, 0x00, 0x00, 0x00, 0x84, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, - 0x00, 0x42, 0xa3, 0x00, 0xe0, 0x45, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x47, 0xe5, 0x20, 0xe0, 0x7d, 0x22, - 0x00, 0xe0, 0x49, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4b, 0xe5, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4d, - 0xe5, 0x00, 0x20, 0x04, 0xf9, 0x00, 0x30, 0x06, 0xf9, 0x00, 0x40, 0x08, 0xf9, 0x00, 0x50, 0x0a, 0xf9, 0x00, 0x60, - 0x0c, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x11, 0x02, 0xfd, 0x80, 0x21, 0x04, 0x7d, 0x00, 0x32, 0x06, 0xfd, 0x80, - 0x42, 0x08, 0x7d, 0x00, 0x53, 0x0a, 0x7d, 0x00, 0x60, 0x0c, 0xf3, 0x00, 0x00, 0x00, 0x84, 0x58, 0x81, 0x00, 0x02, - 0x00, 0x00, 0x48, 0x22, 0x00, 0x40, 0x44, 0xe5, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x20, 0x2c, 0x63, 0x01, 0x60, 0x6b, - 0x22, 0x00, 0x00, 0x42, 0xa3, 0x04, 0x54, 0xe1, 0x35, 0x88, 0x90, 0x00, 0x9c, 0xff, 0x00, 0x40, 0x23, 0x00, 0x00, - 0xa3, 0xe2, 0x02, 0x10, 0x41, 0x28, 0x94, 0x90, 0x00, 0x8a, 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0x21, 0xf5, 0x00, - 0x00, 0x21, 0xf5, 0x00, 0x00, 0xa3, 0xe2, 0x00, 0x20, 0x84, 0x62, 0x00, 0x11, 0x41, 0xe8, 0xa0, 0x90, 0x00, 0x0a, - 0x05, 0x54, 0xf3, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x00, 0x03, 0x72, 0xc9, 0x05, 0x54, 0xc1, 0x39, 0x88, 0x90, 0x00, - 0x9c, 0x00, 0x60, 0x6b, 0xe3, 0x00, 0x54, 0xf5, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x01, 0x54, 0xef, 0xb5, 0x88, 0x90, - 0x00, 0x9c, 0x02, 0x54, 0xfb, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x03, 0x54, 0xfd, 0x35, 0x88, 0x90, 0x00, 0x9c, 0x05, - 0x54, 0xc1, 0x39, 0x88, 0x90, 0x00, 0x9c, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, - 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, 0x00, 0xd0, 0xbb, 0xfb, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x71, 0xaf, - 0xe8, 0x00, 0xe1, 0xbd, 0xe8, 0x00, 0x7f, 0xa9, 0x68, 0xe0, 0x03, 0x74, 0x49, 0x00, 0x04, 0x7a, 0xc9, 0xa0, 0x00, - 0x60, 0xc5, 0x00, 0x00, 0x21, 0xf9, 0xc0, 0x00, 0x62, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, - 0x81, 0x00, 0x98, 0x05, 0x54, 0xc1, 0x39, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x12, 0x00, 0x44, 0xa3, - 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x00, 0x84, 0x6c, 0x90, 0x00, 0x82, 0xf2, 0x00, 0x40, - 0xa3, 0x94, 0x81, 0x00, 0x98, 0x6c, 0x90, 0x00, 0x82, 0xf4, 0x00, 0x40, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x6c, 0x90, - 0x00, 0x82, 0xf6, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x00, 0x00, 0xce, 0x73, 0x00, 0x00, 0xd0, 0x73, 0x00, - 0x00, 0xd2, 0xf3, 0x00, 0x00, 0xd4, 0xf3, 0x00, 0x70, 0xc0, 0xe3, 0x0c, 0x40, 0xc1, 0xa5, 0x4c, 0xa3, 0x00, 0x02, - 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x30, 0x8f, 0x00, 0x02, 0x08, 0x00, 0x56, - 0x23, 0x12, 0x00, 0x58, 0x23, 0x78, 0x8f, 0x00, 0x02, 0x01, 0xc0, 0x58, 0x24, 0xe0, 0x90, 0x00, 0x8a, 0x00, 0x10, - 0xc0, 0xe9, 0x01, 0xb0, 0x56, 0x24, 0xdc, 0x90, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, - 0x81, 0x00, 0x98, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, 0x30, 0x8f, 0x00, 0x02, 0x80, 0x00, 0x5e, 0xa3, - 0x00, 0xf0, 0x1e, 0xf3, 0x00, 0xf0, 0x1e, 0xf3, 0x00, 0xf0, 0x1e, 0xf3, 0x12, 0xb0, 0x56, 0xa4, 0x80, 0xb7, 0xa0, - 0x62, 0x44, 0x91, 0x00, 0x8a, 0x12, 0x00, 0x58, 0x23, 0x78, 0x8f, 0x00, 0x02, 0x01, 0xc0, 0x58, 0x24, 0x30, 0x91, - 0x00, 0x8a, 0x00, 0x10, 0xc0, 0xe9, 0x20, 0x91, 0x00, 0x18, 0x12, 0xb0, 0x56, 0xa2, 0x88, 0x91, 0x00, 0x08, 0x12, - 0x00, 0x58, 0x23, 0x80, 0xc5, 0x58, 0xe4, 0x78, 0x8f, 0x00, 0x02, 0x01, 0xb0, 0x56, 0x24, 0x54, 0x91, 0x00, 0x0a, - 0x01, 0xc0, 0x40, 0x28, 0x9c, 0x91, 0x00, 0x08, 0x04, 0x00, 0x44, 0x23, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x11, 0x02, - 0xfd, 0x00, 0x20, 0x04, 0xf3, 0x01, 0xc0, 0x58, 0x24, 0x70, 0x91, 0x00, 0x0a, 0x80, 0x10, 0x82, 0x24, 0xac, 0x91, - 0x00, 0x98, 0x00, 0x00, 0x42, 0xa3, 0x8a, 0x00, 0x46, 0xa3, 0x80, 0x11, 0xc2, 0xe2, 0x80, 0x10, 0x82, 0x24, 0xac, - 0x91, 0x00, 0x98, 0x84, 0x00, 0x44, 0xa3, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x11, 0x02, 0xfd, 0xac, 0x91, 0x00, 0x98, - 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf6, 0x71, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x70, 0xce, 0xeb, 0x00, 0x70, 0xd2, - 0x6b, 0x00, 0x70, 0xc0, 0xe3, 0x0c, 0xb0, 0xc1, 0xa5, 0x04, 0x00, 0x42, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x10, - 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xd0, 0x91, 0x00, 0x0a, 0x80, 0x10, 0x82, 0x24, 0x00, 0x10, 0xc0, 0xe9, 0x00, - 0x00, 0xf8, 0xf1, 0x60, 0x31, 0x7e, 0x45, 0x80, 0xcd, 0xb7, 0xf9, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, - 0x94, 0x81, 0x00, 0x98, 0x40, 0x31, 0x7e, 0xc5, 0xc0, 0x31, 0x6a, 0x45, 0xe0, 0x31, 0x6c, 0xc5, 0xdc, 0x87, 0x00, - 0x02, 0x01, 0x00, 0x42, 0x23, 0x80, 0x50, 0xab, 0xe2, 0x00, 0x50, 0x2b, 0xed, 0x80, 0x6a, 0xad, 0xe4, 0x00, 0x60, - 0x2d, 0xf9, 0x20, 0x03, 0x6c, 0x49, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x58, 0x81, 0x00, 0x02, 0x00, - 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x6b, 0x65, 0x00, 0x50, 0x2b, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x69, 0xe5, - 0x00, 0x40, 0x29, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x67, 0x65, 0x00, 0x30, 0x27, 0xf9, 0x20, 0xe0, 0x7d, - 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x20, 0x25, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x4c, 0x23, 0x00, 0x60, - 0x8a, 0x70, 0x60, 0xb0, 0x92, 0x22, 0x1f, 0xb0, 0x90, 0x22, 0x20, 0x00, 0x4e, 0x23, 0x00, 0x74, 0x50, 0xe4, 0x00, - 0x80, 0x4e, 0xe3, 0x00, 0x70, 0x0e, 0x63, 0x00, 0x70, 0x0e, 0x63, 0x00, 0x70, 0x0e, 0x63, 0x01, 0x70, 0x4e, 0x24, - 0x00, 0x53, 0x0a, 0x7d, 0x01, 0x80, 0x50, 0x24, 0x90, 0x92, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, 0x70, 0x81, 0x00, - 0x02, 0x00, 0x00, 0x56, 0x63, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x67, 0x65, 0x20, 0xe0, - 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x20, 0x25, 0xf9, 0x00, 0x03, 0x68, 0x45, 0x20, - 0x03, 0x6a, 0x45, 0x40, 0xb0, 0x7a, 0xa2, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, - 0x00, 0x00, 0xc0, 0x2d, 0x64, 0x92, 0x00, 0x82, 0x20, 0x90, 0x40, 0x28, 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, - 0xe3, 0xac, 0x93, 0x00, 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x67, 0x65, 0x20, 0xe0, - 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x20, 0x25, 0xf9, 0x00, 0x03, 0x68, 0x45, 0x20, - 0x03, 0x6a, 0x45, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x20, 0xe1, 0x6b, 0x80, 0x00, 0x7a, 0xa3, 0x00, 0x00, 0x40, 0x23, - 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x2c, 0x92, 0x00, 0x82, 0x00, 0x20, 0xe1, 0x6b, 0x80, 0xd0, 0x7b, - 0x22, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, - 0x56, 0x63, 0x80, 0xd5, 0x7b, 0xe2, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x2c, - 0x92, 0x00, 0x82, 0x80, 0xb0, 0x40, 0xa8, 0xdc, 0x93, 0x00, 0x08, 0x64, 0x92, 0x00, 0x82, 0x60, 0x90, 0x40, 0xa8, - 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, 0xe3, 0x40, 0x90, 0x40, 0x28, 0xac, 0x93, 0x00, 0x88, 0x00, 0x00, 0x66, - 0xa3, 0x20, 0x90, 0x40, 0x28, 0xa0, 0x93, 0x00, 0x88, 0x00, 0x00, 0x68, 0x23, 0x80, 0x52, 0xab, 0x62, 0x80, 0x53, - 0xeb, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x42, 0xa9, 0x62, 0x80, 0x43, 0xe9, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, - 0x32, 0xa7, 0x62, 0x80, 0x33, 0xe7, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x22, 0xa5, 0x62, 0x80, 0x23, 0xe5, 0x62, - 0x10, 0xb0, 0x90, 0x22, 0xd0, 0x93, 0x00, 0x8a, 0x80, 0x2e, 0xa5, 0x64, 0xf8, 0x93, 0x00, 0x98, 0x00, 0x20, 0xe1, - 0x6b, 0x00, 0x00, 0x6a, 0xa3, 0xec, 0x93, 0x00, 0x98, 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x6a, 0xa3, 0xff, 0x00, - 0x4e, 0xa3, 0x80, 0x53, 0xeb, 0x62, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x66, 0xa3, 0x00, 0xd0, 0x65, 0xe3, 0x60, - 0x31, 0x7e, 0x45, 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x21, 0xf9, 0x00, 0x10, 0x23, 0xf9, 0x80, 0x08, 0xb3, 0x79, - 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x60, 0x31, 0x7e, 0x45, 0xe0, 0x03, 0x74, - 0x45, 0x00, 0x04, 0x44, 0x45, 0x80, 0xac, 0x83, 0xff, 0x80, 0x2c, 0x84, 0xff, 0x80, 0xb0, 0x87, 0x7b, 0x00, 0x31, - 0x86, 0x7b, 0x40, 0x03, 0x46, 0xc9, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0x03, 0x58, 0x45, 0x00, - 0xc0, 0x18, 0xf9, 0x10, 0x85, 0x00, 0x82, 0x00, 0x10, 0xbc, 0x28, 0x10, 0x95, 0x00, 0x8a, 0x01, 0x00, 0x5a, 0x23, - 0x00, 0xb6, 0x9c, 0x67, 0x00, 0x90, 0x79, 0xe3, 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x4e, 0xc9, 0x80, 0x03, 0x50, - 0x49, 0xa0, 0x03, 0x52, 0x49, 0xc0, 0x03, 0x54, 0x49, 0x40, 0x03, 0x78, 0x45, 0xc0, 0x31, 0x56, 0x45, 0xe0, 0x31, - 0x58, 0x45, 0x01, 0x00, 0x5a, 0x23, 0x00, 0xb6, 0x9c, 0x67, 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x56, 0xc5, 0x80, - 0x03, 0x58, 0xc5, 0xa0, 0x03, 0x5a, 0xc5, 0xc0, 0x03, 0x5c, 0xc5, 0x00, 0x00, 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, - 0x00, 0x07, 0x9c, 0xfd, 0x18, 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, - 0x63, 0xe4, 0x84, 0x00, 0x82, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x20, 0x03, 0x48, 0x45, 0xff, 0x0f, - 0x7e, 0xa3, 0x00, 0xf0, 0x41, 0x28, 0x00, 0x82, 0x84, 0xe8, 0x18, 0x95, 0x00, 0x0a, 0x00, 0xf0, 0x41, 0x28, 0x00, - 0x82, 0x84, 0xe8, 0x18, 0x95, 0x00, 0x0a, 0xc3, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x10, 0x00, 0x7c, 0x22, - 0x40, 0x03, 0x4a, 0xc5, 0x00, 0x40, 0x08, 0xf9, 0x00, 0xe0, 0x49, 0x69, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4b, - 0xe9, 0x00, 0x00, 0x40, 0x23, 0x50, 0x00, 0x42, 0xa3, 0x2c, 0x95, 0x00, 0x98, 0x36, 0x00, 0x40, 0x23, 0x1c, 0x95, - 0x00, 0x98, 0x36, 0x00, 0x40, 0x23, 0x3c, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, 0x42, 0x23, 0x2c, - 0x95, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x94, 0x81, 0x00, 0x98, 0x00, 0x00, 0x8c, 0x67, - 0x00, 0x63, 0x8c, 0xfb, 0x01, 0x00, 0x7c, 0xa3, 0x00, 0x6f, 0x8e, 0x7b, 0x00, 0x70, 0xbc, 0x28, 0x6c, 0x96, 0x00, - 0x88, 0x60, 0x32, 0x50, 0x45, 0x00, 0x00, 0x7c, 0x23, 0x00, 0xe4, 0x93, 0x7d, 0x00, 0x83, 0x90, 0x67, 0x80, 0x73, - 0x94, 0x67, 0x80, 0xa3, 0x96, 0x67, 0x80, 0x84, 0x90, 0x67, 0x00, 0x85, 0x90, 0xfb, 0x80, 0x84, 0x90, 0x67, 0x80, - 0xb5, 0x98, 0x67, 0x00, 0xc6, 0x94, 0x67, 0x80, 0xc5, 0x98, 0xe7, 0x00, 0xc4, 0x98, 0xe7, 0x00, 0xa6, 0x94, 0x67, - 0x00, 0xa0, 0x42, 0x63, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x25, 0x9a, - 0x67, 0x00, 0xd6, 0x9a, 0x67, 0x00, 0x32, 0x7c, 0xc5, 0x00, 0xdf, 0x9c, 0x67, 0x80, 0xd6, 0x94, 0x67, 0x80, 0xa5, - 0x94, 0xe7, 0x00, 0xa4, 0x88, 0x68, 0xc0, 0x95, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, 0xc8, 0x95, 0x00, 0x98, 0x00, - 0xe0, 0x42, 0xe3, 0xc8, 0x95, 0x00, 0x98, 0x00, 0x93, 0x84, 0xe7, 0x00, 0xd0, 0x86, 0xe7, 0x01, 0xe0, 0x89, 0xa4, - 0x00, 0x32, 0x86, 0xe7, 0x00, 0x3f, 0x88, 0xe7, 0x00, 0x83, 0x8c, 0xe7, 0x80, 0x31, 0x94, 0x67, 0x80, 0xa5, 0x94, - 0xe7, 0x00, 0xa3, 0xbc, 0xfd, 0x00, 0xe0, 0xbd, 0xa8, 0xfc, 0x95, 0x00, 0x0a, 0x00, 0x30, 0x40, 0xe3, 0x04, 0x96, - 0x00, 0x98, 0x00, 0x40, 0x40, 0x63, 0x04, 0x96, 0x00, 0x98, 0x80, 0x10, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, - 0xa4, 0xbc, 0x7d, 0x00, 0xe0, 0xbd, 0xa8, 0x20, 0x96, 0x00, 0x8a, 0x00, 0x90, 0x46, 0xe3, 0x28, 0x96, 0x00, 0x18, - 0x00, 0x20, 0x46, 0x63, 0x28, 0x96, 0x00, 0x18, 0x38, 0x96, 0x00, 0x8a, 0x00, 0x10, 0x44, 0xe3, 0x01, 0x00, 0x7c, - 0xa3, 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, 0x44, 0x63, 0x00, 0x00, 0x7c, 0x23, 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, - 0x40, 0x23, 0x00, 0x01, 0x82, 0xfd, 0x01, 0x00, 0x50, 0x23, 0x00, 0x24, 0x8c, 0x62, 0x00, 0xe3, 0xbd, 0x68, 0x64, - 0x96, 0x00, 0x08, 0x00, 0x10, 0x56, 0xe3, 0x6c, 0x96, 0x00, 0x18, 0x00, 0x20, 0x56, 0xe3, 0x6c, 0x96, 0x00, 0x18, - 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, - 0x02, 0x00, 0x70, 0xbc, 0x28, 0x70, 0x96, 0x00, 0x08, 0x80, 0xb3, 0x9a, 0xe7, 0x00, 0x30, 0x56, 0x63, 0x00, 0x70, - 0x58, 0x63, 0x00, 0x00, 0x00, 0x84, 0x40, 0x31, 0x7e, 0xc5, 0x00, 0x05, 0x42, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0xb4, - 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, 0x02, 0x00, 0x70, 0xbc, 0x28, 0x98, 0x96, 0x00, 0x08, 0x00, 0x33, 0x7c, 0x45, - 0x00, 0x3f, 0x94, 0x67, 0x80, 0x75, 0x9a, 0xe7, 0x80, 0x33, 0x98, 0x7d, 0x80, 0x33, 0x9c, 0xfb, 0x00, 0xd7, 0x80, - 0x67, 0x00, 0x00, 0xbc, 0xa8, 0x98, 0x96, 0x00, 0x08, 0x00, 0xa7, 0x96, 0x67, 0x80, 0xc6, 0x98, 0xe7, 0x00, 0xb6, - 0x9c, 0x67, 0x00, 0xb0, 0x96, 0x67, 0x00, 0xc0, 0x98, 0x67, 0x00, 0x00, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x00, - 0x08, 0x8d, 0xef, 0x00, 0x06, 0x8f, 0xef, 0x80, 0x63, 0x8c, 0x6f, 0x00, 0x60, 0x42, 0x63, 0xa4, 0x82, 0x00, 0x02, - 0x00, 0x30, 0x52, 0xe3, 0x80, 0x93, 0x92, 0x6f, 0x00, 0x31, 0x40, 0xc5, 0x00, 0x90, 0x94, 0xef, 0x80, 0x94, 0x90, - 0x6f, 0x00, 0x88, 0x90, 0x6f, 0x00, 0x86, 0x80, 0xe8, 0x00, 0x90, 0x54, 0xef, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, - 0x68, 0xe3, 0x20, 0x31, 0x40, 0x45, 0x60, 0x30, 0x42, 0xc5, 0x80, 0x30, 0x44, 0x45, 0x00, 0x4a, 0x97, 0x6f, 0x80, - 0x05, 0x96, 0xef, 0x80, 0xb5, 0x98, 0xef, 0x80, 0xc5, 0x98, 0x7b, 0x01, 0x00, 0x48, 0x23, 0x00, 0xc2, 0x9a, 0xfb, - 0x80, 0x26, 0x9a, 0x6f, 0x00, 0x00, 0x48, 0xa3, 0x00, 0x46, 0x9c, 0xfd, 0x00, 0xc0, 0x80, 0xa8, 0x00, 0xe0, 0x40, - 0x6f, 0x00, 0x17, 0x9c, 0x6f, 0x80, 0xd6, 0x98, 0xef, 0x00, 0xe7, 0xa0, 0x6f, 0x00, 0x18, 0x9e, 0xef, 0x80, 0xc7, - 0x98, 0xfb, 0x80, 0xc6, 0x98, 0x6f, 0x00, 0x07, 0xa1, 0x6f, 0x00, 0x28, 0x9e, 0xef, 0x80, 0xc7, 0x98, 0xfb, 0x80, - 0xb6, 0xa2, 0xef, 0xf0, 0x96, 0x00, 0x82, 0x00, 0xba, 0xa4, 0x6f, 0x00, 0x25, 0xa5, 0xef, 0x00, 0xd0, 0x62, 0x6f, - 0x00, 0xa0, 0x64, 0xef, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x19, 0x82, 0xfd, 0x00, 0x49, 0x81, 0x68, 0x01, 0x00, 0x44, - 0x23, 0x00, 0x01, 0x80, 0xe2, 0x00, 0x10, 0x64, 0x6f, 0x00, 0x10, 0x64, 0x63, 0x00, 0x27, 0xa5, 0x6f, 0x00, 0xe0, - 0x66, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x42, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0xb4, 0xa3, 0x00, 0x82, 0x28, - 0x97, 0x00, 0x02, 0x00, 0x30, 0xbd, 0x28, 0xc8, 0x97, 0x00, 0x88, 0x00, 0x00, 0x00, 0x84, 0x20, 0x30, 0x7e, 0x45, - 0x60, 0x10, 0x40, 0x28, 0x18, 0x98, 0x00, 0x08, 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x66, 0xe5, 0x00, 0x30, 0x27, - 0xf9, 0x00, 0x00, 0x68, 0x23, 0x80, 0x49, 0xb9, 0x79, 0x80, 0xc9, 0x83, 0xe8, 0xb4, 0x99, 0x00, 0x0a, 0x00, 0xc0, - 0x83, 0xa8, 0xb4, 0x99, 0x00, 0x88, 0x2c, 0x98, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, 0x00, 0x00, 0xe8, 0xf3, 0x80, - 0x49, 0xb9, 0x79, 0x00, 0xc0, 0x83, 0xa8, 0xb4, 0x99, 0x00, 0x88, 0x00, 0x00, 0xc0, 0xf3, 0x00, 0x00, 0xc2, 0x73, - 0x00, 0x00, 0xc4, 0x73, 0x00, 0x00, 0xc6, 0xf3, 0x00, 0x00, 0xc0, 0x63, 0x0a, 0xc0, 0xc1, 0x25, 0x04, 0x00, 0x44, - 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x04, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x4c, 0x98, 0x00, 0x0a, 0x80, 0x20, - 0x84, 0x24, 0x00, 0x20, 0xc0, 0xe9, 0x00, 0x00, 0xfa, 0x71, 0x20, 0x01, 0x78, 0xc9, 0x40, 0x01, 0x7a, 0x49, 0x20, - 0x30, 0x7e, 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xcf, 0xf9, 0xff, 0x00, 0x30, 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, - 0xc0, 0x30, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, - 0x82, 0x01, 0x00, 0x9c, 0xa4, 0x00, 0xc7, 0x98, 0x6f, 0x00, 0xd7, 0x9a, 0x6f, 0x00, 0xc0, 0x52, 0xe3, 0x00, 0xd0, - 0x54, 0x63, 0x00, 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0xc0, 0x99, 0x00, 0x0a, 0x80, 0x30, 0x50, 0x45, 0xd8, - 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0xc0, 0x99, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0xc0, 0x99, 0x00, 0x0a, - 0x00, 0xb0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0x90, 0x92, 0x6f, 0x80, 0xa0, 0x94, 0x6f, 0x00, 0x90, 0x19, - 0x6d, 0x00, 0xc0, 0x18, 0xf3, 0xaa, 0xc0, 0x98, 0xa4, 0x00, 0xc0, 0x18, 0xf3, 0x00, 0x01, 0x40, 0xc5, 0xff, 0x00, - 0x48, 0xa3, 0x00, 0x02, 0xa8, 0xe2, 0x60, 0x40, 0x41, 0xa8, 0x08, 0x99, 0x00, 0x08, 0x02, 0xc0, 0x98, 0x24, 0x0c, - 0x99, 0x00, 0x18, 0x01, 0xc0, 0x98, 0x24, 0x00, 0xc0, 0x18, 0xf3, 0x01, 0xc0, 0x98, 0x24, 0x04, 0xa4, 0xd9, 0x37, - 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xd3, 0xb7, 0xb4, 0x99, 0x00, 0x9c, 0x06, 0xa4, 0xd5, 0xb7, 0xb4, 0x99, 0x00, - 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, 0x00, 0x9c, 0x20, 0x01, - 0x78, 0xc5, 0x40, 0x01, 0x7a, 0x45, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, - 0xa3, 0x00, 0x82, 0x00, 0xc0, 0xb9, 0xfd, 0x00, 0x00, 0xc4, 0x73, 0x00, 0xd1, 0xbb, 0xe8, 0x00, 0x90, 0x75, 0xe3, - 0xff, 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, 0x80, 0xc4, 0x94, 0x68, 0x00, 0xa4, 0xf9, - 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0x37, 0xb4, 0x99, - 0x00, 0x9c, 0x03, 0xa4, 0xc5, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x04, 0xa4, 0xd5, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x02, - 0xa4, 0xc1, 0xb9, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, - 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, - 0x39, 0x41, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x10, 0x40, 0x28, 0xe0, 0x99, 0x00, 0x08, 0x10, 0x00, - 0x48, 0xa2, 0x00, 0x40, 0x66, 0xe5, 0xe4, 0x99, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, 0x01, 0x00, 0x64, 0xa3, 0x00, - 0x20, 0x25, 0xed, 0x00, 0x00, 0x62, 0x23, 0x00, 0x01, 0x60, 0x23, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x00, 0xc0, 0x2d, - 0x00, 0x00, 0xf9, 0xeb, 0x00, 0xd0, 0x3b, 0xf9, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, - 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x0e, 0xba, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0xd0, 0xfb, 0x62, 0x00, 0xc0, - 0x39, 0xf9, 0x20, 0x01, 0x7a, 0x49, 0x40, 0x01, 0x78, 0xc9, 0x00, 0x00, 0xfc, 0xf3, 0x60, 0x31, 0x7e, 0x45, 0x00, - 0xdf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xc0, 0x31, 0x56, 0x45, 0xe0, 0x31, 0x58, 0x45, 0x00, 0x00, 0xc4, 0x73, - 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x9a, 0xa4, 0x80, 0xb6, 0x96, 0xe7, 0x00, 0xb6, 0x9c, - 0x67, 0x80, 0xc6, 0x98, 0xe7, 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, - 0x52, 0x63, 0x00, 0xe0, 0x54, 0x63, 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, 0xf0, 0x86, 0x00, 0x02, 0x00, - 0x00, 0x40, 0xa8, 0x70, 0x9b, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, 0xe4, 0x84, 0x00, 0x82, - 0x00, 0x90, 0x15, 0x6d, 0x00, 0xa0, 0x14, 0xf3, 0xaa, 0xa0, 0x94, 0xa4, 0x00, 0xa0, 0x14, 0xf3, 0x00, 0x01, 0x40, - 0xc5, 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0x92, 0xe2, 0x60, 0x90, 0x40, 0xa8, 0xc0, 0x9a, 0x00, 0x88, 0x02, 0xa0, - 0x94, 0x24, 0xc4, 0x9a, 0x00, 0x98, 0x01, 0xa0, 0x94, 0x24, 0x00, 0xa0, 0x14, 0xf3, 0x02, 0xa0, 0x94, 0x24, 0x04, - 0xa4, 0xd5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xd1, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, - 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0x9b, 0x00, 0x9c, 0x20, 0x01, 0x78, 0xc5, 0x40, 0x01, 0x7a, - 0x45, 0x00, 0x00, 0x40, 0x23, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x0e, 0xbc, 0xf9, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, - 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x80, 0x24, 0x00, 0xe0, 0xb9, 0x7d, 0x00, 0x00, 0xc4, 0x73, 0x00, - 0xd1, 0xbb, 0xe8, 0x00, 0x90, 0x75, 0xe3, 0xff, 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, - 0x80, 0xa4, 0x94, 0x68, 0x00, 0xa4, 0xf9, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, 0x7c, 0x9b, 0x00, - 0x9c, 0x02, 0xa4, 0xc1, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x03, 0xa4, 0xc5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x04, 0xa4, - 0xd5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0x7c, - 0x9b, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0x41, 0x00, 0x46, 0x23, - 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xc6, - 0xf3, 0x00, 0x00, 0xc8, 0x73, 0x00, 0x00, 0xca, 0xf3, 0x00, 0x00, 0xcc, 0xf3, 0x00, 0x30, 0xc0, 0x63, 0x0b, 0x40, - 0xc1, 0x25, 0x4c, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x43, 0x63, 0x80, - 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xb0, 0x9b, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, - 0x0e, 0x00, 0x7c, 0xa3, 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xc8, 0x9b, 0x00, - 0x0a, 0x04, 0x00, 0x7c, 0xa3, 0x00, 0x00, 0x42, 0xa3, 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, - 0x7d, 0x24, 0xe0, 0x9b, 0x00, 0x0a, 0x1a, 0x00, 0x7c, 0xa3, 0x00, 0x0f, 0xc0, 0xe2, 0x80, 0x00, 0x80, 0x24, 0x00, - 0x00, 0xc0, 0x69, 0x00, 0x00, 0xf6, 0x71, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x30, 0xc6, 0xeb, 0x00, 0x30, 0xca, 0xeb, - 0x00, 0x30, 0xc0, 0x63, 0x0b, 0xb0, 0xc1, 0x25, 0x04, 0x00, 0x42, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x10, 0x02, - 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x20, 0x9c, 0x00, 0x8a, 0x80, 0x10, 0x82, 0x24, 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, - 0xf8, 0xf1, 0x20, 0x01, 0x64, 0x49, 0x20, 0x30, 0x7e, 0x45, 0x80, 0xcd, 0xb7, 0xf9, 0x00, 0xb0, 0x81, 0xa8, 0xdc, - 0x9d, 0x00, 0x88, 0xa0, 0x30, 0x6c, 0xc5, 0xc0, 0x30, 0x6e, 0x45, 0xa8, 0x8b, 0x00, 0x02, 0x00, 0x00, 0x46, 0xe3, - 0x00, 0x00, 0x40, 0xa8, 0xfc, 0x9d, 0x00, 0x8a, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x0b, 0xac, - 0x79, 0x00, 0x60, 0x81, 0x28, 0xe4, 0x9d, 0x00, 0x08, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, - 0x00, 0x82, 0x00, 0x00, 0x72, 0x63, 0x01, 0x90, 0xb3, 0x24, 0x80, 0x9d, 0x83, 0x7f, 0xa8, 0x81, 0x00, 0x02, 0x20, - 0x01, 0x64, 0x45, 0x80, 0x2c, 0x95, 0xff, 0x80, 0x6c, 0x97, 0xff, 0x80, 0xa5, 0x99, 0x7f, 0x80, 0x55, 0x9b, 0xff, - 0x80, 0xc6, 0x96, 0xfb, 0x80, 0xa5, 0x94, 0x7b, 0x00, 0x15, 0x94, 0xff, 0x00, 0xa0, 0x80, 0xa8, 0xec, 0x9d, 0x00, - 0x88, 0x40, 0x01, 0x54, 0x49, 0x00, 0xa0, 0x42, 0x63, 0xa8, 0x81, 0x00, 0x02, 0x80, 0x20, 0xb9, 0x7f, 0x80, 0x60, - 0xb7, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, 0xc0, 0x30, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x94, - 0x8a, 0x00, 0x82, 0x00, 0x90, 0x5e, 0xe3, 0x00, 0xa0, 0x60, 0x63, 0x00, 0xb0, 0x62, 0x63, 0x60, 0x01, 0x58, 0xc5, - 0x80, 0x01, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0xb0, 0x79, 0x63, 0x94, 0x8a, 0x00, 0x82, 0x80, 0xf5, 0x84, - 0xef, 0x80, 0x98, 0x86, 0xef, 0x80, 0x21, 0x80, 0xe8, 0x38, 0x9d, 0x00, 0x0a, 0x80, 0x05, 0x85, 0x6f, 0x80, 0xa8, - 0x86, 0xef, 0x80, 0x21, 0x80, 0xe8, 0xf4, 0x9d, 0x00, 0x0a, 0xfc, 0x89, 0x00, 0x02, 0x00, 0x90, 0x58, 0xe3, 0x00, - 0xa0, 0x5a, 0x63, 0x00, 0xb0, 0x5c, 0xe3, 0x48, 0x9d, 0x00, 0x98, 0x00, 0xf0, 0x58, 0xe3, 0x00, 0x00, 0x5b, 0xe3, - 0x00, 0x10, 0x5d, 0x63, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0xc0, 0x98, - 0x6f, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x06, 0x98, 0x79, 0x00, 0x00, 0x7e, 0xa3, 0x00, 0xf0, - 0x41, 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, 0x9d, 0x00, 0x0a, 0x00, 0xf0, 0x41, 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, - 0x9d, 0x00, 0x0a, 0x00, 0x00, 0x46, 0x23, 0xc3, 0x00, 0x44, 0xa3, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, - 0x00, 0xe0, 0x45, 0x69, 0x00, 0x30, 0x40, 0xa8, 0x01, 0x00, 0x42, 0x23, 0xbc, 0x9d, 0x00, 0x0a, 0x50, 0x00, 0x42, - 0xa3, 0x10, 0x00, 0x7c, 0x22, 0x00, 0x60, 0x2d, 0xf9, 0x00, 0xe0, 0x6d, 0x69, 0x20, 0xe0, 0x7d, 0x22, 0x40, 0x01, - 0x54, 0x45, 0x00, 0xa0, 0x14, 0xf9, 0x00, 0xe0, 0x55, 0xe9, 0x00, 0x30, 0x40, 0xe3, 0x00, 0x00, 0x68, 0x23, 0x00, - 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x76, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, - 0x94, 0x81, 0x00, 0x98, 0x21, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, 0x22, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, - 0x98, 0x23, 0x00, 0x46, 0xa3, 0xfc, 0x9d, 0x00, 0x98, 0x24, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, 0x3c, 0x00, - 0x44, 0xa3, 0x01, 0x00, 0x42, 0x23, 0x84, 0x9d, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x40, 0x31, 0x7e, 0xc5, 0x00, - 0x00, 0x40, 0x23, 0x00, 0x08, 0x80, 0xf9, 0x00, 0x08, 0x80, 0xe8, 0xdc, 0x9e, 0x00, 0x0a, 0xd8, 0x8c, 0x00, 0x02, - 0xdc, 0x9e, 0x00, 0x0a, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xa4, - 0x24, 0x00, 0x09, 0xa1, 0x67, 0x00, 0x19, 0xa3, 0x67, 0x00, 0x00, 0xfc, 0xf3, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x3f, - 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, 0x70, 0x96, 0x00, 0x02, 0x5c, 0x8e, 0x00, 0x82, 0xd0, 0x8e, 0x00, 0x02, 0x00, - 0x70, 0x6e, 0x63, 0x00, 0x80, 0x70, 0x63, 0x00, 0x90, 0x72, 0x63, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, - 0x00, 0x00, 0x4f, 0xe3, 0x00, 0x20, 0x51, 0x63, 0x00, 0x10, 0x53, 0xe3, 0x0c, 0x8d, 0x00, 0x82, 0x00, 0x00, 0xfc, - 0xf3, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x3f, 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, 0x5c, 0x8e, 0x00, 0x82, 0xd0, 0x8e, - 0x00, 0x02, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x80, 0x04, 0x92, 0xfd, 0x00, - 0x70, 0x57, 0x63, 0x00, 0x80, 0x59, 0xe3, 0x00, 0x90, 0x5b, 0xe3, 0x0c, 0x8d, 0x00, 0x82, 0x00, 0xc0, 0x42, 0x63, - 0x74, 0x84, 0x00, 0x82, 0x80, 0xb0, 0x96, 0xe7, 0x80, 0xd0, 0x9a, 0xe7, 0x01, 0x00, 0x58, 0xa3, 0xd4, 0x8d, 0x00, - 0x82, 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x12, 0x00, 0x40, 0x23, 0x00, 0x00, - 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0xa8, 0xa4, 0x00, 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, - 0x00, 0x48, 0x22, 0x00, 0x40, 0x48, 0xe5, 0xff, 0x00, 0x44, 0xa3, 0x00, 0x41, 0x82, 0xe2, 0x00, 0x40, 0x32, 0xf5, - 0x00, 0x90, 0x09, 0xf5, 0x00, 0x40, 0x08, 0xf5, 0x00, 0x91, 0xb3, 0xe2, 0x00, 0x41, 0x88, 0xe2, 0x00, 0x00, 0x00, - 0x84, 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x33, 0x63, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x01, 0x90, - 0x75, 0x22, 0x04, 0xa4, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x02, 0x40, 0x40, 0xa8, 0x54, 0x9f, 0x00, 0x08, 0x01, - 0x40, 0x40, 0xa8, 0x70, 0x9f, 0x00, 0x08, 0xf4, 0x00, 0x46, 0xa3, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, - 0xcc, 0x99, 0x00, 0x82, 0x00, 0x30, 0x40, 0xa8, 0x68, 0x9f, 0x00, 0x08, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, - 0x98, 0xc3, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xe4, 0x97, 0x00, 0x02, 0x00, 0x30, 0x40, 0xa8, 0x84, 0x9f, - 0x00, 0x88, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xc3, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0x64, - 0x81, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa2, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x44, 0x69, 0x00, 0x30, 0x40, 0xe3, - 0x00, 0xa1, 0x00, 0x98, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x68, 0xe3, 0x00, 0x40, 0x6b, 0x22, 0xf0, 0x9e, 0x00, - 0x02, 0x00, 0x90, 0x35, 0x63, 0x01, 0xa0, 0x75, 0x22, 0xf2, 0x00, 0x46, 0xa3, 0x04, 0xa4, 0xc1, 0xb9, 0x70, 0xa0, - 0x00, 0x9e, 0x04, 0xa4, 0xc5, 0x35, 0x7c, 0xa0, 0x00, 0x1c, 0xf6, 0x00, 0x46, 0x23, 0xff, 0x00, 0x7c, 0x23, 0x00, - 0x20, 0x4a, 0x63, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0x01, 0x40, 0x40, 0xa8, 0xf4, 0x9f, 0x00, 0x08, - 0x02, 0x40, 0x40, 0xa8, 0x70, 0xa0, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0xaa, 0x40, 0x40, - 0x28, 0x70, 0xa0, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0x80, 0x4c, 0x40, 0x68, 0x70, 0xa0, - 0x00, 0x8a, 0xf4, 0x00, 0x46, 0xa3, 0x00, 0xe1, 0xbd, 0xe2, 0x02, 0xe0, 0x41, 0x28, 0x44, 0xa0, 0x00, 0x88, 0x01, - 0xe0, 0x41, 0x28, 0x70, 0xa0, 0x00, 0x8a, 0x50, 0x00, 0x42, 0xa3, 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, 0x00, 0x1c, - 0x06, 0xa4, 0xe3, 0x35, 0x7c, 0xa0, 0x00, 0x1c, 0x50, 0xa0, 0x00, 0x18, 0x30, 0x00, 0x42, 0xa3, 0x05, 0xa4, 0xe1, - 0xb5, 0x7c, 0xa0, 0x00, 0x1c, 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0xff, 0x0f, 0x4a, 0x23, 0x80, 0x22, - 0x84, 0x62, 0x00, 0x20, 0x04, 0xf3, 0xc3, 0x20, 0x84, 0xa4, 0x00, 0x00, 0x40, 0x23, 0x8c, 0xa0, 0x00, 0x98, 0x12, - 0x00, 0x44, 0xa3, 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, 0x00, 0x98, 0x3c, 0x00, 0x44, 0xa3, 0xf2, 0x00, 0x46, 0xa3, - 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, 0x00, 0x98, 0x00, 0x50, 0x45, 0xe9, 0x10, 0x40, 0x6d, 0xa2, 0x00, 0x00, 0x21, - 0xf9, 0x00, 0x60, 0x61, 0xe9, 0x20, 0x60, 0x6d, 0x22, 0x00, 0x10, 0x23, 0xf9, 0x00, 0x60, 0x63, 0x69, 0x00, 0x00, - 0x40, 0x23, 0x00, 0xa1, 0x00, 0x98, 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x33, 0x63, 0x64, 0x81, 0x00, 0x02, 0x00, - 0x00, 0x6a, 0x22, 0x03, 0x94, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, - 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, 0x73, 0x22, 0x03, 0x94, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0x04, 0x94, 0xc1, - 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x05, 0x94, 0xc1, 0x39, 0xc3, 0x00, 0x44, 0xa3, 0x00, 0x50, 0x45, 0xe9, 0x01, 0x00, - 0x42, 0x23, 0x00, 0x00, 0x40, 0x23, 0x00, 0xa1, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x00, - 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x44, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x94, 0x81, 0x00, 0x98, - 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, 0x22, 0x00, 0x40, 0x48, 0xe5, 0x00, 0x40, 0x04, 0xf5, 0xff, 0x00, 0x4c, - 0x23, 0x00, 0x23, 0x84, 0x62, 0x00, 0x20, 0x32, 0x63, 0x01, 0x90, 0xb3, 0x24, 0x04, 0x94, 0xcb, 0xb5, 0x0c, 0xa2, - 0x00, 0x1c, 0xff, 0x00, 0x4c, 0x23, 0x00, 0x53, 0x8e, 0xe2, 0x01, 0x70, 0x40, 0xa8, 0x00, 0xa2, 0x00, 0x8a, 0x00, - 0x50, 0x0a, 0xf5, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x53, 0x8e, 0xe2, 0x00, 0x71, 0x40, 0x68, - 0xf4, 0xa1, 0x00, 0x0a, 0x05, 0x94, 0xcb, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x60, 0x01, 0x4a, 0xc9, 0x06, 0x94, 0xcb, - 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x80, 0x01, 0x4a, 0x49, 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, 0x73, 0x24, 0x00, 0x94, - 0xf5, 0xb5, 0x0c, 0xa2, 0x00, 0x1c, 0x01, 0x94, 0xed, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x02, 0x94, 0xeb, 0x35, 0x0c, - 0xa2, 0x00, 0x1c, 0x03, 0x94, 0xef, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x05, 0x94, 0xc1, 0x39, 0x10, 0x00, 0x48, 0xa2, - 0x00, 0x40, 0x64, 0x65, 0x00, 0x20, 0x25, 0xf9, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, - 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, 0x00, 0x50, 0xab, 0xfb, 0x00, 0x00, 0xd4, 0xf3, 0x00, 0x65, - 0xad, 0x68, 0x00, 0x75, 0xaf, 0x68, 0x80, 0x6b, 0xa9, 0xe8, 0xa0, 0x00, 0x60, 0xc5, 0x00, 0x00, 0x21, 0xf9, 0xc0, - 0x00, 0x62, 0x45, 0x88, 0x9b, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf6, 0x00, 0x46, 0x23, 0x14, 0xa2, 0x00, 0x98, - 0x05, 0x94, 0xc1, 0x39, 0xf4, 0x00, 0x46, 0xa3, 0x14, 0xa2, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf2, 0x00, 0x46, - 0xa3, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x05, 0x94, 0xc1, 0x39, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, - 0x7c, 0xa2, 0x12, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x00, 0x30, 0x40, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, - 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x6e, 0x23, - 0x94, 0x81, 0x00, 0x98, 0x20, 0x00, 0x42, 0x23, 0x94, 0x81, 0x00, 0x98, 0xf2, 0x00, 0x40, 0xa3, 0x50, 0xa2, 0x00, - 0x98, 0x00, 0x00, 0xe6, 0x73, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, - 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0x30, 0xe7, 0x62, 0x40, 0x00, 0x66, 0x49, 0x09, - 0x00, 0x60, 0xa3, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, - 0x50, 0xa2, 0x00, 0x98, 0x40, 0x00, 0x66, 0x45, 0x20, 0x00, 0x60, 0x45, 0x60, 0x00, 0x60, 0xc9, 0x0c, 0x9e, 0x00, - 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x20, 0x00, - 0x42, 0x45, 0x00, 0x12, 0xe0, 0xb5, 0x58, 0xa2, 0x00, 0x9c, 0x40, 0x00, 0x66, 0x45, 0x0c, 0x9e, 0x00, 0x02, 0x00, - 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x60, 0x00, 0x60, 0xc5, - 0x00, 0x00, 0x42, 0xa3, 0x00, 0x10, 0xe6, 0x35, 0x58, 0xa2, 0x00, 0x9c, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, - 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0x30, - 0xe7, 0x62, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x00, - 0x00, 0x66, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x50, 0xa2, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, - 0xd0, 0xa3, 0x00, 0x02, 0xe4, 0xa3, 0x00, 0x82, 0x04, 0xa4, 0x00, 0x82, 0x24, 0xa4, 0x00, 0x02, 0x00, 0x00, 0xc0, - 0x2d, 0x00, 0x00, 0xc0, 0x63, 0x94, 0x81, 0x00, 0x98, 0x1c, 0x00, 0x7c, 0xa3, 0x00, 0x10, 0x23, 0xf9, 0x00, 0x00, - 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, 0xfd, 0x80, 0x08, 0x21, 0x7d, 0x00, 0x10, 0x23, 0xf3, 0x01, - 0xe0, 0x7d, 0x24, 0x5c, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, 0xfd, - 0x00, 0x00, 0x21, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x78, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, 0x00, 0x00, 0x00, - 0x84, 0x54, 0x00, 0x46, 0xa3, 0x00, 0x30, 0x06, 0xf3, 0x53, 0x30, 0x86, 0xa4, 0x00, 0x30, 0x06, 0xf3, 0x01, 0x30, - 0x86, 0x24, 0x00, 0x30, 0x06, 0xf3, 0x80, 0x30, 0x86, 0x24, 0x00, 0x30, 0x06, 0xf5, 0x00, 0x00, 0x00, 0x84, 0x90, - 0xa3, 0x00, 0x82, 0x01, 0x06, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xed, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xc0, 0xeb, - 0x00, 0x10, 0x80, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x08, 0x4c, 0xa3, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x60, 0x7e, - 0x69, 0xd4, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x02, 0x4c, 0xa3, 0x10, 0x00, 0x44, 0x23, 0x00, 0x20, - 0x04, 0xf3, 0x00, 0x61, 0x86, 0xe4, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0xf0, 0xa3, 0x00, 0x0a, 0x00, - 0x00, 0x00, 0x84, 0x80, 0x00, 0x4c, 0xa3, 0x50, 0x00, 0x44, 0xa3, 0x00, 0x20, 0x04, 0xf3, 0x00, 0x61, 0x86, 0xe4, - 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0x10, 0xa4, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x40, - 0x23, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x44, 0xa3, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x48, 0xa3, 0x00, 0x00, - 0x4a, 0x23, 0x00, 0x00, 0x4c, 0x23, 0x00, 0x00, 0x4e, 0xa3, 0x00, 0x00, 0x50, 0xa3, 0x00, 0x00, 0x52, 0x23, 0x00, - 0x00, 0x54, 0x23, 0x00, 0x00, 0x56, 0xa3, 0x00, 0x00, 0x58, 0x23, 0x00, 0x00, 0x5a, 0xa3, 0x00, 0x00, 0x5c, 0xa3, - 0x00, 0x00, 0x5e, 0x23, 0x00, 0x00, 0x60, 0xa3, 0x00, 0x00, 0x62, 0x23, 0x00, 0x00, 0x64, 0x23, 0x00, 0x00, 0x66, - 0xa3, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, 0x00, 0x00, 0x6e, 0x23, 0x00, 0x00, - 0x70, 0x23, 0x00, 0x00, 0x72, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x76, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x00, - 0x00, 0x7a, 0x23, 0x00, 0x00, 0x7c, 0x23, 0x00, 0x00, 0x7e, 0xa3, 0x00, 0x00, 0x00, 0x84}; \ No newline at end of file +const uint8_t fw_SPECT[] = { + 0x6b, 0xc1, 0x97, 0x12, 0x62, 0xd1, 0x74, 0x61, 0x11, 0xc6, 0x82, 0x39, 0x3d, 0xb0, 0x9f, 0xb7, + 0xde, 0xb2, 0x09, 0x47, 0x40, 0x54, 0xca, 0xc2, 0x3c, 0x86, 0x9f, 0x05, 0xdb, 0x0e, 0xd7, 0x70, + 0xe8, 0x6a, 0x1d, 0xd0, 0x6d, 0xa3, 0xf7, 0xea, 0x18, 0x4e, 0xda, 0x94, 0x1c, 0x24, 0xaf, 0x8d, + 0x1b, 0x24, 0x34, 0x9c, 0x18, 0x17, 0x38, 0x15, 0x37, 0xf6, 0xc8, 0x61, 0x81, 0x81, 0x7b, 0x05, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa8, 0x24, 0x00, 0x00, 0xd4, 0x7d, 0x50, 0x04, + 0xb7, 0xcf, 0xe1, 0x1e, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x00, 0x7e, 0xa3, 0xe4, 0xa3, 0x00, 0x82, 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, 0x40, 0xa2, + 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0x82, 0x62, 0xf0, 0x10, 0x88, 0xa2, 0x20, 0x33, 0x4a, 0xc5, + 0x00, 0x10, 0x40, 0x28, 0x2c, 0xa3, 0x00, 0x08, 0x60, 0x40, 0x40, 0x28, 0x4c, 0x80, 0x00, 0x88, + 0x10, 0x40, 0x40, 0xa8, 0x84, 0x80, 0x00, 0x08, 0x40, 0x40, 0x40, 0xa8, 0xb8, 0x80, 0x00, 0x08, + 0x70, 0x40, 0x40, 0xa8, 0x20, 0x81, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0x04, 0xa4, 0x00, 0x82, + 0xf4, 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x60, 0x10, 0x40, 0x28, + 0x1c, 0x9f, 0x00, 0x08, 0x61, 0x10, 0x40, 0xa8, 0x1c, 0x9f, 0x00, 0x08, 0x62, 0x10, 0x40, 0xa8, + 0xa4, 0x9f, 0x00, 0x08, 0x63, 0x10, 0x40, 0x28, 0xb0, 0xa0, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, + 0xa8, 0xa4, 0x00, 0x18, 0xf3, 0x50, 0x8a, 0xa4, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, + 0x11, 0x10, 0x40, 0x28, 0x60, 0xa2, 0x00, 0x08, 0x12, 0x10, 0x40, 0x28, 0x9c, 0xa2, 0x00, 0x08, + 0x13, 0x10, 0x40, 0xa8, 0xbc, 0xa2, 0x00, 0x88, 0x14, 0x10, 0x40, 0x28, 0xe0, 0xa2, 0x00, 0x88, + 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x04, 0xa4, 0x00, 0x82, 0xf2, 0x50, 0x8a, 0x24, + 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x41, 0x10, 0x40, 0x28, 0x94, 0x8f, 0x00, 0x88, + 0x42, 0x10, 0x40, 0x28, 0xac, 0x90, 0x00, 0x88, 0x43, 0x10, 0x40, 0xa8, 0xd4, 0x90, 0x00, 0x88, + 0x44, 0x10, 0x40, 0x28, 0x04, 0x91, 0x00, 0x88, 0x45, 0x10, 0x40, 0xa8, 0xfc, 0x91, 0x00, 0x08, + 0x46, 0x10, 0x40, 0xa8, 0xa0, 0x92, 0x00, 0x08, 0x47, 0x10, 0x40, 0x28, 0xf4, 0x92, 0x00, 0x88, + 0x48, 0x10, 0x40, 0x28, 0x30, 0x93, 0x00, 0x88, 0x49, 0x10, 0x40, 0xa8, 0x48, 0x93, 0x00, 0x88, + 0x4a, 0x10, 0x40, 0xa8, 0x18, 0x94, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, + 0x04, 0xa4, 0x00, 0x82, 0xf1, 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, + 0x70, 0x10, 0x40, 0xa8, 0x1c, 0xa1, 0x00, 0x88, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, + 0x02, 0x00, 0x44, 0x23, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x44, 0x69, 0x00, 0x00, 0x42, 0xa3, + 0xf3, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x40, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xf3, + 0x00, 0x00, 0x00, 0x84, 0x50, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, 0x00, 0xf5, 0x00, 0x00, 0x00, 0xf5, 0xff, 0x00, 0x42, 0xa3, + 0x00, 0x10, 0x02, 0xf3, 0xff, 0x10, 0x82, 0xa4, 0x80, 0x00, 0x80, 0xe2, 0x00, 0x00, 0x00, 0x84, + 0xa8, 0xa4, 0x00, 0x18, 0x00, 0x10, 0x02, 0xf3, 0x00, 0x10, 0x02, 0xf3, 0x80, 0x00, 0x40, 0xe2, + 0x00, 0x11, 0x40, 0x49, 0x00, 0x00, 0xc0, 0x93, 0x80, 0x10, 0x84, 0xff, 0x80, 0x20, 0x86, 0x7f, + 0x80, 0x31, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x80, 0x41, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, + 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x80, 0x42, 0x8a, 0xff, + 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x06, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, + 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0xdc, 0x81, 0x00, 0x8a, + 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x0f, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, + 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0xfc, 0x81, 0x00, 0x0a, + 0x80, 0x42, 0x8c, 0xff, 0x00, 0x63, 0x88, 0xff, 0x3f, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, + 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0x1c, 0x82, 0x00, 0x8a, + 0x00, 0x43, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x1e, 0x00, 0x7c, 0x23, + 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, + 0x40, 0x82, 0x00, 0x8a, 0x00, 0x43, 0x88, 0x7f, 0x40, 0x30, 0x4a, 0xc5, 0x80, 0x00, 0x7c, 0xa3, + 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x50, 0x0a, 0x63, 0x80, 0x82, 0x00, 0x8c, + 0x00, 0x50, 0x0a, 0x63, 0x94, 0x82, 0x00, 0x0e, 0x80, 0x40, 0x88, 0xff, 0x94, 0x82, 0x00, 0x98, + 0x00, 0x50, 0x0a, 0x63, 0x90, 0x82, 0x00, 0x0c, 0x00, 0x41, 0x88, 0xff, 0x94, 0x82, 0x00, 0x98, + 0x80, 0x41, 0x88, 0x7f, 0x02, 0xe0, 0x7d, 0x24, 0x60, 0x82, 0x00, 0x0a, 0x00, 0x40, 0x42, 0xe3, + 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x86, 0xef, 0x80, 0x30, 0x88, 0xef, 0x00, 0x42, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x31, 0x86, 0x6f, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x8a, 0x6f, 0x80, 0x52, 0x86, 0xef, 0x09, 0x00, 0x7c, 0x23, + 0x80, 0x31, 0x86, 0xef, 0x01, 0xe0, 0x7d, 0x24, 0xe0, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x86, 0xef, + 0x0a, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x02, 0xe0, 0x7d, 0x24, + 0xf4, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x8a, 0xef, 0x80, 0x52, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, + 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x1e, 0x00, 0x7c, 0x23, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, + 0x20, 0x83, 0x00, 0x0a, 0x80, 0x30, 0x86, 0x6f, 0x80, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x04, 0xe0, 0x7d, 0x24, + 0x3c, 0x83, 0x00, 0x8a, 0x00, 0x31, 0x86, 0x6f, 0x20, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x04, 0xe0, 0x7d, 0x24, + 0x5c, 0x83, 0x00, 0x8a, 0x00, 0x31, 0x86, 0x6f, 0x1e, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, 0x7c, 0x83, 0x00, 0x0a, + 0x80, 0x32, 0x86, 0xef, 0x00, 0x00, 0x00, 0x84, 0xa4, 0x82, 0x00, 0x02, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x30, 0x82, 0xef, 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x84, 0xe7, + 0x80, 0x20, 0x88, 0xe7, 0x00, 0x42, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x41, 0x84, 0x67, + 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, + 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x07, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0x67, + 0x01, 0xe0, 0x7d, 0x24, 0xdc, 0x83, 0x00, 0x0a, 0x80, 0x21, 0x8a, 0xe7, 0x80, 0x52, 0x86, 0x67, + 0x0f, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xf4, 0x83, 0x00, 0x0a, + 0x80, 0x51, 0x84, 0xe7, 0x00, 0x21, 0x86, 0x67, 0x0f, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, + 0x01, 0xe0, 0x7d, 0x24, 0x0c, 0x84, 0x00, 0x0a, 0x80, 0x51, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, + 0x00, 0x21, 0x84, 0xe7, 0x00, 0x22, 0x8a, 0x67, 0x80, 0x52, 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, + 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x30, 0x84, 0x00, 0x0a, 0x80, 0x51, 0x84, 0xe7, + 0x00, 0x21, 0x86, 0x67, 0x63, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, + 0x48, 0x84, 0x00, 0x0a, 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, + 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x60, 0x84, 0x00, 0x0a, 0x80, 0x32, 0x84, 0xe7, + 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, + 0x80, 0x30, 0x86, 0xe7, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, + 0x00, 0x32, 0x82, 0x67, 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0x80, 0x67, + 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, + 0x00, 0x00, 0x80, 0x67, 0x00, 0x21, 0x84, 0xe7, 0x80, 0x20, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, + 0x00, 0x32, 0x48, 0x45, 0x00, 0x22, 0x86, 0x67, 0x00, 0x21, 0x88, 0xe7, 0x80, 0x40, 0x88, 0xe8, + 0xdc, 0x84, 0x00, 0x8a, 0x00, 0x20, 0x42, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x30, 0x42, 0x63, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x90, 0x42, 0x63, 0x74, 0x84, 0x00, 0x82, 0x80, 0x70, 0x8e, 0xe7, + 0x80, 0x80, 0x90, 0xe7, 0x01, 0x00, 0x42, 0x23, 0x80, 0x70, 0x8e, 0xe2, 0x00, 0x80, 0x10, 0xeb, + 0x80, 0x83, 0x90, 0xe4, 0x00, 0x80, 0x10, 0xed, 0x00, 0x80, 0x10, 0xf9, 0x00, 0x00, 0x00, 0x84, + 0x00, 0xc0, 0x60, 0x63, 0x00, 0x00, 0x21, 0x63, 0x24, 0x85, 0x00, 0x8c, 0x00, 0x00, 0x6c, 0xa3, + 0x2c, 0x85, 0x00, 0x18, 0x01, 0x00, 0x6c, 0x23, 0x2c, 0x85, 0x00, 0x18, 0x00, 0x00, 0x21, 0x65, + 0x00, 0x00, 0x59, 0x63, 0x00, 0x08, 0xa1, 0xe7, 0x01, 0x00, 0x42, 0x23, 0x80, 0x00, 0xa9, 0xfd, + 0x00, 0x03, 0xa1, 0x67, 0x80, 0x00, 0xab, 0x7b, 0x80, 0x5a, 0xa5, 0x67, 0x80, 0x2a, 0xa5, 0xe7, + 0x00, 0x2a, 0xa7, 0xe7, 0x00, 0x29, 0xa5, 0x67, 0x80, 0x2a, 0xa5, 0xe7, 0x00, 0x2a, 0x83, 0xe7, + 0x00, 0x10, 0x60, 0xe3, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0xa4, 0x67, 0x00, 0x29, 0xa5, 0x67, + 0x00, 0x28, 0xa5, 0xe7, 0x80, 0x29, 0xa5, 0xe7, 0x00, 0x29, 0xa1, 0xe7, 0x80, 0x0a, 0xa1, 0xe7, + 0x00, 0x32, 0x42, 0x45, 0x80, 0x20, 0xa3, 0xe7, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x0a, 0xbd, 0xe8, + 0x9c, 0x85, 0x00, 0x8a, 0x00, 0x20, 0x41, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x7c, 0x23, + 0x00, 0xea, 0xa9, 0xfd, 0x00, 0x0a, 0xbd, 0xe8, 0xb4, 0x85, 0x00, 0x8a, 0x00, 0x10, 0x41, 0xe3, + 0x01, 0x00, 0x42, 0x23, 0x00, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, 0x88, 0x00, 0x00, 0x42, 0xa3, + 0x00, 0xe0, 0xbd, 0x68, 0xcc, 0x85, 0x00, 0x8a, 0x01, 0x10, 0x82, 0x24, 0x01, 0x60, 0x41, 0xa8, + 0xd8, 0x85, 0x00, 0x8a, 0x02, 0x10, 0x82, 0x24, 0x03, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, 0x88, + 0x00, 0x00, 0x46, 0x23, 0x00, 0x30, 0x86, 0xfd, 0x01, 0x00, 0x7c, 0xa3, 0x00, 0x0f, 0x82, 0xe2, + 0x00, 0x1b, 0x40, 0x68, 0x00, 0x86, 0x00, 0x8a, 0x00, 0x00, 0x56, 0x63, 0x08, 0x86, 0x00, 0x18, + 0x00, 0x30, 0x56, 0x63, 0x08, 0x86, 0x00, 0x18, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x00, 0x84, + 0xff, 0x0f, 0x42, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x80, 0x83, 0x80, 0xfd, 0x80, 0xc5, 0x82, 0xfd, + 0x80, 0x00, 0x80, 0xe7, 0x80, 0x83, 0x82, 0x7b, 0x80, 0xc5, 0x84, 0xfb, 0x00, 0x11, 0x82, 0xe7, + 0x00, 0xa7, 0x84, 0x67, 0x00, 0x23, 0x84, 0x67, 0x00, 0x21, 0x84, 0x7b, 0x80, 0x96, 0x86, 0xe7, + 0x80, 0x31, 0x86, 0xfb, 0x00, 0x10, 0x88, 0xfd, 0x00, 0x10, 0x80, 0x7b, 0x00, 0x31, 0x82, 0xfd, + 0x00, 0x31, 0x84, 0xfb, 0x80, 0x40, 0x96, 0xe7, 0x00, 0x40, 0x9c, 0x67, 0x00, 0x20, 0x98, 0xe7, + 0x80, 0x20, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x80, 0x73, 0x80, 0x67, 0x00, 0x84, 0x82, 0xe7, + 0x80, 0x94, 0x84, 0xe7, 0x00, 0x21, 0x84, 0x7b, 0x80, 0x00, 0x86, 0x7b, 0x00, 0x74, 0x88, 0x7b, + 0x00, 0x42, 0x88, 0xe7, 0x00, 0x32, 0x88, 0xfd, 0x80, 0x00, 0x80, 0x7d, 0x00, 0x20, 0x82, 0xfb, + 0x80, 0x40, 0x8e, 0xe7, 0x80, 0x00, 0x92, 0xe7, 0x80, 0x01, 0x90, 0xe7, 0x80, 0x41, 0x94, 0xe7, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x4e, 0xa3, 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, 0xa3, + 0x00, 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xb0, 0x4e, 0x67, + 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, + 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, + 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0xb8, 0x86, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x05, 0x56, 0xc9, 0x20, 0x05, 0x58, 0xc9, 0x40, 0x05, 0x5a, 0x49, 0x00, 0x00, 0x4e, 0xa3, + 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, 0xa3, + 0x00, 0x00, 0xde, 0xf3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, 0x00, 0xb0, 0x4e, 0x67, + 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, + 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, + 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x14, 0x87, 0x00, 0x0a, 0x00, 0x01, 0x7c, 0xa3, + 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, + 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, + 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, + 0x01, 0xe0, 0x7d, 0x24, 0x50, 0x87, 0x00, 0x0a, 0x00, 0x00, 0x7c, 0x23, 0x80, 0xe3, 0x8f, 0xfd, + 0x00, 0xe5, 0x95, 0xfd, 0x18, 0x86, 0x00, 0x02, 0x80, 0xe3, 0x8f, 0xfd, 0x00, 0xe5, 0x95, 0xfd, + 0x00, 0x05, 0x40, 0x45, 0x20, 0x05, 0x42, 0x45, 0x40, 0x05, 0x44, 0x45, 0x80, 0x06, 0x80, 0xe7, + 0x80, 0x16, 0x82, 0xe7, 0x00, 0xb1, 0x96, 0xe7, 0x00, 0xc1, 0x98, 0xe7, 0x80, 0x05, 0xbc, 0xe8, + 0xd4, 0x87, 0x00, 0x0a, 0x00, 0x16, 0xbc, 0xe8, 0xd4, 0x87, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, + 0x00, 0x00, 0x00, 0x84, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x40, 0x31, 0x7e, 0xc5, + 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xae, 0x24, + 0x80, 0x5b, 0xab, 0x67, 0x00, 0x5b, 0xb1, 0x67, 0x80, 0x6b, 0xad, 0x67, 0x98, 0x96, 0x00, 0x02, + 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, + 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0x02, 0x56, 0x49, 0x20, 0x02, 0x58, 0x49, 0x40, 0x02, 0x5a, 0xc9, + 0x60, 0x02, 0x5c, 0x49, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x08, 0x89, 0x00, 0x0a, + 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0x02, 0x56, 0x45, 0x20, 0x02, 0x58, 0x45, + 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, 0x45, 0x00, 0x02, 0x4e, 0x49, 0x20, 0x02, 0x50, 0xc9, + 0x40, 0x02, 0x52, 0x49, 0x60, 0x02, 0x54, 0xc9, 0x00, 0x50, 0x4f, 0xe3, 0x00, 0x60, 0x51, 0xe3, + 0x00, 0x70, 0x53, 0xe3, 0x00, 0x80, 0x55, 0xe3, 0x00, 0x00, 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, + 0x00, 0x07, 0x9c, 0xfd, 0x18, 0x86, 0x00, 0x02, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xfc, 0xf3, + 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, 0xf0, 0x86, 0x00, 0x02, + 0x00, 0x00, 0x40, 0xa8, 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, + 0x00, 0x02, 0x56, 0x45, 0x20, 0x02, 0x58, 0x45, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, 0x45, + 0x18, 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, + 0x00, 0xe0, 0x54, 0x63, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, + 0x74, 0x84, 0x00, 0x82, 0x80, 0xb0, 0xaa, 0xe7, 0x80, 0xc0, 0xac, 0x67, 0x80, 0x5a, 0x83, 0xe7, + 0x00, 0x6b, 0x85, 0xe7, 0x80, 0x20, 0x86, 0xfd, 0x00, 0x11, 0x88, 0xe7, 0x00, 0x43, 0x88, 0x67, + 0x01, 0x00, 0x40, 0xa3, 0x00, 0x40, 0x88, 0xfb, 0x00, 0x32, 0x80, 0xe8, 0x08, 0x89, 0x00, 0x0a, + 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, + 0x80, 0x73, 0x80, 0x67, 0x00, 0x84, 0x82, 0xe7, 0x80, 0x94, 0x84, 0xe7, 0x00, 0x10, 0x86, 0x7d, + 0x00, 0x31, 0x86, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x03, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, + 0x00, 0x01, 0x80, 0x7b, 0x00, 0x30, 0x86, 0x68, 0x48, 0x89, 0x00, 0x8a, 0x00, 0x74, 0x80, 0x67, + 0x00, 0x95, 0x86, 0x67, 0x00, 0x30, 0x86, 0x68, 0x00, 0x00, 0x00, 0x84, 0x00, 0x96, 0x80, 0xef, + 0x80, 0xa6, 0x82, 0xef, 0x00, 0xb7, 0x84, 0x6f, 0x00, 0x95, 0x86, 0xfb, 0x80, 0xc6, 0x88, 0xfb, + 0x00, 0x32, 0x86, 0x6f, 0x80, 0x00, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x7d, 0x80, 0xa5, 0x88, 0xfb, + 0x00, 0xd7, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xef, 0x00, 0x11, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xfd, + 0x80, 0x95, 0x8a, 0x7b, 0x00, 0xc7, 0x8c, 0x7b, 0x00, 0x53, 0x8a, 0xef, 0x00, 0x01, 0x8c, 0x7b, + 0x00, 0x53, 0x8c, 0xfd, 0x00, 0x81, 0x8e, 0x6f, 0x80, 0x63, 0x8a, 0x7d, 0x80, 0x52, 0x8e, 0x7b, + 0x80, 0x53, 0x8a, 0x7b, 0x80, 0x12, 0x8e, 0xfd, 0x80, 0x12, 0x8a, 0x7b, 0x00, 0x83, 0x8c, 0x6f, + 0x00, 0x21, 0x82, 0x7b, 0x00, 0x11, 0x84, 0x7b, 0x00, 0x61, 0x8c, 0x7d, 0x00, 0x60, 0x8c, 0xfd, + 0x00, 0x63, 0x82, 0x7b, 0x00, 0x13, 0x8c, 0x7b, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x80, 0x7b, + 0x00, 0x01, 0x80, 0x7d, 0x00, 0x43, 0x82, 0xef, 0x00, 0x03, 0x84, 0x6f, 0x80, 0x53, 0x8c, 0x6f, + 0x00, 0x61, 0x9a, 0xfb, 0x80, 0x32, 0x8a, 0xef, 0x80, 0x50, 0x98, 0x7d, 0x80, 0x43, 0x8e, 0x6f, + 0x00, 0x30, 0x82, 0x6f, 0x80, 0x70, 0x9c, 0x7b, 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0xef, + 0x00, 0xa5, 0x82, 0x6f, 0x80, 0xb5, 0x84, 0x6f, 0x00, 0x95, 0x86, 0xef, 0x80, 0x31, 0x86, 0xfb, + 0x80, 0x95, 0x8e, 0xef, 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x81, 0x8c, 0xef, 0x80, 0x63, 0x8c, 0x7d, + 0x00, 0x63, 0x8a, 0xfb, 0x00, 0x53, 0x8c, 0xfb, 0x00, 0x13, 0x8a, 0x7d, 0x00, 0x13, 0x8c, 0x7b, + 0x00, 0x53, 0x8c, 0xef, 0x80, 0x51, 0x8a, 0xef, 0x00, 0x21, 0x86, 0xfb, 0x80, 0x21, 0x84, 0xfb, + 0x80, 0x83, 0x8e, 0x6f, 0x00, 0x71, 0x8e, 0x7d, 0x00, 0x70, 0x8e, 0xfd, 0x80, 0x73, 0x86, 0xfb, + 0x80, 0x71, 0x8e, 0xfb, 0x00, 0x00, 0x86, 0xfb, 0x00, 0x30, 0x80, 0xfb, 0x00, 0x01, 0x80, 0x7d, + 0x80, 0x03, 0x80, 0x6f, 0x00, 0x60, 0x8c, 0xfb, 0x80, 0xa5, 0x80, 0x6f, 0x00, 0x00, 0x80, 0xfb, + 0x80, 0x03, 0x8e, 0xef, 0x80, 0x53, 0x8a, 0x7d, 0x80, 0x00, 0x8e, 0xef, 0x80, 0x73, 0x8e, 0x7b, + 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x50, 0x52, 0xe3, 0x00, 0x60, 0x54, 0xe3, 0x00, 0x70, 0x56, 0xe3, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, 0x00, 0x56, 0xa3, + 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, 0x67, + 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, + 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, + 0xa8, 0x8a, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x58, 0x49, 0x20, 0x05, 0x5a, 0x49, + 0x40, 0x05, 0x5c, 0x49, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, 0x00, 0x56, 0xa3, + 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xde, 0xf3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, + 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, + 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, + 0x01, 0xe0, 0x7d, 0x24, 0xf8, 0x8a, 0x00, 0x0a, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xf0, 0x1e, 0xeb, + 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, + 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, + 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x2c, 0x8b, 0x00, 0x8a, 0x00, 0x00, 0x7c, 0x23, + 0x00, 0xe5, 0x95, 0xfd, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe5, 0x95, 0xfd, 0x00, 0x05, 0x40, 0x45, + 0x20, 0x05, 0x42, 0x45, 0x40, 0x05, 0x44, 0x45, 0x00, 0x07, 0x80, 0x6f, 0x00, 0x17, 0x82, 0x6f, + 0x00, 0xc1, 0x98, 0x6f, 0x00, 0xd1, 0x9a, 0x6f, 0x00, 0x06, 0xbc, 0x68, 0xa0, 0x8b, 0x00, 0x0a, + 0x80, 0x16, 0xbc, 0x68, 0xa0, 0x8b, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, + 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x30, 0x7e, 0xc5, 0x00, 0x00, 0xc4, 0x73, + 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xb0, 0x24, 0x00, 0x6c, 0xad, 0xef, + 0x00, 0x7c, 0xaf, 0xef, 0xc8, 0x97, 0x00, 0x82, 0x00, 0x10, 0x53, 0xe3, 0x00, 0x20, 0x55, 0xe3, + 0x00, 0x30, 0x57, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x20, 0x30, 0x7e, 0x45, + 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0x80, 0x30, 0x50, 0x45, + 0x00, 0x10, 0x59, 0xe3, 0x00, 0x20, 0x5b, 0x63, 0x00, 0x30, 0x5d, 0xe3, 0xd8, 0x8a, 0x00, 0x02, + 0x00, 0x00, 0x40, 0xa8, 0x94, 0x8c, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, + 0x00, 0x00, 0x80, 0x68, 0x00, 0x60, 0x53, 0x6f, 0x00, 0x70, 0x55, 0xef, 0x00, 0x80, 0x57, 0x6f, + 0x00, 0x10, 0x59, 0xe3, 0x00, 0x20, 0x5b, 0x63, 0x00, 0x30, 0x5d, 0xe3, 0x80, 0x06, 0x9a, 0xfd, + 0x4c, 0x89, 0x00, 0x82, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, + 0x00, 0x30, 0x7e, 0xc5, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x94, 0x8c, 0x00, 0x0a, + 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0x60, 0x59, 0x63, 0x00, 0x70, 0x5b, 0x63, + 0x00, 0x80, 0x5d, 0x63, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xc0, 0x52, 0xe3, 0x00, 0xd0, 0x54, 0x63, + 0x00, 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0xe0, 0x42, 0xe3, + 0x98, 0x83, 0x00, 0x82, 0x80, 0xc0, 0xac, 0xef, 0x80, 0xd0, 0xae, 0xef, 0x00, 0x00, 0x40, 0x23, + 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x30, 0x40, 0x45, + 0x80, 0x30, 0x42, 0x45, 0x00, 0xa5, 0x86, 0xef, 0x80, 0x35, 0x86, 0x6f, 0x80, 0x94, 0x84, 0x6f, + 0x80, 0x24, 0x84, 0xef, 0x80, 0xb5, 0x88, 0x6f, 0x80, 0x45, 0x8a, 0xef, 0x80, 0x04, 0x80, 0xef, + 0x00, 0x02, 0x80, 0x6f, 0x80, 0x12, 0x82, 0xef, 0x80, 0x00, 0x80, 0x7b, 0x00, 0x01, 0x80, 0x7b, + 0x80, 0x01, 0x80, 0x68, 0x00, 0x00, 0x00, 0x84, 0x60, 0x32, 0x40, 0xc5, 0x00, 0x08, 0x80, 0xe7, + 0x00, 0x08, 0x83, 0xe7, 0x00, 0x10, 0x82, 0xfb, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x10, 0x82, 0xfb, + 0x00, 0x18, 0x82, 0xe7, 0x98, 0x84, 0x00, 0x02, 0x00, 0x10, 0x62, 0x63, 0x01, 0x00, 0x44, 0x23, + 0x00, 0x20, 0x84, 0x70, 0x00, 0x01, 0x84, 0x62, 0x00, 0x00, 0x00, 0x84, 0xc0, 0x32, 0x68, 0xc5, + 0xe0, 0x32, 0x6a, 0xc5, 0xa0, 0x32, 0x6c, 0x45, 0x00, 0x64, 0x8b, 0x67, 0x80, 0x53, 0x8a, 0x7b, + 0x00, 0x66, 0x8d, 0xe7, 0x80, 0x65, 0x8c, 0x7b, 0x00, 0x53, 0x80, 0x67, 0x80, 0x96, 0x82, 0x67, + 0x00, 0x86, 0x84, 0x67, 0x80, 0x54, 0x86, 0xfb, 0x80, 0x66, 0x88, 0xfb, 0x00, 0x32, 0x86, 0xe7, + 0x80, 0x00, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x7d, 0x00, 0x54, 0x88, 0xfb, 0x00, 0x66, 0x8a, 0xfb, + 0x80, 0x42, 0x88, 0x67, 0x00, 0x01, 0x8a, 0x7b, 0x80, 0x42, 0x88, 0xfd, 0x00, 0x94, 0x8a, 0x7b, + 0x00, 0xd6, 0x96, 0xfb, 0x80, 0x55, 0x8a, 0xe7, 0x00, 0x11, 0x96, 0x7b, 0x80, 0x55, 0x8a, 0x7d, + 0x00, 0x42, 0x99, 0xe7, 0x00, 0x51, 0x97, 0xe7, 0x00, 0xb6, 0x98, 0x7b, 0x00, 0x16, 0x96, 0xfd, + 0x00, 0x16, 0x98, 0x7b, 0x00, 0xb6, 0x9a, 0x67, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x82, 0xfb, + 0x00, 0x41, 0x85, 0x67, 0x00, 0x52, 0x89, 0xe7, 0x00, 0x11, 0x82, 0x7b, 0x00, 0x01, 0x84, 0xfd, + 0x00, 0x41, 0x85, 0x67, 0x00, 0x41, 0x88, 0x7b, 0x00, 0x12, 0x80, 0x67, 0x00, 0xd0, 0x9a, 0xfb, + 0x00, 0x52, 0x80, 0xe7, 0x80, 0x35, 0x96, 0x67, 0x00, 0xb0, 0x96, 0xfd, 0x80, 0x30, 0x80, 0xe7, + 0x00, 0x56, 0x98, 0x67, 0x00, 0xc0, 0x98, 0xfb, 0x00, 0x66, 0xad, 0x67, 0x00, 0xbb, 0x96, 0x7d, + 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0x67, 0x00, 0x04, 0x80, 0xe7, 0x60, 0x32, 0x42, 0x45, + 0x80, 0x13, 0x82, 0xe7, 0x00, 0x14, 0x82, 0x7b, 0x00, 0x14, 0x82, 0xe7, 0x80, 0x73, 0x84, 0xe7, + 0x00, 0x11, 0x82, 0x7b, 0x80, 0x13, 0x82, 0xe7, 0x80, 0x00, 0x80, 0xe8, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x74, 0x80, 0xfb, 0x00, 0x95, 0x82, 0x7d, 0x00, 0x10, 0x82, 0x67, 0x00, 0x74, 0x80, 0xfd, + 0x00, 0x95, 0x84, 0x7b, 0x00, 0x20, 0x84, 0x67, 0x00, 0x11, 0x86, 0xfb, 0x80, 0x31, 0x86, 0x67, + 0x00, 0x11, 0x88, 0x7d, 0x00, 0x42, 0x88, 0xe7, 0x00, 0x36, 0x92, 0x67, 0x00, 0xb2, 0x94, 0x67, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x74, 0x82, 0x7b, 0x80, 0x10, 0x82, 0xe7, 0x00, 0x74, 0x84, 0x7d, + 0x00, 0x21, 0x84, 0xe7, 0x00, 0x11, 0x8e, 0xe7, 0x00, 0x11, 0x82, 0x7d, 0x80, 0x60, 0x86, 0xe7, + 0x00, 0x31, 0x86, 0x7b, 0x80, 0x11, 0x90, 0x67, 0x00, 0x00, 0x00, 0x84, 0x80, 0x32, 0x4c, 0x45, + 0x00, 0xb0, 0x52, 0x63, 0x00, 0xc0, 0x54, 0xe3, 0x01, 0x00, 0x4e, 0x23, 0x00, 0x00, 0x50, 0xa3, + 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xf6, 0xf3, 0x00, 0xb0, 0x37, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, + 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, 0x00, 0x02, + 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x78, 0x8e, 0x00, 0x0a, + 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xb0, 0x37, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0x90, 0x4e, 0xe7, + 0x00, 0xa0, 0x50, 0xe7, 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, 0x00, 0x02, 0x00, 0x90, 0x4e, 0xe7, + 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0xa4, 0x8e, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x76, 0x80, 0xe7, 0x00, 0xb4, 0x82, 0xe7, 0x00, 0x86, 0x84, 0x67, 0x60, 0x32, 0x4c, 0xc5, + 0x00, 0x63, 0x86, 0xfb, 0x00, 0x31, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, 0x80, 0x41, 0x88, 0xfb, + 0x80, 0xb3, 0x8a, 0x67, 0x00, 0x51, 0x8a, 0x7b, 0x80, 0x42, 0x88, 0x67, 0x00, 0x31, 0x86, 0xe7, + 0x80, 0x41, 0x88, 0xfd, 0x00, 0x45, 0x88, 0x67, 0x80, 0x00, 0x82, 0xfd, 0x80, 0x10, 0x82, 0xe7, + 0x80, 0x14, 0x82, 0x67, 0x80, 0x40, 0x92, 0xfd, 0x80, 0xd6, 0x86, 0xfb, 0x00, 0x34, 0x86, 0xe7, + 0x00, 0x35, 0x86, 0x67, 0x00, 0x30, 0x8e, 0xe7, 0x00, 0x31, 0x90, 0x67, 0x00, 0x00, 0x00, 0x84, + 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0x00, 0x42, 0xa3, 0x00, 0xe0, 0x45, 0x65, + 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x47, 0xe5, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x49, 0x65, + 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4b, 0xe5, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4d, 0xe5, + 0x00, 0x20, 0x04, 0xf9, 0x00, 0x30, 0x06, 0xf9, 0x00, 0x40, 0x08, 0xf9, 0x00, 0x50, 0x0a, 0xf9, + 0x00, 0x60, 0x0c, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x11, 0x02, 0xfd, 0x80, 0x21, 0x04, 0x7d, + 0x00, 0x32, 0x06, 0xfd, 0x80, 0x42, 0x08, 0x7d, 0x00, 0x53, 0x0a, 0x7d, 0x00, 0x60, 0x0c, 0xf3, + 0x00, 0x00, 0x00, 0x84, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, 0x22, 0x00, 0x40, 0x44, 0xe5, + 0x00, 0x20, 0x04, 0xf5, 0x00, 0x20, 0x2c, 0x63, 0x01, 0x60, 0x6b, 0x22, 0x00, 0x00, 0x42, 0xa3, + 0x04, 0x54, 0xe1, 0x35, 0x88, 0x90, 0x00, 0x9c, 0xff, 0x00, 0x40, 0x23, 0x00, 0x00, 0xa3, 0xe2, + 0x02, 0x10, 0x41, 0x28, 0x94, 0x90, 0x00, 0x8a, 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0x21, 0xf5, + 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0xa3, 0xe2, 0x00, 0x20, 0x84, 0x62, 0x00, 0x11, 0x41, 0xe8, + 0xa0, 0x90, 0x00, 0x0a, 0x05, 0x54, 0xf3, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x00, 0x03, 0x72, 0xc9, + 0x05, 0x54, 0xc1, 0x39, 0x88, 0x90, 0x00, 0x9c, 0x00, 0x60, 0x6b, 0xe3, 0x00, 0x54, 0xf5, 0xb5, + 0x88, 0x90, 0x00, 0x9c, 0x01, 0x54, 0xef, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x02, 0x54, 0xfb, 0xb5, + 0x88, 0x90, 0x00, 0x9c, 0x03, 0x54, 0xfd, 0x35, 0x88, 0x90, 0x00, 0x9c, 0x05, 0x54, 0xc1, 0x39, + 0x88, 0x90, 0x00, 0x9c, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, + 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, 0x00, 0xd0, 0xbb, 0xfb, 0x00, 0x00, 0xc4, 0x73, + 0x00, 0x71, 0xaf, 0xe8, 0x00, 0xe1, 0xbd, 0xe8, 0x00, 0x7f, 0xa9, 0x68, 0xe0, 0x03, 0x74, 0x49, + 0x00, 0x04, 0x7a, 0xc9, 0xa0, 0x00, 0x60, 0xc5, 0x00, 0x00, 0x21, 0xf9, 0xc0, 0x00, 0x62, 0x45, + 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x05, 0x54, 0xc1, 0x39, + 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x12, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, + 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x00, 0x84, 0x6c, 0x90, 0x00, 0x82, 0xf2, 0x00, 0x40, 0xa3, + 0x94, 0x81, 0x00, 0x98, 0x6c, 0x90, 0x00, 0x82, 0xf4, 0x00, 0x40, 0xa3, 0x94, 0x81, 0x00, 0x98, + 0x6c, 0x90, 0x00, 0x82, 0xf6, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x00, 0x00, 0xce, 0x73, + 0x00, 0x00, 0xd0, 0x73, 0x00, 0x00, 0xd2, 0xf3, 0x00, 0x00, 0xd4, 0xf3, 0x00, 0x70, 0xc0, 0xe3, + 0x0c, 0x40, 0xc1, 0xa5, 0x4c, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x40, 0x23, + 0x94, 0x81, 0x00, 0x98, 0x30, 0x8f, 0x00, 0x02, 0x08, 0x00, 0x56, 0x23, 0x12, 0x00, 0x58, 0x23, + 0x78, 0x8f, 0x00, 0x02, 0x01, 0xc0, 0x58, 0x24, 0xe0, 0x90, 0x00, 0x8a, 0x00, 0x10, 0xc0, 0xe9, + 0x01, 0xb0, 0x56, 0x24, 0xdc, 0x90, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, + 0x94, 0x81, 0x00, 0x98, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, 0x30, 0x8f, 0x00, 0x02, + 0x80, 0x00, 0x5e, 0xa3, 0x00, 0xf0, 0x1e, 0xf3, 0x00, 0xf0, 0x1e, 0xf3, 0x00, 0xf0, 0x1e, 0xf3, + 0x12, 0xb0, 0x56, 0xa4, 0x80, 0xb7, 0xa0, 0x62, 0x44, 0x91, 0x00, 0x8a, 0x12, 0x00, 0x58, 0x23, + 0x78, 0x8f, 0x00, 0x02, 0x01, 0xc0, 0x58, 0x24, 0x30, 0x91, 0x00, 0x8a, 0x00, 0x10, 0xc0, 0xe9, + 0x20, 0x91, 0x00, 0x18, 0x12, 0xb0, 0x56, 0xa2, 0x88, 0x91, 0x00, 0x08, 0x12, 0x00, 0x58, 0x23, + 0x80, 0xc5, 0x58, 0xe4, 0x78, 0x8f, 0x00, 0x02, 0x01, 0xb0, 0x56, 0x24, 0x54, 0x91, 0x00, 0x0a, + 0x01, 0xc0, 0x40, 0x28, 0x9c, 0x91, 0x00, 0x08, 0x04, 0x00, 0x44, 0x23, 0x00, 0x20, 0x04, 0xf5, + 0x00, 0x11, 0x02, 0xfd, 0x00, 0x20, 0x04, 0xf3, 0x01, 0xc0, 0x58, 0x24, 0x70, 0x91, 0x00, 0x0a, + 0x80, 0x10, 0x82, 0x24, 0xac, 0x91, 0x00, 0x98, 0x00, 0x00, 0x42, 0xa3, 0x8a, 0x00, 0x46, 0xa3, + 0x80, 0x11, 0xc2, 0xe2, 0x80, 0x10, 0x82, 0x24, 0xac, 0x91, 0x00, 0x98, 0x84, 0x00, 0x44, 0xa3, + 0x00, 0x20, 0x04, 0xf5, 0x00, 0x11, 0x02, 0xfd, 0xac, 0x91, 0x00, 0x98, 0x00, 0x10, 0xc0, 0xe9, + 0x00, 0x00, 0xf6, 0x71, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x70, 0xce, 0xeb, 0x00, 0x70, 0xd2, 0x6b, + 0x00, 0x70, 0xc0, 0xe3, 0x0c, 0xb0, 0xc1, 0xa5, 0x04, 0x00, 0x42, 0x23, 0x11, 0x00, 0x7c, 0x23, + 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xd0, 0x91, 0x00, 0x0a, 0x80, 0x10, 0x82, 0x24, + 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf8, 0xf1, 0x60, 0x31, 0x7e, 0x45, 0x80, 0xcd, 0xb7, 0xf9, + 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x40, 0x31, 0x7e, 0xc5, + 0xc0, 0x31, 0x6a, 0x45, 0xe0, 0x31, 0x6c, 0xc5, 0xdc, 0x87, 0x00, 0x02, 0x01, 0x00, 0x42, 0x23, + 0x80, 0x50, 0xab, 0xe2, 0x00, 0x50, 0x2b, 0xed, 0x80, 0x6a, 0xad, 0xe4, 0x00, 0x60, 0x2d, 0xf9, + 0x20, 0x03, 0x6c, 0x49, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x58, 0x81, 0x00, 0x02, + 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x6b, 0x65, 0x00, 0x50, 0x2b, 0xf9, 0x20, 0xe0, 0x7d, 0x22, + 0x00, 0xe0, 0x69, 0xe5, 0x00, 0x40, 0x29, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x67, 0x65, + 0x00, 0x30, 0x27, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x20, 0x25, 0xf9, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x4c, 0x23, 0x00, 0x60, 0x8a, 0x70, 0x60, 0xb0, 0x92, 0x22, + 0x1f, 0xb0, 0x90, 0x22, 0x20, 0x00, 0x4e, 0x23, 0x00, 0x74, 0x50, 0xe4, 0x00, 0x80, 0x4e, 0xe3, + 0x00, 0x70, 0x0e, 0x63, 0x00, 0x70, 0x0e, 0x63, 0x00, 0x70, 0x0e, 0x63, 0x01, 0x70, 0x4e, 0x24, + 0x00, 0x53, 0x0a, 0x7d, 0x01, 0x80, 0x50, 0x24, 0x90, 0x92, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, + 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, + 0x00, 0xe0, 0x67, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, + 0x00, 0x20, 0x25, 0xf9, 0x00, 0x03, 0x68, 0x45, 0x20, 0x03, 0x6a, 0x45, 0x40, 0xb0, 0x7a, 0xa2, + 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0x00, 0xc0, 0x2d, + 0x64, 0x92, 0x00, 0x82, 0x20, 0x90, 0x40, 0x28, 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, 0xe3, + 0xac, 0x93, 0x00, 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x67, 0x65, + 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x20, 0x25, 0xf9, + 0x00, 0x03, 0x68, 0x45, 0x20, 0x03, 0x6a, 0x45, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x20, 0xe1, 0x6b, + 0x80, 0x00, 0x7a, 0xa3, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, + 0x2c, 0x92, 0x00, 0x82, 0x00, 0x20, 0xe1, 0x6b, 0x80, 0xd0, 0x7b, 0x22, 0x00, 0x00, 0x40, 0x23, + 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, + 0x80, 0xd5, 0x7b, 0xe2, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, + 0x2c, 0x92, 0x00, 0x82, 0x80, 0xb0, 0x40, 0xa8, 0xdc, 0x93, 0x00, 0x08, 0x64, 0x92, 0x00, 0x82, + 0x60, 0x90, 0x40, 0xa8, 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, 0xe3, 0x40, 0x90, 0x40, 0x28, + 0xac, 0x93, 0x00, 0x88, 0x00, 0x00, 0x66, 0xa3, 0x20, 0x90, 0x40, 0x28, 0xa0, 0x93, 0x00, 0x88, + 0x00, 0x00, 0x68, 0x23, 0x80, 0x52, 0xab, 0x62, 0x80, 0x53, 0xeb, 0x62, 0xf8, 0x93, 0x00, 0x98, + 0x80, 0x42, 0xa9, 0x62, 0x80, 0x43, 0xe9, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x32, 0xa7, 0x62, + 0x80, 0x33, 0xe7, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x22, 0xa5, 0x62, 0x80, 0x23, 0xe5, 0x62, + 0x10, 0xb0, 0x90, 0x22, 0xd0, 0x93, 0x00, 0x8a, 0x80, 0x2e, 0xa5, 0x64, 0xf8, 0x93, 0x00, 0x98, + 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x6a, 0xa3, 0xec, 0x93, 0x00, 0x98, 0x00, 0x20, 0xe1, 0x6b, + 0x00, 0x00, 0x6a, 0xa3, 0xff, 0x00, 0x4e, 0xa3, 0x80, 0x53, 0xeb, 0x62, 0x00, 0x00, 0x68, 0x23, + 0x00, 0x00, 0x66, 0xa3, 0x00, 0xd0, 0x65, 0xe3, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x20, 0xe1, 0x6b, + 0x00, 0x00, 0x21, 0xf9, 0x00, 0x10, 0x23, 0xf9, 0x80, 0x08, 0xb3, 0x79, 0x00, 0x00, 0x40, 0x23, + 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x60, 0x31, 0x7e, 0x45, 0xe0, 0x03, 0x74, 0x45, + 0x00, 0x04, 0x44, 0x45, 0x80, 0xac, 0x83, 0xff, 0x80, 0x2c, 0x84, 0xff, 0x80, 0xb0, 0x87, 0x7b, + 0x00, 0x31, 0x86, 0x7b, 0x40, 0x03, 0x46, 0xc9, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, + 0x00, 0x03, 0x58, 0x45, 0x00, 0xc0, 0x18, 0xf9, 0x10, 0x85, 0x00, 0x82, 0x00, 0x10, 0xbc, 0x28, + 0x10, 0x95, 0x00, 0x8a, 0x01, 0x00, 0x5a, 0x23, 0x00, 0xb6, 0x9c, 0x67, 0x00, 0x90, 0x79, 0xe3, + 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x4e, 0xc9, 0x80, 0x03, 0x50, 0x49, 0xa0, 0x03, 0x52, 0x49, + 0xc0, 0x03, 0x54, 0x49, 0x40, 0x03, 0x78, 0x45, 0xc0, 0x31, 0x56, 0x45, 0xe0, 0x31, 0x58, 0x45, + 0x01, 0x00, 0x5a, 0x23, 0x00, 0xb6, 0x9c, 0x67, 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x56, 0xc5, + 0x80, 0x03, 0x58, 0xc5, 0xa0, 0x03, 0x5a, 0xc5, 0xc0, 0x03, 0x5c, 0xc5, 0x00, 0x00, 0x40, 0x23, + 0x80, 0x05, 0x96, 0xfd, 0x00, 0x07, 0x9c, 0xfd, 0x18, 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, 0xe3, + 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0xe4, 0x84, 0x00, 0x82, 0x64, 0x81, 0x00, 0x02, + 0x00, 0x00, 0x7c, 0xa2, 0x20, 0x03, 0x48, 0x45, 0xff, 0x0f, 0x7e, 0xa3, 0x00, 0xf0, 0x41, 0x28, + 0x00, 0x82, 0x84, 0xe8, 0x18, 0x95, 0x00, 0x0a, 0x00, 0xf0, 0x41, 0x28, 0x00, 0x82, 0x84, 0xe8, + 0x18, 0x95, 0x00, 0x0a, 0xc3, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x10, 0x00, 0x7c, 0x22, + 0x40, 0x03, 0x4a, 0xc5, 0x00, 0x40, 0x08, 0xf9, 0x00, 0xe0, 0x49, 0x69, 0x20, 0xe0, 0x7d, 0x22, + 0x00, 0xe0, 0x4b, 0xe9, 0x00, 0x00, 0x40, 0x23, 0x50, 0x00, 0x42, 0xa3, 0x2c, 0x95, 0x00, 0x98, + 0x36, 0x00, 0x40, 0x23, 0x1c, 0x95, 0x00, 0x98, 0x36, 0x00, 0x40, 0x23, 0x3c, 0x00, 0x44, 0xa3, + 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, 0x42, 0x23, 0x2c, 0x95, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, + 0xd0, 0xa3, 0x00, 0x02, 0x94, 0x81, 0x00, 0x98, 0x00, 0x00, 0x8c, 0x67, 0x00, 0x63, 0x8c, 0xfb, + 0x01, 0x00, 0x7c, 0xa3, 0x00, 0x6f, 0x8e, 0x7b, 0x00, 0x70, 0xbc, 0x28, 0x6c, 0x96, 0x00, 0x88, + 0x60, 0x32, 0x50, 0x45, 0x00, 0x00, 0x7c, 0x23, 0x00, 0xe4, 0x93, 0x7d, 0x00, 0x83, 0x90, 0x67, + 0x80, 0x73, 0x94, 0x67, 0x80, 0xa3, 0x96, 0x67, 0x80, 0x84, 0x90, 0x67, 0x00, 0x85, 0x90, 0xfb, + 0x80, 0x84, 0x90, 0x67, 0x80, 0xb5, 0x98, 0x67, 0x00, 0xc6, 0x94, 0x67, 0x80, 0xc5, 0x98, 0xe7, + 0x00, 0xc4, 0x98, 0xe7, 0x00, 0xa6, 0x94, 0x67, 0x00, 0xa0, 0x42, 0x63, 0xac, 0x83, 0x00, 0x02, + 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x25, 0x9a, 0x67, 0x00, 0xd6, 0x9a, 0x67, + 0x00, 0x32, 0x7c, 0xc5, 0x00, 0xdf, 0x9c, 0x67, 0x80, 0xd6, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, + 0x00, 0xa4, 0x88, 0x68, 0xc0, 0x95, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, 0xc8, 0x95, 0x00, 0x98, + 0x00, 0xe0, 0x42, 0xe3, 0xc8, 0x95, 0x00, 0x98, 0x00, 0x93, 0x84, 0xe7, 0x00, 0xd0, 0x86, 0xe7, + 0x01, 0xe0, 0x89, 0xa4, 0x00, 0x32, 0x86, 0xe7, 0x00, 0x3f, 0x88, 0xe7, 0x00, 0x83, 0x8c, 0xe7, + 0x80, 0x31, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa3, 0xbc, 0xfd, 0x00, 0xe0, 0xbd, 0xa8, + 0xfc, 0x95, 0x00, 0x0a, 0x00, 0x30, 0x40, 0xe3, 0x04, 0x96, 0x00, 0x98, 0x00, 0x40, 0x40, 0x63, + 0x04, 0x96, 0x00, 0x98, 0x80, 0x10, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa4, 0xbc, 0x7d, + 0x00, 0xe0, 0xbd, 0xa8, 0x20, 0x96, 0x00, 0x8a, 0x00, 0x90, 0x46, 0xe3, 0x28, 0x96, 0x00, 0x18, + 0x00, 0x20, 0x46, 0x63, 0x28, 0x96, 0x00, 0x18, 0x38, 0x96, 0x00, 0x8a, 0x00, 0x10, 0x44, 0xe3, + 0x01, 0x00, 0x7c, 0xa3, 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, 0x44, 0x63, 0x00, 0x00, 0x7c, 0x23, + 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, 0x40, 0x23, 0x00, 0x01, 0x82, 0xfd, 0x01, 0x00, 0x50, 0x23, + 0x00, 0x24, 0x8c, 0x62, 0x00, 0xe3, 0xbd, 0x68, 0x64, 0x96, 0x00, 0x08, 0x00, 0x10, 0x56, 0xe3, + 0x6c, 0x96, 0x00, 0x18, 0x00, 0x20, 0x56, 0xe3, 0x6c, 0x96, 0x00, 0x18, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, 0x02, + 0x00, 0x70, 0xbc, 0x28, 0x70, 0x96, 0x00, 0x08, 0x80, 0xb3, 0x9a, 0xe7, 0x00, 0x30, 0x56, 0x63, + 0x00, 0x70, 0x58, 0x63, 0x00, 0x00, 0x00, 0x84, 0x40, 0x31, 0x7e, 0xc5, 0x00, 0x05, 0x42, 0xc5, + 0x00, 0x00, 0xc4, 0x73, 0xb4, 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, 0x02, 0x00, 0x70, 0xbc, 0x28, + 0x98, 0x96, 0x00, 0x08, 0x00, 0x33, 0x7c, 0x45, 0x00, 0x3f, 0x94, 0x67, 0x80, 0x75, 0x9a, 0xe7, + 0x80, 0x33, 0x98, 0x7d, 0x80, 0x33, 0x9c, 0xfb, 0x00, 0xd7, 0x80, 0x67, 0x00, 0x00, 0xbc, 0xa8, + 0x98, 0x96, 0x00, 0x08, 0x00, 0xa7, 0x96, 0x67, 0x80, 0xc6, 0x98, 0xe7, 0x00, 0xb6, 0x9c, 0x67, + 0x00, 0xb0, 0x96, 0x67, 0x00, 0xc0, 0x98, 0x67, 0x00, 0x00, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x08, 0x8d, 0xef, 0x00, 0x06, 0x8f, 0xef, 0x80, 0x63, 0x8c, 0x6f, 0x00, 0x60, 0x42, 0x63, + 0xa4, 0x82, 0x00, 0x02, 0x00, 0x30, 0x52, 0xe3, 0x80, 0x93, 0x92, 0x6f, 0x00, 0x31, 0x40, 0xc5, + 0x00, 0x90, 0x94, 0xef, 0x80, 0x94, 0x90, 0x6f, 0x00, 0x88, 0x90, 0x6f, 0x00, 0x86, 0x80, 0xe8, + 0x00, 0x90, 0x54, 0xef, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x68, 0xe3, 0x20, 0x31, 0x40, 0x45, + 0x60, 0x30, 0x42, 0xc5, 0x80, 0x30, 0x44, 0x45, 0x00, 0x4a, 0x97, 0x6f, 0x80, 0x05, 0x96, 0xef, + 0x80, 0xb5, 0x98, 0xef, 0x80, 0xc5, 0x98, 0x7b, 0x01, 0x00, 0x48, 0x23, 0x00, 0xc2, 0x9a, 0xfb, + 0x80, 0x26, 0x9a, 0x6f, 0x00, 0x00, 0x48, 0xa3, 0x00, 0x46, 0x9c, 0xfd, 0x00, 0xc0, 0x80, 0xa8, + 0x00, 0xe0, 0x40, 0x6f, 0x00, 0x17, 0x9c, 0x6f, 0x80, 0xd6, 0x98, 0xef, 0x00, 0xe7, 0xa0, 0x6f, + 0x00, 0x18, 0x9e, 0xef, 0x80, 0xc7, 0x98, 0xfb, 0x80, 0xc6, 0x98, 0x6f, 0x00, 0x07, 0xa1, 0x6f, + 0x00, 0x28, 0x9e, 0xef, 0x80, 0xc7, 0x98, 0xfb, 0x80, 0xb6, 0xa2, 0xef, 0xf0, 0x96, 0x00, 0x82, + 0x00, 0xba, 0xa4, 0x6f, 0x00, 0x25, 0xa5, 0xef, 0x00, 0xd0, 0x62, 0x6f, 0x00, 0xa0, 0x64, 0xef, + 0x00, 0x00, 0x42, 0xa3, 0x00, 0x19, 0x82, 0xfd, 0x00, 0x49, 0x81, 0x68, 0x01, 0x00, 0x44, 0x23, + 0x00, 0x01, 0x80, 0xe2, 0x00, 0x10, 0x64, 0x6f, 0x00, 0x10, 0x64, 0x63, 0x00, 0x27, 0xa5, 0x6f, + 0x00, 0xe0, 0x66, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x42, 0xc5, 0x00, 0x00, 0xc4, 0x73, + 0xb4, 0xa3, 0x00, 0x82, 0x28, 0x97, 0x00, 0x02, 0x00, 0x30, 0xbd, 0x28, 0xc8, 0x97, 0x00, 0x88, + 0x00, 0x00, 0x00, 0x84, 0x20, 0x30, 0x7e, 0x45, 0x60, 0x10, 0x40, 0x28, 0x18, 0x98, 0x00, 0x08, + 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x66, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x00, 0x68, 0x23, + 0x80, 0x49, 0xb9, 0x79, 0x80, 0xc9, 0x83, 0xe8, 0xb4, 0x99, 0x00, 0x0a, 0x00, 0xc0, 0x83, 0xa8, + 0xb4, 0x99, 0x00, 0x88, 0x2c, 0x98, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, 0x00, 0x00, 0xe8, 0xf3, + 0x80, 0x49, 0xb9, 0x79, 0x00, 0xc0, 0x83, 0xa8, 0xb4, 0x99, 0x00, 0x88, 0x00, 0x00, 0xc0, 0xf3, + 0x00, 0x00, 0xc2, 0x73, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x00, 0xc6, 0xf3, 0x00, 0x00, 0xc0, 0x63, + 0x0a, 0xc0, 0xc1, 0x25, 0x04, 0x00, 0x44, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x04, 0xf3, + 0x01, 0xe0, 0x7d, 0x24, 0x4c, 0x98, 0x00, 0x0a, 0x80, 0x20, 0x84, 0x24, 0x00, 0x20, 0xc0, 0xe9, + 0x00, 0x00, 0xfa, 0x71, 0x20, 0x01, 0x78, 0xc9, 0x40, 0x01, 0x7a, 0x49, 0x20, 0x30, 0x7e, 0x45, + 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xcf, 0xf9, 0xff, 0x00, 0x30, 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, + 0xc0, 0x30, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, + 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x9c, 0xa4, 0x00, 0xc7, 0x98, 0x6f, 0x00, 0xd7, 0x9a, 0x6f, + 0x00, 0xc0, 0x52, 0xe3, 0x00, 0xd0, 0x54, 0x63, 0x00, 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, + 0xc0, 0x99, 0x00, 0x0a, 0x80, 0x30, 0x50, 0x45, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, + 0xc0, 0x99, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0xc0, 0x99, 0x00, 0x0a, 0x00, 0xb0, 0x42, 0xe3, + 0x98, 0x83, 0x00, 0x82, 0x80, 0x90, 0x92, 0x6f, 0x80, 0xa0, 0x94, 0x6f, 0x00, 0x90, 0x19, 0x6d, + 0x00, 0xc0, 0x18, 0xf3, 0xaa, 0xc0, 0x98, 0xa4, 0x00, 0xc0, 0x18, 0xf3, 0x00, 0x01, 0x40, 0xc5, + 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0xa8, 0xe2, 0x60, 0x40, 0x41, 0xa8, 0x08, 0x99, 0x00, 0x08, + 0x02, 0xc0, 0x98, 0x24, 0x0c, 0x99, 0x00, 0x18, 0x01, 0xc0, 0x98, 0x24, 0x00, 0xc0, 0x18, 0xf3, + 0x01, 0xc0, 0x98, 0x24, 0x04, 0xa4, 0xd9, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xd3, 0xb7, + 0xb4, 0x99, 0x00, 0x9c, 0x06, 0xa4, 0xd5, 0xb7, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, + 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, 0x00, 0x9c, 0x20, 0x01, 0x78, 0xc5, + 0x40, 0x01, 0x7a, 0x45, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, + 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xc0, 0xb9, 0xfd, 0x00, 0x00, 0xc4, 0x73, 0x00, 0xd1, 0xbb, 0xe8, + 0x00, 0x90, 0x75, 0xe3, 0xff, 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, + 0x80, 0xc4, 0x94, 0x68, 0x00, 0xa4, 0xf9, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, + 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x03, 0xa4, 0xc5, 0x37, + 0xb4, 0x99, 0x00, 0x9c, 0x04, 0xa4, 0xd5, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, + 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, + 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, + 0x05, 0xa4, 0xc1, 0x39, 0x41, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x10, 0x40, 0x28, + 0xe0, 0x99, 0x00, 0x08, 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x66, 0xe5, 0xe4, 0x99, 0x00, 0x18, + 0x00, 0x00, 0xe6, 0x73, 0x01, 0x00, 0x64, 0xa3, 0x00, 0x20, 0x25, 0xed, 0x00, 0x00, 0x62, 0x23, + 0x00, 0x01, 0x60, 0x23, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xf9, 0xeb, + 0x00, 0xd0, 0x3b, 0xf9, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, + 0x00, 0x00, 0x80, 0x70, 0x80, 0x0e, 0xba, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0xd0, 0xfb, 0x62, + 0x00, 0xc0, 0x39, 0xf9, 0x20, 0x01, 0x7a, 0x49, 0x40, 0x01, 0x78, 0xc9, 0x00, 0x00, 0xfc, 0xf3, + 0x60, 0x31, 0x7e, 0x45, 0x00, 0xdf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xc0, 0x31, 0x56, 0x45, + 0xe0, 0x31, 0x58, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, + 0x01, 0x00, 0x9a, 0xa4, 0x80, 0xb6, 0x96, 0xe7, 0x00, 0xb6, 0x9c, 0x67, 0x80, 0xc6, 0x98, 0xe7, + 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, + 0x00, 0xe0, 0x54, 0x63, 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, 0xf0, 0x86, 0x00, 0x02, + 0x00, 0x00, 0x40, 0xa8, 0x70, 0x9b, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, + 0xe4, 0x84, 0x00, 0x82, 0x00, 0x90, 0x15, 0x6d, 0x00, 0xa0, 0x14, 0xf3, 0xaa, 0xa0, 0x94, 0xa4, + 0x00, 0xa0, 0x14, 0xf3, 0x00, 0x01, 0x40, 0xc5, 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0x92, 0xe2, + 0x60, 0x90, 0x40, 0xa8, 0xc0, 0x9a, 0x00, 0x88, 0x02, 0xa0, 0x94, 0x24, 0xc4, 0x9a, 0x00, 0x98, + 0x01, 0xa0, 0x94, 0x24, 0x00, 0xa0, 0x14, 0xf3, 0x02, 0xa0, 0x94, 0x24, 0x04, 0xa4, 0xd5, 0x37, + 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xd1, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, + 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0x9b, 0x00, 0x9c, 0x20, 0x01, 0x78, 0xc5, + 0x40, 0x01, 0x7a, 0x45, 0x00, 0x00, 0x40, 0x23, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x0e, 0xbc, 0xf9, + 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x80, 0x24, + 0x00, 0xe0, 0xb9, 0x7d, 0x00, 0x00, 0xc4, 0x73, 0x00, 0xd1, 0xbb, 0xe8, 0x00, 0x90, 0x75, 0xe3, + 0xff, 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, 0x80, 0xa4, 0x94, 0x68, + 0x00, 0xa4, 0xf9, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, 0x7c, 0x9b, 0x00, 0x9c, + 0x02, 0xa4, 0xc1, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x03, 0xa4, 0xc5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, + 0x04, 0xa4, 0xd5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0x7c, 0x9b, 0x00, 0x9c, + 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0x9b, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, + 0x05, 0xa4, 0xc1, 0x39, 0x41, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, + 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xc6, 0xf3, 0x00, 0x00, 0xc8, 0x73, + 0x00, 0x00, 0xca, 0xf3, 0x00, 0x00, 0xcc, 0xf3, 0x00, 0x30, 0xc0, 0x63, 0x0b, 0x40, 0xc1, 0x25, + 0x4c, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x43, 0x63, + 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xb0, 0x9b, 0x00, 0x0a, + 0x00, 0x00, 0xc0, 0x69, 0x0e, 0x00, 0x7c, 0xa3, 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, + 0x01, 0xe0, 0x7d, 0x24, 0xc8, 0x9b, 0x00, 0x0a, 0x04, 0x00, 0x7c, 0xa3, 0x00, 0x00, 0x42, 0xa3, + 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xe0, 0x9b, 0x00, 0x0a, + 0x1a, 0x00, 0x7c, 0xa3, 0x00, 0x0f, 0xc0, 0xe2, 0x80, 0x00, 0x80, 0x24, 0x00, 0x00, 0xc0, 0x69, + 0x00, 0x00, 0xf6, 0x71, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x30, 0xc6, 0xeb, 0x00, 0x30, 0xca, 0xeb, + 0x00, 0x30, 0xc0, 0x63, 0x0b, 0xb0, 0xc1, 0x25, 0x04, 0x00, 0x42, 0x23, 0x11, 0x00, 0x7c, 0x23, + 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x20, 0x9c, 0x00, 0x8a, 0x80, 0x10, 0x82, 0x24, + 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf8, 0xf1, 0x20, 0x01, 0x64, 0x49, 0x20, 0x30, 0x7e, 0x45, + 0x80, 0xcd, 0xb7, 0xf9, 0x00, 0xb0, 0x81, 0xa8, 0xdc, 0x9d, 0x00, 0x88, 0xa0, 0x30, 0x6c, 0xc5, + 0xc0, 0x30, 0x6e, 0x45, 0xa8, 0x8b, 0x00, 0x02, 0x00, 0x00, 0x46, 0xe3, 0x00, 0x00, 0x40, 0xa8, + 0xfc, 0x9d, 0x00, 0x8a, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x0b, 0xac, 0x79, + 0x00, 0x60, 0x81, 0x28, 0xe4, 0x9d, 0x00, 0x08, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, + 0xb4, 0xa3, 0x00, 0x82, 0x00, 0x00, 0x72, 0x63, 0x01, 0x90, 0xb3, 0x24, 0x80, 0x9d, 0x83, 0x7f, + 0xa8, 0x81, 0x00, 0x02, 0x20, 0x01, 0x64, 0x45, 0x80, 0x2c, 0x95, 0xff, 0x80, 0x6c, 0x97, 0xff, + 0x80, 0xa5, 0x99, 0x7f, 0x80, 0x55, 0x9b, 0xff, 0x80, 0xc6, 0x96, 0xfb, 0x80, 0xa5, 0x94, 0x7b, + 0x00, 0x15, 0x94, 0xff, 0x00, 0xa0, 0x80, 0xa8, 0xec, 0x9d, 0x00, 0x88, 0x40, 0x01, 0x54, 0x49, + 0x00, 0xa0, 0x42, 0x63, 0xa8, 0x81, 0x00, 0x02, 0x80, 0x20, 0xb9, 0x7f, 0x80, 0x60, 0xb7, 0x7f, + 0x00, 0x30, 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, 0xc0, 0x30, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, + 0x94, 0x8a, 0x00, 0x82, 0x00, 0x90, 0x5e, 0xe3, 0x00, 0xa0, 0x60, 0x63, 0x00, 0xb0, 0x62, 0x63, + 0x60, 0x01, 0x58, 0xc5, 0x80, 0x01, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0xb0, 0x79, 0x63, + 0x94, 0x8a, 0x00, 0x82, 0x80, 0xf5, 0x84, 0xef, 0x80, 0x98, 0x86, 0xef, 0x80, 0x21, 0x80, 0xe8, + 0x38, 0x9d, 0x00, 0x0a, 0x80, 0x05, 0x85, 0x6f, 0x80, 0xa8, 0x86, 0xef, 0x80, 0x21, 0x80, 0xe8, + 0xf4, 0x9d, 0x00, 0x0a, 0xfc, 0x89, 0x00, 0x02, 0x00, 0x90, 0x58, 0xe3, 0x00, 0xa0, 0x5a, 0x63, + 0x00, 0xb0, 0x5c, 0xe3, 0x48, 0x9d, 0x00, 0x98, 0x00, 0xf0, 0x58, 0xe3, 0x00, 0x00, 0x5b, 0xe3, + 0x00, 0x10, 0x5d, 0x63, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, + 0x80, 0xc0, 0x98, 0x6f, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x06, 0x98, 0x79, + 0x00, 0x00, 0x7e, 0xa3, 0x00, 0xf0, 0x41, 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, 0x9d, 0x00, 0x0a, + 0x00, 0xf0, 0x41, 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, 0x9d, 0x00, 0x0a, 0x00, 0x00, 0x46, 0x23, + 0xc3, 0x00, 0x44, 0xa3, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x45, 0x69, + 0x00, 0x30, 0x40, 0xa8, 0x01, 0x00, 0x42, 0x23, 0xbc, 0x9d, 0x00, 0x0a, 0x50, 0x00, 0x42, 0xa3, + 0x10, 0x00, 0x7c, 0x22, 0x00, 0x60, 0x2d, 0xf9, 0x00, 0xe0, 0x6d, 0x69, 0x20, 0xe0, 0x7d, 0x22, + 0x40, 0x01, 0x54, 0x45, 0x00, 0xa0, 0x14, 0xf9, 0x00, 0xe0, 0x55, 0xe9, 0x00, 0x30, 0x40, 0xe3, + 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x76, 0x23, + 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x94, 0x81, 0x00, 0x98, 0x21, 0x00, 0x46, 0x23, + 0xfc, 0x9d, 0x00, 0x98, 0x22, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, 0x23, 0x00, 0x46, 0xa3, + 0xfc, 0x9d, 0x00, 0x98, 0x24, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, 0x3c, 0x00, 0x44, 0xa3, + 0x01, 0x00, 0x42, 0x23, 0x84, 0x9d, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x40, 0x31, 0x7e, 0xc5, + 0x00, 0x00, 0x40, 0x23, 0x00, 0x08, 0x80, 0xf9, 0x00, 0x08, 0x80, 0xe8, 0xdc, 0x9e, 0x00, 0x0a, + 0xd8, 0x8c, 0x00, 0x02, 0xdc, 0x9e, 0x00, 0x0a, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, + 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xa4, 0x24, 0x00, 0x09, 0xa1, 0x67, 0x00, 0x19, 0xa3, 0x67, + 0x00, 0x00, 0xfc, 0xf3, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x3f, 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, + 0x70, 0x96, 0x00, 0x02, 0x5c, 0x8e, 0x00, 0x82, 0xd0, 0x8e, 0x00, 0x02, 0x00, 0x70, 0x6e, 0x63, + 0x00, 0x80, 0x70, 0x63, 0x00, 0x90, 0x72, 0x63, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, + 0x00, 0x00, 0x4f, 0xe3, 0x00, 0x20, 0x51, 0x63, 0x00, 0x10, 0x53, 0xe3, 0x0c, 0x8d, 0x00, 0x82, + 0x00, 0x00, 0xfc, 0xf3, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x3f, 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, + 0x5c, 0x8e, 0x00, 0x82, 0xd0, 0x8e, 0x00, 0x02, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, + 0x00, 0x00, 0x40, 0x23, 0x80, 0x04, 0x92, 0xfd, 0x00, 0x70, 0x57, 0x63, 0x00, 0x80, 0x59, 0xe3, + 0x00, 0x90, 0x5b, 0xe3, 0x0c, 0x8d, 0x00, 0x82, 0x00, 0xc0, 0x42, 0x63, 0x74, 0x84, 0x00, 0x82, + 0x80, 0xb0, 0x96, 0xe7, 0x80, 0xd0, 0x9a, 0xe7, 0x01, 0x00, 0x58, 0xa3, 0xd4, 0x8d, 0x00, 0x82, + 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x12, 0x00, 0x40, 0x23, + 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0xa8, 0xa4, 0x00, 0x18, + 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, 0x22, 0x00, 0x40, 0x48, 0xe5, 0xff, 0x00, 0x44, 0xa3, + 0x00, 0x41, 0x82, 0xe2, 0x00, 0x40, 0x32, 0xf5, 0x00, 0x90, 0x09, 0xf5, 0x00, 0x40, 0x08, 0xf5, + 0x00, 0x91, 0xb3, 0xe2, 0x00, 0x41, 0x88, 0xe2, 0x00, 0x00, 0x00, 0x84, 0xf0, 0x9e, 0x00, 0x02, + 0x00, 0x90, 0x33, 0x63, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x01, 0x90, 0x75, 0x22, + 0x04, 0xa4, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x02, 0x40, 0x40, 0xa8, 0x54, 0x9f, 0x00, 0x08, + 0x01, 0x40, 0x40, 0xa8, 0x70, 0x9f, 0x00, 0x08, 0xf4, 0x00, 0x46, 0xa3, 0x3c, 0x00, 0x44, 0xa3, + 0x8c, 0x9f, 0x00, 0x98, 0xcc, 0x99, 0x00, 0x82, 0x00, 0x30, 0x40, 0xa8, 0x68, 0x9f, 0x00, 0x08, + 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xc3, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, + 0xe4, 0x97, 0x00, 0x02, 0x00, 0x30, 0x40, 0xa8, 0x84, 0x9f, 0x00, 0x88, 0x3c, 0x00, 0x44, 0xa3, + 0x8c, 0x9f, 0x00, 0x98, 0xc3, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0x64, 0x81, 0x00, 0x02, + 0x00, 0x00, 0x40, 0xa2, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x44, 0x69, 0x00, 0x30, 0x40, 0xe3, + 0x00, 0xa1, 0x00, 0x98, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x68, 0xe3, 0x00, 0x40, 0x6b, 0x22, + 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x35, 0x63, 0x01, 0xa0, 0x75, 0x22, 0xf2, 0x00, 0x46, 0xa3, + 0x04, 0xa4, 0xc1, 0xb9, 0x70, 0xa0, 0x00, 0x9e, 0x04, 0xa4, 0xc5, 0x35, 0x7c, 0xa0, 0x00, 0x1c, + 0xf6, 0x00, 0x46, 0x23, 0xff, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x4a, 0x63, 0x00, 0x50, 0x0a, 0xf5, + 0x00, 0x5f, 0x88, 0xe2, 0x01, 0x40, 0x40, 0xa8, 0xf4, 0x9f, 0x00, 0x08, 0x02, 0x40, 0x40, 0xa8, + 0x70, 0xa0, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0xaa, 0x40, 0x40, 0x28, + 0x70, 0xa0, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0x80, 0x4c, 0x40, 0x68, + 0x70, 0xa0, 0x00, 0x8a, 0xf4, 0x00, 0x46, 0xa3, 0x00, 0xe1, 0xbd, 0xe2, 0x02, 0xe0, 0x41, 0x28, + 0x44, 0xa0, 0x00, 0x88, 0x01, 0xe0, 0x41, 0x28, 0x70, 0xa0, 0x00, 0x8a, 0x50, 0x00, 0x42, 0xa3, + 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, 0x00, 0x1c, 0x06, 0xa4, 0xe3, 0x35, 0x7c, 0xa0, 0x00, 0x1c, + 0x50, 0xa0, 0x00, 0x18, 0x30, 0x00, 0x42, 0xa3, 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, 0x00, 0x1c, + 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0xff, 0x0f, 0x4a, 0x23, 0x80, 0x22, 0x84, 0x62, + 0x00, 0x20, 0x04, 0xf3, 0xc3, 0x20, 0x84, 0xa4, 0x00, 0x00, 0x40, 0x23, 0x8c, 0xa0, 0x00, 0x98, + 0x12, 0x00, 0x44, 0xa3, 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, 0x00, 0x98, 0x3c, 0x00, 0x44, 0xa3, + 0xf2, 0x00, 0x46, 0xa3, 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, 0x00, 0x98, 0x00, 0x50, 0x45, 0xe9, + 0x10, 0x40, 0x6d, 0xa2, 0x00, 0x00, 0x21, 0xf9, 0x00, 0x60, 0x61, 0xe9, 0x20, 0x60, 0x6d, 0x22, + 0x00, 0x10, 0x23, 0xf9, 0x00, 0x60, 0x63, 0x69, 0x00, 0x00, 0x40, 0x23, 0x00, 0xa1, 0x00, 0x98, + 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x33, 0x63, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x6a, 0x22, + 0x03, 0x94, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, + 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, 0x73, 0x22, 0x03, 0x94, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, + 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x05, 0x94, 0xc1, 0x39, 0xc3, 0x00, 0x44, 0xa3, + 0x00, 0x50, 0x45, 0xe9, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x40, 0x23, 0x00, 0xa1, 0x00, 0x98, + 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, + 0x00, 0x00, 0x44, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x94, 0x81, 0x00, 0x98, 0x58, 0x81, 0x00, 0x02, + 0x00, 0x00, 0x48, 0x22, 0x00, 0x40, 0x48, 0xe5, 0x00, 0x40, 0x04, 0xf5, 0xff, 0x00, 0x4c, 0x23, + 0x00, 0x23, 0x84, 0x62, 0x00, 0x20, 0x32, 0x63, 0x01, 0x90, 0xb3, 0x24, 0x04, 0x94, 0xcb, 0xb5, + 0x0c, 0xa2, 0x00, 0x1c, 0xff, 0x00, 0x4c, 0x23, 0x00, 0x53, 0x8e, 0xe2, 0x01, 0x70, 0x40, 0xa8, + 0x00, 0xa2, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x50, 0x0a, 0xf5, + 0x00, 0x53, 0x8e, 0xe2, 0x00, 0x71, 0x40, 0x68, 0xf4, 0xa1, 0x00, 0x0a, 0x05, 0x94, 0xcb, 0x35, + 0x0c, 0xa2, 0x00, 0x1c, 0x60, 0x01, 0x4a, 0xc9, 0x06, 0x94, 0xcb, 0x35, 0x0c, 0xa2, 0x00, 0x1c, + 0x80, 0x01, 0x4a, 0x49, 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, 0x73, 0x24, 0x00, 0x94, 0xf5, 0xb5, + 0x0c, 0xa2, 0x00, 0x1c, 0x01, 0x94, 0xed, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x02, 0x94, 0xeb, 0x35, + 0x0c, 0xa2, 0x00, 0x1c, 0x03, 0x94, 0xef, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x05, 0x94, 0xc1, 0x39, + 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x64, 0x65, 0x00, 0x20, 0x25, 0xf9, 0x20, 0x30, 0x7e, 0x45, + 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, + 0x00, 0x50, 0xab, 0xfb, 0x00, 0x00, 0xd4, 0xf3, 0x00, 0x65, 0xad, 0x68, 0x00, 0x75, 0xaf, 0x68, + 0x80, 0x6b, 0xa9, 0xe8, 0xa0, 0x00, 0x60, 0xc5, 0x00, 0x00, 0x21, 0xf9, 0xc0, 0x00, 0x62, 0x45, + 0x88, 0x9b, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf6, 0x00, 0x46, 0x23, 0x14, 0xa2, 0x00, 0x98, + 0x05, 0x94, 0xc1, 0x39, 0xf4, 0x00, 0x46, 0xa3, 0x14, 0xa2, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, + 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x05, 0x94, 0xc1, 0x39, + 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x12, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, + 0x00, 0x30, 0x40, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, + 0x00, 0x00, 0x6c, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x6e, 0x23, 0x94, 0x81, 0x00, 0x98, + 0x20, 0x00, 0x42, 0x23, 0x94, 0x81, 0x00, 0x98, 0xf2, 0x00, 0x40, 0xa3, 0x50, 0xa2, 0x00, 0x98, + 0x00, 0x00, 0xe6, 0x73, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, + 0x00, 0x00, 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0x30, 0xe7, 0x62, + 0x40, 0x00, 0x66, 0x49, 0x09, 0x00, 0x60, 0xa3, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, + 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x40, 0x00, 0x66, 0x45, + 0x20, 0x00, 0x60, 0x45, 0x60, 0x00, 0x60, 0xc9, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, + 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x20, 0x00, 0x42, 0x45, + 0x00, 0x12, 0xe0, 0xb5, 0x58, 0xa2, 0x00, 0x9c, 0x40, 0x00, 0x66, 0x45, 0x0c, 0x9e, 0x00, 0x02, + 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, + 0x60, 0x00, 0x60, 0xc5, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x10, 0xe6, 0x35, 0x58, 0xa2, 0x00, 0x9c, + 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, + 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0x30, 0xe7, 0x62, 0x0c, 0x9e, 0x00, 0x02, + 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x00, 0x00, 0x66, 0xa3, + 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x50, 0xa2, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, + 0xd0, 0xa3, 0x00, 0x02, 0xe4, 0xa3, 0x00, 0x82, 0x04, 0xa4, 0x00, 0x82, 0x24, 0xa4, 0x00, 0x02, + 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xc0, 0x63, 0x94, 0x81, 0x00, 0x98, 0x1c, 0x00, 0x7c, 0xa3, + 0x00, 0x10, 0x23, 0xf9, 0x00, 0x00, 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, 0xfd, + 0x80, 0x08, 0x21, 0x7d, 0x00, 0x10, 0x23, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x5c, 0xa3, 0x00, 0x0a, + 0x00, 0x00, 0xc0, 0x69, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, 0xfd, 0x00, 0x00, 0x21, 0xf3, + 0x01, 0xe0, 0x7d, 0x24, 0x78, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, 0x00, 0x00, 0x00, 0x84, + 0x54, 0x00, 0x46, 0xa3, 0x00, 0x30, 0x06, 0xf3, 0x53, 0x30, 0x86, 0xa4, 0x00, 0x30, 0x06, 0xf3, + 0x01, 0x30, 0x86, 0x24, 0x00, 0x30, 0x06, 0xf3, 0x80, 0x30, 0x86, 0x24, 0x00, 0x30, 0x06, 0xf5, + 0x00, 0x00, 0x00, 0x84, 0x90, 0xa3, 0x00, 0x82, 0x01, 0x06, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xed, + 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xc0, 0xeb, 0x00, 0x10, 0x80, 0xf9, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x08, 0x4c, 0xa3, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x60, 0x7e, 0x69, 0xd4, 0xa3, 0x00, 0x0a, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x02, 0x4c, 0xa3, 0x10, 0x00, 0x44, 0x23, 0x00, 0x20, 0x04, 0xf3, + 0x00, 0x61, 0x86, 0xe4, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0xf0, 0xa3, 0x00, 0x0a, + 0x00, 0x00, 0x00, 0x84, 0x80, 0x00, 0x4c, 0xa3, 0x50, 0x00, 0x44, 0xa3, 0x00, 0x20, 0x04, 0xf3, + 0x00, 0x61, 0x86, 0xe4, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0x10, 0xa4, 0x00, 0x0a, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x44, 0xa3, + 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x48, 0xa3, 0x00, 0x00, 0x4a, 0x23, 0x00, 0x00, 0x4c, 0x23, + 0x00, 0x00, 0x4e, 0xa3, 0x00, 0x00, 0x50, 0xa3, 0x00, 0x00, 0x52, 0x23, 0x00, 0x00, 0x54, 0x23, + 0x00, 0x00, 0x56, 0xa3, 0x00, 0x00, 0x58, 0x23, 0x00, 0x00, 0x5a, 0xa3, 0x00, 0x00, 0x5c, 0xa3, + 0x00, 0x00, 0x5e, 0x23, 0x00, 0x00, 0x60, 0xa3, 0x00, 0x00, 0x62, 0x23, 0x00, 0x00, 0x64, 0x23, + 0x00, 0x00, 0x66, 0xa3, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, + 0x00, 0x00, 0x6e, 0x23, 0x00, 0x00, 0x70, 0x23, 0x00, 0x00, 0x72, 0xa3, 0x00, 0x00, 0x74, 0xa3, + 0x00, 0x00, 0x76, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x7c, 0x23, + 0x00, 0x00, 0x7e, 0xa3, 0x00, 0x00, 0x00, 0x84}; \ No newline at end of file diff --git a/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_2_0_0/fw_CPU.h b/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_2_0_0/fw_CPU.h index ec20b1d59..a9d4b2f05 100644 --- a/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_2_0_0/fw_CPU.h +++ b/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_2_0_0/fw_CPU.h @@ -5,1251 +5,1484 @@ /** * @brief CPU firmware version fw_v2.0.0_signed.bin for bootloader v1.0.1 */ -const uint8_t fw_CPU[] - = {0xe6, 0x36, 0x5d, 0x07, 0xbe, 0xde, 0x15, 0x16, 0xb3, 0xd4, 0xf1, 0x2c, 0xea, 0x45, 0x83, 0x09, 0xfb, 0x82, 0x15, - 0x01, 0x62, 0xe1, 0x40, 0x83, 0xb4, 0x48, 0xc5, 0x33, 0xa9, 0xca, 0x41, 0x35, 0xba, 0xa6, 0x60, 0xf7, 0xe5, 0x50, - 0xe8, 0x83, 0xc8, 0x9b, 0xf5, 0xe6, 0x79, 0xb6, 0x72, 0x34, 0xbb, 0x9a, 0x89, 0xa7, 0xd8, 0x29, 0x8b, 0xd8, 0x62, - 0xe1, 0xd0, 0x85, 0x39, 0x3a, 0x11, 0x0c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x7c, 0x58, 0x00, 0x00, 0x61, 0xcd, 0x51, 0x19, 0x69, 0x21, 0x5c, 0xac, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x6f, 0x30, - 0x40, 0x44, 0x6f, 0x30, 0x60, 0x3e, 0x6f, 0x30, 0x20, 0x3e, 0x6f, 0x30, 0xe0, 0x3d, 0x6f, 0x30, 0xa0, 0x3d, 0x6f, - 0x30, 0x60, 0x3d, 0x6f, 0x30, 0x20, 0x3d, 0x6f, 0x50, 0x40, 0x18, 0x6f, 0x30, 0xa0, 0x3c, 0x6f, 0x30, 0x60, 0x3c, - 0x6f, 0x30, 0x20, 0x3c, 0x6f, 0x30, 0xb0, 0x00, 0x6f, 0x30, 0xa0, 0x3b, 0x6f, 0x30, 0x60, 0x3b, 0x6f, 0x30, 0x20, - 0x3b, 0x6f, 0x30, 0xe0, 0x3a, 0x6f, 0x40, 0x30, 0x7c, 0x6f, 0x30, 0x60, 0x27, 0x6f, 0x30, 0x90, 0x2d, 0x6f, 0x40, - 0x90, 0x37, 0x6f, 0x40, 0x50, 0x37, 0x6f, 0x40, 0x10, 0x37, 0x6f, 0x30, 0xe0, 0x4d, 0x6f, 0x30, 0xe0, 0x4e, 0x6f, - 0x30, 0x70, 0x53, 0x6f, 0x40, 0xd0, 0x5e, 0x6f, 0x30, 0x60, 0x4f, 0x6f, 0x20, 0xf0, 0x21, 0x6f, 0x40, 0xd0, 0x1f, - 0x6f, 0x30, 0xe0, 0x4f, 0x6f, 0x30, 0x40, 0x5c, 0x6f, 0x30, 0x40, 0x40, 0x93, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, - 0x00, 0x93, 0x01, 0x00, 0x00, 0x13, 0x02, 0x00, 0x00, 0x93, 0x02, 0x00, 0x00, 0x13, 0x03, 0x00, 0x00, 0x93, 0x03, - 0x00, 0x00, 0x13, 0x04, 0x00, 0x00, 0x93, 0x04, 0x00, 0x00, 0x13, 0x05, 0x00, 0x00, 0x93, 0x05, 0x00, 0x00, 0x13, - 0x06, 0x00, 0x00, 0x93, 0x06, 0x00, 0x00, 0x13, 0x07, 0x00, 0x00, 0x93, 0x07, 0x00, 0x00, 0x13, 0x08, 0x00, 0x00, - 0x93, 0x08, 0x00, 0x00, 0x13, 0x09, 0x00, 0x00, 0x93, 0x09, 0x00, 0x00, 0x13, 0x0a, 0x00, 0x00, 0x93, 0x0a, 0x00, - 0x00, 0x13, 0x0b, 0x00, 0x00, 0x93, 0x0b, 0x00, 0x00, 0x13, 0x0c, 0x00, 0x00, 0x93, 0x0c, 0x00, 0x00, 0x13, 0x0d, - 0x00, 0x00, 0x93, 0x0d, 0x00, 0x00, 0x13, 0x0e, 0x00, 0x00, 0x93, 0x0e, 0x00, 0x00, 0x13, 0x0f, 0x00, 0x00, 0x93, - 0x0f, 0x00, 0x00, 0x97, 0x00, 0x00, 0x00, 0x93, 0x80, 0x40, 0xf0, 0x73, 0x90, 0x50, 0x30, 0x93, 0x00, 0x00, 0x00, - 0x17, 0x41, 0x10, 0x00, 0x13, 0x01, 0x41, 0xcf, 0x33, 0x04, 0x01, 0x00, 0x17, 0x0d, 0x10, 0x00, 0x13, 0x0d, 0x8d, - 0xee, 0x97, 0x4d, 0x10, 0x00, 0x93, 0x8d, 0x0d, 0xce, 0x63, 0x57, 0xbd, 0x01, 0x23, 0x20, 0x0d, 0x00, 0x11, 0x0d, - 0xe3, 0x4d, 0xbd, 0xff, 0xef, 0x00, 0x70, 0x71, 0x73, 0x00, 0x50, 0x10, 0xf5, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x23, - 0xac, 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa2, 0x07, 0xf4, - 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa0, 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x8e, 0x07, 0xf2, 0x82, 0x80, 0x05, - 0x67, 0x93, 0x07, 0x45, 0x00, 0x01, 0x17, 0x01, 0x45, 0x94, 0x43, 0x99, 0xe6, 0x13, 0x05, 0x05, 0x02, 0x91, 0x07, - 0xe3, 0x1b, 0xe5, 0xfe, 0x82, 0x80, 0x81, 0x47, 0x13, 0x06, 0x00, 0x02, 0x33, 0xd7, 0xf6, 0x00, 0x05, 0x8b, 0x09, - 0xe7, 0x85, 0x07, 0x05, 0x05, 0xe3, 0x9a, 0xc7, 0xfe, 0x82, 0x80, 0x18, 0x41, 0xfd, 0x57, 0x63, 0x02, 0xf7, 0x06, - 0x13, 0x07, 0x45, 0x00, 0x81, 0x47, 0x13, 0x06, 0xf0, 0x07, 0x14, 0x43, 0x81, 0xea, 0x85, 0x07, 0x11, 0x07, 0xe3, - 0x9c, 0xc7, 0xfe, 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x01, 0x47, 0x93, 0x05, 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, - 0x05, 0x8a, 0x19, 0xca, 0x93, 0x05, 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, 0x05, 0x8a, 0x15, 0xc6, 0x05, 0x07, 0xe3, - 0x1b, 0xb7, 0xfe, 0x21, 0xa0, 0x05, 0x07, 0xe3, 0x11, 0xb7, 0xfe, 0x89, 0x07, 0x93, 0x06, 0x00, 0x08, 0x7d, 0x56, - 0xe3, 0x85, 0xd7, 0xfc, 0x85, 0x07, 0x13, 0x97, 0x27, 0x00, 0x2a, 0x97, 0x03, 0x27, 0xc7, 0xff, 0xe3, 0x08, 0xc7, - 0xfe, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x14, 0x20, 0x00, 0x13, 0x04, 0x04, 0x00, - 0x83, 0x46, 0x94, 0x07, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, - 0x77, 0x13, 0x06, 0xc6, 0x52, 0x93, 0x85, 0x85, 0x53, 0x06, 0xc6, 0xef, 0x10, 0xd0, 0x51, 0x03, 0x45, 0x94, 0x07, - 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x40, 0xd0, 0x21, 0xef, 0x20, 0xa0, - 0x5d, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x00, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x40, 0x90, 0x22, 0xb2, 0x40, - 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x05, 0x05, 0x10, 0x2a, 0x84, 0x37, 0x55, 0x10, 0x00, 0x13, - 0x05, 0x05, 0x54, 0x06, 0xc6, 0xef, 0x10, 0xd0, 0x54, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x07, 0xf6, 0x14, 0x43, - 0x85, 0x47, 0xb3, 0x97, 0x87, 0x00, 0xb2, 0x40, 0x22, 0x44, 0x93, 0xc7, 0xf7, 0xff, 0xf5, 0x8f, 0x1c, 0xc3, 0x41, - 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x2a, 0x84, 0x93, 0x04, 0xa0, 0x0a, 0xef, 0x20, - 0x30, 0x77, 0x63, 0x19, 0x95, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, - 0x80, 0x22, 0x85, 0xef, 0x20, 0xb0, 0x79, 0x22, 0x85, 0xef, 0x20, 0x50, 0x75, 0xe3, 0x03, 0x95, 0xfe, 0x37, 0x55, - 0x10, 0x00, 0x13, 0x05, 0x05, 0x54, 0x85, 0x45, 0xef, 0x10, 0xb0, 0x4e, 0x13, 0x05, 0x50, 0x05, 0xd1, 0xbf, 0x01, - 0x11, 0x22, 0xcc, 0x2a, 0x84, 0x37, 0x35, 0x00, 0x08, 0x06, 0xce, 0x2e, 0xc6, 0xef, 0x30, 0x50, 0x14, 0x32, 0x46, - 0xa2, 0x85, 0x37, 0x35, 0x00, 0x08, 0xef, 0x30, 0x70, 0x1b, 0x62, 0x44, 0xf2, 0x40, 0x37, 0x35, 0x00, 0x08, 0x05, - 0x61, 0x6f, 0x30, 0xf0, 0x16, 0x6d, 0x71, 0x23, 0x24, 0x81, 0x10, 0x2a, 0x84, 0x0a, 0x85, 0x23, 0x26, 0x11, 0x10, - 0xef, 0x10, 0xf0, 0x68, 0x0a, 0x85, 0x23, 0x00, 0x81, 0x00, 0xef, 0x20, 0xa0, 0x47, 0x83, 0x20, 0xc1, 0x10, 0x03, - 0x24, 0x81, 0x10, 0x51, 0x61, 0x82, 0x80, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0x2e, 0xc4, 0xef, 0x20, 0xd0, 0x1b, - 0xa2, 0x45, 0x32, 0x45, 0xef, 0x20, 0xf0, 0x33, 0x2a, 0xc4, 0xef, 0x20, 0x90, 0x1c, 0xf2, 0x40, 0x22, 0x45, 0x05, - 0x61, 0x82, 0x80, 0x13, 0x01, 0x01, 0xde, 0x23, 0x2c, 0x81, 0x20, 0x2e, 0x84, 0xaa, 0x05, 0x23, 0x28, 0x21, 0x21, - 0x93, 0x85, 0x05, 0x20, 0x2a, 0x89, 0x08, 0x08, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x2a, 0x91, 0x20, 0x7d, 0x3f, 0x93, - 0x07, 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x04, 0xaa, 0x84, 0x08, 0x08, 0x09, 0x3d, 0x63, 0x00, 0x95, 0x02, 0x22, 0x85, - 0xd1, 0x3d, 0x09, 0x45, 0x83, 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, 0x41, 0x21, 0x03, 0x29, 0x01, - 0x21, 0x13, 0x01, 0x01, 0x22, 0x82, 0x80, 0x42, 0x44, 0x08, 0x08, 0x22, 0xc6, 0x65, 0x3b, 0x09, 0x8c, 0x11, 0x46, - 0x6c, 0x00, 0x4a, 0x85, 0x22, 0xc6, 0xef, 0x50, 0x00, 0x12, 0x05, 0x45, 0xc9, 0xbf, 0x01, 0x45, 0xf9, 0xb7, 0x41, - 0x11, 0x4a, 0xc0, 0x03, 0xa9, 0x05, 0x00, 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0x2e, 0x84, 0xaa, 0x84, 0xef, 0x20, - 0x30, 0x68, 0xca, 0x85, 0x26, 0x85, 0xef, 0x20, 0x70, 0x1f, 0xa6, 0x85, 0x22, 0x85, 0xef, 0x20, 0xd0, 0x29, 0x93, - 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x02, 0x1c, 0x40, 0x63, 0x93, 0x27, 0x03, 0x93, 0x07, 0x44, 0x00, 0x7d, 0x57, - 0x13, 0x04, 0x04, 0x20, 0x94, 0x43, 0x63, 0x9b, 0xe6, 0x00, 0x91, 0x07, 0xe3, 0x9c, 0x87, 0xfe, 0xb2, 0x40, 0x22, - 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0xc5, 0xbf, 0x13, 0x01, 0x01, 0xde, - 0x23, 0x26, 0x31, 0x21, 0x93, 0x19, 0xa5, 0x00, 0x23, 0x2a, 0x91, 0x20, 0x93, 0x84, 0x09, 0x20, 0x23, 0x2c, 0x81, - 0x20, 0xa6, 0x85, 0x2a, 0x84, 0x0a, 0x85, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x28, 0x21, 0x21, 0xfd, 0x35, 0x93, 0x07, - 0xa0, 0x0a, 0x63, 0x00, 0xf5, 0x02, 0x01, 0x45, 0x83, 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, 0x41, - 0x21, 0x03, 0x29, 0x01, 0x21, 0x83, 0x29, 0xc1, 0x20, 0x13, 0x01, 0x01, 0x22, 0x82, 0x80, 0x2a, 0x89, 0x0a, 0x85, - 0x1d, 0x33, 0x63, 0x06, 0x25, 0x01, 0x22, 0x85, 0xe5, 0x33, 0x09, 0x45, 0xd9, 0xbf, 0x02, 0x44, 0x0a, 0x85, 0xcd, - 0x31, 0xaa, 0x87, 0xb3, 0x06, 0xa4, 0x40, 0x0d, 0x45, 0xe3, 0x03, 0xf4, 0xfc, 0x09, 0x45, 0xe3, 0x60, 0xd4, 0xfc, - 0x50, 0x00, 0x01, 0x44, 0x13, 0x08, 0x00, 0x02, 0x13, 0x05, 0xf0, 0x07, 0x0c, 0x42, 0xb1, 0xc5, 0x01, 0x47, 0xb3, - 0xd7, 0xe5, 0x00, 0x85, 0x8b, 0x95, 0xcf, 0x85, 0x47, 0xb3, 0x97, 0xe7, 0x00, 0x93, 0xc7, 0xf7, 0xff, 0xed, 0x8f, - 0x1c, 0xc2, 0xef, 0x20, 0xb0, 0x03, 0x18, 0x04, 0x93, 0x17, 0x24, 0x00, 0xba, 0x97, 0x83, 0xa5, 0x47, 0xe0, 0x13, - 0x05, 0x14, 0x00, 0x0a, 0x05, 0x26, 0x95, 0xef, 0x20, 0x30, 0x14, 0x2a, 0x84, 0xef, 0x20, 0x70, 0x03, 0x13, 0x05, - 0x64, 0xf5, 0x13, 0x35, 0x15, 0x00, 0xad, 0xb7, 0x05, 0x07, 0xe3, 0x1e, 0x07, 0xfb, 0x05, 0x04, 0x11, 0x06, 0xe3, - 0x17, 0xa4, 0xfa, 0xfd, 0x16, 0x8a, 0x85, 0x13, 0x85, 0x09, 0x40, 0x36, 0xc0, 0xc9, 0x35, 0x93, 0x07, 0xa0, 0x0a, - 0xe3, 0x14, 0xf5, 0xf4, 0x8a, 0x85, 0x26, 0x85, 0x55, 0x3d, 0x13, 0x05, 0x65, 0xf5, 0xf9, 0xb7, 0x41, 0x11, 0x22, - 0xc4, 0x06, 0xc6, 0x93, 0x07, 0x30, 0x0c, 0x2a, 0x84, 0x63, 0x04, 0xf5, 0x00, 0xef, 0x20, 0x60, 0x4e, 0xb7, 0x07, - 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x05, 0x67, 0x23, 0x80, 0x87, 0x00, 0xba, 0x97, 0xf8, 0x5b, 0x19, 0xe3, 0x05, - 0x47, 0xf8, 0xdb, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x66, 0x37, 0x05, 0x20, 0x00, 0x41, 0x11, - 0x13, 0x06, 0xc6, 0x07, 0x81, 0x45, 0x13, 0x05, 0x05, 0x00, 0x06, 0xc6, 0xef, 0x40, 0x50, 0x7b, 0xef, 0x20, 0x00, - 0x44, 0xef, 0x40, 0xc0, 0x4e, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x20, 0x80, 0x3a, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x20, - 0xa0, 0x57, 0xef, 0x30, 0xa0, 0x00, 0xef, 0x40, 0x40, 0x1c, 0xef, 0x40, 0x40, 0x7b, 0xb2, 0x40, 0x41, 0x01, 0x6f, - 0x30, 0x20, 0x17, 0x41, 0x11, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x06, 0xc6, 0x23, 0xa4, 0xe7, 0xf4, - 0xef, 0x20, 0xe0, 0x3c, 0x65, 0x37, 0x51, 0x3e, 0xef, 0x30, 0xe0, 0x1b, 0xe1, 0x37, 0xb2, 0x40, 0x1d, 0x65, 0x13, - 0x05, 0x05, 0x6c, 0x41, 0x01, 0x6f, 0x30, 0x60, 0x23, 0x41, 0x11, 0x26, 0xc2, 0xae, 0x84, 0xb6, 0x85, 0x06, 0xc6, - 0x22, 0xc4, 0x4a, 0xc0, 0x36, 0x84, 0x32, 0x89, 0xef, 0x40, 0x00, 0x79, 0x22, 0x86, 0xca, 0x85, 0x13, 0x05, 0x00, - 0x02, 0xef, 0x40, 0x60, 0x7b, 0xef, 0x40, 0x20, 0x76, 0xef, 0x40, 0x80, 0x7b, 0x93, 0x07, 0xa0, 0x0a, 0x13, 0x04, - 0x50, 0x05, 0x63, 0x1a, 0xf5, 0x00, 0x2a, 0x84, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0x00, 0x02, 0x26, 0x85, 0xef, - 0x40, 0x80, 0x78, 0xb2, 0x40, 0x22, 0x85, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x85, 0x67, - 0xc1, 0x07, 0x63, 0xee, 0xb7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xae, 0x84, 0x37, 0x04, 0x20, - 0x00, 0x19, 0xc5, 0x2e, 0x86, 0xaa, 0x85, 0x13, 0x05, 0x04, 0x00, 0xef, 0x40, 0xf0, 0x6b, 0x13, 0x04, 0x04, 0x00, - 0x93, 0x07, 0x30, 0xfc, 0x23, 0x00, 0xf4, 0x00, 0x85, 0x67, 0x3e, 0x94, 0x64, 0xd8, 0xb2, 0x40, 0x22, 0x44, 0x92, - 0x44, 0x41, 0x01, 0x82, 0x80, 0x82, 0x80, 0x13, 0x01, 0x01, 0xdd, 0x23, 0x24, 0x81, 0x22, 0x23, 0x22, 0x91, 0x22, - 0x23, 0x20, 0x21, 0x23, 0x23, 0x2e, 0x31, 0x21, 0x23, 0x2c, 0x41, 0x21, 0x23, 0x2a, 0x51, 0x21, 0x23, 0x28, 0x61, - 0x21, 0x23, 0x26, 0x71, 0x21, 0x23, 0x24, 0x81, 0x21, 0x23, 0x26, 0x11, 0x22, 0x13, 0x04, 0x00, 0x20, 0x01, 0x49, - 0x93, 0x04, 0xa0, 0x0a, 0x37, 0x3a, 0x20, 0x00, 0x85, 0x4a, 0x37, 0x5b, 0x10, 0x00, 0xb7, 0x5b, 0x10, 0x00, 0x37, - 0x5c, 0x10, 0x00, 0xc1, 0x49, 0xa2, 0x85, 0x0a, 0x85, 0x51, 0x39, 0x63, 0x16, 0x95, 0x02, 0x0a, 0x85, 0xfd, 0x34, - 0x63, 0x1e, 0x95, 0x04, 0x13, 0x07, 0x0a, 0xf6, 0x14, 0x43, 0xb3, 0x97, 0x2a, 0x01, 0x13, 0x06, 0x8b, 0x54, 0xd5, - 0x8f, 0x93, 0x85, 0x0b, 0x54, 0xca, 0x86, 0x13, 0x05, 0x8c, 0x77, 0x1c, 0xc3, 0xef, 0x10, 0x10, 0x08, 0x05, 0x09, - 0x13, 0x04, 0x04, 0x40, 0xe3, 0x14, 0x39, 0xfd, 0x83, 0x20, 0xc1, 0x22, 0x03, 0x24, 0x81, 0x22, 0x83, 0x24, 0x41, - 0x22, 0x03, 0x29, 0x01, 0x22, 0x83, 0x29, 0xc1, 0x21, 0x03, 0x2a, 0x81, 0x21, 0x83, 0x2a, 0x41, 0x21, 0x03, 0x2b, - 0x01, 0x21, 0x83, 0x2b, 0xc1, 0x20, 0x03, 0x2c, 0x81, 0x20, 0x13, 0x01, 0x01, 0x23, 0x82, 0x80, 0x93, 0x05, 0x04, - 0x20, 0x0a, 0x85, 0x25, 0x31, 0xe3, 0x10, 0x95, 0xfc, 0x0a, 0x85, 0x49, 0x34, 0xe3, 0x1c, 0x95, 0xfa, 0x22, 0x85, - 0xef, 0x20, 0xd0, 0x33, 0x8a, 0x85, 0x22, 0x85, 0xef, 0x20, 0x30, 0x1b, 0xa2, 0x85, 0x0a, 0x85, 0x21, 0x31, 0xe3, - 0x10, 0x95, 0xfa, 0x0a, 0x85, 0x8d, 0x34, 0xe3, 0x0c, 0x95, 0xf6, 0x51, 0xbf, 0xb7, 0x07, 0x00, 0x80, 0x6d, 0x71, - 0x37, 0x55, 0x10, 0x00, 0x23, 0x26, 0x11, 0x10, 0x13, 0x05, 0x45, 0x55, 0x86, 0x85, 0xbe, 0x95, 0xef, 0x10, 0xf0, - 0x06, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x47, 0xf3, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x1e, 0xf7, 0x02, 0x37, 0x15, - 0x10, 0x00, 0x13, 0x05, 0x85, 0x9f, 0xef, 0x10, 0x70, 0x7b, 0x13, 0x05, 0xc0, 0x0f, 0xef, 0x10, 0xc0, 0x74, 0x0a, - 0x85, 0xef, 0x10, 0xd0, 0x22, 0x93, 0x07, 0xf0, 0x07, 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x00, 0x23, 0x00, - 0xf1, 0x00, 0xef, 0x10, 0x20, 0x6e, 0xa3, 0x00, 0xa1, 0x00, 0x0a, 0x85, 0xef, 0x10, 0x10, 0x7d, 0x05, 0x45, 0xef, - 0x40, 0xf0, 0x03, 0xef, 0x40, 0xf0, 0x02, 0xe5, 0x33, 0xef, 0x10, 0xb0, 0x46, 0xf5, 0xbf, 0x41, 0x11, 0x06, 0xc6, - 0x22, 0xc4, 0xef, 0x40, 0x80, 0x68, 0x93, 0x07, 0x00, 0x08, 0x63, 0xf3, 0xa7, 0x00, 0xad, 0x3f, 0x2a, 0x84, 0x13, - 0x05, 0xa0, 0x0a, 0xef, 0x40, 0x40, 0x27, 0xb7, 0x17, 0x20, 0x00, 0xb2, 0x40, 0x23, 0xaa, 0x87, 0x06, 0x22, 0x44, - 0x13, 0x05, 0x30, 0x0c, 0x41, 0x01, 0x82, 0x80, 0x93, 0x07, 0xf0, 0x17, 0x63, 0xf5, 0xa7, 0x00, 0x41, 0x11, 0x06, - 0xc6, 0xb9, 0x37, 0x6f, 0x10, 0x10, 0x58, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x4a, 0xc0, 0x2e, 0x84, 0x06, 0xc6, - 0xaa, 0x84, 0xc5, 0x37, 0x61, 0x8d, 0x13, 0x09, 0x50, 0x05, 0x19, 0xc1, 0x13, 0x09, 0xa0, 0x0a, 0x26, 0x85, 0xc1, - 0x3f, 0x69, 0x8c, 0x13, 0x05, 0xa0, 0x0a, 0x19, 0xe0, 0x13, 0x05, 0x50, 0x05, 0x63, 0x03, 0x25, 0x01, 0x21, 0x3f, - 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x69, 0x71, 0x08, 0x08, 0x23, 0x22, 0x91, - 0x12, 0x23, 0x20, 0x21, 0x13, 0x23, 0x2c, 0x41, 0x11, 0x37, 0x39, 0x20, 0x00, 0x23, 0x26, 0x11, 0x12, 0x23, 0x24, - 0x81, 0x12, 0x23, 0x2e, 0x31, 0x11, 0x23, 0x2a, 0x51, 0x11, 0xef, 0x10, 0x30, 0x15, 0x91, 0x47, 0x13, 0x07, 0x89, - 0xf5, 0x23, 0x08, 0xf1, 0x00, 0x1c, 0x43, 0x37, 0x1a, 0x20, 0x00, 0xb7, 0x34, 0x20, 0x00, 0x13, 0x09, 0x89, 0xf5, - 0x13, 0x0a, 0x0a, 0x00, 0x93, 0x84, 0x44, 0xf5, 0xc5, 0xeb, 0x83, 0x27, 0x4a, 0x07, 0x23, 0xa0, 0x04, 0x00, 0x1c, - 0xc3, 0x3d, 0x47, 0x63, 0x63, 0xf7, 0x00, 0x45, 0x3d, 0xc1, 0x17, 0x09, 0x46, 0x6c, 0x00, 0x13, 0x05, 0x21, 0x01, - 0x3e, 0xc6, 0xef, 0x40, 0xf0, 0x43, 0x89, 0x47, 0xa3, 0x08, 0xf1, 0x00, 0x13, 0x04, 0xe0, 0x07, 0x93, 0x09, 0x41, - 0x01, 0x03, 0x27, 0x09, 0x00, 0x94, 0x40, 0xb3, 0x07, 0xd7, 0x40, 0x63, 0xf3, 0x87, 0x00, 0x3e, 0x84, 0x37, 0x56, - 0x10, 0x00, 0xb7, 0x5a, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0xa2, 0x87, 0x93, 0x85, 0xca, 0x56, 0x13, 0x06, 0xc6, - 0x55, 0x13, 0x05, 0x45, 0x57, 0xef, 0x10, 0x40, 0x67, 0x8c, 0x40, 0x83, 0x27, 0x4a, 0x07, 0x33, 0x07, 0xb4, 0x00, - 0x63, 0xf8, 0xe7, 0x04, 0x8d, 0x45, 0x13, 0x85, 0xca, 0x56, 0xef, 0x10, 0x20, 0x6d, 0x13, 0x04, 0x50, 0x05, 0xef, - 0xf0, 0x5f, 0x84, 0xef, 0x40, 0xe0, 0x14, 0xef, 0x20, 0x60, 0x0a, 0xef, 0x20, 0x60, 0x01, 0xbd, 0x31, 0x83, 0x20, - 0xc1, 0x12, 0x22, 0x85, 0x03, 0x24, 0x81, 0x12, 0x83, 0x24, 0x41, 0x12, 0x03, 0x29, 0x01, 0x12, 0x83, 0x29, 0xc1, - 0x11, 0x03, 0x2a, 0x81, 0x11, 0x83, 0x2a, 0x41, 0x11, 0x55, 0x61, 0x82, 0x80, 0x13, 0x04, 0x00, 0x08, 0x93, 0x09, - 0x21, 0x01, 0xad, 0xbf, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x22, 0x86, 0xbe, 0x95, 0x4e, 0x85, 0xef, - 0x40, 0x70, 0x39, 0x83, 0x47, 0x11, 0x01, 0x98, 0x40, 0x22, 0x97, 0x3e, 0x94, 0x83, 0x27, 0x09, 0x00, 0xa3, 0x08, - 0x81, 0x00, 0x98, 0xc0, 0x13, 0x04, 0x50, 0x05, 0x63, 0x17, 0xf7, 0x00, 0x89, 0x47, 0x23, 0x08, 0xf1, 0x00, 0x13, - 0x04, 0xa0, 0x0a, 0x08, 0x08, 0xef, 0x10, 0x10, 0x63, 0x59, 0xbf, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, - 0x4a, 0xc8, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xf3, 0xa7, 0x00, 0x5d, 0x3b, 0x0a, 0x05, 0x05, 0x64, 0xb3, 0x04, 0x85, - 0x00, 0x41, 0x04, 0x13, 0x09, 0xc1, 0x00, 0x2a, 0x94, 0x26, 0x85, 0xef, 0x30, 0xc0, 0x0b, 0x23, 0x00, 0xa9, 0x00, - 0x91, 0x04, 0x05, 0x09, 0xe3, 0x99, 0x84, 0xfe, 0xf2, 0x40, 0x62, 0x44, 0x32, 0x45, 0xd2, 0x44, 0x42, 0x49, 0x05, - 0x61, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x8d, 0x47, 0x63, 0xf3, 0xa7, 0x00, 0xad, 0x3b, 0x89, 0x67, 0x93, 0x87, - 0x07, 0xbf, 0x0a, 0x05, 0x3e, 0x95, 0xef, 0x30, 0x80, 0x08, 0xaa, 0x87, 0x13, 0x07, 0xf0, 0x0f, 0x55, 0x45, 0x63, - 0x89, 0xe7, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x59, 0x45, 0x63, 0x94, 0xe7, 0x00, 0x13, 0x05, 0x30, 0x0c, 0xb2, 0x40, - 0x41, 0x01, 0x82, 0x80, 0x05, 0x71, 0x23, 0x2c, 0x81, 0x1c, 0x23, 0x2e, 0x11, 0x1c, 0x23, 0x2a, 0x91, 0x1c, 0x23, - 0x28, 0x21, 0x1d, 0x23, 0x26, 0x31, 0x1d, 0x23, 0x24, 0x41, 0x1d, 0x23, 0x22, 0x51, 0x1d, 0x23, 0x20, 0x61, 0x1d, - 0x23, 0x2e, 0x71, 0x1b, 0x23, 0x2c, 0x81, 0x1b, 0x23, 0x2a, 0x91, 0x1b, 0x23, 0x28, 0xa1, 0x1b, 0x23, 0x26, 0xb1, - 0x1b, 0x83, 0x46, 0x05, 0x00, 0x93, 0x07, 0x20, 0x0a, 0x2a, 0x84, 0x63, 0x82, 0xf6, 0x02, 0x03, 0x47, 0x15, 0x00, - 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x86, 0x57, 0x93, 0x85, 0x45, - 0x55, 0x13, 0x05, 0x85, 0x77, 0xef, 0x10, 0x80, 0x4f, 0x08, 0x11, 0xef, 0x10, 0x00, 0x75, 0x83, 0x47, 0x04, 0x00, - 0x05, 0x47, 0x23, 0x10, 0xe1, 0x0a, 0xc1, 0x46, 0x63, 0x8b, 0xd7, 0x46, 0x63, 0xee, 0xf6, 0x02, 0x91, 0x46, 0x63, - 0x83, 0xd7, 0x36, 0x63, 0xe1, 0xf6, 0x02, 0x63, 0x86, 0xe7, 0x06, 0x09, 0x47, 0x63, 0x81, 0xe7, 0x0e, 0x93, 0x07, - 0xe0, 0x07, 0x23, 0x00, 0xf1, 0x0a, 0x08, 0x11, 0xef, 0x10, 0xd0, 0x4d, 0x93, 0x07, 0x50, 0x05, 0xb1, 0xa9, 0x21, - 0x47, 0xe3, 0x95, 0xe7, 0xfe, 0x83, 0x47, 0x14, 0x00, 0xd1, 0xeb, 0xf5, 0x34, 0x15, 0xa9, 0x93, 0x06, 0x20, 0x0a, - 0x63, 0x85, 0xd7, 0x4e, 0x93, 0x06, 0x30, 0x0b, 0x63, 0x81, 0xd7, 0x48, 0x93, 0x06, 0x00, 0x02, 0xe3, 0x94, 0xd7, - 0xfc, 0x83, 0x47, 0x14, 0x00, 0x63, 0x99, 0xe7, 0x06, 0x03, 0x47, 0x24, 0x00, 0x95, 0x47, 0x63, 0x14, 0xf7, 0x06, - 0x85, 0x45, 0x61, 0x45, 0x39, 0x3b, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x08, 0xf5, 0x44, 0x13, 0x04, 0x80, 0xf8, 0x7d, - 0xa0, 0x03, 0x47, 0x14, 0x00, 0x89, 0x47, 0x63, 0x15, 0xf7, 0x04, 0x83, 0x47, 0x24, 0x00, 0x63, 0x8a, 0xe7, 0x04, - 0x63, 0x6b, 0xf7, 0x02, 0xa1, 0xe3, 0x83, 0x45, 0x34, 0x00, 0xf5, 0x47, 0x63, 0xe9, 0xb7, 0x02, 0x9e, 0x05, 0x13, - 0x06, 0x00, 0x08, 0x93, 0x85, 0x05, 0x10, 0x13, 0x05, 0x21, 0x0a, 0xef, 0x20, 0x90, 0x6f, 0x13, 0x04, 0x00, 0x08, - 0x08, 0x11, 0xa3, 0x00, 0x81, 0x0a, 0xef, 0x10, 0x70, 0x44, 0x93, 0x07, 0xa0, 0x0a, 0xd9, 0xa6, 0x13, 0x05, 0x80, - 0x1e, 0x63, 0x8d, 0xd7, 0x00, 0x13, 0x04, 0x10, 0xf8, 0xa1, 0xa8, 0x89, 0x65, 0x13, 0x06, 0x00, 0x08, 0x93, 0x85, - 0x05, 0x90, 0xf1, 0xb7, 0x13, 0x05, 0x00, 0x1f, 0xef, 0x10, 0x50, 0x22, 0x2a, 0xce, 0x11, 0x46, 0x6c, 0x08, 0x13, - 0x05, 0x21, 0x0a, 0xef, 0x40, 0xf0, 0x17, 0x11, 0x44, 0x7d, 0xbf, 0x83, 0x44, 0x14, 0x00, 0x2d, 0x34, 0x93, 0x07, - 0x10, 0x02, 0xe3, 0x95, 0xf4, 0xfc, 0xef, 0x10, 0xd0, 0x77, 0xef, 0x20, 0xd0, 0x20, 0xef, 0x30, 0x50, 0x40, 0xef, - 0x40, 0xc0, 0x15, 0x03, 0x45, 0x24, 0x02, 0x15, 0x3d, 0x93, 0x07, 0x30, 0x0c, 0x63, 0x0b, 0xf5, 0x02, 0x13, 0x04, - 0x70, 0xf8, 0xb3, 0x06, 0x80, 0x40, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, - 0xf6, 0xf6, 0x0f, 0x13, 0x06, 0x86, 0x59, 0x93, 0x85, 0x45, 0x55, 0x13, 0x05, 0x85, 0x77, 0x23, 0x00, 0xd1, 0x0a, - 0xef, 0x10, 0x40, 0x39, 0xa3, 0x00, 0x01, 0x0a, 0xf9, 0xb5, 0x83, 0x44, 0x24, 0x02, 0xef, 0xf0, 0x9f, 0x98, 0x8d, - 0x47, 0xe3, 0xe2, 0x97, 0xfc, 0x13, 0x06, 0x10, 0x08, 0x81, 0x45, 0x68, 0x08, 0xef, 0x40, 0xf0, 0x13, 0x13, 0x06, - 0x00, 0x02, 0x93, 0x05, 0x24, 0x00, 0x13, 0x05, 0xd1, 0x01, 0x23, 0x0e, 0x91, 0x00, 0xef, 0x40, 0xf0, 0x0e, 0xef, - 0x40, 0xa0, 0x0e, 0x37, 0x25, 0x00, 0x08, 0xef, 0x30, 0xc0, 0x03, 0x81, 0x46, 0x01, 0x46, 0x93, 0x05, 0xd1, 0x03, - 0x45, 0x45, 0xef, 0xf0, 0x9f, 0x9b, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x11, 0xf5, 0xf8, 0x81, 0x45, 0x68, 0x08, 0xef, - 0x30, 0xd0, 0x36, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0xe3, 0x18, 0xf5, 0xf6, 0x93, 0x06, 0x00, 0x02, 0x13, 0x06, - 0xd1, 0x01, 0x93, 0x05, 0xd1, 0x05, 0x49, 0x45, 0xef, 0xf0, 0xdf, 0x98, 0xaa, 0x84, 0xe3, 0x1c, 0x25, 0xf5, 0x85, - 0x45, 0x68, 0x08, 0xef, 0x30, 0x30, 0x34, 0x2a, 0x89, 0xe3, 0x15, 0x95, 0xf4, 0x83, 0x47, 0xc1, 0x01, 0x85, 0x46, - 0x13, 0x06, 0xb1, 0x01, 0x93, 0x05, 0xd1, 0x05, 0x4d, 0x45, 0xa3, 0x0d, 0xf1, 0x00, 0xef, 0xf0, 0x1f, 0x96, 0xaa, - 0x84, 0xe3, 0x16, 0x25, 0xf3, 0x89, 0x45, 0x68, 0x08, 0xef, 0x30, 0x70, 0x31, 0x2a, 0x89, 0xe3, 0x1f, 0x95, 0xf0, - 0x81, 0x46, 0x01, 0x46, 0x93, 0x05, 0xd1, 0x05, 0x51, 0x45, 0xef, 0xf0, 0xff, 0x93, 0xaa, 0x84, 0xe3, 0x15, 0x25, - 0xf1, 0x8d, 0x45, 0x68, 0x08, 0xef, 0x30, 0x50, 0x2f, 0x2a, 0x89, 0xe3, 0x1e, 0x95, 0xee, 0x91, 0x45, 0x68, 0x08, - 0xef, 0x30, 0x70, 0x2e, 0xaa, 0x84, 0xe3, 0x17, 0x25, 0xef, 0x95, 0x45, 0x68, 0x08, 0xef, 0x30, 0x90, 0x2d, 0xe3, - 0x11, 0x95, 0xee, 0xb7, 0x14, 0x20, 0x00, 0x13, 0x85, 0x04, 0x02, 0xef, 0x30, 0xb0, 0x31, 0x37, 0x19, 0x20, 0x00, - 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0xd1, 0x03, 0x13, 0x05, 0x09, 0x03, 0xef, 0x40, 0xd0, 0x00, 0x37, 0x15, 0x20, - 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0xd1, 0x07, 0x13, 0x05, 0x05, 0x05, 0xef, 0x40, 0x80, 0x7f, 0x83, 0x49, - 0x24, 0x02, 0x8d, 0x47, 0x63, 0xf3, 0x37, 0x01, 0xb9, 0x34, 0xb7, 0x5c, 0x10, 0x00, 0xef, 0x10, 0x30, 0x43, 0x01, - 0x4d, 0x93, 0x8c, 0x4c, 0x6c, 0x0d, 0x4a, 0xfd, 0x5a, 0x13, 0x0b, 0x00, 0x0f, 0xc1, 0x6b, 0x37, 0x0c, 0x00, 0x01, - 0x13, 0x17, 0x2d, 0x00, 0xb3, 0x87, 0xec, 0x00, 0x83, 0xcd, 0x07, 0x00, 0x3a, 0xc6, 0x63, 0x81, 0x0d, 0x08, 0x80, - 0x43, 0x13, 0x55, 0x44, 0x01, 0x41, 0x80, 0x75, 0x3c, 0x3d, 0x88, 0x32, 0x47, 0x63, 0x68, 0x8a, 0x00, 0x0e, 0x04, - 0x33, 0x94, 0x8a, 0x00, 0x13, 0x44, 0xf4, 0xff, 0x61, 0x8d, 0xb3, 0x86, 0xec, 0x00, 0x83, 0xc6, 0x16, 0x00, 0x33, - 0x55, 0x35, 0x01, 0x93, 0x77, 0x15, 0x00, 0x93, 0xf6, 0x06, 0x0f, 0x63, 0x82, 0x66, 0x05, 0x93, 0x76, 0x05, 0x10, - 0x99, 0xc2, 0x93, 0xe7, 0x27, 0x00, 0xb3, 0x76, 0x75, 0x01, 0x99, 0xc2, 0x93, 0xe7, 0x47, 0x00, 0x33, 0x75, 0x85, - 0x01, 0x19, 0xc1, 0x93, 0xe7, 0x87, 0x00, 0x66, 0x97, 0x18, 0x43, 0xbd, 0x65, 0xc2, 0x07, 0xf9, 0x8d, 0x21, 0x83, - 0x3d, 0x8b, 0x22, 0x07, 0x4d, 0x8f, 0xb3, 0x65, 0xb7, 0x01, 0x6a, 0x85, 0xdd, 0x8d, 0xef, 0x10, 0x30, 0x3b, 0x05, - 0x0d, 0xad, 0xbf, 0xf9, 0xdf, 0x93, 0x07, 0xf0, 0x0f, 0xe1, 0xbf, 0xef, 0x10, 0xd0, 0x37, 0xb7, 0x37, 0x20, 0x00, - 0x13, 0x07, 0xa0, 0x0a, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0x09, 0x03, 0x13, 0x05, 0x21, 0x0a, 0x23, 0xa4, 0xe7, - 0xf4, 0xef, 0x40, 0x00, 0x72, 0x41, 0x46, 0x93, 0x85, 0x04, 0x02, 0x13, 0x05, 0x21, 0x0c, 0xef, 0x40, 0x20, 0x71, - 0xef, 0x30, 0xf0, 0x76, 0x13, 0x04, 0x00, 0x03, 0xef, 0xf0, 0x2f, 0xfa, 0xa1, 0xb3, 0xb7, 0x37, 0x20, 0x00, 0x03, - 0xa7, 0x87, 0xf4, 0x93, 0x07, 0xa0, 0x0a, 0x83, 0x44, 0x14, 0x00, 0x63, 0x14, 0xf7, 0x0e, 0x91, 0xe4, 0x13, 0x04, - 0x10, 0xf8, 0xef, 0xf0, 0xef, 0xf9, 0x71, 0xbb, 0xb7, 0x39, 0x20, 0x00, 0x83, 0xa7, 0x49, 0xf4, 0x93, 0x89, 0x49, - 0xf4, 0xad, 0xcb, 0x09, 0x04, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x09, 0xf4, 0x83, 0x26, 0x09, 0x00, 0x03, 0xa7, - 0x09, 0x00, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x77, 0xa6, - 0x96, 0x13, 0x06, 0xc6, 0x58, 0x93, 0x85, 0xc5, 0x56, 0xef, 0x10, 0x80, 0x11, 0x03, 0x25, 0x09, 0x00, 0x83, 0xa7, - 0x09, 0x00, 0x33, 0x87, 0xa4, 0x00, 0xe3, 0xe6, 0xe7, 0xfa, 0x85, 0x67, 0x93, 0x87, 0x07, 0x02, 0xe3, 0xe1, 0xe7, - 0xfa, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x26, 0x86, 0x3e, 0x95, 0xa2, 0x85, 0xef, 0x40, 0xa0, 0x67, - 0x83, 0x27, 0x09, 0x00, 0xbe, 0x94, 0x83, 0xa7, 0x09, 0x00, 0x23, 0x20, 0x99, 0x00, 0xbd, 0xe3, 0x75, 0x54, 0x39, - 0xbb, 0x89, 0x47, 0xe3, 0xfb, 0x97, 0xf6, 0x03, 0x49, 0x34, 0x00, 0x83, 0x47, 0x24, 0x00, 0xf9, 0x14, 0x22, 0x09, - 0x3e, 0x99, 0x85, 0x67, 0x93, 0x06, 0xf9, 0xff, 0x13, 0x87, 0xf7, 0x00, 0x11, 0x04, 0xe3, 0x6c, 0xd7, 0xf4, 0x37, - 0x0a, 0x20, 0x00, 0x13, 0x0a, 0x0a, 0x00, 0x3e, 0x9a, 0x41, 0x09, 0x93, 0x07, 0xf0, 0x07, 0xa3, 0x0c, 0xfa, 0x06, - 0x23, 0xa0, 0x29, 0x01, 0xef, 0x10, 0xb0, 0x43, 0xef, 0x20, 0xa0, 0x6c, 0xef, 0x30, 0x30, 0x0c, 0xb7, 0x37, 0x20, - 0x00, 0x23, 0x28, 0x2a, 0x07, 0x23, 0x2a, 0x0a, 0x06, 0x23, 0xa0, 0x07, 0xf4, 0x2d, 0xbf, 0x13, 0x04, 0x60, 0xf8, - 0x39, 0xbf, 0xe3, 0x9e, 0xf4, 0xf8, 0x01, 0x44, 0x89, 0xb1, 0x83, 0x47, 0x14, 0x00, 0xe3, 0x9a, 0x07, 0xc4, 0xef, - 0x10, 0xd0, 0x10, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x04, 0x05, 0xc4, 0x83, 0x20, 0xc1, 0x1d, 0x03, 0x24, 0x81, 0x1d, - 0x83, 0x24, 0x41, 0x1d, 0x03, 0x29, 0x01, 0x1d, 0x83, 0x29, 0xc1, 0x1c, 0x03, 0x2a, 0x81, 0x1c, 0x83, 0x2a, 0x41, - 0x1c, 0x03, 0x2b, 0x01, 0x1c, 0x83, 0x2b, 0xc1, 0x1b, 0x03, 0x2c, 0x81, 0x1b, 0x83, 0x2c, 0x41, 0x1b, 0x03, 0x2d, - 0x01, 0x1b, 0x83, 0x2d, 0xc1, 0x1a, 0x3e, 0x85, 0x3d, 0x61, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa8, 0xa7, - 0xf4, 0x85, 0xbe, 0x83, 0x46, 0x14, 0x00, 0xe3, 0x9e, 0xe6, 0xbe, 0x83, 0x47, 0x24, 0x00, 0x63, 0x8b, 0xd7, 0x02, - 0x0d, 0x47, 0xe3, 0x97, 0xe7, 0xbe, 0xa1, 0x45, 0x01, 0x45, 0xef, 0xf0, 0x5f, 0x8a, 0x93, 0x07, 0xa0, 0x0a, 0x2a, - 0x84, 0xe3, 0x13, 0xf5, 0xb8, 0xb7, 0xb5, 0xb5, 0x61, 0x93, 0x85, 0x55, 0x49, 0x13, 0x05, 0x80, 0x1f, 0xef, 0x10, - 0x00, 0x67, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0x87, 0xf2, 0x95, 0xb7, 0xb7, 0x15, 0x78, 0x4a, 0x93, 0x85, 0x95, - 0x21, 0x13, 0x05, 0x80, 0x1f, 0xef, 0x10, 0x60, 0x65, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xac, - 0xe7, 0xf2, 0x99, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x47, 0xf3, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1f, 0xf7, - 0xb2, 0x83, 0x47, 0x14, 0x00, 0xe3, 0x96, 0x07, 0xb8, 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x0a, 0xef, 0x00, - 0xd0, 0x6b, 0x2a, 0x84, 0xe3, 0x51, 0x05, 0xb6, 0xc9, 0xbe, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, - 0xc8, 0x4e, 0xc6, 0x8d, 0x47, 0x63, 0xf4, 0xa7, 0x00, 0xef, 0xf0, 0x8f, 0xf6, 0x89, 0x67, 0x2a, 0x84, 0x93, 0x87, - 0x07, 0xbf, 0x0a, 0x05, 0x81, 0x45, 0x3e, 0x95, 0x13, 0x09, 0x04, 0x0e, 0xef, 0x20, 0x10, 0x2b, 0x16, 0x09, 0x81, - 0x44, 0x93, 0x09, 0x00, 0x02, 0x33, 0x05, 0x99, 0x00, 0x81, 0x45, 0x91, 0x04, 0xef, 0x20, 0xd0, 0x29, 0xe3, 0x9a, - 0x34, 0xff, 0x22, 0x85, 0xef, 0xf0, 0x1f, 0x9b, 0x59, 0x47, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xe5, 0x00, 0x93, - 0x07, 0x50, 0x05, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x3e, 0x85, 0x05, 0x61, 0x82, 0x80, - 0x41, 0x11, 0x05, 0x45, 0x06, 0xc6, 0xef, 0x30, 0xf0, 0x7a, 0xb2, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, - 0x0a, 0x23, 0xa6, 0xe7, 0xf4, 0x41, 0x01, 0x82, 0x80, 0x31, 0x71, 0x22, 0xdd, 0x37, 0x34, 0x20, 0x00, 0x93, 0x07, - 0x50, 0x05, 0x06, 0xdf, 0x26, 0xdb, 0x4a, 0xd9, 0x56, 0xd3, 0x5e, 0xcf, 0x4e, 0xd7, 0x52, 0xd5, 0x5a, 0xd1, 0x62, - 0xcd, 0x66, 0xcb, 0x6a, 0xc9, 0x6e, 0xc7, 0x37, 0x39, 0x20, 0x00, 0xb7, 0x34, 0x20, 0x00, 0xb7, 0x3b, 0x20, 0x00, - 0x13, 0x04, 0x44, 0xf3, 0x23, 0x26, 0xf9, 0xf4, 0x23, 0xac, 0xf4, 0xf2, 0x23, 0xa8, 0xfb, 0xf4, 0x1c, 0xc0, 0xef, - 0x10, 0xa0, 0x32, 0xef, 0x10, 0x00, 0x4b, 0x13, 0x07, 0xc9, 0xf4, 0x3a, 0xc8, 0x13, 0x87, 0x84, 0xf3, 0x3a, 0xca, - 0x13, 0x87, 0x0b, 0xf5, 0x93, 0x07, 0xa0, 0x0a, 0x3a, 0xc6, 0xb7, 0x5a, 0x10, 0x00, 0x85, 0x45, 0x63, 0x0a, 0xf5, - 0x00, 0x13, 0x85, 0x4a, 0x55, 0xef, 0x00, 0xd0, 0x70, 0xef, 0x10, 0xc0, 0x44, 0xef, 0xf0, 0x0f, 0xe8, 0x41, 0x45, - 0xef, 0xf0, 0x2f, 0xf3, 0x08, 0xc0, 0xb7, 0x07, 0x01, 0x02, 0x80, 0x57, 0x98, 0x5b, 0x29, 0x45, 0x59, 0x8c, 0x98, - 0x5f, 0x59, 0x8c, 0x13, 0x77, 0xf4, 0x87, 0x98, 0xd7, 0x98, 0xdb, 0x98, 0xdf, 0xd8, 0x43, 0x13, 0x67, 0x87, 0x00, - 0xd8, 0xc3, 0xef, 0x10, 0x40, 0x2d, 0xef, 0x30, 0x10, 0x27, 0x13, 0x75, 0x05, 0x78, 0x11, 0xc5, 0x13, 0x05, 0x00, - 0x78, 0x81, 0x45, 0xef, 0x30, 0x70, 0x1f, 0xb7, 0x07, 0x01, 0x02, 0x80, 0xd7, 0x80, 0xdb, 0x37, 0x15, 0x10, 0x00, - 0x80, 0xdf, 0x13, 0x05, 0x85, 0x9f, 0xef, 0x10, 0x00, 0x61, 0x13, 0x05, 0x00, 0x1f, 0xef, 0x10, 0x40, 0x45, 0x37, - 0x56, 0x10, 0x00, 0xb7, 0x59, 0x10, 0x00, 0xaa, 0x86, 0x13, 0x06, 0x06, 0x5a, 0x93, 0x85, 0x4a, 0x55, 0x13, 0x85, - 0x89, 0x77, 0xef, 0x00, 0x50, 0x61, 0xef, 0x30, 0xf0, 0x22, 0x93, 0x07, 0x50, 0x05, 0x63, 0x1e, 0xf5, 0x00, 0x37, - 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x06, 0x5b, 0x93, 0x85, 0x4a, 0x55, 0x13, 0x05, 0x45, 0x57, - 0xef, 0x00, 0x10, 0x5f, 0xef, 0x20, 0x20, 0x20, 0x51, 0x45, 0xef, 0x10, 0xc0, 0x40, 0x1d, 0x89, 0xef, 0x20, 0x40, - 0x20, 0xef, 0x10, 0x30, 0x74, 0xef, 0x20, 0xa0, 0x76, 0xef, 0x20, 0x40, 0x7b, 0xef, 0x20, 0x90, 0x2a, 0x37, 0x35, - 0x00, 0x08, 0xef, 0x20, 0x10, 0x2b, 0x6c, 0x10, 0x11, 0x46, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0x30, 0x32, 0x37, - 0x35, 0x00, 0x08, 0xef, 0x20, 0x10, 0x2e, 0x32, 0x55, 0xef, 0x20, 0x50, 0x1f, 0x09, 0x65, 0x13, 0x05, 0x05, 0x98, - 0xef, 0x20, 0x50, 0x03, 0xfd, 0x57, 0x8d, 0x45, 0x63, 0x12, 0xf5, 0x02, 0x01, 0x44, 0x13, 0x09, 0x00, 0x18, 0x22, - 0x85, 0xef, 0xf0, 0x8f, 0xe2, 0xaa, 0x84, 0x22, 0x85, 0xef, 0xf0, 0x2f, 0xfb, 0x93, 0x47, 0xf5, 0xff, 0x33, 0xf5, - 0x97, 0x00, 0x19, 0xc5, 0x89, 0x45, 0x13, 0x85, 0x4a, 0x55, 0xef, 0x00, 0xb0, 0x5e, 0xcd, 0xb5, 0x11, 0x04, 0xe3, - 0x1d, 0x24, 0xfd, 0x37, 0x55, 0x10, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x13, 0x05, 0x45, 0x72, - 0x23, 0xa4, 0xe7, 0xf4, 0xef, 0x10, 0x30, 0x10, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x40, 0x05, 0x93, 0x85, 0x05, - 0x67, 0x68, 0x10, 0xef, 0x40, 0x00, 0x2d, 0x60, 0x10, 0x48, 0x40, 0x01, 0xc5, 0xef, 0x20, 0x80, 0x7c, 0x48, 0xc0, - 0x31, 0x04, 0x1c, 0x01, 0xe3, 0x99, 0x87, 0xfe, 0x37, 0x55, 0x10, 0x00, 0x1d, 0x46, 0x6c, 0x10, 0x13, 0x05, 0x05, - 0x73, 0xef, 0x20, 0x00, 0x36, 0xef, 0x20, 0x40, 0x4c, 0xef, 0xf0, 0xef, 0xc1, 0x05, 0x45, 0xef, 0x10, 0xa0, 0x77, - 0xef, 0x30, 0xa0, 0x50, 0xef, 0x30, 0xf0, 0x29, 0x01, 0x45, 0xef, 0x30, 0x70, 0x59, 0x37, 0x0a, 0x20, 0x00, 0x05, - 0x6c, 0x93, 0x07, 0x0a, 0x00, 0xb7, 0x14, 0x20, 0x00, 0x33, 0x8b, 0x87, 0x01, 0x93, 0x84, 0xc4, 0x07, 0xef, 0x10, - 0x80, 0x5d, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf4, 0x63, 0x81, 0x07, 0x10, 0x37, 0x37, 0x20, 0x00, 0x03, - 0x27, 0x07, 0xf4, 0x63, 0x9b, 0xe7, 0x0e, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xc7, 0xc7, 0xf3, 0x93, 0x87, 0xc7, 0xf3, - 0x3e, 0xcc, 0xe3, 0x1e, 0x07, 0x2e, 0x03, 0x26, 0x0b, 0x07, 0x93, 0x07, 0xf0, 0x07, 0x37, 0x14, 0x20, 0x00, 0xa3, - 0x0c, 0xfb, 0x06, 0xc1, 0x4c, 0x13, 0x0d, 0x0a, 0x00, 0x13, 0x04, 0x04, 0x00, 0x63, 0xfd, 0xcc, 0x0a, 0x13, 0x09, - 0x06, 0xff, 0xef, 0x10, 0x40, 0x67, 0x01, 0x45, 0xef, 0x30, 0x60, 0x54, 0x4a, 0x86, 0x63, 0xf3, 0x2c, 0x01, 0x41, - 0x46, 0x93, 0x05, 0x0a, 0x00, 0x68, 0x10, 0xef, 0x30, 0xa0, 0x56, 0xef, 0x10, 0xa0, 0x6c, 0xb7, 0x57, 0x10, 0x00, - 0x23, 0x0c, 0xa4, 0x06, 0x93, 0x87, 0x47, 0x6c, 0x03, 0xc7, 0x07, 0x00, 0x63, 0x10, 0x07, 0x14, 0x03, 0x29, 0x04, - 0x07, 0xc1, 0x4b, 0x63, 0xf5, 0x2b, 0x07, 0x01, 0x45, 0xef, 0x30, 0xc0, 0x50, 0x41, 0x19, 0x4a, 0x86, 0x93, 0x05, - 0x0a, 0x00, 0x13, 0x05, 0x0a, 0x00, 0xef, 0x30, 0x20, 0x53, 0xb7, 0x1c, 0x20, 0x00, 0x13, 0x85, 0x0c, 0x02, 0xef, - 0x30, 0xe0, 0x6f, 0xef, 0x30, 0xc0, 0x74, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x5d, 0x10, 0x00, 0xaa, 0x86, 0x13, 0x06, - 0x06, 0x5c, 0x93, 0x85, 0x8d, 0x53, 0x13, 0x85, 0x89, 0x77, 0xef, 0x00, 0xf0, 0x41, 0x93, 0x85, 0x0c, 0x02, 0x41, - 0x46, 0x33, 0x05, 0x2d, 0x01, 0xef, 0x00, 0xf0, 0x30, 0xaa, 0x8c, 0x63, 0x0f, 0x05, 0x0e, 0x89, 0x45, 0x13, 0x85, - 0x8d, 0x53, 0xef, 0x00, 0x70, 0x47, 0x93, 0x07, 0xb0, 0x07, 0xa3, 0x0c, 0xf4, 0x06, 0x37, 0x55, 0x10, 0x00, 0x91, - 0x45, 0x13, 0x05, 0xc5, 0x56, 0xef, 0x00, 0x10, 0x46, 0xef, 0xe0, 0x1f, 0xea, 0xef, 0xe0, 0x5f, 0xfa, 0xef, 0xf0, - 0x4f, 0xa2, 0xef, 0x10, 0x00, 0x4b, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x1d, 0xf5, 0x08, 0xb7, 0x37, 0x20, - 0x00, 0x83, 0xc7, 0xc7, 0xf3, 0xd9, 0xe7, 0xef, 0x00, 0xd0, 0x7a, 0xe3, 0x16, 0x85, 0x18, 0xd2, 0x47, 0x9c, 0x43, - 0x63, 0x9a, 0xa7, 0x00, 0x13, 0x04, 0xa0, 0x0a, 0xef, 0x30, 0xf0, 0x3a, 0xe3, 0x1e, 0x85, 0xfe, 0xef, 0x10, 0x20, - 0x10, 0xb2, 0x47, 0x98, 0x43, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1e, 0xf7, 0x14, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, - 0x46, 0x61, 0x93, 0x85, 0x4a, 0x55, 0x13, 0x85, 0x89, 0x77, 0xef, 0x00, 0x70, 0x38, 0xef, 0xf0, 0x8f, 0x9c, 0x37, - 0x25, 0x00, 0x08, 0xef, 0x20, 0x70, 0x0a, 0xef, 0xf0, 0x0f, 0x9a, 0xef, 0x20, 0xa0, 0x59, 0xef, 0x10, 0x10, 0x0f, - 0xef, 0x20, 0x50, 0x23, 0xef, 0xe0, 0xbf, 0xe5, 0x32, 0x47, 0x37, 0x56, 0x10, 0x00, 0x93, 0x07, 0x50, 0x05, 0x13, - 0x06, 0x06, 0x62, 0x93, 0x85, 0x4a, 0x55, 0x13, 0x85, 0x89, 0x77, 0x1c, 0xc3, 0xef, 0x00, 0xb0, 0x34, 0xef, 0x20, - 0x30, 0x23, 0xef, 0x10, 0x50, 0x3b, 0xef, 0x20, 0x20, 0x5b, 0xef, 0x30, 0x90, 0x08, 0xc2, 0x47, 0x98, 0x43, 0x93, - 0x07, 0x50, 0x05, 0xe3, 0x03, 0xf7, 0xe4, 0x71, 0xb9, 0x63, 0x1c, 0xe5, 0x00, 0x83, 0xc7, 0x17, 0x00, 0xbd, 0x8b, - 0xe3, 0x8d, 0x07, 0xea, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0xa0, 0x60, 0x7d, 0xb5, 0x91, 0x07, 0x4d, 0xb5, 0x03, - 0x29, 0x04, 0x07, 0xe3, 0xef, 0x2b, 0x0d, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0xc5, 0x56, 0xef, 0x00, - 0x10, 0x37, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x56, 0x95, 0x45, 0xef, 0x00, 0x30, 0x36, 0x13, 0x05, 0xf0, - 0x07, 0x09, 0xb7, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0xc7, 0xf5, 0x14, 0x43, 0xb7, 0x55, 0x10, 0x00, 0xde, 0x87, - 0x13, 0x86, 0x16, 0x00, 0x10, 0xc3, 0x03, 0x47, 0x84, 0x07, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0x06, 0x5d, 0x93, - 0x85, 0xc5, 0x56, 0x13, 0x85, 0x89, 0x77, 0xef, 0x00, 0x90, 0x2b, 0x03, 0x47, 0x84, 0x07, 0x93, 0x06, 0x20, 0x04, - 0x63, 0x07, 0xd7, 0x4c, 0x63, 0xeb, 0xe6, 0x18, 0x93, 0x06, 0x10, 0x02, 0x63, 0x0f, 0xd7, 0x3c, 0x63, 0xe3, 0xe6, - 0x08, 0xc5, 0x46, 0x63, 0x04, 0xd7, 0x32, 0x63, 0xe9, 0xe6, 0x02, 0x85, 0x46, 0x63, 0x09, 0xd7, 0x24, 0xc1, 0x46, - 0x63, 0x02, 0xd7, 0x26, 0x89, 0x4c, 0xe5, 0xac, 0x13, 0x07, 0x07, 0xfa, 0x13, 0x77, 0xf7, 0x0f, 0xc5, 0x46, 0xe3, - 0xe9, 0xe6, 0xfe, 0xb7, 0x56, 0x10, 0x00, 0x0a, 0x07, 0x93, 0x86, 0x86, 0x62, 0x36, 0x97, 0x18, 0x43, 0x02, 0x87, - 0xc9, 0x46, 0x63, 0x0e, 0xd7, 0x34, 0x93, 0x06, 0x00, 0x02, 0xe3, 0x1a, 0xd7, 0xfc, 0x21, 0x47, 0x93, 0x0c, 0x00, - 0x08, 0x63, 0x92, 0xeb, 0x2c, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x94, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x80, - 0x63, 0x9e, 0x07, 0x4a, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xea, 0x87, 0x4a, 0x22, 0x85, 0xef, 0x10, 0x50, 0x09, 0xfd, - 0x57, 0x63, 0x14, 0xf5, 0x4a, 0x83, 0x25, 0x4d, 0x00, 0x22, 0x85, 0xef, 0x10, 0x90, 0x11, 0x81, 0xae, 0x93, 0x06, - 0x10, 0x03, 0x63, 0x08, 0xd7, 0x38, 0x63, 0xec, 0xe6, 0x08, 0x93, 0x06, 0x20, 0x02, 0x63, 0x09, 0xd7, 0x36, 0x93, - 0x06, 0x00, 0x03, 0xe3, 0x1e, 0xd7, 0xf6, 0x11, 0x47, 0x93, 0x0c, 0x00, 0x08, 0x63, 0x96, 0xeb, 0x26, 0x03, 0x27, - 0x0d, 0x00, 0x21, 0x83, 0x93, 0x16, 0x07, 0x01, 0x0d, 0x8b, 0xc1, 0x82, 0x63, 0x12, 0x07, 0x46, 0x93, 0x07, 0xf0, - 0x1f, 0x63, 0xee, 0xd7, 0x44, 0x83, 0x47, 0x3d, 0x00, 0x7d, 0x47, 0x63, 0x69, 0xf7, 0x44, 0x13, 0xd4, 0x37, 0x00, - 0x36, 0x94, 0x0a, 0x04, 0x62, 0x94, 0x93, 0xfd, 0x77, 0x00, 0x22, 0x85, 0x05, 0x49, 0xef, 0x20, 0x60, 0x4c, 0x33, - 0x19, 0xb9, 0x01, 0xb3, 0x77, 0xa9, 0x00, 0xaa, 0x8c, 0x63, 0x80, 0x07, 0x22, 0x8a, 0x0d, 0xbd, 0x45, 0xb3, 0x95, - 0xb5, 0x01, 0x93, 0xc5, 0xf5, 0xff, 0x22, 0x85, 0xef, 0x20, 0xa0, 0x4e, 0x22, 0x85, 0x13, 0x49, 0xf9, 0xff, 0xef, - 0x20, 0xc0, 0x49, 0x33, 0x79, 0x99, 0x01, 0x63, 0x0e, 0x25, 0x1f, 0x09, 0x65, 0x81, 0x45, 0x13, 0x05, 0x05, 0x98, - 0xef, 0x20, 0xc0, 0x4c, 0x75, 0xaa, 0x93, 0x06, 0x00, 0x04, 0x63, 0x0d, 0xd7, 0x30, 0x93, 0x06, 0x10, 0x04, 0xe3, - 0x14, 0xd7, 0xee, 0x0d, 0x47, 0x63, 0x90, 0xeb, 0x72, 0x83, 0x27, 0x0d, 0x00, 0x13, 0x07, 0xf0, 0x1f, 0xa1, 0x83, - 0xc2, 0x07, 0xc1, 0x83, 0x63, 0x6a, 0xf7, 0x3c, 0xef, 0x10, 0xf0, 0x48, 0xef, 0x20, 0xe0, 0x75, 0x83, 0x27, 0x0d, - 0x00, 0x91, 0x65, 0x93, 0x85, 0x05, 0x20, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, 0xa6, 0x07, 0x37, 0x15, 0x20, 0x00, - 0xbe, 0x95, 0x13, 0x05, 0x05, 0x08, 0xef, 0x10, 0xd0, 0x0a, 0x2a, 0x84, 0xef, 0x20, 0xa0, 0x75, 0x93, 0x07, 0xb0, - 0x1d, 0xe3, 0xe7, 0x87, 0xa8, 0x93, 0x05, 0x44, 0x00, 0x39, 0xa4, 0x93, 0x06, 0x10, 0x07, 0x63, 0xe9, 0xe6, 0x02, - 0x93, 0x06, 0xf0, 0x05, 0xe3, 0xe4, 0xe6, 0xe8, 0x93, 0x06, 0x00, 0x05, 0xe3, 0x1e, 0xd7, 0xe6, 0x09, 0x47, 0x93, - 0x0c, 0x00, 0x08, 0x63, 0x96, 0xeb, 0x16, 0x03, 0x44, 0x1d, 0x00, 0x37, 0x15, 0x20, 0x00, 0x13, 0x05, 0x05, 0x08, - 0xa2, 0x85, 0xef, 0xe0, 0x9f, 0xc7, 0xd9, 0xb7, 0x93, 0x06, 0x20, 0x08, 0x63, 0x09, 0xd7, 0x64, 0x63, 0xed, 0xe6, - 0x04, 0x93, 0x06, 0x00, 0x08, 0x63, 0x00, 0xd7, 0x5e, 0x93, 0x06, 0x10, 0x08, 0xe3, 0x11, 0xd7, 0xe4, 0x0d, 0x47, - 0x93, 0x0c, 0x00, 0x08, 0x63, 0x99, 0xeb, 0x12, 0x03, 0x45, 0x1d, 0x00, 0x3d, 0x47, 0x81, 0x47, 0x63, 0x6e, 0xa7, - 0x00, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x89, 0x47, 0x33, 0x57, 0xa7, 0x00, 0x05, 0x8b, 0x01, 0xc7, - 0xef, 0xe0, 0xff, 0xd6, 0xaa, 0x87, 0xfd, 0x17, 0x09, 0x47, 0x63, 0x68, 0xf7, 0x30, 0x37, 0x65, 0x10, 0x00, 0x13, - 0x05, 0x85, 0x87, 0xaa, 0x97, 0x83, 0xcc, 0x07, 0x00, 0xd5, 0xa8, 0x93, 0x06, 0x00, 0x09, 0xe3, 0x1a, 0xd7, 0xde, - 0x13, 0x07, 0x40, 0x02, 0x93, 0x0c, 0x00, 0x08, 0x63, 0x91, 0xeb, 0x0e, 0xef, 0x20, 0x20, 0x01, 0xef, 0x20, 0x60, - 0x67, 0xef, 0x20, 0xa0, 0x01, 0x2a, 0x89, 0xef, 0x20, 0xc0, 0x00, 0xef, 0x20, 0xa0, 0x68, 0x13, 0x07, 0xa0, 0x0a, - 0x63, 0x17, 0xe9, 0x2c, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0x80, 0x33, 0x23, 0x2a, 0x74, 0x07, 0x45, 0xa8, 0x13, - 0x07, 0x1c, 0x00, 0x93, 0x0c, 0x00, 0x08, 0x63, 0x65, 0x77, 0x0b, 0xde, 0x85, 0x13, 0x05, 0x0a, 0x00, 0xef, 0xe0, - 0xff, 0xee, 0x61, 0xa8, 0x13, 0x07, 0x40, 0x02, 0x63, 0x9d, 0xeb, 0x5c, 0x03, 0x25, 0x0d, 0x00, 0x0d, 0x44, 0x21, - 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0x68, 0xa4, 0x28, 0xef, 0xf0, 0x8f, 0xa7, 0xd5, 0x47, 0x63, 0x13, 0xf5, 0x28, - 0x03, 0x29, 0x0d, 0x00, 0x13, 0x59, 0x89, 0x00, 0x42, 0x09, 0x13, 0x59, 0x09, 0x01, 0xe3, 0x62, 0x24, 0x97, 0x13, - 0x04, 0x09, 0x0e, 0x16, 0x04, 0x91, 0x4c, 0x71, 0x14, 0x93, 0x0b, 0xa0, 0x0a, 0x93, 0x0d, 0x40, 0x02, 0xb3, 0x05, - 0x9d, 0x01, 0x11, 0x46, 0x68, 0x10, 0xef, 0x30, 0x30, 0x56, 0xb2, 0x55, 0x33, 0x05, 0x94, 0x01, 0xef, 0x20, 0xc0, - 0x36, 0x63, 0x07, 0x75, 0x01, 0x4a, 0x85, 0xef, 0xf0, 0x9f, 0x83, 0xdd, 0x4c, 0x0d, 0xa8, 0x91, 0x0c, 0xe3, 0x9d, - 0xbc, 0xfd, 0x89, 0x67, 0x93, 0x87, 0x07, 0xbf, 0x13, 0x15, 0x29, 0x00, 0xb7, 0xf5, 0xf0, 0xf0, 0x3e, 0x95, 0x93, - 0x85, 0x05, 0x0f, 0xef, 0x20, 0xe0, 0x2e, 0x4a, 0x85, 0xef, 0xf0, 0x6f, 0xa0, 0x93, 0x07, 0x30, 0x0c, 0xe3, 0x1a, - 0xf5, 0xfc, 0x93, 0x0c, 0x30, 0x0c, 0x13, 0x06, 0x0c, 0x01, 0x81, 0x45, 0x26, 0x85, 0xef, 0x30, 0xb0, 0x54, 0x93, - 0x07, 0x00, 0x08, 0xe3, 0x81, 0xfc, 0xc8, 0x13, 0xf5, 0xfc, 0x0f, 0x4d, 0xa3, 0x0d, 0x47, 0x63, 0x94, 0xeb, 0x52, - 0x03, 0x25, 0x0d, 0x00, 0x0d, 0x44, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0x6f, 0xa4, 0x1c, 0xef, 0xf0, 0x6f, - 0x9c, 0x93, 0x07, 0x30, 0x0c, 0x63, 0x04, 0xf5, 0x00, 0xaa, 0x8c, 0xc9, 0xb7, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, - 0xc2, 0x07, 0xc1, 0x83, 0xe3, 0x68, 0xf4, 0x8a, 0x93, 0x87, 0x07, 0x0e, 0x13, 0x94, 0x57, 0x00, 0x13, 0x09, 0x00, - 0x02, 0x33, 0x85, 0x8c, 0x00, 0xef, 0x20, 0xa0, 0x1b, 0xb7, 0x17, 0x20, 0x00, 0x93, 0x87, 0x07, 0x08, 0x2a, 0xd6, - 0x11, 0x46, 0x33, 0x85, 0x97, 0x01, 0x6c, 0x10, 0x91, 0x0c, 0xef, 0x30, 0x10, 0x4a, 0xe3, 0x90, 0x2c, 0xff, 0x93, - 0x05, 0x40, 0x02, 0x26, 0x85, 0xf1, 0xbd, 0x0d, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x9a, 0xeb, 0xf6, 0x03, 0x25, - 0x0d, 0x00, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0xe8, 0xab, 0x16, 0xef, 0xf0, 0x8f, 0x95, 0xd5, 0x47, 0x63, - 0x03, 0xf5, 0x16, 0xd9, 0x47, 0x93, 0x0c, 0x30, 0x0c, 0xe3, 0x09, 0xf5, 0xf4, 0x03, 0x25, 0x0d, 0x00, 0x21, 0x81, - 0x42, 0x05, 0x41, 0x81, 0xef, 0xf0, 0x4f, 0xf4, 0x93, 0x07, 0xa0, 0x0a, 0x15, 0xbf, 0x0d, 0x47, 0x93, 0x0c, 0x00, - 0x08, 0xe3, 0x9a, 0xeb, 0xf2, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x81, - 0x63, 0x96, 0x07, 0x12, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe2, 0xa7, 0x12, 0xef, 0x10, 0x60, 0x50, 0xc8, 0xc0, 0xa1, - 0x45, 0x41, 0xbf, 0x05, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x93, 0xeb, 0xf0, 0x01, 0x45, 0xef, 0x10, 0x70, 0x19, - 0xe5, 0xbd, 0x0d, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x9a, 0xeb, 0xee, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, - 0x95, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x81, 0x63, 0x96, 0x07, 0x0e, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe2, 0xa7, 0x0e, - 0xef, 0xf0, 0x8f, 0x88, 0xc1, 0xb7, 0x93, 0x07, 0xb9, 0xfe, 0x13, 0x07, 0xa0, 0x1d, 0x93, 0x0c, 0x00, 0x08, 0xe3, - 0x62, 0xf7, 0xec, 0x03, 0x25, 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0xee, - 0xa7, 0x0a, 0x11, 0x64, 0x26, 0x05, 0x13, 0x04, 0x04, 0x20, 0x22, 0x95, 0xef, 0x10, 0xb0, 0x0f, 0x93, 0x07, 0xa0, - 0x0a, 0xaa, 0x8d, 0xc1, 0x4c, 0xe3, 0x1c, 0xf5, 0xe8, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0xff, 0x9a, 0xef, 0x20, - 0x80, 0x42, 0x83, 0x27, 0x0d, 0x00, 0xb7, 0x05, 0x20, 0x00, 0x74, 0x10, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, 0xa6, - 0x07, 0x33, 0x85, 0x87, 0x00, 0x13, 0x06, 0xc9, 0xfe, 0x93, 0x85, 0x45, 0x00, 0xef, 0x10, 0x80, 0x7f, 0x2a, 0x84, - 0x93, 0x0c, 0x30, 0x0c, 0xef, 0x20, 0xe0, 0x41, 0xe3, 0x14, 0xb4, 0xe3, 0xa1, 0xbd, 0x0d, 0x47, 0x93, 0x0c, 0x00, - 0x08, 0xe3, 0x98, 0xeb, 0xe4, 0x03, 0x25, 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, - 0x63, 0xe4, 0xa7, 0x04, 0x91, 0x67, 0x26, 0x05, 0x93, 0x87, 0x07, 0x20, 0x3e, 0x95, 0x05, 0xbf, 0x11, 0x47, 0x93, - 0x0c, 0x00, 0x08, 0xe3, 0x94, 0xeb, 0xe2, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0xff, 0x93, 0x68, 0x10, 0xef, 0x10, - 0x80, 0x79, 0xef, 0x30, 0xc0, 0x32, 0xef, 0x20, 0xe0, 0x3a, 0x91, 0x45, 0x13, 0x05, 0x00, 0x06, 0xef, 0x30, 0x00, - 0x47, 0x2a, 0x84, 0xef, 0x20, 0x00, 0x3c, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x0b, 0xf4, 0xde, 0x93, 0x0c, 0xc0, 0x03, - 0xcd, 0xbb, 0x13, 0x07, 0x00, 0x03, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x94, 0xeb, 0xde, 0xc1, 0x45, 0x68, 0x10, 0xef, - 0xe0, 0xff, 0x8f, 0x68, 0x10, 0xef, 0x10, 0x80, 0x75, 0xef, 0x30, 0xc0, 0x2e, 0xef, 0x20, 0xe0, 0x36, 0x93, 0x05, - 0x00, 0x03, 0x13, 0x05, 0x10, 0x06, 0x7d, 0xbf, 0x0d, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x9f, 0xeb, 0xda, 0xef, - 0x30, 0x00, 0x2d, 0xef, 0x20, 0x20, 0x35, 0x8d, 0x45, 0x13, 0x05, 0x20, 0x06, 0xef, 0x30, 0x40, 0x41, 0x2a, 0x84, - 0xef, 0x20, 0x40, 0x36, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x14, 0xf4, 0xfa, 0xef, 0xe0, 0x9f, 0xd8, 0xc9, 0xbb, 0x0d, - 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x97, 0xeb, 0xd8, 0xef, 0x30, 0x00, 0x2a, 0x8d, 0x45, 0x13, 0x05, 0x30, 0x06, - 0xef, 0x30, 0x80, 0x3e, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x11, 0xf5, 0xf8, 0x85, 0xbb, 0x13, 0x07, 0x00, 0x03, 0x93, - 0x0c, 0x00, 0x08, 0xe3, 0x95, 0xeb, 0xd6, 0xef, 0x30, 0xc0, 0x27, 0xef, 0x20, 0xf0, 0x7f, 0xb7, 0x15, 0x20, 0x00, - 0x2a, 0xd6, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, 0xef, 0x30, 0xa0, 0x31, 0x11, - 0x46, 0x6c, 0x10, 0x13, 0x05, 0x00, 0x0c, 0xef, 0x30, 0xe0, 0x30, 0xef, 0x20, 0x80, 0x2d, 0x93, 0x05, 0x40, 0x02, - 0x13, 0x05, 0x00, 0x07, 0xef, 0x30, 0x80, 0x39, 0x2a, 0x84, 0xef, 0x20, 0x80, 0x2e, 0x93, 0x07, 0xa0, 0x0a, 0xe3, - 0x16, 0xf4, 0xf2, 0xef, 0xe0, 0xdf, 0xd0, 0x99, 0xbb, 0x3d, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x79, 0x77, 0xd1, - 0xef, 0x30, 0x40, 0x22, 0xef, 0x20, 0x70, 0x7a, 0xaa, 0x8c, 0x01, 0x45, 0xef, 0x20, 0xf0, 0x53, 0x41, 0x46, 0x93, - 0x05, 0x0a, 0x00, 0x01, 0x45, 0xef, 0x20, 0x90, 0x56, 0xef, 0x20, 0xe0, 0x28, 0xb7, 0x15, 0x20, 0x00, 0x13, 0x06, - 0x00, 0x02, 0x93, 0x85, 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, 0x66, 0xd6, 0xef, 0x30, 0xa0, 0x2a, 0x11, 0x46, 0x6c, - 0x10, 0x13, 0x05, 0x00, 0x0c, 0xef, 0x30, 0xe0, 0x29, 0x85, 0x45, 0x13, 0x05, 0x10, 0x04, 0xef, 0x30, 0xe0, 0x32, - 0x93, 0x07, 0xa0, 0x0a, 0xaa, 0x8c, 0x63, 0x19, 0xf5, 0x00, 0x81, 0x45, 0x13, 0x05, 0x20, 0x04, 0xef, 0x30, 0xa0, - 0x31, 0x63, 0x05, 0x95, 0x01, 0xef, 0x20, 0x80, 0x26, 0x45, 0xbd, 0xef, 0x20, 0x20, 0x26, 0x37, 0x07, 0x20, 0x00, - 0x93, 0x0d, 0x09, 0xfe, 0xee, 0x8c, 0x13, 0x0d, 0x07, 0x01, 0xba, 0x8b, 0x13, 0x07, 0x00, 0x09, 0x63, 0x62, 0x97, - 0x09, 0xea, 0x85, 0x66, 0x86, 0x01, 0x45, 0xef, 0x20, 0x50, 0x4f, 0xe6, 0x85, 0x13, 0x05, 0x40, 0x04, 0xef, 0x30, - 0x00, 0x2e, 0x13, 0x07, 0xa0, 0x0a, 0x2a, 0x8d, 0xe3, 0x1c, 0xe5, 0xe6, 0x81, 0x45, 0x13, 0x05, 0x50, 0x04, 0xef, - 0x30, 0xc0, 0x2c, 0xaa, 0x8c, 0xe3, 0x14, 0xa5, 0xe7, 0x01, 0x45, 0xef, 0x20, 0x50, 0x49, 0x41, 0x46, 0x93, 0x05, - 0x0a, 0x00, 0x01, 0x45, 0xef, 0x20, 0xf0, 0x4b, 0x93, 0x07, 0xf0, 0x03, 0x63, 0xe3, 0xb7, 0x07, 0x93, 0x85, 0x0b, - 0x01, 0x01, 0x45, 0x6e, 0x86, 0xef, 0x20, 0xb0, 0x4a, 0xee, 0x85, 0x13, 0x05, 0x60, 0x04, 0xef, 0x30, 0x60, 0x29, - 0xe3, 0x1a, 0x95, 0xe3, 0x81, 0x45, 0x13, 0x05, 0xa0, 0x04, 0xef, 0x30, 0x80, 0x28, 0x93, 0x07, 0xa0, 0x0a, 0xe3, - 0x11, 0xf5, 0xe2, 0xef, 0x20, 0x10, 0x69, 0x93, 0x07, 0x00, 0x05, 0x7c, 0xd8, 0x19, 0xb1, 0x13, 0x06, 0x00, 0x09, - 0xea, 0x85, 0x01, 0x45, 0xef, 0x20, 0x30, 0x47, 0x93, 0x05, 0x00, 0x09, 0x13, 0x05, 0x30, 0x04, 0xef, 0x30, 0xc0, - 0x25, 0x93, 0x06, 0xa0, 0x0a, 0xe3, 0x1b, 0xd5, 0xde, 0x93, 0x8c, 0x0c, 0xf7, 0x13, 0x0d, 0x0d, 0x09, 0x81, 0xbf, - 0x93, 0x85, 0x0b, 0x01, 0x01, 0x45, 0x13, 0x06, 0x00, 0x04, 0xef, 0x20, 0x70, 0x44, 0x93, 0x05, 0x00, 0x04, 0x13, - 0x05, 0x70, 0x04, 0xef, 0x30, 0x00, 0x23, 0xe3, 0x17, 0x95, 0xdd, 0xb7, 0x0c, 0x20, 0x00, 0x13, 0x09, 0x09, 0xfa, - 0x93, 0x8c, 0x0c, 0x05, 0x93, 0x0d, 0x00, 0x08, 0x93, 0x0b, 0xa0, 0x0a, 0x63, 0xe1, 0x2d, 0x03, 0x4a, 0x86, 0xe6, - 0x85, 0x01, 0x45, 0xef, 0x20, 0x50, 0x41, 0xca, 0x85, 0x13, 0x05, 0x90, 0x04, 0xef, 0x30, 0x00, 0x20, 0x93, 0x07, - 0xa0, 0x0a, 0xe3, 0x1d, 0xf5, 0xd8, 0x9d, 0xb7, 0xe6, 0x85, 0x01, 0x45, 0x13, 0x06, 0x00, 0x08, 0xef, 0x20, 0x50, - 0x3f, 0x93, 0x05, 0x00, 0x08, 0x13, 0x05, 0x80, 0x04, 0xef, 0x30, 0xe0, 0x1d, 0xe3, 0x1e, 0x75, 0xd7, 0x13, 0x09, - 0x09, 0xf8, 0x93, 0x8c, 0x0c, 0x08, 0x6d, 0xbf, 0x21, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x9f, 0xeb, 0xb4, 0x03, - 0x44, 0x1d, 0x00, 0xbd, 0x47, 0xe3, 0xef, 0x87, 0xd4, 0x83, 0x2c, 0x4d, 0x00, 0xfd, 0x57, 0xe3, 0x8a, 0xfc, 0xd4, - 0x13, 0x19, 0xa4, 0x00, 0x13, 0x05, 0x09, 0x40, 0xef, 0xe0, 0x4f, 0xe1, 0x13, 0x07, 0xa0, 0x0a, 0xaa, 0x8b, 0xe3, - 0x1f, 0xe5, 0xd2, 0x13, 0x09, 0x09, 0x20, 0x4a, 0x85, 0xef, 0xe0, 0x0f, 0xe0, 0xaa, 0x8d, 0xe3, 0x17, 0x75, 0xd3, - 0xe6, 0x85, 0x4a, 0x85, 0xef, 0x10, 0x20, 0x17, 0xe3, 0x11, 0xb5, 0xd3, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x07, - 0xf6, 0x85, 0x47, 0x33, 0x94, 0x87, 0x00, 0x1c, 0x43, 0x5d, 0x8c, 0x00, 0xc3, 0xf5, 0xbc, 0x0d, 0x47, 0x93, 0x0c, - 0x00, 0x08, 0xe3, 0x9c, 0xeb, 0xae, 0x83, 0x45, 0x1d, 0x00, 0xbd, 0x47, 0xe3, 0xec, 0xb7, 0xce, 0xb7, 0x37, 0x20, - 0x00, 0x83, 0xa7, 0x07, 0xf6, 0xd1, 0x4c, 0xb3, 0xd7, 0xb7, 0x00, 0x85, 0x8b, 0xe3, 0x8d, 0x07, 0xac, 0x37, 0x15, - 0x20, 0x00, 0x13, 0x05, 0x05, 0x08, 0xef, 0xe0, 0x2f, 0xe6, 0x85, 0x47, 0xe3, 0x0c, 0xf5, 0xba, 0x89, 0x47, 0xe3, - 0x01, 0xf5, 0xac, 0xe1, 0xb1, 0x93, 0x0c, 0x00, 0x08, 0x65, 0xbc, 0xef, 0x10, 0x70, 0x46, 0xef, 0xe0, 0xef, 0xd2, - 0x6f, 0xf0, 0x8f, 0xef, 0xef, 0x00, 0xc0, 0x6f, 0x6f, 0xf0, 0x8f, 0xef, 0xef, 0x00, 0x30, 0x4b, 0x93, 0x0b, 0x09, - 0xff, 0xaa, 0x86, 0x63, 0x0f, 0x05, 0xf2, 0x8d, 0x45, 0x13, 0x85, 0x8d, 0x53, 0x36, 0xce, 0x69, 0x24, 0xf2, 0x46, - 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0x86, 0x5c, 0x93, 0x85, 0x8d, 0x53, 0x13, 0x85, 0x89, 0x77, 0x01, 0x24, 0xf2, - 0x46, 0x09, 0x46, 0x05, 0x47, 0x63, 0x83, 0xc6, 0x00, 0x09, 0x47, 0x83, 0x46, 0x84, 0x07, 0x37, 0x56, 0x10, 0x00, - 0xb7, 0x55, 0x10, 0x00, 0xa3, 0x0c, 0xe4, 0x06, 0x13, 0x06, 0x86, 0x5e, 0x5e, 0x87, 0x93, 0x85, 0xc5, 0x56, 0x13, - 0x85, 0x89, 0x77, 0xd1, 0x2a, 0xef, 0xe0, 0xcf, 0xc8, 0xef, 0xe0, 0xcf, 0xf9, 0x62, 0x47, 0x85, 0x47, 0x23, 0x00, - 0xf7, 0x00, 0xef, 0x00, 0xc0, 0x5a, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0x63, 0x1f, 0xf5, 0xdc, 0x1d, 0x29, 0x2a, - 0x84, 0x63, 0x1b, 0x25, 0xdd, 0xef, 0x30, 0xc0, 0x1a, 0x63, 0x17, 0x85, 0xdc, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, - 0x87, 0xf5, 0xb1, 0xeb, 0x83, 0x27, 0x4b, 0x07, 0x13, 0x07, 0xfc, 0x00, 0xfd, 0x17, 0x63, 0x64, 0xf7, 0x04, 0x05, - 0x45, 0xef, 0x20, 0xf0, 0x23, 0x03, 0x26, 0x4b, 0x07, 0x37, 0x09, 0x20, 0x00, 0x93, 0x05, 0x09, 0x00, 0x13, 0x05, - 0x09, 0x00, 0xef, 0x20, 0x10, 0x34, 0x37, 0x14, 0x20, 0x00, 0x13, 0x05, 0x04, 0x02, 0xef, 0x20, 0xd0, 0x42, 0x03, - 0x25, 0x4b, 0x07, 0x93, 0x07, 0x09, 0x00, 0x41, 0x46, 0x3e, 0x95, 0x93, 0x05, 0x04, 0x02, 0xef, 0x30, 0x40, 0x6e, - 0x83, 0x27, 0x4b, 0x07, 0xc1, 0x07, 0x23, 0x2a, 0xfb, 0x06, 0xef, 0x00, 0x70, 0x1e, 0x13, 0x04, 0xa0, 0x0a, 0x63, - 0x03, 0x85, 0xd6, 0xef, 0xe0, 0x5f, 0xa2, 0x63, 0x1f, 0x85, 0xd4, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, - 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x60, 0x93, 0x85, 0xc5, 0x56, 0x13, 0x05, 0x45, 0x57, 0x31, 0x2a, 0xef, - 0xe0, 0xaf, 0xb0, 0xef, 0x20, 0x50, 0x41, 0xef, 0x00, 0xd0, 0x36, 0xef, 0x00, 0xd0, 0x2d, 0xef, 0xe0, 0x4f, 0xf3, - 0x6f, 0xf0, 0xcf, 0xd2, 0x2a, 0x87, 0x81, 0x47, 0x01, 0x45, 0x63, 0x93, 0xc7, 0x00, 0x82, 0x80, 0xb3, 0x06, 0xf7, - 0x00, 0x33, 0x88, 0xf5, 0x00, 0x83, 0xc6, 0x06, 0x00, 0x03, 0x48, 0x08, 0x00, 0x85, 0x07, 0xb3, 0xc6, 0x06, 0x01, - 0x55, 0x8d, 0x13, 0x75, 0xf5, 0x0f, 0xf9, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x37, 0x37, 0x20, 0x00, 0x03, 0xa8, 0x87, - 0xf6, 0x83, 0x27, 0x47, 0xf6, 0xaa, 0x86, 0x13, 0x07, 0x47, 0xf6, 0x01, 0x45, 0x63, 0x13, 0xf8, 0x00, 0x82, 0x80, - 0x37, 0x26, 0x20, 0x00, 0x13, 0x06, 0xc6, 0x08, 0x93, 0x08, 0xf0, 0x7f, 0x63, 0x01, 0xb5, 0x02, 0x33, 0x0e, 0xf6, - 0x00, 0x03, 0x4e, 0x0e, 0x00, 0x05, 0x05, 0x33, 0x83, 0xa6, 0x00, 0xa3, 0x0f, 0xc3, 0xff, 0x85, 0x07, 0x63, 0xf3, - 0xf8, 0x00, 0x81, 0x47, 0xe3, 0x11, 0xf8, 0xfe, 0x1c, 0xc3, 0x82, 0x80, 0x93, 0x07, 0xf0, 0x7f, 0x63, 0xe5, 0xa7, - 0x02, 0xb7, 0x36, 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x86, 0x46, 0xf6, 0x83, 0xa7, 0x87, 0xf6, 0x98, 0x42, - 0x33, 0x87, 0xe7, 0x40, 0x13, 0x77, 0xf7, 0x7f, 0x63, 0x76, 0xe5, 0x00, 0x89, 0x8f, 0x93, 0xf7, 0xf7, 0x7f, 0x9c, - 0xc2, 0x82, 0x80, 0xb7, 0x36, 0x20, 0x00, 0x03, 0xa8, 0x86, 0xf6, 0x13, 0x07, 0xf0, 0x7f, 0x13, 0x86, 0x86, 0xf6, - 0x93, 0x07, 0x18, 0x00, 0x63, 0x73, 0xf7, 0x00, 0x81, 0x47, 0xb7, 0x36, 0x20, 0x00, 0x83, 0xa8, 0x46, 0xf6, 0x37, - 0x27, 0x20, 0x00, 0x93, 0x85, 0x46, 0xf6, 0x13, 0x07, 0xc7, 0x08, 0x63, 0x9f, 0xf8, 0x00, 0x93, 0x88, 0x17, 0x80, - 0x93, 0x86, 0x17, 0x00, 0x63, 0x93, 0x08, 0x00, 0x81, 0x46, 0x94, 0xc1, 0xba, 0x96, 0x93, 0x05, 0xa0, 0x02, 0x23, - 0x80, 0xb6, 0x00, 0x42, 0x97, 0x23, 0x00, 0xa7, 0x00, 0x1c, 0xc2, 0x82, 0x80, 0x82, 0x80, 0x39, 0x71, 0x22, 0xcc, - 0x26, 0xca, 0x4a, 0xc8, 0x06, 0xce, 0x36, 0xd6, 0x3a, 0xd8, 0x3e, 0xda, 0x42, 0xdc, 0x46, 0xde, 0xaa, 0x84, 0x2e, - 0x89, 0x32, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x6f, 0xfd, 0x63, 0x14, 0x09, 0x00, 0xef, 0xe0, 0xef, 0xfc, 0x19, 0xe0, - 0xef, 0xe0, 0x8f, 0xfc, 0x7c, 0x10, 0x3e, 0xc6, 0xef, 0x30, 0x40, 0x21, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x13, - 0x05, 0xc5, 0x73, 0xef, 0x30, 0x40, 0x46, 0x37, 0x55, 0x10, 0x00, 0x4a, 0x86, 0xa6, 0x85, 0x13, 0x05, 0x45, 0x74, - 0xef, 0x30, 0x40, 0x45, 0xb2, 0x45, 0x22, 0x85, 0xef, 0x30, 0xa0, 0x41, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x05, - 0x75, 0xef, 0x30, 0x00, 0x44, 0xb9, 0x29, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0x21, 0x61, 0x82, 0x80, - 0xae, 0x86, 0x37, 0x56, 0x10, 0x00, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x46, 0x5e, 0x13, 0x05, 0x45, - 0x75, 0x9d, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, 0x83, 0xa6, 0x47, 0x10, - 0x63, 0x7e, 0xd7, 0x00, 0x0a, 0x07, 0x3e, 0x97, 0x18, 0x43, 0x18, 0xc1, 0x03, 0xa7, 0x07, 0x10, 0x13, 0x05, 0xa0, - 0x0a, 0x05, 0x07, 0x23, 0xa0, 0xe7, 0x10, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, 0x26, 0xca, - 0xb7, 0x34, 0x20, 0x00, 0x83, 0xa7, 0xc4, 0xf6, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x11, - 0x47, 0x63, 0x6f, 0xf7, 0x0c, 0x37, 0x57, 0x10, 0x00, 0x8a, 0x07, 0x13, 0x07, 0xc7, 0x77, 0xba, 0x97, 0x9c, 0x43, - 0x2a, 0x84, 0x93, 0x84, 0xc4, 0xf6, 0x82, 0x87, 0x81, 0x45, 0xef, 0x30, 0x40, 0x3f, 0xb7, 0x37, 0x20, 0x00, 0x23, - 0x98, 0xa7, 0xf6, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x86, 0x87, 0x88, 0xef, 0x20, 0x50, 0x73, 0x9c, 0x40, 0x85, 0x07, - 0x81, 0xa8, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0x07, 0xf6, 0x93, 0x07, 0xc0, 0x0f, 0x63, 0xf1, 0xa7, 0x02, 0x62, - 0x44, 0x9d, 0x47, 0xf2, 0x40, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x9c, 0xc0, 0xd2, 0x44, 0x37, 0x55, 0x10, 0x00, - 0x85, 0x45, 0x13, 0x05, 0x85, 0x75, 0x05, 0x61, 0x2d, 0xbf, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x09, 0xf7, 0x83, - 0x55, 0x09, 0x00, 0xef, 0x30, 0xc0, 0x39, 0xb7, 0x37, 0x20, 0x00, 0xa3, 0x86, 0x87, 0x88, 0x23, 0x10, 0xa9, 0x00, - 0x8d, 0x47, 0x5d, 0xf4, 0x9c, 0xc0, 0x91, 0xa8, 0x37, 0x39, 0x20, 0x00, 0x03, 0x27, 0x49, 0xf7, 0x93, 0x07, 0xb0, - 0x0f, 0x13, 0x09, 0x49, 0xf7, 0x63, 0xf4, 0xe7, 0x00, 0xef, 0xe0, 0xcf, 0xe7, 0x83, 0x27, 0x09, 0x00, 0x37, 0x3a, - 0x20, 0x00, 0x13, 0x0a, 0x0a, 0xf7, 0xb7, 0x39, 0x20, 0x00, 0x93, 0x89, 0xc9, 0x88, 0x83, 0x55, 0x0a, 0x00, 0xce, - 0x97, 0x23, 0x81, 0x87, 0x00, 0x22, 0x85, 0xef, 0x30, 0xc0, 0x34, 0x83, 0x27, 0x09, 0x00, 0x03, 0xc7, 0x19, 0x00, - 0x23, 0x10, 0xaa, 0x00, 0x85, 0x07, 0x23, 0x20, 0xf9, 0x00, 0xe3, 0xfd, 0xe7, 0xf4, 0xf2, 0x40, 0x62, 0x44, 0xd2, - 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x99, 0xa7, 0xf6, - 0x3d, 0xbf, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x29, 0xf7, 0x13, 0x14, 0x85, 0x00, 0xb7, 0x39, 0x20, 0x00, 0x03, - 0x55, 0x09, 0x00, 0x93, 0x89, 0x09, 0xf7, 0x83, 0xd7, 0x09, 0x00, 0x49, 0x8c, 0x23, 0x10, 0x89, 0x00, 0xe3, 0x8d, - 0x87, 0xf0, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0x84, 0x75, 0x99, 0x47, 0x89, 0x45, 0x9c, 0xc0, 0x95, 0x3d, 0x93, - 0x05, 0x84, 0x75, 0x62, 0x44, 0x03, 0xd7, 0x09, 0x00, 0x83, 0x56, 0x09, 0x00, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, - 0xb2, 0x49, 0x22, 0x4a, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x75, 0x13, 0x05, 0x85, - 0x77, 0x05, 0x61, 0x6f, 0xf0, 0x3f, 0xdd, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0xb7, 0x25, 0x10, 0x00, - 0x37, 0x25, 0x10, 0x00, 0x23, 0xa0, 0x07, 0x10, 0x23, 0xa2, 0x07, 0x10, 0x93, 0x85, 0xc5, 0xfd, 0xb7, 0x37, 0x20, - 0x00, 0x13, 0x05, 0xe5, 0x00, 0x23, 0xa6, 0x07, 0xf6, 0x6f, 0x20, 0x70, 0x55, 0x11, 0xed, 0x01, 0x11, 0x06, 0xce, - 0x2a, 0xc6, 0xef, 0xe0, 0xcf, 0xd8, 0x32, 0x45, 0xf2, 0x40, 0x13, 0x06, 0xe0, 0x0f, 0x81, 0x45, 0x05, 0x61, 0x6f, - 0x30, 0x40, 0x35, 0x13, 0x06, 0xe0, 0x0f, 0x81, 0x45, 0xdd, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xf6, - 0x13, 0x05, 0xa0, 0x0a, 0x99, 0xc3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, - 0x00, 0x13, 0x04, 0xc4, 0xf6, 0x1c, 0x40, 0x06, 0xc6, 0x15, 0x47, 0x63, 0x98, 0xe7, 0x00, 0x13, 0x05, 0xa0, 0x0a, - 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x81, 0xe7, 0x13, 0x05, 0x50, 0x05, 0xcd, 0xbf, 0xef, 0x20, 0x10, - 0x54, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x19, 0xf5, 0xfe, 0x01, 0x00, 0x18, 0x40, 0x91, 0x47, 0xe3, 0xcd, 0xe7, 0xfc, - 0x99, 0x47, 0x1c, 0xc0, 0xd9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x20, 0x90, 0x53, 0x93, 0x07, 0xa0, 0x0a, 0x63, - 0x04, 0xf5, 0x00, 0xef, 0x20, 0xf0, 0x54, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0xc7, 0xf6, 0x95, 0x47, 0x13, 0x05, - 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, - 0x00, 0x03, 0xa7, 0xc7, 0xf6, 0x99, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, - 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0xc7, 0xf6, 0x9d, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, - 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x37, 0x35, 0x20, 0x00, 0x13, 0x05, 0xc5, 0x88, 0x82, 0x80, 0x01, 0x11, - 0x26, 0xca, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0xaa, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0xcf, 0xc9, 0x83, - 0xc7, 0x14, 0x00, 0x13, 0x07, 0xc0, 0x0f, 0x13, 0x05, 0x50, 0x05, 0x63, 0x65, 0xf7, 0x06, 0x37, 0x39, 0x20, 0x00, - 0x13, 0x04, 0xc9, 0x98, 0x23, 0x20, 0x04, 0x10, 0x03, 0xc7, 0x04, 0x00, 0xa3, 0x00, 0xf4, 0x00, 0x03, 0xc6, 0x14, - 0x00, 0x23, 0x00, 0xe4, 0x00, 0x93, 0x85, 0x24, 0x00, 0x13, 0x05, 0x24, 0x00, 0xef, 0x30, 0x00, 0x20, 0x83, 0xc9, - 0x14, 0x00, 0x13, 0x05, 0xc9, 0x98, 0x13, 0x09, 0xc9, 0x98, 0x93, 0x84, 0x29, 0x00, 0xa6, 0x85, 0xef, 0x30, 0x80, - 0x16, 0xa2, 0x94, 0x23, 0x80, 0xa4, 0x00, 0x4e, 0x94, 0x21, 0x81, 0x93, 0x87, 0x49, 0x00, 0xa3, 0x01, 0xa4, 0x00, - 0xfd, 0x56, 0x13, 0xf7, 0x37, 0x00, 0x19, 0xef, 0x89, 0x83, 0x23, 0x22, 0xf9, 0x10, 0xef, 0x20, 0x30, 0x49, 0x13, - 0x05, 0xa0, 0x0a, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, 0x33, 0x07, - 0xf9, 0x00, 0x23, 0x00, 0xd7, 0x00, 0x85, 0x07, 0xd1, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0x03, - 0xa7, 0x07, 0x10, 0x83, 0xa7, 0x47, 0x10, 0x63, 0x14, 0xf7, 0x00, 0x6f, 0x20, 0xb0, 0x41, 0x13, 0x05, 0x50, 0x05, - 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa6, 0x07, 0xf6, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x93, 0x07, 0x00, - 0x08, 0x73, 0xa0, 0x47, 0x30, 0x93, 0x06, 0x70, 0x3e, 0x09, 0x46, 0x93, 0x05, 0x60, 0x04, 0x37, 0x05, 0x10, 0x01, - 0xef, 0x20, 0xf0, 0x59, 0x8d, 0x45, 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, 0xf0, 0x5d, 0x37, 0x05, 0x10, 0x01, 0xef, - 0x20, 0x70, 0x53, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0xb0, 0x55, 0xfd, 0x56, 0x01, 0x46, 0x93, 0x05, 0x60, 0x04, - 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x50, 0x57, 0xb2, 0x40, 0xb7, 0x07, 0x20, 0x01, 0x23, 0xac, 0x07, 0x00, 0x41, - 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x89, 0x2c, 0xb2, 0x40, 0x41, 0x01, 0x45, 0xb7, 0x41, 0x11, 0x22, 0xc4, - 0xb7, 0x07, 0x20, 0x01, 0x06, 0xc6, 0x23, 0xac, 0x07, 0x00, 0x2a, 0x84, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0xd0, - 0x4e, 0x93, 0x07, 0x80, 0x3e, 0x13, 0x05, 0x80, 0x3e, 0x63, 0xe3, 0x87, 0x00, 0x22, 0x85, 0xb7, 0x07, 0x20, 0x01, - 0x98, 0x4f, 0x13, 0x84, 0x87, 0x01, 0xe3, 0x6d, 0xa7, 0xfe, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x50, 0x4f, 0xb2, - 0x40, 0x23, 0x20, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x11, 0xe1, 0x82, 0x80, 0x01, 0x00, 0x7d, 0x15, - 0xe5, 0xbf, 0x6f, 0xf0, 0x9f, 0xb3, 0x29, 0xa4, 0x01, 0x11, 0x26, 0xca, 0xaa, 0x84, 0x37, 0x05, 0x20, 0x01, 0x4a, - 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x56, 0xc2, 0x06, 0xce, 0x22, 0xcc, 0x2e, 0x89, 0x93, 0x09, 0xa0, 0x0a, 0xef, 0x20, - 0xd0, 0x48, 0x37, 0x0a, 0x20, 0x01, 0x93, 0x0a, 0x80, 0x3e, 0x82, 0x94, 0x2a, 0x84, 0x63, 0x0c, 0x35, 0x03, 0x83, - 0x27, 0x8a, 0x01, 0x63, 0x7a, 0xf9, 0x04, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0x04, 0x79, 0x85, 0x45, 0xef, 0xf0, - 0x9f, 0xb6, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0x05, 0x04, 0x79, 0xa6, 0x86, 0x13, 0x06, 0x46, - 0x79, 0x13, 0x05, 0x85, 0x77, 0xef, 0xf0, 0x9f, 0xad, 0x13, 0x04, 0x50, 0x05, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, - 0xd0, 0x46, 0xf2, 0x40, 0x22, 0x85, 0x62, 0x44, 0xb7, 0x07, 0x20, 0x01, 0x23, 0xac, 0x07, 0x00, 0xd2, 0x44, 0x42, - 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xe3, 0xf0, 0x2a, 0xfb, 0xb5, 0x2a, 0x69, 0xbf, - 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x87, 0x00, 0x1c, 0xc7, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, - 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0xcf, 0xa7, 0xa9, 0x44, 0x03, 0x45, 0x04, 0x00, 0x11, 0xe5, - 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xef, 0xf0, 0xdf, 0xa1, 0x83, 0x47, 0x04, 0x00, 0x63, - 0x94, 0x97, 0x00, 0xef, 0xf0, 0x7f, 0xa6, 0x05, 0x04, 0xf9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0x25, 0x37, 0x93, 0x07, - 0xa0, 0x0a, 0x63, 0x05, 0xf5, 0x00, 0xef, 0xe0, 0x4f, 0xa4, 0x01, 0xa0, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x41, - 0x11, 0x22, 0xc4, 0x37, 0x44, 0x20, 0x00, 0x13, 0x06, 0xc0, 0x1f, 0x81, 0x45, 0x13, 0x05, 0x04, 0xe0, 0x06, 0xc6, - 0x26, 0xc2, 0xef, 0x20, 0xb0, 0x7f, 0x13, 0x05, 0x04, 0xe0, 0x93, 0x05, 0xc0, 0x1f, 0xef, 0x20, 0x30, 0x76, 0x93, - 0x04, 0x04, 0xe0, 0xb2, 0x40, 0x22, 0x44, 0x23, 0xae, 0xa4, 0x1e, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, - 0x37, 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, 0xc0, 0x1f, 0x13, 0x04, 0x05, 0xe0, 0x13, 0x05, 0x05, 0xe0, 0x06, - 0xc6, 0xef, 0x20, 0x70, 0x73, 0x03, 0x27, 0xc4, 0x1f, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xa7, 0x00, 0x93, 0x07, - 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x3e, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, 0xaa, 0x87, 0x63, - 0x6e, 0xa7, 0x00, 0x13, 0x77, 0x35, 0x00, 0x01, 0x45, 0x11, 0xeb, 0x37, 0x45, 0x20, 0x00, 0x13, 0x05, 0x05, 0xe0, - 0xf1, 0x9b, 0xaa, 0x97, 0x88, 0x43, 0x82, 0x80, 0x01, 0x45, 0x82, 0x80, 0x93, 0x07, 0xb0, 0x1f, 0x63, 0xec, 0xa7, - 0x00, 0x93, 0x77, 0x35, 0x00, 0x81, 0xeb, 0xb7, 0x47, 0x20, 0x00, 0x71, 0x99, 0x93, 0x87, 0x07, 0xe0, 0x3e, 0x95, - 0x0c, 0xc1, 0x82, 0x80, 0x41, 0x11, 0x37, 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, 0xc0, 0x1f, 0x13, 0x04, 0x05, - 0xe0, 0x13, 0x05, 0x05, 0xe0, 0x06, 0xc6, 0xef, 0x20, 0xf0, 0x6b, 0xb2, 0x40, 0x23, 0x2e, 0xa4, 0x1e, 0x22, 0x44, - 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, 0x63, 0x61, 0xa7, 0x02, 0x93, 0x77, 0x35, 0x00, 0x13, 0x07, 0x50, - 0x05, 0x89, 0xef, 0x41, 0x11, 0x06, 0xc6, 0x5d, 0x37, 0xc9, 0x37, 0xb2, 0x40, 0x13, 0x07, 0xa0, 0x0a, 0x3a, 0x85, - 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0x50, 0x05, 0x3a, 0x85, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x00, 0x90, - 0x6c, 0xef, 0x20, 0xe0, 0x5f, 0xb2, 0x40, 0x13, 0x05, 0xa0, 0x0a, 0x41, 0x01, 0x82, 0x80, 0x73, 0x00, 0x50, 0x10, - 0x82, 0x80, 0x3d, 0xce, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x06, 0xd6, 0x4e, 0xce, 0x52, 0xcc, 0x2a, - 0x84, 0x2e, 0x89, 0xb2, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x0f, 0x90, 0x93, 0x77, 0x39, 0x00, 0x99, 0xc3, 0xef, 0xe0, - 0x6f, 0x8f, 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x87, 0x34, 0x41, 0x33, 0x05, 0x34, 0x01, 0x63, 0x6c, 0xfa, 0x02, 0x13, - 0xd6, 0x24, 0x00, 0xf1, 0x57, 0x33, 0x06, 0xf6, 0x02, 0x93, 0xf5, 0xc4, 0xff, 0x33, 0x05, 0xb4, 0x00, 0x2e, 0x99, - 0x26, 0x96, 0x19, 0xc6, 0x83, 0x27, 0x09, 0x00, 0x6c, 0x00, 0x3e, 0xc6, 0xef, 0x20, 0xf0, 0x65, 0xb2, 0x50, 0x22, - 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0xb3, 0x07, 0x39, 0x01, 0x9c, 0x43, - 0x11, 0x46, 0x6c, 0x00, 0x3e, 0xc6, 0x91, 0x09, 0xef, 0x20, 0xd0, 0x63, 0x7d, 0xb7, 0x82, 0x80, 0x3d, 0xce, 0x79, - 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x06, 0xd6, 0x4e, 0xce, 0x52, 0xcc, 0x2a, 0x84, 0x2e, 0x89, 0xb2, 0x84, - 0x99, 0xe1, 0xef, 0xe0, 0x0f, 0x88, 0x93, 0x77, 0x34, 0x00, 0x99, 0xc3, 0xef, 0xe0, 0x6f, 0x87, 0x81, 0x49, 0x0d, - 0x4a, 0xb3, 0x87, 0x34, 0x41, 0xb3, 0x05, 0x39, 0x01, 0x63, 0x6c, 0xfa, 0x02, 0x13, 0xd6, 0x24, 0x00, 0xf1, 0x57, - 0x33, 0x06, 0xf6, 0x02, 0x93, 0xf5, 0xc4, 0xff, 0x2e, 0x94, 0xca, 0x95, 0x26, 0x96, 0x01, 0xca, 0x1c, 0x40, 0x68, - 0x00, 0x3e, 0xc6, 0xef, 0x20, 0x30, 0x5e, 0xb2, 0x47, 0x1c, 0xc0, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, - 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0x11, 0x46, 0x68, 0x00, 0xef, 0x20, 0x70, 0x5c, 0x32, 0x47, 0xb3, - 0x07, 0x34, 0x01, 0x91, 0x09, 0x98, 0xc3, 0x7d, 0xb7, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, - 0x19, 0xe1, 0xef, 0xe0, 0xef, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf6, 0xb7, - 0x37, 0x20, 0x00, 0x23, 0xa0, 0x87, 0xf8, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x8a, 0x07, 0xa8, 0xef, 0xf0, 0x9f, 0xb3, - 0xb7, 0x37, 0x20, 0x00, 0x23, 0xae, 0xa7, 0xf6, 0x19, 0xe1, 0xef, 0xd0, 0x1f, 0xfe, 0x22, 0x44, 0xb2, 0x40, 0x41, - 0x01, 0x6f, 0xf0, 0x7f, 0xa1, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xd0, 0x9f, 0xfc, - 0x37, 0x35, 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0xa2, 0x85, 0x13, 0x06, 0xe0, 0x0f, 0x13, 0x05, 0x45, 0xa9, 0x23, - 0x8a, 0x07, 0xb8, 0xef, 0x20, 0xb0, 0x54, 0x22, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x7f, 0xaf, - 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xd0, 0x3f, 0xf9, 0xb7, 0x34, 0x20, - 0x00, 0x83, 0xc7, 0x44, 0xb9, 0x99, 0xcb, 0x37, 0x35, 0x20, 0x00, 0x13, 0x06, 0xe0, 0x0f, 0x93, 0x85, 0x44, 0xb9, - 0x13, 0x05, 0x45, 0xa9, 0xef, 0x20, 0x10, 0x51, 0xa2, 0x85, 0x13, 0x85, 0x44, 0xb9, 0x13, 0x06, 0xe0, 0x0f, 0xef, - 0x20, 0x30, 0x50, 0x22, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x92, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0xdf, 0xaa, 0xb7, 0x37, - 0x20, 0x00, 0x03, 0xa5, 0x87, 0xf7, 0x82, 0x80, 0x37, 0x35, 0x20, 0x00, 0x83, 0x47, 0x45, 0xa9, 0x85, 0xc3, 0xb7, - 0x37, 0x20, 0x00, 0x83, 0xc7, 0x47, 0xb9, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xac, - 0xe7, 0xf6, 0x13, 0x05, 0x45, 0xa9, 0x6f, 0xf0, 0xbf, 0xa7, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x06, - 0xc6, 0xef, 0xf0, 0x9f, 0x9a, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xf5, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, - 0x41, 0x01, 0x82, 0x80, 0x6d, 0x71, 0x23, 0x26, 0x11, 0x10, 0x23, 0x24, 0x81, 0x10, 0x23, 0x22, 0x91, 0x10, 0xef, - 0xf0, 0x9f, 0x99, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x02, 0x2a, 0x84, 0xef, 0xf0, 0x1f, 0x9d, 0x63, 0x12, - 0x85, 0x06, 0xb7, 0x37, 0x20, 0x00, 0x37, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xf8, 0x03, 0x25, 0xc7, 0xf7, 0x82, - 0x97, 0xef, 0xf0, 0x3f, 0xae, 0xef, 0xf0, 0x1f, 0xac, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x18, 0xf5, 0x02, - 0xef, 0xf0, 0xbf, 0x94, 0x63, 0x14, 0x85, 0x02, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x84, 0xf7, 0x04, 0x40, 0xb7, - 0x35, 0x20, 0x00, 0x63, 0x9c, 0xa4, 0x04, 0x13, 0x85, 0x45, 0xb9, 0xef, 0xf0, 0x1f, 0x9f, 0x63, 0x15, 0x95, 0x00, - 0x93, 0x07, 0x50, 0x05, 0x1c, 0xc0, 0x83, 0x20, 0xc1, 0x10, 0x03, 0x24, 0x81, 0x10, 0x83, 0x24, 0x41, 0x10, 0x51, - 0x61, 0x82, 0x80, 0xef, 0xf0, 0x9f, 0x99, 0x81, 0x44, 0x63, 0x14, 0x85, 0x00, 0x93, 0x04, 0xc0, 0x07, 0xef, 0xf0, - 0x3f, 0x9a, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0xc1, 0xdc, 0x0a, 0x85, 0x23, 0x00, 0x91, 0x00, 0xa3, - 0x00, 0x01, 0x00, 0xef, 0xf0, 0x7f, 0xe8, 0x61, 0xb7, 0x93, 0x04, 0xc0, 0x07, 0xf5, 0xb7, 0x83, 0xc7, 0x45, 0xb9, - 0xcd, 0xdf, 0x03, 0x24, 0x81, 0x10, 0x83, 0x20, 0xc1, 0x10, 0x83, 0x24, 0x41, 0x10, 0x37, 0x35, 0x20, 0x00, 0x13, - 0x06, 0xe0, 0x0f, 0x93, 0x85, 0x45, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0x51, 0x61, 0x6f, 0x20, 0x50, 0x3c, 0xb7, 0x07, - 0x01, 0x04, 0x23, 0xa2, 0x07, 0x00, 0x21, 0x65, 0x6f, 0x20, 0x80, 0x30, 0x41, 0x11, 0x21, 0x65, 0x06, 0xc6, 0xef, - 0x20, 0x20, 0x2f, 0xb2, 0x40, 0xb7, 0x07, 0x01, 0x04, 0x05, 0x47, 0xd8, 0xc3, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, - 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x07, 0x70, 0x02, 0x2a, 0x84, 0xae, 0x84, 0x63, 0xf4, 0xa7, 0x00, 0xef, - 0xd0, 0xbf, 0xde, 0x37, 0x05, 0x01, 0x04, 0x0a, 0x04, 0x13, 0x05, 0x05, 0x10, 0x2a, 0x94, 0x04, 0xc0, 0xb2, 0x40, - 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x13, 0x87, 0x07, 0x10, 0x93, 0x87, 0x07, - 0x1a, 0x23, 0x20, 0x07, 0x00, 0x11, 0x07, 0xe3, 0x1d, 0xf7, 0xfe, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0xc8, 0xcb, - 0x82, 0x80, 0x42, 0x05, 0xb7, 0x07, 0x01, 0x04, 0xc8, 0xcb, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x88, 0x4b, 0x13, - 0x75, 0xf5, 0x0f, 0x82, 0x80, 0x89, 0x67, 0x37, 0x07, 0x01, 0x04, 0x8d, 0x07, 0x1c, 0xc7, 0x23, 0x2a, 0x07, 0x00, - 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0x2a, 0x84, 0xad, 0x37, 0xb7, 0x07, 0x01, 0x04, 0x80, 0xcf, 0xc5, - 0x37, 0x65, 0x37, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xf4, 0xb7, 0x06, 0x01, 0x04, 0x9c, 0x46, - 0x05, 0x45, 0x13, 0xf7, 0x17, 0x00, 0x1d, 0xc7, 0x13, 0xf7, 0x07, 0x40, 0x0d, 0x45, 0x1d, 0xe3, 0x98, 0x4a, 0x13, - 0x77, 0xf7, 0x0f, 0x19, 0xcf, 0x13, 0xf7, 0x27, 0x20, 0x09, 0x45, 0x19, 0xeb, 0x13, 0xd7, 0xb7, 0x00, 0x05, 0x8b, - 0x11, 0x45, 0x11, 0xe7, 0x13, 0xd5, 0x87, 0x00, 0x13, 0x45, 0x15, 0x00, 0x05, 0x89, 0x82, 0x80, 0xb7, 0x07, 0x01, - 0x04, 0x88, 0xcf, 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, 0x06, 0xce, 0x33, 0x07, 0xb6, 0x00, 0x93, 0x07, 0x00, 0x09, - 0x2e, 0x84, 0x63, 0xf8, 0xe7, 0x00, 0x32, 0xc6, 0x2a, 0xc4, 0xef, 0xd0, 0xff, 0xd0, 0x32, 0x46, 0x22, 0x45, 0xb7, - 0x15, 0x01, 0x04, 0xa2, 0x95, 0xef, 0xf0, 0x9f, 0xbe, 0xf2, 0x40, 0x62, 0x44, 0x13, 0x05, 0xa0, 0x0a, 0x05, 0x61, - 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, 0x26, 0xca, 0x06, 0xce, 0x33, 0x07, 0xb6, 0x00, 0x93, 0x07, 0x00, 0x08, 0xaa, - 0x84, 0x2e, 0x84, 0x63, 0xf6, 0xe7, 0x00, 0x32, 0xc6, 0xef, 0xd0, 0x7f, 0xcd, 0x32, 0x46, 0x37, 0x25, 0x01, 0x04, - 0x13, 0x05, 0x05, 0x80, 0x22, 0x95, 0x62, 0x44, 0xf2, 0x40, 0xa6, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x6f, 0xf0, 0x5f, - 0xc2, 0x39, 0x71, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, - 0x10, 0x00, 0x13, 0x06, 0x06, 0x7a, 0x93, 0x85, 0x05, 0x7b, 0x13, 0x05, 0x45, 0x7b, 0x06, 0xde, 0x16, 0xdc, 0x1a, - 0xda, 0x1e, 0xd8, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, - 0x7e, 0xc0, 0xef, 0xf0, 0xcf, 0xc8, 0xef, 0xe0, 0x8f, 0xd6, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, - 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, - 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x09, 0x65, 0x6f, 0x20, 0x00, 0x13, 0x09, 0x65, 0x6f, - 0x20, 0x60, 0x13, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xd0, 0xbf, 0xc3, 0xdd, 0x37, - 0xb7, 0x07, 0x00, 0x07, 0xd8, 0x43, 0x83, 0x47, 0x64, 0x00, 0xbd, 0x46, 0x63, 0x85, 0xd7, 0x00, 0x61, 0x9b, 0x9d, - 0x8b, 0x5d, 0x8f, 0x93, 0x77, 0x77, 0xff, 0x03, 0x47, 0x74, 0x00, 0x83, 0x46, 0x44, 0x00, 0xb2, 0x40, 0x0e, 0x07, - 0x21, 0x8b, 0x5d, 0x8f, 0xfd, 0x77, 0xbd, 0x07, 0x7d, 0x8f, 0x83, 0x47, 0x84, 0x00, 0x92, 0x07, 0x5d, 0x8f, 0xb7, - 0x17, 0x80, 0xff, 0xfd, 0x17, 0x7d, 0x8f, 0x83, 0x47, 0x54, 0x00, 0xa2, 0x07, 0xd5, 0x8f, 0xb2, 0x07, 0xb7, 0xf6, - 0x7f, 0x00, 0xf5, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x80, 0xf8, 0x7d, 0x17, 0xf9, 0x8f, 0x03, 0x47, 0xa4, 0x00, 0xb7, - 0x06, 0x80, 0x07, 0x5e, 0x07, 0x75, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x00, 0x88, 0x7d, 0x17, 0xf9, 0x8f, 0x03, 0x47, - 0x94, 0x00, 0xb7, 0x06, 0x00, 0x78, 0x22, 0x44, 0x6e, 0x07, 0x75, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x00, 0x07, 0x5c, - 0xc3, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x87, 0xf8, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x05, - 0x83, 0xa7, 0xc7, 0x20, 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, - 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x13, 0x05, 0xa0, 0x0a, 0x89, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, - 0x82, 0x80, 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x85, 0xbb, 0x6f, 0xf0, 0x5f, - 0x91, 0x41, 0x11, 0xb7, 0x07, 0x08, 0x05, 0x22, 0xc4, 0x03, 0xa4, 0xc7, 0x20, 0x37, 0x07, 0x00, 0x04, 0x06, 0xc6, - 0x26, 0xc2, 0xb3, 0x76, 0xe4, 0x00, 0x91, 0xca, 0x37, 0x55, 0x10, 0x00, 0x23, 0xa6, 0xe7, 0x20, 0xa5, 0x45, 0x13, - 0x05, 0x85, 0x7b, 0xef, 0xf0, 0xef, 0xbb, 0xb7, 0x07, 0x80, 0x6b, 0xe1, 0x8f, 0x95, 0xcb, 0x37, 0x07, 0x08, 0x05, - 0x23, 0x26, 0xf7, 0x20, 0xb7, 0x07, 0x00, 0x68, 0x7d, 0x8c, 0x93, 0x04, 0x50, 0x05, 0x11, 0xc8, 0x37, 0x55, 0x10, - 0x00, 0x9d, 0x45, 0x13, 0x05, 0x85, 0x7b, 0xef, 0xf0, 0x4f, 0xb9, 0xef, 0xd0, 0xdf, 0xb0, 0xb2, 0x40, 0x22, 0x44, - 0x26, 0x85, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0xf8, 0x84, 0x43, 0x13, - 0x07, 0xa0, 0x0a, 0x63, 0x96, 0xe4, 0x00, 0x13, 0x07, 0x50, 0x05, 0x98, 0xc3, 0xe1, 0xbf, 0x93, 0x04, 0xa0, 0x0a, - 0xd9, 0xbf, 0x81, 0x47, 0xb7, 0x05, 0x08, 0x05, 0x13, 0x07, 0x00, 0x20, 0xb3, 0x86, 0xb7, 0x00, 0x90, 0x42, 0xb3, - 0x06, 0xf5, 0x00, 0x91, 0x07, 0x90, 0xc2, 0xe3, 0x99, 0xe7, 0xfe, 0x6f, 0xf0, 0xff, 0xf5, 0x41, 0x11, 0x06, 0xc6, - 0x22, 0xc4, 0x2a, 0x84, 0xef, 0xf0, 0x1f, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa4, 0xe7, - 0xf8, 0x8d, 0x47, 0x33, 0x95, 0x87, 0x00, 0xb7, 0xb7, 0xaa, 0x02, 0x93, 0x87, 0xa7, 0xaa, 0x3d, 0x8d, 0xb7, 0x07, - 0x08, 0x05, 0x23, 0xa4, 0xa7, 0x20, 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x85, - 0xb9, 0xef, 0xf0, 0xdf, 0x82, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0xf1, 0x41, 0x11, 0x06, 0xc6, - 0xef, 0xf0, 0x9f, 0xef, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf8, 0x37, 0x07, 0x08, 0x05, 0x13, 0x05, 0x00, - 0x20, 0xf9, 0x9b, 0x23, 0x22, 0xf7, 0x20, 0xef, 0x10, 0x10, 0x74, 0xb2, 0x40, 0x39, 0x45, 0x41, 0x01, 0x6f, 0x10, - 0x30, 0x75, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf8, 0x1c, 0x43, 0x93, 0xf7, 0xf7, 0xfd, 0x1c, 0xc3, 0x37, - 0x07, 0x08, 0x05, 0x23, 0x22, 0xf7, 0x20, 0x82, 0x80, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf8, 0x1c, 0x43, - 0x93, 0xe7, 0x07, 0x02, 0x1c, 0xc3, 0x37, 0x07, 0x08, 0x05, 0x23, 0x22, 0xf7, 0x20, 0x82, 0x80, 0x33, 0x87, 0xc5, - 0x00, 0xb7, 0x07, 0x08, 0x00, 0x63, 0x7c, 0xf7, 0x06, 0x01, 0x11, 0x22, 0xcc, 0x26, 0xca, 0x4e, 0xc6, 0x06, 0xce, - 0x4a, 0xc8, 0x93, 0xf4, 0x35, 0x00, 0xaa, 0x89, 0x2e, 0x84, 0x13, 0x05, 0x50, 0x05, 0x9d, 0xec, 0x32, 0x89, 0xef, - 0xf0, 0x5f, 0xe7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x47, 0xf8, 0xb7, 0x06, 0x08, 0x05, 0xb7, 0x05, 0x00, 0x05, - 0x13, 0x67, 0x27, 0x00, 0x23, 0xa2, 0xe6, 0x20, 0x93, 0x87, 0x47, 0xf8, 0x0d, 0x47, 0x2e, 0x94, 0xb3, 0x06, 0x99, - 0x40, 0x63, 0x60, 0xd7, 0x02, 0x98, 0x43, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x05, 0xa0, 0x0a, 0x23, 0xa2, 0xe7, 0x20, - 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, 0xb3, 0x06, 0x94, 0x00, 0x90, - 0x42, 0xb3, 0x86, 0x99, 0x00, 0x91, 0x04, 0x90, 0xc2, 0xf9, 0xb7, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, - 0xaa, 0x85, 0x11, 0x46, 0x68, 0x00, 0x06, 0xce, 0xef, 0xf0, 0x1f, 0xf7, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, - 0x00, 0x32, 0x45, 0xf2, 0x40, 0x05, 0x61, 0x82, 0x80, 0x01, 0x45, 0xe5, 0xbf, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xef, - 0xa7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x8d, 0xe3, 0xae, - 0x84, 0xef, 0xf0, 0xbf, 0xdd, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x22, 0x44, 0xb2, 0x40, 0x23, 0xaa, - 0x97, 0x20, 0x92, 0x44, 0x01, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x9f, 0xe7, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, - 0x01, 0x82, 0x80, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xaa, 0x84, 0x2e, 0x84, 0xef, 0xf0, - 0x1f, 0xfb, 0x26, 0x85, 0xef, 0xf0, 0x9f, 0xf8, 0x63, 0x09, 0x85, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, - 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xcd, 0xbf, 0x01, 0x11, 0x22, 0xcc, 0x2e, 0xc6, - 0x06, 0xce, 0x2a, 0x84, 0xef, 0xf0, 0x3f, 0xf6, 0xb2, 0x45, 0x63, 0x03, 0xb5, 0x02, 0xfd, 0x57, 0x63, 0x1a, 0xf5, - 0x00, 0x63, 0x8e, 0xa5, 0x00, 0x22, 0x85, 0x62, 0x44, 0xf2, 0x40, 0x05, 0x61, 0x6f, 0xf0, 0xdf, 0xfa, 0x13, 0x05, - 0x50, 0x05, 0xf2, 0x40, 0x62, 0x44, 0x05, 0x61, 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xd5, 0xbf, 0xb7, 0x07, 0x08, - 0x00, 0x63, 0xe0, 0xb7, 0x04, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0xf7, 0xf5, 0x1f, 0xaa, 0x84, - 0x2e, 0x84, 0x13, 0x05, 0x50, 0x05, 0x99, 0xef, 0xef, 0xf0, 0x9f, 0xd2, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, - 0x20, 0x39, 0x45, 0xef, 0xf0, 0x3f, 0xdd, 0x26, 0x85, 0xef, 0xf0, 0xdf, 0xda, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, - 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, 0x06, 0xce, 0x22, - 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xfb, 0xb7, 0x00, 0x81, 0x44, 0xf2, 0x40, - 0x62, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x26, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x82, 0x80, 0x93, 0xf4, 0xf5, 0x1f, 0x2e, - 0x84, 0xe5, 0xf4, 0x2a, 0x89, 0xef, 0xf0, 0xdf, 0xcc, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x41, 0x45, - 0xef, 0xf0, 0x7f, 0xd7, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x17, 0xf5, 0xfc, 0x37, 0x34, 0x20, 0x00, 0x13, 0x05, 0x44, - 0xc9, 0xef, 0xf0, 0x3f, 0xd4, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x87, 0x07, 0x20, 0x23, 0xa0, 0x07, 0x00, 0x91, 0x07, - 0xe3, 0x9d, 0xe7, 0xfe, 0x93, 0x09, 0x44, 0xc9, 0x03, 0xd6, 0xc9, 0x1f, 0x93, 0x07, 0xc0, 0x1d, 0x63, 0xfa, 0xc7, - 0x00, 0x37, 0x55, 0x10, 0x00, 0x99, 0x45, 0x13, 0x05, 0x85, 0x7b, 0xef, 0xf0, 0x2f, 0x87, 0x41, 0xbf, 0x93, 0x05, - 0x44, 0xc9, 0x4a, 0x85, 0xef, 0x20, 0xe0, 0x57, 0x83, 0xd4, 0xc9, 0x1f, 0x41, 0xb7, 0xb7, 0x07, 0x08, 0x00, 0x63, - 0xe7, 0xa7, 0x04, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x13, 0x05, - 0x50, 0x05, 0x9d, 0xe7, 0xef, 0xf0, 0x9f, 0xc4, 0x85, 0x67, 0xb7, 0x04, 0x08, 0x05, 0x93, 0x87, 0x97, 0x82, 0x23, - 0xa2, 0xf4, 0x20, 0x23, 0xac, 0x84, 0x20, 0x39, 0x45, 0xef, 0xf0, 0x9f, 0xce, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, - 0x47, 0xf8, 0x13, 0x05, 0xa0, 0x0a, 0x23, 0xa2, 0xf4, 0x20, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, - 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x0d, 0x65, 0x01, 0x11, 0x13, 0x05, 0x05, 0x20, 0x06, 0xce, 0x22, 0xcc, - 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xef, 0x10, 0x10, 0x45, 0x39, 0x45, 0xef, 0x10, 0x70, 0x46, 0x13, 0x05, 0x80, - 0x07, 0x37, 0x39, 0x20, 0x00, 0xef, 0xf0, 0xef, 0xbd, 0x93, 0x09, 0x49, 0xf8, 0x83, 0xa7, 0x09, 0x00, 0x37, 0x04, - 0x08, 0x05, 0x93, 0x04, 0x04, 0x20, 0xdc, 0xc0, 0xb7, 0x07, 0x46, 0x00, 0x85, 0x07, 0xdc, 0xcc, 0x85, 0x67, 0x93, - 0x87, 0x57, 0x86, 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, 0xdc, 0xc0, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x25, 0xba, - 0xef, 0xf0, 0x6f, 0xcd, 0xb7, 0x07, 0x40, 0x08, 0x9c, 0xc8, 0xdc, 0x40, 0x01, 0x45, 0x13, 0x09, 0x49, 0xf8, 0x93, - 0xe7, 0x07, 0x18, 0x23, 0xa0, 0xf9, 0x00, 0xef, 0xf0, 0x7f, 0xf3, 0x93, 0x07, 0x04, 0x10, 0x98, 0x43, 0xb7, 0x67, - 0xa5, 0xf0, 0x93, 0x87, 0xf7, 0xa0, 0x63, 0x05, 0xf7, 0x02, 0x37, 0x55, 0x10, 0x00, 0x95, 0x45, 0x13, 0x05, 0x85, - 0x7b, 0xef, 0xe0, 0x3f, 0xf7, 0x41, 0x67, 0x7d, 0x17, 0x93, 0x07, 0x04, 0x18, 0xb8, 0xd3, 0xf8, 0xd3, 0xb8, 0xd7, - 0xf8, 0xd7, 0xb8, 0xdb, 0xf8, 0xdb, 0xb8, 0xdf, 0xf8, 0xdf, 0x51, 0x45, 0xef, 0xf0, 0x5f, 0xc1, 0xb7, 0x07, 0x08, - 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x91, 0x8b, 0x91, 0xeb, 0x37, 0x55, 0x10, 0x00, 0x91, 0x45, 0x13, 0x05, 0x85, 0x7b, - 0xef, 0xe0, 0xbf, 0xf3, 0xef, 0xd0, 0x2f, 0xeb, 0xb7, 0x07, 0x08, 0x05, 0x37, 0x07, 0x40, 0x00, 0x23, 0xa6, 0xe7, - 0x20, 0x03, 0x27, 0x09, 0x00, 0xf2, 0x40, 0x62, 0x44, 0x23, 0xa2, 0xe7, 0x20, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, - 0x05, 0x61, 0x82, 0x80, 0x85, 0x67, 0x37, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0x86, 0x23, 0x22, 0xf7, 0xf8, 0x37, - 0x37, 0x20, 0x00, 0x93, 0x07, 0x50, 0x05, 0x23, 0x24, 0xf7, 0xf8, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xf8, - 0x6f, 0xf0, 0xbf, 0xee, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe0, 0xa7, 0x06, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x77, 0xf5, - 0x1f, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x13, 0x05, 0x50, 0x05, 0xa1, 0xe3, 0xae, 0x84, 0xef, 0xf0, 0x5f, 0xad, - 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x01, 0x47, 0x93, 0x06, 0x00, 0x20, 0xb3, 0x85, 0xe4, 0x00, 0x8c, - 0x41, 0x33, 0x06, 0xf7, 0x00, 0x11, 0x07, 0x0c, 0xc2, 0xe3, 0x19, 0xd7, 0xfe, 0x7d, 0x57, 0x93, 0x87, 0x07, 0x20, - 0xf8, 0xc3, 0xb8, 0xc7, 0xf8, 0xc7, 0xb8, 0xcb, 0x29, 0x45, 0xef, 0xf0, 0x9f, 0xb5, 0x13, 0x05, 0xa0, 0x0a, 0xb2, - 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xaa, 0x85, 0x37, 0x05, - 0x08, 0x05, 0x41, 0x46, 0x13, 0x05, 0x05, 0x26, 0x6f, 0xf0, 0x8f, 0xd5, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xef, 0xa7, - 0x0a, 0x01, 0x11, 0x26, 0xca, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, - 0x56, 0xc2, 0xaa, 0x84, 0x13, 0x05, 0x50, 0x05, 0xd9, 0xe7, 0x93, 0x07, 0xc0, 0x1d, 0x32, 0x89, 0x63, 0xe3, 0xc7, - 0x08, 0xb6, 0x89, 0x37, 0x34, 0x20, 0x00, 0x2e, 0x8a, 0xef, 0xf0, 0x3f, 0xa4, 0x13, 0x06, 0x00, 0x20, 0x81, 0x45, - 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x00, 0x38, 0x4a, 0x86, 0xd2, 0x85, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x80, - 0x33, 0x4e, 0x85, 0xef, 0xf0, 0xbf, 0xf9, 0x93, 0x0a, 0x44, 0xc9, 0xb7, 0x07, 0x08, 0x05, 0x23, 0x9e, 0x2a, 0x1f, - 0x13, 0x07, 0x44, 0xc9, 0x93, 0x86, 0x07, 0x20, 0x10, 0x43, 0x11, 0x07, 0x90, 0xc3, 0x91, 0x07, 0xe3, 0x9c, 0xd7, - 0xfe, 0x13, 0x06, 0x00, 0x20, 0x81, 0x45, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x00, 0x34, 0xb7, 0x07, 0x08, 0x05, - 0x23, 0xac, 0x97, 0x20, 0x31, 0x45, 0xef, 0xf0, 0xff, 0xa9, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0x37, - 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x7b, 0x8d, 0x45, 0xef, 0xe0, 0x9f, 0xdc, 0x13, 0x05, 0x50, 0x05, 0xf2, 0x40, - 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x13, 0x05, 0x50, - 0x05, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xeb, 0xa7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, - 0xf5, 0x1f, 0x2a, 0x84, 0x89, 0xef, 0xef, 0xf0, 0xbf, 0x99, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x22, - 0x44, 0xb2, 0x40, 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0xff, 0xa3, 0xb2, 0x40, 0x22, 0x44, 0x13, 0x05, 0x50, 0x05, - 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x37, 0x04, 0x08, - 0x05, 0x23, 0x2c, 0xa4, 0x20, 0xef, 0xf0, 0x3f, 0x96, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa4, - 0xe7, 0xf8, 0xb7, 0xb7, 0xaa, 0x02, 0x93, 0x87, 0x67, 0xaa, 0xb2, 0x40, 0x23, 0x24, 0xf4, 0x20, 0x22, 0x44, 0x41, - 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xbf, 0x93, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, - 0x23, 0xa4, 0xe7, 0xf8, 0xb2, 0x40, 0xb7, 0xb7, 0xa6, 0x02, 0x37, 0x07, 0x08, 0x05, 0x93, 0x87, 0xa7, 0xaa, 0x23, - 0x24, 0xf7, 0x20, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x3e, 0xcc, 0xb7, 0x07, 0x08, 0x05, 0x3a, 0xce, 0x03, 0xa7, - 0xc7, 0x20, 0x36, 0xd0, 0xb7, 0x06, 0x40, 0x00, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, - 0xd4, 0x32, 0xd2, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0x75, 0x8f, 0x05, 0xcf, - 0x23, 0xa6, 0xd7, 0x20, 0x13, 0x07, 0xa0, 0x0a, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0xe7, 0xf8, 0xf2, 0x50, 0xe2, - 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, - 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x03, 0xa7, 0xc7, - 0x20, 0xb7, 0x06, 0x00, 0x08, 0x37, 0x55, 0x10, 0x00, 0x75, 0x8f, 0x0d, 0xc3, 0x23, 0xa6, 0xd7, 0x20, 0x85, 0x45, - 0x13, 0x05, 0x85, 0x7b, 0xef, 0xe0, 0xbf, 0xc8, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, - 0xf8, 0xef, 0xd0, 0x5f, 0xce, 0x75, 0xb7, 0x89, 0x45, 0x13, 0x05, 0x85, 0x7b, 0xef, 0xe0, 0xff, 0xc6, 0xb7, 0x07, - 0x02, 0x00, 0x73, 0xb0, 0x47, 0x30, 0xe5, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa8, 0xe7, - 0xf8, 0x82, 0x80, 0x99, 0x47, 0x63, 0x05, 0xf5, 0x02, 0x9d, 0x47, 0x63, 0x0b, 0xf5, 0x00, 0x95, 0x47, 0x63, 0x15, - 0xf5, 0x02, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xf7, 0xf7, 0xf7, 0x29, 0xa8, 0xb7, 0x37, 0x20, 0x00, 0x13, - 0x07, 0xa0, 0x0a, 0x23, 0xa8, 0xe7, 0xf8, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xe7, 0x07, 0x08, - 0x7c, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf9, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, 0xf7, - 0x00, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xe7, 0x07, 0x08, 0x7c, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, - 0x03, 0xa7, 0x07, 0xf9, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, 0xf7, 0x00, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, - 0xf7, 0xf7, 0xf7, 0x7c, 0xc3, 0x82, 0x80, 0x39, 0x71, 0x2a, 0xd6, 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, 0x13, 0x05, - 0xc5, 0x7b, 0x85, 0x45, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, - 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0x1f, 0xbb, 0xef, 0xd0, - 0x7f, 0xc1, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, - 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, - 0x20, 0x30, 0x39, 0x71, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, - 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xf3, 0x25, - 0x20, 0x34, 0xc1, 0x67, 0x37, 0x55, 0x10, 0x00, 0xdd, 0x8d, 0x13, 0x05, 0xc5, 0x7b, 0xef, 0xe0, 0x1f, 0xb5, 0xef, - 0xd0, 0x7f, 0xbb, 0x01, 0xa0, 0x39, 0x71, 0x2a, 0xd6, 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, 0x13, 0x05, 0xc5, 0x7b, - 0x89, 0x45, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, - 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0xbf, 0xb1, 0xef, 0xd0, 0x1f, 0xb8, - 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, - 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, - 0x37, 0x07, 0x01, 0x01, 0xb7, 0x07, 0x00, 0x01, 0x13, 0x07, 0x17, 0x10, 0x98, 0xd3, 0x37, 0x07, 0x03, 0x04, 0x09, - 0x07, 0xd8, 0xd3, 0x13, 0x07, 0x50, 0x60, 0x98, 0xd7, 0x37, 0x17, 0x09, 0x00, 0x13, 0x07, 0x77, 0x80, 0xd8, 0xd7, - 0x37, 0x17, 0x0b, 0x0b, 0x13, 0x07, 0xa7, 0xa0, 0x98, 0xdb, 0x37, 0x17, 0x0c, 0x00, 0x13, 0x07, 0xb7, 0xc0, 0xd8, - 0xdb, 0x37, 0x17, 0x0f, 0x00, 0x13, 0x07, 0xd7, 0xe0, 0x98, 0xdf, 0x05, 0x67, 0xd8, 0xdf, 0xb7, 0x17, 0xff, 0x7f, - 0x93, 0x87, 0x07, 0x80, 0x73, 0xa0, 0x47, 0x30, 0xa1, 0x47, 0x73, 0xa0, 0x07, 0x30, 0x82, 0x80, 0x41, 0x11, 0x3e, - 0xc6, 0xb7, 0x07, 0x40, 0x00, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, - 0x3e, 0xc6, 0xb7, 0x07, 0x80, 0x00, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, - 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x00, 0x04, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, - 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x00, 0x20, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, - 0x30, 0x05, 0x65, 0x6f, 0x10, 0xc0, 0x69, 0x05, 0x65, 0x6f, 0x10, 0x20, 0x6a, 0x01, 0x11, 0x22, 0xcc, 0x4a, 0xc8, - 0x4e, 0xc6, 0x06, 0xce, 0x26, 0xca, 0x52, 0xc4, 0x56, 0xc2, 0x9d, 0x47, 0x2a, 0x84, 0xae, 0x89, 0x32, 0x89, 0x63, - 0xd4, 0xc7, 0x00, 0xef, 0xd0, 0x4f, 0x99, 0xef, 0xf0, 0x5f, 0xfd, 0xb7, 0x07, 0x01, 0x07, 0x18, 0x40, 0xdc, 0x43, - 0x93, 0x06, 0xf0, 0x0f, 0x63, 0x05, 0xd7, 0x00, 0xf1, 0x9b, 0x0d, 0x8b, 0xd9, 0x8f, 0x13, 0xf7, 0xb7, 0xff, 0x83, - 0x47, 0x44, 0x00, 0x81, 0x44, 0x31, 0x4a, 0x8a, 0x07, 0x91, 0x8b, 0xd9, 0x8f, 0x37, 0x07, 0x01, 0x07, 0x5c, 0xc3, - 0xb7, 0x1a, 0x01, 0x07, 0x63, 0xcf, 0x24, 0x03, 0x14, 0x40, 0x05, 0x47, 0xad, 0x47, 0x63, 0x9e, 0xe6, 0x00, 0x83, - 0x46, 0x44, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0xbd, 0x47, 0x63, 0x97, 0xe6, 0x00, 0x14, 0x44, 0x37, 0x37, 0x20, 0x00, - 0x23, 0x2a, 0xd7, 0xf8, 0xf2, 0x40, 0x62, 0x44, 0x37, 0x07, 0x01, 0x07, 0x5c, 0xc7, 0xd2, 0x44, 0x42, 0x49, 0xb2, - 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xb3, 0x85, 0x44, 0x03, 0x13, 0x95, 0x44, 0x00, 0x31, 0x46, - 0x56, 0x95, 0x85, 0x04, 0xce, 0x95, 0xef, 0xf0, 0x4f, 0x87, 0x7d, 0xb7, 0x1d, 0x71, 0x3e, 0xda, 0xb7, 0x07, 0x01, - 0x07, 0xa2, 0xc6, 0x80, 0x47, 0x86, 0xce, 0x96, 0xcc, 0x9a, 0xca, 0x9e, 0xc8, 0xaa, 0xc4, 0xae, 0xc2, 0xb2, 0xc0, - 0x36, 0xde, 0x3a, 0xdc, 0x42, 0xd8, 0x46, 0xd6, 0x72, 0xd4, 0x76, 0xd2, 0x7a, 0xd0, 0x7e, 0xce, 0x93, 0x77, 0xb4, - 0x00, 0x95, 0xc7, 0xb7, 0x07, 0x00, 0x40, 0x73, 0xb0, 0x47, 0x30, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, - 0x37, 0x55, 0x10, 0x00, 0xa2, 0x86, 0x13, 0x06, 0x06, 0x7c, 0x93, 0x85, 0x85, 0x7c, 0x13, 0x05, 0x85, 0x77, 0xef, - 0xe0, 0x3f, 0x8c, 0xef, 0xd0, 0xff, 0x99, 0x93, 0x77, 0x44, 0x00, 0x99, 0xcf, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, - 0x47, 0xf9, 0x91, 0xcb, 0x6c, 0x00, 0x28, 0x00, 0x82, 0x97, 0x22, 0x47, 0xb7, 0x07, 0x01, 0x07, 0x98, 0xcb, 0x32, - 0x47, 0xd8, 0xcb, 0xb7, 0x07, 0x01, 0x07, 0x80, 0xc7, 0x36, 0x44, 0xf6, 0x40, 0xe6, 0x42, 0x56, 0x43, 0xc6, 0x43, - 0x26, 0x45, 0x96, 0x45, 0x06, 0x46, 0xf2, 0x56, 0x62, 0x57, 0xd2, 0x57, 0x42, 0x58, 0xb2, 0x58, 0x22, 0x5e, 0x92, - 0x5e, 0x02, 0x5f, 0xf2, 0x4f, 0x25, 0x61, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x07, 0x02, 0x04, 0xdc, 0x47, 0x13, 0x05, - 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x82, 0x80, 0x13, 0x05, 0x00, 0x08, 0x6f, - 0x10, 0x40, 0x52, 0x13, 0x05, 0x00, 0x08, 0x6f, 0x10, 0x80, 0x52, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, - 0x93, 0x07, 0xd0, 0x79, 0x37, 0x04, 0x02, 0x04, 0x5c, 0xc4, 0x85, 0x44, 0x95, 0x65, 0x37, 0x35, 0x10, 0x00, 0x04, - 0xc4, 0x93, 0x85, 0x05, 0xe2, 0x13, 0x05, 0x65, 0x6e, 0xef, 0xe0, 0xdf, 0xce, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x13, - 0xf5, 0x02, 0x54, 0x44, 0x63, 0x82, 0x96, 0x02, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, - 0x00, 0x13, 0x06, 0xc6, 0x7c, 0x93, 0x85, 0x45, 0x7d, 0x13, 0x05, 0x45, 0x75, 0xef, 0xe0, 0x6f, 0xff, 0x13, 0x05, - 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xdf, - 0xf8, 0xb2, 0x40, 0xb7, 0x07, 0x02, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0xb7, 0x37, - 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x22, 0xc4, 0x26, 0xc2, 0x23, 0xac, 0xe7, 0xf8, 0x06, 0xc6, 0x37, 0x07, 0x02, - 0x02, 0x89, 0x46, 0x54, 0xc7, 0x13, 0x84, 0x87, 0xf9, 0x93, 0x04, 0x50, 0x05, 0xef, 0xe0, 0x5f, 0xc7, 0x1c, 0x40, - 0xe3, 0x9d, 0x97, 0xfe, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x02, 0x02, 0xc8, - 0xcb, 0x05, 0x47, 0xd8, 0xc7, 0xd8, 0x53, 0x69, 0x8f, 0x63, 0x1e, 0xa7, 0x00, 0xd4, 0x57, 0x7d, 0x55, 0xf9, 0x8e, - 0x91, 0xea, 0x94, 0x57, 0x75, 0x8f, 0x19, 0xe7, 0x88, 0x47, 0x05, 0x89, 0x33, 0x05, 0xa0, 0x40, 0x82, 0x80, 0x7d, - 0x55, 0x82, 0x80, 0x41, 0x45, 0x6f, 0x10, 0x60, 0x44, 0x41, 0x45, 0x6f, 0x10, 0x40, 0x43, 0x01, 0x11, 0x06, 0xce, - 0x22, 0xcc, 0x2a, 0xc6, 0xef, 0xf0, 0x3f, 0xff, 0x13, 0x07, 0x50, 0x05, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0xe7, - 0xf8, 0x37, 0x04, 0x02, 0x02, 0xa1, 0x47, 0x5c, 0xc4, 0x32, 0x45, 0x85, 0x47, 0x1c, 0xc8, 0x93, 0x07, 0x10, 0x40, - 0x5c, 0xc0, 0xef, 0xf0, 0xbf, 0xf9, 0xef, 0xf0, 0xff, 0xf5, 0x23, 0x22, 0x04, 0x00, 0x62, 0x44, 0xf2, 0x40, 0x05, - 0x61, 0x6f, 0xf0, 0x7f, 0xfb, 0x41, 0x11, 0x3a, 0xc6, 0x37, 0x07, 0x02, 0x02, 0x3e, 0xc4, 0x1c, 0x47, 0x1c, 0xc7, - 0x85, 0x8b, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf8, 0x32, 0x47, 0xa2, - 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0xc7, 0xf9, 0x82, 0x80, 0xb7, 0x27, - 0x00, 0x06, 0x9c, 0x47, 0x05, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x9d, 0x8b, 0xfd, 0x17, 0x63, 0x74, 0xf7, 0x00, 0x13, - 0x05, 0x50, 0x05, 0x82, 0x80, 0x37, 0x27, 0x00, 0x06, 0x1c, 0x47, 0x85, 0x46, 0x13, 0x05, 0xa0, 0x0a, 0x9d, 0x8b, - 0x63, 0x89, 0xd7, 0x00, 0x1c, 0x47, 0x09, 0x47, 0x9d, 0x8b, 0x63, 0x84, 0xe7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, - 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xc0, 0x1f, 0xe9, - 0x89, 0x67, 0x63, 0x64, 0xf4, 0x00, 0xef, 0xc0, 0x7f, 0xe8, 0x89, 0x65, 0x37, 0x45, 0x10, 0x00, 0x13, 0x05, 0x25, - 0x88, 0x93, 0x85, 0x05, 0x71, 0xef, 0xe0, 0x3f, 0xc2, 0x37, 0x05, 0x00, 0x06, 0x2a, 0x94, 0x08, 0x40, 0xb2, 0x40, - 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x65, 0xb7, 0x37, 0x20, 0x00, 0x41, 0x11, 0x13, 0x07, 0x50, 0x05, 0x13, - 0x05, 0x05, 0x80, 0x23, 0xae, 0xe7, 0xf8, 0x06, 0xc6, 0xef, 0x10, 0xc0, 0x32, 0xef, 0xf0, 0xdf, 0xf6, 0x93, 0x07, - 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0x85, 0x7d, 0xef, 0xe0, 0x4f, - 0xeb, 0xef, 0xc0, 0xdf, 0xe2, 0xb7, 0x07, 0x46, 0x00, 0xb2, 0x40, 0x37, 0x27, 0x00, 0x06, 0x85, 0x07, 0x5c, 0xcf, - 0x85, 0x47, 0x5c, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x00, 0x03, 0x93, - 0x85, 0xc5, 0x7d, 0x0a, 0x85, 0x22, 0xdc, 0x26, 0xda, 0x4a, 0xd8, 0x06, 0xde, 0x0a, 0x84, 0xef, 0x10, 0x50, 0x39, - 0x7d, 0x59, 0xb7, 0x24, 0x00, 0x06, 0x08, 0x40, 0x19, 0xc9, 0xef, 0xf0, 0xdf, 0xf4, 0x63, 0x13, 0x25, 0x01, 0x08, - 0x44, 0x5c, 0x40, 0x31, 0x04, 0xa6, 0x97, 0x88, 0xc3, 0xed, 0xb7, 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, 0x42, 0x59, - 0x21, 0x61, 0x82, 0x80, 0x37, 0x27, 0x00, 0x06, 0x1c, 0x47, 0x85, 0x46, 0x9d, 0x8b, 0x63, 0x89, 0xd7, 0x02, 0x41, - 0x11, 0x06, 0xc6, 0x89, 0x65, 0x37, 0x45, 0x10, 0x00, 0x14, 0xcb, 0x13, 0x05, 0x85, 0x86, 0x93, 0x85, 0x05, 0x71, - 0xef, 0xe0, 0x7f, 0xb5, 0xb7, 0x27, 0x00, 0x06, 0x09, 0x47, 0x98, 0xcb, 0x05, 0x65, 0xb2, 0x40, 0x13, 0x05, 0x05, - 0x80, 0x41, 0x01, 0x6f, 0x10, 0x00, 0x28, 0xb7, 0x27, 0x00, 0x06, 0x09, 0x47, 0x05, 0x65, 0x98, 0xcb, 0x13, 0x05, - 0x05, 0x80, 0xfd, 0xb7, 0x05, 0x65, 0x41, 0x11, 0x13, 0x05, 0x05, 0x80, 0x06, 0xc6, 0xef, 0x10, 0x60, 0x25, 0xb2, - 0x40, 0xb7, 0x27, 0x00, 0x06, 0x21, 0x47, 0x98, 0xcb, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, - 0x26, 0xc2, 0xaa, 0x84, 0xef, 0xf0, 0xbf, 0xeb, 0x2a, 0x84, 0x6d, 0x2a, 0x13, 0x75, 0xf5, 0x07, 0xef, 0xe0, 0x7f, - 0xa1, 0x26, 0x85, 0xef, 0xf0, 0x9f, 0xea, 0x63, 0x05, 0xa4, 0x00, 0xef, 0xc0, 0xff, 0xd3, 0x01, 0x45, 0xb2, 0x40, - 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x06, - 0xd6, 0x52, 0xcc, 0xaa, 0x89, 0x2e, 0x89, 0x93, 0x74, 0xc6, 0xff, 0x01, 0x44, 0x33, 0x8a, 0x89, 0x00, 0x33, 0x05, - 0x89, 0x00, 0x63, 0x1a, 0x94, 0x00, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, - 0x61, 0x82, 0x80, 0xef, 0xf0, 0x9f, 0xf9, 0x2a, 0xc6, 0x11, 0x46, 0x6c, 0x00, 0x52, 0x85, 0xef, 0x10, 0xb0, 0x28, - 0x11, 0x04, 0xc9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x1f, 0xf8, 0x2a, 0x87, 0x85, 0x46, 0x01, 0x45, 0x89, - 0x45, 0x01, 0xe7, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x93, 0x77, 0xf7, 0x00, 0x01, 0x46, 0x81, 0xef, 0x63, 0xd3, - 0xc5, 0x00, 0xb6, 0x87, 0x5d, 0x8d, 0x86, 0x06, 0x13, 0x75, 0xf5, 0x0f, 0x93, 0xf6, 0xf6, 0x0f, 0x11, 0x83, 0xf1, - 0xbf, 0x13, 0xf8, 0x17, 0x00, 0x85, 0x83, 0x42, 0x96, 0x93, 0xf7, 0xf7, 0x0f, 0xf1, 0xbf, 0x41, 0x11, 0x22, 0xc4, - 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0xae, 0x84, 0x99, 0xc3, 0xef, 0xc0, 0x1f, 0xc9, 0x89, - 0x67, 0x63, 0x64, 0xf4, 0x00, 0xef, 0xc0, 0x7f, 0xc8, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xae, - 0xe7, 0xf8, 0xb7, 0x27, 0x00, 0x06, 0x84, 0xcf, 0xc0, 0xcb, 0x22, 0x44, 0xb2, 0x40, 0x92, 0x44, 0x11, 0x47, 0x98, - 0xcb, 0x89, 0x65, 0x37, 0x45, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0xe5, 0x85, 0x41, 0x01, 0x6f, 0xe0, - 0x3f, 0xa0, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xaa, 0x84, 0x2e, 0x84, 0xef, 0xf0, 0x3f, 0xfa, 0x26, - 0x85, 0xef, 0xf0, 0x1f, 0xda, 0x63, 0x09, 0x85, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, - 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xcd, 0xbf, 0x39, 0x71, 0x3a, 0xce, 0x37, 0x27, 0x00, 0x06, 0x3e, - 0xcc, 0x1c, 0x47, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, - 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xa1, 0x8b, 0x85, 0xcf, 0xa1, 0x47, 0x1c, - 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xae, 0xe7, 0xf8, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, - 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, - 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, - 0x13, 0x05, 0x85, 0x7d, 0xef, 0xe0, 0xaf, 0xc3, 0xef, 0xd0, 0x0f, 0xca, 0xe1, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x23, - 0xa0, 0xa7, 0xfa, 0x05, 0x47, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x82, 0xe7, 0xfa, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, - 0x83, 0xc7, 0x47, 0xfa, 0x41, 0x11, 0x06, 0xc6, 0x99, 0xe3, 0xef, 0xc0, 0xbf, 0xb8, 0xb7, 0x37, 0x20, 0x00, 0x93, - 0x87, 0x07, 0xfa, 0x88, 0x43, 0x37, 0x67, 0x19, 0x00, 0x13, 0x07, 0xd7, 0x60, 0x33, 0x05, 0xe5, 0x02, 0x37, 0xf7, - 0x6e, 0x3c, 0xb2, 0x40, 0x13, 0x07, 0xf7, 0x35, 0x3a, 0x95, 0x88, 0xc3, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, - 0x00, 0x93, 0x87, 0x47, 0xe9, 0x98, 0x43, 0x94, 0x47, 0xdc, 0x43, 0x18, 0x4f, 0x13, 0x05, 0xa0, 0x0a, 0x75, 0x8f, - 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0xe9, 0x88, - 0xc3, 0x37, 0x45, 0x10, 0x00, 0x13, 0x07, 0x00, 0x10, 0x93, 0x05, 0x80, 0x3e, 0x13, 0x05, 0x45, 0xbe, 0x23, 0xa2, - 0x07, 0x00, 0x98, 0xc7, 0x6f, 0xe0, 0x8f, 0xff, 0x37, 0x07, 0x01, 0x02, 0x5c, 0x43, 0xb7, 0x06, 0x05, 0x00, 0xd5, - 0x8f, 0x5c, 0xc3, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0xb7, 0x37, 0x00, 0x08, 0x37, 0x05, - 0x08, 0x00, 0x63, 0x0c, 0xf4, 0x00, 0xb7, 0x27, 0x00, 0x08, 0x37, 0x05, 0x04, 0x00, 0x63, 0x06, 0xf4, 0x00, 0xef, - 0xc0, 0xbf, 0xae, 0x37, 0x05, 0x08, 0x00, 0xef, 0x00, 0x50, 0x7c, 0x5c, 0x5c, 0x22, 0x85, 0xb2, 0x40, 0x93, 0xe7, - 0x37, 0x00, 0x5c, 0xdc, 0x23, 0x2c, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0xdf, 0xf8, 0xfd, 0x77, 0x41, - 0x11, 0xfd, 0x17, 0x22, 0xc4, 0x06, 0xc6, 0xe9, 0x8f, 0x37, 0x27, 0x00, 0x08, 0x2a, 0x84, 0x63, 0x84, 0xe7, 0x00, - 0xef, 0xc0, 0x1f, 0xab, 0x5c, 0x5c, 0x37, 0x05, 0x04, 0x00, 0xf5, 0x9b, 0x5c, 0xdc, 0xb7, 0x27, 0x00, 0x08, 0x63, - 0x04, 0xf4, 0x00, 0x37, 0x05, 0x08, 0x00, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x00, 0xf0, 0x77, 0x39, 0x71, - 0x22, 0xdc, 0x26, 0xda, 0x4a, 0xd8, 0x06, 0xde, 0x4e, 0xd6, 0x52, 0xd4, 0x56, 0xd2, 0x5a, 0xd0, 0x5e, 0xce, 0x62, - 0xcc, 0xaa, 0x84, 0x2e, 0x89, 0x32, 0x84, 0x99, 0xe1, 0xef, 0xc0, 0xff, 0xa6, 0xfd, 0x77, 0xfd, 0x17, 0xe5, 0x8f, - 0x37, 0x27, 0x00, 0x08, 0x63, 0x84, 0xe7, 0x00, 0xef, 0xc0, 0xdf, 0xa5, 0xb7, 0x39, 0x20, 0x00, 0x93, 0x89, 0x49, - 0xe9, 0x85, 0x4a, 0x37, 0x4b, 0x10, 0x00, 0x93, 0x0b, 0xa0, 0x0a, 0x11, 0x4c, 0x15, 0xe4, 0x9c, 0x4c, 0x37, 0x07, - 0x11, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x99, 0xc3, 0x13, 0x05, 0x50, 0x05, 0xf2, 0x50, 0x62, 0x54, 0xd2, - 0x54, 0x42, 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, 0x21, 0x61, 0x82, 0x80, - 0x93, 0x05, 0x80, 0x3e, 0x13, 0x05, 0x4b, 0xbe, 0x23, 0xa0, 0x99, 0x00, 0x23, 0xa2, 0x59, 0x01, 0x23, 0xa4, 0x59, - 0x01, 0xef, 0xe0, 0xef, 0xed, 0xe3, 0x16, 0x75, 0xfd, 0xdc, 0x50, 0x22, 0x8a, 0x3e, 0xc6, 0x63, 0x73, 0x8c, 0x00, - 0x11, 0x4a, 0x4a, 0x85, 0x52, 0x86, 0x6c, 0x00, 0xef, 0x10, 0x60, 0x78, 0x52, 0x99, 0x33, 0x04, 0x44, 0x41, 0x71, - 0xbf, 0x41, 0x11, 0x37, 0x05, 0x02, 0x00, 0x06, 0xc6, 0xef, 0x00, 0x90, 0x6b, 0xb2, 0x40, 0xb7, 0x17, 0x00, 0x08, - 0x37, 0x07, 0x07, 0x00, 0x98, 0xd3, 0x13, 0x05, 0x40, 0x1f, 0x41, 0x01, 0x6f, 0xe0, 0x2f, 0xe4, 0xb7, 0x17, 0x00, - 0x08, 0x23, 0xa0, 0x07, 0x02, 0x37, 0x05, 0x02, 0x00, 0x6f, 0x00, 0xf0, 0x69, 0x39, 0x71, 0x3e, 0xcc, 0xb7, 0x17, - 0x00, 0x08, 0x3a, 0xce, 0x98, 0x57, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, - 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0x05, 0x8b, 0x05, 0xcb, - 0x98, 0x57, 0x13, 0x67, 0x17, 0x00, 0x98, 0xd7, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, - 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, - 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x98, 0x57, 0x09, 0x8b, 0x09, 0xc7, 0x98, 0x57, 0x13, 0x67, 0x27, - 0x00, 0xf1, 0xb7, 0x98, 0x57, 0x11, 0x8b, 0x09, 0xc7, 0x98, 0x57, 0x13, 0x67, 0x47, 0x00, 0x7d, 0xbf, 0xb7, 0x07, - 0x00, 0x01, 0x73, 0xb0, 0x47, 0x30, 0xef, 0xd0, 0xcf, 0xa1, 0x4d, 0xbf, 0x37, 0x07, 0x00, 0x02, 0x5c, 0x4f, 0xb7, - 0x36, 0x20, 0x00, 0x13, 0xf6, 0x77, 0x00, 0xe1, 0x9b, 0x23, 0xa4, 0xc6, 0xfa, 0x93, 0xe7, 0x47, 0x00, 0x5c, 0xcf, - 0x1c, 0x4f, 0xf9, 0x9b, 0x1c, 0xcf, 0x82, 0x80, 0x41, 0x11, 0x26, 0xc2, 0xb7, 0x04, 0x00, 0x02, 0x22, 0xc4, 0xc0, - 0x4c, 0x9c, 0x4c, 0x06, 0xc6, 0x13, 0x05, 0x80, 0x07, 0x93, 0xe7, 0x17, 0x00, 0x9c, 0xcc, 0xef, 0xe0, 0xef, 0xd6, - 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x87, 0xfa, 0x61, 0x98, 0xb2, 0x40, 0x5d, 0x8c, 0xc0, 0xcc, 0x22, 0x44, 0x92, - 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x17, 0x05, 0x01, 0x93, 0x17, 0x85, 0x01, 0xba, 0x97, 0x13, 0x17, 0x85, 0x00, - 0xba, 0x97, 0x3e, 0x95, 0xb7, 0x07, 0x00, 0x04, 0x88, 0xd3, 0xc8, 0xd3, 0x88, 0xd7, 0xc8, 0xd7, 0x88, 0xdb, 0xc8, - 0xdb, 0x88, 0xdf, 0xc8, 0xdf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x00, 0x08, 0x98, 0xd3, 0x23, 0xa2, - 0x07, 0x02, 0x23, 0xa4, 0x07, 0x02, 0x23, 0xa6, 0x07, 0x02, 0x23, 0xa8, 0x07, 0x02, 0x23, 0xaa, 0x07, 0x02, 0x23, - 0xac, 0x07, 0x02, 0x23, 0xae, 0x07, 0x02, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x07, 0xeb, 0x82, 0x80, - 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0x6f, 0xe0, 0x0f, 0xfd, 0xb7, - 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa8, 0xe7, 0xea, 0xb7, 0x07, 0x00, 0x04, 0xc8, 0xc3, 0x13, 0x07, - 0x90, 0x02, 0x85, 0x65, 0x37, 0x45, 0x10, 0x00, 0x98, 0xc7, 0x93, 0x85, 0x85, 0x38, 0x13, 0x05, 0x25, 0xec, 0x6f, - 0xe0, 0x8f, 0xd1, 0x41, 0x11, 0x22, 0xc4, 0x01, 0x45, 0x37, 0x34, 0x20, 0x00, 0x06, 0xc6, 0x13, 0x04, 0x04, 0xea, - 0xef, 0xf0, 0xbf, 0xf5, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0xfb, 0x48, 0x44, 0xb7, - 0x07, 0x02, 0x00, 0x95, 0x07, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0xbf, 0xfa, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, - 0x05, 0x05, 0xef, 0xf0, 0xff, 0xf9, 0x48, 0x44, 0xb7, 0x07, 0x00, 0x10, 0x99, 0x07, 0x7e, 0x05, 0x5d, 0x8d, 0xef, - 0xf0, 0xff, 0xf8, 0x48, 0x44, 0xb7, 0x07, 0x01, 0x10, 0x99, 0x07, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0xff, 0xf7, - 0x22, 0x44, 0xb2, 0x40, 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0xf7, 0x7d, 0x47, 0x63, 0x7e, 0xb7, 0x04, 0xaa, - 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0x6f, 0xe0, 0x6f, 0xf2, 0xb3, 0x06, - 0xf5, 0x00, 0x83, 0xc6, 0x06, 0x00, 0x33, 0x07, 0xf1, 0x00, 0x85, 0x07, 0x23, 0x00, 0xd7, 0x00, 0xe3, 0x97, 0xf5, - 0xfe, 0x18, 0x10, 0x93, 0x87, 0x15, 0x00, 0xba, 0x95, 0x13, 0x07, 0x00, 0xf8, 0x23, 0x80, 0xe5, 0xfe, 0x13, 0x07, - 0x00, 0x02, 0x63, 0x92, 0xe7, 0x02, 0x37, 0x05, 0x00, 0x04, 0x8a, 0x85, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, 0x05, - 0x02, 0xef, 0xe0, 0x6f, 0xee, 0xb2, 0x50, 0x45, 0x61, 0x82, 0x80, 0x79, 0x71, 0x06, 0xd6, 0x81, 0x47, 0xd9, 0xb7, - 0xb3, 0x06, 0xf1, 0x00, 0x23, 0x80, 0x06, 0x00, 0x85, 0x07, 0xc9, 0xbf, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x00, - 0x08, 0x98, 0xd3, 0x23, 0xa2, 0x07, 0x02, 0x23, 0xa4, 0x07, 0x02, 0x23, 0xa6, 0x07, 0x02, 0x23, 0xa8, 0x07, 0x02, - 0x13, 0x17, 0xb5, 0x00, 0xb7, 0x06, 0xff, 0x00, 0x23, 0xaa, 0x07, 0x02, 0x75, 0x8f, 0x6e, 0x05, 0x23, 0xac, 0x07, - 0x02, 0x3a, 0x95, 0xc8, 0xdf, 0x82, 0x80, 0x37, 0x65, 0x10, 0x00, 0x01, 0x11, 0x13, 0x05, 0x45, 0x81, 0x06, 0xce, - 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x37, 0x34, 0x20, 0x00, 0xef, 0xf0, 0xdf, 0xe9, 0x93, - 0x07, 0x04, 0xea, 0xc8, 0x47, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xff, 0xe9, 0x93, 0x07, 0xa0, 0x0a, - 0x63, 0x10, 0xf5, 0x2e, 0xaa, 0x84, 0x13, 0x05, 0x00, 0x02, 0xef, 0xf0, 0x1f, 0xf9, 0x13, 0x04, 0x04, 0xea, 0x48, - 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xe7, 0xaa, 0x89, 0x63, 0x10, 0x95, 0x2c, 0x48, 0x44, - 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x7f, 0xe6, 0xaa, 0x84, 0x63, 0x15, 0x35, - 0x2b, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x5f, 0xe5, 0xaa, 0x89, 0x63, 0x1c, 0x95, 0x28, - 0x1c, 0x40, 0x48, 0x44, 0x37, 0x0a, 0x00, 0x04, 0x83, 0xc7, 0x07, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x15, 0x00, 0x93, - 0xe7, 0x07, 0x20, 0x23, 0x2c, 0xfa, 0x00, 0xef, 0xf0, 0x1f, 0xe3, 0xaa, 0x84, 0x63, 0x1a, 0x35, 0x27, 0x48, 0x44, - 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0xff, 0xe1, 0x2a, 0x89, 0x63, 0x11, 0x95, 0x26, 0xef, 0xf0, 0x1f, - 0xdd, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x9f, 0xe0, 0xaa, 0x84, 0x63, 0x16, 0x25, 0x25, - 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0xff, 0xef, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, - 0x17, 0xef, 0xf0, 0xbf, 0xde, 0x2a, 0x89, 0x63, 0x17, 0x95, 0x22, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, - 0xef, 0xf0, 0x9f, 0xdd, 0xaa, 0x84, 0x63, 0x1e, 0x25, 0x21, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, - 0xf0, 0x7f, 0xdc, 0x63, 0x16, 0x95, 0x20, 0x48, 0x44, 0x93, 0x07, 0x00, 0x10, 0x23, 0x2c, 0xfa, 0x00, 0x7e, 0x05, - 0x13, 0x65, 0x15, 0x00, 0xef, 0xf0, 0xff, 0xda, 0x93, 0x07, 0xa0, 0x0a, 0xaa, 0x84, 0x63, 0x17, 0xf5, 0x1e, 0x48, - 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x5f, 0xd9, 0xaa, 0x89, 0x63, 0x1c, - 0x95, 0x1c, 0xef, 0xf0, 0x7f, 0xd4, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xff, 0xd7, 0xaa, - 0x84, 0x63, 0x11, 0x35, 0x1d, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x5f, 0xe7, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, - 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x1f, 0xd6, 0xaa, 0x89, 0x63, 0x12, 0x95, 0x1a, 0x48, 0x44, 0x7e, - 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xff, 0xd4, 0xaa, 0x84, 0x63, 0x19, 0x35, 0x19, 0x48, 0x44, 0x7e, 0x05, - 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xdf, 0xd3, 0xaa, 0x89, 0x63, 0x10, 0x95, 0x18, 0x08, 0x40, 0x05, 0x05, 0xef, - 0xf0, 0xdf, 0xd1, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x3f, 0xd2, 0xaa, 0x84, 0x63, 0x13, - 0x35, 0x17, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x1f, 0xd1, 0x2a, 0x89, 0x63, 0x1a, 0x95, - 0x14, 0xef, 0xf0, 0x3f, 0xcc, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0xcf, 0xaa, 0x84, - 0x63, 0x1f, 0x25, 0x13, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x1f, 0xdf, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, - 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xcd, 0x63, 0x11, 0x95, 0x12, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, - 0x35, 0x00, 0xef, 0xf0, 0xdf, 0xcc, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0x63, 0x16, 0xf5, 0x10, 0x48, 0x44, 0x7e, - 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x7f, 0xcb, 0xaa, 0x84, 0x63, 0x1d, 0x25, 0x0f, 0x13, 0x05, 0x10, 0x02, - 0xef, 0xf0, 0xdf, 0xda, 0x1c, 0x40, 0x48, 0x44, 0x21, 0x67, 0x83, 0xc7, 0x07, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, - 0x17, 0xd9, 0x8f, 0x23, 0x20, 0xfa, 0x02, 0xef, 0xf0, 0xff, 0xc8, 0xaa, 0x89, 0x63, 0x19, 0x95, 0x0c, 0x48, 0x44, - 0x89, 0x64, 0x8d, 0x04, 0x7e, 0x05, 0x45, 0x8d, 0xef, 0xf0, 0xbf, 0xc7, 0x2a, 0x89, 0x63, 0x1f, 0x35, 0x0b, 0x48, - 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x9f, 0xc6, 0xaa, 0x89, 0x63, 0x16, 0x25, 0x0b, 0x08, 0x40, - 0x13, 0x05, 0x15, 0x02, 0xef, 0xf0, 0x7f, 0xc4, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, - 0xc4, 0x2a, 0x89, 0x63, 0x18, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, 0x45, 0x8d, 0xef, 0xf0, 0xdf, 0xc3, 0xaa, 0x84, - 0x63, 0x10, 0x25, 0x09, 0xef, 0xf0, 0xff, 0xbe, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x7f, - 0xc2, 0x2a, 0x89, 0x63, 0x15, 0x95, 0x06, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0xdf, 0xd1, 0x48, 0x44, 0x23, 0x20, - 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x9f, 0xc0, 0xaa, 0x84, 0x63, 0x16, 0x25, 0x05, 0x48, - 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x7f, 0xbf, 0x63, 0x1e, 0x95, 0x02, 0x48, 0x44, 0x7e, 0x05, - 0x13, 0x65, 0x05, 0x52, 0xef, 0xf0, 0x7f, 0xbe, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x14, 0xf5, 0x02, 0x08, 0x40, 0x62, - 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, - 0x93, 0x85, 0x05, 0x06, 0x13, 0x05, 0x15, 0x06, 0x05, 0x61, 0x6f, 0xe0, 0x6f, 0xb0, 0xf2, 0x40, 0x62, 0x44, 0xd2, - 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x4e, 0xc6, 0x06, 0xce, 0x22, 0xcc, - 0x26, 0xca, 0x4a, 0xc8, 0x52, 0xc4, 0x93, 0x09, 0x00, 0x04, 0x63, 0xe8, 0xb9, 0x08, 0x37, 0x3a, 0x20, 0x00, 0xaa, - 0x84, 0x2e, 0x84, 0x13, 0x09, 0x0a, 0xea, 0xef, 0xf0, 0x7f, 0xc1, 0x03, 0x25, 0xc9, 0x00, 0x13, 0x0a, 0x0a, 0xea, - 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x3f, 0xb7, 0x13, 0x85, 0x04, 0x02, 0x63, 0x19, 0x34, 0x03, 0xaa, - 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x05, 0x05, 0x02, 0x13, 0x06, 0x00, 0x02, 0xef, 0xe0, 0x4f, 0xb2, 0x03, 0x25, - 0xc9, 0x00, 0x62, 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x7e, 0x05, 0x13, 0x65, 0x05, - 0x17, 0x05, 0x61, 0x6f, 0xf0, 0xdf, 0xb3, 0xfd, 0x47, 0x63, 0xf5, 0x87, 0x02, 0x93, 0x05, 0x04, 0xfe, 0xef, 0xf0, - 0x1f, 0xbc, 0x13, 0x04, 0x04, 0x04, 0x93, 0x17, 0xb4, 0x00, 0x37, 0x07, 0xff, 0x00, 0xf9, 0x8f, 0x6e, 0x04, 0x3e, - 0x94, 0xb7, 0x07, 0x00, 0x04, 0x03, 0x25, 0xca, 0x00, 0xc0, 0xdf, 0x7d, 0xbf, 0x01, 0x45, 0xef, 0xf0, 0xff, 0xa9, - 0xf1, 0xbf, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x01, - 0x11, 0x22, 0xcc, 0x37, 0x34, 0x20, 0x00, 0x93, 0x07, 0x04, 0xea, 0x52, 0xc4, 0x2a, 0x8a, 0xc8, 0x47, 0x56, 0xc2, - 0x06, 0xce, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x30, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xae, 0x8a, 0xef, 0xf0, 0x1f, - 0xad, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x11, 0xf5, 0x12, 0xaa, 0x84, 0x13, 0x05, 0x60, 0x03, 0xef, 0xf0, 0x3f, 0xa5, - 0x13, 0x04, 0x04, 0xea, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x45, 0x00, 0xef, 0xf0, 0xff, 0xaa, 0x2a, 0x89, 0x63, - 0x11, 0x95, 0x10, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xa9, 0xaa, 0x84, 0x63, 0x18, - 0x25, 0x0f, 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x7f, 0xa8, 0xaa, - 0x89, 0x63, 0x1d, 0x95, 0x0c, 0xd6, 0x85, 0x52, 0x85, 0xef, 0xf0, 0x3f, 0xed, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, - 0x35, 0x00, 0xef, 0xf0, 0xdf, 0xa6, 0xaa, 0x84, 0x63, 0x10, 0x35, 0x0d, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, - 0x03, 0xef, 0xf0, 0xbf, 0xa5, 0xaa, 0x89, 0x63, 0x17, 0x95, 0x0a, 0x13, 0x05, 0xc0, 0x05, 0xef, 0xf0, 0x1f, 0x9e, - 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x45, 0x00, 0xef, 0xf0, 0x1f, 0xa4, 0xaa, 0x84, 0x63, 0x1a, 0x35, 0x09, 0x48, - 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xff, 0xa2, 0xaa, 0x89, 0x63, 0x11, 0x95, 0x08, 0x48, 0x44, - 0x7e, 0x05, 0x13, 0x65, 0x05, 0x32, 0xef, 0xf0, 0xdf, 0xa1, 0xaa, 0x84, 0x63, 0x18, 0x35, 0x07, 0x48, 0x44, 0x7e, - 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0xbf, 0xa0, 0x63, 0x10, 0x95, 0x06, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, - 0x05, 0x03, 0xef, 0xf0, 0xbf, 0x9f, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0x63, 0x15, 0xf5, 0x04, 0x13, 0x05, 0x00, - 0x06, 0xef, 0xf0, 0xdf, 0xae, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0x9d, 0xaa, 0x84, - 0x63, 0x18, 0x25, 0x03, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xbf, 0x9c, 0x63, 0x10, 0x95, - 0x02, 0x48, 0x44, 0x62, 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x7e, 0x05, - 0x13, 0x65, 0x05, 0x02, 0x05, 0x61, 0x6f, 0xf0, 0xbf, 0x9a, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, - 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x39, 0x71, 0x22, 0xdc, 0x37, 0x34, 0x20, 0x00, 0x06, 0xde, - 0x4a, 0xd8, 0x26, 0xda, 0x32, 0x89, 0x13, 0x04, 0x04, 0xea, 0xef, 0xf0, 0xdf, 0xe8, 0x48, 0x44, 0x7e, 0x05, 0x13, - 0x65, 0x05, 0x40, 0xef, 0xf0, 0x5f, 0x97, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x0a, 0xaa, 0x84, 0x37, 0x65, - 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0xc5, 0x80, 0xef, 0xf0, 0x9f, 0xe6, 0x85, 0x47, 0x63, 0x07, 0xf9, 0x08, 0x48, - 0x44, 0x85, 0x67, 0x93, 0x87, 0x07, 0x80, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0x7f, 0x94, 0x2a, 0x89, 0x63, 0x1c, - 0x95, 0x06, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x04, 0x68, 0x00, 0xef, 0xe0, 0xaf, - 0x87, 0x48, 0x44, 0x89, 0x47, 0x23, 0x06, 0xf1, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x20, 0xef, 0xf0, 0xdf, 0x91, - 0xaa, 0x84, 0x63, 0x17, 0x25, 0x05, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xbf, 0x90, 0x2a, - 0x89, 0x63, 0x1e, 0x95, 0x02, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x42, 0xef, 0xf0, 0x9f, 0x8f, 0xaa, 0x84, - 0x63, 0x15, 0x25, 0x03, 0x68, 0x00, 0x93, 0x05, 0x10, 0x02, 0xef, 0xf0, 0x5f, 0xdf, 0x48, 0x44, 0x7e, 0x05, 0x13, - 0x65, 0x05, 0x10, 0xef, 0xf0, 0xdf, 0x8d, 0x63, 0x18, 0x95, 0x00, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, - 0xef, 0xf0, 0xdf, 0x8c, 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, 0x42, 0x59, 0x21, 0x61, 0x82, 0x80, 0x41, 0x11, 0x22, - 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, 0xea, 0x08, 0x40, 0x09, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, - 0x15, 0x04, 0x06, 0xc6, 0xef, 0xf0, 0xff, 0xf0, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x71, 0xef, 0xf0, 0x7f, - 0x89, 0x48, 0x44, 0x22, 0x44, 0xb2, 0x40, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x5f, 0x88, - 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x07, 0xea, 0x05, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x6f, - 0xf0, 0xbf, 0xed, 0x41, 0x11, 0xb7, 0x65, 0x10, 0x00, 0x37, 0x05, 0x00, 0x04, 0x22, 0xc4, 0x13, 0x06, 0x00, 0x02, - 0x93, 0x85, 0x45, 0x81, 0x13, 0x05, 0x05, 0x02, 0x37, 0x34, 0x20, 0x00, 0x06, 0xc6, 0x13, 0x04, 0x04, 0xea, 0xef, - 0xe0, 0x4f, 0x81, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xdf, 0x83, 0x93, 0x07, 0xa0, 0x0a, - 0x63, 0x1d, 0xf5, 0x00, 0x08, 0x40, 0x22, 0x44, 0xb2, 0x40, 0x05, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, - 0x04, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xe8, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, - 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, 0xea, 0x48, 0x44, 0x06, 0xc6, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, - 0xf0, 0xcf, 0xff, 0x08, 0x40, 0x13, 0x06, 0x00, 0x02, 0x81, 0x45, 0x13, 0x05, 0x15, 0x04, 0xef, 0x00, 0x90, 0x62, - 0x08, 0x40, 0x09, 0x46, 0x81, 0x45, 0x13, 0x05, 0x15, 0x04, 0xef, 0xf0, 0xbf, 0xe4, 0x48, 0x44, 0x7e, 0x05, 0x13, - 0x65, 0x05, 0x60, 0xef, 0xf0, 0x2f, 0xfd, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x71, 0xef, 0xf0, 0x6f, 0xfc, - 0x01, 0x45, 0xef, 0xf0, 0x4f, 0xf5, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x4f, 0xfb, 0x48, - 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x8f, 0xfa, 0xb2, 0x40, 0x22, 0x44, 0xb7, 0x07, 0x00, 0x04, - 0x69, 0x47, 0x98, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x11, 0x65, 0xd5, 0xa1, 0x37, 0x35, 0x20, 0x00, 0x41, 0x11, 0x51, - 0x46, 0x81, 0x45, 0x13, 0x05, 0x05, 0xea, 0x06, 0xc6, 0xef, 0x00, 0xd0, 0x5b, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, - 0x50, 0x05, 0x1d, 0x65, 0x23, 0xa6, 0xe7, 0xfa, 0x55, 0x29, 0xb2, 0x40, 0xb7, 0x07, 0x00, 0x04, 0x05, 0x47, 0x98, - 0xcb, 0x41, 0x01, 0x6f, 0xf0, 0xdf, 0xfc, 0x11, 0x65, 0x45, 0xa1, 0x41, 0x11, 0x26, 0xc2, 0x4a, 0xc0, 0x06, 0xc6, - 0x22, 0xc4, 0x2a, 0x89, 0xae, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0xdf, 0xfa, 0x95, 0x47, 0x13, 0x05, 0x50, 0x05, 0x63, - 0xe6, 0x97, 0x02, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, 0xea, 0xb7, 0x65, 0x10, 0x00, 0x04, 0xc4, 0x93, 0x85, - 0x85, 0x83, 0x8a, 0x04, 0x85, 0x47, 0xae, 0x94, 0x5c, 0xc0, 0x9c, 0x40, 0x23, 0x20, 0x24, 0x01, 0x82, 0x97, 0x08, - 0x48, 0x23, 0x22, 0x04, 0x00, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x05, 0xe1, - 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0xef, 0xb0, 0x3f, 0xf6, 0xb7, 0x05, 0x00, 0x04, 0x32, 0x45, 0xf2, 0x40, 0x41, - 0x46, 0x93, 0x85, 0x05, 0x08, 0x05, 0x61, 0x6f, 0xd0, 0x7f, 0xe3, 0xb7, 0x05, 0x00, 0x04, 0x41, 0x46, 0x93, 0x85, - 0x05, 0x08, 0xcd, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x85, 0x47, 0x2a, 0x84, 0x63, 0xf4, 0xa7, 0x00, 0xef, - 0xb0, 0x1f, 0xf3, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xea, 0xc8, 0x47, 0x46, 0x04, 0xb2, 0x40, 0x7e, 0x05, - 0x49, 0x8c, 0x21, 0x65, 0x15, 0x05, 0x41, 0x8d, 0x22, 0x44, 0x09, 0x47, 0xd8, 0xc3, 0x41, 0x01, 0x6f, 0xf0, 0x8f, - 0xea, 0x39, 0x71, 0x22, 0xdc, 0x56, 0xd2, 0x5a, 0xd0, 0x06, 0xde, 0x26, 0xda, 0x4a, 0xd8, 0x4e, 0xd6, 0x52, 0xd4, - 0x5e, 0xce, 0x62, 0xcc, 0x66, 0xca, 0x6a, 0xc8, 0x2a, 0x84, 0x2e, 0x8b, 0xb2, 0x8a, 0x99, 0xe1, 0xef, 0xb0, 0x7f, - 0xee, 0xb7, 0x0b, 0x00, 0x04, 0xb7, 0x39, 0x20, 0x00, 0x05, 0x6c, 0x81, 0x44, 0x01, 0x49, 0xc1, 0x4c, 0x93, 0x8b, - 0x0b, 0x02, 0x93, 0x89, 0x09, 0xea, 0x09, 0x0c, 0x37, 0x3d, 0x20, 0x00, 0xb3, 0x05, 0x9b, 0x00, 0x63, 0xe0, 0x54, - 0x03, 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, 0x4b, - 0x62, 0x4c, 0xd2, 0x4c, 0x42, 0x4d, 0x21, 0x61, 0x82, 0x80, 0x33, 0x8a, 0x9a, 0x40, 0x63, 0xd3, 0x4c, 0x01, 0x41, - 0x4a, 0x4a, 0x85, 0x2e, 0xc6, 0xef, 0xe0, 0xcf, 0x8d, 0xb2, 0x45, 0x13, 0x06, 0x3a, 0x00, 0x71, 0x9a, 0x5e, 0x85, - 0xef, 0xd0, 0xdf, 0xde, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x2f, 0xe1, 0x03, - 0xa5, 0xc9, 0x00, 0x93, 0x17, 0x8a, 0x01, 0x7e, 0x05, 0x5d, 0x8d, 0x13, 0x65, 0x75, 0x00, 0xef, 0xf0, 0xef, 0xdf, - 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x33, 0x65, 0x85, 0x01, 0xef, 0xf0, 0x0f, 0xdf, 0x03, 0x27, 0xcd, 0xfa, 0x93, - 0x07, 0x50, 0x05, 0x63, 0x19, 0xf7, 0x00, 0x19, 0xc4, 0x22, 0x85, 0x52, 0x86, 0xca, 0x85, 0xef, 0xe0, 0x6f, 0x91, - 0x41, 0x04, 0x93, 0x07, 0x00, 0x07, 0x63, 0xe3, 0x27, 0x01, 0x41, 0x09, 0xc1, 0x04, 0x9d, 0xb7, 0x39, 0x71, 0x26, - 0xda, 0x52, 0xd4, 0x56, 0xd2, 0x06, 0xde, 0x22, 0xdc, 0x4a, 0xd8, 0x4e, 0xd6, 0x5a, 0xd0, 0x5e, 0xce, 0x62, 0xcc, - 0x66, 0xca, 0x6a, 0xc8, 0x6e, 0xc6, 0xaa, 0x8a, 0xae, 0x84, 0x32, 0x8a, 0x19, 0xe1, 0xef, 0xb0, 0x5f, 0xe0, 0xb7, - 0x39, 0x20, 0x00, 0x37, 0x0b, 0x02, 0x00, 0x85, 0x6b, 0x01, 0x49, 0x81, 0x4d, 0x37, 0x3c, 0x20, 0x00, 0x41, 0x4d, - 0x93, 0x89, 0x09, 0xea, 0x1d, 0x0b, 0x93, 0x8b, 0x0b, 0x82, 0xb3, 0x8c, 0x2a, 0x01, 0x93, 0x07, 0xcc, 0xfa, 0x63, - 0x64, 0x49, 0x03, 0xf2, 0x50, 0x62, 0x54, 0x13, 0x07, 0x50, 0x05, 0x98, 0xc3, 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, - 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, 0xd2, 0x4c, 0x42, 0x4d, 0xb2, 0x4d, 0x21, 0x61, 0x82, - 0x80, 0x33, 0x04, 0x2a, 0x41, 0x63, 0x73, 0x8d, 0x00, 0x41, 0x44, 0x6e, 0x85, 0xef, 0xd0, 0x9f, 0xff, 0xb7, 0x37, - 0x20, 0x00, 0x93, 0x87, 0xc7, 0xfa, 0x98, 0x43, 0x93, 0x07, 0x50, 0x05, 0x63, 0x19, 0xf7, 0x00, 0x99, 0xc4, 0x26, - 0x85, 0x22, 0x86, 0xee, 0x85, 0xef, 0xe0, 0x8f, 0x89, 0xc1, 0x04, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, - 0x25, 0x00, 0xef, 0xf0, 0x4f, 0xd1, 0x03, 0xa5, 0xc9, 0x00, 0x93, 0x17, 0x84, 0x01, 0x0d, 0x04, 0x7e, 0x05, 0x5d, - 0x8d, 0x33, 0x65, 0x65, 0x01, 0xef, 0xf0, 0xef, 0xcf, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x33, 0x65, 0x75, 0x01, - 0xef, 0xf0, 0x0f, 0xcf, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x76, 0xc4, 0xff, 0x93, 0x85, 0x05, 0x04, 0x66, 0x85, 0xef, - 0xd0, 0xbf, 0xc2, 0x93, 0x07, 0x00, 0x06, 0x63, 0xe3, 0xb7, 0x01, 0xc1, 0x0d, 0x41, 0x09, 0x81, 0xbf, 0x41, 0x11, - 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x7f, 0xd2, 0x21, 0x45, 0xef, 0xf0, 0xcf, 0xcb, 0x93, - 0x07, 0xa0, 0x0a, 0x63, 0x19, 0xf5, 0x00, 0x22, 0x85, 0xef, 0xf0, 0x9f, 0xda, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa2, - 0x07, 0xea, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa6, 0xa7, 0xfa, 0x82, - 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x60, 0x02, 0x98, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, - 0x98, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0xc8, 0x4b, 0x82, 0x80, 0x39, 0x71, 0x36, 0xd0, 0x3a, 0xce, 0x3e, - 0xcc, 0x05, 0x47, 0xb7, 0x07, 0x00, 0x04, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, - 0x32, 0xd2, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xd8, 0xc7, 0xb7, 0x37, 0x20, - 0x00, 0x93, 0x87, 0x07, 0xea, 0xd8, 0x43, 0x89, 0x46, 0x7d, 0x17, 0x63, 0xfe, 0xe6, 0x02, 0x37, 0x65, 0x10, 0x00, - 0x85, 0x45, 0x13, 0x05, 0x05, 0x81, 0xef, 0xd0, 0x4f, 0xd1, 0xef, 0xc0, 0xaf, 0xd7, 0xf2, 0x50, 0xe2, 0x52, 0x52, - 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, - 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x13, 0x07, 0xa0, 0x0a, 0x98, - 0xcb, 0xd1, 0xbf, 0xb7, 0x07, 0x01, 0x02, 0x88, 0xd7, 0xcc, 0xd7, 0x88, 0xdb, 0xcc, 0xdb, 0x88, 0xdf, 0xcc, 0xdf, - 0x82, 0x80, 0x01, 0x11, 0x26, 0xca, 0xb7, 0x04, 0x01, 0x02, 0x22, 0xcc, 0xc0, 0x40, 0xf5, 0x77, 0x93, 0x87, 0xf7, - 0xa5, 0x7d, 0x8c, 0x89, 0x67, 0x93, 0x87, 0x07, 0x1a, 0x06, 0xce, 0x4a, 0xc8, 0x4e, 0xc6, 0xc1, 0x8f, 0xaa, 0x89, - 0xdc, 0xc0, 0x05, 0x45, 0x2e, 0x89, 0xef, 0xd0, 0x1f, 0x8a, 0x93, 0x67, 0x04, 0x40, 0xdc, 0xc0, 0x05, 0x45, 0xef, - 0xd0, 0x5f, 0x89, 0x85, 0x67, 0x93, 0x87, 0x07, 0x40, 0x5d, 0x8c, 0xc0, 0xc0, 0xb7, 0x47, 0x00, 0x08, 0x23, 0xa4, - 0x07, 0x00, 0xb7, 0x57, 0x00, 0x08, 0x23, 0xa4, 0x07, 0x00, 0xf2, 0x40, 0x62, 0x44, 0x23, 0xa0, 0x34, 0x03, 0x23, - 0xa2, 0x24, 0x03, 0xb2, 0x49, 0xd2, 0x44, 0x42, 0x49, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x02, 0x88, 0x53, - 0xcc, 0x53, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x02, 0x88, 0x47, 0x21, 0x81, 0x13, 0x75, 0xf5, 0x0f, 0x82, 0x80, 0x41, - 0x11, 0x01, 0x45, 0x81, 0x45, 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0xef, 0xf0, 0x1f, 0xf6, 0xef, 0xf0, 0x9f, 0xfd, - 0xaa, 0x84, 0x2e, 0x84, 0x2a, 0x87, 0xae, 0x86, 0x37, 0x66, 0x10, 0x00, 0xb7, 0x65, 0x10, 0x00, 0x37, 0x55, 0x10, - 0x00, 0x93, 0x85, 0x85, 0x86, 0x13, 0x05, 0x85, 0x77, 0x13, 0x06, 0x06, 0x85, 0xef, 0xd0, 0x0f, 0xba, 0xa2, 0x85, - 0x22, 0x44, 0xb2, 0x40, 0x26, 0x85, 0x92, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xf3, 0x39, 0x71, 0x06, 0xde, 0x16, - 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, - 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xf0, 0x7f, 0xf9, 0xef, 0xc0, 0x6f, 0xc4, 0xf2, - 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, - 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0xb7, - 0x07, 0x00, 0x02, 0x0d, 0x47, 0xf8, 0xcb, 0x13, 0x07, 0x30, 0x03, 0xb8, 0xcf, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, - 0x5c, 0x47, 0xc9, 0x8f, 0x5c, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0xd8, 0x47, 0x13, 0x45, 0xf5, 0xff, 0x79, - 0x8d, 0xc8, 0xc7, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x4f, 0xc9, 0x8f, 0x1c, 0xcf, 0x82, 0x80, 0xb7, 0x07, - 0x00, 0x02, 0x98, 0x4f, 0x13, 0x45, 0xf5, 0xff, 0x79, 0x8d, 0x88, 0xcf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0xc8, - 0xcb, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x47, 0x00, 0x1c, 0xc7, 0xb7, 0x07, 0x00, 0x03, - 0x94, 0x4b, 0x37, 0x37, 0x20, 0x00, 0x23, 0x28, 0xd7, 0xfa, 0x23, 0xa8, 0x07, 0x00, 0x82, 0x80, 0x37, 0x07, 0x00, - 0x02, 0x1c, 0x47, 0xb7, 0x06, 0x00, 0x03, 0xf9, 0x9b, 0x1c, 0xc7, 0x37, 0x07, 0x08, 0x00, 0x9c, 0x46, 0xf9, 0x8f, - 0xf5, 0xff, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x17, 0x00, 0x1c, 0xc7, 0xb7, 0x37, 0x20, - 0x00, 0x03, 0xa7, 0x07, 0xfb, 0xb7, 0x07, 0x00, 0x03, 0x98, 0xcb, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, - 0x47, 0xfb, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0xb7, 0x27, 0x03, 0x04, 0x9c, 0x47, 0x13, 0x05, 0xa0, - 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x13, 0x05, 0x00, 0x10, 0x6f, 0xf0, 0x3f, 0xf4, - 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2a, 0xf7, 0xfa, 0x41, 0x11, 0x37, 0x37, 0x20, 0x00, 0x23, - 0x2c, 0xf7, 0xfa, 0x06, 0xc6, 0xef, 0xf0, 0x1f, 0xfe, 0xb7, 0x27, 0x03, 0x04, 0x09, 0x47, 0xd8, 0xc3, 0x37, 0x17, - 0x03, 0x04, 0xb7, 0x07, 0x03, 0x04, 0x13, 0x07, 0x07, 0x80, 0x23, 0xa0, 0x07, 0x00, 0x91, 0x07, 0xe3, 0x9d, 0xe7, - 0xfe, 0xb7, 0x27, 0x03, 0x04, 0x0d, 0x47, 0xd8, 0xc7, 0x98, 0x47, 0x85, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, - 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x00, 0x10, 0x6f, 0xf0, 0xff, - 0xee, 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2a, 0xf7, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2c, - 0xf7, 0xfa, 0xb7, 0x27, 0x03, 0x04, 0x05, 0x47, 0xd8, 0xc3, 0x82, 0x80, 0xc2, 0x05, 0xc9, 0x8d, 0x93, 0xe5, 0x05, - 0x10, 0xb7, 0x07, 0x03, 0x04, 0x23, 0xa0, 0xb7, 0x10, 0x82, 0x80, 0xc2, 0x05, 0xc9, 0x8d, 0x11, 0x65, 0x13, 0x05, - 0x05, 0x50, 0xc9, 0x8d, 0xb7, 0x07, 0x03, 0x04, 0x23, 0xa0, 0xb7, 0x10, 0x82, 0x80, 0xb7, 0x17, 0x03, 0x04, 0xbe, - 0x95, 0x6f, 0xd0, 0x9f, 0x89, 0xb7, 0x07, 0x03, 0x04, 0x3e, 0x95, 0x6f, 0xd0, 0xff, 0x90, 0xb7, 0x95, 0x04, 0x00, - 0x37, 0x55, 0x10, 0x00, 0x41, 0x11, 0x93, 0x85, 0x05, 0x3e, 0x13, 0x05, 0xa5, 0xcb, 0x06, 0xc6, 0x22, 0xc4, 0xef, - 0xd0, 0x6f, 0xe6, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0f, 0xf5, 0x00, 0x37, 0x65, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, - 0x05, 0x87, 0xef, 0xd0, 0xaf, 0x9f, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, - 0x17, 0x03, 0x04, 0x83, 0xa7, 0x07, 0x10, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x84, 0xfb, 0x93, 0xf7, 0xf7, 0x0f, - 0x81, 0xe7, 0x1c, 0x40, 0x63, 0x9d, 0xa7, 0x00, 0x37, 0x65, 0x10, 0x00, 0x8d, 0x45, 0x13, 0x05, 0x05, 0x87, 0xef, - 0xd0, 0x4f, 0x9c, 0x93, 0x07, 0xa0, 0x0a, 0x1c, 0xc0, 0xd1, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x47, 0xfb, - 0x13, 0x84, 0x47, 0xfb, 0x63, 0x09, 0xa7, 0x00, 0x37, 0x65, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0x05, 0x87, 0xef, - 0xd0, 0xef, 0x99, 0x08, 0x40, 0x5d, 0xb7, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x3f, 0xf4, 0xef, 0xf0, 0xff, 0xf0, - 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x1f, 0xf6, 0xb7, 0x17, 0x03, 0x04, 0x03, 0xa5, 0x07, 0x10, 0x41, 0x81, 0x82, - 0x80, 0x41, 0x11, 0x3a, 0xc4, 0x37, 0x27, 0x03, 0x04, 0x3e, 0xc2, 0x1c, 0x47, 0x36, 0xc6, 0x93, 0xf6, 0x27, 0x00, - 0x89, 0xca, 0x89, 0x46, 0x14, 0xc7, 0x37, 0x37, 0x20, 0x00, 0x93, 0x06, 0xa0, 0x0a, 0x23, 0x2a, 0xd7, 0xfa, 0x91, - 0x8b, 0x99, 0xcf, 0xb7, 0x27, 0x03, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x93, 0x07, 0xa0, 0x0a, 0x37, 0x37, 0x20, 0x00, - 0x23, 0x2c, 0xf7, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2a, 0xf7, 0xfa, 0xb2, 0x46, 0x22, 0x47, 0x92, 0x47, 0x41, - 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x04, 0x00, 0x03, 0x1c, 0x48, 0x06, 0xc6, 0xdd, 0x9b, - 0x1c, 0xc8, 0xef, 0xe0, 0xcf, 0xd1, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x02, 0x5c, 0xcc, 0xb2, 0x40, 0x22, - 0x44, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x80, 0x07, 0xfc, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x2a, 0x84, - 0x21, 0x45, 0x06, 0xc6, 0xef, 0xf0, 0x5f, 0xd8, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x5f, 0xd4, 0x22, 0x04, 0x13, - 0x64, 0x04, 0x03, 0x37, 0x07, 0x00, 0x03, 0x40, 0xc3, 0xb2, 0x40, 0x22, 0x44, 0xc1, 0x67, 0x93, 0x87, 0xa7, 0xfa, - 0x1c, 0xcf, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xaa, 0x84, 0x2e, 0x84, 0x19, - 0xe1, 0xef, 0xb0, 0x5f, 0x83, 0x19, 0xe0, 0xef, 0xb0, 0xff, 0x82, 0x09, 0x45, 0xef, 0xf0, 0x5f, 0xfb, 0x37, 0x07, - 0x20, 0x00, 0xb7, 0x07, 0x00, 0x03, 0x13, 0x07, 0x07, 0x02, 0xd8, 0xcf, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2e, 0x97, - 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x22, 0x87, 0xfc, 0xb2, 0x40, 0x22, 0x44, 0x05, 0x47, 0x98, 0xcb, 0x37, 0x07, - 0x08, 0x00, 0x98, 0xc7, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x03, 0x9c, 0x47, 0x37, 0x07, 0x04, - 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x37, 0x07, 0x00, 0x03, - 0x5c, 0x53, 0x13, 0x05, 0x50, 0x05, 0x93, 0x96, 0x07, 0x01, 0xc1, 0x82, 0xc1, 0x83, 0x63, 0x97, 0xf6, 0x00, 0x1c, - 0x47, 0x91, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x3f, 0xf1, - 0x37, 0x07, 0x00, 0x03, 0x5c, 0x47, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc7, 0x5c, 0x47, 0x85, 0x8b, 0xf5, 0xff, 0xb2, - 0x40, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xfc, 0x95, 0xc3, 0x41, 0x11, 0x06, 0xc6, - 0xef, 0xf0, 0x9f, 0xee, 0xb7, 0x07, 0x00, 0x03, 0x98, 0x4b, 0xb2, 0x40, 0x13, 0x67, 0x87, 0x00, 0x98, 0xcb, 0x37, - 0x07, 0x08, 0x00, 0x98, 0xc7, 0x41, 0x01, 0x6f, 0xe0, 0xcf, 0xbd, 0x82, 0x80, 0x37, 0x07, 0x00, 0x03, 0x1c, 0x4b, - 0xf9, 0x9b, 0x1c, 0xcb, 0x82, 0x80, 0xb7, 0x06, 0x00, 0x03, 0xdc, 0x42, 0x7d, 0x77, 0x13, 0x07, 0xf7, 0x0f, 0xf9, - 0x8f, 0x05, 0x67, 0x22, 0x05, 0x13, 0x07, 0x07, 0xf0, 0x79, 0x8d, 0x5d, 0x8d, 0xc8, 0xc2, 0x82, 0x80, 0x1d, 0x71, - 0x3a, 0xda, 0x37, 0x07, 0x00, 0x03, 0x3e, 0xd8, 0x1c, 0x47, 0x86, 0xce, 0x96, 0xcc, 0x9a, 0xca, 0x9e, 0xc8, 0xa2, - 0xc6, 0xa6, 0xc4, 0xaa, 0xc2, 0xae, 0xc0, 0x32, 0xde, 0x36, 0xdc, 0x42, 0xd6, 0x46, 0xd4, 0x4a, 0xd2, 0x4e, 0xd0, - 0x72, 0xce, 0x76, 0xcc, 0x7a, 0xca, 0x7e, 0xc8, 0x85, 0x8b, 0xa1, 0xc7, 0x04, 0x57, 0x11, 0x44, 0x37, 0x39, 0x20, - 0x00, 0x83, 0x27, 0xc9, 0xfb, 0x13, 0xf5, 0xf4, 0x0f, 0x7d, 0x14, 0x82, 0x97, 0xa1, 0x80, 0x6d, 0xf8, 0x36, 0x44, - 0xf6, 0x40, 0xe6, 0x42, 0x56, 0x43, 0xc6, 0x43, 0xa6, 0x44, 0x16, 0x45, 0x86, 0x45, 0x72, 0x56, 0xe2, 0x56, 0x52, - 0x57, 0xc2, 0x57, 0x32, 0x58, 0xa2, 0x58, 0x12, 0x59, 0x82, 0x59, 0x72, 0x4e, 0xe2, 0x4e, 0x52, 0x4f, 0xc2, 0x4f, - 0x25, 0x61, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xc7, 0x07, 0xfc, 0x13, 0x84, 0x07, 0xfc, 0x05, - 0xeb, 0xb7, 0x04, 0x00, 0x03, 0x37, 0x39, 0x20, 0x00, 0x93, 0x09, 0xa0, 0x0a, 0x9c, 0x44, 0x91, 0x8b, 0xd5, 0xfb, - 0x83, 0x27, 0x49, 0xfc, 0x68, 0x00, 0x82, 0x97, 0x63, 0x0d, 0x35, 0x01, 0x85, 0x47, 0x23, 0x00, 0xf4, 0x00, 0xc1, - 0x67, 0x93, 0x87, 0x07, 0x02, 0xdc, 0xcc, 0x61, 0xbf, 0xef, 0xf0, 0x9f, 0xde, 0x49, 0xbf, 0xb2, 0x47, 0x9c, 0xd8, - 0xd1, 0xbf, 0xb7, 0x07, 0xf0, 0xfe, 0x37, 0x07, 0xf0, 0xff, 0x41, 0x11, 0xaa, 0x97, 0x7d, 0x17, 0x22, 0xc4, 0x06, - 0xc6, 0xf9, 0x8f, 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xb0, 0x6f, 0xe6, 0x5c, 0x40, 0xb2, 0x40, 0x93, 0xe7, 0x17, 0x00, - 0x5c, 0xc0, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0xf0, 0xfe, 0x37, 0x07, 0xf0, 0xff, 0x41, 0x11, 0xaa, - 0x97, 0x7d, 0x17, 0x22, 0xc4, 0x06, 0xc6, 0xf9, 0x8f, 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xb0, 0xaf, 0xe3, 0x5c, 0x40, - 0xb2, 0x40, 0xf9, 0x9b, 0x5c, 0xc0, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0xf0, 0xfe, 0x37, 0x07, 0xf0, - 0xff, 0x01, 0x11, 0xaa, 0x97, 0x7d, 0x17, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0x06, 0xce, 0xf9, 0x8f, - 0x2a, 0x84, 0x2e, 0x89, 0xb2, 0x84, 0xb6, 0x89, 0x99, 0xc3, 0xef, 0xb0, 0x4f, 0xe0, 0x5c, 0x40, 0x13, 0xf6, 0x24, - 0x00, 0xf2, 0x40, 0xf5, 0x9b, 0x5d, 0x8e, 0x50, 0xc0, 0x23, 0x28, 0x34, 0x01, 0x23, 0x2a, 0x24, 0x01, 0x62, 0x44, - 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x07, 0xf0, 0xfe, 0x37, 0x07, 0xf0, 0xff, 0x41, - 0x11, 0xaa, 0x97, 0x7d, 0x17, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xf9, 0x8f, 0x2a, 0x84, 0xae, 0x84, 0x99, 0xc3, - 0xef, 0xb0, 0x2f, 0xdc, 0x5c, 0x44, 0xb2, 0x40, 0xb3, 0xe5, 0x97, 0x00, 0x4c, 0xc4, 0x22, 0x44, 0x92, 0x44, 0x41, - 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x87, 0xfc, 0x82, 0x80, 0x39, 0x71, 0x3a, 0xce, 0x37, 0x07, - 0x10, 0x01, 0x3e, 0xcc, 0x1c, 0x47, 0x58, 0x47, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, - 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xf9, 0x8f, - 0x91, 0xcf, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x87, 0xfc, 0x98, 0x43, 0x05, 0x07, 0x98, 0xc3, 0xb7, 0x07, 0x10, - 0x01, 0x98, 0x47, 0x0d, 0x8b, 0x98, 0xc7, 0x19, 0xa8, 0xb7, 0x07, 0x20, 0x01, 0x98, 0x47, 0xdc, 0x47, 0x7d, 0x8f, - 0xb7, 0x07, 0x20, 0x01, 0x6d, 0xf7, 0xef, 0xb0, 0x9f, 0xe3, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, - 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, - 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x1c, 0x41, 0x63, 0xf7, 0xb7, 0x00, 0x23, 0x80, 0xc7, - 0x00, 0x1c, 0x41, 0x85, 0x07, 0x1c, 0xc1, 0x82, 0x80, 0x1d, 0x71, 0xa2, 0xcc, 0xa6, 0xca, 0xca, 0xc8, 0x86, 0xce, - 0xce, 0xc6, 0xd2, 0xc4, 0xd6, 0xc2, 0xda, 0xc0, 0x5e, 0xde, 0x62, 0xdc, 0x66, 0xda, 0x6a, 0xd8, 0x6e, 0xd6, 0x2a, - 0xc6, 0x2e, 0x84, 0x32, 0x89, 0xb6, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x8f, 0xce, 0x63, 0x14, 0x09, 0x00, 0xef, 0xb0, - 0x0f, 0xce, 0x01, 0x45, 0x05, 0xc4, 0xb2, 0x4a, 0x7d, 0x14, 0x25, 0x4a, 0x56, 0x94, 0x93, 0x0c, 0xc0, 0x06, 0x13, - 0x0b, 0x30, 0x07, 0xa9, 0x4b, 0x1d, 0x4d, 0x03, 0x46, 0x09, 0x00, 0x15, 0xe6, 0xb2, 0x47, 0x23, 0x80, 0x07, 0x00, - 0x32, 0x45, 0x33, 0x05, 0x55, 0x41, 0xf6, 0x40, 0x66, 0x44, 0xd6, 0x44, 0x46, 0x49, 0xb6, 0x49, 0x26, 0x4a, 0x96, - 0x4a, 0x06, 0x4b, 0xf2, 0x5b, 0x62, 0x5c, 0xd2, 0x5c, 0x42, 0x5d, 0xb2, 0x5d, 0x25, 0x61, 0x82, 0x80, 0x93, 0x07, - 0x50, 0x02, 0x63, 0x1f, 0xf6, 0x02, 0x93, 0x07, 0x19, 0x00, 0x83, 0xc6, 0x07, 0x00, 0x3e, 0x89, 0x85, 0x07, 0x13, - 0x87, 0x06, 0xfd, 0x13, 0x77, 0xf7, 0x0f, 0xe3, 0x78, 0xea, 0xfe, 0x63, 0x93, 0x96, 0x01, 0x3e, 0x89, 0x03, 0x46, - 0x09, 0x00, 0x63, 0x06, 0x66, 0x0d, 0x63, 0x60, 0xcb, 0x02, 0x93, 0x07, 0x30, 0x06, 0x63, 0x05, 0xf6, 0x06, 0x93, - 0x07, 0x40, 0x06, 0x63, 0x0c, 0xf6, 0x06, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, 0xf2, 0xa6, 0x89, 0x95, 0xa0, - 0x93, 0x07, 0x50, 0x07, 0x63, 0x02, 0xf6, 0x06, 0x93, 0x07, 0x80, 0x07, 0xe3, 0x14, 0xf6, 0xfe, 0x98, 0x40, 0x93, - 0x89, 0x44, 0x00, 0x81, 0x46, 0x37, 0x06, 0x00, 0xf0, 0xb3, 0x75, 0xc7, 0x00, 0xba, 0x84, 0x36, 0x8c, 0x12, 0x07, - 0x85, 0x06, 0x89, 0xe5, 0xe3, 0x99, 0xa6, 0xff, 0x1d, 0x4c, 0xba, 0x84, 0xa1, 0x4d, 0x13, 0xd7, 0xc4, 0x01, 0x63, - 0x74, 0xea, 0x08, 0x13, 0x06, 0x77, 0x05, 0xa2, 0x85, 0x68, 0x00, 0x05, 0x0c, 0xef, 0xf0, 0x1f, 0xee, 0x92, 0x04, - 0xe3, 0x14, 0xbc, 0xff, 0x09, 0xa8, 0x03, 0xc6, 0x04, 0x00, 0xa2, 0x85, 0x68, 0x00, 0x93, 0x89, 0x44, 0x00, 0xef, - 0xf0, 0x9f, 0xec, 0x05, 0x09, 0xce, 0x84, 0x31, 0xbf, 0x5c, 0x08, 0x98, 0x40, 0x93, 0x89, 0x44, 0x00, 0x3e, 0x8c, - 0x81, 0x44, 0xb3, 0x76, 0x77, 0x03, 0x85, 0x04, 0x85, 0x07, 0x93, 0x86, 0x06, 0x03, 0xa3, 0x8f, 0xd7, 0xfe, 0xba, - 0x86, 0x33, 0x57, 0x77, 0x03, 0xe3, 0x65, 0xda, 0xfe, 0xfd, 0x5d, 0xfd, 0x14, 0xe3, 0x88, 0xb4, 0xfd, 0xb3, 0x07, - 0x9c, 0x00, 0x03, 0xc6, 0x07, 0x00, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0x5f, 0xe8, 0xed, 0xb7, 0x93, 0x89, 0x44, - 0x00, 0x84, 0x40, 0x03, 0xc6, 0x04, 0x00, 0x45, 0xda, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, 0xe6, 0x85, 0x04, - 0xc5, 0xbf, 0x13, 0x06, 0x07, 0x03, 0xb5, 0xbf, 0x41, 0x11, 0x26, 0xc2, 0xb7, 0x34, 0x20, 0x00, 0x2a, 0x86, 0xae, - 0x86, 0x13, 0x85, 0x44, 0xeb, 0x93, 0x05, 0x00, 0x08, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0xf0, 0xbf, 0xe5, 0x2a, 0x84, - 0x13, 0x85, 0x44, 0xeb, 0xef, 0xd0, 0x6f, 0x8d, 0xb2, 0x40, 0x22, 0x85, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, - 0x80, 0x39, 0x71, 0x26, 0xca, 0xb7, 0x34, 0x20, 0x00, 0x2e, 0xd2, 0x32, 0xd4, 0x36, 0xd6, 0x2a, 0x86, 0x54, 0x10, - 0x93, 0x05, 0x00, 0x08, 0x13, 0x85, 0x44, 0xeb, 0x06, 0xce, 0x22, 0xcc, 0x3a, 0xd8, 0x3e, 0xda, 0x42, 0xdc, 0x46, - 0xde, 0x36, 0xc6, 0xef, 0xf0, 0x9f, 0xe1, 0x2a, 0x84, 0x13, 0x85, 0x44, 0xeb, 0xef, 0xd0, 0x4f, 0x89, 0xf2, 0x40, - 0x22, 0x85, 0x62, 0x44, 0xd2, 0x44, 0x21, 0x61, 0x82, 0x80, 0x22, 0x05, 0x61, 0x77, 0x2d, 0x8d, 0xa1, 0x47, 0x15, - 0x07, 0x93, 0x16, 0x05, 0x01, 0x06, 0x05, 0x42, 0x05, 0xc1, 0x86, 0x41, 0x81, 0x63, 0xd5, 0x06, 0x00, 0x39, 0x8d, - 0x42, 0x05, 0x41, 0x81, 0xfd, 0x17, 0xe5, 0xf7, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x2a, - 0x84, 0xae, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x8f, 0xad, 0xa2, 0x94, 0x01, 0x45, 0x63, 0x17, 0x94, 0x00, 0xb2, 0x40, - 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x04, 0xaa, 0x85, 0x03, 0x45, 0xf4, 0xff, 0xef, 0xf0, 0xff, - 0xfa, 0xdd, 0xb7, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x2a, 0x84, 0xae, 0x84, 0x19, 0xe1, 0xef, 0xb0, - 0x6f, 0xaa, 0xb7, 0x86, 0xb8, 0xed, 0x01, 0x47, 0xfd, 0x57, 0x93, 0x86, 0x06, 0x32, 0x63, 0x19, 0x97, 0x00, 0xb2, - 0x40, 0x22, 0x44, 0x92, 0x44, 0x13, 0xc5, 0xf7, 0xff, 0x41, 0x01, 0x82, 0x80, 0x33, 0x06, 0xe4, 0x00, 0x03, 0x46, - 0x06, 0x00, 0xb1, 0x8f, 0x21, 0x46, 0x93, 0xd5, 0x17, 0x00, 0x85, 0x8b, 0x91, 0xc3, 0xb6, 0x87, 0x7d, 0x16, 0xad, - 0x8f, 0x6d, 0xfa, 0x05, 0x07, 0xc1, 0xbf, 0x2a, 0x83, 0x09, 0xca, 0x83, 0x83, 0x05, 0x00, 0x23, 0x00, 0x73, 0x00, - 0x7d, 0x16, 0x05, 0x03, 0x85, 0x05, 0x6d, 0xfa, 0x82, 0x80, 0x15, 0xc2, 0x2a, 0x83, 0x85, 0x46, 0x63, 0x67, 0xb5, - 0x00, 0xfd, 0x56, 0x13, 0x07, 0xf6, 0xff, 0x3a, 0x93, 0xba, 0x95, 0x83, 0x83, 0x05, 0x00, 0x23, 0x00, 0x73, 0x00, - 0x7d, 0x16, 0x36, 0x93, 0xb6, 0x95, 0x6d, 0xfa, 0x82, 0x80, 0x2a, 0x83, 0x11, 0xc6, 0x23, 0x00, 0xb3, 0x00, 0x7d, - 0x16, 0x05, 0x03, 0x65, 0xfe, 0x82, 0x80, 0x00, 0x00, 0x63, 0x6f, 0x64, 0x65, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, - 0x00, 0x00, 0x53, 0x45, 0x43, 0x43, 0x48, 0x4e, 0x4c, 0x00, 0x4d, 0x43, 0x4e, 0x54, 0x00, 0x00, 0x00, 0x00, 0x65, - 0x6e, 0x61, 0x62, 0x6c, 0x65, 0x64, 0x20, 0x25, 0x64, 0x00, 0x00, 0x4d, 0x41, 0x49, 0x4e, 0x00, 0x00, 0x00, 0x00, - 0x54, 0x58, 0x3a, 0x20, 0x25, 0x64, 0x2f, 0x25, 0x64, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x43, 0x4d, 0x44, - 0x33, 0x00, 0x00, 0x00, 0x00, 0x49, 0x00, 0x00, 0x00, 0x52, 0x58, 0x3a, 0x20, 0x63, 0x6d, 0x64, 0x3d, 0x30, 0x78, - 0x25, 0x30, 0x32, 0x78, 0x2c, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x6c, 0x65, 0x6e, 0x20, 0x25, 0x64, 0x2f, 0x25, 0x64, - 0x00, 0x00, 0x00, 0x72, 0x73, 0x70, 0x3d, 0x25, 0x78, 0x00, 0x00, 0x73, 0x74, 0x61, 0x72, 0x74, 0x2c, 0x20, 0x76, - 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, 0x50, 0x52, 0x4f, 0x56, 0x49, 0x53, 0x49, 0x4f, 0x4e, 0x20, 0x4f, - 0x4b, 0x00, 0x00, 0x00, 0x00, 0x4e, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x43, 0x50, 0x42, 0x3a, 0x20, 0x25, - 0x64, 0x00, 0x4c, 0x33, 0x20, 0x63, 0x6d, 0x64, 0x20, 0x25, 0x64, 0x3a, 0x20, 0x25, 0x78, 0x2c, 0x20, 0x6c, 0x65, - 0x6e, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x00, 0x4c, 0x33, 0x20, 0x61, 0x63, 0x63, 0x65, 0x73, 0x73, 0x20, 0x66, 0x61, - 0x69, 0x6c, 0x65, 0x64, 0x2c, 0x20, 0x63, 0x6d, 0x64, 0x3a, 0x20, 0x25, 0x64, 0x2c, 0x20, 0x6c, 0x65, 0x6e, 0x3a, - 0x20, 0x25, 0x64, 0x20, 0x00, 0x73, 0x65, 0x6e, 0x74, 0x00, 0x00, 0x00, 0x00, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x20, - 0x73, 0x6c, 0x65, 0x65, 0x70, 0x00, 0x77, 0x61, 0x6b, 0x65, 0x75, 0x70, 0x00, 0x00, 0x9a, 0x19, 0x10, 0x00, 0xd8, - 0x19, 0x10, 0x00, 0x04, 0x1a, 0x10, 0x00, 0x34, 0x1a, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, - 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, - 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, - 0x10, 0x00, 0x56, 0x1a, 0x10, 0x00, 0xb0, 0x1a, 0x10, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, - 0x1f, 0x00, 0x06, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x1f, 0x00, 0x06, 0x02, 0x00, 0x05, 0x01, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x06, 0x03, 0x10, 0x08, 0x00, 0x00, 0x18, 0x00, 0x00, 0x40, 0x1f, 0x00, - 0x06, 0x06, 0x10, 0x08, 0x00, 0x04, 0x18, 0x00, 0x00, 0x60, 0x1f, 0x00, 0x06, 0x04, 0x00, 0x09, 0x01, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x80, 0x06, 0x05, 0x05, 0x7f, 0x07, 0x01, 0x08, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - 0xf0, 0x01, 0x10, 0x10, 0x00, 0x04, 0x02, 0x11, 0x00, 0x44, 0x02, 0x12, 0x00, 0x84, 0x02, 0x20, 0x90, 0x01, 0x03, - 0x21, 0x80, 0x42, 0x03, 0x22, 0xf0, 0x01, 0x03, 0x30, 0x80, 0x02, 0x04, 0x31, 0x80, 0x42, 0x04, 0x40, 0x70, 0x04, - 0x11, 0x41, 0x70, 0x44, 0x11, 0x42, 0x70, 0x84, 0x11, 0x50, 0xf0, 0x01, 0x12, 0x60, 0x32, 0x04, 0x13, 0x61, 0x32, - 0x44, 0x13, 0x62, 0x32, 0x84, 0x13, 0x63, 0x32, 0xc4, 0x13, 0x70, 0x32, 0x04, 0x14, 0x71, 0x32, 0x44, 0x14, 0x80, - 0x20, 0x04, 0x15, 0x81, 0x20, 0x84, 0x15, 0x82, 0x20, 0x44, 0x15, 0x90, 0x51, 0x04, 0x16, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x0f, 0x00, 0x14, 0x04, 0x04, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x20, 0x25, 0x6c, 0x75, 0x20, 0x00, 0x00, 0x25, 0x73, 0x28, 0x25, 0x73, 0x29, - 0x3a, 0x20, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x45, 0x00, 0x00, 0x00, 0x4d, 0x53, 0x47, 0x00, 0x43, - 0x52, 0x43, 0x20, 0x72, 0x78, 0x3a, 0x20, 0x25, 0x30, 0x34, 0x78, 0x2c, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x3a, 0x20, - 0x25, 0x30, 0x34, 0x78, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x40, 0x20, 0x10, 0x00, 0x60, 0x20, 0x10, - 0x00, 0xb2, 0x20, 0x10, 0x00, 0x14, 0x21, 0x10, 0x00, 0x1e, 0x21, 0x10, 0x00, 0x4f, 0x53, 0x00, 0x00, 0x63, 0x6f, - 0x6e, 0x64, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, 0x43, 0x50, 0x42, 0x20, 0x49, 0x6e, 0x74, 0x65, 0x72, - 0x72, 0x75, 0x70, 0x74, 0x20, 0x21, 0x00, 0x43, 0x50, 0x42, 0x00, 0x57, 0x00, 0x00, 0x00, 0x46, 0x53, 0x53, 0x00, - 0x49, 0x52, 0x51, 0x00, 0x53, 0x54, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x4b, 0x44, 0x42, 0x00, 0x73, 0x74, 0x3a, - 0x20, 0x25, 0x78, 0x00, 0x00, 0x4d, 0x41, 0x44, 0x00, 0x4f, 0x54, 0x50, 0x00, 0x0c, 0x18, 0x00, 0x00, 0x20, 0x00, - 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00, 0x10, 0x18, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x05, 0x0a, 0x0a, 0x0a, 0x14, - 0x18, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x53, 0x43, 0x42, 0x00, 0x4e, 0x6f, 0x69, 0x73, 0x65, 0x5f, 0x4b, - 0x4b, 0x31, 0x5f, 0x32, 0x35, 0x35, 0x31, 0x39, 0x5f, 0x41, 0x45, 0x53, 0x47, 0x43, 0x4d, 0x5f, 0x53, 0x48, 0x41, - 0x32, 0x35, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0x40, 0x10, 0x00, 0x74, 0x46, 0x10, 0x00, 0x5e, - 0x46, 0x10, 0x00, 0x22, 0x46, 0x10, 0x00, 0x08, 0x3f, 0x10, 0x00, 0xcc, 0x46, 0x10, 0x00, 0x41, 0x4c, 0x41, 0x52, - 0x4d, 0x20, 0x43, 0x48, 0x41, 0x4e, 0x4e, 0x45, 0x4c, 0x53, 0x3a, 0x20, 0x25, 0x78, 0x20, 0x25, 0x78, 0x00, 0x00, - 0x00, 0x53, 0x43, 0x4e, 0x54, 0x52, 0x00, 0x00, 0x00, 0x53, 0x50, 0x45, 0x43, 0x54, 0x00, 0x00, 0x00, 0xc3, 0x14, - 0x13, 0x00}; +const uint8_t fw_CPU[] = { + 0xe6, 0x36, 0x5d, 0x07, 0xbe, 0xde, 0x15, 0x16, 0xb3, 0xd4, 0xf1, 0x2c, 0xea, 0x45, 0x83, 0x09, + 0xfb, 0x82, 0x15, 0x01, 0x62, 0xe1, 0x40, 0x83, 0xb4, 0x48, 0xc5, 0x33, 0xa9, 0xca, 0x41, 0x35, + 0xba, 0xa6, 0x60, 0xf7, 0xe5, 0x50, 0xe8, 0x83, 0xc8, 0x9b, 0xf5, 0xe6, 0x79, 0xb6, 0x72, 0x34, + 0xbb, 0x9a, 0x89, 0xa7, 0xd8, 0x29, 0x8b, 0xd8, 0x62, 0xe1, 0xd0, 0x85, 0x39, 0x3a, 0x11, 0x0c, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x7c, 0x58, 0x00, 0x00, 0x61, 0xcd, 0x51, 0x19, + 0x69, 0x21, 0x5c, 0xac, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x6f, 0x30, 0x40, 0x44, 0x6f, 0x30, 0x60, 0x3e, 0x6f, 0x30, 0x20, 0x3e, 0x6f, 0x30, 0xe0, 0x3d, + 0x6f, 0x30, 0xa0, 0x3d, 0x6f, 0x30, 0x60, 0x3d, 0x6f, 0x30, 0x20, 0x3d, 0x6f, 0x50, 0x40, 0x18, + 0x6f, 0x30, 0xa0, 0x3c, 0x6f, 0x30, 0x60, 0x3c, 0x6f, 0x30, 0x20, 0x3c, 0x6f, 0x30, 0xb0, 0x00, + 0x6f, 0x30, 0xa0, 0x3b, 0x6f, 0x30, 0x60, 0x3b, 0x6f, 0x30, 0x20, 0x3b, 0x6f, 0x30, 0xe0, 0x3a, + 0x6f, 0x40, 0x30, 0x7c, 0x6f, 0x30, 0x60, 0x27, 0x6f, 0x30, 0x90, 0x2d, 0x6f, 0x40, 0x90, 0x37, + 0x6f, 0x40, 0x50, 0x37, 0x6f, 0x40, 0x10, 0x37, 0x6f, 0x30, 0xe0, 0x4d, 0x6f, 0x30, 0xe0, 0x4e, + 0x6f, 0x30, 0x70, 0x53, 0x6f, 0x40, 0xd0, 0x5e, 0x6f, 0x30, 0x60, 0x4f, 0x6f, 0x20, 0xf0, 0x21, + 0x6f, 0x40, 0xd0, 0x1f, 0x6f, 0x30, 0xe0, 0x4f, 0x6f, 0x30, 0x40, 0x5c, 0x6f, 0x30, 0x40, 0x40, + 0x93, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x93, 0x01, 0x00, 0x00, 0x13, 0x02, 0x00, 0x00, + 0x93, 0x02, 0x00, 0x00, 0x13, 0x03, 0x00, 0x00, 0x93, 0x03, 0x00, 0x00, 0x13, 0x04, 0x00, 0x00, + 0x93, 0x04, 0x00, 0x00, 0x13, 0x05, 0x00, 0x00, 0x93, 0x05, 0x00, 0x00, 0x13, 0x06, 0x00, 0x00, + 0x93, 0x06, 0x00, 0x00, 0x13, 0x07, 0x00, 0x00, 0x93, 0x07, 0x00, 0x00, 0x13, 0x08, 0x00, 0x00, + 0x93, 0x08, 0x00, 0x00, 0x13, 0x09, 0x00, 0x00, 0x93, 0x09, 0x00, 0x00, 0x13, 0x0a, 0x00, 0x00, + 0x93, 0x0a, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x93, 0x0b, 0x00, 0x00, 0x13, 0x0c, 0x00, 0x00, + 0x93, 0x0c, 0x00, 0x00, 0x13, 0x0d, 0x00, 0x00, 0x93, 0x0d, 0x00, 0x00, 0x13, 0x0e, 0x00, 0x00, + 0x93, 0x0e, 0x00, 0x00, 0x13, 0x0f, 0x00, 0x00, 0x93, 0x0f, 0x00, 0x00, 0x97, 0x00, 0x00, 0x00, + 0x93, 0x80, 0x40, 0xf0, 0x73, 0x90, 0x50, 0x30, 0x93, 0x00, 0x00, 0x00, 0x17, 0x41, 0x10, 0x00, + 0x13, 0x01, 0x41, 0xcf, 0x33, 0x04, 0x01, 0x00, 0x17, 0x0d, 0x10, 0x00, 0x13, 0x0d, 0x8d, 0xee, + 0x97, 0x4d, 0x10, 0x00, 0x93, 0x8d, 0x0d, 0xce, 0x63, 0x57, 0xbd, 0x01, 0x23, 0x20, 0x0d, 0x00, + 0x11, 0x0d, 0xe3, 0x4d, 0xbd, 0xff, 0xef, 0x00, 0x70, 0x71, 0x73, 0x00, 0x50, 0x10, 0xf5, 0xbf, + 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0x07, 0xf4, + 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa2, 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa0, 0x07, 0xf4, + 0xb7, 0x37, 0x20, 0x00, 0x23, 0x8e, 0x07, 0xf2, 0x82, 0x80, 0x05, 0x67, 0x93, 0x07, 0x45, 0x00, + 0x01, 0x17, 0x01, 0x45, 0x94, 0x43, 0x99, 0xe6, 0x13, 0x05, 0x05, 0x02, 0x91, 0x07, 0xe3, 0x1b, + 0xe5, 0xfe, 0x82, 0x80, 0x81, 0x47, 0x13, 0x06, 0x00, 0x02, 0x33, 0xd7, 0xf6, 0x00, 0x05, 0x8b, + 0x09, 0xe7, 0x85, 0x07, 0x05, 0x05, 0xe3, 0x9a, 0xc7, 0xfe, 0x82, 0x80, 0x18, 0x41, 0xfd, 0x57, + 0x63, 0x02, 0xf7, 0x06, 0x13, 0x07, 0x45, 0x00, 0x81, 0x47, 0x13, 0x06, 0xf0, 0x07, 0x14, 0x43, + 0x81, 0xea, 0x85, 0x07, 0x11, 0x07, 0xe3, 0x9c, 0xc7, 0xfe, 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, + 0x01, 0x47, 0x93, 0x05, 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, 0x05, 0x8a, 0x19, 0xca, 0x93, 0x05, + 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, 0x05, 0x8a, 0x15, 0xc6, 0x05, 0x07, 0xe3, 0x1b, 0xb7, 0xfe, + 0x21, 0xa0, 0x05, 0x07, 0xe3, 0x11, 0xb7, 0xfe, 0x89, 0x07, 0x93, 0x06, 0x00, 0x08, 0x7d, 0x56, + 0xe3, 0x85, 0xd7, 0xfc, 0x85, 0x07, 0x13, 0x97, 0x27, 0x00, 0x2a, 0x97, 0x03, 0x27, 0xc7, 0xff, + 0xe3, 0x08, 0xc7, 0xfe, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x14, + 0x20, 0x00, 0x13, 0x04, 0x04, 0x00, 0x83, 0x46, 0x94, 0x07, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, + 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x77, 0x13, 0x06, 0xc6, 0x52, 0x93, 0x85, + 0x85, 0x53, 0x06, 0xc6, 0xef, 0x10, 0xd0, 0x51, 0x03, 0x45, 0x94, 0x07, 0xb2, 0x40, 0x22, 0x44, + 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x40, 0xd0, 0x21, 0xef, 0x20, 0xa0, 0x5d, + 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x00, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x40, 0x90, 0x22, + 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x05, 0x05, 0x10, 0x2a, 0x84, + 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x05, 0x54, 0x06, 0xc6, 0xef, 0x10, 0xd0, 0x54, 0x37, 0x37, + 0x20, 0x00, 0x13, 0x07, 0x07, 0xf6, 0x14, 0x43, 0x85, 0x47, 0xb3, 0x97, 0x87, 0x00, 0xb2, 0x40, + 0x22, 0x44, 0x93, 0xc7, 0xf7, 0xff, 0xf5, 0x8f, 0x1c, 0xc3, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, + 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x2a, 0x84, 0x93, 0x04, 0xa0, 0x0a, 0xef, 0x20, 0x30, 0x77, + 0x63, 0x19, 0x95, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, + 0x82, 0x80, 0x22, 0x85, 0xef, 0x20, 0xb0, 0x79, 0x22, 0x85, 0xef, 0x20, 0x50, 0x75, 0xe3, 0x03, + 0x95, 0xfe, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x05, 0x54, 0x85, 0x45, 0xef, 0x10, 0xb0, 0x4e, + 0x13, 0x05, 0x50, 0x05, 0xd1, 0xbf, 0x01, 0x11, 0x22, 0xcc, 0x2a, 0x84, 0x37, 0x35, 0x00, 0x08, + 0x06, 0xce, 0x2e, 0xc6, 0xef, 0x30, 0x50, 0x14, 0x32, 0x46, 0xa2, 0x85, 0x37, 0x35, 0x00, 0x08, + 0xef, 0x30, 0x70, 0x1b, 0x62, 0x44, 0xf2, 0x40, 0x37, 0x35, 0x00, 0x08, 0x05, 0x61, 0x6f, 0x30, + 0xf0, 0x16, 0x6d, 0x71, 0x23, 0x24, 0x81, 0x10, 0x2a, 0x84, 0x0a, 0x85, 0x23, 0x26, 0x11, 0x10, + 0xef, 0x10, 0xf0, 0x68, 0x0a, 0x85, 0x23, 0x00, 0x81, 0x00, 0xef, 0x20, 0xa0, 0x47, 0x83, 0x20, + 0xc1, 0x10, 0x03, 0x24, 0x81, 0x10, 0x51, 0x61, 0x82, 0x80, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, + 0x2e, 0xc4, 0xef, 0x20, 0xd0, 0x1b, 0xa2, 0x45, 0x32, 0x45, 0xef, 0x20, 0xf0, 0x33, 0x2a, 0xc4, + 0xef, 0x20, 0x90, 0x1c, 0xf2, 0x40, 0x22, 0x45, 0x05, 0x61, 0x82, 0x80, 0x13, 0x01, 0x01, 0xde, + 0x23, 0x2c, 0x81, 0x20, 0x2e, 0x84, 0xaa, 0x05, 0x23, 0x28, 0x21, 0x21, 0x93, 0x85, 0x05, 0x20, + 0x2a, 0x89, 0x08, 0x08, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x2a, 0x91, 0x20, 0x7d, 0x3f, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x04, 0xaa, 0x84, 0x08, 0x08, 0x09, 0x3d, 0x63, 0x00, 0x95, 0x02, + 0x22, 0x85, 0xd1, 0x3d, 0x09, 0x45, 0x83, 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, + 0x41, 0x21, 0x03, 0x29, 0x01, 0x21, 0x13, 0x01, 0x01, 0x22, 0x82, 0x80, 0x42, 0x44, 0x08, 0x08, + 0x22, 0xc6, 0x65, 0x3b, 0x09, 0x8c, 0x11, 0x46, 0x6c, 0x00, 0x4a, 0x85, 0x22, 0xc6, 0xef, 0x50, + 0x00, 0x12, 0x05, 0x45, 0xc9, 0xbf, 0x01, 0x45, 0xf9, 0xb7, 0x41, 0x11, 0x4a, 0xc0, 0x03, 0xa9, + 0x05, 0x00, 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0x2e, 0x84, 0xaa, 0x84, 0xef, 0x20, 0x30, 0x68, + 0xca, 0x85, 0x26, 0x85, 0xef, 0x20, 0x70, 0x1f, 0xa6, 0x85, 0x22, 0x85, 0xef, 0x20, 0xd0, 0x29, + 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x02, 0x1c, 0x40, 0x63, 0x93, 0x27, 0x03, 0x93, 0x07, + 0x44, 0x00, 0x7d, 0x57, 0x13, 0x04, 0x04, 0x20, 0x94, 0x43, 0x63, 0x9b, 0xe6, 0x00, 0x91, 0x07, + 0xe3, 0x9c, 0x87, 0xfe, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, + 0x13, 0x05, 0x50, 0x05, 0xc5, 0xbf, 0x13, 0x01, 0x01, 0xde, 0x23, 0x26, 0x31, 0x21, 0x93, 0x19, + 0xa5, 0x00, 0x23, 0x2a, 0x91, 0x20, 0x93, 0x84, 0x09, 0x20, 0x23, 0x2c, 0x81, 0x20, 0xa6, 0x85, + 0x2a, 0x84, 0x0a, 0x85, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x28, 0x21, 0x21, 0xfd, 0x35, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x00, 0xf5, 0x02, 0x01, 0x45, 0x83, 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, + 0x83, 0x24, 0x41, 0x21, 0x03, 0x29, 0x01, 0x21, 0x83, 0x29, 0xc1, 0x20, 0x13, 0x01, 0x01, 0x22, + 0x82, 0x80, 0x2a, 0x89, 0x0a, 0x85, 0x1d, 0x33, 0x63, 0x06, 0x25, 0x01, 0x22, 0x85, 0xe5, 0x33, + 0x09, 0x45, 0xd9, 0xbf, 0x02, 0x44, 0x0a, 0x85, 0xcd, 0x31, 0xaa, 0x87, 0xb3, 0x06, 0xa4, 0x40, + 0x0d, 0x45, 0xe3, 0x03, 0xf4, 0xfc, 0x09, 0x45, 0xe3, 0x60, 0xd4, 0xfc, 0x50, 0x00, 0x01, 0x44, + 0x13, 0x08, 0x00, 0x02, 0x13, 0x05, 0xf0, 0x07, 0x0c, 0x42, 0xb1, 0xc5, 0x01, 0x47, 0xb3, 0xd7, + 0xe5, 0x00, 0x85, 0x8b, 0x95, 0xcf, 0x85, 0x47, 0xb3, 0x97, 0xe7, 0x00, 0x93, 0xc7, 0xf7, 0xff, + 0xed, 0x8f, 0x1c, 0xc2, 0xef, 0x20, 0xb0, 0x03, 0x18, 0x04, 0x93, 0x17, 0x24, 0x00, 0xba, 0x97, + 0x83, 0xa5, 0x47, 0xe0, 0x13, 0x05, 0x14, 0x00, 0x0a, 0x05, 0x26, 0x95, 0xef, 0x20, 0x30, 0x14, + 0x2a, 0x84, 0xef, 0x20, 0x70, 0x03, 0x13, 0x05, 0x64, 0xf5, 0x13, 0x35, 0x15, 0x00, 0xad, 0xb7, + 0x05, 0x07, 0xe3, 0x1e, 0x07, 0xfb, 0x05, 0x04, 0x11, 0x06, 0xe3, 0x17, 0xa4, 0xfa, 0xfd, 0x16, + 0x8a, 0x85, 0x13, 0x85, 0x09, 0x40, 0x36, 0xc0, 0xc9, 0x35, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x14, + 0xf5, 0xf4, 0x8a, 0x85, 0x26, 0x85, 0x55, 0x3d, 0x13, 0x05, 0x65, 0xf5, 0xf9, 0xb7, 0x41, 0x11, + 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x07, 0x30, 0x0c, 0x2a, 0x84, 0x63, 0x04, 0xf5, 0x00, 0xef, 0x20, + 0x60, 0x4e, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x05, 0x67, 0x23, 0x80, 0x87, 0x00, + 0xba, 0x97, 0xf8, 0x5b, 0x19, 0xe3, 0x05, 0x47, 0xf8, 0xdb, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, + 0x82, 0x80, 0x05, 0x66, 0x37, 0x05, 0x20, 0x00, 0x41, 0x11, 0x13, 0x06, 0xc6, 0x07, 0x81, 0x45, + 0x13, 0x05, 0x05, 0x00, 0x06, 0xc6, 0xef, 0x40, 0x50, 0x7b, 0xef, 0x20, 0x00, 0x44, 0xef, 0x40, + 0xc0, 0x4e, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x20, 0x80, 0x3a, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x20, + 0xa0, 0x57, 0xef, 0x30, 0xa0, 0x00, 0xef, 0x40, 0x40, 0x1c, 0xef, 0x40, 0x40, 0x7b, 0xb2, 0x40, + 0x41, 0x01, 0x6f, 0x30, 0x20, 0x17, 0x41, 0x11, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, + 0x06, 0xc6, 0x23, 0xa4, 0xe7, 0xf4, 0xef, 0x20, 0xe0, 0x3c, 0x65, 0x37, 0x51, 0x3e, 0xef, 0x30, + 0xe0, 0x1b, 0xe1, 0x37, 0xb2, 0x40, 0x1d, 0x65, 0x13, 0x05, 0x05, 0x6c, 0x41, 0x01, 0x6f, 0x30, + 0x60, 0x23, 0x41, 0x11, 0x26, 0xc2, 0xae, 0x84, 0xb6, 0x85, 0x06, 0xc6, 0x22, 0xc4, 0x4a, 0xc0, + 0x36, 0x84, 0x32, 0x89, 0xef, 0x40, 0x00, 0x79, 0x22, 0x86, 0xca, 0x85, 0x13, 0x05, 0x00, 0x02, + 0xef, 0x40, 0x60, 0x7b, 0xef, 0x40, 0x20, 0x76, 0xef, 0x40, 0x80, 0x7b, 0x93, 0x07, 0xa0, 0x0a, + 0x13, 0x04, 0x50, 0x05, 0x63, 0x1a, 0xf5, 0x00, 0x2a, 0x84, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, + 0x00, 0x02, 0x26, 0x85, 0xef, 0x40, 0x80, 0x78, 0xb2, 0x40, 0x22, 0x85, 0x22, 0x44, 0x92, 0x44, + 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x85, 0x67, 0xc1, 0x07, 0x63, 0xee, 0xb7, 0x02, 0x41, 0x11, + 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xae, 0x84, 0x37, 0x04, 0x20, 0x00, 0x19, 0xc5, 0x2e, 0x86, + 0xaa, 0x85, 0x13, 0x05, 0x04, 0x00, 0xef, 0x40, 0xf0, 0x6b, 0x13, 0x04, 0x04, 0x00, 0x93, 0x07, + 0x30, 0xfc, 0x23, 0x00, 0xf4, 0x00, 0x85, 0x67, 0x3e, 0x94, 0x64, 0xd8, 0xb2, 0x40, 0x22, 0x44, + 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x82, 0x80, 0x13, 0x01, 0x01, 0xdd, 0x23, 0x24, 0x81, 0x22, + 0x23, 0x22, 0x91, 0x22, 0x23, 0x20, 0x21, 0x23, 0x23, 0x2e, 0x31, 0x21, 0x23, 0x2c, 0x41, 0x21, + 0x23, 0x2a, 0x51, 0x21, 0x23, 0x28, 0x61, 0x21, 0x23, 0x26, 0x71, 0x21, 0x23, 0x24, 0x81, 0x21, + 0x23, 0x26, 0x11, 0x22, 0x13, 0x04, 0x00, 0x20, 0x01, 0x49, 0x93, 0x04, 0xa0, 0x0a, 0x37, 0x3a, + 0x20, 0x00, 0x85, 0x4a, 0x37, 0x5b, 0x10, 0x00, 0xb7, 0x5b, 0x10, 0x00, 0x37, 0x5c, 0x10, 0x00, + 0xc1, 0x49, 0xa2, 0x85, 0x0a, 0x85, 0x51, 0x39, 0x63, 0x16, 0x95, 0x02, 0x0a, 0x85, 0xfd, 0x34, + 0x63, 0x1e, 0x95, 0x04, 0x13, 0x07, 0x0a, 0xf6, 0x14, 0x43, 0xb3, 0x97, 0x2a, 0x01, 0x13, 0x06, + 0x8b, 0x54, 0xd5, 0x8f, 0x93, 0x85, 0x0b, 0x54, 0xca, 0x86, 0x13, 0x05, 0x8c, 0x77, 0x1c, 0xc3, + 0xef, 0x10, 0x10, 0x08, 0x05, 0x09, 0x13, 0x04, 0x04, 0x40, 0xe3, 0x14, 0x39, 0xfd, 0x83, 0x20, + 0xc1, 0x22, 0x03, 0x24, 0x81, 0x22, 0x83, 0x24, 0x41, 0x22, 0x03, 0x29, 0x01, 0x22, 0x83, 0x29, + 0xc1, 0x21, 0x03, 0x2a, 0x81, 0x21, 0x83, 0x2a, 0x41, 0x21, 0x03, 0x2b, 0x01, 0x21, 0x83, 0x2b, + 0xc1, 0x20, 0x03, 0x2c, 0x81, 0x20, 0x13, 0x01, 0x01, 0x23, 0x82, 0x80, 0x93, 0x05, 0x04, 0x20, + 0x0a, 0x85, 0x25, 0x31, 0xe3, 0x10, 0x95, 0xfc, 0x0a, 0x85, 0x49, 0x34, 0xe3, 0x1c, 0x95, 0xfa, + 0x22, 0x85, 0xef, 0x20, 0xd0, 0x33, 0x8a, 0x85, 0x22, 0x85, 0xef, 0x20, 0x30, 0x1b, 0xa2, 0x85, + 0x0a, 0x85, 0x21, 0x31, 0xe3, 0x10, 0x95, 0xfa, 0x0a, 0x85, 0x8d, 0x34, 0xe3, 0x0c, 0x95, 0xf6, + 0x51, 0xbf, 0xb7, 0x07, 0x00, 0x80, 0x6d, 0x71, 0x37, 0x55, 0x10, 0x00, 0x23, 0x26, 0x11, 0x10, + 0x13, 0x05, 0x45, 0x55, 0x86, 0x85, 0xbe, 0x95, 0xef, 0x10, 0xf0, 0x06, 0xb7, 0x37, 0x20, 0x00, + 0x03, 0xa7, 0x47, 0xf3, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x1e, 0xf7, 0x02, 0x37, 0x15, 0x10, 0x00, + 0x13, 0x05, 0x85, 0x9f, 0xef, 0x10, 0x70, 0x7b, 0x13, 0x05, 0xc0, 0x0f, 0xef, 0x10, 0xc0, 0x74, + 0x0a, 0x85, 0xef, 0x10, 0xd0, 0x22, 0x93, 0x07, 0xf0, 0x07, 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, + 0x21, 0x00, 0x23, 0x00, 0xf1, 0x00, 0xef, 0x10, 0x20, 0x6e, 0xa3, 0x00, 0xa1, 0x00, 0x0a, 0x85, + 0xef, 0x10, 0x10, 0x7d, 0x05, 0x45, 0xef, 0x40, 0xf0, 0x03, 0xef, 0x40, 0xf0, 0x02, 0xe5, 0x33, + 0xef, 0x10, 0xb0, 0x46, 0xf5, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0x40, 0x80, 0x68, + 0x93, 0x07, 0x00, 0x08, 0x63, 0xf3, 0xa7, 0x00, 0xad, 0x3f, 0x2a, 0x84, 0x13, 0x05, 0xa0, 0x0a, + 0xef, 0x40, 0x40, 0x27, 0xb7, 0x17, 0x20, 0x00, 0xb2, 0x40, 0x23, 0xaa, 0x87, 0x06, 0x22, 0x44, + 0x13, 0x05, 0x30, 0x0c, 0x41, 0x01, 0x82, 0x80, 0x93, 0x07, 0xf0, 0x17, 0x63, 0xf5, 0xa7, 0x00, + 0x41, 0x11, 0x06, 0xc6, 0xb9, 0x37, 0x6f, 0x10, 0x10, 0x58, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, + 0x4a, 0xc0, 0x2e, 0x84, 0x06, 0xc6, 0xaa, 0x84, 0xc5, 0x37, 0x61, 0x8d, 0x13, 0x09, 0x50, 0x05, + 0x19, 0xc1, 0x13, 0x09, 0xa0, 0x0a, 0x26, 0x85, 0xc1, 0x3f, 0x69, 0x8c, 0x13, 0x05, 0xa0, 0x0a, + 0x19, 0xe0, 0x13, 0x05, 0x50, 0x05, 0x63, 0x03, 0x25, 0x01, 0x21, 0x3f, 0xb2, 0x40, 0x22, 0x44, + 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x69, 0x71, 0x08, 0x08, 0x23, 0x22, 0x91, 0x12, + 0x23, 0x20, 0x21, 0x13, 0x23, 0x2c, 0x41, 0x11, 0x37, 0x39, 0x20, 0x00, 0x23, 0x26, 0x11, 0x12, + 0x23, 0x24, 0x81, 0x12, 0x23, 0x2e, 0x31, 0x11, 0x23, 0x2a, 0x51, 0x11, 0xef, 0x10, 0x30, 0x15, + 0x91, 0x47, 0x13, 0x07, 0x89, 0xf5, 0x23, 0x08, 0xf1, 0x00, 0x1c, 0x43, 0x37, 0x1a, 0x20, 0x00, + 0xb7, 0x34, 0x20, 0x00, 0x13, 0x09, 0x89, 0xf5, 0x13, 0x0a, 0x0a, 0x00, 0x93, 0x84, 0x44, 0xf5, + 0xc5, 0xeb, 0x83, 0x27, 0x4a, 0x07, 0x23, 0xa0, 0x04, 0x00, 0x1c, 0xc3, 0x3d, 0x47, 0x63, 0x63, + 0xf7, 0x00, 0x45, 0x3d, 0xc1, 0x17, 0x09, 0x46, 0x6c, 0x00, 0x13, 0x05, 0x21, 0x01, 0x3e, 0xc6, + 0xef, 0x40, 0xf0, 0x43, 0x89, 0x47, 0xa3, 0x08, 0xf1, 0x00, 0x13, 0x04, 0xe0, 0x07, 0x93, 0x09, + 0x41, 0x01, 0x03, 0x27, 0x09, 0x00, 0x94, 0x40, 0xb3, 0x07, 0xd7, 0x40, 0x63, 0xf3, 0x87, 0x00, + 0x3e, 0x84, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x5a, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0xa2, 0x87, + 0x93, 0x85, 0xca, 0x56, 0x13, 0x06, 0xc6, 0x55, 0x13, 0x05, 0x45, 0x57, 0xef, 0x10, 0x40, 0x67, + 0x8c, 0x40, 0x83, 0x27, 0x4a, 0x07, 0x33, 0x07, 0xb4, 0x00, 0x63, 0xf8, 0xe7, 0x04, 0x8d, 0x45, + 0x13, 0x85, 0xca, 0x56, 0xef, 0x10, 0x20, 0x6d, 0x13, 0x04, 0x50, 0x05, 0xef, 0xf0, 0x5f, 0x84, + 0xef, 0x40, 0xe0, 0x14, 0xef, 0x20, 0x60, 0x0a, 0xef, 0x20, 0x60, 0x01, 0xbd, 0x31, 0x83, 0x20, + 0xc1, 0x12, 0x22, 0x85, 0x03, 0x24, 0x81, 0x12, 0x83, 0x24, 0x41, 0x12, 0x03, 0x29, 0x01, 0x12, + 0x83, 0x29, 0xc1, 0x11, 0x03, 0x2a, 0x81, 0x11, 0x83, 0x2a, 0x41, 0x11, 0x55, 0x61, 0x82, 0x80, + 0x13, 0x04, 0x00, 0x08, 0x93, 0x09, 0x21, 0x01, 0xad, 0xbf, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, + 0x07, 0x00, 0x22, 0x86, 0xbe, 0x95, 0x4e, 0x85, 0xef, 0x40, 0x70, 0x39, 0x83, 0x47, 0x11, 0x01, + 0x98, 0x40, 0x22, 0x97, 0x3e, 0x94, 0x83, 0x27, 0x09, 0x00, 0xa3, 0x08, 0x81, 0x00, 0x98, 0xc0, + 0x13, 0x04, 0x50, 0x05, 0x63, 0x17, 0xf7, 0x00, 0x89, 0x47, 0x23, 0x08, 0xf1, 0x00, 0x13, 0x04, + 0xa0, 0x0a, 0x08, 0x08, 0xef, 0x10, 0x10, 0x63, 0x59, 0xbf, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, + 0x26, 0xca, 0x4a, 0xc8, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xf3, 0xa7, 0x00, 0x5d, 0x3b, 0x0a, 0x05, + 0x05, 0x64, 0xb3, 0x04, 0x85, 0x00, 0x41, 0x04, 0x13, 0x09, 0xc1, 0x00, 0x2a, 0x94, 0x26, 0x85, + 0xef, 0x30, 0xc0, 0x0b, 0x23, 0x00, 0xa9, 0x00, 0x91, 0x04, 0x05, 0x09, 0xe3, 0x99, 0x84, 0xfe, + 0xf2, 0x40, 0x62, 0x44, 0x32, 0x45, 0xd2, 0x44, 0x42, 0x49, 0x05, 0x61, 0x82, 0x80, 0x41, 0x11, + 0x06, 0xc6, 0x8d, 0x47, 0x63, 0xf3, 0xa7, 0x00, 0xad, 0x3b, 0x89, 0x67, 0x93, 0x87, 0x07, 0xbf, + 0x0a, 0x05, 0x3e, 0x95, 0xef, 0x30, 0x80, 0x08, 0xaa, 0x87, 0x13, 0x07, 0xf0, 0x0f, 0x55, 0x45, + 0x63, 0x89, 0xe7, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x59, 0x45, 0x63, 0x94, 0xe7, 0x00, 0x13, 0x05, + 0x30, 0x0c, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x05, 0x71, 0x23, 0x2c, 0x81, 0x1c, 0x23, 0x2e, + 0x11, 0x1c, 0x23, 0x2a, 0x91, 0x1c, 0x23, 0x28, 0x21, 0x1d, 0x23, 0x26, 0x31, 0x1d, 0x23, 0x24, + 0x41, 0x1d, 0x23, 0x22, 0x51, 0x1d, 0x23, 0x20, 0x61, 0x1d, 0x23, 0x2e, 0x71, 0x1b, 0x23, 0x2c, + 0x81, 0x1b, 0x23, 0x2a, 0x91, 0x1b, 0x23, 0x28, 0xa1, 0x1b, 0x23, 0x26, 0xb1, 0x1b, 0x83, 0x46, + 0x05, 0x00, 0x93, 0x07, 0x20, 0x0a, 0x2a, 0x84, 0x63, 0x82, 0xf6, 0x02, 0x03, 0x47, 0x15, 0x00, + 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x86, 0x57, + 0x93, 0x85, 0x45, 0x55, 0x13, 0x05, 0x85, 0x77, 0xef, 0x10, 0x80, 0x4f, 0x08, 0x11, 0xef, 0x10, + 0x00, 0x75, 0x83, 0x47, 0x04, 0x00, 0x05, 0x47, 0x23, 0x10, 0xe1, 0x0a, 0xc1, 0x46, 0x63, 0x8b, + 0xd7, 0x46, 0x63, 0xee, 0xf6, 0x02, 0x91, 0x46, 0x63, 0x83, 0xd7, 0x36, 0x63, 0xe1, 0xf6, 0x02, + 0x63, 0x86, 0xe7, 0x06, 0x09, 0x47, 0x63, 0x81, 0xe7, 0x0e, 0x93, 0x07, 0xe0, 0x07, 0x23, 0x00, + 0xf1, 0x0a, 0x08, 0x11, 0xef, 0x10, 0xd0, 0x4d, 0x93, 0x07, 0x50, 0x05, 0xb1, 0xa9, 0x21, 0x47, + 0xe3, 0x95, 0xe7, 0xfe, 0x83, 0x47, 0x14, 0x00, 0xd1, 0xeb, 0xf5, 0x34, 0x15, 0xa9, 0x93, 0x06, + 0x20, 0x0a, 0x63, 0x85, 0xd7, 0x4e, 0x93, 0x06, 0x30, 0x0b, 0x63, 0x81, 0xd7, 0x48, 0x93, 0x06, + 0x00, 0x02, 0xe3, 0x94, 0xd7, 0xfc, 0x83, 0x47, 0x14, 0x00, 0x63, 0x99, 0xe7, 0x06, 0x03, 0x47, + 0x24, 0x00, 0x95, 0x47, 0x63, 0x14, 0xf7, 0x06, 0x85, 0x45, 0x61, 0x45, 0x39, 0x3b, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x08, 0xf5, 0x44, 0x13, 0x04, 0x80, 0xf8, 0x7d, 0xa0, 0x03, 0x47, 0x14, 0x00, + 0x89, 0x47, 0x63, 0x15, 0xf7, 0x04, 0x83, 0x47, 0x24, 0x00, 0x63, 0x8a, 0xe7, 0x04, 0x63, 0x6b, + 0xf7, 0x02, 0xa1, 0xe3, 0x83, 0x45, 0x34, 0x00, 0xf5, 0x47, 0x63, 0xe9, 0xb7, 0x02, 0x9e, 0x05, + 0x13, 0x06, 0x00, 0x08, 0x93, 0x85, 0x05, 0x10, 0x13, 0x05, 0x21, 0x0a, 0xef, 0x20, 0x90, 0x6f, + 0x13, 0x04, 0x00, 0x08, 0x08, 0x11, 0xa3, 0x00, 0x81, 0x0a, 0xef, 0x10, 0x70, 0x44, 0x93, 0x07, + 0xa0, 0x0a, 0xd9, 0xa6, 0x13, 0x05, 0x80, 0x1e, 0x63, 0x8d, 0xd7, 0x00, 0x13, 0x04, 0x10, 0xf8, + 0xa1, 0xa8, 0x89, 0x65, 0x13, 0x06, 0x00, 0x08, 0x93, 0x85, 0x05, 0x90, 0xf1, 0xb7, 0x13, 0x05, + 0x00, 0x1f, 0xef, 0x10, 0x50, 0x22, 0x2a, 0xce, 0x11, 0x46, 0x6c, 0x08, 0x13, 0x05, 0x21, 0x0a, + 0xef, 0x40, 0xf0, 0x17, 0x11, 0x44, 0x7d, 0xbf, 0x83, 0x44, 0x14, 0x00, 0x2d, 0x34, 0x93, 0x07, + 0x10, 0x02, 0xe3, 0x95, 0xf4, 0xfc, 0xef, 0x10, 0xd0, 0x77, 0xef, 0x20, 0xd0, 0x20, 0xef, 0x30, + 0x50, 0x40, 0xef, 0x40, 0xc0, 0x15, 0x03, 0x45, 0x24, 0x02, 0x15, 0x3d, 0x93, 0x07, 0x30, 0x0c, + 0x63, 0x0b, 0xf5, 0x02, 0x13, 0x04, 0x70, 0xf8, 0xb3, 0x06, 0x80, 0x40, 0x37, 0x56, 0x10, 0x00, + 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0xf6, 0xf6, 0x0f, 0x13, 0x06, 0x86, 0x59, + 0x93, 0x85, 0x45, 0x55, 0x13, 0x05, 0x85, 0x77, 0x23, 0x00, 0xd1, 0x0a, 0xef, 0x10, 0x40, 0x39, + 0xa3, 0x00, 0x01, 0x0a, 0xf9, 0xb5, 0x83, 0x44, 0x24, 0x02, 0xef, 0xf0, 0x9f, 0x98, 0x8d, 0x47, + 0xe3, 0xe2, 0x97, 0xfc, 0x13, 0x06, 0x10, 0x08, 0x81, 0x45, 0x68, 0x08, 0xef, 0x40, 0xf0, 0x13, + 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0x24, 0x00, 0x13, 0x05, 0xd1, 0x01, 0x23, 0x0e, 0x91, 0x00, + 0xef, 0x40, 0xf0, 0x0e, 0xef, 0x40, 0xa0, 0x0e, 0x37, 0x25, 0x00, 0x08, 0xef, 0x30, 0xc0, 0x03, + 0x81, 0x46, 0x01, 0x46, 0x93, 0x05, 0xd1, 0x03, 0x45, 0x45, 0xef, 0xf0, 0x9f, 0x9b, 0x93, 0x07, + 0xa0, 0x0a, 0xe3, 0x11, 0xf5, 0xf8, 0x81, 0x45, 0x68, 0x08, 0xef, 0x30, 0xd0, 0x36, 0x93, 0x07, + 0xa0, 0x0a, 0x2a, 0x89, 0xe3, 0x18, 0xf5, 0xf6, 0x93, 0x06, 0x00, 0x02, 0x13, 0x06, 0xd1, 0x01, + 0x93, 0x05, 0xd1, 0x05, 0x49, 0x45, 0xef, 0xf0, 0xdf, 0x98, 0xaa, 0x84, 0xe3, 0x1c, 0x25, 0xf5, + 0x85, 0x45, 0x68, 0x08, 0xef, 0x30, 0x30, 0x34, 0x2a, 0x89, 0xe3, 0x15, 0x95, 0xf4, 0x83, 0x47, + 0xc1, 0x01, 0x85, 0x46, 0x13, 0x06, 0xb1, 0x01, 0x93, 0x05, 0xd1, 0x05, 0x4d, 0x45, 0xa3, 0x0d, + 0xf1, 0x00, 0xef, 0xf0, 0x1f, 0x96, 0xaa, 0x84, 0xe3, 0x16, 0x25, 0xf3, 0x89, 0x45, 0x68, 0x08, + 0xef, 0x30, 0x70, 0x31, 0x2a, 0x89, 0xe3, 0x1f, 0x95, 0xf0, 0x81, 0x46, 0x01, 0x46, 0x93, 0x05, + 0xd1, 0x05, 0x51, 0x45, 0xef, 0xf0, 0xff, 0x93, 0xaa, 0x84, 0xe3, 0x15, 0x25, 0xf1, 0x8d, 0x45, + 0x68, 0x08, 0xef, 0x30, 0x50, 0x2f, 0x2a, 0x89, 0xe3, 0x1e, 0x95, 0xee, 0x91, 0x45, 0x68, 0x08, + 0xef, 0x30, 0x70, 0x2e, 0xaa, 0x84, 0xe3, 0x17, 0x25, 0xef, 0x95, 0x45, 0x68, 0x08, 0xef, 0x30, + 0x90, 0x2d, 0xe3, 0x11, 0x95, 0xee, 0xb7, 0x14, 0x20, 0x00, 0x13, 0x85, 0x04, 0x02, 0xef, 0x30, + 0xb0, 0x31, 0x37, 0x19, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0xd1, 0x03, 0x13, 0x05, + 0x09, 0x03, 0xef, 0x40, 0xd0, 0x00, 0x37, 0x15, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, + 0xd1, 0x07, 0x13, 0x05, 0x05, 0x05, 0xef, 0x40, 0x80, 0x7f, 0x83, 0x49, 0x24, 0x02, 0x8d, 0x47, + 0x63, 0xf3, 0x37, 0x01, 0xb9, 0x34, 0xb7, 0x5c, 0x10, 0x00, 0xef, 0x10, 0x30, 0x43, 0x01, 0x4d, + 0x93, 0x8c, 0x4c, 0x6c, 0x0d, 0x4a, 0xfd, 0x5a, 0x13, 0x0b, 0x00, 0x0f, 0xc1, 0x6b, 0x37, 0x0c, + 0x00, 0x01, 0x13, 0x17, 0x2d, 0x00, 0xb3, 0x87, 0xec, 0x00, 0x83, 0xcd, 0x07, 0x00, 0x3a, 0xc6, + 0x63, 0x81, 0x0d, 0x08, 0x80, 0x43, 0x13, 0x55, 0x44, 0x01, 0x41, 0x80, 0x75, 0x3c, 0x3d, 0x88, + 0x32, 0x47, 0x63, 0x68, 0x8a, 0x00, 0x0e, 0x04, 0x33, 0x94, 0x8a, 0x00, 0x13, 0x44, 0xf4, 0xff, + 0x61, 0x8d, 0xb3, 0x86, 0xec, 0x00, 0x83, 0xc6, 0x16, 0x00, 0x33, 0x55, 0x35, 0x01, 0x93, 0x77, + 0x15, 0x00, 0x93, 0xf6, 0x06, 0x0f, 0x63, 0x82, 0x66, 0x05, 0x93, 0x76, 0x05, 0x10, 0x99, 0xc2, + 0x93, 0xe7, 0x27, 0x00, 0xb3, 0x76, 0x75, 0x01, 0x99, 0xc2, 0x93, 0xe7, 0x47, 0x00, 0x33, 0x75, + 0x85, 0x01, 0x19, 0xc1, 0x93, 0xe7, 0x87, 0x00, 0x66, 0x97, 0x18, 0x43, 0xbd, 0x65, 0xc2, 0x07, + 0xf9, 0x8d, 0x21, 0x83, 0x3d, 0x8b, 0x22, 0x07, 0x4d, 0x8f, 0xb3, 0x65, 0xb7, 0x01, 0x6a, 0x85, + 0xdd, 0x8d, 0xef, 0x10, 0x30, 0x3b, 0x05, 0x0d, 0xad, 0xbf, 0xf9, 0xdf, 0x93, 0x07, 0xf0, 0x0f, + 0xe1, 0xbf, 0xef, 0x10, 0xd0, 0x37, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x13, 0x06, + 0x00, 0x02, 0x93, 0x05, 0x09, 0x03, 0x13, 0x05, 0x21, 0x0a, 0x23, 0xa4, 0xe7, 0xf4, 0xef, 0x40, + 0x00, 0x72, 0x41, 0x46, 0x93, 0x85, 0x04, 0x02, 0x13, 0x05, 0x21, 0x0c, 0xef, 0x40, 0x20, 0x71, + 0xef, 0x30, 0xf0, 0x76, 0x13, 0x04, 0x00, 0x03, 0xef, 0xf0, 0x2f, 0xfa, 0xa1, 0xb3, 0xb7, 0x37, + 0x20, 0x00, 0x03, 0xa7, 0x87, 0xf4, 0x93, 0x07, 0xa0, 0x0a, 0x83, 0x44, 0x14, 0x00, 0x63, 0x14, + 0xf7, 0x0e, 0x91, 0xe4, 0x13, 0x04, 0x10, 0xf8, 0xef, 0xf0, 0xef, 0xf9, 0x71, 0xbb, 0xb7, 0x39, + 0x20, 0x00, 0x83, 0xa7, 0x49, 0xf4, 0x93, 0x89, 0x49, 0xf4, 0xad, 0xcb, 0x09, 0x04, 0x37, 0x39, + 0x20, 0x00, 0x13, 0x09, 0x09, 0xf4, 0x83, 0x26, 0x09, 0x00, 0x03, 0xa7, 0x09, 0x00, 0x37, 0x56, + 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x77, 0xa6, 0x96, + 0x13, 0x06, 0xc6, 0x58, 0x93, 0x85, 0xc5, 0x56, 0xef, 0x10, 0x80, 0x11, 0x03, 0x25, 0x09, 0x00, + 0x83, 0xa7, 0x09, 0x00, 0x33, 0x87, 0xa4, 0x00, 0xe3, 0xe6, 0xe7, 0xfa, 0x85, 0x67, 0x93, 0x87, + 0x07, 0x02, 0xe3, 0xe1, 0xe7, 0xfa, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x26, 0x86, + 0x3e, 0x95, 0xa2, 0x85, 0xef, 0x40, 0xa0, 0x67, 0x83, 0x27, 0x09, 0x00, 0xbe, 0x94, 0x83, 0xa7, + 0x09, 0x00, 0x23, 0x20, 0x99, 0x00, 0xbd, 0xe3, 0x75, 0x54, 0x39, 0xbb, 0x89, 0x47, 0xe3, 0xfb, + 0x97, 0xf6, 0x03, 0x49, 0x34, 0x00, 0x83, 0x47, 0x24, 0x00, 0xf9, 0x14, 0x22, 0x09, 0x3e, 0x99, + 0x85, 0x67, 0x93, 0x06, 0xf9, 0xff, 0x13, 0x87, 0xf7, 0x00, 0x11, 0x04, 0xe3, 0x6c, 0xd7, 0xf4, + 0x37, 0x0a, 0x20, 0x00, 0x13, 0x0a, 0x0a, 0x00, 0x3e, 0x9a, 0x41, 0x09, 0x93, 0x07, 0xf0, 0x07, + 0xa3, 0x0c, 0xfa, 0x06, 0x23, 0xa0, 0x29, 0x01, 0xef, 0x10, 0xb0, 0x43, 0xef, 0x20, 0xa0, 0x6c, + 0xef, 0x30, 0x30, 0x0c, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x28, 0x2a, 0x07, 0x23, 0x2a, 0x0a, 0x06, + 0x23, 0xa0, 0x07, 0xf4, 0x2d, 0xbf, 0x13, 0x04, 0x60, 0xf8, 0x39, 0xbf, 0xe3, 0x9e, 0xf4, 0xf8, + 0x01, 0x44, 0x89, 0xb1, 0x83, 0x47, 0x14, 0x00, 0xe3, 0x9a, 0x07, 0xc4, 0xef, 0x10, 0xd0, 0x10, + 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x04, 0x05, 0xc4, 0x83, 0x20, 0xc1, 0x1d, 0x03, 0x24, 0x81, 0x1d, + 0x83, 0x24, 0x41, 0x1d, 0x03, 0x29, 0x01, 0x1d, 0x83, 0x29, 0xc1, 0x1c, 0x03, 0x2a, 0x81, 0x1c, + 0x83, 0x2a, 0x41, 0x1c, 0x03, 0x2b, 0x01, 0x1c, 0x83, 0x2b, 0xc1, 0x1b, 0x03, 0x2c, 0x81, 0x1b, + 0x83, 0x2c, 0x41, 0x1b, 0x03, 0x2d, 0x01, 0x1b, 0x83, 0x2d, 0xc1, 0x1a, 0x3e, 0x85, 0x3d, 0x61, + 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa8, 0xa7, 0xf4, 0x85, 0xbe, 0x83, 0x46, 0x14, 0x00, + 0xe3, 0x9e, 0xe6, 0xbe, 0x83, 0x47, 0x24, 0x00, 0x63, 0x8b, 0xd7, 0x02, 0x0d, 0x47, 0xe3, 0x97, + 0xe7, 0xbe, 0xa1, 0x45, 0x01, 0x45, 0xef, 0xf0, 0x5f, 0x8a, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, + 0xe3, 0x13, 0xf5, 0xb8, 0xb7, 0xb5, 0xb5, 0x61, 0x93, 0x85, 0x55, 0x49, 0x13, 0x05, 0x80, 0x1f, + 0xef, 0x10, 0x00, 0x67, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0x87, 0xf2, 0x95, 0xb7, 0xb7, 0x15, + 0x78, 0x4a, 0x93, 0x85, 0x95, 0x21, 0x13, 0x05, 0x80, 0x1f, 0xef, 0x10, 0x60, 0x65, 0xb7, 0x37, + 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xac, 0xe7, 0xf2, 0x99, 0xb7, 0xb7, 0x37, 0x20, 0x00, + 0x03, 0xa7, 0x47, 0xf3, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1f, 0xf7, 0xb2, 0x83, 0x47, 0x14, 0x00, + 0xe3, 0x96, 0x07, 0xb8, 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x0a, 0xef, 0x00, 0xd0, 0x6b, + 0x2a, 0x84, 0xe3, 0x51, 0x05, 0xb6, 0xc9, 0xbe, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, + 0x4a, 0xc8, 0x4e, 0xc6, 0x8d, 0x47, 0x63, 0xf4, 0xa7, 0x00, 0xef, 0xf0, 0x8f, 0xf6, 0x89, 0x67, + 0x2a, 0x84, 0x93, 0x87, 0x07, 0xbf, 0x0a, 0x05, 0x81, 0x45, 0x3e, 0x95, 0x13, 0x09, 0x04, 0x0e, + 0xef, 0x20, 0x10, 0x2b, 0x16, 0x09, 0x81, 0x44, 0x93, 0x09, 0x00, 0x02, 0x33, 0x05, 0x99, 0x00, + 0x81, 0x45, 0x91, 0x04, 0xef, 0x20, 0xd0, 0x29, 0xe3, 0x9a, 0x34, 0xff, 0x22, 0x85, 0xef, 0xf0, + 0x1f, 0x9b, 0x59, 0x47, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xe5, 0x00, 0x93, 0x07, 0x50, 0x05, + 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x3e, 0x85, 0x05, 0x61, 0x82, 0x80, + 0x41, 0x11, 0x05, 0x45, 0x06, 0xc6, 0xef, 0x30, 0xf0, 0x7a, 0xb2, 0x40, 0xb7, 0x37, 0x20, 0x00, + 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf4, 0x41, 0x01, 0x82, 0x80, 0x31, 0x71, 0x22, 0xdd, + 0x37, 0x34, 0x20, 0x00, 0x93, 0x07, 0x50, 0x05, 0x06, 0xdf, 0x26, 0xdb, 0x4a, 0xd9, 0x56, 0xd3, + 0x5e, 0xcf, 0x4e, 0xd7, 0x52, 0xd5, 0x5a, 0xd1, 0x62, 0xcd, 0x66, 0xcb, 0x6a, 0xc9, 0x6e, 0xc7, + 0x37, 0x39, 0x20, 0x00, 0xb7, 0x34, 0x20, 0x00, 0xb7, 0x3b, 0x20, 0x00, 0x13, 0x04, 0x44, 0xf3, + 0x23, 0x26, 0xf9, 0xf4, 0x23, 0xac, 0xf4, 0xf2, 0x23, 0xa8, 0xfb, 0xf4, 0x1c, 0xc0, 0xef, 0x10, + 0xa0, 0x32, 0xef, 0x10, 0x00, 0x4b, 0x13, 0x07, 0xc9, 0xf4, 0x3a, 0xc8, 0x13, 0x87, 0x84, 0xf3, + 0x3a, 0xca, 0x13, 0x87, 0x0b, 0xf5, 0x93, 0x07, 0xa0, 0x0a, 0x3a, 0xc6, 0xb7, 0x5a, 0x10, 0x00, + 0x85, 0x45, 0x63, 0x0a, 0xf5, 0x00, 0x13, 0x85, 0x4a, 0x55, 0xef, 0x00, 0xd0, 0x70, 0xef, 0x10, + 0xc0, 0x44, 0xef, 0xf0, 0x0f, 0xe8, 0x41, 0x45, 0xef, 0xf0, 0x2f, 0xf3, 0x08, 0xc0, 0xb7, 0x07, + 0x01, 0x02, 0x80, 0x57, 0x98, 0x5b, 0x29, 0x45, 0x59, 0x8c, 0x98, 0x5f, 0x59, 0x8c, 0x13, 0x77, + 0xf4, 0x87, 0x98, 0xd7, 0x98, 0xdb, 0x98, 0xdf, 0xd8, 0x43, 0x13, 0x67, 0x87, 0x00, 0xd8, 0xc3, + 0xef, 0x10, 0x40, 0x2d, 0xef, 0x30, 0x10, 0x27, 0x13, 0x75, 0x05, 0x78, 0x11, 0xc5, 0x13, 0x05, + 0x00, 0x78, 0x81, 0x45, 0xef, 0x30, 0x70, 0x1f, 0xb7, 0x07, 0x01, 0x02, 0x80, 0xd7, 0x80, 0xdb, + 0x37, 0x15, 0x10, 0x00, 0x80, 0xdf, 0x13, 0x05, 0x85, 0x9f, 0xef, 0x10, 0x00, 0x61, 0x13, 0x05, + 0x00, 0x1f, 0xef, 0x10, 0x40, 0x45, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x59, 0x10, 0x00, 0xaa, 0x86, + 0x13, 0x06, 0x06, 0x5a, 0x93, 0x85, 0x4a, 0x55, 0x13, 0x85, 0x89, 0x77, 0xef, 0x00, 0x50, 0x61, + 0xef, 0x30, 0xf0, 0x22, 0x93, 0x07, 0x50, 0x05, 0x63, 0x1e, 0xf5, 0x00, 0x37, 0x56, 0x10, 0x00, + 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x06, 0x5b, 0x93, 0x85, 0x4a, 0x55, 0x13, 0x05, 0x45, 0x57, + 0xef, 0x00, 0x10, 0x5f, 0xef, 0x20, 0x20, 0x20, 0x51, 0x45, 0xef, 0x10, 0xc0, 0x40, 0x1d, 0x89, + 0xef, 0x20, 0x40, 0x20, 0xef, 0x10, 0x30, 0x74, 0xef, 0x20, 0xa0, 0x76, 0xef, 0x20, 0x40, 0x7b, + 0xef, 0x20, 0x90, 0x2a, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0x10, 0x2b, 0x6c, 0x10, 0x11, 0x46, + 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0x30, 0x32, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0x10, 0x2e, + 0x32, 0x55, 0xef, 0x20, 0x50, 0x1f, 0x09, 0x65, 0x13, 0x05, 0x05, 0x98, 0xef, 0x20, 0x50, 0x03, + 0xfd, 0x57, 0x8d, 0x45, 0x63, 0x12, 0xf5, 0x02, 0x01, 0x44, 0x13, 0x09, 0x00, 0x18, 0x22, 0x85, + 0xef, 0xf0, 0x8f, 0xe2, 0xaa, 0x84, 0x22, 0x85, 0xef, 0xf0, 0x2f, 0xfb, 0x93, 0x47, 0xf5, 0xff, + 0x33, 0xf5, 0x97, 0x00, 0x19, 0xc5, 0x89, 0x45, 0x13, 0x85, 0x4a, 0x55, 0xef, 0x00, 0xb0, 0x5e, + 0xcd, 0xb5, 0x11, 0x04, 0xe3, 0x1d, 0x24, 0xfd, 0x37, 0x55, 0x10, 0x00, 0xb7, 0x37, 0x20, 0x00, + 0x13, 0x07, 0x50, 0x05, 0x13, 0x05, 0x45, 0x72, 0x23, 0xa4, 0xe7, 0xf4, 0xef, 0x10, 0x30, 0x10, + 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x40, 0x05, 0x93, 0x85, 0x05, 0x67, 0x68, 0x10, 0xef, 0x40, + 0x00, 0x2d, 0x60, 0x10, 0x48, 0x40, 0x01, 0xc5, 0xef, 0x20, 0x80, 0x7c, 0x48, 0xc0, 0x31, 0x04, + 0x1c, 0x01, 0xe3, 0x99, 0x87, 0xfe, 0x37, 0x55, 0x10, 0x00, 0x1d, 0x46, 0x6c, 0x10, 0x13, 0x05, + 0x05, 0x73, 0xef, 0x20, 0x00, 0x36, 0xef, 0x20, 0x40, 0x4c, 0xef, 0xf0, 0xef, 0xc1, 0x05, 0x45, + 0xef, 0x10, 0xa0, 0x77, 0xef, 0x30, 0xa0, 0x50, 0xef, 0x30, 0xf0, 0x29, 0x01, 0x45, 0xef, 0x30, + 0x70, 0x59, 0x37, 0x0a, 0x20, 0x00, 0x05, 0x6c, 0x93, 0x07, 0x0a, 0x00, 0xb7, 0x14, 0x20, 0x00, + 0x33, 0x8b, 0x87, 0x01, 0x93, 0x84, 0xc4, 0x07, 0xef, 0x10, 0x80, 0x5d, 0xb7, 0x37, 0x20, 0x00, + 0x83, 0xa7, 0x47, 0xf4, 0x63, 0x81, 0x07, 0x10, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0x07, 0xf4, + 0x63, 0x9b, 0xe7, 0x0e, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xc7, 0xc7, 0xf3, 0x93, 0x87, 0xc7, 0xf3, + 0x3e, 0xcc, 0xe3, 0x1e, 0x07, 0x2e, 0x03, 0x26, 0x0b, 0x07, 0x93, 0x07, 0xf0, 0x07, 0x37, 0x14, + 0x20, 0x00, 0xa3, 0x0c, 0xfb, 0x06, 0xc1, 0x4c, 0x13, 0x0d, 0x0a, 0x00, 0x13, 0x04, 0x04, 0x00, + 0x63, 0xfd, 0xcc, 0x0a, 0x13, 0x09, 0x06, 0xff, 0xef, 0x10, 0x40, 0x67, 0x01, 0x45, 0xef, 0x30, + 0x60, 0x54, 0x4a, 0x86, 0x63, 0xf3, 0x2c, 0x01, 0x41, 0x46, 0x93, 0x05, 0x0a, 0x00, 0x68, 0x10, + 0xef, 0x30, 0xa0, 0x56, 0xef, 0x10, 0xa0, 0x6c, 0xb7, 0x57, 0x10, 0x00, 0x23, 0x0c, 0xa4, 0x06, + 0x93, 0x87, 0x47, 0x6c, 0x03, 0xc7, 0x07, 0x00, 0x63, 0x10, 0x07, 0x14, 0x03, 0x29, 0x04, 0x07, + 0xc1, 0x4b, 0x63, 0xf5, 0x2b, 0x07, 0x01, 0x45, 0xef, 0x30, 0xc0, 0x50, 0x41, 0x19, 0x4a, 0x86, + 0x93, 0x05, 0x0a, 0x00, 0x13, 0x05, 0x0a, 0x00, 0xef, 0x30, 0x20, 0x53, 0xb7, 0x1c, 0x20, 0x00, + 0x13, 0x85, 0x0c, 0x02, 0xef, 0x30, 0xe0, 0x6f, 0xef, 0x30, 0xc0, 0x74, 0x37, 0x56, 0x10, 0x00, + 0xb7, 0x5d, 0x10, 0x00, 0xaa, 0x86, 0x13, 0x06, 0x06, 0x5c, 0x93, 0x85, 0x8d, 0x53, 0x13, 0x85, + 0x89, 0x77, 0xef, 0x00, 0xf0, 0x41, 0x93, 0x85, 0x0c, 0x02, 0x41, 0x46, 0x33, 0x05, 0x2d, 0x01, + 0xef, 0x00, 0xf0, 0x30, 0xaa, 0x8c, 0x63, 0x0f, 0x05, 0x0e, 0x89, 0x45, 0x13, 0x85, 0x8d, 0x53, + 0xef, 0x00, 0x70, 0x47, 0x93, 0x07, 0xb0, 0x07, 0xa3, 0x0c, 0xf4, 0x06, 0x37, 0x55, 0x10, 0x00, + 0x91, 0x45, 0x13, 0x05, 0xc5, 0x56, 0xef, 0x00, 0x10, 0x46, 0xef, 0xe0, 0x1f, 0xea, 0xef, 0xe0, + 0x5f, 0xfa, 0xef, 0xf0, 0x4f, 0xa2, 0xef, 0x10, 0x00, 0x4b, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, + 0x63, 0x1d, 0xf5, 0x08, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xc7, 0xc7, 0xf3, 0xd9, 0xe7, 0xef, 0x00, + 0xd0, 0x7a, 0xe3, 0x16, 0x85, 0x18, 0xd2, 0x47, 0x9c, 0x43, 0x63, 0x9a, 0xa7, 0x00, 0x13, 0x04, + 0xa0, 0x0a, 0xef, 0x30, 0xf0, 0x3a, 0xe3, 0x1e, 0x85, 0xfe, 0xef, 0x10, 0x20, 0x10, 0xb2, 0x47, + 0x98, 0x43, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1e, 0xf7, 0x14, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, + 0x46, 0x61, 0x93, 0x85, 0x4a, 0x55, 0x13, 0x85, 0x89, 0x77, 0xef, 0x00, 0x70, 0x38, 0xef, 0xf0, + 0x8f, 0x9c, 0x37, 0x25, 0x00, 0x08, 0xef, 0x20, 0x70, 0x0a, 0xef, 0xf0, 0x0f, 0x9a, 0xef, 0x20, + 0xa0, 0x59, 0xef, 0x10, 0x10, 0x0f, 0xef, 0x20, 0x50, 0x23, 0xef, 0xe0, 0xbf, 0xe5, 0x32, 0x47, + 0x37, 0x56, 0x10, 0x00, 0x93, 0x07, 0x50, 0x05, 0x13, 0x06, 0x06, 0x62, 0x93, 0x85, 0x4a, 0x55, + 0x13, 0x85, 0x89, 0x77, 0x1c, 0xc3, 0xef, 0x00, 0xb0, 0x34, 0xef, 0x20, 0x30, 0x23, 0xef, 0x10, + 0x50, 0x3b, 0xef, 0x20, 0x20, 0x5b, 0xef, 0x30, 0x90, 0x08, 0xc2, 0x47, 0x98, 0x43, 0x93, 0x07, + 0x50, 0x05, 0xe3, 0x03, 0xf7, 0xe4, 0x71, 0xb9, 0x63, 0x1c, 0xe5, 0x00, 0x83, 0xc7, 0x17, 0x00, + 0xbd, 0x8b, 0xe3, 0x8d, 0x07, 0xea, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0xa0, 0x60, 0x7d, 0xb5, + 0x91, 0x07, 0x4d, 0xb5, 0x03, 0x29, 0x04, 0x07, 0xe3, 0xef, 0x2b, 0x0d, 0x37, 0x55, 0x10, 0x00, + 0x89, 0x45, 0x13, 0x05, 0xc5, 0x56, 0xef, 0x00, 0x10, 0x37, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, + 0xc5, 0x56, 0x95, 0x45, 0xef, 0x00, 0x30, 0x36, 0x13, 0x05, 0xf0, 0x07, 0x09, 0xb7, 0x37, 0x37, + 0x20, 0x00, 0x13, 0x07, 0xc7, 0xf5, 0x14, 0x43, 0xb7, 0x55, 0x10, 0x00, 0xde, 0x87, 0x13, 0x86, + 0x16, 0x00, 0x10, 0xc3, 0x03, 0x47, 0x84, 0x07, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0x06, 0x5d, + 0x93, 0x85, 0xc5, 0x56, 0x13, 0x85, 0x89, 0x77, 0xef, 0x00, 0x90, 0x2b, 0x03, 0x47, 0x84, 0x07, + 0x93, 0x06, 0x20, 0x04, 0x63, 0x07, 0xd7, 0x4c, 0x63, 0xeb, 0xe6, 0x18, 0x93, 0x06, 0x10, 0x02, + 0x63, 0x0f, 0xd7, 0x3c, 0x63, 0xe3, 0xe6, 0x08, 0xc5, 0x46, 0x63, 0x04, 0xd7, 0x32, 0x63, 0xe9, + 0xe6, 0x02, 0x85, 0x46, 0x63, 0x09, 0xd7, 0x24, 0xc1, 0x46, 0x63, 0x02, 0xd7, 0x26, 0x89, 0x4c, + 0xe5, 0xac, 0x13, 0x07, 0x07, 0xfa, 0x13, 0x77, 0xf7, 0x0f, 0xc5, 0x46, 0xe3, 0xe9, 0xe6, 0xfe, + 0xb7, 0x56, 0x10, 0x00, 0x0a, 0x07, 0x93, 0x86, 0x86, 0x62, 0x36, 0x97, 0x18, 0x43, 0x02, 0x87, + 0xc9, 0x46, 0x63, 0x0e, 0xd7, 0x34, 0x93, 0x06, 0x00, 0x02, 0xe3, 0x1a, 0xd7, 0xfc, 0x21, 0x47, + 0x93, 0x0c, 0x00, 0x08, 0x63, 0x92, 0xeb, 0x2c, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x94, + 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x80, 0x63, 0x9e, 0x07, 0x4a, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xea, + 0x87, 0x4a, 0x22, 0x85, 0xef, 0x10, 0x50, 0x09, 0xfd, 0x57, 0x63, 0x14, 0xf5, 0x4a, 0x83, 0x25, + 0x4d, 0x00, 0x22, 0x85, 0xef, 0x10, 0x90, 0x11, 0x81, 0xae, 0x93, 0x06, 0x10, 0x03, 0x63, 0x08, + 0xd7, 0x38, 0x63, 0xec, 0xe6, 0x08, 0x93, 0x06, 0x20, 0x02, 0x63, 0x09, 0xd7, 0x36, 0x93, 0x06, + 0x00, 0x03, 0xe3, 0x1e, 0xd7, 0xf6, 0x11, 0x47, 0x93, 0x0c, 0x00, 0x08, 0x63, 0x96, 0xeb, 0x26, + 0x03, 0x27, 0x0d, 0x00, 0x21, 0x83, 0x93, 0x16, 0x07, 0x01, 0x0d, 0x8b, 0xc1, 0x82, 0x63, 0x12, + 0x07, 0x46, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xee, 0xd7, 0x44, 0x83, 0x47, 0x3d, 0x00, 0x7d, 0x47, + 0x63, 0x69, 0xf7, 0x44, 0x13, 0xd4, 0x37, 0x00, 0x36, 0x94, 0x0a, 0x04, 0x62, 0x94, 0x93, 0xfd, + 0x77, 0x00, 0x22, 0x85, 0x05, 0x49, 0xef, 0x20, 0x60, 0x4c, 0x33, 0x19, 0xb9, 0x01, 0xb3, 0x77, + 0xa9, 0x00, 0xaa, 0x8c, 0x63, 0x80, 0x07, 0x22, 0x8a, 0x0d, 0xbd, 0x45, 0xb3, 0x95, 0xb5, 0x01, + 0x93, 0xc5, 0xf5, 0xff, 0x22, 0x85, 0xef, 0x20, 0xa0, 0x4e, 0x22, 0x85, 0x13, 0x49, 0xf9, 0xff, + 0xef, 0x20, 0xc0, 0x49, 0x33, 0x79, 0x99, 0x01, 0x63, 0x0e, 0x25, 0x1f, 0x09, 0x65, 0x81, 0x45, + 0x13, 0x05, 0x05, 0x98, 0xef, 0x20, 0xc0, 0x4c, 0x75, 0xaa, 0x93, 0x06, 0x00, 0x04, 0x63, 0x0d, + 0xd7, 0x30, 0x93, 0x06, 0x10, 0x04, 0xe3, 0x14, 0xd7, 0xee, 0x0d, 0x47, 0x63, 0x90, 0xeb, 0x72, + 0x83, 0x27, 0x0d, 0x00, 0x13, 0x07, 0xf0, 0x1f, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, 0x63, 0x6a, + 0xf7, 0x3c, 0xef, 0x10, 0xf0, 0x48, 0xef, 0x20, 0xe0, 0x75, 0x83, 0x27, 0x0d, 0x00, 0x91, 0x65, + 0x93, 0x85, 0x05, 0x20, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, 0xa6, 0x07, 0x37, 0x15, 0x20, 0x00, + 0xbe, 0x95, 0x13, 0x05, 0x05, 0x08, 0xef, 0x10, 0xd0, 0x0a, 0x2a, 0x84, 0xef, 0x20, 0xa0, 0x75, + 0x93, 0x07, 0xb0, 0x1d, 0xe3, 0xe7, 0x87, 0xa8, 0x93, 0x05, 0x44, 0x00, 0x39, 0xa4, 0x93, 0x06, + 0x10, 0x07, 0x63, 0xe9, 0xe6, 0x02, 0x93, 0x06, 0xf0, 0x05, 0xe3, 0xe4, 0xe6, 0xe8, 0x93, 0x06, + 0x00, 0x05, 0xe3, 0x1e, 0xd7, 0xe6, 0x09, 0x47, 0x93, 0x0c, 0x00, 0x08, 0x63, 0x96, 0xeb, 0x16, + 0x03, 0x44, 0x1d, 0x00, 0x37, 0x15, 0x20, 0x00, 0x13, 0x05, 0x05, 0x08, 0xa2, 0x85, 0xef, 0xe0, + 0x9f, 0xc7, 0xd9, 0xb7, 0x93, 0x06, 0x20, 0x08, 0x63, 0x09, 0xd7, 0x64, 0x63, 0xed, 0xe6, 0x04, + 0x93, 0x06, 0x00, 0x08, 0x63, 0x00, 0xd7, 0x5e, 0x93, 0x06, 0x10, 0x08, 0xe3, 0x11, 0xd7, 0xe4, + 0x0d, 0x47, 0x93, 0x0c, 0x00, 0x08, 0x63, 0x99, 0xeb, 0x12, 0x03, 0x45, 0x1d, 0x00, 0x3d, 0x47, + 0x81, 0x47, 0x63, 0x6e, 0xa7, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x89, 0x47, + 0x33, 0x57, 0xa7, 0x00, 0x05, 0x8b, 0x01, 0xc7, 0xef, 0xe0, 0xff, 0xd6, 0xaa, 0x87, 0xfd, 0x17, + 0x09, 0x47, 0x63, 0x68, 0xf7, 0x30, 0x37, 0x65, 0x10, 0x00, 0x13, 0x05, 0x85, 0x87, 0xaa, 0x97, + 0x83, 0xcc, 0x07, 0x00, 0xd5, 0xa8, 0x93, 0x06, 0x00, 0x09, 0xe3, 0x1a, 0xd7, 0xde, 0x13, 0x07, + 0x40, 0x02, 0x93, 0x0c, 0x00, 0x08, 0x63, 0x91, 0xeb, 0x0e, 0xef, 0x20, 0x20, 0x01, 0xef, 0x20, + 0x60, 0x67, 0xef, 0x20, 0xa0, 0x01, 0x2a, 0x89, 0xef, 0x20, 0xc0, 0x00, 0xef, 0x20, 0xa0, 0x68, + 0x13, 0x07, 0xa0, 0x0a, 0x63, 0x17, 0xe9, 0x2c, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0x80, 0x33, + 0x23, 0x2a, 0x74, 0x07, 0x45, 0xa8, 0x13, 0x07, 0x1c, 0x00, 0x93, 0x0c, 0x00, 0x08, 0x63, 0x65, + 0x77, 0x0b, 0xde, 0x85, 0x13, 0x05, 0x0a, 0x00, 0xef, 0xe0, 0xff, 0xee, 0x61, 0xa8, 0x13, 0x07, + 0x40, 0x02, 0x63, 0x9d, 0xeb, 0x5c, 0x03, 0x25, 0x0d, 0x00, 0x0d, 0x44, 0x21, 0x81, 0x42, 0x05, + 0x41, 0x81, 0x63, 0x68, 0xa4, 0x28, 0xef, 0xf0, 0x8f, 0xa7, 0xd5, 0x47, 0x63, 0x13, 0xf5, 0x28, + 0x03, 0x29, 0x0d, 0x00, 0x13, 0x59, 0x89, 0x00, 0x42, 0x09, 0x13, 0x59, 0x09, 0x01, 0xe3, 0x62, + 0x24, 0x97, 0x13, 0x04, 0x09, 0x0e, 0x16, 0x04, 0x91, 0x4c, 0x71, 0x14, 0x93, 0x0b, 0xa0, 0x0a, + 0x93, 0x0d, 0x40, 0x02, 0xb3, 0x05, 0x9d, 0x01, 0x11, 0x46, 0x68, 0x10, 0xef, 0x30, 0x30, 0x56, + 0xb2, 0x55, 0x33, 0x05, 0x94, 0x01, 0xef, 0x20, 0xc0, 0x36, 0x63, 0x07, 0x75, 0x01, 0x4a, 0x85, + 0xef, 0xf0, 0x9f, 0x83, 0xdd, 0x4c, 0x0d, 0xa8, 0x91, 0x0c, 0xe3, 0x9d, 0xbc, 0xfd, 0x89, 0x67, + 0x93, 0x87, 0x07, 0xbf, 0x13, 0x15, 0x29, 0x00, 0xb7, 0xf5, 0xf0, 0xf0, 0x3e, 0x95, 0x93, 0x85, + 0x05, 0x0f, 0xef, 0x20, 0xe0, 0x2e, 0x4a, 0x85, 0xef, 0xf0, 0x6f, 0xa0, 0x93, 0x07, 0x30, 0x0c, + 0xe3, 0x1a, 0xf5, 0xfc, 0x93, 0x0c, 0x30, 0x0c, 0x13, 0x06, 0x0c, 0x01, 0x81, 0x45, 0x26, 0x85, + 0xef, 0x30, 0xb0, 0x54, 0x93, 0x07, 0x00, 0x08, 0xe3, 0x81, 0xfc, 0xc8, 0x13, 0xf5, 0xfc, 0x0f, + 0x4d, 0xa3, 0x0d, 0x47, 0x63, 0x94, 0xeb, 0x52, 0x03, 0x25, 0x0d, 0x00, 0x0d, 0x44, 0x21, 0x81, + 0x42, 0x05, 0x41, 0x81, 0x63, 0x6f, 0xa4, 0x1c, 0xef, 0xf0, 0x6f, 0x9c, 0x93, 0x07, 0x30, 0x0c, + 0x63, 0x04, 0xf5, 0x00, 0xaa, 0x8c, 0xc9, 0xb7, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0xc2, 0x07, + 0xc1, 0x83, 0xe3, 0x68, 0xf4, 0x8a, 0x93, 0x87, 0x07, 0x0e, 0x13, 0x94, 0x57, 0x00, 0x13, 0x09, + 0x00, 0x02, 0x33, 0x85, 0x8c, 0x00, 0xef, 0x20, 0xa0, 0x1b, 0xb7, 0x17, 0x20, 0x00, 0x93, 0x87, + 0x07, 0x08, 0x2a, 0xd6, 0x11, 0x46, 0x33, 0x85, 0x97, 0x01, 0x6c, 0x10, 0x91, 0x0c, 0xef, 0x30, + 0x10, 0x4a, 0xe3, 0x90, 0x2c, 0xff, 0x93, 0x05, 0x40, 0x02, 0x26, 0x85, 0xf1, 0xbd, 0x0d, 0x47, + 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x9a, 0xeb, 0xf6, 0x03, 0x25, 0x0d, 0x00, 0x21, 0x81, 0x42, 0x05, + 0x41, 0x81, 0x63, 0xe8, 0xab, 0x16, 0xef, 0xf0, 0x8f, 0x95, 0xd5, 0x47, 0x63, 0x03, 0xf5, 0x16, + 0xd9, 0x47, 0x93, 0x0c, 0x30, 0x0c, 0xe3, 0x09, 0xf5, 0xf4, 0x03, 0x25, 0x0d, 0x00, 0x21, 0x81, + 0x42, 0x05, 0x41, 0x81, 0xef, 0xf0, 0x4f, 0xf4, 0x93, 0x07, 0xa0, 0x0a, 0x15, 0xbf, 0x0d, 0x47, + 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x9a, 0xeb, 0xf2, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, + 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x81, 0x63, 0x96, 0x07, 0x12, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe2, + 0xa7, 0x12, 0xef, 0x10, 0x60, 0x50, 0xc8, 0xc0, 0xa1, 0x45, 0x41, 0xbf, 0x05, 0x47, 0x93, 0x0c, + 0x00, 0x08, 0xe3, 0x93, 0xeb, 0xf0, 0x01, 0x45, 0xef, 0x10, 0x70, 0x19, 0xe5, 0xbd, 0x0d, 0x47, + 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x9a, 0xeb, 0xee, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, + 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x81, 0x63, 0x96, 0x07, 0x0e, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe2, + 0xa7, 0x0e, 0xef, 0xf0, 0x8f, 0x88, 0xc1, 0xb7, 0x93, 0x07, 0xb9, 0xfe, 0x13, 0x07, 0xa0, 0x1d, + 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x62, 0xf7, 0xec, 0x03, 0x25, 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, + 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0xee, 0xa7, 0x0a, 0x11, 0x64, 0x26, 0x05, 0x13, 0x04, + 0x04, 0x20, 0x22, 0x95, 0xef, 0x10, 0xb0, 0x0f, 0x93, 0x07, 0xa0, 0x0a, 0xaa, 0x8d, 0xc1, 0x4c, + 0xe3, 0x1c, 0xf5, 0xe8, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0xff, 0x9a, 0xef, 0x20, 0x80, 0x42, + 0x83, 0x27, 0x0d, 0x00, 0xb7, 0x05, 0x20, 0x00, 0x74, 0x10, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, + 0xa6, 0x07, 0x33, 0x85, 0x87, 0x00, 0x13, 0x06, 0xc9, 0xfe, 0x93, 0x85, 0x45, 0x00, 0xef, 0x10, + 0x80, 0x7f, 0x2a, 0x84, 0x93, 0x0c, 0x30, 0x0c, 0xef, 0x20, 0xe0, 0x41, 0xe3, 0x14, 0xb4, 0xe3, + 0xa1, 0xbd, 0x0d, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x98, 0xeb, 0xe4, 0x03, 0x25, 0x0d, 0x00, + 0x93, 0x07, 0xf0, 0x1f, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0xe4, 0xa7, 0x04, 0x91, 0x67, + 0x26, 0x05, 0x93, 0x87, 0x07, 0x20, 0x3e, 0x95, 0x05, 0xbf, 0x11, 0x47, 0x93, 0x0c, 0x00, 0x08, + 0xe3, 0x94, 0xeb, 0xe2, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0xff, 0x93, 0x68, 0x10, 0xef, 0x10, + 0x80, 0x79, 0xef, 0x30, 0xc0, 0x32, 0xef, 0x20, 0xe0, 0x3a, 0x91, 0x45, 0x13, 0x05, 0x00, 0x06, + 0xef, 0x30, 0x00, 0x47, 0x2a, 0x84, 0xef, 0x20, 0x00, 0x3c, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x0b, + 0xf4, 0xde, 0x93, 0x0c, 0xc0, 0x03, 0xcd, 0xbb, 0x13, 0x07, 0x00, 0x03, 0x93, 0x0c, 0x00, 0x08, + 0xe3, 0x94, 0xeb, 0xde, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0xff, 0x8f, 0x68, 0x10, 0xef, 0x10, + 0x80, 0x75, 0xef, 0x30, 0xc0, 0x2e, 0xef, 0x20, 0xe0, 0x36, 0x93, 0x05, 0x00, 0x03, 0x13, 0x05, + 0x10, 0x06, 0x7d, 0xbf, 0x0d, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x9f, 0xeb, 0xda, 0xef, 0x30, + 0x00, 0x2d, 0xef, 0x20, 0x20, 0x35, 0x8d, 0x45, 0x13, 0x05, 0x20, 0x06, 0xef, 0x30, 0x40, 0x41, + 0x2a, 0x84, 0xef, 0x20, 0x40, 0x36, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x14, 0xf4, 0xfa, 0xef, 0xe0, + 0x9f, 0xd8, 0xc9, 0xbb, 0x0d, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x97, 0xeb, 0xd8, 0xef, 0x30, + 0x00, 0x2a, 0x8d, 0x45, 0x13, 0x05, 0x30, 0x06, 0xef, 0x30, 0x80, 0x3e, 0x93, 0x07, 0xa0, 0x0a, + 0xe3, 0x11, 0xf5, 0xf8, 0x85, 0xbb, 0x13, 0x07, 0x00, 0x03, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x95, + 0xeb, 0xd6, 0xef, 0x30, 0xc0, 0x27, 0xef, 0x20, 0xf0, 0x7f, 0xb7, 0x15, 0x20, 0x00, 0x2a, 0xd6, + 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, 0xef, 0x30, 0xa0, 0x31, + 0x11, 0x46, 0x6c, 0x10, 0x13, 0x05, 0x00, 0x0c, 0xef, 0x30, 0xe0, 0x30, 0xef, 0x20, 0x80, 0x2d, + 0x93, 0x05, 0x40, 0x02, 0x13, 0x05, 0x00, 0x07, 0xef, 0x30, 0x80, 0x39, 0x2a, 0x84, 0xef, 0x20, + 0x80, 0x2e, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x16, 0xf4, 0xf2, 0xef, 0xe0, 0xdf, 0xd0, 0x99, 0xbb, + 0x3d, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x79, 0x77, 0xd1, 0xef, 0x30, 0x40, 0x22, 0xef, 0x20, + 0x70, 0x7a, 0xaa, 0x8c, 0x01, 0x45, 0xef, 0x20, 0xf0, 0x53, 0x41, 0x46, 0x93, 0x05, 0x0a, 0x00, + 0x01, 0x45, 0xef, 0x20, 0x90, 0x56, 0xef, 0x20, 0xe0, 0x28, 0xb7, 0x15, 0x20, 0x00, 0x13, 0x06, + 0x00, 0x02, 0x93, 0x85, 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, 0x66, 0xd6, 0xef, 0x30, 0xa0, 0x2a, + 0x11, 0x46, 0x6c, 0x10, 0x13, 0x05, 0x00, 0x0c, 0xef, 0x30, 0xe0, 0x29, 0x85, 0x45, 0x13, 0x05, + 0x10, 0x04, 0xef, 0x30, 0xe0, 0x32, 0x93, 0x07, 0xa0, 0x0a, 0xaa, 0x8c, 0x63, 0x19, 0xf5, 0x00, + 0x81, 0x45, 0x13, 0x05, 0x20, 0x04, 0xef, 0x30, 0xa0, 0x31, 0x63, 0x05, 0x95, 0x01, 0xef, 0x20, + 0x80, 0x26, 0x45, 0xbd, 0xef, 0x20, 0x20, 0x26, 0x37, 0x07, 0x20, 0x00, 0x93, 0x0d, 0x09, 0xfe, + 0xee, 0x8c, 0x13, 0x0d, 0x07, 0x01, 0xba, 0x8b, 0x13, 0x07, 0x00, 0x09, 0x63, 0x62, 0x97, 0x09, + 0xea, 0x85, 0x66, 0x86, 0x01, 0x45, 0xef, 0x20, 0x50, 0x4f, 0xe6, 0x85, 0x13, 0x05, 0x40, 0x04, + 0xef, 0x30, 0x00, 0x2e, 0x13, 0x07, 0xa0, 0x0a, 0x2a, 0x8d, 0xe3, 0x1c, 0xe5, 0xe6, 0x81, 0x45, + 0x13, 0x05, 0x50, 0x04, 0xef, 0x30, 0xc0, 0x2c, 0xaa, 0x8c, 0xe3, 0x14, 0xa5, 0xe7, 0x01, 0x45, + 0xef, 0x20, 0x50, 0x49, 0x41, 0x46, 0x93, 0x05, 0x0a, 0x00, 0x01, 0x45, 0xef, 0x20, 0xf0, 0x4b, + 0x93, 0x07, 0xf0, 0x03, 0x63, 0xe3, 0xb7, 0x07, 0x93, 0x85, 0x0b, 0x01, 0x01, 0x45, 0x6e, 0x86, + 0xef, 0x20, 0xb0, 0x4a, 0xee, 0x85, 0x13, 0x05, 0x60, 0x04, 0xef, 0x30, 0x60, 0x29, 0xe3, 0x1a, + 0x95, 0xe3, 0x81, 0x45, 0x13, 0x05, 0xa0, 0x04, 0xef, 0x30, 0x80, 0x28, 0x93, 0x07, 0xa0, 0x0a, + 0xe3, 0x11, 0xf5, 0xe2, 0xef, 0x20, 0x10, 0x69, 0x93, 0x07, 0x00, 0x05, 0x7c, 0xd8, 0x19, 0xb1, + 0x13, 0x06, 0x00, 0x09, 0xea, 0x85, 0x01, 0x45, 0xef, 0x20, 0x30, 0x47, 0x93, 0x05, 0x00, 0x09, + 0x13, 0x05, 0x30, 0x04, 0xef, 0x30, 0xc0, 0x25, 0x93, 0x06, 0xa0, 0x0a, 0xe3, 0x1b, 0xd5, 0xde, + 0x93, 0x8c, 0x0c, 0xf7, 0x13, 0x0d, 0x0d, 0x09, 0x81, 0xbf, 0x93, 0x85, 0x0b, 0x01, 0x01, 0x45, + 0x13, 0x06, 0x00, 0x04, 0xef, 0x20, 0x70, 0x44, 0x93, 0x05, 0x00, 0x04, 0x13, 0x05, 0x70, 0x04, + 0xef, 0x30, 0x00, 0x23, 0xe3, 0x17, 0x95, 0xdd, 0xb7, 0x0c, 0x20, 0x00, 0x13, 0x09, 0x09, 0xfa, + 0x93, 0x8c, 0x0c, 0x05, 0x93, 0x0d, 0x00, 0x08, 0x93, 0x0b, 0xa0, 0x0a, 0x63, 0xe1, 0x2d, 0x03, + 0x4a, 0x86, 0xe6, 0x85, 0x01, 0x45, 0xef, 0x20, 0x50, 0x41, 0xca, 0x85, 0x13, 0x05, 0x90, 0x04, + 0xef, 0x30, 0x00, 0x20, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1d, 0xf5, 0xd8, 0x9d, 0xb7, 0xe6, 0x85, + 0x01, 0x45, 0x13, 0x06, 0x00, 0x08, 0xef, 0x20, 0x50, 0x3f, 0x93, 0x05, 0x00, 0x08, 0x13, 0x05, + 0x80, 0x04, 0xef, 0x30, 0xe0, 0x1d, 0xe3, 0x1e, 0x75, 0xd7, 0x13, 0x09, 0x09, 0xf8, 0x93, 0x8c, + 0x0c, 0x08, 0x6d, 0xbf, 0x21, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x9f, 0xeb, 0xb4, 0x03, 0x44, + 0x1d, 0x00, 0xbd, 0x47, 0xe3, 0xef, 0x87, 0xd4, 0x83, 0x2c, 0x4d, 0x00, 0xfd, 0x57, 0xe3, 0x8a, + 0xfc, 0xd4, 0x13, 0x19, 0xa4, 0x00, 0x13, 0x05, 0x09, 0x40, 0xef, 0xe0, 0x4f, 0xe1, 0x13, 0x07, + 0xa0, 0x0a, 0xaa, 0x8b, 0xe3, 0x1f, 0xe5, 0xd2, 0x13, 0x09, 0x09, 0x20, 0x4a, 0x85, 0xef, 0xe0, + 0x0f, 0xe0, 0xaa, 0x8d, 0xe3, 0x17, 0x75, 0xd3, 0xe6, 0x85, 0x4a, 0x85, 0xef, 0x10, 0x20, 0x17, + 0xe3, 0x11, 0xb5, 0xd3, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x07, 0xf6, 0x85, 0x47, 0x33, 0x94, + 0x87, 0x00, 0x1c, 0x43, 0x5d, 0x8c, 0x00, 0xc3, 0xf5, 0xbc, 0x0d, 0x47, 0x93, 0x0c, 0x00, 0x08, + 0xe3, 0x9c, 0xeb, 0xae, 0x83, 0x45, 0x1d, 0x00, 0xbd, 0x47, 0xe3, 0xec, 0xb7, 0xce, 0xb7, 0x37, + 0x20, 0x00, 0x83, 0xa7, 0x07, 0xf6, 0xd1, 0x4c, 0xb3, 0xd7, 0xb7, 0x00, 0x85, 0x8b, 0xe3, 0x8d, + 0x07, 0xac, 0x37, 0x15, 0x20, 0x00, 0x13, 0x05, 0x05, 0x08, 0xef, 0xe0, 0x2f, 0xe6, 0x85, 0x47, + 0xe3, 0x0c, 0xf5, 0xba, 0x89, 0x47, 0xe3, 0x01, 0xf5, 0xac, 0xe1, 0xb1, 0x93, 0x0c, 0x00, 0x08, + 0x65, 0xbc, 0xef, 0x10, 0x70, 0x46, 0xef, 0xe0, 0xef, 0xd2, 0x6f, 0xf0, 0x8f, 0xef, 0xef, 0x00, + 0xc0, 0x6f, 0x6f, 0xf0, 0x8f, 0xef, 0xef, 0x00, 0x30, 0x4b, 0x93, 0x0b, 0x09, 0xff, 0xaa, 0x86, + 0x63, 0x0f, 0x05, 0xf2, 0x8d, 0x45, 0x13, 0x85, 0x8d, 0x53, 0x36, 0xce, 0x69, 0x24, 0xf2, 0x46, + 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0x86, 0x5c, 0x93, 0x85, 0x8d, 0x53, 0x13, 0x85, 0x89, 0x77, + 0x01, 0x24, 0xf2, 0x46, 0x09, 0x46, 0x05, 0x47, 0x63, 0x83, 0xc6, 0x00, 0x09, 0x47, 0x83, 0x46, + 0x84, 0x07, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0xa3, 0x0c, 0xe4, 0x06, 0x13, 0x06, + 0x86, 0x5e, 0x5e, 0x87, 0x93, 0x85, 0xc5, 0x56, 0x13, 0x85, 0x89, 0x77, 0xd1, 0x2a, 0xef, 0xe0, + 0xcf, 0xc8, 0xef, 0xe0, 0xcf, 0xf9, 0x62, 0x47, 0x85, 0x47, 0x23, 0x00, 0xf7, 0x00, 0xef, 0x00, + 0xc0, 0x5a, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0x63, 0x1f, 0xf5, 0xdc, 0x1d, 0x29, 0x2a, 0x84, + 0x63, 0x1b, 0x25, 0xdd, 0xef, 0x30, 0xc0, 0x1a, 0x63, 0x17, 0x85, 0xdc, 0xb7, 0x37, 0x20, 0x00, + 0x83, 0xa7, 0x87, 0xf5, 0xb1, 0xeb, 0x83, 0x27, 0x4b, 0x07, 0x13, 0x07, 0xfc, 0x00, 0xfd, 0x17, + 0x63, 0x64, 0xf7, 0x04, 0x05, 0x45, 0xef, 0x20, 0xf0, 0x23, 0x03, 0x26, 0x4b, 0x07, 0x37, 0x09, + 0x20, 0x00, 0x93, 0x05, 0x09, 0x00, 0x13, 0x05, 0x09, 0x00, 0xef, 0x20, 0x10, 0x34, 0x37, 0x14, + 0x20, 0x00, 0x13, 0x05, 0x04, 0x02, 0xef, 0x20, 0xd0, 0x42, 0x03, 0x25, 0x4b, 0x07, 0x93, 0x07, + 0x09, 0x00, 0x41, 0x46, 0x3e, 0x95, 0x93, 0x05, 0x04, 0x02, 0xef, 0x30, 0x40, 0x6e, 0x83, 0x27, + 0x4b, 0x07, 0xc1, 0x07, 0x23, 0x2a, 0xfb, 0x06, 0xef, 0x00, 0x70, 0x1e, 0x13, 0x04, 0xa0, 0x0a, + 0x63, 0x03, 0x85, 0xd6, 0xef, 0xe0, 0x5f, 0xa2, 0x63, 0x1f, 0x85, 0xd4, 0x37, 0x56, 0x10, 0x00, + 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x60, 0x93, 0x85, 0xc5, 0x56, + 0x13, 0x05, 0x45, 0x57, 0x31, 0x2a, 0xef, 0xe0, 0xaf, 0xb0, 0xef, 0x20, 0x50, 0x41, 0xef, 0x00, + 0xd0, 0x36, 0xef, 0x00, 0xd0, 0x2d, 0xef, 0xe0, 0x4f, 0xf3, 0x6f, 0xf0, 0xcf, 0xd2, 0x2a, 0x87, + 0x81, 0x47, 0x01, 0x45, 0x63, 0x93, 0xc7, 0x00, 0x82, 0x80, 0xb3, 0x06, 0xf7, 0x00, 0x33, 0x88, + 0xf5, 0x00, 0x83, 0xc6, 0x06, 0x00, 0x03, 0x48, 0x08, 0x00, 0x85, 0x07, 0xb3, 0xc6, 0x06, 0x01, + 0x55, 0x8d, 0x13, 0x75, 0xf5, 0x0f, 0xf9, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x37, 0x37, 0x20, 0x00, + 0x03, 0xa8, 0x87, 0xf6, 0x83, 0x27, 0x47, 0xf6, 0xaa, 0x86, 0x13, 0x07, 0x47, 0xf6, 0x01, 0x45, + 0x63, 0x13, 0xf8, 0x00, 0x82, 0x80, 0x37, 0x26, 0x20, 0x00, 0x13, 0x06, 0xc6, 0x08, 0x93, 0x08, + 0xf0, 0x7f, 0x63, 0x01, 0xb5, 0x02, 0x33, 0x0e, 0xf6, 0x00, 0x03, 0x4e, 0x0e, 0x00, 0x05, 0x05, + 0x33, 0x83, 0xa6, 0x00, 0xa3, 0x0f, 0xc3, 0xff, 0x85, 0x07, 0x63, 0xf3, 0xf8, 0x00, 0x81, 0x47, + 0xe3, 0x11, 0xf8, 0xfe, 0x1c, 0xc3, 0x82, 0x80, 0x93, 0x07, 0xf0, 0x7f, 0x63, 0xe5, 0xa7, 0x02, + 0xb7, 0x36, 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x86, 0x46, 0xf6, 0x83, 0xa7, 0x87, 0xf6, + 0x98, 0x42, 0x33, 0x87, 0xe7, 0x40, 0x13, 0x77, 0xf7, 0x7f, 0x63, 0x76, 0xe5, 0x00, 0x89, 0x8f, + 0x93, 0xf7, 0xf7, 0x7f, 0x9c, 0xc2, 0x82, 0x80, 0xb7, 0x36, 0x20, 0x00, 0x03, 0xa8, 0x86, 0xf6, + 0x13, 0x07, 0xf0, 0x7f, 0x13, 0x86, 0x86, 0xf6, 0x93, 0x07, 0x18, 0x00, 0x63, 0x73, 0xf7, 0x00, + 0x81, 0x47, 0xb7, 0x36, 0x20, 0x00, 0x83, 0xa8, 0x46, 0xf6, 0x37, 0x27, 0x20, 0x00, 0x93, 0x85, + 0x46, 0xf6, 0x13, 0x07, 0xc7, 0x08, 0x63, 0x9f, 0xf8, 0x00, 0x93, 0x88, 0x17, 0x80, 0x93, 0x86, + 0x17, 0x00, 0x63, 0x93, 0x08, 0x00, 0x81, 0x46, 0x94, 0xc1, 0xba, 0x96, 0x93, 0x05, 0xa0, 0x02, + 0x23, 0x80, 0xb6, 0x00, 0x42, 0x97, 0x23, 0x00, 0xa7, 0x00, 0x1c, 0xc2, 0x82, 0x80, 0x82, 0x80, + 0x39, 0x71, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x06, 0xce, 0x36, 0xd6, 0x3a, 0xd8, 0x3e, 0xda, + 0x42, 0xdc, 0x46, 0xde, 0xaa, 0x84, 0x2e, 0x89, 0x32, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x6f, 0xfd, + 0x63, 0x14, 0x09, 0x00, 0xef, 0xe0, 0xef, 0xfc, 0x19, 0xe0, 0xef, 0xe0, 0x8f, 0xfc, 0x7c, 0x10, + 0x3e, 0xc6, 0xef, 0x30, 0x40, 0x21, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x73, + 0xef, 0x30, 0x40, 0x46, 0x37, 0x55, 0x10, 0x00, 0x4a, 0x86, 0xa6, 0x85, 0x13, 0x05, 0x45, 0x74, + 0xef, 0x30, 0x40, 0x45, 0xb2, 0x45, 0x22, 0x85, 0xef, 0x30, 0xa0, 0x41, 0x37, 0x55, 0x10, 0x00, + 0x13, 0x05, 0x05, 0x75, 0xef, 0x30, 0x00, 0x44, 0xb9, 0x29, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, + 0x42, 0x49, 0x21, 0x61, 0x82, 0x80, 0xae, 0x86, 0x37, 0x56, 0x10, 0x00, 0xaa, 0x85, 0x37, 0x55, + 0x10, 0x00, 0x13, 0x06, 0x46, 0x5e, 0x13, 0x05, 0x45, 0x75, 0x9d, 0xbf, 0xb7, 0x37, 0x20, 0x00, + 0x93, 0x87, 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, 0x83, 0xa6, 0x47, 0x10, 0x63, 0x7e, 0xd7, 0x00, + 0x0a, 0x07, 0x3e, 0x97, 0x18, 0x43, 0x18, 0xc1, 0x03, 0xa7, 0x07, 0x10, 0x13, 0x05, 0xa0, 0x0a, + 0x05, 0x07, 0x23, 0xa0, 0xe7, 0x10, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, + 0x26, 0xca, 0xb7, 0x34, 0x20, 0x00, 0x83, 0xa7, 0xc4, 0xf6, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, + 0x4e, 0xc6, 0x52, 0xc4, 0x11, 0x47, 0x63, 0x6f, 0xf7, 0x0c, 0x37, 0x57, 0x10, 0x00, 0x8a, 0x07, + 0x13, 0x07, 0xc7, 0x77, 0xba, 0x97, 0x9c, 0x43, 0x2a, 0x84, 0x93, 0x84, 0xc4, 0xf6, 0x82, 0x87, + 0x81, 0x45, 0xef, 0x30, 0x40, 0x3f, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x98, 0xa7, 0xf6, 0xb7, 0x37, + 0x20, 0x00, 0x23, 0x86, 0x87, 0x88, 0xef, 0x20, 0x50, 0x73, 0x9c, 0x40, 0x85, 0x07, 0x81, 0xa8, + 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0x07, 0xf6, 0x93, 0x07, 0xc0, 0x0f, 0x63, 0xf1, 0xa7, 0x02, + 0x62, 0x44, 0x9d, 0x47, 0xf2, 0x40, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x9c, 0xc0, 0xd2, 0x44, + 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x85, 0x75, 0x05, 0x61, 0x2d, 0xbf, 0x37, 0x39, + 0x20, 0x00, 0x13, 0x09, 0x09, 0xf7, 0x83, 0x55, 0x09, 0x00, 0xef, 0x30, 0xc0, 0x39, 0xb7, 0x37, + 0x20, 0x00, 0xa3, 0x86, 0x87, 0x88, 0x23, 0x10, 0xa9, 0x00, 0x8d, 0x47, 0x5d, 0xf4, 0x9c, 0xc0, + 0x91, 0xa8, 0x37, 0x39, 0x20, 0x00, 0x03, 0x27, 0x49, 0xf7, 0x93, 0x07, 0xb0, 0x0f, 0x13, 0x09, + 0x49, 0xf7, 0x63, 0xf4, 0xe7, 0x00, 0xef, 0xe0, 0xcf, 0xe7, 0x83, 0x27, 0x09, 0x00, 0x37, 0x3a, + 0x20, 0x00, 0x13, 0x0a, 0x0a, 0xf7, 0xb7, 0x39, 0x20, 0x00, 0x93, 0x89, 0xc9, 0x88, 0x83, 0x55, + 0x0a, 0x00, 0xce, 0x97, 0x23, 0x81, 0x87, 0x00, 0x22, 0x85, 0xef, 0x30, 0xc0, 0x34, 0x83, 0x27, + 0x09, 0x00, 0x03, 0xc7, 0x19, 0x00, 0x23, 0x10, 0xaa, 0x00, 0x85, 0x07, 0x23, 0x20, 0xf9, 0x00, + 0xe3, 0xfd, 0xe7, 0xf4, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, + 0x05, 0x61, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x99, 0xa7, 0xf6, 0x3d, 0xbf, 0x37, 0x39, + 0x20, 0x00, 0x13, 0x09, 0x29, 0xf7, 0x13, 0x14, 0x85, 0x00, 0xb7, 0x39, 0x20, 0x00, 0x03, 0x55, + 0x09, 0x00, 0x93, 0x89, 0x09, 0xf7, 0x83, 0xd7, 0x09, 0x00, 0x49, 0x8c, 0x23, 0x10, 0x89, 0x00, + 0xe3, 0x8d, 0x87, 0xf0, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0x84, 0x75, 0x99, 0x47, 0x89, 0x45, + 0x9c, 0xc0, 0x95, 0x3d, 0x93, 0x05, 0x84, 0x75, 0x62, 0x44, 0x03, 0xd7, 0x09, 0x00, 0x83, 0x56, + 0x09, 0x00, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x37, 0x56, 0x10, 0x00, + 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x75, 0x13, 0x05, 0x85, 0x77, 0x05, 0x61, 0x6f, 0xf0, + 0x3f, 0xdd, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0xb7, 0x25, 0x10, 0x00, 0x37, 0x25, + 0x10, 0x00, 0x23, 0xa0, 0x07, 0x10, 0x23, 0xa2, 0x07, 0x10, 0x93, 0x85, 0xc5, 0xfd, 0xb7, 0x37, + 0x20, 0x00, 0x13, 0x05, 0xe5, 0x00, 0x23, 0xa6, 0x07, 0xf6, 0x6f, 0x20, 0x70, 0x55, 0x11, 0xed, + 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0xef, 0xe0, 0xcf, 0xd8, 0x32, 0x45, 0xf2, 0x40, 0x13, 0x06, + 0xe0, 0x0f, 0x81, 0x45, 0x05, 0x61, 0x6f, 0x30, 0x40, 0x35, 0x13, 0x06, 0xe0, 0x0f, 0x81, 0x45, + 0xdd, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xf6, 0x13, 0x05, 0xa0, 0x0a, 0x99, 0xc3, + 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, + 0xc4, 0xf6, 0x1c, 0x40, 0x06, 0xc6, 0x15, 0x47, 0x63, 0x98, 0xe7, 0x00, 0x13, 0x05, 0xa0, 0x0a, + 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x81, 0xe7, 0x13, 0x05, 0x50, 0x05, 0xcd, 0xbf, + 0xef, 0x20, 0x10, 0x54, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x19, 0xf5, 0xfe, 0x01, 0x00, 0x18, 0x40, + 0x91, 0x47, 0xe3, 0xcd, 0xe7, 0xfc, 0x99, 0x47, 0x1c, 0xc0, 0xd9, 0xbf, 0x41, 0x11, 0x06, 0xc6, + 0xef, 0x20, 0x90, 0x53, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xf5, 0x00, 0xef, 0x20, 0xf0, 0x54, + 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0xc7, 0xf6, 0x95, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, + 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, + 0x03, 0xa7, 0xc7, 0xf6, 0x99, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, + 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0xc7, 0xf6, 0x9d, 0x47, 0x13, 0x05, + 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x37, 0x35, 0x20, 0x00, + 0x13, 0x05, 0xc5, 0x88, 0x82, 0x80, 0x01, 0x11, 0x26, 0xca, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, + 0x4e, 0xc6, 0xaa, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0xcf, 0xc9, 0x83, 0xc7, 0x14, 0x00, 0x13, 0x07, + 0xc0, 0x0f, 0x13, 0x05, 0x50, 0x05, 0x63, 0x65, 0xf7, 0x06, 0x37, 0x39, 0x20, 0x00, 0x13, 0x04, + 0xc9, 0x98, 0x23, 0x20, 0x04, 0x10, 0x03, 0xc7, 0x04, 0x00, 0xa3, 0x00, 0xf4, 0x00, 0x03, 0xc6, + 0x14, 0x00, 0x23, 0x00, 0xe4, 0x00, 0x93, 0x85, 0x24, 0x00, 0x13, 0x05, 0x24, 0x00, 0xef, 0x30, + 0x00, 0x20, 0x83, 0xc9, 0x14, 0x00, 0x13, 0x05, 0xc9, 0x98, 0x13, 0x09, 0xc9, 0x98, 0x93, 0x84, + 0x29, 0x00, 0xa6, 0x85, 0xef, 0x30, 0x80, 0x16, 0xa2, 0x94, 0x23, 0x80, 0xa4, 0x00, 0x4e, 0x94, + 0x21, 0x81, 0x93, 0x87, 0x49, 0x00, 0xa3, 0x01, 0xa4, 0x00, 0xfd, 0x56, 0x13, 0xf7, 0x37, 0x00, + 0x19, 0xef, 0x89, 0x83, 0x23, 0x22, 0xf9, 0x10, 0xef, 0x20, 0x30, 0x49, 0x13, 0x05, 0xa0, 0x0a, + 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, 0x33, 0x07, + 0xf9, 0x00, 0x23, 0x00, 0xd7, 0x00, 0x85, 0x07, 0xd1, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, + 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, 0x83, 0xa7, 0x47, 0x10, 0x63, 0x14, 0xf7, 0x00, 0x6f, 0x20, + 0xb0, 0x41, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa6, 0x07, 0xf6, + 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x93, 0x07, 0x00, 0x08, 0x73, 0xa0, 0x47, 0x30, 0x93, 0x06, + 0x70, 0x3e, 0x09, 0x46, 0x93, 0x05, 0x60, 0x04, 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, 0xf0, 0x59, + 0x8d, 0x45, 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, 0xf0, 0x5d, 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, + 0x70, 0x53, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0xb0, 0x55, 0xfd, 0x56, 0x01, 0x46, 0x93, 0x05, + 0x60, 0x04, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x50, 0x57, 0xb2, 0x40, 0xb7, 0x07, 0x20, 0x01, + 0x23, 0xac, 0x07, 0x00, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x89, 0x2c, 0xb2, 0x40, + 0x41, 0x01, 0x45, 0xb7, 0x41, 0x11, 0x22, 0xc4, 0xb7, 0x07, 0x20, 0x01, 0x06, 0xc6, 0x23, 0xac, + 0x07, 0x00, 0x2a, 0x84, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0xd0, 0x4e, 0x93, 0x07, 0x80, 0x3e, + 0x13, 0x05, 0x80, 0x3e, 0x63, 0xe3, 0x87, 0x00, 0x22, 0x85, 0xb7, 0x07, 0x20, 0x01, 0x98, 0x4f, + 0x13, 0x84, 0x87, 0x01, 0xe3, 0x6d, 0xa7, 0xfe, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x50, 0x4f, + 0xb2, 0x40, 0x23, 0x20, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x11, 0xe1, 0x82, 0x80, + 0x01, 0x00, 0x7d, 0x15, 0xe5, 0xbf, 0x6f, 0xf0, 0x9f, 0xb3, 0x29, 0xa4, 0x01, 0x11, 0x26, 0xca, + 0xaa, 0x84, 0x37, 0x05, 0x20, 0x01, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x56, 0xc2, 0x06, 0xce, + 0x22, 0xcc, 0x2e, 0x89, 0x93, 0x09, 0xa0, 0x0a, 0xef, 0x20, 0xd0, 0x48, 0x37, 0x0a, 0x20, 0x01, + 0x93, 0x0a, 0x80, 0x3e, 0x82, 0x94, 0x2a, 0x84, 0x63, 0x0c, 0x35, 0x03, 0x83, 0x27, 0x8a, 0x01, + 0x63, 0x7a, 0xf9, 0x04, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0x04, 0x79, 0x85, 0x45, 0xef, 0xf0, + 0x9f, 0xb6, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0x05, 0x04, 0x79, 0xa6, 0x86, + 0x13, 0x06, 0x46, 0x79, 0x13, 0x05, 0x85, 0x77, 0xef, 0xf0, 0x9f, 0xad, 0x13, 0x04, 0x50, 0x05, + 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0xd0, 0x46, 0xf2, 0x40, 0x22, 0x85, 0x62, 0x44, 0xb7, 0x07, + 0x20, 0x01, 0x23, 0xac, 0x07, 0x00, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, + 0x05, 0x61, 0x82, 0x80, 0xe3, 0xf0, 0x2a, 0xfb, 0xb5, 0x2a, 0x69, 0xbf, 0x37, 0x07, 0x00, 0x02, + 0x1c, 0x47, 0x93, 0xe7, 0x87, 0x00, 0x1c, 0xc7, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, + 0x26, 0xc2, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0xcf, 0xa7, 0xa9, 0x44, 0x03, 0x45, 0x04, 0x00, + 0x11, 0xe5, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xef, 0xf0, 0xdf, 0xa1, + 0x83, 0x47, 0x04, 0x00, 0x63, 0x94, 0x97, 0x00, 0xef, 0xf0, 0x7f, 0xa6, 0x05, 0x04, 0xf9, 0xbf, + 0x41, 0x11, 0x06, 0xc6, 0x25, 0x37, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x05, 0xf5, 0x00, 0xef, 0xe0, + 0x4f, 0xa4, 0x01, 0xa0, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x44, + 0x20, 0x00, 0x13, 0x06, 0xc0, 0x1f, 0x81, 0x45, 0x13, 0x05, 0x04, 0xe0, 0x06, 0xc6, 0x26, 0xc2, + 0xef, 0x20, 0xb0, 0x7f, 0x13, 0x05, 0x04, 0xe0, 0x93, 0x05, 0xc0, 0x1f, 0xef, 0x20, 0x30, 0x76, + 0x93, 0x04, 0x04, 0xe0, 0xb2, 0x40, 0x22, 0x44, 0x23, 0xae, 0xa4, 0x1e, 0x92, 0x44, 0x41, 0x01, + 0x82, 0x80, 0x41, 0x11, 0x37, 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, 0xc0, 0x1f, 0x13, 0x04, + 0x05, 0xe0, 0x13, 0x05, 0x05, 0xe0, 0x06, 0xc6, 0xef, 0x20, 0x70, 0x73, 0x03, 0x27, 0xc4, 0x1f, + 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xa7, 0x00, 0x93, 0x07, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, + 0x3e, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, 0xaa, 0x87, 0x63, 0x6e, 0xa7, 0x00, + 0x13, 0x77, 0x35, 0x00, 0x01, 0x45, 0x11, 0xeb, 0x37, 0x45, 0x20, 0x00, 0x13, 0x05, 0x05, 0xe0, + 0xf1, 0x9b, 0xaa, 0x97, 0x88, 0x43, 0x82, 0x80, 0x01, 0x45, 0x82, 0x80, 0x93, 0x07, 0xb0, 0x1f, + 0x63, 0xec, 0xa7, 0x00, 0x93, 0x77, 0x35, 0x00, 0x81, 0xeb, 0xb7, 0x47, 0x20, 0x00, 0x71, 0x99, + 0x93, 0x87, 0x07, 0xe0, 0x3e, 0x95, 0x0c, 0xc1, 0x82, 0x80, 0x41, 0x11, 0x37, 0x45, 0x20, 0x00, + 0x22, 0xc4, 0x93, 0x05, 0xc0, 0x1f, 0x13, 0x04, 0x05, 0xe0, 0x13, 0x05, 0x05, 0xe0, 0x06, 0xc6, + 0xef, 0x20, 0xf0, 0x6b, 0xb2, 0x40, 0x23, 0x2e, 0xa4, 0x1e, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, + 0x13, 0x07, 0xb0, 0x1f, 0x63, 0x61, 0xa7, 0x02, 0x93, 0x77, 0x35, 0x00, 0x13, 0x07, 0x50, 0x05, + 0x89, 0xef, 0x41, 0x11, 0x06, 0xc6, 0x5d, 0x37, 0xc9, 0x37, 0xb2, 0x40, 0x13, 0x07, 0xa0, 0x0a, + 0x3a, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0x50, 0x05, 0x3a, 0x85, 0x82, 0x80, 0x41, 0x11, + 0x06, 0xc6, 0xef, 0x00, 0x90, 0x6c, 0xef, 0x20, 0xe0, 0x5f, 0xb2, 0x40, 0x13, 0x05, 0xa0, 0x0a, + 0x41, 0x01, 0x82, 0x80, 0x73, 0x00, 0x50, 0x10, 0x82, 0x80, 0x3d, 0xce, 0x79, 0x71, 0x22, 0xd4, + 0x26, 0xd2, 0x4a, 0xd0, 0x06, 0xd6, 0x4e, 0xce, 0x52, 0xcc, 0x2a, 0x84, 0x2e, 0x89, 0xb2, 0x84, + 0x19, 0xe1, 0xef, 0xe0, 0x0f, 0x90, 0x93, 0x77, 0x39, 0x00, 0x99, 0xc3, 0xef, 0xe0, 0x6f, 0x8f, + 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x87, 0x34, 0x41, 0x33, 0x05, 0x34, 0x01, 0x63, 0x6c, 0xfa, 0x02, + 0x13, 0xd6, 0x24, 0x00, 0xf1, 0x57, 0x33, 0x06, 0xf6, 0x02, 0x93, 0xf5, 0xc4, 0xff, 0x33, 0x05, + 0xb4, 0x00, 0x2e, 0x99, 0x26, 0x96, 0x19, 0xc6, 0x83, 0x27, 0x09, 0x00, 0x6c, 0x00, 0x3e, 0xc6, + 0xef, 0x20, 0xf0, 0x65, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, + 0x45, 0x61, 0x82, 0x80, 0xb3, 0x07, 0x39, 0x01, 0x9c, 0x43, 0x11, 0x46, 0x6c, 0x00, 0x3e, 0xc6, + 0x91, 0x09, 0xef, 0x20, 0xd0, 0x63, 0x7d, 0xb7, 0x82, 0x80, 0x3d, 0xce, 0x79, 0x71, 0x22, 0xd4, + 0x26, 0xd2, 0x4a, 0xd0, 0x06, 0xd6, 0x4e, 0xce, 0x52, 0xcc, 0x2a, 0x84, 0x2e, 0x89, 0xb2, 0x84, + 0x99, 0xe1, 0xef, 0xe0, 0x0f, 0x88, 0x93, 0x77, 0x34, 0x00, 0x99, 0xc3, 0xef, 0xe0, 0x6f, 0x87, + 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x87, 0x34, 0x41, 0xb3, 0x05, 0x39, 0x01, 0x63, 0x6c, 0xfa, 0x02, + 0x13, 0xd6, 0x24, 0x00, 0xf1, 0x57, 0x33, 0x06, 0xf6, 0x02, 0x93, 0xf5, 0xc4, 0xff, 0x2e, 0x94, + 0xca, 0x95, 0x26, 0x96, 0x01, 0xca, 0x1c, 0x40, 0x68, 0x00, 0x3e, 0xc6, 0xef, 0x20, 0x30, 0x5e, + 0xb2, 0x47, 0x1c, 0xc0, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, + 0x45, 0x61, 0x82, 0x80, 0x11, 0x46, 0x68, 0x00, 0xef, 0x20, 0x70, 0x5c, 0x32, 0x47, 0xb3, 0x07, + 0x34, 0x01, 0x91, 0x09, 0x98, 0xc3, 0x7d, 0xb7, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, + 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0xef, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, + 0x23, 0xac, 0xe7, 0xf6, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa0, 0x87, 0xf8, 0xb7, 0x37, 0x20, 0x00, + 0x23, 0x8a, 0x07, 0xa8, 0xef, 0xf0, 0x9f, 0xb3, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xae, 0xa7, 0xf6, + 0x19, 0xe1, 0xef, 0xd0, 0x1f, 0xfe, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x7f, 0xa1, + 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xd0, 0x9f, 0xfc, 0x37, 0x35, + 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0xa2, 0x85, 0x13, 0x06, 0xe0, 0x0f, 0x13, 0x05, 0x45, 0xa9, + 0x23, 0x8a, 0x07, 0xb8, 0xef, 0x20, 0xb0, 0x54, 0x22, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, + 0x6f, 0xf0, 0x7f, 0xaf, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x19, 0xe1, + 0xef, 0xd0, 0x3f, 0xf9, 0xb7, 0x34, 0x20, 0x00, 0x83, 0xc7, 0x44, 0xb9, 0x99, 0xcb, 0x37, 0x35, + 0x20, 0x00, 0x13, 0x06, 0xe0, 0x0f, 0x93, 0x85, 0x44, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0xef, 0x20, + 0x10, 0x51, 0xa2, 0x85, 0x13, 0x85, 0x44, 0xb9, 0x13, 0x06, 0xe0, 0x0f, 0xef, 0x20, 0x30, 0x50, + 0x22, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x92, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0xdf, 0xaa, 0xb7, 0x37, + 0x20, 0x00, 0x03, 0xa5, 0x87, 0xf7, 0x82, 0x80, 0x37, 0x35, 0x20, 0x00, 0x83, 0x47, 0x45, 0xa9, + 0x85, 0xc3, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xc7, 0x47, 0xb9, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, + 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xac, 0xe7, 0xf6, 0x13, 0x05, 0x45, 0xa9, 0x6f, 0xf0, 0xbf, 0xa7, + 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x9f, 0x9a, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x04, 0xf5, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, + 0x6d, 0x71, 0x23, 0x26, 0x11, 0x10, 0x23, 0x24, 0x81, 0x10, 0x23, 0x22, 0x91, 0x10, 0xef, 0xf0, + 0x9f, 0x99, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x02, 0x2a, 0x84, 0xef, 0xf0, 0x1f, 0x9d, + 0x63, 0x12, 0x85, 0x06, 0xb7, 0x37, 0x20, 0x00, 0x37, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xf8, + 0x03, 0x25, 0xc7, 0xf7, 0x82, 0x97, 0xef, 0xf0, 0x3f, 0xae, 0xef, 0xf0, 0x1f, 0xac, 0x93, 0x07, + 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x18, 0xf5, 0x02, 0xef, 0xf0, 0xbf, 0x94, 0x63, 0x14, 0x85, 0x02, + 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x84, 0xf7, 0x04, 0x40, 0xb7, 0x35, 0x20, 0x00, 0x63, 0x9c, + 0xa4, 0x04, 0x13, 0x85, 0x45, 0xb9, 0xef, 0xf0, 0x1f, 0x9f, 0x63, 0x15, 0x95, 0x00, 0x93, 0x07, + 0x50, 0x05, 0x1c, 0xc0, 0x83, 0x20, 0xc1, 0x10, 0x03, 0x24, 0x81, 0x10, 0x83, 0x24, 0x41, 0x10, + 0x51, 0x61, 0x82, 0x80, 0xef, 0xf0, 0x9f, 0x99, 0x81, 0x44, 0x63, 0x14, 0x85, 0x00, 0x93, 0x04, + 0xc0, 0x07, 0xef, 0xf0, 0x3f, 0x9a, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0xc1, 0xdc, + 0x0a, 0x85, 0x23, 0x00, 0x91, 0x00, 0xa3, 0x00, 0x01, 0x00, 0xef, 0xf0, 0x7f, 0xe8, 0x61, 0xb7, + 0x93, 0x04, 0xc0, 0x07, 0xf5, 0xb7, 0x83, 0xc7, 0x45, 0xb9, 0xcd, 0xdf, 0x03, 0x24, 0x81, 0x10, + 0x83, 0x20, 0xc1, 0x10, 0x83, 0x24, 0x41, 0x10, 0x37, 0x35, 0x20, 0x00, 0x13, 0x06, 0xe0, 0x0f, + 0x93, 0x85, 0x45, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0x51, 0x61, 0x6f, 0x20, 0x50, 0x3c, 0xb7, 0x07, + 0x01, 0x04, 0x23, 0xa2, 0x07, 0x00, 0x21, 0x65, 0x6f, 0x20, 0x80, 0x30, 0x41, 0x11, 0x21, 0x65, + 0x06, 0xc6, 0xef, 0x20, 0x20, 0x2f, 0xb2, 0x40, 0xb7, 0x07, 0x01, 0x04, 0x05, 0x47, 0xd8, 0xc3, + 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x07, 0x70, 0x02, + 0x2a, 0x84, 0xae, 0x84, 0x63, 0xf4, 0xa7, 0x00, 0xef, 0xd0, 0xbf, 0xde, 0x37, 0x05, 0x01, 0x04, + 0x0a, 0x04, 0x13, 0x05, 0x05, 0x10, 0x2a, 0x94, 0x04, 0xc0, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, + 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x13, 0x87, 0x07, 0x10, 0x93, 0x87, 0x07, 0x1a, + 0x23, 0x20, 0x07, 0x00, 0x11, 0x07, 0xe3, 0x1d, 0xf7, 0xfe, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, + 0xc8, 0xcb, 0x82, 0x80, 0x42, 0x05, 0xb7, 0x07, 0x01, 0x04, 0xc8, 0xcb, 0x82, 0x80, 0xb7, 0x07, + 0x01, 0x04, 0x88, 0x4b, 0x13, 0x75, 0xf5, 0x0f, 0x82, 0x80, 0x89, 0x67, 0x37, 0x07, 0x01, 0x04, + 0x8d, 0x07, 0x1c, 0xc7, 0x23, 0x2a, 0x07, 0x00, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, + 0x2a, 0x84, 0xad, 0x37, 0xb7, 0x07, 0x01, 0x04, 0x80, 0xcf, 0xc5, 0x37, 0x65, 0x37, 0x22, 0x44, + 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xf4, 0xb7, 0x06, 0x01, 0x04, 0x9c, 0x46, 0x05, 0x45, + 0x13, 0xf7, 0x17, 0x00, 0x1d, 0xc7, 0x13, 0xf7, 0x07, 0x40, 0x0d, 0x45, 0x1d, 0xe3, 0x98, 0x4a, + 0x13, 0x77, 0xf7, 0x0f, 0x19, 0xcf, 0x13, 0xf7, 0x27, 0x20, 0x09, 0x45, 0x19, 0xeb, 0x13, 0xd7, + 0xb7, 0x00, 0x05, 0x8b, 0x11, 0x45, 0x11, 0xe7, 0x13, 0xd5, 0x87, 0x00, 0x13, 0x45, 0x15, 0x00, + 0x05, 0x89, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x88, 0xcf, 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, + 0x06, 0xce, 0x33, 0x07, 0xb6, 0x00, 0x93, 0x07, 0x00, 0x09, 0x2e, 0x84, 0x63, 0xf8, 0xe7, 0x00, + 0x32, 0xc6, 0x2a, 0xc4, 0xef, 0xd0, 0xff, 0xd0, 0x32, 0x46, 0x22, 0x45, 0xb7, 0x15, 0x01, 0x04, + 0xa2, 0x95, 0xef, 0xf0, 0x9f, 0xbe, 0xf2, 0x40, 0x62, 0x44, 0x13, 0x05, 0xa0, 0x0a, 0x05, 0x61, + 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, 0x26, 0xca, 0x06, 0xce, 0x33, 0x07, 0xb6, 0x00, 0x93, 0x07, + 0x00, 0x08, 0xaa, 0x84, 0x2e, 0x84, 0x63, 0xf6, 0xe7, 0x00, 0x32, 0xc6, 0xef, 0xd0, 0x7f, 0xcd, + 0x32, 0x46, 0x37, 0x25, 0x01, 0x04, 0x13, 0x05, 0x05, 0x80, 0x22, 0x95, 0x62, 0x44, 0xf2, 0x40, + 0xa6, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x6f, 0xf0, 0x5f, 0xc2, 0x39, 0x71, 0x2a, 0xd6, 0x2e, 0xd4, + 0x32, 0xd2, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, + 0x06, 0x7a, 0x93, 0x85, 0x05, 0x7b, 0x13, 0x05, 0x45, 0x7b, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, + 0x1e, 0xd8, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, + 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xf0, 0xcf, 0xc8, 0xef, 0xe0, 0x8f, 0xd6, 0xf2, 0x50, 0xe2, 0x52, + 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, + 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, + 0x20, 0x30, 0x09, 0x65, 0x6f, 0x20, 0x00, 0x13, 0x09, 0x65, 0x6f, 0x20, 0x60, 0x13, 0x41, 0x11, + 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xd0, 0xbf, 0xc3, 0xdd, 0x37, 0xb7, 0x07, + 0x00, 0x07, 0xd8, 0x43, 0x83, 0x47, 0x64, 0x00, 0xbd, 0x46, 0x63, 0x85, 0xd7, 0x00, 0x61, 0x9b, + 0x9d, 0x8b, 0x5d, 0x8f, 0x93, 0x77, 0x77, 0xff, 0x03, 0x47, 0x74, 0x00, 0x83, 0x46, 0x44, 0x00, + 0xb2, 0x40, 0x0e, 0x07, 0x21, 0x8b, 0x5d, 0x8f, 0xfd, 0x77, 0xbd, 0x07, 0x7d, 0x8f, 0x83, 0x47, + 0x84, 0x00, 0x92, 0x07, 0x5d, 0x8f, 0xb7, 0x17, 0x80, 0xff, 0xfd, 0x17, 0x7d, 0x8f, 0x83, 0x47, + 0x54, 0x00, 0xa2, 0x07, 0xd5, 0x8f, 0xb2, 0x07, 0xb7, 0xf6, 0x7f, 0x00, 0xf5, 0x8f, 0xd9, 0x8f, + 0x37, 0x07, 0x80, 0xf8, 0x7d, 0x17, 0xf9, 0x8f, 0x03, 0x47, 0xa4, 0x00, 0xb7, 0x06, 0x80, 0x07, + 0x5e, 0x07, 0x75, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x00, 0x88, 0x7d, 0x17, 0xf9, 0x8f, 0x03, 0x47, + 0x94, 0x00, 0xb7, 0x06, 0x00, 0x78, 0x22, 0x44, 0x6e, 0x07, 0x75, 0x8f, 0xd9, 0x8f, 0x37, 0x07, + 0x00, 0x07, 0x5c, 0xc3, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x87, 0xf8, + 0x82, 0x80, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, + 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, + 0x13, 0x05, 0xa0, 0x0a, 0x89, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x89, 0x65, + 0x37, 0x35, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x85, 0xbb, 0x6f, 0xf0, 0x5f, 0x91, + 0x41, 0x11, 0xb7, 0x07, 0x08, 0x05, 0x22, 0xc4, 0x03, 0xa4, 0xc7, 0x20, 0x37, 0x07, 0x00, 0x04, + 0x06, 0xc6, 0x26, 0xc2, 0xb3, 0x76, 0xe4, 0x00, 0x91, 0xca, 0x37, 0x55, 0x10, 0x00, 0x23, 0xa6, + 0xe7, 0x20, 0xa5, 0x45, 0x13, 0x05, 0x85, 0x7b, 0xef, 0xf0, 0xef, 0xbb, 0xb7, 0x07, 0x80, 0x6b, + 0xe1, 0x8f, 0x95, 0xcb, 0x37, 0x07, 0x08, 0x05, 0x23, 0x26, 0xf7, 0x20, 0xb7, 0x07, 0x00, 0x68, + 0x7d, 0x8c, 0x93, 0x04, 0x50, 0x05, 0x11, 0xc8, 0x37, 0x55, 0x10, 0x00, 0x9d, 0x45, 0x13, 0x05, + 0x85, 0x7b, 0xef, 0xf0, 0x4f, 0xb9, 0xef, 0xd0, 0xdf, 0xb0, 0xb2, 0x40, 0x22, 0x44, 0x26, 0x85, + 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0xf8, 0x84, 0x43, + 0x13, 0x07, 0xa0, 0x0a, 0x63, 0x96, 0xe4, 0x00, 0x13, 0x07, 0x50, 0x05, 0x98, 0xc3, 0xe1, 0xbf, + 0x93, 0x04, 0xa0, 0x0a, 0xd9, 0xbf, 0x81, 0x47, 0xb7, 0x05, 0x08, 0x05, 0x13, 0x07, 0x00, 0x20, + 0xb3, 0x86, 0xb7, 0x00, 0x90, 0x42, 0xb3, 0x06, 0xf5, 0x00, 0x91, 0x07, 0x90, 0xc2, 0xe3, 0x99, + 0xe7, 0xfe, 0x6f, 0xf0, 0xff, 0xf5, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0x2a, 0x84, 0xef, 0xf0, + 0x1f, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa4, 0xe7, 0xf8, 0x8d, 0x47, + 0x33, 0x95, 0x87, 0x00, 0xb7, 0xb7, 0xaa, 0x02, 0x93, 0x87, 0xa7, 0xaa, 0x3d, 0x8d, 0xb7, 0x07, + 0x08, 0x05, 0x23, 0xa4, 0xa7, 0x20, 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, + 0x13, 0x05, 0x85, 0xb9, 0xef, 0xf0, 0xdf, 0x82, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, + 0x3f, 0xf1, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x9f, 0xef, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, + 0x47, 0xf8, 0x37, 0x07, 0x08, 0x05, 0x13, 0x05, 0x00, 0x20, 0xf9, 0x9b, 0x23, 0x22, 0xf7, 0x20, + 0xef, 0x10, 0x10, 0x74, 0xb2, 0x40, 0x39, 0x45, 0x41, 0x01, 0x6f, 0x10, 0x30, 0x75, 0x37, 0x37, + 0x20, 0x00, 0x13, 0x07, 0x47, 0xf8, 0x1c, 0x43, 0x93, 0xf7, 0xf7, 0xfd, 0x1c, 0xc3, 0x37, 0x07, + 0x08, 0x05, 0x23, 0x22, 0xf7, 0x20, 0x82, 0x80, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf8, + 0x1c, 0x43, 0x93, 0xe7, 0x07, 0x02, 0x1c, 0xc3, 0x37, 0x07, 0x08, 0x05, 0x23, 0x22, 0xf7, 0x20, + 0x82, 0x80, 0x33, 0x87, 0xc5, 0x00, 0xb7, 0x07, 0x08, 0x00, 0x63, 0x7c, 0xf7, 0x06, 0x01, 0x11, + 0x22, 0xcc, 0x26, 0xca, 0x4e, 0xc6, 0x06, 0xce, 0x4a, 0xc8, 0x93, 0xf4, 0x35, 0x00, 0xaa, 0x89, + 0x2e, 0x84, 0x13, 0x05, 0x50, 0x05, 0x9d, 0xec, 0x32, 0x89, 0xef, 0xf0, 0x5f, 0xe7, 0xb7, 0x37, + 0x20, 0x00, 0x03, 0xa7, 0x47, 0xf8, 0xb7, 0x06, 0x08, 0x05, 0xb7, 0x05, 0x00, 0x05, 0x13, 0x67, + 0x27, 0x00, 0x23, 0xa2, 0xe6, 0x20, 0x93, 0x87, 0x47, 0xf8, 0x0d, 0x47, 0x2e, 0x94, 0xb3, 0x06, + 0x99, 0x40, 0x63, 0x60, 0xd7, 0x02, 0x98, 0x43, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x05, 0xa0, 0x0a, + 0x23, 0xa2, 0xe7, 0x20, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, + 0x82, 0x80, 0xb3, 0x06, 0x94, 0x00, 0x90, 0x42, 0xb3, 0x86, 0x99, 0x00, 0x91, 0x04, 0x90, 0xc2, + 0xf9, 0xb7, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, 0xaa, 0x85, 0x11, 0x46, 0x68, 0x00, + 0x06, 0xce, 0xef, 0xf0, 0x1f, 0xf7, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x00, 0x32, 0x45, + 0xf2, 0x40, 0x05, 0x61, 0x82, 0x80, 0x01, 0x45, 0xe5, 0xbf, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xef, + 0xa7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, + 0x8d, 0xe3, 0xae, 0x84, 0xef, 0xf0, 0xbf, 0xdd, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, + 0x22, 0x44, 0xb2, 0x40, 0x23, 0xaa, 0x97, 0x20, 0x92, 0x44, 0x01, 0x45, 0x41, 0x01, 0x6f, 0xf0, + 0x9f, 0xe7, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x82, 0x80, 0x41, 0x11, + 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xaa, 0x84, 0x2e, 0x84, 0xef, 0xf0, 0x1f, 0xfb, 0x26, 0x85, + 0xef, 0xf0, 0x9f, 0xf8, 0x63, 0x09, 0x85, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, + 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xcd, 0xbf, 0x01, 0x11, 0x22, 0xcc, + 0x2e, 0xc6, 0x06, 0xce, 0x2a, 0x84, 0xef, 0xf0, 0x3f, 0xf6, 0xb2, 0x45, 0x63, 0x03, 0xb5, 0x02, + 0xfd, 0x57, 0x63, 0x1a, 0xf5, 0x00, 0x63, 0x8e, 0xa5, 0x00, 0x22, 0x85, 0x62, 0x44, 0xf2, 0x40, + 0x05, 0x61, 0x6f, 0xf0, 0xdf, 0xfa, 0x13, 0x05, 0x50, 0x05, 0xf2, 0x40, 0x62, 0x44, 0x05, 0x61, + 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xd5, 0xbf, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe0, 0xb7, 0x04, + 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0xf7, 0xf5, 0x1f, 0xaa, 0x84, 0x2e, 0x84, + 0x13, 0x05, 0x50, 0x05, 0x99, 0xef, 0xef, 0xf0, 0x9f, 0xd2, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, + 0x87, 0x20, 0x39, 0x45, 0xef, 0xf0, 0x3f, 0xdd, 0x26, 0x85, 0xef, 0xf0, 0xdf, 0xda, 0x13, 0x05, + 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, + 0x82, 0x80, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xb7, 0x07, + 0x08, 0x00, 0x63, 0xfb, 0xb7, 0x00, 0x81, 0x44, 0xf2, 0x40, 0x62, 0x44, 0x42, 0x49, 0xb2, 0x49, + 0x26, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x82, 0x80, 0x93, 0xf4, 0xf5, 0x1f, 0x2e, 0x84, 0xe5, 0xf4, + 0x2a, 0x89, 0xef, 0xf0, 0xdf, 0xcc, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x41, 0x45, + 0xef, 0xf0, 0x7f, 0xd7, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x17, 0xf5, 0xfc, 0x37, 0x34, 0x20, 0x00, + 0x13, 0x05, 0x44, 0xc9, 0xef, 0xf0, 0x3f, 0xd4, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x87, 0x07, 0x20, + 0x23, 0xa0, 0x07, 0x00, 0x91, 0x07, 0xe3, 0x9d, 0xe7, 0xfe, 0x93, 0x09, 0x44, 0xc9, 0x03, 0xd6, + 0xc9, 0x1f, 0x93, 0x07, 0xc0, 0x1d, 0x63, 0xfa, 0xc7, 0x00, 0x37, 0x55, 0x10, 0x00, 0x99, 0x45, + 0x13, 0x05, 0x85, 0x7b, 0xef, 0xf0, 0x2f, 0x87, 0x41, 0xbf, 0x93, 0x05, 0x44, 0xc9, 0x4a, 0x85, + 0xef, 0x20, 0xe0, 0x57, 0x83, 0xd4, 0xc9, 0x1f, 0x41, 0xb7, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe7, + 0xa7, 0x04, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, + 0x13, 0x05, 0x50, 0x05, 0x9d, 0xe7, 0xef, 0xf0, 0x9f, 0xc4, 0x85, 0x67, 0xb7, 0x04, 0x08, 0x05, + 0x93, 0x87, 0x97, 0x82, 0x23, 0xa2, 0xf4, 0x20, 0x23, 0xac, 0x84, 0x20, 0x39, 0x45, 0xef, 0xf0, + 0x9f, 0xce, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf8, 0x13, 0x05, 0xa0, 0x0a, 0x23, 0xa2, + 0xf4, 0x20, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, + 0x82, 0x80, 0x0d, 0x65, 0x01, 0x11, 0x13, 0x05, 0x05, 0x20, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, + 0x4a, 0xc8, 0x4e, 0xc6, 0xef, 0x10, 0x10, 0x45, 0x39, 0x45, 0xef, 0x10, 0x70, 0x46, 0x13, 0x05, + 0x80, 0x07, 0x37, 0x39, 0x20, 0x00, 0xef, 0xf0, 0xef, 0xbd, 0x93, 0x09, 0x49, 0xf8, 0x83, 0xa7, + 0x09, 0x00, 0x37, 0x04, 0x08, 0x05, 0x93, 0x04, 0x04, 0x20, 0xdc, 0xc0, 0xb7, 0x07, 0x46, 0x00, + 0x85, 0x07, 0xdc, 0xcc, 0x85, 0x67, 0x93, 0x87, 0x57, 0x86, 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, + 0xdc, 0xc0, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x25, 0xba, 0xef, 0xf0, 0x6f, 0xcd, 0xb7, 0x07, + 0x40, 0x08, 0x9c, 0xc8, 0xdc, 0x40, 0x01, 0x45, 0x13, 0x09, 0x49, 0xf8, 0x93, 0xe7, 0x07, 0x18, + 0x23, 0xa0, 0xf9, 0x00, 0xef, 0xf0, 0x7f, 0xf3, 0x93, 0x07, 0x04, 0x10, 0x98, 0x43, 0xb7, 0x67, + 0xa5, 0xf0, 0x93, 0x87, 0xf7, 0xa0, 0x63, 0x05, 0xf7, 0x02, 0x37, 0x55, 0x10, 0x00, 0x95, 0x45, + 0x13, 0x05, 0x85, 0x7b, 0xef, 0xe0, 0x3f, 0xf7, 0x41, 0x67, 0x7d, 0x17, 0x93, 0x07, 0x04, 0x18, + 0xb8, 0xd3, 0xf8, 0xd3, 0xb8, 0xd7, 0xf8, 0xd7, 0xb8, 0xdb, 0xf8, 0xdb, 0xb8, 0xdf, 0xf8, 0xdf, + 0x51, 0x45, 0xef, 0xf0, 0x5f, 0xc1, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x91, 0x8b, + 0x91, 0xeb, 0x37, 0x55, 0x10, 0x00, 0x91, 0x45, 0x13, 0x05, 0x85, 0x7b, 0xef, 0xe0, 0xbf, 0xf3, + 0xef, 0xd0, 0x2f, 0xeb, 0xb7, 0x07, 0x08, 0x05, 0x37, 0x07, 0x40, 0x00, 0x23, 0xa6, 0xe7, 0x20, + 0x03, 0x27, 0x09, 0x00, 0xf2, 0x40, 0x62, 0x44, 0x23, 0xa2, 0xe7, 0x20, 0xd2, 0x44, 0x42, 0x49, + 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, 0x85, 0x67, 0x37, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0x86, + 0x23, 0x22, 0xf7, 0xf8, 0x37, 0x37, 0x20, 0x00, 0x93, 0x07, 0x50, 0x05, 0x23, 0x24, 0xf7, 0xf8, + 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xf8, 0x6f, 0xf0, 0xbf, 0xee, 0xb7, 0x07, 0x08, 0x00, + 0x63, 0xe0, 0xa7, 0x06, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xc6, 0x26, 0xc2, + 0x2a, 0x84, 0x13, 0x05, 0x50, 0x05, 0xa1, 0xe3, 0xae, 0x84, 0xef, 0xf0, 0x5f, 0xad, 0xb7, 0x07, + 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x01, 0x47, 0x93, 0x06, 0x00, 0x20, 0xb3, 0x85, 0xe4, 0x00, + 0x8c, 0x41, 0x33, 0x06, 0xf7, 0x00, 0x11, 0x07, 0x0c, 0xc2, 0xe3, 0x19, 0xd7, 0xfe, 0x7d, 0x57, + 0x93, 0x87, 0x07, 0x20, 0xf8, 0xc3, 0xb8, 0xc7, 0xf8, 0xc7, 0xb8, 0xcb, 0x29, 0x45, 0xef, 0xf0, + 0x9f, 0xb5, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, + 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xaa, 0x85, 0x37, 0x05, 0x08, 0x05, 0x41, 0x46, 0x13, 0x05, + 0x05, 0x26, 0x6f, 0xf0, 0x8f, 0xd5, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xef, 0xa7, 0x0a, 0x01, 0x11, + 0x26, 0xca, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, + 0x56, 0xc2, 0xaa, 0x84, 0x13, 0x05, 0x50, 0x05, 0xd9, 0xe7, 0x93, 0x07, 0xc0, 0x1d, 0x32, 0x89, + 0x63, 0xe3, 0xc7, 0x08, 0xb6, 0x89, 0x37, 0x34, 0x20, 0x00, 0x2e, 0x8a, 0xef, 0xf0, 0x3f, 0xa4, + 0x13, 0x06, 0x00, 0x20, 0x81, 0x45, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x00, 0x38, 0x4a, 0x86, + 0xd2, 0x85, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x80, 0x33, 0x4e, 0x85, 0xef, 0xf0, 0xbf, 0xf9, + 0x93, 0x0a, 0x44, 0xc9, 0xb7, 0x07, 0x08, 0x05, 0x23, 0x9e, 0x2a, 0x1f, 0x13, 0x07, 0x44, 0xc9, + 0x93, 0x86, 0x07, 0x20, 0x10, 0x43, 0x11, 0x07, 0x90, 0xc3, 0x91, 0x07, 0xe3, 0x9c, 0xd7, 0xfe, + 0x13, 0x06, 0x00, 0x20, 0x81, 0x45, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x00, 0x34, 0xb7, 0x07, + 0x08, 0x05, 0x23, 0xac, 0x97, 0x20, 0x31, 0x45, 0xef, 0xf0, 0xff, 0xa9, 0x93, 0x07, 0xa0, 0x0a, + 0x63, 0x0b, 0xf5, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x7b, 0x8d, 0x45, 0xef, 0xe0, + 0x9f, 0xdc, 0x13, 0x05, 0x50, 0x05, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, + 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x07, + 0x08, 0x00, 0x63, 0xeb, 0xa7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0xf5, 0x1f, + 0x2a, 0x84, 0x89, 0xef, 0xef, 0xf0, 0xbf, 0x99, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, + 0x22, 0x44, 0xb2, 0x40, 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0xff, 0xa3, 0xb2, 0x40, 0x22, 0x44, + 0x13, 0x05, 0x50, 0x05, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, + 0x22, 0xc4, 0x06, 0xc6, 0x37, 0x04, 0x08, 0x05, 0x23, 0x2c, 0xa4, 0x20, 0xef, 0xf0, 0x3f, 0x96, + 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa4, 0xe7, 0xf8, 0xb7, 0xb7, 0xaa, 0x02, + 0x93, 0x87, 0x67, 0xaa, 0xb2, 0x40, 0x23, 0x24, 0xf4, 0x20, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, + 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xbf, 0x93, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, + 0x23, 0xa4, 0xe7, 0xf8, 0xb2, 0x40, 0xb7, 0xb7, 0xa6, 0x02, 0x37, 0x07, 0x08, 0x05, 0x93, 0x87, + 0xa7, 0xaa, 0x23, 0x24, 0xf7, 0x20, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x3e, 0xcc, 0xb7, 0x07, + 0x08, 0x05, 0x3a, 0xce, 0x03, 0xa7, 0xc7, 0x20, 0x36, 0xd0, 0xb7, 0x06, 0x40, 0x00, 0x06, 0xde, + 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x42, 0xca, 0x46, 0xc8, + 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0x75, 0x8f, 0x05, 0xcf, 0x23, 0xa6, 0xd7, 0x20, + 0x13, 0x07, 0xa0, 0x0a, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0xe7, 0xf8, 0xf2, 0x50, 0xe2, 0x52, + 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, + 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, + 0x20, 0x30, 0x03, 0xa7, 0xc7, 0x20, 0xb7, 0x06, 0x00, 0x08, 0x37, 0x55, 0x10, 0x00, 0x75, 0x8f, + 0x0d, 0xc3, 0x23, 0xa6, 0xd7, 0x20, 0x85, 0x45, 0x13, 0x05, 0x85, 0x7b, 0xef, 0xe0, 0xbf, 0xc8, + 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf8, 0xef, 0xd0, 0x5f, 0xce, + 0x75, 0xb7, 0x89, 0x45, 0x13, 0x05, 0x85, 0x7b, 0xef, 0xe0, 0xff, 0xc6, 0xb7, 0x07, 0x02, 0x00, + 0x73, 0xb0, 0x47, 0x30, 0xe5, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa8, + 0xe7, 0xf8, 0x82, 0x80, 0x99, 0x47, 0x63, 0x05, 0xf5, 0x02, 0x9d, 0x47, 0x63, 0x0b, 0xf5, 0x00, + 0x95, 0x47, 0x63, 0x15, 0xf5, 0x02, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xf7, 0xf7, 0xf7, + 0x29, 0xa8, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa8, 0xe7, 0xf8, 0x82, 0x80, + 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xe7, 0x07, 0x08, 0x7c, 0xc3, 0x82, 0x80, 0xb7, 0x37, + 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf9, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, 0xf7, 0x00, 0x37, 0x07, + 0x00, 0x02, 0x7c, 0x43, 0x93, 0xe7, 0x07, 0x08, 0x7c, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, + 0x03, 0xa7, 0x07, 0xf9, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, 0xf7, 0x00, 0x37, 0x07, 0x00, 0x02, + 0x7c, 0x43, 0x93, 0xf7, 0xf7, 0xf7, 0x7c, 0xc3, 0x82, 0x80, 0x39, 0x71, 0x2a, 0xd6, 0x37, 0x55, + 0x10, 0x00, 0x2e, 0xd4, 0x13, 0x05, 0xc5, 0x7b, 0x85, 0x45, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, + 0x1e, 0xd8, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, + 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0x1f, 0xbb, 0xef, 0xd0, 0x7f, 0xc1, 0xf2, 0x50, + 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, + 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, + 0x73, 0x00, 0x20, 0x30, 0x39, 0x71, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, + 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, + 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xf3, 0x25, 0x20, 0x34, 0xc1, 0x67, 0x37, 0x55, 0x10, 0x00, + 0xdd, 0x8d, 0x13, 0x05, 0xc5, 0x7b, 0xef, 0xe0, 0x1f, 0xb5, 0xef, 0xd0, 0x7f, 0xbb, 0x01, 0xa0, + 0x39, 0x71, 0x2a, 0xd6, 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, 0x13, 0x05, 0xc5, 0x7b, 0x89, 0x45, + 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, + 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0xbf, 0xb1, + 0xef, 0xd0, 0x1f, 0xb8, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, + 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, + 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x07, 0x01, 0x01, 0xb7, 0x07, + 0x00, 0x01, 0x13, 0x07, 0x17, 0x10, 0x98, 0xd3, 0x37, 0x07, 0x03, 0x04, 0x09, 0x07, 0xd8, 0xd3, + 0x13, 0x07, 0x50, 0x60, 0x98, 0xd7, 0x37, 0x17, 0x09, 0x00, 0x13, 0x07, 0x77, 0x80, 0xd8, 0xd7, + 0x37, 0x17, 0x0b, 0x0b, 0x13, 0x07, 0xa7, 0xa0, 0x98, 0xdb, 0x37, 0x17, 0x0c, 0x00, 0x13, 0x07, + 0xb7, 0xc0, 0xd8, 0xdb, 0x37, 0x17, 0x0f, 0x00, 0x13, 0x07, 0xd7, 0xe0, 0x98, 0xdf, 0x05, 0x67, + 0xd8, 0xdf, 0xb7, 0x17, 0xff, 0x7f, 0x93, 0x87, 0x07, 0x80, 0x73, 0xa0, 0x47, 0x30, 0xa1, 0x47, + 0x73, 0xa0, 0x07, 0x30, 0x82, 0x80, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x40, 0x00, 0x73, 0xb0, + 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, + 0x80, 0x00, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, + 0x3e, 0xc6, 0xb7, 0x07, 0x00, 0x04, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, + 0x20, 0x30, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x00, 0x20, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, + 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x05, 0x65, 0x6f, 0x10, 0xc0, 0x69, 0x05, 0x65, 0x6f, 0x10, + 0x20, 0x6a, 0x01, 0x11, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x06, 0xce, 0x26, 0xca, 0x52, 0xc4, + 0x56, 0xc2, 0x9d, 0x47, 0x2a, 0x84, 0xae, 0x89, 0x32, 0x89, 0x63, 0xd4, 0xc7, 0x00, 0xef, 0xd0, + 0x4f, 0x99, 0xef, 0xf0, 0x5f, 0xfd, 0xb7, 0x07, 0x01, 0x07, 0x18, 0x40, 0xdc, 0x43, 0x93, 0x06, + 0xf0, 0x0f, 0x63, 0x05, 0xd7, 0x00, 0xf1, 0x9b, 0x0d, 0x8b, 0xd9, 0x8f, 0x13, 0xf7, 0xb7, 0xff, + 0x83, 0x47, 0x44, 0x00, 0x81, 0x44, 0x31, 0x4a, 0x8a, 0x07, 0x91, 0x8b, 0xd9, 0x8f, 0x37, 0x07, + 0x01, 0x07, 0x5c, 0xc3, 0xb7, 0x1a, 0x01, 0x07, 0x63, 0xcf, 0x24, 0x03, 0x14, 0x40, 0x05, 0x47, + 0xad, 0x47, 0x63, 0x9e, 0xe6, 0x00, 0x83, 0x46, 0x44, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0xbd, 0x47, + 0x63, 0x97, 0xe6, 0x00, 0x14, 0x44, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2a, 0xd7, 0xf8, 0xf2, 0x40, + 0x62, 0x44, 0x37, 0x07, 0x01, 0x07, 0x5c, 0xc7, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, + 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xb3, 0x85, 0x44, 0x03, 0x13, 0x95, 0x44, 0x00, 0x31, 0x46, + 0x56, 0x95, 0x85, 0x04, 0xce, 0x95, 0xef, 0xf0, 0x4f, 0x87, 0x7d, 0xb7, 0x1d, 0x71, 0x3e, 0xda, + 0xb7, 0x07, 0x01, 0x07, 0xa2, 0xc6, 0x80, 0x47, 0x86, 0xce, 0x96, 0xcc, 0x9a, 0xca, 0x9e, 0xc8, + 0xaa, 0xc4, 0xae, 0xc2, 0xb2, 0xc0, 0x36, 0xde, 0x3a, 0xdc, 0x42, 0xd8, 0x46, 0xd6, 0x72, 0xd4, + 0x76, 0xd2, 0x7a, 0xd0, 0x7e, 0xce, 0x93, 0x77, 0xb4, 0x00, 0x95, 0xc7, 0xb7, 0x07, 0x00, 0x40, + 0x73, 0xb0, 0x47, 0x30, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, + 0xa2, 0x86, 0x13, 0x06, 0x06, 0x7c, 0x93, 0x85, 0x85, 0x7c, 0x13, 0x05, 0x85, 0x77, 0xef, 0xe0, + 0x3f, 0x8c, 0xef, 0xd0, 0xff, 0x99, 0x93, 0x77, 0x44, 0x00, 0x99, 0xcf, 0xb7, 0x37, 0x20, 0x00, + 0x83, 0xa7, 0x47, 0xf9, 0x91, 0xcb, 0x6c, 0x00, 0x28, 0x00, 0x82, 0x97, 0x22, 0x47, 0xb7, 0x07, + 0x01, 0x07, 0x98, 0xcb, 0x32, 0x47, 0xd8, 0xcb, 0xb7, 0x07, 0x01, 0x07, 0x80, 0xc7, 0x36, 0x44, + 0xf6, 0x40, 0xe6, 0x42, 0x56, 0x43, 0xc6, 0x43, 0x26, 0x45, 0x96, 0x45, 0x06, 0x46, 0xf2, 0x56, + 0x62, 0x57, 0xd2, 0x57, 0x42, 0x58, 0xb2, 0x58, 0x22, 0x5e, 0x92, 0x5e, 0x02, 0x5f, 0xf2, 0x4f, + 0x25, 0x61, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x07, 0x02, 0x04, 0xdc, 0x47, 0x13, 0x05, 0xa0, 0x0a, + 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x82, 0x80, 0x13, 0x05, 0x00, 0x08, + 0x6f, 0x10, 0x40, 0x52, 0x13, 0x05, 0x00, 0x08, 0x6f, 0x10, 0x80, 0x52, 0x41, 0x11, 0x22, 0xc4, + 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x07, 0xd0, 0x79, 0x37, 0x04, 0x02, 0x04, 0x5c, 0xc4, 0x85, 0x44, + 0x95, 0x65, 0x37, 0x35, 0x10, 0x00, 0x04, 0xc4, 0x93, 0x85, 0x05, 0xe2, 0x13, 0x05, 0x65, 0x6e, + 0xef, 0xe0, 0xdf, 0xce, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x13, 0xf5, 0x02, 0x54, 0x44, 0x63, 0x82, + 0x96, 0x02, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, + 0xc6, 0x7c, 0x93, 0x85, 0x45, 0x7d, 0x13, 0x05, 0x45, 0x75, 0xef, 0xe0, 0x6f, 0xff, 0x13, 0x05, + 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, + 0xef, 0xf0, 0xdf, 0xf8, 0xb2, 0x40, 0xb7, 0x07, 0x02, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x41, 0x01, + 0x82, 0x80, 0x41, 0x11, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x22, 0xc4, 0x26, 0xc2, + 0x23, 0xac, 0xe7, 0xf8, 0x06, 0xc6, 0x37, 0x07, 0x02, 0x02, 0x89, 0x46, 0x54, 0xc7, 0x13, 0x84, + 0x87, 0xf9, 0x93, 0x04, 0x50, 0x05, 0xef, 0xe0, 0x5f, 0xc7, 0x1c, 0x40, 0xe3, 0x9d, 0x97, 0xfe, + 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x02, 0x02, 0xc8, 0xcb, + 0x05, 0x47, 0xd8, 0xc7, 0xd8, 0x53, 0x69, 0x8f, 0x63, 0x1e, 0xa7, 0x00, 0xd4, 0x57, 0x7d, 0x55, + 0xf9, 0x8e, 0x91, 0xea, 0x94, 0x57, 0x75, 0x8f, 0x19, 0xe7, 0x88, 0x47, 0x05, 0x89, 0x33, 0x05, + 0xa0, 0x40, 0x82, 0x80, 0x7d, 0x55, 0x82, 0x80, 0x41, 0x45, 0x6f, 0x10, 0x60, 0x44, 0x41, 0x45, + 0x6f, 0x10, 0x40, 0x43, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, 0x2a, 0xc6, 0xef, 0xf0, 0x3f, 0xff, + 0x13, 0x07, 0x50, 0x05, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0xe7, 0xf8, 0x37, 0x04, 0x02, 0x02, + 0xa1, 0x47, 0x5c, 0xc4, 0x32, 0x45, 0x85, 0x47, 0x1c, 0xc8, 0x93, 0x07, 0x10, 0x40, 0x5c, 0xc0, + 0xef, 0xf0, 0xbf, 0xf9, 0xef, 0xf0, 0xff, 0xf5, 0x23, 0x22, 0x04, 0x00, 0x62, 0x44, 0xf2, 0x40, + 0x05, 0x61, 0x6f, 0xf0, 0x7f, 0xfb, 0x41, 0x11, 0x3a, 0xc6, 0x37, 0x07, 0x02, 0x02, 0x3e, 0xc4, + 0x1c, 0x47, 0x1c, 0xc7, 0x85, 0x8b, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, + 0x23, 0xac, 0xe7, 0xf8, 0x32, 0x47, 0xa2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x37, + 0x20, 0x00, 0x03, 0xa5, 0xc7, 0xf9, 0x82, 0x80, 0xb7, 0x27, 0x00, 0x06, 0x9c, 0x47, 0x05, 0x47, + 0x13, 0x05, 0xa0, 0x0a, 0x9d, 0x8b, 0xfd, 0x17, 0x63, 0x74, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, + 0x82, 0x80, 0x37, 0x27, 0x00, 0x06, 0x1c, 0x47, 0x85, 0x46, 0x13, 0x05, 0xa0, 0x0a, 0x9d, 0x8b, + 0x63, 0x89, 0xd7, 0x00, 0x1c, 0x47, 0x09, 0x47, 0x9d, 0x8b, 0x63, 0x84, 0xe7, 0x00, 0x13, 0x05, + 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, + 0x99, 0xc3, 0xef, 0xc0, 0x1f, 0xe9, 0x89, 0x67, 0x63, 0x64, 0xf4, 0x00, 0xef, 0xc0, 0x7f, 0xe8, + 0x89, 0x65, 0x37, 0x45, 0x10, 0x00, 0x13, 0x05, 0x25, 0x88, 0x93, 0x85, 0x05, 0x71, 0xef, 0xe0, + 0x3f, 0xc2, 0x37, 0x05, 0x00, 0x06, 0x2a, 0x94, 0x08, 0x40, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, + 0x82, 0x80, 0x05, 0x65, 0xb7, 0x37, 0x20, 0x00, 0x41, 0x11, 0x13, 0x07, 0x50, 0x05, 0x13, 0x05, + 0x05, 0x80, 0x23, 0xae, 0xe7, 0xf8, 0x06, 0xc6, 0xef, 0x10, 0xc0, 0x32, 0xef, 0xf0, 0xdf, 0xf6, + 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, + 0x85, 0x7d, 0xef, 0xe0, 0x4f, 0xeb, 0xef, 0xc0, 0xdf, 0xe2, 0xb7, 0x07, 0x46, 0x00, 0xb2, 0x40, + 0x37, 0x27, 0x00, 0x06, 0x85, 0x07, 0x5c, 0xcf, 0x85, 0x47, 0x5c, 0xc7, 0x41, 0x01, 0x82, 0x80, + 0x39, 0x71, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x00, 0x03, 0x93, 0x85, 0xc5, 0x7d, 0x0a, 0x85, + 0x22, 0xdc, 0x26, 0xda, 0x4a, 0xd8, 0x06, 0xde, 0x0a, 0x84, 0xef, 0x10, 0x50, 0x39, 0x7d, 0x59, + 0xb7, 0x24, 0x00, 0x06, 0x08, 0x40, 0x19, 0xc9, 0xef, 0xf0, 0xdf, 0xf4, 0x63, 0x13, 0x25, 0x01, + 0x08, 0x44, 0x5c, 0x40, 0x31, 0x04, 0xa6, 0x97, 0x88, 0xc3, 0xed, 0xb7, 0xf2, 0x50, 0x62, 0x54, + 0xd2, 0x54, 0x42, 0x59, 0x21, 0x61, 0x82, 0x80, 0x37, 0x27, 0x00, 0x06, 0x1c, 0x47, 0x85, 0x46, + 0x9d, 0x8b, 0x63, 0x89, 0xd7, 0x02, 0x41, 0x11, 0x06, 0xc6, 0x89, 0x65, 0x37, 0x45, 0x10, 0x00, + 0x14, 0xcb, 0x13, 0x05, 0x85, 0x86, 0x93, 0x85, 0x05, 0x71, 0xef, 0xe0, 0x7f, 0xb5, 0xb7, 0x27, + 0x00, 0x06, 0x09, 0x47, 0x98, 0xcb, 0x05, 0x65, 0xb2, 0x40, 0x13, 0x05, 0x05, 0x80, 0x41, 0x01, + 0x6f, 0x10, 0x00, 0x28, 0xb7, 0x27, 0x00, 0x06, 0x09, 0x47, 0x05, 0x65, 0x98, 0xcb, 0x13, 0x05, + 0x05, 0x80, 0xfd, 0xb7, 0x05, 0x65, 0x41, 0x11, 0x13, 0x05, 0x05, 0x80, 0x06, 0xc6, 0xef, 0x10, + 0x60, 0x25, 0xb2, 0x40, 0xb7, 0x27, 0x00, 0x06, 0x21, 0x47, 0x98, 0xcb, 0x41, 0x01, 0x82, 0x80, + 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0xaa, 0x84, 0xef, 0xf0, 0xbf, 0xeb, 0x2a, 0x84, + 0x6d, 0x2a, 0x13, 0x75, 0xf5, 0x07, 0xef, 0xe0, 0x7f, 0xa1, 0x26, 0x85, 0xef, 0xf0, 0x9f, 0xea, + 0x63, 0x05, 0xa4, 0x00, 0xef, 0xc0, 0xff, 0xd3, 0x01, 0x45, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, + 0x41, 0x01, 0x82, 0x80, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x06, 0xd6, + 0x52, 0xcc, 0xaa, 0x89, 0x2e, 0x89, 0x93, 0x74, 0xc6, 0xff, 0x01, 0x44, 0x33, 0x8a, 0x89, 0x00, + 0x33, 0x05, 0x89, 0x00, 0x63, 0x1a, 0x94, 0x00, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, + 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0xef, 0xf0, 0x9f, 0xf9, 0x2a, 0xc6, 0x11, 0x46, + 0x6c, 0x00, 0x52, 0x85, 0xef, 0x10, 0xb0, 0x28, 0x11, 0x04, 0xc9, 0xbf, 0x41, 0x11, 0x06, 0xc6, + 0xef, 0xf0, 0x1f, 0xf8, 0x2a, 0x87, 0x85, 0x46, 0x01, 0x45, 0x89, 0x45, 0x01, 0xe7, 0xb2, 0x40, + 0x41, 0x01, 0x82, 0x80, 0x93, 0x77, 0xf7, 0x00, 0x01, 0x46, 0x81, 0xef, 0x63, 0xd3, 0xc5, 0x00, + 0xb6, 0x87, 0x5d, 0x8d, 0x86, 0x06, 0x13, 0x75, 0xf5, 0x0f, 0x93, 0xf6, 0xf6, 0x0f, 0x11, 0x83, + 0xf1, 0xbf, 0x13, 0xf8, 0x17, 0x00, 0x85, 0x83, 0x42, 0x96, 0x93, 0xf7, 0xf7, 0x0f, 0xf1, 0xbf, + 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0xae, 0x84, + 0x99, 0xc3, 0xef, 0xc0, 0x1f, 0xc9, 0x89, 0x67, 0x63, 0x64, 0xf4, 0x00, 0xef, 0xc0, 0x7f, 0xc8, + 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xae, 0xe7, 0xf8, 0xb7, 0x27, 0x00, 0x06, + 0x84, 0xcf, 0xc0, 0xcb, 0x22, 0x44, 0xb2, 0x40, 0x92, 0x44, 0x11, 0x47, 0x98, 0xcb, 0x89, 0x65, + 0x37, 0x45, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0xe5, 0x85, 0x41, 0x01, 0x6f, 0xe0, + 0x3f, 0xa0, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xaa, 0x84, 0x2e, 0x84, 0xef, 0xf0, + 0x3f, 0xfa, 0x26, 0x85, 0xef, 0xf0, 0x1f, 0xda, 0x63, 0x09, 0x85, 0x00, 0x13, 0x05, 0x50, 0x05, + 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xcd, 0xbf, + 0x39, 0x71, 0x3a, 0xce, 0x37, 0x27, 0x00, 0x06, 0x3e, 0xcc, 0x1c, 0x47, 0x06, 0xde, 0x16, 0xdc, + 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, + 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xa1, 0x8b, 0x85, 0xcf, 0xa1, 0x47, 0x1c, 0xc7, + 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xae, 0xe7, 0xf8, 0xf2, 0x50, 0xe2, 0x52, + 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, + 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, + 0x20, 0x30, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x85, 0x7d, 0xef, 0xe0, 0xaf, 0xc3, + 0xef, 0xd0, 0x0f, 0xca, 0xe1, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa0, 0xa7, 0xfa, 0x05, 0x47, + 0xb7, 0x37, 0x20, 0x00, 0x23, 0x82, 0xe7, 0xfa, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xc7, + 0x47, 0xfa, 0x41, 0x11, 0x06, 0xc6, 0x99, 0xe3, 0xef, 0xc0, 0xbf, 0xb8, 0xb7, 0x37, 0x20, 0x00, + 0x93, 0x87, 0x07, 0xfa, 0x88, 0x43, 0x37, 0x67, 0x19, 0x00, 0x13, 0x07, 0xd7, 0x60, 0x33, 0x05, + 0xe5, 0x02, 0x37, 0xf7, 0x6e, 0x3c, 0xb2, 0x40, 0x13, 0x07, 0xf7, 0x35, 0x3a, 0x95, 0x88, 0xc3, + 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0xe9, 0x98, 0x43, 0x94, 0x47, + 0xdc, 0x43, 0x18, 0x4f, 0x13, 0x05, 0xa0, 0x0a, 0x75, 0x8f, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, + 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0xe9, 0x88, 0xc3, 0x37, 0x45, + 0x10, 0x00, 0x13, 0x07, 0x00, 0x10, 0x93, 0x05, 0x80, 0x3e, 0x13, 0x05, 0x45, 0xbe, 0x23, 0xa2, + 0x07, 0x00, 0x98, 0xc7, 0x6f, 0xe0, 0x8f, 0xff, 0x37, 0x07, 0x01, 0x02, 0x5c, 0x43, 0xb7, 0x06, + 0x05, 0x00, 0xd5, 0x8f, 0x5c, 0xc3, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, + 0xb7, 0x37, 0x00, 0x08, 0x37, 0x05, 0x08, 0x00, 0x63, 0x0c, 0xf4, 0x00, 0xb7, 0x27, 0x00, 0x08, + 0x37, 0x05, 0x04, 0x00, 0x63, 0x06, 0xf4, 0x00, 0xef, 0xc0, 0xbf, 0xae, 0x37, 0x05, 0x08, 0x00, + 0xef, 0x00, 0x50, 0x7c, 0x5c, 0x5c, 0x22, 0x85, 0xb2, 0x40, 0x93, 0xe7, 0x37, 0x00, 0x5c, 0xdc, + 0x23, 0x2c, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0xdf, 0xf8, 0xfd, 0x77, 0x41, 0x11, + 0xfd, 0x17, 0x22, 0xc4, 0x06, 0xc6, 0xe9, 0x8f, 0x37, 0x27, 0x00, 0x08, 0x2a, 0x84, 0x63, 0x84, + 0xe7, 0x00, 0xef, 0xc0, 0x1f, 0xab, 0x5c, 0x5c, 0x37, 0x05, 0x04, 0x00, 0xf5, 0x9b, 0x5c, 0xdc, + 0xb7, 0x27, 0x00, 0x08, 0x63, 0x04, 0xf4, 0x00, 0x37, 0x05, 0x08, 0x00, 0x22, 0x44, 0xb2, 0x40, + 0x41, 0x01, 0x6f, 0x00, 0xf0, 0x77, 0x39, 0x71, 0x22, 0xdc, 0x26, 0xda, 0x4a, 0xd8, 0x06, 0xde, + 0x4e, 0xd6, 0x52, 0xd4, 0x56, 0xd2, 0x5a, 0xd0, 0x5e, 0xce, 0x62, 0xcc, 0xaa, 0x84, 0x2e, 0x89, + 0x32, 0x84, 0x99, 0xe1, 0xef, 0xc0, 0xff, 0xa6, 0xfd, 0x77, 0xfd, 0x17, 0xe5, 0x8f, 0x37, 0x27, + 0x00, 0x08, 0x63, 0x84, 0xe7, 0x00, 0xef, 0xc0, 0xdf, 0xa5, 0xb7, 0x39, 0x20, 0x00, 0x93, 0x89, + 0x49, 0xe9, 0x85, 0x4a, 0x37, 0x4b, 0x10, 0x00, 0x93, 0x0b, 0xa0, 0x0a, 0x11, 0x4c, 0x15, 0xe4, + 0x9c, 0x4c, 0x37, 0x07, 0x11, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x99, 0xc3, 0x13, 0x05, + 0x50, 0x05, 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, 0x5a, + 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, 0x21, 0x61, 0x82, 0x80, 0x93, 0x05, 0x80, 0x3e, 0x13, 0x05, + 0x4b, 0xbe, 0x23, 0xa0, 0x99, 0x00, 0x23, 0xa2, 0x59, 0x01, 0x23, 0xa4, 0x59, 0x01, 0xef, 0xe0, + 0xef, 0xed, 0xe3, 0x16, 0x75, 0xfd, 0xdc, 0x50, 0x22, 0x8a, 0x3e, 0xc6, 0x63, 0x73, 0x8c, 0x00, + 0x11, 0x4a, 0x4a, 0x85, 0x52, 0x86, 0x6c, 0x00, 0xef, 0x10, 0x60, 0x78, 0x52, 0x99, 0x33, 0x04, + 0x44, 0x41, 0x71, 0xbf, 0x41, 0x11, 0x37, 0x05, 0x02, 0x00, 0x06, 0xc6, 0xef, 0x00, 0x90, 0x6b, + 0xb2, 0x40, 0xb7, 0x17, 0x00, 0x08, 0x37, 0x07, 0x07, 0x00, 0x98, 0xd3, 0x13, 0x05, 0x40, 0x1f, + 0x41, 0x01, 0x6f, 0xe0, 0x2f, 0xe4, 0xb7, 0x17, 0x00, 0x08, 0x23, 0xa0, 0x07, 0x02, 0x37, 0x05, + 0x02, 0x00, 0x6f, 0x00, 0xf0, 0x69, 0x39, 0x71, 0x3e, 0xcc, 0xb7, 0x17, 0x00, 0x08, 0x3a, 0xce, + 0x98, 0x57, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, + 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0x05, 0x8b, + 0x05, 0xcb, 0x98, 0x57, 0x13, 0x67, 0x17, 0x00, 0x98, 0xd7, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, + 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, + 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, + 0x98, 0x57, 0x09, 0x8b, 0x09, 0xc7, 0x98, 0x57, 0x13, 0x67, 0x27, 0x00, 0xf1, 0xb7, 0x98, 0x57, + 0x11, 0x8b, 0x09, 0xc7, 0x98, 0x57, 0x13, 0x67, 0x47, 0x00, 0x7d, 0xbf, 0xb7, 0x07, 0x00, 0x01, + 0x73, 0xb0, 0x47, 0x30, 0xef, 0xd0, 0xcf, 0xa1, 0x4d, 0xbf, 0x37, 0x07, 0x00, 0x02, 0x5c, 0x4f, + 0xb7, 0x36, 0x20, 0x00, 0x13, 0xf6, 0x77, 0x00, 0xe1, 0x9b, 0x23, 0xa4, 0xc6, 0xfa, 0x93, 0xe7, + 0x47, 0x00, 0x5c, 0xcf, 0x1c, 0x4f, 0xf9, 0x9b, 0x1c, 0xcf, 0x82, 0x80, 0x41, 0x11, 0x26, 0xc2, + 0xb7, 0x04, 0x00, 0x02, 0x22, 0xc4, 0xc0, 0x4c, 0x9c, 0x4c, 0x06, 0xc6, 0x13, 0x05, 0x80, 0x07, + 0x93, 0xe7, 0x17, 0x00, 0x9c, 0xcc, 0xef, 0xe0, 0xef, 0xd6, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, + 0x87, 0xfa, 0x61, 0x98, 0xb2, 0x40, 0x5d, 0x8c, 0xc0, 0xcc, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, + 0x82, 0x80, 0x13, 0x17, 0x05, 0x01, 0x93, 0x17, 0x85, 0x01, 0xba, 0x97, 0x13, 0x17, 0x85, 0x00, + 0xba, 0x97, 0x3e, 0x95, 0xb7, 0x07, 0x00, 0x04, 0x88, 0xd3, 0xc8, 0xd3, 0x88, 0xd7, 0xc8, 0xd7, + 0x88, 0xdb, 0xc8, 0xdb, 0x88, 0xdf, 0xc8, 0xdf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, + 0x00, 0x08, 0x98, 0xd3, 0x23, 0xa2, 0x07, 0x02, 0x23, 0xa4, 0x07, 0x02, 0x23, 0xa6, 0x07, 0x02, + 0x23, 0xa8, 0x07, 0x02, 0x23, 0xaa, 0x07, 0x02, 0x23, 0xac, 0x07, 0x02, 0x23, 0xae, 0x07, 0x02, + 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x07, 0xeb, 0x82, 0x80, 0xaa, 0x85, 0x37, 0x05, + 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0x6f, 0xe0, 0x0f, 0xfd, 0xb7, 0x37, + 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa8, 0xe7, 0xea, 0xb7, 0x07, 0x00, 0x04, 0xc8, 0xc3, + 0x13, 0x07, 0x90, 0x02, 0x85, 0x65, 0x37, 0x45, 0x10, 0x00, 0x98, 0xc7, 0x93, 0x85, 0x85, 0x38, + 0x13, 0x05, 0x25, 0xec, 0x6f, 0xe0, 0x8f, 0xd1, 0x41, 0x11, 0x22, 0xc4, 0x01, 0x45, 0x37, 0x34, + 0x20, 0x00, 0x06, 0xc6, 0x13, 0x04, 0x04, 0xea, 0xef, 0xf0, 0xbf, 0xf5, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0xfb, 0x48, 0x44, 0xb7, 0x07, 0x02, 0x00, 0x95, 0x07, + 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0xbf, 0xfa, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x05, + 0xef, 0xf0, 0xff, 0xf9, 0x48, 0x44, 0xb7, 0x07, 0x00, 0x10, 0x99, 0x07, 0x7e, 0x05, 0x5d, 0x8d, + 0xef, 0xf0, 0xff, 0xf8, 0x48, 0x44, 0xb7, 0x07, 0x01, 0x10, 0x99, 0x07, 0x7e, 0x05, 0x5d, 0x8d, + 0xef, 0xf0, 0xff, 0xf7, 0x22, 0x44, 0xb2, 0x40, 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0xf7, + 0x7d, 0x47, 0x63, 0x7e, 0xb7, 0x04, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, + 0x13, 0x05, 0x05, 0x02, 0x6f, 0xe0, 0x6f, 0xf2, 0xb3, 0x06, 0xf5, 0x00, 0x83, 0xc6, 0x06, 0x00, + 0x33, 0x07, 0xf1, 0x00, 0x85, 0x07, 0x23, 0x00, 0xd7, 0x00, 0xe3, 0x97, 0xf5, 0xfe, 0x18, 0x10, + 0x93, 0x87, 0x15, 0x00, 0xba, 0x95, 0x13, 0x07, 0x00, 0xf8, 0x23, 0x80, 0xe5, 0xfe, 0x13, 0x07, + 0x00, 0x02, 0x63, 0x92, 0xe7, 0x02, 0x37, 0x05, 0x00, 0x04, 0x8a, 0x85, 0x13, 0x06, 0x00, 0x02, + 0x13, 0x05, 0x05, 0x02, 0xef, 0xe0, 0x6f, 0xee, 0xb2, 0x50, 0x45, 0x61, 0x82, 0x80, 0x79, 0x71, + 0x06, 0xd6, 0x81, 0x47, 0xd9, 0xb7, 0xb3, 0x06, 0xf1, 0x00, 0x23, 0x80, 0x06, 0x00, 0x85, 0x07, + 0xc9, 0xbf, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x00, 0x08, 0x98, 0xd3, 0x23, 0xa2, 0x07, 0x02, + 0x23, 0xa4, 0x07, 0x02, 0x23, 0xa6, 0x07, 0x02, 0x23, 0xa8, 0x07, 0x02, 0x13, 0x17, 0xb5, 0x00, + 0xb7, 0x06, 0xff, 0x00, 0x23, 0xaa, 0x07, 0x02, 0x75, 0x8f, 0x6e, 0x05, 0x23, 0xac, 0x07, 0x02, + 0x3a, 0x95, 0xc8, 0xdf, 0x82, 0x80, 0x37, 0x65, 0x10, 0x00, 0x01, 0x11, 0x13, 0x05, 0x45, 0x81, + 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x37, 0x34, 0x20, 0x00, + 0xef, 0xf0, 0xdf, 0xe9, 0x93, 0x07, 0x04, 0xea, 0xc8, 0x47, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, + 0xef, 0xf0, 0xff, 0xe9, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x10, 0xf5, 0x2e, 0xaa, 0x84, 0x13, 0x05, + 0x00, 0x02, 0xef, 0xf0, 0x1f, 0xf9, 0x13, 0x04, 0x04, 0xea, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xe7, 0xaa, 0x89, 0x63, 0x10, 0x95, 0x2c, 0x48, 0x44, 0x09, 0x69, + 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x7f, 0xe6, 0xaa, 0x84, 0x63, 0x15, + 0x35, 0x2b, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x5f, 0xe5, 0xaa, 0x89, + 0x63, 0x1c, 0x95, 0x28, 0x1c, 0x40, 0x48, 0x44, 0x37, 0x0a, 0x00, 0x04, 0x83, 0xc7, 0x07, 0x00, + 0x7e, 0x05, 0x13, 0x65, 0x15, 0x00, 0x93, 0xe7, 0x07, 0x20, 0x23, 0x2c, 0xfa, 0x00, 0xef, 0xf0, + 0x1f, 0xe3, 0xaa, 0x84, 0x63, 0x1a, 0x35, 0x27, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, + 0xef, 0xf0, 0xff, 0xe1, 0x2a, 0x89, 0x63, 0x11, 0x95, 0x26, 0xef, 0xf0, 0x1f, 0xdd, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x9f, 0xe0, 0xaa, 0x84, 0x63, 0x16, 0x25, 0x25, + 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0xff, 0xef, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xbf, 0xde, 0x2a, 0x89, 0x63, 0x17, 0x95, 0x22, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x9f, 0xdd, 0xaa, 0x84, 0x63, 0x1e, 0x25, 0x21, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x7f, 0xdc, 0x63, 0x16, 0x95, 0x20, + 0x48, 0x44, 0x93, 0x07, 0x00, 0x10, 0x23, 0x2c, 0xfa, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x15, 0x00, + 0xef, 0xf0, 0xff, 0xda, 0x93, 0x07, 0xa0, 0x0a, 0xaa, 0x84, 0x63, 0x17, 0xf5, 0x1e, 0x48, 0x44, + 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x5f, 0xd9, 0xaa, 0x89, + 0x63, 0x1c, 0x95, 0x1c, 0xef, 0xf0, 0x7f, 0xd4, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, + 0xef, 0xf0, 0xff, 0xd7, 0xaa, 0x84, 0x63, 0x11, 0x35, 0x1d, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, + 0x5f, 0xe7, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, + 0x1f, 0xd6, 0xaa, 0x89, 0x63, 0x12, 0x95, 0x1a, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, + 0xef, 0xf0, 0xff, 0xd4, 0xaa, 0x84, 0x63, 0x19, 0x35, 0x19, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x02, 0xef, 0xf0, 0xdf, 0xd3, 0xaa, 0x89, 0x63, 0x10, 0x95, 0x18, 0x08, 0x40, 0x05, 0x05, + 0xef, 0xf0, 0xdf, 0xd1, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x3f, 0xd2, + 0xaa, 0x84, 0x63, 0x13, 0x35, 0x17, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, + 0x1f, 0xd1, 0x2a, 0x89, 0x63, 0x1a, 0x95, 0x14, 0xef, 0xf0, 0x3f, 0xcc, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0xcf, 0xaa, 0x84, 0x63, 0x1f, 0x25, 0x13, 0x13, 0x05, + 0x00, 0x04, 0xef, 0xf0, 0x1f, 0xdf, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xcd, 0x63, 0x11, 0x95, 0x12, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x35, 0x00, 0xef, 0xf0, 0xdf, 0xcc, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0x63, 0x16, 0xf5, 0x10, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x7f, 0xcb, 0xaa, 0x84, 0x63, 0x1d, + 0x25, 0x0f, 0x13, 0x05, 0x10, 0x02, 0xef, 0xf0, 0xdf, 0xda, 0x1c, 0x40, 0x48, 0x44, 0x21, 0x67, + 0x83, 0xc7, 0x07, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xd9, 0x8f, 0x23, 0x20, 0xfa, 0x02, + 0xef, 0xf0, 0xff, 0xc8, 0xaa, 0x89, 0x63, 0x19, 0x95, 0x0c, 0x48, 0x44, 0x89, 0x64, 0x8d, 0x04, + 0x7e, 0x05, 0x45, 0x8d, 0xef, 0xf0, 0xbf, 0xc7, 0x2a, 0x89, 0x63, 0x1f, 0x35, 0x0b, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x9f, 0xc6, 0xaa, 0x89, 0x63, 0x16, 0x25, 0x0b, + 0x08, 0x40, 0x13, 0x05, 0x15, 0x02, 0xef, 0xf0, 0x7f, 0xc4, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xc4, 0x2a, 0x89, 0x63, 0x18, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, + 0x45, 0x8d, 0xef, 0xf0, 0xdf, 0xc3, 0xaa, 0x84, 0x63, 0x10, 0x25, 0x09, 0xef, 0xf0, 0xff, 0xbe, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x7f, 0xc2, 0x2a, 0x89, 0x63, 0x15, + 0x95, 0x06, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0xdf, 0xd1, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x9f, 0xc0, 0xaa, 0x84, 0x63, 0x16, 0x25, 0x05, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x7f, 0xbf, 0x63, 0x1e, 0x95, 0x02, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x52, 0xef, 0xf0, 0x7f, 0xbe, 0x93, 0x07, 0xa0, 0x0a, + 0x63, 0x14, 0xf5, 0x02, 0x08, 0x40, 0x62, 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, + 0x22, 0x4a, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x06, 0x13, 0x05, + 0x15, 0x06, 0x05, 0x61, 0x6f, 0xe0, 0x6f, 0xb0, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, + 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x4e, 0xc6, 0x06, 0xce, 0x22, 0xcc, + 0x26, 0xca, 0x4a, 0xc8, 0x52, 0xc4, 0x93, 0x09, 0x00, 0x04, 0x63, 0xe8, 0xb9, 0x08, 0x37, 0x3a, + 0x20, 0x00, 0xaa, 0x84, 0x2e, 0x84, 0x13, 0x09, 0x0a, 0xea, 0xef, 0xf0, 0x7f, 0xc1, 0x03, 0x25, + 0xc9, 0x00, 0x13, 0x0a, 0x0a, 0xea, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x3f, 0xb7, + 0x13, 0x85, 0x04, 0x02, 0x63, 0x19, 0x34, 0x03, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x05, + 0x05, 0x02, 0x13, 0x06, 0x00, 0x02, 0xef, 0xe0, 0x4f, 0xb2, 0x03, 0x25, 0xc9, 0x00, 0x62, 0x44, + 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, + 0x05, 0x61, 0x6f, 0xf0, 0xdf, 0xb3, 0xfd, 0x47, 0x63, 0xf5, 0x87, 0x02, 0x93, 0x05, 0x04, 0xfe, + 0xef, 0xf0, 0x1f, 0xbc, 0x13, 0x04, 0x04, 0x04, 0x93, 0x17, 0xb4, 0x00, 0x37, 0x07, 0xff, 0x00, + 0xf9, 0x8f, 0x6e, 0x04, 0x3e, 0x94, 0xb7, 0x07, 0x00, 0x04, 0x03, 0x25, 0xca, 0x00, 0xc0, 0xdf, + 0x7d, 0xbf, 0x01, 0x45, 0xef, 0xf0, 0xff, 0xa9, 0xf1, 0xbf, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, + 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, 0x37, 0x34, + 0x20, 0x00, 0x93, 0x07, 0x04, 0xea, 0x52, 0xc4, 0x2a, 0x8a, 0xc8, 0x47, 0x56, 0xc2, 0x06, 0xce, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x30, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xae, 0x8a, 0xef, 0xf0, + 0x1f, 0xad, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x11, 0xf5, 0x12, 0xaa, 0x84, 0x13, 0x05, 0x60, 0x03, + 0xef, 0xf0, 0x3f, 0xa5, 0x13, 0x04, 0x04, 0xea, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x45, 0x00, + 0xef, 0xf0, 0xff, 0xaa, 0x2a, 0x89, 0x63, 0x11, 0x95, 0x10, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xa9, 0xaa, 0x84, 0x63, 0x18, 0x25, 0x0f, 0x48, 0x44, 0x09, 0x69, + 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x7f, 0xa8, 0xaa, 0x89, 0x63, 0x1d, + 0x95, 0x0c, 0xd6, 0x85, 0x52, 0x85, 0xef, 0xf0, 0x3f, 0xed, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x35, 0x00, 0xef, 0xf0, 0xdf, 0xa6, 0xaa, 0x84, 0x63, 0x10, 0x35, 0x0d, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x03, 0xef, 0xf0, 0xbf, 0xa5, 0xaa, 0x89, 0x63, 0x17, 0x95, 0x0a, 0x13, 0x05, + 0xc0, 0x05, 0xef, 0xf0, 0x1f, 0x9e, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x45, 0x00, 0xef, 0xf0, + 0x1f, 0xa4, 0xaa, 0x84, 0x63, 0x1a, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, + 0xef, 0xf0, 0xff, 0xa2, 0xaa, 0x89, 0x63, 0x11, 0x95, 0x08, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x32, 0xef, 0xf0, 0xdf, 0xa1, 0xaa, 0x84, 0x63, 0x18, 0x35, 0x07, 0x48, 0x44, 0x7e, 0x05, + 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0xbf, 0xa0, 0x63, 0x10, 0x95, 0x06, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x03, 0xef, 0xf0, 0xbf, 0x9f, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0x63, 0x15, + 0xf5, 0x04, 0x13, 0x05, 0x00, 0x06, 0xef, 0xf0, 0xdf, 0xae, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x17, 0xef, 0xf0, 0xdf, 0x9d, 0xaa, 0x84, 0x63, 0x18, 0x25, 0x03, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xbf, 0x9c, 0x63, 0x10, 0x95, 0x02, 0x48, 0x44, 0x62, 0x44, + 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x02, 0x05, 0x61, 0x6f, 0xf0, 0xbf, 0x9a, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, + 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x39, 0x71, 0x22, 0xdc, 0x37, 0x34, + 0x20, 0x00, 0x06, 0xde, 0x4a, 0xd8, 0x26, 0xda, 0x32, 0x89, 0x13, 0x04, 0x04, 0xea, 0xef, 0xf0, + 0xdf, 0xe8, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x40, 0xef, 0xf0, 0x5f, 0x97, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x0a, 0xaa, 0x84, 0x37, 0x65, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, + 0xc5, 0x80, 0xef, 0xf0, 0x9f, 0xe6, 0x85, 0x47, 0x63, 0x07, 0xf9, 0x08, 0x48, 0x44, 0x85, 0x67, + 0x93, 0x87, 0x07, 0x80, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0x7f, 0x94, 0x2a, 0x89, 0x63, 0x1c, + 0x95, 0x06, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x04, 0x68, 0x00, + 0xef, 0xe0, 0xaf, 0x87, 0x48, 0x44, 0x89, 0x47, 0x23, 0x06, 0xf1, 0x02, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x20, 0xef, 0xf0, 0xdf, 0x91, 0xaa, 0x84, 0x63, 0x17, 0x25, 0x05, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xbf, 0x90, 0x2a, 0x89, 0x63, 0x1e, 0x95, 0x02, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x42, 0xef, 0xf0, 0x9f, 0x8f, 0xaa, 0x84, 0x63, 0x15, 0x25, 0x03, + 0x68, 0x00, 0x93, 0x05, 0x10, 0x02, 0xef, 0xf0, 0x5f, 0xdf, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x10, 0xef, 0xf0, 0xdf, 0x8d, 0x63, 0x18, 0x95, 0x00, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x04, 0xef, 0xf0, 0xdf, 0x8c, 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, 0x42, 0x59, 0x21, 0x61, + 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, 0xea, 0x08, 0x40, + 0x09, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x06, 0xc6, 0xef, 0xf0, 0xff, 0xf0, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x71, 0xef, 0xf0, 0x7f, 0x89, 0x48, 0x44, 0x22, 0x44, + 0xb2, 0x40, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x5f, 0x88, 0xb7, 0x37, + 0x20, 0x00, 0x03, 0xa5, 0x07, 0xea, 0x05, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, + 0x6f, 0xf0, 0xbf, 0xed, 0x41, 0x11, 0xb7, 0x65, 0x10, 0x00, 0x37, 0x05, 0x00, 0x04, 0x22, 0xc4, + 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x45, 0x81, 0x13, 0x05, 0x05, 0x02, 0x37, 0x34, 0x20, 0x00, + 0x06, 0xc6, 0x13, 0x04, 0x04, 0xea, 0xef, 0xe0, 0x4f, 0x81, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x07, 0xef, 0xf0, 0xdf, 0x83, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x1d, 0xf5, 0x00, 0x08, 0x40, + 0x22, 0x44, 0xb2, 0x40, 0x05, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x41, 0x01, + 0x6f, 0xf0, 0xbf, 0xe8, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, + 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, 0xea, 0x48, 0x44, 0x06, 0xc6, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x04, 0xef, 0xf0, 0xcf, 0xff, 0x08, 0x40, 0x13, 0x06, 0x00, 0x02, 0x81, 0x45, 0x13, 0x05, + 0x15, 0x04, 0xef, 0x00, 0x90, 0x62, 0x08, 0x40, 0x09, 0x46, 0x81, 0x45, 0x13, 0x05, 0x15, 0x04, + 0xef, 0xf0, 0xbf, 0xe4, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x60, 0xef, 0xf0, 0x2f, 0xfd, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x71, 0xef, 0xf0, 0x6f, 0xfc, 0x01, 0x45, 0xef, 0xf0, + 0x4f, 0xf5, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x4f, 0xfb, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x8f, 0xfa, 0xb2, 0x40, 0x22, 0x44, 0xb7, 0x07, + 0x00, 0x04, 0x69, 0x47, 0x98, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x11, 0x65, 0xd5, 0xa1, 0x37, 0x35, + 0x20, 0x00, 0x41, 0x11, 0x51, 0x46, 0x81, 0x45, 0x13, 0x05, 0x05, 0xea, 0x06, 0xc6, 0xef, 0x00, + 0xd0, 0x5b, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x1d, 0x65, 0x23, 0xa6, 0xe7, 0xfa, + 0x55, 0x29, 0xb2, 0x40, 0xb7, 0x07, 0x00, 0x04, 0x05, 0x47, 0x98, 0xcb, 0x41, 0x01, 0x6f, 0xf0, + 0xdf, 0xfc, 0x11, 0x65, 0x45, 0xa1, 0x41, 0x11, 0x26, 0xc2, 0x4a, 0xc0, 0x06, 0xc6, 0x22, 0xc4, + 0x2a, 0x89, 0xae, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0xdf, 0xfa, 0x95, 0x47, 0x13, 0x05, 0x50, 0x05, + 0x63, 0xe6, 0x97, 0x02, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, 0xea, 0xb7, 0x65, 0x10, 0x00, + 0x04, 0xc4, 0x93, 0x85, 0x85, 0x83, 0x8a, 0x04, 0x85, 0x47, 0xae, 0x94, 0x5c, 0xc0, 0x9c, 0x40, + 0x23, 0x20, 0x24, 0x01, 0x82, 0x97, 0x08, 0x48, 0x23, 0x22, 0x04, 0x00, 0xb2, 0x40, 0x22, 0x44, + 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x05, 0xe1, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, + 0xef, 0xb0, 0x3f, 0xf6, 0xb7, 0x05, 0x00, 0x04, 0x32, 0x45, 0xf2, 0x40, 0x41, 0x46, 0x93, 0x85, + 0x05, 0x08, 0x05, 0x61, 0x6f, 0xd0, 0x7f, 0xe3, 0xb7, 0x05, 0x00, 0x04, 0x41, 0x46, 0x93, 0x85, + 0x05, 0x08, 0xcd, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x85, 0x47, 0x2a, 0x84, 0x63, 0xf4, + 0xa7, 0x00, 0xef, 0xb0, 0x1f, 0xf3, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xea, 0xc8, 0x47, + 0x46, 0x04, 0xb2, 0x40, 0x7e, 0x05, 0x49, 0x8c, 0x21, 0x65, 0x15, 0x05, 0x41, 0x8d, 0x22, 0x44, + 0x09, 0x47, 0xd8, 0xc3, 0x41, 0x01, 0x6f, 0xf0, 0x8f, 0xea, 0x39, 0x71, 0x22, 0xdc, 0x56, 0xd2, + 0x5a, 0xd0, 0x06, 0xde, 0x26, 0xda, 0x4a, 0xd8, 0x4e, 0xd6, 0x52, 0xd4, 0x5e, 0xce, 0x62, 0xcc, + 0x66, 0xca, 0x6a, 0xc8, 0x2a, 0x84, 0x2e, 0x8b, 0xb2, 0x8a, 0x99, 0xe1, 0xef, 0xb0, 0x7f, 0xee, + 0xb7, 0x0b, 0x00, 0x04, 0xb7, 0x39, 0x20, 0x00, 0x05, 0x6c, 0x81, 0x44, 0x01, 0x49, 0xc1, 0x4c, + 0x93, 0x8b, 0x0b, 0x02, 0x93, 0x89, 0x09, 0xea, 0x09, 0x0c, 0x37, 0x3d, 0x20, 0x00, 0xb3, 0x05, + 0x9b, 0x00, 0x63, 0xe0, 0x54, 0x03, 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, + 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, 0xd2, 0x4c, 0x42, 0x4d, 0x21, 0x61, + 0x82, 0x80, 0x33, 0x8a, 0x9a, 0x40, 0x63, 0xd3, 0x4c, 0x01, 0x41, 0x4a, 0x4a, 0x85, 0x2e, 0xc6, + 0xef, 0xe0, 0xcf, 0x8d, 0xb2, 0x45, 0x13, 0x06, 0x3a, 0x00, 0x71, 0x9a, 0x5e, 0x85, 0xef, 0xd0, + 0xdf, 0xde, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x2f, 0xe1, + 0x03, 0xa5, 0xc9, 0x00, 0x93, 0x17, 0x8a, 0x01, 0x7e, 0x05, 0x5d, 0x8d, 0x13, 0x65, 0x75, 0x00, + 0xef, 0xf0, 0xef, 0xdf, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x33, 0x65, 0x85, 0x01, 0xef, 0xf0, + 0x0f, 0xdf, 0x03, 0x27, 0xcd, 0xfa, 0x93, 0x07, 0x50, 0x05, 0x63, 0x19, 0xf7, 0x00, 0x19, 0xc4, + 0x22, 0x85, 0x52, 0x86, 0xca, 0x85, 0xef, 0xe0, 0x6f, 0x91, 0x41, 0x04, 0x93, 0x07, 0x00, 0x07, + 0x63, 0xe3, 0x27, 0x01, 0x41, 0x09, 0xc1, 0x04, 0x9d, 0xb7, 0x39, 0x71, 0x26, 0xda, 0x52, 0xd4, + 0x56, 0xd2, 0x06, 0xde, 0x22, 0xdc, 0x4a, 0xd8, 0x4e, 0xd6, 0x5a, 0xd0, 0x5e, 0xce, 0x62, 0xcc, + 0x66, 0xca, 0x6a, 0xc8, 0x6e, 0xc6, 0xaa, 0x8a, 0xae, 0x84, 0x32, 0x8a, 0x19, 0xe1, 0xef, 0xb0, + 0x5f, 0xe0, 0xb7, 0x39, 0x20, 0x00, 0x37, 0x0b, 0x02, 0x00, 0x85, 0x6b, 0x01, 0x49, 0x81, 0x4d, + 0x37, 0x3c, 0x20, 0x00, 0x41, 0x4d, 0x93, 0x89, 0x09, 0xea, 0x1d, 0x0b, 0x93, 0x8b, 0x0b, 0x82, + 0xb3, 0x8c, 0x2a, 0x01, 0x93, 0x07, 0xcc, 0xfa, 0x63, 0x64, 0x49, 0x03, 0xf2, 0x50, 0x62, 0x54, + 0x13, 0x07, 0x50, 0x05, 0x98, 0xc3, 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, 0x5a, + 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, 0xd2, 0x4c, 0x42, 0x4d, 0xb2, 0x4d, 0x21, 0x61, 0x82, 0x80, + 0x33, 0x04, 0x2a, 0x41, 0x63, 0x73, 0x8d, 0x00, 0x41, 0x44, 0x6e, 0x85, 0xef, 0xd0, 0x9f, 0xff, + 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0xfa, 0x98, 0x43, 0x93, 0x07, 0x50, 0x05, 0x63, 0x19, + 0xf7, 0x00, 0x99, 0xc4, 0x26, 0x85, 0x22, 0x86, 0xee, 0x85, 0xef, 0xe0, 0x8f, 0x89, 0xc1, 0x04, + 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x25, 0x00, 0xef, 0xf0, 0x4f, 0xd1, 0x03, 0xa5, + 0xc9, 0x00, 0x93, 0x17, 0x84, 0x01, 0x0d, 0x04, 0x7e, 0x05, 0x5d, 0x8d, 0x33, 0x65, 0x65, 0x01, + 0xef, 0xf0, 0xef, 0xcf, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x33, 0x65, 0x75, 0x01, 0xef, 0xf0, + 0x0f, 0xcf, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x76, 0xc4, 0xff, 0x93, 0x85, 0x05, 0x04, 0x66, 0x85, + 0xef, 0xd0, 0xbf, 0xc2, 0x93, 0x07, 0x00, 0x06, 0x63, 0xe3, 0xb7, 0x01, 0xc1, 0x0d, 0x41, 0x09, + 0x81, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x7f, 0xd2, + 0x21, 0x45, 0xef, 0xf0, 0xcf, 0xcb, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x19, 0xf5, 0x00, 0x22, 0x85, + 0xef, 0xf0, 0x9f, 0xda, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa2, 0x07, 0xea, 0xb2, 0x40, 0x22, 0x44, + 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa6, 0xa7, 0xfa, 0x82, 0x80, 0xb7, 0x07, + 0x00, 0x04, 0x13, 0x07, 0x60, 0x02, 0x98, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, + 0x98, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0xc8, 0x4b, 0x82, 0x80, 0x39, 0x71, 0x36, 0xd0, + 0x3a, 0xce, 0x3e, 0xcc, 0x05, 0x47, 0xb7, 0x07, 0x00, 0x04, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, + 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, + 0x7a, 0xc2, 0x7e, 0xc0, 0xd8, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xea, 0xd8, 0x43, + 0x89, 0x46, 0x7d, 0x17, 0x63, 0xfe, 0xe6, 0x02, 0x37, 0x65, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, + 0x05, 0x81, 0xef, 0xd0, 0x4f, 0xd1, 0xef, 0xc0, 0xaf, 0xd7, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, + 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, + 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, + 0x13, 0x07, 0xa0, 0x0a, 0x98, 0xcb, 0xd1, 0xbf, 0xb7, 0x07, 0x01, 0x02, 0x88, 0xd7, 0xcc, 0xd7, + 0x88, 0xdb, 0xcc, 0xdb, 0x88, 0xdf, 0xcc, 0xdf, 0x82, 0x80, 0x01, 0x11, 0x26, 0xca, 0xb7, 0x04, + 0x01, 0x02, 0x22, 0xcc, 0xc0, 0x40, 0xf5, 0x77, 0x93, 0x87, 0xf7, 0xa5, 0x7d, 0x8c, 0x89, 0x67, + 0x93, 0x87, 0x07, 0x1a, 0x06, 0xce, 0x4a, 0xc8, 0x4e, 0xc6, 0xc1, 0x8f, 0xaa, 0x89, 0xdc, 0xc0, + 0x05, 0x45, 0x2e, 0x89, 0xef, 0xd0, 0x1f, 0x8a, 0x93, 0x67, 0x04, 0x40, 0xdc, 0xc0, 0x05, 0x45, + 0xef, 0xd0, 0x5f, 0x89, 0x85, 0x67, 0x93, 0x87, 0x07, 0x40, 0x5d, 0x8c, 0xc0, 0xc0, 0xb7, 0x47, + 0x00, 0x08, 0x23, 0xa4, 0x07, 0x00, 0xb7, 0x57, 0x00, 0x08, 0x23, 0xa4, 0x07, 0x00, 0xf2, 0x40, + 0x62, 0x44, 0x23, 0xa0, 0x34, 0x03, 0x23, 0xa2, 0x24, 0x03, 0xb2, 0x49, 0xd2, 0x44, 0x42, 0x49, + 0x05, 0x61, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x02, 0x88, 0x53, 0xcc, 0x53, 0x82, 0x80, 0xb7, 0x07, + 0x01, 0x02, 0x88, 0x47, 0x21, 0x81, 0x13, 0x75, 0xf5, 0x0f, 0x82, 0x80, 0x41, 0x11, 0x01, 0x45, + 0x81, 0x45, 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0xef, 0xf0, 0x1f, 0xf6, 0xef, 0xf0, 0x9f, 0xfd, + 0xaa, 0x84, 0x2e, 0x84, 0x2a, 0x87, 0xae, 0x86, 0x37, 0x66, 0x10, 0x00, 0xb7, 0x65, 0x10, 0x00, + 0x37, 0x55, 0x10, 0x00, 0x93, 0x85, 0x85, 0x86, 0x13, 0x05, 0x85, 0x77, 0x13, 0x06, 0x06, 0x85, + 0xef, 0xd0, 0x0f, 0xba, 0xa2, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x26, 0x85, 0x92, 0x44, 0x41, 0x01, + 0x6f, 0xf0, 0xbf, 0xf3, 0x39, 0x71, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, + 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, + 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xf0, 0x7f, 0xf9, 0xef, 0xc0, 0x6f, 0xc4, 0xf2, 0x50, + 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, + 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, + 0x73, 0x00, 0x20, 0x30, 0xb7, 0x07, 0x00, 0x02, 0x0d, 0x47, 0xf8, 0xcb, 0x13, 0x07, 0x30, 0x03, + 0xb8, 0xcf, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x5c, 0x47, 0xc9, 0x8f, 0x5c, 0xc7, 0x82, 0x80, + 0xb7, 0x07, 0x00, 0x02, 0xd8, 0x47, 0x13, 0x45, 0xf5, 0xff, 0x79, 0x8d, 0xc8, 0xc7, 0x82, 0x80, + 0x37, 0x07, 0x00, 0x02, 0x1c, 0x4f, 0xc9, 0x8f, 0x1c, 0xcf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, + 0x98, 0x4f, 0x13, 0x45, 0xf5, 0xff, 0x79, 0x8d, 0x88, 0xcf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, + 0xc8, 0xcb, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x47, 0x00, 0x1c, 0xc7, + 0xb7, 0x07, 0x00, 0x03, 0x94, 0x4b, 0x37, 0x37, 0x20, 0x00, 0x23, 0x28, 0xd7, 0xfa, 0x23, 0xa8, + 0x07, 0x00, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0xb7, 0x06, 0x00, 0x03, 0xf9, 0x9b, + 0x1c, 0xc7, 0x37, 0x07, 0x08, 0x00, 0x9c, 0x46, 0xf9, 0x8f, 0xf5, 0xff, 0x82, 0x80, 0x37, 0x07, + 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x17, 0x00, 0x1c, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, + 0x07, 0xfb, 0xb7, 0x07, 0x00, 0x03, 0x98, 0xcb, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, + 0x47, 0xfb, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0xb7, 0x27, 0x03, 0x04, 0x9c, 0x47, + 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x13, 0x05, + 0x00, 0x10, 0x6f, 0xf0, 0x3f, 0xf4, 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2a, + 0xf7, 0xfa, 0x41, 0x11, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2c, 0xf7, 0xfa, 0x06, 0xc6, 0xef, 0xf0, + 0x1f, 0xfe, 0xb7, 0x27, 0x03, 0x04, 0x09, 0x47, 0xd8, 0xc3, 0x37, 0x17, 0x03, 0x04, 0xb7, 0x07, + 0x03, 0x04, 0x13, 0x07, 0x07, 0x80, 0x23, 0xa0, 0x07, 0x00, 0x91, 0x07, 0xe3, 0x9d, 0xe7, 0xfe, + 0xb7, 0x27, 0x03, 0x04, 0x0d, 0x47, 0xd8, 0xc7, 0x98, 0x47, 0x85, 0x47, 0x13, 0x05, 0xa0, 0x0a, + 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, + 0x00, 0x10, 0x6f, 0xf0, 0xff, 0xee, 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2a, + 0xf7, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2c, 0xf7, 0xfa, 0xb7, 0x27, 0x03, 0x04, 0x05, 0x47, + 0xd8, 0xc3, 0x82, 0x80, 0xc2, 0x05, 0xc9, 0x8d, 0x93, 0xe5, 0x05, 0x10, 0xb7, 0x07, 0x03, 0x04, + 0x23, 0xa0, 0xb7, 0x10, 0x82, 0x80, 0xc2, 0x05, 0xc9, 0x8d, 0x11, 0x65, 0x13, 0x05, 0x05, 0x50, + 0xc9, 0x8d, 0xb7, 0x07, 0x03, 0x04, 0x23, 0xa0, 0xb7, 0x10, 0x82, 0x80, 0xb7, 0x17, 0x03, 0x04, + 0xbe, 0x95, 0x6f, 0xd0, 0x9f, 0x89, 0xb7, 0x07, 0x03, 0x04, 0x3e, 0x95, 0x6f, 0xd0, 0xff, 0x90, + 0xb7, 0x95, 0x04, 0x00, 0x37, 0x55, 0x10, 0x00, 0x41, 0x11, 0x93, 0x85, 0x05, 0x3e, 0x13, 0x05, + 0xa5, 0xcb, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0xd0, 0x6f, 0xe6, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0f, + 0xf5, 0x00, 0x37, 0x65, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x05, 0x87, 0xef, 0xd0, 0xaf, 0x9f, + 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x17, 0x03, 0x04, + 0x83, 0xa7, 0x07, 0x10, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x84, 0xfb, 0x93, 0xf7, 0xf7, 0x0f, + 0x81, 0xe7, 0x1c, 0x40, 0x63, 0x9d, 0xa7, 0x00, 0x37, 0x65, 0x10, 0x00, 0x8d, 0x45, 0x13, 0x05, + 0x05, 0x87, 0xef, 0xd0, 0x4f, 0x9c, 0x93, 0x07, 0xa0, 0x0a, 0x1c, 0xc0, 0xd1, 0xb7, 0xb7, 0x37, + 0x20, 0x00, 0x03, 0xa7, 0x47, 0xfb, 0x13, 0x84, 0x47, 0xfb, 0x63, 0x09, 0xa7, 0x00, 0x37, 0x65, + 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0x05, 0x87, 0xef, 0xd0, 0xef, 0x99, 0x08, 0x40, 0x5d, 0xb7, + 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x3f, 0xf4, 0xef, 0xf0, 0xff, 0xf0, 0xb2, 0x40, 0x41, 0x01, + 0x6f, 0xf0, 0x1f, 0xf6, 0xb7, 0x17, 0x03, 0x04, 0x03, 0xa5, 0x07, 0x10, 0x41, 0x81, 0x82, 0x80, + 0x41, 0x11, 0x3a, 0xc4, 0x37, 0x27, 0x03, 0x04, 0x3e, 0xc2, 0x1c, 0x47, 0x36, 0xc6, 0x93, 0xf6, + 0x27, 0x00, 0x89, 0xca, 0x89, 0x46, 0x14, 0xc7, 0x37, 0x37, 0x20, 0x00, 0x93, 0x06, 0xa0, 0x0a, + 0x23, 0x2a, 0xd7, 0xfa, 0x91, 0x8b, 0x99, 0xcf, 0xb7, 0x27, 0x03, 0x04, 0x11, 0x47, 0x98, 0xc7, + 0x93, 0x07, 0xa0, 0x0a, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2c, 0xf7, 0xfa, 0x37, 0x37, 0x20, 0x00, + 0x23, 0x2a, 0xf7, 0xfa, 0xb2, 0x46, 0x22, 0x47, 0x92, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, + 0x41, 0x11, 0x22, 0xc4, 0x37, 0x04, 0x00, 0x03, 0x1c, 0x48, 0x06, 0xc6, 0xdd, 0x9b, 0x1c, 0xc8, + 0xef, 0xe0, 0xcf, 0xd1, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x02, 0x5c, 0xcc, 0xb2, 0x40, + 0x22, 0x44, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x80, 0x07, 0xfc, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, + 0x22, 0xc4, 0x2a, 0x84, 0x21, 0x45, 0x06, 0xc6, 0xef, 0xf0, 0x5f, 0xd8, 0x13, 0x05, 0x00, 0x04, + 0xef, 0xf0, 0x5f, 0xd4, 0x22, 0x04, 0x13, 0x64, 0x04, 0x03, 0x37, 0x07, 0x00, 0x03, 0x40, 0xc3, + 0xb2, 0x40, 0x22, 0x44, 0xc1, 0x67, 0x93, 0x87, 0xa7, 0xfa, 0x1c, 0xcf, 0x41, 0x01, 0x82, 0x80, + 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xaa, 0x84, 0x2e, 0x84, 0x19, 0xe1, 0xef, 0xb0, + 0x5f, 0x83, 0x19, 0xe0, 0xef, 0xb0, 0xff, 0x82, 0x09, 0x45, 0xef, 0xf0, 0x5f, 0xfb, 0x37, 0x07, + 0x20, 0x00, 0xb7, 0x07, 0x00, 0x03, 0x13, 0x07, 0x07, 0x02, 0xd8, 0xcf, 0x37, 0x37, 0x20, 0x00, + 0x23, 0x2e, 0x97, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x22, 0x87, 0xfc, 0xb2, 0x40, 0x22, 0x44, + 0x05, 0x47, 0x98, 0xcb, 0x37, 0x07, 0x08, 0x00, 0x98, 0xc7, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, + 0xb7, 0x07, 0x00, 0x03, 0x9c, 0x47, 0x37, 0x07, 0x04, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, + 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x37, 0x07, 0x00, 0x03, 0x5c, 0x53, 0x13, 0x05, + 0x50, 0x05, 0x93, 0x96, 0x07, 0x01, 0xc1, 0x82, 0xc1, 0x83, 0x63, 0x97, 0xf6, 0x00, 0x1c, 0x47, + 0x91, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, + 0x3f, 0xf1, 0x37, 0x07, 0x00, 0x03, 0x5c, 0x47, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc7, 0x5c, 0x47, + 0x85, 0x8b, 0xf5, 0xff, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, + 0x47, 0xfc, 0x95, 0xc3, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x9f, 0xee, 0xb7, 0x07, 0x00, 0x03, + 0x98, 0x4b, 0xb2, 0x40, 0x13, 0x67, 0x87, 0x00, 0x98, 0xcb, 0x37, 0x07, 0x08, 0x00, 0x98, 0xc7, + 0x41, 0x01, 0x6f, 0xe0, 0xcf, 0xbd, 0x82, 0x80, 0x37, 0x07, 0x00, 0x03, 0x1c, 0x4b, 0xf9, 0x9b, + 0x1c, 0xcb, 0x82, 0x80, 0xb7, 0x06, 0x00, 0x03, 0xdc, 0x42, 0x7d, 0x77, 0x13, 0x07, 0xf7, 0x0f, + 0xf9, 0x8f, 0x05, 0x67, 0x22, 0x05, 0x13, 0x07, 0x07, 0xf0, 0x79, 0x8d, 0x5d, 0x8d, 0xc8, 0xc2, + 0x82, 0x80, 0x1d, 0x71, 0x3a, 0xda, 0x37, 0x07, 0x00, 0x03, 0x3e, 0xd8, 0x1c, 0x47, 0x86, 0xce, + 0x96, 0xcc, 0x9a, 0xca, 0x9e, 0xc8, 0xa2, 0xc6, 0xa6, 0xc4, 0xaa, 0xc2, 0xae, 0xc0, 0x32, 0xde, + 0x36, 0xdc, 0x42, 0xd6, 0x46, 0xd4, 0x4a, 0xd2, 0x4e, 0xd0, 0x72, 0xce, 0x76, 0xcc, 0x7a, 0xca, + 0x7e, 0xc8, 0x85, 0x8b, 0xa1, 0xc7, 0x04, 0x57, 0x11, 0x44, 0x37, 0x39, 0x20, 0x00, 0x83, 0x27, + 0xc9, 0xfb, 0x13, 0xf5, 0xf4, 0x0f, 0x7d, 0x14, 0x82, 0x97, 0xa1, 0x80, 0x6d, 0xf8, 0x36, 0x44, + 0xf6, 0x40, 0xe6, 0x42, 0x56, 0x43, 0xc6, 0x43, 0xa6, 0x44, 0x16, 0x45, 0x86, 0x45, 0x72, 0x56, + 0xe2, 0x56, 0x52, 0x57, 0xc2, 0x57, 0x32, 0x58, 0xa2, 0x58, 0x12, 0x59, 0x82, 0x59, 0x72, 0x4e, + 0xe2, 0x4e, 0x52, 0x4f, 0xc2, 0x4f, 0x25, 0x61, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x37, 0x20, 0x00, + 0x03, 0xc7, 0x07, 0xfc, 0x13, 0x84, 0x07, 0xfc, 0x05, 0xeb, 0xb7, 0x04, 0x00, 0x03, 0x37, 0x39, + 0x20, 0x00, 0x93, 0x09, 0xa0, 0x0a, 0x9c, 0x44, 0x91, 0x8b, 0xd5, 0xfb, 0x83, 0x27, 0x49, 0xfc, + 0x68, 0x00, 0x82, 0x97, 0x63, 0x0d, 0x35, 0x01, 0x85, 0x47, 0x23, 0x00, 0xf4, 0x00, 0xc1, 0x67, + 0x93, 0x87, 0x07, 0x02, 0xdc, 0xcc, 0x61, 0xbf, 0xef, 0xf0, 0x9f, 0xde, 0x49, 0xbf, 0xb2, 0x47, + 0x9c, 0xd8, 0xd1, 0xbf, 0xb7, 0x07, 0xf0, 0xfe, 0x37, 0x07, 0xf0, 0xff, 0x41, 0x11, 0xaa, 0x97, + 0x7d, 0x17, 0x22, 0xc4, 0x06, 0xc6, 0xf9, 0x8f, 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xb0, 0x6f, 0xe6, + 0x5c, 0x40, 0xb2, 0x40, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc0, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, + 0xb7, 0x07, 0xf0, 0xfe, 0x37, 0x07, 0xf0, 0xff, 0x41, 0x11, 0xaa, 0x97, 0x7d, 0x17, 0x22, 0xc4, + 0x06, 0xc6, 0xf9, 0x8f, 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xb0, 0xaf, 0xe3, 0x5c, 0x40, 0xb2, 0x40, + 0xf9, 0x9b, 0x5c, 0xc0, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0xf0, 0xfe, 0x37, 0x07, + 0xf0, 0xff, 0x01, 0x11, 0xaa, 0x97, 0x7d, 0x17, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, + 0x06, 0xce, 0xf9, 0x8f, 0x2a, 0x84, 0x2e, 0x89, 0xb2, 0x84, 0xb6, 0x89, 0x99, 0xc3, 0xef, 0xb0, + 0x4f, 0xe0, 0x5c, 0x40, 0x13, 0xf6, 0x24, 0x00, 0xf2, 0x40, 0xf5, 0x9b, 0x5d, 0x8e, 0x50, 0xc0, + 0x23, 0x28, 0x34, 0x01, 0x23, 0x2a, 0x24, 0x01, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, + 0x05, 0x61, 0x82, 0x80, 0xb7, 0x07, 0xf0, 0xfe, 0x37, 0x07, 0xf0, 0xff, 0x41, 0x11, 0xaa, 0x97, + 0x7d, 0x17, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xf9, 0x8f, 0x2a, 0x84, 0xae, 0x84, 0x99, 0xc3, + 0xef, 0xb0, 0x2f, 0xdc, 0x5c, 0x44, 0xb2, 0x40, 0xb3, 0xe5, 0x97, 0x00, 0x4c, 0xc4, 0x22, 0x44, + 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x87, 0xfc, 0x82, 0x80, + 0x39, 0x71, 0x3a, 0xce, 0x37, 0x07, 0x10, 0x01, 0x3e, 0xcc, 0x1c, 0x47, 0x58, 0x47, 0x06, 0xde, + 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, + 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xf9, 0x8f, 0x91, 0xcf, 0xb7, 0x37, + 0x20, 0x00, 0x93, 0x87, 0x87, 0xfc, 0x98, 0x43, 0x05, 0x07, 0x98, 0xc3, 0xb7, 0x07, 0x10, 0x01, + 0x98, 0x47, 0x0d, 0x8b, 0x98, 0xc7, 0x19, 0xa8, 0xb7, 0x07, 0x20, 0x01, 0x98, 0x47, 0xdc, 0x47, + 0x7d, 0x8f, 0xb7, 0x07, 0x20, 0x01, 0x6d, 0xf7, 0xef, 0xb0, 0x9f, 0xe3, 0xf2, 0x50, 0xe2, 0x52, + 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, + 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, + 0x20, 0x30, 0x1c, 0x41, 0x63, 0xf7, 0xb7, 0x00, 0x23, 0x80, 0xc7, 0x00, 0x1c, 0x41, 0x85, 0x07, + 0x1c, 0xc1, 0x82, 0x80, 0x1d, 0x71, 0xa2, 0xcc, 0xa6, 0xca, 0xca, 0xc8, 0x86, 0xce, 0xce, 0xc6, + 0xd2, 0xc4, 0xd6, 0xc2, 0xda, 0xc0, 0x5e, 0xde, 0x62, 0xdc, 0x66, 0xda, 0x6a, 0xd8, 0x6e, 0xd6, + 0x2a, 0xc6, 0x2e, 0x84, 0x32, 0x89, 0xb6, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x8f, 0xce, 0x63, 0x14, + 0x09, 0x00, 0xef, 0xb0, 0x0f, 0xce, 0x01, 0x45, 0x05, 0xc4, 0xb2, 0x4a, 0x7d, 0x14, 0x25, 0x4a, + 0x56, 0x94, 0x93, 0x0c, 0xc0, 0x06, 0x13, 0x0b, 0x30, 0x07, 0xa9, 0x4b, 0x1d, 0x4d, 0x03, 0x46, + 0x09, 0x00, 0x15, 0xe6, 0xb2, 0x47, 0x23, 0x80, 0x07, 0x00, 0x32, 0x45, 0x33, 0x05, 0x55, 0x41, + 0xf6, 0x40, 0x66, 0x44, 0xd6, 0x44, 0x46, 0x49, 0xb6, 0x49, 0x26, 0x4a, 0x96, 0x4a, 0x06, 0x4b, + 0xf2, 0x5b, 0x62, 0x5c, 0xd2, 0x5c, 0x42, 0x5d, 0xb2, 0x5d, 0x25, 0x61, 0x82, 0x80, 0x93, 0x07, + 0x50, 0x02, 0x63, 0x1f, 0xf6, 0x02, 0x93, 0x07, 0x19, 0x00, 0x83, 0xc6, 0x07, 0x00, 0x3e, 0x89, + 0x85, 0x07, 0x13, 0x87, 0x06, 0xfd, 0x13, 0x77, 0xf7, 0x0f, 0xe3, 0x78, 0xea, 0xfe, 0x63, 0x93, + 0x96, 0x01, 0x3e, 0x89, 0x03, 0x46, 0x09, 0x00, 0x63, 0x06, 0x66, 0x0d, 0x63, 0x60, 0xcb, 0x02, + 0x93, 0x07, 0x30, 0x06, 0x63, 0x05, 0xf6, 0x06, 0x93, 0x07, 0x40, 0x06, 0x63, 0x0c, 0xf6, 0x06, + 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, 0xf2, 0xa6, 0x89, 0x95, 0xa0, 0x93, 0x07, 0x50, 0x07, + 0x63, 0x02, 0xf6, 0x06, 0x93, 0x07, 0x80, 0x07, 0xe3, 0x14, 0xf6, 0xfe, 0x98, 0x40, 0x93, 0x89, + 0x44, 0x00, 0x81, 0x46, 0x37, 0x06, 0x00, 0xf0, 0xb3, 0x75, 0xc7, 0x00, 0xba, 0x84, 0x36, 0x8c, + 0x12, 0x07, 0x85, 0x06, 0x89, 0xe5, 0xe3, 0x99, 0xa6, 0xff, 0x1d, 0x4c, 0xba, 0x84, 0xa1, 0x4d, + 0x13, 0xd7, 0xc4, 0x01, 0x63, 0x74, 0xea, 0x08, 0x13, 0x06, 0x77, 0x05, 0xa2, 0x85, 0x68, 0x00, + 0x05, 0x0c, 0xef, 0xf0, 0x1f, 0xee, 0x92, 0x04, 0xe3, 0x14, 0xbc, 0xff, 0x09, 0xa8, 0x03, 0xc6, + 0x04, 0x00, 0xa2, 0x85, 0x68, 0x00, 0x93, 0x89, 0x44, 0x00, 0xef, 0xf0, 0x9f, 0xec, 0x05, 0x09, + 0xce, 0x84, 0x31, 0xbf, 0x5c, 0x08, 0x98, 0x40, 0x93, 0x89, 0x44, 0x00, 0x3e, 0x8c, 0x81, 0x44, + 0xb3, 0x76, 0x77, 0x03, 0x85, 0x04, 0x85, 0x07, 0x93, 0x86, 0x06, 0x03, 0xa3, 0x8f, 0xd7, 0xfe, + 0xba, 0x86, 0x33, 0x57, 0x77, 0x03, 0xe3, 0x65, 0xda, 0xfe, 0xfd, 0x5d, 0xfd, 0x14, 0xe3, 0x88, + 0xb4, 0xfd, 0xb3, 0x07, 0x9c, 0x00, 0x03, 0xc6, 0x07, 0x00, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, + 0x5f, 0xe8, 0xed, 0xb7, 0x93, 0x89, 0x44, 0x00, 0x84, 0x40, 0x03, 0xc6, 0x04, 0x00, 0x45, 0xda, + 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, 0xe6, 0x85, 0x04, 0xc5, 0xbf, 0x13, 0x06, 0x07, 0x03, + 0xb5, 0xbf, 0x41, 0x11, 0x26, 0xc2, 0xb7, 0x34, 0x20, 0x00, 0x2a, 0x86, 0xae, 0x86, 0x13, 0x85, + 0x44, 0xeb, 0x93, 0x05, 0x00, 0x08, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0xf0, 0xbf, 0xe5, 0x2a, 0x84, + 0x13, 0x85, 0x44, 0xeb, 0xef, 0xd0, 0x6f, 0x8d, 0xb2, 0x40, 0x22, 0x85, 0x22, 0x44, 0x92, 0x44, + 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x26, 0xca, 0xb7, 0x34, 0x20, 0x00, 0x2e, 0xd2, 0x32, 0xd4, + 0x36, 0xd6, 0x2a, 0x86, 0x54, 0x10, 0x93, 0x05, 0x00, 0x08, 0x13, 0x85, 0x44, 0xeb, 0x06, 0xce, + 0x22, 0xcc, 0x3a, 0xd8, 0x3e, 0xda, 0x42, 0xdc, 0x46, 0xde, 0x36, 0xc6, 0xef, 0xf0, 0x9f, 0xe1, + 0x2a, 0x84, 0x13, 0x85, 0x44, 0xeb, 0xef, 0xd0, 0x4f, 0x89, 0xf2, 0x40, 0x22, 0x85, 0x62, 0x44, + 0xd2, 0x44, 0x21, 0x61, 0x82, 0x80, 0x22, 0x05, 0x61, 0x77, 0x2d, 0x8d, 0xa1, 0x47, 0x15, 0x07, + 0x93, 0x16, 0x05, 0x01, 0x06, 0x05, 0x42, 0x05, 0xc1, 0x86, 0x41, 0x81, 0x63, 0xd5, 0x06, 0x00, + 0x39, 0x8d, 0x42, 0x05, 0x41, 0x81, 0xfd, 0x17, 0xe5, 0xf7, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, + 0x26, 0xc2, 0x06, 0xc6, 0x2a, 0x84, 0xae, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x8f, 0xad, 0xa2, 0x94, + 0x01, 0x45, 0x63, 0x17, 0x94, 0x00, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, + 0x05, 0x04, 0xaa, 0x85, 0x03, 0x45, 0xf4, 0xff, 0xef, 0xf0, 0xff, 0xfa, 0xdd, 0xb7, 0x41, 0x11, + 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x2a, 0x84, 0xae, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x6f, 0xaa, + 0xb7, 0x86, 0xb8, 0xed, 0x01, 0x47, 0xfd, 0x57, 0x93, 0x86, 0x06, 0x32, 0x63, 0x19, 0x97, 0x00, + 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x13, 0xc5, 0xf7, 0xff, 0x41, 0x01, 0x82, 0x80, 0x33, 0x06, + 0xe4, 0x00, 0x03, 0x46, 0x06, 0x00, 0xb1, 0x8f, 0x21, 0x46, 0x93, 0xd5, 0x17, 0x00, 0x85, 0x8b, + 0x91, 0xc3, 0xb6, 0x87, 0x7d, 0x16, 0xad, 0x8f, 0x6d, 0xfa, 0x05, 0x07, 0xc1, 0xbf, 0x2a, 0x83, + 0x09, 0xca, 0x83, 0x83, 0x05, 0x00, 0x23, 0x00, 0x73, 0x00, 0x7d, 0x16, 0x05, 0x03, 0x85, 0x05, + 0x6d, 0xfa, 0x82, 0x80, 0x15, 0xc2, 0x2a, 0x83, 0x85, 0x46, 0x63, 0x67, 0xb5, 0x00, 0xfd, 0x56, + 0x13, 0x07, 0xf6, 0xff, 0x3a, 0x93, 0xba, 0x95, 0x83, 0x83, 0x05, 0x00, 0x23, 0x00, 0x73, 0x00, + 0x7d, 0x16, 0x36, 0x93, 0xb6, 0x95, 0x6d, 0xfa, 0x82, 0x80, 0x2a, 0x83, 0x11, 0xc6, 0x23, 0x00, + 0xb3, 0x00, 0x7d, 0x16, 0x05, 0x03, 0x65, 0xfe, 0x82, 0x80, 0x00, 0x00, 0x63, 0x6f, 0x64, 0x65, + 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, 0x53, 0x45, 0x43, 0x43, 0x48, 0x4e, 0x4c, 0x00, + 0x4d, 0x43, 0x4e, 0x54, 0x00, 0x00, 0x00, 0x00, 0x65, 0x6e, 0x61, 0x62, 0x6c, 0x65, 0x64, 0x20, + 0x25, 0x64, 0x00, 0x00, 0x4d, 0x41, 0x49, 0x4e, 0x00, 0x00, 0x00, 0x00, 0x54, 0x58, 0x3a, 0x20, + 0x25, 0x64, 0x2f, 0x25, 0x64, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x43, 0x4d, 0x44, 0x33, + 0x00, 0x00, 0x00, 0x00, 0x49, 0x00, 0x00, 0x00, 0x52, 0x58, 0x3a, 0x20, 0x63, 0x6d, 0x64, 0x3d, + 0x30, 0x78, 0x25, 0x30, 0x32, 0x78, 0x2c, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x6c, 0x65, 0x6e, 0x20, + 0x25, 0x64, 0x2f, 0x25, 0x64, 0x00, 0x00, 0x00, 0x72, 0x73, 0x70, 0x3d, 0x25, 0x78, 0x00, 0x00, + 0x73, 0x74, 0x61, 0x72, 0x74, 0x2c, 0x20, 0x76, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, + 0x50, 0x52, 0x4f, 0x56, 0x49, 0x53, 0x49, 0x4f, 0x4e, 0x20, 0x4f, 0x4b, 0x00, 0x00, 0x00, 0x00, + 0x4e, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x43, 0x50, 0x42, 0x3a, 0x20, 0x25, 0x64, 0x00, + 0x4c, 0x33, 0x20, 0x63, 0x6d, 0x64, 0x20, 0x25, 0x64, 0x3a, 0x20, 0x25, 0x78, 0x2c, 0x20, 0x6c, + 0x65, 0x6e, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x00, 0x4c, 0x33, 0x20, 0x61, 0x63, 0x63, 0x65, 0x73, + 0x73, 0x20, 0x66, 0x61, 0x69, 0x6c, 0x65, 0x64, 0x2c, 0x20, 0x63, 0x6d, 0x64, 0x3a, 0x20, 0x25, + 0x64, 0x2c, 0x20, 0x6c, 0x65, 0x6e, 0x3a, 0x20, 0x25, 0x64, 0x20, 0x00, 0x73, 0x65, 0x6e, 0x74, + 0x00, 0x00, 0x00, 0x00, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x20, 0x73, 0x6c, 0x65, 0x65, 0x70, 0x00, + 0x77, 0x61, 0x6b, 0x65, 0x75, 0x70, 0x00, 0x00, 0x9a, 0x19, 0x10, 0x00, 0xd8, 0x19, 0x10, 0x00, + 0x04, 0x1a, 0x10, 0x00, 0x34, 0x1a, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, + 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, + 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, + 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0x56, 0x1a, 0x10, 0x00, 0xb0, 0x1a, 0x10, 0x00, + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 0x00, 0x06, 0x01, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0xa0, 0x1f, 0x00, 0x06, 0x02, 0x00, 0x05, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x1c, 0x00, 0x06, 0x03, 0x10, 0x08, 0x00, 0x00, 0x18, 0x00, 0x00, 0x40, 0x1f, 0x00, 0x06, + 0x06, 0x10, 0x08, 0x00, 0x04, 0x18, 0x00, 0x00, 0x60, 0x1f, 0x00, 0x06, 0x04, 0x00, 0x09, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x06, 0x05, 0x05, 0x7f, 0x07, 0x01, 0x08, 0x18, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0xf0, 0x01, 0x10, 0x10, 0x00, 0x04, 0x02, 0x11, 0x00, 0x44, 0x02, + 0x12, 0x00, 0x84, 0x02, 0x20, 0x90, 0x01, 0x03, 0x21, 0x80, 0x42, 0x03, 0x22, 0xf0, 0x01, 0x03, + 0x30, 0x80, 0x02, 0x04, 0x31, 0x80, 0x42, 0x04, 0x40, 0x70, 0x04, 0x11, 0x41, 0x70, 0x44, 0x11, + 0x42, 0x70, 0x84, 0x11, 0x50, 0xf0, 0x01, 0x12, 0x60, 0x32, 0x04, 0x13, 0x61, 0x32, 0x44, 0x13, + 0x62, 0x32, 0x84, 0x13, 0x63, 0x32, 0xc4, 0x13, 0x70, 0x32, 0x04, 0x14, 0x71, 0x32, 0x44, 0x14, + 0x80, 0x20, 0x04, 0x15, 0x81, 0x20, 0x84, 0x15, 0x82, 0x20, 0x44, 0x15, 0x90, 0x51, 0x04, 0x16, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x0f, 0x00, 0x14, 0x04, 0x04, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x20, 0x25, 0x6c, + 0x75, 0x20, 0x00, 0x00, 0x25, 0x73, 0x28, 0x25, 0x73, 0x29, 0x3a, 0x20, 0x00, 0x00, 0x00, 0x00, + 0x0a, 0x00, 0x00, 0x00, 0x45, 0x00, 0x00, 0x00, 0x4d, 0x53, 0x47, 0x00, 0x43, 0x52, 0x43, 0x20, + 0x72, 0x78, 0x3a, 0x20, 0x25, 0x30, 0x34, 0x78, 0x2c, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x3a, 0x20, + 0x25, 0x30, 0x34, 0x78, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x40, 0x20, 0x10, 0x00, + 0x60, 0x20, 0x10, 0x00, 0xb2, 0x20, 0x10, 0x00, 0x14, 0x21, 0x10, 0x00, 0x1e, 0x21, 0x10, 0x00, + 0x4f, 0x53, 0x00, 0x00, 0x63, 0x6f, 0x6e, 0x64, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, + 0x43, 0x50, 0x42, 0x20, 0x49, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x20, 0x21, 0x00, + 0x43, 0x50, 0x42, 0x00, 0x57, 0x00, 0x00, 0x00, 0x46, 0x53, 0x53, 0x00, 0x49, 0x52, 0x51, 0x00, + 0x53, 0x54, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x4b, 0x44, 0x42, 0x00, 0x73, 0x74, 0x3a, 0x20, + 0x25, 0x78, 0x00, 0x00, 0x4d, 0x41, 0x44, 0x00, 0x4f, 0x54, 0x50, 0x00, 0x0c, 0x18, 0x00, 0x00, + 0x20, 0x00, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00, 0x10, 0x18, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, + 0x05, 0x0a, 0x0a, 0x0a, 0x14, 0x18, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x14, 0x14, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x53, 0x43, 0x42, 0x00, 0x4e, 0x6f, 0x69, 0x73, 0x65, 0x5f, 0x4b, 0x4b, 0x31, 0x5f, 0x32, 0x35, + 0x35, 0x31, 0x39, 0x5f, 0x41, 0x45, 0x53, 0x47, 0x43, 0x4d, 0x5f, 0x53, 0x48, 0x41, 0x32, 0x35, + 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0x40, 0x10, 0x00, 0x74, 0x46, 0x10, 0x00, + 0x5e, 0x46, 0x10, 0x00, 0x22, 0x46, 0x10, 0x00, 0x08, 0x3f, 0x10, 0x00, 0xcc, 0x46, 0x10, 0x00, + 0x41, 0x4c, 0x41, 0x52, 0x4d, 0x20, 0x43, 0x48, 0x41, 0x4e, 0x4e, 0x45, 0x4c, 0x53, 0x3a, 0x20, + 0x25, 0x78, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x53, 0x43, 0x4e, 0x54, 0x52, 0x00, 0x00, 0x00, + 0x53, 0x50, 0x45, 0x43, 0x54, 0x00, 0x00, 0x00, 0xc3, 0x14, 0x13, 0x00}; diff --git a/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_2_0_0/fw_SPECT.h b/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_2_0_0/fw_SPECT.h index fabbeaf72..f04140f54 100644 --- a/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_2_0_0/fw_SPECT.h +++ b/TROPIC01_fw_update_files/boot_v_1_0_1/fw_v_2_0_0/fw_SPECT.h @@ -5,552 +5,655 @@ /** * @brief SPECT firmware version spect_app-v1.0.0_signed.bin for bootloader v1.0.1 */ -const uint8_t fw_SPECT[] - = {0x37, 0xd9, 0x5c, 0xd3, 0xde, 0xc2, 0xd0, 0x50, 0x41, 0x15, 0x80, 0xf8, 0x8a, 0x1a, 0xd4, 0xcd, 0x55, 0x93, 0xb3, - 0xd8, 0x02, 0x35, 0x63, 0x5a, 0x70, 0xc4, 0x27, 0x3b, 0x96, 0x80, 0x19, 0xc9, 0x46, 0x9b, 0x56, 0xfe, 0x8d, 0x3a, - 0xa9, 0xa1, 0xe0, 0x97, 0x8e, 0xc5, 0x26, 0x7e, 0xf4, 0x4c, 0x5e, 0xea, 0xf5, 0xb1, 0xa9, 0x79, 0xda, 0xc8, 0x9a, - 0xf7, 0xdc, 0xf7, 0x8c, 0x8c, 0x87, 0x0b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x02, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa8, 0x24, 0x00, 0x00, 0x45, 0x07, 0xdd, 0x4c, 0xb7, 0xcf, 0xe1, 0x1e, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, - 0x7e, 0xa3, 0xe4, 0xa3, 0x00, 0x82, 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, 0x40, 0xa2, 0xff, 0x00, 0x48, 0xa3, 0x00, - 0x02, 0x82, 0x62, 0xf0, 0x10, 0x88, 0xa2, 0x20, 0x33, 0x4a, 0xc5, 0x00, 0x10, 0x40, 0x28, 0x2c, 0xa3, 0x00, 0x08, - 0x60, 0x40, 0x40, 0x28, 0x4c, 0x80, 0x00, 0x88, 0x10, 0x40, 0x40, 0xa8, 0x84, 0x80, 0x00, 0x08, 0x40, 0x40, 0x40, - 0xa8, 0xb8, 0x80, 0x00, 0x08, 0x70, 0x40, 0x40, 0xa8, 0x20, 0x81, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0x04, 0xa4, - 0x00, 0x82, 0xf4, 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x60, 0x10, 0x40, 0x28, 0x1c, - 0x9f, 0x00, 0x08, 0x61, 0x10, 0x40, 0xa8, 0x1c, 0x9f, 0x00, 0x08, 0x62, 0x10, 0x40, 0xa8, 0xa4, 0x9f, 0x00, 0x08, - 0x63, 0x10, 0x40, 0x28, 0xb0, 0xa0, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0xf3, 0x50, 0x8a, - 0xa4, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x11, 0x10, 0x40, 0x28, 0x60, 0xa2, 0x00, 0x08, 0x12, 0x10, - 0x40, 0x28, 0x9c, 0xa2, 0x00, 0x08, 0x13, 0x10, 0x40, 0xa8, 0xbc, 0xa2, 0x00, 0x88, 0x14, 0x10, 0x40, 0x28, 0xe0, - 0xa2, 0x00, 0x88, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x04, 0xa4, 0x00, 0x82, 0xf2, 0x50, 0x8a, 0x24, - 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x41, 0x10, 0x40, 0x28, 0x94, 0x8f, 0x00, 0x88, 0x42, 0x10, 0x40, - 0x28, 0xac, 0x90, 0x00, 0x88, 0x43, 0x10, 0x40, 0xa8, 0xd4, 0x90, 0x00, 0x88, 0x44, 0x10, 0x40, 0x28, 0x04, 0x91, - 0x00, 0x88, 0x45, 0x10, 0x40, 0xa8, 0xfc, 0x91, 0x00, 0x08, 0x46, 0x10, 0x40, 0xa8, 0xa0, 0x92, 0x00, 0x08, 0x47, - 0x10, 0x40, 0x28, 0xf4, 0x92, 0x00, 0x88, 0x48, 0x10, 0x40, 0x28, 0x30, 0x93, 0x00, 0x88, 0x49, 0x10, 0x40, 0xa8, - 0x48, 0x93, 0x00, 0x88, 0x4a, 0x10, 0x40, 0xa8, 0x18, 0x94, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, - 0x18, 0x04, 0xa4, 0x00, 0x82, 0xf1, 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x70, 0x10, - 0x40, 0xa8, 0x1c, 0xa1, 0x00, 0x88, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x02, 0x00, 0x44, 0x23, 0x64, - 0x81, 0x00, 0x02, 0x00, 0x00, 0x44, 0x69, 0x00, 0x00, 0x42, 0xa3, 0xf3, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, - 0x40, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x84, 0x50, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, - 0xf3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, 0x00, 0xf5, 0x00, 0x00, 0x00, 0xf5, 0xff, 0x00, - 0x42, 0xa3, 0x00, 0x10, 0x02, 0xf3, 0xff, 0x10, 0x82, 0xa4, 0x80, 0x00, 0x80, 0xe2, 0x00, 0x00, 0x00, 0x84, 0xa8, - 0xa4, 0x00, 0x18, 0x00, 0x10, 0x02, 0xf3, 0x00, 0x10, 0x02, 0xf3, 0x80, 0x00, 0x40, 0xe2, 0x00, 0x11, 0x40, 0x49, - 0x00, 0x00, 0xc0, 0x93, 0x80, 0x10, 0x84, 0xff, 0x80, 0x20, 0x86, 0x7f, 0x80, 0x31, 0x88, 0xff, 0x00, 0x42, 0x88, - 0xff, 0x80, 0x41, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, - 0x88, 0xff, 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x06, 0x00, 0x7c, 0x23, 0x00, - 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0xdc, 0x81, 0x00, 0x8a, - 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x0f, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, - 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0xfc, 0x81, 0x00, 0x0a, 0x80, 0x42, 0x8c, 0xff, 0x00, 0x63, - 0x88, 0xff, 0x3f, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, - 0xe0, 0x7d, 0xa4, 0x1c, 0x82, 0x00, 0x8a, 0x00, 0x43, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, - 0x1e, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, - 0xa4, 0x40, 0x82, 0x00, 0x8a, 0x00, 0x43, 0x88, 0x7f, 0x40, 0x30, 0x4a, 0xc5, 0x80, 0x00, 0x7c, 0xa3, 0x00, 0x42, - 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x50, 0x0a, 0x63, 0x80, 0x82, 0x00, 0x8c, 0x00, 0x50, 0x0a, 0x63, 0x94, - 0x82, 0x00, 0x0e, 0x80, 0x40, 0x88, 0xff, 0x94, 0x82, 0x00, 0x98, 0x00, 0x50, 0x0a, 0x63, 0x90, 0x82, 0x00, 0x0c, - 0x00, 0x41, 0x88, 0xff, 0x94, 0x82, 0x00, 0x98, 0x80, 0x41, 0x88, 0x7f, 0x02, 0xe0, 0x7d, 0x24, 0x60, 0x82, 0x00, - 0x0a, 0x00, 0x40, 0x42, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x86, 0xef, 0x80, 0x30, 0x88, 0xef, 0x00, 0x42, - 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, - 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x31, 0x86, 0x6f, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, - 0x00, 0x32, 0x8a, 0x6f, 0x80, 0x52, 0x86, 0xef, 0x09, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x01, 0xe0, 0x7d, - 0x24, 0xe0, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x86, 0xef, 0x0a, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, - 0x86, 0xef, 0x02, 0xe0, 0x7d, 0x24, 0xf4, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x8a, 0xef, 0x80, 0x52, 0x86, 0xef, 0x80, - 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x1e, 0x00, 0x7c, 0x23, - 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, 0x20, 0x83, 0x00, - 0x0a, 0x80, 0x30, 0x86, 0x6f, 0x80, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, - 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x04, 0xe0, 0x7d, 0x24, 0x3c, 0x83, 0x00, 0x8a, 0x00, 0x31, 0x86, 0x6f, 0x20, - 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, - 0x04, 0xe0, 0x7d, 0x24, 0x5c, 0x83, 0x00, 0x8a, 0x00, 0x31, 0x86, 0x6f, 0x1e, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, - 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, 0x7c, 0x83, 0x00, 0x0a, 0x80, 0x32, - 0x86, 0xef, 0x00, 0x00, 0x00, 0x84, 0xa4, 0x82, 0x00, 0x02, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, - 0x30, 0x82, 0xef, 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x84, 0xe7, 0x80, 0x20, 0x88, 0xe7, 0x00, 0x42, 0x86, 0x67, - 0x80, 0x31, 0x86, 0x67, 0x80, 0x41, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, - 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x07, 0x00, 0x7c, 0xa3, 0x80, 0x31, - 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xdc, 0x83, 0x00, 0x0a, 0x80, 0x21, 0x8a, 0xe7, 0x80, 0x52, 0x86, 0x67, 0x0f, - 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xf4, 0x83, 0x00, 0x0a, 0x80, 0x51, 0x84, 0xe7, - 0x00, 0x21, 0x86, 0x67, 0x0f, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x0c, 0x84, 0x00, - 0x0a, 0x80, 0x51, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x22, 0x8a, 0x67, 0x80, 0x52, - 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x30, 0x84, 0x00, 0x0a, 0x80, - 0x51, 0x84, 0xe7, 0x00, 0x21, 0x86, 0x67, 0x63, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, - 0x48, 0x84, 0x00, 0x0a, 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, - 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x60, 0x84, 0x00, 0x0a, 0x80, 0x32, 0x84, 0xe7, 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, - 0x00, 0x02, 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x30, 0x86, 0xe7, 0x80, 0x31, 0x86, 0x67, 0x80, - 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x00, 0x32, 0x82, 0x67, 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, 0x00, 0x02, - 0x00, 0x21, 0x80, 0x67, 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, - 0xe7, 0x00, 0x00, 0x80, 0x67, 0x00, 0x21, 0x84, 0xe7, 0x80, 0x20, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x32, - 0x48, 0x45, 0x00, 0x22, 0x86, 0x67, 0x00, 0x21, 0x88, 0xe7, 0x80, 0x40, 0x88, 0xe8, 0xdc, 0x84, 0x00, 0x8a, 0x00, - 0x20, 0x42, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x30, 0x42, 0x63, 0x00, 0x00, 0x00, 0x84, 0x00, 0x90, 0x42, 0x63, - 0x74, 0x84, 0x00, 0x82, 0x80, 0x70, 0x8e, 0xe7, 0x80, 0x80, 0x90, 0xe7, 0x01, 0x00, 0x42, 0x23, 0x80, 0x70, 0x8e, - 0xe2, 0x00, 0x80, 0x10, 0xeb, 0x80, 0x83, 0x90, 0xe4, 0x00, 0x80, 0x10, 0xed, 0x00, 0x80, 0x10, 0xf9, 0x00, 0x00, - 0x00, 0x84, 0x00, 0xc0, 0x60, 0x63, 0x00, 0x00, 0x21, 0x63, 0x24, 0x85, 0x00, 0x8c, 0x00, 0x00, 0x6c, 0xa3, 0x2c, - 0x85, 0x00, 0x18, 0x01, 0x00, 0x6c, 0x23, 0x2c, 0x85, 0x00, 0x18, 0x00, 0x00, 0x21, 0x65, 0x00, 0x00, 0x59, 0x63, - 0x00, 0x08, 0xa1, 0xe7, 0x01, 0x00, 0x42, 0x23, 0x80, 0x00, 0xa9, 0xfd, 0x00, 0x03, 0xa1, 0x67, 0x80, 0x00, 0xab, - 0x7b, 0x80, 0x5a, 0xa5, 0x67, 0x80, 0x2a, 0xa5, 0xe7, 0x00, 0x2a, 0xa7, 0xe7, 0x00, 0x29, 0xa5, 0x67, 0x80, 0x2a, - 0xa5, 0xe7, 0x00, 0x2a, 0x83, 0xe7, 0x00, 0x10, 0x60, 0xe3, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0xa4, 0x67, 0x00, - 0x29, 0xa5, 0x67, 0x00, 0x28, 0xa5, 0xe7, 0x80, 0x29, 0xa5, 0xe7, 0x00, 0x29, 0xa1, 0xe7, 0x80, 0x0a, 0xa1, 0xe7, - 0x00, 0x32, 0x42, 0x45, 0x80, 0x20, 0xa3, 0xe7, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x0a, 0xbd, 0xe8, 0x9c, 0x85, 0x00, - 0x8a, 0x00, 0x20, 0x41, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x7c, 0x23, 0x00, 0xea, 0xa9, 0xfd, 0x00, 0x0a, - 0xbd, 0xe8, 0xb4, 0x85, 0x00, 0x8a, 0x00, 0x10, 0x41, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x10, 0x40, 0x28, 0x10, - 0x86, 0x00, 0x88, 0x00, 0x00, 0x42, 0xa3, 0x00, 0xe0, 0xbd, 0x68, 0xcc, 0x85, 0x00, 0x8a, 0x01, 0x10, 0x82, 0x24, - 0x01, 0x60, 0x41, 0xa8, 0xd8, 0x85, 0x00, 0x8a, 0x02, 0x10, 0x82, 0x24, 0x03, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, - 0x88, 0x00, 0x00, 0x46, 0x23, 0x00, 0x30, 0x86, 0xfd, 0x01, 0x00, 0x7c, 0xa3, 0x00, 0x0f, 0x82, 0xe2, 0x00, 0x1b, - 0x40, 0x68, 0x00, 0x86, 0x00, 0x8a, 0x00, 0x00, 0x56, 0x63, 0x08, 0x86, 0x00, 0x18, 0x00, 0x30, 0x56, 0x63, 0x08, - 0x86, 0x00, 0x18, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x00, 0x84, 0xff, 0x0f, 0x42, 0xa3, 0x00, 0x00, 0x00, 0x84, - 0x80, 0x83, 0x80, 0xfd, 0x80, 0xc5, 0x82, 0xfd, 0x80, 0x00, 0x80, 0xe7, 0x80, 0x83, 0x82, 0x7b, 0x80, 0xc5, 0x84, - 0xfb, 0x00, 0x11, 0x82, 0xe7, 0x00, 0xa7, 0x84, 0x67, 0x00, 0x23, 0x84, 0x67, 0x00, 0x21, 0x84, 0x7b, 0x80, 0x96, - 0x86, 0xe7, 0x80, 0x31, 0x86, 0xfb, 0x00, 0x10, 0x88, 0xfd, 0x00, 0x10, 0x80, 0x7b, 0x00, 0x31, 0x82, 0xfd, 0x00, - 0x31, 0x84, 0xfb, 0x80, 0x40, 0x96, 0xe7, 0x00, 0x40, 0x9c, 0x67, 0x00, 0x20, 0x98, 0xe7, 0x80, 0x20, 0x9a, 0xe7, - 0x00, 0x00, 0x00, 0x84, 0x80, 0x73, 0x80, 0x67, 0x00, 0x84, 0x82, 0xe7, 0x80, 0x94, 0x84, 0xe7, 0x00, 0x21, 0x84, - 0x7b, 0x80, 0x00, 0x86, 0x7b, 0x00, 0x74, 0x88, 0x7b, 0x00, 0x42, 0x88, 0xe7, 0x00, 0x32, 0x88, 0xfd, 0x80, 0x00, - 0x80, 0x7d, 0x00, 0x20, 0x82, 0xfb, 0x80, 0x40, 0x8e, 0xe7, 0x80, 0x00, 0x92, 0xe7, 0x80, 0x01, 0x90, 0xe7, 0x80, - 0x41, 0x94, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x4e, 0xa3, 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, 0xa3, - 0x00, 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, - 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, - 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0xb8, - 0x86, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x56, 0xc9, 0x20, 0x05, 0x58, 0xc9, 0x40, 0x05, 0x5a, 0x49, - 0x00, 0x00, 0x4e, 0xa3, 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, - 0xa3, 0x00, 0x00, 0xde, 0xf3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, - 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, - 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, - 0x14, 0x87, 0x00, 0x0a, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xb0, 0x4e, - 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, 0x68, 0x86, - 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x01, - 0xe0, 0x7d, 0x24, 0x50, 0x87, 0x00, 0x0a, 0x00, 0x00, 0x7c, 0x23, 0x80, 0xe3, 0x8f, 0xfd, 0x00, 0xe5, 0x95, 0xfd, - 0x18, 0x86, 0x00, 0x02, 0x80, 0xe3, 0x8f, 0xfd, 0x00, 0xe5, 0x95, 0xfd, 0x00, 0x05, 0x40, 0x45, 0x20, 0x05, 0x42, - 0x45, 0x40, 0x05, 0x44, 0x45, 0x80, 0x06, 0x80, 0xe7, 0x80, 0x16, 0x82, 0xe7, 0x00, 0xb1, 0x96, 0xe7, 0x00, 0xc1, - 0x98, 0xe7, 0x80, 0x05, 0xbc, 0xe8, 0xd4, 0x87, 0x00, 0x0a, 0x00, 0x16, 0xbc, 0xe8, 0xd4, 0x87, 0x00, 0x0a, 0x00, - 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x40, 0x31, 0x7e, 0xc5, - 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xae, 0x24, 0x80, 0x5b, 0xab, - 0x67, 0x00, 0x5b, 0xb1, 0x67, 0x80, 0x6b, 0xad, 0x67, 0x98, 0x96, 0x00, 0x02, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x00, - 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0x02, 0x56, 0x49, 0x20, - 0x02, 0x58, 0x49, 0x40, 0x02, 0x5a, 0xc9, 0x60, 0x02, 0x5c, 0x49, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, - 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0x02, 0x56, 0x45, 0x20, 0x02, 0x58, - 0x45, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, 0x45, 0x00, 0x02, 0x4e, 0x49, 0x20, 0x02, 0x50, 0xc9, 0x40, 0x02, - 0x52, 0x49, 0x60, 0x02, 0x54, 0xc9, 0x00, 0x50, 0x4f, 0xe3, 0x00, 0x60, 0x51, 0xe3, 0x00, 0x70, 0x53, 0xe3, 0x00, - 0x80, 0x55, 0xe3, 0x00, 0x00, 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, 0x00, 0x07, 0x9c, 0xfd, 0x18, 0x86, 0x00, 0x02, - 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, - 0xc5, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, - 0x00, 0x0a, 0x00, 0x02, 0x56, 0x45, 0x20, 0x02, 0x58, 0x45, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, 0x45, 0x18, - 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0x00, 0xe0, 0x54, 0x63, - 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, 0x74, 0x84, 0x00, 0x82, 0x80, 0xb0, 0xaa, - 0xe7, 0x80, 0xc0, 0xac, 0x67, 0x80, 0x5a, 0x83, 0xe7, 0x00, 0x6b, 0x85, 0xe7, 0x80, 0x20, 0x86, 0xfd, 0x00, 0x11, - 0x88, 0xe7, 0x00, 0x43, 0x88, 0x67, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x40, 0x88, 0xfb, 0x00, 0x32, 0x80, 0xe8, 0x08, - 0x89, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, - 0x80, 0x73, 0x80, 0x67, 0x00, 0x84, 0x82, 0xe7, 0x80, 0x94, 0x84, 0xe7, 0x00, 0x10, 0x86, 0x7d, 0x00, 0x31, 0x86, - 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x03, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x01, 0x80, 0x7b, 0x00, 0x30, - 0x86, 0x68, 0x48, 0x89, 0x00, 0x8a, 0x00, 0x74, 0x80, 0x67, 0x00, 0x95, 0x86, 0x67, 0x00, 0x30, 0x86, 0x68, 0x00, - 0x00, 0x00, 0x84, 0x00, 0x96, 0x80, 0xef, 0x80, 0xa6, 0x82, 0xef, 0x00, 0xb7, 0x84, 0x6f, 0x00, 0x95, 0x86, 0xfb, - 0x80, 0xc6, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x6f, 0x80, 0x00, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x7d, 0x80, 0xa5, 0x88, - 0xfb, 0x00, 0xd7, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xef, 0x00, 0x11, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xfd, 0x80, 0x95, - 0x8a, 0x7b, 0x00, 0xc7, 0x8c, 0x7b, 0x00, 0x53, 0x8a, 0xef, 0x00, 0x01, 0x8c, 0x7b, 0x00, 0x53, 0x8c, 0xfd, 0x00, - 0x81, 0x8e, 0x6f, 0x80, 0x63, 0x8a, 0x7d, 0x80, 0x52, 0x8e, 0x7b, 0x80, 0x53, 0x8a, 0x7b, 0x80, 0x12, 0x8e, 0xfd, - 0x80, 0x12, 0x8a, 0x7b, 0x00, 0x83, 0x8c, 0x6f, 0x00, 0x21, 0x82, 0x7b, 0x00, 0x11, 0x84, 0x7b, 0x00, 0x61, 0x8c, - 0x7d, 0x00, 0x60, 0x8c, 0xfd, 0x00, 0x63, 0x82, 0x7b, 0x00, 0x13, 0x8c, 0x7b, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, - 0x80, 0x7b, 0x00, 0x01, 0x80, 0x7d, 0x00, 0x43, 0x82, 0xef, 0x00, 0x03, 0x84, 0x6f, 0x80, 0x53, 0x8c, 0x6f, 0x00, - 0x61, 0x9a, 0xfb, 0x80, 0x32, 0x8a, 0xef, 0x80, 0x50, 0x98, 0x7d, 0x80, 0x43, 0x8e, 0x6f, 0x00, 0x30, 0x82, 0x6f, - 0x80, 0x70, 0x9c, 0x7b, 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0xef, 0x00, 0xa5, 0x82, 0x6f, 0x80, 0xb5, 0x84, - 0x6f, 0x00, 0x95, 0x86, 0xef, 0x80, 0x31, 0x86, 0xfb, 0x80, 0x95, 0x8e, 0xef, 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x81, - 0x8c, 0xef, 0x80, 0x63, 0x8c, 0x7d, 0x00, 0x63, 0x8a, 0xfb, 0x00, 0x53, 0x8c, 0xfb, 0x00, 0x13, 0x8a, 0x7d, 0x00, - 0x13, 0x8c, 0x7b, 0x00, 0x53, 0x8c, 0xef, 0x80, 0x51, 0x8a, 0xef, 0x00, 0x21, 0x86, 0xfb, 0x80, 0x21, 0x84, 0xfb, - 0x80, 0x83, 0x8e, 0x6f, 0x00, 0x71, 0x8e, 0x7d, 0x00, 0x70, 0x8e, 0xfd, 0x80, 0x73, 0x86, 0xfb, 0x80, 0x71, 0x8e, - 0xfb, 0x00, 0x00, 0x86, 0xfb, 0x00, 0x30, 0x80, 0xfb, 0x00, 0x01, 0x80, 0x7d, 0x80, 0x03, 0x80, 0x6f, 0x00, 0x60, - 0x8c, 0xfb, 0x80, 0xa5, 0x80, 0x6f, 0x00, 0x00, 0x80, 0xfb, 0x80, 0x03, 0x8e, 0xef, 0x80, 0x53, 0x8a, 0x7d, 0x80, - 0x00, 0x8e, 0xef, 0x80, 0x73, 0x8e, 0x7b, 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x50, 0x52, 0xe3, 0x00, 0x60, 0x54, 0xe3, - 0x00, 0x70, 0x56, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, 0x00, 0x56, - 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, - 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, - 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xa8, 0x8a, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, - 0x00, 0x05, 0x58, 0x49, 0x20, 0x05, 0x5a, 0x49, 0x40, 0x05, 0x5c, 0x49, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, - 0xa3, 0x00, 0x00, 0x56, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xde, 0xf3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xd0, - 0x3b, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, - 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, - 0xf8, 0x8a, 0x00, 0x0a, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, - 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, - 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x2c, 0x8b, 0x00, 0x8a, 0x00, - 0x00, 0x7c, 0x23, 0x00, 0xe5, 0x95, 0xfd, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe5, 0x95, 0xfd, 0x00, 0x05, 0x40, 0x45, - 0x20, 0x05, 0x42, 0x45, 0x40, 0x05, 0x44, 0x45, 0x00, 0x07, 0x80, 0x6f, 0x00, 0x17, 0x82, 0x6f, 0x00, 0xc1, 0x98, - 0x6f, 0x00, 0xd1, 0x9a, 0x6f, 0x00, 0x06, 0xbc, 0x68, 0xa0, 0x8b, 0x00, 0x0a, 0x80, 0x16, 0xbc, 0x68, 0xa0, 0x8b, - 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, - 0x30, 0x7e, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xb0, 0x24, - 0x00, 0x6c, 0xad, 0xef, 0x00, 0x7c, 0xaf, 0xef, 0xc8, 0x97, 0x00, 0x82, 0x00, 0x10, 0x53, 0xe3, 0x00, 0x20, 0x55, - 0xe3, 0x00, 0x30, 0x57, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, - 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0x80, 0x30, 0x50, 0x45, 0x00, 0x10, 0x59, 0xe3, 0x00, - 0x20, 0x5b, 0x63, 0x00, 0x30, 0x5d, 0xe3, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x94, 0x8c, 0x00, 0x0a, - 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0x00, 0x80, 0x68, 0x00, 0x60, 0x53, 0x6f, 0x00, 0x70, 0x55, - 0xef, 0x00, 0x80, 0x57, 0x6f, 0x00, 0x10, 0x59, 0xe3, 0x00, 0x20, 0x5b, 0x63, 0x00, 0x30, 0x5d, 0xe3, 0x80, 0x06, - 0x9a, 0xfd, 0x4c, 0x89, 0x00, 0x82, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x00, - 0x30, 0x7e, 0xc5, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x94, 0x8c, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, - 0x94, 0x8c, 0x00, 0x0a, 0x00, 0x60, 0x59, 0x63, 0x00, 0x70, 0x5b, 0x63, 0x00, 0x80, 0x5d, 0x63, 0x4c, 0x89, 0x00, - 0x82, 0x00, 0xc0, 0x52, 0xe3, 0x00, 0xd0, 0x54, 0x63, 0x00, 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, - 0x00, 0x0a, 0x00, 0xe0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0xc0, 0xac, 0xef, 0x80, 0xd0, 0xae, 0xef, 0x00, - 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x30, 0x40, 0x45, - 0x80, 0x30, 0x42, 0x45, 0x00, 0xa5, 0x86, 0xef, 0x80, 0x35, 0x86, 0x6f, 0x80, 0x94, 0x84, 0x6f, 0x80, 0x24, 0x84, - 0xef, 0x80, 0xb5, 0x88, 0x6f, 0x80, 0x45, 0x8a, 0xef, 0x80, 0x04, 0x80, 0xef, 0x00, 0x02, 0x80, 0x6f, 0x80, 0x12, - 0x82, 0xef, 0x80, 0x00, 0x80, 0x7b, 0x00, 0x01, 0x80, 0x7b, 0x80, 0x01, 0x80, 0x68, 0x00, 0x00, 0x00, 0x84, 0x60, - 0x32, 0x40, 0xc5, 0x00, 0x08, 0x80, 0xe7, 0x00, 0x08, 0x83, 0xe7, 0x00, 0x10, 0x82, 0xfb, 0x01, 0x00, 0x40, 0xa3, - 0x00, 0x10, 0x82, 0xfb, 0x00, 0x18, 0x82, 0xe7, 0x98, 0x84, 0x00, 0x02, 0x00, 0x10, 0x62, 0x63, 0x01, 0x00, 0x44, - 0x23, 0x00, 0x20, 0x84, 0x70, 0x00, 0x01, 0x84, 0x62, 0x00, 0x00, 0x00, 0x84, 0xc0, 0x32, 0x68, 0xc5, 0xe0, 0x32, - 0x6a, 0xc5, 0xa0, 0x32, 0x6c, 0x45, 0x00, 0x64, 0x8b, 0x67, 0x80, 0x53, 0x8a, 0x7b, 0x00, 0x66, 0x8d, 0xe7, 0x80, - 0x65, 0x8c, 0x7b, 0x00, 0x53, 0x80, 0x67, 0x80, 0x96, 0x82, 0x67, 0x00, 0x86, 0x84, 0x67, 0x80, 0x54, 0x86, 0xfb, - 0x80, 0x66, 0x88, 0xfb, 0x00, 0x32, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x7d, 0x00, 0x54, 0x88, - 0xfb, 0x00, 0x66, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0x67, 0x00, 0x01, 0x8a, 0x7b, 0x80, 0x42, 0x88, 0xfd, 0x00, 0x94, - 0x8a, 0x7b, 0x00, 0xd6, 0x96, 0xfb, 0x80, 0x55, 0x8a, 0xe7, 0x00, 0x11, 0x96, 0x7b, 0x80, 0x55, 0x8a, 0x7d, 0x00, - 0x42, 0x99, 0xe7, 0x00, 0x51, 0x97, 0xe7, 0x00, 0xb6, 0x98, 0x7b, 0x00, 0x16, 0x96, 0xfd, 0x00, 0x16, 0x98, 0x7b, - 0x00, 0xb6, 0x9a, 0x67, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x82, 0xfb, 0x00, 0x41, 0x85, 0x67, 0x00, 0x52, 0x89, - 0xe7, 0x00, 0x11, 0x82, 0x7b, 0x00, 0x01, 0x84, 0xfd, 0x00, 0x41, 0x85, 0x67, 0x00, 0x41, 0x88, 0x7b, 0x00, 0x12, - 0x80, 0x67, 0x00, 0xd0, 0x9a, 0xfb, 0x00, 0x52, 0x80, 0xe7, 0x80, 0x35, 0x96, 0x67, 0x00, 0xb0, 0x96, 0xfd, 0x80, - 0x30, 0x80, 0xe7, 0x00, 0x56, 0x98, 0x67, 0x00, 0xc0, 0x98, 0xfb, 0x00, 0x66, 0xad, 0x67, 0x00, 0xbb, 0x96, 0x7d, - 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0x67, 0x00, 0x04, 0x80, 0xe7, 0x60, 0x32, 0x42, 0x45, 0x80, 0x13, 0x82, - 0xe7, 0x00, 0x14, 0x82, 0x7b, 0x00, 0x14, 0x82, 0xe7, 0x80, 0x73, 0x84, 0xe7, 0x00, 0x11, 0x82, 0x7b, 0x80, 0x13, - 0x82, 0xe7, 0x80, 0x00, 0x80, 0xe8, 0x00, 0x00, 0x00, 0x84, 0x00, 0x74, 0x80, 0xfb, 0x00, 0x95, 0x82, 0x7d, 0x00, - 0x10, 0x82, 0x67, 0x00, 0x74, 0x80, 0xfd, 0x00, 0x95, 0x84, 0x7b, 0x00, 0x20, 0x84, 0x67, 0x00, 0x11, 0x86, 0xfb, - 0x80, 0x31, 0x86, 0x67, 0x00, 0x11, 0x88, 0x7d, 0x00, 0x42, 0x88, 0xe7, 0x00, 0x36, 0x92, 0x67, 0x00, 0xb2, 0x94, - 0x67, 0x00, 0x00, 0x00, 0x84, 0x00, 0x74, 0x82, 0x7b, 0x80, 0x10, 0x82, 0xe7, 0x00, 0x74, 0x84, 0x7d, 0x00, 0x21, - 0x84, 0xe7, 0x00, 0x11, 0x8e, 0xe7, 0x00, 0x11, 0x82, 0x7d, 0x80, 0x60, 0x86, 0xe7, 0x00, 0x31, 0x86, 0x7b, 0x80, - 0x11, 0x90, 0x67, 0x00, 0x00, 0x00, 0x84, 0x80, 0x32, 0x4c, 0x45, 0x00, 0xb0, 0x52, 0x63, 0x00, 0xc0, 0x54, 0xe3, - 0x01, 0x00, 0x4e, 0x23, 0x00, 0x00, 0x50, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xf6, 0xf3, 0x00, 0xb0, 0x37, - 0xeb, 0x00, 0xd0, 0x3b, 0xeb, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, - 0x00, 0x02, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x78, 0x8e, 0x00, 0x0a, 0x00, - 0x01, 0x7c, 0xa3, 0x00, 0xb0, 0x37, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, - 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, 0x00, 0x02, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, - 0x24, 0xa4, 0x8e, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x76, 0x80, 0xe7, 0x00, 0xb4, 0x82, 0xe7, 0x00, 0x86, - 0x84, 0x67, 0x60, 0x32, 0x4c, 0xc5, 0x00, 0x63, 0x86, 0xfb, 0x00, 0x31, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, 0x80, - 0x41, 0x88, 0xfb, 0x80, 0xb3, 0x8a, 0x67, 0x00, 0x51, 0x8a, 0x7b, 0x80, 0x42, 0x88, 0x67, 0x00, 0x31, 0x86, 0xe7, - 0x80, 0x41, 0x88, 0xfd, 0x00, 0x45, 0x88, 0x67, 0x80, 0x00, 0x82, 0xfd, 0x80, 0x10, 0x82, 0xe7, 0x80, 0x14, 0x82, - 0x67, 0x80, 0x40, 0x92, 0xfd, 0x80, 0xd6, 0x86, 0xfb, 0x00, 0x34, 0x86, 0xe7, 0x00, 0x35, 0x86, 0x67, 0x00, 0x30, - 0x8e, 0xe7, 0x00, 0x31, 0x90, 0x67, 0x00, 0x00, 0x00, 0x84, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, - 0x00, 0x42, 0xa3, 0x00, 0xe0, 0x45, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x47, 0xe5, 0x20, 0xe0, 0x7d, 0x22, - 0x00, 0xe0, 0x49, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4b, 0xe5, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4d, - 0xe5, 0x00, 0x20, 0x04, 0xf9, 0x00, 0x30, 0x06, 0xf9, 0x00, 0x40, 0x08, 0xf9, 0x00, 0x50, 0x0a, 0xf9, 0x00, 0x60, - 0x0c, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x11, 0x02, 0xfd, 0x80, 0x21, 0x04, 0x7d, 0x00, 0x32, 0x06, 0xfd, 0x80, - 0x42, 0x08, 0x7d, 0x00, 0x53, 0x0a, 0x7d, 0x00, 0x60, 0x0c, 0xf3, 0x00, 0x00, 0x00, 0x84, 0x58, 0x81, 0x00, 0x02, - 0x00, 0x00, 0x48, 0x22, 0x00, 0x40, 0x44, 0xe5, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x20, 0x2c, 0x63, 0x01, 0x60, 0x6b, - 0x22, 0x00, 0x00, 0x42, 0xa3, 0x04, 0x54, 0xe1, 0x35, 0x88, 0x90, 0x00, 0x9c, 0xff, 0x00, 0x40, 0x23, 0x00, 0x00, - 0xa3, 0xe2, 0x02, 0x10, 0x41, 0x28, 0x94, 0x90, 0x00, 0x8a, 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0x21, 0xf5, 0x00, - 0x00, 0x21, 0xf5, 0x00, 0x00, 0xa3, 0xe2, 0x00, 0x20, 0x84, 0x62, 0x00, 0x11, 0x41, 0xe8, 0xa0, 0x90, 0x00, 0x0a, - 0x05, 0x54, 0xf3, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x00, 0x03, 0x72, 0xc9, 0x05, 0x54, 0xc1, 0x39, 0x88, 0x90, 0x00, - 0x9c, 0x00, 0x60, 0x6b, 0xe3, 0x00, 0x54, 0xf5, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x01, 0x54, 0xef, 0xb5, 0x88, 0x90, - 0x00, 0x9c, 0x02, 0x54, 0xfb, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x03, 0x54, 0xfd, 0x35, 0x88, 0x90, 0x00, 0x9c, 0x05, - 0x54, 0xc1, 0x39, 0x88, 0x90, 0x00, 0x9c, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, - 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, 0x00, 0xd0, 0xbb, 0xfb, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x71, 0xaf, - 0xe8, 0x00, 0xe1, 0xbd, 0xe8, 0x00, 0x7f, 0xa9, 0x68, 0xe0, 0x03, 0x74, 0x49, 0x00, 0x04, 0x7a, 0xc9, 0xa0, 0x00, - 0x60, 0xc5, 0x00, 0x00, 0x21, 0xf9, 0xc0, 0x00, 0x62, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, - 0x81, 0x00, 0x98, 0x05, 0x54, 0xc1, 0x39, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x12, 0x00, 0x44, 0xa3, - 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x00, 0x84, 0x6c, 0x90, 0x00, 0x82, 0xf2, 0x00, 0x40, - 0xa3, 0x94, 0x81, 0x00, 0x98, 0x6c, 0x90, 0x00, 0x82, 0xf4, 0x00, 0x40, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x6c, 0x90, - 0x00, 0x82, 0xf6, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x00, 0x00, 0xce, 0x73, 0x00, 0x00, 0xd0, 0x73, 0x00, - 0x00, 0xd2, 0xf3, 0x00, 0x00, 0xd4, 0xf3, 0x00, 0x70, 0xc0, 0xe3, 0x0c, 0x40, 0xc1, 0xa5, 0x4c, 0xa3, 0x00, 0x02, - 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x30, 0x8f, 0x00, 0x02, 0x08, 0x00, 0x56, - 0x23, 0x12, 0x00, 0x58, 0x23, 0x78, 0x8f, 0x00, 0x02, 0x01, 0xc0, 0x58, 0x24, 0xe0, 0x90, 0x00, 0x8a, 0x00, 0x10, - 0xc0, 0xe9, 0x01, 0xb0, 0x56, 0x24, 0xdc, 0x90, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, - 0x81, 0x00, 0x98, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, 0x30, 0x8f, 0x00, 0x02, 0x80, 0x00, 0x5e, 0xa3, - 0x00, 0xf0, 0x1e, 0xf3, 0x00, 0xf0, 0x1e, 0xf3, 0x00, 0xf0, 0x1e, 0xf3, 0x12, 0xb0, 0x56, 0xa4, 0x80, 0xb7, 0xa0, - 0x62, 0x44, 0x91, 0x00, 0x8a, 0x12, 0x00, 0x58, 0x23, 0x78, 0x8f, 0x00, 0x02, 0x01, 0xc0, 0x58, 0x24, 0x30, 0x91, - 0x00, 0x8a, 0x00, 0x10, 0xc0, 0xe9, 0x20, 0x91, 0x00, 0x18, 0x12, 0xb0, 0x56, 0xa2, 0x88, 0x91, 0x00, 0x08, 0x12, - 0x00, 0x58, 0x23, 0x80, 0xc5, 0x58, 0xe4, 0x78, 0x8f, 0x00, 0x02, 0x01, 0xb0, 0x56, 0x24, 0x54, 0x91, 0x00, 0x0a, - 0x01, 0xc0, 0x40, 0x28, 0x9c, 0x91, 0x00, 0x08, 0x04, 0x00, 0x44, 0x23, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x11, 0x02, - 0xfd, 0x00, 0x20, 0x04, 0xf3, 0x01, 0xc0, 0x58, 0x24, 0x70, 0x91, 0x00, 0x0a, 0x80, 0x10, 0x82, 0x24, 0xac, 0x91, - 0x00, 0x98, 0x00, 0x00, 0x42, 0xa3, 0x8a, 0x00, 0x46, 0xa3, 0x80, 0x11, 0xc2, 0xe2, 0x80, 0x10, 0x82, 0x24, 0xac, - 0x91, 0x00, 0x98, 0x84, 0x00, 0x44, 0xa3, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x11, 0x02, 0xfd, 0xac, 0x91, 0x00, 0x98, - 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf6, 0x71, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x70, 0xce, 0xeb, 0x00, 0x70, 0xd2, - 0x6b, 0x00, 0x70, 0xc0, 0xe3, 0x0c, 0xb0, 0xc1, 0xa5, 0x04, 0x00, 0x42, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x10, - 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xd0, 0x91, 0x00, 0x0a, 0x80, 0x10, 0x82, 0x24, 0x00, 0x10, 0xc0, 0xe9, 0x00, - 0x00, 0xf8, 0xf1, 0x60, 0x31, 0x7e, 0x45, 0x80, 0xcd, 0xb7, 0xf9, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, - 0x94, 0x81, 0x00, 0x98, 0x40, 0x31, 0x7e, 0xc5, 0xc0, 0x31, 0x6a, 0x45, 0xe0, 0x31, 0x6c, 0xc5, 0xdc, 0x87, 0x00, - 0x02, 0x01, 0x00, 0x42, 0x23, 0x80, 0x50, 0xab, 0xe2, 0x00, 0x50, 0x2b, 0xed, 0x80, 0x6a, 0xad, 0xe4, 0x00, 0x60, - 0x2d, 0xf9, 0x20, 0x03, 0x6c, 0x49, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x58, 0x81, 0x00, 0x02, 0x00, - 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x6b, 0x65, 0x00, 0x50, 0x2b, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x69, 0xe5, - 0x00, 0x40, 0x29, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x67, 0x65, 0x00, 0x30, 0x27, 0xf9, 0x20, 0xe0, 0x7d, - 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x20, 0x25, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x4c, 0x23, 0x00, 0x60, - 0x8a, 0x70, 0x60, 0xb0, 0x92, 0x22, 0x1f, 0xb0, 0x90, 0x22, 0x20, 0x00, 0x4e, 0x23, 0x00, 0x74, 0x50, 0xe4, 0x00, - 0x80, 0x4e, 0xe3, 0x00, 0x70, 0x0e, 0x63, 0x00, 0x70, 0x0e, 0x63, 0x00, 0x70, 0x0e, 0x63, 0x01, 0x70, 0x4e, 0x24, - 0x00, 0x53, 0x0a, 0x7d, 0x01, 0x80, 0x50, 0x24, 0x90, 0x92, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, 0x70, 0x81, 0x00, - 0x02, 0x00, 0x00, 0x56, 0x63, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x67, 0x65, 0x20, 0xe0, - 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x20, 0x25, 0xf9, 0x00, 0x03, 0x68, 0x45, 0x20, - 0x03, 0x6a, 0x45, 0x40, 0xb0, 0x7a, 0xa2, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, - 0x00, 0x00, 0xc0, 0x2d, 0x64, 0x92, 0x00, 0x82, 0x20, 0x90, 0x40, 0x28, 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, - 0xe3, 0xac, 0x93, 0x00, 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x67, 0x65, 0x20, 0xe0, - 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x20, 0x25, 0xf9, 0x00, 0x03, 0x68, 0x45, 0x20, - 0x03, 0x6a, 0x45, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x20, 0xe1, 0x6b, 0x80, 0x00, 0x7a, 0xa3, 0x00, 0x00, 0x40, 0x23, - 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x2c, 0x92, 0x00, 0x82, 0x00, 0x20, 0xe1, 0x6b, 0x80, 0xd0, 0x7b, - 0x22, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, - 0x56, 0x63, 0x80, 0xd5, 0x7b, 0xe2, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x2c, - 0x92, 0x00, 0x82, 0x80, 0xb0, 0x40, 0xa8, 0xdc, 0x93, 0x00, 0x08, 0x64, 0x92, 0x00, 0x82, 0x60, 0x90, 0x40, 0xa8, - 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, 0xe3, 0x40, 0x90, 0x40, 0x28, 0xac, 0x93, 0x00, 0x88, 0x00, 0x00, 0x66, - 0xa3, 0x20, 0x90, 0x40, 0x28, 0xa0, 0x93, 0x00, 0x88, 0x00, 0x00, 0x68, 0x23, 0x80, 0x52, 0xab, 0x62, 0x80, 0x53, - 0xeb, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x42, 0xa9, 0x62, 0x80, 0x43, 0xe9, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, - 0x32, 0xa7, 0x62, 0x80, 0x33, 0xe7, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x22, 0xa5, 0x62, 0x80, 0x23, 0xe5, 0x62, - 0x10, 0xb0, 0x90, 0x22, 0xd0, 0x93, 0x00, 0x8a, 0x80, 0x2e, 0xa5, 0x64, 0xf8, 0x93, 0x00, 0x98, 0x00, 0x20, 0xe1, - 0x6b, 0x00, 0x00, 0x6a, 0xa3, 0xec, 0x93, 0x00, 0x98, 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x6a, 0xa3, 0xff, 0x00, - 0x4e, 0xa3, 0x80, 0x53, 0xeb, 0x62, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x66, 0xa3, 0x00, 0xd0, 0x65, 0xe3, 0x60, - 0x31, 0x7e, 0x45, 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x21, 0xf9, 0x00, 0x10, 0x23, 0xf9, 0x80, 0x08, 0xb3, 0x79, - 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x60, 0x31, 0x7e, 0x45, 0xe0, 0x03, 0x74, - 0x45, 0x00, 0x04, 0x44, 0x45, 0x80, 0xac, 0x83, 0xff, 0x80, 0x2c, 0x84, 0xff, 0x80, 0xb0, 0x87, 0x7b, 0x00, 0x31, - 0x86, 0x7b, 0x40, 0x03, 0x46, 0xc9, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0x03, 0x58, 0x45, 0x00, - 0xc0, 0x18, 0xf9, 0x10, 0x85, 0x00, 0x82, 0x00, 0x10, 0xbc, 0x28, 0x10, 0x95, 0x00, 0x8a, 0x01, 0x00, 0x5a, 0x23, - 0x00, 0xb6, 0x9c, 0x67, 0x00, 0x90, 0x79, 0xe3, 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x4e, 0xc9, 0x80, 0x03, 0x50, - 0x49, 0xa0, 0x03, 0x52, 0x49, 0xc0, 0x03, 0x54, 0x49, 0x40, 0x03, 0x78, 0x45, 0xc0, 0x31, 0x56, 0x45, 0xe0, 0x31, - 0x58, 0x45, 0x01, 0x00, 0x5a, 0x23, 0x00, 0xb6, 0x9c, 0x67, 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x56, 0xc5, 0x80, - 0x03, 0x58, 0xc5, 0xa0, 0x03, 0x5a, 0xc5, 0xc0, 0x03, 0x5c, 0xc5, 0x00, 0x00, 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, - 0x00, 0x07, 0x9c, 0xfd, 0x18, 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, - 0x63, 0xe4, 0x84, 0x00, 0x82, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x20, 0x03, 0x48, 0x45, 0xff, 0x0f, - 0x7e, 0xa3, 0x00, 0xf0, 0x41, 0x28, 0x00, 0x82, 0x84, 0xe8, 0x18, 0x95, 0x00, 0x0a, 0x00, 0xf0, 0x41, 0x28, 0x00, - 0x82, 0x84, 0xe8, 0x18, 0x95, 0x00, 0x0a, 0xc3, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x10, 0x00, 0x7c, 0x22, - 0x40, 0x03, 0x4a, 0xc5, 0x00, 0x40, 0x08, 0xf9, 0x00, 0xe0, 0x49, 0x69, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4b, - 0xe9, 0x00, 0x00, 0x40, 0x23, 0x50, 0x00, 0x42, 0xa3, 0x2c, 0x95, 0x00, 0x98, 0x36, 0x00, 0x40, 0x23, 0x1c, 0x95, - 0x00, 0x98, 0x36, 0x00, 0x40, 0x23, 0x3c, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, 0x42, 0x23, 0x2c, - 0x95, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x94, 0x81, 0x00, 0x98, 0x00, 0x00, 0x8c, 0x67, - 0x00, 0x63, 0x8c, 0xfb, 0x01, 0x00, 0x7c, 0xa3, 0x00, 0x6f, 0x8e, 0x7b, 0x00, 0x70, 0xbc, 0x28, 0x6c, 0x96, 0x00, - 0x88, 0x60, 0x32, 0x50, 0x45, 0x00, 0x00, 0x7c, 0x23, 0x00, 0xe4, 0x93, 0x7d, 0x00, 0x83, 0x90, 0x67, 0x80, 0x73, - 0x94, 0x67, 0x80, 0xa3, 0x96, 0x67, 0x80, 0x84, 0x90, 0x67, 0x00, 0x85, 0x90, 0xfb, 0x80, 0x84, 0x90, 0x67, 0x80, - 0xb5, 0x98, 0x67, 0x00, 0xc6, 0x94, 0x67, 0x80, 0xc5, 0x98, 0xe7, 0x00, 0xc4, 0x98, 0xe7, 0x00, 0xa6, 0x94, 0x67, - 0x00, 0xa0, 0x42, 0x63, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x25, 0x9a, - 0x67, 0x00, 0xd6, 0x9a, 0x67, 0x00, 0x32, 0x7c, 0xc5, 0x00, 0xdf, 0x9c, 0x67, 0x80, 0xd6, 0x94, 0x67, 0x80, 0xa5, - 0x94, 0xe7, 0x00, 0xa4, 0x88, 0x68, 0xc0, 0x95, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, 0xc8, 0x95, 0x00, 0x98, 0x00, - 0xe0, 0x42, 0xe3, 0xc8, 0x95, 0x00, 0x98, 0x00, 0x93, 0x84, 0xe7, 0x00, 0xd0, 0x86, 0xe7, 0x01, 0xe0, 0x89, 0xa4, - 0x00, 0x32, 0x86, 0xe7, 0x00, 0x3f, 0x88, 0xe7, 0x00, 0x83, 0x8c, 0xe7, 0x80, 0x31, 0x94, 0x67, 0x80, 0xa5, 0x94, - 0xe7, 0x00, 0xa3, 0xbc, 0xfd, 0x00, 0xe0, 0xbd, 0xa8, 0xfc, 0x95, 0x00, 0x0a, 0x00, 0x30, 0x40, 0xe3, 0x04, 0x96, - 0x00, 0x98, 0x00, 0x40, 0x40, 0x63, 0x04, 0x96, 0x00, 0x98, 0x80, 0x10, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, - 0xa4, 0xbc, 0x7d, 0x00, 0xe0, 0xbd, 0xa8, 0x20, 0x96, 0x00, 0x8a, 0x00, 0x90, 0x46, 0xe3, 0x28, 0x96, 0x00, 0x18, - 0x00, 0x20, 0x46, 0x63, 0x28, 0x96, 0x00, 0x18, 0x38, 0x96, 0x00, 0x8a, 0x00, 0x10, 0x44, 0xe3, 0x01, 0x00, 0x7c, - 0xa3, 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, 0x44, 0x63, 0x00, 0x00, 0x7c, 0x23, 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, - 0x40, 0x23, 0x00, 0x01, 0x82, 0xfd, 0x01, 0x00, 0x50, 0x23, 0x00, 0x24, 0x8c, 0x62, 0x00, 0xe3, 0xbd, 0x68, 0x64, - 0x96, 0x00, 0x08, 0x00, 0x10, 0x56, 0xe3, 0x6c, 0x96, 0x00, 0x18, 0x00, 0x20, 0x56, 0xe3, 0x6c, 0x96, 0x00, 0x18, - 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, - 0x02, 0x00, 0x70, 0xbc, 0x28, 0x70, 0x96, 0x00, 0x08, 0x80, 0xb3, 0x9a, 0xe7, 0x00, 0x30, 0x56, 0x63, 0x00, 0x70, - 0x58, 0x63, 0x00, 0x00, 0x00, 0x84, 0x40, 0x31, 0x7e, 0xc5, 0x00, 0x05, 0x42, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0xb4, - 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, 0x02, 0x00, 0x70, 0xbc, 0x28, 0x98, 0x96, 0x00, 0x08, 0x00, 0x33, 0x7c, 0x45, - 0x00, 0x3f, 0x94, 0x67, 0x80, 0x75, 0x9a, 0xe7, 0x80, 0x33, 0x98, 0x7d, 0x80, 0x33, 0x9c, 0xfb, 0x00, 0xd7, 0x80, - 0x67, 0x00, 0x00, 0xbc, 0xa8, 0x98, 0x96, 0x00, 0x08, 0x00, 0xa7, 0x96, 0x67, 0x80, 0xc6, 0x98, 0xe7, 0x00, 0xb6, - 0x9c, 0x67, 0x00, 0xb0, 0x96, 0x67, 0x00, 0xc0, 0x98, 0x67, 0x00, 0x00, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x00, - 0x08, 0x8d, 0xef, 0x00, 0x06, 0x8f, 0xef, 0x80, 0x63, 0x8c, 0x6f, 0x00, 0x60, 0x42, 0x63, 0xa4, 0x82, 0x00, 0x02, - 0x00, 0x30, 0x52, 0xe3, 0x80, 0x93, 0x92, 0x6f, 0x00, 0x31, 0x40, 0xc5, 0x00, 0x90, 0x94, 0xef, 0x80, 0x94, 0x90, - 0x6f, 0x00, 0x88, 0x90, 0x6f, 0x00, 0x86, 0x80, 0xe8, 0x00, 0x90, 0x54, 0xef, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, - 0x68, 0xe3, 0x20, 0x31, 0x40, 0x45, 0x60, 0x30, 0x42, 0xc5, 0x80, 0x30, 0x44, 0x45, 0x00, 0x4a, 0x97, 0x6f, 0x80, - 0x05, 0x96, 0xef, 0x80, 0xb5, 0x98, 0xef, 0x80, 0xc5, 0x98, 0x7b, 0x01, 0x00, 0x48, 0x23, 0x00, 0xc2, 0x9a, 0xfb, - 0x80, 0x26, 0x9a, 0x6f, 0x00, 0x00, 0x48, 0xa3, 0x00, 0x46, 0x9c, 0xfd, 0x00, 0xc0, 0x80, 0xa8, 0x00, 0xe0, 0x40, - 0x6f, 0x00, 0x17, 0x9c, 0x6f, 0x80, 0xd6, 0x98, 0xef, 0x00, 0xe7, 0xa0, 0x6f, 0x00, 0x18, 0x9e, 0xef, 0x80, 0xc7, - 0x98, 0xfb, 0x80, 0xc6, 0x98, 0x6f, 0x00, 0x07, 0xa1, 0x6f, 0x00, 0x28, 0x9e, 0xef, 0x80, 0xc7, 0x98, 0xfb, 0x80, - 0xb6, 0xa2, 0xef, 0xf0, 0x96, 0x00, 0x82, 0x00, 0xba, 0xa4, 0x6f, 0x00, 0x25, 0xa5, 0xef, 0x00, 0xd0, 0x62, 0x6f, - 0x00, 0xa0, 0x64, 0xef, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x19, 0x82, 0xfd, 0x00, 0x49, 0x81, 0x68, 0x01, 0x00, 0x44, - 0x23, 0x00, 0x01, 0x80, 0xe2, 0x00, 0x10, 0x64, 0x6f, 0x00, 0x10, 0x64, 0x63, 0x00, 0x27, 0xa5, 0x6f, 0x00, 0xe0, - 0x66, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x42, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0xb4, 0xa3, 0x00, 0x82, 0x28, - 0x97, 0x00, 0x02, 0x00, 0x30, 0xbd, 0x28, 0xc8, 0x97, 0x00, 0x88, 0x00, 0x00, 0x00, 0x84, 0x20, 0x30, 0x7e, 0x45, - 0x60, 0x10, 0x40, 0x28, 0x18, 0x98, 0x00, 0x08, 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x66, 0xe5, 0x00, 0x30, 0x27, - 0xf9, 0x00, 0x00, 0x68, 0x23, 0x80, 0x49, 0xb9, 0x79, 0x80, 0xc9, 0x83, 0xe8, 0xb4, 0x99, 0x00, 0x0a, 0x00, 0xc0, - 0x83, 0xa8, 0xb4, 0x99, 0x00, 0x88, 0x2c, 0x98, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, 0x00, 0x00, 0xe8, 0xf3, 0x80, - 0x49, 0xb9, 0x79, 0x00, 0xc0, 0x83, 0xa8, 0xb4, 0x99, 0x00, 0x88, 0x00, 0x00, 0xc0, 0xf3, 0x00, 0x00, 0xc2, 0x73, - 0x00, 0x00, 0xc4, 0x73, 0x00, 0x00, 0xc6, 0xf3, 0x00, 0x00, 0xc0, 0x63, 0x0a, 0xc0, 0xc1, 0x25, 0x04, 0x00, 0x44, - 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x04, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x4c, 0x98, 0x00, 0x0a, 0x80, 0x20, - 0x84, 0x24, 0x00, 0x20, 0xc0, 0xe9, 0x00, 0x00, 0xfa, 0x71, 0x20, 0x01, 0x78, 0xc9, 0x40, 0x01, 0x7a, 0x49, 0x20, - 0x30, 0x7e, 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xcf, 0xf9, 0xff, 0x00, 0x30, 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, - 0xc0, 0x30, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, - 0x82, 0x01, 0x00, 0x9c, 0xa4, 0x00, 0xc7, 0x98, 0x6f, 0x00, 0xd7, 0x9a, 0x6f, 0x00, 0xc0, 0x52, 0xe3, 0x00, 0xd0, - 0x54, 0x63, 0x00, 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0xc0, 0x99, 0x00, 0x0a, 0x80, 0x30, 0x50, 0x45, 0xd8, - 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0xc0, 0x99, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0xc0, 0x99, 0x00, 0x0a, - 0x00, 0xb0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0x90, 0x92, 0x6f, 0x80, 0xa0, 0x94, 0x6f, 0x00, 0x90, 0x19, - 0x6d, 0x00, 0xc0, 0x18, 0xf3, 0xaa, 0xc0, 0x98, 0xa4, 0x00, 0xc0, 0x18, 0xf3, 0x00, 0x01, 0x40, 0xc5, 0xff, 0x00, - 0x48, 0xa3, 0x00, 0x02, 0xa8, 0xe2, 0x60, 0x40, 0x41, 0xa8, 0x08, 0x99, 0x00, 0x08, 0x02, 0xc0, 0x98, 0x24, 0x0c, - 0x99, 0x00, 0x18, 0x01, 0xc0, 0x98, 0x24, 0x00, 0xc0, 0x18, 0xf3, 0x01, 0xc0, 0x98, 0x24, 0x04, 0xa4, 0xd9, 0x37, - 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xd3, 0xb7, 0xb4, 0x99, 0x00, 0x9c, 0x06, 0xa4, 0xd5, 0xb7, 0xb4, 0x99, 0x00, - 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, 0x00, 0x9c, 0x20, 0x01, - 0x78, 0xc5, 0x40, 0x01, 0x7a, 0x45, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, - 0xa3, 0x00, 0x82, 0x00, 0xc0, 0xb9, 0xfd, 0x00, 0x00, 0xc4, 0x73, 0x00, 0xd1, 0xbb, 0xe8, 0x00, 0x90, 0x75, 0xe3, - 0xff, 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, 0x80, 0xc4, 0x94, 0x68, 0x00, 0xa4, 0xf9, - 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0x37, 0xb4, 0x99, - 0x00, 0x9c, 0x03, 0xa4, 0xc5, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x04, 0xa4, 0xd5, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x02, - 0xa4, 0xc1, 0xb9, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, - 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, - 0x39, 0x41, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x10, 0x40, 0x28, 0xe0, 0x99, 0x00, 0x08, 0x10, 0x00, - 0x48, 0xa2, 0x00, 0x40, 0x66, 0xe5, 0xe4, 0x99, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, 0x01, 0x00, 0x64, 0xa3, 0x00, - 0x20, 0x25, 0xed, 0x00, 0x00, 0x62, 0x23, 0x00, 0x01, 0x60, 0x23, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x00, 0xc0, 0x2d, - 0x00, 0x00, 0xf9, 0xeb, 0x00, 0xd0, 0x3b, 0xf9, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, - 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x0e, 0xba, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0xd0, 0xfb, 0x62, 0x00, 0xc0, - 0x39, 0xf9, 0x20, 0x01, 0x7a, 0x49, 0x40, 0x01, 0x78, 0xc9, 0x00, 0x00, 0xfc, 0xf3, 0x60, 0x31, 0x7e, 0x45, 0x00, - 0xdf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xc0, 0x31, 0x56, 0x45, 0xe0, 0x31, 0x58, 0x45, 0x00, 0x00, 0xc4, 0x73, - 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x9a, 0xa4, 0x80, 0xb6, 0x96, 0xe7, 0x00, 0xb6, 0x9c, - 0x67, 0x80, 0xc6, 0x98, 0xe7, 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, - 0x52, 0x63, 0x00, 0xe0, 0x54, 0x63, 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, 0xf0, 0x86, 0x00, 0x02, 0x00, - 0x00, 0x40, 0xa8, 0x70, 0x9b, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, 0xe4, 0x84, 0x00, 0x82, - 0x00, 0x90, 0x15, 0x6d, 0x00, 0xa0, 0x14, 0xf3, 0xaa, 0xa0, 0x94, 0xa4, 0x00, 0xa0, 0x14, 0xf3, 0x00, 0x01, 0x40, - 0xc5, 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0x92, 0xe2, 0x60, 0x90, 0x40, 0xa8, 0xc0, 0x9a, 0x00, 0x88, 0x02, 0xa0, - 0x94, 0x24, 0xc4, 0x9a, 0x00, 0x98, 0x01, 0xa0, 0x94, 0x24, 0x00, 0xa0, 0x14, 0xf3, 0x02, 0xa0, 0x94, 0x24, 0x04, - 0xa4, 0xd5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xd1, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, - 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0x9b, 0x00, 0x9c, 0x20, 0x01, 0x78, 0xc5, 0x40, 0x01, 0x7a, - 0x45, 0x00, 0x00, 0x40, 0x23, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x0e, 0xbc, 0xf9, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, - 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x80, 0x24, 0x00, 0xe0, 0xb9, 0x7d, 0x00, 0x00, 0xc4, 0x73, 0x00, - 0xd1, 0xbb, 0xe8, 0x00, 0x90, 0x75, 0xe3, 0xff, 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, - 0x80, 0xa4, 0x94, 0x68, 0x00, 0xa4, 0xf9, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, 0x7c, 0x9b, 0x00, - 0x9c, 0x02, 0xa4, 0xc1, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x03, 0xa4, 0xc5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x04, 0xa4, - 0xd5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0x7c, - 0x9b, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0x41, 0x00, 0x46, 0x23, - 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xc6, - 0xf3, 0x00, 0x00, 0xc8, 0x73, 0x00, 0x00, 0xca, 0xf3, 0x00, 0x00, 0xcc, 0xf3, 0x00, 0x30, 0xc0, 0x63, 0x0b, 0x40, - 0xc1, 0x25, 0x4c, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x43, 0x63, 0x80, - 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xb0, 0x9b, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, - 0x0e, 0x00, 0x7c, 0xa3, 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xc8, 0x9b, 0x00, - 0x0a, 0x04, 0x00, 0x7c, 0xa3, 0x00, 0x00, 0x42, 0xa3, 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, - 0x7d, 0x24, 0xe0, 0x9b, 0x00, 0x0a, 0x1a, 0x00, 0x7c, 0xa3, 0x00, 0x0f, 0xc0, 0xe2, 0x80, 0x00, 0x80, 0x24, 0x00, - 0x00, 0xc0, 0x69, 0x00, 0x00, 0xf6, 0x71, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x30, 0xc6, 0xeb, 0x00, 0x30, 0xca, 0xeb, - 0x00, 0x30, 0xc0, 0x63, 0x0b, 0xb0, 0xc1, 0x25, 0x04, 0x00, 0x42, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x10, 0x02, - 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x20, 0x9c, 0x00, 0x8a, 0x80, 0x10, 0x82, 0x24, 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, - 0xf8, 0xf1, 0x20, 0x01, 0x64, 0x49, 0x20, 0x30, 0x7e, 0x45, 0x80, 0xcd, 0xb7, 0xf9, 0x00, 0xb0, 0x81, 0xa8, 0xdc, - 0x9d, 0x00, 0x88, 0xa0, 0x30, 0x6c, 0xc5, 0xc0, 0x30, 0x6e, 0x45, 0xa8, 0x8b, 0x00, 0x02, 0x00, 0x00, 0x46, 0xe3, - 0x00, 0x00, 0x40, 0xa8, 0xfc, 0x9d, 0x00, 0x8a, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x0b, 0xac, - 0x79, 0x00, 0x60, 0x81, 0x28, 0xe4, 0x9d, 0x00, 0x08, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, - 0x00, 0x82, 0x00, 0x00, 0x72, 0x63, 0x01, 0x90, 0xb3, 0x24, 0x80, 0x9d, 0x83, 0x7f, 0xa8, 0x81, 0x00, 0x02, 0x20, - 0x01, 0x64, 0x45, 0x80, 0x2c, 0x95, 0xff, 0x80, 0x6c, 0x97, 0xff, 0x80, 0xa5, 0x99, 0x7f, 0x80, 0x55, 0x9b, 0xff, - 0x80, 0xc6, 0x96, 0xfb, 0x80, 0xa5, 0x94, 0x7b, 0x00, 0x15, 0x94, 0xff, 0x00, 0xa0, 0x80, 0xa8, 0xec, 0x9d, 0x00, - 0x88, 0x40, 0x01, 0x54, 0x49, 0x00, 0xa0, 0x42, 0x63, 0xa8, 0x81, 0x00, 0x02, 0x80, 0x20, 0xb9, 0x7f, 0x80, 0x60, - 0xb7, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, 0xc0, 0x30, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x94, - 0x8a, 0x00, 0x82, 0x00, 0x90, 0x5e, 0xe3, 0x00, 0xa0, 0x60, 0x63, 0x00, 0xb0, 0x62, 0x63, 0x60, 0x01, 0x58, 0xc5, - 0x80, 0x01, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0xb0, 0x79, 0x63, 0x94, 0x8a, 0x00, 0x82, 0x80, 0xf5, 0x84, - 0xef, 0x80, 0x98, 0x86, 0xef, 0x80, 0x21, 0x80, 0xe8, 0x38, 0x9d, 0x00, 0x0a, 0x80, 0x05, 0x85, 0x6f, 0x80, 0xa8, - 0x86, 0xef, 0x80, 0x21, 0x80, 0xe8, 0xf4, 0x9d, 0x00, 0x0a, 0xfc, 0x89, 0x00, 0x02, 0x00, 0x90, 0x58, 0xe3, 0x00, - 0xa0, 0x5a, 0x63, 0x00, 0xb0, 0x5c, 0xe3, 0x48, 0x9d, 0x00, 0x98, 0x00, 0xf0, 0x58, 0xe3, 0x00, 0x00, 0x5b, 0xe3, - 0x00, 0x10, 0x5d, 0x63, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0xc0, 0x98, - 0x6f, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x06, 0x98, 0x79, 0x00, 0x00, 0x7e, 0xa3, 0x00, 0xf0, - 0x41, 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, 0x9d, 0x00, 0x0a, 0x00, 0xf0, 0x41, 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, - 0x9d, 0x00, 0x0a, 0x00, 0x00, 0x46, 0x23, 0xc3, 0x00, 0x44, 0xa3, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, - 0x00, 0xe0, 0x45, 0x69, 0x00, 0x30, 0x40, 0xa8, 0x01, 0x00, 0x42, 0x23, 0xbc, 0x9d, 0x00, 0x0a, 0x50, 0x00, 0x42, - 0xa3, 0x10, 0x00, 0x7c, 0x22, 0x00, 0x60, 0x2d, 0xf9, 0x00, 0xe0, 0x6d, 0x69, 0x20, 0xe0, 0x7d, 0x22, 0x40, 0x01, - 0x54, 0x45, 0x00, 0xa0, 0x14, 0xf9, 0x00, 0xe0, 0x55, 0xe9, 0x00, 0x30, 0x40, 0xe3, 0x00, 0x00, 0x68, 0x23, 0x00, - 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x76, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, - 0x94, 0x81, 0x00, 0x98, 0x21, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, 0x22, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, - 0x98, 0x23, 0x00, 0x46, 0xa3, 0xfc, 0x9d, 0x00, 0x98, 0x24, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, 0x3c, 0x00, - 0x44, 0xa3, 0x01, 0x00, 0x42, 0x23, 0x84, 0x9d, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x40, 0x31, 0x7e, 0xc5, 0x00, - 0x00, 0x40, 0x23, 0x00, 0x08, 0x80, 0xf9, 0x00, 0x08, 0x80, 0xe8, 0xdc, 0x9e, 0x00, 0x0a, 0xd8, 0x8c, 0x00, 0x02, - 0xdc, 0x9e, 0x00, 0x0a, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xa4, - 0x24, 0x00, 0x09, 0xa1, 0x67, 0x00, 0x19, 0xa3, 0x67, 0x00, 0x00, 0xfc, 0xf3, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x3f, - 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, 0x70, 0x96, 0x00, 0x02, 0x5c, 0x8e, 0x00, 0x82, 0xd0, 0x8e, 0x00, 0x02, 0x00, - 0x70, 0x6e, 0x63, 0x00, 0x80, 0x70, 0x63, 0x00, 0x90, 0x72, 0x63, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, - 0x00, 0x00, 0x4f, 0xe3, 0x00, 0x20, 0x51, 0x63, 0x00, 0x10, 0x53, 0xe3, 0x0c, 0x8d, 0x00, 0x82, 0x00, 0x00, 0xfc, - 0xf3, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x3f, 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, 0x5c, 0x8e, 0x00, 0x82, 0xd0, 0x8e, - 0x00, 0x02, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x80, 0x04, 0x92, 0xfd, 0x00, - 0x70, 0x57, 0x63, 0x00, 0x80, 0x59, 0xe3, 0x00, 0x90, 0x5b, 0xe3, 0x0c, 0x8d, 0x00, 0x82, 0x00, 0xc0, 0x42, 0x63, - 0x74, 0x84, 0x00, 0x82, 0x80, 0xb0, 0x96, 0xe7, 0x80, 0xd0, 0x9a, 0xe7, 0x01, 0x00, 0x58, 0xa3, 0xd4, 0x8d, 0x00, - 0x82, 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x12, 0x00, 0x40, 0x23, 0x00, 0x00, - 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0xa8, 0xa4, 0x00, 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, - 0x00, 0x48, 0x22, 0x00, 0x40, 0x48, 0xe5, 0xff, 0x00, 0x44, 0xa3, 0x00, 0x41, 0x82, 0xe2, 0x00, 0x40, 0x32, 0xf5, - 0x00, 0x90, 0x09, 0xf5, 0x00, 0x40, 0x08, 0xf5, 0x00, 0x91, 0xb3, 0xe2, 0x00, 0x41, 0x88, 0xe2, 0x00, 0x00, 0x00, - 0x84, 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x33, 0x63, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x01, 0x90, - 0x75, 0x22, 0x04, 0xa4, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x02, 0x40, 0x40, 0xa8, 0x54, 0x9f, 0x00, 0x08, 0x01, - 0x40, 0x40, 0xa8, 0x70, 0x9f, 0x00, 0x08, 0xf4, 0x00, 0x46, 0xa3, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, - 0xcc, 0x99, 0x00, 0x82, 0x00, 0x30, 0x40, 0xa8, 0x68, 0x9f, 0x00, 0x08, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, - 0x98, 0xc3, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xe4, 0x97, 0x00, 0x02, 0x00, 0x30, 0x40, 0xa8, 0x84, 0x9f, - 0x00, 0x88, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xc3, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0x64, - 0x81, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa2, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x44, 0x69, 0x00, 0x30, 0x40, 0xe3, - 0x00, 0xa1, 0x00, 0x98, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x68, 0xe3, 0x00, 0x40, 0x6b, 0x22, 0xf0, 0x9e, 0x00, - 0x02, 0x00, 0x90, 0x35, 0x63, 0x01, 0xa0, 0x75, 0x22, 0xf2, 0x00, 0x46, 0xa3, 0x04, 0xa4, 0xc1, 0xb9, 0x70, 0xa0, - 0x00, 0x9e, 0x04, 0xa4, 0xc5, 0x35, 0x7c, 0xa0, 0x00, 0x1c, 0xf6, 0x00, 0x46, 0x23, 0xff, 0x00, 0x7c, 0x23, 0x00, - 0x20, 0x4a, 0x63, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0x01, 0x40, 0x40, 0xa8, 0xf4, 0x9f, 0x00, 0x08, - 0x02, 0x40, 0x40, 0xa8, 0x70, 0xa0, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0xaa, 0x40, 0x40, - 0x28, 0x70, 0xa0, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0x80, 0x4c, 0x40, 0x68, 0x70, 0xa0, - 0x00, 0x8a, 0xf4, 0x00, 0x46, 0xa3, 0x00, 0xe1, 0xbd, 0xe2, 0x02, 0xe0, 0x41, 0x28, 0x44, 0xa0, 0x00, 0x88, 0x01, - 0xe0, 0x41, 0x28, 0x70, 0xa0, 0x00, 0x8a, 0x50, 0x00, 0x42, 0xa3, 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, 0x00, 0x1c, - 0x06, 0xa4, 0xe3, 0x35, 0x7c, 0xa0, 0x00, 0x1c, 0x50, 0xa0, 0x00, 0x18, 0x30, 0x00, 0x42, 0xa3, 0x05, 0xa4, 0xe1, - 0xb5, 0x7c, 0xa0, 0x00, 0x1c, 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0xff, 0x0f, 0x4a, 0x23, 0x80, 0x22, - 0x84, 0x62, 0x00, 0x20, 0x04, 0xf3, 0xc3, 0x20, 0x84, 0xa4, 0x00, 0x00, 0x40, 0x23, 0x8c, 0xa0, 0x00, 0x98, 0x12, - 0x00, 0x44, 0xa3, 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, 0x00, 0x98, 0x3c, 0x00, 0x44, 0xa3, 0xf2, 0x00, 0x46, 0xa3, - 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, 0x00, 0x98, 0x00, 0x50, 0x45, 0xe9, 0x10, 0x40, 0x6d, 0xa2, 0x00, 0x00, 0x21, - 0xf9, 0x00, 0x60, 0x61, 0xe9, 0x20, 0x60, 0x6d, 0x22, 0x00, 0x10, 0x23, 0xf9, 0x00, 0x60, 0x63, 0x69, 0x00, 0x00, - 0x40, 0x23, 0x00, 0xa1, 0x00, 0x98, 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x33, 0x63, 0x64, 0x81, 0x00, 0x02, 0x00, - 0x00, 0x6a, 0x22, 0x03, 0x94, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, - 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, 0x73, 0x22, 0x03, 0x94, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0x04, 0x94, 0xc1, - 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x05, 0x94, 0xc1, 0x39, 0xc3, 0x00, 0x44, 0xa3, 0x00, 0x50, 0x45, 0xe9, 0x01, 0x00, - 0x42, 0x23, 0x00, 0x00, 0x40, 0x23, 0x00, 0xa1, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x00, - 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x44, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x94, 0x81, 0x00, 0x98, - 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, 0x22, 0x00, 0x40, 0x48, 0xe5, 0x00, 0x40, 0x04, 0xf5, 0xff, 0x00, 0x4c, - 0x23, 0x00, 0x23, 0x84, 0x62, 0x00, 0x20, 0x32, 0x63, 0x01, 0x90, 0xb3, 0x24, 0x04, 0x94, 0xcb, 0xb5, 0x0c, 0xa2, - 0x00, 0x1c, 0xff, 0x00, 0x4c, 0x23, 0x00, 0x53, 0x8e, 0xe2, 0x01, 0x70, 0x40, 0xa8, 0x00, 0xa2, 0x00, 0x8a, 0x00, - 0x50, 0x0a, 0xf5, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x53, 0x8e, 0xe2, 0x00, 0x71, 0x40, 0x68, - 0xf4, 0xa1, 0x00, 0x0a, 0x05, 0x94, 0xcb, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x60, 0x01, 0x4a, 0xc9, 0x06, 0x94, 0xcb, - 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x80, 0x01, 0x4a, 0x49, 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, 0x73, 0x24, 0x00, 0x94, - 0xf5, 0xb5, 0x0c, 0xa2, 0x00, 0x1c, 0x01, 0x94, 0xed, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x02, 0x94, 0xeb, 0x35, 0x0c, - 0xa2, 0x00, 0x1c, 0x03, 0x94, 0xef, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x05, 0x94, 0xc1, 0x39, 0x10, 0x00, 0x48, 0xa2, - 0x00, 0x40, 0x64, 0x65, 0x00, 0x20, 0x25, 0xf9, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, - 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, 0x00, 0x50, 0xab, 0xfb, 0x00, 0x00, 0xd4, 0xf3, 0x00, 0x65, - 0xad, 0x68, 0x00, 0x75, 0xaf, 0x68, 0x80, 0x6b, 0xa9, 0xe8, 0xa0, 0x00, 0x60, 0xc5, 0x00, 0x00, 0x21, 0xf9, 0xc0, - 0x00, 0x62, 0x45, 0x88, 0x9b, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf6, 0x00, 0x46, 0x23, 0x14, 0xa2, 0x00, 0x98, - 0x05, 0x94, 0xc1, 0x39, 0xf4, 0x00, 0x46, 0xa3, 0x14, 0xa2, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf2, 0x00, 0x46, - 0xa3, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x05, 0x94, 0xc1, 0x39, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, - 0x7c, 0xa2, 0x12, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x00, 0x30, 0x40, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, - 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x6e, 0x23, - 0x94, 0x81, 0x00, 0x98, 0x20, 0x00, 0x42, 0x23, 0x94, 0x81, 0x00, 0x98, 0xf2, 0x00, 0x40, 0xa3, 0x50, 0xa2, 0x00, - 0x98, 0x00, 0x00, 0xe6, 0x73, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, - 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0x30, 0xe7, 0x62, 0x40, 0x00, 0x66, 0x49, 0x09, - 0x00, 0x60, 0xa3, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, - 0x50, 0xa2, 0x00, 0x98, 0x40, 0x00, 0x66, 0x45, 0x20, 0x00, 0x60, 0x45, 0x60, 0x00, 0x60, 0xc9, 0x0c, 0x9e, 0x00, - 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x20, 0x00, - 0x42, 0x45, 0x00, 0x12, 0xe0, 0xb5, 0x58, 0xa2, 0x00, 0x9c, 0x40, 0x00, 0x66, 0x45, 0x0c, 0x9e, 0x00, 0x02, 0x00, - 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x60, 0x00, 0x60, 0xc5, - 0x00, 0x00, 0x42, 0xa3, 0x00, 0x10, 0xe6, 0x35, 0x58, 0xa2, 0x00, 0x9c, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, - 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0x30, - 0xe7, 0x62, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x00, - 0x00, 0x66, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x50, 0xa2, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, - 0xd0, 0xa3, 0x00, 0x02, 0xe4, 0xa3, 0x00, 0x82, 0x04, 0xa4, 0x00, 0x82, 0x24, 0xa4, 0x00, 0x02, 0x00, 0x00, 0xc0, - 0x2d, 0x00, 0x00, 0xc0, 0x63, 0x94, 0x81, 0x00, 0x98, 0x1c, 0x00, 0x7c, 0xa3, 0x00, 0x10, 0x23, 0xf9, 0x00, 0x00, - 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, 0xfd, 0x80, 0x08, 0x21, 0x7d, 0x00, 0x10, 0x23, 0xf3, 0x01, - 0xe0, 0x7d, 0x24, 0x5c, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, 0xfd, - 0x00, 0x00, 0x21, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x78, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, 0x00, 0x00, 0x00, - 0x84, 0x54, 0x00, 0x46, 0xa3, 0x00, 0x30, 0x06, 0xf3, 0x53, 0x30, 0x86, 0xa4, 0x00, 0x30, 0x06, 0xf3, 0x01, 0x30, - 0x86, 0x24, 0x00, 0x30, 0x06, 0xf3, 0x80, 0x30, 0x86, 0x24, 0x00, 0x30, 0x06, 0xf5, 0x00, 0x00, 0x00, 0x84, 0x90, - 0xa3, 0x00, 0x82, 0x01, 0x06, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xed, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xc0, 0xeb, - 0x00, 0x10, 0x80, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x08, 0x4c, 0xa3, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x60, 0x7e, - 0x69, 0xd4, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x02, 0x4c, 0xa3, 0x10, 0x00, 0x44, 0x23, 0x00, 0x20, - 0x04, 0xf3, 0x00, 0x61, 0x86, 0xe4, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0xf0, 0xa3, 0x00, 0x0a, 0x00, - 0x00, 0x00, 0x84, 0x80, 0x00, 0x4c, 0xa3, 0x50, 0x00, 0x44, 0xa3, 0x00, 0x20, 0x04, 0xf3, 0x00, 0x61, 0x86, 0xe4, - 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0x10, 0xa4, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x40, - 0x23, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x44, 0xa3, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x48, 0xa3, 0x00, 0x00, - 0x4a, 0x23, 0x00, 0x00, 0x4c, 0x23, 0x00, 0x00, 0x4e, 0xa3, 0x00, 0x00, 0x50, 0xa3, 0x00, 0x00, 0x52, 0x23, 0x00, - 0x00, 0x54, 0x23, 0x00, 0x00, 0x56, 0xa3, 0x00, 0x00, 0x58, 0x23, 0x00, 0x00, 0x5a, 0xa3, 0x00, 0x00, 0x5c, 0xa3, - 0x00, 0x00, 0x5e, 0x23, 0x00, 0x00, 0x60, 0xa3, 0x00, 0x00, 0x62, 0x23, 0x00, 0x00, 0x64, 0x23, 0x00, 0x00, 0x66, - 0xa3, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, 0x00, 0x00, 0x6e, 0x23, 0x00, 0x00, - 0x70, 0x23, 0x00, 0x00, 0x72, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x76, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x00, - 0x00, 0x7a, 0x23, 0x00, 0x00, 0x7c, 0x23, 0x00, 0x00, 0x7e, 0xa3, 0x00, 0x00, 0x00, 0x84}; +const uint8_t fw_SPECT[] = { + 0x37, 0xd9, 0x5c, 0xd3, 0xde, 0xc2, 0xd0, 0x50, 0x41, 0x15, 0x80, 0xf8, 0x8a, 0x1a, 0xd4, 0xcd, + 0x55, 0x93, 0xb3, 0xd8, 0x02, 0x35, 0x63, 0x5a, 0x70, 0xc4, 0x27, 0x3b, 0x96, 0x80, 0x19, 0xc9, + 0x46, 0x9b, 0x56, 0xfe, 0x8d, 0x3a, 0xa9, 0xa1, 0xe0, 0x97, 0x8e, 0xc5, 0x26, 0x7e, 0xf4, 0x4c, + 0x5e, 0xea, 0xf5, 0xb1, 0xa9, 0x79, 0xda, 0xc8, 0x9a, 0xf7, 0xdc, 0xf7, 0x8c, 0x8c, 0x87, 0x0b, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa8, 0x24, 0x00, 0x00, 0x45, 0x07, 0xdd, 0x4c, + 0xb7, 0xcf, 0xe1, 0x1e, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x00, 0x7e, 0xa3, 0xe4, 0xa3, 0x00, 0x82, 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, 0x40, 0xa2, + 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0x82, 0x62, 0xf0, 0x10, 0x88, 0xa2, 0x20, 0x33, 0x4a, 0xc5, + 0x00, 0x10, 0x40, 0x28, 0x2c, 0xa3, 0x00, 0x08, 0x60, 0x40, 0x40, 0x28, 0x4c, 0x80, 0x00, 0x88, + 0x10, 0x40, 0x40, 0xa8, 0x84, 0x80, 0x00, 0x08, 0x40, 0x40, 0x40, 0xa8, 0xb8, 0x80, 0x00, 0x08, + 0x70, 0x40, 0x40, 0xa8, 0x20, 0x81, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0x04, 0xa4, 0x00, 0x82, + 0xf4, 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x60, 0x10, 0x40, 0x28, + 0x1c, 0x9f, 0x00, 0x08, 0x61, 0x10, 0x40, 0xa8, 0x1c, 0x9f, 0x00, 0x08, 0x62, 0x10, 0x40, 0xa8, + 0xa4, 0x9f, 0x00, 0x08, 0x63, 0x10, 0x40, 0x28, 0xb0, 0xa0, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, + 0xa8, 0xa4, 0x00, 0x18, 0xf3, 0x50, 0x8a, 0xa4, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, + 0x11, 0x10, 0x40, 0x28, 0x60, 0xa2, 0x00, 0x08, 0x12, 0x10, 0x40, 0x28, 0x9c, 0xa2, 0x00, 0x08, + 0x13, 0x10, 0x40, 0xa8, 0xbc, 0xa2, 0x00, 0x88, 0x14, 0x10, 0x40, 0x28, 0xe0, 0xa2, 0x00, 0x88, + 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x04, 0xa4, 0x00, 0x82, 0xf2, 0x50, 0x8a, 0x24, + 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x41, 0x10, 0x40, 0x28, 0x94, 0x8f, 0x00, 0x88, + 0x42, 0x10, 0x40, 0x28, 0xac, 0x90, 0x00, 0x88, 0x43, 0x10, 0x40, 0xa8, 0xd4, 0x90, 0x00, 0x88, + 0x44, 0x10, 0x40, 0x28, 0x04, 0x91, 0x00, 0x88, 0x45, 0x10, 0x40, 0xa8, 0xfc, 0x91, 0x00, 0x08, + 0x46, 0x10, 0x40, 0xa8, 0xa0, 0x92, 0x00, 0x08, 0x47, 0x10, 0x40, 0x28, 0xf4, 0x92, 0x00, 0x88, + 0x48, 0x10, 0x40, 0x28, 0x30, 0x93, 0x00, 0x88, 0x49, 0x10, 0x40, 0xa8, 0x48, 0x93, 0x00, 0x88, + 0x4a, 0x10, 0x40, 0xa8, 0x18, 0x94, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, + 0x04, 0xa4, 0x00, 0x82, 0xf1, 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, + 0x70, 0x10, 0x40, 0xa8, 0x1c, 0xa1, 0x00, 0x88, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, + 0x02, 0x00, 0x44, 0x23, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x44, 0x69, 0x00, 0x00, 0x42, 0xa3, + 0xf3, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x40, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xf3, + 0x00, 0x00, 0x00, 0x84, 0x50, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, 0x00, 0xf5, 0x00, 0x00, 0x00, 0xf5, 0xff, 0x00, 0x42, 0xa3, + 0x00, 0x10, 0x02, 0xf3, 0xff, 0x10, 0x82, 0xa4, 0x80, 0x00, 0x80, 0xe2, 0x00, 0x00, 0x00, 0x84, + 0xa8, 0xa4, 0x00, 0x18, 0x00, 0x10, 0x02, 0xf3, 0x00, 0x10, 0x02, 0xf3, 0x80, 0x00, 0x40, 0xe2, + 0x00, 0x11, 0x40, 0x49, 0x00, 0x00, 0xc0, 0x93, 0x80, 0x10, 0x84, 0xff, 0x80, 0x20, 0x86, 0x7f, + 0x80, 0x31, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x80, 0x41, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, + 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x80, 0x42, 0x8a, 0xff, + 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x06, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, + 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0xdc, 0x81, 0x00, 0x8a, + 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x0f, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, + 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0xfc, 0x81, 0x00, 0x0a, + 0x80, 0x42, 0x8c, 0xff, 0x00, 0x63, 0x88, 0xff, 0x3f, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, + 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0x1c, 0x82, 0x00, 0x8a, + 0x00, 0x43, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x1e, 0x00, 0x7c, 0x23, + 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, + 0x40, 0x82, 0x00, 0x8a, 0x00, 0x43, 0x88, 0x7f, 0x40, 0x30, 0x4a, 0xc5, 0x80, 0x00, 0x7c, 0xa3, + 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x50, 0x0a, 0x63, 0x80, 0x82, 0x00, 0x8c, + 0x00, 0x50, 0x0a, 0x63, 0x94, 0x82, 0x00, 0x0e, 0x80, 0x40, 0x88, 0xff, 0x94, 0x82, 0x00, 0x98, + 0x00, 0x50, 0x0a, 0x63, 0x90, 0x82, 0x00, 0x0c, 0x00, 0x41, 0x88, 0xff, 0x94, 0x82, 0x00, 0x98, + 0x80, 0x41, 0x88, 0x7f, 0x02, 0xe0, 0x7d, 0x24, 0x60, 0x82, 0x00, 0x0a, 0x00, 0x40, 0x42, 0xe3, + 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x86, 0xef, 0x80, 0x30, 0x88, 0xef, 0x00, 0x42, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x31, 0x86, 0x6f, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x8a, 0x6f, 0x80, 0x52, 0x86, 0xef, 0x09, 0x00, 0x7c, 0x23, + 0x80, 0x31, 0x86, 0xef, 0x01, 0xe0, 0x7d, 0x24, 0xe0, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x86, 0xef, + 0x0a, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x02, 0xe0, 0x7d, 0x24, + 0xf4, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x8a, 0xef, 0x80, 0x52, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, + 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x1e, 0x00, 0x7c, 0x23, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, + 0x20, 0x83, 0x00, 0x0a, 0x80, 0x30, 0x86, 0x6f, 0x80, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x04, 0xe0, 0x7d, 0x24, + 0x3c, 0x83, 0x00, 0x8a, 0x00, 0x31, 0x86, 0x6f, 0x20, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x04, 0xe0, 0x7d, 0x24, + 0x5c, 0x83, 0x00, 0x8a, 0x00, 0x31, 0x86, 0x6f, 0x1e, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, 0x7c, 0x83, 0x00, 0x0a, + 0x80, 0x32, 0x86, 0xef, 0x00, 0x00, 0x00, 0x84, 0xa4, 0x82, 0x00, 0x02, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x30, 0x82, 0xef, 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x84, 0xe7, + 0x80, 0x20, 0x88, 0xe7, 0x00, 0x42, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x41, 0x84, 0x67, + 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, + 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x07, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0x67, + 0x01, 0xe0, 0x7d, 0x24, 0xdc, 0x83, 0x00, 0x0a, 0x80, 0x21, 0x8a, 0xe7, 0x80, 0x52, 0x86, 0x67, + 0x0f, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xf4, 0x83, 0x00, 0x0a, + 0x80, 0x51, 0x84, 0xe7, 0x00, 0x21, 0x86, 0x67, 0x0f, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, + 0x01, 0xe0, 0x7d, 0x24, 0x0c, 0x84, 0x00, 0x0a, 0x80, 0x51, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, + 0x00, 0x21, 0x84, 0xe7, 0x00, 0x22, 0x8a, 0x67, 0x80, 0x52, 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, + 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x30, 0x84, 0x00, 0x0a, 0x80, 0x51, 0x84, 0xe7, + 0x00, 0x21, 0x86, 0x67, 0x63, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, + 0x48, 0x84, 0x00, 0x0a, 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, + 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x60, 0x84, 0x00, 0x0a, 0x80, 0x32, 0x84, 0xe7, + 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, + 0x80, 0x30, 0x86, 0xe7, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, + 0x00, 0x32, 0x82, 0x67, 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0x80, 0x67, + 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, + 0x00, 0x00, 0x80, 0x67, 0x00, 0x21, 0x84, 0xe7, 0x80, 0x20, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, + 0x00, 0x32, 0x48, 0x45, 0x00, 0x22, 0x86, 0x67, 0x00, 0x21, 0x88, 0xe7, 0x80, 0x40, 0x88, 0xe8, + 0xdc, 0x84, 0x00, 0x8a, 0x00, 0x20, 0x42, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x30, 0x42, 0x63, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x90, 0x42, 0x63, 0x74, 0x84, 0x00, 0x82, 0x80, 0x70, 0x8e, 0xe7, + 0x80, 0x80, 0x90, 0xe7, 0x01, 0x00, 0x42, 0x23, 0x80, 0x70, 0x8e, 0xe2, 0x00, 0x80, 0x10, 0xeb, + 0x80, 0x83, 0x90, 0xe4, 0x00, 0x80, 0x10, 0xed, 0x00, 0x80, 0x10, 0xf9, 0x00, 0x00, 0x00, 0x84, + 0x00, 0xc0, 0x60, 0x63, 0x00, 0x00, 0x21, 0x63, 0x24, 0x85, 0x00, 0x8c, 0x00, 0x00, 0x6c, 0xa3, + 0x2c, 0x85, 0x00, 0x18, 0x01, 0x00, 0x6c, 0x23, 0x2c, 0x85, 0x00, 0x18, 0x00, 0x00, 0x21, 0x65, + 0x00, 0x00, 0x59, 0x63, 0x00, 0x08, 0xa1, 0xe7, 0x01, 0x00, 0x42, 0x23, 0x80, 0x00, 0xa9, 0xfd, + 0x00, 0x03, 0xa1, 0x67, 0x80, 0x00, 0xab, 0x7b, 0x80, 0x5a, 0xa5, 0x67, 0x80, 0x2a, 0xa5, 0xe7, + 0x00, 0x2a, 0xa7, 0xe7, 0x00, 0x29, 0xa5, 0x67, 0x80, 0x2a, 0xa5, 0xe7, 0x00, 0x2a, 0x83, 0xe7, + 0x00, 0x10, 0x60, 0xe3, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0xa4, 0x67, 0x00, 0x29, 0xa5, 0x67, + 0x00, 0x28, 0xa5, 0xe7, 0x80, 0x29, 0xa5, 0xe7, 0x00, 0x29, 0xa1, 0xe7, 0x80, 0x0a, 0xa1, 0xe7, + 0x00, 0x32, 0x42, 0x45, 0x80, 0x20, 0xa3, 0xe7, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x0a, 0xbd, 0xe8, + 0x9c, 0x85, 0x00, 0x8a, 0x00, 0x20, 0x41, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x7c, 0x23, + 0x00, 0xea, 0xa9, 0xfd, 0x00, 0x0a, 0xbd, 0xe8, 0xb4, 0x85, 0x00, 0x8a, 0x00, 0x10, 0x41, 0xe3, + 0x01, 0x00, 0x42, 0x23, 0x00, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, 0x88, 0x00, 0x00, 0x42, 0xa3, + 0x00, 0xe0, 0xbd, 0x68, 0xcc, 0x85, 0x00, 0x8a, 0x01, 0x10, 0x82, 0x24, 0x01, 0x60, 0x41, 0xa8, + 0xd8, 0x85, 0x00, 0x8a, 0x02, 0x10, 0x82, 0x24, 0x03, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, 0x88, + 0x00, 0x00, 0x46, 0x23, 0x00, 0x30, 0x86, 0xfd, 0x01, 0x00, 0x7c, 0xa3, 0x00, 0x0f, 0x82, 0xe2, + 0x00, 0x1b, 0x40, 0x68, 0x00, 0x86, 0x00, 0x8a, 0x00, 0x00, 0x56, 0x63, 0x08, 0x86, 0x00, 0x18, + 0x00, 0x30, 0x56, 0x63, 0x08, 0x86, 0x00, 0x18, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x00, 0x84, + 0xff, 0x0f, 0x42, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x80, 0x83, 0x80, 0xfd, 0x80, 0xc5, 0x82, 0xfd, + 0x80, 0x00, 0x80, 0xe7, 0x80, 0x83, 0x82, 0x7b, 0x80, 0xc5, 0x84, 0xfb, 0x00, 0x11, 0x82, 0xe7, + 0x00, 0xa7, 0x84, 0x67, 0x00, 0x23, 0x84, 0x67, 0x00, 0x21, 0x84, 0x7b, 0x80, 0x96, 0x86, 0xe7, + 0x80, 0x31, 0x86, 0xfb, 0x00, 0x10, 0x88, 0xfd, 0x00, 0x10, 0x80, 0x7b, 0x00, 0x31, 0x82, 0xfd, + 0x00, 0x31, 0x84, 0xfb, 0x80, 0x40, 0x96, 0xe7, 0x00, 0x40, 0x9c, 0x67, 0x00, 0x20, 0x98, 0xe7, + 0x80, 0x20, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x80, 0x73, 0x80, 0x67, 0x00, 0x84, 0x82, 0xe7, + 0x80, 0x94, 0x84, 0xe7, 0x00, 0x21, 0x84, 0x7b, 0x80, 0x00, 0x86, 0x7b, 0x00, 0x74, 0x88, 0x7b, + 0x00, 0x42, 0x88, 0xe7, 0x00, 0x32, 0x88, 0xfd, 0x80, 0x00, 0x80, 0x7d, 0x00, 0x20, 0x82, 0xfb, + 0x80, 0x40, 0x8e, 0xe7, 0x80, 0x00, 0x92, 0xe7, 0x80, 0x01, 0x90, 0xe7, 0x80, 0x41, 0x94, 0xe7, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x4e, 0xa3, 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, 0xa3, + 0x00, 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xb0, 0x4e, 0x67, + 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, + 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, + 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0xb8, 0x86, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x05, 0x56, 0xc9, 0x20, 0x05, 0x58, 0xc9, 0x40, 0x05, 0x5a, 0x49, 0x00, 0x00, 0x4e, 0xa3, + 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, 0xa3, + 0x00, 0x00, 0xde, 0xf3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, 0x00, 0xb0, 0x4e, 0x67, + 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, + 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, + 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x14, 0x87, 0x00, 0x0a, 0x00, 0x01, 0x7c, 0xa3, + 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, + 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, + 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, + 0x01, 0xe0, 0x7d, 0x24, 0x50, 0x87, 0x00, 0x0a, 0x00, 0x00, 0x7c, 0x23, 0x80, 0xe3, 0x8f, 0xfd, + 0x00, 0xe5, 0x95, 0xfd, 0x18, 0x86, 0x00, 0x02, 0x80, 0xe3, 0x8f, 0xfd, 0x00, 0xe5, 0x95, 0xfd, + 0x00, 0x05, 0x40, 0x45, 0x20, 0x05, 0x42, 0x45, 0x40, 0x05, 0x44, 0x45, 0x80, 0x06, 0x80, 0xe7, + 0x80, 0x16, 0x82, 0xe7, 0x00, 0xb1, 0x96, 0xe7, 0x00, 0xc1, 0x98, 0xe7, 0x80, 0x05, 0xbc, 0xe8, + 0xd4, 0x87, 0x00, 0x0a, 0x00, 0x16, 0xbc, 0xe8, 0xd4, 0x87, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, + 0x00, 0x00, 0x00, 0x84, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x40, 0x31, 0x7e, 0xc5, + 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xae, 0x24, + 0x80, 0x5b, 0xab, 0x67, 0x00, 0x5b, 0xb1, 0x67, 0x80, 0x6b, 0xad, 0x67, 0x98, 0x96, 0x00, 0x02, + 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, + 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0x02, 0x56, 0x49, 0x20, 0x02, 0x58, 0x49, 0x40, 0x02, 0x5a, 0xc9, + 0x60, 0x02, 0x5c, 0x49, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x08, 0x89, 0x00, 0x0a, + 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0x02, 0x56, 0x45, 0x20, 0x02, 0x58, 0x45, + 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, 0x45, 0x00, 0x02, 0x4e, 0x49, 0x20, 0x02, 0x50, 0xc9, + 0x40, 0x02, 0x52, 0x49, 0x60, 0x02, 0x54, 0xc9, 0x00, 0x50, 0x4f, 0xe3, 0x00, 0x60, 0x51, 0xe3, + 0x00, 0x70, 0x53, 0xe3, 0x00, 0x80, 0x55, 0xe3, 0x00, 0x00, 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, + 0x00, 0x07, 0x9c, 0xfd, 0x18, 0x86, 0x00, 0x02, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xfc, 0xf3, + 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, 0xf0, 0x86, 0x00, 0x02, + 0x00, 0x00, 0x40, 0xa8, 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, + 0x00, 0x02, 0x56, 0x45, 0x20, 0x02, 0x58, 0x45, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, 0x45, + 0x18, 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, + 0x00, 0xe0, 0x54, 0x63, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, + 0x74, 0x84, 0x00, 0x82, 0x80, 0xb0, 0xaa, 0xe7, 0x80, 0xc0, 0xac, 0x67, 0x80, 0x5a, 0x83, 0xe7, + 0x00, 0x6b, 0x85, 0xe7, 0x80, 0x20, 0x86, 0xfd, 0x00, 0x11, 0x88, 0xe7, 0x00, 0x43, 0x88, 0x67, + 0x01, 0x00, 0x40, 0xa3, 0x00, 0x40, 0x88, 0xfb, 0x00, 0x32, 0x80, 0xe8, 0x08, 0x89, 0x00, 0x0a, + 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, + 0x80, 0x73, 0x80, 0x67, 0x00, 0x84, 0x82, 0xe7, 0x80, 0x94, 0x84, 0xe7, 0x00, 0x10, 0x86, 0x7d, + 0x00, 0x31, 0x86, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x03, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, + 0x00, 0x01, 0x80, 0x7b, 0x00, 0x30, 0x86, 0x68, 0x48, 0x89, 0x00, 0x8a, 0x00, 0x74, 0x80, 0x67, + 0x00, 0x95, 0x86, 0x67, 0x00, 0x30, 0x86, 0x68, 0x00, 0x00, 0x00, 0x84, 0x00, 0x96, 0x80, 0xef, + 0x80, 0xa6, 0x82, 0xef, 0x00, 0xb7, 0x84, 0x6f, 0x00, 0x95, 0x86, 0xfb, 0x80, 0xc6, 0x88, 0xfb, + 0x00, 0x32, 0x86, 0x6f, 0x80, 0x00, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x7d, 0x80, 0xa5, 0x88, 0xfb, + 0x00, 0xd7, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xef, 0x00, 0x11, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xfd, + 0x80, 0x95, 0x8a, 0x7b, 0x00, 0xc7, 0x8c, 0x7b, 0x00, 0x53, 0x8a, 0xef, 0x00, 0x01, 0x8c, 0x7b, + 0x00, 0x53, 0x8c, 0xfd, 0x00, 0x81, 0x8e, 0x6f, 0x80, 0x63, 0x8a, 0x7d, 0x80, 0x52, 0x8e, 0x7b, + 0x80, 0x53, 0x8a, 0x7b, 0x80, 0x12, 0x8e, 0xfd, 0x80, 0x12, 0x8a, 0x7b, 0x00, 0x83, 0x8c, 0x6f, + 0x00, 0x21, 0x82, 0x7b, 0x00, 0x11, 0x84, 0x7b, 0x00, 0x61, 0x8c, 0x7d, 0x00, 0x60, 0x8c, 0xfd, + 0x00, 0x63, 0x82, 0x7b, 0x00, 0x13, 0x8c, 0x7b, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x80, 0x7b, + 0x00, 0x01, 0x80, 0x7d, 0x00, 0x43, 0x82, 0xef, 0x00, 0x03, 0x84, 0x6f, 0x80, 0x53, 0x8c, 0x6f, + 0x00, 0x61, 0x9a, 0xfb, 0x80, 0x32, 0x8a, 0xef, 0x80, 0x50, 0x98, 0x7d, 0x80, 0x43, 0x8e, 0x6f, + 0x00, 0x30, 0x82, 0x6f, 0x80, 0x70, 0x9c, 0x7b, 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0xef, + 0x00, 0xa5, 0x82, 0x6f, 0x80, 0xb5, 0x84, 0x6f, 0x00, 0x95, 0x86, 0xef, 0x80, 0x31, 0x86, 0xfb, + 0x80, 0x95, 0x8e, 0xef, 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x81, 0x8c, 0xef, 0x80, 0x63, 0x8c, 0x7d, + 0x00, 0x63, 0x8a, 0xfb, 0x00, 0x53, 0x8c, 0xfb, 0x00, 0x13, 0x8a, 0x7d, 0x00, 0x13, 0x8c, 0x7b, + 0x00, 0x53, 0x8c, 0xef, 0x80, 0x51, 0x8a, 0xef, 0x00, 0x21, 0x86, 0xfb, 0x80, 0x21, 0x84, 0xfb, + 0x80, 0x83, 0x8e, 0x6f, 0x00, 0x71, 0x8e, 0x7d, 0x00, 0x70, 0x8e, 0xfd, 0x80, 0x73, 0x86, 0xfb, + 0x80, 0x71, 0x8e, 0xfb, 0x00, 0x00, 0x86, 0xfb, 0x00, 0x30, 0x80, 0xfb, 0x00, 0x01, 0x80, 0x7d, + 0x80, 0x03, 0x80, 0x6f, 0x00, 0x60, 0x8c, 0xfb, 0x80, 0xa5, 0x80, 0x6f, 0x00, 0x00, 0x80, 0xfb, + 0x80, 0x03, 0x8e, 0xef, 0x80, 0x53, 0x8a, 0x7d, 0x80, 0x00, 0x8e, 0xef, 0x80, 0x73, 0x8e, 0x7b, + 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x50, 0x52, 0xe3, 0x00, 0x60, 0x54, 0xe3, 0x00, 0x70, 0x56, 0xe3, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, 0x00, 0x56, 0xa3, + 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, 0x67, + 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, + 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, + 0xa8, 0x8a, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x58, 0x49, 0x20, 0x05, 0x5a, 0x49, + 0x40, 0x05, 0x5c, 0x49, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, 0x00, 0x56, 0xa3, + 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xde, 0xf3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, + 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, + 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, + 0x01, 0xe0, 0x7d, 0x24, 0xf8, 0x8a, 0x00, 0x0a, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xf0, 0x1e, 0xeb, + 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, + 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, + 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x2c, 0x8b, 0x00, 0x8a, 0x00, 0x00, 0x7c, 0x23, + 0x00, 0xe5, 0x95, 0xfd, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe5, 0x95, 0xfd, 0x00, 0x05, 0x40, 0x45, + 0x20, 0x05, 0x42, 0x45, 0x40, 0x05, 0x44, 0x45, 0x00, 0x07, 0x80, 0x6f, 0x00, 0x17, 0x82, 0x6f, + 0x00, 0xc1, 0x98, 0x6f, 0x00, 0xd1, 0x9a, 0x6f, 0x00, 0x06, 0xbc, 0x68, 0xa0, 0x8b, 0x00, 0x0a, + 0x80, 0x16, 0xbc, 0x68, 0xa0, 0x8b, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, + 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x30, 0x7e, 0xc5, 0x00, 0x00, 0xc4, 0x73, + 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xb0, 0x24, 0x00, 0x6c, 0xad, 0xef, + 0x00, 0x7c, 0xaf, 0xef, 0xc8, 0x97, 0x00, 0x82, 0x00, 0x10, 0x53, 0xe3, 0x00, 0x20, 0x55, 0xe3, + 0x00, 0x30, 0x57, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x20, 0x30, 0x7e, 0x45, + 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0x80, 0x30, 0x50, 0x45, + 0x00, 0x10, 0x59, 0xe3, 0x00, 0x20, 0x5b, 0x63, 0x00, 0x30, 0x5d, 0xe3, 0xd8, 0x8a, 0x00, 0x02, + 0x00, 0x00, 0x40, 0xa8, 0x94, 0x8c, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, + 0x00, 0x00, 0x80, 0x68, 0x00, 0x60, 0x53, 0x6f, 0x00, 0x70, 0x55, 0xef, 0x00, 0x80, 0x57, 0x6f, + 0x00, 0x10, 0x59, 0xe3, 0x00, 0x20, 0x5b, 0x63, 0x00, 0x30, 0x5d, 0xe3, 0x80, 0x06, 0x9a, 0xfd, + 0x4c, 0x89, 0x00, 0x82, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, + 0x00, 0x30, 0x7e, 0xc5, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x94, 0x8c, 0x00, 0x0a, + 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0x60, 0x59, 0x63, 0x00, 0x70, 0x5b, 0x63, + 0x00, 0x80, 0x5d, 0x63, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xc0, 0x52, 0xe3, 0x00, 0xd0, 0x54, 0x63, + 0x00, 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0xe0, 0x42, 0xe3, + 0x98, 0x83, 0x00, 0x82, 0x80, 0xc0, 0xac, 0xef, 0x80, 0xd0, 0xae, 0xef, 0x00, 0x00, 0x40, 0x23, + 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x30, 0x40, 0x45, + 0x80, 0x30, 0x42, 0x45, 0x00, 0xa5, 0x86, 0xef, 0x80, 0x35, 0x86, 0x6f, 0x80, 0x94, 0x84, 0x6f, + 0x80, 0x24, 0x84, 0xef, 0x80, 0xb5, 0x88, 0x6f, 0x80, 0x45, 0x8a, 0xef, 0x80, 0x04, 0x80, 0xef, + 0x00, 0x02, 0x80, 0x6f, 0x80, 0x12, 0x82, 0xef, 0x80, 0x00, 0x80, 0x7b, 0x00, 0x01, 0x80, 0x7b, + 0x80, 0x01, 0x80, 0x68, 0x00, 0x00, 0x00, 0x84, 0x60, 0x32, 0x40, 0xc5, 0x00, 0x08, 0x80, 0xe7, + 0x00, 0x08, 0x83, 0xe7, 0x00, 0x10, 0x82, 0xfb, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x10, 0x82, 0xfb, + 0x00, 0x18, 0x82, 0xe7, 0x98, 0x84, 0x00, 0x02, 0x00, 0x10, 0x62, 0x63, 0x01, 0x00, 0x44, 0x23, + 0x00, 0x20, 0x84, 0x70, 0x00, 0x01, 0x84, 0x62, 0x00, 0x00, 0x00, 0x84, 0xc0, 0x32, 0x68, 0xc5, + 0xe0, 0x32, 0x6a, 0xc5, 0xa0, 0x32, 0x6c, 0x45, 0x00, 0x64, 0x8b, 0x67, 0x80, 0x53, 0x8a, 0x7b, + 0x00, 0x66, 0x8d, 0xe7, 0x80, 0x65, 0x8c, 0x7b, 0x00, 0x53, 0x80, 0x67, 0x80, 0x96, 0x82, 0x67, + 0x00, 0x86, 0x84, 0x67, 0x80, 0x54, 0x86, 0xfb, 0x80, 0x66, 0x88, 0xfb, 0x00, 0x32, 0x86, 0xe7, + 0x80, 0x00, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x7d, 0x00, 0x54, 0x88, 0xfb, 0x00, 0x66, 0x8a, 0xfb, + 0x80, 0x42, 0x88, 0x67, 0x00, 0x01, 0x8a, 0x7b, 0x80, 0x42, 0x88, 0xfd, 0x00, 0x94, 0x8a, 0x7b, + 0x00, 0xd6, 0x96, 0xfb, 0x80, 0x55, 0x8a, 0xe7, 0x00, 0x11, 0x96, 0x7b, 0x80, 0x55, 0x8a, 0x7d, + 0x00, 0x42, 0x99, 0xe7, 0x00, 0x51, 0x97, 0xe7, 0x00, 0xb6, 0x98, 0x7b, 0x00, 0x16, 0x96, 0xfd, + 0x00, 0x16, 0x98, 0x7b, 0x00, 0xb6, 0x9a, 0x67, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x82, 0xfb, + 0x00, 0x41, 0x85, 0x67, 0x00, 0x52, 0x89, 0xe7, 0x00, 0x11, 0x82, 0x7b, 0x00, 0x01, 0x84, 0xfd, + 0x00, 0x41, 0x85, 0x67, 0x00, 0x41, 0x88, 0x7b, 0x00, 0x12, 0x80, 0x67, 0x00, 0xd0, 0x9a, 0xfb, + 0x00, 0x52, 0x80, 0xe7, 0x80, 0x35, 0x96, 0x67, 0x00, 0xb0, 0x96, 0xfd, 0x80, 0x30, 0x80, 0xe7, + 0x00, 0x56, 0x98, 0x67, 0x00, 0xc0, 0x98, 0xfb, 0x00, 0x66, 0xad, 0x67, 0x00, 0xbb, 0x96, 0x7d, + 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0x67, 0x00, 0x04, 0x80, 0xe7, 0x60, 0x32, 0x42, 0x45, + 0x80, 0x13, 0x82, 0xe7, 0x00, 0x14, 0x82, 0x7b, 0x00, 0x14, 0x82, 0xe7, 0x80, 0x73, 0x84, 0xe7, + 0x00, 0x11, 0x82, 0x7b, 0x80, 0x13, 0x82, 0xe7, 0x80, 0x00, 0x80, 0xe8, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x74, 0x80, 0xfb, 0x00, 0x95, 0x82, 0x7d, 0x00, 0x10, 0x82, 0x67, 0x00, 0x74, 0x80, 0xfd, + 0x00, 0x95, 0x84, 0x7b, 0x00, 0x20, 0x84, 0x67, 0x00, 0x11, 0x86, 0xfb, 0x80, 0x31, 0x86, 0x67, + 0x00, 0x11, 0x88, 0x7d, 0x00, 0x42, 0x88, 0xe7, 0x00, 0x36, 0x92, 0x67, 0x00, 0xb2, 0x94, 0x67, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x74, 0x82, 0x7b, 0x80, 0x10, 0x82, 0xe7, 0x00, 0x74, 0x84, 0x7d, + 0x00, 0x21, 0x84, 0xe7, 0x00, 0x11, 0x8e, 0xe7, 0x00, 0x11, 0x82, 0x7d, 0x80, 0x60, 0x86, 0xe7, + 0x00, 0x31, 0x86, 0x7b, 0x80, 0x11, 0x90, 0x67, 0x00, 0x00, 0x00, 0x84, 0x80, 0x32, 0x4c, 0x45, + 0x00, 0xb0, 0x52, 0x63, 0x00, 0xc0, 0x54, 0xe3, 0x01, 0x00, 0x4e, 0x23, 0x00, 0x00, 0x50, 0xa3, + 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xf6, 0xf3, 0x00, 0xb0, 0x37, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, + 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, 0x00, 0x02, + 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x78, 0x8e, 0x00, 0x0a, + 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xb0, 0x37, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0x90, 0x4e, 0xe7, + 0x00, 0xa0, 0x50, 0xe7, 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, 0x00, 0x02, 0x00, 0x90, 0x4e, 0xe7, + 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0xa4, 0x8e, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x76, 0x80, 0xe7, 0x00, 0xb4, 0x82, 0xe7, 0x00, 0x86, 0x84, 0x67, 0x60, 0x32, 0x4c, 0xc5, + 0x00, 0x63, 0x86, 0xfb, 0x00, 0x31, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, 0x80, 0x41, 0x88, 0xfb, + 0x80, 0xb3, 0x8a, 0x67, 0x00, 0x51, 0x8a, 0x7b, 0x80, 0x42, 0x88, 0x67, 0x00, 0x31, 0x86, 0xe7, + 0x80, 0x41, 0x88, 0xfd, 0x00, 0x45, 0x88, 0x67, 0x80, 0x00, 0x82, 0xfd, 0x80, 0x10, 0x82, 0xe7, + 0x80, 0x14, 0x82, 0x67, 0x80, 0x40, 0x92, 0xfd, 0x80, 0xd6, 0x86, 0xfb, 0x00, 0x34, 0x86, 0xe7, + 0x00, 0x35, 0x86, 0x67, 0x00, 0x30, 0x8e, 0xe7, 0x00, 0x31, 0x90, 0x67, 0x00, 0x00, 0x00, 0x84, + 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0x00, 0x42, 0xa3, 0x00, 0xe0, 0x45, 0x65, + 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x47, 0xe5, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x49, 0x65, + 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4b, 0xe5, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4d, 0xe5, + 0x00, 0x20, 0x04, 0xf9, 0x00, 0x30, 0x06, 0xf9, 0x00, 0x40, 0x08, 0xf9, 0x00, 0x50, 0x0a, 0xf9, + 0x00, 0x60, 0x0c, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x11, 0x02, 0xfd, 0x80, 0x21, 0x04, 0x7d, + 0x00, 0x32, 0x06, 0xfd, 0x80, 0x42, 0x08, 0x7d, 0x00, 0x53, 0x0a, 0x7d, 0x00, 0x60, 0x0c, 0xf3, + 0x00, 0x00, 0x00, 0x84, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, 0x22, 0x00, 0x40, 0x44, 0xe5, + 0x00, 0x20, 0x04, 0xf5, 0x00, 0x20, 0x2c, 0x63, 0x01, 0x60, 0x6b, 0x22, 0x00, 0x00, 0x42, 0xa3, + 0x04, 0x54, 0xe1, 0x35, 0x88, 0x90, 0x00, 0x9c, 0xff, 0x00, 0x40, 0x23, 0x00, 0x00, 0xa3, 0xe2, + 0x02, 0x10, 0x41, 0x28, 0x94, 0x90, 0x00, 0x8a, 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0x21, 0xf5, + 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0xa3, 0xe2, 0x00, 0x20, 0x84, 0x62, 0x00, 0x11, 0x41, 0xe8, + 0xa0, 0x90, 0x00, 0x0a, 0x05, 0x54, 0xf3, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x00, 0x03, 0x72, 0xc9, + 0x05, 0x54, 0xc1, 0x39, 0x88, 0x90, 0x00, 0x9c, 0x00, 0x60, 0x6b, 0xe3, 0x00, 0x54, 0xf5, 0xb5, + 0x88, 0x90, 0x00, 0x9c, 0x01, 0x54, 0xef, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x02, 0x54, 0xfb, 0xb5, + 0x88, 0x90, 0x00, 0x9c, 0x03, 0x54, 0xfd, 0x35, 0x88, 0x90, 0x00, 0x9c, 0x05, 0x54, 0xc1, 0x39, + 0x88, 0x90, 0x00, 0x9c, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, + 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, 0x00, 0xd0, 0xbb, 0xfb, 0x00, 0x00, 0xc4, 0x73, + 0x00, 0x71, 0xaf, 0xe8, 0x00, 0xe1, 0xbd, 0xe8, 0x00, 0x7f, 0xa9, 0x68, 0xe0, 0x03, 0x74, 0x49, + 0x00, 0x04, 0x7a, 0xc9, 0xa0, 0x00, 0x60, 0xc5, 0x00, 0x00, 0x21, 0xf9, 0xc0, 0x00, 0x62, 0x45, + 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x05, 0x54, 0xc1, 0x39, + 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x12, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, + 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x00, 0x84, 0x6c, 0x90, 0x00, 0x82, 0xf2, 0x00, 0x40, 0xa3, + 0x94, 0x81, 0x00, 0x98, 0x6c, 0x90, 0x00, 0x82, 0xf4, 0x00, 0x40, 0xa3, 0x94, 0x81, 0x00, 0x98, + 0x6c, 0x90, 0x00, 0x82, 0xf6, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x00, 0x00, 0xce, 0x73, + 0x00, 0x00, 0xd0, 0x73, 0x00, 0x00, 0xd2, 0xf3, 0x00, 0x00, 0xd4, 0xf3, 0x00, 0x70, 0xc0, 0xe3, + 0x0c, 0x40, 0xc1, 0xa5, 0x4c, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x40, 0x23, + 0x94, 0x81, 0x00, 0x98, 0x30, 0x8f, 0x00, 0x02, 0x08, 0x00, 0x56, 0x23, 0x12, 0x00, 0x58, 0x23, + 0x78, 0x8f, 0x00, 0x02, 0x01, 0xc0, 0x58, 0x24, 0xe0, 0x90, 0x00, 0x8a, 0x00, 0x10, 0xc0, 0xe9, + 0x01, 0xb0, 0x56, 0x24, 0xdc, 0x90, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, + 0x94, 0x81, 0x00, 0x98, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, 0x30, 0x8f, 0x00, 0x02, + 0x80, 0x00, 0x5e, 0xa3, 0x00, 0xf0, 0x1e, 0xf3, 0x00, 0xf0, 0x1e, 0xf3, 0x00, 0xf0, 0x1e, 0xf3, + 0x12, 0xb0, 0x56, 0xa4, 0x80, 0xb7, 0xa0, 0x62, 0x44, 0x91, 0x00, 0x8a, 0x12, 0x00, 0x58, 0x23, + 0x78, 0x8f, 0x00, 0x02, 0x01, 0xc0, 0x58, 0x24, 0x30, 0x91, 0x00, 0x8a, 0x00, 0x10, 0xc0, 0xe9, + 0x20, 0x91, 0x00, 0x18, 0x12, 0xb0, 0x56, 0xa2, 0x88, 0x91, 0x00, 0x08, 0x12, 0x00, 0x58, 0x23, + 0x80, 0xc5, 0x58, 0xe4, 0x78, 0x8f, 0x00, 0x02, 0x01, 0xb0, 0x56, 0x24, 0x54, 0x91, 0x00, 0x0a, + 0x01, 0xc0, 0x40, 0x28, 0x9c, 0x91, 0x00, 0x08, 0x04, 0x00, 0x44, 0x23, 0x00, 0x20, 0x04, 0xf5, + 0x00, 0x11, 0x02, 0xfd, 0x00, 0x20, 0x04, 0xf3, 0x01, 0xc0, 0x58, 0x24, 0x70, 0x91, 0x00, 0x0a, + 0x80, 0x10, 0x82, 0x24, 0xac, 0x91, 0x00, 0x98, 0x00, 0x00, 0x42, 0xa3, 0x8a, 0x00, 0x46, 0xa3, + 0x80, 0x11, 0xc2, 0xe2, 0x80, 0x10, 0x82, 0x24, 0xac, 0x91, 0x00, 0x98, 0x84, 0x00, 0x44, 0xa3, + 0x00, 0x20, 0x04, 0xf5, 0x00, 0x11, 0x02, 0xfd, 0xac, 0x91, 0x00, 0x98, 0x00, 0x10, 0xc0, 0xe9, + 0x00, 0x00, 0xf6, 0x71, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x70, 0xce, 0xeb, 0x00, 0x70, 0xd2, 0x6b, + 0x00, 0x70, 0xc0, 0xe3, 0x0c, 0xb0, 0xc1, 0xa5, 0x04, 0x00, 0x42, 0x23, 0x11, 0x00, 0x7c, 0x23, + 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xd0, 0x91, 0x00, 0x0a, 0x80, 0x10, 0x82, 0x24, + 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf8, 0xf1, 0x60, 0x31, 0x7e, 0x45, 0x80, 0xcd, 0xb7, 0xf9, + 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x40, 0x31, 0x7e, 0xc5, + 0xc0, 0x31, 0x6a, 0x45, 0xe0, 0x31, 0x6c, 0xc5, 0xdc, 0x87, 0x00, 0x02, 0x01, 0x00, 0x42, 0x23, + 0x80, 0x50, 0xab, 0xe2, 0x00, 0x50, 0x2b, 0xed, 0x80, 0x6a, 0xad, 0xe4, 0x00, 0x60, 0x2d, 0xf9, + 0x20, 0x03, 0x6c, 0x49, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x58, 0x81, 0x00, 0x02, + 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x6b, 0x65, 0x00, 0x50, 0x2b, 0xf9, 0x20, 0xe0, 0x7d, 0x22, + 0x00, 0xe0, 0x69, 0xe5, 0x00, 0x40, 0x29, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x67, 0x65, + 0x00, 0x30, 0x27, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x20, 0x25, 0xf9, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x4c, 0x23, 0x00, 0x60, 0x8a, 0x70, 0x60, 0xb0, 0x92, 0x22, + 0x1f, 0xb0, 0x90, 0x22, 0x20, 0x00, 0x4e, 0x23, 0x00, 0x74, 0x50, 0xe4, 0x00, 0x80, 0x4e, 0xe3, + 0x00, 0x70, 0x0e, 0x63, 0x00, 0x70, 0x0e, 0x63, 0x00, 0x70, 0x0e, 0x63, 0x01, 0x70, 0x4e, 0x24, + 0x00, 0x53, 0x0a, 0x7d, 0x01, 0x80, 0x50, 0x24, 0x90, 0x92, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, + 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, + 0x00, 0xe0, 0x67, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, + 0x00, 0x20, 0x25, 0xf9, 0x00, 0x03, 0x68, 0x45, 0x20, 0x03, 0x6a, 0x45, 0x40, 0xb0, 0x7a, 0xa2, + 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0x00, 0xc0, 0x2d, + 0x64, 0x92, 0x00, 0x82, 0x20, 0x90, 0x40, 0x28, 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, 0xe3, + 0xac, 0x93, 0x00, 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x67, 0x65, + 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x20, 0x25, 0xf9, + 0x00, 0x03, 0x68, 0x45, 0x20, 0x03, 0x6a, 0x45, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x20, 0xe1, 0x6b, + 0x80, 0x00, 0x7a, 0xa3, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, + 0x2c, 0x92, 0x00, 0x82, 0x00, 0x20, 0xe1, 0x6b, 0x80, 0xd0, 0x7b, 0x22, 0x00, 0x00, 0x40, 0x23, + 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, + 0x80, 0xd5, 0x7b, 0xe2, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, + 0x2c, 0x92, 0x00, 0x82, 0x80, 0xb0, 0x40, 0xa8, 0xdc, 0x93, 0x00, 0x08, 0x64, 0x92, 0x00, 0x82, + 0x60, 0x90, 0x40, 0xa8, 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, 0xe3, 0x40, 0x90, 0x40, 0x28, + 0xac, 0x93, 0x00, 0x88, 0x00, 0x00, 0x66, 0xa3, 0x20, 0x90, 0x40, 0x28, 0xa0, 0x93, 0x00, 0x88, + 0x00, 0x00, 0x68, 0x23, 0x80, 0x52, 0xab, 0x62, 0x80, 0x53, 0xeb, 0x62, 0xf8, 0x93, 0x00, 0x98, + 0x80, 0x42, 0xa9, 0x62, 0x80, 0x43, 0xe9, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x32, 0xa7, 0x62, + 0x80, 0x33, 0xe7, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x22, 0xa5, 0x62, 0x80, 0x23, 0xe5, 0x62, + 0x10, 0xb0, 0x90, 0x22, 0xd0, 0x93, 0x00, 0x8a, 0x80, 0x2e, 0xa5, 0x64, 0xf8, 0x93, 0x00, 0x98, + 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x6a, 0xa3, 0xec, 0x93, 0x00, 0x98, 0x00, 0x20, 0xe1, 0x6b, + 0x00, 0x00, 0x6a, 0xa3, 0xff, 0x00, 0x4e, 0xa3, 0x80, 0x53, 0xeb, 0x62, 0x00, 0x00, 0x68, 0x23, + 0x00, 0x00, 0x66, 0xa3, 0x00, 0xd0, 0x65, 0xe3, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x20, 0xe1, 0x6b, + 0x00, 0x00, 0x21, 0xf9, 0x00, 0x10, 0x23, 0xf9, 0x80, 0x08, 0xb3, 0x79, 0x00, 0x00, 0x40, 0x23, + 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x60, 0x31, 0x7e, 0x45, 0xe0, 0x03, 0x74, 0x45, + 0x00, 0x04, 0x44, 0x45, 0x80, 0xac, 0x83, 0xff, 0x80, 0x2c, 0x84, 0xff, 0x80, 0xb0, 0x87, 0x7b, + 0x00, 0x31, 0x86, 0x7b, 0x40, 0x03, 0x46, 0xc9, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, + 0x00, 0x03, 0x58, 0x45, 0x00, 0xc0, 0x18, 0xf9, 0x10, 0x85, 0x00, 0x82, 0x00, 0x10, 0xbc, 0x28, + 0x10, 0x95, 0x00, 0x8a, 0x01, 0x00, 0x5a, 0x23, 0x00, 0xb6, 0x9c, 0x67, 0x00, 0x90, 0x79, 0xe3, + 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x4e, 0xc9, 0x80, 0x03, 0x50, 0x49, 0xa0, 0x03, 0x52, 0x49, + 0xc0, 0x03, 0x54, 0x49, 0x40, 0x03, 0x78, 0x45, 0xc0, 0x31, 0x56, 0x45, 0xe0, 0x31, 0x58, 0x45, + 0x01, 0x00, 0x5a, 0x23, 0x00, 0xb6, 0x9c, 0x67, 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x56, 0xc5, + 0x80, 0x03, 0x58, 0xc5, 0xa0, 0x03, 0x5a, 0xc5, 0xc0, 0x03, 0x5c, 0xc5, 0x00, 0x00, 0x40, 0x23, + 0x80, 0x05, 0x96, 0xfd, 0x00, 0x07, 0x9c, 0xfd, 0x18, 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, 0xe3, + 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0xe4, 0x84, 0x00, 0x82, 0x64, 0x81, 0x00, 0x02, + 0x00, 0x00, 0x7c, 0xa2, 0x20, 0x03, 0x48, 0x45, 0xff, 0x0f, 0x7e, 0xa3, 0x00, 0xf0, 0x41, 0x28, + 0x00, 0x82, 0x84, 0xe8, 0x18, 0x95, 0x00, 0x0a, 0x00, 0xf0, 0x41, 0x28, 0x00, 0x82, 0x84, 0xe8, + 0x18, 0x95, 0x00, 0x0a, 0xc3, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x10, 0x00, 0x7c, 0x22, + 0x40, 0x03, 0x4a, 0xc5, 0x00, 0x40, 0x08, 0xf9, 0x00, 0xe0, 0x49, 0x69, 0x20, 0xe0, 0x7d, 0x22, + 0x00, 0xe0, 0x4b, 0xe9, 0x00, 0x00, 0x40, 0x23, 0x50, 0x00, 0x42, 0xa3, 0x2c, 0x95, 0x00, 0x98, + 0x36, 0x00, 0x40, 0x23, 0x1c, 0x95, 0x00, 0x98, 0x36, 0x00, 0x40, 0x23, 0x3c, 0x00, 0x44, 0xa3, + 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, 0x42, 0x23, 0x2c, 0x95, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, + 0xd0, 0xa3, 0x00, 0x02, 0x94, 0x81, 0x00, 0x98, 0x00, 0x00, 0x8c, 0x67, 0x00, 0x63, 0x8c, 0xfb, + 0x01, 0x00, 0x7c, 0xa3, 0x00, 0x6f, 0x8e, 0x7b, 0x00, 0x70, 0xbc, 0x28, 0x6c, 0x96, 0x00, 0x88, + 0x60, 0x32, 0x50, 0x45, 0x00, 0x00, 0x7c, 0x23, 0x00, 0xe4, 0x93, 0x7d, 0x00, 0x83, 0x90, 0x67, + 0x80, 0x73, 0x94, 0x67, 0x80, 0xa3, 0x96, 0x67, 0x80, 0x84, 0x90, 0x67, 0x00, 0x85, 0x90, 0xfb, + 0x80, 0x84, 0x90, 0x67, 0x80, 0xb5, 0x98, 0x67, 0x00, 0xc6, 0x94, 0x67, 0x80, 0xc5, 0x98, 0xe7, + 0x00, 0xc4, 0x98, 0xe7, 0x00, 0xa6, 0x94, 0x67, 0x00, 0xa0, 0x42, 0x63, 0xac, 0x83, 0x00, 0x02, + 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x25, 0x9a, 0x67, 0x00, 0xd6, 0x9a, 0x67, + 0x00, 0x32, 0x7c, 0xc5, 0x00, 0xdf, 0x9c, 0x67, 0x80, 0xd6, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, + 0x00, 0xa4, 0x88, 0x68, 0xc0, 0x95, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, 0xc8, 0x95, 0x00, 0x98, + 0x00, 0xe0, 0x42, 0xe3, 0xc8, 0x95, 0x00, 0x98, 0x00, 0x93, 0x84, 0xe7, 0x00, 0xd0, 0x86, 0xe7, + 0x01, 0xe0, 0x89, 0xa4, 0x00, 0x32, 0x86, 0xe7, 0x00, 0x3f, 0x88, 0xe7, 0x00, 0x83, 0x8c, 0xe7, + 0x80, 0x31, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa3, 0xbc, 0xfd, 0x00, 0xe0, 0xbd, 0xa8, + 0xfc, 0x95, 0x00, 0x0a, 0x00, 0x30, 0x40, 0xe3, 0x04, 0x96, 0x00, 0x98, 0x00, 0x40, 0x40, 0x63, + 0x04, 0x96, 0x00, 0x98, 0x80, 0x10, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa4, 0xbc, 0x7d, + 0x00, 0xe0, 0xbd, 0xa8, 0x20, 0x96, 0x00, 0x8a, 0x00, 0x90, 0x46, 0xe3, 0x28, 0x96, 0x00, 0x18, + 0x00, 0x20, 0x46, 0x63, 0x28, 0x96, 0x00, 0x18, 0x38, 0x96, 0x00, 0x8a, 0x00, 0x10, 0x44, 0xe3, + 0x01, 0x00, 0x7c, 0xa3, 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, 0x44, 0x63, 0x00, 0x00, 0x7c, 0x23, + 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, 0x40, 0x23, 0x00, 0x01, 0x82, 0xfd, 0x01, 0x00, 0x50, 0x23, + 0x00, 0x24, 0x8c, 0x62, 0x00, 0xe3, 0xbd, 0x68, 0x64, 0x96, 0x00, 0x08, 0x00, 0x10, 0x56, 0xe3, + 0x6c, 0x96, 0x00, 0x18, 0x00, 0x20, 0x56, 0xe3, 0x6c, 0x96, 0x00, 0x18, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, 0x02, + 0x00, 0x70, 0xbc, 0x28, 0x70, 0x96, 0x00, 0x08, 0x80, 0xb3, 0x9a, 0xe7, 0x00, 0x30, 0x56, 0x63, + 0x00, 0x70, 0x58, 0x63, 0x00, 0x00, 0x00, 0x84, 0x40, 0x31, 0x7e, 0xc5, 0x00, 0x05, 0x42, 0xc5, + 0x00, 0x00, 0xc4, 0x73, 0xb4, 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, 0x02, 0x00, 0x70, 0xbc, 0x28, + 0x98, 0x96, 0x00, 0x08, 0x00, 0x33, 0x7c, 0x45, 0x00, 0x3f, 0x94, 0x67, 0x80, 0x75, 0x9a, 0xe7, + 0x80, 0x33, 0x98, 0x7d, 0x80, 0x33, 0x9c, 0xfb, 0x00, 0xd7, 0x80, 0x67, 0x00, 0x00, 0xbc, 0xa8, + 0x98, 0x96, 0x00, 0x08, 0x00, 0xa7, 0x96, 0x67, 0x80, 0xc6, 0x98, 0xe7, 0x00, 0xb6, 0x9c, 0x67, + 0x00, 0xb0, 0x96, 0x67, 0x00, 0xc0, 0x98, 0x67, 0x00, 0x00, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x08, 0x8d, 0xef, 0x00, 0x06, 0x8f, 0xef, 0x80, 0x63, 0x8c, 0x6f, 0x00, 0x60, 0x42, 0x63, + 0xa4, 0x82, 0x00, 0x02, 0x00, 0x30, 0x52, 0xe3, 0x80, 0x93, 0x92, 0x6f, 0x00, 0x31, 0x40, 0xc5, + 0x00, 0x90, 0x94, 0xef, 0x80, 0x94, 0x90, 0x6f, 0x00, 0x88, 0x90, 0x6f, 0x00, 0x86, 0x80, 0xe8, + 0x00, 0x90, 0x54, 0xef, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x68, 0xe3, 0x20, 0x31, 0x40, 0x45, + 0x60, 0x30, 0x42, 0xc5, 0x80, 0x30, 0x44, 0x45, 0x00, 0x4a, 0x97, 0x6f, 0x80, 0x05, 0x96, 0xef, + 0x80, 0xb5, 0x98, 0xef, 0x80, 0xc5, 0x98, 0x7b, 0x01, 0x00, 0x48, 0x23, 0x00, 0xc2, 0x9a, 0xfb, + 0x80, 0x26, 0x9a, 0x6f, 0x00, 0x00, 0x48, 0xa3, 0x00, 0x46, 0x9c, 0xfd, 0x00, 0xc0, 0x80, 0xa8, + 0x00, 0xe0, 0x40, 0x6f, 0x00, 0x17, 0x9c, 0x6f, 0x80, 0xd6, 0x98, 0xef, 0x00, 0xe7, 0xa0, 0x6f, + 0x00, 0x18, 0x9e, 0xef, 0x80, 0xc7, 0x98, 0xfb, 0x80, 0xc6, 0x98, 0x6f, 0x00, 0x07, 0xa1, 0x6f, + 0x00, 0x28, 0x9e, 0xef, 0x80, 0xc7, 0x98, 0xfb, 0x80, 0xb6, 0xa2, 0xef, 0xf0, 0x96, 0x00, 0x82, + 0x00, 0xba, 0xa4, 0x6f, 0x00, 0x25, 0xa5, 0xef, 0x00, 0xd0, 0x62, 0x6f, 0x00, 0xa0, 0x64, 0xef, + 0x00, 0x00, 0x42, 0xa3, 0x00, 0x19, 0x82, 0xfd, 0x00, 0x49, 0x81, 0x68, 0x01, 0x00, 0x44, 0x23, + 0x00, 0x01, 0x80, 0xe2, 0x00, 0x10, 0x64, 0x6f, 0x00, 0x10, 0x64, 0x63, 0x00, 0x27, 0xa5, 0x6f, + 0x00, 0xe0, 0x66, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x42, 0xc5, 0x00, 0x00, 0xc4, 0x73, + 0xb4, 0xa3, 0x00, 0x82, 0x28, 0x97, 0x00, 0x02, 0x00, 0x30, 0xbd, 0x28, 0xc8, 0x97, 0x00, 0x88, + 0x00, 0x00, 0x00, 0x84, 0x20, 0x30, 0x7e, 0x45, 0x60, 0x10, 0x40, 0x28, 0x18, 0x98, 0x00, 0x08, + 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x66, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x00, 0x68, 0x23, + 0x80, 0x49, 0xb9, 0x79, 0x80, 0xc9, 0x83, 0xe8, 0xb4, 0x99, 0x00, 0x0a, 0x00, 0xc0, 0x83, 0xa8, + 0xb4, 0x99, 0x00, 0x88, 0x2c, 0x98, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, 0x00, 0x00, 0xe8, 0xf3, + 0x80, 0x49, 0xb9, 0x79, 0x00, 0xc0, 0x83, 0xa8, 0xb4, 0x99, 0x00, 0x88, 0x00, 0x00, 0xc0, 0xf3, + 0x00, 0x00, 0xc2, 0x73, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x00, 0xc6, 0xf3, 0x00, 0x00, 0xc0, 0x63, + 0x0a, 0xc0, 0xc1, 0x25, 0x04, 0x00, 0x44, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x04, 0xf3, + 0x01, 0xe0, 0x7d, 0x24, 0x4c, 0x98, 0x00, 0x0a, 0x80, 0x20, 0x84, 0x24, 0x00, 0x20, 0xc0, 0xe9, + 0x00, 0x00, 0xfa, 0x71, 0x20, 0x01, 0x78, 0xc9, 0x40, 0x01, 0x7a, 0x49, 0x20, 0x30, 0x7e, 0x45, + 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xcf, 0xf9, 0xff, 0x00, 0x30, 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, + 0xc0, 0x30, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, + 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x9c, 0xa4, 0x00, 0xc7, 0x98, 0x6f, 0x00, 0xd7, 0x9a, 0x6f, + 0x00, 0xc0, 0x52, 0xe3, 0x00, 0xd0, 0x54, 0x63, 0x00, 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, + 0xc0, 0x99, 0x00, 0x0a, 0x80, 0x30, 0x50, 0x45, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, + 0xc0, 0x99, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0xc0, 0x99, 0x00, 0x0a, 0x00, 0xb0, 0x42, 0xe3, + 0x98, 0x83, 0x00, 0x82, 0x80, 0x90, 0x92, 0x6f, 0x80, 0xa0, 0x94, 0x6f, 0x00, 0x90, 0x19, 0x6d, + 0x00, 0xc0, 0x18, 0xf3, 0xaa, 0xc0, 0x98, 0xa4, 0x00, 0xc0, 0x18, 0xf3, 0x00, 0x01, 0x40, 0xc5, + 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0xa8, 0xe2, 0x60, 0x40, 0x41, 0xa8, 0x08, 0x99, 0x00, 0x08, + 0x02, 0xc0, 0x98, 0x24, 0x0c, 0x99, 0x00, 0x18, 0x01, 0xc0, 0x98, 0x24, 0x00, 0xc0, 0x18, 0xf3, + 0x01, 0xc0, 0x98, 0x24, 0x04, 0xa4, 0xd9, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xd3, 0xb7, + 0xb4, 0x99, 0x00, 0x9c, 0x06, 0xa4, 0xd5, 0xb7, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, + 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, 0x00, 0x9c, 0x20, 0x01, 0x78, 0xc5, + 0x40, 0x01, 0x7a, 0x45, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, + 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xc0, 0xb9, 0xfd, 0x00, 0x00, 0xc4, 0x73, 0x00, 0xd1, 0xbb, 0xe8, + 0x00, 0x90, 0x75, 0xe3, 0xff, 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, + 0x80, 0xc4, 0x94, 0x68, 0x00, 0xa4, 0xf9, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, + 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x03, 0xa4, 0xc5, 0x37, + 0xb4, 0x99, 0x00, 0x9c, 0x04, 0xa4, 0xd5, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, + 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, + 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, + 0x05, 0xa4, 0xc1, 0x39, 0x41, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x10, 0x40, 0x28, + 0xe0, 0x99, 0x00, 0x08, 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x66, 0xe5, 0xe4, 0x99, 0x00, 0x18, + 0x00, 0x00, 0xe6, 0x73, 0x01, 0x00, 0x64, 0xa3, 0x00, 0x20, 0x25, 0xed, 0x00, 0x00, 0x62, 0x23, + 0x00, 0x01, 0x60, 0x23, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xf9, 0xeb, + 0x00, 0xd0, 0x3b, 0xf9, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, + 0x00, 0x00, 0x80, 0x70, 0x80, 0x0e, 0xba, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0xd0, 0xfb, 0x62, + 0x00, 0xc0, 0x39, 0xf9, 0x20, 0x01, 0x7a, 0x49, 0x40, 0x01, 0x78, 0xc9, 0x00, 0x00, 0xfc, 0xf3, + 0x60, 0x31, 0x7e, 0x45, 0x00, 0xdf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xc0, 0x31, 0x56, 0x45, + 0xe0, 0x31, 0x58, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, + 0x01, 0x00, 0x9a, 0xa4, 0x80, 0xb6, 0x96, 0xe7, 0x00, 0xb6, 0x9c, 0x67, 0x80, 0xc6, 0x98, 0xe7, + 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, + 0x00, 0xe0, 0x54, 0x63, 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, 0xf0, 0x86, 0x00, 0x02, + 0x00, 0x00, 0x40, 0xa8, 0x70, 0x9b, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, + 0xe4, 0x84, 0x00, 0x82, 0x00, 0x90, 0x15, 0x6d, 0x00, 0xa0, 0x14, 0xf3, 0xaa, 0xa0, 0x94, 0xa4, + 0x00, 0xa0, 0x14, 0xf3, 0x00, 0x01, 0x40, 0xc5, 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0x92, 0xe2, + 0x60, 0x90, 0x40, 0xa8, 0xc0, 0x9a, 0x00, 0x88, 0x02, 0xa0, 0x94, 0x24, 0xc4, 0x9a, 0x00, 0x98, + 0x01, 0xa0, 0x94, 0x24, 0x00, 0xa0, 0x14, 0xf3, 0x02, 0xa0, 0x94, 0x24, 0x04, 0xa4, 0xd5, 0x37, + 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xd1, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, + 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0x9b, 0x00, 0x9c, 0x20, 0x01, 0x78, 0xc5, + 0x40, 0x01, 0x7a, 0x45, 0x00, 0x00, 0x40, 0x23, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x0e, 0xbc, 0xf9, + 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x80, 0x24, + 0x00, 0xe0, 0xb9, 0x7d, 0x00, 0x00, 0xc4, 0x73, 0x00, 0xd1, 0xbb, 0xe8, 0x00, 0x90, 0x75, 0xe3, + 0xff, 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, 0x80, 0xa4, 0x94, 0x68, + 0x00, 0xa4, 0xf9, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, 0x7c, 0x9b, 0x00, 0x9c, + 0x02, 0xa4, 0xc1, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x03, 0xa4, 0xc5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, + 0x04, 0xa4, 0xd5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0x7c, 0x9b, 0x00, 0x9c, + 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0x9b, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, + 0x05, 0xa4, 0xc1, 0x39, 0x41, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, + 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xc6, 0xf3, 0x00, 0x00, 0xc8, 0x73, + 0x00, 0x00, 0xca, 0xf3, 0x00, 0x00, 0xcc, 0xf3, 0x00, 0x30, 0xc0, 0x63, 0x0b, 0x40, 0xc1, 0x25, + 0x4c, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x43, 0x63, + 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xb0, 0x9b, 0x00, 0x0a, + 0x00, 0x00, 0xc0, 0x69, 0x0e, 0x00, 0x7c, 0xa3, 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, + 0x01, 0xe0, 0x7d, 0x24, 0xc8, 0x9b, 0x00, 0x0a, 0x04, 0x00, 0x7c, 0xa3, 0x00, 0x00, 0x42, 0xa3, + 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xe0, 0x9b, 0x00, 0x0a, + 0x1a, 0x00, 0x7c, 0xa3, 0x00, 0x0f, 0xc0, 0xe2, 0x80, 0x00, 0x80, 0x24, 0x00, 0x00, 0xc0, 0x69, + 0x00, 0x00, 0xf6, 0x71, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x30, 0xc6, 0xeb, 0x00, 0x30, 0xca, 0xeb, + 0x00, 0x30, 0xc0, 0x63, 0x0b, 0xb0, 0xc1, 0x25, 0x04, 0x00, 0x42, 0x23, 0x11, 0x00, 0x7c, 0x23, + 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x20, 0x9c, 0x00, 0x8a, 0x80, 0x10, 0x82, 0x24, + 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf8, 0xf1, 0x20, 0x01, 0x64, 0x49, 0x20, 0x30, 0x7e, 0x45, + 0x80, 0xcd, 0xb7, 0xf9, 0x00, 0xb0, 0x81, 0xa8, 0xdc, 0x9d, 0x00, 0x88, 0xa0, 0x30, 0x6c, 0xc5, + 0xc0, 0x30, 0x6e, 0x45, 0xa8, 0x8b, 0x00, 0x02, 0x00, 0x00, 0x46, 0xe3, 0x00, 0x00, 0x40, 0xa8, + 0xfc, 0x9d, 0x00, 0x8a, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x0b, 0xac, 0x79, + 0x00, 0x60, 0x81, 0x28, 0xe4, 0x9d, 0x00, 0x08, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, + 0xb4, 0xa3, 0x00, 0x82, 0x00, 0x00, 0x72, 0x63, 0x01, 0x90, 0xb3, 0x24, 0x80, 0x9d, 0x83, 0x7f, + 0xa8, 0x81, 0x00, 0x02, 0x20, 0x01, 0x64, 0x45, 0x80, 0x2c, 0x95, 0xff, 0x80, 0x6c, 0x97, 0xff, + 0x80, 0xa5, 0x99, 0x7f, 0x80, 0x55, 0x9b, 0xff, 0x80, 0xc6, 0x96, 0xfb, 0x80, 0xa5, 0x94, 0x7b, + 0x00, 0x15, 0x94, 0xff, 0x00, 0xa0, 0x80, 0xa8, 0xec, 0x9d, 0x00, 0x88, 0x40, 0x01, 0x54, 0x49, + 0x00, 0xa0, 0x42, 0x63, 0xa8, 0x81, 0x00, 0x02, 0x80, 0x20, 0xb9, 0x7f, 0x80, 0x60, 0xb7, 0x7f, + 0x00, 0x30, 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, 0xc0, 0x30, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, + 0x94, 0x8a, 0x00, 0x82, 0x00, 0x90, 0x5e, 0xe3, 0x00, 0xa0, 0x60, 0x63, 0x00, 0xb0, 0x62, 0x63, + 0x60, 0x01, 0x58, 0xc5, 0x80, 0x01, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0xb0, 0x79, 0x63, + 0x94, 0x8a, 0x00, 0x82, 0x80, 0xf5, 0x84, 0xef, 0x80, 0x98, 0x86, 0xef, 0x80, 0x21, 0x80, 0xe8, + 0x38, 0x9d, 0x00, 0x0a, 0x80, 0x05, 0x85, 0x6f, 0x80, 0xa8, 0x86, 0xef, 0x80, 0x21, 0x80, 0xe8, + 0xf4, 0x9d, 0x00, 0x0a, 0xfc, 0x89, 0x00, 0x02, 0x00, 0x90, 0x58, 0xe3, 0x00, 0xa0, 0x5a, 0x63, + 0x00, 0xb0, 0x5c, 0xe3, 0x48, 0x9d, 0x00, 0x98, 0x00, 0xf0, 0x58, 0xe3, 0x00, 0x00, 0x5b, 0xe3, + 0x00, 0x10, 0x5d, 0x63, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, + 0x80, 0xc0, 0x98, 0x6f, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x06, 0x98, 0x79, + 0x00, 0x00, 0x7e, 0xa3, 0x00, 0xf0, 0x41, 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, 0x9d, 0x00, 0x0a, + 0x00, 0xf0, 0x41, 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, 0x9d, 0x00, 0x0a, 0x00, 0x00, 0x46, 0x23, + 0xc3, 0x00, 0x44, 0xa3, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x45, 0x69, + 0x00, 0x30, 0x40, 0xa8, 0x01, 0x00, 0x42, 0x23, 0xbc, 0x9d, 0x00, 0x0a, 0x50, 0x00, 0x42, 0xa3, + 0x10, 0x00, 0x7c, 0x22, 0x00, 0x60, 0x2d, 0xf9, 0x00, 0xe0, 0x6d, 0x69, 0x20, 0xe0, 0x7d, 0x22, + 0x40, 0x01, 0x54, 0x45, 0x00, 0xa0, 0x14, 0xf9, 0x00, 0xe0, 0x55, 0xe9, 0x00, 0x30, 0x40, 0xe3, + 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x76, 0x23, + 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x94, 0x81, 0x00, 0x98, 0x21, 0x00, 0x46, 0x23, + 0xfc, 0x9d, 0x00, 0x98, 0x22, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, 0x23, 0x00, 0x46, 0xa3, + 0xfc, 0x9d, 0x00, 0x98, 0x24, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, 0x3c, 0x00, 0x44, 0xa3, + 0x01, 0x00, 0x42, 0x23, 0x84, 0x9d, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x40, 0x31, 0x7e, 0xc5, + 0x00, 0x00, 0x40, 0x23, 0x00, 0x08, 0x80, 0xf9, 0x00, 0x08, 0x80, 0xe8, 0xdc, 0x9e, 0x00, 0x0a, + 0xd8, 0x8c, 0x00, 0x02, 0xdc, 0x9e, 0x00, 0x0a, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, + 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xa4, 0x24, 0x00, 0x09, 0xa1, 0x67, 0x00, 0x19, 0xa3, 0x67, + 0x00, 0x00, 0xfc, 0xf3, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x3f, 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, + 0x70, 0x96, 0x00, 0x02, 0x5c, 0x8e, 0x00, 0x82, 0xd0, 0x8e, 0x00, 0x02, 0x00, 0x70, 0x6e, 0x63, + 0x00, 0x80, 0x70, 0x63, 0x00, 0x90, 0x72, 0x63, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, + 0x00, 0x00, 0x4f, 0xe3, 0x00, 0x20, 0x51, 0x63, 0x00, 0x10, 0x53, 0xe3, 0x0c, 0x8d, 0x00, 0x82, + 0x00, 0x00, 0xfc, 0xf3, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x3f, 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, + 0x5c, 0x8e, 0x00, 0x82, 0xd0, 0x8e, 0x00, 0x02, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, + 0x00, 0x00, 0x40, 0x23, 0x80, 0x04, 0x92, 0xfd, 0x00, 0x70, 0x57, 0x63, 0x00, 0x80, 0x59, 0xe3, + 0x00, 0x90, 0x5b, 0xe3, 0x0c, 0x8d, 0x00, 0x82, 0x00, 0xc0, 0x42, 0x63, 0x74, 0x84, 0x00, 0x82, + 0x80, 0xb0, 0x96, 0xe7, 0x80, 0xd0, 0x9a, 0xe7, 0x01, 0x00, 0x58, 0xa3, 0xd4, 0x8d, 0x00, 0x82, + 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x12, 0x00, 0x40, 0x23, + 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0xa8, 0xa4, 0x00, 0x18, + 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, 0x22, 0x00, 0x40, 0x48, 0xe5, 0xff, 0x00, 0x44, 0xa3, + 0x00, 0x41, 0x82, 0xe2, 0x00, 0x40, 0x32, 0xf5, 0x00, 0x90, 0x09, 0xf5, 0x00, 0x40, 0x08, 0xf5, + 0x00, 0x91, 0xb3, 0xe2, 0x00, 0x41, 0x88, 0xe2, 0x00, 0x00, 0x00, 0x84, 0xf0, 0x9e, 0x00, 0x02, + 0x00, 0x90, 0x33, 0x63, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x01, 0x90, 0x75, 0x22, + 0x04, 0xa4, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x02, 0x40, 0x40, 0xa8, 0x54, 0x9f, 0x00, 0x08, + 0x01, 0x40, 0x40, 0xa8, 0x70, 0x9f, 0x00, 0x08, 0xf4, 0x00, 0x46, 0xa3, 0x3c, 0x00, 0x44, 0xa3, + 0x8c, 0x9f, 0x00, 0x98, 0xcc, 0x99, 0x00, 0x82, 0x00, 0x30, 0x40, 0xa8, 0x68, 0x9f, 0x00, 0x08, + 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xc3, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, + 0xe4, 0x97, 0x00, 0x02, 0x00, 0x30, 0x40, 0xa8, 0x84, 0x9f, 0x00, 0x88, 0x3c, 0x00, 0x44, 0xa3, + 0x8c, 0x9f, 0x00, 0x98, 0xc3, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0x64, 0x81, 0x00, 0x02, + 0x00, 0x00, 0x40, 0xa2, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x44, 0x69, 0x00, 0x30, 0x40, 0xe3, + 0x00, 0xa1, 0x00, 0x98, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x68, 0xe3, 0x00, 0x40, 0x6b, 0x22, + 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x35, 0x63, 0x01, 0xa0, 0x75, 0x22, 0xf2, 0x00, 0x46, 0xa3, + 0x04, 0xa4, 0xc1, 0xb9, 0x70, 0xa0, 0x00, 0x9e, 0x04, 0xa4, 0xc5, 0x35, 0x7c, 0xa0, 0x00, 0x1c, + 0xf6, 0x00, 0x46, 0x23, 0xff, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x4a, 0x63, 0x00, 0x50, 0x0a, 0xf5, + 0x00, 0x5f, 0x88, 0xe2, 0x01, 0x40, 0x40, 0xa8, 0xf4, 0x9f, 0x00, 0x08, 0x02, 0x40, 0x40, 0xa8, + 0x70, 0xa0, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0xaa, 0x40, 0x40, 0x28, + 0x70, 0xa0, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0x80, 0x4c, 0x40, 0x68, + 0x70, 0xa0, 0x00, 0x8a, 0xf4, 0x00, 0x46, 0xa3, 0x00, 0xe1, 0xbd, 0xe2, 0x02, 0xe0, 0x41, 0x28, + 0x44, 0xa0, 0x00, 0x88, 0x01, 0xe0, 0x41, 0x28, 0x70, 0xa0, 0x00, 0x8a, 0x50, 0x00, 0x42, 0xa3, + 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, 0x00, 0x1c, 0x06, 0xa4, 0xe3, 0x35, 0x7c, 0xa0, 0x00, 0x1c, + 0x50, 0xa0, 0x00, 0x18, 0x30, 0x00, 0x42, 0xa3, 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, 0x00, 0x1c, + 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0xff, 0x0f, 0x4a, 0x23, 0x80, 0x22, 0x84, 0x62, + 0x00, 0x20, 0x04, 0xf3, 0xc3, 0x20, 0x84, 0xa4, 0x00, 0x00, 0x40, 0x23, 0x8c, 0xa0, 0x00, 0x98, + 0x12, 0x00, 0x44, 0xa3, 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, 0x00, 0x98, 0x3c, 0x00, 0x44, 0xa3, + 0xf2, 0x00, 0x46, 0xa3, 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, 0x00, 0x98, 0x00, 0x50, 0x45, 0xe9, + 0x10, 0x40, 0x6d, 0xa2, 0x00, 0x00, 0x21, 0xf9, 0x00, 0x60, 0x61, 0xe9, 0x20, 0x60, 0x6d, 0x22, + 0x00, 0x10, 0x23, 0xf9, 0x00, 0x60, 0x63, 0x69, 0x00, 0x00, 0x40, 0x23, 0x00, 0xa1, 0x00, 0x98, + 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x33, 0x63, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x6a, 0x22, + 0x03, 0x94, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, + 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, 0x73, 0x22, 0x03, 0x94, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, + 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x05, 0x94, 0xc1, 0x39, 0xc3, 0x00, 0x44, 0xa3, + 0x00, 0x50, 0x45, 0xe9, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x40, 0x23, 0x00, 0xa1, 0x00, 0x98, + 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, + 0x00, 0x00, 0x44, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x94, 0x81, 0x00, 0x98, 0x58, 0x81, 0x00, 0x02, + 0x00, 0x00, 0x48, 0x22, 0x00, 0x40, 0x48, 0xe5, 0x00, 0x40, 0x04, 0xf5, 0xff, 0x00, 0x4c, 0x23, + 0x00, 0x23, 0x84, 0x62, 0x00, 0x20, 0x32, 0x63, 0x01, 0x90, 0xb3, 0x24, 0x04, 0x94, 0xcb, 0xb5, + 0x0c, 0xa2, 0x00, 0x1c, 0xff, 0x00, 0x4c, 0x23, 0x00, 0x53, 0x8e, 0xe2, 0x01, 0x70, 0x40, 0xa8, + 0x00, 0xa2, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x50, 0x0a, 0xf5, + 0x00, 0x53, 0x8e, 0xe2, 0x00, 0x71, 0x40, 0x68, 0xf4, 0xa1, 0x00, 0x0a, 0x05, 0x94, 0xcb, 0x35, + 0x0c, 0xa2, 0x00, 0x1c, 0x60, 0x01, 0x4a, 0xc9, 0x06, 0x94, 0xcb, 0x35, 0x0c, 0xa2, 0x00, 0x1c, + 0x80, 0x01, 0x4a, 0x49, 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, 0x73, 0x24, 0x00, 0x94, 0xf5, 0xb5, + 0x0c, 0xa2, 0x00, 0x1c, 0x01, 0x94, 0xed, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x02, 0x94, 0xeb, 0x35, + 0x0c, 0xa2, 0x00, 0x1c, 0x03, 0x94, 0xef, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x05, 0x94, 0xc1, 0x39, + 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x64, 0x65, 0x00, 0x20, 0x25, 0xf9, 0x20, 0x30, 0x7e, 0x45, + 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, + 0x00, 0x50, 0xab, 0xfb, 0x00, 0x00, 0xd4, 0xf3, 0x00, 0x65, 0xad, 0x68, 0x00, 0x75, 0xaf, 0x68, + 0x80, 0x6b, 0xa9, 0xe8, 0xa0, 0x00, 0x60, 0xc5, 0x00, 0x00, 0x21, 0xf9, 0xc0, 0x00, 0x62, 0x45, + 0x88, 0x9b, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf6, 0x00, 0x46, 0x23, 0x14, 0xa2, 0x00, 0x98, + 0x05, 0x94, 0xc1, 0x39, 0xf4, 0x00, 0x46, 0xa3, 0x14, 0xa2, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, + 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x05, 0x94, 0xc1, 0x39, + 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x12, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, + 0x00, 0x30, 0x40, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, + 0x00, 0x00, 0x6c, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x6e, 0x23, 0x94, 0x81, 0x00, 0x98, + 0x20, 0x00, 0x42, 0x23, 0x94, 0x81, 0x00, 0x98, 0xf2, 0x00, 0x40, 0xa3, 0x50, 0xa2, 0x00, 0x98, + 0x00, 0x00, 0xe6, 0x73, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, + 0x00, 0x00, 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0x30, 0xe7, 0x62, + 0x40, 0x00, 0x66, 0x49, 0x09, 0x00, 0x60, 0xa3, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, + 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x40, 0x00, 0x66, 0x45, + 0x20, 0x00, 0x60, 0x45, 0x60, 0x00, 0x60, 0xc9, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, + 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x20, 0x00, 0x42, 0x45, + 0x00, 0x12, 0xe0, 0xb5, 0x58, 0xa2, 0x00, 0x9c, 0x40, 0x00, 0x66, 0x45, 0x0c, 0x9e, 0x00, 0x02, + 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, + 0x60, 0x00, 0x60, 0xc5, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x10, 0xe6, 0x35, 0x58, 0xa2, 0x00, 0x9c, + 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, + 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0x30, 0xe7, 0x62, 0x0c, 0x9e, 0x00, 0x02, + 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x00, 0x00, 0x66, 0xa3, + 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x50, 0xa2, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, + 0xd0, 0xa3, 0x00, 0x02, 0xe4, 0xa3, 0x00, 0x82, 0x04, 0xa4, 0x00, 0x82, 0x24, 0xa4, 0x00, 0x02, + 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xc0, 0x63, 0x94, 0x81, 0x00, 0x98, 0x1c, 0x00, 0x7c, 0xa3, + 0x00, 0x10, 0x23, 0xf9, 0x00, 0x00, 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, 0xfd, + 0x80, 0x08, 0x21, 0x7d, 0x00, 0x10, 0x23, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x5c, 0xa3, 0x00, 0x0a, + 0x00, 0x00, 0xc0, 0x69, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, 0xfd, 0x00, 0x00, 0x21, 0xf3, + 0x01, 0xe0, 0x7d, 0x24, 0x78, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, 0x00, 0x00, 0x00, 0x84, + 0x54, 0x00, 0x46, 0xa3, 0x00, 0x30, 0x06, 0xf3, 0x53, 0x30, 0x86, 0xa4, 0x00, 0x30, 0x06, 0xf3, + 0x01, 0x30, 0x86, 0x24, 0x00, 0x30, 0x06, 0xf3, 0x80, 0x30, 0x86, 0x24, 0x00, 0x30, 0x06, 0xf5, + 0x00, 0x00, 0x00, 0x84, 0x90, 0xa3, 0x00, 0x82, 0x01, 0x06, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xed, + 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xc0, 0xeb, 0x00, 0x10, 0x80, 0xf9, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x08, 0x4c, 0xa3, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x60, 0x7e, 0x69, 0xd4, 0xa3, 0x00, 0x0a, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x02, 0x4c, 0xa3, 0x10, 0x00, 0x44, 0x23, 0x00, 0x20, 0x04, 0xf3, + 0x00, 0x61, 0x86, 0xe4, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0xf0, 0xa3, 0x00, 0x0a, + 0x00, 0x00, 0x00, 0x84, 0x80, 0x00, 0x4c, 0xa3, 0x50, 0x00, 0x44, 0xa3, 0x00, 0x20, 0x04, 0xf3, + 0x00, 0x61, 0x86, 0xe4, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0x10, 0xa4, 0x00, 0x0a, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x44, 0xa3, + 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x48, 0xa3, 0x00, 0x00, 0x4a, 0x23, 0x00, 0x00, 0x4c, 0x23, + 0x00, 0x00, 0x4e, 0xa3, 0x00, 0x00, 0x50, 0xa3, 0x00, 0x00, 0x52, 0x23, 0x00, 0x00, 0x54, 0x23, + 0x00, 0x00, 0x56, 0xa3, 0x00, 0x00, 0x58, 0x23, 0x00, 0x00, 0x5a, 0xa3, 0x00, 0x00, 0x5c, 0xa3, + 0x00, 0x00, 0x5e, 0x23, 0x00, 0x00, 0x60, 0xa3, 0x00, 0x00, 0x62, 0x23, 0x00, 0x00, 0x64, 0x23, + 0x00, 0x00, 0x66, 0xa3, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, + 0x00, 0x00, 0x6e, 0x23, 0x00, 0x00, 0x70, 0x23, 0x00, 0x00, 0x72, 0xa3, 0x00, 0x00, 0x74, 0xa3, + 0x00, 0x00, 0x76, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x7c, 0x23, + 0x00, 0x00, 0x7e, 0xa3, 0x00, 0x00, 0x00, 0x84}; diff --git a/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_1_0_0/fw_CPU.h b/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_1_0_0/fw_CPU.h index 485b5e4cd..e7694a508 100644 --- a/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_1_0_0/fw_CPU.h +++ b/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_1_0_0/fw_CPU.h @@ -5,1439 +5,1708 @@ /** * @brief CPU firmware version fw_v1.0.0.hex32_signed_chunks.bin for bootloader v2.0.1 */ -const uint8_t fw_CPU[] - = {0x68, 0x7b, 0x1f, 0x5f, 0x8a, 0xfa, 0xff, 0xb1, 0xa1, 0xdd, 0xcb, 0x77, 0xcb, 0x04, 0x01, 0xa8, 0x25, 0x9d, 0xbc, - 0x51, 0xc3, 0x26, 0x45, 0xa2, 0xde, 0x55, 0x2c, 0xd5, 0xbd, 0x9c, 0xa6, 0x77, 0x27, 0xfc, 0x29, 0xad, 0xd9, 0x5c, - 0xb2, 0x23, 0xda, 0x05, 0x8f, 0x4b, 0xaa, 0x71, 0x8d, 0x63, 0x9b, 0x24, 0x28, 0x00, 0x3f, 0xf4, 0x63, 0x29, 0x0e, - 0x42, 0xd0, 0x09, 0x02, 0x74, 0xed, 0x64, 0x0f, 0x0f, 0xd0, 0x75, 0xb6, 0xcc, 0xb1, 0x94, 0x3e, 0xfd, 0x07, 0x46, - 0xc3, 0xda, 0xbe, 0x5f, 0xc9, 0xff, 0x39, 0x84, 0x13, 0x5a, 0x9d, 0xb6, 0x2c, 0x65, 0x88, 0x2e, 0x18, 0x03, 0xd4, - 0xc2, 0x72, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0xfa, 0x79, 0xf4, 0xfe, 0x81, 0x56, 0x6e, 0xdc, 0x29, - 0x3d, 0xb2, 0xe1, 0x3b, 0xa1, 0xfa, 0x98, 0x2b, 0x31, 0xc8, 0xcc, 0x7e, 0x58, 0x13, 0x41, 0x3d, 0x50, 0x9d, 0x82, - 0xd3, 0x5d, 0xb5, 0x23, 0x56, 0x00, 0x00, 0xc0, 0xa6, 0xd9, 0x50, 0x89, 0xe0, 0x6b, 0xd4, 0xd6, 0x78, 0x33, 0x1a, - 0x36, 0x2b, 0x60, 0x8d, 0xbb, 0x82, 0xe3, 0x56, 0xf4, 0x83, 0x89, 0x9c, 0xe7, 0x0a, 0x77, 0x0d, 0xeb, 0x72, 0x15, - 0xf2, 0xf5, 0x46, 0xbe, 0xa8, 0x43, 0x6b, 0xa9, 0xc9, 0x2d, 0x74, 0xa3, 0x34, 0x48, 0x56, 0x2c, 0x6e, 0x77, 0xa6, - 0x12, 0x75, 0x87, 0x10, 0x50, 0xd8, 0xf0, 0xa3, 0x1f, 0x2e, 0xea, 0xdc, 0x9b, 0x0a, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xd3, 0x83, 0x87, 0x72, - 0xb4, 0xff, 0xa1, 0xb6, 0x43, 0x95, 0xa8, 0x07, 0xcf, 0x88, 0xe8, 0x32, 0x17, 0x89, 0x90, 0x87, 0xb4, 0xd5, 0x4e, - 0xcc, 0xbb, 0x97, 0xf4, 0x3e, 0xe0, 0x46, 0xd4, 0x69, 0xd8, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, - 0x38, 0xd8, 0x68, 0x70, 0x75, 0xac, 0x2a, 0x66, 0x52, 0x1e, 0xf7, 0x61, 0x4f, 0x8d, 0xc0, 0x05, 0x5a, 0x90, 0x0b, - 0x8c, 0xe8, 0x87, 0xa8, 0x50, 0xb9, 0xfd, 0xa7, 0x5b, 0x0b, 0x14, 0x7a, 0x9b, 0xb0, 0x01, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x2c, 0x57, 0x00, 0x00, 0xbe, 0x52, 0xea, 0x0a, 0xe3, 0x51, 0x85, - 0x8b, 0x68, 0x79, 0xed, 0x3f, 0x06, 0xb0, 0xa3, 0x97, 0x8e, 0x8a, 0x18, 0xd6, 0x4d, 0x72, 0xb4, 0xcc, 0xb2, 0x13, - 0xc3, 0x64, 0x76, 0x30, 0xf7, 0x31, 0x82, 0x64, 0x8f, 0xda, 0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xfa, 0x5c, 0x23, 0x4d, 0x45, 0x4e, 0xd2, 0x6d, 0x46, 0x30, 0x20, 0x2d, 0x5b, 0x5c, 0x4f, 0x73, - 0xf7, 0x03, 0x7b, 0xe6, 0x42, 0x9d, 0x50, 0x17, 0xe0, 0xf2, 0xbb, 0x26, 0x1c, 0x67, 0x71, 0x47, 0xcf, 0x88, 0x02, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xa5, 0x83, 0xfc, 0x9d, 0x7b, 0xe3, 0x4b, 0x6a, 0xab, 0x74, 0x96, - 0x89, 0xd9, 0xa9, 0x67, 0xc0, 0xb1, 0x6d, 0x91, 0x7a, 0x70, 0x92, 0x1b, 0xae, 0x7c, 0x81, 0x25, 0xc1, 0xdd, 0x3b, - 0x7d, 0x3e, 0x60, 0x03, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x6f, 0x30, 0x00, 0x43, 0x6f, 0x30, 0x20, - 0x3d, 0x6f, 0x30, 0xe0, 0x3c, 0x6f, 0x30, 0xa0, 0x3c, 0x6f, 0x30, 0x60, 0x3c, 0x6f, 0x30, 0x20, 0x3c, 0x6f, 0x30, - 0xe0, 0x3b, 0x6f, 0x50, 0x60, 0x04, 0x6f, 0x30, 0x60, 0x3b, 0x6f, 0x30, 0x20, 0x3b, 0x6f, 0x30, 0xe0, 0x3a, 0x6f, - 0x30, 0xa0, 0x7f, 0x6f, 0x30, 0x60, 0x3a, 0x6f, 0x30, 0x20, 0x3a, 0xfa, 0xd8, 0x31, 0xce, 0x5f, 0xa8, 0x9e, 0x11, - 0x71, 0xdc, 0x79, 0xcd, 0xd3, 0x3a, 0x7e, 0xcb, 0x3b, 0x3f, 0x92, 0x79, 0x19, 0x91, 0xe4, 0xd3, 0x9f, 0xdf, 0x5d, - 0x61, 0x69, 0x67, 0x25, 0x53, 0xa5, 0x38, 0x04, 0x6f, 0x30, 0xe0, 0x39, 0x6f, 0x30, 0xa0, 0x39, 0x6f, 0x40, 0xf0, - 0x72, 0x6f, 0x30, 0x20, 0x26, 0x6f, 0x30, 0x50, 0x20, 0x6f, 0x40, 0x30, 0x22, 0x6f, 0x40, 0xf0, 0x21, 0x6f, 0x40, - 0xb0, 0x21, 0x6f, 0x30, 0xa0, 0x4c, 0x6f, 0x30, 0xa0, 0x4d, 0x6f, 0x30, 0xf0, 0x42, 0x6f, 0x40, 0x50, 0x56, 0x6f, - 0x30, 0x20, 0x4e, 0x6f, 0x20, 0x30, 0x1f, 0x6f, 0x40, 0x70, 0x0a, 0x6f, 0x30, 0xa0, 0x4e, 0x6f, 0x30, 0x00, 0x5b, - 0x6f, 0x30, 0x00, 0x3f, 0x93, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x93, 0x01, 0x00, 0x00, 0x13, 0x02, 0x00, - 0x00, 0x93, 0x02, 0x00, 0x00, 0x13, 0x03, 0x00, 0x00, 0x93, 0x03, 0x00, 0x00, 0x13, 0x04, 0x00, 0x00, 0x93, 0x04, - 0x00, 0x00, 0x13, 0x05, 0x00, 0x00, 0x93, 0x05, 0x00, 0x00, 0x13, 0x06, 0x00, 0x00, 0x93, 0x06, 0x00, 0x00, 0x13, - 0x07, 0x00, 0x00, 0x93, 0x07, 0x00, 0x00, 0x13, 0x08, 0x00, 0x00, 0x93, 0x08, 0x00, 0x00, 0x13, 0x09, 0x00, 0x00, - 0x93, 0x09, 0x00, 0x00, 0x13, 0x0a, 0x00, 0x00, 0x93, 0x0a, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x93, 0x0b, 0x00, - 0x00, 0x13, 0x0c, 0x00, 0x00, 0x93, 0x0c, 0x00, 0x00, 0x13, 0x0d, 0x00, 0x00, 0x93, 0x0d, 0x00, 0x00, 0x13, 0x0e, - 0x00, 0x00, 0x93, 0x0e, 0x00, 0x00, 0x13, 0x0f, 0x00, 0x00, 0x93, 0x0f, 0x00, 0x00, 0x97, 0x00, 0x00, 0x00, 0x93, - 0x80, 0x40, 0xf0, 0x73, 0x90, 0x50, 0x30, 0x93, 0x00, 0x00, 0x00, 0x17, 0x41, 0x10, 0x00, 0xfa, 0x8c, 0x38, 0x4b, - 0x9e, 0xf7, 0xd8, 0x36, 0x8a, 0x5e, 0xb4, 0xaf, 0x58, 0xe5, 0x16, 0x9f, 0x62, 0x85, 0xb1, 0xa9, 0x34, 0xb8, 0x37, - 0x50, 0xd0, 0x6f, 0x48, 0x35, 0x7b, 0xfd, 0xbb, 0x88, 0x6b, 0x10, 0x05, 0x13, 0x01, 0x41, 0xcf, 0x33, 0x04, 0x01, - 0x00, 0x17, 0x0d, 0x10, 0x00, 0x13, 0x0d, 0x8d, 0xee, 0x97, 0x4d, 0x10, 0x00, 0x93, 0x8d, 0x0d, 0xce, 0x63, 0x57, - 0xbd, 0x01, 0x23, 0x20, 0x0d, 0x00, 0x11, 0x0d, 0xe3, 0x4d, 0xbd, 0xff, 0xef, 0x00, 0xf0, 0x60, 0x73, 0x00, 0x50, - 0x10, 0xf5, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa6, 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0x07, 0xf4, - 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0x07, 0xf2, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0x07, 0xf2, 0xb7, 0x37, 0x20, - 0x00, 0x23, 0x88, 0x07, 0xf2, 0x82, 0x80, 0x18, 0x41, 0xfd, 0x57, 0x63, 0x02, 0xf7, 0x06, 0x13, 0x07, 0x45, 0x00, - 0x81, 0x47, 0x13, 0x06, 0xf0, 0x07, 0x14, 0x43, 0x81, 0xea, 0x85, 0x07, 0x11, 0x07, 0xe3, 0x9c, 0xc7, 0xfe, 0x13, - 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x01, 0x47, 0x93, 0x05, 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, 0x05, 0x8a, 0x19, 0xca, - 0x93, 0x05, 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, 0x05, 0x8a, 0x15, 0xc6, 0x05, 0x07, 0xe3, 0x1b, 0xb7, 0xfe, 0x21, - 0xa0, 0x05, 0x07, 0xe3, 0x11, 0xb7, 0xfe, 0x89, 0x07, 0x93, 0x06, 0x00, 0x08, 0x7d, 0x56, 0xe3, 0x85, 0xd7, 0xfc, - 0x85, 0x07, 0x13, 0x97, 0x27, 0x00, 0x2a, 0x97, 0x03, 0x27, 0xc7, 0xff, 0xe3, 0x08, 0xc7, 0xfe, 0x13, 0x05, 0x50, - 0x05, 0x82, 0x80, 0x05, 0x67, 0xaa, 0x87, 0x01, 0x17, 0x01, 0x45, 0x94, 0x43, 0x99, 0xe6, 0x13, 0x05, 0x05, 0x02, - 0xfa, 0x52, 0x1b, 0x54, 0xca, 0x45, 0x78, 0x0a, 0xe4, 0xbf, 0x96, 0x91, 0x74, 0x22, 0x07, 0xd7, 0xc2, 0x2c, 0x98, - 0x2c, 0xcb, 0x7c, 0x27, 0xd3, 0x77, 0x07, 0x3b, 0x7e, 0x40, 0x3b, 0x6a, 0x3c, 0x0b, 0xe8, 0x05, 0x91, 0x07, 0xe3, - 0x1b, 0xe5, 0xfe, 0x82, 0x80, 0x81, 0x47, 0x13, 0x06, 0x00, 0x02, 0x33, 0xd7, 0xf6, 0x00, 0x05, 0x8b, 0x09, 0xe7, - 0x85, 0x07, 0x05, 0x05, 0xe3, 0x9a, 0xc7, 0xfe, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x14, 0x20, 0x00, 0x13, - 0x04, 0x04, 0x00, 0x83, 0x46, 0x94, 0x07, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, - 0x13, 0x05, 0x45, 0x64, 0x13, 0x06, 0x06, 0x3d, 0x93, 0x85, 0xc5, 0x3d, 0x06, 0xc6, 0xef, 0x10, 0x30, 0x4c, 0x03, - 0x45, 0x94, 0x07, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x40, 0x90, 0x0b, - 0xef, 0x20, 0xc0, 0x58, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x00, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x40, 0x50, - 0x0c, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x05, 0x05, 0x10, 0x2a, 0x84, 0x37, 0x55, - 0x10, 0x00, 0x13, 0x05, 0x45, 0x3e, 0x06, 0xc6, 0xef, 0x10, 0x30, 0x4f, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, - 0xf5, 0x14, 0x43, 0x85, 0x47, 0xb3, 0x97, 0x87, 0x00, 0xb2, 0x40, 0x22, 0x44, 0x93, 0xc7, 0xf7, 0xff, 0xf5, 0x8f, - 0x1c, 0xc3, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x2a, 0x84, 0x93, 0x04, 0xa0, - 0x0a, 0xef, 0x20, 0x10, 0x76, 0x63, 0x19, 0x95, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, - 0x41, 0x01, 0x82, 0x80, 0xfa, 0x95, 0xa9, 0xbb, 0xb8, 0x79, 0xf6, 0x12, 0x84, 0xcc, 0xba, 0xc5, 0xe8, 0x6c, 0xb3, - 0xc4, 0xb5, 0x96, 0x43, 0x09, 0x28, 0x37, 0xb4, 0x8f, 0xdb, 0x78, 0xe7, 0x28, 0xf4, 0x79, 0xba, 0xac, 0x94, 0xc0, - 0x06, 0x22, 0x85, 0xef, 0x20, 0x90, 0x78, 0x22, 0x85, 0xef, 0x20, 0x30, 0x74, 0xe3, 0x03, 0x95, 0xfe, 0x37, 0x55, - 0x10, 0x00, 0x13, 0x05, 0x45, 0x3e, 0x85, 0x45, 0xef, 0x10, 0x10, 0x49, 0x13, 0x05, 0x50, 0x05, 0xd1, 0xbf, 0x01, - 0x11, 0x22, 0xcc, 0x2a, 0x84, 0x37, 0x35, 0x00, 0x08, 0x06, 0xce, 0x2e, 0xc6, 0xef, 0x30, 0x10, 0x0a, 0x32, 0x46, - 0xa2, 0x85, 0x37, 0x35, 0x00, 0x08, 0xef, 0x30, 0x50, 0x0e, 0x62, 0x44, 0xf2, 0x40, 0x37, 0x35, 0x00, 0x08, 0x05, - 0x61, 0x6f, 0x30, 0xb0, 0x0b, 0x6d, 0x71, 0x23, 0x24, 0x81, 0x10, 0x2a, 0x84, 0x0a, 0x85, 0x23, 0x26, 0x11, 0x10, - 0xef, 0x10, 0x50, 0x63, 0x0a, 0x85, 0x23, 0x00, 0x81, 0x00, 0xef, 0x20, 0xc0, 0x3e, 0x83, 0x20, 0xc1, 0x10, 0x03, - 0x24, 0x81, 0x10, 0x51, 0x61, 0x82, 0x80, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0x2e, 0xc4, 0xef, 0x20, 0xd0, 0x1a, - 0xa2, 0x45, 0x32, 0x45, 0xef, 0x20, 0xd0, 0x32, 0x2a, 0xc4, 0xef, 0x20, 0x90, 0x1b, 0xf2, 0x40, 0x22, 0x45, 0x05, - 0x61, 0x82, 0x80, 0x13, 0x01, 0x01, 0xde, 0x23, 0x2c, 0x81, 0x20, 0x2e, 0x84, 0xaa, 0x05, 0x23, 0x28, 0x21, 0x21, - 0x93, 0x85, 0x05, 0x20, 0x2a, 0x89, 0x08, 0x08, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x2a, 0x91, 0x20, 0x7d, 0x3f, 0x93, - 0x07, 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x04, 0xaa, 0x84, 0x08, 0x08, 0xcd, 0x33, 0x63, 0x00, 0x95, 0x02, 0x22, 0x85, - 0xd1, 0x3d, 0x09, 0x45, 0x83, 0x20, 0xc1, 0x21, 0xfa, 0x6d, 0xda, 0xfa, 0x5d, 0x24, 0x3d, 0x74, 0xe5, 0x1a, 0x0d, - 0x11, 0x43, 0xbe, 0xb6, 0x3c, 0x6f, 0xc8, 0x25, 0xaf, 0x99, 0x26, 0x67, 0xee, 0xd0, 0x92, 0xc0, 0xc6, 0x1b, 0x2e, - 0x4f, 0xbd, 0x8c, 0x98, 0x07, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, 0x41, 0x21, 0x03, 0x29, 0x01, 0x21, 0x13, 0x01, - 0x01, 0x22, 0x82, 0x80, 0x42, 0x44, 0x48, 0x08, 0x22, 0xc6, 0x25, 0x35, 0x09, 0x8c, 0x11, 0x46, 0x6c, 0x00, 0x4a, - 0x85, 0x22, 0xc6, 0xef, 0x40, 0x70, 0x7c, 0x05, 0x45, 0xc9, 0xbf, 0x01, 0x45, 0xf9, 0xb7, 0x41, 0x11, 0x4a, 0xc0, - 0x03, 0xa9, 0x05, 0x00, 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0x2e, 0x84, 0xaa, 0x84, 0xef, 0x20, 0x10, 0x67, 0xca, - 0x85, 0x26, 0x85, 0xef, 0x20, 0x70, 0x1e, 0xa6, 0x85, 0x22, 0x85, 0xef, 0x20, 0xb0, 0x28, 0x93, 0x07, 0xa0, 0x0a, - 0x63, 0x16, 0xf5, 0x02, 0x1c, 0x40, 0x63, 0x93, 0x27, 0x03, 0x93, 0x07, 0x44, 0x00, 0x7d, 0x57, 0x13, 0x04, 0x04, - 0x20, 0x94, 0x43, 0x63, 0x9b, 0xe6, 0x00, 0x91, 0x07, 0xe3, 0x9c, 0x87, 0xfe, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, - 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0xc5, 0xbf, 0x13, 0x01, 0x01, 0xde, 0x23, 0x26, 0x31, - 0x21, 0x93, 0x19, 0xa5, 0x00, 0x23, 0x2a, 0x91, 0x20, 0x93, 0x84, 0x09, 0x20, 0x23, 0x2c, 0x81, 0x20, 0xa6, 0x85, - 0x2a, 0x84, 0x0a, 0x85, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x28, 0x21, 0x21, 0xfd, 0x35, 0x93, 0x07, 0xa0, 0x0a, 0x63, - 0x00, 0xf5, 0x02, 0x01, 0x45, 0x83, 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, 0x41, 0x21, 0x03, 0x29, - 0x01, 0x21, 0x83, 0x29, 0xc1, 0x20, 0x13, 0x01, 0x01, 0x22, 0x82, 0x80, 0xfa, 0xf5, 0x68, 0x71, 0xa8, 0x2d, 0xa8, - 0x39, 0x0f, 0xbb, 0x03, 0xbc, 0x0a, 0x15, 0xc4, 0x54, 0xe1, 0xdd, 0x4e, 0xe3, 0xd6, 0x42, 0x20, 0xb3, 0x5a, 0xdf, - 0x9b, 0x20, 0xe0, 0x92, 0xad, 0x96, 0x83, 0x70, 0x08, 0x2a, 0x89, 0x0a, 0x85, 0xdd, 0x39, 0x63, 0x06, 0x25, 0x01, - 0x22, 0x85, 0xe5, 0x33, 0x09, 0x45, 0xd9, 0xbf, 0x02, 0x44, 0x48, 0x00, 0x89, 0x3b, 0xaa, 0x87, 0x33, 0x06, 0xa4, - 0x40, 0x0d, 0x45, 0xe3, 0x03, 0xf4, 0xfc, 0x09, 0x45, 0xe3, 0x60, 0xc4, 0xfc, 0x5c, 0x00, 0x01, 0x44, 0x13, 0x08, - 0x00, 0x02, 0x13, 0x05, 0xf0, 0x07, 0x8c, 0x43, 0x89, 0xc9, 0x81, 0x46, 0x33, 0xd7, 0xd5, 0x00, 0x05, 0x8b, 0x05, - 0xeb, 0x85, 0x06, 0xe3, 0x9b, 0x06, 0xff, 0x05, 0x04, 0x91, 0x07, 0xe3, 0x14, 0xa4, 0xfe, 0x7d, 0x16, 0x8a, 0x85, - 0x13, 0x85, 0x09, 0x40, 0x32, 0xc0, 0xf5, 0x3d, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x11, 0xf5, 0xf8, 0x8a, 0x85, 0x26, - 0x85, 0xfd, 0x35, 0x13, 0x05, 0x65, 0xf5, 0x1d, 0xa8, 0x05, 0x47, 0x33, 0x17, 0xd7, 0x00, 0x13, 0x47, 0xf7, 0xff, - 0x6d, 0x8f, 0x98, 0xc3, 0xef, 0x20, 0xc0, 0x7f, 0x18, 0x04, 0x93, 0x17, 0x24, 0x00, 0xba, 0x97, 0x83, 0xa5, 0x47, - 0xe0, 0x13, 0x05, 0x14, 0x00, 0x0a, 0x05, 0x26, 0x95, 0xef, 0x20, 0x50, 0x10, 0x2a, 0x84, 0xef, 0x20, 0x80, 0x7f, - 0x13, 0x05, 0x64, 0xf5, 0x13, 0x35, 0x15, 0x00, 0x35, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x07, 0x30, - 0x0c, 0x2a, 0x84, 0x63, 0x04, 0xf5, 0x00, 0xef, 0x20, 0xc0, 0x4b, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, - 0x05, 0x67, 0x23, 0x80, 0x87, 0x00, 0xba, 0x97, 0xf8, 0x5b, 0x19, 0xe3, 0x05, 0x47, 0xf8, 0xdb, 0xfa, 0x1e, 0x3c, - 0x60, 0x76, 0xc5, 0x61, 0xca, 0xfe, 0xbf, 0x37, 0x81, 0x1a, 0x70, 0x4b, 0xb9, 0x7f, 0xa3, 0x87, 0x18, 0x19, 0x39, - 0x58, 0xc4, 0x05, 0x1e, 0xfa, 0xfa, 0x82, 0xf8, 0xbd, 0xd2, 0x6a, 0x48, 0x09, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, - 0x82, 0x80, 0x05, 0x66, 0x37, 0x05, 0x20, 0x00, 0x41, 0x11, 0x13, 0x06, 0xc6, 0x07, 0x81, 0x45, 0x13, 0x05, 0x05, - 0x00, 0x06, 0xc6, 0xef, 0x40, 0xb0, 0x65, 0xef, 0x20, 0x80, 0x41, 0xef, 0x40, 0x80, 0x39, 0xb2, 0x40, 0x41, 0x01, - 0x6f, 0x20, 0x00, 0x38, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x20, 0x00, 0x55, 0xef, 0x20, 0x90, 0x7f, 0xef, 0x40, 0xa0, - 0x0c, 0xef, 0x40, 0x00, 0x65, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x30, 0xe0, 0x15, 0x69, 0x71, 0x08, 0x08, 0x23, 0x22, - 0x91, 0x12, 0x23, 0x20, 0x21, 0x13, 0x23, 0x2c, 0x41, 0x11, 0x23, 0x26, 0x11, 0x12, 0x23, 0x24, 0x81, 0x12, 0x23, - 0x2e, 0x31, 0x11, 0x23, 0x2a, 0x51, 0x11, 0xef, 0x10, 0xf0, 0x39, 0x91, 0x47, 0x37, 0x39, 0x20, 0x00, 0x23, 0x08, - 0xf1, 0x00, 0x83, 0x27, 0xc9, 0xf4, 0x37, 0x1a, 0x20, 0x00, 0xb7, 0x34, 0x20, 0x00, 0x13, 0x09, 0xc9, 0xf4, 0x13, - 0x0a, 0x0a, 0x00, 0x93, 0x84, 0x84, 0xf4, 0xc5, 0xe7, 0x83, 0x27, 0x4a, 0x07, 0x09, 0x46, 0x6c, 0x00, 0x23, 0x20, - 0xf9, 0x00, 0x13, 0x05, 0x21, 0x01, 0xc1, 0x17, 0x3e, 0xc6, 0x23, 0xa0, 0x04, 0x00, 0xef, 0x40, 0xf0, 0x58, 0x89, - 0x47, 0xa3, 0x08, 0xf1, 0x00, 0x13, 0x04, 0xe0, 0x07, 0x93, 0x09, 0x41, 0x01, 0x03, 0x27, 0x09, 0x00, 0x94, 0x40, - 0xb3, 0x07, 0xd7, 0x40, 0x63, 0xf3, 0x87, 0x00, 0x3e, 0x84, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x5a, 0x10, 0x00, 0x37, - 0x55, 0xfa, 0x91, 0x26, 0xde, 0x69, 0xcb, 0x7d, 0x21, 0xd2, 0x14, 0xfe, 0x53, 0xc7, 0x55, 0x75, 0xe7, 0x05, 0xfc, - 0xe4, 0xb3, 0xd3, 0x8b, 0xf6, 0xea, 0xcc, 0x23, 0x26, 0x91, 0xf9, 0x23, 0x32, 0x0e, 0x14, 0x20, 0x0a, 0x10, 0x00, - 0xa2, 0x87, 0x93, 0x85, 0xca, 0x3f, 0x13, 0x06, 0xc6, 0x3e, 0x13, 0x05, 0x45, 0x40, 0xef, 0x10, 0x50, 0x0c, 0x8c, - 0x40, 0x83, 0x27, 0x4a, 0x07, 0x33, 0x07, 0xb4, 0x00, 0x63, 0xf7, 0xe7, 0x04, 0x8d, 0x45, 0x13, 0x85, 0xca, 0x3f, - 0xef, 0x10, 0x30, 0x12, 0x13, 0x04, 0x50, 0x05, 0xc5, 0x3c, 0xef, 0x40, 0x60, 0x2a, 0xef, 0x20, 0xa0, 0x32, 0xef, - 0x20, 0xa0, 0x29, 0x29, 0x3f, 0x83, 0x20, 0xc1, 0x12, 0x22, 0x85, 0x03, 0x24, 0x81, 0x12, 0x83, 0x24, 0x41, 0x12, - 0x03, 0x29, 0x01, 0x12, 0x83, 0x29, 0xc1, 0x11, 0x03, 0x2a, 0x81, 0x11, 0x83, 0x2a, 0x41, 0x11, 0x55, 0x61, 0x82, - 0x80, 0x13, 0x04, 0x00, 0x08, 0x93, 0x09, 0x21, 0x01, 0xb5, 0xbf, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, - 0x22, 0x86, 0xbe, 0x95, 0x4e, 0x85, 0xef, 0x40, 0x90, 0x4e, 0x83, 0x47, 0x11, 0x01, 0x98, 0x40, 0x22, 0x97, 0x3e, - 0x94, 0x83, 0x27, 0x09, 0x00, 0xa3, 0x08, 0x81, 0x00, 0x98, 0xc0, 0x13, 0x04, 0x50, 0x05, 0x63, 0x17, 0xf7, 0x00, - 0x89, 0x47, 0x23, 0x08, 0xf1, 0x00, 0x13, 0x04, 0xa0, 0x0a, 0x08, 0x08, 0xef, 0x20, 0xe0, 0x04, 0x59, 0xbf, 0x41, - 0x11, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x06, 0xc6, 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x20, 0xe0, 0x26, - 0x85, 0x3d, 0xb9, 0x3c, 0xef, 0x30, 0x20, 0x07, 0x41, 0x3d, 0xb2, 0x40, 0x1d, 0x65, 0x13, 0x05, 0x05, 0x6c, 0x41, - 0x01, 0x6f, 0x30, 0x00, 0x0f, 0xfa, 0xf6, 0xaa, 0x81, 0xf6, 0x74, 0x4c, 0x1f, 0x20, 0x1a, 0x6c, 0x44, 0x55, 0x84, - 0x9f, 0x6f, 0xef, 0x37, 0x4f, 0xab, 0x96, 0x06, 0x9e, 0xb3, 0x12, 0x78, 0xf4, 0xa0, 0x3d, 0x92, 0xd2, 0x92, 0xa1, - 0xf8, 0x0a, 0x41, 0x11, 0x26, 0xc2, 0xae, 0x84, 0xb6, 0x85, 0x06, 0xc6, 0x22, 0xc4, 0x4a, 0xc0, 0x36, 0x84, 0x32, - 0x89, 0xef, 0x40, 0x40, 0x4f, 0x22, 0x86, 0xca, 0x85, 0x13, 0x05, 0x00, 0x02, 0xef, 0x40, 0x00, 0x58, 0xef, 0x40, - 0x60, 0x4c, 0xef, 0x40, 0xe0, 0x67, 0x93, 0x07, 0xa0, 0x0a, 0x13, 0x04, 0x50, 0x05, 0x63, 0x1a, 0xf5, 0x00, 0x2a, - 0x84, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0x00, 0x02, 0x26, 0x85, 0xef, 0x40, 0xe0, 0x50, 0xb2, 0x40, 0x22, 0x85, - 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x85, 0x67, 0xc1, 0x07, 0x63, 0xee, 0xb7, 0x02, 0x41, - 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xae, 0x84, 0x37, 0x04, 0x20, 0x00, 0x19, 0xc5, 0x2e, 0x86, 0xaa, 0x85, - 0x13, 0x05, 0x04, 0x00, 0xef, 0x40, 0xd0, 0x42, 0x13, 0x04, 0x04, 0x00, 0x93, 0x07, 0x30, 0xfc, 0x23, 0x00, 0xf4, - 0x00, 0x85, 0x67, 0x3e, 0x94, 0x64, 0xd8, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x82, 0x80, - 0x13, 0x01, 0x01, 0xdd, 0x23, 0x24, 0x81, 0x22, 0x23, 0x22, 0x91, 0x22, 0x23, 0x20, 0x21, 0x23, 0x23, 0x2e, 0x31, - 0x21, 0x23, 0x2c, 0x41, 0x21, 0x23, 0x2a, 0x51, 0x21, 0x23, 0x28, 0x61, 0x21, 0x23, 0x26, 0x71, 0x21, 0x23, 0x24, - 0x81, 0x21, 0x23, 0x26, 0x11, 0x22, 0x13, 0x04, 0x00, 0x20, 0x01, 0x49, 0x93, 0x04, 0xa0, 0x0a, 0x37, 0x3a, 0x20, - 0x00, 0x85, 0x4a, 0x37, 0x5b, 0x10, 0x00, 0xb7, 0x5b, 0xfa, 0x64, 0x38, 0xe7, 0xac, 0xe1, 0xa4, 0x84, 0x8e, 0x0a, - 0x58, 0x23, 0x7e, 0x6e, 0x2d, 0x9d, 0x11, 0xed, 0xb8, 0xc2, 0x64, 0x19, 0x20, 0xaf, 0x9f, 0xc8, 0x49, 0x86, 0x62, - 0x5e, 0x11, 0x1a, 0xa0, 0xd0, 0x0b, 0x10, 0x00, 0x37, 0x5c, 0x10, 0x00, 0xc1, 0x49, 0xa2, 0x85, 0x0a, 0x85, 0xb1, - 0x3e, 0x63, 0x16, 0x95, 0x02, 0x0a, 0x85, 0x59, 0x32, 0x63, 0x1e, 0x95, 0x04, 0x13, 0x07, 0x4a, 0xf5, 0x14, 0x43, - 0xb3, 0x97, 0x2a, 0x01, 0x13, 0x06, 0x8b, 0x40, 0xd5, 0x8f, 0x93, 0x85, 0x4b, 0x3e, 0xca, 0x86, 0x13, 0x05, 0x4c, - 0x64, 0x1c, 0xc3, 0xef, 0x10, 0xe0, 0x6e, 0x05, 0x09, 0x13, 0x04, 0x04, 0x40, 0xe3, 0x14, 0x39, 0xfd, 0x83, 0x20, - 0xc1, 0x22, 0x03, 0x24, 0x81, 0x22, 0x83, 0x24, 0x41, 0x22, 0x03, 0x29, 0x01, 0x22, 0x83, 0x29, 0xc1, 0x21, 0x03, - 0x2a, 0x81, 0x21, 0x83, 0x2a, 0x41, 0x21, 0x03, 0x2b, 0x01, 0x21, 0x83, 0x2b, 0xc1, 0x20, 0x03, 0x2c, 0x81, 0x20, - 0x13, 0x01, 0x01, 0x23, 0x82, 0x80, 0x93, 0x05, 0x04, 0x20, 0x0a, 0x85, 0xc5, 0x3c, 0xe3, 0x10, 0x95, 0xfc, 0x0a, - 0x85, 0xef, 0xf0, 0xbf, 0x91, 0xe3, 0x1b, 0x95, 0xfa, 0x22, 0x85, 0xef, 0x20, 0x10, 0x1f, 0x8a, 0x85, 0x22, 0x85, - 0xef, 0x20, 0x70, 0x06, 0xa2, 0x85, 0x0a, 0x85, 0xf9, 0x34, 0xe3, 0x1f, 0x95, 0xf8, 0x0a, 0x85, 0xef, 0xf0, 0x9f, - 0x8f, 0xe3, 0x0a, 0x95, 0xf6, 0x41, 0xbf, 0xb7, 0x05, 0x00, 0x80, 0x37, 0x55, 0x10, 0x00, 0x86, 0x87, 0x6d, 0x71, - 0xbe, 0x95, 0x13, 0x05, 0x45, 0x41, 0x23, 0x26, 0x11, 0x10, 0xef, 0x10, 0x80, 0x6d, 0xb7, 0x37, 0x20, 0x00, 0x03, - 0xa7, 0x87, 0xf2, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x1e, 0xf7, 0x02, 0x37, 0x15, 0xfa, 0x1e, 0x8d, 0xca, 0xa1, 0x1e, - 0x9e, 0x6d, 0x0c, 0x79, 0x8d, 0x62, 0xa7, 0x19, 0xb8, 0x15, 0x99, 0x54, 0x67, 0x24, 0x6c, 0x1f, 0xec, 0x56, 0xfa, - 0xfa, 0x30, 0x49, 0x04, 0x8e, 0xc6, 0x8d, 0xf7, 0xa8, 0x0c, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x9a, 0xef, 0x10, 0xf0, - 0x5f, 0x13, 0x05, 0xc0, 0x0f, 0xef, 0x10, 0xa0, 0x5a, 0x0a, 0x85, 0xef, 0x10, 0x70, 0x09, 0x93, 0x07, 0xf0, 0x07, - 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x00, 0x23, 0x00, 0xf1, 0x00, 0xef, 0x10, 0x00, 0x54, 0xa3, 0x00, 0xa1, - 0x00, 0x0a, 0x85, 0xef, 0x10, 0x70, 0x60, 0x05, 0x45, 0xef, 0x40, 0x00, 0x67, 0xef, 0x40, 0x00, 0x66, 0xd5, 0x33, - 0xef, 0x10, 0x50, 0x2d, 0xf5, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0x40, 0x60, 0x4c, 0x93, 0x07, 0x00, - 0x08, 0x63, 0xf3, 0xa7, 0x00, 0xad, 0x3f, 0x2a, 0x84, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0x50, 0x7e, 0xb7, 0x17, - 0x20, 0x00, 0xb2, 0x40, 0x23, 0xaa, 0x87, 0x06, 0x22, 0x44, 0x13, 0x05, 0x30, 0x0c, 0x41, 0x01, 0x82, 0x80, 0x93, - 0x07, 0xf0, 0x17, 0x63, 0xf5, 0xa7, 0x00, 0x41, 0x11, 0x06, 0xc6, 0xb9, 0x37, 0x6f, 0x10, 0xb0, 0x3e, 0x41, 0x11, - 0x22, 0xc4, 0x26, 0xc2, 0x4a, 0xc0, 0x2e, 0x84, 0x06, 0xc6, 0xaa, 0x84, 0xc5, 0x37, 0x61, 0x8d, 0x13, 0x09, 0x50, - 0x05, 0x19, 0xc1, 0x13, 0x09, 0xa0, 0x0a, 0x26, 0x85, 0xc1, 0x3f, 0x69, 0x8c, 0x13, 0x05, 0xa0, 0x0a, 0x19, 0xe0, - 0x13, 0x05, 0x50, 0x05, 0x63, 0x03, 0x25, 0x01, 0x21, 0x3f, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, - 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x8d, 0x47, 0x63, 0xf3, 0xa7, 0x00, 0x01, 0x37, 0x89, 0x67, 0xfa, 0x7c, - 0x04, 0x9a, 0xc3, 0x9e, 0x14, 0xd9, 0x7c, 0x48, 0xa8, 0xd3, 0xba, 0x40, 0x2f, 0x30, 0x6e, 0xaa, 0x95, 0xd6, 0x7b, - 0x6d, 0x2a, 0x1c, 0x64, 0x88, 0x77, 0xfb, 0xd0, 0xf0, 0xc7, 0x3b, 0xc6, 0x80, 0x0d, 0x93, 0x87, 0x07, 0xbf, 0x0a, - 0x05, 0x3e, 0x95, 0xef, 0x30, 0xe0, 0x02, 0xaa, 0x87, 0x13, 0x07, 0xf0, 0x0f, 0x55, 0x45, 0x63, 0x89, 0xe7, 0x00, - 0x13, 0x07, 0xa0, 0x0a, 0x59, 0x45, 0x63, 0x94, 0xe7, 0x00, 0x13, 0x05, 0x30, 0x0c, 0xb2, 0x40, 0x41, 0x01, 0x82, - 0x80, 0x21, 0x71, 0x23, 0x2c, 0x81, 0x1a, 0x2a, 0x84, 0x08, 0x09, 0x23, 0x2e, 0x11, 0x1a, 0x23, 0x2a, 0x91, 0x1a, - 0x23, 0x28, 0x21, 0x1b, 0x23, 0x26, 0x31, 0x1b, 0x23, 0x24, 0x41, 0x1b, 0x23, 0x22, 0x51, 0x1b, 0x23, 0x20, 0x61, - 0x1b, 0x23, 0x2e, 0x71, 0x19, 0x23, 0x2c, 0x81, 0x19, 0x23, 0x2a, 0x91, 0x19, 0xef, 0x10, 0x40, 0x77, 0x83, 0x47, - 0x04, 0x00, 0x05, 0x47, 0x23, 0x18, 0xe1, 0x08, 0xc1, 0x46, 0x63, 0x80, 0xd7, 0x46, 0x63, 0xee, 0xf6, 0x02, 0x91, - 0x46, 0x63, 0x88, 0xd7, 0x34, 0x63, 0xe1, 0xf6, 0x02, 0x63, 0x86, 0xe7, 0x06, 0x09, 0x47, 0x63, 0x81, 0xe7, 0x0e, - 0x93, 0x07, 0xe0, 0x07, 0x23, 0x08, 0xf1, 0x08, 0x08, 0x09, 0xef, 0x10, 0xd0, 0x4c, 0x93, 0x07, 0x50, 0x05, 0x99, - 0xa1, 0x21, 0x47, 0xe3, 0x95, 0xe7, 0xfe, 0x83, 0x47, 0x14, 0x00, 0xd1, 0xeb, 0x4d, 0x31, 0x39, 0xa9, 0x93, 0x06, - 0x20, 0x0a, 0x63, 0x85, 0xd7, 0x4c, 0x93, 0x06, 0x30, 0x0b, 0x63, 0x82, 0xd7, 0x46, 0x93, 0x06, 0x00, 0x02, 0xe3, - 0x94, 0xd7, 0xfc, 0x83, 0x47, 0x14, 0x00, 0x63, 0x99, 0xe7, 0x06, 0x03, 0x47, 0x24, 0x00, 0x95, 0x47, 0x63, 0x14, - 0xf7, 0x06, 0xfa, 0xeb, 0x8c, 0x17, 0x29, 0xa7, 0xe4, 0x6f, 0xfd, 0x02, 0xd7, 0x94, 0x7b, 0x38, 0x27, 0x89, 0x5e, - 0x30, 0x2e, 0x53, 0x49, 0x89, 0x2b, 0x09, 0xc4, 0xf1, 0x64, 0x19, 0xcf, 0x37, 0x9a, 0x54, 0xb3, 0x58, 0x0e, 0x85, - 0x45, 0x61, 0x45, 0xe1, 0x3d, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x09, 0xf5, 0x42, 0x13, 0x04, 0x80, 0xf8, 0x7d, 0xa0, - 0x03, 0x47, 0x14, 0x00, 0x89, 0x47, 0x63, 0x15, 0xf7, 0x04, 0x83, 0x47, 0x24, 0x00, 0x63, 0x8a, 0xe7, 0x04, 0x63, - 0x6b, 0xf7, 0x02, 0xa1, 0xe3, 0x83, 0x45, 0x34, 0x00, 0xf5, 0x47, 0x63, 0xe9, 0xb7, 0x02, 0x9e, 0x05, 0x13, 0x06, - 0x00, 0x08, 0x93, 0x85, 0x05, 0x10, 0x13, 0x05, 0x21, 0x09, 0xef, 0x20, 0x30, 0x6d, 0x13, 0x04, 0x00, 0x08, 0x08, - 0x09, 0xa3, 0x08, 0x81, 0x08, 0xef, 0x10, 0x70, 0x43, 0x93, 0x07, 0xa0, 0x0a, 0x45, 0xae, 0x13, 0x05, 0x80, 0x1e, - 0x63, 0x8d, 0xd7, 0x00, 0x13, 0x04, 0x10, 0xf8, 0xa1, 0xa8, 0x89, 0x65, 0x13, 0x06, 0x00, 0x08, 0x93, 0x85, 0x05, - 0x90, 0xf1, 0xb7, 0x13, 0x05, 0x00, 0x1f, 0xef, 0x10, 0x90, 0x24, 0x2a, 0xc6, 0x11, 0x46, 0x6c, 0x00, 0x13, 0x05, - 0x21, 0x09, 0xef, 0x40, 0x30, 0x0a, 0x11, 0x44, 0x7d, 0xbf, 0x83, 0x44, 0x14, 0x00, 0xc5, 0x36, 0x93, 0x07, 0x10, - 0x02, 0xe3, 0x95, 0xf4, 0xfc, 0xef, 0x10, 0x10, 0x7d, 0xef, 0x20, 0x90, 0x27, 0xef, 0x30, 0x90, 0x38, 0xef, 0x40, - 0x60, 0x07, 0x03, 0x45, 0x24, 0x02, 0xa5, 0x35, 0x93, 0x07, 0x30, 0x0c, 0x63, 0x0b, 0xf5, 0x02, 0x13, 0x04, 0x70, - 0xf8, 0xb3, 0x06, 0x80, 0x40, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0xf6, - 0xf6, 0x0f, 0x13, 0x06, 0x86, 0x42, 0xfa, 0x93, 0x90, 0x10, 0x44, 0xea, 0x8b, 0x92, 0x2d, 0xd1, 0xc8, 0xd7, 0x57, - 0x7a, 0xde, 0x71, 0x9e, 0x6b, 0xe9, 0x83, 0x79, 0x81, 0xf4, 0x73, 0x1a, 0xcc, 0x39, 0x10, 0xb8, 0xb2, 0x2d, 0xc0, - 0xb1, 0x30, 0x0f, 0x93, 0x85, 0x45, 0x41, 0x13, 0x05, 0x45, 0x64, 0x23, 0x08, 0xd1, 0x08, 0xef, 0x10, 0x80, 0x3b, - 0xa3, 0x08, 0x01, 0x08, 0xf9, 0xb5, 0x83, 0x44, 0x24, 0x02, 0x19, 0x34, 0x8d, 0x47, 0xe3, 0xe3, 0x97, 0xfc, 0x13, - 0x06, 0x10, 0x08, 0x81, 0x45, 0x68, 0x00, 0xef, 0x40, 0x50, 0x06, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0x24, 0x00, - 0x13, 0x05, 0xd1, 0x00, 0x23, 0x06, 0x91, 0x00, 0xef, 0x40, 0x50, 0x01, 0xef, 0x40, 0x60, 0x00, 0x37, 0x25, 0x00, - 0x08, 0xef, 0x30, 0x80, 0x01, 0x81, 0x46, 0x01, 0x46, 0x93, 0x05, 0xd1, 0x02, 0x45, 0x45, 0x85, 0x3e, 0x93, 0x07, - 0xa0, 0x0a, 0xe3, 0x13, 0xf5, 0xf8, 0x81, 0x45, 0x68, 0x00, 0xef, 0x30, 0x50, 0x2f, 0x93, 0x07, 0xa0, 0x0a, 0x2a, - 0x89, 0xe3, 0x1a, 0xf5, 0xf6, 0x93, 0x06, 0x00, 0x02, 0x13, 0x06, 0xd1, 0x00, 0x93, 0x05, 0xd1, 0x04, 0x49, 0x45, - 0x99, 0x36, 0xaa, 0x84, 0xe3, 0x1f, 0x25, 0xf5, 0x85, 0x45, 0x68, 0x00, 0xef, 0x30, 0xd0, 0x2c, 0x2a, 0x89, 0xe3, - 0x18, 0x95, 0xf4, 0x83, 0x47, 0xc1, 0x00, 0x85, 0x46, 0x13, 0x06, 0xb1, 0x00, 0x93, 0x05, 0xd1, 0x04, 0x4d, 0x45, - 0xa3, 0x05, 0xf1, 0x00, 0x31, 0x3e, 0xaa, 0x84, 0xe3, 0x1a, 0x25, 0xf3, 0x89, 0x45, 0x68, 0x00, 0xef, 0x30, 0x30, - 0x2a, 0x2a, 0x89, 0xe3, 0x13, 0x95, 0xf2, 0x81, 0x46, 0x01, 0x46, 0x93, 0x05, 0xd1, 0x04, 0x51, 0x45, 0xf5, 0x3c, - 0xaa, 0x84, 0xe3, 0x1a, 0x25, 0xf1, 0x8d, 0x45, 0x68, 0x00, 0xfa, 0x40, 0x8d, 0xb1, 0x09, 0x16, 0xc7, 0x8b, 0xf9, - 0xd6, 0xde, 0xe6, 0x71, 0x88, 0x5c, 0x0d, 0xf1, 0xba, 0x73, 0x3c, 0x4a, 0xd0, 0x21, 0x61, 0xf0, 0xf2, 0xe8, 0xfc, - 0x17, 0xd4, 0xd9, 0x80, 0x5a, 0x08, 0x10, 0xef, 0x30, 0x30, 0x28, 0x2a, 0x89, 0xe3, 0x13, 0x95, 0xf0, 0x91, 0x45, - 0x68, 0x00, 0xef, 0x30, 0x50, 0x27, 0xaa, 0x84, 0xe3, 0x1c, 0x25, 0xef, 0x95, 0x45, 0x68, 0x00, 0xef, 0x30, 0x70, - 0x26, 0xe3, 0x16, 0x95, 0xee, 0xb7, 0x19, 0x20, 0x00, 0x13, 0x85, 0x09, 0x02, 0xef, 0x30, 0x70, 0x29, 0xb7, 0x14, - 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0xd1, 0x02, 0x13, 0x85, 0x04, 0x03, 0xef, 0x40, 0xa0, 0x73, 0x37, - 0x15, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0xd1, 0x06, 0x13, 0x05, 0x05, 0x05, 0xef, 0x40, 0x60, 0x72, - 0x03, 0x49, 0x24, 0x02, 0x8d, 0x47, 0x4e, 0x84, 0x63, 0xf3, 0x27, 0x01, 0x01, 0x39, 0x37, 0x5c, 0x10, 0x00, 0xef, - 0x10, 0x10, 0x49, 0x81, 0x4c, 0x13, 0x0c, 0x8c, 0x58, 0x8d, 0x49, 0xfd, 0x5a, 0x13, 0x0a, 0x00, 0x0f, 0x41, 0x6b, - 0xb7, 0x0b, 0x00, 0x01, 0x03, 0x25, 0x0c, 0x00, 0x51, 0x81, 0x49, 0x39, 0x03, 0x27, 0x0c, 0x00, 0x93, 0x57, 0x07, - 0x01, 0xbd, 0x8b, 0x63, 0xe8, 0xf9, 0x00, 0x8e, 0x07, 0xb3, 0x97, 0xfa, 0x00, 0x93, 0xc7, 0xf7, 0xff, 0x7d, 0x8d, - 0x83, 0x46, 0x1c, 0x00, 0x33, 0x55, 0x25, 0x01, 0x93, 0x77, 0x15, 0x00, 0x93, 0xf6, 0x06, 0x0f, 0x63, 0x96, 0x46, - 0x07, 0x99, 0xc3, 0x93, 0x07, 0xf0, 0x0f, 0xbd, 0x65, 0xf9, 0x8d, 0x21, 0x83, 0x3d, 0x8b, 0x22, 0x07, 0x4d, 0x8f, - 0x83, 0x45, 0x0c, 0x00, 0xc2, 0x07, 0x66, 0x85, 0xd9, 0x8d, 0xdd, 0x8d, 0xef, 0x10, 0xfa, 0xbb, 0xf5, 0xc9, 0x9f, - 0x3a, 0xa4, 0xdc, 0xc2, 0x96, 0xab, 0x48, 0x68, 0x5d, 0xb2, 0x0c, 0x89, 0x6c, 0xd2, 0x3b, 0x71, 0x51, 0x52, 0x94, - 0xbc, 0xd4, 0xe6, 0x5a, 0x2f, 0xdb, 0x00, 0x09, 0x5e, 0xe0, 0x10, 0xd0, 0x43, 0x83, 0x47, 0x4c, 0x00, 0x11, 0x0c, - 0x85, 0x0c, 0xc5, 0xf3, 0xef, 0x10, 0x90, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x13, 0x06, 0x00, - 0x02, 0x93, 0x85, 0x04, 0x03, 0x13, 0x05, 0x21, 0x09, 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x40, 0xa0, 0x67, 0x93, 0x05, - 0x04, 0x02, 0x41, 0x46, 0x13, 0x05, 0x21, 0x0b, 0xef, 0x40, 0xc0, 0x66, 0xef, 0x30, 0xf0, 0x6b, 0x13, 0x04, 0x00, - 0x03, 0xef, 0xf0, 0x7f, 0x85, 0xbd, 0xbb, 0x93, 0x76, 0x05, 0x10, 0x99, 0xc2, 0x93, 0xe7, 0x27, 0x00, 0xb3, 0x76, - 0x65, 0x01, 0x99, 0xc2, 0x93, 0xe7, 0x47, 0x00, 0x33, 0x75, 0x75, 0x01, 0x59, 0xd1, 0x93, 0xe7, 0x87, 0x00, 0x41, - 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0xc7, 0xf3, 0x93, 0x07, 0xa0, 0x0a, 0x83, 0x44, 0x14, 0x00, 0x63, 0x14, - 0xf7, 0x0e, 0x91, 0xe4, 0x13, 0x04, 0x10, 0xf8, 0xef, 0xf0, 0xbf, 0x96, 0x4d, 0xbb, 0xb7, 0x39, 0x20, 0x00, 0x83, - 0xa7, 0x89, 0xf3, 0x93, 0x89, 0x89, 0xf3, 0xad, 0xcb, 0x09, 0x04, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x49, 0xf3, - 0x83, 0x26, 0x09, 0x00, 0x03, 0xa7, 0x09, 0x00, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, - 0x00, 0x13, 0x05, 0x45, 0x64, 0xa6, 0x96, 0x13, 0x06, 0xc6, 0x41, 0x93, 0x85, 0xc5, 0x3f, 0xef, 0x10, 0x20, 0x15, - 0x03, 0x25, 0x09, 0x00, 0x83, 0xa7, 0x09, 0x00, 0x33, 0x87, 0xa4, 0x00, 0xe3, 0xe6, 0xe7, 0xfa, 0x85, 0x67, 0xfa, - 0xf3, 0x0a, 0x2c, 0x68, 0x1e, 0x1e, 0xe0, 0xc2, 0x21, 0x0b, 0xe6, 0x19, 0x58, 0xc1, 0x7b, 0x06, 0xf8, 0x5a, 0xae, - 0x57, 0x62, 0x69, 0x7b, 0xe9, 0x9f, 0xb9, 0x02, 0xb1, 0x9c, 0x6a, 0xb1, 0xe7, 0xb8, 0x11, 0x93, 0x87, 0x07, 0x02, - 0xe3, 0xe1, 0xe7, 0xfa, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x26, 0x86, 0x3e, 0x95, 0xa2, 0x85, 0xef, - 0x40, 0x40, 0x5b, 0x83, 0x27, 0x09, 0x00, 0xbe, 0x94, 0x83, 0xa7, 0x09, 0x00, 0x23, 0x20, 0x99, 0x00, 0xbd, 0xe3, - 0x75, 0x54, 0x15, 0xbb, 0x89, 0x47, 0xe3, 0xfb, 0x97, 0xf6, 0x03, 0x49, 0x34, 0x00, 0x83, 0x47, 0x24, 0x00, 0xf9, - 0x14, 0x22, 0x09, 0x3e, 0x99, 0x85, 0x67, 0x93, 0x06, 0xf9, 0xff, 0x13, 0x87, 0xf7, 0x00, 0x11, 0x04, 0xe3, 0x6c, - 0xd7, 0xf4, 0x37, 0x0a, 0x20, 0x00, 0x13, 0x0a, 0x0a, 0x00, 0x3e, 0x9a, 0x41, 0x09, 0x93, 0x07, 0xf0, 0x07, 0xa3, - 0x0c, 0xfa, 0x06, 0x23, 0xa0, 0x29, 0x01, 0xef, 0x10, 0x50, 0x4a, 0xef, 0x20, 0xc0, 0x74, 0xef, 0x30, 0xd0, 0x05, - 0xb7, 0x37, 0x20, 0x00, 0x23, 0x28, 0x2a, 0x07, 0x23, 0x2a, 0x0a, 0x06, 0x23, 0xaa, 0x07, 0xf2, 0x2d, 0xbf, 0x13, - 0x04, 0x60, 0xf8, 0x39, 0xbf, 0xe3, 0x9e, 0xf4, 0xf8, 0x01, 0x44, 0xa1, 0xb9, 0x83, 0x47, 0x14, 0x00, 0xe3, 0x95, - 0x07, 0xc6, 0xef, 0x10, 0x30, 0x15, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x0f, 0x05, 0xc4, 0x83, 0x20, 0xc1, 0x1b, 0x03, - 0x24, 0x81, 0x1b, 0x83, 0x24, 0x41, 0x1b, 0x03, 0x29, 0x01, 0x1b, 0x83, 0x29, 0xc1, 0x1a, 0x03, 0x2a, 0x81, 0x1a, - 0x83, 0x2a, 0x41, 0x1a, 0x03, 0x2b, 0x01, 0x1a, 0x83, 0x2b, 0xc1, 0x19, 0x03, 0x2c, 0x81, 0x19, 0x83, 0x2c, 0x41, - 0x19, 0x3e, 0x85, 0xfa, 0x42, 0x66, 0xc2, 0xea, 0xb1, 0xc2, 0x8c, 0xe0, 0xea, 0xd9, 0xb7, 0x90, 0xe6, 0xa5, 0x01, - 0x75, 0x6d, 0x44, 0x76, 0xbc, 0x8a, 0xcb, 0x45, 0x1d, 0x1f, 0x32, 0xfd, 0xb5, 0xec, 0xea, 0x26, 0xf7, 0x90, 0x12, - 0x39, 0x61, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa2, 0xa7, 0xf4, 0x7d, 0xb7, 0x83, 0x46, 0x14, 0x00, 0xe3, - 0x9d, 0xe6, 0xc0, 0x83, 0x47, 0x24, 0x00, 0x63, 0x8a, 0xd7, 0x02, 0x0d, 0x47, 0xe3, 0x96, 0xe7, 0xc0, 0xa1, 0x45, - 0x01, 0x45, 0xb5, 0x3c, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0xe3, 0x13, 0xf5, 0xba, 0xb7, 0xb5, 0xb5, 0x61, 0x93, - 0x85, 0x55, 0x49, 0x13, 0x05, 0x80, 0x1f, 0xef, 0x10, 0x40, 0x6b, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa6, 0x87, 0xf2, - 0xbd, 0xb7, 0xb7, 0x15, 0x78, 0x4a, 0x93, 0x85, 0x95, 0x21, 0x13, 0x05, 0x80, 0x1f, 0xef, 0x10, 0xa0, 0x69, 0xb7, - 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf2, 0x81, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, - 0x87, 0xf2, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1f, 0xf7, 0xb4, 0x83, 0x47, 0x14, 0x00, 0xe3, 0x96, 0x07, 0xba, 0x93, - 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x09, 0xef, 0x00, 0x50, 0x6f, 0x2a, 0x84, 0xe3, 0x51, 0x05, 0xb8, 0xcd, 0xbe, - 0x41, 0x11, 0x05, 0x45, 0x06, 0xc6, 0xef, 0x40, 0x20, 0x02, 0xb2, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, - 0x0a, 0x23, 0xa0, 0xe7, 0xf4, 0x41, 0x01, 0x82, 0x80, 0x31, 0x71, 0x22, 0xdd, 0x37, 0x34, 0x20, 0x00, 0x93, 0x07, - 0x50, 0x05, 0x06, 0xdf, 0x4a, 0xd9, 0x52, 0xd5, 0x56, 0xd3, 0x62, 0xcd, 0x26, 0xdb, 0x4e, 0xd7, 0x5a, 0xd1, 0x5e, - 0xcf, 0x66, 0xcb, 0x6a, 0xc9, 0x6e, 0xc7, 0xfa, 0x06, 0x4e, 0xfb, 0x7e, 0xe9, 0x3e, 0x95, 0x1b, 0x0a, 0xbe, 0xe4, - 0x6b, 0xc5, 0xc0, 0x3c, 0x86, 0x11, 0x8b, 0xcb, 0x9a, 0xbf, 0x3c, 0xc5, 0x72, 0x9b, 0xe5, 0xc3, 0xd0, 0x6c, 0x12, - 0x70, 0x87, 0x68, 0x13, 0xb7, 0x3a, 0x20, 0x00, 0x37, 0x3a, 0x20, 0x00, 0x37, 0x39, 0x20, 0x00, 0x13, 0x04, 0x84, - 0xf2, 0x23, 0xa0, 0xfa, 0xf4, 0x23, 0x26, 0xfa, 0xf2, 0x23, 0x22, 0xf9, 0xf4, 0x1c, 0xc0, 0xef, 0x10, 0x60, 0x3d, - 0xef, 0x10, 0xc0, 0x55, 0x13, 0x87, 0x0a, 0xf4, 0x3a, 0xc8, 0x13, 0x07, 0xca, 0xf2, 0x3a, 0xca, 0x13, 0x07, 0x49, - 0xf4, 0x93, 0x07, 0xa0, 0x0a, 0x3a, 0xc6, 0x37, 0x5c, 0x10, 0x00, 0x85, 0x45, 0x63, 0x0a, 0xf5, 0x00, 0x13, 0x05, - 0x4c, 0x41, 0xef, 0x00, 0x90, 0x7b, 0xef, 0x10, 0x80, 0x4f, 0xef, 0xf0, 0x3f, 0x8c, 0x41, 0x45, 0xef, 0xf0, 0x5f, - 0x97, 0x08, 0xc0, 0xb7, 0x07, 0x01, 0x02, 0x80, 0x57, 0x98, 0x5b, 0x29, 0x45, 0x59, 0x8c, 0x98, 0x5f, 0x59, 0x8c, - 0x13, 0x77, 0xf4, 0x87, 0x98, 0xd7, 0x98, 0xdb, 0x98, 0xdf, 0xd8, 0x43, 0x13, 0x67, 0x87, 0x00, 0xd8, 0xc3, 0xef, - 0x10, 0x00, 0x38, 0xef, 0x30, 0x30, 0x22, 0x13, 0x75, 0x05, 0x78, 0x11, 0xc5, 0x13, 0x05, 0x00, 0x78, 0x81, 0x45, - 0xef, 0x30, 0x90, 0x1a, 0xb7, 0x07, 0x01, 0x02, 0x80, 0xd7, 0x80, 0xdb, 0x37, 0x15, 0x10, 0x00, 0x80, 0xdf, 0x13, - 0x05, 0xc5, 0x9a, 0xef, 0x10, 0xa0, 0x69, 0x37, 0x56, 0x10, 0x00, 0x37, 0x59, 0x10, 0x00, 0x81, 0x47, 0x01, 0x47, - 0x85, 0x46, 0x13, 0x06, 0x06, 0x43, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x50, 0x6c, 0xef, - 0x30, 0x50, 0x1e, 0x93, 0x07, 0x50, 0x05, 0x63, 0x1e, 0xf5, 0x00, 0xfa, 0x86, 0x50, 0x83, 0xed, 0x9b, 0x2d, 0x0e, - 0x5f, 0xbb, 0x12, 0x85, 0x0a, 0x45, 0x1d, 0x4e, 0x0e, 0x68, 0x8e, 0x71, 0xd1, 0xb0, 0xce, 0xa7, 0x75, 0x8b, 0xa8, - 0x53, 0xe8, 0xf8, 0xc7, 0xe2, 0xd8, 0x40, 0x14, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x46, - 0x44, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x45, 0x40, 0xef, 0x00, 0x10, 0x6a, 0xef, 0x20, 0xa0, 0x2f, 0x51, 0x45, - 0xef, 0x10, 0xc0, 0x4b, 0x1d, 0x89, 0xef, 0x20, 0xc0, 0x2f, 0xef, 0x20, 0xa0, 0x03, 0xef, 0x20, 0x10, 0x03, 0xef, - 0x20, 0x30, 0x31, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0xb0, 0x31, 0x11, 0x46, 0x6c, 0x10, 0x37, 0x35, 0x00, 0x08, - 0xef, 0x20, 0xf0, 0x35, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0xb0, 0x33, 0x32, 0x55, 0xc1, 0x7a, 0x37, 0x0b, 0x01, - 0xff, 0xb7, 0x0b, 0x00, 0x01, 0xef, 0x20, 0x70, 0x22, 0x05, 0x64, 0x01, 0x4a, 0x93, 0x8a, 0xfa, 0x0f, 0x7d, 0x1b, - 0xfd, 0x1b, 0x13, 0x0d, 0x00, 0x18, 0x52, 0x85, 0xef, 0xf0, 0x1f, 0x87, 0xaa, 0x8c, 0x22, 0x85, 0xef, 0x20, 0xd0, - 0x0f, 0x93, 0xf9, 0x09, 0xf0, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, 0x44, 0x00, 0xef, 0x20, 0xd0, 0x0e, 0x22, 0x05, - 0xb3, 0xf9, 0x59, 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, 0x84, 0x00, 0xef, 0x20, 0xb0, 0x0d, 0x42, 0x05, 0xb3, - 0xf9, 0x69, 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, 0xc4, 0x00, 0xef, 0x20, 0x90, 0x0c, 0x62, 0x05, 0xb3, 0xf9, - 0x79, 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x93, 0xc7, 0xf9, 0xff, 0x33, 0xf5, 0x97, 0x01, 0xe3, 0x1b, 0x05, 0xea, 0x11, - 0x0a, 0x41, 0x04, 0xe3, 0x12, 0xaa, 0xfb, 0x37, 0x55, 0x10, 0x00, 0xb7, 0x37, 0x20, 0x00, 0xfa, 0x2c, 0xd8, 0xfc, - 0x42, 0x4d, 0xdb, 0x61, 0x6d, 0x0b, 0x0a, 0x7c, 0x82, 0x39, 0x57, 0x23, 0xcf, 0xbf, 0xd8, 0xf1, 0x52, 0x74, 0x8d, - 0x09, 0x14, 0x23, 0x05, 0x33, 0xaa, 0x1e, 0x0d, 0xd9, 0x41, 0x18, 0x15, 0x13, 0x07, 0x50, 0x05, 0x13, 0x05, 0x85, - 0x5e, 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x10, 0xf0, 0x1a, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x40, 0x05, 0x93, 0x85, - 0x45, 0x53, 0x68, 0x10, 0xef, 0x40, 0xc0, 0x24, 0x60, 0x10, 0x48, 0x40, 0x01, 0xc5, 0xef, 0x20, 0xa0, 0x7f, 0x48, - 0xc0, 0x31, 0x04, 0x1c, 0x01, 0xe3, 0x99, 0x87, 0xfe, 0x37, 0x55, 0x10, 0x00, 0x1d, 0x46, 0x6c, 0x10, 0x13, 0x05, - 0xc5, 0x5f, 0xef, 0x20, 0x40, 0x42, 0xef, 0xf0, 0x0f, 0xe3, 0x05, 0x45, 0xef, 0x10, 0xd0, 0x02, 0xef, 0x30, 0xa0, - 0x4e, 0xef, 0x30, 0x50, 0x21, 0x01, 0x45, 0xef, 0x30, 0xf0, 0x5d, 0xb7, 0x0a, 0x20, 0x00, 0x93, 0x87, 0x0a, 0x00, - 0x05, 0x6b, 0xb3, 0x8b, 0x67, 0x01, 0xb7, 0x17, 0x20, 0x00, 0x13, 0x8a, 0xc7, 0x07, 0xef, 0x10, 0x40, 0x66, 0xb7, - 0x37, 0x20, 0x00, 0x83, 0xa7, 0x87, 0xf3, 0x63, 0x82, 0x07, 0x10, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0x47, 0xf3, - 0x63, 0x9c, 0xe7, 0x0e, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xc7, 0x07, 0xf3, 0x93, 0x87, 0x07, 0xf3, 0x3e, 0xcc, 0xe3, - 0x1d, 0x07, 0x36, 0x03, 0xa6, 0x0b, 0x07, 0x93, 0x07, 0xf0, 0x07, 0xb7, 0x19, 0x20, 0x00, 0xa3, 0x8c, 0xfb, 0x06, - 0xc1, 0x4c, 0x13, 0x8d, 0x0a, 0x00, 0x93, 0x89, 0x09, 0x00, 0x63, 0xfe, 0xcc, 0x0a, 0x13, 0x04, 0x06, 0xff, 0xef, - 0x10, 0x60, 0x72, 0x01, 0x45, 0xef, 0x30, 0x60, 0x4f, 0x22, 0x86, 0x63, 0xf3, 0x8c, 0x00, 0x41, 0x46, 0x93, 0x85, - 0xfa, 0x4a, 0x76, 0xcf, 0x78, 0x75, 0xcb, 0xc3, 0x0b, 0x1d, 0x9d, 0xb2, 0x59, 0xa8, 0x5e, 0x32, 0x9a, 0xd3, 0x99, - 0xfc, 0xbc, 0x5f, 0x7d, 0x38, 0x13, 0x80, 0xf7, 0x7e, 0x00, 0x1a, 0xd7, 0x14, 0x5f, 0xf0, 0x15, 0x0a, 0x00, 0x68, - 0x10, 0xef, 0x30, 0x20, 0x50, 0xef, 0x10, 0xc0, 0x77, 0xb7, 0x57, 0x10, 0x00, 0x23, 0x8c, 0xa9, 0x06, 0x93, 0x87, - 0x87, 0x58, 0x03, 0xc7, 0x07, 0x00, 0x63, 0x1b, 0x07, 0x12, 0x03, 0xa4, 0x09, 0x07, 0xc1, 0x47, 0xe3, 0xf2, 0x87, - 0xda, 0x01, 0x45, 0xef, 0x30, 0xc0, 0x4b, 0x41, 0x14, 0x22, 0x86, 0x93, 0x85, 0x0a, 0x00, 0x13, 0x85, 0x0a, 0x00, - 0xef, 0x30, 0xa0, 0x4c, 0xb7, 0x1c, 0x20, 0x00, 0x13, 0x85, 0x0c, 0x02, 0xef, 0x30, 0xa0, 0x68, 0xef, 0x30, 0x20, - 0x6d, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x5d, 0x10, 0x00, 0xaa, 0x86, 0x13, 0x06, 0x46, 0x45, 0x93, 0x85, 0xcd, 0x3d, - 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0xf0, 0x49, 0x93, 0x85, 0x0c, 0x02, 0x41, 0x46, 0x33, 0x05, 0x8d, 0x00, 0xef, - 0x00, 0x30, 0x38, 0xaa, 0x8c, 0xc1, 0x47, 0x63, 0x09, 0x05, 0x0e, 0x89, 0x45, 0x13, 0x85, 0xcd, 0x3d, 0xef, 0x00, - 0x50, 0x4f, 0x37, 0x55, 0x10, 0x00, 0x93, 0x07, 0xb0, 0x07, 0x91, 0x45, 0x13, 0x05, 0xc5, 0x3f, 0xa3, 0x8c, 0xf9, - 0x06, 0xef, 0x00, 0xf0, 0x4d, 0xef, 0xe0, 0x9f, 0xf7, 0xef, 0xf0, 0xcf, 0x87, 0xef, 0xf0, 0x4f, 0xc3, 0xef, 0x10, - 0xa0, 0x53, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x17, 0xf5, 0x08, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xc7, 0x07, - 0xf3, 0xc9, 0xe3, 0xef, 0x10, 0xa0, 0x02, 0xe3, 0x15, 0x85, 0x20, 0xd2, 0x47, 0x9c, 0x43, 0x63, 0x94, 0xa7, 0x00, - 0xef, 0x10, 0xc0, 0x18, 0xfa, 0x31, 0xbf, 0x8e, 0xf4, 0x59, 0x4c, 0x65, 0xcd, 0x11, 0x4d, 0x2c, 0xc5, 0x06, 0xe7, - 0x37, 0xcb, 0x54, 0x53, 0xe5, 0xfc, 0x42, 0xb2, 0x11, 0x89, 0xd1, 0xbe, 0xdc, 0x39, 0xa4, 0x9a, 0x1d, 0x9b, 0xc8, - 0x16, 0xb2, 0x47, 0x98, 0x43, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x13, 0xf7, 0x1e, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, - 0x86, 0x4d, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x10, 0x41, 0xef, 0xf0, 0x4f, 0xbe, 0x37, - 0x25, 0x00, 0x08, 0xef, 0x20, 0x70, 0x0d, 0xef, 0xf0, 0x4f, 0xa8, 0xef, 0x20, 0x60, 0x5f, 0xef, 0x10, 0x50, 0x1c, - 0xef, 0x20, 0x30, 0x21, 0xef, 0xe0, 0xff, 0xf3, 0x32, 0x47, 0x37, 0x56, 0x10, 0x00, 0x93, 0x07, 0x50, 0x05, 0x13, - 0x06, 0x46, 0x4e, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, 0x64, 0x1c, 0xc3, 0xef, 0x00, 0x50, 0x3d, 0xef, 0x20, - 0x10, 0x21, 0xef, 0x10, 0x70, 0x48, 0xef, 0x20, 0x20, 0x5f, 0xef, 0x30, 0x90, 0x00, 0xc2, 0x47, 0x98, 0x43, 0x93, - 0x07, 0x50, 0x05, 0xe3, 0x08, 0xf7, 0xe4, 0xad, 0xb9, 0x63, 0x1c, 0xe5, 0x00, 0x83, 0xc7, 0x17, 0x00, 0xbd, 0x8b, - 0xe3, 0x82, 0x07, 0xec, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0xa0, 0x59, 0x65, 0xbd, 0x91, 0x07, 0x75, 0xb5, 0x03, - 0xa4, 0x09, 0x07, 0xe3, 0xe4, 0x87, 0x16, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0xc5, 0x3f, 0xef, 0x00, - 0xb0, 0x3f, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x3f, 0x95, 0x45, 0xef, 0x00, 0xd0, 0x3e, 0x13, 0x05, 0xf0, - 0x07, 0x39, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xf5, 0x94, 0x43, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, - 0x10, 0x00, 0x13, 0x87, 0x16, 0x00, 0x98, 0xc3, 0xfa, 0x17, 0xa7, 0x05, 0x06, 0x4d, 0x7e, 0xa8, 0x78, 0x15, 0x6f, - 0xa1, 0x25, 0xe1, 0x63, 0xc0, 0xb0, 0x49, 0x09, 0xd5, 0xd2, 0xe8, 0x56, 0x1c, 0xdc, 0x2d, 0x4f, 0x66, 0xdc, 0xd8, - 0x94, 0x1b, 0xf0, 0xa0, 0x17, 0x03, 0xc7, 0x89, 0x07, 0xa2, 0x87, 0x13, 0x06, 0x46, 0x46, 0x93, 0x85, 0xc5, 0x3f, - 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x30, 0x34, 0xb7, 0x17, 0x20, 0x00, 0x13, 0x85, 0xc7, 0x07, 0x3d, 0x46, 0x81, - 0x45, 0xef, 0x30, 0xd0, 0x7f, 0x83, 0xc7, 0x89, 0x07, 0x13, 0x07, 0x20, 0x04, 0x63, 0x80, 0xe7, 0x56, 0x63, 0x69, - 0xf7, 0x16, 0x13, 0x07, 0x10, 0x02, 0x63, 0x89, 0xe7, 0x3e, 0x63, 0x60, 0xf7, 0x08, 0x45, 0x47, 0x63, 0x82, 0xe7, - 0x30, 0x63, 0x69, 0xf7, 0x02, 0x05, 0x47, 0x63, 0x85, 0xe7, 0x24, 0x41, 0x47, 0x63, 0x8d, 0xe7, 0x26, 0x89, 0x49, - 0x3d, 0xa3, 0x93, 0x87, 0x07, 0xfa, 0x93, 0xf7, 0xf7, 0x0f, 0x45, 0x47, 0xe3, 0x69, 0xf7, 0xfe, 0x37, 0x57, 0x10, - 0x00, 0x8a, 0x07, 0x13, 0x07, 0xc7, 0x4e, 0xba, 0x97, 0x9c, 0x43, 0x82, 0x87, 0x49, 0x47, 0x63, 0x82, 0xe7, 0x34, - 0x13, 0x07, 0x00, 0x02, 0xe3, 0x9a, 0xe7, 0xfc, 0x42, 0x04, 0x41, 0x80, 0xa1, 0x47, 0xe3, 0x13, 0xf4, 0xf4, 0x83, - 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x81, 0x63, 0x97, 0x07, 0x54, 0x93, 0x07, - 0xf0, 0x1f, 0x63, 0xe3, 0xa7, 0x54, 0x83, 0x25, 0x4d, 0x00, 0xef, 0x10, 0x90, 0x1e, 0x93, 0x07, 0xa0, 0x0a, 0x63, - 0x1b, 0xf5, 0x52, 0xad, 0xa6, 0x13, 0x07, 0x10, 0x03, 0x63, 0x86, 0xe7, 0x3a, 0x63, 0x6f, 0xf7, 0x04, 0x13, 0x07, - 0x20, 0x02, 0x63, 0x87, 0xe7, 0x38, 0x13, 0x07, 0x00, 0x03, 0xe3, 0x91, 0xfa, 0xbb, 0x57, 0x46, 0x61, 0xf1, 0xd6, - 0x72, 0xeb, 0xc2, 0xe3, 0x87, 0xfe, 0x58, 0x11, 0x70, 0x8e, 0x60, 0x1b, 0x6b, 0x0b, 0x3e, 0x42, 0x1b, 0x31, 0x4c, - 0xce, 0x9d, 0xf4, 0x5a, 0x82, 0x39, 0x20, 0x78, 0x18, 0xe7, 0xf8, 0x42, 0x04, 0x41, 0x80, 0x91, 0x47, 0xe3, 0x1a, - 0xf4, 0xee, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x97, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x83, 0x63, 0x9e, 0x07, - 0x4e, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xea, 0xe7, 0x4e, 0x03, 0x45, 0x3d, 0x00, 0xfd, 0x47, 0x63, 0xe5, 0xa7, 0x4e, - 0x93, 0x15, 0x25, 0x00, 0x0d, 0x81, 0x93, 0xf7, 0xc5, 0x01, 0x3a, 0x95, 0xbd, 0x45, 0xb3, 0x95, 0xf5, 0x00, 0x0a, - 0x05, 0x93, 0xc5, 0xf5, 0xff, 0x5a, 0x95, 0x05, 0xa4, 0x13, 0x07, 0x00, 0x04, 0x63, 0x8f, 0xe7, 0x3a, 0x13, 0x07, - 0x10, 0x04, 0xe3, 0x94, 0xe7, 0xf2, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x1d, 0xf4, 0xe8, 0x83, 0x26, 0x0d, - 0x00, 0x93, 0x07, 0xf0, 0x1f, 0xa1, 0x82, 0xc2, 0x06, 0xc1, 0x82, 0x63, 0xe1, 0xd7, 0x4a, 0x37, 0x56, 0x10, 0x00, - 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x86, 0x4b, 0x93, 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x10, - 0x1f, 0xef, 0x10, 0x50, 0x57, 0xef, 0x20, 0x00, 0x75, 0x83, 0x27, 0x0d, 0x00, 0x91, 0x65, 0x93, 0x85, 0x05, 0x20, - 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, 0xa6, 0x07, 0x37, 0x15, 0x20, 0x00, 0xbe, 0x95, 0x13, 0x05, 0x05, 0x08, 0xef, - 0x10, 0x30, 0x19, 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x74, 0x93, 0x07, 0xc0, 0x1b, 0xe3, 0xe0, 0x87, 0xa8, 0x93, 0x05, - 0x44, 0x00, 0x29, 0xac, 0x13, 0x07, 0x10, 0x07, 0x63, 0x69, 0xf7, 0x02, 0x13, 0x07, 0xf0, 0x05, 0xfa, 0x8a, 0x29, - 0x7b, 0xdd, 0xde, 0x5b, 0x79, 0xb8, 0x49, 0x0a, 0x0c, 0x22, 0xe2, 0x6f, 0xe0, 0xc5, 0x95, 0xa2, 0x1d, 0x56, 0x4f, - 0xf4, 0x3a, 0x5f, 0xfa, 0x6b, 0xbc, 0xd9, 0xfe, 0x7e, 0x16, 0x4f, 0x50, 0x19, 0xe3, 0x66, 0xf7, 0xea, 0x13, 0x07, - 0x00, 0x05, 0xe3, 0x90, 0xe7, 0xea, 0x42, 0x04, 0x41, 0x80, 0x89, 0x47, 0xe3, 0x19, 0xf4, 0xe0, 0x03, 0x44, 0x1d, - 0x00, 0x37, 0x15, 0x20, 0x00, 0x13, 0x05, 0x05, 0x08, 0xa2, 0x85, 0xef, 0xe0, 0x1f, 0xd7, 0xd9, 0xb7, 0x13, 0x07, - 0x20, 0x08, 0x63, 0x8b, 0xe7, 0x6e, 0x63, 0x6d, 0xf7, 0x04, 0x13, 0x07, 0x00, 0x08, 0x63, 0x82, 0xe7, 0x68, 0x13, - 0x07, 0x10, 0x08, 0xe3, 0x93, 0xe7, 0xe6, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x1c, 0xf4, 0xdc, 0x03, 0x45, - 0x1d, 0x00, 0x3d, 0x47, 0x81, 0x47, 0x63, 0x6e, 0xa7, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x47, 0xf5, 0x89, - 0x47, 0x33, 0x57, 0xa7, 0x00, 0x05, 0x8b, 0x01, 0xc7, 0xef, 0xe0, 0x7f, 0xe6, 0xaa, 0x87, 0xfd, 0x17, 0x09, 0x47, - 0x63, 0x63, 0xf7, 0x3c, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x72, 0xaa, 0x97, 0x83, 0xc9, 0x07, 0x00, 0x1d, - 0xaa, 0x13, 0x07, 0x00, 0x09, 0xe3, 0x9c, 0xe7, 0xe0, 0x93, 0x17, 0x04, 0x01, 0xc1, 0x83, 0x13, 0x07, 0x30, 0x02, - 0xe3, 0x73, 0xf7, 0xd8, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0xbe, 0x86, 0x13, 0x06, 0x06, 0x4c, 0x93, - 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0xd0, 0x0e, 0xef, 0x20, 0xa0, 0x0d, 0xef, 0x20, 0xc0, 0x64, - 0xef, 0x20, 0x20, 0x0e, 0x2a, 0x84, 0xef, 0x20, 0x40, 0x0d, 0xef, 0x20, 0x00, 0x66, 0x93, 0x07, 0xa0, 0x0a, 0x63, - 0x14, 0xfa, 0x33, 0x70, 0x2d, 0x9c, 0xff, 0x0d, 0xdf, 0x20, 0xd3, 0xf8, 0xc7, 0x95, 0x5d, 0xf8, 0xb3, 0x5f, 0x58, - 0xee, 0x56, 0x9f, 0x6f, 0x9d, 0x87, 0x90, 0x41, 0x8d, 0xb2, 0x11, 0x85, 0xc1, 0xdd, 0x05, 0x28, 0x1a, 0xf4, 0x36, - 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0x00, 0x2c, 0x93, 0x07, 0x40, 0x02, 0x81, 0xa3, 0x93, 0x19, 0x04, 0x01, 0x93, - 0xd9, 0x09, 0x01, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0xce, 0x86, 0x13, 0x06, 0x06, 0x4a, 0x93, 0x85, - 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0xf0, 0x09, 0x93, 0x07, 0x1b, 0x00, 0xe3, 0xeb, 0x37, 0xd1, 0xce, - 0x85, 0x13, 0x85, 0x0a, 0x00, 0xef, 0xf0, 0x4f, 0x8e, 0xa9, 0xaa, 0x42, 0x04, 0x41, 0x80, 0x93, 0x07, 0x40, 0x02, - 0xe3, 0x1f, 0xf4, 0xce, 0x03, 0x25, 0x0d, 0x00, 0x0d, 0x44, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0x64, 0xa4, - 0x30, 0xef, 0xf0, 0x8f, 0xae, 0xd5, 0x47, 0x63, 0x1f, 0xf5, 0x2e, 0x83, 0x29, 0x0d, 0x00, 0x93, 0xd9, 0x89, 0x00, - 0xc2, 0x09, 0x93, 0xd9, 0x09, 0x01, 0xe3, 0x6c, 0x34, 0x91, 0x13, 0x84, 0x09, 0x0e, 0x16, 0x04, 0x91, 0x4c, 0x71, - 0x14, 0x93, 0x0d, 0x40, 0x02, 0xb3, 0x05, 0x9d, 0x01, 0x11, 0x46, 0x68, 0x10, 0xef, 0x30, 0x70, 0x4c, 0xb2, 0x55, - 0x33, 0x05, 0x94, 0x01, 0x91, 0x0c, 0xef, 0x20, 0x20, 0x33, 0xe3, 0x94, 0xbc, 0xff, 0x09, 0x65, 0x8a, 0x09, 0xb7, - 0xf5, 0xf0, 0xf0, 0x13, 0x05, 0x05, 0xbf, 0x93, 0x85, 0x05, 0x0f, 0x4e, 0x95, 0xef, 0x20, 0x80, 0x31, 0xc5, 0xa0, - 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x13, 0xf4, 0xc8, 0x03, 0x25, 0x0d, 0x00, 0x0d, 0x44, 0x21, 0x81, 0x42, - 0x05, 0x41, 0x81, 0x63, 0x68, 0xfa, 0xd1, 0xe1, 0x9b, 0x97, 0x17, 0x68, 0xef, 0xb6, 0x82, 0xbc, 0xa0, 0x2b, 0x8d, - 0x94, 0xbb, 0x89, 0xe9, 0x31, 0x9c, 0xe3, 0x3a, 0x5b, 0xa3, 0xa6, 0xca, 0x01, 0xdb, 0x04, 0xd0, 0x41, 0x88, 0x2c, - 0x00, 0x1b, 0xa4, 0x28, 0xef, 0xf0, 0x0f, 0xa7, 0x93, 0x07, 0x30, 0x0c, 0x63, 0x08, 0xf5, 0x00, 0xaa, 0x89, 0x93, - 0x07, 0x00, 0x08, 0x63, 0x9a, 0xf9, 0x20, 0xb1, 0xb9, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, - 0xe3, 0x6b, 0xf4, 0x88, 0x93, 0x87, 0x07, 0x0e, 0x13, 0x94, 0x57, 0x00, 0x93, 0x09, 0x00, 0x02, 0x33, 0x05, 0x94, - 0x01, 0xef, 0x20, 0x20, 0x20, 0xb7, 0x17, 0x20, 0x00, 0x93, 0x87, 0x07, 0x08, 0x2a, 0xd6, 0x11, 0x46, 0x33, 0x85, - 0x97, 0x01, 0x6c, 0x10, 0x91, 0x0c, 0xef, 0x30, 0x30, 0x43, 0xe3, 0x90, 0x3c, 0xff, 0x93, 0x05, 0x40, 0x02, 0x52, - 0x85, 0x29, 0xb7, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x17, 0xf4, 0xc0, 0x03, 0x25, 0x0d, 0x00, 0x21, 0x81, - 0x42, 0x05, 0x41, 0x81, 0x63, 0x6d, 0xa4, 0x20, 0xef, 0xf0, 0xaf, 0x9f, 0xd5, 0x47, 0x63, 0x08, 0xf5, 0x20, 0xd9, - 0x47, 0x63, 0x01, 0xf5, 0x04, 0x83, 0x29, 0x0d, 0x00, 0x93, 0xd9, 0x89, 0x00, 0xc2, 0x09, 0x93, 0xd9, 0x09, 0x01, - 0xe3, 0x62, 0x34, 0x83, 0x89, 0x67, 0x13, 0x95, 0x29, 0x00, 0x93, 0x87, 0x07, 0xbf, 0x81, 0x45, 0x3e, 0x95, 0x93, - 0x89, 0x09, 0x0e, 0xef, 0x20, 0xe0, 0x24, 0x96, 0x09, 0x13, 0x04, 0x00, 0x02, 0x33, 0x85, 0x99, 0x01, 0x81, 0x45, - 0x91, 0x0c, 0xef, 0x20, 0xc0, 0x23, 0xe3, 0x9a, 0x8c, 0xfe, 0x93, 0x09, 0x30, 0x0c, 0xb9, 0xaa, 0x42, 0x04, 0x41, - 0x80, 0x8d, 0x47, 0xe3, 0x11, 0xf4, 0xba, 0x83, 0x27, 0xfa, 0x03, 0x45, 0x33, 0x20, 0x5d, 0x9d, 0x33, 0x5e, 0x67, - 0x9f, 0xa6, 0xd8, 0x4b, 0xd3, 0xbd, 0x1e, 0x12, 0x27, 0xef, 0x53, 0xa9, 0xe8, 0x82, 0x1f, 0x29, 0x8f, 0xcd, 0xee, - 0x20, 0xd5, 0x28, 0x85, 0xd8, 0x1b, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x81, 0x63, - 0x95, 0x07, 0x1a, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe1, 0xa7, 0x1a, 0xef, 0x10, 0x60, 0x5b, 0x23, 0x22, 0xaa, 0x00, - 0xa1, 0x45, 0x8d, 0xb7, 0x42, 0x04, 0x41, 0x80, 0x85, 0x47, 0x01, 0x45, 0xe3, 0x18, 0xf4, 0xb6, 0xef, 0x10, 0x30, - 0x24, 0x6d, 0xbf, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x10, 0xf4, 0xb6, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, - 0x13, 0x94, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x80, 0x63, 0x94, 0x07, 0x16, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe0, 0x87, - 0x16, 0x0a, 0x04, 0x33, 0x05, 0x64, 0x01, 0xef, 0x20, 0xe0, 0x17, 0x93, 0xf4, 0x04, 0xf0, 0xc9, 0x8c, 0x13, 0x05, - 0x4b, 0x00, 0x22, 0x95, 0xef, 0x20, 0xe0, 0x16, 0xc1, 0x77, 0x93, 0x87, 0xf7, 0x0f, 0xfd, 0x8c, 0x22, 0x05, 0xc9, - 0x8c, 0x13, 0x05, 0x8b, 0x00, 0x22, 0x95, 0xef, 0x20, 0x80, 0x15, 0xb7, 0x07, 0x01, 0xff, 0xfd, 0x17, 0x42, 0x05, - 0xfd, 0x8c, 0xc9, 0x8c, 0x13, 0x05, 0xcb, 0x00, 0x22, 0x95, 0xef, 0x20, 0x20, 0x14, 0xa2, 0x04, 0x62, 0x05, 0xa1, - 0x80, 0xc9, 0x8c, 0x23, 0x22, 0x9a, 0x00, 0x95, 0xbf, 0x93, 0x07, 0xb4, 0xff, 0xc2, 0x07, 0xc1, 0x83, 0x13, 0x07, - 0xb0, 0x1b, 0xe3, 0x61, 0xf7, 0xae, 0x83, 0x26, 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0x93, 0x09, 0xc0, 0x03, 0xa1, - 0x82, 0xc2, 0x06, 0xc1, 0x82, 0x63, 0xe0, 0xd7, 0x08, 0x37, 0x56, 0x10, 0x00, 0xfa, 0x4a, 0x99, 0x46, 0x9c, 0x37, - 0xa3, 0xdc, 0xa6, 0x39, 0xdd, 0x41, 0x45, 0x19, 0xd8, 0xa3, 0xe9, 0x2c, 0x60, 0x1c, 0xfb, 0xe9, 0xa4, 0xf5, 0xa0, - 0x9f, 0x91, 0xa8, 0x5b, 0xc9, 0xf1, 0x98, 0x0b, 0xb0, 0x1c, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x06, 0x4b, 0x93, - 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x40, 0x63, 0x03, 0x25, 0x0d, 0x00, 0x91, 0x69, 0x93, 0x89, - 0x09, 0x20, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x26, 0x05, 0x4e, 0x95, 0xef, 0x10, 0x30, 0x13, 0x93, 0x07, 0xa0, - 0x0a, 0xaa, 0x8c, 0x63, 0x12, 0xf5, 0x04, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0xbf, 0x9f, 0xef, 0x20, 0xe0, 0x36, - 0x83, 0x27, 0x0d, 0x00, 0x42, 0x04, 0x41, 0x80, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, 0xa6, 0x07, 0xb7, 0x05, 0x20, - 0x00, 0x13, 0x06, 0xc4, 0xff, 0x33, 0x85, 0x37, 0x01, 0x74, 0x10, 0x93, 0x85, 0x45, 0x00, 0xef, 0x10, 0xf0, 0x02, - 0x2a, 0x84, 0x93, 0x09, 0x30, 0x0c, 0xef, 0x20, 0x00, 0x36, 0x63, 0x03, 0x94, 0x01, 0xc1, 0x49, 0x13, 0xf5, 0xf9, - 0x0f, 0xe5, 0xae, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x10, 0xf4, 0xa4, 0x03, 0x25, 0x0d, 0x00, 0x93, 0x07, - 0xf0, 0x1f, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0xe4, 0xa7, 0x04, 0x91, 0x67, 0x26, 0x05, 0x93, 0x87, 0x07, - 0x20, 0x3e, 0x95, 0x55, 0xbd, 0x42, 0x04, 0x41, 0x80, 0x91, 0x47, 0xe3, 0x1c, 0xf4, 0xa0, 0xc1, 0x45, 0x68, 0x10, - 0xef, 0xe0, 0x1f, 0x98, 0x68, 0x10, 0xef, 0x10, 0x80, 0x7c, 0xef, 0x30, 0xa0, 0x20, 0xef, 0x20, 0xa0, 0x2e, 0x91, - 0x45, 0x13, 0x05, 0x00, 0x06, 0xef, 0x30, 0xc0, 0x42, 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x2f, 0x93, 0x07, 0xfa, 0x2c, - 0x94, 0x85, 0x95, 0xbe, 0xbc, 0x46, 0x32, 0x05, 0xf9, 0xdb, 0xf9, 0x27, 0xa4, 0x26, 0xe9, 0x8b, 0xe1, 0xf3, 0x66, - 0x23, 0xcb, 0x7b, 0xbb, 0xdc, 0xa0, 0xbf, 0xa9, 0x42, 0xeb, 0x91, 0xab, 0x88, 0x1d, 0xa0, 0x0a, 0xe3, 0x0e, 0xf4, - 0xe2, 0x93, 0x09, 0xc0, 0x03, 0x59, 0xbf, 0x42, 0x04, 0x41, 0x80, 0x93, 0x07, 0x00, 0x03, 0xe3, 0x1c, 0xf4, 0x9c, - 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0x1f, 0x94, 0x68, 0x10, 0xef, 0x10, 0x80, 0x78, 0xef, 0x30, 0xa0, 0x1c, 0xef, - 0x20, 0xa0, 0x2a, 0x93, 0x05, 0x00, 0x03, 0x13, 0x05, 0x10, 0x06, 0x7d, 0xbf, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, - 0xe3, 0x17, 0xf4, 0x9a, 0xef, 0x30, 0xe0, 0x1a, 0xef, 0x20, 0xe0, 0x28, 0x8d, 0x45, 0x13, 0x05, 0x20, 0x06, 0xef, - 0x30, 0x00, 0x3d, 0x2a, 0x84, 0xef, 0x20, 0x00, 0x2a, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x14, 0xf4, 0xfa, 0xef, 0xe0, - 0x7f, 0xf0, 0x05, 0xb3, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x1f, 0xf4, 0x96, 0xef, 0x30, 0xe0, 0x17, 0x8d, - 0x45, 0x13, 0x05, 0x30, 0x06, 0xef, 0x30, 0x40, 0x3a, 0xb1, 0xb4, 0x42, 0x04, 0x41, 0x80, 0x93, 0x07, 0x00, 0x03, - 0xe3, 0x11, 0xf4, 0x96, 0xef, 0x30, 0x20, 0x16, 0xef, 0x20, 0x50, 0x6f, 0xb7, 0x15, 0x20, 0x00, 0x2a, 0xd6, 0x13, - 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, 0xef, 0x30, 0x60, 0x26, 0x11, 0x46, 0x6c, 0x10, - 0x13, 0x05, 0x00, 0x0c, 0xef, 0x30, 0xa0, 0x25, 0xef, 0x20, 0xc0, 0x21, 0x93, 0x05, 0x00, 0x03, 0x13, 0x05, 0x00, - 0x07, 0xef, 0x30, 0xc0, 0x35, 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x22, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1a, 0xf4, 0xf2, - 0xef, 0xe0, 0xfa, 0x0c, 0x14, 0xa4, 0x33, 0x93, 0x2e, 0xdb, 0xa3, 0x9f, 0x89, 0x46, 0x26, 0xd5, 0xe6, 0x56, 0xc9, - 0x2f, 0x9b, 0x99, 0xaa, 0x99, 0x9d, 0xed, 0x7d, 0x6c, 0xd4, 0xee, 0x7c, 0xa4, 0xd5, 0x99, 0xea, 0x60, 0x1e, 0x3f, - 0xe9, 0x75, 0xb1, 0x93, 0x17, 0x04, 0x01, 0xc1, 0x83, 0x3d, 0x47, 0xe3, 0x74, 0xf7, 0x90, 0xef, 0x30, 0x80, 0x10, - 0xef, 0x20, 0xb0, 0x69, 0xaa, 0x8c, 0x01, 0x45, 0xef, 0x20, 0xd0, 0x45, 0x41, 0x46, 0x93, 0x85, 0x0a, 0x00, 0x01, - 0x45, 0xef, 0x20, 0xf0, 0x46, 0xef, 0x20, 0x00, 0x1d, 0xb7, 0x15, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, - 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, 0x66, 0xd6, 0xef, 0x30, 0x40, 0x1f, 0x11, 0x46, 0x6c, 0x10, 0x13, 0x05, 0x00, - 0x0c, 0xef, 0x30, 0x80, 0x1e, 0x85, 0x45, 0x13, 0x05, 0x10, 0x04, 0xef, 0x30, 0x00, 0x2f, 0x93, 0x07, 0xa0, 0x0a, - 0xaa, 0x8c, 0x63, 0x19, 0xf5, 0x00, 0x81, 0x45, 0x13, 0x05, 0x20, 0x04, 0xef, 0x30, 0xc0, 0x2d, 0x63, 0x05, 0x95, - 0x01, 0xef, 0x20, 0xa0, 0x1a, 0x5d, 0xbd, 0x42, 0x04, 0x41, 0x80, 0x93, 0x0d, 0x04, 0xff, 0xef, 0x20, 0xc0, 0x19, - 0xee, 0x8c, 0x22, 0x9d, 0x93, 0x07, 0x00, 0x09, 0xb3, 0x05, 0x9d, 0x41, 0x63, 0xe5, 0x97, 0x09, 0x66, 0x86, 0x01, - 0x45, 0xef, 0x20, 0xd0, 0x3f, 0xe6, 0x85, 0x13, 0x05, 0x40, 0x04, 0xef, 0x30, 0x40, 0x2a, 0x13, 0x07, 0xa0, 0x0a, - 0xe3, 0x11, 0xe5, 0xe8, 0x2a, 0xce, 0x81, 0x45, 0x13, 0x05, 0x50, 0x04, 0xef, 0x30, 0x00, 0x29, 0xf2, 0x47, 0xaa, - 0x8c, 0xe3, 0x17, 0xf5, 0xe6, 0x01, 0x45, 0xef, 0x20, 0x30, 0x3b, 0x93, 0x85, 0x0a, 0x00, 0x41, 0x46, 0x01, 0x45, - 0xef, 0x20, 0x50, 0x3c, 0x93, 0x07, 0xfa, 0x21, 0xf4, 0x65, 0xd1, 0xab, 0xb2, 0x5f, 0x75, 0x8a, 0x05, 0x69, 0x14, - 0x53, 0xeb, 0xee, 0x9a, 0x9a, 0x91, 0x1b, 0x59, 0x12, 0xd0, 0x01, 0x82, 0xea, 0x19, 0xb4, 0xd9, 0x27, 0x85, 0x86, - 0x14, 0x38, 0x1f, 0xf0, 0x03, 0xb7, 0x05, 0x20, 0x00, 0x63, 0xe1, 0xb7, 0x07, 0x93, 0x85, 0x05, 0x01, 0x01, 0x45, - 0x6e, 0x86, 0xef, 0x20, 0xd0, 0x3a, 0xee, 0x85, 0x13, 0x05, 0x60, 0x04, 0xef, 0x30, 0x40, 0x25, 0xe3, 0x1b, 0x95, - 0xe3, 0x81, 0x45, 0x13, 0x05, 0xa0, 0x04, 0xef, 0x30, 0x60, 0x24, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x12, 0xf5, 0xe2, - 0xef, 0x20, 0x10, 0x58, 0x93, 0x07, 0x00, 0x05, 0x23, 0xaa, 0xf9, 0x06, 0xb1, 0xb1, 0x13, 0x06, 0x00, 0x09, 0x01, - 0x45, 0xef, 0x20, 0x50, 0x37, 0x93, 0x05, 0x00, 0x09, 0x13, 0x05, 0x30, 0x04, 0xef, 0x30, 0xa0, 0x21, 0x13, 0x07, - 0xa0, 0x0a, 0xe3, 0x1c, 0xe5, 0xde, 0x93, 0x8c, 0x0c, 0xf7, 0xb1, 0xb7, 0x93, 0x85, 0x05, 0x01, 0x01, 0x45, 0x13, - 0x06, 0x00, 0x04, 0xef, 0x20, 0xd0, 0x34, 0x93, 0x05, 0x00, 0x04, 0x13, 0x05, 0x70, 0x04, 0xef, 0x30, 0x20, 0x1f, - 0xe3, 0x1a, 0x95, 0xdd, 0x13, 0x04, 0x04, 0xfb, 0x93, 0x0c, 0x00, 0x08, 0x93, 0x0d, 0xa0, 0x0a, 0xb3, 0x05, 0x8d, - 0x40, 0x63, 0xe0, 0x8c, 0x02, 0x22, 0x86, 0x01, 0x45, 0xef, 0x20, 0x10, 0x32, 0xa2, 0x85, 0x13, 0x05, 0x90, 0x04, - 0xef, 0x30, 0x80, 0x1c, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x13, 0xf5, 0xda, 0x85, 0xbf, 0x01, 0x45, 0x13, 0x06, 0x00, - 0x08, 0xef, 0x20, 0x30, 0x30, 0x93, 0x05, 0x00, 0x08, 0x13, 0x05, 0x80, 0x04, 0xef, 0x30, 0x80, 0x1a, 0xe3, 0x15, - 0xb5, 0xd9, 0x13, 0x04, 0x04, 0xf8, 0x7d, 0xbf, 0x42, 0x04, 0xfa, 0x97, 0x76, 0x47, 0x17, 0xcf, 0xa6, 0x2f, 0x96, - 0xc8, 0xad, 0x25, 0xe4, 0x10, 0x25, 0x9e, 0xb3, 0xaf, 0x9d, 0xfc, 0x36, 0x13, 0xb4, 0xa0, 0xf9, 0xfe, 0xe4, 0x13, - 0xc9, 0x39, 0x8e, 0x86, 0xe3, 0x10, 0x20, 0x41, 0x80, 0xa1, 0x47, 0x63, 0x10, 0xf4, 0xf6, 0x03, 0x44, 0x1d, 0x00, - 0xbd, 0x47, 0xe3, 0xe8, 0x87, 0xd6, 0x83, 0x2c, 0x4d, 0x00, 0xfd, 0x57, 0xe3, 0x83, 0xfc, 0xd6, 0x93, 0x19, 0xa4, - 0x00, 0x13, 0x85, 0x09, 0x40, 0xef, 0xe0, 0x8f, 0xe6, 0x13, 0x07, 0xa0, 0x0a, 0x2a, 0x8d, 0xe3, 0x18, 0xe5, 0xd4, - 0x93, 0x89, 0x09, 0x20, 0x4e, 0x85, 0xef, 0xe0, 0x4f, 0xe5, 0xaa, 0x8d, 0xe3, 0x10, 0xa5, 0xd5, 0xe6, 0x85, 0x4e, - 0x85, 0xef, 0x10, 0x60, 0x1b, 0xe3, 0x1a, 0xb5, 0xd3, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf5, 0x85, 0x47, - 0x33, 0x94, 0x87, 0x00, 0x1c, 0x43, 0x5d, 0x8c, 0x00, 0xc3, 0x91, 0xbe, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0x63, - 0x1d, 0xf4, 0xee, 0x83, 0x45, 0x1d, 0x00, 0xbd, 0x47, 0xe3, 0xe5, 0xb7, 0xd0, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, - 0x47, 0xf5, 0xd1, 0x49, 0xb3, 0xd7, 0xb7, 0x00, 0x85, 0x8b, 0xe3, 0x88, 0x07, 0xc8, 0x37, 0x15, 0x20, 0x00, 0x13, - 0x05, 0x05, 0x08, 0xef, 0xe0, 0x6f, 0xeb, 0x85, 0x47, 0xe3, 0x07, 0xf5, 0xb4, 0x89, 0x47, 0xe3, 0x0c, 0xf5, 0xc6, - 0xe9, 0xb9, 0xef, 0x10, 0x90, 0x43, 0xef, 0xe0, 0x8f, 0xd8, 0x6f, 0xf0, 0xef, 0xe6, 0xef, 0x00, 0xc0, 0x6f, 0x6f, - 0xf0, 0xef, 0xe6, 0xef, 0x00, 0x30, 0x4e, 0x41, 0x14, 0xaa, 0x86, 0x63, 0x0b, 0x05, 0xea, 0x8d, 0x45, 0x13, 0x85, - 0xcd, 0x3d, 0x36, 0xce, 0x71, 0x24, 0xf2, 0x46, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0xfa, 0xfa, 0xed, 0x0e, 0x25, - 0x97, 0x1a, 0x14, 0x04, 0xa4, 0xbd, 0xd2, 0x3a, 0x3a, 0x9f, 0xe3, 0x8b, 0x67, 0x47, 0xe8, 0x6a, 0xdc, 0x29, 0x81, - 0x3b, 0x50, 0x99, 0x56, 0xc0, 0x95, 0x76, 0x28, 0x2b, 0xe8, 0x20, 0xc6, 0x45, 0x93, 0x85, 0xcd, 0x3d, 0x13, 0x05, - 0x49, 0x64, 0x09, 0x24, 0xf2, 0x46, 0x09, 0x47, 0x85, 0x47, 0x63, 0x83, 0xe6, 0x00, 0x89, 0x47, 0x83, 0xc6, 0x89, - 0x07, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x22, 0x87, 0x13, 0x06, 0xc6, 0x47, 0x93, 0x85, 0xc5, 0x3f, - 0x13, 0x05, 0x49, 0x64, 0xa3, 0x8c, 0xf9, 0x06, 0xd9, 0x2a, 0xef, 0xe0, 0x8f, 0xce, 0xef, 0xe0, 0x8f, 0xff, 0x62, - 0x47, 0x85, 0x47, 0x23, 0x00, 0xf7, 0x00, 0xef, 0x00, 0xe0, 0x5a, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x11, - 0xf5, 0xd6, 0x25, 0x29, 0x63, 0x1e, 0x85, 0xd4, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xf4, 0xb1, 0xeb, 0x83, - 0xa7, 0x4b, 0x07, 0x13, 0x07, 0xfb, 0x00, 0xfd, 0x17, 0x63, 0x64, 0xf7, 0x04, 0x05, 0x45, 0xef, 0x20, 0xb0, 0x17, - 0x03, 0xa6, 0x4b, 0x07, 0xb7, 0x09, 0x20, 0x00, 0x93, 0x85, 0x09, 0x00, 0x13, 0x85, 0x09, 0x00, 0xef, 0x20, 0xf0, - 0x25, 0x37, 0x14, 0x20, 0x00, 0x13, 0x05, 0x04, 0x02, 0xef, 0x20, 0x50, 0x34, 0x03, 0xa5, 0x4b, 0x07, 0x93, 0x87, - 0x09, 0x00, 0x41, 0x46, 0x3e, 0x95, 0x93, 0x05, 0x04, 0x02, 0xef, 0x30, 0x00, 0x5f, 0x83, 0xa7, 0x4b, 0x07, 0xc1, - 0x07, 0x23, 0xaa, 0xfb, 0x06, 0xef, 0x00, 0xf0, 0x1b, 0x13, 0x04, 0xa0, 0x0a, 0x63, 0x0a, 0x85, 0xce, 0xef, 0xe0, - 0x8f, 0xfe, 0x63, 0x16, 0x85, 0xce, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0xfa, - 0xee, 0xcd, 0x72, 0xe8, 0x11, 0xe1, 0x86, 0x9a, 0x0d, 0x80, 0x99, 0x72, 0x80, 0xf7, 0x48, 0xdd, 0x8d, 0xda, 0xa6, - 0xcc, 0x34, 0x93, 0x16, 0x5a, 0x6e, 0x0f, 0xb1, 0xa0, 0x8f, 0xfb, 0x20, 0xf9, 0xc0, 0x21, 0x13, 0x06, 0x06, 0x4d, - 0x93, 0x85, 0xc5, 0x3f, 0x13, 0x05, 0x45, 0x40, 0x25, 0x22, 0xef, 0xe0, 0x2f, 0xb7, 0xef, 0x20, 0x70, 0x32, 0xef, - 0x00, 0xb0, 0x3a, 0xef, 0x00, 0xb0, 0x31, 0xef, 0xe0, 0xaf, 0xf9, 0x6f, 0xf0, 0xaf, 0xcb, 0x2a, 0x87, 0x81, 0x47, - 0x01, 0x45, 0x63, 0x93, 0xc7, 0x00, 0x82, 0x80, 0xb3, 0x06, 0xf7, 0x00, 0x33, 0x88, 0xf5, 0x00, 0x83, 0xc6, 0x06, - 0x00, 0x03, 0x48, 0x08, 0x00, 0x85, 0x07, 0xb3, 0xc6, 0x06, 0x01, 0x55, 0x8d, 0x13, 0x75, 0xf5, 0x0f, 0xf9, 0xbf, - 0xb7, 0x37, 0x20, 0x00, 0x37, 0x37, 0x20, 0x00, 0x03, 0xa8, 0xc7, 0xf5, 0x83, 0x27, 0x87, 0xf5, 0xaa, 0x86, 0x13, - 0x07, 0x87, 0xf5, 0x01, 0x45, 0x63, 0x13, 0xf8, 0x00, 0x82, 0x80, 0x37, 0x26, 0x20, 0x00, 0x13, 0x06, 0xc6, 0x08, - 0x93, 0x08, 0xf0, 0x7f, 0x63, 0x01, 0xb5, 0x02, 0x33, 0x0e, 0xf6, 0x00, 0x03, 0x4e, 0x0e, 0x00, 0x05, 0x05, 0x33, - 0x83, 0xa6, 0x00, 0xa3, 0x0f, 0xc3, 0xff, 0x85, 0x07, 0x63, 0xf3, 0xf8, 0x00, 0x81, 0x47, 0xe3, 0x11, 0xf8, 0xfe, - 0x1c, 0xc3, 0x82, 0x80, 0xb7, 0x36, 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x86, 0xf5, 0x83, 0xa7, 0xc7, - 0xf5, 0x93, 0x86, 0x86, 0xf5, 0x33, 0x87, 0xe7, 0x40, 0x63, 0x56, 0x07, 0x00, 0x05, 0x66, 0x13, 0x06, 0x06, 0x80, - 0x32, 0x97, 0x63, 0x5b, 0xe5, 0x00, 0x33, 0x85, 0xa7, 0x40, 0x85, 0x67, 0x93, 0x87, 0x07, 0x80, 0x63, 0xf3, 0xa7, - 0x00, 0x3e, 0x95, 0xfa, 0x15, 0xcc, 0xaa, 0x68, 0x39, 0xfb, 0x6e, 0x69, 0x05, 0x96, 0xc7, 0x2a, 0xd1, 0x84, 0x5c, - 0xfb, 0xc6, 0xdd, 0x36, 0x93, 0x9a, 0x83, 0x7c, 0x41, 0xab, 0x77, 0xf6, 0x79, 0xea, 0xad, 0x86, 0x44, 0x98, 0x22, - 0x88, 0xc2, 0x82, 0x80, 0xb7, 0x36, 0x20, 0x00, 0x03, 0xa8, 0xc6, 0xf5, 0x13, 0x07, 0xf0, 0x7f, 0x13, 0x86, 0xc6, - 0xf5, 0x93, 0x07, 0x18, 0x00, 0x63, 0x73, 0xf7, 0x00, 0x81, 0x47, 0xb7, 0x36, 0x20, 0x00, 0x83, 0xa8, 0x86, 0xf5, - 0x37, 0x27, 0x20, 0x00, 0x93, 0x85, 0x86, 0xf5, 0x13, 0x07, 0xc7, 0x08, 0x63, 0x9f, 0xf8, 0x00, 0x93, 0x88, 0x17, - 0x80, 0x93, 0x86, 0x17, 0x00, 0x63, 0x93, 0x08, 0x00, 0x81, 0x46, 0x94, 0xc1, 0xba, 0x96, 0x93, 0x05, 0xa0, 0x02, - 0x23, 0x80, 0xb6, 0x00, 0x42, 0x97, 0x23, 0x00, 0xa7, 0x00, 0x1c, 0xc2, 0x82, 0x80, 0x82, 0x80, 0x39, 0x71, 0x22, - 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x06, 0xce, 0x36, 0xd6, 0x3a, 0xd8, 0x3e, 0xda, 0x42, 0xdc, 0x46, 0xde, 0xaa, 0x84, - 0x2e, 0x89, 0x32, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0xdf, 0x96, 0x63, 0x14, 0x09, 0x00, 0xef, 0xe0, 0x5f, 0x96, 0x19, - 0xe0, 0xef, 0xe0, 0xff, 0x95, 0x7c, 0x10, 0x3e, 0xc6, 0xef, 0x30, 0x20, 0x13, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, - 0x13, 0x05, 0x85, 0x60, 0xef, 0x30, 0x20, 0x38, 0x37, 0x55, 0x10, 0x00, 0x4a, 0x86, 0xa6, 0x85, 0x13, 0x05, 0x05, - 0x61, 0xef, 0x30, 0x20, 0x37, 0xb2, 0x45, 0x22, 0x85, 0xef, 0x30, 0x80, 0x33, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, - 0xc5, 0x61, 0xef, 0x30, 0xe0, 0x35, 0xb9, 0x29, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0x21, 0x61, 0x82, - 0x80, 0xae, 0x86, 0x37, 0x56, 0x10, 0x00, 0xfa, 0x19, 0xec, 0x43, 0xf5, 0xf7, 0x10, 0xef, 0xba, 0x41, 0x9b, 0x08, - 0x7a, 0xeb, 0x0a, 0xf9, 0x9d, 0xfa, 0x4b, 0xac, 0x76, 0x2f, 0x8f, 0x6e, 0x1e, 0x22, 0x50, 0x1a, 0xc3, 0x1d, 0x20, - 0x63, 0x01, 0x70, 0x23, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x4b, 0x13, 0x05, 0x05, 0x62, 0x9d, - 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, 0x83, 0xa6, 0x47, 0x10, 0x63, 0x7e, - 0xd7, 0x00, 0x0a, 0x07, 0x3e, 0x97, 0x18, 0x43, 0x18, 0xc1, 0x03, 0xa7, 0x07, 0x10, 0x13, 0x05, 0xa0, 0x0a, 0x05, - 0x07, 0x23, 0xa0, 0xe7, 0x10, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, 0x26, 0xca, 0xb7, 0x34, - 0x20, 0x00, 0x83, 0xa7, 0x04, 0xf6, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x11, 0x47, 0x63, - 0x6f, 0xf7, 0x0c, 0x37, 0x57, 0x10, 0x00, 0x8a, 0x07, 0x13, 0x07, 0x87, 0x64, 0xba, 0x97, 0x9c, 0x43, 0x2a, 0x84, - 0x93, 0x84, 0x04, 0xf6, 0x82, 0x87, 0x81, 0x45, 0xef, 0x30, 0x20, 0x31, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x92, 0xa7, - 0xf6, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x86, 0x87, 0x88, 0xef, 0x20, 0xd0, 0x6f, 0x9c, 0x40, 0x85, 0x07, 0x81, 0xa8, - 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0x07, 0xf6, 0x93, 0x07, 0xc0, 0x0f, 0x63, 0xf1, 0xa7, 0x02, 0x62, 0x44, 0x9d, - 0x47, 0xf2, 0x40, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x9c, 0xc0, 0xd2, 0x44, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, - 0x13, 0x05, 0x45, 0x62, 0x05, 0x61, 0x2d, 0xbf, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x49, 0xf6, 0x83, 0x55, 0x09, - 0x00, 0xef, 0x30, 0xa0, 0x2b, 0xb7, 0x37, 0x20, 0x00, 0xa3, 0x86, 0xfa, 0xe1, 0x89, 0x69, 0x3c, 0xbb, 0x3d, 0xa6, - 0x8a, 0x75, 0x3d, 0xa4, 0xe2, 0x78, 0x6a, 0x48, 0x56, 0x26, 0x01, 0x36, 0x65, 0x68, 0xf6, 0x03, 0xab, 0x63, 0x8f, - 0xa6, 0x8c, 0x7e, 0x7c, 0xdc, 0x6c, 0x48, 0x24, 0x87, 0x88, 0x23, 0x10, 0xa9, 0x00, 0x8d, 0x47, 0x5d, 0xf4, 0x9c, - 0xc0, 0x91, 0xa8, 0x37, 0x39, 0x20, 0x00, 0x03, 0x27, 0x89, 0xf6, 0x93, 0x07, 0xb0, 0x0f, 0x13, 0x09, 0x89, 0xf6, - 0x63, 0xf4, 0xe7, 0x00, 0xef, 0xe0, 0x3f, 0x81, 0x83, 0x27, 0x09, 0x00, 0x37, 0x3a, 0x20, 0x00, 0x13, 0x0a, 0x4a, - 0xf6, 0xb7, 0x39, 0x20, 0x00, 0x93, 0x89, 0xc9, 0x88, 0x83, 0x55, 0x0a, 0x00, 0xce, 0x97, 0x23, 0x81, 0x87, 0x00, - 0x22, 0x85, 0xef, 0x30, 0xa0, 0x26, 0x83, 0x27, 0x09, 0x00, 0x03, 0xc7, 0x19, 0x00, 0x23, 0x10, 0xaa, 0x00, 0x85, - 0x07, 0x23, 0x20, 0xf9, 0x00, 0xe3, 0xfd, 0xe7, 0xf4, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, - 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x93, 0xa7, 0xf6, 0x3d, 0xbf, 0x37, 0x39, 0x20, - 0x00, 0x13, 0x09, 0x69, 0xf6, 0x13, 0x14, 0x85, 0x00, 0xb7, 0x39, 0x20, 0x00, 0x03, 0x55, 0x09, 0x00, 0x93, 0x89, - 0x49, 0xf6, 0x83, 0xd7, 0x09, 0x00, 0x49, 0x8c, 0x23, 0x10, 0x89, 0x00, 0xe3, 0x8d, 0x87, 0xf0, 0x37, 0x54, 0x10, - 0x00, 0x13, 0x05, 0x44, 0x62, 0x99, 0x47, 0x89, 0x45, 0x9c, 0xc0, 0x95, 0x3d, 0x93, 0x05, 0x44, 0x62, 0x62, 0x44, - 0x03, 0xd7, 0x09, 0x00, 0x83, 0x56, 0x09, 0x00, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x37, - 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x86, 0x62, 0x13, 0x05, 0x45, 0x64, 0xfa, 0x13, 0xa0, 0xfe, - 0xe6, 0x97, 0x97, 0xfc, 0x05, 0xad, 0x6d, 0xc1, 0x90, 0x45, 0x32, 0x83, 0x16, 0x84, 0xb7, 0xae, 0x80, 0xb3, 0x10, - 0x97, 0x4c, 0x89, 0xa3, 0x5c, 0x15, 0xc4, 0x30, 0x20, 0x00, 0x20, 0x25, 0x05, 0x61, 0x6f, 0xf0, 0x3f, 0xdd, 0xb7, - 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0xb7, 0x25, 0x10, 0x00, 0x37, 0x25, 0x10, 0x00, 0x23, 0xa0, 0x07, 0x10, - 0x23, 0xa2, 0x07, 0x10, 0x93, 0x85, 0x05, 0xf8, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x05, 0x25, 0xfb, 0x23, 0xa0, 0x07, - 0xf6, 0x6f, 0x20, 0xb0, 0x52, 0x11, 0xed, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0xef, 0xe0, 0x2f, 0xf2, 0x32, 0x45, - 0xf2, 0x40, 0x13, 0x06, 0xe0, 0x0f, 0x81, 0x45, 0x05, 0x61, 0x6f, 0x30, 0x40, 0x25, 0x13, 0x06, 0xe0, 0x0f, 0x81, - 0x45, 0xdd, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xf6, 0x13, 0x05, 0xa0, 0x0a, 0x99, 0xc3, 0x13, 0x05, - 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, 0xf6, 0x1c, 0x40, 0x06, - 0xc6, 0x15, 0x47, 0x63, 0x98, 0xe7, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, - 0x81, 0xe7, 0x13, 0x05, 0x50, 0x05, 0xcd, 0xbf, 0xef, 0x20, 0x90, 0x50, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x19, 0xf5, - 0xfe, 0x01, 0x00, 0x18, 0x40, 0x91, 0x47, 0xe3, 0xcd, 0xe7, 0xfc, 0x99, 0x47, 0x1c, 0xc0, 0xd9, 0xbf, 0x41, 0x11, - 0x06, 0xc6, 0xef, 0x20, 0x10, 0x50, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xf5, 0x00, 0xef, 0x20, 0x70, 0x51, 0xb7, - 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x95, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, - 0xfa, 0xca, 0xa6, 0x83, 0xd7, 0x7d, 0x53, 0xa9, 0xaa, 0x73, 0x81, 0x1f, 0xa9, 0xcf, 0x0f, 0x1b, 0x12, 0x76, 0xef, - 0x97, 0x8c, 0xce, 0xe0, 0x13, 0x0e, 0x44, 0xc4, 0xd0, 0xfe, 0x0d, 0xe4, 0x36, 0xa3, 0xf8, 0x25, 0x50, 0x05, 0xb2, - 0x40, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x99, 0x47, 0x13, 0x05, 0xa0, 0x0a, - 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x9d, - 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x37, 0x35, 0x20, 0x00, - 0x13, 0x05, 0xc5, 0x88, 0x82, 0x80, 0x01, 0x11, 0x26, 0xca, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0xaa, - 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, 0xe3, 0x83, 0xc7, 0x14, 0x00, 0x13, 0x07, 0xc0, 0x0f, 0x13, 0x05, 0x50, 0x05, - 0x63, 0x65, 0xf7, 0x06, 0x37, 0x39, 0x20, 0x00, 0x13, 0x04, 0xc9, 0x98, 0x23, 0x20, 0x04, 0x10, 0x03, 0xc7, 0x04, - 0x00, 0xa3, 0x00, 0xf4, 0x00, 0x03, 0xc6, 0x14, 0x00, 0x23, 0x00, 0xe4, 0x00, 0x93, 0x85, 0x24, 0x00, 0x13, 0x05, - 0x24, 0x00, 0xef, 0x30, 0x00, 0x10, 0x83, 0xc9, 0x14, 0x00, 0x13, 0x05, 0xc9, 0x98, 0x13, 0x09, 0xc9, 0x98, 0x93, - 0x84, 0x29, 0x00, 0xa6, 0x85, 0xef, 0x30, 0x60, 0x08, 0xa2, 0x94, 0x23, 0x80, 0xa4, 0x00, 0x4e, 0x94, 0x21, 0x81, - 0x93, 0x87, 0x49, 0x00, 0xa3, 0x01, 0xa4, 0x00, 0xfd, 0x56, 0x13, 0xf7, 0x37, 0x00, 0x19, 0xef, 0x89, 0x83, 0x23, - 0x22, 0xf9, 0x10, 0xef, 0x20, 0xb0, 0x45, 0x13, 0x05, 0xa0, 0x0a, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, - 0xb2, 0x49, 0x05, 0x61, 0xfa, 0x42, 0x8f, 0x96, 0xf9, 0x34, 0x25, 0x1f, 0x81, 0xb7, 0xfe, 0xbd, 0x46, 0x43, 0x19, - 0xc3, 0xbd, 0xfe, 0xc4, 0x15, 0xd2, 0xa1, 0xe8, 0x11, 0xdc, 0xeb, 0xce, 0x72, 0x09, 0xfb, 0xf0, 0xde, 0x38, 0xd0, - 0x26, 0x82, 0x80, 0x33, 0x07, 0xf9, 0x00, 0x23, 0x00, 0xd7, 0x00, 0x85, 0x07, 0xd1, 0xbf, 0xb7, 0x37, 0x20, 0x00, - 0x93, 0x87, 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, 0x83, 0xa7, 0x47, 0x10, 0x63, 0x14, 0xf7, 0x00, 0x6f, 0x20, 0x30, - 0x3e, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa0, 0x07, 0xf6, 0x82, 0x80, 0x41, 0x11, - 0x06, 0xc6, 0x93, 0x07, 0x00, 0x08, 0x73, 0xa0, 0x47, 0x30, 0x93, 0x06, 0x70, 0x3e, 0x09, 0x46, 0x93, 0x05, 0x60, - 0x04, 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, 0x30, 0x52, 0x8d, 0x45, 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, 0x70, 0x52, - 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, 0xf0, 0x4f, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x10, 0x50, 0xfd, 0x56, 0x01, - 0x46, 0x93, 0x05, 0x60, 0x04, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x90, 0x4f, 0xb2, 0x40, 0xb7, 0x07, 0x20, 0x01, - 0x23, 0xac, 0x07, 0x00, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x89, 0x2c, 0xb2, 0x40, 0x41, 0x01, 0x45, - 0xb7, 0x41, 0x11, 0x22, 0xc4, 0xb7, 0x07, 0x20, 0x01, 0x06, 0xc6, 0x23, 0xac, 0x07, 0x00, 0x2a, 0x84, 0x37, 0x05, - 0x20, 0x01, 0xef, 0x20, 0x50, 0x4b, 0x93, 0x07, 0x80, 0x3e, 0x13, 0x05, 0x80, 0x3e, 0x63, 0xe3, 0x87, 0x00, 0x22, - 0x85, 0xb7, 0x07, 0x20, 0x01, 0x98, 0x4f, 0x13, 0x84, 0x87, 0x01, 0xe3, 0x6d, 0xa7, 0xfe, 0x37, 0x05, 0x20, 0x01, - 0xef, 0x20, 0xb0, 0x49, 0xb2, 0x40, 0x23, 0x20, 0xfa, 0x9b, 0x07, 0xb3, 0x36, 0x28, 0x7f, 0xc6, 0xca, 0xff, 0x0c, - 0x98, 0xc8, 0xc6, 0xbe, 0xcf, 0xcd, 0x4b, 0xb5, 0x6c, 0x32, 0x48, 0x0e, 0x70, 0x8d, 0xad, 0xf2, 0x9d, 0x21, 0x0a, - 0x2a, 0x2e, 0xc1, 0xa8, 0x27, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x11, 0xe1, 0x82, 0x80, 0x01, 0x00, - 0x7d, 0x15, 0xe5, 0xbf, 0x6f, 0xf0, 0x9f, 0xb3, 0x39, 0xa4, 0x01, 0x11, 0x26, 0xca, 0xaa, 0x84, 0x37, 0x05, 0x20, - 0x01, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x56, 0xc2, 0x06, 0xce, 0x22, 0xcc, 0x2e, 0x89, 0x93, 0x09, 0xa0, 0x0a, - 0xef, 0x20, 0x50, 0x45, 0x37, 0x0a, 0x20, 0x01, 0x93, 0x0a, 0x80, 0x3e, 0x82, 0x94, 0x2a, 0x84, 0x63, 0x0c, 0x35, - 0x03, 0x83, 0x27, 0x8a, 0x01, 0x63, 0x7a, 0xf9, 0x04, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0xc4, 0x65, 0x85, 0x45, - 0xef, 0xf0, 0x9f, 0xb6, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0x05, 0xc4, 0x65, 0xa6, 0x86, 0x13, - 0x06, 0x06, 0x66, 0x13, 0x05, 0x45, 0x64, 0xef, 0xf0, 0x9f, 0xad, 0x13, 0x04, 0x50, 0x05, 0x37, 0x05, 0x20, 0x01, - 0xef, 0x20, 0x30, 0x41, 0xf2, 0x40, 0x22, 0x85, 0x62, 0x44, 0xb7, 0x07, 0x20, 0x01, 0x23, 0xac, 0x07, 0x00, 0xd2, - 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xe3, 0xf0, 0x2a, 0xfb, 0x41, 0x22, - 0x69, 0xbf, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x87, 0x00, 0x1c, 0xc7, 0x82, 0x80, 0x41, 0x11, 0x22, - 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, 0xc1, 0xa9, 0x44, 0x03, 0x45, 0x04, 0x00, - 0x11, 0xe5, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xfa, 0x64, 0xf6, 0xce, 0x84, 0x88, 0x24, - 0x76, 0xd8, 0x4d, 0x95, 0x7b, 0xf3, 0x36, 0xe2, 0xe5, 0x99, 0x6d, 0x8f, 0xf2, 0xc0, 0xc6, 0x9f, 0x30, 0x1e, 0x9d, - 0x16, 0xfb, 0x95, 0x44, 0xae, 0x6e, 0x02, 0x80, 0x28, 0xef, 0xf0, 0xdf, 0xa1, 0x83, 0x47, 0x04, 0x00, 0x63, 0x94, - 0x97, 0x00, 0xef, 0xf0, 0x7f, 0xa6, 0x05, 0x04, 0xf9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0x25, 0x37, 0x93, 0x07, 0xa0, - 0x0a, 0x63, 0x05, 0xf5, 0x00, 0xef, 0xe0, 0xaf, 0xbd, 0x01, 0xa0, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, - 0x22, 0xc4, 0x37, 0x44, 0x20, 0x00, 0x13, 0x06, 0xc0, 0x1f, 0x81, 0x45, 0x13, 0x05, 0x04, 0xe0, 0x06, 0xc6, 0x26, - 0xc2, 0xef, 0x20, 0xb0, 0x6f, 0x13, 0x05, 0x04, 0xe0, 0x93, 0x05, 0xc0, 0x1f, 0xef, 0x20, 0xb0, 0x67, 0x93, 0x04, - 0x04, 0xe0, 0xb2, 0x40, 0x22, 0x44, 0x23, 0xae, 0xa4, 0x1e, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x37, - 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, 0xc0, 0x1f, 0x13, 0x04, 0x05, 0xe0, 0x13, 0x05, 0x05, 0xe0, 0x06, 0xc6, - 0xef, 0x20, 0xf0, 0x64, 0x03, 0x27, 0xc4, 0x1f, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xa7, 0x00, 0x93, 0x07, 0x50, - 0x05, 0xb2, 0x40, 0x22, 0x44, 0x3e, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, 0xaa, 0x87, 0x63, 0x6e, - 0xa7, 0x00, 0x13, 0x77, 0x35, 0x00, 0x01, 0x45, 0x11, 0xeb, 0x37, 0x45, 0x20, 0x00, 0x13, 0x05, 0x05, 0xe0, 0xf1, - 0x9b, 0xaa, 0x97, 0x88, 0x43, 0x82, 0x80, 0x01, 0x45, 0x82, 0x80, 0x93, 0x07, 0xb0, 0x1f, 0x63, 0xec, 0xa7, 0x00, - 0x93, 0x77, 0x35, 0x00, 0x81, 0xeb, 0xb7, 0x47, 0x20, 0x00, 0x71, 0x99, 0x93, 0x87, 0x07, 0xe0, 0xfa, 0xa5, 0xf1, - 0xcc, 0x0e, 0x38, 0x57, 0xc4, 0xf4, 0x5e, 0xcb, 0xb6, 0xb8, 0xe1, 0x94, 0xa4, 0xd4, 0x5c, 0x5e, 0xa1, 0x3a, 0x9f, - 0xdd, 0x18, 0xe3, 0xb4, 0x27, 0x7f, 0x90, 0x45, 0xee, 0x37, 0x24, 0x58, 0x29, 0x3e, 0x95, 0x0c, 0xc1, 0x82, 0x80, - 0x41, 0x11, 0x37, 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, 0xc0, 0x1f, 0x13, 0x04, 0x05, 0xe0, 0x13, 0x05, 0x05, - 0xe0, 0x06, 0xc6, 0xef, 0x20, 0x70, 0x5d, 0xb2, 0x40, 0x23, 0x2e, 0xa4, 0x1e, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, - 0x13, 0x07, 0xb0, 0x1f, 0x63, 0x61, 0xa7, 0x02, 0x93, 0x77, 0x35, 0x00, 0x13, 0x07, 0x50, 0x05, 0x89, 0xef, 0x41, - 0x11, 0x06, 0xc6, 0x5d, 0x37, 0xc9, 0x37, 0xb2, 0x40, 0x13, 0x07, 0xa0, 0x0a, 0x3a, 0x85, 0x41, 0x01, 0x82, 0x80, - 0x13, 0x07, 0x50, 0x05, 0x3a, 0x85, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x00, 0x10, 0x71, 0xb2, 0x40, 0xb7, - 0x07, 0x00, 0x02, 0x0d, 0x47, 0xf8, 0xcb, 0x13, 0x05, 0xa0, 0x0a, 0x41, 0x01, 0x82, 0x80, 0x73, 0x00, 0x50, 0x10, - 0x82, 0x80, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x52, 0xcc, 0x06, 0xd6, 0x2a, 0x84, 0xae, - 0x84, 0x32, 0x89, 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x07, 0x39, 0x41, 0x33, 0x05, 0x34, 0x01, 0x63, 0x6c, 0xfa, 0x02, - 0x71, 0x56, 0x93, 0x57, 0x29, 0x00, 0xb3, 0x87, 0xc7, 0x02, 0x93, 0x75, 0xc9, 0xff, 0x33, 0x05, 0xb4, 0x00, 0xae, - 0x94, 0x33, 0x86, 0x27, 0x01, 0x11, 0xc6, 0x9c, 0x40, 0x6c, 0x00, 0x3e, 0xc6, 0xef, 0x20, 0xd0, 0x56, 0xb2, 0x50, - 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0xb3, 0x87, 0x34, 0x01, 0x9c, - 0x43, 0xfa, 0x96, 0x2d, 0x7e, 0x3a, 0xd4, 0x29, 0xdc, 0xc6, 0xf5, 0x7b, 0x9d, 0xde, 0x3a, 0xe3, 0x13, 0xf0, 0xa4, - 0xda, 0xb9, 0xcb, 0x28, 0xf6, 0x65, 0x59, 0xcb, 0x7c, 0xca, 0xb7, 0x30, 0x66, 0xd9, 0x07, 0x30, 0x2a, 0x11, 0x46, - 0x6c, 0x00, 0x3e, 0xc6, 0x91, 0x09, 0xef, 0x20, 0xb0, 0x54, 0x7d, 0xb7, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, - 0xd0, 0x4e, 0xce, 0x52, 0xcc, 0x06, 0xd6, 0x2a, 0x84, 0xae, 0x84, 0x32, 0x89, 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x07, - 0x39, 0x41, 0xb3, 0x85, 0x34, 0x01, 0x63, 0x6d, 0xfa, 0x02, 0x71, 0x56, 0x93, 0x57, 0x29, 0x00, 0xb3, 0x87, 0xc7, - 0x02, 0x93, 0x75, 0xc9, 0xff, 0x2e, 0x94, 0xa6, 0x95, 0x33, 0x86, 0x27, 0x01, 0x01, 0xca, 0x1c, 0x40, 0x68, 0x00, - 0x3e, 0xc6, 0xef, 0x20, 0x30, 0x50, 0xb2, 0x47, 0x1c, 0xc0, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, - 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0x11, 0x46, 0x68, 0x00, 0xef, 0x20, 0x70, 0x4e, 0x32, 0x47, 0xb3, 0x07, - 0x34, 0x01, 0x91, 0x09, 0x98, 0xc3, 0x75, 0xb7, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, - 0xe0, 0x6f, 0x9c, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa6, 0xe7, 0xf6, 0xb7, 0x37, 0x20, 0x00, - 0x23, 0xa8, 0x87, 0xf6, 0x22, 0x44, 0xb2, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x8a, 0x07, 0xa8, 0x41, 0x01, 0x6f, - 0xf0, 0xbf, 0xa4, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, 0x99, 0x37, 0x35, - 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0xa2, 0x85, 0x13, 0x06, 0xe0, 0x0f, 0x13, 0x05, 0x45, 0xa9, 0x23, 0x8a, 0x07, - 0xb8, 0xef, 0x20, 0xf0, 0x47, 0xfa, 0xf5, 0xf6, 0x53, 0xaf, 0xb2, 0x2b, 0x3b, 0x05, 0xa1, 0xfd, 0x11, 0x48, 0x09, - 0x71, 0x5b, 0x0d, 0x75, 0x63, 0x38, 0x76, 0x8a, 0x94, 0xff, 0xca, 0xca, 0x71, 0x6f, 0x6d, 0x48, 0xc9, 0xc4, 0x5b, - 0x08, 0x2b, 0x22, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xb2, 0x41, 0x11, 0x22, 0xc4, 0x06, - 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0xcf, 0x95, 0xb7, 0x34, 0x20, 0x00, 0x83, 0xc7, 0x44, 0xb9, - 0x99, 0xcb, 0x37, 0x35, 0x20, 0x00, 0x13, 0x06, 0xe0, 0x0f, 0x93, 0x85, 0x44, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0xef, - 0x20, 0x50, 0x44, 0xa2, 0x85, 0x13, 0x85, 0x44, 0xb9, 0x13, 0x06, 0xe0, 0x0f, 0xef, 0x20, 0x70, 0x43, 0x22, 0x85, - 0x22, 0x44, 0xb2, 0x40, 0x92, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0x1f, 0xae, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0xc7, - 0xf6, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0xc4, 0xf6, 0x26, 0xc2, 0x04, 0x40, - 0x06, 0xc6, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x89, 0xf4, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x92, - 0x44, 0x41, 0x01, 0x82, 0x80, 0x37, 0x35, 0x20, 0x00, 0x13, 0x05, 0x45, 0xb9, 0xef, 0xf0, 0x3f, 0xaa, 0xe3, 0x13, - 0x95, 0xfe, 0x93, 0x07, 0x50, 0x05, 0x1c, 0xc0, 0xc5, 0xb7, 0x37, 0x35, 0x20, 0x00, 0x83, 0x47, 0x45, 0xa9, 0x85, - 0xc3, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xc7, 0x47, 0xb9, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, - 0x23, 0xa6, 0xe7, 0xf6, 0x13, 0x05, 0x45, 0xa9, 0x6f, 0xf0, 0xff, 0xa6, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, - 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xdf, 0x99, 0x93, 0x07, 0xfa, 0x40, 0xaf, 0x15, 0x12, 0x17, 0xb6, 0x43, 0x1a, 0xa9, - 0x9b, 0xa0, 0x07, 0x95, 0xfa, 0x8a, 0xce, 0xbd, 0x9e, 0x0c, 0xbf, 0x1f, 0xff, 0x1d, 0x40, 0x36, 0xf2, 0xe6, 0xe0, - 0x9e, 0x30, 0x8b, 0x01, 0xe0, 0x2b, 0xa0, 0x0a, 0x63, 0x04, 0xf5, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, - 0x01, 0x82, 0x80, 0x6d, 0x71, 0x23, 0x26, 0x11, 0x10, 0x23, 0x24, 0x81, 0x10, 0x23, 0x22, 0x91, 0x10, 0xef, 0xf0, - 0xdf, 0x98, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x04, 0x2a, 0x84, 0xef, 0xf0, 0x5f, 0x9c, 0x63, 0x1b, 0x85, - 0x06, 0xef, 0xf0, 0xdf, 0xa1, 0x83, 0x46, 0x05, 0x00, 0x93, 0x07, 0x20, 0x0a, 0x2a, 0x84, 0x63, 0x80, 0xf6, 0x02, - 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x66, 0x93, 0x85, 0xc5, - 0x67, 0x13, 0x05, 0x45, 0x64, 0xef, 0xf0, 0x6f, 0xeb, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xf7, 0x22, 0x85, - 0x82, 0x97, 0xef, 0xf0, 0xff, 0xaa, 0xef, 0xf0, 0xdf, 0xa8, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x14, 0xf5, - 0x08, 0xef, 0xf0, 0x7f, 0x91, 0x63, 0x10, 0x85, 0x08, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xf6, 0x63, 0x94, - 0xa7, 0x04, 0x03, 0x24, 0x81, 0x10, 0x83, 0x20, 0xc1, 0x10, 0x83, 0x24, 0x41, 0x10, 0x51, 0x61, 0x6f, 0xf0, 0x7f, - 0xee, 0xef, 0xf0, 0xbf, 0x97, 0x81, 0x44, 0x63, 0x14, 0x85, 0x00, 0x93, 0x04, 0xc0, 0x07, 0xef, 0xf0, 0x5f, 0x98, - 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0xdd, 0xd4, 0x0a, 0x85, 0x23, 0x00, 0x91, 0x00, 0xa3, 0x00, 0x01, - 0x00, 0xef, 0xf0, 0x5f, 0xe3, 0x79, 0xbf, 0x93, 0x04, 0xc0, 0x07, 0xf5, 0xb7, 0xfa, 0x95, 0xdb, 0x48, 0x6d, 0x01, - 0xaa, 0x0e, 0x83, 0xe5, 0x77, 0x95, 0xb2, 0x83, 0x53, 0x78, 0x3d, 0x9d, 0xff, 0xf9, 0xf5, 0xac, 0x28, 0xc6, 0x1f, - 0xd6, 0xd3, 0xe6, 0x71, 0x0e, 0x17, 0xdb, 0xc3, 0xb8, 0x2c, 0xb7, 0x35, 0x20, 0x00, 0x83, 0xc7, 0x45, 0xb9, 0x95, - 0xc3, 0x03, 0x24, 0x81, 0x10, 0x83, 0x20, 0xc1, 0x10, 0x83, 0x24, 0x41, 0x10, 0x37, 0x35, 0x20, 0x00, 0x13, 0x06, - 0xe0, 0x0f, 0x93, 0x85, 0x45, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0x51, 0x61, 0x6f, 0x20, 0x30, 0x2a, 0x83, 0x20, 0xc1, - 0x10, 0x03, 0x24, 0x81, 0x10, 0x83, 0x24, 0x41, 0x10, 0x51, 0x61, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x23, 0xa2, - 0x07, 0x00, 0x21, 0x65, 0x6f, 0x20, 0xc0, 0x1c, 0x41, 0x11, 0x21, 0x65, 0x06, 0xc6, 0xef, 0x20, 0x60, 0x1b, 0xb2, - 0x40, 0xb7, 0x07, 0x01, 0x04, 0x05, 0x47, 0xd8, 0xc3, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, - 0x06, 0xc6, 0x93, 0x07, 0x70, 0x02, 0x2a, 0x84, 0xae, 0x84, 0x63, 0xf4, 0xa7, 0x00, 0xef, 0xd0, 0xff, 0xf4, 0x37, - 0x05, 0x01, 0x04, 0x0a, 0x04, 0x13, 0x05, 0x05, 0x10, 0x2a, 0x94, 0x04, 0xc0, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, - 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x13, 0x87, 0x07, 0x10, 0x93, 0x87, 0x07, 0x1a, 0x23, 0x20, 0x07, - 0x00, 0x11, 0x07, 0xe3, 0x1d, 0xf7, 0xfe, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0xc8, 0xcb, 0x82, 0x80, 0x42, 0x05, - 0xb7, 0x07, 0x01, 0x04, 0xc8, 0xcb, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x88, 0x4b, 0x13, 0x75, 0xf5, 0x0f, 0x82, - 0x80, 0x89, 0x67, 0x37, 0x07, 0x01, 0x04, 0x8d, 0x07, 0x1c, 0xc7, 0x23, 0x2a, 0x07, 0x00, 0x82, 0x80, 0xfa, 0x4c, - 0x04, 0x05, 0x12, 0x0c, 0x74, 0xdd, 0x85, 0x01, 0x4f, 0x18, 0x97, 0x4d, 0x7d, 0xa9, 0x14, 0xf5, 0x47, 0x44, 0x40, - 0x40, 0xba, 0x6f, 0x07, 0xab, 0x90, 0xf1, 0xf2, 0x29, 0x30, 0x11, 0x5c, 0x90, 0x2d, 0x41, 0x11, 0x06, 0xc6, 0x22, - 0xc4, 0x2a, 0x84, 0xad, 0x37, 0xb7, 0x07, 0x01, 0x04, 0x80, 0xcf, 0xc5, 0x37, 0x65, 0x37, 0x22, 0x44, 0xb2, 0x40, - 0x41, 0x01, 0xa9, 0xb7, 0xb7, 0x06, 0x01, 0x04, 0x9c, 0x46, 0x05, 0x45, 0x13, 0xf7, 0x17, 0x00, 0x1d, 0xc7, 0x13, - 0xf7, 0x07, 0x40, 0x0d, 0x45, 0x1d, 0xe3, 0x98, 0x4a, 0x13, 0x77, 0xf7, 0x0f, 0x19, 0xcf, 0x13, 0xf7, 0x27, 0x20, - 0x09, 0x45, 0x19, 0xeb, 0x13, 0xd7, 0xb7, 0x00, 0x05, 0x8b, 0x11, 0x45, 0x11, 0xe7, 0x13, 0xd5, 0x87, 0x00, 0x13, - 0x45, 0x15, 0x00, 0x05, 0x89, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x88, 0xcf, 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, - 0x06, 0xce, 0x33, 0x07, 0xb6, 0x00, 0x93, 0x07, 0x00, 0x09, 0x2e, 0x84, 0x63, 0xf8, 0xe7, 0x00, 0x32, 0xc6, 0x2a, - 0xc4, 0xef, 0xd0, 0x5f, 0xe7, 0x32, 0x46, 0x22, 0x45, 0xb7, 0x15, 0x01, 0x04, 0xa2, 0x95, 0xef, 0xf0, 0xdf, 0xbb, - 0xf2, 0x40, 0x62, 0x44, 0x13, 0x05, 0xa0, 0x0a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, 0x26, 0xca, 0x06, - 0xce, 0x33, 0x07, 0xb6, 0x00, 0x93, 0x07, 0x00, 0x08, 0xaa, 0x84, 0x2e, 0x84, 0x63, 0xf6, 0xe7, 0x00, 0x32, 0xc6, - 0xef, 0xd0, 0xdf, 0xe3, 0x32, 0x46, 0x37, 0x25, 0x01, 0x04, 0x13, 0x05, 0x05, 0x80, 0x22, 0x95, 0x62, 0x44, 0xf2, - 0x40, 0xa6, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x6f, 0xf0, 0x5f, 0xbe, 0x39, 0x71, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, - 0xb7, 0x55, 0xfa, 0x05, 0x46, 0x85, 0x81, 0x50, 0x32, 0xe0, 0x11, 0xb7, 0x79, 0xe8, 0xb6, 0xf6, 0x15, 0x1e, 0xad, - 0xe0, 0x41, 0x05, 0x0e, 0x83, 0xba, 0xde, 0x42, 0x1b, 0x6d, 0x61, 0xe6, 0xcf, 0x8d, 0x9f, 0x14, 0x68, 0x2e, 0x10, - 0x00, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x06, 0x68, 0x93, 0x85, 0x05, 0x69, 0x13, 0x05, - 0x45, 0x69, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, - 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xf0, 0xcf, 0xc5, 0xef, 0xe0, 0xcf, 0xc8, 0xf2, 0x50, - 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, - 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x09, 0x65, - 0x6f, 0x10, 0x70, 0x7f, 0x09, 0x65, 0x6f, 0x10, 0xd0, 0x7f, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, - 0xe1, 0xef, 0xd0, 0x1f, 0xda, 0xdd, 0x37, 0xb7, 0x07, 0x00, 0x07, 0x83, 0x46, 0x14, 0x00, 0xd8, 0x43, 0x83, 0x47, - 0x04, 0x00, 0xa2, 0x06, 0xdd, 0x8e, 0x83, 0x47, 0x24, 0x00, 0xc2, 0x07, 0xdd, 0x8e, 0x83, 0x47, 0x34, 0x00, 0xe2, - 0x07, 0xd5, 0x8f, 0x93, 0x06, 0xf0, 0x0f, 0x63, 0x85, 0xd7, 0x00, 0x61, 0x9b, 0x9d, 0x8b, 0x5d, 0x8f, 0x93, 0x77, - 0x77, 0xff, 0x03, 0x47, 0x44, 0x00, 0x83, 0x46, 0x94, 0x00, 0xb2, 0x40, 0x0e, 0x07, 0x21, 0x8b, 0x5d, 0x8f, 0xfd, - 0x77, 0xbd, 0x07, 0x7d, 0x8f, 0x83, 0x47, 0x54, 0x00, 0x92, 0x07, 0x5d, 0x8f, 0xb7, 0x17, 0x80, 0xff, 0xfd, 0x17, - 0x7d, 0x8f, 0x83, 0x47, 0xa4, 0x00, 0xfa, 0x14, 0x86, 0xe1, 0xa4, 0x5c, 0x00, 0xa3, 0x9c, 0xfa, 0xe2, 0x50, 0x11, - 0x30, 0x19, 0xab, 0x38, 0x6f, 0x70, 0x36, 0x0a, 0xe3, 0x2b, 0x82, 0xf0, 0x4a, 0x07, 0xc7, 0x12, 0x67, 0x80, 0x21, - 0x10, 0x40, 0x2f, 0xa2, 0x07, 0xd5, 0x8f, 0xb2, 0x07, 0xb7, 0xf6, 0x7f, 0x00, 0xf5, 0x8f, 0xd9, 0x8f, 0x37, 0x07, - 0x80, 0xf8, 0x7d, 0x17, 0xf9, 0x8f, 0x03, 0x47, 0x74, 0x00, 0xb7, 0x06, 0x80, 0x07, 0x5e, 0x07, 0x75, 0x8f, 0xd9, - 0x8f, 0x37, 0x07, 0x00, 0x88, 0x7d, 0x17, 0xf9, 0x8f, 0x03, 0x47, 0x64, 0x00, 0xb7, 0x06, 0x00, 0x78, 0x22, 0x44, - 0x6e, 0x07, 0x75, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x00, 0x07, 0x5c, 0xc3, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, - 0x00, 0x03, 0xa5, 0x87, 0xf7, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x13, 0x05, 0xa0, 0x0a, - 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x13, - 0x05, 0xa0, 0x0a, 0x89, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, - 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x65, 0xba, 0x6f, 0xf0, 0xbf, 0x8c, 0x41, 0x11, 0xb7, 0x07, 0x08, 0x05, 0x22, - 0xc4, 0x03, 0xa4, 0xc7, 0x20, 0x37, 0x07, 0x00, 0x04, 0x06, 0xc6, 0x26, 0xc2, 0xb3, 0x76, 0xe4, 0x00, 0x91, 0xca, - 0x37, 0x55, 0x10, 0x00, 0x23, 0xa6, 0xe7, 0x20, 0xa5, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xf0, 0x4f, 0xb7, 0xb7, - 0x07, 0x80, 0x6b, 0xe1, 0x8f, 0x95, 0xcb, 0x37, 0x07, 0x08, 0x05, 0x23, 0x26, 0xf7, 0x20, 0xb7, 0x07, 0x00, 0x68, - 0x7d, 0x8c, 0x93, 0x04, 0x50, 0x05, 0x11, 0xc8, 0x37, 0x55, 0xfa, 0x8e, 0xf5, 0x52, 0x1f, 0x6e, 0xfd, 0x26, 0x25, - 0xc2, 0xba, 0x74, 0xa9, 0x51, 0x70, 0xbe, 0xd3, 0xd4, 0xad, 0xde, 0x05, 0x25, 0xd6, 0x75, 0xec, 0xb0, 0x8f, 0x31, - 0xb7, 0x3c, 0xf7, 0x02, 0xf8, 0x18, 0x30, 0x10, 0x00, 0x9d, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xf0, 0xaf, 0xb4, - 0xef, 0xd0, 0x9f, 0xc5, 0xb2, 0x40, 0x22, 0x44, 0x26, 0x85, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, - 0x00, 0x93, 0x87, 0xc7, 0xf7, 0x84, 0x43, 0x13, 0x07, 0xa0, 0x0a, 0x63, 0x96, 0xe4, 0x00, 0x13, 0x07, 0x50, 0x05, - 0x98, 0xc3, 0xe1, 0xbf, 0x93, 0x04, 0xa0, 0x0a, 0xd9, 0xbf, 0x81, 0x47, 0xb7, 0x05, 0x08, 0x05, 0x13, 0x07, 0x00, - 0x20, 0xb3, 0x86, 0xb7, 0x00, 0x90, 0x42, 0xb3, 0x06, 0xf5, 0x00, 0x91, 0x07, 0x90, 0xc2, 0xe3, 0x99, 0xe7, 0xfe, - 0x6f, 0xf0, 0xff, 0xf5, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0x2a, 0x84, 0xef, 0xf0, 0x1f, 0xf4, 0xb7, 0x37, 0x20, - 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf6, 0x8d, 0x47, 0x33, 0x95, 0x87, 0x00, 0xb7, 0xb7, 0xaa, 0x02, - 0x93, 0x87, 0xa7, 0xaa, 0x3d, 0x8d, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xa4, 0xa7, 0x20, 0x89, 0x65, 0x37, 0x35, 0x10, - 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x65, 0xb8, 0xef, 0xf0, 0x2f, 0xfe, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, - 0x6f, 0xf0, 0x3f, 0xf1, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x9f, 0xef, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, - 0xf7, 0x37, 0x07, 0x08, 0x05, 0x13, 0x05, 0x00, 0x20, 0xf9, 0x9b, 0x23, 0x22, 0xf7, 0x20, 0xef, 0x10, 0xd0, 0x5e, - 0xb2, 0x40, 0x39, 0x45, 0x41, 0x01, 0x6f, 0x10, 0xf0, 0x5f, 0x37, 0x37, 0x20, 0x00, 0xfa, 0x56, 0x84, 0x51, 0x84, - 0x21, 0x1f, 0x67, 0xc3, 0x25, 0x4a, 0x29, 0x3f, 0x5d, 0x30, 0x2c, 0x3c, 0x48, 0x9c, 0xb8, 0x81, 0x37, 0x43, 0x96, - 0x5a, 0x4d, 0x5f, 0x88, 0x65, 0xd0, 0xee, 0x8f, 0x91, 0xf0, 0x30, 0x13, 0x07, 0x47, 0xf7, 0x1c, 0x43, 0x93, 0xf7, - 0xf7, 0xfd, 0x1c, 0xc3, 0x37, 0x07, 0x08, 0x05, 0x23, 0x22, 0xf7, 0x20, 0x82, 0x80, 0x37, 0x37, 0x20, 0x00, 0x13, - 0x07, 0x47, 0xf7, 0x1c, 0x43, 0x93, 0xe7, 0x07, 0x02, 0x1c, 0xc3, 0x37, 0x07, 0x08, 0x05, 0x23, 0x22, 0xf7, 0x20, - 0x82, 0x80, 0x33, 0x87, 0xc5, 0x00, 0xb7, 0x07, 0x08, 0x00, 0x63, 0x7c, 0xf7, 0x06, 0x01, 0x11, 0x22, 0xcc, 0x26, - 0xca, 0x4e, 0xc6, 0x06, 0xce, 0x4a, 0xc8, 0x93, 0xf4, 0x35, 0x00, 0xaa, 0x89, 0x2e, 0x84, 0x13, 0x05, 0x50, 0x05, - 0x9d, 0xec, 0x32, 0x89, 0xef, 0xf0, 0x5f, 0xe7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x47, 0xf7, 0xb7, 0x06, 0x08, - 0x05, 0xb7, 0x05, 0x00, 0x05, 0x13, 0x67, 0x27, 0x00, 0x23, 0xa2, 0xe6, 0x20, 0x93, 0x87, 0x47, 0xf7, 0x0d, 0x47, - 0x2e, 0x94, 0xb3, 0x06, 0x99, 0x40, 0x63, 0x60, 0xd7, 0x02, 0x98, 0x43, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x05, 0xa0, - 0x0a, 0x23, 0xa2, 0xe7, 0x20, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, - 0xb3, 0x06, 0x94, 0x00, 0x90, 0x42, 0xb3, 0x86, 0x99, 0x00, 0x91, 0x04, 0x90, 0xc2, 0xf9, 0xb7, 0x13, 0x05, 0x50, - 0x05, 0x82, 0x80, 0x01, 0x11, 0xaa, 0x85, 0x11, 0x46, 0x68, 0x00, 0x06, 0xce, 0xef, 0xf0, 0x1f, 0xf7, 0x93, 0x07, - 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x00, 0x32, 0x45, 0xf2, 0x40, 0x05, 0x61, 0x82, 0x80, 0x01, 0x45, 0xe5, 0xbf, 0xfa, - 0x8e, 0xa8, 0x4b, 0x5c, 0xb4, 0xcb, 0x70, 0xf2, 0x84, 0x9d, 0x29, 0xc9, 0xe7, 0x05, 0x7b, 0xe9, 0xa3, 0x1a, 0x9e, - 0xc2, 0xd8, 0x3d, 0x17, 0x2e, 0x4e, 0x49, 0xa8, 0x58, 0x67, 0x53, 0x3d, 0x30, 0xc8, 0x31, 0xb7, 0x07, 0x08, 0x00, - 0x63, 0xef, 0xa7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x8d, - 0xe3, 0xae, 0x84, 0xef, 0xf0, 0xbf, 0xdd, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x22, 0x44, 0xb2, 0x40, - 0x23, 0xaa, 0x97, 0x20, 0x92, 0x44, 0x01, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x9f, 0xe7, 0xb2, 0x40, 0x22, 0x44, 0x92, - 0x44, 0x41, 0x01, 0x82, 0x80, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xaa, 0x84, 0x2e, 0x84, - 0x45, 0x3f, 0x26, 0x85, 0xef, 0xf0, 0xbf, 0xf8, 0x63, 0x09, 0x85, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, - 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xcd, 0xbf, 0x01, 0x11, 0x22, 0xcc, 0x2e, 0xc6, - 0x06, 0xce, 0x2a, 0x84, 0xef, 0xf0, 0x5f, 0xf6, 0xb2, 0x45, 0x63, 0x03, 0xb5, 0x02, 0xfd, 0x57, 0x63, 0x1a, 0xf5, - 0x00, 0x63, 0x8e, 0xa5, 0x00, 0x22, 0x85, 0x62, 0x44, 0xf2, 0x40, 0x05, 0x61, 0x6f, 0xf0, 0xff, 0xfa, 0x13, 0x05, - 0x50, 0x05, 0xf2, 0x40, 0x62, 0x44, 0x05, 0x61, 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xd5, 0xbf, 0xb7, 0x07, 0x08, - 0x00, 0x63, 0xe0, 0xb7, 0x04, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0xf7, 0xf5, 0x1f, 0xaa, 0x84, - 0x2e, 0x84, 0x13, 0x05, 0x50, 0x05, 0x99, 0xef, 0xef, 0xf0, 0xbf, 0xd2, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, - 0x20, 0x39, 0x45, 0xfa, 0xae, 0x12, 0x6b, 0xf5, 0x7c, 0xf1, 0x60, 0xfb, 0x50, 0x98, 0xd0, 0xcd, 0x92, 0x00, 0x69, - 0xd6, 0x9f, 0x11, 0xa4, 0x60, 0xdd, 0xc9, 0x37, 0x27, 0x2a, 0x0b, 0x62, 0x16, 0x8f, 0x8d, 0x5f, 0x4f, 0xa0, 0x32, - 0xef, 0xf0, 0x5f, 0xdd, 0x26, 0x85, 0xef, 0xf0, 0xff, 0xda, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, - 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, - 0x4a, 0xc8, 0x4e, 0xc6, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xfb, 0xb7, 0x00, 0x81, 0x44, 0xf2, 0x40, 0x62, 0x44, 0x42, - 0x49, 0xb2, 0x49, 0x26, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x82, 0x80, 0x93, 0xf4, 0xf5, 0x1f, 0x2e, 0x84, 0xe5, 0xf4, - 0x2a, 0x89, 0xef, 0xf0, 0xff, 0xcc, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x41, 0x45, 0xef, 0xf0, 0x9f, - 0xd7, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x17, 0xf5, 0xfc, 0x37, 0x34, 0x20, 0x00, 0x13, 0x05, 0x44, 0xc9, 0xef, 0xf0, - 0x5f, 0xd4, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x87, 0x07, 0x20, 0x23, 0xa0, 0x07, 0x00, 0x91, 0x07, 0xe3, 0x9d, 0xe7, - 0xfe, 0x93, 0x09, 0x44, 0xc9, 0x03, 0xd6, 0xc9, 0x1f, 0x93, 0x07, 0xc0, 0x1d, 0x63, 0xfa, 0xc7, 0x00, 0x37, 0x55, - 0x10, 0x00, 0x99, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xf0, 0xaf, 0x82, 0x41, 0xbf, 0x93, 0x05, 0x44, 0xc9, 0x4a, - 0x85, 0xef, 0x20, 0x60, 0x43, 0x83, 0xd4, 0xc9, 0x1f, 0x41, 0xb7, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe7, 0xa7, 0x04, - 0x41, 0x11, 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x13, 0x05, 0x50, 0x05, 0x9d, - 0xe7, 0xef, 0xf0, 0xbf, 0xc4, 0x85, 0x67, 0xfa, 0x98, 0x7d, 0xd6, 0xbd, 0x4c, 0x7f, 0x66, 0x14, 0x0e, 0xb7, 0xd3, - 0x03, 0xf0, 0x61, 0x38, 0x62, 0xac, 0xd9, 0xe6, 0xe0, 0x22, 0xb7, 0xe4, 0xf6, 0xaf, 0x7e, 0x60, 0x65, 0x80, 0xf6, - 0x02, 0xfe, 0x78, 0x33, 0xb7, 0x04, 0x08, 0x05, 0x93, 0x87, 0x97, 0x82, 0x23, 0xa2, 0xf4, 0x20, 0x23, 0xac, 0x84, - 0x20, 0x39, 0x45, 0xef, 0xf0, 0xbf, 0xce, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf7, 0x13, 0x05, 0xa0, 0x0a, - 0x23, 0xa2, 0xf4, 0x20, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, - 0x80, 0x0d, 0x65, 0x01, 0x11, 0x13, 0x05, 0x05, 0x20, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, - 0xef, 0x10, 0xf0, 0x2f, 0x39, 0x45, 0xef, 0x10, 0x50, 0x31, 0x13, 0x05, 0x80, 0x07, 0x37, 0x39, 0x20, 0x00, 0xef, - 0xf0, 0x6f, 0xb9, 0x93, 0x09, 0x49, 0xf7, 0x83, 0xa7, 0x09, 0x00, 0x37, 0x04, 0x08, 0x05, 0x93, 0x04, 0x04, 0x20, - 0xdc, 0xc0, 0xb7, 0x07, 0x46, 0x00, 0x85, 0x07, 0xdc, 0xcc, 0x85, 0x67, 0x93, 0x87, 0x57, 0x86, 0x89, 0x65, 0x37, - 0x35, 0x10, 0x00, 0xdc, 0xc0, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x05, 0xb9, 0xef, 0xf0, 0xef, 0xc8, 0xb7, 0x07, - 0x40, 0x08, 0x9c, 0xc8, 0xdc, 0x40, 0x01, 0x45, 0x13, 0x09, 0x49, 0xf7, 0x93, 0xe7, 0x07, 0x18, 0x23, 0xa0, 0xf9, - 0x00, 0xef, 0xf0, 0x7f, 0xf3, 0x93, 0x07, 0x04, 0x10, 0x98, 0x43, 0xb7, 0x67, 0xa5, 0xf0, 0x93, 0x87, 0xf7, 0xa0, - 0x63, 0x05, 0xf7, 0x02, 0x37, 0x55, 0x10, 0x00, 0x95, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, 0xbf, 0xf2, 0x41, - 0x67, 0x7d, 0x17, 0x93, 0x07, 0x04, 0x18, 0xb8, 0xd3, 0xf8, 0xd3, 0xfa, 0xb8, 0x2d, 0x0d, 0x74, 0xa2, 0xc0, 0x13, - 0xb8, 0xfa, 0x03, 0x40, 0xaa, 0x55, 0xc0, 0x46, 0x6a, 0x1e, 0xf3, 0x5f, 0x4c, 0xdf, 0xdd, 0x3d, 0x0a, 0x63, 0x3f, - 0xb9, 0x91, 0xb9, 0x15, 0x6f, 0xb0, 0x50, 0x34, 0xb8, 0xd7, 0xf8, 0xd7, 0xb8, 0xdb, 0xf8, 0xdb, 0xb8, 0xdf, 0xf8, - 0xdf, 0x51, 0x45, 0xef, 0xf0, 0x7f, 0xc1, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x91, 0x8b, 0x91, 0xeb, - 0x37, 0x55, 0x10, 0x00, 0x91, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, 0x3f, 0xef, 0xef, 0xd0, 0x1f, 0x80, 0xb7, - 0x07, 0x08, 0x05, 0x37, 0x07, 0x40, 0x00, 0x23, 0xa6, 0xe7, 0x20, 0x03, 0x27, 0x09, 0x00, 0xf2, 0x40, 0x62, 0x44, - 0x23, 0xa2, 0xe7, 0x20, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, 0x85, 0x67, 0x37, 0x37, 0x20, - 0x00, 0x93, 0x87, 0x47, 0x86, 0x23, 0x2a, 0xf7, 0xf6, 0x37, 0x37, 0x20, 0x00, 0x93, 0x07, 0x50, 0x05, 0x23, 0x2c, - 0xf7, 0xf6, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2e, 0xf7, 0xf6, 0x6f, 0xf0, 0xbf, 0xee, 0xb7, 0x07, 0x08, 0x00, 0x63, - 0xe0, 0xa7, 0x06, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x13, 0x05, - 0x50, 0x05, 0xa1, 0xe3, 0xae, 0x84, 0xef, 0xf0, 0x7f, 0xad, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x01, - 0x47, 0x93, 0x06, 0x00, 0x20, 0xb3, 0x85, 0xe4, 0x00, 0x8c, 0x41, 0x33, 0x06, 0xf7, 0x00, 0x11, 0x07, 0x0c, 0xc2, - 0xe3, 0x19, 0xd7, 0xfe, 0x7d, 0x57, 0x93, 0x87, 0x07, 0x20, 0xf8, 0xc3, 0xb8, 0xc7, 0xf8, 0xc7, 0xb8, 0xcb, 0x29, - 0x45, 0xef, 0xf0, 0xbf, 0xb5, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0xfa, 0x43, 0xf3, 0xa6, - 0x53, 0xa0, 0x13, 0x87, 0x84, 0x9f, 0x78, 0x47, 0x6a, 0xd0, 0x5b, 0xd2, 0x61, 0x1c, 0xd3, 0xd9, 0x55, 0xd8, 0xc8, - 0xf5, 0x70, 0xce, 0x63, 0xde, 0x2e, 0xe9, 0xbe, 0x7b, 0x84, 0x28, 0x35, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, - 0x05, 0x82, 0x80, 0xaa, 0x85, 0x37, 0x05, 0x08, 0x05, 0x41, 0x46, 0x13, 0x05, 0x05, 0x26, 0x6f, 0xf0, 0x0f, 0xd0, - 0xb7, 0x07, 0x08, 0x00, 0x63, 0xef, 0xa7, 0x0a, 0x01, 0x11, 0x26, 0xca, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xce, 0x22, - 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x56, 0xc2, 0xaa, 0x84, 0x13, 0x05, 0x50, 0x05, 0xd9, 0xe7, 0x93, 0x07, - 0xc0, 0x1d, 0x32, 0x89, 0x63, 0xe3, 0xc7, 0x08, 0xb6, 0x89, 0x37, 0x34, 0x20, 0x00, 0x2e, 0x8a, 0xef, 0xf0, 0x5f, - 0xa4, 0x13, 0x06, 0x00, 0x20, 0x81, 0x45, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x80, 0x23, 0x4a, 0x86, 0xd2, 0x85, - 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x00, 0x1f, 0x4e, 0x85, 0xef, 0xf0, 0xbf, 0xf9, 0x93, 0x0a, 0x44, 0xc9, 0xb7, - 0x07, 0x08, 0x05, 0x23, 0x9e, 0x2a, 0x1f, 0x13, 0x07, 0x44, 0xc9, 0x93, 0x86, 0x07, 0x20, 0x10, 0x43, 0x11, 0x07, - 0x90, 0xc3, 0x91, 0x07, 0xe3, 0x9c, 0xd7, 0xfe, 0x13, 0x06, 0x00, 0x20, 0x81, 0x45, 0x13, 0x05, 0x44, 0xc9, 0xef, - 0x20, 0x80, 0x1f, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x97, 0x20, 0x31, 0x45, 0xef, 0xf0, 0x1f, 0xaa, 0x93, 0x07, - 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x69, 0x8d, 0x45, 0xef, 0xe0, 0x1f, - 0xd8, 0x13, 0x05, 0x50, 0x05, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, - 0xfa, 0x17, 0x92, 0xcc, 0xb6, 0x56, 0x95, 0x0c, 0xe8, 0xd7, 0xe2, 0x7d, 0x65, 0x79, 0xc1, 0x8c, 0x55, 0xb2, 0x5f, - 0x86, 0xc8, 0xce, 0x43, 0xf4, 0x79, 0xaf, 0x8f, 0x0a, 0x93, 0x35, 0x6b, 0x86, 0x32, 0x00, 0x36, 0x05, 0x61, 0x82, - 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xeb, 0xa7, 0x02, 0x41, 0x11, 0x22, 0xc4, - 0x06, 0xc6, 0x93, 0x77, 0xf5, 0x1f, 0x2a, 0x84, 0x89, 0xef, 0xef, 0xf0, 0xdf, 0x99, 0xb7, 0x07, 0x08, 0x05, 0x23, - 0xac, 0x87, 0x20, 0x22, 0x44, 0xb2, 0x40, 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x1f, 0xa4, 0xb2, 0x40, 0x22, 0x44, - 0x13, 0x05, 0x50, 0x05, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, - 0xc6, 0x37, 0x04, 0x08, 0x05, 0x23, 0x2c, 0xa4, 0x20, 0xef, 0xf0, 0x5f, 0x96, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, - 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf6, 0xb7, 0xb7, 0xaa, 0x02, 0x93, 0x87, 0x67, 0xaa, 0xb2, 0x40, 0x23, 0x24, 0xf4, - 0x20, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xdf, 0x93, 0xb7, 0x37, 0x20, 0x00, - 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf6, 0xb2, 0x40, 0xb7, 0xb7, 0xa6, 0x02, 0x37, 0x07, 0x08, 0x05, 0x93, - 0x87, 0xa7, 0xaa, 0x23, 0x24, 0xf7, 0x20, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x3e, 0xcc, 0xb7, 0x07, 0x08, 0x05, - 0x3a, 0xce, 0x03, 0xa7, 0xc7, 0x20, 0x36, 0xd0, 0xb7, 0x06, 0x40, 0x00, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, - 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, - 0x75, 0x8f, 0x05, 0xcf, 0xfa, 0xb4, 0x26, 0x29, 0xb7, 0xc2, 0x32, 0xd8, 0x10, 0x6c, 0x29, 0xef, 0x4e, 0x89, 0x8c, - 0x15, 0xb9, 0x60, 0xc4, 0x98, 0x16, 0x49, 0xb8, 0xf8, 0x21, 0x0c, 0xd1, 0x85, 0x81, 0xaf, 0x32, 0xda, 0xcc, 0xd8, - 0x36, 0x23, 0xa6, 0xd7, 0x20, 0x13, 0x07, 0xa0, 0x0a, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0xe7, 0xf6, 0xf2, 0x50, - 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, - 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x03, 0xa7, - 0xc7, 0x20, 0xb7, 0x06, 0x00, 0x08, 0x37, 0x55, 0x10, 0x00, 0x75, 0x8f, 0x0d, 0xc3, 0x23, 0xa6, 0xd7, 0x20, 0x85, - 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, 0x3f, 0xc4, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xae, - 0xe7, 0xf6, 0xef, 0xd0, 0x1f, 0xbf, 0x75, 0xb7, 0x89, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, 0x7f, 0xc2, 0xb7, - 0x07, 0x02, 0x00, 0x73, 0xb0, 0x47, 0x30, 0xe5, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa0, - 0xe7, 0xf8, 0x82, 0x80, 0x99, 0x47, 0x63, 0x05, 0xf5, 0x02, 0x9d, 0x47, 0x63, 0x0b, 0xf5, 0x00, 0x95, 0x47, 0x63, - 0x15, 0xf5, 0x02, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xf7, 0xf7, 0xf7, 0x29, 0xa8, 0xb7, 0x37, 0x20, 0x00, - 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa0, 0xe7, 0xf8, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xe7, 0x07, - 0x08, 0x7c, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf8, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, - 0xf7, 0x00, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0xfa, 0x1d, 0xef, 0x8a, 0xc6, 0xb0, 0x1e, 0x0d, 0x22, 0xa7, 0x33, - 0x28, 0x0d, 0x25, 0xf1, 0x25, 0x22, 0x9a, 0xaf, 0xa1, 0x7e, 0x90, 0xba, 0x18, 0xb0, 0xf7, 0x2c, 0xbf, 0x7b, 0x9e, - 0x3a, 0x52, 0x76, 0xb0, 0x37, 0x93, 0xe7, 0x07, 0x08, 0x7c, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, - 0x07, 0xf8, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, 0xf7, 0x00, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xf7, 0xf7, - 0xf7, 0x7c, 0xc3, 0x82, 0x80, 0x39, 0x71, 0x2a, 0xd6, 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, 0x13, 0x05, 0xc5, 0x69, - 0x85, 0x45, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, - 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0x9f, 0xb6, 0xef, 0xd0, 0x3f, 0xb2, - 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, - 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, - 0x39, 0x71, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x3a, - 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xf3, 0x25, 0x20, 0x34, - 0xc1, 0x67, 0x37, 0x55, 0x10, 0x00, 0xdd, 0x8d, 0x13, 0x05, 0xc5, 0x69, 0xef, 0xe0, 0x9f, 0xb0, 0xef, 0xd0, 0x3f, - 0xac, 0x01, 0xa0, 0x39, 0x71, 0x2a, 0xd6, 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, 0x13, 0x05, 0xc5, 0x69, 0x89, 0x45, - 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, 0x36, 0xd0, 0xfa, 0x58, 0xb2, 0xe1, 0xe7, 0x50, 0x6e, - 0xd5, 0xd4, 0x3a, 0xdc, 0x7d, 0x80, 0x37, 0xd2, 0x06, 0xea, 0xb3, 0x35, 0xb0, 0x7e, 0xef, 0x45, 0x2f, 0x2c, 0x3e, - 0xd9, 0x53, 0x37, 0x57, 0x19, 0x76, 0x9c, 0x88, 0x38, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, - 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0x3f, 0xad, 0xef, 0xd0, 0xdf, 0xa8, 0xf2, 0x50, 0xe2, 0x52, 0x52, - 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, - 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x07, 0x01, 0x01, 0xb7, - 0x07, 0x00, 0x01, 0x13, 0x07, 0x17, 0x10, 0x98, 0xd3, 0x37, 0x07, 0x03, 0x04, 0x09, 0x07, 0xd8, 0xd3, 0x13, 0x07, - 0x50, 0x60, 0x98, 0xd7, 0x37, 0x17, 0x09, 0x00, 0x13, 0x07, 0x77, 0x80, 0xd8, 0xd7, 0x37, 0x17, 0x0b, 0x0b, 0x13, - 0x07, 0xa7, 0xa0, 0x98, 0xdb, 0x37, 0x17, 0x0c, 0x00, 0x13, 0x07, 0xb7, 0xc0, 0xd8, 0xdb, 0x37, 0x17, 0x0f, 0x00, - 0x13, 0x07, 0xd7, 0xe0, 0x98, 0xdf, 0x05, 0x67, 0xd8, 0xdf, 0xb7, 0x17, 0xff, 0x7f, 0x93, 0x87, 0x07, 0x80, 0x73, - 0xa0, 0x47, 0x30, 0xa1, 0x47, 0x73, 0xa0, 0x07, 0x30, 0x82, 0x80, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x40, 0x00, - 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x80, - 0x00, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, - 0x00, 0x04, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0xfa, 0x8c, 0xa9, - 0xb2, 0x78, 0xbc, 0xb3, 0x9a, 0x79, 0x97, 0xc2, 0x73, 0xbf, 0xc4, 0x6b, 0x14, 0x89, 0xea, 0xf2, 0xba, 0x44, 0xaf, - 0x2e, 0xeb, 0x9c, 0x1c, 0xd4, 0x53, 0xda, 0x89, 0x57, 0xea, 0xcc, 0x60, 0x39, 0x3e, 0xc6, 0xb7, 0x07, 0x00, 0x20, - 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x05, 0x65, 0x6f, 0x10, 0xa0, 0x54, 0x05, - 0x65, 0x6f, 0x10, 0x00, 0x55, 0x01, 0x11, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x06, 0xce, 0x26, 0xca, 0x52, 0xc4, - 0x56, 0xc2, 0x9d, 0x47, 0x2a, 0x84, 0xae, 0x89, 0x32, 0x89, 0x63, 0xd4, 0xc7, 0x00, 0xef, 0xd0, 0x2f, 0xae, 0xef, - 0xf0, 0x5f, 0xfd, 0xb7, 0x07, 0x01, 0x07, 0x18, 0x40, 0xdc, 0x43, 0x93, 0x06, 0xf0, 0x0f, 0x63, 0x05, 0xd7, 0x00, - 0xf1, 0x9b, 0x0d, 0x8b, 0xd9, 0x8f, 0x13, 0xf7, 0xb7, 0xff, 0x83, 0x47, 0x44, 0x00, 0x81, 0x44, 0x31, 0x4a, 0x8a, - 0x07, 0x91, 0x8b, 0xd9, 0x8f, 0x37, 0x07, 0x01, 0x07, 0x5c, 0xc3, 0xb7, 0x1a, 0x01, 0x07, 0x63, 0xcf, 0x24, 0x03, - 0x14, 0x40, 0x05, 0x47, 0xad, 0x47, 0x63, 0x9e, 0xe6, 0x00, 0x83, 0x46, 0x44, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0xbd, - 0x47, 0x63, 0x97, 0xe6, 0x00, 0x14, 0x44, 0x37, 0x37, 0x20, 0x00, 0x23, 0x22, 0xd7, 0xf8, 0xf2, 0x40, 0x62, 0x44, - 0x37, 0x07, 0x01, 0x07, 0x5c, 0xc7, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, - 0x80, 0xb3, 0x85, 0x44, 0x03, 0x13, 0x95, 0x44, 0x00, 0x31, 0x46, 0x56, 0x95, 0x85, 0x04, 0xce, 0x95, 0xef, 0xf0, - 0xcf, 0x81, 0x7d, 0xb7, 0x1d, 0x71, 0x3e, 0xda, 0xb7, 0x07, 0x01, 0x07, 0xa2, 0xc6, 0x80, 0x47, 0x86, 0xce, 0x96, - 0xcc, 0xfa, 0xd3, 0x39, 0xdd, 0x0d, 0x4c, 0xcf, 0x07, 0x11, 0xa2, 0xf6, 0x29, 0x3f, 0xf1, 0x6d, 0x91, 0x0d, 0x79, - 0x86, 0x3c, 0xbd, 0xc5, 0x90, 0x68, 0xf7, 0xe3, 0xe8, 0x1a, 0x83, 0x65, 0x5c, 0x07, 0x2c, 0x38, 0x3a, 0x9a, 0xca, - 0x9e, 0xc8, 0xaa, 0xc4, 0xae, 0xc2, 0xb2, 0xc0, 0x36, 0xde, 0x3a, 0xdc, 0x42, 0xd8, 0x46, 0xd6, 0x72, 0xd4, 0x76, - 0xd2, 0x7a, 0xd0, 0x7e, 0xce, 0x93, 0x77, 0xb4, 0x00, 0x95, 0xc7, 0xb7, 0x07, 0x00, 0x40, 0x73, 0xb0, 0x47, 0x30, - 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0xa2, 0x86, 0x13, 0x06, 0x06, 0x6a, 0x93, - 0x85, 0x85, 0x6a, 0x13, 0x05, 0x45, 0x64, 0xef, 0xe0, 0xbf, 0x87, 0xef, 0xd0, 0xbf, 0x8a, 0x93, 0x77, 0x44, 0x00, - 0x99, 0xcf, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf8, 0x91, 0xcb, 0x6c, 0x00, 0x28, 0x00, 0x82, 0x97, 0x22, - 0x47, 0xb7, 0x07, 0x01, 0x07, 0x98, 0xcb, 0x32, 0x47, 0xd8, 0xcb, 0xb7, 0x07, 0x01, 0x07, 0x80, 0xc7, 0x36, 0x44, - 0xf6, 0x40, 0xe6, 0x42, 0x56, 0x43, 0xc6, 0x43, 0x26, 0x45, 0x96, 0x45, 0x06, 0x46, 0xf2, 0x56, 0x62, 0x57, 0xd2, - 0x57, 0x42, 0x58, 0xb2, 0x58, 0x22, 0x5e, 0x92, 0x5e, 0x02, 0x5f, 0xf2, 0x4f, 0x25, 0x61, 0x73, 0x00, 0x20, 0x30, - 0xb7, 0x07, 0x02, 0x04, 0xdc, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, - 0x80, 0x13, 0x05, 0x00, 0x08, 0x6f, 0x10, 0x40, 0x3d, 0x13, 0x05, 0x00, 0x08, 0x6f, 0x10, 0x80, 0x3d, 0x41, 0x11, - 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x07, 0xd0, 0x79, 0x37, 0x04, 0x02, 0x04, 0x5c, 0xc4, 0x85, 0x44, 0x95, - 0x65, 0x37, 0x35, 0x10, 0x00, 0xfa, 0x72, 0x97, 0x86, 0xd0, 0xf1, 0x8f, 0x3b, 0x47, 0x1d, 0x7c, 0x3e, 0x8b, 0xc9, - 0xc4, 0xa0, 0x20, 0x2e, 0x30, 0x23, 0x47, 0x9a, 0x07, 0xeb, 0x76, 0x20, 0xd3, 0x0b, 0xdd, 0x58, 0xfa, 0x02, 0xfc, - 0x10, 0x3b, 0x04, 0xc4, 0x93, 0x85, 0x05, 0xe2, 0x13, 0x05, 0x25, 0x6d, 0xef, 0xe0, 0x7f, 0xca, 0x93, 0x07, 0xa0, - 0x0a, 0x63, 0x13, 0xf5, 0x02, 0x54, 0x44, 0x63, 0x82, 0x96, 0x02, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, - 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x6a, 0x93, 0x85, 0x45, 0x6b, 0x13, 0x05, 0x05, 0x62, 0xef, 0xe0, 0x0f, - 0xfb, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, - 0xef, 0xf0, 0xdf, 0xf8, 0xb2, 0x40, 0xb7, 0x07, 0x02, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x41, - 0x11, 0x05, 0x45, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xef, 0xe0, 0x3f, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, - 0xa0, 0x0a, 0x23, 0xa4, 0xe7, 0xf8, 0x89, 0x46, 0x37, 0x07, 0x02, 0x02, 0x54, 0xc7, 0x13, 0x84, 0x87, 0xf8, 0x93, - 0x04, 0x50, 0x05, 0xef, 0xe0, 0x9f, 0xc2, 0x1c, 0x40, 0xe3, 0x9d, 0x97, 0xfe, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, - 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x02, 0x02, 0xc8, 0xcb, 0x05, 0x47, 0xd8, 0xc7, 0xd8, 0x53, 0x69, 0x8f, 0x63, - 0x1e, 0xa7, 0x00, 0xd4, 0x57, 0x7d, 0x55, 0xf9, 0x8e, 0x91, 0xea, 0x94, 0x57, 0x75, 0x8f, 0x19, 0xe7, 0x88, 0x47, - 0x05, 0x89, 0x33, 0x05, 0xa0, 0x40, 0x82, 0x80, 0x7d, 0x55, 0x82, 0x80, 0x41, 0x45, 0x6f, 0x10, 0x00, 0x2f, 0x41, - 0x45, 0x6f, 0x10, 0xe0, 0x2d, 0x01, 0x11, 0x06, 0xce, 0xfa, 0x5a, 0xdb, 0x7a, 0x09, 0x77, 0x12, 0x81, 0xe8, 0xb1, - 0x79, 0x65, 0x13, 0xe5, 0xa8, 0xf7, 0xf6, 0x4e, 0xc5, 0xd0, 0x71, 0x6d, 0x9f, 0xd4, 0xc0, 0xa5, 0x28, 0xb9, 0x29, - 0x5d, 0x29, 0xe3, 0x7c, 0xe8, 0x3b, 0x22, 0xcc, 0x2a, 0xc6, 0xef, 0xf0, 0x3f, 0xff, 0x13, 0x07, 0x50, 0x05, 0xb7, - 0x37, 0x20, 0x00, 0x23, 0xa4, 0xe7, 0xf8, 0x37, 0x04, 0x02, 0x02, 0xa1, 0x47, 0x5c, 0xc4, 0x32, 0x45, 0x85, 0x47, - 0x1c, 0xc8, 0x93, 0x07, 0x10, 0x40, 0x5c, 0xc0, 0xef, 0xf0, 0xbf, 0xf9, 0xef, 0xf0, 0x9f, 0xf5, 0x23, 0x22, 0x04, - 0x00, 0x62, 0x44, 0xf2, 0x40, 0x05, 0x61, 0x6f, 0xf0, 0x7f, 0xfb, 0x41, 0x11, 0x3a, 0xc6, 0x37, 0x07, 0x02, 0x02, - 0x3e, 0xc4, 0x1c, 0x47, 0x1c, 0xc7, 0x85, 0x8b, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, - 0xa4, 0xe7, 0xf8, 0x32, 0x47, 0xa2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, - 0xc7, 0xf8, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x99, 0xc3, 0xef, - 0xd0, 0x6f, 0x81, 0x89, 0x67, 0x63, 0x64, 0xf4, 0x00, 0xef, 0xd0, 0xcf, 0x80, 0x37, 0x27, 0x00, 0x06, 0x85, 0x46, - 0x09, 0x46, 0x1c, 0x47, 0x9d, 0x8b, 0x63, 0x86, 0xd7, 0x00, 0x1c, 0x47, 0x9d, 0x8b, 0xe3, 0x9a, 0xc7, 0xfe, 0x37, - 0x05, 0x00, 0x06, 0x2a, 0x94, 0x08, 0x40, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x65, 0xb7, 0x37, - 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x41, 0x11, 0x13, 0x05, 0x05, 0x80, 0x23, 0xa6, 0xe7, 0xf8, 0x06, 0xc6, 0xef, - 0x10, 0xc0, 0x20, 0xb7, 0x27, 0x00, 0x06, 0x9c, 0x47, 0x05, 0x47, 0x9d, 0x8b, 0xfa, 0xce, 0xbf, 0x98, 0xb9, 0x2c, - 0xe4, 0xa9, 0xc0, 0x33, 0xc1, 0x50, 0x40, 0x2f, 0x2c, 0x1d, 0x3a, 0xcf, 0x61, 0xfa, 0xde, 0x2b, 0x3d, 0xb3, 0xbe, - 0xd9, 0x1f, 0xa4, 0xf9, 0x07, 0x0c, 0x82, 0x1c, 0xc0, 0x3c, 0xfd, 0x17, 0x63, 0x7b, 0xf7, 0x00, 0x37, 0x55, 0x10, - 0x00, 0x89, 0x45, 0x13, 0x05, 0x85, 0x6b, 0xef, 0xe0, 0xaf, 0xe9, 0xef, 0xc0, 0x9f, 0xfa, 0xb7, 0x07, 0x46, 0x00, - 0xb2, 0x40, 0x37, 0x27, 0x00, 0x06, 0x85, 0x07, 0x5c, 0xcf, 0x85, 0x47, 0x5c, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x37, - 0x27, 0x00, 0x06, 0x1c, 0x47, 0x85, 0x46, 0x9d, 0x8b, 0x63, 0x8a, 0xd7, 0x00, 0x14, 0xcb, 0xb7, 0x26, 0x00, 0x06, - 0x05, 0x47, 0x9c, 0x46, 0x9d, 0x8b, 0xe3, 0x9e, 0xe7, 0xfe, 0xb7, 0x27, 0x00, 0x06, 0x09, 0x47, 0x05, 0x65, 0x98, - 0xcb, 0x13, 0x05, 0x05, 0x80, 0x6f, 0x10, 0x00, 0x1b, 0x05, 0x65, 0x41, 0x11, 0x13, 0x05, 0x05, 0x80, 0x06, 0xc6, - 0xef, 0x10, 0x60, 0x19, 0xb2, 0x40, 0xb7, 0x27, 0x00, 0x06, 0x21, 0x47, 0x98, 0xcb, 0x41, 0x01, 0x82, 0x80, 0x41, - 0x11, 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0xaa, 0x84, 0xef, 0xf0, 0x5f, 0xf1, 0x2a, 0x84, 0x49, 0x22, 0x13, 0x75, - 0xf5, 0x0f, 0xef, 0xe0, 0x1f, 0xa6, 0x26, 0x85, 0xef, 0xf0, 0x3f, 0xf0, 0x63, 0x05, 0xa4, 0x00, 0xef, 0xc0, 0xff, - 0xf1, 0x01, 0x45, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, - 0x4a, 0xd0, 0x4e, 0xce, 0x06, 0xd6, 0x52, 0xcc, 0xaa, 0x89, 0x2e, 0x89, 0x93, 0x74, 0xc6, 0xff, 0x01, 0x44, 0x33, - 0x8a, 0x89, 0x00, 0x33, 0x05, 0x89, 0x00, 0x63, 0x1a, 0x94, 0x00, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0xfa, 0x05, - 0x16, 0x0b, 0x27, 0x9c, 0xbd, 0xa0, 0x19, 0x42, 0x49, 0x9b, 0x1a, 0x08, 0x98, 0xc5, 0xb5, 0x39, 0x66, 0x19, 0x4c, - 0x8f, 0x62, 0xce, 0x88, 0x12, 0x33, 0x6a, 0x68, 0x93, 0x78, 0x94, 0x7c, 0x98, 0x3d, 0x02, 0x59, 0xf2, 0x49, 0x62, - 0x4a, 0x45, 0x61, 0x82, 0x80, 0xef, 0xf0, 0x9f, 0xf9, 0x2a, 0xc6, 0x11, 0x46, 0x6c, 0x00, 0x52, 0x85, 0xef, 0x10, - 0x50, 0x1d, 0x11, 0x04, 0xc9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x1f, 0xf8, 0x2a, 0x87, 0x85, 0x46, 0x01, - 0x45, 0x89, 0x45, 0x01, 0xe7, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x93, 0x77, 0xf7, 0x00, 0x01, 0x46, 0x81, 0xef, - 0x63, 0xd3, 0xc5, 0x00, 0xb6, 0x87, 0x5d, 0x8d, 0x86, 0x06, 0x13, 0x75, 0xf5, 0x0f, 0x93, 0xf6, 0xf6, 0x0f, 0x11, - 0x83, 0xf1, 0xbf, 0x13, 0xf8, 0x17, 0x00, 0x85, 0x83, 0x42, 0x96, 0x93, 0xf7, 0xf7, 0x0f, 0xf1, 0xbf, 0x41, 0x11, - 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0xae, 0x84, 0x99, 0xc3, 0xef, 0xc0, 0x1f, - 0xe7, 0x89, 0x67, 0x63, 0x64, 0xf4, 0x00, 0xef, 0xc0, 0x7f, 0xe6, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, - 0x23, 0xa6, 0xe7, 0xf8, 0xb7, 0x27, 0x00, 0x06, 0x84, 0xcf, 0xc0, 0xcb, 0x22, 0x44, 0xb2, 0x40, 0x92, 0x44, 0x11, - 0x47, 0x98, 0xcb, 0x89, 0x65, 0x37, 0x45, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0xe5, 0x84, 0x41, 0x01, - 0x6f, 0xe0, 0xdf, 0xa4, 0x39, 0x71, 0x3a, 0xce, 0x37, 0x27, 0x00, 0x06, 0x3e, 0xcc, 0x1c, 0x47, 0x06, 0xde, 0x16, - 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, - 0x76, 0xc4, 0xfa, 0x4d, 0x54, 0xef, 0xad, 0xc7, 0xa3, 0x35, 0x08, 0x61, 0xdd, 0xa8, 0xe0, 0xa3, 0xb3, 0xb5, 0x4c, - 0x0e, 0xb9, 0xfe, 0x2c, 0xba, 0xb6, 0x89, 0x47, 0xbe, 0xef, 0xa3, 0x71, 0xbf, 0xa7, 0x87, 0xf0, 0x70, 0x3e, 0x7a, - 0xc2, 0x7e, 0xc0, 0xa1, 0x8b, 0x85, 0xcf, 0xa1, 0x47, 0x1c, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, - 0x23, 0xa6, 0xe7, 0xf8, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, - 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, - 0x73, 0x00, 0x20, 0x30, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x85, 0x6b, 0xef, 0xe0, 0x2f, 0xcb, 0xef, - 0xd0, 0xcf, 0xc6, 0xe1, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa8, 0xa7, 0xf8, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, - 0x93, 0x87, 0x07, 0xf9, 0x88, 0x43, 0x37, 0x67, 0x19, 0x00, 0x13, 0x07, 0xd7, 0x60, 0x33, 0x05, 0xe5, 0x02, 0x37, - 0xf7, 0x6e, 0x3c, 0x13, 0x07, 0xf7, 0x35, 0x3a, 0x95, 0x88, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, - 0x47, 0xf9, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0x87, 0xf9, 0x9c, 0x4f, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x37, - 0x37, 0x20, 0x00, 0x03, 0x27, 0xc7, 0xf9, 0x63, 0x84, 0xe7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xfd, 0x77, - 0xfd, 0x17, 0xe9, 0x8f, 0xb7, 0x26, 0x00, 0x08, 0x2e, 0x87, 0xb2, 0x85, 0x63, 0x94, 0xd7, 0x02, 0xb7, 0x37, 0x20, - 0x00, 0x23, 0xaa, 0xa7, 0xf8, 0xb7, 0x37, 0x20, 0x00, 0x37, 0x45, 0x10, 0x00, 0x23, 0xae, 0xe7, 0xf8, 0x13, 0x05, - 0x05, 0xaf, 0xb7, 0x37, 0x20, 0x00, 0xfa, 0x3c, 0x34, 0xa4, 0xc5, 0x1c, 0x8d, 0x12, 0xe6, 0x65, 0x41, 0x5e, 0x8c, - 0x49, 0xe6, 0x5a, 0xb2, 0x30, 0x94, 0xc5, 0x35, 0x93, 0xab, 0x6d, 0x8d, 0x65, 0xb2, 0xe5, 0xf7, 0x68, 0x18, 0x4a, - 0x8f, 0x48, 0x3f, 0x23, 0xac, 0xe7, 0xf8, 0x6f, 0xe0, 0x5f, 0x87, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, - 0x20, 0x00, 0x23, 0xaa, 0xa7, 0xf8, 0xb7, 0x37, 0x20, 0x00, 0x37, 0x45, 0x10, 0x00, 0x23, 0xae, 0x07, 0xf8, 0x13, - 0x07, 0x00, 0x10, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x05, 0x80, 0x3e, 0x13, 0x05, 0x05, 0xaf, 0x23, 0xac, 0xe7, 0xf8, - 0x6f, 0xe0, 0x3f, 0x84, 0x37, 0x07, 0x01, 0x02, 0x5c, 0x43, 0xb7, 0x06, 0x05, 0x00, 0xd5, 0x8f, 0x5c, 0xc3, 0x82, - 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0xb7, 0x27, 0x00, 0x08, 0x37, 0x05, 0x08, 0x00, 0x63, 0x14, - 0xf4, 0x00, 0x37, 0x05, 0x04, 0x00, 0xef, 0x00, 0x50, 0x71, 0x5c, 0x5c, 0x22, 0x85, 0xb2, 0x40, 0x93, 0xe7, 0x37, - 0x00, 0x5c, 0xdc, 0x23, 0x2c, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0x5f, 0xf9, 0x58, 0x5d, 0xaa, 0x87, - 0x75, 0x9b, 0x58, 0xdd, 0x37, 0x27, 0x00, 0x08, 0x37, 0x05, 0x04, 0x00, 0x63, 0x84, 0xe7, 0x00, 0x37, 0x05, 0x08, - 0x00, 0x6f, 0x00, 0xd0, 0x6e, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x06, 0xd6, 0x4e, 0xce, 0x52, 0xcc, - 0x56, 0xca, 0x2a, 0x89, 0xae, 0x84, 0x32, 0x84, 0x99, 0xe1, 0xef, 0xc0, 0x3f, 0xc8, 0x13, 0x0a, 0xa0, 0x0a, 0x91, - 0x4a, 0x05, 0xe4, 0x83, 0x27, 0x89, 0x01, 0x37, 0x07, 0x11, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x99, 0xc3, - 0x13, 0x05, 0x50, 0x05, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0xfa, 0xc8, 0xad, 0x53, 0x66, 0x47, 0xe0, 0x33, 0x5d, - 0x3d, 0xca, 0x5c, 0x56, 0xb7, 0x62, 0x0c, 0x4e, 0x11, 0xad, 0x71, 0x96, 0x1c, 0xa7, 0x76, 0x17, 0x6e, 0x57, 0x29, - 0x10, 0x37, 0x89, 0xa9, 0x92, 0x20, 0x40, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0xd2, 0x4a, 0x45, 0x61, 0x82, 0x80, - 0x13, 0x06, 0x80, 0x3e, 0x85, 0x45, 0x4a, 0x85, 0xef, 0xf0, 0x7f, 0xee, 0xe3, 0x1f, 0x45, 0xfd, 0x83, 0x27, 0x49, - 0x02, 0xa2, 0x89, 0x3e, 0xc6, 0x63, 0xf3, 0x8a, 0x00, 0x91, 0x49, 0x26, 0x85, 0x4e, 0x86, 0x6c, 0x00, 0xef, 0x10, - 0x20, 0x73, 0xce, 0x94, 0x33, 0x04, 0x34, 0x41, 0x6d, 0xb7, 0x41, 0x11, 0x37, 0x05, 0x02, 0x00, 0x06, 0xc6, 0xef, - 0x00, 0xb0, 0x65, 0xb2, 0x40, 0xb7, 0x17, 0x00, 0x08, 0x37, 0x07, 0x07, 0x00, 0x98, 0xd3, 0x13, 0x05, 0x40, 0x1f, - 0x41, 0x01, 0x6f, 0xe0, 0xef, 0xee, 0xb7, 0x17, 0x00, 0x08, 0x23, 0xa0, 0x07, 0x02, 0x37, 0x05, 0x02, 0x00, 0x6f, - 0x00, 0x10, 0x64, 0x39, 0x71, 0x3e, 0xcc, 0xb7, 0x17, 0x00, 0x08, 0x3a, 0xce, 0x98, 0x57, 0x06, 0xde, 0x16, 0xdc, - 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, - 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0x05, 0x8b, 0x05, 0xcb, 0x98, 0x57, 0x13, 0x67, 0x17, 0x00, 0x98, 0xd7, 0xf2, 0x50, - 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, - 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x98, 0x57, - 0x09, 0x8b, 0x09, 0xc7, 0x98, 0x57, 0x13, 0x67, 0x27, 0x00, 0xf1, 0xb7, 0x98, 0x57, 0xfa, 0x48, 0x72, 0x90, 0x10, - 0x25, 0x85, 0x9c, 0xd6, 0x23, 0x79, 0xb8, 0xde, 0xe2, 0xbd, 0xc2, 0x74, 0xfe, 0xe0, 0x63, 0x22, 0x49, 0xf6, 0x73, - 0x23, 0x66, 0xba, 0x78, 0x98, 0xf8, 0x11, 0xf2, 0x26, 0xf8, 0x40, 0x11, 0x8b, 0x09, 0xc7, 0x98, 0x57, 0x13, 0x67, - 0x47, 0x00, 0x7d, 0xbf, 0xb7, 0x07, 0x00, 0x01, 0x73, 0xb0, 0x47, 0x30, 0xef, 0xd0, 0xcf, 0xa1, 0x4d, 0xbf, 0x37, - 0x07, 0x00, 0x02, 0x5c, 0x4f, 0xb7, 0x36, 0x20, 0x00, 0x13, 0xf6, 0x77, 0x00, 0xe1, 0x9b, 0x23, 0xa0, 0xc6, 0xfa, - 0x93, 0xe7, 0x47, 0x00, 0x5c, 0xcf, 0x1c, 0x4f, 0xf9, 0x9b, 0x1c, 0xcf, 0x82, 0x80, 0x41, 0x11, 0x26, 0xc2, 0xb7, - 0x04, 0x00, 0x02, 0x22, 0xc4, 0xc0, 0x4c, 0x9c, 0x4c, 0x06, 0xc6, 0x13, 0x05, 0x80, 0x07, 0x93, 0xe7, 0x17, 0x00, - 0x9c, 0xcc, 0xef, 0xe0, 0xaf, 0xe1, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xfa, 0x61, 0x98, 0xb2, 0x40, 0x5d, - 0x8c, 0xc0, 0xcc, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x17, 0x05, 0x01, 0x93, 0x17, 0x85, 0x01, - 0xba, 0x97, 0x13, 0x17, 0x85, 0x00, 0xba, 0x97, 0x3e, 0x95, 0xb7, 0x07, 0x00, 0x04, 0x88, 0xd3, 0xc8, 0xd3, 0x88, - 0xd7, 0xc8, 0xd7, 0x88, 0xdb, 0xc8, 0xdb, 0x88, 0xdf, 0xc8, 0xdf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, - 0x00, 0x08, 0x98, 0xd3, 0x23, 0xa2, 0x07, 0x02, 0x0e, 0x05, 0x23, 0xa4, 0x07, 0x02, 0x42, 0x05, 0x23, 0xa6, 0x07, - 0x02, 0x41, 0x81, 0x23, 0xa8, 0x07, 0x02, 0x13, 0x17, 0x85, 0x00, 0xb7, 0x06, 0xff, 0x00, 0x23, 0xaa, 0x07, 0x02, - 0x75, 0x8f, 0x62, 0x05, 0x23, 0xac, 0x07, 0x02, 0x3a, 0x95, 0xc8, 0xdf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0xfa, - 0x58, 0x79, 0x18, 0x78, 0xc7, 0x7c, 0x01, 0x3c, 0x5e, 0xe8, 0x38, 0xbe, 0xce, 0x54, 0x22, 0x87, 0xbf, 0xcf, 0x2e, - 0x05, 0x05, 0x63, 0xc6, 0xf4, 0xf7, 0xae, 0x01, 0x21, 0x65, 0xf5, 0xb3, 0xc1, 0xd0, 0x41, 0x13, 0x07, 0x00, 0x08, - 0x98, 0xd3, 0x23, 0xa2, 0x07, 0x02, 0x23, 0xa4, 0x07, 0x02, 0x23, 0xa6, 0x07, 0x02, 0x23, 0xa8, 0x07, 0x02, 0x23, - 0xaa, 0x07, 0x02, 0x23, 0xac, 0x07, 0x02, 0x23, 0xae, 0x07, 0x02, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, - 0x47, 0xea, 0x82, 0x80, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0x6f, - 0xe0, 0x3f, 0x83, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa2, 0xe7, 0xea, 0xb7, 0x07, 0x00, 0x04, - 0xc8, 0xc3, 0x13, 0x07, 0x90, 0x02, 0x85, 0x65, 0x37, 0x45, 0x10, 0x00, 0x98, 0xc7, 0x93, 0x85, 0x85, 0x38, 0x13, - 0x05, 0x45, 0xdf, 0x6f, 0xe0, 0xaf, 0xd8, 0x41, 0x11, 0x22, 0xc4, 0x01, 0x45, 0x37, 0x34, 0x20, 0x00, 0x06, 0xc6, - 0x13, 0x04, 0x44, 0xe9, 0xef, 0xf0, 0x1f, 0xf2, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, - 0xfb, 0x48, 0x44, 0xb7, 0x07, 0x02, 0x00, 0x95, 0x07, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0xbf, 0xfa, 0x48, 0x44, - 0x7e, 0x05, 0x13, 0x65, 0x05, 0x05, 0xef, 0xf0, 0xff, 0xf9, 0x48, 0x44, 0xb7, 0x07, 0x00, 0x10, 0x99, 0x07, 0x7e, - 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0xff, 0xf8, 0x48, 0x44, 0xb7, 0x07, 0x01, 0x10, 0x99, 0x07, 0x7e, 0x05, 0x5d, 0x8d, - 0xef, 0xf0, 0xff, 0xf7, 0x22, 0x44, 0xb2, 0x40, 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0xf7, 0x7d, 0x47, 0x63, - 0x7e, 0xb7, 0x04, 0xfa, 0x2e, 0xb1, 0x66, 0xd9, 0xe7, 0x32, 0x03, 0x63, 0x15, 0x89, 0x6a, 0xae, 0xaf, 0x61, 0x6e, - 0x4b, 0x14, 0x27, 0x5f, 0x2a, 0x10, 0x4d, 0x94, 0x8e, 0x13, 0xe1, 0x4a, 0x62, 0x0f, 0x2a, 0x56, 0xa0, 0xa8, 0x42, - 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0x6f, 0xe0, 0x8f, 0xf8, 0xb3, - 0x06, 0xf5, 0x00, 0x83, 0xc6, 0x06, 0x00, 0x33, 0x07, 0xf1, 0x00, 0x85, 0x07, 0x23, 0x00, 0xd7, 0x00, 0xe3, 0x97, - 0xf5, 0xfe, 0x18, 0x10, 0x93, 0x87, 0x15, 0x00, 0xba, 0x95, 0x13, 0x07, 0x00, 0xf8, 0x23, 0x80, 0xe5, 0xfe, 0x13, - 0x07, 0x00, 0x02, 0x63, 0x92, 0xe7, 0x02, 0x37, 0x05, 0x00, 0x04, 0x8a, 0x85, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, - 0x05, 0x02, 0xef, 0xe0, 0x8f, 0xf4, 0xb2, 0x50, 0x45, 0x61, 0x82, 0x80, 0x79, 0x71, 0x06, 0xd6, 0x81, 0x47, 0xd9, - 0xb7, 0xb3, 0x06, 0xf1, 0x00, 0x23, 0x80, 0x06, 0x00, 0x85, 0x07, 0xc9, 0xbf, 0x37, 0x55, 0x10, 0x00, 0x01, 0x11, - 0x13, 0x05, 0x45, 0x6c, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x37, 0x34, 0x20, - 0x00, 0xef, 0xf0, 0x1f, 0xed, 0x93, 0x07, 0x44, 0xe9, 0xc8, 0x47, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, - 0x3f, 0xed, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x10, 0xf5, 0x2e, 0xaa, 0x84, 0x13, 0x05, 0x00, 0x02, 0xef, 0xf0, 0x3f, - 0xe4, 0x13, 0x04, 0x44, 0xe9, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x1f, 0xeb, 0xaa, 0x89, - 0x63, 0x10, 0x95, 0x2c, 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0xbf, - 0xe9, 0xaa, 0x84, 0x63, 0x15, 0x35, 0x2b, 0xfa, 0x91, 0x2f, 0xf9, 0x87, 0xe2, 0x7b, 0x59, 0x78, 0x12, 0xf6, 0xbc, - 0xfb, 0xf6, 0x1d, 0x67, 0xf1, 0x41, 0xef, 0x8e, 0xca, 0xac, 0xdf, 0x01, 0x32, 0xda, 0x2c, 0x04, 0x5f, 0x4e, 0xd9, - 0x99, 0xe2, 0x80, 0x43, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x9f, 0xe8, 0xaa, 0x89, 0x63, - 0x1c, 0x95, 0x28, 0x1c, 0x40, 0x48, 0x44, 0x37, 0x0a, 0x00, 0x04, 0x83, 0xc7, 0x07, 0x00, 0x7e, 0x05, 0x13, 0x65, - 0x15, 0x00, 0x93, 0xe7, 0x07, 0x20, 0x23, 0x2c, 0xfa, 0x00, 0xef, 0xf0, 0x5f, 0xe6, 0xaa, 0x84, 0x63, 0x1a, 0x35, - 0x27, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x3f, 0xe5, 0x2a, 0x89, 0x63, 0x11, 0x95, 0x26, - 0xef, 0xf0, 0x5f, 0xe0, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xdf, 0xe3, 0xaa, 0x84, 0x63, - 0x16, 0x25, 0x25, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x1f, 0xdb, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, - 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xff, 0xe1, 0x2a, 0x89, 0x63, 0x17, 0x95, 0x22, 0x48, 0x44, 0x7e, 0x05, 0x13, - 0x65, 0x35, 0x00, 0xef, 0xf0, 0xdf, 0xe0, 0xaa, 0x84, 0x63, 0x1e, 0x25, 0x21, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, - 0x05, 0x02, 0xef, 0xf0, 0xbf, 0xdf, 0x63, 0x16, 0x95, 0x20, 0x48, 0x44, 0x93, 0x07, 0x00, 0x10, 0x23, 0x2c, 0xfa, - 0x00, 0x7e, 0x05, 0x13, 0x65, 0x15, 0x00, 0xef, 0xf0, 0x3f, 0xde, 0x93, 0x07, 0xa0, 0x0a, 0xaa, 0x84, 0x63, 0x17, - 0xf5, 0x1e, 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x9f, 0xdc, 0xaa, - 0x89, 0x63, 0x1c, 0x95, 0x1c, 0xef, 0xf0, 0xbf, 0xd7, 0x48, 0x44, 0xfa, 0xad, 0x15, 0x42, 0x2e, 0x51, 0xa3, 0x77, - 0x4c, 0x9e, 0xf4, 0x30, 0x0c, 0xf3, 0x41, 0xe0, 0x63, 0x94, 0x96, 0x7c, 0x6f, 0x27, 0x23, 0x04, 0x5f, 0xc5, 0xdc, - 0x31, 0x88, 0x65, 0x71, 0xcd, 0x50, 0x58, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x3f, 0xdb, 0xaa, - 0x84, 0x63, 0x11, 0x35, 0x1d, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x7f, 0xd2, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, - 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x5f, 0xd9, 0xaa, 0x89, 0x63, 0x12, 0x95, 0x1a, 0x48, 0x44, 0x7e, - 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x3f, 0xd8, 0xaa, 0x84, 0x63, 0x19, 0x35, 0x19, 0x48, 0x44, 0x7e, 0x05, - 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x1f, 0xd7, 0xaa, 0x89, 0x63, 0x10, 0x95, 0x18, 0x08, 0x40, 0x05, 0x05, 0xef, - 0xf0, 0x1f, 0xd5, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x7f, 0xd5, 0xaa, 0x84, 0x63, 0x13, - 0x35, 0x17, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x5f, 0xd4, 0x2a, 0x89, 0x63, 0x1a, 0x95, - 0x14, 0xef, 0xf0, 0x7f, 0xcf, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xff, 0xd2, 0xaa, 0x84, - 0x63, 0x1f, 0x25, 0x13, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x3f, 0xca, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, - 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x1f, 0xd1, 0x63, 0x11, 0x95, 0x12, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, - 0x35, 0x00, 0xef, 0xf0, 0x1f, 0xd0, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0x63, 0x16, 0xf5, 0x10, 0x48, 0x44, 0x7e, - 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xbf, 0xce, 0xaa, 0x84, 0x63, 0x1d, 0x25, 0x0f, 0xfa, 0x23, 0xe5, 0xdd, - 0xa6, 0x85, 0x7f, 0x95, 0xa3, 0x6e, 0xc6, 0x40, 0x79, 0x1c, 0x78, 0xd0, 0xdc, 0x84, 0xe8, 0x86, 0x8e, 0xd1, 0x76, - 0x71, 0x26, 0x42, 0x94, 0x88, 0x22, 0x67, 0xb1, 0x8a, 0xb8, 0x30, 0x45, 0x13, 0x05, 0x10, 0x02, 0xef, 0xf0, 0xff, - 0xc5, 0x1c, 0x40, 0x48, 0x44, 0x21, 0x67, 0x83, 0xc7, 0x07, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xd9, 0x8f, - 0x23, 0x20, 0xfa, 0x02, 0xef, 0xf0, 0x3f, 0xcc, 0xaa, 0x89, 0x63, 0x19, 0x95, 0x0c, 0x48, 0x44, 0x89, 0x64, 0x8d, - 0x04, 0x7e, 0x05, 0x45, 0x8d, 0xef, 0xf0, 0xff, 0xca, 0x2a, 0x89, 0x63, 0x1f, 0x35, 0x0b, 0x48, 0x44, 0x7e, 0x05, - 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xdf, 0xc9, 0xaa, 0x89, 0x63, 0x16, 0x25, 0x0b, 0x08, 0x40, 0x13, 0x05, 0x15, - 0x02, 0xef, 0xf0, 0xbf, 0xc7, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x1f, 0xc8, 0x2a, 0x89, - 0x63, 0x18, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, 0x45, 0x8d, 0xef, 0xf0, 0x1f, 0xc7, 0xaa, 0x84, 0x63, 0x10, 0x25, - 0x09, 0xef, 0xf0, 0x3f, 0xc2, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0xc5, 0x2a, 0x89, - 0x63, 0x15, 0x95, 0x06, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0xff, 0xbc, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, - 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xc3, 0xaa, 0x84, 0x63, 0x16, 0x25, 0x05, 0x48, 0x44, 0x7e, 0x05, - 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xbf, 0xc2, 0x63, 0x1e, 0x95, 0x02, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, - 0x52, 0xef, 0xf0, 0xbf, 0xc1, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x14, 0xf5, 0x02, 0x08, 0x40, 0x62, 0x44, 0xf2, 0x40, - 0xfa, 0x77, 0x91, 0xe4, 0x63, 0xc5, 0xd3, 0x00, 0xec, 0x07, 0x6d, 0x73, 0xd9, 0xbd, 0x73, 0xd9, 0x24, 0xea, 0x8f, - 0xd4, 0x98, 0x7f, 0x6e, 0xc0, 0xa3, 0x56, 0x6c, 0x79, 0x52, 0xa7, 0xe1, 0x5a, 0xb0, 0x08, 0x46, 0xd2, 0x44, 0x42, - 0x49, 0xb2, 0x49, 0x22, 0x4a, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x06, 0x13, 0x05, - 0x15, 0x06, 0x05, 0x61, 0x6f, 0xe0, 0x0f, 0xbb, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, - 0x4a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x4e, 0xc6, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x52, 0xc4, - 0x93, 0x09, 0x00, 0x04, 0x63, 0xeb, 0xb9, 0x08, 0x37, 0x3a, 0x20, 0x00, 0xaa, 0x84, 0x2e, 0x84, 0x13, 0x09, 0x4a, - 0xe9, 0xef, 0xf0, 0xbf, 0xc4, 0x03, 0x25, 0xc9, 0x00, 0x13, 0x0a, 0x4a, 0xe9, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, - 0xef, 0xf0, 0x7f, 0xba, 0x13, 0x85, 0x04, 0x02, 0x63, 0x19, 0x34, 0x03, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, - 0x05, 0x05, 0x02, 0x13, 0x06, 0x00, 0x02, 0xef, 0xe0, 0xaf, 0xbb, 0x03, 0x25, 0xc9, 0x00, 0x62, 0x44, 0xf2, 0x40, - 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0x05, 0x61, 0x6f, 0xf0, 0x1f, - 0xb7, 0xfd, 0x47, 0x63, 0xf8, 0x87, 0x02, 0x93, 0x05, 0x04, 0xfe, 0xef, 0xf0, 0x5f, 0xbf, 0x13, 0x04, 0x04, 0x04, - 0x0e, 0x04, 0x42, 0x04, 0x41, 0x80, 0x93, 0x17, 0x84, 0x00, 0x37, 0x07, 0xff, 0x00, 0xf9, 0x8f, 0x62, 0x04, 0x3e, - 0x94, 0xb7, 0x07, 0x00, 0x04, 0x03, 0x25, 0xca, 0x00, 0xc0, 0xdf, 0x65, 0xbf, 0x01, 0x45, 0xef, 0xf0, 0x3f, 0xa9, - 0xd9, 0xbf, 0xf2, 0x40, 0xfa, 0x35, 0xb9, 0x4d, 0xc4, 0x75, 0x9e, 0xa8, 0xdd, 0x16, 0x2c, 0xac, 0xdb, 0x5a, 0xe6, - 0x80, 0x8f, 0x72, 0x57, 0xaa, 0xfd, 0x26, 0x9c, 0x70, 0x1b, 0xce, 0xa0, 0x79, 0x41, 0x63, 0x72, 0x43, 0x7c, 0xe0, - 0x46, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, - 0x37, 0x34, 0x20, 0x00, 0x93, 0x07, 0x44, 0xe9, 0x52, 0xc4, 0x2a, 0x8a, 0xc8, 0x47, 0x56, 0xc2, 0x06, 0xce, 0x7e, - 0x05, 0x13, 0x65, 0x05, 0x30, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xae, 0x8a, 0xef, 0xf0, 0xff, 0xaf, 0x93, 0x07, - 0xa0, 0x0a, 0x63, 0x11, 0xf5, 0x12, 0xaa, 0x84, 0x13, 0x05, 0x60, 0x03, 0xef, 0xf0, 0x7f, 0xa4, 0x13, 0x04, 0x44, - 0xe9, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x45, 0x00, 0xef, 0xf0, 0xdf, 0xad, 0x2a, 0x89, 0x63, 0x11, 0x95, 0x10, - 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xbf, 0xac, 0xaa, 0x84, 0x63, 0x18, 0x25, 0x0f, 0x48, - 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x5f, 0xab, 0xaa, 0x89, 0x63, 0x1d, - 0x95, 0x0c, 0xd6, 0x85, 0x52, 0x85, 0xef, 0xf0, 0xdf, 0xec, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, - 0xf0, 0xbf, 0xa9, 0xaa, 0x84, 0x63, 0x10, 0x35, 0x0d, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x03, 0xef, 0xf0, - 0x9f, 0xa8, 0xaa, 0x89, 0x63, 0x17, 0x95, 0x0a, 0x13, 0x05, 0xc0, 0x05, 0xef, 0xf0, 0x5f, 0x9d, 0x48, 0x44, 0x7e, - 0x05, 0x13, 0x65, 0x45, 0x00, 0xef, 0xf0, 0xff, 0xa6, 0xaa, 0x84, 0x63, 0x1a, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, - 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xa5, 0xfa, 0xe3, 0x0a, 0x61, 0x37, 0x59, 0x2c, 0xd8, 0x60, 0x77, 0x81, - 0x93, 0x22, 0x6f, 0x28, 0x70, 0x4c, 0x4a, 0x3b, 0x5a, 0xea, 0xdf, 0xa8, 0xf7, 0x3a, 0x2c, 0xbc, 0x0b, 0x23, 0x00, - 0x50, 0x0e, 0xfc, 0xb8, 0x47, 0xaa, 0x89, 0x63, 0x11, 0x95, 0x08, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x32, - 0xef, 0xf0, 0xbf, 0xa4, 0xaa, 0x84, 0x63, 0x18, 0x35, 0x07, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, - 0xf0, 0x9f, 0xa3, 0x63, 0x10, 0x95, 0x06, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x03, 0xef, 0xf0, 0x9f, 0xa2, - 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0x63, 0x15, 0xf5, 0x04, 0x13, 0x05, 0x00, 0x06, 0xef, 0xf0, 0x9f, 0x99, 0x48, - 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xbf, 0xa0, 0xaa, 0x84, 0x63, 0x18, 0x25, 0x03, 0x48, 0x44, - 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x9f, 0x9f, 0x63, 0x10, 0x95, 0x02, 0x48, 0x44, 0x62, 0x44, 0xf2, - 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0x05, 0x61, - 0x6f, 0xf0, 0x9f, 0x9d, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, - 0x61, 0x82, 0x80, 0x39, 0x71, 0x22, 0xdc, 0x37, 0x34, 0x20, 0x00, 0x06, 0xde, 0x4a, 0xd8, 0x26, 0xda, 0x32, 0x89, - 0x13, 0x04, 0x44, 0xe9, 0xef, 0xf0, 0xdf, 0xe8, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x40, 0xef, 0xf0, 0x3f, - 0x9a, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x0a, 0xaa, 0x84, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, - 0xc5, 0x6b, 0xef, 0xf0, 0x9f, 0xe6, 0x85, 0x47, 0x63, 0x07, 0xf9, 0x08, 0xfa, 0xbf, 0xa1, 0x9f, 0x42, 0x31, 0x1c, - 0x31, 0xc5, 0x2c, 0x39, 0x12, 0x99, 0x30, 0xb5, 0x57, 0x6d, 0xdb, 0x71, 0x11, 0x1f, 0xb7, 0x49, 0x17, 0xd0, 0xae, - 0xba, 0xc1, 0xe1, 0xb0, 0xab, 0x1e, 0x79, 0x90, 0x48, 0x48, 0x44, 0x85, 0x67, 0x93, 0x87, 0x07, 0x80, 0x7e, 0x05, - 0x5d, 0x8d, 0xef, 0xf0, 0x5f, 0x97, 0x2a, 0x89, 0x63, 0x1c, 0x95, 0x06, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, - 0x02, 0x93, 0x85, 0x05, 0x04, 0x68, 0x00, 0xef, 0xe0, 0xef, 0x91, 0x48, 0x44, 0x89, 0x47, 0x23, 0x06, 0xf1, 0x02, - 0x7e, 0x05, 0x13, 0x65, 0x05, 0x20, 0xef, 0xf0, 0xbf, 0x94, 0xaa, 0x84, 0x63, 0x17, 0x25, 0x05, 0x48, 0x44, 0x7e, - 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0x9f, 0x93, 0x2a, 0x89, 0x63, 0x1e, 0x95, 0x02, 0x48, 0x44, 0x7e, 0x05, - 0x13, 0x65, 0x05, 0x42, 0xef, 0xf0, 0x7f, 0x92, 0xaa, 0x84, 0x63, 0x15, 0x25, 0x03, 0x68, 0x00, 0x93, 0x05, 0x10, - 0x02, 0xef, 0xf0, 0x5f, 0xdf, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x10, 0xef, 0xf0, 0xbf, 0x90, 0x63, 0x18, - 0x95, 0x00, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xbf, 0x8f, 0xf2, 0x50, 0x62, 0x54, 0xd2, - 0x54, 0x42, 0x59, 0x21, 0x61, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x44, 0xe9, - 0x08, 0x40, 0x09, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x06, 0xc6, 0xef, 0xf0, 0xff, 0xf0, 0x48, - 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x71, 0xef, 0xf0, 0x5f, 0x8c, 0x48, 0x44, 0x22, 0x44, 0xb2, 0x40, 0x7e, 0x05, - 0x13, 0x65, 0x05, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0x8b, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0xfa, 0x6e, 0x14, - 0x78, 0x38, 0xc4, 0xd9, 0x74, 0x0f, 0x12, 0x73, 0x0a, 0x34, 0x45, 0x89, 0xea, 0x0a, 0x1c, 0x20, 0x38, 0x2a, 0x1e, - 0x81, 0x17, 0xdb, 0xd5, 0x86, 0x8b, 0x4a, 0x6f, 0x68, 0x28, 0xff, 0x68, 0x49, 0x47, 0xe9, 0x05, 0x46, 0x93, 0x05, - 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x6f, 0xf0, 0xbf, 0xed, 0x41, 0x11, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x05, 0x00, - 0x04, 0x22, 0xc4, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x45, 0x6c, 0x13, 0x05, 0x05, 0x02, 0x37, 0x34, 0x20, 0x00, - 0x06, 0xc6, 0x13, 0x04, 0x44, 0xe9, 0xef, 0xe0, 0x4f, 0x8a, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, - 0xf0, 0xbf, 0x86, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x1d, 0xf5, 0x00, 0x08, 0x40, 0x22, 0x44, 0xb2, 0x40, 0x05, 0x46, - 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xe8, 0xb2, 0x40, 0x22, 0x44, 0x41, - 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x44, 0xe9, 0x48, 0x44, 0x06, 0xc6, - 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xbf, 0x82, 0x08, 0x40, 0x13, 0x06, 0x00, 0x02, 0x81, 0x45, 0x13, - 0x05, 0x15, 0x04, 0xef, 0x00, 0x90, 0x5c, 0x08, 0x40, 0x09, 0x46, 0x81, 0x45, 0x13, 0x05, 0x15, 0x04, 0xef, 0xf0, - 0xbf, 0xe4, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x60, 0xef, 0xf0, 0x1f, 0x80, 0x48, 0x44, 0x7e, 0x05, 0x13, - 0x65, 0x05, 0x71, 0xef, 0xf0, 0x4f, 0xff, 0x01, 0x45, 0xef, 0xf0, 0x8f, 0xf4, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, - 0x05, 0x07, 0xef, 0xf0, 0x2f, 0xfe, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x6f, 0xfd, 0xb2, - 0x40, 0xfa, 0x57, 0x22, 0xaa, 0x1e, 0x7c, 0x0e, 0x8c, 0x55, 0x47, 0x16, 0x49, 0x46, 0x1d, 0xa8, 0x81, 0x1f, 0x8c, - 0x85, 0xdc, 0xf8, 0x90, 0xb3, 0xf5, 0x94, 0x32, 0x77, 0x15, 0x05, 0x20, 0x67, 0xbc, 0x45, 0x40, 0x4a, 0x22, 0x44, - 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, 0x98, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x11, 0x65, 0xad, 0xa9, 0x37, 0x35, 0x20, - 0x00, 0x41, 0x11, 0x51, 0x46, 0x81, 0x45, 0x13, 0x05, 0x45, 0xe9, 0x06, 0xc6, 0xef, 0x00, 0xd0, 0x55, 0xb7, 0x37, - 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x1d, 0x65, 0x23, 0xa2, 0xe7, 0xfa, 0xa9, 0x21, 0xb2, 0x40, 0xb7, 0x07, 0x00, - 0x04, 0x05, 0x47, 0x98, 0xcb, 0x41, 0x01, 0x6f, 0xf0, 0xdf, 0xfc, 0x11, 0x65, 0x1d, 0xa9, 0x95, 0x47, 0x63, 0xec, - 0xb7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x44, 0xe9, 0x85, 0x47, 0x5c, 0xc0, 0xb7, - 0x57, 0x10, 0x00, 0x0c, 0xc4, 0x93, 0x87, 0x87, 0x6e, 0x8a, 0x05, 0xbe, 0x95, 0x9c, 0x41, 0x06, 0xc6, 0x08, 0xc0, - 0x82, 0x97, 0x08, 0x48, 0xb2, 0x40, 0x23, 0x22, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, - 0x05, 0x82, 0x80, 0xb7, 0x05, 0x00, 0x04, 0x41, 0x46, 0x93, 0x85, 0x05, 0x08, 0x6f, 0xd0, 0xff, 0xef, 0x37, 0x37, - 0x20, 0x00, 0x13, 0x07, 0x47, 0xe9, 0x89, 0x47, 0x5c, 0xc3, 0x5c, 0x47, 0x46, 0x05, 0xfe, 0x07, 0xc9, 0x8f, 0x21, - 0x65, 0x15, 0x05, 0x5d, 0x8d, 0x6f, 0xf0, 0xef, 0xf1, 0x39, 0x71, 0x4e, 0xd6, 0x5e, 0xce, 0x62, 0xcc, 0xb7, 0x0b, - 0x00, 0x04, 0xb7, 0x39, 0x20, 0x00, 0x05, 0x6c, 0x22, 0xdc, 0x26, 0xda, 0x4a, 0xd8, 0x56, 0xd2, 0x5a, 0xd0, 0x66, - 0xca, 0x6a, 0xc8, 0x06, 0xde, 0xfa, 0x65, 0xb9, 0x0c, 0x88, 0x3f, 0x5b, 0x66, 0xde, 0x7a, 0xed, 0xe1, 0x97, 0x78, - 0xec, 0x24, 0xa1, 0xb2, 0xc1, 0x8b, 0x4a, 0x99, 0xae, 0xe9, 0x9f, 0xe8, 0xfb, 0xcb, 0x08, 0x0c, 0x8a, 0x24, 0xa7, - 0x18, 0x4b, 0x52, 0xd4, 0x2a, 0x84, 0x2e, 0x8b, 0xb2, 0x8a, 0x81, 0x44, 0x01, 0x49, 0xc1, 0x4c, 0x93, 0x8b, 0x0b, - 0x02, 0x93, 0x89, 0x49, 0xe9, 0x09, 0x0c, 0x37, 0x3d, 0x20, 0x00, 0xb3, 0x05, 0x9b, 0x00, 0x63, 0xe0, 0x54, 0x03, - 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, 0x4b, 0x62, - 0x4c, 0xd2, 0x4c, 0x42, 0x4d, 0x21, 0x61, 0x82, 0x80, 0x33, 0x8a, 0x9a, 0x40, 0x63, 0xd3, 0x4c, 0x01, 0x41, 0x4a, - 0x4a, 0x85, 0x2e, 0xc6, 0xef, 0xe0, 0xcf, 0x9f, 0xb2, 0x45, 0x13, 0x06, 0x3a, 0x00, 0x71, 0x9a, 0x5e, 0x85, 0xef, - 0xd0, 0xbf, 0xec, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xef, 0xe8, 0x03, 0xa5, - 0xc9, 0x00, 0x93, 0x17, 0x8a, 0x01, 0x7e, 0x05, 0x5d, 0x8d, 0x13, 0x65, 0x75, 0x00, 0xef, 0xf0, 0xaf, 0xe7, 0x03, - 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x33, 0x65, 0x85, 0x01, 0xef, 0xf0, 0xcf, 0xe6, 0x03, 0x27, 0x4d, 0xfa, 0x93, 0x07, - 0x50, 0x05, 0x63, 0x19, 0xf7, 0x00, 0x19, 0xc4, 0x22, 0x85, 0x52, 0x86, 0xca, 0x85, 0xef, 0xe0, 0x4f, 0xa3, 0x41, - 0x04, 0x93, 0x07, 0x00, 0x07, 0x63, 0xe3, 0x27, 0x01, 0x41, 0x09, 0xc1, 0x04, 0x9d, 0xb7, 0x39, 0x71, 0x4e, 0xd6, - 0x5a, 0xd0, 0x5e, 0xce, 0xb7, 0x39, 0x20, 0x00, 0x37, 0x0b, 0x02, 0x00, 0x85, 0x6b, 0x26, 0xda, 0x4a, 0xd8, 0x52, - 0xd4, 0x56, 0xd2, 0x62, 0xcc, 0x6a, 0xc8, 0x6e, 0xc6, 0xfa, 0xd2, 0xaa, 0x40, 0x04, 0x8d, 0x72, 0x7b, 0xb3, 0xf9, - 0xe3, 0xef, 0xdb, 0xce, 0xbc, 0xf2, 0xac, 0xb2, 0x83, 0xb2, 0x4e, 0x4e, 0xe9, 0xca, 0x4f, 0x79, 0x98, 0x07, 0x37, - 0xde, 0xdd, 0xbc, 0x0e, 0xf0, 0x4b, 0x06, 0xde, 0x22, 0xdc, 0x66, 0xca, 0xaa, 0x8a, 0xae, 0x84, 0x32, 0x8a, 0x01, - 0x49, 0x81, 0x4d, 0x37, 0x3c, 0x20, 0x00, 0x41, 0x4d, 0x93, 0x89, 0x49, 0xe9, 0x1d, 0x0b, 0x93, 0x8b, 0x0b, 0x82, - 0xb3, 0x8c, 0x2a, 0x01, 0x93, 0x07, 0x4c, 0xfa, 0x63, 0x64, 0x49, 0x03, 0xf2, 0x50, 0x62, 0x54, 0x13, 0x07, 0x50, - 0x05, 0x98, 0xc3, 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, - 0xd2, 0x4c, 0x42, 0x4d, 0xb2, 0x4d, 0x21, 0x61, 0x82, 0x80, 0x33, 0x04, 0x2a, 0x41, 0x63, 0x73, 0x8d, 0x00, 0x41, - 0x44, 0x6e, 0x85, 0xef, 0xe0, 0xef, 0x91, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0xfa, 0x98, 0x43, 0x93, 0x07, - 0x50, 0x05, 0x63, 0x19, 0xf7, 0x00, 0x99, 0xc4, 0x26, 0x85, 0x22, 0x86, 0xee, 0x85, 0xef, 0xe0, 0xcf, 0x9b, 0xc1, - 0x04, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x25, 0x00, 0xef, 0xf0, 0x6f, 0xd9, 0x03, 0xa5, 0xc9, 0x00, - 0x93, 0x17, 0x84, 0x01, 0x0d, 0x04, 0x7e, 0x05, 0x5d, 0x8d, 0x33, 0x65, 0x65, 0x01, 0xef, 0xf0, 0x0f, 0xd8, 0x03, - 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x33, 0x65, 0x75, 0x01, 0xef, 0xf0, 0x2f, 0xd7, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x76, - 0xc4, 0xff, 0x93, 0x85, 0x05, 0x04, 0x66, 0x85, 0xef, 0xd0, 0x3f, 0xd2, 0x93, 0x07, 0x00, 0x06, 0x63, 0xe3, 0xb7, - 0x01, 0xc1, 0x0d, 0x41, 0x09, 0x81, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x2a, 0x84, 0xfa, 0xe4, 0x9f, 0x33, 0x88, 0xe3, - 0x5c, 0x0f, 0x58, 0x0c, 0xef, 0xff, 0xbd, 0xba, 0x7a, 0x34, 0x0b, 0x73, 0x41, 0xc6, 0xf6, 0x89, 0xf9, 0x0c, 0x38, - 0x09, 0x56, 0x4d, 0xcb, 0x48, 0xea, 0x20, 0x65, 0xc8, 0x4c, 0x21, 0x45, 0x06, 0xc6, 0xef, 0xf0, 0x4f, 0xd4, 0x93, - 0x07, 0xa0, 0x0a, 0x63, 0x19, 0xf5, 0x00, 0x22, 0x85, 0xef, 0xf0, 0x1f, 0xdf, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, - 0x07, 0xe8, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa2, 0xa7, 0xfa, 0x82, - 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x60, 0x02, 0x98, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, - 0x98, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0xc8, 0x4b, 0x82, 0x80, 0x39, 0x71, 0x36, 0xd0, 0x3a, 0xce, 0x3e, - 0xcc, 0x05, 0x47, 0xb7, 0x07, 0x00, 0x04, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, - 0x32, 0xd2, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xd8, 0xc7, 0xb7, 0x37, 0x20, - 0x00, 0x93, 0x87, 0x47, 0xe9, 0xd8, 0x43, 0x89, 0x46, 0x7d, 0x17, 0x63, 0xfe, 0xe6, 0x02, 0x37, 0x55, 0x10, 0x00, - 0x85, 0x45, 0x13, 0x05, 0x05, 0x6c, 0xef, 0xd0, 0xef, 0xe0, 0xef, 0xc0, 0x8f, 0xdc, 0xf2, 0x50, 0xe2, 0x52, 0x52, - 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, - 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x13, 0x07, 0xa0, 0x0a, 0x98, - 0xcb, 0xd1, 0xbf, 0xb7, 0x07, 0x01, 0x02, 0x88, 0xd7, 0xcc, 0xd7, 0x88, 0xdb, 0xcc, 0xdb, 0x88, 0xdf, 0xfa, 0xf0, - 0x45, 0x71, 0x22, 0x19, 0x65, 0x77, 0x86, 0xb0, 0xbf, 0xec, 0xcc, 0x91, 0xa8, 0x07, 0x81, 0xc8, 0x60, 0x4c, 0x1f, - 0x41, 0x46, 0x98, 0xdd, 0xc2, 0x2f, 0xbd, 0x80, 0x56, 0x18, 0xfd, 0x31, 0xa0, 0x4d, 0xcc, 0xdf, 0x82, 0x80, 0x01, - 0x11, 0x26, 0xca, 0xb7, 0x04, 0x01, 0x02, 0x22, 0xcc, 0xc0, 0x40, 0xf5, 0x77, 0x93, 0x87, 0xf7, 0xa5, 0x7d, 0x8c, - 0x89, 0x67, 0x93, 0x87, 0x07, 0x1a, 0x06, 0xce, 0x4a, 0xc8, 0x4e, 0xc6, 0xc1, 0x8f, 0xaa, 0x89, 0xdc, 0xc0, 0x05, - 0x45, 0x2e, 0x89, 0xef, 0xd0, 0xbf, 0x99, 0x93, 0x67, 0x04, 0x40, 0xdc, 0xc0, 0x05, 0x45, 0xef, 0xd0, 0xff, 0x98, - 0x85, 0x67, 0x93, 0x87, 0x07, 0x40, 0x5d, 0x8c, 0xc0, 0xc0, 0xb7, 0x47, 0x00, 0x08, 0x23, 0xa4, 0x07, 0x00, 0xb7, - 0x57, 0x00, 0x08, 0x23, 0xa4, 0x07, 0x00, 0xf2, 0x40, 0x62, 0x44, 0x23, 0xa0, 0x34, 0x03, 0x23, 0xa2, 0x24, 0x03, - 0xb2, 0x49, 0xd2, 0x44, 0x42, 0x49, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x02, 0x88, 0x53, 0xcc, 0x53, 0x82, - 0x80, 0xb7, 0x07, 0x01, 0x02, 0x88, 0x47, 0x21, 0x81, 0x13, 0x75, 0xf5, 0x0f, 0x82, 0x80, 0x41, 0x11, 0x01, 0x45, - 0x81, 0x45, 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0xef, 0xf0, 0x1f, 0xf6, 0xef, 0xf0, 0x9f, 0xfd, 0xaa, 0x84, 0x2e, - 0x84, 0x2a, 0x87, 0xae, 0x86, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0x85, - 0x85, 0x71, 0x13, 0x05, 0x45, 0x64, 0x13, 0x06, 0x06, 0x70, 0xef, 0xd0, 0xaf, 0xc9, 0xa2, 0x85, 0x22, 0x44, 0xb2, - 0x40, 0x26, 0x85, 0x92, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xf3, 0x39, 0x71, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, - 0x1e, 0xd8, 0xfa, 0xe9, 0x21, 0xe6, 0x06, 0x84, 0x89, 0xc9, 0x40, 0xa9, 0x3a, 0xb2, 0xa5, 0x17, 0xf0, 0x91, 0xee, - 0xbf, 0x76, 0xa0, 0x8e, 0x35, 0x28, 0x6e, 0x15, 0xae, 0xa7, 0xba, 0xf5, 0x5e, 0xd0, 0x31, 0x5c, 0x78, 0x4e, 0x2a, - 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, - 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xf0, 0x7f, 0xf9, 0xef, 0xc0, 0x4f, 0xc9, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, - 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, - 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x07, 0x00, 0x02, 0x5c, 0x47, 0xc9, - 0x8f, 0x5c, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0xd8, 0x47, 0x13, 0x45, 0xf5, 0xff, 0x79, 0x8d, 0xc8, 0xc7, - 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x4f, 0xc9, 0x8f, 0x1c, 0xcf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0x98, - 0x4f, 0x13, 0x45, 0xf5, 0xff, 0x79, 0x8d, 0x88, 0xcf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0xc8, 0xcb, 0x82, 0x80, - 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x47, 0x00, 0x1c, 0xc7, 0xb7, 0x07, 0x00, 0x03, 0x94, 0x4b, 0x37, - 0x37, 0x20, 0x00, 0x23, 0x24, 0xd7, 0xfa, 0x23, 0xa8, 0x07, 0x00, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, - 0xb7, 0x06, 0x00, 0x03, 0xf9, 0x9b, 0x1c, 0xc7, 0x37, 0x07, 0x08, 0x00, 0x9c, 0x46, 0xf9, 0x8f, 0xf5, 0xff, 0x82, - 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x17, 0x00, 0x1c, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, - 0x87, 0xfa, 0xb7, 0x07, 0x00, 0x03, 0xfa, 0x95, 0xfb, 0xf0, 0x86, 0x8c, 0x28, 0xbb, 0x4c, 0xec, 0xe8, 0x65, 0xa0, - 0x37, 0xc3, 0x43, 0xc0, 0x5e, 0x9c, 0xbb, 0x07, 0xab, 0xd3, 0x1e, 0x06, 0xe5, 0xe9, 0xf5, 0x57, 0x28, 0x8e, 0x46, - 0xfe, 0x50, 0x4f, 0x98, 0xcb, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0xc7, 0xfa, 0x93, 0x07, 0xa0, 0x0a, - 0x63, 0x0b, 0xf5, 0x00, 0xb7, 0x27, 0x03, 0x04, 0x9c, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, - 0x05, 0x50, 0x05, 0x82, 0x80, 0x13, 0x05, 0x00, 0x10, 0x6f, 0xf0, 0x3f, 0xf4, 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, - 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0x41, 0x11, 0x37, 0x37, 0x20, 0x00, 0x23, 0x28, 0xf7, 0xfa, 0x06, 0xc6, 0xef, - 0xf0, 0x1f, 0xfe, 0xb7, 0x27, 0x03, 0x04, 0x09, 0x47, 0xd8, 0xc3, 0x37, 0x17, 0x03, 0x04, 0xb7, 0x07, 0x03, 0x04, - 0x13, 0x07, 0x07, 0x80, 0x23, 0xa0, 0x07, 0x00, 0x91, 0x07, 0xe3, 0x9d, 0xe7, 0xfe, 0xb7, 0x27, 0x03, 0x04, 0x0d, - 0x47, 0xd8, 0xc7, 0x98, 0x47, 0x85, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, - 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x00, 0x10, 0x6f, 0xf0, 0xff, 0xee, 0x93, 0x07, 0x50, 0x05, 0x37, - 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x28, 0xf7, 0xfa, 0xb7, 0x27, 0x03, 0x04, - 0x05, 0x47, 0xd8, 0xc3, 0x82, 0x80, 0xc2, 0x05, 0xc9, 0x8d, 0x93, 0xe5, 0x05, 0x10, 0xb7, 0x07, 0x03, 0x04, 0x23, - 0xa0, 0xb7, 0x10, 0x82, 0x80, 0xc2, 0x05, 0xc9, 0x8d, 0x11, 0x65, 0x13, 0x05, 0x05, 0x50, 0xc9, 0x8d, 0xb7, 0x07, - 0x03, 0x04, 0x23, 0xa0, 0xb7, 0x10, 0x82, 0x80, 0x41, 0x11, 0xfa, 0x3b, 0x27, 0xae, 0x5e, 0xb8, 0x6d, 0xaf, 0x1c, - 0xec, 0x02, 0xd8, 0x56, 0xd6, 0xdf, 0xb4, 0x34, 0xf5, 0x69, 0x6c, 0x00, 0xa4, 0xbb, 0xc4, 0xe5, 0x6e, 0x2a, 0x70, - 0x51, 0x62, 0x4d, 0xdc, 0x5c, 0x28, 0x50, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x99, 0xc3, - 0xef, 0xb0, 0x9f, 0xc4, 0x37, 0x15, 0x03, 0x04, 0x2a, 0x94, 0x08, 0x40, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, - 0x80, 0x79, 0x71, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x06, 0xd6, 0x22, 0xd4, 0xaa, 0x84, 0x2e, 0x89, 0xb2, 0x89, - 0x19, 0xe1, 0xef, 0xb0, 0x1f, 0xc2, 0x93, 0x77, 0x39, 0x00, 0x99, 0xc3, 0xef, 0xb0, 0x7f, 0xc1, 0x01, 0x44, 0x63, - 0x69, 0x34, 0x01, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x45, 0x61, 0x82, 0x80, 0x33, 0x05, - 0x24, 0x01, 0xef, 0xf0, 0x5f, 0xfa, 0x2a, 0xc6, 0x11, 0x46, 0x33, 0x85, 0x84, 0x00, 0x6c, 0x00, 0xcd, 0x2d, 0x11, - 0x04, 0xe1, 0xbf, 0x79, 0x71, 0x22, 0xd4, 0x4a, 0xd0, 0x4e, 0xce, 0x56, 0xca, 0x06, 0xd6, 0x26, 0xd2, 0x52, 0xcc, - 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0xae, 0x89, 0x32, 0x89, 0x93, 0x7a, 0xc6, 0xff, 0x99, 0xc3, 0xef, 0xb0, 0x7f, - 0xbc, 0x37, 0x0a, 0x03, 0x04, 0x81, 0x44, 0x22, 0x9a, 0x63, 0xe9, 0x54, 0x03, 0x13, 0x76, 0x39, 0x00, 0x01, 0xce, - 0xb3, 0x85, 0x99, 0x00, 0x68, 0x00, 0x02, 0xc6, 0x7d, 0x25, 0xb2, 0x47, 0x37, 0x05, 0x03, 0x04, 0x2a, 0x94, 0x26, - 0x94, 0x1c, 0xc0, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0xd2, 0x4a, 0x45, 0x61, - 0x82, 0x80, 0x63, 0x94, 0x09, 0x00, 0xef, 0xb0, 0x5f, 0xb8, 0xb3, 0x85, 0x99, 0x00, 0xfa, 0xc7, 0xa5, 0x70, 0x8e, - 0x36, 0xca, 0xbc, 0x79, 0x52, 0xab, 0xcc, 0xcc, 0xaf, 0xe6, 0x32, 0x83, 0xe5, 0x88, 0xf9, 0x8a, 0x81, 0xbc, 0x5e, - 0xb4, 0xf3, 0xd4, 0xe8, 0xb9, 0xcf, 0x5f, 0x82, 0xe6, 0x00, 0x51, 0x11, 0x46, 0x68, 0x00, 0xbd, 0x2d, 0x32, 0x47, - 0xb3, 0x07, 0x9a, 0x00, 0x91, 0x04, 0x98, 0xc3, 0x4d, 0xbf, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x41, 0x11, 0x13, - 0x05, 0x45, 0xb5, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0xd0, 0xef, 0xe9, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0f, 0xf5, 0x00, - 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x05, 0x72, 0xef, 0xd0, 0x2f, 0xa3, 0x13, 0x05, 0x50, 0x05, 0xb2, - 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x17, 0x03, 0x04, 0x83, 0xa7, 0x07, 0x10, 0x37, 0x34, 0x20, 0x00, - 0x13, 0x04, 0x04, 0xfb, 0x93, 0xf7, 0xf7, 0x0f, 0x81, 0xe7, 0x1c, 0x40, 0x63, 0x9d, 0xa7, 0x00, 0x37, 0x55, 0x10, - 0x00, 0x8d, 0x45, 0x13, 0x05, 0x05, 0x72, 0xef, 0xd0, 0xcf, 0x9f, 0x93, 0x07, 0xa0, 0x0a, 0x1c, 0xc0, 0xd1, 0xb7, - 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0xc7, 0xfa, 0x13, 0x84, 0xc7, 0xfa, 0x63, 0x09, 0xa7, 0x00, 0x37, 0x55, 0x10, - 0x00, 0x89, 0x45, 0x13, 0x05, 0x05, 0x72, 0xef, 0xd0, 0x6f, 0x9d, 0x08, 0x40, 0x5d, 0xb7, 0x37, 0x95, 0x04, 0x00, - 0x13, 0x05, 0x05, 0x3e, 0x6f, 0xf0, 0xff, 0xf6, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x5f, 0xe6, 0xef, 0xf0, 0x1f, - 0xe3, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x5f, 0xfe, 0xb7, 0x17, 0x03, 0x04, 0x03, 0xa5, 0x07, 0x10, 0x41, 0x81, - 0x82, 0x80, 0x41, 0x11, 0x3a, 0xc4, 0x37, 0x27, 0x03, 0x04, 0x3e, 0xc2, 0x1c, 0x47, 0x36, 0xc6, 0x93, 0xf6, 0xfa, - 0xec, 0x42, 0x1d, 0xe1, 0x7c, 0xe3, 0x34, 0x80, 0x26, 0x54, 0x32, 0x5f, 0x6c, 0x88, 0x6d, 0xa4, 0x80, 0xdb, 0x62, - 0x99, 0x7b, 0x26, 0x78, 0x02, 0x0d, 0x71, 0x74, 0xc9, 0x8d, 0xf3, 0xc0, 0xd6, 0xd8, 0x51, 0x27, 0x00, 0x89, 0xca, - 0x89, 0x46, 0x14, 0xc7, 0x37, 0x37, 0x20, 0x00, 0x93, 0x06, 0xa0, 0x0a, 0x23, 0x26, 0xd7, 0xfa, 0x91, 0x8b, 0x99, - 0xcf, 0xb7, 0x27, 0x03, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x93, 0x07, 0xa0, 0x0a, 0x37, 0x37, 0x20, 0x00, 0x23, 0x28, - 0xf7, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0xb2, 0x46, 0x22, 0x47, 0x92, 0x47, 0x41, 0x01, 0x73, - 0x00, 0x20, 0x30, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x04, 0x00, 0x03, 0x1c, 0x48, 0x06, 0xc6, 0xdd, 0x9b, 0x1c, 0xc8, - 0xef, 0xe0, 0x0f, 0xd9, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x02, 0x5c, 0xcc, 0xb2, 0x40, 0x22, 0x44, 0xb7, - 0x37, 0x20, 0x00, 0x23, 0x8c, 0x07, 0xfa, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x2a, 0x84, 0x21, 0x45, - 0x06, 0xc6, 0xef, 0xf0, 0x7f, 0xca, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x7f, 0xc6, 0x22, 0x04, 0x13, 0x64, 0x04, - 0x03, 0x37, 0x07, 0x00, 0x03, 0x40, 0xc3, 0xb2, 0x40, 0x22, 0x44, 0xc1, 0x67, 0x93, 0x87, 0xa7, 0xfa, 0x1c, 0xcf, - 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x26, 0xc2, 0xaa, 0x84, 0x09, 0x45, 0x22, 0xc4, 0x06, 0xc6, 0x2e, 0x84, 0xef, - 0xf0, 0x1f, 0xfc, 0x37, 0x07, 0x20, 0x00, 0xb7, 0x07, 0x00, 0x03, 0x13, 0x07, 0x07, 0x02, 0xd8, 0xcf, 0x37, 0x37, - 0x20, 0x00, 0x23, 0x2a, 0x97, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2e, 0x87, 0xfa, 0xb2, 0x40, 0x22, 0x44, 0x05, - 0x47, 0x98, 0xcb, 0xfa, 0xa7, 0x12, 0x8f, 0xd2, 0xc8, 0x61, 0x87, 0x7d, 0xa1, 0x71, 0x61, 0x90, 0xb6, 0x21, 0x51, - 0x78, 0xc2, 0x56, 0x74, 0xce, 0x9b, 0xd5, 0xd8, 0x59, 0x8d, 0xf3, 0x9b, 0xc6, 0xd3, 0xb7, 0x73, 0x4f, 0xb0, 0x52, - 0x37, 0x07, 0x08, 0x00, 0x98, 0xc7, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x03, 0x9c, 0x47, 0x37, - 0x07, 0x04, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x37, 0x07, - 0x00, 0x03, 0x5c, 0x53, 0x13, 0x05, 0x50, 0x05, 0x93, 0x96, 0x07, 0x01, 0xc1, 0x82, 0xc1, 0x83, 0x63, 0x97, 0xf6, - 0x00, 0x1c, 0x47, 0x91, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, - 0xff, 0xf1, 0x37, 0x07, 0x00, 0x03, 0x5c, 0x47, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc7, 0x5c, 0x47, 0x85, 0x8b, 0xf5, - 0xff, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xfb, 0x95, 0xc3, 0x41, 0x11, - 0x06, 0xc6, 0xef, 0xf0, 0x5f, 0xef, 0xb7, 0x07, 0x00, 0x03, 0x98, 0x4b, 0xb2, 0x40, 0x13, 0x67, 0x87, 0x00, 0x98, - 0xcb, 0x37, 0x07, 0x08, 0x00, 0x98, 0xc7, 0x41, 0x01, 0x6f, 0xe0, 0xcf, 0xc5, 0x82, 0x80, 0x37, 0x07, 0x00, 0x03, - 0x1c, 0x4b, 0xf9, 0x9b, 0x1c, 0xcb, 0x82, 0x80, 0xb7, 0x06, 0x00, 0x03, 0xdc, 0x42, 0x7d, 0x77, 0x13, 0x07, 0xf7, - 0x0f, 0xf9, 0x8f, 0x05, 0x67, 0x22, 0x05, 0x13, 0x07, 0x07, 0xf0, 0x79, 0x8d, 0x5d, 0x8d, 0xc8, 0xc2, 0x82, 0x80, - 0x1d, 0x71, 0x3a, 0xda, 0x37, 0x07, 0x00, 0x03, 0x3e, 0xd8, 0x1c, 0x47, 0x86, 0xce, 0x96, 0xcc, 0x9a, 0xca, 0x9e, - 0xc8, 0xa2, 0xc6, 0xa6, 0xc4, 0xaa, 0xc2, 0xfa, 0xed, 0xed, 0xe1, 0x01, 0xe8, 0xc4, 0xe4, 0xc5, 0x64, 0x65, 0x42, - 0xc9, 0xb4, 0x83, 0x9c, 0x76, 0x94, 0xef, 0x48, 0xca, 0x46, 0xaa, 0x52, 0x7d, 0x52, 0x28, 0xc4, 0xb9, 0xe0, 0x99, - 0x35, 0x07, 0x88, 0x53, 0xae, 0xc0, 0x32, 0xde, 0x36, 0xdc, 0x42, 0xd6, 0x46, 0xd4, 0x4a, 0xd2, 0x4e, 0xd0, 0x72, - 0xce, 0x76, 0xcc, 0x7a, 0xca, 0x7e, 0xc8, 0x85, 0x8b, 0xa1, 0xc7, 0x04, 0x57, 0x11, 0x44, 0x37, 0x39, 0x20, 0x00, - 0x83, 0x27, 0x49, 0xfb, 0x13, 0xf5, 0xf4, 0x0f, 0x7d, 0x14, 0x82, 0x97, 0xa1, 0x80, 0x6d, 0xf8, 0x36, 0x44, 0xf6, - 0x40, 0xe6, 0x42, 0x56, 0x43, 0xc6, 0x43, 0xa6, 0x44, 0x16, 0x45, 0x86, 0x45, 0x72, 0x56, 0xe2, 0x56, 0x52, 0x57, - 0xc2, 0x57, 0x32, 0x58, 0xa2, 0x58, 0x12, 0x59, 0x82, 0x59, 0x72, 0x4e, 0xe2, 0x4e, 0x52, 0x4f, 0xc2, 0x4f, 0x25, - 0x61, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xc7, 0x87, 0xfb, 0x13, 0x84, 0x87, 0xfb, 0x05, 0xeb, - 0xb7, 0x04, 0x00, 0x03, 0x37, 0x39, 0x20, 0x00, 0x93, 0x09, 0xa0, 0x0a, 0x9c, 0x44, 0x91, 0x8b, 0xd5, 0xfb, 0x83, - 0x27, 0xc9, 0xfb, 0x68, 0x00, 0x82, 0x97, 0x63, 0x0d, 0x35, 0x01, 0x85, 0x47, 0x23, 0x00, 0xf4, 0x00, 0xc1, 0x67, - 0x93, 0x87, 0x07, 0x02, 0xdc, 0xcc, 0x61, 0xbf, 0xef, 0xf0, 0x5f, 0xdf, 0x49, 0xbf, 0xb2, 0x47, 0x9c, 0xd8, 0xd1, - 0xbf, 0x5c, 0x41, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc1, 0x82, 0x80, 0x5c, 0x41, 0xf9, 0x9b, 0x5c, 0xc1, 0x82, 0x80, - 0x5c, 0x41, 0xf5, 0x9b, 0xd1, 0x8f, 0x5c, 0xc1, 0x14, 0xc9, 0x4c, 0xc9, 0x82, 0x80, 0x5c, 0x45, 0xcd, 0x8f, 0x5c, - 0xc5, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x07, 0xfc, 0xfa, 0x9f, 0xa6, 0x16, 0xa0, 0xa2, 0xa7, 0xcd, - 0x18, 0x6a, 0x30, 0x34, 0x43, 0x0f, 0x18, 0x91, 0xec, 0xab, 0x4e, 0x13, 0xb4, 0xe1, 0x03, 0x40, 0x5e, 0x56, 0x1b, - 0x89, 0x18, 0x8b, 0x78, 0x55, 0x00, 0x60, 0x54, 0x82, 0x80, 0x39, 0x71, 0x3a, 0xce, 0x37, 0x07, 0x10, 0x01, 0x3e, - 0xcc, 0x1c, 0x47, 0x58, 0x47, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, - 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xf9, 0x8f, 0x91, 0xcf, 0xb7, - 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xfc, 0x98, 0x43, 0x05, 0x07, 0x98, 0xc3, 0xb7, 0x07, 0x10, 0x01, 0x98, 0x47, - 0x0d, 0x8b, 0x98, 0xc7, 0x19, 0xa8, 0xb7, 0x07, 0x20, 0x01, 0x98, 0x47, 0xdc, 0x47, 0x7d, 0x8f, 0xb7, 0x07, 0x20, - 0x01, 0x6d, 0xf7, 0xef, 0xb0, 0xff, 0xe6, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, - 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, - 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x1c, 0x41, 0x63, 0xf7, 0xb7, 0x00, 0x23, 0x80, 0xc7, 0x00, 0x1c, 0x41, - 0x85, 0x07, 0x1c, 0xc1, 0x82, 0x80, 0x1d, 0x71, 0xa2, 0xcc, 0xa6, 0xca, 0xca, 0xc8, 0x86, 0xce, 0xce, 0xc6, 0xd2, - 0xc4, 0xd6, 0xc2, 0xda, 0xc0, 0x5e, 0xde, 0x62, 0xdc, 0x66, 0xda, 0x6a, 0xd8, 0x6e, 0xd6, 0x2a, 0xc6, 0x2e, 0x84, - 0x32, 0x89, 0xb6, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x0f, 0xf6, 0x63, 0x14, 0x09, 0x00, 0xef, 0xb0, 0x8f, 0xf5, 0x01, - 0x45, 0x05, 0xc4, 0xb2, 0x4a, 0x7d, 0x14, 0x25, 0x4a, 0x56, 0x94, 0x93, 0x0c, 0xc0, 0x06, 0xfa, 0x78, 0xb3, 0xf1, - 0xdd, 0xc5, 0x13, 0x54, 0x08, 0x05, 0xc9, 0x57, 0xa0, 0x7d, 0x61, 0x7f, 0x3c, 0x03, 0xc6, 0x40, 0x73, 0xd2, 0x7c, - 0x9a, 0xf2, 0xd5, 0x07, 0x3d, 0x6c, 0x0e, 0xe4, 0x7c, 0x6f, 0x38, 0x55, 0x13, 0x0b, 0x30, 0x07, 0xa9, 0x4b, 0x1d, - 0x4d, 0x03, 0x46, 0x09, 0x00, 0x15, 0xe6, 0xb2, 0x47, 0x23, 0x80, 0x07, 0x00, 0x32, 0x45, 0x33, 0x05, 0x55, 0x41, - 0xf6, 0x40, 0x66, 0x44, 0xd6, 0x44, 0x46, 0x49, 0xb6, 0x49, 0x26, 0x4a, 0x96, 0x4a, 0x06, 0x4b, 0xf2, 0x5b, 0x62, - 0x5c, 0xd2, 0x5c, 0x42, 0x5d, 0xb2, 0x5d, 0x25, 0x61, 0x82, 0x80, 0x93, 0x07, 0x50, 0x02, 0x63, 0x1f, 0xf6, 0x02, - 0x93, 0x07, 0x19, 0x00, 0x83, 0xc6, 0x07, 0x00, 0x3e, 0x89, 0x85, 0x07, 0x13, 0x87, 0x06, 0xfd, 0x13, 0x77, 0xf7, - 0x0f, 0xe3, 0x78, 0xea, 0xfe, 0x63, 0x93, 0x96, 0x01, 0x3e, 0x89, 0x03, 0x46, 0x09, 0x00, 0x63, 0x06, 0x66, 0x0d, - 0x63, 0x60, 0xcb, 0x02, 0x93, 0x07, 0x30, 0x06, 0x63, 0x05, 0xf6, 0x06, 0x93, 0x07, 0x40, 0x06, 0x63, 0x0c, 0xf6, - 0x06, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, 0xf2, 0xa6, 0x89, 0x95, 0xa0, 0x93, 0x07, 0x50, 0x07, 0x63, 0x02, - 0xf6, 0x06, 0x93, 0x07, 0x80, 0x07, 0xe3, 0x14, 0xf6, 0xfe, 0x98, 0x40, 0x93, 0x89, 0x44, 0x00, 0x81, 0x46, 0x37, - 0x06, 0x00, 0xf0, 0xb3, 0x75, 0xc7, 0x00, 0xba, 0x84, 0x36, 0x8c, 0x12, 0x07, 0x85, 0x06, 0x89, 0xe5, 0xe3, 0x99, - 0xa6, 0xff, 0x1d, 0x4c, 0xba, 0x84, 0xa1, 0x4d, 0x13, 0xd7, 0xc4, 0x01, 0x63, 0x74, 0xea, 0x08, 0x13, 0x06, 0x77, - 0x05, 0xa2, 0x85, 0x68, 0x00, 0x05, 0x0c, 0xef, 0xf0, 0x1f, 0xee, 0x92, 0x04, 0xe3, 0x14, 0xbc, 0xff, 0x09, 0xa8, - 0xfa, 0xd5, 0xda, 0x2e, 0x8e, 0x22, 0x59, 0xac, 0x83, 0x89, 0x57, 0x76, 0x65, 0x16, 0xb6, 0x2b, 0xd5, 0xca, 0xc5, - 0x22, 0x0a, 0x1f, 0x76, 0x8a, 0xb1, 0x0a, 0xac, 0xcd, 0x33, 0x87, 0x5d, 0x8c, 0xfd, 0x10, 0x56, 0x03, 0xc6, 0x04, - 0x00, 0xa2, 0x85, 0x68, 0x00, 0x93, 0x89, 0x44, 0x00, 0xef, 0xf0, 0x9f, 0xec, 0x05, 0x09, 0xce, 0x84, 0x31, 0xbf, - 0x5c, 0x08, 0x98, 0x40, 0x93, 0x89, 0x44, 0x00, 0x3e, 0x8c, 0x81, 0x44, 0xb3, 0x76, 0x77, 0x03, 0x85, 0x04, 0x85, - 0x07, 0x93, 0x86, 0x06, 0x03, 0xa3, 0x8f, 0xd7, 0xfe, 0xba, 0x86, 0x33, 0x57, 0x77, 0x03, 0xe3, 0x65, 0xda, 0xfe, - 0xfd, 0x5d, 0xfd, 0x14, 0xe3, 0x88, 0xb4, 0xfd, 0xb3, 0x07, 0x9c, 0x00, 0x03, 0xc6, 0x07, 0x00, 0xa2, 0x85, 0x68, - 0x00, 0xef, 0xf0, 0x5f, 0xe8, 0xed, 0xb7, 0x93, 0x89, 0x44, 0x00, 0x84, 0x40, 0x03, 0xc6, 0x04, 0x00, 0x45, 0xda, - 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, 0xe6, 0x85, 0x04, 0xc5, 0xbf, 0x13, 0x06, 0x07, 0x03, 0xb5, 0xbf, 0x41, - 0x11, 0x26, 0xc2, 0xb7, 0x34, 0x20, 0x00, 0x2a, 0x86, 0xae, 0x86, 0x13, 0x85, 0x84, 0xea, 0x93, 0x05, 0x00, 0x08, - 0x06, 0xc6, 0x22, 0xc4, 0xef, 0xf0, 0xbf, 0xe5, 0x2a, 0x84, 0x13, 0x85, 0x84, 0xea, 0xef, 0xd0, 0x8f, 0x9b, 0xb2, - 0x40, 0x22, 0x85, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x26, 0xca, 0xb7, 0x34, 0x20, 0x00, - 0x2e, 0xd2, 0x32, 0xd4, 0x36, 0xd6, 0x2a, 0x86, 0x54, 0x10, 0x93, 0x05, 0x00, 0x08, 0x13, 0x85, 0x84, 0xea, 0x06, - 0xce, 0x22, 0xcc, 0x3a, 0xd8, 0x3e, 0xda, 0x42, 0xdc, 0x46, 0xde, 0x36, 0xc6, 0xef, 0xf0, 0x9f, 0xe1, 0x2a, 0x84, - 0x13, 0x85, 0x84, 0xea, 0xfa, 0x4f, 0x82, 0xf5, 0x7e, 0x43, 0x23, 0x29, 0xf0, 0x77, 0x76, 0x2c, 0x66, 0x4c, 0xce, - 0x3a, 0x5b, 0x6a, 0xba, 0x96, 0xfc, 0x39, 0xc3, 0xa7, 0x0e, 0xd2, 0xdf, 0xed, 0xb7, 0x03, 0x5c, 0x83, 0x12, 0xe8, - 0x56, 0xef, 0xd0, 0x6f, 0x97, 0xf2, 0x40, 0x22, 0x85, 0x62, 0x44, 0xd2, 0x44, 0x21, 0x61, 0x82, 0x80, 0x22, 0x05, - 0x61, 0x77, 0x2d, 0x8d, 0xa1, 0x47, 0x15, 0x07, 0x93, 0x16, 0x05, 0x01, 0x06, 0x05, 0x42, 0x05, 0xc1, 0x86, 0x41, - 0x81, 0x63, 0xd5, 0x06, 0x00, 0x39, 0x8d, 0x42, 0x05, 0x41, 0x81, 0xfd, 0x17, 0xe5, 0xf7, 0x82, 0x80, 0x41, 0x11, - 0x22, 0xc4, 0x26, 0xc2, 0x2a, 0x84, 0xb3, 0x04, 0xb5, 0x00, 0x06, 0xc6, 0x01, 0x45, 0x63, 0x97, 0x84, 0x00, 0xb2, - 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x04, 0xaa, 0x85, 0x03, 0x45, 0xf4, 0xff, 0xef, 0xf0, - 0x5f, 0xfb, 0xdd, 0xb7, 0xb7, 0x86, 0xb8, 0xed, 0x01, 0x47, 0xfd, 0x57, 0x93, 0x86, 0x06, 0x32, 0x63, 0x15, 0xb7, - 0x00, 0x13, 0xc5, 0xf7, 0xff, 0x82, 0x80, 0x33, 0x06, 0xe5, 0x00, 0x03, 0x46, 0x06, 0x00, 0xb1, 0x8f, 0x21, 0x46, - 0x13, 0xd8, 0x17, 0x00, 0x85, 0x8b, 0x91, 0xc3, 0xb6, 0x87, 0x7d, 0x16, 0xb3, 0x47, 0xf8, 0x00, 0x65, 0xfa, 0x05, - 0x07, 0xd9, 0xbf, 0x2a, 0x83, 0x09, 0xca, 0x83, 0x83, 0x05, 0x00, 0x23, 0x00, 0x73, 0x00, 0x7d, 0x16, 0x05, 0x03, - 0x85, 0x05, 0x6d, 0xfa, 0x82, 0x80, 0x15, 0xc2, 0x2a, 0x83, 0x85, 0x46, 0x63, 0x67, 0xb5, 0x00, 0xfd, 0x56, 0x13, - 0x07, 0xf6, 0xff, 0x3a, 0x93, 0xba, 0x95, 0x83, 0x83, 0x05, 0x00, 0x23, 0x00, 0x73, 0x00, 0x7d, 0x16, 0x36, 0x93, - 0xb6, 0x95, 0x6d, 0xfa, 0x82, 0x80, 0x2a, 0x83, 0xfa, 0xa6, 0xc8, 0xcd, 0xda, 0xc8, 0x00, 0x98, 0xe6, 0xa6, 0x42, - 0x5e, 0x14, 0x62, 0xa7, 0xc7, 0xaa, 0x0d, 0xc7, 0x0f, 0xde, 0x0f, 0xdc, 0x00, 0x91, 0x22, 0xa1, 0xea, 0x24, 0x09, - 0x49, 0x80, 0xd4, 0xc0, 0x57, 0x11, 0xc6, 0x23, 0x00, 0xb3, 0x00, 0x7d, 0x16, 0x05, 0x03, 0x65, 0xfe, 0x82, 0x80, - 0x00, 0x00, 0x63, 0x6f, 0x64, 0x65, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, 0x53, 0x45, 0x43, 0x43, 0x48, - 0x4e, 0x4c, 0x00, 0x4d, 0x43, 0x4e, 0x54, 0x00, 0x00, 0x00, 0x00, 0x54, 0x58, 0x3a, 0x20, 0x25, 0x64, 0x2f, 0x25, - 0x64, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x43, 0x4d, 0x44, 0x33, 0x00, 0x00, 0x00, 0x00, 0x49, 0x00, 0x00, - 0x00, 0x65, 0x6e, 0x61, 0x62, 0x6c, 0x65, 0x64, 0x20, 0x25, 0x64, 0x00, 0x00, 0x4d, 0x41, 0x49, 0x4e, 0x00, 0x00, - 0x00, 0x00, 0x6c, 0x65, 0x6e, 0x20, 0x25, 0x64, 0x2f, 0x25, 0x64, 0x00, 0x00, 0x00, 0x72, 0x73, 0x70, 0x3d, 0x25, - 0x78, 0x00, 0x00, 0x73, 0x74, 0x61, 0x72, 0x74, 0x2c, 0x20, 0x76, 0x25, 0x75, 0x2e, 0x25, 0x75, 0x2e, 0x25, 0x75, - 0x00, 0x00, 0x00, 0x00, 0x50, 0x52, 0x4f, 0x56, 0x49, 0x53, 0x49, 0x4f, 0x4e, 0x20, 0x4f, 0x4b, 0x00, 0x00, 0x00, - 0x00, 0x4e, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x43, 0x50, 0x42, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x4c, 0x33, - 0x20, 0x63, 0x6d, 0x64, 0x20, 0x25, 0x64, 0x3a, 0x20, 0x25, 0x78, 0x2c, 0x20, 0x6c, 0x65, 0x6e, 0x3a, 0x20, 0x25, - 0x64, 0x00, 0x00, 0x4c, 0x33, 0x20, 0x61, 0x63, 0x63, 0x65, 0x73, 0x73, 0x20, 0x66, 0x61, 0x69, 0x6c, 0x65, 0x64, - 0x2c, 0x20, 0x63, 0x6d, 0x64, 0x3a, 0x20, 0x25, 0x64, 0x2c, 0x20, 0x6c, 0xfa, 0x53, 0x55, 0xdd, 0x52, 0x34, 0x63, - 0x1c, 0x99, 0x07, 0xfe, 0xe1, 0x96, 0x57, 0xc6, 0xb2, 0x75, 0x87, 0xef, 0x27, 0x44, 0x95, 0xe6, 0x44, 0x00, 0xd6, - 0x11, 0xa1, 0xc2, 0x85, 0x14, 0xcc, 0xcb, 0x98, 0x58, 0x65, 0x6e, 0x3a, 0x20, 0x25, 0x64, 0x20, 0x00, 0x70, 0x69, - 0x6e, 0x67, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x00, 0x4c, 0x33, 0x00, 0x00, 0x57, 0x52, 0x3a, 0x20, 0x25, - 0x64, 0x00, 0x00, 0x52, 0x44, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x00, 0x6d, 0x61, 0x63, 0x61, 0x6e, 0x64, 0x64, 0x2c, - 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x00, 0x00, 0x73, 0x65, 0x6e, 0x74, 0x00, 0x00, 0x00, 0x00, 0x65, 0x6e, 0x74, - 0x65, 0x72, 0x20, 0x73, 0x6c, 0x65, 0x65, 0x70, 0x00, 0x77, 0x61, 0x6b, 0x65, 0x75, 0x70, 0x00, 0x00, 0x56, 0x19, - 0x10, 0x00, 0x94, 0x19, 0x10, 0x00, 0xc0, 0x19, 0x10, 0x00, 0xf0, 0x19, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, - 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, - 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, - 0x00, 0xf8, 0x13, 0x10, 0x00, 0x0a, 0x1a, 0x10, 0x00, 0x64, 0x1a, 0x10, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, - 0x00, 0x00, 0x80, 0x1f, 0x00, 0x06, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x1f, 0x00, 0x06, 0x02, - 0x00, 0x05, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x06, 0x03, 0x10, 0x08, 0x00, 0x00, 0x18, 0x00, 0x00, - 0x40, 0x1f, 0x00, 0x06, 0x06, 0x10, 0x08, 0x00, 0x04, 0x18, 0x00, 0x00, 0x60, 0x1f, 0x00, 0x06, 0xfa, 0x85, 0xe0, - 0x36, 0x11, 0x49, 0x41, 0x92, 0x3d, 0x86, 0xd4, 0x75, 0x3a, 0x7c, 0x31, 0xcc, 0x20, 0x59, 0x14, 0x0a, 0x95, 0xba, - 0x92, 0xba, 0x8e, 0x4f, 0x7a, 0xec, 0x60, 0xd3, 0x0c, 0x3a, 0xcf, 0x70, 0x59, 0x04, 0x00, 0x09, 0x01, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x80, 0x06, 0x05, 0x05, 0x7f, 0x07, 0x01, 0x08, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - 0xf0, 0x01, 0x10, 0x10, 0x00, 0x04, 0x02, 0x11, 0x00, 0x44, 0x02, 0x12, 0x00, 0x84, 0x02, 0x20, 0x90, 0x01, 0x03, - 0x21, 0x80, 0x42, 0x03, 0x22, 0xf0, 0x01, 0x03, 0x30, 0x80, 0x02, 0x04, 0x31, 0x80, 0x42, 0x04, 0x40, 0x70, 0x04, - 0x11, 0x41, 0x70, 0x44, 0x11, 0x42, 0x70, 0x84, 0x11, 0x50, 0xf0, 0x01, 0x12, 0x60, 0x32, 0x04, 0x13, 0x61, 0x32, - 0x44, 0x13, 0x62, 0x32, 0x84, 0x13, 0x63, 0x32, 0xc4, 0x13, 0x70, 0x32, 0x04, 0x14, 0x71, 0x32, 0x44, 0x14, 0x80, - 0x20, 0x04, 0x15, 0x81, 0x20, 0x84, 0x15, 0x82, 0x20, 0x44, 0x15, 0x90, 0x51, 0x04, 0x16, 0x00, 0x00, 0x00, 0x00, - 0xff, 0x00, 0x00, 0x00, 0x00, 0x14, 0x04, 0x04, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x20, 0x25, 0x6c, 0x75, 0x20, - 0x00, 0x00, 0x25, 0x73, 0x28, 0x25, 0x73, 0x29, 0x3a, 0x20, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x45, - 0x00, 0x00, 0x00, 0x4d, 0x53, 0x47, 0x00, 0x43, 0x52, 0x43, 0x20, 0x72, 0x78, 0x3a, 0x20, 0x25, 0x30, 0x34, 0x78, - 0x2c, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x3a, 0x20, 0x25, 0x30, 0x34, 0x78, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, - 0x00, 0xfa, 0xab, 0xdf, 0x5f, 0xff, 0xec, 0xf4, 0xbc, 0x19, 0x3c, 0xb2, 0x93, 0x30, 0x2f, 0x7d, 0x58, 0xe6, 0x85, - 0xd3, 0x3d, 0x95, 0xc9, 0x91, 0x95, 0x01, 0x02, 0xfd, 0x7a, 0xb9, 0x0c, 0x61, 0x3e, 0x85, 0x48, 0x5a, 0xe4, 0x1f, - 0x10, 0x00, 0x04, 0x20, 0x10, 0x00, 0x56, 0x20, 0x10, 0x00, 0xb8, 0x20, 0x10, 0x00, 0xc2, 0x20, 0x10, 0x00, 0x4f, - 0x53, 0x00, 0x00, 0x63, 0x6f, 0x6e, 0x64, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, 0x52, 0x58, 0x3a, 0x20, - 0x63, 0x6d, 0x64, 0x3d, 0x30, 0x78, 0x25, 0x30, 0x32, 0x78, 0x00, 0x00, 0x55, 0x49, 0x00, 0x00, 0x43, 0x50, 0x42, - 0x20, 0x49, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x20, 0x21, 0x00, 0x43, 0x50, 0x42, 0x00, 0x57, 0x00, - 0x00, 0x00, 0x46, 0x53, 0x53, 0x00, 0x49, 0x52, 0x51, 0x00, 0x53, 0x54, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x4b, - 0x44, 0x42, 0x00, 0x73, 0x74, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x4d, 0x41, 0x44, 0x00, 0x4f, 0x54, 0x50, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x53, 0x43, 0x42, 0x00, 0x4e, 0x6f, 0x69, 0x73, 0x65, 0x5f, 0x4b, 0x4b, 0x31, 0x5f, 0x32, - 0x35, 0x35, 0x31, 0x39, 0x5f, 0x41, 0x45, 0x53, 0x47, 0x43, 0x4d, 0x5f, 0x53, 0x48, 0x41, 0x32, 0x35, 0x36, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x3f, 0x10, 0x00, 0x78, 0x45, 0x10, 0x00, 0x62, 0x45, 0x10, 0x00, 0x26, - 0x45, 0x10, 0x00, 0x3a, 0x3e, 0x10, 0x00, 0xd0, 0x45, 0x10, 0x00, 0x41, 0x4c, 0x41, 0x52, 0x4d, 0x20, 0x43, 0x48, - 0x41, 0x4e, 0x4e, 0x45, 0x4c, 0x53, 0x3a, 0x20, 0x25, 0x78, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x53, 0x43, 0x4e, - 0x54, 0x52, 0x00, 0x00, 0x00, 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x20, 0x5b, 0x53, 0x50, 0x45, 0x43, 0x54, 0x00, 0x00, 0x00, 0xc3, 0x14, 0x13, 0x00}; \ No newline at end of file +const uint8_t fw_CPU[] = { + 0x68, 0x7b, 0x1f, 0x5f, 0x8a, 0xfa, 0xff, 0xb1, 0xa1, 0xdd, 0xcb, 0x77, 0xcb, 0x04, 0x01, 0xa8, + 0x25, 0x9d, 0xbc, 0x51, 0xc3, 0x26, 0x45, 0xa2, 0xde, 0x55, 0x2c, 0xd5, 0xbd, 0x9c, 0xa6, 0x77, + 0x27, 0xfc, 0x29, 0xad, 0xd9, 0x5c, 0xb2, 0x23, 0xda, 0x05, 0x8f, 0x4b, 0xaa, 0x71, 0x8d, 0x63, + 0x9b, 0x24, 0x28, 0x00, 0x3f, 0xf4, 0x63, 0x29, 0x0e, 0x42, 0xd0, 0x09, 0x02, 0x74, 0xed, 0x64, + 0x0f, 0x0f, 0xd0, 0x75, 0xb6, 0xcc, 0xb1, 0x94, 0x3e, 0xfd, 0x07, 0x46, 0xc3, 0xda, 0xbe, 0x5f, + 0xc9, 0xff, 0x39, 0x84, 0x13, 0x5a, 0x9d, 0xb6, 0x2c, 0x65, 0x88, 0x2e, 0x18, 0x03, 0xd4, 0xc2, + 0x72, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0xfa, 0x79, 0xf4, 0xfe, 0x81, 0x56, 0x6e, + 0xdc, 0x29, 0x3d, 0xb2, 0xe1, 0x3b, 0xa1, 0xfa, 0x98, 0x2b, 0x31, 0xc8, 0xcc, 0x7e, 0x58, 0x13, + 0x41, 0x3d, 0x50, 0x9d, 0x82, 0xd3, 0x5d, 0xb5, 0x23, 0x56, 0x00, 0x00, 0xc0, 0xa6, 0xd9, 0x50, + 0x89, 0xe0, 0x6b, 0xd4, 0xd6, 0x78, 0x33, 0x1a, 0x36, 0x2b, 0x60, 0x8d, 0xbb, 0x82, 0xe3, 0x56, + 0xf4, 0x83, 0x89, 0x9c, 0xe7, 0x0a, 0x77, 0x0d, 0xeb, 0x72, 0x15, 0xf2, 0xf5, 0x46, 0xbe, 0xa8, + 0x43, 0x6b, 0xa9, 0xc9, 0x2d, 0x74, 0xa3, 0x34, 0x48, 0x56, 0x2c, 0x6e, 0x77, 0xa6, 0x12, 0x75, + 0x87, 0x10, 0x50, 0xd8, 0xf0, 0xa3, 0x1f, 0x2e, 0xea, 0xdc, 0x9b, 0x0a, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfa, 0xd3, 0x83, 0x87, 0x72, 0xb4, 0xff, 0xa1, 0xb6, 0x43, 0x95, 0xa8, + 0x07, 0xcf, 0x88, 0xe8, 0x32, 0x17, 0x89, 0x90, 0x87, 0xb4, 0xd5, 0x4e, 0xcc, 0xbb, 0x97, 0xf4, + 0x3e, 0xe0, 0x46, 0xd4, 0x69, 0xd8, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, + 0x38, 0xd8, 0x68, 0x70, 0x75, 0xac, 0x2a, 0x66, 0x52, 0x1e, 0xf7, 0x61, 0x4f, 0x8d, 0xc0, 0x05, + 0x5a, 0x90, 0x0b, 0x8c, 0xe8, 0x87, 0xa8, 0x50, 0xb9, 0xfd, 0xa7, 0x5b, 0x0b, 0x14, 0x7a, 0x9b, + 0xb0, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x2c, 0x57, 0x00, 0x00, 0xbe, 0x52, + 0xea, 0x0a, 0xe3, 0x51, 0x85, 0x8b, 0x68, 0x79, 0xed, 0x3f, 0x06, 0xb0, 0xa3, 0x97, 0x8e, 0x8a, + 0x18, 0xd6, 0x4d, 0x72, 0xb4, 0xcc, 0xb2, 0x13, 0xc3, 0x64, 0x76, 0x30, 0xf7, 0x31, 0x82, 0x64, + 0x8f, 0xda, 0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x5c, 0x23, 0x4d, 0x45, 0x4e, + 0xd2, 0x6d, 0x46, 0x30, 0x20, 0x2d, 0x5b, 0x5c, 0x4f, 0x73, 0xf7, 0x03, 0x7b, 0xe6, 0x42, 0x9d, + 0x50, 0x17, 0xe0, 0xf2, 0xbb, 0x26, 0x1c, 0x67, 0x71, 0x47, 0xcf, 0x88, 0x02, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xa5, 0x83, 0xfc, 0x9d, 0x7b, 0xe3, 0x4b, 0x6a, 0xab, 0x74, + 0x96, 0x89, 0xd9, 0xa9, 0x67, 0xc0, 0xb1, 0x6d, 0x91, 0x7a, 0x70, 0x92, 0x1b, 0xae, 0x7c, 0x81, + 0x25, 0xc1, 0xdd, 0x3b, 0x7d, 0x3e, 0x60, 0x03, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x6f, 0x30, 0x00, 0x43, 0x6f, 0x30, 0x20, 0x3d, + 0x6f, 0x30, 0xe0, 0x3c, 0x6f, 0x30, 0xa0, 0x3c, 0x6f, 0x30, 0x60, 0x3c, 0x6f, 0x30, 0x20, 0x3c, + 0x6f, 0x30, 0xe0, 0x3b, 0x6f, 0x50, 0x60, 0x04, 0x6f, 0x30, 0x60, 0x3b, 0x6f, 0x30, 0x20, 0x3b, + 0x6f, 0x30, 0xe0, 0x3a, 0x6f, 0x30, 0xa0, 0x7f, 0x6f, 0x30, 0x60, 0x3a, 0x6f, 0x30, 0x20, 0x3a, + 0xfa, 0xd8, 0x31, 0xce, 0x5f, 0xa8, 0x9e, 0x11, 0x71, 0xdc, 0x79, 0xcd, 0xd3, 0x3a, 0x7e, 0xcb, + 0x3b, 0x3f, 0x92, 0x79, 0x19, 0x91, 0xe4, 0xd3, 0x9f, 0xdf, 0x5d, 0x61, 0x69, 0x67, 0x25, 0x53, + 0xa5, 0x38, 0x04, 0x6f, 0x30, 0xe0, 0x39, 0x6f, 0x30, 0xa0, 0x39, 0x6f, 0x40, 0xf0, 0x72, 0x6f, + 0x30, 0x20, 0x26, 0x6f, 0x30, 0x50, 0x20, 0x6f, 0x40, 0x30, 0x22, 0x6f, 0x40, 0xf0, 0x21, 0x6f, + 0x40, 0xb0, 0x21, 0x6f, 0x30, 0xa0, 0x4c, 0x6f, 0x30, 0xa0, 0x4d, 0x6f, 0x30, 0xf0, 0x42, 0x6f, + 0x40, 0x50, 0x56, 0x6f, 0x30, 0x20, 0x4e, 0x6f, 0x20, 0x30, 0x1f, 0x6f, 0x40, 0x70, 0x0a, 0x6f, + 0x30, 0xa0, 0x4e, 0x6f, 0x30, 0x00, 0x5b, 0x6f, 0x30, 0x00, 0x3f, 0x93, 0x00, 0x00, 0x00, 0x13, + 0x01, 0x00, 0x00, 0x93, 0x01, 0x00, 0x00, 0x13, 0x02, 0x00, 0x00, 0x93, 0x02, 0x00, 0x00, 0x13, + 0x03, 0x00, 0x00, 0x93, 0x03, 0x00, 0x00, 0x13, 0x04, 0x00, 0x00, 0x93, 0x04, 0x00, 0x00, 0x13, + 0x05, 0x00, 0x00, 0x93, 0x05, 0x00, 0x00, 0x13, 0x06, 0x00, 0x00, 0x93, 0x06, 0x00, 0x00, 0x13, + 0x07, 0x00, 0x00, 0x93, 0x07, 0x00, 0x00, 0x13, 0x08, 0x00, 0x00, 0x93, 0x08, 0x00, 0x00, 0x13, + 0x09, 0x00, 0x00, 0x93, 0x09, 0x00, 0x00, 0x13, 0x0a, 0x00, 0x00, 0x93, 0x0a, 0x00, 0x00, 0x13, + 0x0b, 0x00, 0x00, 0x93, 0x0b, 0x00, 0x00, 0x13, 0x0c, 0x00, 0x00, 0x93, 0x0c, 0x00, 0x00, 0x13, + 0x0d, 0x00, 0x00, 0x93, 0x0d, 0x00, 0x00, 0x13, 0x0e, 0x00, 0x00, 0x93, 0x0e, 0x00, 0x00, 0x13, + 0x0f, 0x00, 0x00, 0x93, 0x0f, 0x00, 0x00, 0x97, 0x00, 0x00, 0x00, 0x93, 0x80, 0x40, 0xf0, 0x73, + 0x90, 0x50, 0x30, 0x93, 0x00, 0x00, 0x00, 0x17, 0x41, 0x10, 0x00, 0xfa, 0x8c, 0x38, 0x4b, 0x9e, + 0xf7, 0xd8, 0x36, 0x8a, 0x5e, 0xb4, 0xaf, 0x58, 0xe5, 0x16, 0x9f, 0x62, 0x85, 0xb1, 0xa9, 0x34, + 0xb8, 0x37, 0x50, 0xd0, 0x6f, 0x48, 0x35, 0x7b, 0xfd, 0xbb, 0x88, 0x6b, 0x10, 0x05, 0x13, 0x01, + 0x41, 0xcf, 0x33, 0x04, 0x01, 0x00, 0x17, 0x0d, 0x10, 0x00, 0x13, 0x0d, 0x8d, 0xee, 0x97, 0x4d, + 0x10, 0x00, 0x93, 0x8d, 0x0d, 0xce, 0x63, 0x57, 0xbd, 0x01, 0x23, 0x20, 0x0d, 0x00, 0x11, 0x0d, + 0xe3, 0x4d, 0xbd, 0xff, 0xef, 0x00, 0xf0, 0x60, 0x73, 0x00, 0x50, 0x10, 0xf5, 0xbf, 0xb7, 0x37, + 0x20, 0x00, 0x23, 0xa6, 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0x07, 0xf4, 0xb7, 0x37, + 0x20, 0x00, 0x23, 0xac, 0x07, 0xf2, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0x07, 0xf2, 0xb7, 0x37, + 0x20, 0x00, 0x23, 0x88, 0x07, 0xf2, 0x82, 0x80, 0x18, 0x41, 0xfd, 0x57, 0x63, 0x02, 0xf7, 0x06, + 0x13, 0x07, 0x45, 0x00, 0x81, 0x47, 0x13, 0x06, 0xf0, 0x07, 0x14, 0x43, 0x81, 0xea, 0x85, 0x07, + 0x11, 0x07, 0xe3, 0x9c, 0xc7, 0xfe, 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x01, 0x47, 0x93, 0x05, + 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, 0x05, 0x8a, 0x19, 0xca, 0x93, 0x05, 0x00, 0x02, 0x33, 0xd6, + 0xe6, 0x00, 0x05, 0x8a, 0x15, 0xc6, 0x05, 0x07, 0xe3, 0x1b, 0xb7, 0xfe, 0x21, 0xa0, 0x05, 0x07, + 0xe3, 0x11, 0xb7, 0xfe, 0x89, 0x07, 0x93, 0x06, 0x00, 0x08, 0x7d, 0x56, 0xe3, 0x85, 0xd7, 0xfc, + 0x85, 0x07, 0x13, 0x97, 0x27, 0x00, 0x2a, 0x97, 0x03, 0x27, 0xc7, 0xff, 0xe3, 0x08, 0xc7, 0xfe, + 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x05, 0x67, 0xaa, 0x87, 0x01, 0x17, 0x01, 0x45, 0x94, 0x43, + 0x99, 0xe6, 0x13, 0x05, 0x05, 0x02, 0xfa, 0x52, 0x1b, 0x54, 0xca, 0x45, 0x78, 0x0a, 0xe4, 0xbf, + 0x96, 0x91, 0x74, 0x22, 0x07, 0xd7, 0xc2, 0x2c, 0x98, 0x2c, 0xcb, 0x7c, 0x27, 0xd3, 0x77, 0x07, + 0x3b, 0x7e, 0x40, 0x3b, 0x6a, 0x3c, 0x0b, 0xe8, 0x05, 0x91, 0x07, 0xe3, 0x1b, 0xe5, 0xfe, 0x82, + 0x80, 0x81, 0x47, 0x13, 0x06, 0x00, 0x02, 0x33, 0xd7, 0xf6, 0x00, 0x05, 0x8b, 0x09, 0xe7, 0x85, + 0x07, 0x05, 0x05, 0xe3, 0x9a, 0xc7, 0xfe, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x14, 0x20, + 0x00, 0x13, 0x04, 0x04, 0x00, 0x83, 0x46, 0x94, 0x07, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, + 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, 0x64, 0x13, 0x06, 0x06, 0x3d, 0x93, 0x85, 0xc5, + 0x3d, 0x06, 0xc6, 0xef, 0x10, 0x30, 0x4c, 0x03, 0x45, 0x94, 0x07, 0xb2, 0x40, 0x22, 0x44, 0x41, + 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x40, 0x90, 0x0b, 0xef, 0x20, 0xc0, 0x58, 0x93, + 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x00, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x40, 0x50, 0x0c, 0xb2, + 0x40, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x05, 0x05, 0x10, 0x2a, 0x84, 0x37, + 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, 0x3e, 0x06, 0xc6, 0xef, 0x10, 0x30, 0x4f, 0x37, 0x37, 0x20, + 0x00, 0x13, 0x07, 0x47, 0xf5, 0x14, 0x43, 0x85, 0x47, 0xb3, 0x97, 0x87, 0x00, 0xb2, 0x40, 0x22, + 0x44, 0x93, 0xc7, 0xf7, 0xff, 0xf5, 0x8f, 0x1c, 0xc3, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, + 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x2a, 0x84, 0x93, 0x04, 0xa0, 0x0a, 0xef, 0x20, 0x10, 0x76, 0x63, + 0x19, 0x95, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, + 0x80, 0xfa, 0x95, 0xa9, 0xbb, 0xb8, 0x79, 0xf6, 0x12, 0x84, 0xcc, 0xba, 0xc5, 0xe8, 0x6c, 0xb3, + 0xc4, 0xb5, 0x96, 0x43, 0x09, 0x28, 0x37, 0xb4, 0x8f, 0xdb, 0x78, 0xe7, 0x28, 0xf4, 0x79, 0xba, + 0xac, 0x94, 0xc0, 0x06, 0x22, 0x85, 0xef, 0x20, 0x90, 0x78, 0x22, 0x85, 0xef, 0x20, 0x30, 0x74, + 0xe3, 0x03, 0x95, 0xfe, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, 0x3e, 0x85, 0x45, 0xef, 0x10, + 0x10, 0x49, 0x13, 0x05, 0x50, 0x05, 0xd1, 0xbf, 0x01, 0x11, 0x22, 0xcc, 0x2a, 0x84, 0x37, 0x35, + 0x00, 0x08, 0x06, 0xce, 0x2e, 0xc6, 0xef, 0x30, 0x10, 0x0a, 0x32, 0x46, 0xa2, 0x85, 0x37, 0x35, + 0x00, 0x08, 0xef, 0x30, 0x50, 0x0e, 0x62, 0x44, 0xf2, 0x40, 0x37, 0x35, 0x00, 0x08, 0x05, 0x61, + 0x6f, 0x30, 0xb0, 0x0b, 0x6d, 0x71, 0x23, 0x24, 0x81, 0x10, 0x2a, 0x84, 0x0a, 0x85, 0x23, 0x26, + 0x11, 0x10, 0xef, 0x10, 0x50, 0x63, 0x0a, 0x85, 0x23, 0x00, 0x81, 0x00, 0xef, 0x20, 0xc0, 0x3e, + 0x83, 0x20, 0xc1, 0x10, 0x03, 0x24, 0x81, 0x10, 0x51, 0x61, 0x82, 0x80, 0x01, 0x11, 0x06, 0xce, + 0x2a, 0xc6, 0x2e, 0xc4, 0xef, 0x20, 0xd0, 0x1a, 0xa2, 0x45, 0x32, 0x45, 0xef, 0x20, 0xd0, 0x32, + 0x2a, 0xc4, 0xef, 0x20, 0x90, 0x1b, 0xf2, 0x40, 0x22, 0x45, 0x05, 0x61, 0x82, 0x80, 0x13, 0x01, + 0x01, 0xde, 0x23, 0x2c, 0x81, 0x20, 0x2e, 0x84, 0xaa, 0x05, 0x23, 0x28, 0x21, 0x21, 0x93, 0x85, + 0x05, 0x20, 0x2a, 0x89, 0x08, 0x08, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x2a, 0x91, 0x20, 0x7d, 0x3f, + 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x04, 0xaa, 0x84, 0x08, 0x08, 0xcd, 0x33, 0x63, 0x00, + 0x95, 0x02, 0x22, 0x85, 0xd1, 0x3d, 0x09, 0x45, 0x83, 0x20, 0xc1, 0x21, 0xfa, 0x6d, 0xda, 0xfa, + 0x5d, 0x24, 0x3d, 0x74, 0xe5, 0x1a, 0x0d, 0x11, 0x43, 0xbe, 0xb6, 0x3c, 0x6f, 0xc8, 0x25, 0xaf, + 0x99, 0x26, 0x67, 0xee, 0xd0, 0x92, 0xc0, 0xc6, 0x1b, 0x2e, 0x4f, 0xbd, 0x8c, 0x98, 0x07, 0x03, + 0x24, 0x81, 0x21, 0x83, 0x24, 0x41, 0x21, 0x03, 0x29, 0x01, 0x21, 0x13, 0x01, 0x01, 0x22, 0x82, + 0x80, 0x42, 0x44, 0x48, 0x08, 0x22, 0xc6, 0x25, 0x35, 0x09, 0x8c, 0x11, 0x46, 0x6c, 0x00, 0x4a, + 0x85, 0x22, 0xc6, 0xef, 0x40, 0x70, 0x7c, 0x05, 0x45, 0xc9, 0xbf, 0x01, 0x45, 0xf9, 0xb7, 0x41, + 0x11, 0x4a, 0xc0, 0x03, 0xa9, 0x05, 0x00, 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0x2e, 0x84, 0xaa, + 0x84, 0xef, 0x20, 0x10, 0x67, 0xca, 0x85, 0x26, 0x85, 0xef, 0x20, 0x70, 0x1e, 0xa6, 0x85, 0x22, + 0x85, 0xef, 0x20, 0xb0, 0x28, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x02, 0x1c, 0x40, 0x63, + 0x93, 0x27, 0x03, 0x93, 0x07, 0x44, 0x00, 0x7d, 0x57, 0x13, 0x04, 0x04, 0x20, 0x94, 0x43, 0x63, + 0x9b, 0xe6, 0x00, 0x91, 0x07, 0xe3, 0x9c, 0x87, 0xfe, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x02, + 0x49, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0xc5, 0xbf, 0x13, 0x01, 0x01, 0xde, 0x23, + 0x26, 0x31, 0x21, 0x93, 0x19, 0xa5, 0x00, 0x23, 0x2a, 0x91, 0x20, 0x93, 0x84, 0x09, 0x20, 0x23, + 0x2c, 0x81, 0x20, 0xa6, 0x85, 0x2a, 0x84, 0x0a, 0x85, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x28, 0x21, + 0x21, 0xfd, 0x35, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x00, 0xf5, 0x02, 0x01, 0x45, 0x83, 0x20, 0xc1, + 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, 0x41, 0x21, 0x03, 0x29, 0x01, 0x21, 0x83, 0x29, 0xc1, + 0x20, 0x13, 0x01, 0x01, 0x22, 0x82, 0x80, 0xfa, 0xf5, 0x68, 0x71, 0xa8, 0x2d, 0xa8, 0x39, 0x0f, + 0xbb, 0x03, 0xbc, 0x0a, 0x15, 0xc4, 0x54, 0xe1, 0xdd, 0x4e, 0xe3, 0xd6, 0x42, 0x20, 0xb3, 0x5a, + 0xdf, 0x9b, 0x20, 0xe0, 0x92, 0xad, 0x96, 0x83, 0x70, 0x08, 0x2a, 0x89, 0x0a, 0x85, 0xdd, 0x39, + 0x63, 0x06, 0x25, 0x01, 0x22, 0x85, 0xe5, 0x33, 0x09, 0x45, 0xd9, 0xbf, 0x02, 0x44, 0x48, 0x00, + 0x89, 0x3b, 0xaa, 0x87, 0x33, 0x06, 0xa4, 0x40, 0x0d, 0x45, 0xe3, 0x03, 0xf4, 0xfc, 0x09, 0x45, + 0xe3, 0x60, 0xc4, 0xfc, 0x5c, 0x00, 0x01, 0x44, 0x13, 0x08, 0x00, 0x02, 0x13, 0x05, 0xf0, 0x07, + 0x8c, 0x43, 0x89, 0xc9, 0x81, 0x46, 0x33, 0xd7, 0xd5, 0x00, 0x05, 0x8b, 0x05, 0xeb, 0x85, 0x06, + 0xe3, 0x9b, 0x06, 0xff, 0x05, 0x04, 0x91, 0x07, 0xe3, 0x14, 0xa4, 0xfe, 0x7d, 0x16, 0x8a, 0x85, + 0x13, 0x85, 0x09, 0x40, 0x32, 0xc0, 0xf5, 0x3d, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x11, 0xf5, 0xf8, + 0x8a, 0x85, 0x26, 0x85, 0xfd, 0x35, 0x13, 0x05, 0x65, 0xf5, 0x1d, 0xa8, 0x05, 0x47, 0x33, 0x17, + 0xd7, 0x00, 0x13, 0x47, 0xf7, 0xff, 0x6d, 0x8f, 0x98, 0xc3, 0xef, 0x20, 0xc0, 0x7f, 0x18, 0x04, + 0x93, 0x17, 0x24, 0x00, 0xba, 0x97, 0x83, 0xa5, 0x47, 0xe0, 0x13, 0x05, 0x14, 0x00, 0x0a, 0x05, + 0x26, 0x95, 0xef, 0x20, 0x50, 0x10, 0x2a, 0x84, 0xef, 0x20, 0x80, 0x7f, 0x13, 0x05, 0x64, 0xf5, + 0x13, 0x35, 0x15, 0x00, 0x35, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x07, 0x30, 0x0c, + 0x2a, 0x84, 0x63, 0x04, 0xf5, 0x00, 0xef, 0x20, 0xc0, 0x4b, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, + 0x07, 0x00, 0x05, 0x67, 0x23, 0x80, 0x87, 0x00, 0xba, 0x97, 0xf8, 0x5b, 0x19, 0xe3, 0x05, 0x47, + 0xf8, 0xdb, 0xfa, 0x1e, 0x3c, 0x60, 0x76, 0xc5, 0x61, 0xca, 0xfe, 0xbf, 0x37, 0x81, 0x1a, 0x70, + 0x4b, 0xb9, 0x7f, 0xa3, 0x87, 0x18, 0x19, 0x39, 0x58, 0xc4, 0x05, 0x1e, 0xfa, 0xfa, 0x82, 0xf8, + 0xbd, 0xd2, 0x6a, 0x48, 0x09, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x66, 0x37, + 0x05, 0x20, 0x00, 0x41, 0x11, 0x13, 0x06, 0xc6, 0x07, 0x81, 0x45, 0x13, 0x05, 0x05, 0x00, 0x06, + 0xc6, 0xef, 0x40, 0xb0, 0x65, 0xef, 0x20, 0x80, 0x41, 0xef, 0x40, 0x80, 0x39, 0xb2, 0x40, 0x41, + 0x01, 0x6f, 0x20, 0x00, 0x38, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x20, 0x00, 0x55, 0xef, 0x20, 0x90, + 0x7f, 0xef, 0x40, 0xa0, 0x0c, 0xef, 0x40, 0x00, 0x65, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x30, 0xe0, + 0x15, 0x69, 0x71, 0x08, 0x08, 0x23, 0x22, 0x91, 0x12, 0x23, 0x20, 0x21, 0x13, 0x23, 0x2c, 0x41, + 0x11, 0x23, 0x26, 0x11, 0x12, 0x23, 0x24, 0x81, 0x12, 0x23, 0x2e, 0x31, 0x11, 0x23, 0x2a, 0x51, + 0x11, 0xef, 0x10, 0xf0, 0x39, 0x91, 0x47, 0x37, 0x39, 0x20, 0x00, 0x23, 0x08, 0xf1, 0x00, 0x83, + 0x27, 0xc9, 0xf4, 0x37, 0x1a, 0x20, 0x00, 0xb7, 0x34, 0x20, 0x00, 0x13, 0x09, 0xc9, 0xf4, 0x13, + 0x0a, 0x0a, 0x00, 0x93, 0x84, 0x84, 0xf4, 0xc5, 0xe7, 0x83, 0x27, 0x4a, 0x07, 0x09, 0x46, 0x6c, + 0x00, 0x23, 0x20, 0xf9, 0x00, 0x13, 0x05, 0x21, 0x01, 0xc1, 0x17, 0x3e, 0xc6, 0x23, 0xa0, 0x04, + 0x00, 0xef, 0x40, 0xf0, 0x58, 0x89, 0x47, 0xa3, 0x08, 0xf1, 0x00, 0x13, 0x04, 0xe0, 0x07, 0x93, + 0x09, 0x41, 0x01, 0x03, 0x27, 0x09, 0x00, 0x94, 0x40, 0xb3, 0x07, 0xd7, 0x40, 0x63, 0xf3, 0x87, + 0x00, 0x3e, 0x84, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x5a, 0x10, 0x00, 0x37, 0x55, 0xfa, 0x91, 0x26, + 0xde, 0x69, 0xcb, 0x7d, 0x21, 0xd2, 0x14, 0xfe, 0x53, 0xc7, 0x55, 0x75, 0xe7, 0x05, 0xfc, 0xe4, + 0xb3, 0xd3, 0x8b, 0xf6, 0xea, 0xcc, 0x23, 0x26, 0x91, 0xf9, 0x23, 0x32, 0x0e, 0x14, 0x20, 0x0a, + 0x10, 0x00, 0xa2, 0x87, 0x93, 0x85, 0xca, 0x3f, 0x13, 0x06, 0xc6, 0x3e, 0x13, 0x05, 0x45, 0x40, + 0xef, 0x10, 0x50, 0x0c, 0x8c, 0x40, 0x83, 0x27, 0x4a, 0x07, 0x33, 0x07, 0xb4, 0x00, 0x63, 0xf7, + 0xe7, 0x04, 0x8d, 0x45, 0x13, 0x85, 0xca, 0x3f, 0xef, 0x10, 0x30, 0x12, 0x13, 0x04, 0x50, 0x05, + 0xc5, 0x3c, 0xef, 0x40, 0x60, 0x2a, 0xef, 0x20, 0xa0, 0x32, 0xef, 0x20, 0xa0, 0x29, 0x29, 0x3f, + 0x83, 0x20, 0xc1, 0x12, 0x22, 0x85, 0x03, 0x24, 0x81, 0x12, 0x83, 0x24, 0x41, 0x12, 0x03, 0x29, + 0x01, 0x12, 0x83, 0x29, 0xc1, 0x11, 0x03, 0x2a, 0x81, 0x11, 0x83, 0x2a, 0x41, 0x11, 0x55, 0x61, + 0x82, 0x80, 0x13, 0x04, 0x00, 0x08, 0x93, 0x09, 0x21, 0x01, 0xb5, 0xbf, 0xb7, 0x07, 0x20, 0x00, + 0x93, 0x87, 0x07, 0x00, 0x22, 0x86, 0xbe, 0x95, 0x4e, 0x85, 0xef, 0x40, 0x90, 0x4e, 0x83, 0x47, + 0x11, 0x01, 0x98, 0x40, 0x22, 0x97, 0x3e, 0x94, 0x83, 0x27, 0x09, 0x00, 0xa3, 0x08, 0x81, 0x00, + 0x98, 0xc0, 0x13, 0x04, 0x50, 0x05, 0x63, 0x17, 0xf7, 0x00, 0x89, 0x47, 0x23, 0x08, 0xf1, 0x00, + 0x13, 0x04, 0xa0, 0x0a, 0x08, 0x08, 0xef, 0x20, 0xe0, 0x04, 0x59, 0xbf, 0x41, 0x11, 0xb7, 0x37, + 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x06, 0xc6, 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x20, 0xe0, 0x26, + 0x85, 0x3d, 0xb9, 0x3c, 0xef, 0x30, 0x20, 0x07, 0x41, 0x3d, 0xb2, 0x40, 0x1d, 0x65, 0x13, 0x05, + 0x05, 0x6c, 0x41, 0x01, 0x6f, 0x30, 0x00, 0x0f, 0xfa, 0xf6, 0xaa, 0x81, 0xf6, 0x74, 0x4c, 0x1f, + 0x20, 0x1a, 0x6c, 0x44, 0x55, 0x84, 0x9f, 0x6f, 0xef, 0x37, 0x4f, 0xab, 0x96, 0x06, 0x9e, 0xb3, + 0x12, 0x78, 0xf4, 0xa0, 0x3d, 0x92, 0xd2, 0x92, 0xa1, 0xf8, 0x0a, 0x41, 0x11, 0x26, 0xc2, 0xae, + 0x84, 0xb6, 0x85, 0x06, 0xc6, 0x22, 0xc4, 0x4a, 0xc0, 0x36, 0x84, 0x32, 0x89, 0xef, 0x40, 0x40, + 0x4f, 0x22, 0x86, 0xca, 0x85, 0x13, 0x05, 0x00, 0x02, 0xef, 0x40, 0x00, 0x58, 0xef, 0x40, 0x60, + 0x4c, 0xef, 0x40, 0xe0, 0x67, 0x93, 0x07, 0xa0, 0x0a, 0x13, 0x04, 0x50, 0x05, 0x63, 0x1a, 0xf5, + 0x00, 0x2a, 0x84, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0x00, 0x02, 0x26, 0x85, 0xef, 0x40, 0xe0, + 0x50, 0xb2, 0x40, 0x22, 0x85, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x85, + 0x67, 0xc1, 0x07, 0x63, 0xee, 0xb7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xae, + 0x84, 0x37, 0x04, 0x20, 0x00, 0x19, 0xc5, 0x2e, 0x86, 0xaa, 0x85, 0x13, 0x05, 0x04, 0x00, 0xef, + 0x40, 0xd0, 0x42, 0x13, 0x04, 0x04, 0x00, 0x93, 0x07, 0x30, 0xfc, 0x23, 0x00, 0xf4, 0x00, 0x85, + 0x67, 0x3e, 0x94, 0x64, 0xd8, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x82, + 0x80, 0x13, 0x01, 0x01, 0xdd, 0x23, 0x24, 0x81, 0x22, 0x23, 0x22, 0x91, 0x22, 0x23, 0x20, 0x21, + 0x23, 0x23, 0x2e, 0x31, 0x21, 0x23, 0x2c, 0x41, 0x21, 0x23, 0x2a, 0x51, 0x21, 0x23, 0x28, 0x61, + 0x21, 0x23, 0x26, 0x71, 0x21, 0x23, 0x24, 0x81, 0x21, 0x23, 0x26, 0x11, 0x22, 0x13, 0x04, 0x00, + 0x20, 0x01, 0x49, 0x93, 0x04, 0xa0, 0x0a, 0x37, 0x3a, 0x20, 0x00, 0x85, 0x4a, 0x37, 0x5b, 0x10, + 0x00, 0xb7, 0x5b, 0xfa, 0x64, 0x38, 0xe7, 0xac, 0xe1, 0xa4, 0x84, 0x8e, 0x0a, 0x58, 0x23, 0x7e, + 0x6e, 0x2d, 0x9d, 0x11, 0xed, 0xb8, 0xc2, 0x64, 0x19, 0x20, 0xaf, 0x9f, 0xc8, 0x49, 0x86, 0x62, + 0x5e, 0x11, 0x1a, 0xa0, 0xd0, 0x0b, 0x10, 0x00, 0x37, 0x5c, 0x10, 0x00, 0xc1, 0x49, 0xa2, 0x85, + 0x0a, 0x85, 0xb1, 0x3e, 0x63, 0x16, 0x95, 0x02, 0x0a, 0x85, 0x59, 0x32, 0x63, 0x1e, 0x95, 0x04, + 0x13, 0x07, 0x4a, 0xf5, 0x14, 0x43, 0xb3, 0x97, 0x2a, 0x01, 0x13, 0x06, 0x8b, 0x40, 0xd5, 0x8f, + 0x93, 0x85, 0x4b, 0x3e, 0xca, 0x86, 0x13, 0x05, 0x4c, 0x64, 0x1c, 0xc3, 0xef, 0x10, 0xe0, 0x6e, + 0x05, 0x09, 0x13, 0x04, 0x04, 0x40, 0xe3, 0x14, 0x39, 0xfd, 0x83, 0x20, 0xc1, 0x22, 0x03, 0x24, + 0x81, 0x22, 0x83, 0x24, 0x41, 0x22, 0x03, 0x29, 0x01, 0x22, 0x83, 0x29, 0xc1, 0x21, 0x03, 0x2a, + 0x81, 0x21, 0x83, 0x2a, 0x41, 0x21, 0x03, 0x2b, 0x01, 0x21, 0x83, 0x2b, 0xc1, 0x20, 0x03, 0x2c, + 0x81, 0x20, 0x13, 0x01, 0x01, 0x23, 0x82, 0x80, 0x93, 0x05, 0x04, 0x20, 0x0a, 0x85, 0xc5, 0x3c, + 0xe3, 0x10, 0x95, 0xfc, 0x0a, 0x85, 0xef, 0xf0, 0xbf, 0x91, 0xe3, 0x1b, 0x95, 0xfa, 0x22, 0x85, + 0xef, 0x20, 0x10, 0x1f, 0x8a, 0x85, 0x22, 0x85, 0xef, 0x20, 0x70, 0x06, 0xa2, 0x85, 0x0a, 0x85, + 0xf9, 0x34, 0xe3, 0x1f, 0x95, 0xf8, 0x0a, 0x85, 0xef, 0xf0, 0x9f, 0x8f, 0xe3, 0x0a, 0x95, 0xf6, + 0x41, 0xbf, 0xb7, 0x05, 0x00, 0x80, 0x37, 0x55, 0x10, 0x00, 0x86, 0x87, 0x6d, 0x71, 0xbe, 0x95, + 0x13, 0x05, 0x45, 0x41, 0x23, 0x26, 0x11, 0x10, 0xef, 0x10, 0x80, 0x6d, 0xb7, 0x37, 0x20, 0x00, + 0x03, 0xa7, 0x87, 0xf2, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x1e, 0xf7, 0x02, 0x37, 0x15, 0xfa, 0x1e, + 0x8d, 0xca, 0xa1, 0x1e, 0x9e, 0x6d, 0x0c, 0x79, 0x8d, 0x62, 0xa7, 0x19, 0xb8, 0x15, 0x99, 0x54, + 0x67, 0x24, 0x6c, 0x1f, 0xec, 0x56, 0xfa, 0xfa, 0x30, 0x49, 0x04, 0x8e, 0xc6, 0x8d, 0xf7, 0xa8, + 0x0c, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x9a, 0xef, 0x10, 0xf0, 0x5f, 0x13, 0x05, 0xc0, 0x0f, 0xef, + 0x10, 0xa0, 0x5a, 0x0a, 0x85, 0xef, 0x10, 0x70, 0x09, 0x93, 0x07, 0xf0, 0x07, 0x93, 0x05, 0xc0, + 0x0f, 0x13, 0x05, 0x21, 0x00, 0x23, 0x00, 0xf1, 0x00, 0xef, 0x10, 0x00, 0x54, 0xa3, 0x00, 0xa1, + 0x00, 0x0a, 0x85, 0xef, 0x10, 0x70, 0x60, 0x05, 0x45, 0xef, 0x40, 0x00, 0x67, 0xef, 0x40, 0x00, + 0x66, 0xd5, 0x33, 0xef, 0x10, 0x50, 0x2d, 0xf5, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0xef, + 0x40, 0x60, 0x4c, 0x93, 0x07, 0x00, 0x08, 0x63, 0xf3, 0xa7, 0x00, 0xad, 0x3f, 0x2a, 0x84, 0x13, + 0x05, 0xa0, 0x0a, 0xef, 0x30, 0x50, 0x7e, 0xb7, 0x17, 0x20, 0x00, 0xb2, 0x40, 0x23, 0xaa, 0x87, + 0x06, 0x22, 0x44, 0x13, 0x05, 0x30, 0x0c, 0x41, 0x01, 0x82, 0x80, 0x93, 0x07, 0xf0, 0x17, 0x63, + 0xf5, 0xa7, 0x00, 0x41, 0x11, 0x06, 0xc6, 0xb9, 0x37, 0x6f, 0x10, 0xb0, 0x3e, 0x41, 0x11, 0x22, + 0xc4, 0x26, 0xc2, 0x4a, 0xc0, 0x2e, 0x84, 0x06, 0xc6, 0xaa, 0x84, 0xc5, 0x37, 0x61, 0x8d, 0x13, + 0x09, 0x50, 0x05, 0x19, 0xc1, 0x13, 0x09, 0xa0, 0x0a, 0x26, 0x85, 0xc1, 0x3f, 0x69, 0x8c, 0x13, + 0x05, 0xa0, 0x0a, 0x19, 0xe0, 0x13, 0x05, 0x50, 0x05, 0x63, 0x03, 0x25, 0x01, 0x21, 0x3f, 0xb2, + 0x40, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x8d, + 0x47, 0x63, 0xf3, 0xa7, 0x00, 0x01, 0x37, 0x89, 0x67, 0xfa, 0x7c, 0x04, 0x9a, 0xc3, 0x9e, 0x14, + 0xd9, 0x7c, 0x48, 0xa8, 0xd3, 0xba, 0x40, 0x2f, 0x30, 0x6e, 0xaa, 0x95, 0xd6, 0x7b, 0x6d, 0x2a, + 0x1c, 0x64, 0x88, 0x77, 0xfb, 0xd0, 0xf0, 0xc7, 0x3b, 0xc6, 0x80, 0x0d, 0x93, 0x87, 0x07, 0xbf, + 0x0a, 0x05, 0x3e, 0x95, 0xef, 0x30, 0xe0, 0x02, 0xaa, 0x87, 0x13, 0x07, 0xf0, 0x0f, 0x55, 0x45, + 0x63, 0x89, 0xe7, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x59, 0x45, 0x63, 0x94, 0xe7, 0x00, 0x13, 0x05, + 0x30, 0x0c, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x21, 0x71, 0x23, 0x2c, 0x81, 0x1a, 0x2a, 0x84, + 0x08, 0x09, 0x23, 0x2e, 0x11, 0x1a, 0x23, 0x2a, 0x91, 0x1a, 0x23, 0x28, 0x21, 0x1b, 0x23, 0x26, + 0x31, 0x1b, 0x23, 0x24, 0x41, 0x1b, 0x23, 0x22, 0x51, 0x1b, 0x23, 0x20, 0x61, 0x1b, 0x23, 0x2e, + 0x71, 0x19, 0x23, 0x2c, 0x81, 0x19, 0x23, 0x2a, 0x91, 0x19, 0xef, 0x10, 0x40, 0x77, 0x83, 0x47, + 0x04, 0x00, 0x05, 0x47, 0x23, 0x18, 0xe1, 0x08, 0xc1, 0x46, 0x63, 0x80, 0xd7, 0x46, 0x63, 0xee, + 0xf6, 0x02, 0x91, 0x46, 0x63, 0x88, 0xd7, 0x34, 0x63, 0xe1, 0xf6, 0x02, 0x63, 0x86, 0xe7, 0x06, + 0x09, 0x47, 0x63, 0x81, 0xe7, 0x0e, 0x93, 0x07, 0xe0, 0x07, 0x23, 0x08, 0xf1, 0x08, 0x08, 0x09, + 0xef, 0x10, 0xd0, 0x4c, 0x93, 0x07, 0x50, 0x05, 0x99, 0xa1, 0x21, 0x47, 0xe3, 0x95, 0xe7, 0xfe, + 0x83, 0x47, 0x14, 0x00, 0xd1, 0xeb, 0x4d, 0x31, 0x39, 0xa9, 0x93, 0x06, 0x20, 0x0a, 0x63, 0x85, + 0xd7, 0x4c, 0x93, 0x06, 0x30, 0x0b, 0x63, 0x82, 0xd7, 0x46, 0x93, 0x06, 0x00, 0x02, 0xe3, 0x94, + 0xd7, 0xfc, 0x83, 0x47, 0x14, 0x00, 0x63, 0x99, 0xe7, 0x06, 0x03, 0x47, 0x24, 0x00, 0x95, 0x47, + 0x63, 0x14, 0xf7, 0x06, 0xfa, 0xeb, 0x8c, 0x17, 0x29, 0xa7, 0xe4, 0x6f, 0xfd, 0x02, 0xd7, 0x94, + 0x7b, 0x38, 0x27, 0x89, 0x5e, 0x30, 0x2e, 0x53, 0x49, 0x89, 0x2b, 0x09, 0xc4, 0xf1, 0x64, 0x19, + 0xcf, 0x37, 0x9a, 0x54, 0xb3, 0x58, 0x0e, 0x85, 0x45, 0x61, 0x45, 0xe1, 0x3d, 0x93, 0x07, 0xa0, + 0x0a, 0x63, 0x09, 0xf5, 0x42, 0x13, 0x04, 0x80, 0xf8, 0x7d, 0xa0, 0x03, 0x47, 0x14, 0x00, 0x89, + 0x47, 0x63, 0x15, 0xf7, 0x04, 0x83, 0x47, 0x24, 0x00, 0x63, 0x8a, 0xe7, 0x04, 0x63, 0x6b, 0xf7, + 0x02, 0xa1, 0xe3, 0x83, 0x45, 0x34, 0x00, 0xf5, 0x47, 0x63, 0xe9, 0xb7, 0x02, 0x9e, 0x05, 0x13, + 0x06, 0x00, 0x08, 0x93, 0x85, 0x05, 0x10, 0x13, 0x05, 0x21, 0x09, 0xef, 0x20, 0x30, 0x6d, 0x13, + 0x04, 0x00, 0x08, 0x08, 0x09, 0xa3, 0x08, 0x81, 0x08, 0xef, 0x10, 0x70, 0x43, 0x93, 0x07, 0xa0, + 0x0a, 0x45, 0xae, 0x13, 0x05, 0x80, 0x1e, 0x63, 0x8d, 0xd7, 0x00, 0x13, 0x04, 0x10, 0xf8, 0xa1, + 0xa8, 0x89, 0x65, 0x13, 0x06, 0x00, 0x08, 0x93, 0x85, 0x05, 0x90, 0xf1, 0xb7, 0x13, 0x05, 0x00, + 0x1f, 0xef, 0x10, 0x90, 0x24, 0x2a, 0xc6, 0x11, 0x46, 0x6c, 0x00, 0x13, 0x05, 0x21, 0x09, 0xef, + 0x40, 0x30, 0x0a, 0x11, 0x44, 0x7d, 0xbf, 0x83, 0x44, 0x14, 0x00, 0xc5, 0x36, 0x93, 0x07, 0x10, + 0x02, 0xe3, 0x95, 0xf4, 0xfc, 0xef, 0x10, 0x10, 0x7d, 0xef, 0x20, 0x90, 0x27, 0xef, 0x30, 0x90, + 0x38, 0xef, 0x40, 0x60, 0x07, 0x03, 0x45, 0x24, 0x02, 0xa5, 0x35, 0x93, 0x07, 0x30, 0x0c, 0x63, + 0x0b, 0xf5, 0x02, 0x13, 0x04, 0x70, 0xf8, 0xb3, 0x06, 0x80, 0x40, 0x37, 0x56, 0x10, 0x00, 0xb7, + 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0xf6, 0xf6, 0x0f, 0x13, 0x06, 0x86, 0x42, 0xfa, + 0x93, 0x90, 0x10, 0x44, 0xea, 0x8b, 0x92, 0x2d, 0xd1, 0xc8, 0xd7, 0x57, 0x7a, 0xde, 0x71, 0x9e, + 0x6b, 0xe9, 0x83, 0x79, 0x81, 0xf4, 0x73, 0x1a, 0xcc, 0x39, 0x10, 0xb8, 0xb2, 0x2d, 0xc0, 0xb1, + 0x30, 0x0f, 0x93, 0x85, 0x45, 0x41, 0x13, 0x05, 0x45, 0x64, 0x23, 0x08, 0xd1, 0x08, 0xef, 0x10, + 0x80, 0x3b, 0xa3, 0x08, 0x01, 0x08, 0xf9, 0xb5, 0x83, 0x44, 0x24, 0x02, 0x19, 0x34, 0x8d, 0x47, + 0xe3, 0xe3, 0x97, 0xfc, 0x13, 0x06, 0x10, 0x08, 0x81, 0x45, 0x68, 0x00, 0xef, 0x40, 0x50, 0x06, + 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0x24, 0x00, 0x13, 0x05, 0xd1, 0x00, 0x23, 0x06, 0x91, 0x00, + 0xef, 0x40, 0x50, 0x01, 0xef, 0x40, 0x60, 0x00, 0x37, 0x25, 0x00, 0x08, 0xef, 0x30, 0x80, 0x01, + 0x81, 0x46, 0x01, 0x46, 0x93, 0x05, 0xd1, 0x02, 0x45, 0x45, 0x85, 0x3e, 0x93, 0x07, 0xa0, 0x0a, + 0xe3, 0x13, 0xf5, 0xf8, 0x81, 0x45, 0x68, 0x00, 0xef, 0x30, 0x50, 0x2f, 0x93, 0x07, 0xa0, 0x0a, + 0x2a, 0x89, 0xe3, 0x1a, 0xf5, 0xf6, 0x93, 0x06, 0x00, 0x02, 0x13, 0x06, 0xd1, 0x00, 0x93, 0x05, + 0xd1, 0x04, 0x49, 0x45, 0x99, 0x36, 0xaa, 0x84, 0xe3, 0x1f, 0x25, 0xf5, 0x85, 0x45, 0x68, 0x00, + 0xef, 0x30, 0xd0, 0x2c, 0x2a, 0x89, 0xe3, 0x18, 0x95, 0xf4, 0x83, 0x47, 0xc1, 0x00, 0x85, 0x46, + 0x13, 0x06, 0xb1, 0x00, 0x93, 0x05, 0xd1, 0x04, 0x4d, 0x45, 0xa3, 0x05, 0xf1, 0x00, 0x31, 0x3e, + 0xaa, 0x84, 0xe3, 0x1a, 0x25, 0xf3, 0x89, 0x45, 0x68, 0x00, 0xef, 0x30, 0x30, 0x2a, 0x2a, 0x89, + 0xe3, 0x13, 0x95, 0xf2, 0x81, 0x46, 0x01, 0x46, 0x93, 0x05, 0xd1, 0x04, 0x51, 0x45, 0xf5, 0x3c, + 0xaa, 0x84, 0xe3, 0x1a, 0x25, 0xf1, 0x8d, 0x45, 0x68, 0x00, 0xfa, 0x40, 0x8d, 0xb1, 0x09, 0x16, + 0xc7, 0x8b, 0xf9, 0xd6, 0xde, 0xe6, 0x71, 0x88, 0x5c, 0x0d, 0xf1, 0xba, 0x73, 0x3c, 0x4a, 0xd0, + 0x21, 0x61, 0xf0, 0xf2, 0xe8, 0xfc, 0x17, 0xd4, 0xd9, 0x80, 0x5a, 0x08, 0x10, 0xef, 0x30, 0x30, + 0x28, 0x2a, 0x89, 0xe3, 0x13, 0x95, 0xf0, 0x91, 0x45, 0x68, 0x00, 0xef, 0x30, 0x50, 0x27, 0xaa, + 0x84, 0xe3, 0x1c, 0x25, 0xef, 0x95, 0x45, 0x68, 0x00, 0xef, 0x30, 0x70, 0x26, 0xe3, 0x16, 0x95, + 0xee, 0xb7, 0x19, 0x20, 0x00, 0x13, 0x85, 0x09, 0x02, 0xef, 0x30, 0x70, 0x29, 0xb7, 0x14, 0x20, + 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0xd1, 0x02, 0x13, 0x85, 0x04, 0x03, 0xef, 0x40, 0xa0, + 0x73, 0x37, 0x15, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0xd1, 0x06, 0x13, 0x05, 0x05, + 0x05, 0xef, 0x40, 0x60, 0x72, 0x03, 0x49, 0x24, 0x02, 0x8d, 0x47, 0x4e, 0x84, 0x63, 0xf3, 0x27, + 0x01, 0x01, 0x39, 0x37, 0x5c, 0x10, 0x00, 0xef, 0x10, 0x10, 0x49, 0x81, 0x4c, 0x13, 0x0c, 0x8c, + 0x58, 0x8d, 0x49, 0xfd, 0x5a, 0x13, 0x0a, 0x00, 0x0f, 0x41, 0x6b, 0xb7, 0x0b, 0x00, 0x01, 0x03, + 0x25, 0x0c, 0x00, 0x51, 0x81, 0x49, 0x39, 0x03, 0x27, 0x0c, 0x00, 0x93, 0x57, 0x07, 0x01, 0xbd, + 0x8b, 0x63, 0xe8, 0xf9, 0x00, 0x8e, 0x07, 0xb3, 0x97, 0xfa, 0x00, 0x93, 0xc7, 0xf7, 0xff, 0x7d, + 0x8d, 0x83, 0x46, 0x1c, 0x00, 0x33, 0x55, 0x25, 0x01, 0x93, 0x77, 0x15, 0x00, 0x93, 0xf6, 0x06, + 0x0f, 0x63, 0x96, 0x46, 0x07, 0x99, 0xc3, 0x93, 0x07, 0xf0, 0x0f, 0xbd, 0x65, 0xf9, 0x8d, 0x21, + 0x83, 0x3d, 0x8b, 0x22, 0x07, 0x4d, 0x8f, 0x83, 0x45, 0x0c, 0x00, 0xc2, 0x07, 0x66, 0x85, 0xd9, + 0x8d, 0xdd, 0x8d, 0xef, 0x10, 0xfa, 0xbb, 0xf5, 0xc9, 0x9f, 0x3a, 0xa4, 0xdc, 0xc2, 0x96, 0xab, + 0x48, 0x68, 0x5d, 0xb2, 0x0c, 0x89, 0x6c, 0xd2, 0x3b, 0x71, 0x51, 0x52, 0x94, 0xbc, 0xd4, 0xe6, + 0x5a, 0x2f, 0xdb, 0x00, 0x09, 0x5e, 0xe0, 0x10, 0xd0, 0x43, 0x83, 0x47, 0x4c, 0x00, 0x11, 0x0c, + 0x85, 0x0c, 0xc5, 0xf3, 0xef, 0x10, 0x90, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, + 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x04, 0x03, 0x13, 0x05, 0x21, 0x09, 0x23, 0xae, 0xe7, 0xf2, + 0xef, 0x40, 0xa0, 0x67, 0x93, 0x05, 0x04, 0x02, 0x41, 0x46, 0x13, 0x05, 0x21, 0x0b, 0xef, 0x40, + 0xc0, 0x66, 0xef, 0x30, 0xf0, 0x6b, 0x13, 0x04, 0x00, 0x03, 0xef, 0xf0, 0x7f, 0x85, 0xbd, 0xbb, + 0x93, 0x76, 0x05, 0x10, 0x99, 0xc2, 0x93, 0xe7, 0x27, 0x00, 0xb3, 0x76, 0x65, 0x01, 0x99, 0xc2, + 0x93, 0xe7, 0x47, 0x00, 0x33, 0x75, 0x75, 0x01, 0x59, 0xd1, 0x93, 0xe7, 0x87, 0x00, 0x41, 0xb7, + 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0xc7, 0xf3, 0x93, 0x07, 0xa0, 0x0a, 0x83, 0x44, 0x14, 0x00, + 0x63, 0x14, 0xf7, 0x0e, 0x91, 0xe4, 0x13, 0x04, 0x10, 0xf8, 0xef, 0xf0, 0xbf, 0x96, 0x4d, 0xbb, + 0xb7, 0x39, 0x20, 0x00, 0x83, 0xa7, 0x89, 0xf3, 0x93, 0x89, 0x89, 0xf3, 0xad, 0xcb, 0x09, 0x04, + 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x49, 0xf3, 0x83, 0x26, 0x09, 0x00, 0x03, 0xa7, 0x09, 0x00, + 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, 0x64, + 0xa6, 0x96, 0x13, 0x06, 0xc6, 0x41, 0x93, 0x85, 0xc5, 0x3f, 0xef, 0x10, 0x20, 0x15, 0x03, 0x25, + 0x09, 0x00, 0x83, 0xa7, 0x09, 0x00, 0x33, 0x87, 0xa4, 0x00, 0xe3, 0xe6, 0xe7, 0xfa, 0x85, 0x67, + 0xfa, 0xf3, 0x0a, 0x2c, 0x68, 0x1e, 0x1e, 0xe0, 0xc2, 0x21, 0x0b, 0xe6, 0x19, 0x58, 0xc1, 0x7b, + 0x06, 0xf8, 0x5a, 0xae, 0x57, 0x62, 0x69, 0x7b, 0xe9, 0x9f, 0xb9, 0x02, 0xb1, 0x9c, 0x6a, 0xb1, + 0xe7, 0xb8, 0x11, 0x93, 0x87, 0x07, 0x02, 0xe3, 0xe1, 0xe7, 0xfa, 0xb7, 0x07, 0x20, 0x00, 0x93, + 0x87, 0x07, 0x00, 0x26, 0x86, 0x3e, 0x95, 0xa2, 0x85, 0xef, 0x40, 0x40, 0x5b, 0x83, 0x27, 0x09, + 0x00, 0xbe, 0x94, 0x83, 0xa7, 0x09, 0x00, 0x23, 0x20, 0x99, 0x00, 0xbd, 0xe3, 0x75, 0x54, 0x15, + 0xbb, 0x89, 0x47, 0xe3, 0xfb, 0x97, 0xf6, 0x03, 0x49, 0x34, 0x00, 0x83, 0x47, 0x24, 0x00, 0xf9, + 0x14, 0x22, 0x09, 0x3e, 0x99, 0x85, 0x67, 0x93, 0x06, 0xf9, 0xff, 0x13, 0x87, 0xf7, 0x00, 0x11, + 0x04, 0xe3, 0x6c, 0xd7, 0xf4, 0x37, 0x0a, 0x20, 0x00, 0x13, 0x0a, 0x0a, 0x00, 0x3e, 0x9a, 0x41, + 0x09, 0x93, 0x07, 0xf0, 0x07, 0xa3, 0x0c, 0xfa, 0x06, 0x23, 0xa0, 0x29, 0x01, 0xef, 0x10, 0x50, + 0x4a, 0xef, 0x20, 0xc0, 0x74, 0xef, 0x30, 0xd0, 0x05, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x28, 0x2a, + 0x07, 0x23, 0x2a, 0x0a, 0x06, 0x23, 0xaa, 0x07, 0xf2, 0x2d, 0xbf, 0x13, 0x04, 0x60, 0xf8, 0x39, + 0xbf, 0xe3, 0x9e, 0xf4, 0xf8, 0x01, 0x44, 0xa1, 0xb9, 0x83, 0x47, 0x14, 0x00, 0xe3, 0x95, 0x07, + 0xc6, 0xef, 0x10, 0x30, 0x15, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x0f, 0x05, 0xc4, 0x83, 0x20, 0xc1, + 0x1b, 0x03, 0x24, 0x81, 0x1b, 0x83, 0x24, 0x41, 0x1b, 0x03, 0x29, 0x01, 0x1b, 0x83, 0x29, 0xc1, + 0x1a, 0x03, 0x2a, 0x81, 0x1a, 0x83, 0x2a, 0x41, 0x1a, 0x03, 0x2b, 0x01, 0x1a, 0x83, 0x2b, 0xc1, + 0x19, 0x03, 0x2c, 0x81, 0x19, 0x83, 0x2c, 0x41, 0x19, 0x3e, 0x85, 0xfa, 0x42, 0x66, 0xc2, 0xea, + 0xb1, 0xc2, 0x8c, 0xe0, 0xea, 0xd9, 0xb7, 0x90, 0xe6, 0xa5, 0x01, 0x75, 0x6d, 0x44, 0x76, 0xbc, + 0x8a, 0xcb, 0x45, 0x1d, 0x1f, 0x32, 0xfd, 0xb5, 0xec, 0xea, 0x26, 0xf7, 0x90, 0x12, 0x39, 0x61, + 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa2, 0xa7, 0xf4, 0x7d, 0xb7, 0x83, 0x46, 0x14, 0x00, + 0xe3, 0x9d, 0xe6, 0xc0, 0x83, 0x47, 0x24, 0x00, 0x63, 0x8a, 0xd7, 0x02, 0x0d, 0x47, 0xe3, 0x96, + 0xe7, 0xc0, 0xa1, 0x45, 0x01, 0x45, 0xb5, 0x3c, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0xe3, 0x13, + 0xf5, 0xba, 0xb7, 0xb5, 0xb5, 0x61, 0x93, 0x85, 0x55, 0x49, 0x13, 0x05, 0x80, 0x1f, 0xef, 0x10, + 0x40, 0x6b, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa6, 0x87, 0xf2, 0xbd, 0xb7, 0xb7, 0x15, 0x78, 0x4a, + 0x93, 0x85, 0x95, 0x21, 0x13, 0x05, 0x80, 0x1f, 0xef, 0x10, 0xa0, 0x69, 0xb7, 0x37, 0x20, 0x00, + 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf2, 0x81, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, + 0x87, 0xf2, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1f, 0xf7, 0xb4, 0x83, 0x47, 0x14, 0x00, 0xe3, 0x96, + 0x07, 0xba, 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x09, 0xef, 0x00, 0x50, 0x6f, 0x2a, 0x84, + 0xe3, 0x51, 0x05, 0xb8, 0xcd, 0xbe, 0x41, 0x11, 0x05, 0x45, 0x06, 0xc6, 0xef, 0x40, 0x20, 0x02, + 0xb2, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa0, 0xe7, 0xf4, 0x41, 0x01, + 0x82, 0x80, 0x31, 0x71, 0x22, 0xdd, 0x37, 0x34, 0x20, 0x00, 0x93, 0x07, 0x50, 0x05, 0x06, 0xdf, + 0x4a, 0xd9, 0x52, 0xd5, 0x56, 0xd3, 0x62, 0xcd, 0x26, 0xdb, 0x4e, 0xd7, 0x5a, 0xd1, 0x5e, 0xcf, + 0x66, 0xcb, 0x6a, 0xc9, 0x6e, 0xc7, 0xfa, 0x06, 0x4e, 0xfb, 0x7e, 0xe9, 0x3e, 0x95, 0x1b, 0x0a, + 0xbe, 0xe4, 0x6b, 0xc5, 0xc0, 0x3c, 0x86, 0x11, 0x8b, 0xcb, 0x9a, 0xbf, 0x3c, 0xc5, 0x72, 0x9b, + 0xe5, 0xc3, 0xd0, 0x6c, 0x12, 0x70, 0x87, 0x68, 0x13, 0xb7, 0x3a, 0x20, 0x00, 0x37, 0x3a, 0x20, + 0x00, 0x37, 0x39, 0x20, 0x00, 0x13, 0x04, 0x84, 0xf2, 0x23, 0xa0, 0xfa, 0xf4, 0x23, 0x26, 0xfa, + 0xf2, 0x23, 0x22, 0xf9, 0xf4, 0x1c, 0xc0, 0xef, 0x10, 0x60, 0x3d, 0xef, 0x10, 0xc0, 0x55, 0x13, + 0x87, 0x0a, 0xf4, 0x3a, 0xc8, 0x13, 0x07, 0xca, 0xf2, 0x3a, 0xca, 0x13, 0x07, 0x49, 0xf4, 0x93, + 0x07, 0xa0, 0x0a, 0x3a, 0xc6, 0x37, 0x5c, 0x10, 0x00, 0x85, 0x45, 0x63, 0x0a, 0xf5, 0x00, 0x13, + 0x05, 0x4c, 0x41, 0xef, 0x00, 0x90, 0x7b, 0xef, 0x10, 0x80, 0x4f, 0xef, 0xf0, 0x3f, 0x8c, 0x41, + 0x45, 0xef, 0xf0, 0x5f, 0x97, 0x08, 0xc0, 0xb7, 0x07, 0x01, 0x02, 0x80, 0x57, 0x98, 0x5b, 0x29, + 0x45, 0x59, 0x8c, 0x98, 0x5f, 0x59, 0x8c, 0x13, 0x77, 0xf4, 0x87, 0x98, 0xd7, 0x98, 0xdb, 0x98, + 0xdf, 0xd8, 0x43, 0x13, 0x67, 0x87, 0x00, 0xd8, 0xc3, 0xef, 0x10, 0x00, 0x38, 0xef, 0x30, 0x30, + 0x22, 0x13, 0x75, 0x05, 0x78, 0x11, 0xc5, 0x13, 0x05, 0x00, 0x78, 0x81, 0x45, 0xef, 0x30, 0x90, + 0x1a, 0xb7, 0x07, 0x01, 0x02, 0x80, 0xd7, 0x80, 0xdb, 0x37, 0x15, 0x10, 0x00, 0x80, 0xdf, 0x13, + 0x05, 0xc5, 0x9a, 0xef, 0x10, 0xa0, 0x69, 0x37, 0x56, 0x10, 0x00, 0x37, 0x59, 0x10, 0x00, 0x81, + 0x47, 0x01, 0x47, 0x85, 0x46, 0x13, 0x06, 0x06, 0x43, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, + 0x64, 0xef, 0x00, 0x50, 0x6c, 0xef, 0x30, 0x50, 0x1e, 0x93, 0x07, 0x50, 0x05, 0x63, 0x1e, 0xf5, + 0x00, 0xfa, 0x86, 0x50, 0x83, 0xed, 0x9b, 0x2d, 0x0e, 0x5f, 0xbb, 0x12, 0x85, 0x0a, 0x45, 0x1d, + 0x4e, 0x0e, 0x68, 0x8e, 0x71, 0xd1, 0xb0, 0xce, 0xa7, 0x75, 0x8b, 0xa8, 0x53, 0xe8, 0xf8, 0xc7, + 0xe2, 0xd8, 0x40, 0x14, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x46, 0x44, + 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x45, 0x40, 0xef, 0x00, 0x10, 0x6a, 0xef, 0x20, 0xa0, 0x2f, + 0x51, 0x45, 0xef, 0x10, 0xc0, 0x4b, 0x1d, 0x89, 0xef, 0x20, 0xc0, 0x2f, 0xef, 0x20, 0xa0, 0x03, + 0xef, 0x20, 0x10, 0x03, 0xef, 0x20, 0x30, 0x31, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0xb0, 0x31, + 0x11, 0x46, 0x6c, 0x10, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0xf0, 0x35, 0x37, 0x35, 0x00, 0x08, + 0xef, 0x20, 0xb0, 0x33, 0x32, 0x55, 0xc1, 0x7a, 0x37, 0x0b, 0x01, 0xff, 0xb7, 0x0b, 0x00, 0x01, + 0xef, 0x20, 0x70, 0x22, 0x05, 0x64, 0x01, 0x4a, 0x93, 0x8a, 0xfa, 0x0f, 0x7d, 0x1b, 0xfd, 0x1b, + 0x13, 0x0d, 0x00, 0x18, 0x52, 0x85, 0xef, 0xf0, 0x1f, 0x87, 0xaa, 0x8c, 0x22, 0x85, 0xef, 0x20, + 0xd0, 0x0f, 0x93, 0xf9, 0x09, 0xf0, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, 0x44, 0x00, 0xef, 0x20, + 0xd0, 0x0e, 0x22, 0x05, 0xb3, 0xf9, 0x59, 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, 0x84, 0x00, + 0xef, 0x20, 0xb0, 0x0d, 0x42, 0x05, 0xb3, 0xf9, 0x69, 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, + 0xc4, 0x00, 0xef, 0x20, 0x90, 0x0c, 0x62, 0x05, 0xb3, 0xf9, 0x79, 0x01, 0xb3, 0xe9, 0xa9, 0x00, + 0x93, 0xc7, 0xf9, 0xff, 0x33, 0xf5, 0x97, 0x01, 0xe3, 0x1b, 0x05, 0xea, 0x11, 0x0a, 0x41, 0x04, + 0xe3, 0x12, 0xaa, 0xfb, 0x37, 0x55, 0x10, 0x00, 0xb7, 0x37, 0x20, 0x00, 0xfa, 0x2c, 0xd8, 0xfc, + 0x42, 0x4d, 0xdb, 0x61, 0x6d, 0x0b, 0x0a, 0x7c, 0x82, 0x39, 0x57, 0x23, 0xcf, 0xbf, 0xd8, 0xf1, + 0x52, 0x74, 0x8d, 0x09, 0x14, 0x23, 0x05, 0x33, 0xaa, 0x1e, 0x0d, 0xd9, 0x41, 0x18, 0x15, 0x13, + 0x07, 0x50, 0x05, 0x13, 0x05, 0x85, 0x5e, 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x10, 0xf0, 0x1a, 0xb7, + 0x55, 0x10, 0x00, 0x13, 0x06, 0x40, 0x05, 0x93, 0x85, 0x45, 0x53, 0x68, 0x10, 0xef, 0x40, 0xc0, + 0x24, 0x60, 0x10, 0x48, 0x40, 0x01, 0xc5, 0xef, 0x20, 0xa0, 0x7f, 0x48, 0xc0, 0x31, 0x04, 0x1c, + 0x01, 0xe3, 0x99, 0x87, 0xfe, 0x37, 0x55, 0x10, 0x00, 0x1d, 0x46, 0x6c, 0x10, 0x13, 0x05, 0xc5, + 0x5f, 0xef, 0x20, 0x40, 0x42, 0xef, 0xf0, 0x0f, 0xe3, 0x05, 0x45, 0xef, 0x10, 0xd0, 0x02, 0xef, + 0x30, 0xa0, 0x4e, 0xef, 0x30, 0x50, 0x21, 0x01, 0x45, 0xef, 0x30, 0xf0, 0x5d, 0xb7, 0x0a, 0x20, + 0x00, 0x93, 0x87, 0x0a, 0x00, 0x05, 0x6b, 0xb3, 0x8b, 0x67, 0x01, 0xb7, 0x17, 0x20, 0x00, 0x13, + 0x8a, 0xc7, 0x07, 0xef, 0x10, 0x40, 0x66, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x87, 0xf3, 0x63, + 0x82, 0x07, 0x10, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0x47, 0xf3, 0x63, 0x9c, 0xe7, 0x0e, 0xb7, + 0x37, 0x20, 0x00, 0x03, 0xc7, 0x07, 0xf3, 0x93, 0x87, 0x07, 0xf3, 0x3e, 0xcc, 0xe3, 0x1d, 0x07, + 0x36, 0x03, 0xa6, 0x0b, 0x07, 0x93, 0x07, 0xf0, 0x07, 0xb7, 0x19, 0x20, 0x00, 0xa3, 0x8c, 0xfb, + 0x06, 0xc1, 0x4c, 0x13, 0x8d, 0x0a, 0x00, 0x93, 0x89, 0x09, 0x00, 0x63, 0xfe, 0xcc, 0x0a, 0x13, + 0x04, 0x06, 0xff, 0xef, 0x10, 0x60, 0x72, 0x01, 0x45, 0xef, 0x30, 0x60, 0x4f, 0x22, 0x86, 0x63, + 0xf3, 0x8c, 0x00, 0x41, 0x46, 0x93, 0x85, 0xfa, 0x4a, 0x76, 0xcf, 0x78, 0x75, 0xcb, 0xc3, 0x0b, + 0x1d, 0x9d, 0xb2, 0x59, 0xa8, 0x5e, 0x32, 0x9a, 0xd3, 0x99, 0xfc, 0xbc, 0x5f, 0x7d, 0x38, 0x13, + 0x80, 0xf7, 0x7e, 0x00, 0x1a, 0xd7, 0x14, 0x5f, 0xf0, 0x15, 0x0a, 0x00, 0x68, 0x10, 0xef, 0x30, + 0x20, 0x50, 0xef, 0x10, 0xc0, 0x77, 0xb7, 0x57, 0x10, 0x00, 0x23, 0x8c, 0xa9, 0x06, 0x93, 0x87, + 0x87, 0x58, 0x03, 0xc7, 0x07, 0x00, 0x63, 0x1b, 0x07, 0x12, 0x03, 0xa4, 0x09, 0x07, 0xc1, 0x47, + 0xe3, 0xf2, 0x87, 0xda, 0x01, 0x45, 0xef, 0x30, 0xc0, 0x4b, 0x41, 0x14, 0x22, 0x86, 0x93, 0x85, + 0x0a, 0x00, 0x13, 0x85, 0x0a, 0x00, 0xef, 0x30, 0xa0, 0x4c, 0xb7, 0x1c, 0x20, 0x00, 0x13, 0x85, + 0x0c, 0x02, 0xef, 0x30, 0xa0, 0x68, 0xef, 0x30, 0x20, 0x6d, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x5d, + 0x10, 0x00, 0xaa, 0x86, 0x13, 0x06, 0x46, 0x45, 0x93, 0x85, 0xcd, 0x3d, 0x13, 0x05, 0x49, 0x64, + 0xef, 0x00, 0xf0, 0x49, 0x93, 0x85, 0x0c, 0x02, 0x41, 0x46, 0x33, 0x05, 0x8d, 0x00, 0xef, 0x00, + 0x30, 0x38, 0xaa, 0x8c, 0xc1, 0x47, 0x63, 0x09, 0x05, 0x0e, 0x89, 0x45, 0x13, 0x85, 0xcd, 0x3d, + 0xef, 0x00, 0x50, 0x4f, 0x37, 0x55, 0x10, 0x00, 0x93, 0x07, 0xb0, 0x07, 0x91, 0x45, 0x13, 0x05, + 0xc5, 0x3f, 0xa3, 0x8c, 0xf9, 0x06, 0xef, 0x00, 0xf0, 0x4d, 0xef, 0xe0, 0x9f, 0xf7, 0xef, 0xf0, + 0xcf, 0x87, 0xef, 0xf0, 0x4f, 0xc3, 0xef, 0x10, 0xa0, 0x53, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, + 0x63, 0x17, 0xf5, 0x08, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xc7, 0x07, 0xf3, 0xc9, 0xe3, 0xef, 0x10, + 0xa0, 0x02, 0xe3, 0x15, 0x85, 0x20, 0xd2, 0x47, 0x9c, 0x43, 0x63, 0x94, 0xa7, 0x00, 0xef, 0x10, + 0xc0, 0x18, 0xfa, 0x31, 0xbf, 0x8e, 0xf4, 0x59, 0x4c, 0x65, 0xcd, 0x11, 0x4d, 0x2c, 0xc5, 0x06, + 0xe7, 0x37, 0xcb, 0x54, 0x53, 0xe5, 0xfc, 0x42, 0xb2, 0x11, 0x89, 0xd1, 0xbe, 0xdc, 0x39, 0xa4, + 0x9a, 0x1d, 0x9b, 0xc8, 0x16, 0xb2, 0x47, 0x98, 0x43, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x13, 0xf7, + 0x1e, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0x86, 0x4d, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, + 0x64, 0xef, 0x00, 0x10, 0x41, 0xef, 0xf0, 0x4f, 0xbe, 0x37, 0x25, 0x00, 0x08, 0xef, 0x20, 0x70, + 0x0d, 0xef, 0xf0, 0x4f, 0xa8, 0xef, 0x20, 0x60, 0x5f, 0xef, 0x10, 0x50, 0x1c, 0xef, 0x20, 0x30, + 0x21, 0xef, 0xe0, 0xff, 0xf3, 0x32, 0x47, 0x37, 0x56, 0x10, 0x00, 0x93, 0x07, 0x50, 0x05, 0x13, + 0x06, 0x46, 0x4e, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, 0x64, 0x1c, 0xc3, 0xef, 0x00, 0x50, + 0x3d, 0xef, 0x20, 0x10, 0x21, 0xef, 0x10, 0x70, 0x48, 0xef, 0x20, 0x20, 0x5f, 0xef, 0x30, 0x90, + 0x00, 0xc2, 0x47, 0x98, 0x43, 0x93, 0x07, 0x50, 0x05, 0xe3, 0x08, 0xf7, 0xe4, 0xad, 0xb9, 0x63, + 0x1c, 0xe5, 0x00, 0x83, 0xc7, 0x17, 0x00, 0xbd, 0x8b, 0xe3, 0x82, 0x07, 0xec, 0x13, 0x05, 0xa0, + 0x0a, 0xef, 0x30, 0xa0, 0x59, 0x65, 0xbd, 0x91, 0x07, 0x75, 0xb5, 0x03, 0xa4, 0x09, 0x07, 0xe3, + 0xe4, 0x87, 0x16, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0xc5, 0x3f, 0xef, 0x00, 0xb0, + 0x3f, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x3f, 0x95, 0x45, 0xef, 0x00, 0xd0, 0x3e, 0x13, + 0x05, 0xf0, 0x07, 0x39, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xf5, 0x94, 0x43, 0x37, + 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x87, 0x16, 0x00, 0x98, 0xc3, 0xfa, 0x17, 0xa7, + 0x05, 0x06, 0x4d, 0x7e, 0xa8, 0x78, 0x15, 0x6f, 0xa1, 0x25, 0xe1, 0x63, 0xc0, 0xb0, 0x49, 0x09, + 0xd5, 0xd2, 0xe8, 0x56, 0x1c, 0xdc, 0x2d, 0x4f, 0x66, 0xdc, 0xd8, 0x94, 0x1b, 0xf0, 0xa0, 0x17, + 0x03, 0xc7, 0x89, 0x07, 0xa2, 0x87, 0x13, 0x06, 0x46, 0x46, 0x93, 0x85, 0xc5, 0x3f, 0x13, 0x05, + 0x49, 0x64, 0xef, 0x00, 0x30, 0x34, 0xb7, 0x17, 0x20, 0x00, 0x13, 0x85, 0xc7, 0x07, 0x3d, 0x46, + 0x81, 0x45, 0xef, 0x30, 0xd0, 0x7f, 0x83, 0xc7, 0x89, 0x07, 0x13, 0x07, 0x20, 0x04, 0x63, 0x80, + 0xe7, 0x56, 0x63, 0x69, 0xf7, 0x16, 0x13, 0x07, 0x10, 0x02, 0x63, 0x89, 0xe7, 0x3e, 0x63, 0x60, + 0xf7, 0x08, 0x45, 0x47, 0x63, 0x82, 0xe7, 0x30, 0x63, 0x69, 0xf7, 0x02, 0x05, 0x47, 0x63, 0x85, + 0xe7, 0x24, 0x41, 0x47, 0x63, 0x8d, 0xe7, 0x26, 0x89, 0x49, 0x3d, 0xa3, 0x93, 0x87, 0x07, 0xfa, + 0x93, 0xf7, 0xf7, 0x0f, 0x45, 0x47, 0xe3, 0x69, 0xf7, 0xfe, 0x37, 0x57, 0x10, 0x00, 0x8a, 0x07, + 0x13, 0x07, 0xc7, 0x4e, 0xba, 0x97, 0x9c, 0x43, 0x82, 0x87, 0x49, 0x47, 0x63, 0x82, 0xe7, 0x34, + 0x13, 0x07, 0x00, 0x02, 0xe3, 0x9a, 0xe7, 0xfc, 0x42, 0x04, 0x41, 0x80, 0xa1, 0x47, 0xe3, 0x13, + 0xf4, 0xf4, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x81, + 0x63, 0x97, 0x07, 0x54, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe3, 0xa7, 0x54, 0x83, 0x25, 0x4d, 0x00, + 0xef, 0x10, 0x90, 0x1e, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x1b, 0xf5, 0x52, 0xad, 0xa6, 0x13, 0x07, + 0x10, 0x03, 0x63, 0x86, 0xe7, 0x3a, 0x63, 0x6f, 0xf7, 0x04, 0x13, 0x07, 0x20, 0x02, 0x63, 0x87, + 0xe7, 0x38, 0x13, 0x07, 0x00, 0x03, 0xe3, 0x91, 0xfa, 0xbb, 0x57, 0x46, 0x61, 0xf1, 0xd6, 0x72, + 0xeb, 0xc2, 0xe3, 0x87, 0xfe, 0x58, 0x11, 0x70, 0x8e, 0x60, 0x1b, 0x6b, 0x0b, 0x3e, 0x42, 0x1b, + 0x31, 0x4c, 0xce, 0x9d, 0xf4, 0x5a, 0x82, 0x39, 0x20, 0x78, 0x18, 0xe7, 0xf8, 0x42, 0x04, 0x41, + 0x80, 0x91, 0x47, 0xe3, 0x1a, 0xf4, 0xee, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x97, 0x07, + 0x01, 0x8d, 0x8b, 0x41, 0x83, 0x63, 0x9e, 0x07, 0x4e, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xea, 0xe7, + 0x4e, 0x03, 0x45, 0x3d, 0x00, 0xfd, 0x47, 0x63, 0xe5, 0xa7, 0x4e, 0x93, 0x15, 0x25, 0x00, 0x0d, + 0x81, 0x93, 0xf7, 0xc5, 0x01, 0x3a, 0x95, 0xbd, 0x45, 0xb3, 0x95, 0xf5, 0x00, 0x0a, 0x05, 0x93, + 0xc5, 0xf5, 0xff, 0x5a, 0x95, 0x05, 0xa4, 0x13, 0x07, 0x00, 0x04, 0x63, 0x8f, 0xe7, 0x3a, 0x13, + 0x07, 0x10, 0x04, 0xe3, 0x94, 0xe7, 0xf2, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x1d, 0xf4, + 0xe8, 0x83, 0x26, 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0xa1, 0x82, 0xc2, 0x06, 0xc1, 0x82, 0x63, + 0xe1, 0xd7, 0x4a, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x86, 0x4b, 0x93, + 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x10, 0x1f, 0xef, 0x10, 0x50, 0x57, 0xef, + 0x20, 0x00, 0x75, 0x83, 0x27, 0x0d, 0x00, 0x91, 0x65, 0x93, 0x85, 0x05, 0x20, 0xa1, 0x83, 0xc2, + 0x07, 0xc1, 0x83, 0xa6, 0x07, 0x37, 0x15, 0x20, 0x00, 0xbe, 0x95, 0x13, 0x05, 0x05, 0x08, 0xef, + 0x10, 0x30, 0x19, 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x74, 0x93, 0x07, 0xc0, 0x1b, 0xe3, 0xe0, 0x87, + 0xa8, 0x93, 0x05, 0x44, 0x00, 0x29, 0xac, 0x13, 0x07, 0x10, 0x07, 0x63, 0x69, 0xf7, 0x02, 0x13, + 0x07, 0xf0, 0x05, 0xfa, 0x8a, 0x29, 0x7b, 0xdd, 0xde, 0x5b, 0x79, 0xb8, 0x49, 0x0a, 0x0c, 0x22, + 0xe2, 0x6f, 0xe0, 0xc5, 0x95, 0xa2, 0x1d, 0x56, 0x4f, 0xf4, 0x3a, 0x5f, 0xfa, 0x6b, 0xbc, 0xd9, + 0xfe, 0x7e, 0x16, 0x4f, 0x50, 0x19, 0xe3, 0x66, 0xf7, 0xea, 0x13, 0x07, 0x00, 0x05, 0xe3, 0x90, + 0xe7, 0xea, 0x42, 0x04, 0x41, 0x80, 0x89, 0x47, 0xe3, 0x19, 0xf4, 0xe0, 0x03, 0x44, 0x1d, 0x00, + 0x37, 0x15, 0x20, 0x00, 0x13, 0x05, 0x05, 0x08, 0xa2, 0x85, 0xef, 0xe0, 0x1f, 0xd7, 0xd9, 0xb7, + 0x13, 0x07, 0x20, 0x08, 0x63, 0x8b, 0xe7, 0x6e, 0x63, 0x6d, 0xf7, 0x04, 0x13, 0x07, 0x00, 0x08, + 0x63, 0x82, 0xe7, 0x68, 0x13, 0x07, 0x10, 0x08, 0xe3, 0x93, 0xe7, 0xe6, 0x42, 0x04, 0x41, 0x80, + 0x8d, 0x47, 0xe3, 0x1c, 0xf4, 0xdc, 0x03, 0x45, 0x1d, 0x00, 0x3d, 0x47, 0x81, 0x47, 0x63, 0x6e, + 0xa7, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x47, 0xf5, 0x89, 0x47, 0x33, 0x57, 0xa7, 0x00, + 0x05, 0x8b, 0x01, 0xc7, 0xef, 0xe0, 0x7f, 0xe6, 0xaa, 0x87, 0xfd, 0x17, 0x09, 0x47, 0x63, 0x63, + 0xf7, 0x3c, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x72, 0xaa, 0x97, 0x83, 0xc9, 0x07, 0x00, + 0x1d, 0xaa, 0x13, 0x07, 0x00, 0x09, 0xe3, 0x9c, 0xe7, 0xe0, 0x93, 0x17, 0x04, 0x01, 0xc1, 0x83, + 0x13, 0x07, 0x30, 0x02, 0xe3, 0x73, 0xf7, 0xd8, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, + 0xbe, 0x86, 0x13, 0x06, 0x06, 0x4c, 0x93, 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, + 0xd0, 0x0e, 0xef, 0x20, 0xa0, 0x0d, 0xef, 0x20, 0xc0, 0x64, 0xef, 0x20, 0x20, 0x0e, 0x2a, 0x84, + 0xef, 0x20, 0x40, 0x0d, 0xef, 0x20, 0x00, 0x66, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x14, 0xfa, 0x33, + 0x70, 0x2d, 0x9c, 0xff, 0x0d, 0xdf, 0x20, 0xd3, 0xf8, 0xc7, 0x95, 0x5d, 0xf8, 0xb3, 0x5f, 0x58, + 0xee, 0x56, 0x9f, 0x6f, 0x9d, 0x87, 0x90, 0x41, 0x8d, 0xb2, 0x11, 0x85, 0xc1, 0xdd, 0x05, 0x28, + 0x1a, 0xf4, 0x36, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0x00, 0x2c, 0x93, 0x07, 0x40, 0x02, 0x81, + 0xa3, 0x93, 0x19, 0x04, 0x01, 0x93, 0xd9, 0x09, 0x01, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, + 0x00, 0xce, 0x86, 0x13, 0x06, 0x06, 0x4a, 0x93, 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, + 0x00, 0xf0, 0x09, 0x93, 0x07, 0x1b, 0x00, 0xe3, 0xeb, 0x37, 0xd1, 0xce, 0x85, 0x13, 0x85, 0x0a, + 0x00, 0xef, 0xf0, 0x4f, 0x8e, 0xa9, 0xaa, 0x42, 0x04, 0x41, 0x80, 0x93, 0x07, 0x40, 0x02, 0xe3, + 0x1f, 0xf4, 0xce, 0x03, 0x25, 0x0d, 0x00, 0x0d, 0x44, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, + 0x64, 0xa4, 0x30, 0xef, 0xf0, 0x8f, 0xae, 0xd5, 0x47, 0x63, 0x1f, 0xf5, 0x2e, 0x83, 0x29, 0x0d, + 0x00, 0x93, 0xd9, 0x89, 0x00, 0xc2, 0x09, 0x93, 0xd9, 0x09, 0x01, 0xe3, 0x6c, 0x34, 0x91, 0x13, + 0x84, 0x09, 0x0e, 0x16, 0x04, 0x91, 0x4c, 0x71, 0x14, 0x93, 0x0d, 0x40, 0x02, 0xb3, 0x05, 0x9d, + 0x01, 0x11, 0x46, 0x68, 0x10, 0xef, 0x30, 0x70, 0x4c, 0xb2, 0x55, 0x33, 0x05, 0x94, 0x01, 0x91, + 0x0c, 0xef, 0x20, 0x20, 0x33, 0xe3, 0x94, 0xbc, 0xff, 0x09, 0x65, 0x8a, 0x09, 0xb7, 0xf5, 0xf0, + 0xf0, 0x13, 0x05, 0x05, 0xbf, 0x93, 0x85, 0x05, 0x0f, 0x4e, 0x95, 0xef, 0x20, 0x80, 0x31, 0xc5, + 0xa0, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x13, 0xf4, 0xc8, 0x03, 0x25, 0x0d, 0x00, 0x0d, + 0x44, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0x68, 0xfa, 0xd1, 0xe1, 0x9b, 0x97, 0x17, 0x68, + 0xef, 0xb6, 0x82, 0xbc, 0xa0, 0x2b, 0x8d, 0x94, 0xbb, 0x89, 0xe9, 0x31, 0x9c, 0xe3, 0x3a, 0x5b, + 0xa3, 0xa6, 0xca, 0x01, 0xdb, 0x04, 0xd0, 0x41, 0x88, 0x2c, 0x00, 0x1b, 0xa4, 0x28, 0xef, 0xf0, + 0x0f, 0xa7, 0x93, 0x07, 0x30, 0x0c, 0x63, 0x08, 0xf5, 0x00, 0xaa, 0x89, 0x93, 0x07, 0x00, 0x08, + 0x63, 0x9a, 0xf9, 0x20, 0xb1, 0xb9, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, + 0xe3, 0x6b, 0xf4, 0x88, 0x93, 0x87, 0x07, 0x0e, 0x13, 0x94, 0x57, 0x00, 0x93, 0x09, 0x00, 0x02, + 0x33, 0x05, 0x94, 0x01, 0xef, 0x20, 0x20, 0x20, 0xb7, 0x17, 0x20, 0x00, 0x93, 0x87, 0x07, 0x08, + 0x2a, 0xd6, 0x11, 0x46, 0x33, 0x85, 0x97, 0x01, 0x6c, 0x10, 0x91, 0x0c, 0xef, 0x30, 0x30, 0x43, + 0xe3, 0x90, 0x3c, 0xff, 0x93, 0x05, 0x40, 0x02, 0x52, 0x85, 0x29, 0xb7, 0x42, 0x04, 0x41, 0x80, + 0x8d, 0x47, 0xe3, 0x17, 0xf4, 0xc0, 0x03, 0x25, 0x0d, 0x00, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, + 0x63, 0x6d, 0xa4, 0x20, 0xef, 0xf0, 0xaf, 0x9f, 0xd5, 0x47, 0x63, 0x08, 0xf5, 0x20, 0xd9, 0x47, + 0x63, 0x01, 0xf5, 0x04, 0x83, 0x29, 0x0d, 0x00, 0x93, 0xd9, 0x89, 0x00, 0xc2, 0x09, 0x93, 0xd9, + 0x09, 0x01, 0xe3, 0x62, 0x34, 0x83, 0x89, 0x67, 0x13, 0x95, 0x29, 0x00, 0x93, 0x87, 0x07, 0xbf, + 0x81, 0x45, 0x3e, 0x95, 0x93, 0x89, 0x09, 0x0e, 0xef, 0x20, 0xe0, 0x24, 0x96, 0x09, 0x13, 0x04, + 0x00, 0x02, 0x33, 0x85, 0x99, 0x01, 0x81, 0x45, 0x91, 0x0c, 0xef, 0x20, 0xc0, 0x23, 0xe3, 0x9a, + 0x8c, 0xfe, 0x93, 0x09, 0x30, 0x0c, 0xb9, 0xaa, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x11, + 0xf4, 0xba, 0x83, 0x27, 0xfa, 0x03, 0x45, 0x33, 0x20, 0x5d, 0x9d, 0x33, 0x5e, 0x67, 0x9f, 0xa6, + 0xd8, 0x4b, 0xd3, 0xbd, 0x1e, 0x12, 0x27, 0xef, 0x53, 0xa9, 0xe8, 0x82, 0x1f, 0x29, 0x8f, 0xcd, + 0xee, 0x20, 0xd5, 0x28, 0x85, 0xd8, 0x1b, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, 0x07, 0x01, 0x8d, + 0x8b, 0x41, 0x81, 0x63, 0x95, 0x07, 0x1a, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe1, 0xa7, 0x1a, 0xef, + 0x10, 0x60, 0x5b, 0x23, 0x22, 0xaa, 0x00, 0xa1, 0x45, 0x8d, 0xb7, 0x42, 0x04, 0x41, 0x80, 0x85, + 0x47, 0x01, 0x45, 0xe3, 0x18, 0xf4, 0xb6, 0xef, 0x10, 0x30, 0x24, 0x6d, 0xbf, 0x42, 0x04, 0x41, + 0x80, 0x8d, 0x47, 0xe3, 0x10, 0xf4, 0xb6, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x94, 0x07, + 0x01, 0x8d, 0x8b, 0x41, 0x80, 0x63, 0x94, 0x07, 0x16, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe0, 0x87, + 0x16, 0x0a, 0x04, 0x33, 0x05, 0x64, 0x01, 0xef, 0x20, 0xe0, 0x17, 0x93, 0xf4, 0x04, 0xf0, 0xc9, + 0x8c, 0x13, 0x05, 0x4b, 0x00, 0x22, 0x95, 0xef, 0x20, 0xe0, 0x16, 0xc1, 0x77, 0x93, 0x87, 0xf7, + 0x0f, 0xfd, 0x8c, 0x22, 0x05, 0xc9, 0x8c, 0x13, 0x05, 0x8b, 0x00, 0x22, 0x95, 0xef, 0x20, 0x80, + 0x15, 0xb7, 0x07, 0x01, 0xff, 0xfd, 0x17, 0x42, 0x05, 0xfd, 0x8c, 0xc9, 0x8c, 0x13, 0x05, 0xcb, + 0x00, 0x22, 0x95, 0xef, 0x20, 0x20, 0x14, 0xa2, 0x04, 0x62, 0x05, 0xa1, 0x80, 0xc9, 0x8c, 0x23, + 0x22, 0x9a, 0x00, 0x95, 0xbf, 0x93, 0x07, 0xb4, 0xff, 0xc2, 0x07, 0xc1, 0x83, 0x13, 0x07, 0xb0, + 0x1b, 0xe3, 0x61, 0xf7, 0xae, 0x83, 0x26, 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0x93, 0x09, 0xc0, + 0x03, 0xa1, 0x82, 0xc2, 0x06, 0xc1, 0x82, 0x63, 0xe0, 0xd7, 0x08, 0x37, 0x56, 0x10, 0x00, 0xfa, + 0x4a, 0x99, 0x46, 0x9c, 0x37, 0xa3, 0xdc, 0xa6, 0x39, 0xdd, 0x41, 0x45, 0x19, 0xd8, 0xa3, 0xe9, + 0x2c, 0x60, 0x1c, 0xfb, 0xe9, 0xa4, 0xf5, 0xa0, 0x9f, 0x91, 0xa8, 0x5b, 0xc9, 0xf1, 0x98, 0x0b, + 0xb0, 0x1c, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x06, 0x4b, 0x93, 0x85, 0xc5, 0x4a, 0x13, 0x05, + 0x49, 0x64, 0xef, 0x00, 0x40, 0x63, 0x03, 0x25, 0x0d, 0x00, 0x91, 0x69, 0x93, 0x89, 0x09, 0x20, + 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x26, 0x05, 0x4e, 0x95, 0xef, 0x10, 0x30, 0x13, 0x93, 0x07, + 0xa0, 0x0a, 0xaa, 0x8c, 0x63, 0x12, 0xf5, 0x04, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0xbf, 0x9f, + 0xef, 0x20, 0xe0, 0x36, 0x83, 0x27, 0x0d, 0x00, 0x42, 0x04, 0x41, 0x80, 0xa1, 0x83, 0xc2, 0x07, + 0xc1, 0x83, 0xa6, 0x07, 0xb7, 0x05, 0x20, 0x00, 0x13, 0x06, 0xc4, 0xff, 0x33, 0x85, 0x37, 0x01, + 0x74, 0x10, 0x93, 0x85, 0x45, 0x00, 0xef, 0x10, 0xf0, 0x02, 0x2a, 0x84, 0x93, 0x09, 0x30, 0x0c, + 0xef, 0x20, 0x00, 0x36, 0x63, 0x03, 0x94, 0x01, 0xc1, 0x49, 0x13, 0xf5, 0xf9, 0x0f, 0xe5, 0xae, + 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x10, 0xf4, 0xa4, 0x03, 0x25, 0x0d, 0x00, 0x93, 0x07, + 0xf0, 0x1f, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0xe4, 0xa7, 0x04, 0x91, 0x67, 0x26, 0x05, + 0x93, 0x87, 0x07, 0x20, 0x3e, 0x95, 0x55, 0xbd, 0x42, 0x04, 0x41, 0x80, 0x91, 0x47, 0xe3, 0x1c, + 0xf4, 0xa0, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0x1f, 0x98, 0x68, 0x10, 0xef, 0x10, 0x80, 0x7c, + 0xef, 0x30, 0xa0, 0x20, 0xef, 0x20, 0xa0, 0x2e, 0x91, 0x45, 0x13, 0x05, 0x00, 0x06, 0xef, 0x30, + 0xc0, 0x42, 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x2f, 0x93, 0x07, 0xfa, 0x2c, 0x94, 0x85, 0x95, 0xbe, + 0xbc, 0x46, 0x32, 0x05, 0xf9, 0xdb, 0xf9, 0x27, 0xa4, 0x26, 0xe9, 0x8b, 0xe1, 0xf3, 0x66, 0x23, + 0xcb, 0x7b, 0xbb, 0xdc, 0xa0, 0xbf, 0xa9, 0x42, 0xeb, 0x91, 0xab, 0x88, 0x1d, 0xa0, 0x0a, 0xe3, + 0x0e, 0xf4, 0xe2, 0x93, 0x09, 0xc0, 0x03, 0x59, 0xbf, 0x42, 0x04, 0x41, 0x80, 0x93, 0x07, 0x00, + 0x03, 0xe3, 0x1c, 0xf4, 0x9c, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0x1f, 0x94, 0x68, 0x10, 0xef, + 0x10, 0x80, 0x78, 0xef, 0x30, 0xa0, 0x1c, 0xef, 0x20, 0xa0, 0x2a, 0x93, 0x05, 0x00, 0x03, 0x13, + 0x05, 0x10, 0x06, 0x7d, 0xbf, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x17, 0xf4, 0x9a, 0xef, + 0x30, 0xe0, 0x1a, 0xef, 0x20, 0xe0, 0x28, 0x8d, 0x45, 0x13, 0x05, 0x20, 0x06, 0xef, 0x30, 0x00, + 0x3d, 0x2a, 0x84, 0xef, 0x20, 0x00, 0x2a, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x14, 0xf4, 0xfa, 0xef, + 0xe0, 0x7f, 0xf0, 0x05, 0xb3, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x1f, 0xf4, 0x96, 0xef, + 0x30, 0xe0, 0x17, 0x8d, 0x45, 0x13, 0x05, 0x30, 0x06, 0xef, 0x30, 0x40, 0x3a, 0xb1, 0xb4, 0x42, + 0x04, 0x41, 0x80, 0x93, 0x07, 0x00, 0x03, 0xe3, 0x11, 0xf4, 0x96, 0xef, 0x30, 0x20, 0x16, 0xef, + 0x20, 0x50, 0x6f, 0xb7, 0x15, 0x20, 0x00, 0x2a, 0xd6, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, + 0x05, 0x13, 0x05, 0x00, 0x0a, 0xef, 0x30, 0x60, 0x26, 0x11, 0x46, 0x6c, 0x10, 0x13, 0x05, 0x00, + 0x0c, 0xef, 0x30, 0xa0, 0x25, 0xef, 0x20, 0xc0, 0x21, 0x93, 0x05, 0x00, 0x03, 0x13, 0x05, 0x00, + 0x07, 0xef, 0x30, 0xc0, 0x35, 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x22, 0x93, 0x07, 0xa0, 0x0a, 0xe3, + 0x1a, 0xf4, 0xf2, 0xef, 0xe0, 0xfa, 0x0c, 0x14, 0xa4, 0x33, 0x93, 0x2e, 0xdb, 0xa3, 0x9f, 0x89, + 0x46, 0x26, 0xd5, 0xe6, 0x56, 0xc9, 0x2f, 0x9b, 0x99, 0xaa, 0x99, 0x9d, 0xed, 0x7d, 0x6c, 0xd4, + 0xee, 0x7c, 0xa4, 0xd5, 0x99, 0xea, 0x60, 0x1e, 0x3f, 0xe9, 0x75, 0xb1, 0x93, 0x17, 0x04, 0x01, + 0xc1, 0x83, 0x3d, 0x47, 0xe3, 0x74, 0xf7, 0x90, 0xef, 0x30, 0x80, 0x10, 0xef, 0x20, 0xb0, 0x69, + 0xaa, 0x8c, 0x01, 0x45, 0xef, 0x20, 0xd0, 0x45, 0x41, 0x46, 0x93, 0x85, 0x0a, 0x00, 0x01, 0x45, + 0xef, 0x20, 0xf0, 0x46, 0xef, 0x20, 0x00, 0x1d, 0xb7, 0x15, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, + 0x93, 0x85, 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, 0x66, 0xd6, 0xef, 0x30, 0x40, 0x1f, 0x11, 0x46, + 0x6c, 0x10, 0x13, 0x05, 0x00, 0x0c, 0xef, 0x30, 0x80, 0x1e, 0x85, 0x45, 0x13, 0x05, 0x10, 0x04, + 0xef, 0x30, 0x00, 0x2f, 0x93, 0x07, 0xa0, 0x0a, 0xaa, 0x8c, 0x63, 0x19, 0xf5, 0x00, 0x81, 0x45, + 0x13, 0x05, 0x20, 0x04, 0xef, 0x30, 0xc0, 0x2d, 0x63, 0x05, 0x95, 0x01, 0xef, 0x20, 0xa0, 0x1a, + 0x5d, 0xbd, 0x42, 0x04, 0x41, 0x80, 0x93, 0x0d, 0x04, 0xff, 0xef, 0x20, 0xc0, 0x19, 0xee, 0x8c, + 0x22, 0x9d, 0x93, 0x07, 0x00, 0x09, 0xb3, 0x05, 0x9d, 0x41, 0x63, 0xe5, 0x97, 0x09, 0x66, 0x86, + 0x01, 0x45, 0xef, 0x20, 0xd0, 0x3f, 0xe6, 0x85, 0x13, 0x05, 0x40, 0x04, 0xef, 0x30, 0x40, 0x2a, + 0x13, 0x07, 0xa0, 0x0a, 0xe3, 0x11, 0xe5, 0xe8, 0x2a, 0xce, 0x81, 0x45, 0x13, 0x05, 0x50, 0x04, + 0xef, 0x30, 0x00, 0x29, 0xf2, 0x47, 0xaa, 0x8c, 0xe3, 0x17, 0xf5, 0xe6, 0x01, 0x45, 0xef, 0x20, + 0x30, 0x3b, 0x93, 0x85, 0x0a, 0x00, 0x41, 0x46, 0x01, 0x45, 0xef, 0x20, 0x50, 0x3c, 0x93, 0x07, + 0xfa, 0x21, 0xf4, 0x65, 0xd1, 0xab, 0xb2, 0x5f, 0x75, 0x8a, 0x05, 0x69, 0x14, 0x53, 0xeb, 0xee, + 0x9a, 0x9a, 0x91, 0x1b, 0x59, 0x12, 0xd0, 0x01, 0x82, 0xea, 0x19, 0xb4, 0xd9, 0x27, 0x85, 0x86, + 0x14, 0x38, 0x1f, 0xf0, 0x03, 0xb7, 0x05, 0x20, 0x00, 0x63, 0xe1, 0xb7, 0x07, 0x93, 0x85, 0x05, + 0x01, 0x01, 0x45, 0x6e, 0x86, 0xef, 0x20, 0xd0, 0x3a, 0xee, 0x85, 0x13, 0x05, 0x60, 0x04, 0xef, + 0x30, 0x40, 0x25, 0xe3, 0x1b, 0x95, 0xe3, 0x81, 0x45, 0x13, 0x05, 0xa0, 0x04, 0xef, 0x30, 0x60, + 0x24, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x12, 0xf5, 0xe2, 0xef, 0x20, 0x10, 0x58, 0x93, 0x07, 0x00, + 0x05, 0x23, 0xaa, 0xf9, 0x06, 0xb1, 0xb1, 0x13, 0x06, 0x00, 0x09, 0x01, 0x45, 0xef, 0x20, 0x50, + 0x37, 0x93, 0x05, 0x00, 0x09, 0x13, 0x05, 0x30, 0x04, 0xef, 0x30, 0xa0, 0x21, 0x13, 0x07, 0xa0, + 0x0a, 0xe3, 0x1c, 0xe5, 0xde, 0x93, 0x8c, 0x0c, 0xf7, 0xb1, 0xb7, 0x93, 0x85, 0x05, 0x01, 0x01, + 0x45, 0x13, 0x06, 0x00, 0x04, 0xef, 0x20, 0xd0, 0x34, 0x93, 0x05, 0x00, 0x04, 0x13, 0x05, 0x70, + 0x04, 0xef, 0x30, 0x20, 0x1f, 0xe3, 0x1a, 0x95, 0xdd, 0x13, 0x04, 0x04, 0xfb, 0x93, 0x0c, 0x00, + 0x08, 0x93, 0x0d, 0xa0, 0x0a, 0xb3, 0x05, 0x8d, 0x40, 0x63, 0xe0, 0x8c, 0x02, 0x22, 0x86, 0x01, + 0x45, 0xef, 0x20, 0x10, 0x32, 0xa2, 0x85, 0x13, 0x05, 0x90, 0x04, 0xef, 0x30, 0x80, 0x1c, 0x93, + 0x07, 0xa0, 0x0a, 0xe3, 0x13, 0xf5, 0xda, 0x85, 0xbf, 0x01, 0x45, 0x13, 0x06, 0x00, 0x08, 0xef, + 0x20, 0x30, 0x30, 0x93, 0x05, 0x00, 0x08, 0x13, 0x05, 0x80, 0x04, 0xef, 0x30, 0x80, 0x1a, 0xe3, + 0x15, 0xb5, 0xd9, 0x13, 0x04, 0x04, 0xf8, 0x7d, 0xbf, 0x42, 0x04, 0xfa, 0x97, 0x76, 0x47, 0x17, + 0xcf, 0xa6, 0x2f, 0x96, 0xc8, 0xad, 0x25, 0xe4, 0x10, 0x25, 0x9e, 0xb3, 0xaf, 0x9d, 0xfc, 0x36, + 0x13, 0xb4, 0xa0, 0xf9, 0xfe, 0xe4, 0x13, 0xc9, 0x39, 0x8e, 0x86, 0xe3, 0x10, 0x20, 0x41, 0x80, + 0xa1, 0x47, 0x63, 0x10, 0xf4, 0xf6, 0x03, 0x44, 0x1d, 0x00, 0xbd, 0x47, 0xe3, 0xe8, 0x87, 0xd6, + 0x83, 0x2c, 0x4d, 0x00, 0xfd, 0x57, 0xe3, 0x83, 0xfc, 0xd6, 0x93, 0x19, 0xa4, 0x00, 0x13, 0x85, + 0x09, 0x40, 0xef, 0xe0, 0x8f, 0xe6, 0x13, 0x07, 0xa0, 0x0a, 0x2a, 0x8d, 0xe3, 0x18, 0xe5, 0xd4, + 0x93, 0x89, 0x09, 0x20, 0x4e, 0x85, 0xef, 0xe0, 0x4f, 0xe5, 0xaa, 0x8d, 0xe3, 0x10, 0xa5, 0xd5, + 0xe6, 0x85, 0x4e, 0x85, 0xef, 0x10, 0x60, 0x1b, 0xe3, 0x1a, 0xb5, 0xd3, 0x37, 0x37, 0x20, 0x00, + 0x13, 0x07, 0x47, 0xf5, 0x85, 0x47, 0x33, 0x94, 0x87, 0x00, 0x1c, 0x43, 0x5d, 0x8c, 0x00, 0xc3, + 0x91, 0xbe, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0x63, 0x1d, 0xf4, 0xee, 0x83, 0x45, 0x1d, 0x00, + 0xbd, 0x47, 0xe3, 0xe5, 0xb7, 0xd0, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf5, 0xd1, 0x49, + 0xb3, 0xd7, 0xb7, 0x00, 0x85, 0x8b, 0xe3, 0x88, 0x07, 0xc8, 0x37, 0x15, 0x20, 0x00, 0x13, 0x05, + 0x05, 0x08, 0xef, 0xe0, 0x6f, 0xeb, 0x85, 0x47, 0xe3, 0x07, 0xf5, 0xb4, 0x89, 0x47, 0xe3, 0x0c, + 0xf5, 0xc6, 0xe9, 0xb9, 0xef, 0x10, 0x90, 0x43, 0xef, 0xe0, 0x8f, 0xd8, 0x6f, 0xf0, 0xef, 0xe6, + 0xef, 0x00, 0xc0, 0x6f, 0x6f, 0xf0, 0xef, 0xe6, 0xef, 0x00, 0x30, 0x4e, 0x41, 0x14, 0xaa, 0x86, + 0x63, 0x0b, 0x05, 0xea, 0x8d, 0x45, 0x13, 0x85, 0xcd, 0x3d, 0x36, 0xce, 0x71, 0x24, 0xf2, 0x46, + 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0xfa, 0xfa, 0xed, 0x0e, 0x25, 0x97, 0x1a, 0x14, 0x04, 0xa4, + 0xbd, 0xd2, 0x3a, 0x3a, 0x9f, 0xe3, 0x8b, 0x67, 0x47, 0xe8, 0x6a, 0xdc, 0x29, 0x81, 0x3b, 0x50, + 0x99, 0x56, 0xc0, 0x95, 0x76, 0x28, 0x2b, 0xe8, 0x20, 0xc6, 0x45, 0x93, 0x85, 0xcd, 0x3d, 0x13, + 0x05, 0x49, 0x64, 0x09, 0x24, 0xf2, 0x46, 0x09, 0x47, 0x85, 0x47, 0x63, 0x83, 0xe6, 0x00, 0x89, + 0x47, 0x83, 0xc6, 0x89, 0x07, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x22, 0x87, 0x13, + 0x06, 0xc6, 0x47, 0x93, 0x85, 0xc5, 0x3f, 0x13, 0x05, 0x49, 0x64, 0xa3, 0x8c, 0xf9, 0x06, 0xd9, + 0x2a, 0xef, 0xe0, 0x8f, 0xce, 0xef, 0xe0, 0x8f, 0xff, 0x62, 0x47, 0x85, 0x47, 0x23, 0x00, 0xf7, + 0x00, 0xef, 0x00, 0xe0, 0x5a, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x11, 0xf5, 0xd6, 0x25, + 0x29, 0x63, 0x1e, 0x85, 0xd4, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xf4, 0xb1, 0xeb, 0x83, + 0xa7, 0x4b, 0x07, 0x13, 0x07, 0xfb, 0x00, 0xfd, 0x17, 0x63, 0x64, 0xf7, 0x04, 0x05, 0x45, 0xef, + 0x20, 0xb0, 0x17, 0x03, 0xa6, 0x4b, 0x07, 0xb7, 0x09, 0x20, 0x00, 0x93, 0x85, 0x09, 0x00, 0x13, + 0x85, 0x09, 0x00, 0xef, 0x20, 0xf0, 0x25, 0x37, 0x14, 0x20, 0x00, 0x13, 0x05, 0x04, 0x02, 0xef, + 0x20, 0x50, 0x34, 0x03, 0xa5, 0x4b, 0x07, 0x93, 0x87, 0x09, 0x00, 0x41, 0x46, 0x3e, 0x95, 0x93, + 0x05, 0x04, 0x02, 0xef, 0x30, 0x00, 0x5f, 0x83, 0xa7, 0x4b, 0x07, 0xc1, 0x07, 0x23, 0xaa, 0xfb, + 0x06, 0xef, 0x00, 0xf0, 0x1b, 0x13, 0x04, 0xa0, 0x0a, 0x63, 0x0a, 0x85, 0xce, 0xef, 0xe0, 0x8f, + 0xfe, 0x63, 0x16, 0x85, 0xce, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, + 0x00, 0xfa, 0xee, 0xcd, 0x72, 0xe8, 0x11, 0xe1, 0x86, 0x9a, 0x0d, 0x80, 0x99, 0x72, 0x80, 0xf7, + 0x48, 0xdd, 0x8d, 0xda, 0xa6, 0xcc, 0x34, 0x93, 0x16, 0x5a, 0x6e, 0x0f, 0xb1, 0xa0, 0x8f, 0xfb, + 0x20, 0xf9, 0xc0, 0x21, 0x13, 0x06, 0x06, 0x4d, 0x93, 0x85, 0xc5, 0x3f, 0x13, 0x05, 0x45, 0x40, + 0x25, 0x22, 0xef, 0xe0, 0x2f, 0xb7, 0xef, 0x20, 0x70, 0x32, 0xef, 0x00, 0xb0, 0x3a, 0xef, 0x00, + 0xb0, 0x31, 0xef, 0xe0, 0xaf, 0xf9, 0x6f, 0xf0, 0xaf, 0xcb, 0x2a, 0x87, 0x81, 0x47, 0x01, 0x45, + 0x63, 0x93, 0xc7, 0x00, 0x82, 0x80, 0xb3, 0x06, 0xf7, 0x00, 0x33, 0x88, 0xf5, 0x00, 0x83, 0xc6, + 0x06, 0x00, 0x03, 0x48, 0x08, 0x00, 0x85, 0x07, 0xb3, 0xc6, 0x06, 0x01, 0x55, 0x8d, 0x13, 0x75, + 0xf5, 0x0f, 0xf9, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x37, 0x37, 0x20, 0x00, 0x03, 0xa8, 0xc7, 0xf5, + 0x83, 0x27, 0x87, 0xf5, 0xaa, 0x86, 0x13, 0x07, 0x87, 0xf5, 0x01, 0x45, 0x63, 0x13, 0xf8, 0x00, + 0x82, 0x80, 0x37, 0x26, 0x20, 0x00, 0x13, 0x06, 0xc6, 0x08, 0x93, 0x08, 0xf0, 0x7f, 0x63, 0x01, + 0xb5, 0x02, 0x33, 0x0e, 0xf6, 0x00, 0x03, 0x4e, 0x0e, 0x00, 0x05, 0x05, 0x33, 0x83, 0xa6, 0x00, + 0xa3, 0x0f, 0xc3, 0xff, 0x85, 0x07, 0x63, 0xf3, 0xf8, 0x00, 0x81, 0x47, 0xe3, 0x11, 0xf8, 0xfe, + 0x1c, 0xc3, 0x82, 0x80, 0xb7, 0x36, 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x86, 0xf5, + 0x83, 0xa7, 0xc7, 0xf5, 0x93, 0x86, 0x86, 0xf5, 0x33, 0x87, 0xe7, 0x40, 0x63, 0x56, 0x07, 0x00, + 0x05, 0x66, 0x13, 0x06, 0x06, 0x80, 0x32, 0x97, 0x63, 0x5b, 0xe5, 0x00, 0x33, 0x85, 0xa7, 0x40, + 0x85, 0x67, 0x93, 0x87, 0x07, 0x80, 0x63, 0xf3, 0xa7, 0x00, 0x3e, 0x95, 0xfa, 0x15, 0xcc, 0xaa, + 0x68, 0x39, 0xfb, 0x6e, 0x69, 0x05, 0x96, 0xc7, 0x2a, 0xd1, 0x84, 0x5c, 0xfb, 0xc6, 0xdd, 0x36, + 0x93, 0x9a, 0x83, 0x7c, 0x41, 0xab, 0x77, 0xf6, 0x79, 0xea, 0xad, 0x86, 0x44, 0x98, 0x22, 0x88, + 0xc2, 0x82, 0x80, 0xb7, 0x36, 0x20, 0x00, 0x03, 0xa8, 0xc6, 0xf5, 0x13, 0x07, 0xf0, 0x7f, 0x13, + 0x86, 0xc6, 0xf5, 0x93, 0x07, 0x18, 0x00, 0x63, 0x73, 0xf7, 0x00, 0x81, 0x47, 0xb7, 0x36, 0x20, + 0x00, 0x83, 0xa8, 0x86, 0xf5, 0x37, 0x27, 0x20, 0x00, 0x93, 0x85, 0x86, 0xf5, 0x13, 0x07, 0xc7, + 0x08, 0x63, 0x9f, 0xf8, 0x00, 0x93, 0x88, 0x17, 0x80, 0x93, 0x86, 0x17, 0x00, 0x63, 0x93, 0x08, + 0x00, 0x81, 0x46, 0x94, 0xc1, 0xba, 0x96, 0x93, 0x05, 0xa0, 0x02, 0x23, 0x80, 0xb6, 0x00, 0x42, + 0x97, 0x23, 0x00, 0xa7, 0x00, 0x1c, 0xc2, 0x82, 0x80, 0x82, 0x80, 0x39, 0x71, 0x22, 0xcc, 0x26, + 0xca, 0x4a, 0xc8, 0x06, 0xce, 0x36, 0xd6, 0x3a, 0xd8, 0x3e, 0xda, 0x42, 0xdc, 0x46, 0xde, 0xaa, + 0x84, 0x2e, 0x89, 0x32, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0xdf, 0x96, 0x63, 0x14, 0x09, 0x00, 0xef, + 0xe0, 0x5f, 0x96, 0x19, 0xe0, 0xef, 0xe0, 0xff, 0x95, 0x7c, 0x10, 0x3e, 0xc6, 0xef, 0x30, 0x20, + 0x13, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x60, 0xef, 0x30, 0x20, 0x38, 0x37, + 0x55, 0x10, 0x00, 0x4a, 0x86, 0xa6, 0x85, 0x13, 0x05, 0x05, 0x61, 0xef, 0x30, 0x20, 0x37, 0xb2, + 0x45, 0x22, 0x85, 0xef, 0x30, 0x80, 0x33, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x61, 0xef, + 0x30, 0xe0, 0x35, 0xb9, 0x29, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0x21, 0x61, 0x82, + 0x80, 0xae, 0x86, 0x37, 0x56, 0x10, 0x00, 0xfa, 0x19, 0xec, 0x43, 0xf5, 0xf7, 0x10, 0xef, 0xba, + 0x41, 0x9b, 0x08, 0x7a, 0xeb, 0x0a, 0xf9, 0x9d, 0xfa, 0x4b, 0xac, 0x76, 0x2f, 0x8f, 0x6e, 0x1e, + 0x22, 0x50, 0x1a, 0xc3, 0x1d, 0x20, 0x63, 0x01, 0x70, 0x23, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, + 0x13, 0x06, 0xc6, 0x4b, 0x13, 0x05, 0x05, 0x62, 0x9d, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, + 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, 0x83, 0xa6, 0x47, 0x10, 0x63, 0x7e, 0xd7, 0x00, 0x0a, 0x07, + 0x3e, 0x97, 0x18, 0x43, 0x18, 0xc1, 0x03, 0xa7, 0x07, 0x10, 0x13, 0x05, 0xa0, 0x0a, 0x05, 0x07, + 0x23, 0xa0, 0xe7, 0x10, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, 0x26, 0xca, + 0xb7, 0x34, 0x20, 0x00, 0x83, 0xa7, 0x04, 0xf6, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, + 0x52, 0xc4, 0x11, 0x47, 0x63, 0x6f, 0xf7, 0x0c, 0x37, 0x57, 0x10, 0x00, 0x8a, 0x07, 0x13, 0x07, + 0x87, 0x64, 0xba, 0x97, 0x9c, 0x43, 0x2a, 0x84, 0x93, 0x84, 0x04, 0xf6, 0x82, 0x87, 0x81, 0x45, + 0xef, 0x30, 0x20, 0x31, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x92, 0xa7, 0xf6, 0xb7, 0x37, 0x20, 0x00, + 0x23, 0x86, 0x87, 0x88, 0xef, 0x20, 0xd0, 0x6f, 0x9c, 0x40, 0x85, 0x07, 0x81, 0xa8, 0xb7, 0x37, + 0x20, 0x00, 0x23, 0xa4, 0x07, 0xf6, 0x93, 0x07, 0xc0, 0x0f, 0x63, 0xf1, 0xa7, 0x02, 0x62, 0x44, + 0x9d, 0x47, 0xf2, 0x40, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x9c, 0xc0, 0xd2, 0x44, 0x37, 0x55, + 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x45, 0x62, 0x05, 0x61, 0x2d, 0xbf, 0x37, 0x39, 0x20, 0x00, + 0x13, 0x09, 0x49, 0xf6, 0x83, 0x55, 0x09, 0x00, 0xef, 0x30, 0xa0, 0x2b, 0xb7, 0x37, 0x20, 0x00, + 0xa3, 0x86, 0xfa, 0xe1, 0x89, 0x69, 0x3c, 0xbb, 0x3d, 0xa6, 0x8a, 0x75, 0x3d, 0xa4, 0xe2, 0x78, + 0x6a, 0x48, 0x56, 0x26, 0x01, 0x36, 0x65, 0x68, 0xf6, 0x03, 0xab, 0x63, 0x8f, 0xa6, 0x8c, 0x7e, + 0x7c, 0xdc, 0x6c, 0x48, 0x24, 0x87, 0x88, 0x23, 0x10, 0xa9, 0x00, 0x8d, 0x47, 0x5d, 0xf4, 0x9c, + 0xc0, 0x91, 0xa8, 0x37, 0x39, 0x20, 0x00, 0x03, 0x27, 0x89, 0xf6, 0x93, 0x07, 0xb0, 0x0f, 0x13, + 0x09, 0x89, 0xf6, 0x63, 0xf4, 0xe7, 0x00, 0xef, 0xe0, 0x3f, 0x81, 0x83, 0x27, 0x09, 0x00, 0x37, + 0x3a, 0x20, 0x00, 0x13, 0x0a, 0x4a, 0xf6, 0xb7, 0x39, 0x20, 0x00, 0x93, 0x89, 0xc9, 0x88, 0x83, + 0x55, 0x0a, 0x00, 0xce, 0x97, 0x23, 0x81, 0x87, 0x00, 0x22, 0x85, 0xef, 0x30, 0xa0, 0x26, 0x83, + 0x27, 0x09, 0x00, 0x03, 0xc7, 0x19, 0x00, 0x23, 0x10, 0xaa, 0x00, 0x85, 0x07, 0x23, 0x20, 0xf9, + 0x00, 0xe3, 0xfd, 0xe7, 0xf4, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, + 0x4a, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x93, 0xa7, 0xf6, 0x3d, 0xbf, 0x37, + 0x39, 0x20, 0x00, 0x13, 0x09, 0x69, 0xf6, 0x13, 0x14, 0x85, 0x00, 0xb7, 0x39, 0x20, 0x00, 0x03, + 0x55, 0x09, 0x00, 0x93, 0x89, 0x49, 0xf6, 0x83, 0xd7, 0x09, 0x00, 0x49, 0x8c, 0x23, 0x10, 0x89, + 0x00, 0xe3, 0x8d, 0x87, 0xf0, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0x44, 0x62, 0x99, 0x47, 0x89, + 0x45, 0x9c, 0xc0, 0x95, 0x3d, 0x93, 0x05, 0x44, 0x62, 0x62, 0x44, 0x03, 0xd7, 0x09, 0x00, 0x83, + 0x56, 0x09, 0x00, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x37, 0x56, 0x10, + 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x86, 0x62, 0x13, 0x05, 0x45, 0x64, 0xfa, 0x13, 0xa0, + 0xfe, 0xe6, 0x97, 0x97, 0xfc, 0x05, 0xad, 0x6d, 0xc1, 0x90, 0x45, 0x32, 0x83, 0x16, 0x84, 0xb7, + 0xae, 0x80, 0xb3, 0x10, 0x97, 0x4c, 0x89, 0xa3, 0x5c, 0x15, 0xc4, 0x30, 0x20, 0x00, 0x20, 0x25, + 0x05, 0x61, 0x6f, 0xf0, 0x3f, 0xdd, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0xb7, 0x25, + 0x10, 0x00, 0x37, 0x25, 0x10, 0x00, 0x23, 0xa0, 0x07, 0x10, 0x23, 0xa2, 0x07, 0x10, 0x93, 0x85, + 0x05, 0xf8, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x05, 0x25, 0xfb, 0x23, 0xa0, 0x07, 0xf6, 0x6f, 0x20, + 0xb0, 0x52, 0x11, 0xed, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0xef, 0xe0, 0x2f, 0xf2, 0x32, 0x45, + 0xf2, 0x40, 0x13, 0x06, 0xe0, 0x0f, 0x81, 0x45, 0x05, 0x61, 0x6f, 0x30, 0x40, 0x25, 0x13, 0x06, + 0xe0, 0x0f, 0x81, 0x45, 0xdd, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xf6, 0x13, 0x05, + 0xa0, 0x0a, 0x99, 0xc3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, + 0x20, 0x00, 0x13, 0x04, 0x04, 0xf6, 0x1c, 0x40, 0x06, 0xc6, 0x15, 0x47, 0x63, 0x98, 0xe7, 0x00, + 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x81, 0xe7, 0x13, 0x05, + 0x50, 0x05, 0xcd, 0xbf, 0xef, 0x20, 0x90, 0x50, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x19, 0xf5, 0xfe, + 0x01, 0x00, 0x18, 0x40, 0x91, 0x47, 0xe3, 0xcd, 0xe7, 0xfc, 0x99, 0x47, 0x1c, 0xc0, 0xd9, 0xbf, + 0x41, 0x11, 0x06, 0xc6, 0xef, 0x20, 0x10, 0x50, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xf5, 0x00, + 0xef, 0x20, 0x70, 0x51, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x95, 0x47, 0x13, 0x05, + 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0xfa, 0xca, 0xa6, 0x83, 0xd7, 0x7d, 0x53, 0xa9, + 0xaa, 0x73, 0x81, 0x1f, 0xa9, 0xcf, 0x0f, 0x1b, 0x12, 0x76, 0xef, 0x97, 0x8c, 0xce, 0xe0, 0x13, + 0x0e, 0x44, 0xc4, 0xd0, 0xfe, 0x0d, 0xe4, 0x36, 0xa3, 0xf8, 0x25, 0x50, 0x05, 0xb2, 0x40, 0x41, + 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x99, 0x47, 0x13, 0x05, 0xa0, + 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, + 0xa7, 0x07, 0xf6, 0x9d, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, + 0x05, 0x82, 0x80, 0x37, 0x35, 0x20, 0x00, 0x13, 0x05, 0xc5, 0x88, 0x82, 0x80, 0x01, 0x11, 0x26, + 0xca, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0xaa, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, + 0xe3, 0x83, 0xc7, 0x14, 0x00, 0x13, 0x07, 0xc0, 0x0f, 0x13, 0x05, 0x50, 0x05, 0x63, 0x65, 0xf7, + 0x06, 0x37, 0x39, 0x20, 0x00, 0x13, 0x04, 0xc9, 0x98, 0x23, 0x20, 0x04, 0x10, 0x03, 0xc7, 0x04, + 0x00, 0xa3, 0x00, 0xf4, 0x00, 0x03, 0xc6, 0x14, 0x00, 0x23, 0x00, 0xe4, 0x00, 0x93, 0x85, 0x24, + 0x00, 0x13, 0x05, 0x24, 0x00, 0xef, 0x30, 0x00, 0x10, 0x83, 0xc9, 0x14, 0x00, 0x13, 0x05, 0xc9, + 0x98, 0x13, 0x09, 0xc9, 0x98, 0x93, 0x84, 0x29, 0x00, 0xa6, 0x85, 0xef, 0x30, 0x60, 0x08, 0xa2, + 0x94, 0x23, 0x80, 0xa4, 0x00, 0x4e, 0x94, 0x21, 0x81, 0x93, 0x87, 0x49, 0x00, 0xa3, 0x01, 0xa4, + 0x00, 0xfd, 0x56, 0x13, 0xf7, 0x37, 0x00, 0x19, 0xef, 0x89, 0x83, 0x23, 0x22, 0xf9, 0x10, 0xef, + 0x20, 0xb0, 0x45, 0x13, 0x05, 0xa0, 0x0a, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, + 0x49, 0x05, 0x61, 0xfa, 0x42, 0x8f, 0x96, 0xf9, 0x34, 0x25, 0x1f, 0x81, 0xb7, 0xfe, 0xbd, 0x46, + 0x43, 0x19, 0xc3, 0xbd, 0xfe, 0xc4, 0x15, 0xd2, 0xa1, 0xe8, 0x11, 0xdc, 0xeb, 0xce, 0x72, 0x09, + 0xfb, 0xf0, 0xde, 0x38, 0xd0, 0x26, 0x82, 0x80, 0x33, 0x07, 0xf9, 0x00, 0x23, 0x00, 0xd7, 0x00, + 0x85, 0x07, 0xd1, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, + 0x83, 0xa7, 0x47, 0x10, 0x63, 0x14, 0xf7, 0x00, 0x6f, 0x20, 0x30, 0x3e, 0x13, 0x05, 0x50, 0x05, + 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa0, 0x07, 0xf6, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, + 0x93, 0x07, 0x00, 0x08, 0x73, 0xa0, 0x47, 0x30, 0x93, 0x06, 0x70, 0x3e, 0x09, 0x46, 0x93, 0x05, + 0x60, 0x04, 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, 0x30, 0x52, 0x8d, 0x45, 0x37, 0x05, 0x10, 0x01, + 0xef, 0x20, 0x70, 0x52, 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, 0xf0, 0x4f, 0x37, 0x05, 0x20, 0x01, + 0xef, 0x20, 0x10, 0x50, 0xfd, 0x56, 0x01, 0x46, 0x93, 0x05, 0x60, 0x04, 0x37, 0x05, 0x20, 0x01, + 0xef, 0x20, 0x90, 0x4f, 0xb2, 0x40, 0xb7, 0x07, 0x20, 0x01, 0x23, 0xac, 0x07, 0x00, 0x41, 0x01, + 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x89, 0x2c, 0xb2, 0x40, 0x41, 0x01, 0x45, 0xb7, 0x41, 0x11, + 0x22, 0xc4, 0xb7, 0x07, 0x20, 0x01, 0x06, 0xc6, 0x23, 0xac, 0x07, 0x00, 0x2a, 0x84, 0x37, 0x05, + 0x20, 0x01, 0xef, 0x20, 0x50, 0x4b, 0x93, 0x07, 0x80, 0x3e, 0x13, 0x05, 0x80, 0x3e, 0x63, 0xe3, + 0x87, 0x00, 0x22, 0x85, 0xb7, 0x07, 0x20, 0x01, 0x98, 0x4f, 0x13, 0x84, 0x87, 0x01, 0xe3, 0x6d, + 0xa7, 0xfe, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0xb0, 0x49, 0xb2, 0x40, 0x23, 0x20, 0xfa, 0x9b, + 0x07, 0xb3, 0x36, 0x28, 0x7f, 0xc6, 0xca, 0xff, 0x0c, 0x98, 0xc8, 0xc6, 0xbe, 0xcf, 0xcd, 0x4b, + 0xb5, 0x6c, 0x32, 0x48, 0x0e, 0x70, 0x8d, 0xad, 0xf2, 0x9d, 0x21, 0x0a, 0x2a, 0x2e, 0xc1, 0xa8, + 0x27, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x11, 0xe1, 0x82, 0x80, 0x01, 0x00, 0x7d, + 0x15, 0xe5, 0xbf, 0x6f, 0xf0, 0x9f, 0xb3, 0x39, 0xa4, 0x01, 0x11, 0x26, 0xca, 0xaa, 0x84, 0x37, + 0x05, 0x20, 0x01, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x56, 0xc2, 0x06, 0xce, 0x22, 0xcc, 0x2e, + 0x89, 0x93, 0x09, 0xa0, 0x0a, 0xef, 0x20, 0x50, 0x45, 0x37, 0x0a, 0x20, 0x01, 0x93, 0x0a, 0x80, + 0x3e, 0x82, 0x94, 0x2a, 0x84, 0x63, 0x0c, 0x35, 0x03, 0x83, 0x27, 0x8a, 0x01, 0x63, 0x7a, 0xf9, + 0x04, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0xc4, 0x65, 0x85, 0x45, 0xef, 0xf0, 0x9f, 0xb6, 0x37, + 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0x05, 0xc4, 0x65, 0xa6, 0x86, 0x13, 0x06, 0x06, + 0x66, 0x13, 0x05, 0x45, 0x64, 0xef, 0xf0, 0x9f, 0xad, 0x13, 0x04, 0x50, 0x05, 0x37, 0x05, 0x20, + 0x01, 0xef, 0x20, 0x30, 0x41, 0xf2, 0x40, 0x22, 0x85, 0x62, 0x44, 0xb7, 0x07, 0x20, 0x01, 0x23, + 0xac, 0x07, 0x00, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, + 0x80, 0xe3, 0xf0, 0x2a, 0xfb, 0x41, 0x22, 0x69, 0xbf, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, + 0xe7, 0x87, 0x00, 0x1c, 0xc7, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x2a, + 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, 0xc1, 0xa9, 0x44, 0x03, 0x45, 0x04, 0x00, 0x11, 0xe5, 0xb2, + 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xfa, 0x64, 0xf6, 0xce, 0x84, 0x88, 0x24, + 0x76, 0xd8, 0x4d, 0x95, 0x7b, 0xf3, 0x36, 0xe2, 0xe5, 0x99, 0x6d, 0x8f, 0xf2, 0xc0, 0xc6, 0x9f, + 0x30, 0x1e, 0x9d, 0x16, 0xfb, 0x95, 0x44, 0xae, 0x6e, 0x02, 0x80, 0x28, 0xef, 0xf0, 0xdf, 0xa1, + 0x83, 0x47, 0x04, 0x00, 0x63, 0x94, 0x97, 0x00, 0xef, 0xf0, 0x7f, 0xa6, 0x05, 0x04, 0xf9, 0xbf, + 0x41, 0x11, 0x06, 0xc6, 0x25, 0x37, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x05, 0xf5, 0x00, 0xef, 0xe0, + 0xaf, 0xbd, 0x01, 0xa0, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x44, + 0x20, 0x00, 0x13, 0x06, 0xc0, 0x1f, 0x81, 0x45, 0x13, 0x05, 0x04, 0xe0, 0x06, 0xc6, 0x26, 0xc2, + 0xef, 0x20, 0xb0, 0x6f, 0x13, 0x05, 0x04, 0xe0, 0x93, 0x05, 0xc0, 0x1f, 0xef, 0x20, 0xb0, 0x67, + 0x93, 0x04, 0x04, 0xe0, 0xb2, 0x40, 0x22, 0x44, 0x23, 0xae, 0xa4, 0x1e, 0x92, 0x44, 0x41, 0x01, + 0x82, 0x80, 0x41, 0x11, 0x37, 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, 0xc0, 0x1f, 0x13, 0x04, + 0x05, 0xe0, 0x13, 0x05, 0x05, 0xe0, 0x06, 0xc6, 0xef, 0x20, 0xf0, 0x64, 0x03, 0x27, 0xc4, 0x1f, + 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xa7, 0x00, 0x93, 0x07, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, + 0x3e, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, 0xaa, 0x87, 0x63, 0x6e, 0xa7, 0x00, + 0x13, 0x77, 0x35, 0x00, 0x01, 0x45, 0x11, 0xeb, 0x37, 0x45, 0x20, 0x00, 0x13, 0x05, 0x05, 0xe0, + 0xf1, 0x9b, 0xaa, 0x97, 0x88, 0x43, 0x82, 0x80, 0x01, 0x45, 0x82, 0x80, 0x93, 0x07, 0xb0, 0x1f, + 0x63, 0xec, 0xa7, 0x00, 0x93, 0x77, 0x35, 0x00, 0x81, 0xeb, 0xb7, 0x47, 0x20, 0x00, 0x71, 0x99, + 0x93, 0x87, 0x07, 0xe0, 0xfa, 0xa5, 0xf1, 0xcc, 0x0e, 0x38, 0x57, 0xc4, 0xf4, 0x5e, 0xcb, 0xb6, + 0xb8, 0xe1, 0x94, 0xa4, 0xd4, 0x5c, 0x5e, 0xa1, 0x3a, 0x9f, 0xdd, 0x18, 0xe3, 0xb4, 0x27, 0x7f, + 0x90, 0x45, 0xee, 0x37, 0x24, 0x58, 0x29, 0x3e, 0x95, 0x0c, 0xc1, 0x82, 0x80, 0x41, 0x11, 0x37, + 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, 0xc0, 0x1f, 0x13, 0x04, 0x05, 0xe0, 0x13, 0x05, 0x05, + 0xe0, 0x06, 0xc6, 0xef, 0x20, 0x70, 0x5d, 0xb2, 0x40, 0x23, 0x2e, 0xa4, 0x1e, 0x22, 0x44, 0x41, + 0x01, 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, 0x63, 0x61, 0xa7, 0x02, 0x93, 0x77, 0x35, 0x00, 0x13, + 0x07, 0x50, 0x05, 0x89, 0xef, 0x41, 0x11, 0x06, 0xc6, 0x5d, 0x37, 0xc9, 0x37, 0xb2, 0x40, 0x13, + 0x07, 0xa0, 0x0a, 0x3a, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0x50, 0x05, 0x3a, 0x85, 0x82, + 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x00, 0x10, 0x71, 0xb2, 0x40, 0xb7, 0x07, 0x00, 0x02, 0x0d, + 0x47, 0xf8, 0xcb, 0x13, 0x05, 0xa0, 0x0a, 0x41, 0x01, 0x82, 0x80, 0x73, 0x00, 0x50, 0x10, 0x82, + 0x80, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x52, 0xcc, 0x06, 0xd6, 0x2a, + 0x84, 0xae, 0x84, 0x32, 0x89, 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x07, 0x39, 0x41, 0x33, 0x05, 0x34, + 0x01, 0x63, 0x6c, 0xfa, 0x02, 0x71, 0x56, 0x93, 0x57, 0x29, 0x00, 0xb3, 0x87, 0xc7, 0x02, 0x93, + 0x75, 0xc9, 0xff, 0x33, 0x05, 0xb4, 0x00, 0xae, 0x94, 0x33, 0x86, 0x27, 0x01, 0x11, 0xc6, 0x9c, + 0x40, 0x6c, 0x00, 0x3e, 0xc6, 0xef, 0x20, 0xd0, 0x56, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, + 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0xb3, 0x87, 0x34, 0x01, 0x9c, 0x43, 0xfa, + 0x96, 0x2d, 0x7e, 0x3a, 0xd4, 0x29, 0xdc, 0xc6, 0xf5, 0x7b, 0x9d, 0xde, 0x3a, 0xe3, 0x13, 0xf0, + 0xa4, 0xda, 0xb9, 0xcb, 0x28, 0xf6, 0x65, 0x59, 0xcb, 0x7c, 0xca, 0xb7, 0x30, 0x66, 0xd9, 0x07, + 0x30, 0x2a, 0x11, 0x46, 0x6c, 0x00, 0x3e, 0xc6, 0x91, 0x09, 0xef, 0x20, 0xb0, 0x54, 0x7d, 0xb7, + 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x52, 0xcc, 0x06, 0xd6, 0x2a, 0x84, + 0xae, 0x84, 0x32, 0x89, 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x07, 0x39, 0x41, 0xb3, 0x85, 0x34, 0x01, + 0x63, 0x6d, 0xfa, 0x02, 0x71, 0x56, 0x93, 0x57, 0x29, 0x00, 0xb3, 0x87, 0xc7, 0x02, 0x93, 0x75, + 0xc9, 0xff, 0x2e, 0x94, 0xa6, 0x95, 0x33, 0x86, 0x27, 0x01, 0x01, 0xca, 0x1c, 0x40, 0x68, 0x00, + 0x3e, 0xc6, 0xef, 0x20, 0x30, 0x50, 0xb2, 0x47, 0x1c, 0xc0, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, + 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0x11, 0x46, 0x68, 0x00, 0xef, 0x20, + 0x70, 0x4e, 0x32, 0x47, 0xb3, 0x07, 0x34, 0x01, 0x91, 0x09, 0x98, 0xc3, 0x75, 0xb7, 0x41, 0x11, + 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x6f, 0x9c, 0xb7, 0x37, 0x20, 0x00, + 0x13, 0x07, 0x50, 0x05, 0x23, 0xa6, 0xe7, 0xf6, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa8, 0x87, 0xf6, + 0x22, 0x44, 0xb2, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x8a, 0x07, 0xa8, 0x41, 0x01, 0x6f, 0xf0, + 0xbf, 0xa4, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, 0x99, + 0x37, 0x35, 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0xa2, 0x85, 0x13, 0x06, 0xe0, 0x0f, 0x13, 0x05, + 0x45, 0xa9, 0x23, 0x8a, 0x07, 0xb8, 0xef, 0x20, 0xf0, 0x47, 0xfa, 0xf5, 0xf6, 0x53, 0xaf, 0xb2, + 0x2b, 0x3b, 0x05, 0xa1, 0xfd, 0x11, 0x48, 0x09, 0x71, 0x5b, 0x0d, 0x75, 0x63, 0x38, 0x76, 0x8a, + 0x94, 0xff, 0xca, 0xca, 0x71, 0x6f, 0x6d, 0x48, 0xc9, 0xc4, 0x5b, 0x08, 0x2b, 0x22, 0x85, 0x22, + 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xb2, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x26, + 0xc2, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0xcf, 0x95, 0xb7, 0x34, 0x20, 0x00, 0x83, 0xc7, 0x44, + 0xb9, 0x99, 0xcb, 0x37, 0x35, 0x20, 0x00, 0x13, 0x06, 0xe0, 0x0f, 0x93, 0x85, 0x44, 0xb9, 0x13, + 0x05, 0x45, 0xa9, 0xef, 0x20, 0x50, 0x44, 0xa2, 0x85, 0x13, 0x85, 0x44, 0xb9, 0x13, 0x06, 0xe0, + 0x0f, 0xef, 0x20, 0x70, 0x43, 0x22, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x92, 0x44, 0x41, 0x01, 0x6f, + 0xf0, 0x1f, 0xae, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0xc7, 0xf6, 0x82, 0x80, 0x41, 0x11, 0x22, + 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0xc4, 0xf6, 0x26, 0xc2, 0x04, 0x40, 0x06, 0xc6, 0x93, + 0x07, 0xa0, 0x0a, 0x63, 0x89, 0xf4, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x92, + 0x44, 0x41, 0x01, 0x82, 0x80, 0x37, 0x35, 0x20, 0x00, 0x13, 0x05, 0x45, 0xb9, 0xef, 0xf0, 0x3f, + 0xaa, 0xe3, 0x13, 0x95, 0xfe, 0x93, 0x07, 0x50, 0x05, 0x1c, 0xc0, 0xc5, 0xb7, 0x37, 0x35, 0x20, + 0x00, 0x83, 0x47, 0x45, 0xa9, 0x85, 0xc3, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xc7, 0x47, 0xb9, 0x99, + 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf6, 0x13, 0x05, 0x45, + 0xa9, 0x6f, 0xf0, 0xff, 0xa6, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, + 0xf0, 0xdf, 0x99, 0x93, 0x07, 0xfa, 0x40, 0xaf, 0x15, 0x12, 0x17, 0xb6, 0x43, 0x1a, 0xa9, 0x9b, + 0xa0, 0x07, 0x95, 0xfa, 0x8a, 0xce, 0xbd, 0x9e, 0x0c, 0xbf, 0x1f, 0xff, 0x1d, 0x40, 0x36, 0xf2, + 0xe6, 0xe0, 0x9e, 0x30, 0x8b, 0x01, 0xe0, 0x2b, 0xa0, 0x0a, 0x63, 0x04, 0xf5, 0x00, 0x13, 0x05, + 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x6d, 0x71, 0x23, 0x26, 0x11, 0x10, 0x23, 0x24, + 0x81, 0x10, 0x23, 0x22, 0x91, 0x10, 0xef, 0xf0, 0xdf, 0x98, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, + 0xf5, 0x04, 0x2a, 0x84, 0xef, 0xf0, 0x5f, 0x9c, 0x63, 0x1b, 0x85, 0x06, 0xef, 0xf0, 0xdf, 0xa1, + 0x83, 0x46, 0x05, 0x00, 0x93, 0x07, 0x20, 0x0a, 0x2a, 0x84, 0x63, 0x80, 0xf6, 0x02, 0x37, 0x56, + 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x66, 0x93, 0x85, + 0xc5, 0x67, 0x13, 0x05, 0x45, 0x64, 0xef, 0xf0, 0x6f, 0xeb, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, + 0x07, 0xf7, 0x22, 0x85, 0x82, 0x97, 0xef, 0xf0, 0xff, 0xaa, 0xef, 0xf0, 0xdf, 0xa8, 0x93, 0x07, + 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x14, 0xf5, 0x08, 0xef, 0xf0, 0x7f, 0x91, 0x63, 0x10, 0x85, 0x08, + 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xf6, 0x63, 0x94, 0xa7, 0x04, 0x03, 0x24, 0x81, 0x10, + 0x83, 0x20, 0xc1, 0x10, 0x83, 0x24, 0x41, 0x10, 0x51, 0x61, 0x6f, 0xf0, 0x7f, 0xee, 0xef, 0xf0, + 0xbf, 0x97, 0x81, 0x44, 0x63, 0x14, 0x85, 0x00, 0x93, 0x04, 0xc0, 0x07, 0xef, 0xf0, 0x5f, 0x98, + 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0xdd, 0xd4, 0x0a, 0x85, 0x23, 0x00, 0x91, 0x00, + 0xa3, 0x00, 0x01, 0x00, 0xef, 0xf0, 0x5f, 0xe3, 0x79, 0xbf, 0x93, 0x04, 0xc0, 0x07, 0xf5, 0xb7, + 0xfa, 0x95, 0xdb, 0x48, 0x6d, 0x01, 0xaa, 0x0e, 0x83, 0xe5, 0x77, 0x95, 0xb2, 0x83, 0x53, 0x78, + 0x3d, 0x9d, 0xff, 0xf9, 0xf5, 0xac, 0x28, 0xc6, 0x1f, 0xd6, 0xd3, 0xe6, 0x71, 0x0e, 0x17, 0xdb, + 0xc3, 0xb8, 0x2c, 0xb7, 0x35, 0x20, 0x00, 0x83, 0xc7, 0x45, 0xb9, 0x95, 0xc3, 0x03, 0x24, 0x81, + 0x10, 0x83, 0x20, 0xc1, 0x10, 0x83, 0x24, 0x41, 0x10, 0x37, 0x35, 0x20, 0x00, 0x13, 0x06, 0xe0, + 0x0f, 0x93, 0x85, 0x45, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0x51, 0x61, 0x6f, 0x20, 0x30, 0x2a, 0x83, + 0x20, 0xc1, 0x10, 0x03, 0x24, 0x81, 0x10, 0x83, 0x24, 0x41, 0x10, 0x51, 0x61, 0x82, 0x80, 0xb7, + 0x07, 0x01, 0x04, 0x23, 0xa2, 0x07, 0x00, 0x21, 0x65, 0x6f, 0x20, 0xc0, 0x1c, 0x41, 0x11, 0x21, + 0x65, 0x06, 0xc6, 0xef, 0x20, 0x60, 0x1b, 0xb2, 0x40, 0xb7, 0x07, 0x01, 0x04, 0x05, 0x47, 0xd8, + 0xc3, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x07, 0x70, + 0x02, 0x2a, 0x84, 0xae, 0x84, 0x63, 0xf4, 0xa7, 0x00, 0xef, 0xd0, 0xff, 0xf4, 0x37, 0x05, 0x01, + 0x04, 0x0a, 0x04, 0x13, 0x05, 0x05, 0x10, 0x2a, 0x94, 0x04, 0xc0, 0xb2, 0x40, 0x22, 0x44, 0x92, + 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x13, 0x87, 0x07, 0x10, 0x93, 0x87, 0x07, + 0x1a, 0x23, 0x20, 0x07, 0x00, 0x11, 0x07, 0xe3, 0x1d, 0xf7, 0xfe, 0x82, 0x80, 0xb7, 0x07, 0x01, + 0x04, 0xc8, 0xcb, 0x82, 0x80, 0x42, 0x05, 0xb7, 0x07, 0x01, 0x04, 0xc8, 0xcb, 0x82, 0x80, 0xb7, + 0x07, 0x01, 0x04, 0x88, 0x4b, 0x13, 0x75, 0xf5, 0x0f, 0x82, 0x80, 0x89, 0x67, 0x37, 0x07, 0x01, + 0x04, 0x8d, 0x07, 0x1c, 0xc7, 0x23, 0x2a, 0x07, 0x00, 0x82, 0x80, 0xfa, 0x4c, 0x04, 0x05, 0x12, + 0x0c, 0x74, 0xdd, 0x85, 0x01, 0x4f, 0x18, 0x97, 0x4d, 0x7d, 0xa9, 0x14, 0xf5, 0x47, 0x44, 0x40, + 0x40, 0xba, 0x6f, 0x07, 0xab, 0x90, 0xf1, 0xf2, 0x29, 0x30, 0x11, 0x5c, 0x90, 0x2d, 0x41, 0x11, + 0x06, 0xc6, 0x22, 0xc4, 0x2a, 0x84, 0xad, 0x37, 0xb7, 0x07, 0x01, 0x04, 0x80, 0xcf, 0xc5, 0x37, + 0x65, 0x37, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0xa9, 0xb7, 0xb7, 0x06, 0x01, 0x04, 0x9c, 0x46, + 0x05, 0x45, 0x13, 0xf7, 0x17, 0x00, 0x1d, 0xc7, 0x13, 0xf7, 0x07, 0x40, 0x0d, 0x45, 0x1d, 0xe3, + 0x98, 0x4a, 0x13, 0x77, 0xf7, 0x0f, 0x19, 0xcf, 0x13, 0xf7, 0x27, 0x20, 0x09, 0x45, 0x19, 0xeb, + 0x13, 0xd7, 0xb7, 0x00, 0x05, 0x8b, 0x11, 0x45, 0x11, 0xe7, 0x13, 0xd5, 0x87, 0x00, 0x13, 0x45, + 0x15, 0x00, 0x05, 0x89, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x88, 0xcf, 0x82, 0x80, 0x01, 0x11, + 0x22, 0xcc, 0x06, 0xce, 0x33, 0x07, 0xb6, 0x00, 0x93, 0x07, 0x00, 0x09, 0x2e, 0x84, 0x63, 0xf8, + 0xe7, 0x00, 0x32, 0xc6, 0x2a, 0xc4, 0xef, 0xd0, 0x5f, 0xe7, 0x32, 0x46, 0x22, 0x45, 0xb7, 0x15, + 0x01, 0x04, 0xa2, 0x95, 0xef, 0xf0, 0xdf, 0xbb, 0xf2, 0x40, 0x62, 0x44, 0x13, 0x05, 0xa0, 0x0a, + 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, 0x26, 0xca, 0x06, 0xce, 0x33, 0x07, 0xb6, 0x00, + 0x93, 0x07, 0x00, 0x08, 0xaa, 0x84, 0x2e, 0x84, 0x63, 0xf6, 0xe7, 0x00, 0x32, 0xc6, 0xef, 0xd0, + 0xdf, 0xe3, 0x32, 0x46, 0x37, 0x25, 0x01, 0x04, 0x13, 0x05, 0x05, 0x80, 0x22, 0x95, 0x62, 0x44, + 0xf2, 0x40, 0xa6, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x6f, 0xf0, 0x5f, 0xbe, 0x39, 0x71, 0x2a, 0xd6, + 0x2e, 0xd4, 0x32, 0xd2, 0xb7, 0x55, 0xfa, 0x05, 0x46, 0x85, 0x81, 0x50, 0x32, 0xe0, 0x11, 0xb7, + 0x79, 0xe8, 0xb6, 0xf6, 0x15, 0x1e, 0xad, 0xe0, 0x41, 0x05, 0x0e, 0x83, 0xba, 0xde, 0x42, 0x1b, + 0x6d, 0x61, 0xe6, 0xcf, 0x8d, 0x9f, 0x14, 0x68, 0x2e, 0x10, 0x00, 0x37, 0x56, 0x10, 0x00, 0x37, + 0x55, 0x10, 0x00, 0x13, 0x06, 0x06, 0x68, 0x93, 0x85, 0x05, 0x69, 0x13, 0x05, 0x45, 0x69, 0x06, + 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, + 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xf0, 0xcf, 0xc5, 0xef, 0xe0, 0xcf, + 0xc8, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, + 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, + 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x09, 0x65, 0x6f, 0x10, 0x70, 0x7f, 0x09, 0x65, 0x6f, + 0x10, 0xd0, 0x7f, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xd0, 0x1f, + 0xda, 0xdd, 0x37, 0xb7, 0x07, 0x00, 0x07, 0x83, 0x46, 0x14, 0x00, 0xd8, 0x43, 0x83, 0x47, 0x04, + 0x00, 0xa2, 0x06, 0xdd, 0x8e, 0x83, 0x47, 0x24, 0x00, 0xc2, 0x07, 0xdd, 0x8e, 0x83, 0x47, 0x34, + 0x00, 0xe2, 0x07, 0xd5, 0x8f, 0x93, 0x06, 0xf0, 0x0f, 0x63, 0x85, 0xd7, 0x00, 0x61, 0x9b, 0x9d, + 0x8b, 0x5d, 0x8f, 0x93, 0x77, 0x77, 0xff, 0x03, 0x47, 0x44, 0x00, 0x83, 0x46, 0x94, 0x00, 0xb2, + 0x40, 0x0e, 0x07, 0x21, 0x8b, 0x5d, 0x8f, 0xfd, 0x77, 0xbd, 0x07, 0x7d, 0x8f, 0x83, 0x47, 0x54, + 0x00, 0x92, 0x07, 0x5d, 0x8f, 0xb7, 0x17, 0x80, 0xff, 0xfd, 0x17, 0x7d, 0x8f, 0x83, 0x47, 0xa4, + 0x00, 0xfa, 0x14, 0x86, 0xe1, 0xa4, 0x5c, 0x00, 0xa3, 0x9c, 0xfa, 0xe2, 0x50, 0x11, 0x30, 0x19, + 0xab, 0x38, 0x6f, 0x70, 0x36, 0x0a, 0xe3, 0x2b, 0x82, 0xf0, 0x4a, 0x07, 0xc7, 0x12, 0x67, 0x80, + 0x21, 0x10, 0x40, 0x2f, 0xa2, 0x07, 0xd5, 0x8f, 0xb2, 0x07, 0xb7, 0xf6, 0x7f, 0x00, 0xf5, 0x8f, + 0xd9, 0x8f, 0x37, 0x07, 0x80, 0xf8, 0x7d, 0x17, 0xf9, 0x8f, 0x03, 0x47, 0x74, 0x00, 0xb7, 0x06, + 0x80, 0x07, 0x5e, 0x07, 0x75, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x00, 0x88, 0x7d, 0x17, 0xf9, 0x8f, + 0x03, 0x47, 0x64, 0x00, 0xb7, 0x06, 0x00, 0x78, 0x22, 0x44, 0x6e, 0x07, 0x75, 0x8f, 0xd9, 0x8f, + 0x37, 0x07, 0x00, 0x07, 0x5c, 0xc3, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, + 0x87, 0xf7, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x13, 0x05, 0xa0, 0x0a, + 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, + 0xc7, 0x20, 0x13, 0x05, 0xa0, 0x0a, 0x89, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, + 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x65, 0xba, 0x6f, 0xf0, + 0xbf, 0x8c, 0x41, 0x11, 0xb7, 0x07, 0x08, 0x05, 0x22, 0xc4, 0x03, 0xa4, 0xc7, 0x20, 0x37, 0x07, + 0x00, 0x04, 0x06, 0xc6, 0x26, 0xc2, 0xb3, 0x76, 0xe4, 0x00, 0x91, 0xca, 0x37, 0x55, 0x10, 0x00, + 0x23, 0xa6, 0xe7, 0x20, 0xa5, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xf0, 0x4f, 0xb7, 0xb7, 0x07, + 0x80, 0x6b, 0xe1, 0x8f, 0x95, 0xcb, 0x37, 0x07, 0x08, 0x05, 0x23, 0x26, 0xf7, 0x20, 0xb7, 0x07, + 0x00, 0x68, 0x7d, 0x8c, 0x93, 0x04, 0x50, 0x05, 0x11, 0xc8, 0x37, 0x55, 0xfa, 0x8e, 0xf5, 0x52, + 0x1f, 0x6e, 0xfd, 0x26, 0x25, 0xc2, 0xba, 0x74, 0xa9, 0x51, 0x70, 0xbe, 0xd3, 0xd4, 0xad, 0xde, + 0x05, 0x25, 0xd6, 0x75, 0xec, 0xb0, 0x8f, 0x31, 0xb7, 0x3c, 0xf7, 0x02, 0xf8, 0x18, 0x30, 0x10, + 0x00, 0x9d, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xf0, 0xaf, 0xb4, 0xef, 0xd0, 0x9f, 0xc5, 0xb2, + 0x40, 0x22, 0x44, 0x26, 0x85, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x93, + 0x87, 0xc7, 0xf7, 0x84, 0x43, 0x13, 0x07, 0xa0, 0x0a, 0x63, 0x96, 0xe4, 0x00, 0x13, 0x07, 0x50, + 0x05, 0x98, 0xc3, 0xe1, 0xbf, 0x93, 0x04, 0xa0, 0x0a, 0xd9, 0xbf, 0x81, 0x47, 0xb7, 0x05, 0x08, + 0x05, 0x13, 0x07, 0x00, 0x20, 0xb3, 0x86, 0xb7, 0x00, 0x90, 0x42, 0xb3, 0x06, 0xf5, 0x00, 0x91, + 0x07, 0x90, 0xc2, 0xe3, 0x99, 0xe7, 0xfe, 0x6f, 0xf0, 0xff, 0xf5, 0x41, 0x11, 0x06, 0xc6, 0x22, + 0xc4, 0x2a, 0x84, 0xef, 0xf0, 0x1f, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, + 0xac, 0xe7, 0xf6, 0x8d, 0x47, 0x33, 0x95, 0x87, 0x00, 0xb7, 0xb7, 0xaa, 0x02, 0x93, 0x87, 0xa7, + 0xaa, 0x3d, 0x8d, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xa4, 0xa7, 0x20, 0x89, 0x65, 0x37, 0x35, 0x10, + 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x65, 0xb8, 0xef, 0xf0, 0x2f, 0xfe, 0x22, 0x44, 0xb2, + 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0xf1, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x9f, 0xef, 0xb7, + 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf7, 0x37, 0x07, 0x08, 0x05, 0x13, 0x05, 0x00, 0x20, 0xf9, + 0x9b, 0x23, 0x22, 0xf7, 0x20, 0xef, 0x10, 0xd0, 0x5e, 0xb2, 0x40, 0x39, 0x45, 0x41, 0x01, 0x6f, + 0x10, 0xf0, 0x5f, 0x37, 0x37, 0x20, 0x00, 0xfa, 0x56, 0x84, 0x51, 0x84, 0x21, 0x1f, 0x67, 0xc3, + 0x25, 0x4a, 0x29, 0x3f, 0x5d, 0x30, 0x2c, 0x3c, 0x48, 0x9c, 0xb8, 0x81, 0x37, 0x43, 0x96, 0x5a, + 0x4d, 0x5f, 0x88, 0x65, 0xd0, 0xee, 0x8f, 0x91, 0xf0, 0x30, 0x13, 0x07, 0x47, 0xf7, 0x1c, 0x43, + 0x93, 0xf7, 0xf7, 0xfd, 0x1c, 0xc3, 0x37, 0x07, 0x08, 0x05, 0x23, 0x22, 0xf7, 0x20, 0x82, 0x80, + 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf7, 0x1c, 0x43, 0x93, 0xe7, 0x07, 0x02, 0x1c, 0xc3, + 0x37, 0x07, 0x08, 0x05, 0x23, 0x22, 0xf7, 0x20, 0x82, 0x80, 0x33, 0x87, 0xc5, 0x00, 0xb7, 0x07, + 0x08, 0x00, 0x63, 0x7c, 0xf7, 0x06, 0x01, 0x11, 0x22, 0xcc, 0x26, 0xca, 0x4e, 0xc6, 0x06, 0xce, + 0x4a, 0xc8, 0x93, 0xf4, 0x35, 0x00, 0xaa, 0x89, 0x2e, 0x84, 0x13, 0x05, 0x50, 0x05, 0x9d, 0xec, + 0x32, 0x89, 0xef, 0xf0, 0x5f, 0xe7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x47, 0xf7, 0xb7, 0x06, + 0x08, 0x05, 0xb7, 0x05, 0x00, 0x05, 0x13, 0x67, 0x27, 0x00, 0x23, 0xa2, 0xe6, 0x20, 0x93, 0x87, + 0x47, 0xf7, 0x0d, 0x47, 0x2e, 0x94, 0xb3, 0x06, 0x99, 0x40, 0x63, 0x60, 0xd7, 0x02, 0x98, 0x43, + 0xb7, 0x07, 0x08, 0x05, 0x13, 0x05, 0xa0, 0x0a, 0x23, 0xa2, 0xe7, 0x20, 0xf2, 0x40, 0x62, 0x44, + 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, 0xb3, 0x06, 0x94, 0x00, 0x90, 0x42, + 0xb3, 0x86, 0x99, 0x00, 0x91, 0x04, 0x90, 0xc2, 0xf9, 0xb7, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, + 0x01, 0x11, 0xaa, 0x85, 0x11, 0x46, 0x68, 0x00, 0x06, 0xce, 0xef, 0xf0, 0x1f, 0xf7, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x00, 0x32, 0x45, 0xf2, 0x40, 0x05, 0x61, 0x82, 0x80, 0x01, 0x45, + 0xe5, 0xbf, 0xfa, 0x8e, 0xa8, 0x4b, 0x5c, 0xb4, 0xcb, 0x70, 0xf2, 0x84, 0x9d, 0x29, 0xc9, 0xe7, + 0x05, 0x7b, 0xe9, 0xa3, 0x1a, 0x9e, 0xc2, 0xd8, 0x3d, 0x17, 0x2e, 0x4e, 0x49, 0xa8, 0x58, 0x67, + 0x53, 0x3d, 0x30, 0xc8, 0x31, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xef, 0xa7, 0x02, 0x41, 0x11, 0x22, + 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x8d, 0xe3, 0xae, 0x84, 0xef, + 0xf0, 0xbf, 0xdd, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x22, 0x44, 0xb2, 0x40, 0x23, + 0xaa, 0x97, 0x20, 0x92, 0x44, 0x01, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x9f, 0xe7, 0xb2, 0x40, 0x22, + 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, + 0xc6, 0xaa, 0x84, 0x2e, 0x84, 0x45, 0x3f, 0x26, 0x85, 0xef, 0xf0, 0xbf, 0xf8, 0x63, 0x09, 0x85, + 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, + 0x05, 0xa0, 0x0a, 0xcd, 0xbf, 0x01, 0x11, 0x22, 0xcc, 0x2e, 0xc6, 0x06, 0xce, 0x2a, 0x84, 0xef, + 0xf0, 0x5f, 0xf6, 0xb2, 0x45, 0x63, 0x03, 0xb5, 0x02, 0xfd, 0x57, 0x63, 0x1a, 0xf5, 0x00, 0x63, + 0x8e, 0xa5, 0x00, 0x22, 0x85, 0x62, 0x44, 0xf2, 0x40, 0x05, 0x61, 0x6f, 0xf0, 0xff, 0xfa, 0x13, + 0x05, 0x50, 0x05, 0xf2, 0x40, 0x62, 0x44, 0x05, 0x61, 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xd5, + 0xbf, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe0, 0xb7, 0x04, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, + 0xc6, 0x93, 0xf7, 0xf5, 0x1f, 0xaa, 0x84, 0x2e, 0x84, 0x13, 0x05, 0x50, 0x05, 0x99, 0xef, 0xef, + 0xf0, 0xbf, 0xd2, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x39, 0x45, 0xfa, 0xae, 0x12, + 0x6b, 0xf5, 0x7c, 0xf1, 0x60, 0xfb, 0x50, 0x98, 0xd0, 0xcd, 0x92, 0x00, 0x69, 0xd6, 0x9f, 0x11, + 0xa4, 0x60, 0xdd, 0xc9, 0x37, 0x27, 0x2a, 0x0b, 0x62, 0x16, 0x8f, 0x8d, 0x5f, 0x4f, 0xa0, 0x32, + 0xef, 0xf0, 0x5f, 0xdd, 0x26, 0x85, 0xef, 0xf0, 0xff, 0xda, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, + 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, + 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xfb, + 0xb7, 0x00, 0x81, 0x44, 0xf2, 0x40, 0x62, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x26, 0x85, 0xd2, 0x44, + 0x05, 0x61, 0x82, 0x80, 0x93, 0xf4, 0xf5, 0x1f, 0x2e, 0x84, 0xe5, 0xf4, 0x2a, 0x89, 0xef, 0xf0, + 0xff, 0xcc, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x41, 0x45, 0xef, 0xf0, 0x9f, 0xd7, + 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x17, 0xf5, 0xfc, 0x37, 0x34, 0x20, 0x00, 0x13, 0x05, 0x44, 0xc9, + 0xef, 0xf0, 0x5f, 0xd4, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x87, 0x07, 0x20, 0x23, 0xa0, 0x07, 0x00, + 0x91, 0x07, 0xe3, 0x9d, 0xe7, 0xfe, 0x93, 0x09, 0x44, 0xc9, 0x03, 0xd6, 0xc9, 0x1f, 0x93, 0x07, + 0xc0, 0x1d, 0x63, 0xfa, 0xc7, 0x00, 0x37, 0x55, 0x10, 0x00, 0x99, 0x45, 0x13, 0x05, 0x85, 0x69, + 0xef, 0xf0, 0xaf, 0x82, 0x41, 0xbf, 0x93, 0x05, 0x44, 0xc9, 0x4a, 0x85, 0xef, 0x20, 0x60, 0x43, + 0x83, 0xd4, 0xc9, 0x1f, 0x41, 0xb7, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe7, 0xa7, 0x04, 0x41, 0x11, + 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x13, 0x05, 0x50, 0x05, + 0x9d, 0xe7, 0xef, 0xf0, 0xbf, 0xc4, 0x85, 0x67, 0xfa, 0x98, 0x7d, 0xd6, 0xbd, 0x4c, 0x7f, 0x66, + 0x14, 0x0e, 0xb7, 0xd3, 0x03, 0xf0, 0x61, 0x38, 0x62, 0xac, 0xd9, 0xe6, 0xe0, 0x22, 0xb7, 0xe4, + 0xf6, 0xaf, 0x7e, 0x60, 0x65, 0x80, 0xf6, 0x02, 0xfe, 0x78, 0x33, 0xb7, 0x04, 0x08, 0x05, 0x93, + 0x87, 0x97, 0x82, 0x23, 0xa2, 0xf4, 0x20, 0x23, 0xac, 0x84, 0x20, 0x39, 0x45, 0xef, 0xf0, 0xbf, + 0xce, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf7, 0x13, 0x05, 0xa0, 0x0a, 0x23, 0xa2, 0xf4, + 0x20, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, + 0x80, 0x0d, 0x65, 0x01, 0x11, 0x13, 0x05, 0x05, 0x20, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, + 0xc8, 0x4e, 0xc6, 0xef, 0x10, 0xf0, 0x2f, 0x39, 0x45, 0xef, 0x10, 0x50, 0x31, 0x13, 0x05, 0x80, + 0x07, 0x37, 0x39, 0x20, 0x00, 0xef, 0xf0, 0x6f, 0xb9, 0x93, 0x09, 0x49, 0xf7, 0x83, 0xa7, 0x09, + 0x00, 0x37, 0x04, 0x08, 0x05, 0x93, 0x04, 0x04, 0x20, 0xdc, 0xc0, 0xb7, 0x07, 0x46, 0x00, 0x85, + 0x07, 0xdc, 0xcc, 0x85, 0x67, 0x93, 0x87, 0x57, 0x86, 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, 0xdc, + 0xc0, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x05, 0xb9, 0xef, 0xf0, 0xef, 0xc8, 0xb7, 0x07, 0x40, + 0x08, 0x9c, 0xc8, 0xdc, 0x40, 0x01, 0x45, 0x13, 0x09, 0x49, 0xf7, 0x93, 0xe7, 0x07, 0x18, 0x23, + 0xa0, 0xf9, 0x00, 0xef, 0xf0, 0x7f, 0xf3, 0x93, 0x07, 0x04, 0x10, 0x98, 0x43, 0xb7, 0x67, 0xa5, + 0xf0, 0x93, 0x87, 0xf7, 0xa0, 0x63, 0x05, 0xf7, 0x02, 0x37, 0x55, 0x10, 0x00, 0x95, 0x45, 0x13, + 0x05, 0x85, 0x69, 0xef, 0xe0, 0xbf, 0xf2, 0x41, 0x67, 0x7d, 0x17, 0x93, 0x07, 0x04, 0x18, 0xb8, + 0xd3, 0xf8, 0xd3, 0xfa, 0xb8, 0x2d, 0x0d, 0x74, 0xa2, 0xc0, 0x13, 0xb8, 0xfa, 0x03, 0x40, 0xaa, + 0x55, 0xc0, 0x46, 0x6a, 0x1e, 0xf3, 0x5f, 0x4c, 0xdf, 0xdd, 0x3d, 0x0a, 0x63, 0x3f, 0xb9, 0x91, + 0xb9, 0x15, 0x6f, 0xb0, 0x50, 0x34, 0xb8, 0xd7, 0xf8, 0xd7, 0xb8, 0xdb, 0xf8, 0xdb, 0xb8, 0xdf, + 0xf8, 0xdf, 0x51, 0x45, 0xef, 0xf0, 0x7f, 0xc1, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, + 0x91, 0x8b, 0x91, 0xeb, 0x37, 0x55, 0x10, 0x00, 0x91, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, + 0x3f, 0xef, 0xef, 0xd0, 0x1f, 0x80, 0xb7, 0x07, 0x08, 0x05, 0x37, 0x07, 0x40, 0x00, 0x23, 0xa6, + 0xe7, 0x20, 0x03, 0x27, 0x09, 0x00, 0xf2, 0x40, 0x62, 0x44, 0x23, 0xa2, 0xe7, 0x20, 0xd2, 0x44, + 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, 0x85, 0x67, 0x37, 0x37, 0x20, 0x00, 0x93, 0x87, + 0x47, 0x86, 0x23, 0x2a, 0xf7, 0xf6, 0x37, 0x37, 0x20, 0x00, 0x93, 0x07, 0x50, 0x05, 0x23, 0x2c, + 0xf7, 0xf6, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2e, 0xf7, 0xf6, 0x6f, 0xf0, 0xbf, 0xee, 0xb7, 0x07, + 0x08, 0x00, 0x63, 0xe0, 0xa7, 0x06, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xc6, + 0x26, 0xc2, 0x2a, 0x84, 0x13, 0x05, 0x50, 0x05, 0xa1, 0xe3, 0xae, 0x84, 0xef, 0xf0, 0x7f, 0xad, + 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x01, 0x47, 0x93, 0x06, 0x00, 0x20, 0xb3, 0x85, + 0xe4, 0x00, 0x8c, 0x41, 0x33, 0x06, 0xf7, 0x00, 0x11, 0x07, 0x0c, 0xc2, 0xe3, 0x19, 0xd7, 0xfe, + 0x7d, 0x57, 0x93, 0x87, 0x07, 0x20, 0xf8, 0xc3, 0xb8, 0xc7, 0xf8, 0xc7, 0xb8, 0xcb, 0x29, 0x45, + 0xef, 0xf0, 0xbf, 0xb5, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0xfa, 0x43, + 0xf3, 0xa6, 0x53, 0xa0, 0x13, 0x87, 0x84, 0x9f, 0x78, 0x47, 0x6a, 0xd0, 0x5b, 0xd2, 0x61, 0x1c, + 0xd3, 0xd9, 0x55, 0xd8, 0xc8, 0xf5, 0x70, 0xce, 0x63, 0xde, 0x2e, 0xe9, 0xbe, 0x7b, 0x84, 0x28, + 0x35, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xaa, 0x85, 0x37, 0x05, 0x08, + 0x05, 0x41, 0x46, 0x13, 0x05, 0x05, 0x26, 0x6f, 0xf0, 0x0f, 0xd0, 0xb7, 0x07, 0x08, 0x00, 0x63, + 0xef, 0xa7, 0x0a, 0x01, 0x11, 0x26, 0xca, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xce, 0x22, 0xcc, 0x4a, + 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x56, 0xc2, 0xaa, 0x84, 0x13, 0x05, 0x50, 0x05, 0xd9, 0xe7, 0x93, + 0x07, 0xc0, 0x1d, 0x32, 0x89, 0x63, 0xe3, 0xc7, 0x08, 0xb6, 0x89, 0x37, 0x34, 0x20, 0x00, 0x2e, + 0x8a, 0xef, 0xf0, 0x5f, 0xa4, 0x13, 0x06, 0x00, 0x20, 0x81, 0x45, 0x13, 0x05, 0x44, 0xc9, 0xef, + 0x20, 0x80, 0x23, 0x4a, 0x86, 0xd2, 0x85, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x00, 0x1f, 0x4e, + 0x85, 0xef, 0xf0, 0xbf, 0xf9, 0x93, 0x0a, 0x44, 0xc9, 0xb7, 0x07, 0x08, 0x05, 0x23, 0x9e, 0x2a, + 0x1f, 0x13, 0x07, 0x44, 0xc9, 0x93, 0x86, 0x07, 0x20, 0x10, 0x43, 0x11, 0x07, 0x90, 0xc3, 0x91, + 0x07, 0xe3, 0x9c, 0xd7, 0xfe, 0x13, 0x06, 0x00, 0x20, 0x81, 0x45, 0x13, 0x05, 0x44, 0xc9, 0xef, + 0x20, 0x80, 0x1f, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x97, 0x20, 0x31, 0x45, 0xef, 0xf0, 0x1f, + 0xaa, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, + 0x69, 0x8d, 0x45, 0xef, 0xe0, 0x1f, 0xd8, 0x13, 0x05, 0x50, 0x05, 0xf2, 0x40, 0x62, 0x44, 0xd2, + 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0xfa, 0x17, 0x92, 0xcc, 0xb6, 0x56, 0x95, + 0x0c, 0xe8, 0xd7, 0xe2, 0x7d, 0x65, 0x79, 0xc1, 0x8c, 0x55, 0xb2, 0x5f, 0x86, 0xc8, 0xce, 0x43, + 0xf4, 0x79, 0xaf, 0x8f, 0x0a, 0x93, 0x35, 0x6b, 0x86, 0x32, 0x00, 0x36, 0x05, 0x61, 0x82, 0x80, + 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xeb, 0xa7, 0x02, 0x41, 0x11, + 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0xf5, 0x1f, 0x2a, 0x84, 0x89, 0xef, 0xef, 0xf0, 0xdf, 0x99, + 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x22, 0x44, 0xb2, 0x40, 0x21, 0x45, 0x41, 0x01, + 0x6f, 0xf0, 0x1f, 0xa4, 0xb2, 0x40, 0x22, 0x44, 0x13, 0x05, 0x50, 0x05, 0x41, 0x01, 0x82, 0x80, + 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x37, 0x04, 0x08, 0x05, + 0x23, 0x2c, 0xa4, 0x20, 0xef, 0xf0, 0x5f, 0x96, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, + 0x23, 0xac, 0xe7, 0xf6, 0xb7, 0xb7, 0xaa, 0x02, 0x93, 0x87, 0x67, 0xaa, 0xb2, 0x40, 0x23, 0x24, + 0xf4, 0x20, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xdf, 0x93, + 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf6, 0xb2, 0x40, 0xb7, 0xb7, + 0xa6, 0x02, 0x37, 0x07, 0x08, 0x05, 0x93, 0x87, 0xa7, 0xaa, 0x23, 0x24, 0xf7, 0x20, 0x41, 0x01, + 0x82, 0x80, 0x39, 0x71, 0x3e, 0xcc, 0xb7, 0x07, 0x08, 0x05, 0x3a, 0xce, 0x03, 0xa7, 0xc7, 0x20, + 0x36, 0xd0, 0xb7, 0x06, 0x40, 0x00, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, + 0x2e, 0xd4, 0x32, 0xd2, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, + 0x75, 0x8f, 0x05, 0xcf, 0xfa, 0xb4, 0x26, 0x29, 0xb7, 0xc2, 0x32, 0xd8, 0x10, 0x6c, 0x29, 0xef, + 0x4e, 0x89, 0x8c, 0x15, 0xb9, 0x60, 0xc4, 0x98, 0x16, 0x49, 0xb8, 0xf8, 0x21, 0x0c, 0xd1, 0x85, + 0x81, 0xaf, 0x32, 0xda, 0xcc, 0xd8, 0x36, 0x23, 0xa6, 0xd7, 0x20, 0x13, 0x07, 0xa0, 0x0a, 0xb7, + 0x37, 0x20, 0x00, 0x23, 0xac, 0xe7, 0xf6, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, + 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, + 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x03, 0xa7, 0xc7, + 0x20, 0xb7, 0x06, 0x00, 0x08, 0x37, 0x55, 0x10, 0x00, 0x75, 0x8f, 0x0d, 0xc3, 0x23, 0xa6, 0xd7, + 0x20, 0x85, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, 0x3f, 0xc4, 0xb7, 0x37, 0x20, 0x00, 0x13, + 0x07, 0xa0, 0x0a, 0x23, 0xae, 0xe7, 0xf6, 0xef, 0xd0, 0x1f, 0xbf, 0x75, 0xb7, 0x89, 0x45, 0x13, + 0x05, 0x85, 0x69, 0xef, 0xe0, 0x7f, 0xc2, 0xb7, 0x07, 0x02, 0x00, 0x73, 0xb0, 0x47, 0x30, 0xe5, + 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa0, 0xe7, 0xf8, 0x82, 0x80, 0x99, + 0x47, 0x63, 0x05, 0xf5, 0x02, 0x9d, 0x47, 0x63, 0x0b, 0xf5, 0x00, 0x95, 0x47, 0x63, 0x15, 0xf5, + 0x02, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xf7, 0xf7, 0xf7, 0x29, 0xa8, 0xb7, 0x37, 0x20, + 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa0, 0xe7, 0xf8, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x7c, + 0x43, 0x93, 0xe7, 0x07, 0x08, 0x7c, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, + 0xf8, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, 0xf7, 0x00, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0xfa, + 0x1d, 0xef, 0x8a, 0xc6, 0xb0, 0x1e, 0x0d, 0x22, 0xa7, 0x33, 0x28, 0x0d, 0x25, 0xf1, 0x25, 0x22, + 0x9a, 0xaf, 0xa1, 0x7e, 0x90, 0xba, 0x18, 0xb0, 0xf7, 0x2c, 0xbf, 0x7b, 0x9e, 0x3a, 0x52, 0x76, + 0xb0, 0x37, 0x93, 0xe7, 0x07, 0x08, 0x7c, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, + 0x07, 0xf8, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, 0xf7, 0x00, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, + 0x93, 0xf7, 0xf7, 0xf7, 0x7c, 0xc3, 0x82, 0x80, 0x39, 0x71, 0x2a, 0xd6, 0x37, 0x55, 0x10, 0x00, + 0x2e, 0xd4, 0x13, 0x05, 0xc5, 0x69, 0x85, 0x45, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, + 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, + 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0x9f, 0xb6, 0xef, 0xd0, 0x3f, 0xb2, 0xf2, 0x50, 0xe2, 0x52, + 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, + 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, + 0x20, 0x30, 0x39, 0x71, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, + 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, + 0x7a, 0xc2, 0x7e, 0xc0, 0xf3, 0x25, 0x20, 0x34, 0xc1, 0x67, 0x37, 0x55, 0x10, 0x00, 0xdd, 0x8d, + 0x13, 0x05, 0xc5, 0x69, 0xef, 0xe0, 0x9f, 0xb0, 0xef, 0xd0, 0x3f, 0xac, 0x01, 0xa0, 0x39, 0x71, + 0x2a, 0xd6, 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, 0x13, 0x05, 0xc5, 0x69, 0x89, 0x45, 0x06, 0xde, + 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, 0x36, 0xd0, 0xfa, 0x58, 0xb2, 0xe1, 0xe7, 0x50, + 0x6e, 0xd5, 0xd4, 0x3a, 0xdc, 0x7d, 0x80, 0x37, 0xd2, 0x06, 0xea, 0xb3, 0x35, 0xb0, 0x7e, 0xef, + 0x45, 0x2f, 0x2c, 0x3e, 0xd9, 0x53, 0x37, 0x57, 0x19, 0x76, 0x9c, 0x88, 0x38, 0x3a, 0xce, 0x3e, + 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0x3f, + 0xad, 0xef, 0xd0, 0xdf, 0xa8, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, + 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, + 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x07, 0x01, 0x01, 0xb7, + 0x07, 0x00, 0x01, 0x13, 0x07, 0x17, 0x10, 0x98, 0xd3, 0x37, 0x07, 0x03, 0x04, 0x09, 0x07, 0xd8, + 0xd3, 0x13, 0x07, 0x50, 0x60, 0x98, 0xd7, 0x37, 0x17, 0x09, 0x00, 0x13, 0x07, 0x77, 0x80, 0xd8, + 0xd7, 0x37, 0x17, 0x0b, 0x0b, 0x13, 0x07, 0xa7, 0xa0, 0x98, 0xdb, 0x37, 0x17, 0x0c, 0x00, 0x13, + 0x07, 0xb7, 0xc0, 0xd8, 0xdb, 0x37, 0x17, 0x0f, 0x00, 0x13, 0x07, 0xd7, 0xe0, 0x98, 0xdf, 0x05, + 0x67, 0xd8, 0xdf, 0xb7, 0x17, 0xff, 0x7f, 0x93, 0x87, 0x07, 0x80, 0x73, 0xa0, 0x47, 0x30, 0xa1, + 0x47, 0x73, 0xa0, 0x07, 0x30, 0x82, 0x80, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x40, 0x00, 0x73, + 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x3e, 0xc6, 0xb7, + 0x07, 0x80, 0x00, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, + 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x00, 0x04, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, + 0x00, 0x20, 0x30, 0x41, 0x11, 0xfa, 0x8c, 0xa9, 0xb2, 0x78, 0xbc, 0xb3, 0x9a, 0x79, 0x97, 0xc2, + 0x73, 0xbf, 0xc4, 0x6b, 0x14, 0x89, 0xea, 0xf2, 0xba, 0x44, 0xaf, 0x2e, 0xeb, 0x9c, 0x1c, 0xd4, + 0x53, 0xda, 0x89, 0x57, 0xea, 0xcc, 0x60, 0x39, 0x3e, 0xc6, 0xb7, 0x07, 0x00, 0x20, 0x73, 0xb0, + 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x05, 0x65, 0x6f, 0x10, 0xa0, 0x54, + 0x05, 0x65, 0x6f, 0x10, 0x00, 0x55, 0x01, 0x11, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x06, 0xce, + 0x26, 0xca, 0x52, 0xc4, 0x56, 0xc2, 0x9d, 0x47, 0x2a, 0x84, 0xae, 0x89, 0x32, 0x89, 0x63, 0xd4, + 0xc7, 0x00, 0xef, 0xd0, 0x2f, 0xae, 0xef, 0xf0, 0x5f, 0xfd, 0xb7, 0x07, 0x01, 0x07, 0x18, 0x40, + 0xdc, 0x43, 0x93, 0x06, 0xf0, 0x0f, 0x63, 0x05, 0xd7, 0x00, 0xf1, 0x9b, 0x0d, 0x8b, 0xd9, 0x8f, + 0x13, 0xf7, 0xb7, 0xff, 0x83, 0x47, 0x44, 0x00, 0x81, 0x44, 0x31, 0x4a, 0x8a, 0x07, 0x91, 0x8b, + 0xd9, 0x8f, 0x37, 0x07, 0x01, 0x07, 0x5c, 0xc3, 0xb7, 0x1a, 0x01, 0x07, 0x63, 0xcf, 0x24, 0x03, + 0x14, 0x40, 0x05, 0x47, 0xad, 0x47, 0x63, 0x9e, 0xe6, 0x00, 0x83, 0x46, 0x44, 0x00, 0x13, 0x07, + 0xa0, 0x0a, 0xbd, 0x47, 0x63, 0x97, 0xe6, 0x00, 0x14, 0x44, 0x37, 0x37, 0x20, 0x00, 0x23, 0x22, + 0xd7, 0xf8, 0xf2, 0x40, 0x62, 0x44, 0x37, 0x07, 0x01, 0x07, 0x5c, 0xc7, 0xd2, 0x44, 0x42, 0x49, + 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xb3, 0x85, 0x44, 0x03, 0x13, 0x95, + 0x44, 0x00, 0x31, 0x46, 0x56, 0x95, 0x85, 0x04, 0xce, 0x95, 0xef, 0xf0, 0xcf, 0x81, 0x7d, 0xb7, + 0x1d, 0x71, 0x3e, 0xda, 0xb7, 0x07, 0x01, 0x07, 0xa2, 0xc6, 0x80, 0x47, 0x86, 0xce, 0x96, 0xcc, + 0xfa, 0xd3, 0x39, 0xdd, 0x0d, 0x4c, 0xcf, 0x07, 0x11, 0xa2, 0xf6, 0x29, 0x3f, 0xf1, 0x6d, 0x91, + 0x0d, 0x79, 0x86, 0x3c, 0xbd, 0xc5, 0x90, 0x68, 0xf7, 0xe3, 0xe8, 0x1a, 0x83, 0x65, 0x5c, 0x07, + 0x2c, 0x38, 0x3a, 0x9a, 0xca, 0x9e, 0xc8, 0xaa, 0xc4, 0xae, 0xc2, 0xb2, 0xc0, 0x36, 0xde, 0x3a, + 0xdc, 0x42, 0xd8, 0x46, 0xd6, 0x72, 0xd4, 0x76, 0xd2, 0x7a, 0xd0, 0x7e, 0xce, 0x93, 0x77, 0xb4, + 0x00, 0x95, 0xc7, 0xb7, 0x07, 0x00, 0x40, 0x73, 0xb0, 0x47, 0x30, 0x37, 0x56, 0x10, 0x00, 0xb7, + 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0xa2, 0x86, 0x13, 0x06, 0x06, 0x6a, 0x93, 0x85, 0x85, + 0x6a, 0x13, 0x05, 0x45, 0x64, 0xef, 0xe0, 0xbf, 0x87, 0xef, 0xd0, 0xbf, 0x8a, 0x93, 0x77, 0x44, + 0x00, 0x99, 0xcf, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf8, 0x91, 0xcb, 0x6c, 0x00, 0x28, + 0x00, 0x82, 0x97, 0x22, 0x47, 0xb7, 0x07, 0x01, 0x07, 0x98, 0xcb, 0x32, 0x47, 0xd8, 0xcb, 0xb7, + 0x07, 0x01, 0x07, 0x80, 0xc7, 0x36, 0x44, 0xf6, 0x40, 0xe6, 0x42, 0x56, 0x43, 0xc6, 0x43, 0x26, + 0x45, 0x96, 0x45, 0x06, 0x46, 0xf2, 0x56, 0x62, 0x57, 0xd2, 0x57, 0x42, 0x58, 0xb2, 0x58, 0x22, + 0x5e, 0x92, 0x5e, 0x02, 0x5f, 0xf2, 0x4f, 0x25, 0x61, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x07, 0x02, + 0x04, 0xdc, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, + 0x80, 0x13, 0x05, 0x00, 0x08, 0x6f, 0x10, 0x40, 0x3d, 0x13, 0x05, 0x00, 0x08, 0x6f, 0x10, 0x80, + 0x3d, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x07, 0xd0, 0x79, 0x37, 0x04, 0x02, + 0x04, 0x5c, 0xc4, 0x85, 0x44, 0x95, 0x65, 0x37, 0x35, 0x10, 0x00, 0xfa, 0x72, 0x97, 0x86, 0xd0, + 0xf1, 0x8f, 0x3b, 0x47, 0x1d, 0x7c, 0x3e, 0x8b, 0xc9, 0xc4, 0xa0, 0x20, 0x2e, 0x30, 0x23, 0x47, + 0x9a, 0x07, 0xeb, 0x76, 0x20, 0xd3, 0x0b, 0xdd, 0x58, 0xfa, 0x02, 0xfc, 0x10, 0x3b, 0x04, 0xc4, + 0x93, 0x85, 0x05, 0xe2, 0x13, 0x05, 0x25, 0x6d, 0xef, 0xe0, 0x7f, 0xca, 0x93, 0x07, 0xa0, 0x0a, + 0x63, 0x13, 0xf5, 0x02, 0x54, 0x44, 0x63, 0x82, 0x96, 0x02, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, + 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x6a, 0x93, 0x85, 0x45, 0x6b, 0x13, 0x05, + 0x05, 0x62, 0xef, 0xe0, 0x0f, 0xfb, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, + 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xdf, 0xf8, 0xb2, 0x40, 0xb7, 0x07, + 0x02, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x05, 0x45, 0x22, 0xc4, + 0x26, 0xc2, 0x06, 0xc6, 0xef, 0xe0, 0x3f, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, + 0x23, 0xa4, 0xe7, 0xf8, 0x89, 0x46, 0x37, 0x07, 0x02, 0x02, 0x54, 0xc7, 0x13, 0x84, 0x87, 0xf8, + 0x93, 0x04, 0x50, 0x05, 0xef, 0xe0, 0x9f, 0xc2, 0x1c, 0x40, 0xe3, 0x9d, 0x97, 0xfe, 0xb2, 0x40, + 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x02, 0x02, 0xc8, 0xcb, 0x05, 0x47, + 0xd8, 0xc7, 0xd8, 0x53, 0x69, 0x8f, 0x63, 0x1e, 0xa7, 0x00, 0xd4, 0x57, 0x7d, 0x55, 0xf9, 0x8e, + 0x91, 0xea, 0x94, 0x57, 0x75, 0x8f, 0x19, 0xe7, 0x88, 0x47, 0x05, 0x89, 0x33, 0x05, 0xa0, 0x40, + 0x82, 0x80, 0x7d, 0x55, 0x82, 0x80, 0x41, 0x45, 0x6f, 0x10, 0x00, 0x2f, 0x41, 0x45, 0x6f, 0x10, + 0xe0, 0x2d, 0x01, 0x11, 0x06, 0xce, 0xfa, 0x5a, 0xdb, 0x7a, 0x09, 0x77, 0x12, 0x81, 0xe8, 0xb1, + 0x79, 0x65, 0x13, 0xe5, 0xa8, 0xf7, 0xf6, 0x4e, 0xc5, 0xd0, 0x71, 0x6d, 0x9f, 0xd4, 0xc0, 0xa5, + 0x28, 0xb9, 0x29, 0x5d, 0x29, 0xe3, 0x7c, 0xe8, 0x3b, 0x22, 0xcc, 0x2a, 0xc6, 0xef, 0xf0, 0x3f, + 0xff, 0x13, 0x07, 0x50, 0x05, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0xe7, 0xf8, 0x37, 0x04, 0x02, + 0x02, 0xa1, 0x47, 0x5c, 0xc4, 0x32, 0x45, 0x85, 0x47, 0x1c, 0xc8, 0x93, 0x07, 0x10, 0x40, 0x5c, + 0xc0, 0xef, 0xf0, 0xbf, 0xf9, 0xef, 0xf0, 0x9f, 0xf5, 0x23, 0x22, 0x04, 0x00, 0x62, 0x44, 0xf2, + 0x40, 0x05, 0x61, 0x6f, 0xf0, 0x7f, 0xfb, 0x41, 0x11, 0x3a, 0xc6, 0x37, 0x07, 0x02, 0x02, 0x3e, + 0xc4, 0x1c, 0x47, 0x1c, 0xc7, 0x85, 0x8b, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, + 0x05, 0x23, 0xa4, 0xe7, 0xf8, 0x32, 0x47, 0xa2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0xb7, + 0x37, 0x20, 0x00, 0x03, 0xa5, 0xc7, 0xf8, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, + 0x77, 0x35, 0x00, 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xd0, 0x6f, 0x81, 0x89, 0x67, 0x63, 0x64, 0xf4, + 0x00, 0xef, 0xd0, 0xcf, 0x80, 0x37, 0x27, 0x00, 0x06, 0x85, 0x46, 0x09, 0x46, 0x1c, 0x47, 0x9d, + 0x8b, 0x63, 0x86, 0xd7, 0x00, 0x1c, 0x47, 0x9d, 0x8b, 0xe3, 0x9a, 0xc7, 0xfe, 0x37, 0x05, 0x00, + 0x06, 0x2a, 0x94, 0x08, 0x40, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x65, 0xb7, + 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x41, 0x11, 0x13, 0x05, 0x05, 0x80, 0x23, 0xa6, 0xe7, + 0xf8, 0x06, 0xc6, 0xef, 0x10, 0xc0, 0x20, 0xb7, 0x27, 0x00, 0x06, 0x9c, 0x47, 0x05, 0x47, 0x9d, + 0x8b, 0xfa, 0xce, 0xbf, 0x98, 0xb9, 0x2c, 0xe4, 0xa9, 0xc0, 0x33, 0xc1, 0x50, 0x40, 0x2f, 0x2c, + 0x1d, 0x3a, 0xcf, 0x61, 0xfa, 0xde, 0x2b, 0x3d, 0xb3, 0xbe, 0xd9, 0x1f, 0xa4, 0xf9, 0x07, 0x0c, + 0x82, 0x1c, 0xc0, 0x3c, 0xfd, 0x17, 0x63, 0x7b, 0xf7, 0x00, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, + 0x13, 0x05, 0x85, 0x6b, 0xef, 0xe0, 0xaf, 0xe9, 0xef, 0xc0, 0x9f, 0xfa, 0xb7, 0x07, 0x46, 0x00, + 0xb2, 0x40, 0x37, 0x27, 0x00, 0x06, 0x85, 0x07, 0x5c, 0xcf, 0x85, 0x47, 0x5c, 0xc7, 0x41, 0x01, + 0x82, 0x80, 0x37, 0x27, 0x00, 0x06, 0x1c, 0x47, 0x85, 0x46, 0x9d, 0x8b, 0x63, 0x8a, 0xd7, 0x00, + 0x14, 0xcb, 0xb7, 0x26, 0x00, 0x06, 0x05, 0x47, 0x9c, 0x46, 0x9d, 0x8b, 0xe3, 0x9e, 0xe7, 0xfe, + 0xb7, 0x27, 0x00, 0x06, 0x09, 0x47, 0x05, 0x65, 0x98, 0xcb, 0x13, 0x05, 0x05, 0x80, 0x6f, 0x10, + 0x00, 0x1b, 0x05, 0x65, 0x41, 0x11, 0x13, 0x05, 0x05, 0x80, 0x06, 0xc6, 0xef, 0x10, 0x60, 0x19, + 0xb2, 0x40, 0xb7, 0x27, 0x00, 0x06, 0x21, 0x47, 0x98, 0xcb, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, + 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0xaa, 0x84, 0xef, 0xf0, 0x5f, 0xf1, 0x2a, 0x84, 0x49, 0x22, + 0x13, 0x75, 0xf5, 0x0f, 0xef, 0xe0, 0x1f, 0xa6, 0x26, 0x85, 0xef, 0xf0, 0x3f, 0xf0, 0x63, 0x05, + 0xa4, 0x00, 0xef, 0xc0, 0xff, 0xf1, 0x01, 0x45, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, + 0x82, 0x80, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x06, 0xd6, 0x52, 0xcc, + 0xaa, 0x89, 0x2e, 0x89, 0x93, 0x74, 0xc6, 0xff, 0x01, 0x44, 0x33, 0x8a, 0x89, 0x00, 0x33, 0x05, + 0x89, 0x00, 0x63, 0x1a, 0x94, 0x00, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0xfa, 0x05, 0x16, 0x0b, + 0x27, 0x9c, 0xbd, 0xa0, 0x19, 0x42, 0x49, 0x9b, 0x1a, 0x08, 0x98, 0xc5, 0xb5, 0x39, 0x66, 0x19, + 0x4c, 0x8f, 0x62, 0xce, 0x88, 0x12, 0x33, 0x6a, 0x68, 0x93, 0x78, 0x94, 0x7c, 0x98, 0x3d, 0x02, + 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0xef, 0xf0, 0x9f, 0xf9, 0x2a, 0xc6, 0x11, + 0x46, 0x6c, 0x00, 0x52, 0x85, 0xef, 0x10, 0x50, 0x1d, 0x11, 0x04, 0xc9, 0xbf, 0x41, 0x11, 0x06, + 0xc6, 0xef, 0xf0, 0x1f, 0xf8, 0x2a, 0x87, 0x85, 0x46, 0x01, 0x45, 0x89, 0x45, 0x01, 0xe7, 0xb2, + 0x40, 0x41, 0x01, 0x82, 0x80, 0x93, 0x77, 0xf7, 0x00, 0x01, 0x46, 0x81, 0xef, 0x63, 0xd3, 0xc5, + 0x00, 0xb6, 0x87, 0x5d, 0x8d, 0x86, 0x06, 0x13, 0x75, 0xf5, 0x0f, 0x93, 0xf6, 0xf6, 0x0f, 0x11, + 0x83, 0xf1, 0xbf, 0x13, 0xf8, 0x17, 0x00, 0x85, 0x83, 0x42, 0x96, 0x93, 0xf7, 0xf7, 0x0f, 0xf1, + 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0xae, + 0x84, 0x99, 0xc3, 0xef, 0xc0, 0x1f, 0xe7, 0x89, 0x67, 0x63, 0x64, 0xf4, 0x00, 0xef, 0xc0, 0x7f, + 0xe6, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa6, 0xe7, 0xf8, 0xb7, 0x27, 0x00, + 0x06, 0x84, 0xcf, 0xc0, 0xcb, 0x22, 0x44, 0xb2, 0x40, 0x92, 0x44, 0x11, 0x47, 0x98, 0xcb, 0x89, + 0x65, 0x37, 0x45, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0xe5, 0x84, 0x41, 0x01, 0x6f, + 0xe0, 0xdf, 0xa4, 0x39, 0x71, 0x3a, 0xce, 0x37, 0x27, 0x00, 0x06, 0x3e, 0xcc, 0x1c, 0x47, 0x06, + 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, + 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0xfa, 0x4d, 0x54, 0xef, 0xad, 0xc7, 0xa3, 0x35, 0x08, + 0x61, 0xdd, 0xa8, 0xe0, 0xa3, 0xb3, 0xb5, 0x4c, 0x0e, 0xb9, 0xfe, 0x2c, 0xba, 0xb6, 0x89, 0x47, + 0xbe, 0xef, 0xa3, 0x71, 0xbf, 0xa7, 0x87, 0xf0, 0x70, 0x3e, 0x7a, 0xc2, 0x7e, 0xc0, 0xa1, 0x8b, + 0x85, 0xcf, 0xa1, 0x47, 0x1c, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, + 0xe7, 0xf8, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, + 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, + 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, + 0x85, 0x6b, 0xef, 0xe0, 0x2f, 0xcb, 0xef, 0xd0, 0xcf, 0xc6, 0xe1, 0xb7, 0xb7, 0x37, 0x20, 0x00, + 0x23, 0xa8, 0xa7, 0xf8, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xf9, 0x88, 0x43, + 0x37, 0x67, 0x19, 0x00, 0x13, 0x07, 0xd7, 0x60, 0x33, 0x05, 0xe5, 0x02, 0x37, 0xf7, 0x6e, 0x3c, + 0x13, 0x07, 0xf7, 0x35, 0x3a, 0x95, 0x88, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, + 0x47, 0xf9, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0x87, 0xf9, 0x9c, 0x4f, 0x13, 0x05, 0xa0, 0x0a, + 0xf9, 0x8f, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0xc7, 0xf9, 0x63, 0x84, 0xe7, 0x00, 0x13, 0x05, + 0x50, 0x05, 0x82, 0x80, 0xfd, 0x77, 0xfd, 0x17, 0xe9, 0x8f, 0xb7, 0x26, 0x00, 0x08, 0x2e, 0x87, + 0xb2, 0x85, 0x63, 0x94, 0xd7, 0x02, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0xa7, 0xf8, 0xb7, 0x37, + 0x20, 0x00, 0x37, 0x45, 0x10, 0x00, 0x23, 0xae, 0xe7, 0xf8, 0x13, 0x05, 0x05, 0xaf, 0xb7, 0x37, + 0x20, 0x00, 0xfa, 0x3c, 0x34, 0xa4, 0xc5, 0x1c, 0x8d, 0x12, 0xe6, 0x65, 0x41, 0x5e, 0x8c, 0x49, + 0xe6, 0x5a, 0xb2, 0x30, 0x94, 0xc5, 0x35, 0x93, 0xab, 0x6d, 0x8d, 0x65, 0xb2, 0xe5, 0xf7, 0x68, + 0x18, 0x4a, 0x8f, 0x48, 0x3f, 0x23, 0xac, 0xe7, 0xf8, 0x6f, 0xe0, 0x5f, 0x87, 0x13, 0x05, 0x50, + 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0xa7, 0xf8, 0xb7, 0x37, 0x20, 0x00, 0x37, + 0x45, 0x10, 0x00, 0x23, 0xae, 0x07, 0xf8, 0x13, 0x07, 0x00, 0x10, 0xb7, 0x37, 0x20, 0x00, 0x93, + 0x05, 0x80, 0x3e, 0x13, 0x05, 0x05, 0xaf, 0x23, 0xac, 0xe7, 0xf8, 0x6f, 0xe0, 0x3f, 0x84, 0x37, + 0x07, 0x01, 0x02, 0x5c, 0x43, 0xb7, 0x06, 0x05, 0x00, 0xd5, 0x8f, 0x5c, 0xc3, 0x82, 0x80, 0x41, + 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0xb7, 0x27, 0x00, 0x08, 0x37, 0x05, 0x08, 0x00, 0x63, + 0x14, 0xf4, 0x00, 0x37, 0x05, 0x04, 0x00, 0xef, 0x00, 0x50, 0x71, 0x5c, 0x5c, 0x22, 0x85, 0xb2, + 0x40, 0x93, 0xe7, 0x37, 0x00, 0x5c, 0xdc, 0x23, 0x2c, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x6f, + 0xf0, 0x5f, 0xf9, 0x58, 0x5d, 0xaa, 0x87, 0x75, 0x9b, 0x58, 0xdd, 0x37, 0x27, 0x00, 0x08, 0x37, + 0x05, 0x04, 0x00, 0x63, 0x84, 0xe7, 0x00, 0x37, 0x05, 0x08, 0x00, 0x6f, 0x00, 0xd0, 0x6e, 0x79, + 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x06, 0xd6, 0x4e, 0xce, 0x52, 0xcc, 0x56, 0xca, 0x2a, + 0x89, 0xae, 0x84, 0x32, 0x84, 0x99, 0xe1, 0xef, 0xc0, 0x3f, 0xc8, 0x13, 0x0a, 0xa0, 0x0a, 0x91, + 0x4a, 0x05, 0xe4, 0x83, 0x27, 0x89, 0x01, 0x37, 0x07, 0x11, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xf9, + 0x8f, 0x99, 0xc3, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0xfa, 0xc8, 0xad, + 0x53, 0x66, 0x47, 0xe0, 0x33, 0x5d, 0x3d, 0xca, 0x5c, 0x56, 0xb7, 0x62, 0x0c, 0x4e, 0x11, 0xad, + 0x71, 0x96, 0x1c, 0xa7, 0x76, 0x17, 0x6e, 0x57, 0x29, 0x10, 0x37, 0x89, 0xa9, 0x92, 0x20, 0x40, + 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0xd2, 0x4a, 0x45, 0x61, 0x82, 0x80, 0x13, 0x06, 0x80, 0x3e, + 0x85, 0x45, 0x4a, 0x85, 0xef, 0xf0, 0x7f, 0xee, 0xe3, 0x1f, 0x45, 0xfd, 0x83, 0x27, 0x49, 0x02, + 0xa2, 0x89, 0x3e, 0xc6, 0x63, 0xf3, 0x8a, 0x00, 0x91, 0x49, 0x26, 0x85, 0x4e, 0x86, 0x6c, 0x00, + 0xef, 0x10, 0x20, 0x73, 0xce, 0x94, 0x33, 0x04, 0x34, 0x41, 0x6d, 0xb7, 0x41, 0x11, 0x37, 0x05, + 0x02, 0x00, 0x06, 0xc6, 0xef, 0x00, 0xb0, 0x65, 0xb2, 0x40, 0xb7, 0x17, 0x00, 0x08, 0x37, 0x07, + 0x07, 0x00, 0x98, 0xd3, 0x13, 0x05, 0x40, 0x1f, 0x41, 0x01, 0x6f, 0xe0, 0xef, 0xee, 0xb7, 0x17, + 0x00, 0x08, 0x23, 0xa0, 0x07, 0x02, 0x37, 0x05, 0x02, 0x00, 0x6f, 0x00, 0x10, 0x64, 0x39, 0x71, + 0x3e, 0xcc, 0xb7, 0x17, 0x00, 0x08, 0x3a, 0xce, 0x98, 0x57, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, + 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, + 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0x05, 0x8b, 0x05, 0xcb, 0x98, 0x57, 0x13, 0x67, 0x17, 0x00, + 0x98, 0xd7, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, + 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, + 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x98, 0x57, 0x09, 0x8b, 0x09, 0xc7, 0x98, 0x57, + 0x13, 0x67, 0x27, 0x00, 0xf1, 0xb7, 0x98, 0x57, 0xfa, 0x48, 0x72, 0x90, 0x10, 0x25, 0x85, 0x9c, + 0xd6, 0x23, 0x79, 0xb8, 0xde, 0xe2, 0xbd, 0xc2, 0x74, 0xfe, 0xe0, 0x63, 0x22, 0x49, 0xf6, 0x73, + 0x23, 0x66, 0xba, 0x78, 0x98, 0xf8, 0x11, 0xf2, 0x26, 0xf8, 0x40, 0x11, 0x8b, 0x09, 0xc7, 0x98, + 0x57, 0x13, 0x67, 0x47, 0x00, 0x7d, 0xbf, 0xb7, 0x07, 0x00, 0x01, 0x73, 0xb0, 0x47, 0x30, 0xef, + 0xd0, 0xcf, 0xa1, 0x4d, 0xbf, 0x37, 0x07, 0x00, 0x02, 0x5c, 0x4f, 0xb7, 0x36, 0x20, 0x00, 0x13, + 0xf6, 0x77, 0x00, 0xe1, 0x9b, 0x23, 0xa0, 0xc6, 0xfa, 0x93, 0xe7, 0x47, 0x00, 0x5c, 0xcf, 0x1c, + 0x4f, 0xf9, 0x9b, 0x1c, 0xcf, 0x82, 0x80, 0x41, 0x11, 0x26, 0xc2, 0xb7, 0x04, 0x00, 0x02, 0x22, + 0xc4, 0xc0, 0x4c, 0x9c, 0x4c, 0x06, 0xc6, 0x13, 0x05, 0x80, 0x07, 0x93, 0xe7, 0x17, 0x00, 0x9c, + 0xcc, 0xef, 0xe0, 0xaf, 0xe1, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xfa, 0x61, 0x98, 0xb2, + 0x40, 0x5d, 0x8c, 0xc0, 0xcc, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x17, 0x05, + 0x01, 0x93, 0x17, 0x85, 0x01, 0xba, 0x97, 0x13, 0x17, 0x85, 0x00, 0xba, 0x97, 0x3e, 0x95, 0xb7, + 0x07, 0x00, 0x04, 0x88, 0xd3, 0xc8, 0xd3, 0x88, 0xd7, 0xc8, 0xd7, 0x88, 0xdb, 0xc8, 0xdb, 0x88, + 0xdf, 0xc8, 0xdf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x00, 0x08, 0x98, 0xd3, 0x23, + 0xa2, 0x07, 0x02, 0x0e, 0x05, 0x23, 0xa4, 0x07, 0x02, 0x42, 0x05, 0x23, 0xa6, 0x07, 0x02, 0x41, + 0x81, 0x23, 0xa8, 0x07, 0x02, 0x13, 0x17, 0x85, 0x00, 0xb7, 0x06, 0xff, 0x00, 0x23, 0xaa, 0x07, + 0x02, 0x75, 0x8f, 0x62, 0x05, 0x23, 0xac, 0x07, 0x02, 0x3a, 0x95, 0xc8, 0xdf, 0x82, 0x80, 0xb7, + 0x07, 0x00, 0x04, 0xfa, 0x58, 0x79, 0x18, 0x78, 0xc7, 0x7c, 0x01, 0x3c, 0x5e, 0xe8, 0x38, 0xbe, + 0xce, 0x54, 0x22, 0x87, 0xbf, 0xcf, 0x2e, 0x05, 0x05, 0x63, 0xc6, 0xf4, 0xf7, 0xae, 0x01, 0x21, + 0x65, 0xf5, 0xb3, 0xc1, 0xd0, 0x41, 0x13, 0x07, 0x00, 0x08, 0x98, 0xd3, 0x23, 0xa2, 0x07, 0x02, + 0x23, 0xa4, 0x07, 0x02, 0x23, 0xa6, 0x07, 0x02, 0x23, 0xa8, 0x07, 0x02, 0x23, 0xaa, 0x07, 0x02, + 0x23, 0xac, 0x07, 0x02, 0x23, 0xae, 0x07, 0x02, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, + 0x47, 0xea, 0x82, 0x80, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, + 0x05, 0x02, 0x6f, 0xe0, 0x3f, 0x83, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa2, + 0xe7, 0xea, 0xb7, 0x07, 0x00, 0x04, 0xc8, 0xc3, 0x13, 0x07, 0x90, 0x02, 0x85, 0x65, 0x37, 0x45, + 0x10, 0x00, 0x98, 0xc7, 0x93, 0x85, 0x85, 0x38, 0x13, 0x05, 0x45, 0xdf, 0x6f, 0xe0, 0xaf, 0xd8, + 0x41, 0x11, 0x22, 0xc4, 0x01, 0x45, 0x37, 0x34, 0x20, 0x00, 0x06, 0xc6, 0x13, 0x04, 0x44, 0xe9, + 0xef, 0xf0, 0x1f, 0xf2, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0xfb, + 0x48, 0x44, 0xb7, 0x07, 0x02, 0x00, 0x95, 0x07, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0xbf, 0xfa, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x05, 0xef, 0xf0, 0xff, 0xf9, 0x48, 0x44, 0xb7, 0x07, + 0x00, 0x10, 0x99, 0x07, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0xff, 0xf8, 0x48, 0x44, 0xb7, 0x07, + 0x01, 0x10, 0x99, 0x07, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0xff, 0xf7, 0x22, 0x44, 0xb2, 0x40, + 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0xf7, 0x7d, 0x47, 0x63, 0x7e, 0xb7, 0x04, 0xfa, 0x2e, + 0xb1, 0x66, 0xd9, 0xe7, 0x32, 0x03, 0x63, 0x15, 0x89, 0x6a, 0xae, 0xaf, 0x61, 0x6e, 0x4b, 0x14, + 0x27, 0x5f, 0x2a, 0x10, 0x4d, 0x94, 0x8e, 0x13, 0xe1, 0x4a, 0x62, 0x0f, 0x2a, 0x56, 0xa0, 0xa8, + 0x42, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0x6f, + 0xe0, 0x8f, 0xf8, 0xb3, 0x06, 0xf5, 0x00, 0x83, 0xc6, 0x06, 0x00, 0x33, 0x07, 0xf1, 0x00, 0x85, + 0x07, 0x23, 0x00, 0xd7, 0x00, 0xe3, 0x97, 0xf5, 0xfe, 0x18, 0x10, 0x93, 0x87, 0x15, 0x00, 0xba, + 0x95, 0x13, 0x07, 0x00, 0xf8, 0x23, 0x80, 0xe5, 0xfe, 0x13, 0x07, 0x00, 0x02, 0x63, 0x92, 0xe7, + 0x02, 0x37, 0x05, 0x00, 0x04, 0x8a, 0x85, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0xef, + 0xe0, 0x8f, 0xf4, 0xb2, 0x50, 0x45, 0x61, 0x82, 0x80, 0x79, 0x71, 0x06, 0xd6, 0x81, 0x47, 0xd9, + 0xb7, 0xb3, 0x06, 0xf1, 0x00, 0x23, 0x80, 0x06, 0x00, 0x85, 0x07, 0xc9, 0xbf, 0x37, 0x55, 0x10, + 0x00, 0x01, 0x11, 0x13, 0x05, 0x45, 0x6c, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, + 0xc6, 0x52, 0xc4, 0x37, 0x34, 0x20, 0x00, 0xef, 0xf0, 0x1f, 0xed, 0x93, 0x07, 0x44, 0xe9, 0xc8, + 0x47, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x3f, 0xed, 0x93, 0x07, 0xa0, 0x0a, 0x63, + 0x10, 0xf5, 0x2e, 0xaa, 0x84, 0x13, 0x05, 0x00, 0x02, 0xef, 0xf0, 0x3f, 0xe4, 0x13, 0x04, 0x44, + 0xe9, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x1f, 0xeb, 0xaa, 0x89, 0x63, + 0x10, 0x95, 0x2c, 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, + 0xf0, 0xbf, 0xe9, 0xaa, 0x84, 0x63, 0x15, 0x35, 0x2b, 0xfa, 0x91, 0x2f, 0xf9, 0x87, 0xe2, 0x7b, + 0x59, 0x78, 0x12, 0xf6, 0xbc, 0xfb, 0xf6, 0x1d, 0x67, 0xf1, 0x41, 0xef, 0x8e, 0xca, 0xac, 0xdf, + 0x01, 0x32, 0xda, 0x2c, 0x04, 0x5f, 0x4e, 0xd9, 0x99, 0xe2, 0x80, 0x43, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x9f, 0xe8, 0xaa, 0x89, 0x63, 0x1c, 0x95, 0x28, 0x1c, 0x40, + 0x48, 0x44, 0x37, 0x0a, 0x00, 0x04, 0x83, 0xc7, 0x07, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x15, 0x00, + 0x93, 0xe7, 0x07, 0x20, 0x23, 0x2c, 0xfa, 0x00, 0xef, 0xf0, 0x5f, 0xe6, 0xaa, 0x84, 0x63, 0x1a, + 0x35, 0x27, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x3f, 0xe5, 0x2a, 0x89, + 0x63, 0x11, 0x95, 0x26, 0xef, 0xf0, 0x5f, 0xe0, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, + 0xef, 0xf0, 0xdf, 0xe3, 0xaa, 0x84, 0x63, 0x16, 0x25, 0x25, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, + 0x1f, 0xdb, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, + 0xff, 0xe1, 0x2a, 0x89, 0x63, 0x17, 0x95, 0x22, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, + 0xef, 0xf0, 0xdf, 0xe0, 0xaa, 0x84, 0x63, 0x1e, 0x25, 0x21, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x02, 0xef, 0xf0, 0xbf, 0xdf, 0x63, 0x16, 0x95, 0x20, 0x48, 0x44, 0x93, 0x07, 0x00, 0x10, + 0x23, 0x2c, 0xfa, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x15, 0x00, 0xef, 0xf0, 0x3f, 0xde, 0x93, 0x07, + 0xa0, 0x0a, 0xaa, 0x84, 0x63, 0x17, 0xf5, 0x1e, 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, + 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x9f, 0xdc, 0xaa, 0x89, 0x63, 0x1c, 0x95, 0x1c, 0xef, 0xf0, + 0xbf, 0xd7, 0x48, 0x44, 0xfa, 0xad, 0x15, 0x42, 0x2e, 0x51, 0xa3, 0x77, 0x4c, 0x9e, 0xf4, 0x30, + 0x0c, 0xf3, 0x41, 0xe0, 0x63, 0x94, 0x96, 0x7c, 0x6f, 0x27, 0x23, 0x04, 0x5f, 0xc5, 0xdc, 0x31, + 0x88, 0x65, 0x71, 0xcd, 0x50, 0x58, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x3f, + 0xdb, 0xaa, 0x84, 0x63, 0x11, 0x35, 0x1d, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x7f, 0xd2, 0x48, + 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x5f, 0xd9, 0xaa, + 0x89, 0x63, 0x12, 0x95, 0x1a, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x3f, + 0xd8, 0xaa, 0x84, 0x63, 0x19, 0x35, 0x19, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, + 0xf0, 0x1f, 0xd7, 0xaa, 0x89, 0x63, 0x10, 0x95, 0x18, 0x08, 0x40, 0x05, 0x05, 0xef, 0xf0, 0x1f, + 0xd5, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x7f, 0xd5, 0xaa, 0x84, 0x63, + 0x13, 0x35, 0x17, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x5f, 0xd4, 0x2a, + 0x89, 0x63, 0x1a, 0x95, 0x14, 0xef, 0xf0, 0x7f, 0xcf, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, + 0x07, 0xef, 0xf0, 0xff, 0xd2, 0xaa, 0x84, 0x63, 0x1f, 0x25, 0x13, 0x13, 0x05, 0x00, 0x04, 0xef, + 0xf0, 0x3f, 0xca, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, + 0xf0, 0x1f, 0xd1, 0x63, 0x11, 0x95, 0x12, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, + 0xf0, 0x1f, 0xd0, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0x63, 0x16, 0xf5, 0x10, 0x48, 0x44, 0x7e, + 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xbf, 0xce, 0xaa, 0x84, 0x63, 0x1d, 0x25, 0x0f, 0xfa, + 0x23, 0xe5, 0xdd, 0xa6, 0x85, 0x7f, 0x95, 0xa3, 0x6e, 0xc6, 0x40, 0x79, 0x1c, 0x78, 0xd0, 0xdc, + 0x84, 0xe8, 0x86, 0x8e, 0xd1, 0x76, 0x71, 0x26, 0x42, 0x94, 0x88, 0x22, 0x67, 0xb1, 0x8a, 0xb8, + 0x30, 0x45, 0x13, 0x05, 0x10, 0x02, 0xef, 0xf0, 0xff, 0xc5, 0x1c, 0x40, 0x48, 0x44, 0x21, 0x67, + 0x83, 0xc7, 0x07, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xd9, 0x8f, 0x23, 0x20, 0xfa, 0x02, + 0xef, 0xf0, 0x3f, 0xcc, 0xaa, 0x89, 0x63, 0x19, 0x95, 0x0c, 0x48, 0x44, 0x89, 0x64, 0x8d, 0x04, + 0x7e, 0x05, 0x45, 0x8d, 0xef, 0xf0, 0xff, 0xca, 0x2a, 0x89, 0x63, 0x1f, 0x35, 0x0b, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xdf, 0xc9, 0xaa, 0x89, 0x63, 0x16, 0x25, 0x0b, + 0x08, 0x40, 0x13, 0x05, 0x15, 0x02, 0xef, 0xf0, 0xbf, 0xc7, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x17, 0xef, 0xf0, 0x1f, 0xc8, 0x2a, 0x89, 0x63, 0x18, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, + 0x45, 0x8d, 0xef, 0xf0, 0x1f, 0xc7, 0xaa, 0x84, 0x63, 0x10, 0x25, 0x09, 0xef, 0xf0, 0x3f, 0xc2, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0xc5, 0x2a, 0x89, 0x63, 0x15, + 0x95, 0x06, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0xff, 0xbc, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xc3, 0xaa, 0x84, 0x63, 0x16, 0x25, 0x05, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xbf, 0xc2, 0x63, 0x1e, 0x95, 0x02, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x52, 0xef, 0xf0, 0xbf, 0xc1, 0x93, 0x07, 0xa0, 0x0a, + 0x63, 0x14, 0xf5, 0x02, 0x08, 0x40, 0x62, 0x44, 0xf2, 0x40, 0xfa, 0x77, 0x91, 0xe4, 0x63, 0xc5, + 0xd3, 0x00, 0xec, 0x07, 0x6d, 0x73, 0xd9, 0xbd, 0x73, 0xd9, 0x24, 0xea, 0x8f, 0xd4, 0x98, 0x7f, + 0x6e, 0xc0, 0xa3, 0x56, 0x6c, 0x79, 0x52, 0xa7, 0xe1, 0x5a, 0xb0, 0x08, 0x46, 0xd2, 0x44, 0x42, + 0x49, 0xb2, 0x49, 0x22, 0x4a, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, + 0x06, 0x13, 0x05, 0x15, 0x06, 0x05, 0x61, 0x6f, 0xe0, 0x0f, 0xbb, 0xf2, 0x40, 0x62, 0x44, 0xd2, + 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x4e, 0xc6, 0x06, + 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x52, 0xc4, 0x93, 0x09, 0x00, 0x04, 0x63, 0xeb, 0xb9, + 0x08, 0x37, 0x3a, 0x20, 0x00, 0xaa, 0x84, 0x2e, 0x84, 0x13, 0x09, 0x4a, 0xe9, 0xef, 0xf0, 0xbf, + 0xc4, 0x03, 0x25, 0xc9, 0x00, 0x13, 0x0a, 0x4a, 0xe9, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, + 0xf0, 0x7f, 0xba, 0x13, 0x85, 0x04, 0x02, 0x63, 0x19, 0x34, 0x03, 0xaa, 0x85, 0x37, 0x05, 0x00, + 0x04, 0x13, 0x05, 0x05, 0x02, 0x13, 0x06, 0x00, 0x02, 0xef, 0xe0, 0xaf, 0xbb, 0x03, 0x25, 0xc9, + 0x00, 0x62, 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x7e, 0x05, 0x13, + 0x65, 0x05, 0x17, 0x05, 0x61, 0x6f, 0xf0, 0x1f, 0xb7, 0xfd, 0x47, 0x63, 0xf8, 0x87, 0x02, 0x93, + 0x05, 0x04, 0xfe, 0xef, 0xf0, 0x5f, 0xbf, 0x13, 0x04, 0x04, 0x04, 0x0e, 0x04, 0x42, 0x04, 0x41, + 0x80, 0x93, 0x17, 0x84, 0x00, 0x37, 0x07, 0xff, 0x00, 0xf9, 0x8f, 0x62, 0x04, 0x3e, 0x94, 0xb7, + 0x07, 0x00, 0x04, 0x03, 0x25, 0xca, 0x00, 0xc0, 0xdf, 0x65, 0xbf, 0x01, 0x45, 0xef, 0xf0, 0x3f, + 0xa9, 0xd9, 0xbf, 0xf2, 0x40, 0xfa, 0x35, 0xb9, 0x4d, 0xc4, 0x75, 0x9e, 0xa8, 0xdd, 0x16, 0x2c, + 0xac, 0xdb, 0x5a, 0xe6, 0x80, 0x8f, 0x72, 0x57, 0xaa, 0xfd, 0x26, 0x9c, 0x70, 0x1b, 0xce, 0xa0, + 0x79, 0x41, 0x63, 0x72, 0x43, 0x7c, 0xe0, 0x46, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, + 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, 0x37, 0x34, 0x20, 0x00, 0x93, 0x07, + 0x44, 0xe9, 0x52, 0xc4, 0x2a, 0x8a, 0xc8, 0x47, 0x56, 0xc2, 0x06, 0xce, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x30, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xae, 0x8a, 0xef, 0xf0, 0xff, 0xaf, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x11, 0xf5, 0x12, 0xaa, 0x84, 0x13, 0x05, 0x60, 0x03, 0xef, 0xf0, 0x7f, 0xa4, + 0x13, 0x04, 0x44, 0xe9, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x45, 0x00, 0xef, 0xf0, 0xdf, 0xad, + 0x2a, 0x89, 0x63, 0x11, 0x95, 0x10, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, + 0xbf, 0xac, 0xaa, 0x84, 0x63, 0x18, 0x25, 0x0f, 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, + 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x5f, 0xab, 0xaa, 0x89, 0x63, 0x1d, 0x95, 0x0c, 0xd6, 0x85, + 0x52, 0x85, 0xef, 0xf0, 0xdf, 0xec, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, + 0xbf, 0xa9, 0xaa, 0x84, 0x63, 0x10, 0x35, 0x0d, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x03, + 0xef, 0xf0, 0x9f, 0xa8, 0xaa, 0x89, 0x63, 0x17, 0x95, 0x0a, 0x13, 0x05, 0xc0, 0x05, 0xef, 0xf0, + 0x5f, 0x9d, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x45, 0x00, 0xef, 0xf0, 0xff, 0xa6, 0xaa, 0x84, + 0x63, 0x1a, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xa5, + 0xfa, 0xe3, 0x0a, 0x61, 0x37, 0x59, 0x2c, 0xd8, 0x60, 0x77, 0x81, 0x93, 0x22, 0x6f, 0x28, 0x70, + 0x4c, 0x4a, 0x3b, 0x5a, 0xea, 0xdf, 0xa8, 0xf7, 0x3a, 0x2c, 0xbc, 0x0b, 0x23, 0x00, 0x50, 0x0e, + 0xfc, 0xb8, 0x47, 0xaa, 0x89, 0x63, 0x11, 0x95, 0x08, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, + 0x32, 0xef, 0xf0, 0xbf, 0xa4, 0xaa, 0x84, 0x63, 0x18, 0x35, 0x07, 0x48, 0x44, 0x7e, 0x05, 0x33, + 0x65, 0x25, 0x01, 0xef, 0xf0, 0x9f, 0xa3, 0x63, 0x10, 0x95, 0x06, 0x48, 0x44, 0x7e, 0x05, 0x13, + 0x65, 0x05, 0x03, 0xef, 0xf0, 0x9f, 0xa2, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0x63, 0x15, 0xf5, + 0x04, 0x13, 0x05, 0x00, 0x06, 0xef, 0xf0, 0x9f, 0x99, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, + 0x17, 0xef, 0xf0, 0xbf, 0xa0, 0xaa, 0x84, 0x63, 0x18, 0x25, 0x03, 0x48, 0x44, 0x7e, 0x05, 0x13, + 0x65, 0x35, 0x00, 0xef, 0xf0, 0x9f, 0x9f, 0x63, 0x10, 0x95, 0x02, 0x48, 0x44, 0x62, 0x44, 0xf2, + 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x7e, 0x05, 0x13, 0x65, 0x05, + 0x02, 0x05, 0x61, 0x6f, 0xf0, 0x9f, 0x9d, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, + 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x39, 0x71, 0x22, 0xdc, 0x37, 0x34, 0x20, + 0x00, 0x06, 0xde, 0x4a, 0xd8, 0x26, 0xda, 0x32, 0x89, 0x13, 0x04, 0x44, 0xe9, 0xef, 0xf0, 0xdf, + 0xe8, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x40, 0xef, 0xf0, 0x3f, 0x9a, 0x93, 0x07, 0xa0, + 0x0a, 0x63, 0x12, 0xf5, 0x0a, 0xaa, 0x84, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0xc5, + 0x6b, 0xef, 0xf0, 0x9f, 0xe6, 0x85, 0x47, 0x63, 0x07, 0xf9, 0x08, 0xfa, 0xbf, 0xa1, 0x9f, 0x42, + 0x31, 0x1c, 0x31, 0xc5, 0x2c, 0x39, 0x12, 0x99, 0x30, 0xb5, 0x57, 0x6d, 0xdb, 0x71, 0x11, 0x1f, + 0xb7, 0x49, 0x17, 0xd0, 0xae, 0xba, 0xc1, 0xe1, 0xb0, 0xab, 0x1e, 0x79, 0x90, 0x48, 0x48, 0x44, + 0x85, 0x67, 0x93, 0x87, 0x07, 0x80, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0x5f, 0x97, 0x2a, 0x89, + 0x63, 0x1c, 0x95, 0x06, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x04, + 0x68, 0x00, 0xef, 0xe0, 0xef, 0x91, 0x48, 0x44, 0x89, 0x47, 0x23, 0x06, 0xf1, 0x02, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x20, 0xef, 0xf0, 0xbf, 0x94, 0xaa, 0x84, 0x63, 0x17, 0x25, 0x05, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0x9f, 0x93, 0x2a, 0x89, 0x63, 0x1e, 0x95, 0x02, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x42, 0xef, 0xf0, 0x7f, 0x92, 0xaa, 0x84, 0x63, 0x15, + 0x25, 0x03, 0x68, 0x00, 0x93, 0x05, 0x10, 0x02, 0xef, 0xf0, 0x5f, 0xdf, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x10, 0xef, 0xf0, 0xbf, 0x90, 0x63, 0x18, 0x95, 0x00, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xbf, 0x8f, 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, 0x42, 0x59, + 0x21, 0x61, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x44, 0xe9, + 0x08, 0x40, 0x09, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x06, 0xc6, 0xef, 0xf0, + 0xff, 0xf0, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x71, 0xef, 0xf0, 0x5f, 0x8c, 0x48, 0x44, + 0x22, 0x44, 0xb2, 0x40, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0x8b, + 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0xfa, 0x6e, 0x14, 0x78, 0x38, 0xc4, 0xd9, 0x74, 0x0f, 0x12, + 0x73, 0x0a, 0x34, 0x45, 0x89, 0xea, 0x0a, 0x1c, 0x20, 0x38, 0x2a, 0x1e, 0x81, 0x17, 0xdb, 0xd5, + 0x86, 0x8b, 0x4a, 0x6f, 0x68, 0x28, 0xff, 0x68, 0x49, 0x47, 0xe9, 0x05, 0x46, 0x93, 0x05, 0x00, + 0x02, 0x13, 0x05, 0x15, 0x04, 0x6f, 0xf0, 0xbf, 0xed, 0x41, 0x11, 0xb7, 0x55, 0x10, 0x00, 0x37, + 0x05, 0x00, 0x04, 0x22, 0xc4, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x45, 0x6c, 0x13, 0x05, 0x05, + 0x02, 0x37, 0x34, 0x20, 0x00, 0x06, 0xc6, 0x13, 0x04, 0x44, 0xe9, 0xef, 0xe0, 0x4f, 0x8a, 0x48, + 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0x86, 0x93, 0x07, 0xa0, 0x0a, 0x63, + 0x1d, 0xf5, 0x00, 0x08, 0x40, 0x22, 0x44, 0xb2, 0x40, 0x05, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, + 0x05, 0x15, 0x04, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xe8, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, + 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x44, 0xe9, 0x48, 0x44, 0x06, + 0xc6, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xbf, 0x82, 0x08, 0x40, 0x13, 0x06, 0x00, + 0x02, 0x81, 0x45, 0x13, 0x05, 0x15, 0x04, 0xef, 0x00, 0x90, 0x5c, 0x08, 0x40, 0x09, 0x46, 0x81, + 0x45, 0x13, 0x05, 0x15, 0x04, 0xef, 0xf0, 0xbf, 0xe4, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, + 0x60, 0xef, 0xf0, 0x1f, 0x80, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x71, 0xef, 0xf0, 0x4f, + 0xff, 0x01, 0x45, 0xef, 0xf0, 0x8f, 0xf4, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, + 0xf0, 0x2f, 0xfe, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x6f, 0xfd, 0xb2, + 0x40, 0xfa, 0x57, 0x22, 0xaa, 0x1e, 0x7c, 0x0e, 0x8c, 0x55, 0x47, 0x16, 0x49, 0x46, 0x1d, 0xa8, + 0x81, 0x1f, 0x8c, 0x85, 0xdc, 0xf8, 0x90, 0xb3, 0xf5, 0x94, 0x32, 0x77, 0x15, 0x05, 0x20, 0x67, + 0xbc, 0x45, 0x40, 0x4a, 0x22, 0x44, 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, 0x98, 0xc7, 0x41, 0x01, + 0x82, 0x80, 0x11, 0x65, 0xad, 0xa9, 0x37, 0x35, 0x20, 0x00, 0x41, 0x11, 0x51, 0x46, 0x81, 0x45, + 0x13, 0x05, 0x45, 0xe9, 0x06, 0xc6, 0xef, 0x00, 0xd0, 0x55, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, + 0x50, 0x05, 0x1d, 0x65, 0x23, 0xa2, 0xe7, 0xfa, 0xa9, 0x21, 0xb2, 0x40, 0xb7, 0x07, 0x00, 0x04, + 0x05, 0x47, 0x98, 0xcb, 0x41, 0x01, 0x6f, 0xf0, 0xdf, 0xfc, 0x11, 0x65, 0x1d, 0xa9, 0x95, 0x47, + 0x63, 0xec, 0xb7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x44, 0xe9, + 0x85, 0x47, 0x5c, 0xc0, 0xb7, 0x57, 0x10, 0x00, 0x0c, 0xc4, 0x93, 0x87, 0x87, 0x6e, 0x8a, 0x05, + 0xbe, 0x95, 0x9c, 0x41, 0x06, 0xc6, 0x08, 0xc0, 0x82, 0x97, 0x08, 0x48, 0xb2, 0x40, 0x23, 0x22, + 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x05, + 0x00, 0x04, 0x41, 0x46, 0x93, 0x85, 0x05, 0x08, 0x6f, 0xd0, 0xff, 0xef, 0x37, 0x37, 0x20, 0x00, + 0x13, 0x07, 0x47, 0xe9, 0x89, 0x47, 0x5c, 0xc3, 0x5c, 0x47, 0x46, 0x05, 0xfe, 0x07, 0xc9, 0x8f, + 0x21, 0x65, 0x15, 0x05, 0x5d, 0x8d, 0x6f, 0xf0, 0xef, 0xf1, 0x39, 0x71, 0x4e, 0xd6, 0x5e, 0xce, + 0x62, 0xcc, 0xb7, 0x0b, 0x00, 0x04, 0xb7, 0x39, 0x20, 0x00, 0x05, 0x6c, 0x22, 0xdc, 0x26, 0xda, + 0x4a, 0xd8, 0x56, 0xd2, 0x5a, 0xd0, 0x66, 0xca, 0x6a, 0xc8, 0x06, 0xde, 0xfa, 0x65, 0xb9, 0x0c, + 0x88, 0x3f, 0x5b, 0x66, 0xde, 0x7a, 0xed, 0xe1, 0x97, 0x78, 0xec, 0x24, 0xa1, 0xb2, 0xc1, 0x8b, + 0x4a, 0x99, 0xae, 0xe9, 0x9f, 0xe8, 0xfb, 0xcb, 0x08, 0x0c, 0x8a, 0x24, 0xa7, 0x18, 0x4b, 0x52, + 0xd4, 0x2a, 0x84, 0x2e, 0x8b, 0xb2, 0x8a, 0x81, 0x44, 0x01, 0x49, 0xc1, 0x4c, 0x93, 0x8b, 0x0b, + 0x02, 0x93, 0x89, 0x49, 0xe9, 0x09, 0x0c, 0x37, 0x3d, 0x20, 0x00, 0xb3, 0x05, 0x9b, 0x00, 0x63, + 0xe0, 0x54, 0x03, 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, + 0x5a, 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, 0xd2, 0x4c, 0x42, 0x4d, 0x21, 0x61, 0x82, 0x80, 0x33, + 0x8a, 0x9a, 0x40, 0x63, 0xd3, 0x4c, 0x01, 0x41, 0x4a, 0x4a, 0x85, 0x2e, 0xc6, 0xef, 0xe0, 0xcf, + 0x9f, 0xb2, 0x45, 0x13, 0x06, 0x3a, 0x00, 0x71, 0x9a, 0x5e, 0x85, 0xef, 0xd0, 0xbf, 0xec, 0x03, + 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xef, 0xe8, 0x03, 0xa5, 0xc9, + 0x00, 0x93, 0x17, 0x8a, 0x01, 0x7e, 0x05, 0x5d, 0x8d, 0x13, 0x65, 0x75, 0x00, 0xef, 0xf0, 0xaf, + 0xe7, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x33, 0x65, 0x85, 0x01, 0xef, 0xf0, 0xcf, 0xe6, 0x03, + 0x27, 0x4d, 0xfa, 0x93, 0x07, 0x50, 0x05, 0x63, 0x19, 0xf7, 0x00, 0x19, 0xc4, 0x22, 0x85, 0x52, + 0x86, 0xca, 0x85, 0xef, 0xe0, 0x4f, 0xa3, 0x41, 0x04, 0x93, 0x07, 0x00, 0x07, 0x63, 0xe3, 0x27, + 0x01, 0x41, 0x09, 0xc1, 0x04, 0x9d, 0xb7, 0x39, 0x71, 0x4e, 0xd6, 0x5a, 0xd0, 0x5e, 0xce, 0xb7, + 0x39, 0x20, 0x00, 0x37, 0x0b, 0x02, 0x00, 0x85, 0x6b, 0x26, 0xda, 0x4a, 0xd8, 0x52, 0xd4, 0x56, + 0xd2, 0x62, 0xcc, 0x6a, 0xc8, 0x6e, 0xc6, 0xfa, 0xd2, 0xaa, 0x40, 0x04, 0x8d, 0x72, 0x7b, 0xb3, + 0xf9, 0xe3, 0xef, 0xdb, 0xce, 0xbc, 0xf2, 0xac, 0xb2, 0x83, 0xb2, 0x4e, 0x4e, 0xe9, 0xca, 0x4f, + 0x79, 0x98, 0x07, 0x37, 0xde, 0xdd, 0xbc, 0x0e, 0xf0, 0x4b, 0x06, 0xde, 0x22, 0xdc, 0x66, 0xca, + 0xaa, 0x8a, 0xae, 0x84, 0x32, 0x8a, 0x01, 0x49, 0x81, 0x4d, 0x37, 0x3c, 0x20, 0x00, 0x41, 0x4d, + 0x93, 0x89, 0x49, 0xe9, 0x1d, 0x0b, 0x93, 0x8b, 0x0b, 0x82, 0xb3, 0x8c, 0x2a, 0x01, 0x93, 0x07, + 0x4c, 0xfa, 0x63, 0x64, 0x49, 0x03, 0xf2, 0x50, 0x62, 0x54, 0x13, 0x07, 0x50, 0x05, 0x98, 0xc3, + 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, + 0xd2, 0x4c, 0x42, 0x4d, 0xb2, 0x4d, 0x21, 0x61, 0x82, 0x80, 0x33, 0x04, 0x2a, 0x41, 0x63, 0x73, + 0x8d, 0x00, 0x41, 0x44, 0x6e, 0x85, 0xef, 0xe0, 0xef, 0x91, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, + 0x47, 0xfa, 0x98, 0x43, 0x93, 0x07, 0x50, 0x05, 0x63, 0x19, 0xf7, 0x00, 0x99, 0xc4, 0x26, 0x85, + 0x22, 0x86, 0xee, 0x85, 0xef, 0xe0, 0xcf, 0x9b, 0xc1, 0x04, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, + 0x13, 0x65, 0x25, 0x00, 0xef, 0xf0, 0x6f, 0xd9, 0x03, 0xa5, 0xc9, 0x00, 0x93, 0x17, 0x84, 0x01, + 0x0d, 0x04, 0x7e, 0x05, 0x5d, 0x8d, 0x33, 0x65, 0x65, 0x01, 0xef, 0xf0, 0x0f, 0xd8, 0x03, 0xa5, + 0xc9, 0x00, 0x7e, 0x05, 0x33, 0x65, 0x75, 0x01, 0xef, 0xf0, 0x2f, 0xd7, 0xb7, 0x05, 0x00, 0x04, + 0x13, 0x76, 0xc4, 0xff, 0x93, 0x85, 0x05, 0x04, 0x66, 0x85, 0xef, 0xd0, 0x3f, 0xd2, 0x93, 0x07, + 0x00, 0x06, 0x63, 0xe3, 0xb7, 0x01, 0xc1, 0x0d, 0x41, 0x09, 0x81, 0xbf, 0x41, 0x11, 0x22, 0xc4, + 0x2a, 0x84, 0xfa, 0xe4, 0x9f, 0x33, 0x88, 0xe3, 0x5c, 0x0f, 0x58, 0x0c, 0xef, 0xff, 0xbd, 0xba, + 0x7a, 0x34, 0x0b, 0x73, 0x41, 0xc6, 0xf6, 0x89, 0xf9, 0x0c, 0x38, 0x09, 0x56, 0x4d, 0xcb, 0x48, + 0xea, 0x20, 0x65, 0xc8, 0x4c, 0x21, 0x45, 0x06, 0xc6, 0xef, 0xf0, 0x4f, 0xd4, 0x93, 0x07, 0xa0, + 0x0a, 0x63, 0x19, 0xf5, 0x00, 0x22, 0x85, 0xef, 0xf0, 0x1f, 0xdf, 0xb7, 0x37, 0x20, 0x00, 0x23, + 0xac, 0x07, 0xe8, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, + 0xa2, 0xa7, 0xfa, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x60, 0x02, 0x98, 0xc7, 0x82, + 0x80, 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, 0x98, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0xc8, + 0x4b, 0x82, 0x80, 0x39, 0x71, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x05, 0x47, 0xb7, 0x07, 0x00, + 0x04, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x42, + 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xd8, 0xc7, 0xb7, 0x37, 0x20, + 0x00, 0x93, 0x87, 0x47, 0xe9, 0xd8, 0x43, 0x89, 0x46, 0x7d, 0x17, 0x63, 0xfe, 0xe6, 0x02, 0x37, + 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x05, 0x6c, 0xef, 0xd0, 0xef, 0xe0, 0xef, 0xc0, 0x8f, + 0xdc, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, + 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, + 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x13, 0x07, 0xa0, 0x0a, 0x98, 0xcb, 0xd1, 0xbf, 0xb7, + 0x07, 0x01, 0x02, 0x88, 0xd7, 0xcc, 0xd7, 0x88, 0xdb, 0xcc, 0xdb, 0x88, 0xdf, 0xfa, 0xf0, 0x45, + 0x71, 0x22, 0x19, 0x65, 0x77, 0x86, 0xb0, 0xbf, 0xec, 0xcc, 0x91, 0xa8, 0x07, 0x81, 0xc8, 0x60, + 0x4c, 0x1f, 0x41, 0x46, 0x98, 0xdd, 0xc2, 0x2f, 0xbd, 0x80, 0x56, 0x18, 0xfd, 0x31, 0xa0, 0x4d, + 0xcc, 0xdf, 0x82, 0x80, 0x01, 0x11, 0x26, 0xca, 0xb7, 0x04, 0x01, 0x02, 0x22, 0xcc, 0xc0, 0x40, + 0xf5, 0x77, 0x93, 0x87, 0xf7, 0xa5, 0x7d, 0x8c, 0x89, 0x67, 0x93, 0x87, 0x07, 0x1a, 0x06, 0xce, + 0x4a, 0xc8, 0x4e, 0xc6, 0xc1, 0x8f, 0xaa, 0x89, 0xdc, 0xc0, 0x05, 0x45, 0x2e, 0x89, 0xef, 0xd0, + 0xbf, 0x99, 0x93, 0x67, 0x04, 0x40, 0xdc, 0xc0, 0x05, 0x45, 0xef, 0xd0, 0xff, 0x98, 0x85, 0x67, + 0x93, 0x87, 0x07, 0x40, 0x5d, 0x8c, 0xc0, 0xc0, 0xb7, 0x47, 0x00, 0x08, 0x23, 0xa4, 0x07, 0x00, + 0xb7, 0x57, 0x00, 0x08, 0x23, 0xa4, 0x07, 0x00, 0xf2, 0x40, 0x62, 0x44, 0x23, 0xa0, 0x34, 0x03, + 0x23, 0xa2, 0x24, 0x03, 0xb2, 0x49, 0xd2, 0x44, 0x42, 0x49, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x07, + 0x01, 0x02, 0x88, 0x53, 0xcc, 0x53, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x02, 0x88, 0x47, 0x21, 0x81, + 0x13, 0x75, 0xf5, 0x0f, 0x82, 0x80, 0x41, 0x11, 0x01, 0x45, 0x81, 0x45, 0x06, 0xc6, 0x22, 0xc4, + 0x26, 0xc2, 0xef, 0xf0, 0x1f, 0xf6, 0xef, 0xf0, 0x9f, 0xfd, 0xaa, 0x84, 0x2e, 0x84, 0x2a, 0x87, + 0xae, 0x86, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0x85, + 0x85, 0x71, 0x13, 0x05, 0x45, 0x64, 0x13, 0x06, 0x06, 0x70, 0xef, 0xd0, 0xaf, 0xc9, 0xa2, 0x85, + 0x22, 0x44, 0xb2, 0x40, 0x26, 0x85, 0x92, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xf3, 0x39, 0x71, + 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0xfa, 0xe9, 0x21, 0xe6, 0x06, 0x84, 0x89, 0xc9, + 0x40, 0xa9, 0x3a, 0xb2, 0xa5, 0x17, 0xf0, 0x91, 0xee, 0xbf, 0x76, 0xa0, 0x8e, 0x35, 0x28, 0x6e, + 0x15, 0xae, 0xa7, 0xba, 0xf5, 0x5e, 0xd0, 0x31, 0x5c, 0x78, 0x4e, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, + 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, + 0xc2, 0x7e, 0xc0, 0xef, 0xf0, 0x7f, 0xf9, 0xef, 0xc0, 0x4f, 0xc9, 0xf2, 0x50, 0xe2, 0x52, 0x52, + 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, + 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, + 0x30, 0x37, 0x07, 0x00, 0x02, 0x5c, 0x47, 0xc9, 0x8f, 0x5c, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, + 0x02, 0xd8, 0x47, 0x13, 0x45, 0xf5, 0xff, 0x79, 0x8d, 0xc8, 0xc7, 0x82, 0x80, 0x37, 0x07, 0x00, + 0x02, 0x1c, 0x4f, 0xc9, 0x8f, 0x1c, 0xcf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0x98, 0x4f, 0x13, + 0x45, 0xf5, 0xff, 0x79, 0x8d, 0x88, 0xcf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0xc8, 0xcb, 0x82, + 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x47, 0x00, 0x1c, 0xc7, 0xb7, 0x07, 0x00, + 0x03, 0x94, 0x4b, 0x37, 0x37, 0x20, 0x00, 0x23, 0x24, 0xd7, 0xfa, 0x23, 0xa8, 0x07, 0x00, 0x82, + 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0xb7, 0x06, 0x00, 0x03, 0xf9, 0x9b, 0x1c, 0xc7, 0x37, + 0x07, 0x08, 0x00, 0x9c, 0x46, 0xf9, 0x8f, 0xf5, 0xff, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, + 0x47, 0x93, 0xe7, 0x17, 0x00, 0x1c, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x87, 0xfa, 0xb7, + 0x07, 0x00, 0x03, 0xfa, 0x95, 0xfb, 0xf0, 0x86, 0x8c, 0x28, 0xbb, 0x4c, 0xec, 0xe8, 0x65, 0xa0, + 0x37, 0xc3, 0x43, 0xc0, 0x5e, 0x9c, 0xbb, 0x07, 0xab, 0xd3, 0x1e, 0x06, 0xe5, 0xe9, 0xf5, 0x57, + 0x28, 0x8e, 0x46, 0xfe, 0x50, 0x4f, 0x98, 0xcb, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, + 0xc7, 0xfa, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0xb7, 0x27, 0x03, 0x04, 0x9c, 0x47, + 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x13, 0x05, + 0x00, 0x10, 0x6f, 0xf0, 0x3f, 0xf4, 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, + 0xf7, 0xfa, 0x41, 0x11, 0x37, 0x37, 0x20, 0x00, 0x23, 0x28, 0xf7, 0xfa, 0x06, 0xc6, 0xef, 0xf0, + 0x1f, 0xfe, 0xb7, 0x27, 0x03, 0x04, 0x09, 0x47, 0xd8, 0xc3, 0x37, 0x17, 0x03, 0x04, 0xb7, 0x07, + 0x03, 0x04, 0x13, 0x07, 0x07, 0x80, 0x23, 0xa0, 0x07, 0x00, 0x91, 0x07, 0xe3, 0x9d, 0xe7, 0xfe, + 0xb7, 0x27, 0x03, 0x04, 0x0d, 0x47, 0xd8, 0xc7, 0x98, 0x47, 0x85, 0x47, 0x13, 0x05, 0xa0, 0x0a, + 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, + 0x00, 0x10, 0x6f, 0xf0, 0xff, 0xee, 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, + 0xf7, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x28, 0xf7, 0xfa, 0xb7, 0x27, 0x03, 0x04, 0x05, 0x47, + 0xd8, 0xc3, 0x82, 0x80, 0xc2, 0x05, 0xc9, 0x8d, 0x93, 0xe5, 0x05, 0x10, 0xb7, 0x07, 0x03, 0x04, + 0x23, 0xa0, 0xb7, 0x10, 0x82, 0x80, 0xc2, 0x05, 0xc9, 0x8d, 0x11, 0x65, 0x13, 0x05, 0x05, 0x50, + 0xc9, 0x8d, 0xb7, 0x07, 0x03, 0x04, 0x23, 0xa0, 0xb7, 0x10, 0x82, 0x80, 0x41, 0x11, 0xfa, 0x3b, + 0x27, 0xae, 0x5e, 0xb8, 0x6d, 0xaf, 0x1c, 0xec, 0x02, 0xd8, 0x56, 0xd6, 0xdf, 0xb4, 0x34, 0xf5, + 0x69, 0x6c, 0x00, 0xa4, 0xbb, 0xc4, 0xe5, 0x6e, 0x2a, 0x70, 0x51, 0x62, 0x4d, 0xdc, 0x5c, 0x28, + 0x50, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xb0, 0x9f, + 0xc4, 0x37, 0x15, 0x03, 0x04, 0x2a, 0x94, 0x08, 0x40, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, + 0x80, 0x79, 0x71, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x06, 0xd6, 0x22, 0xd4, 0xaa, 0x84, 0x2e, + 0x89, 0xb2, 0x89, 0x19, 0xe1, 0xef, 0xb0, 0x1f, 0xc2, 0x93, 0x77, 0x39, 0x00, 0x99, 0xc3, 0xef, + 0xb0, 0x7f, 0xc1, 0x01, 0x44, 0x63, 0x69, 0x34, 0x01, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, + 0x59, 0xf2, 0x49, 0x45, 0x61, 0x82, 0x80, 0x33, 0x05, 0x24, 0x01, 0xef, 0xf0, 0x5f, 0xfa, 0x2a, + 0xc6, 0x11, 0x46, 0x33, 0x85, 0x84, 0x00, 0x6c, 0x00, 0xcd, 0x2d, 0x11, 0x04, 0xe1, 0xbf, 0x79, + 0x71, 0x22, 0xd4, 0x4a, 0xd0, 0x4e, 0xce, 0x56, 0xca, 0x06, 0xd6, 0x26, 0xd2, 0x52, 0xcc, 0x93, + 0x77, 0x35, 0x00, 0x2a, 0x84, 0xae, 0x89, 0x32, 0x89, 0x93, 0x7a, 0xc6, 0xff, 0x99, 0xc3, 0xef, + 0xb0, 0x7f, 0xbc, 0x37, 0x0a, 0x03, 0x04, 0x81, 0x44, 0x22, 0x9a, 0x63, 0xe9, 0x54, 0x03, 0x13, + 0x76, 0x39, 0x00, 0x01, 0xce, 0xb3, 0x85, 0x99, 0x00, 0x68, 0x00, 0x02, 0xc6, 0x7d, 0x25, 0xb2, + 0x47, 0x37, 0x05, 0x03, 0x04, 0x2a, 0x94, 0x26, 0x94, 0x1c, 0xc0, 0xb2, 0x50, 0x22, 0x54, 0x92, + 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0xd2, 0x4a, 0x45, 0x61, 0x82, 0x80, 0x63, 0x94, 0x09, + 0x00, 0xef, 0xb0, 0x5f, 0xb8, 0xb3, 0x85, 0x99, 0x00, 0xfa, 0xc7, 0xa5, 0x70, 0x8e, 0x36, 0xca, + 0xbc, 0x79, 0x52, 0xab, 0xcc, 0xcc, 0xaf, 0xe6, 0x32, 0x83, 0xe5, 0x88, 0xf9, 0x8a, 0x81, 0xbc, + 0x5e, 0xb4, 0xf3, 0xd4, 0xe8, 0xb9, 0xcf, 0x5f, 0x82, 0xe6, 0x00, 0x51, 0x11, 0x46, 0x68, 0x00, + 0xbd, 0x2d, 0x32, 0x47, 0xb3, 0x07, 0x9a, 0x00, 0x91, 0x04, 0x98, 0xc3, 0x4d, 0xbf, 0xaa, 0x85, + 0x37, 0x55, 0x10, 0x00, 0x41, 0x11, 0x13, 0x05, 0x45, 0xb5, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0xd0, + 0xef, 0xe9, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0f, 0xf5, 0x00, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, + 0x13, 0x05, 0x05, 0x72, 0xef, 0xd0, 0x2f, 0xa3, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, + 0x41, 0x01, 0x82, 0x80, 0xb7, 0x17, 0x03, 0x04, 0x83, 0xa7, 0x07, 0x10, 0x37, 0x34, 0x20, 0x00, + 0x13, 0x04, 0x04, 0xfb, 0x93, 0xf7, 0xf7, 0x0f, 0x81, 0xe7, 0x1c, 0x40, 0x63, 0x9d, 0xa7, 0x00, + 0x37, 0x55, 0x10, 0x00, 0x8d, 0x45, 0x13, 0x05, 0x05, 0x72, 0xef, 0xd0, 0xcf, 0x9f, 0x93, 0x07, + 0xa0, 0x0a, 0x1c, 0xc0, 0xd1, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0xc7, 0xfa, 0x13, 0x84, + 0xc7, 0xfa, 0x63, 0x09, 0xa7, 0x00, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0x05, 0x72, + 0xef, 0xd0, 0x6f, 0x9d, 0x08, 0x40, 0x5d, 0xb7, 0x37, 0x95, 0x04, 0x00, 0x13, 0x05, 0x05, 0x3e, + 0x6f, 0xf0, 0xff, 0xf6, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x5f, 0xe6, 0xef, 0xf0, 0x1f, 0xe3, + 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x5f, 0xfe, 0xb7, 0x17, 0x03, 0x04, 0x03, 0xa5, 0x07, 0x10, + 0x41, 0x81, 0x82, 0x80, 0x41, 0x11, 0x3a, 0xc4, 0x37, 0x27, 0x03, 0x04, 0x3e, 0xc2, 0x1c, 0x47, + 0x36, 0xc6, 0x93, 0xf6, 0xfa, 0xec, 0x42, 0x1d, 0xe1, 0x7c, 0xe3, 0x34, 0x80, 0x26, 0x54, 0x32, + 0x5f, 0x6c, 0x88, 0x6d, 0xa4, 0x80, 0xdb, 0x62, 0x99, 0x7b, 0x26, 0x78, 0x02, 0x0d, 0x71, 0x74, + 0xc9, 0x8d, 0xf3, 0xc0, 0xd6, 0xd8, 0x51, 0x27, 0x00, 0x89, 0xca, 0x89, 0x46, 0x14, 0xc7, 0x37, + 0x37, 0x20, 0x00, 0x93, 0x06, 0xa0, 0x0a, 0x23, 0x26, 0xd7, 0xfa, 0x91, 0x8b, 0x99, 0xcf, 0xb7, + 0x27, 0x03, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x93, 0x07, 0xa0, 0x0a, 0x37, 0x37, 0x20, 0x00, 0x23, + 0x28, 0xf7, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0xb2, 0x46, 0x22, 0x47, 0x92, + 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x04, 0x00, 0x03, 0x1c, + 0x48, 0x06, 0xc6, 0xdd, 0x9b, 0x1c, 0xc8, 0xef, 0xe0, 0x0f, 0xd9, 0xb7, 0x07, 0x20, 0x00, 0x93, + 0x87, 0x07, 0x02, 0x5c, 0xcc, 0xb2, 0x40, 0x22, 0x44, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x8c, 0x07, + 0xfa, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x2a, 0x84, 0x21, 0x45, 0x06, 0xc6, 0xef, + 0xf0, 0x7f, 0xca, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x7f, 0xc6, 0x22, 0x04, 0x13, 0x64, 0x04, + 0x03, 0x37, 0x07, 0x00, 0x03, 0x40, 0xc3, 0xb2, 0x40, 0x22, 0x44, 0xc1, 0x67, 0x93, 0x87, 0xa7, + 0xfa, 0x1c, 0xcf, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x26, 0xc2, 0xaa, 0x84, 0x09, 0x45, 0x22, + 0xc4, 0x06, 0xc6, 0x2e, 0x84, 0xef, 0xf0, 0x1f, 0xfc, 0x37, 0x07, 0x20, 0x00, 0xb7, 0x07, 0x00, + 0x03, 0x13, 0x07, 0x07, 0x02, 0xd8, 0xcf, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2a, 0x97, 0xfa, 0x37, + 0x37, 0x20, 0x00, 0x23, 0x2e, 0x87, 0xfa, 0xb2, 0x40, 0x22, 0x44, 0x05, 0x47, 0x98, 0xcb, 0xfa, + 0xa7, 0x12, 0x8f, 0xd2, 0xc8, 0x61, 0x87, 0x7d, 0xa1, 0x71, 0x61, 0x90, 0xb6, 0x21, 0x51, 0x78, + 0xc2, 0x56, 0x74, 0xce, 0x9b, 0xd5, 0xd8, 0x59, 0x8d, 0xf3, 0x9b, 0xc6, 0xd3, 0xb7, 0x73, 0x4f, + 0xb0, 0x52, 0x37, 0x07, 0x08, 0x00, 0x98, 0xc7, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, + 0x00, 0x03, 0x9c, 0x47, 0x37, 0x07, 0x04, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x99, 0xe3, + 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x37, 0x07, 0x00, 0x03, 0x5c, 0x53, 0x13, 0x05, 0x50, 0x05, + 0x93, 0x96, 0x07, 0x01, 0xc1, 0x82, 0xc1, 0x83, 0x63, 0x97, 0xf6, 0x00, 0x1c, 0x47, 0x91, 0x8b, + 0x99, 0xe3, 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xff, 0xf1, + 0x37, 0x07, 0x00, 0x03, 0x5c, 0x47, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc7, 0x5c, 0x47, 0x85, 0x8b, + 0xf5, 0xff, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xfb, + 0x95, 0xc3, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x5f, 0xef, 0xb7, 0x07, 0x00, 0x03, 0x98, 0x4b, + 0xb2, 0x40, 0x13, 0x67, 0x87, 0x00, 0x98, 0xcb, 0x37, 0x07, 0x08, 0x00, 0x98, 0xc7, 0x41, 0x01, + 0x6f, 0xe0, 0xcf, 0xc5, 0x82, 0x80, 0x37, 0x07, 0x00, 0x03, 0x1c, 0x4b, 0xf9, 0x9b, 0x1c, 0xcb, + 0x82, 0x80, 0xb7, 0x06, 0x00, 0x03, 0xdc, 0x42, 0x7d, 0x77, 0x13, 0x07, 0xf7, 0x0f, 0xf9, 0x8f, + 0x05, 0x67, 0x22, 0x05, 0x13, 0x07, 0x07, 0xf0, 0x79, 0x8d, 0x5d, 0x8d, 0xc8, 0xc2, 0x82, 0x80, + 0x1d, 0x71, 0x3a, 0xda, 0x37, 0x07, 0x00, 0x03, 0x3e, 0xd8, 0x1c, 0x47, 0x86, 0xce, 0x96, 0xcc, + 0x9a, 0xca, 0x9e, 0xc8, 0xa2, 0xc6, 0xa6, 0xc4, 0xaa, 0xc2, 0xfa, 0xed, 0xed, 0xe1, 0x01, 0xe8, + 0xc4, 0xe4, 0xc5, 0x64, 0x65, 0x42, 0xc9, 0xb4, 0x83, 0x9c, 0x76, 0x94, 0xef, 0x48, 0xca, 0x46, + 0xaa, 0x52, 0x7d, 0x52, 0x28, 0xc4, 0xb9, 0xe0, 0x99, 0x35, 0x07, 0x88, 0x53, 0xae, 0xc0, 0x32, + 0xde, 0x36, 0xdc, 0x42, 0xd6, 0x46, 0xd4, 0x4a, 0xd2, 0x4e, 0xd0, 0x72, 0xce, 0x76, 0xcc, 0x7a, + 0xca, 0x7e, 0xc8, 0x85, 0x8b, 0xa1, 0xc7, 0x04, 0x57, 0x11, 0x44, 0x37, 0x39, 0x20, 0x00, 0x83, + 0x27, 0x49, 0xfb, 0x13, 0xf5, 0xf4, 0x0f, 0x7d, 0x14, 0x82, 0x97, 0xa1, 0x80, 0x6d, 0xf8, 0x36, + 0x44, 0xf6, 0x40, 0xe6, 0x42, 0x56, 0x43, 0xc6, 0x43, 0xa6, 0x44, 0x16, 0x45, 0x86, 0x45, 0x72, + 0x56, 0xe2, 0x56, 0x52, 0x57, 0xc2, 0x57, 0x32, 0x58, 0xa2, 0x58, 0x12, 0x59, 0x82, 0x59, 0x72, + 0x4e, 0xe2, 0x4e, 0x52, 0x4f, 0xc2, 0x4f, 0x25, 0x61, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x37, 0x20, + 0x00, 0x03, 0xc7, 0x87, 0xfb, 0x13, 0x84, 0x87, 0xfb, 0x05, 0xeb, 0xb7, 0x04, 0x00, 0x03, 0x37, + 0x39, 0x20, 0x00, 0x93, 0x09, 0xa0, 0x0a, 0x9c, 0x44, 0x91, 0x8b, 0xd5, 0xfb, 0x83, 0x27, 0xc9, + 0xfb, 0x68, 0x00, 0x82, 0x97, 0x63, 0x0d, 0x35, 0x01, 0x85, 0x47, 0x23, 0x00, 0xf4, 0x00, 0xc1, + 0x67, 0x93, 0x87, 0x07, 0x02, 0xdc, 0xcc, 0x61, 0xbf, 0xef, 0xf0, 0x5f, 0xdf, 0x49, 0xbf, 0xb2, + 0x47, 0x9c, 0xd8, 0xd1, 0xbf, 0x5c, 0x41, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc1, 0x82, 0x80, 0x5c, + 0x41, 0xf9, 0x9b, 0x5c, 0xc1, 0x82, 0x80, 0x5c, 0x41, 0xf5, 0x9b, 0xd1, 0x8f, 0x5c, 0xc1, 0x14, + 0xc9, 0x4c, 0xc9, 0x82, 0x80, 0x5c, 0x45, 0xcd, 0x8f, 0x5c, 0xc5, 0x82, 0x80, 0xb7, 0x37, 0x20, + 0x00, 0x03, 0xa5, 0x07, 0xfc, 0xfa, 0x9f, 0xa6, 0x16, 0xa0, 0xa2, 0xa7, 0xcd, 0x18, 0x6a, 0x30, + 0x34, 0x43, 0x0f, 0x18, 0x91, 0xec, 0xab, 0x4e, 0x13, 0xb4, 0xe1, 0x03, 0x40, 0x5e, 0x56, 0x1b, + 0x89, 0x18, 0x8b, 0x78, 0x55, 0x00, 0x60, 0x54, 0x82, 0x80, 0x39, 0x71, 0x3a, 0xce, 0x37, 0x07, + 0x10, 0x01, 0x3e, 0xcc, 0x1c, 0x47, 0x58, 0x47, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, + 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, + 0x7a, 0xc2, 0x7e, 0xc0, 0xf9, 0x8f, 0x91, 0xcf, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xfc, + 0x98, 0x43, 0x05, 0x07, 0x98, 0xc3, 0xb7, 0x07, 0x10, 0x01, 0x98, 0x47, 0x0d, 0x8b, 0x98, 0xc7, + 0x19, 0xa8, 0xb7, 0x07, 0x20, 0x01, 0x98, 0x47, 0xdc, 0x47, 0x7d, 0x8f, 0xb7, 0x07, 0x20, 0x01, + 0x6d, 0xf7, 0xef, 0xb0, 0xff, 0xe6, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, + 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, + 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x1c, 0x41, 0x63, 0xf7, + 0xb7, 0x00, 0x23, 0x80, 0xc7, 0x00, 0x1c, 0x41, 0x85, 0x07, 0x1c, 0xc1, 0x82, 0x80, 0x1d, 0x71, + 0xa2, 0xcc, 0xa6, 0xca, 0xca, 0xc8, 0x86, 0xce, 0xce, 0xc6, 0xd2, 0xc4, 0xd6, 0xc2, 0xda, 0xc0, + 0x5e, 0xde, 0x62, 0xdc, 0x66, 0xda, 0x6a, 0xd8, 0x6e, 0xd6, 0x2a, 0xc6, 0x2e, 0x84, 0x32, 0x89, + 0xb6, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x0f, 0xf6, 0x63, 0x14, 0x09, 0x00, 0xef, 0xb0, 0x8f, 0xf5, + 0x01, 0x45, 0x05, 0xc4, 0xb2, 0x4a, 0x7d, 0x14, 0x25, 0x4a, 0x56, 0x94, 0x93, 0x0c, 0xc0, 0x06, + 0xfa, 0x78, 0xb3, 0xf1, 0xdd, 0xc5, 0x13, 0x54, 0x08, 0x05, 0xc9, 0x57, 0xa0, 0x7d, 0x61, 0x7f, + 0x3c, 0x03, 0xc6, 0x40, 0x73, 0xd2, 0x7c, 0x9a, 0xf2, 0xd5, 0x07, 0x3d, 0x6c, 0x0e, 0xe4, 0x7c, + 0x6f, 0x38, 0x55, 0x13, 0x0b, 0x30, 0x07, 0xa9, 0x4b, 0x1d, 0x4d, 0x03, 0x46, 0x09, 0x00, 0x15, + 0xe6, 0xb2, 0x47, 0x23, 0x80, 0x07, 0x00, 0x32, 0x45, 0x33, 0x05, 0x55, 0x41, 0xf6, 0x40, 0x66, + 0x44, 0xd6, 0x44, 0x46, 0x49, 0xb6, 0x49, 0x26, 0x4a, 0x96, 0x4a, 0x06, 0x4b, 0xf2, 0x5b, 0x62, + 0x5c, 0xd2, 0x5c, 0x42, 0x5d, 0xb2, 0x5d, 0x25, 0x61, 0x82, 0x80, 0x93, 0x07, 0x50, 0x02, 0x63, + 0x1f, 0xf6, 0x02, 0x93, 0x07, 0x19, 0x00, 0x83, 0xc6, 0x07, 0x00, 0x3e, 0x89, 0x85, 0x07, 0x13, + 0x87, 0x06, 0xfd, 0x13, 0x77, 0xf7, 0x0f, 0xe3, 0x78, 0xea, 0xfe, 0x63, 0x93, 0x96, 0x01, 0x3e, + 0x89, 0x03, 0x46, 0x09, 0x00, 0x63, 0x06, 0x66, 0x0d, 0x63, 0x60, 0xcb, 0x02, 0x93, 0x07, 0x30, + 0x06, 0x63, 0x05, 0xf6, 0x06, 0x93, 0x07, 0x40, 0x06, 0x63, 0x0c, 0xf6, 0x06, 0xa2, 0x85, 0x68, + 0x00, 0xef, 0xf0, 0xff, 0xf2, 0xa6, 0x89, 0x95, 0xa0, 0x93, 0x07, 0x50, 0x07, 0x63, 0x02, 0xf6, + 0x06, 0x93, 0x07, 0x80, 0x07, 0xe3, 0x14, 0xf6, 0xfe, 0x98, 0x40, 0x93, 0x89, 0x44, 0x00, 0x81, + 0x46, 0x37, 0x06, 0x00, 0xf0, 0xb3, 0x75, 0xc7, 0x00, 0xba, 0x84, 0x36, 0x8c, 0x12, 0x07, 0x85, + 0x06, 0x89, 0xe5, 0xe3, 0x99, 0xa6, 0xff, 0x1d, 0x4c, 0xba, 0x84, 0xa1, 0x4d, 0x13, 0xd7, 0xc4, + 0x01, 0x63, 0x74, 0xea, 0x08, 0x13, 0x06, 0x77, 0x05, 0xa2, 0x85, 0x68, 0x00, 0x05, 0x0c, 0xef, + 0xf0, 0x1f, 0xee, 0x92, 0x04, 0xe3, 0x14, 0xbc, 0xff, 0x09, 0xa8, 0xfa, 0xd5, 0xda, 0x2e, 0x8e, + 0x22, 0x59, 0xac, 0x83, 0x89, 0x57, 0x76, 0x65, 0x16, 0xb6, 0x2b, 0xd5, 0xca, 0xc5, 0x22, 0x0a, + 0x1f, 0x76, 0x8a, 0xb1, 0x0a, 0xac, 0xcd, 0x33, 0x87, 0x5d, 0x8c, 0xfd, 0x10, 0x56, 0x03, 0xc6, + 0x04, 0x00, 0xa2, 0x85, 0x68, 0x00, 0x93, 0x89, 0x44, 0x00, 0xef, 0xf0, 0x9f, 0xec, 0x05, 0x09, + 0xce, 0x84, 0x31, 0xbf, 0x5c, 0x08, 0x98, 0x40, 0x93, 0x89, 0x44, 0x00, 0x3e, 0x8c, 0x81, 0x44, + 0xb3, 0x76, 0x77, 0x03, 0x85, 0x04, 0x85, 0x07, 0x93, 0x86, 0x06, 0x03, 0xa3, 0x8f, 0xd7, 0xfe, + 0xba, 0x86, 0x33, 0x57, 0x77, 0x03, 0xe3, 0x65, 0xda, 0xfe, 0xfd, 0x5d, 0xfd, 0x14, 0xe3, 0x88, + 0xb4, 0xfd, 0xb3, 0x07, 0x9c, 0x00, 0x03, 0xc6, 0x07, 0x00, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, + 0x5f, 0xe8, 0xed, 0xb7, 0x93, 0x89, 0x44, 0x00, 0x84, 0x40, 0x03, 0xc6, 0x04, 0x00, 0x45, 0xda, + 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, 0xe6, 0x85, 0x04, 0xc5, 0xbf, 0x13, 0x06, 0x07, 0x03, + 0xb5, 0xbf, 0x41, 0x11, 0x26, 0xc2, 0xb7, 0x34, 0x20, 0x00, 0x2a, 0x86, 0xae, 0x86, 0x13, 0x85, + 0x84, 0xea, 0x93, 0x05, 0x00, 0x08, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0xf0, 0xbf, 0xe5, 0x2a, 0x84, + 0x13, 0x85, 0x84, 0xea, 0xef, 0xd0, 0x8f, 0x9b, 0xb2, 0x40, 0x22, 0x85, 0x22, 0x44, 0x92, 0x44, + 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x26, 0xca, 0xb7, 0x34, 0x20, 0x00, 0x2e, 0xd2, 0x32, 0xd4, + 0x36, 0xd6, 0x2a, 0x86, 0x54, 0x10, 0x93, 0x05, 0x00, 0x08, 0x13, 0x85, 0x84, 0xea, 0x06, 0xce, + 0x22, 0xcc, 0x3a, 0xd8, 0x3e, 0xda, 0x42, 0xdc, 0x46, 0xde, 0x36, 0xc6, 0xef, 0xf0, 0x9f, 0xe1, + 0x2a, 0x84, 0x13, 0x85, 0x84, 0xea, 0xfa, 0x4f, 0x82, 0xf5, 0x7e, 0x43, 0x23, 0x29, 0xf0, 0x77, + 0x76, 0x2c, 0x66, 0x4c, 0xce, 0x3a, 0x5b, 0x6a, 0xba, 0x96, 0xfc, 0x39, 0xc3, 0xa7, 0x0e, 0xd2, + 0xdf, 0xed, 0xb7, 0x03, 0x5c, 0x83, 0x12, 0xe8, 0x56, 0xef, 0xd0, 0x6f, 0x97, 0xf2, 0x40, 0x22, + 0x85, 0x62, 0x44, 0xd2, 0x44, 0x21, 0x61, 0x82, 0x80, 0x22, 0x05, 0x61, 0x77, 0x2d, 0x8d, 0xa1, + 0x47, 0x15, 0x07, 0x93, 0x16, 0x05, 0x01, 0x06, 0x05, 0x42, 0x05, 0xc1, 0x86, 0x41, 0x81, 0x63, + 0xd5, 0x06, 0x00, 0x39, 0x8d, 0x42, 0x05, 0x41, 0x81, 0xfd, 0x17, 0xe5, 0xf7, 0x82, 0x80, 0x41, + 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x2a, 0x84, 0xb3, 0x04, 0xb5, 0x00, 0x06, 0xc6, 0x01, 0x45, 0x63, + 0x97, 0x84, 0x00, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x04, 0xaa, + 0x85, 0x03, 0x45, 0xf4, 0xff, 0xef, 0xf0, 0x5f, 0xfb, 0xdd, 0xb7, 0xb7, 0x86, 0xb8, 0xed, 0x01, + 0x47, 0xfd, 0x57, 0x93, 0x86, 0x06, 0x32, 0x63, 0x15, 0xb7, 0x00, 0x13, 0xc5, 0xf7, 0xff, 0x82, + 0x80, 0x33, 0x06, 0xe5, 0x00, 0x03, 0x46, 0x06, 0x00, 0xb1, 0x8f, 0x21, 0x46, 0x13, 0xd8, 0x17, + 0x00, 0x85, 0x8b, 0x91, 0xc3, 0xb6, 0x87, 0x7d, 0x16, 0xb3, 0x47, 0xf8, 0x00, 0x65, 0xfa, 0x05, + 0x07, 0xd9, 0xbf, 0x2a, 0x83, 0x09, 0xca, 0x83, 0x83, 0x05, 0x00, 0x23, 0x00, 0x73, 0x00, 0x7d, + 0x16, 0x05, 0x03, 0x85, 0x05, 0x6d, 0xfa, 0x82, 0x80, 0x15, 0xc2, 0x2a, 0x83, 0x85, 0x46, 0x63, + 0x67, 0xb5, 0x00, 0xfd, 0x56, 0x13, 0x07, 0xf6, 0xff, 0x3a, 0x93, 0xba, 0x95, 0x83, 0x83, 0x05, + 0x00, 0x23, 0x00, 0x73, 0x00, 0x7d, 0x16, 0x36, 0x93, 0xb6, 0x95, 0x6d, 0xfa, 0x82, 0x80, 0x2a, + 0x83, 0xfa, 0xa6, 0xc8, 0xcd, 0xda, 0xc8, 0x00, 0x98, 0xe6, 0xa6, 0x42, 0x5e, 0x14, 0x62, 0xa7, + 0xc7, 0xaa, 0x0d, 0xc7, 0x0f, 0xde, 0x0f, 0xdc, 0x00, 0x91, 0x22, 0xa1, 0xea, 0x24, 0x09, 0x49, + 0x80, 0xd4, 0xc0, 0x57, 0x11, 0xc6, 0x23, 0x00, 0xb3, 0x00, 0x7d, 0x16, 0x05, 0x03, 0x65, 0xfe, + 0x82, 0x80, 0x00, 0x00, 0x63, 0x6f, 0x64, 0x65, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, + 0x53, 0x45, 0x43, 0x43, 0x48, 0x4e, 0x4c, 0x00, 0x4d, 0x43, 0x4e, 0x54, 0x00, 0x00, 0x00, 0x00, + 0x54, 0x58, 0x3a, 0x20, 0x25, 0x64, 0x2f, 0x25, 0x64, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, + 0x43, 0x4d, 0x44, 0x33, 0x00, 0x00, 0x00, 0x00, 0x49, 0x00, 0x00, 0x00, 0x65, 0x6e, 0x61, 0x62, + 0x6c, 0x65, 0x64, 0x20, 0x25, 0x64, 0x00, 0x00, 0x4d, 0x41, 0x49, 0x4e, 0x00, 0x00, 0x00, 0x00, + 0x6c, 0x65, 0x6e, 0x20, 0x25, 0x64, 0x2f, 0x25, 0x64, 0x00, 0x00, 0x00, 0x72, 0x73, 0x70, 0x3d, + 0x25, 0x78, 0x00, 0x00, 0x73, 0x74, 0x61, 0x72, 0x74, 0x2c, 0x20, 0x76, 0x25, 0x75, 0x2e, 0x25, + 0x75, 0x2e, 0x25, 0x75, 0x00, 0x00, 0x00, 0x00, 0x50, 0x52, 0x4f, 0x56, 0x49, 0x53, 0x49, 0x4f, + 0x4e, 0x20, 0x4f, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x4e, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, + 0x43, 0x50, 0x42, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x4c, 0x33, 0x20, 0x63, 0x6d, 0x64, 0x20, 0x25, + 0x64, 0x3a, 0x20, 0x25, 0x78, 0x2c, 0x20, 0x6c, 0x65, 0x6e, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x00, + 0x4c, 0x33, 0x20, 0x61, 0x63, 0x63, 0x65, 0x73, 0x73, 0x20, 0x66, 0x61, 0x69, 0x6c, 0x65, 0x64, + 0x2c, 0x20, 0x63, 0x6d, 0x64, 0x3a, 0x20, 0x25, 0x64, 0x2c, 0x20, 0x6c, 0xfa, 0x53, 0x55, 0xdd, + 0x52, 0x34, 0x63, 0x1c, 0x99, 0x07, 0xfe, 0xe1, 0x96, 0x57, 0xc6, 0xb2, 0x75, 0x87, 0xef, 0x27, + 0x44, 0x95, 0xe6, 0x44, 0x00, 0xd6, 0x11, 0xa1, 0xc2, 0x85, 0x14, 0xcc, 0xcb, 0x98, 0x58, 0x65, + 0x6e, 0x3a, 0x20, 0x25, 0x64, 0x20, 0x00, 0x70, 0x69, 0x6e, 0x67, 0x2c, 0x20, 0x6c, 0x3d, 0x25, + 0x64, 0x00, 0x00, 0x4c, 0x33, 0x00, 0x00, 0x57, 0x52, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x00, 0x52, + 0x44, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x00, 0x6d, 0x61, 0x63, 0x61, 0x6e, 0x64, 0x64, 0x2c, 0x20, + 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x00, 0x00, 0x73, 0x65, 0x6e, 0x74, 0x00, 0x00, 0x00, 0x00, 0x65, + 0x6e, 0x74, 0x65, 0x72, 0x20, 0x73, 0x6c, 0x65, 0x65, 0x70, 0x00, 0x77, 0x61, 0x6b, 0x65, 0x75, + 0x70, 0x00, 0x00, 0x56, 0x19, 0x10, 0x00, 0x94, 0x19, 0x10, 0x00, 0xc0, 0x19, 0x10, 0x00, 0xf0, + 0x19, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, + 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, + 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, + 0x13, 0x10, 0x00, 0x0a, 0x1a, 0x10, 0x00, 0x64, 0x1a, 0x10, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + 0x00, 0x00, 0x00, 0x80, 0x1f, 0x00, 0x06, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0xa0, + 0x1f, 0x00, 0x06, 0x02, 0x00, 0x05, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x06, 0x03, + 0x10, 0x08, 0x00, 0x00, 0x18, 0x00, 0x00, 0x40, 0x1f, 0x00, 0x06, 0x06, 0x10, 0x08, 0x00, 0x04, + 0x18, 0x00, 0x00, 0x60, 0x1f, 0x00, 0x06, 0xfa, 0x85, 0xe0, 0x36, 0x11, 0x49, 0x41, 0x92, 0x3d, + 0x86, 0xd4, 0x75, 0x3a, 0x7c, 0x31, 0xcc, 0x20, 0x59, 0x14, 0x0a, 0x95, 0xba, 0x92, 0xba, 0x8e, + 0x4f, 0x7a, 0xec, 0x60, 0xd3, 0x0c, 0x3a, 0xcf, 0x70, 0x59, 0x04, 0x00, 0x09, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x80, 0x06, 0x05, 0x05, 0x7f, 0x07, 0x01, 0x08, 0x18, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x01, 0xf0, 0x01, 0x10, 0x10, 0x00, 0x04, 0x02, 0x11, 0x00, 0x44, 0x02, 0x12, 0x00, + 0x84, 0x02, 0x20, 0x90, 0x01, 0x03, 0x21, 0x80, 0x42, 0x03, 0x22, 0xf0, 0x01, 0x03, 0x30, 0x80, + 0x02, 0x04, 0x31, 0x80, 0x42, 0x04, 0x40, 0x70, 0x04, 0x11, 0x41, 0x70, 0x44, 0x11, 0x42, 0x70, + 0x84, 0x11, 0x50, 0xf0, 0x01, 0x12, 0x60, 0x32, 0x04, 0x13, 0x61, 0x32, 0x44, 0x13, 0x62, 0x32, + 0x84, 0x13, 0x63, 0x32, 0xc4, 0x13, 0x70, 0x32, 0x04, 0x14, 0x71, 0x32, 0x44, 0x14, 0x80, 0x20, + 0x04, 0x15, 0x81, 0x20, 0x84, 0x15, 0x82, 0x20, 0x44, 0x15, 0x90, 0x51, 0x04, 0x16, 0x00, 0x00, + 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x14, 0x04, 0x04, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x23, 0x20, 0x25, 0x6c, 0x75, 0x20, 0x00, 0x00, 0x25, 0x73, 0x28, 0x25, 0x73, 0x29, + 0x3a, 0x20, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x45, 0x00, 0x00, 0x00, 0x4d, 0x53, + 0x47, 0x00, 0x43, 0x52, 0x43, 0x20, 0x72, 0x78, 0x3a, 0x20, 0x25, 0x30, 0x34, 0x78, 0x2c, 0x20, + 0x63, 0x61, 0x6c, 0x63, 0x3a, 0x20, 0x25, 0x30, 0x34, 0x78, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, + 0x00, 0x00, 0xfa, 0xab, 0xdf, 0x5f, 0xff, 0xec, 0xf4, 0xbc, 0x19, 0x3c, 0xb2, 0x93, 0x30, 0x2f, + 0x7d, 0x58, 0xe6, 0x85, 0xd3, 0x3d, 0x95, 0xc9, 0x91, 0x95, 0x01, 0x02, 0xfd, 0x7a, 0xb9, 0x0c, + 0x61, 0x3e, 0x85, 0x48, 0x5a, 0xe4, 0x1f, 0x10, 0x00, 0x04, 0x20, 0x10, 0x00, 0x56, 0x20, 0x10, + 0x00, 0xb8, 0x20, 0x10, 0x00, 0xc2, 0x20, 0x10, 0x00, 0x4f, 0x53, 0x00, 0x00, 0x63, 0x6f, 0x6e, + 0x64, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, 0x52, 0x58, 0x3a, 0x20, 0x63, 0x6d, 0x64, + 0x3d, 0x30, 0x78, 0x25, 0x30, 0x32, 0x78, 0x00, 0x00, 0x55, 0x49, 0x00, 0x00, 0x43, 0x50, 0x42, + 0x20, 0x49, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x20, 0x21, 0x00, 0x43, 0x50, 0x42, + 0x00, 0x57, 0x00, 0x00, 0x00, 0x46, 0x53, 0x53, 0x00, 0x49, 0x52, 0x51, 0x00, 0x53, 0x54, 0x3a, + 0x20, 0x25, 0x78, 0x00, 0x00, 0x4b, 0x44, 0x42, 0x00, 0x73, 0x74, 0x3a, 0x20, 0x25, 0x78, 0x00, + 0x00, 0x4d, 0x41, 0x44, 0x00, 0x4f, 0x54, 0x50, 0x00, 0x01, 0x00, 0x00, 0x00, 0x53, 0x43, 0x42, + 0x00, 0x4e, 0x6f, 0x69, 0x73, 0x65, 0x5f, 0x4b, 0x4b, 0x31, 0x5f, 0x32, 0x35, 0x35, 0x31, 0x39, + 0x5f, 0x41, 0x45, 0x53, 0x47, 0x43, 0x4d, 0x5f, 0x53, 0x48, 0x41, 0x32, 0x35, 0x36, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x3f, 0x10, 0x00, 0x78, 0x45, 0x10, 0x00, 0x62, 0x45, 0x10, + 0x00, 0x26, 0x45, 0x10, 0x00, 0x3a, 0x3e, 0x10, 0x00, 0xd0, 0x45, 0x10, 0x00, 0x41, 0x4c, 0x41, + 0x52, 0x4d, 0x20, 0x43, 0x48, 0x41, 0x4e, 0x4e, 0x45, 0x4c, 0x53, 0x3a, 0x20, 0x25, 0x78, 0x20, + 0x25, 0x78, 0x00, 0x00, 0x00, 0x53, 0x43, 0x4e, 0x54, 0x52, 0x00, 0x00, 0x00, 0x2e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x5b, + 0x53, 0x50, 0x45, 0x43, 0x54, 0x00, 0x00, 0x00, 0xc3, 0x14, 0x13, 0x00}; \ No newline at end of file diff --git a/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_1_0_0/fw_SPECT.h b/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_1_0_0/fw_SPECT.h index be96766d7..479502e04 100644 --- a/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_1_0_0/fw_SPECT.h +++ b/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_1_0_0/fw_SPECT.h @@ -5,648 +5,769 @@ /** * @brief SPECT firmware version spect_app-v1.0.0_signed_chunks.bin for bootloader v2.0.1 */ -const uint8_t fw_SPECT[] - = {0x68, 0xab, 0xf0, 0xa7, 0x7a, 0x50, 0xce, 0xdd, 0x55, 0x3d, 0xb0, 0xf1, 0x76, 0x9f, 0xcb, 0x6a, 0x67, 0xf5, 0xcb, - 0xfc, 0x24, 0x76, 0xb2, 0x52, 0xa0, 0x4a, 0x8d, 0xe5, 0x2d, 0xd4, 0x2e, 0x89, 0x4d, 0xf6, 0xbd, 0xc0, 0xe0, 0xc7, - 0x95, 0x13, 0x72, 0xad, 0xcc, 0x48, 0x86, 0x3a, 0x7d, 0xda, 0x6b, 0x8b, 0x3f, 0x1a, 0x86, 0x84, 0x61, 0xc9, 0x13, - 0x79, 0x51, 0x2b, 0x3f, 0x75, 0xa9, 0xe4, 0x0c, 0x48, 0x5d, 0xf0, 0x6b, 0x12, 0x14, 0x52, 0x77, 0x96, 0x33, 0xba, - 0x34, 0x28, 0xeb, 0x80, 0x57, 0x3d, 0x94, 0xe6, 0x34, 0x7c, 0x70, 0x56, 0xa8, 0x01, 0x2f, 0xe5, 0x0f, 0x7f, 0x4e, - 0x2f, 0x1c, 0x02, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0xfa, 0xfa, 0xe4, 0x4c, 0x3f, 0x09, 0x0c, 0xec, 0x1f, - 0xdc, 0x76, 0xd8, 0x51, 0x17, 0xaf, 0x15, 0x9b, 0x29, 0xc6, 0xbd, 0xa7, 0xf6, 0x75, 0xb3, 0x5c, 0xa0, 0xcf, 0x68, - 0xc0, 0xee, 0x2a, 0x8e, 0x6c, 0x00, 0x00, 0x2f, 0x82, 0xf0, 0xe9, 0x8a, 0x1d, 0xf3, 0x23, 0x8f, 0x1d, 0xac, 0x6f, - 0x9d, 0xd2, 0x9c, 0x27, 0x32, 0x09, 0x47, 0xf5, 0x59, 0xf3, 0x54, 0x5b, 0xbf, 0x4f, 0x8b, 0x45, 0x79, 0xa9, 0x37, - 0x1e, 0x57, 0xd4, 0x61, 0xa1, 0xa2, 0x21, 0xea, 0x64, 0x27, 0x05, 0xfd, 0x23, 0xa6, 0x3f, 0x98, 0x2a, 0x8c, 0xd9, - 0x68, 0xa0, 0x93, 0x96, 0x98, 0xba, 0x72, 0x85, 0x9c, 0x02, 0x07, 0xc2, 0x59, 0x0e, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x2d, 0xfa, 0x3e, 0x5e, - 0x5f, 0xe0, 0xdf, 0xbf, 0xea, 0x93, 0xdd, 0x0a, 0x41, 0xd8, 0xbb, 0x82, 0x31, 0x51, 0x8d, 0x90, 0xae, 0x64, 0xf2, - 0x61, 0x7e, 0x01, 0xd8, 0x57, 0x83, 0x64, 0x69, 0xd8, 0xd8, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, - 0x9a, 0x9a, 0x06, 0x43, 0x2c, 0x84, 0x2b, 0x3f, 0x4a, 0x63, 0x9c, 0x51, 0xdc, 0x7b, 0x63, 0x33, 0x70, 0xac, 0x17, - 0xfc, 0xd4, 0xca, 0x19, 0x9e, 0xf9, 0xbd, 0x20, 0xba, 0x5f, 0xff, 0x8d, 0x73, 0xb0, 0x01, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0x02, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0xa8, 0x24, 0x00, 0x00, 0xd4, 0x7d, 0x50, 0x04, 0x3e, 0x76, 0xee, - 0xe1, 0x59, 0xcb, 0x26, 0x98, 0xc7, 0x25, 0x91, 0xb2, 0x59, 0xdd, 0x1c, 0xf0, 0x9e, 0xef, 0xd3, 0x1c, 0x5d, 0xb6, - 0x34, 0xbb, 0x20, 0xd4, 0x52, 0x09, 0xd2, 0x56, 0xbf, 0xa0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xfa, 0xfd, 0x93, 0x16, 0x38, 0x91, 0xe1, 0x51, 0x15, 0xde, 0x7f, 0x92, 0x54, 0xb7, 0xfa, 0xba, - 0xab, 0x86, 0xa5, 0x37, 0x39, 0x3b, 0xab, 0xda, 0x0e, 0x7d, 0xd4, 0x61, 0xa9, 0xdb, 0xfb, 0x4e, 0x57, 0x88, 0x02, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x9f, 0x03, 0xfd, 0x15, 0xcd, 0x52, 0x37, 0x43, 0x12, 0xa7, 0x47, - 0xf3, 0x4c, 0x08, 0x25, 0x5f, 0x01, 0xc0, 0xf9, 0x27, 0x07, 0x7a, 0x05, 0x70, 0x44, 0xae, 0xf1, 0x53, 0xae, 0xdd, - 0x90, 0xee, 0x60, 0x03, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x7e, 0xa3, 0xe4, 0xa3, 0x00, - 0x82, 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, 0x40, 0xa2, 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0x82, 0x62, 0xf0, 0x10, - 0x88, 0xa2, 0x20, 0x33, 0x4a, 0xc5, 0x00, 0x10, 0x40, 0x28, 0x2c, 0xa3, 0x00, 0x08, 0x60, 0x40, 0x40, 0x28, 0x4c, - 0x80, 0x00, 0x88, 0x10, 0x40, 0x40, 0xa8, 0x84, 0x80, 0x00, 0x08, 0xfa, 0xd3, 0x0b, 0x9a, 0xa9, 0x26, 0x2d, 0x4c, - 0xa8, 0x2c, 0xbb, 0x5e, 0x96, 0xf9, 0x73, 0x44, 0x7b, 0x04, 0x8d, 0x06, 0x97, 0x98, 0x1a, 0xc8, 0x58, 0xce, 0xc2, - 0x62, 0x43, 0x93, 0xb6, 0xe6, 0xc4, 0x38, 0x04, 0x40, 0x40, 0x40, 0xa8, 0xb8, 0x80, 0x00, 0x08, 0x70, 0x40, 0x40, - 0xa8, 0x20, 0x81, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0x04, 0xa4, 0x00, 0x82, 0xf4, 0x50, 0x8a, 0x24, 0x00, 0x50, - 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x60, 0x10, 0x40, 0x28, 0x1c, 0x9f, 0x00, 0x08, 0x61, 0x10, 0x40, 0xa8, 0x1c, - 0x9f, 0x00, 0x08, 0x62, 0x10, 0x40, 0xa8, 0xa4, 0x9f, 0x00, 0x08, 0x63, 0x10, 0x40, 0x28, 0xb0, 0xa0, 0x00, 0x08, - 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0xf3, 0x50, 0x8a, 0xa4, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, - 0x49, 0x11, 0x10, 0x40, 0x28, 0x60, 0xa2, 0x00, 0x08, 0x12, 0x10, 0x40, 0x28, 0x9c, 0xa2, 0x00, 0x08, 0x13, 0x10, - 0x40, 0xa8, 0xbc, 0xa2, 0x00, 0x88, 0x14, 0x10, 0x40, 0x28, 0xe0, 0xa2, 0x00, 0x88, 0x40, 0x81, 0x00, 0x98, 0xa8, - 0xa4, 0x00, 0x18, 0x04, 0xa4, 0x00, 0x82, 0xf2, 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, - 0x41, 0x10, 0x40, 0x28, 0x94, 0x8f, 0x00, 0x88, 0x42, 0x10, 0x40, 0x28, 0xac, 0x90, 0x00, 0x88, 0x43, 0x10, 0x40, - 0xa8, 0xd4, 0x90, 0x00, 0x88, 0x44, 0x10, 0x40, 0x28, 0x04, 0x91, 0x00, 0x88, 0x45, 0x10, 0x40, 0xa8, 0xfc, 0x91, - 0x00, 0x08, 0x46, 0x10, 0x40, 0xa8, 0xa0, 0x92, 0x00, 0x08, 0x47, 0x10, 0x40, 0x28, 0xf4, 0x92, 0x00, 0x88, 0x48, - 0x10, 0x40, 0x28, 0x30, 0x93, 0x00, 0x88, 0x49, 0x10, 0x40, 0xa8, 0x48, 0x93, 0x00, 0x88, 0xfa, 0xdd, 0x34, 0x32, - 0x10, 0xea, 0xae, 0x70, 0x34, 0x9b, 0x88, 0xd3, 0xdf, 0x44, 0xa4, 0xb5, 0xb9, 0x34, 0xf1, 0x53, 0x3f, 0x0c, 0xcf, - 0x42, 0x4d, 0x35, 0x5a, 0xc6, 0xa8, 0x18, 0x41, 0xd2, 0x8e, 0x10, 0x05, 0x4a, 0x10, 0x40, 0xa8, 0x18, 0x94, 0x00, - 0x08, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x04, 0xa4, 0x00, 0x82, 0xf1, 0x50, 0x8a, 0x24, 0x00, 0x50, - 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x70, 0x10, 0x40, 0xa8, 0x1c, 0xa1, 0x00, 0x88, 0x40, 0x81, 0x00, 0x98, 0xa8, - 0xa4, 0x00, 0x18, 0x02, 0x00, 0x44, 0x23, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x44, 0x69, 0x00, 0x00, 0x42, 0xa3, - 0xf3, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x40, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, - 0x84, 0x50, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, - 0x00, 0xf5, 0x00, 0x00, 0x00, 0xf5, 0xff, 0x00, 0x42, 0xa3, 0x00, 0x10, 0x02, 0xf3, 0xff, 0x10, 0x82, 0xa4, 0x80, - 0x00, 0x80, 0xe2, 0x00, 0x00, 0x00, 0x84, 0xa8, 0xa4, 0x00, 0x18, 0x00, 0x10, 0x02, 0xf3, 0x00, 0x10, 0x02, 0xf3, - 0x80, 0x00, 0x40, 0xe2, 0x00, 0x11, 0x40, 0x49, 0x00, 0x00, 0xc0, 0x93, 0x80, 0x10, 0x84, 0xff, 0x80, 0x20, 0x86, - 0x7f, 0x80, 0x31, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x80, 0x41, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, - 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, - 0x42, 0x88, 0xff, 0x06, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, - 0xfa, 0x4f, 0xea, 0x9d, 0xdc, 0xe0, 0x34, 0x82, 0xd0, 0xc3, 0xee, 0xb7, 0x4c, 0x55, 0xcd, 0x62, 0xb3, 0xd3, 0xc9, - 0x08, 0x09, 0xcc, 0xb3, 0xca, 0x13, 0xcd, 0x0c, 0xd4, 0xa8, 0x78, 0x10, 0x18, 0x47, 0xe8, 0x05, 0x03, 0xe0, 0x7d, - 0xa4, 0xdc, 0x81, 0x00, 0x8a, 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x0f, 0x00, 0x7c, 0x23, 0x00, 0x42, - 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0xfc, 0x81, 0x00, 0x0a, 0x80, - 0x42, 0x8c, 0xff, 0x00, 0x63, 0x88, 0xff, 0x3f, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, - 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0x1c, 0x82, 0x00, 0x8a, 0x00, 0x43, 0x8a, 0xff, 0x80, 0x52, 0x88, - 0xff, 0x00, 0x42, 0x88, 0xff, 0x1e, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, - 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0x40, 0x82, 0x00, 0x8a, 0x00, 0x43, 0x88, 0x7f, 0x40, 0x30, 0x4a, 0xc5, 0x80, - 0x00, 0x7c, 0xa3, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x50, 0x0a, 0x63, 0x80, 0x82, 0x00, 0x8c, - 0x00, 0x50, 0x0a, 0x63, 0x94, 0x82, 0x00, 0x0e, 0x80, 0x40, 0x88, 0xff, 0x94, 0x82, 0x00, 0x98, 0x00, 0x50, 0x0a, - 0x63, 0x90, 0x82, 0x00, 0x0c, 0x00, 0x41, 0x88, 0xff, 0x94, 0x82, 0x00, 0x98, 0x80, 0x41, 0x88, 0x7f, 0x02, 0xe0, - 0x7d, 0x24, 0x60, 0x82, 0x00, 0x0a, 0x00, 0x40, 0x42, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x86, 0xef, 0x80, - 0x30, 0x88, 0xef, 0x00, 0x42, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, - 0x80, 0x31, 0x86, 0xef, 0xfa, 0x2f, 0x9b, 0xfc, 0xe2, 0x69, 0xc7, 0xa1, 0x8b, 0xf0, 0x54, 0x4c, 0xfa, 0x69, 0x81, - 0x47, 0x1c, 0x54, 0xcd, 0x22, 0x21, 0xaa, 0x59, 0x3a, 0xc5, 0x61, 0x9d, 0xd7, 0x95, 0x94, 0x0b, 0x78, 0x3e, 0xc0, - 0x06, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x31, 0x86, 0x6f, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, - 0x86, 0xef, 0x00, 0x32, 0x8a, 0x6f, 0x80, 0x52, 0x86, 0xef, 0x09, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x01, - 0xe0, 0x7d, 0x24, 0xe0, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x86, 0xef, 0x0a, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, - 0x80, 0x31, 0x86, 0xef, 0x02, 0xe0, 0x7d, 0x24, 0xf4, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x8a, 0xef, 0x80, 0x52, 0x86, - 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x1e, 0x00, - 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, 0x20, - 0x83, 0x00, 0x0a, 0x80, 0x30, 0x86, 0x6f, 0x80, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, - 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x04, 0xe0, 0x7d, 0x24, 0x3c, 0x83, 0x00, 0x8a, 0x00, 0x31, 0x86, - 0x6f, 0x20, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, - 0x86, 0xef, 0x04, 0xe0, 0x7d, 0x24, 0x5c, 0x83, 0x00, 0x8a, 0x00, 0x31, 0x86, 0x6f, 0x1e, 0x00, 0x7c, 0x23, 0x80, - 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, 0x7c, 0x83, 0x00, 0x0a, - 0x80, 0x32, 0x86, 0xef, 0x00, 0x00, 0x00, 0x84, 0xfa, 0x31, 0x53, 0x84, 0xc5, 0x65, 0xd8, 0x2d, 0x6a, 0xd2, 0xe6, - 0x0e, 0x92, 0x2a, 0xc4, 0xd1, 0x51, 0x88, 0x21, 0x8f, 0x06, 0xfd, 0xe9, 0x5f, 0x07, 0x37, 0xe1, 0xa8, 0x63, 0x7d, - 0x14, 0x7d, 0x65, 0x98, 0x07, 0xa4, 0x82, 0x00, 0x02, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x30, - 0x82, 0xef, 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x84, 0xe7, 0x80, 0x20, 0x88, 0xe7, 0x00, 0x42, 0x86, 0x67, 0x80, - 0x31, 0x86, 0x67, 0x80, 0x41, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, - 0x80, 0x31, 0x86, 0x67, 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x07, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, - 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xdc, 0x83, 0x00, 0x0a, 0x80, 0x21, 0x8a, 0xe7, 0x80, 0x52, 0x86, 0x67, 0x0f, 0x00, - 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xf4, 0x83, 0x00, 0x0a, 0x80, 0x51, 0x84, 0xe7, 0x00, - 0x21, 0x86, 0x67, 0x0f, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x0c, 0x84, 0x00, 0x0a, - 0x80, 0x51, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x22, 0x8a, 0x67, 0x80, 0x52, 0x86, - 0x67, 0x31, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x30, 0x84, 0x00, 0x0a, 0x80, 0x51, - 0x84, 0xe7, 0x00, 0x21, 0x86, 0x67, 0x63, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x48, - 0x84, 0x00, 0x0a, 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0x67, - 0x01, 0xe0, 0x7d, 0x24, 0x60, 0x84, 0x00, 0x0a, 0x80, 0x32, 0x84, 0xe7, 0xfa, 0x8d, 0xc0, 0xa9, 0x35, 0x3b, 0x01, - 0x45, 0xdb, 0xba, 0xa4, 0x31, 0x7d, 0x18, 0xd6, 0x32, 0xa6, 0xa8, 0xa7, 0x9e, 0xc6, 0x21, 0xf0, 0xd9, 0x61, 0xea, - 0x71, 0x3c, 0xeb, 0xb0, 0x4f, 0xac, 0x1c, 0x70, 0x08, 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, - 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x30, 0x86, 0xe7, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, - 0x31, 0x86, 0x67, 0x00, 0x32, 0x82, 0x67, 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0x80, 0x67, - 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x00, 0x80, - 0x67, 0x00, 0x21, 0x84, 0xe7, 0x80, 0x20, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x32, 0x48, 0x45, 0x00, 0x22, - 0x86, 0x67, 0x00, 0x21, 0x88, 0xe7, 0x80, 0x40, 0x88, 0xe8, 0xdc, 0x84, 0x00, 0x8a, 0x00, 0x20, 0x42, 0xe3, 0x00, - 0x00, 0x00, 0x84, 0x00, 0x30, 0x42, 0x63, 0x00, 0x00, 0x00, 0x84, 0x00, 0x90, 0x42, 0x63, 0x74, 0x84, 0x00, 0x82, - 0x80, 0x70, 0x8e, 0xe7, 0x80, 0x80, 0x90, 0xe7, 0x01, 0x00, 0x42, 0x23, 0x80, 0x70, 0x8e, 0xe2, 0x00, 0x80, 0x10, - 0xeb, 0x80, 0x83, 0x90, 0xe4, 0x00, 0x80, 0x10, 0xed, 0x00, 0x80, 0x10, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0xc0, - 0x60, 0x63, 0x00, 0x00, 0x21, 0x63, 0x24, 0x85, 0x00, 0x8c, 0x00, 0x00, 0x6c, 0xa3, 0x2c, 0x85, 0x00, 0x18, 0x01, - 0x00, 0x6c, 0x23, 0x2c, 0x85, 0x00, 0x18, 0x00, 0x00, 0x21, 0x65, 0x00, 0x00, 0x59, 0x63, 0x00, 0x08, 0xa1, 0xe7, - 0x01, 0x00, 0x42, 0x23, 0x80, 0x00, 0xa9, 0xfd, 0x00, 0x03, 0xa1, 0x67, 0x80, 0x00, 0xab, 0x7b, 0xfa, 0xa8, 0xaf, - 0xdd, 0xb8, 0xba, 0xaa, 0x08, 0x6c, 0xd4, 0x88, 0xf3, 0x77, 0x9b, 0x7e, 0xa7, 0xf8, 0x8f, 0x4b, 0xdd, 0xf9, 0xbe, - 0x8d, 0x63, 0xb9, 0x23, 0x90, 0x0f, 0xef, 0x9f, 0x88, 0x37, 0x9e, 0x48, 0x09, 0x80, 0x5a, 0xa5, 0x67, 0x80, 0x2a, - 0xa5, 0xe7, 0x00, 0x2a, 0xa7, 0xe7, 0x00, 0x29, 0xa5, 0x67, 0x80, 0x2a, 0xa5, 0xe7, 0x00, 0x2a, 0x83, 0xe7, 0x00, - 0x10, 0x60, 0xe3, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0xa4, 0x67, 0x00, 0x29, 0xa5, 0x67, 0x00, 0x28, 0xa5, 0xe7, - 0x80, 0x29, 0xa5, 0xe7, 0x00, 0x29, 0xa1, 0xe7, 0x80, 0x0a, 0xa1, 0xe7, 0x00, 0x32, 0x42, 0x45, 0x80, 0x20, 0xa3, - 0xe7, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x0a, 0xbd, 0xe8, 0x9c, 0x85, 0x00, 0x8a, 0x00, 0x20, 0x41, 0xe3, 0x01, 0x00, - 0x42, 0x23, 0x00, 0x00, 0x7c, 0x23, 0x00, 0xea, 0xa9, 0xfd, 0x00, 0x0a, 0xbd, 0xe8, 0xb4, 0x85, 0x00, 0x8a, 0x00, - 0x10, 0x41, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, 0x88, 0x00, 0x00, 0x42, 0xa3, - 0x00, 0xe0, 0xbd, 0x68, 0xcc, 0x85, 0x00, 0x8a, 0x01, 0x10, 0x82, 0x24, 0x01, 0x60, 0x41, 0xa8, 0xd8, 0x85, 0x00, - 0x8a, 0x02, 0x10, 0x82, 0x24, 0x03, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, 0x88, 0x00, 0x00, 0x46, 0x23, 0x00, 0x30, - 0x86, 0xfd, 0x01, 0x00, 0x7c, 0xa3, 0x00, 0x0f, 0x82, 0xe2, 0x00, 0x1b, 0x40, 0x68, 0x00, 0x86, 0x00, 0x8a, 0x00, - 0x00, 0x56, 0x63, 0x08, 0x86, 0x00, 0x18, 0x00, 0x30, 0x56, 0x63, 0x08, 0x86, 0x00, 0x18, 0x00, 0x00, 0x42, 0xa3, - 0x00, 0x00, 0x00, 0x84, 0xff, 0x0f, 0x42, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x80, 0x83, 0x80, 0xfd, 0x80, 0xc5, 0x82, - 0xfd, 0xfa, 0x2d, 0xe4, 0xc2, 0x35, 0x0d, 0x09, 0x7b, 0xcf, 0xa5, 0x80, 0x6c, 0x50, 0x37, 0x0f, 0x88, 0xc8, 0xb2, - 0x30, 0x17, 0x0b, 0x0c, 0x73, 0x25, 0x9c, 0x3c, 0x35, 0xa7, 0xd8, 0xd8, 0xd6, 0x70, 0x2f, 0x20, 0x0a, 0x80, 0x00, - 0x80, 0xe7, 0x80, 0x83, 0x82, 0x7b, 0x80, 0xc5, 0x84, 0xfb, 0x00, 0x11, 0x82, 0xe7, 0x00, 0xa7, 0x84, 0x67, 0x00, - 0x23, 0x84, 0x67, 0x00, 0x21, 0x84, 0x7b, 0x80, 0x96, 0x86, 0xe7, 0x80, 0x31, 0x86, 0xfb, 0x00, 0x10, 0x88, 0xfd, - 0x00, 0x10, 0x80, 0x7b, 0x00, 0x31, 0x82, 0xfd, 0x00, 0x31, 0x84, 0xfb, 0x80, 0x40, 0x96, 0xe7, 0x00, 0x40, 0x9c, - 0x67, 0x00, 0x20, 0x98, 0xe7, 0x80, 0x20, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x80, 0x73, 0x80, 0x67, 0x00, 0x84, - 0x82, 0xe7, 0x80, 0x94, 0x84, 0xe7, 0x00, 0x21, 0x84, 0x7b, 0x80, 0x00, 0x86, 0x7b, 0x00, 0x74, 0x88, 0x7b, 0x00, - 0x42, 0x88, 0xe7, 0x00, 0x32, 0x88, 0xfd, 0x80, 0x00, 0x80, 0x7d, 0x00, 0x20, 0x82, 0xfb, 0x80, 0x40, 0x8e, 0xe7, - 0x80, 0x00, 0x92, 0xe7, 0x80, 0x01, 0x90, 0xe7, 0x80, 0x41, 0x94, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x4e, - 0xa3, 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, - 0x39, 0xeb, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, - 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, - 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0xb8, 0x86, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x56, - 0xc9, 0x20, 0x05, 0x58, 0xc9, 0xfa, 0x0f, 0xee, 0x07, 0xd2, 0xf4, 0xa2, 0x2d, 0x0d, 0x40, 0x79, 0xfa, 0x2d, 0x57, - 0x83, 0x0f, 0x41, 0x07, 0x75, 0xb7, 0xe5, 0xd5, 0xd7, 0xac, 0x9b, 0xf8, 0x00, 0x5e, 0xf4, 0x04, 0xe4, 0xcf, 0xf4, - 0xf8, 0x0a, 0x40, 0x05, 0x5a, 0x49, 0x00, 0x00, 0x4e, 0xa3, 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, 0xa3, 0x00, - 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xde, 0xf3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, - 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, - 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, - 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x14, 0x87, 0x00, 0x0a, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, - 0xc0, 0x39, 0xeb, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, - 0x18, 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, - 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x50, 0x87, 0x00, 0x0a, 0x00, 0x00, 0x7c, 0x23, 0x80, 0xe3, - 0x8f, 0xfd, 0x00, 0xe5, 0x95, 0xfd, 0x18, 0x86, 0x00, 0x02, 0x80, 0xe3, 0x8f, 0xfd, 0x00, 0xe5, 0x95, 0xfd, 0x00, - 0x05, 0x40, 0x45, 0x20, 0x05, 0x42, 0x45, 0x40, 0x05, 0x44, 0x45, 0x80, 0x06, 0x80, 0xe7, 0x80, 0x16, 0x82, 0xe7, - 0x00, 0xb1, 0x96, 0xe7, 0x00, 0xc1, 0x98, 0xe7, 0x80, 0x05, 0xbc, 0xe8, 0xd4, 0x87, 0x00, 0x0a, 0x00, 0x16, 0xbc, - 0xe8, 0xd4, 0x87, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0xfa, 0xfe, 0x14, 0x49, 0x21, 0x60, 0xff, 0x7e, 0x5d, 0x00, - 0x19, 0x5b, 0xd4, 0x90, 0x1b, 0xdc, 0x48, 0x41, 0x2e, 0x9c, 0x5b, 0x19, 0xcb, 0xc0, 0x02, 0x1c, 0x36, 0x73, 0x88, - 0x29, 0x18, 0xc8, 0x17, 0xd0, 0x0b, 0x00, 0x00, 0x00, 0x84, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x40, - 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xae, 0x24, - 0x80, 0x5b, 0xab, 0x67, 0x00, 0x5b, 0xb1, 0x67, 0x80, 0x6b, 0xad, 0x67, 0x98, 0x96, 0x00, 0x02, 0x80, 0x31, 0x7e, - 0xc5, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0x02, - 0x56, 0x49, 0x20, 0x02, 0x58, 0x49, 0x40, 0x02, 0x5a, 0xc9, 0x60, 0x02, 0x5c, 0x49, 0xf0, 0x86, 0x00, 0x02, 0x00, - 0x00, 0x40, 0xa8, 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0x02, 0x56, 0x45, - 0x20, 0x02, 0x58, 0x45, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, 0x45, 0x00, 0x02, 0x4e, 0x49, 0x20, 0x02, 0x50, - 0xc9, 0x40, 0x02, 0x52, 0x49, 0x60, 0x02, 0x54, 0xc9, 0x00, 0x50, 0x4f, 0xe3, 0x00, 0x60, 0x51, 0xe3, 0x00, 0x70, - 0x53, 0xe3, 0x00, 0x80, 0x55, 0xe3, 0x00, 0x00, 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, 0x00, 0x07, 0x9c, 0xfd, 0x18, - 0x86, 0x00, 0x02, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, - 0xa0, 0x31, 0x4c, 0xc5, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, 0x00, - 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0x02, 0x56, 0x45, 0x20, 0x02, 0x58, 0x45, 0xfa, 0x31, 0x1e, 0xae, 0xa7, 0x68, - 0x3e, 0x48, 0xa1, 0xb0, 0x5d, 0x94, 0x7f, 0x0e, 0x69, 0x39, 0x45, 0xe9, 0x26, 0x00, 0x27, 0xa6, 0xd1, 0x0f, 0xb4, - 0x49, 0x35, 0xc6, 0x1f, 0x18, 0xd4, 0x55, 0xc1, 0xa8, 0x0c, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, 0x45, 0x18, - 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0x00, 0xe0, 0x54, 0x63, - 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, 0x74, 0x84, 0x00, 0x82, 0x80, 0xb0, 0xaa, - 0xe7, 0x80, 0xc0, 0xac, 0x67, 0x80, 0x5a, 0x83, 0xe7, 0x00, 0x6b, 0x85, 0xe7, 0x80, 0x20, 0x86, 0xfd, 0x00, 0x11, - 0x88, 0xe7, 0x00, 0x43, 0x88, 0x67, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x40, 0x88, 0xfb, 0x00, 0x32, 0x80, 0xe8, 0x08, - 0x89, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, - 0x80, 0x73, 0x80, 0x67, 0x00, 0x84, 0x82, 0xe7, 0x80, 0x94, 0x84, 0xe7, 0x00, 0x10, 0x86, 0x7d, 0x00, 0x31, 0x86, - 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x03, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x01, 0x80, 0x7b, 0x00, 0x30, - 0x86, 0x68, 0x48, 0x89, 0x00, 0x8a, 0x00, 0x74, 0x80, 0x67, 0x00, 0x95, 0x86, 0x67, 0x00, 0x30, 0x86, 0x68, 0x00, - 0x00, 0x00, 0x84, 0x00, 0x96, 0x80, 0xef, 0x80, 0xa6, 0x82, 0xef, 0x00, 0xb7, 0x84, 0x6f, 0x00, 0x95, 0x86, 0xfb, - 0x80, 0xc6, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x6f, 0x80, 0x00, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x7d, 0x80, 0xa5, 0x88, - 0xfb, 0x00, 0xd7, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xef, 0x00, 0x11, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xfd, 0xfa, 0x94, - 0x96, 0xe3, 0x85, 0x52, 0x4e, 0xab, 0x44, 0xf3, 0xe1, 0x73, 0xcf, 0x77, 0xf0, 0x1b, 0x15, 0x54, 0xff, 0x6b, 0xb7, - 0x2a, 0x1c, 0x22, 0xdb, 0x15, 0xa7, 0x65, 0x7f, 0x14, 0xfb, 0x89, 0x41, 0x80, 0x0d, 0x80, 0x95, 0x8a, 0x7b, 0x00, - 0xc7, 0x8c, 0x7b, 0x00, 0x53, 0x8a, 0xef, 0x00, 0x01, 0x8c, 0x7b, 0x00, 0x53, 0x8c, 0xfd, 0x00, 0x81, 0x8e, 0x6f, - 0x80, 0x63, 0x8a, 0x7d, 0x80, 0x52, 0x8e, 0x7b, 0x80, 0x53, 0x8a, 0x7b, 0x80, 0x12, 0x8e, 0xfd, 0x80, 0x12, 0x8a, - 0x7b, 0x00, 0x83, 0x8c, 0x6f, 0x00, 0x21, 0x82, 0x7b, 0x00, 0x11, 0x84, 0x7b, 0x00, 0x61, 0x8c, 0x7d, 0x00, 0x60, - 0x8c, 0xfd, 0x00, 0x63, 0x82, 0x7b, 0x00, 0x13, 0x8c, 0x7b, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x80, 0x7b, 0x00, - 0x01, 0x80, 0x7d, 0x00, 0x43, 0x82, 0xef, 0x00, 0x03, 0x84, 0x6f, 0x80, 0x53, 0x8c, 0x6f, 0x00, 0x61, 0x9a, 0xfb, - 0x80, 0x32, 0x8a, 0xef, 0x80, 0x50, 0x98, 0x7d, 0x80, 0x43, 0x8e, 0x6f, 0x00, 0x30, 0x82, 0x6f, 0x80, 0x70, 0x9c, - 0x7b, 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0xef, 0x00, 0xa5, 0x82, 0x6f, 0x80, 0xb5, 0x84, 0x6f, 0x00, 0x95, - 0x86, 0xef, 0x80, 0x31, 0x86, 0xfb, 0x80, 0x95, 0x8e, 0xef, 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x81, 0x8c, 0xef, 0x80, - 0x63, 0x8c, 0x7d, 0x00, 0x63, 0x8a, 0xfb, 0x00, 0x53, 0x8c, 0xfb, 0x00, 0x13, 0x8a, 0x7d, 0x00, 0x13, 0x8c, 0x7b, - 0x00, 0x53, 0x8c, 0xef, 0x80, 0x51, 0x8a, 0xef, 0x00, 0x21, 0x86, 0xfb, 0x80, 0x21, 0x84, 0xfb, 0x80, 0x83, 0x8e, - 0x6f, 0x00, 0x71, 0x8e, 0x7d, 0x00, 0x70, 0x8e, 0xfd, 0x80, 0x73, 0x86, 0xfb, 0x80, 0x71, 0x8e, 0xfb, 0x00, 0x00, - 0x86, 0xfb, 0xfa, 0xcc, 0x6d, 0xcb, 0xad, 0x89, 0x62, 0xc2, 0x58, 0xe9, 0x5c, 0x59, 0x07, 0x1d, 0x65, 0xa8, 0x3c, - 0x07, 0x36, 0xba, 0x80, 0x63, 0x10, 0x99, 0x09, 0x91, 0xf7, 0x4f, 0x15, 0xc5, 0x6f, 0x0d, 0xfe, 0x58, 0x0e, 0x00, - 0x30, 0x80, 0xfb, 0x00, 0x01, 0x80, 0x7d, 0x80, 0x03, 0x80, 0x6f, 0x00, 0x60, 0x8c, 0xfb, 0x80, 0xa5, 0x80, 0x6f, - 0x00, 0x00, 0x80, 0xfb, 0x80, 0x03, 0x8e, 0xef, 0x80, 0x53, 0x8a, 0x7d, 0x80, 0x00, 0x8e, 0xef, 0x80, 0x73, 0x8e, - 0x7b, 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x50, 0x52, 0xe3, 0x00, 0x60, 0x54, 0xe3, 0x00, 0x70, 0x56, 0xe3, 0x00, 0x00, - 0x00, 0x84, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, 0x00, 0x56, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, - 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, - 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, - 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xa8, 0x8a, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x58, 0x49, 0x20, 0x05, - 0x5a, 0x49, 0x40, 0x05, 0x5c, 0x49, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, 0x00, 0x56, 0xa3, 0x00, - 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xde, 0xf3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, 0x00, 0xc0, 0x52, 0x67, - 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, - 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xf8, 0x8a, 0x00, 0x0a, 0x00, 0x01, - 0x7c, 0xa3, 0x00, 0xf0, 0x1e, 0xeb, 0xfa, 0x54, 0x1c, 0x74, 0x4c, 0x9b, 0x90, 0x65, 0x7b, 0xde, 0x1d, 0x55, 0xf8, - 0x5f, 0x85, 0xe3, 0x39, 0x91, 0xe4, 0xa1, 0x0a, 0xf7, 0xf7, 0x97, 0x01, 0x79, 0xc4, 0x5a, 0x0e, 0x20, 0x84, 0xb7, - 0xb1, 0x30, 0x0f, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, - 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, - 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x2c, 0x8b, 0x00, 0x8a, 0x00, 0x00, 0x7c, 0x23, 0x00, 0xe5, 0x95, 0xfd, 0x4c, 0x89, - 0x00, 0x82, 0x00, 0xe5, 0x95, 0xfd, 0x00, 0x05, 0x40, 0x45, 0x20, 0x05, 0x42, 0x45, 0x40, 0x05, 0x44, 0x45, 0x00, - 0x07, 0x80, 0x6f, 0x00, 0x17, 0x82, 0x6f, 0x00, 0xc1, 0x98, 0x6f, 0x00, 0xd1, 0x9a, 0x6f, 0x00, 0x06, 0xbc, 0x68, - 0xa0, 0x8b, 0x00, 0x0a, 0x80, 0x16, 0xbc, 0x68, 0xa0, 0x8b, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, - 0x84, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x30, 0x7e, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, - 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xb0, 0x24, 0x00, 0x6c, 0xad, 0xef, 0x00, 0x7c, 0xaf, 0xef, 0xc8, - 0x97, 0x00, 0x82, 0x00, 0x10, 0x53, 0xe3, 0x00, 0x20, 0x55, 0xe3, 0x00, 0x30, 0x57, 0xe3, 0x9c, 0x8c, 0x00, 0x02, - 0x94, 0x8c, 0x00, 0x0a, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x00, 0x30, 0x7e, - 0xc5, 0x80, 0x30, 0x50, 0x45, 0x00, 0x10, 0x59, 0xe3, 0x00, 0x20, 0x5b, 0x63, 0x00, 0x30, 0x5d, 0xe3, 0xd8, 0x8a, - 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x94, 0x8c, 0x00, 0x0a, 0xfa, 0x62, 0x58, 0xee, 0x51, 0x13, 0xf7, 0x00, 0x08, - 0xe6, 0x1c, 0x79, 0xd4, 0x2f, 0xce, 0xb8, 0xa2, 0x58, 0x88, 0x20, 0x1a, 0xab, 0xa7, 0x23, 0x41, 0x0c, 0xd8, 0xb6, - 0x30, 0xa9, 0x01, 0xba, 0x1e, 0x08, 0x10, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0x00, 0x80, 0x68, - 0x00, 0x60, 0x53, 0x6f, 0x00, 0x70, 0x55, 0xef, 0x00, 0x80, 0x57, 0x6f, 0x00, 0x10, 0x59, 0xe3, 0x00, 0x20, 0x5b, - 0x63, 0x00, 0x30, 0x5d, 0xe3, 0x80, 0x06, 0x9a, 0xfd, 0x4c, 0x89, 0x00, 0x82, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, - 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x94, - 0x8c, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0x60, 0x59, 0x63, 0x00, 0x70, 0x5b, 0x63, - 0x00, 0x80, 0x5d, 0x63, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xc0, 0x52, 0xe3, 0x00, 0xd0, 0x54, 0x63, 0x00, 0xe0, 0x56, - 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0xe0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0xc0, - 0xac, 0xef, 0x80, 0xd0, 0xae, 0xef, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, - 0x00, 0x00, 0x84, 0x60, 0x30, 0x40, 0x45, 0x80, 0x30, 0x42, 0x45, 0x00, 0xa5, 0x86, 0xef, 0x80, 0x35, 0x86, 0x6f, - 0x80, 0x94, 0x84, 0x6f, 0x80, 0x24, 0x84, 0xef, 0x80, 0xb5, 0x88, 0x6f, 0x80, 0x45, 0x8a, 0xef, 0x80, 0x04, 0x80, - 0xef, 0x00, 0x02, 0x80, 0x6f, 0x80, 0x12, 0x82, 0xef, 0x80, 0x00, 0x80, 0x7b, 0x00, 0x01, 0x80, 0x7b, 0x80, 0x01, - 0x80, 0x68, 0x00, 0x00, 0x00, 0x84, 0x60, 0x32, 0x40, 0xc5, 0x00, 0x08, 0x80, 0xe7, 0xfa, 0x3e, 0xf3, 0xbf, 0xbf, - 0x4c, 0x33, 0x5d, 0x93, 0x4b, 0xf4, 0x1a, 0xe2, 0x89, 0xc8, 0xee, 0x37, 0xf4, 0x14, 0xbb, 0x8b, 0x11, 0xf8, 0x95, - 0x9e, 0x50, 0x8a, 0x70, 0x17, 0x27, 0x33, 0x81, 0x07, 0xe0, 0x10, 0x00, 0x08, 0x83, 0xe7, 0x00, 0x10, 0x82, 0xfb, - 0x01, 0x00, 0x40, 0xa3, 0x00, 0x10, 0x82, 0xfb, 0x00, 0x18, 0x82, 0xe7, 0x98, 0x84, 0x00, 0x02, 0x00, 0x10, 0x62, - 0x63, 0x01, 0x00, 0x44, 0x23, 0x00, 0x20, 0x84, 0x70, 0x00, 0x01, 0x84, 0x62, 0x00, 0x00, 0x00, 0x84, 0xc0, 0x32, - 0x68, 0xc5, 0xe0, 0x32, 0x6a, 0xc5, 0xa0, 0x32, 0x6c, 0x45, 0x00, 0x64, 0x8b, 0x67, 0x80, 0x53, 0x8a, 0x7b, 0x00, - 0x66, 0x8d, 0xe7, 0x80, 0x65, 0x8c, 0x7b, 0x00, 0x53, 0x80, 0x67, 0x80, 0x96, 0x82, 0x67, 0x00, 0x86, 0x84, 0x67, - 0x80, 0x54, 0x86, 0xfb, 0x80, 0x66, 0x88, 0xfb, 0x00, 0x32, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, 0x00, 0x32, 0x86, - 0x7d, 0x00, 0x54, 0x88, 0xfb, 0x00, 0x66, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0x67, 0x00, 0x01, 0x8a, 0x7b, 0x80, 0x42, - 0x88, 0xfd, 0x00, 0x94, 0x8a, 0x7b, 0x00, 0xd6, 0x96, 0xfb, 0x80, 0x55, 0x8a, 0xe7, 0x00, 0x11, 0x96, 0x7b, 0x80, - 0x55, 0x8a, 0x7d, 0x00, 0x42, 0x99, 0xe7, 0x00, 0x51, 0x97, 0xe7, 0x00, 0xb6, 0x98, 0x7b, 0x00, 0x16, 0x96, 0xfd, - 0x00, 0x16, 0x98, 0x7b, 0x00, 0xb6, 0x9a, 0x67, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x82, 0xfb, 0x00, 0x41, 0x85, - 0x67, 0x00, 0x52, 0x89, 0xe7, 0x00, 0x11, 0x82, 0x7b, 0x00, 0x01, 0x84, 0xfd, 0x00, 0x41, 0x85, 0x67, 0x00, 0x41, - 0x88, 0x7b, 0x00, 0x12, 0x80, 0x67, 0x00, 0xd0, 0x9a, 0xfb, 0x00, 0x52, 0x80, 0xe7, 0x80, 0x35, 0x96, 0x67, 0xfa, - 0x18, 0x32, 0x64, 0x6f, 0xd5, 0xa3, 0xde, 0x72, 0x05, 0x43, 0x4c, 0xae, 0x7c, 0x7f, 0xa8, 0xf8, 0x61, 0x9c, 0x4c, - 0x8a, 0x5d, 0x4e, 0x55, 0xfc, 0x27, 0x39, 0xd7, 0xa8, 0x28, 0x99, 0x39, 0xe1, 0xb8, 0x11, 0x00, 0xb0, 0x96, 0xfd, - 0x80, 0x30, 0x80, 0xe7, 0x00, 0x56, 0x98, 0x67, 0x00, 0xc0, 0x98, 0xfb, 0x00, 0x66, 0xad, 0x67, 0x00, 0xbb, 0x96, - 0x7d, 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0x67, 0x00, 0x04, 0x80, 0xe7, 0x60, 0x32, 0x42, 0x45, 0x80, 0x13, - 0x82, 0xe7, 0x00, 0x14, 0x82, 0x7b, 0x00, 0x14, 0x82, 0xe7, 0x80, 0x73, 0x84, 0xe7, 0x00, 0x11, 0x82, 0x7b, 0x80, - 0x13, 0x82, 0xe7, 0x80, 0x00, 0x80, 0xe8, 0x00, 0x00, 0x00, 0x84, 0x00, 0x74, 0x80, 0xfb, 0x00, 0x95, 0x82, 0x7d, - 0x00, 0x10, 0x82, 0x67, 0x00, 0x74, 0x80, 0xfd, 0x00, 0x95, 0x84, 0x7b, 0x00, 0x20, 0x84, 0x67, 0x00, 0x11, 0x86, - 0xfb, 0x80, 0x31, 0x86, 0x67, 0x00, 0x11, 0x88, 0x7d, 0x00, 0x42, 0x88, 0xe7, 0x00, 0x36, 0x92, 0x67, 0x00, 0xb2, - 0x94, 0x67, 0x00, 0x00, 0x00, 0x84, 0x00, 0x74, 0x82, 0x7b, 0x80, 0x10, 0x82, 0xe7, 0x00, 0x74, 0x84, 0x7d, 0x00, - 0x21, 0x84, 0xe7, 0x00, 0x11, 0x8e, 0xe7, 0x00, 0x11, 0x82, 0x7d, 0x80, 0x60, 0x86, 0xe7, 0x00, 0x31, 0x86, 0x7b, - 0x80, 0x11, 0x90, 0x67, 0x00, 0x00, 0x00, 0x84, 0x80, 0x32, 0x4c, 0x45, 0x00, 0xb0, 0x52, 0x63, 0x00, 0xc0, 0x54, - 0xe3, 0x01, 0x00, 0x4e, 0x23, 0x00, 0x00, 0x50, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xf6, 0xf3, 0x00, 0xb0, - 0x37, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x00, 0x8e, 0x00, 0x82, 0x34, - 0x8e, 0x00, 0x02, 0xfa, 0xe9, 0xae, 0x32, 0x50, 0xc8, 0x40, 0xd2, 0x58, 0xb8, 0x9c, 0x34, 0x8f, 0x8c, 0x09, 0xce, - 0x7a, 0x6f, 0xcb, 0x67, 0xaa, 0x17, 0x48, 0x18, 0x37, 0xb0, 0x34, 0x59, 0x82, 0x25, 0x28, 0xde, 0x83, 0x90, 0x12, - 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x78, 0x8e, 0x00, 0x0a, 0x00, 0x01, 0x7c, - 0xa3, 0x00, 0xb0, 0x37, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x00, 0x8e, - 0x00, 0x82, 0x34, 0x8e, 0x00, 0x02, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0xa4, - 0x8e, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x76, 0x80, 0xe7, 0x00, 0xb4, 0x82, 0xe7, 0x00, 0x86, 0x84, 0x67, - 0x60, 0x32, 0x4c, 0xc5, 0x00, 0x63, 0x86, 0xfb, 0x00, 0x31, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, 0x80, 0x41, 0x88, - 0xfb, 0x80, 0xb3, 0x8a, 0x67, 0x00, 0x51, 0x8a, 0x7b, 0x80, 0x42, 0x88, 0x67, 0x00, 0x31, 0x86, 0xe7, 0x80, 0x41, - 0x88, 0xfd, 0x00, 0x45, 0x88, 0x67, 0x80, 0x00, 0x82, 0xfd, 0x80, 0x10, 0x82, 0xe7, 0x80, 0x14, 0x82, 0x67, 0x80, - 0x40, 0x92, 0xfd, 0x80, 0xd6, 0x86, 0xfb, 0x00, 0x34, 0x86, 0xe7, 0x00, 0x35, 0x86, 0x67, 0x00, 0x30, 0x8e, 0xe7, - 0x00, 0x31, 0x90, 0x67, 0x00, 0x00, 0x00, 0x84, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0x00, 0x42, - 0xa3, 0x00, 0xe0, 0x45, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x47, 0xe5, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, - 0x49, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4b, 0xe5, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4d, 0xe5, 0x00, - 0x20, 0x04, 0xf9, 0x00, 0x30, 0x06, 0xf9, 0xfa, 0xb4, 0x5b, 0xaa, 0xcc, 0x50, 0x15, 0xa8, 0x18, 0xac, 0x58, 0x09, - 0x38, 0xf8, 0x85, 0xb6, 0x6d, 0x04, 0x24, 0x75, 0x55, 0xc9, 0xa7, 0x1a, 0xb5, 0xe2, 0xd4, 0x12, 0x23, 0x35, 0x67, - 0x99, 0xf9, 0x68, 0x13, 0x00, 0x40, 0x08, 0xf9, 0x00, 0x50, 0x0a, 0xf9, 0x00, 0x60, 0x0c, 0xf9, 0x00, 0x00, 0x00, - 0x84, 0x00, 0x11, 0x02, 0xfd, 0x80, 0x21, 0x04, 0x7d, 0x00, 0x32, 0x06, 0xfd, 0x80, 0x42, 0x08, 0x7d, 0x00, 0x53, - 0x0a, 0x7d, 0x00, 0x60, 0x0c, 0xf3, 0x00, 0x00, 0x00, 0x84, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, 0x22, 0x00, - 0x40, 0x44, 0xe5, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x20, 0x2c, 0x63, 0x01, 0x60, 0x6b, 0x22, 0x00, 0x00, 0x42, 0xa3, - 0x04, 0x54, 0xe1, 0x35, 0x88, 0x90, 0x00, 0x9c, 0xff, 0x00, 0x40, 0x23, 0x00, 0x00, 0xa3, 0xe2, 0x02, 0x10, 0x41, - 0x28, 0x94, 0x90, 0x00, 0x8a, 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, - 0xa3, 0xe2, 0x00, 0x20, 0x84, 0x62, 0x00, 0x11, 0x41, 0xe8, 0xa0, 0x90, 0x00, 0x0a, 0x05, 0x54, 0xf3, 0xb5, 0x88, - 0x90, 0x00, 0x9c, 0x00, 0x03, 0x72, 0xc9, 0x05, 0x54, 0xc1, 0x39, 0x88, 0x90, 0x00, 0x9c, 0x00, 0x60, 0x6b, 0xe3, - 0x00, 0x54, 0xf5, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x01, 0x54, 0xef, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x02, 0x54, 0xfb, - 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x03, 0x54, 0xfd, 0x35, 0x88, 0x90, 0x00, 0x9c, 0x05, 0x54, 0xc1, 0x39, 0x88, 0x90, - 0x00, 0x9c, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, - 0xa0, 0xb5, 0xfd, 0x00, 0xd0, 0xbb, 0xfb, 0x00, 0x00, 0xc4, 0x73, 0xfa, 0x89, 0xb0, 0x12, 0x7e, 0xd4, 0x5a, 0x36, - 0xa6, 0xbb, 0x5c, 0x83, 0x6e, 0x7f, 0xf5, 0x0a, 0x62, 0x09, 0x8c, 0x99, 0xb6, 0xae, 0x58, 0xe0, 0x2e, 0xbc, 0x6b, - 0xe9, 0x52, 0x86, 0xe5, 0x8a, 0xc4, 0x40, 0x14, 0x00, 0x71, 0xaf, 0xe8, 0x00, 0xe1, 0xbd, 0xe8, 0x00, 0x7f, 0xa9, - 0x68, 0xe0, 0x03, 0x74, 0x49, 0x00, 0x04, 0x7a, 0xc9, 0xa0, 0x00, 0x60, 0xc5, 0x00, 0x00, 0x21, 0xf9, 0xc0, 0x00, - 0x62, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x05, 0x54, 0xc1, 0x39, 0x64, - 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x12, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, 0x42, 0x23, - 0x00, 0x00, 0x00, 0x84, 0x6c, 0x90, 0x00, 0x82, 0xf2, 0x00, 0x40, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x6c, 0x90, 0x00, - 0x82, 0xf4, 0x00, 0x40, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x6c, 0x90, 0x00, 0x82, 0xf6, 0x00, 0x40, 0x23, 0x94, 0x81, - 0x00, 0x98, 0x00, 0x00, 0xce, 0x73, 0x00, 0x00, 0xd0, 0x73, 0x00, 0x00, 0xd2, 0xf3, 0x00, 0x00, 0xd4, 0xf3, 0x00, - 0x70, 0xc0, 0xe3, 0x0c, 0x40, 0xc1, 0xa5, 0x4c, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x40, 0x23, - 0x94, 0x81, 0x00, 0x98, 0x30, 0x8f, 0x00, 0x02, 0x08, 0x00, 0x56, 0x23, 0x12, 0x00, 0x58, 0x23, 0x78, 0x8f, 0x00, - 0x02, 0x01, 0xc0, 0x58, 0x24, 0xe0, 0x90, 0x00, 0x8a, 0x00, 0x10, 0xc0, 0xe9, 0x01, 0xb0, 0x56, 0x24, 0xdc, 0x90, - 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x70, 0x81, 0x00, 0x02, 0x00, - 0x00, 0x56, 0x63, 0x30, 0x8f, 0x00, 0x02, 0x80, 0x00, 0x5e, 0xa3, 0x00, 0xf0, 0x1e, 0xf3, 0xfa, 0x24, 0x2a, 0xdc, - 0xd0, 0xb7, 0xb4, 0xcb, 0x7c, 0x3b, 0x7c, 0x58, 0x44, 0xd0, 0x96, 0xf0, 0x18, 0x08, 0xbf, 0x69, 0x25, 0xf8, 0x73, - 0x8f, 0x1e, 0xa7, 0xa0, 0x9c, 0x57, 0x88, 0x6a, 0xdc, 0xfe, 0x18, 0x15, 0x00, 0xf0, 0x1e, 0xf3, 0x00, 0xf0, 0x1e, - 0xf3, 0x12, 0xb0, 0x56, 0xa4, 0x80, 0xb7, 0xa0, 0x62, 0x44, 0x91, 0x00, 0x8a, 0x12, 0x00, 0x58, 0x23, 0x78, 0x8f, - 0x00, 0x02, 0x01, 0xc0, 0x58, 0x24, 0x30, 0x91, 0x00, 0x8a, 0x00, 0x10, 0xc0, 0xe9, 0x20, 0x91, 0x00, 0x18, 0x12, - 0xb0, 0x56, 0xa2, 0x88, 0x91, 0x00, 0x08, 0x12, 0x00, 0x58, 0x23, 0x80, 0xc5, 0x58, 0xe4, 0x78, 0x8f, 0x00, 0x02, - 0x01, 0xb0, 0x56, 0x24, 0x54, 0x91, 0x00, 0x0a, 0x01, 0xc0, 0x40, 0x28, 0x9c, 0x91, 0x00, 0x08, 0x04, 0x00, 0x44, - 0x23, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x11, 0x02, 0xfd, 0x00, 0x20, 0x04, 0xf3, 0x01, 0xc0, 0x58, 0x24, 0x70, 0x91, - 0x00, 0x0a, 0x80, 0x10, 0x82, 0x24, 0xac, 0x91, 0x00, 0x98, 0x00, 0x00, 0x42, 0xa3, 0x8a, 0x00, 0x46, 0xa3, 0x80, - 0x11, 0xc2, 0xe2, 0x80, 0x10, 0x82, 0x24, 0xac, 0x91, 0x00, 0x98, 0x84, 0x00, 0x44, 0xa3, 0x00, 0x20, 0x04, 0xf5, - 0x00, 0x11, 0x02, 0xfd, 0xac, 0x91, 0x00, 0x98, 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf6, 0x71, 0x00, 0x00, 0xc0, - 0x2d, 0x00, 0x70, 0xce, 0xeb, 0x00, 0x70, 0xd2, 0x6b, 0x00, 0x70, 0xc0, 0xe3, 0x0c, 0xb0, 0xc1, 0xa5, 0x04, 0x00, - 0x42, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xd0, 0x91, 0x00, 0x0a, 0x80, - 0x10, 0x82, 0x24, 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf8, 0xf1, 0x60, 0x31, 0x7e, 0x45, 0x80, 0xcd, 0xb7, 0xf9, - 0xfa, 0x95, 0x77, 0x24, 0x3c, 0xa0, 0x62, 0x4b, 0x4b, 0x0d, 0xf5, 0xd3, 0xd7, 0xca, 0xc8, 0x5c, 0x12, 0xa8, 0x07, - 0x23, 0x4c, 0x32, 0x13, 0x89, 0x83, 0xe0, 0xa0, 0x5a, 0x97, 0xcc, 0x3f, 0x0a, 0xc7, 0xf0, 0x15, 0x00, 0x00, 0x40, - 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x40, 0x31, 0x7e, 0xc5, 0xc0, 0x31, 0x6a, 0x45, 0xe0, 0x31, - 0x6c, 0xc5, 0xdc, 0x87, 0x00, 0x02, 0x01, 0x00, 0x42, 0x23, 0x80, 0x50, 0xab, 0xe2, 0x00, 0x50, 0x2b, 0xed, 0x80, - 0x6a, 0xad, 0xe4, 0x00, 0x60, 0x2d, 0xf9, 0x20, 0x03, 0x6c, 0x49, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, - 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x6b, 0x65, 0x00, 0x50, 0x2b, 0xf9, 0x20, 0xe0, 0x7d, - 0x22, 0x00, 0xe0, 0x69, 0xe5, 0x00, 0x40, 0x29, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x67, 0x65, 0x00, 0x30, - 0x27, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x20, 0x25, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, - 0x00, 0x4c, 0x23, 0x00, 0x60, 0x8a, 0x70, 0x60, 0xb0, 0x92, 0x22, 0x1f, 0xb0, 0x90, 0x22, 0x20, 0x00, 0x4e, 0x23, - 0x00, 0x74, 0x50, 0xe4, 0x00, 0x80, 0x4e, 0xe3, 0x00, 0x70, 0x0e, 0x63, 0x00, 0x70, 0x0e, 0x63, 0x00, 0x70, 0x0e, - 0x63, 0x01, 0x70, 0x4e, 0x24, 0x00, 0x53, 0x0a, 0x7d, 0x01, 0x80, 0x50, 0x24, 0x90, 0x92, 0x00, 0x8a, 0x00, 0x00, - 0x00, 0x84, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, - 0xe0, 0x67, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x20, 0x25, 0xf9, - 0x00, 0x03, 0x68, 0x45, 0xfa, 0x94, 0x00, 0xcb, 0x53, 0xaa, 0xfc, 0x6e, 0x75, 0x94, 0xff, 0xb2, 0xed, 0x06, 0x75, - 0x8b, 0xcf, 0xf5, 0xf9, 0xb5, 0xae, 0x0f, 0x0d, 0x0d, 0x48, 0xa6, 0x9d, 0x77, 0x8c, 0x8b, 0xdd, 0x53, 0xd1, 0xc8, - 0x16, 0x20, 0x03, 0x6a, 0x45, 0x40, 0xb0, 0x7a, 0xa2, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, - 0x3b, 0x63, 0x00, 0x00, 0xc0, 0x2d, 0x64, 0x92, 0x00, 0x82, 0x20, 0x90, 0x40, 0x28, 0xb8, 0x93, 0x00, 0x88, 0x00, - 0xd0, 0x65, 0xe3, 0xac, 0x93, 0x00, 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x67, 0x65, - 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x20, 0x25, 0xf9, 0x00, 0x03, 0x68, - 0x45, 0x20, 0x03, 0x6a, 0x45, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x20, 0xe1, 0x6b, 0x80, 0x00, 0x7a, 0xa3, 0x00, 0x00, - 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x2c, 0x92, 0x00, 0x82, 0x00, 0x20, 0xe1, 0x6b, 0x80, - 0xd0, 0x7b, 0x22, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x70, 0x81, 0x00, 0x02, - 0x00, 0x00, 0x56, 0x63, 0x80, 0xd5, 0x7b, 0xe2, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, - 0x63, 0x2c, 0x92, 0x00, 0x82, 0x80, 0xb0, 0x40, 0xa8, 0xdc, 0x93, 0x00, 0x08, 0x64, 0x92, 0x00, 0x82, 0x60, 0x90, - 0x40, 0xa8, 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, 0xe3, 0x40, 0x90, 0x40, 0x28, 0xac, 0x93, 0x00, 0x88, 0x00, - 0x00, 0x66, 0xa3, 0x20, 0x90, 0x40, 0x28, 0xa0, 0x93, 0x00, 0x88, 0x00, 0x00, 0x68, 0x23, 0x80, 0x52, 0xab, 0x62, - 0x80, 0x53, 0xeb, 0x62, 0xf8, 0x93, 0x00, 0x98, 0xfa, 0xc8, 0x41, 0xc5, 0x5d, 0xc9, 0x24, 0x51, 0x56, 0xbf, 0xc9, - 0xa9, 0x64, 0x3f, 0xca, 0x64, 0xda, 0x26, 0xd1, 0xc6, 0x5a, 0xb4, 0x61, 0x44, 0x9c, 0x75, 0x00, 0x39, 0xb9, 0x94, - 0x2f, 0x9f, 0x38, 0xa0, 0x17, 0x80, 0x42, 0xa9, 0x62, 0x80, 0x43, 0xe9, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x32, - 0xa7, 0x62, 0x80, 0x33, 0xe7, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x22, 0xa5, 0x62, 0x80, 0x23, 0xe5, 0x62, 0x10, - 0xb0, 0x90, 0x22, 0xd0, 0x93, 0x00, 0x8a, 0x80, 0x2e, 0xa5, 0x64, 0xf8, 0x93, 0x00, 0x98, 0x00, 0x20, 0xe1, 0x6b, - 0x00, 0x00, 0x6a, 0xa3, 0xec, 0x93, 0x00, 0x98, 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x6a, 0xa3, 0xff, 0x00, 0x4e, - 0xa3, 0x80, 0x53, 0xeb, 0x62, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x66, 0xa3, 0x00, 0xd0, 0x65, 0xe3, 0x60, 0x31, - 0x7e, 0x45, 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x21, 0xf9, 0x00, 0x10, 0x23, 0xf9, 0x80, 0x08, 0xb3, 0x79, 0x00, - 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x60, 0x31, 0x7e, 0x45, 0xe0, 0x03, 0x74, 0x45, - 0x00, 0x04, 0x44, 0x45, 0x80, 0xac, 0x83, 0xff, 0x80, 0x2c, 0x84, 0xff, 0x80, 0xb0, 0x87, 0x7b, 0x00, 0x31, 0x86, - 0x7b, 0x40, 0x03, 0x46, 0xc9, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0x03, 0x58, 0x45, 0x00, 0xc0, - 0x18, 0xf9, 0x10, 0x85, 0x00, 0x82, 0x00, 0x10, 0xbc, 0x28, 0x10, 0x95, 0x00, 0x8a, 0x01, 0x00, 0x5a, 0x23, 0x00, - 0xb6, 0x9c, 0x67, 0x00, 0x90, 0x79, 0xe3, 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x4e, 0xc9, 0x80, 0x03, 0x50, 0x49, - 0xa0, 0x03, 0x52, 0x49, 0xc0, 0x03, 0x54, 0x49, 0x40, 0x03, 0x78, 0x45, 0xfa, 0xee, 0x1e, 0x5f, 0x3d, 0xb1, 0xc9, - 0xcc, 0xa5, 0x4c, 0x27, 0xa7, 0xdb, 0x16, 0xaa, 0xde, 0x67, 0x74, 0xd3, 0x5b, 0x19, 0x58, 0x54, 0x83, 0xea, 0x51, - 0x85, 0x41, 0x6f, 0xec, 0x68, 0x4b, 0xce, 0x78, 0x18, 0xc0, 0x31, 0x56, 0x45, 0xe0, 0x31, 0x58, 0x45, 0x01, 0x00, - 0x5a, 0x23, 0x00, 0xb6, 0x9c, 0x67, 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x56, 0xc5, 0x80, 0x03, 0x58, 0xc5, 0xa0, - 0x03, 0x5a, 0xc5, 0xc0, 0x03, 0x5c, 0xc5, 0x00, 0x00, 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, 0x00, 0x07, 0x9c, 0xfd, - 0x18, 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0xe4, 0x84, 0x00, - 0x82, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x20, 0x03, 0x48, 0x45, 0xff, 0x0f, 0x7e, 0xa3, 0x00, 0xf0, - 0x41, 0x28, 0x00, 0x82, 0x84, 0xe8, 0x18, 0x95, 0x00, 0x0a, 0x00, 0xf0, 0x41, 0x28, 0x00, 0x82, 0x84, 0xe8, 0x18, - 0x95, 0x00, 0x0a, 0xc3, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x10, 0x00, 0x7c, 0x22, 0x40, 0x03, 0x4a, 0xc5, - 0x00, 0x40, 0x08, 0xf9, 0x00, 0xe0, 0x49, 0x69, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4b, 0xe9, 0x00, 0x00, 0x40, - 0x23, 0x50, 0x00, 0x42, 0xa3, 0x2c, 0x95, 0x00, 0x98, 0x36, 0x00, 0x40, 0x23, 0x1c, 0x95, 0x00, 0x98, 0x36, 0x00, - 0x40, 0x23, 0x3c, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, 0x42, 0x23, 0x2c, 0x95, 0x00, 0x98, 0x00, - 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x94, 0x81, 0x00, 0x98, 0x00, 0x00, 0x8c, 0x67, 0x00, 0x63, 0x8c, 0xfb, - 0x01, 0x00, 0x7c, 0xa3, 0x00, 0x6f, 0x8e, 0x7b, 0x00, 0x70, 0xbc, 0x28, 0x6c, 0x96, 0x00, 0x88, 0xfa, 0xf5, 0xad, - 0x23, 0xf7, 0x3d, 0x20, 0xa5, 0xfe, 0x69, 0xe0, 0xd6, 0xbf, 0x89, 0xf0, 0x4d, 0x23, 0xcb, 0x7f, 0xa7, 0x17, 0x64, - 0xb3, 0xab, 0x19, 0x99, 0x6f, 0x64, 0x6a, 0xb4, 0xa3, 0x85, 0x57, 0x50, 0x19, 0x60, 0x32, 0x50, 0x45, 0x00, 0x00, - 0x7c, 0x23, 0x00, 0xe4, 0x93, 0x7d, 0x00, 0x83, 0x90, 0x67, 0x80, 0x73, 0x94, 0x67, 0x80, 0xa3, 0x96, 0x67, 0x80, - 0x84, 0x90, 0x67, 0x00, 0x85, 0x90, 0xfb, 0x80, 0x84, 0x90, 0x67, 0x80, 0xb5, 0x98, 0x67, 0x00, 0xc6, 0x94, 0x67, - 0x80, 0xc5, 0x98, 0xe7, 0x00, 0xc4, 0x98, 0xe7, 0x00, 0xa6, 0x94, 0x67, 0x00, 0xa0, 0x42, 0x63, 0xac, 0x83, 0x00, - 0x02, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x25, 0x9a, 0x67, 0x00, 0xd6, 0x9a, 0x67, 0x00, 0x32, - 0x7c, 0xc5, 0x00, 0xdf, 0x9c, 0x67, 0x80, 0xd6, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa4, 0x88, 0x68, 0xc0, - 0x95, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, 0xc8, 0x95, 0x00, 0x98, 0x00, 0xe0, 0x42, 0xe3, 0xc8, 0x95, 0x00, 0x98, - 0x00, 0x93, 0x84, 0xe7, 0x00, 0xd0, 0x86, 0xe7, 0x01, 0xe0, 0x89, 0xa4, 0x00, 0x32, 0x86, 0xe7, 0x00, 0x3f, 0x88, - 0xe7, 0x00, 0x83, 0x8c, 0xe7, 0x80, 0x31, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa3, 0xbc, 0xfd, 0x00, 0xe0, - 0xbd, 0xa8, 0xfc, 0x95, 0x00, 0x0a, 0x00, 0x30, 0x40, 0xe3, 0x04, 0x96, 0x00, 0x98, 0x00, 0x40, 0x40, 0x63, 0x04, - 0x96, 0x00, 0x98, 0x80, 0x10, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa4, 0xbc, 0x7d, 0x00, 0xe0, 0xbd, 0xa8, - 0x20, 0x96, 0x00, 0x8a, 0x00, 0x90, 0x46, 0xe3, 0x28, 0x96, 0x00, 0x18, 0x00, 0x20, 0x46, 0x63, 0x28, 0x96, 0x00, - 0x18, 0xfa, 0xfd, 0x83, 0xd3, 0x73, 0x71, 0xfe, 0x2c, 0xbc, 0x12, 0xe4, 0x48, 0xaa, 0x70, 0xb8, 0xf5, 0xa9, 0xe4, - 0x29, 0x65, 0xf1, 0x21, 0x20, 0xc5, 0x4d, 0x6f, 0x9c, 0x37, 0x2a, 0xa4, 0x7c, 0x59, 0xcc, 0x28, 0x1a, 0x38, 0x96, - 0x00, 0x8a, 0x00, 0x10, 0x44, 0xe3, 0x01, 0x00, 0x7c, 0xa3, 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, 0x44, 0x63, 0x00, - 0x00, 0x7c, 0x23, 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, 0x40, 0x23, 0x00, 0x01, 0x82, 0xfd, 0x01, 0x00, 0x50, 0x23, - 0x00, 0x24, 0x8c, 0x62, 0x00, 0xe3, 0xbd, 0x68, 0x64, 0x96, 0x00, 0x08, 0x00, 0x10, 0x56, 0xe3, 0x6c, 0x96, 0x00, - 0x18, 0x00, 0x20, 0x56, 0xe3, 0x6c, 0x96, 0x00, 0x18, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, - 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, 0x02, 0x00, 0x70, 0xbc, 0x28, 0x70, 0x96, 0x00, 0x08, 0x80, - 0xb3, 0x9a, 0xe7, 0x00, 0x30, 0x56, 0x63, 0x00, 0x70, 0x58, 0x63, 0x00, 0x00, 0x00, 0x84, 0x40, 0x31, 0x7e, 0xc5, - 0x00, 0x05, 0x42, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0xb4, 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, 0x02, 0x00, 0x70, 0xbc, - 0x28, 0x98, 0x96, 0x00, 0x08, 0x00, 0x33, 0x7c, 0x45, 0x00, 0x3f, 0x94, 0x67, 0x80, 0x75, 0x9a, 0xe7, 0x80, 0x33, - 0x98, 0x7d, 0x80, 0x33, 0x9c, 0xfb, 0x00, 0xd7, 0x80, 0x67, 0x00, 0x00, 0xbc, 0xa8, 0x98, 0x96, 0x00, 0x08, 0x00, - 0xa7, 0x96, 0x67, 0x80, 0xc6, 0x98, 0xe7, 0x00, 0xb6, 0x9c, 0x67, 0x00, 0xb0, 0x96, 0x67, 0x00, 0xc0, 0x98, 0x67, - 0x00, 0x00, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x00, 0x08, 0x8d, 0xef, 0x00, 0x06, 0x8f, 0xef, 0x80, 0x63, 0x8c, - 0x6f, 0x00, 0x60, 0x42, 0x63, 0xfa, 0xef, 0xdf, 0xf8, 0xe0, 0x42, 0x0a, 0x57, 0x90, 0x1c, 0x19, 0x51, 0x02, 0x57, - 0x93, 0xa8, 0xee, 0x16, 0x63, 0x4b, 0x79, 0xb3, 0xcb, 0x28, 0x09, 0xab, 0x02, 0xea, 0xb2, 0x15, 0xed, 0x35, 0x27, - 0x00, 0x1b, 0xa4, 0x82, 0x00, 0x02, 0x00, 0x30, 0x52, 0xe3, 0x80, 0x93, 0x92, 0x6f, 0x00, 0x31, 0x40, 0xc5, 0x00, - 0x90, 0x94, 0xef, 0x80, 0x94, 0x90, 0x6f, 0x00, 0x88, 0x90, 0x6f, 0x00, 0x86, 0x80, 0xe8, 0x00, 0x90, 0x54, 0xef, - 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x68, 0xe3, 0x20, 0x31, 0x40, 0x45, 0x60, 0x30, 0x42, 0xc5, 0x80, 0x30, 0x44, - 0x45, 0x00, 0x4a, 0x97, 0x6f, 0x80, 0x05, 0x96, 0xef, 0x80, 0xb5, 0x98, 0xef, 0x80, 0xc5, 0x98, 0x7b, 0x01, 0x00, - 0x48, 0x23, 0x00, 0xc2, 0x9a, 0xfb, 0x80, 0x26, 0x9a, 0x6f, 0x00, 0x00, 0x48, 0xa3, 0x00, 0x46, 0x9c, 0xfd, 0x00, - 0xc0, 0x80, 0xa8, 0x00, 0xe0, 0x40, 0x6f, 0x00, 0x17, 0x9c, 0x6f, 0x80, 0xd6, 0x98, 0xef, 0x00, 0xe7, 0xa0, 0x6f, - 0x00, 0x18, 0x9e, 0xef, 0x80, 0xc7, 0x98, 0xfb, 0x80, 0xc6, 0x98, 0x6f, 0x00, 0x07, 0xa1, 0x6f, 0x00, 0x28, 0x9e, - 0xef, 0x80, 0xc7, 0x98, 0xfb, 0x80, 0xb6, 0xa2, 0xef, 0xf0, 0x96, 0x00, 0x82, 0x00, 0xba, 0xa4, 0x6f, 0x00, 0x25, - 0xa5, 0xef, 0x00, 0xd0, 0x62, 0x6f, 0x00, 0xa0, 0x64, 0xef, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x19, 0x82, 0xfd, 0x00, - 0x49, 0x81, 0x68, 0x01, 0x00, 0x44, 0x23, 0x00, 0x01, 0x80, 0xe2, 0x00, 0x10, 0x64, 0x6f, 0x00, 0x10, 0x64, 0x63, - 0x00, 0x27, 0xa5, 0x6f, 0x00, 0xe0, 0x66, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x42, 0xc5, 0x00, 0x00, 0xc4, - 0x73, 0xb4, 0xa3, 0x00, 0x82, 0x28, 0x97, 0x00, 0x02, 0xfa, 0x5f, 0xa4, 0x00, 0x8c, 0xc3, 0xac, 0x26, 0x42, 0xb5, - 0x43, 0x7a, 0x37, 0x49, 0x9c, 0x12, 0xb3, 0xd4, 0x14, 0x38, 0xa2, 0xbe, 0x25, 0xdf, 0x86, 0x12, 0x08, 0xf5, 0x99, - 0x66, 0x3b, 0x7d, 0x41, 0xd8, 0x1b, 0x00, 0x30, 0xbd, 0x28, 0xc8, 0x97, 0x00, 0x88, 0x00, 0x00, 0x00, 0x84, 0x20, - 0x30, 0x7e, 0x45, 0x60, 0x10, 0x40, 0x28, 0x18, 0x98, 0x00, 0x08, 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x66, 0xe5, - 0x00, 0x30, 0x27, 0xf9, 0x00, 0x00, 0x68, 0x23, 0x80, 0x49, 0xb9, 0x79, 0x80, 0xc9, 0x83, 0xe8, 0xb4, 0x99, 0x00, - 0x0a, 0x00, 0xc0, 0x83, 0xa8, 0xb4, 0x99, 0x00, 0x88, 0x2c, 0x98, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, 0x00, 0x00, - 0xe8, 0xf3, 0x80, 0x49, 0xb9, 0x79, 0x00, 0xc0, 0x83, 0xa8, 0xb4, 0x99, 0x00, 0x88, 0x00, 0x00, 0xc0, 0xf3, 0x00, - 0x00, 0xc2, 0x73, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x00, 0xc6, 0xf3, 0x00, 0x00, 0xc0, 0x63, 0x0a, 0xc0, 0xc1, 0x25, - 0x04, 0x00, 0x44, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x04, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x4c, 0x98, 0x00, - 0x0a, 0x80, 0x20, 0x84, 0x24, 0x00, 0x20, 0xc0, 0xe9, 0x00, 0x00, 0xfa, 0x71, 0x20, 0x01, 0x78, 0xc9, 0x40, 0x01, - 0x7a, 0x49, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xcf, 0xf9, 0xff, 0x00, 0x30, 0x7e, 0xc5, 0xa0, - 0x30, 0x58, 0x45, 0xc0, 0x30, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, - 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x9c, 0xa4, 0x00, 0xc7, 0x98, 0x6f, 0x00, 0xd7, 0x9a, 0x6f, 0x00, 0xc0, 0x52, - 0xe3, 0x00, 0xd0, 0x54, 0x63, 0x00, 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0xfa, 0x3b, 0xbd, 0x2a, 0xed, 0x5b, - 0x43, 0x55, 0x15, 0x85, 0x4e, 0x90, 0xc3, 0x5d, 0x5b, 0xee, 0x00, 0x81, 0xb1, 0x16, 0x4d, 0x1a, 0xda, 0x4c, 0x2f, - 0xbd, 0x46, 0x4b, 0x0e, 0xa8, 0xf3, 0x70, 0xf5, 0xb0, 0x1c, 0xc0, 0x99, 0x00, 0x0a, 0x80, 0x30, 0x50, 0x45, 0xd8, - 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0xc0, 0x99, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0xc0, 0x99, 0x00, 0x0a, - 0x00, 0xb0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0x90, 0x92, 0x6f, 0x80, 0xa0, 0x94, 0x6f, 0x00, 0x90, 0x19, - 0x6d, 0x00, 0xc0, 0x18, 0xf3, 0xaa, 0xc0, 0x98, 0xa4, 0x00, 0xc0, 0x18, 0xf3, 0x00, 0x01, 0x40, 0xc5, 0xff, 0x00, - 0x48, 0xa3, 0x00, 0x02, 0xa8, 0xe2, 0x60, 0x40, 0x41, 0xa8, 0x08, 0x99, 0x00, 0x08, 0x02, 0xc0, 0x98, 0x24, 0x0c, - 0x99, 0x00, 0x18, 0x01, 0xc0, 0x98, 0x24, 0x00, 0xc0, 0x18, 0xf3, 0x01, 0xc0, 0x98, 0x24, 0x04, 0xa4, 0xd9, 0x37, - 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xd3, 0xb7, 0xb4, 0x99, 0x00, 0x9c, 0x06, 0xa4, 0xd5, 0xb7, 0xb4, 0x99, 0x00, - 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, 0x00, 0x9c, 0x20, 0x01, - 0x78, 0xc5, 0x40, 0x01, 0x7a, 0x45, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, - 0xa3, 0x00, 0x82, 0x00, 0xc0, 0xb9, 0xfd, 0x00, 0x00, 0xc4, 0x73, 0x00, 0xd1, 0xbb, 0xe8, 0x00, 0x90, 0x75, 0xe3, - 0xff, 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, 0x80, 0xc4, 0x94, 0x68, 0x00, 0xa4, 0xf9, - 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0x37, 0xfa, 0x45, - 0xd4, 0x14, 0xe9, 0x9f, 0xd9, 0x0e, 0x80, 0xa8, 0xb7, 0xfa, 0xe2, 0x4c, 0xc3, 0x28, 0xc7, 0xdb, 0x2b, 0xcf, 0xe3, - 0x57, 0x92, 0x30, 0x13, 0x88, 0x36, 0x66, 0x56, 0x5a, 0x6d, 0x6c, 0x6d, 0x88, 0x1d, 0xb4, 0x99, 0x00, 0x9c, 0x03, - 0xa4, 0xc5, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x04, 0xa4, 0xd5, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, - 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, - 0x84, 0x05, 0xa4, 0xc1, 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0x41, 0x00, - 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x10, 0x40, 0x28, 0xe0, 0x99, 0x00, 0x08, 0x10, 0x00, 0x48, 0xa2, 0x00, - 0x40, 0x66, 0xe5, 0xe4, 0x99, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, 0x01, 0x00, 0x64, 0xa3, 0x00, 0x20, 0x25, 0xed, - 0x00, 0x00, 0x62, 0x23, 0x00, 0x01, 0x60, 0x23, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xf9, - 0xeb, 0x00, 0xd0, 0x3b, 0xf9, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, - 0x80, 0x70, 0x80, 0x0e, 0xba, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0xd0, 0xfb, 0x62, 0x00, 0xc0, 0x39, 0xf9, 0x20, - 0x01, 0x7a, 0x49, 0x40, 0x01, 0x78, 0xc9, 0x00, 0x00, 0xfc, 0xf3, 0x60, 0x31, 0x7e, 0x45, 0x00, 0xdf, 0xf9, 0x7f, - 0x40, 0x31, 0x7e, 0xc5, 0xc0, 0x31, 0x56, 0x45, 0xe0, 0x31, 0x58, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, - 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x9a, 0xa4, 0x80, 0xb6, 0x96, 0xe7, 0x00, 0xb6, 0x9c, 0x67, 0x80, 0xc6, - 0x98, 0xe7, 0xfa, 0xf3, 0xe9, 0x29, 0x44, 0x9c, 0x55, 0x88, 0x7a, 0x3f, 0xb9, 0xcf, 0x5a, 0xf9, 0x23, 0xfa, 0xaf, - 0x40, 0xef, 0xd0, 0xb2, 0xa3, 0x3c, 0x61, 0xb8, 0xd7, 0x76, 0xf0, 0x28, 0x83, 0xd1, 0x75, 0x80, 0x60, 0x1e, 0xa0, - 0x31, 0x4c, 0xc5, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0x00, 0xe0, 0x54, 0x63, - 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x70, 0x9b, 0x00, - 0x0a, 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, 0xe4, 0x84, 0x00, 0x82, 0x00, 0x90, 0x15, 0x6d, 0x00, 0xa0, - 0x14, 0xf3, 0xaa, 0xa0, 0x94, 0xa4, 0x00, 0xa0, 0x14, 0xf3, 0x00, 0x01, 0x40, 0xc5, 0xff, 0x00, 0x48, 0xa3, 0x00, - 0x02, 0x92, 0xe2, 0x60, 0x90, 0x40, 0xa8, 0xc0, 0x9a, 0x00, 0x88, 0x02, 0xa0, 0x94, 0x24, 0xc4, 0x9a, 0x00, 0x98, - 0x01, 0xa0, 0x94, 0x24, 0x00, 0xa0, 0x14, 0xf3, 0x02, 0xa0, 0x94, 0x24, 0x04, 0xa4, 0xd5, 0x37, 0x7c, 0x9b, 0x00, - 0x9c, 0x05, 0xa4, 0xd1, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, - 0xc1, 0x39, 0x7c, 0x9b, 0x00, 0x9c, 0x20, 0x01, 0x78, 0xc5, 0x40, 0x01, 0x7a, 0x45, 0x00, 0x00, 0x40, 0x23, 0x60, - 0x31, 0x7e, 0x45, 0x00, 0x0e, 0xbc, 0xf9, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, - 0x01, 0x00, 0x80, 0x24, 0x00, 0xe0, 0xb9, 0x7d, 0x00, 0x00, 0xc4, 0x73, 0x00, 0xd1, 0xbb, 0xe8, 0x00, 0x90, 0x75, - 0xe3, 0xff, 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, 0x80, 0xa4, 0x94, 0x68, 0x00, 0xa4, - 0xf9, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0xfa, 0xad, 0x56, 0x9d, 0x5b, 0x5e, 0x2b, 0xc5, 0x13, 0xfa, 0x8b, 0x0e, 0x56, - 0x14, 0xa5, 0xf3, 0xd4, 0xfd, 0x10, 0xfa, 0xc4, 0xf4, 0xbc, 0x0c, 0xaa, 0x96, 0x7a, 0x7e, 0xd4, 0x5f, 0x98, 0xd1, - 0x37, 0x38, 0x1f, 0x01, 0xa4, 0xfb, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0x37, 0x7c, 0x9b, 0x00, 0x9c, - 0x03, 0xa4, 0xc5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x04, 0xa4, 0xd5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, - 0xb9, 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0x9b, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, - 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0x41, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0xf2, - 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xc6, 0xf3, 0x00, 0x00, 0xc8, 0x73, 0x00, 0x00, 0xca, 0xf3, - 0x00, 0x00, 0xcc, 0xf3, 0x00, 0x30, 0xc0, 0x63, 0x0b, 0x40, 0xc1, 0x25, 0x4c, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x40, - 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x43, 0x63, 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, - 0x7d, 0x24, 0xb0, 0x9b, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, 0x0e, 0x00, 0x7c, 0xa3, 0x80, 0x00, 0x00, 0xfd, 0x00, - 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xc8, 0x9b, 0x00, 0x0a, 0x04, 0x00, 0x7c, 0xa3, 0x00, 0x00, 0x42, 0xa3, - 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xe0, 0x9b, 0x00, 0x0a, 0x1a, 0x00, 0x7c, - 0xa3, 0x00, 0x0f, 0xc0, 0xe2, 0x80, 0x00, 0x80, 0x24, 0x00, 0x00, 0xc0, 0x69, 0x00, 0x00, 0xf6, 0x71, 0x00, 0x00, - 0xc0, 0x2d, 0x00, 0x30, 0xc6, 0xeb, 0x00, 0x30, 0xca, 0xeb, 0xfa, 0x0c, 0xb2, 0x39, 0xf3, 0xa2, 0xe5, 0x7c, 0xb2, - 0x21, 0x30, 0xee, 0xdd, 0x77, 0x8b, 0x10, 0x23, 0x20, 0x70, 0x11, 0xd4, 0x62, 0x1e, 0xca, 0xca, 0xbd, 0xab, 0xe7, - 0x53, 0x29, 0xf5, 0x60, 0xa6, 0x10, 0x20, 0x00, 0x30, 0xc0, 0x63, 0x0b, 0xb0, 0xc1, 0x25, 0x04, 0x00, 0x42, 0x23, - 0x11, 0x00, 0x7c, 0x23, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x20, 0x9c, 0x00, 0x8a, 0x80, 0x10, 0x82, - 0x24, 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf8, 0xf1, 0x20, 0x01, 0x64, 0x49, 0x20, 0x30, 0x7e, 0x45, 0x80, 0xcd, - 0xb7, 0xf9, 0x00, 0xb0, 0x81, 0xa8, 0xdc, 0x9d, 0x00, 0x88, 0xa0, 0x30, 0x6c, 0xc5, 0xc0, 0x30, 0x6e, 0x45, 0xa8, - 0x8b, 0x00, 0x02, 0x00, 0x00, 0x46, 0xe3, 0x00, 0x00, 0x40, 0xa8, 0xfc, 0x9d, 0x00, 0x8a, 0x20, 0x30, 0x7e, 0x45, - 0x00, 0x00, 0x40, 0x23, 0x00, 0x0b, 0xac, 0x79, 0x00, 0x60, 0x81, 0x28, 0xe4, 0x9d, 0x00, 0x08, 0x00, 0x00, 0xc4, - 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0x00, 0x72, 0x63, 0x01, 0x90, 0xb3, 0x24, 0x80, 0x9d, - 0x83, 0x7f, 0xa8, 0x81, 0x00, 0x02, 0x20, 0x01, 0x64, 0x45, 0x80, 0x2c, 0x95, 0xff, 0x80, 0x6c, 0x97, 0xff, 0x80, - 0xa5, 0x99, 0x7f, 0x80, 0x55, 0x9b, 0xff, 0x80, 0xc6, 0x96, 0xfb, 0x80, 0xa5, 0x94, 0x7b, 0x00, 0x15, 0x94, 0xff, - 0x00, 0xa0, 0x80, 0xa8, 0xec, 0x9d, 0x00, 0x88, 0x40, 0x01, 0x54, 0x49, 0x00, 0xa0, 0x42, 0x63, 0xa8, 0x81, 0x00, - 0x02, 0x80, 0x20, 0xb9, 0x7f, 0x80, 0x60, 0xb7, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, 0xc0, 0x30, - 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x94, 0x8a, 0x00, 0x82, 0x00, 0x90, 0x5e, 0xe3, 0xfa, 0x2d, 0x2b, 0x3c, 0x7a, - 0xab, 0xd9, 0xd4, 0x8f, 0x2e, 0x43, 0xd9, 0xfb, 0x55, 0xc9, 0xc1, 0x31, 0x8e, 0xa8, 0x98, 0xad, 0xc1, 0x02, 0x10, - 0xd2, 0xd3, 0x6d, 0xe5, 0x5d, 0xfd, 0x4f, 0x8b, 0xe2, 0xe8, 0x20, 0x00, 0xa0, 0x60, 0x63, 0x00, 0xb0, 0x62, 0x63, - 0x60, 0x01, 0x58, 0xc5, 0x80, 0x01, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0xb0, 0x79, 0x63, 0x94, 0x8a, 0x00, - 0x82, 0x80, 0xf5, 0x84, 0xef, 0x80, 0x98, 0x86, 0xef, 0x80, 0x21, 0x80, 0xe8, 0x38, 0x9d, 0x00, 0x0a, 0x80, 0x05, - 0x85, 0x6f, 0x80, 0xa8, 0x86, 0xef, 0x80, 0x21, 0x80, 0xe8, 0xf4, 0x9d, 0x00, 0x0a, 0xfc, 0x89, 0x00, 0x02, 0x00, - 0x90, 0x58, 0xe3, 0x00, 0xa0, 0x5a, 0x63, 0x00, 0xb0, 0x5c, 0xe3, 0x48, 0x9d, 0x00, 0x98, 0x00, 0xf0, 0x58, 0xe3, - 0x00, 0x00, 0x5b, 0xe3, 0x00, 0x10, 0x5d, 0x63, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe0, 0x42, 0xe3, 0x98, 0x83, 0x00, - 0x82, 0x80, 0xc0, 0x98, 0x6f, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x06, 0x98, 0x79, 0x00, 0x00, - 0x7e, 0xa3, 0x00, 0xf0, 0x41, 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, 0x9d, 0x00, 0x0a, 0x00, 0xf0, 0x41, 0x28, 0x00, - 0xcb, 0x82, 0x68, 0xf4, 0x9d, 0x00, 0x0a, 0x00, 0x00, 0x46, 0x23, 0xc3, 0x00, 0x44, 0xa3, 0x64, 0x81, 0x00, 0x02, - 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x45, 0x69, 0x00, 0x30, 0x40, 0xa8, 0x01, 0x00, 0x42, 0x23, 0xbc, 0x9d, 0x00, - 0x0a, 0x50, 0x00, 0x42, 0xa3, 0x10, 0x00, 0x7c, 0x22, 0x00, 0x60, 0x2d, 0xf9, 0x00, 0xe0, 0x6d, 0x69, 0x20, 0xe0, - 0x7d, 0x22, 0x40, 0x01, 0x54, 0x45, 0x00, 0xa0, 0x14, 0xf9, 0x00, 0xe0, 0x55, 0xe9, 0x00, 0x30, 0x40, 0xe3, 0xfa, - 0x50, 0x17, 0xdd, 0xae, 0x37, 0x2e, 0xa3, 0x8e, 0x0a, 0x04, 0xd0, 0x65, 0x48, 0x11, 0x5d, 0xa6, 0x97, 0xda, 0x82, - 0x32, 0x82, 0x11, 0x54, 0xaf, 0xd8, 0x29, 0x34, 0x53, 0x60, 0x73, 0x91, 0x54, 0xc0, 0x21, 0x00, 0x00, 0x68, 0x23, - 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x76, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, - 0x23, 0x94, 0x81, 0x00, 0x98, 0x21, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, 0x22, 0x00, 0x46, 0x23, 0xfc, 0x9d, - 0x00, 0x98, 0x23, 0x00, 0x46, 0xa3, 0xfc, 0x9d, 0x00, 0x98, 0x24, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, 0x3c, - 0x00, 0x44, 0xa3, 0x01, 0x00, 0x42, 0x23, 0x84, 0x9d, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x40, 0x31, 0x7e, 0xc5, - 0x00, 0x00, 0x40, 0x23, 0x00, 0x08, 0x80, 0xf9, 0x00, 0x08, 0x80, 0xe8, 0xdc, 0x9e, 0x00, 0x0a, 0xd8, 0x8c, 0x00, - 0x02, 0xdc, 0x9e, 0x00, 0x0a, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, - 0xa4, 0x24, 0x00, 0x09, 0xa1, 0x67, 0x00, 0x19, 0xa3, 0x67, 0x00, 0x00, 0xfc, 0xf3, 0x80, 0x31, 0x7e, 0xc5, 0x00, - 0x3f, 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, 0x70, 0x96, 0x00, 0x02, 0x5c, 0x8e, 0x00, 0x82, 0xd0, 0x8e, 0x00, 0x02, - 0x00, 0x70, 0x6e, 0x63, 0x00, 0x80, 0x70, 0x63, 0x00, 0x90, 0x72, 0x63, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, - 0x8a, 0x00, 0x00, 0x4f, 0xe3, 0x00, 0x20, 0x51, 0x63, 0x00, 0x10, 0x53, 0xe3, 0x0c, 0x8d, 0x00, 0x82, 0x00, 0x00, - 0xfc, 0xf3, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x3f, 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, 0x5c, 0x8e, 0x00, 0x82, 0xd0, - 0x8e, 0x00, 0x02, 0xfa, 0x3b, 0x0b, 0xc2, 0x9a, 0xbf, 0xc1, 0x56, 0x52, 0x87, 0x47, 0x29, 0xe6, 0x7f, 0x67, 0x7a, - 0x11, 0xa5, 0x6b, 0x91, 0x03, 0xf7, 0xa8, 0xa5, 0xdb, 0x49, 0x07, 0x8c, 0xc0, 0x40, 0x6b, 0xf2, 0xf8, 0x98, 0x22, - 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x80, 0x04, 0x92, 0xfd, 0x00, 0x70, 0x57, - 0x63, 0x00, 0x80, 0x59, 0xe3, 0x00, 0x90, 0x5b, 0xe3, 0x0c, 0x8d, 0x00, 0x82, 0x00, 0xc0, 0x42, 0x63, 0x74, 0x84, - 0x00, 0x82, 0x80, 0xb0, 0x96, 0xe7, 0x80, 0xd0, 0x9a, 0xe7, 0x01, 0x00, 0x58, 0xa3, 0xd4, 0x8d, 0x00, 0x82, 0xe4, - 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x12, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, - 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0xa8, 0xa4, 0x00, 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, - 0x22, 0x00, 0x40, 0x48, 0xe5, 0xff, 0x00, 0x44, 0xa3, 0x00, 0x41, 0x82, 0xe2, 0x00, 0x40, 0x32, 0xf5, 0x00, 0x90, - 0x09, 0xf5, 0x00, 0x40, 0x08, 0xf5, 0x00, 0x91, 0xb3, 0xe2, 0x00, 0x41, 0x88, 0xe2, 0x00, 0x00, 0x00, 0x84, 0xf0, - 0x9e, 0x00, 0x02, 0x00, 0x90, 0x33, 0x63, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x01, 0x90, 0x75, 0x22, - 0x04, 0xa4, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x02, 0x40, 0x40, 0xa8, 0x54, 0x9f, 0x00, 0x08, 0x01, 0x40, 0x40, - 0xa8, 0x70, 0x9f, 0x00, 0x08, 0xf4, 0x00, 0x46, 0xa3, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xcc, 0x99, - 0x00, 0x82, 0x00, 0x30, 0x40, 0xa8, 0x68, 0x9f, 0x00, 0x08, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xc3, - 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xfa, 0x11, 0x0b, 0x0b, 0xbf, 0xbd, 0x78, 0xa8, 0x06, 0x83, 0xf6, 0xb6, - 0x4f, 0x3e, 0x39, 0x17, 0x95, 0x92, 0x10, 0x13, 0x6c, 0xed, 0xec, 0xda, 0xe2, 0x2c, 0x65, 0xcb, 0x8d, 0x0b, 0xa7, - 0x91, 0xef, 0x70, 0x23, 0xe4, 0x97, 0x00, 0x02, 0x00, 0x30, 0x40, 0xa8, 0x84, 0x9f, 0x00, 0x88, 0x3c, 0x00, 0x44, - 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xc3, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, - 0x40, 0xa2, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x44, 0x69, 0x00, 0x30, 0x40, 0xe3, 0x00, 0xa1, 0x00, 0x98, 0x64, - 0x81, 0x00, 0x02, 0x00, 0x00, 0x68, 0xe3, 0x00, 0x40, 0x6b, 0x22, 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x35, 0x63, - 0x01, 0xa0, 0x75, 0x22, 0xf2, 0x00, 0x46, 0xa3, 0x04, 0xa4, 0xc1, 0xb9, 0x70, 0xa0, 0x00, 0x9e, 0x04, 0xa4, 0xc5, - 0x35, 0x7c, 0xa0, 0x00, 0x1c, 0xf6, 0x00, 0x46, 0x23, 0xff, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x4a, 0x63, 0x00, 0x50, - 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0x01, 0x40, 0x40, 0xa8, 0xf4, 0x9f, 0x00, 0x08, 0x02, 0x40, 0x40, 0xa8, 0x70, - 0xa0, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0xaa, 0x40, 0x40, 0x28, 0x70, 0xa0, 0x00, 0x8a, - 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0x80, 0x4c, 0x40, 0x68, 0x70, 0xa0, 0x00, 0x8a, 0xf4, 0x00, 0x46, - 0xa3, 0x00, 0xe1, 0xbd, 0xe2, 0x02, 0xe0, 0x41, 0x28, 0x44, 0xa0, 0x00, 0x88, 0x01, 0xe0, 0x41, 0x28, 0x70, 0xa0, - 0x00, 0x8a, 0x50, 0x00, 0x42, 0xa3, 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, 0x00, 0x1c, 0x06, 0xa4, 0xe3, 0x35, 0x7c, - 0xa0, 0x00, 0x1c, 0x50, 0xa0, 0x00, 0x18, 0x30, 0x00, 0x42, 0xa3, 0xfa, 0x4e, 0xad, 0x37, 0xa9, 0x48, 0x0f, 0x6d, - 0xa3, 0xed, 0x43, 0xbb, 0xa1, 0xef, 0x8b, 0xac, 0x8a, 0xef, 0xee, 0x61, 0x82, 0xb1, 0x59, 0xc9, 0xff, 0x7c, 0x80, - 0xe9, 0x51, 0xe7, 0xcd, 0x32, 0x86, 0x48, 0x24, 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, 0x00, 0x1c, 0x05, 0xa4, 0xc1, - 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0xff, 0x0f, 0x4a, 0x23, 0x80, 0x22, 0x84, 0x62, 0x00, 0x20, 0x04, 0xf3, 0xc3, 0x20, - 0x84, 0xa4, 0x00, 0x00, 0x40, 0x23, 0x8c, 0xa0, 0x00, 0x98, 0x12, 0x00, 0x44, 0xa3, 0x05, 0xa4, 0xc1, 0x39, 0x8c, - 0x9f, 0x00, 0x98, 0x3c, 0x00, 0x44, 0xa3, 0xf2, 0x00, 0x46, 0xa3, 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, 0x00, 0x98, - 0x00, 0x50, 0x45, 0xe9, 0x10, 0x40, 0x6d, 0xa2, 0x00, 0x00, 0x21, 0xf9, 0x00, 0x60, 0x61, 0xe9, 0x20, 0x60, 0x6d, - 0x22, 0x00, 0x10, 0x23, 0xf9, 0x00, 0x60, 0x63, 0x69, 0x00, 0x00, 0x40, 0x23, 0x00, 0xa1, 0x00, 0x98, 0xf0, 0x9e, - 0x00, 0x02, 0x00, 0x90, 0x33, 0x63, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x6a, 0x22, 0x03, 0x94, 0xc1, 0x39, 0x7c, - 0xa0, 0x00, 0x1c, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, 0x73, 0x22, - 0x03, 0x94, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x05, 0x94, 0xc1, - 0x39, 0xc3, 0x00, 0x44, 0xa3, 0x00, 0x50, 0x45, 0xe9, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x40, 0x23, 0x00, 0xa1, - 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, - 0x00, 0x44, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x94, 0x81, 0x00, 0x98, 0x58, 0x81, 0x00, 0x02, 0xfa, 0x43, 0xa1, 0xb7, - 0x84, 0x50, 0xf7, 0x72, 0x45, 0x64, 0xe7, 0x10, 0x4e, 0x30, 0x56, 0xae, 0x1f, 0x5f, 0xf8, 0x4b, 0x57, 0x00, 0x14, - 0x6c, 0xaf, 0xae, 0xa9, 0xfb, 0xc5, 0x15, 0xf1, 0x2a, 0x42, 0x20, 0x25, 0x00, 0x00, 0x48, 0x22, 0x00, 0x40, 0x48, - 0xe5, 0x00, 0x40, 0x04, 0xf5, 0xff, 0x00, 0x4c, 0x23, 0x00, 0x23, 0x84, 0x62, 0x00, 0x20, 0x32, 0x63, 0x01, 0x90, - 0xb3, 0x24, 0x04, 0x94, 0xcb, 0xb5, 0x0c, 0xa2, 0x00, 0x1c, 0xff, 0x00, 0x4c, 0x23, 0x00, 0x53, 0x8e, 0xe2, 0x01, - 0x70, 0x40, 0xa8, 0x00, 0xa2, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x50, 0x0a, 0xf5, - 0x00, 0x53, 0x8e, 0xe2, 0x00, 0x71, 0x40, 0x68, 0xf4, 0xa1, 0x00, 0x0a, 0x05, 0x94, 0xcb, 0x35, 0x0c, 0xa2, 0x00, - 0x1c, 0x60, 0x01, 0x4a, 0xc9, 0x06, 0x94, 0xcb, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x80, 0x01, 0x4a, 0x49, 0x05, 0x94, - 0xc1, 0x39, 0x01, 0x90, 0x73, 0x24, 0x00, 0x94, 0xf5, 0xb5, 0x0c, 0xa2, 0x00, 0x1c, 0x01, 0x94, 0xed, 0x35, 0x0c, - 0xa2, 0x00, 0x1c, 0x02, 0x94, 0xeb, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x03, 0x94, 0xef, 0x35, 0x0c, 0xa2, 0x00, 0x1c, - 0x05, 0x94, 0xc1, 0x39, 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x64, 0x65, 0x00, 0x20, 0x25, 0xf9, 0x20, 0x30, 0x7e, - 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, 0x00, 0x50, - 0xab, 0xfb, 0x00, 0x00, 0xd4, 0xf3, 0x00, 0x65, 0xad, 0x68, 0x00, 0x75, 0xaf, 0x68, 0x80, 0x6b, 0xa9, 0xe8, 0xa0, - 0x00, 0x60, 0xc5, 0x00, 0x00, 0x21, 0xf9, 0xc0, 0x00, 0x62, 0x45, 0x88, 0x9b, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, - 0xfa, 0x9b, 0x81, 0xa2, 0x92, 0x89, 0x54, 0x3f, 0x38, 0xfd, 0xfd, 0x35, 0x84, 0xd1, 0x73, 0xac, 0x9b, 0xcf, 0xc9, - 0xf2, 0x3f, 0x5f, 0xa8, 0x25, 0x95, 0x4f, 0xf7, 0xa4, 0xa3, 0x71, 0xcc, 0x62, 0x90, 0xf8, 0x25, 0xf6, 0x00, 0x46, - 0x23, 0x14, 0xa2, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf4, 0x00, 0x46, 0xa3, 0x14, 0xa2, 0x00, 0x98, 0x05, 0x94, - 0xc1, 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x05, 0x94, 0xc1, 0x39, 0x64, - 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x12, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x00, 0x30, 0x40, 0xe3, - 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, 0x00, 0x00, 0x74, - 0xa3, 0x00, 0x00, 0x6e, 0x23, 0x94, 0x81, 0x00, 0x98, 0x20, 0x00, 0x42, 0x23, 0x94, 0x81, 0x00, 0x98, 0xf2, 0x00, - 0x40, 0xa3, 0x50, 0xa2, 0x00, 0x98, 0x00, 0x00, 0xe6, 0x73, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, - 0x00, 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0x30, 0xe7, 0x62, - 0x40, 0x00, 0x66, 0x49, 0x09, 0x00, 0x60, 0xa3, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, - 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x40, 0x00, 0x66, 0x45, 0x20, 0x00, 0x60, 0x45, 0x60, 0x00, - 0x60, 0xc9, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, - 0xa2, 0x00, 0x98, 0x20, 0x00, 0x42, 0x45, 0x00, 0x12, 0xe0, 0xb5, 0x58, 0xa2, 0x00, 0x9c, 0x40, 0x00, 0x66, 0x45, - 0x0c, 0x9e, 0x00, 0x02, 0xfa, 0x9c, 0xe8, 0x54, 0x98, 0x1b, 0x31, 0x10, 0x46, 0x38, 0xce, 0x34, 0xae, 0x23, 0x2c, - 0x4f, 0x0a, 0x24, 0xf1, 0x80, 0x15, 0xd3, 0x83, 0x23, 0xa5, 0x65, 0xf5, 0xec, 0xbf, 0x7b, 0x67, 0xa4, 0x6c, 0xd0, - 0x26, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x60, 0x00, - 0x60, 0xc5, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x10, 0xe6, 0x35, 0x58, 0xa2, 0x00, 0x9c, 0x07, 0x00, 0x40, 0xa3, 0xff, - 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, 0x42, 0x23, - 0x80, 0x30, 0xe7, 0x62, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, - 0xc9, 0x00, 0x00, 0x66, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x50, 0xa2, 0x00, 0x98, 0x00, 0x00, - 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0xe4, 0xa3, 0x00, 0x82, 0x04, 0xa4, 0x00, 0x82, 0x24, 0xa4, 0x00, 0x02, 0x00, - 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xc0, 0x63, 0x94, 0x81, 0x00, 0x98, 0x1c, 0x00, 0x7c, 0xa3, 0x00, 0x10, 0x23, 0xf9, - 0x00, 0x00, 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, 0xfd, 0x80, 0x08, 0x21, 0x7d, 0x00, 0x10, 0x23, - 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x5c, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, - 0x00, 0xfd, 0x00, 0x00, 0x21, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x78, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, 0x00, - 0x00, 0x00, 0x84, 0x54, 0x00, 0x46, 0xa3, 0x00, 0x30, 0x06, 0xf3, 0x53, 0x30, 0x86, 0xa4, 0x00, 0x30, 0x06, 0xf3, - 0x01, 0x30, 0x86, 0x24, 0x00, 0x30, 0x06, 0xf3, 0xfa, 0x40, 0x33, 0xe1, 0xc2, 0x84, 0xb0, 0xc7, 0xf0, 0xdb, 0xa4, - 0x54, 0x80, 0xf8, 0x49, 0x0c, 0x30, 0x82, 0x86, 0x13, 0x5a, 0x7a, 0x47, 0x82, 0xc1, 0xfe, 0x24, 0xd1, 0x6c, 0x37, - 0x7f, 0x1b, 0xdd, 0xa8, 0x27, 0x80, 0x30, 0x86, 0x24, 0x00, 0x30, 0x06, 0xf5, 0x00, 0x00, 0x00, 0x84, 0x90, 0xa3, - 0x00, 0x82, 0x01, 0x06, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xed, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xc0, 0xeb, 0x00, - 0x10, 0x80, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x08, 0x4c, 0xa3, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x60, 0x7e, 0x69, - 0xd4, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x02, 0x4c, 0xa3, 0x10, 0x00, 0x44, 0x23, 0x00, 0x20, 0x04, - 0xf3, 0x00, 0x61, 0x86, 0xe4, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0xf0, 0xa3, 0x00, 0x0a, 0x00, 0x00, - 0x00, 0x84, 0x80, 0x00, 0x4c, 0xa3, 0x50, 0x00, 0x44, 0xa3, 0x00, 0x20, 0x04, 0xf3, 0x00, 0x61, 0x86, 0xe4, 0x20, - 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0x10, 0xa4, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x40, 0x23, - 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x44, 0xa3, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x48, 0xa3, 0x00, 0x00, 0x4a, - 0x23, 0x00, 0x00, 0x4c, 0x23, 0x00, 0x00, 0x4e, 0xa3, 0x00, 0x00, 0x50, 0xa3, 0x00, 0x00, 0x52, 0x23, 0x00, 0x00, - 0x54, 0x23, 0x00, 0x00, 0x56, 0xa3, 0x00, 0x00, 0x58, 0x23, 0x00, 0x00, 0x5a, 0xa3, 0x00, 0x00, 0x5c, 0xa3, 0x00, - 0x00, 0x5e, 0x23, 0x00, 0x00, 0x60, 0xa3, 0x00, 0x00, 0x62, 0x23, 0x00, 0x00, 0x64, 0x23, 0x00, 0x00, 0x66, 0xa3, - 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x28, 0x00, 0x00, 0x6e, 0x23, 0x00, 0x00, 0x70, 0x23, 0x00, 0x00, - 0x72, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x76, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, - 0x00, 0x7c, 0x23, 0x00, 0x00, 0x7e, 0xa3, 0x00, 0x00, 0x00, 0x84}; \ No newline at end of file +const uint8_t fw_SPECT[] = { + 0x68, 0xab, 0xf0, 0xa7, 0x7a, 0x50, 0xce, 0xdd, 0x55, 0x3d, 0xb0, 0xf1, 0x76, 0x9f, 0xcb, 0x6a, + 0x67, 0xf5, 0xcb, 0xfc, 0x24, 0x76, 0xb2, 0x52, 0xa0, 0x4a, 0x8d, 0xe5, 0x2d, 0xd4, 0x2e, 0x89, + 0x4d, 0xf6, 0xbd, 0xc0, 0xe0, 0xc7, 0x95, 0x13, 0x72, 0xad, 0xcc, 0x48, 0x86, 0x3a, 0x7d, 0xda, + 0x6b, 0x8b, 0x3f, 0x1a, 0x86, 0x84, 0x61, 0xc9, 0x13, 0x79, 0x51, 0x2b, 0x3f, 0x75, 0xa9, 0xe4, + 0x0c, 0x48, 0x5d, 0xf0, 0x6b, 0x12, 0x14, 0x52, 0x77, 0x96, 0x33, 0xba, 0x34, 0x28, 0xeb, 0x80, + 0x57, 0x3d, 0x94, 0xe6, 0x34, 0x7c, 0x70, 0x56, 0xa8, 0x01, 0x2f, 0xe5, 0x0f, 0x7f, 0x4e, 0x2f, + 0x1c, 0x02, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0xfa, 0xfa, 0xe4, 0x4c, 0x3f, 0x09, 0x0c, + 0xec, 0x1f, 0xdc, 0x76, 0xd8, 0x51, 0x17, 0xaf, 0x15, 0x9b, 0x29, 0xc6, 0xbd, 0xa7, 0xf6, 0x75, + 0xb3, 0x5c, 0xa0, 0xcf, 0x68, 0xc0, 0xee, 0x2a, 0x8e, 0x6c, 0x00, 0x00, 0x2f, 0x82, 0xf0, 0xe9, + 0x8a, 0x1d, 0xf3, 0x23, 0x8f, 0x1d, 0xac, 0x6f, 0x9d, 0xd2, 0x9c, 0x27, 0x32, 0x09, 0x47, 0xf5, + 0x59, 0xf3, 0x54, 0x5b, 0xbf, 0x4f, 0x8b, 0x45, 0x79, 0xa9, 0x37, 0x1e, 0x57, 0xd4, 0x61, 0xa1, + 0xa2, 0x21, 0xea, 0x64, 0x27, 0x05, 0xfd, 0x23, 0xa6, 0x3f, 0x98, 0x2a, 0x8c, 0xd9, 0x68, 0xa0, + 0x93, 0x96, 0x98, 0xba, 0x72, 0x85, 0x9c, 0x02, 0x07, 0xc2, 0x59, 0x0e, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfa, 0x2d, 0xfa, 0x3e, 0x5e, 0x5f, 0xe0, 0xdf, 0xbf, 0xea, 0x93, 0xdd, + 0x0a, 0x41, 0xd8, 0xbb, 0x82, 0x31, 0x51, 0x8d, 0x90, 0xae, 0x64, 0xf2, 0x61, 0x7e, 0x01, 0xd8, + 0x57, 0x83, 0x64, 0x69, 0xd8, 0xd8, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, + 0x9a, 0x9a, 0x06, 0x43, 0x2c, 0x84, 0x2b, 0x3f, 0x4a, 0x63, 0x9c, 0x51, 0xdc, 0x7b, 0x63, 0x33, + 0x70, 0xac, 0x17, 0xfc, 0xd4, 0xca, 0x19, 0x9e, 0xf9, 0xbd, 0x20, 0xba, 0x5f, 0xff, 0x8d, 0x73, + 0xb0, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x02, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0xa8, 0x24, 0x00, 0x00, 0xd4, 0x7d, + 0x50, 0x04, 0x3e, 0x76, 0xee, 0xe1, 0x59, 0xcb, 0x26, 0x98, 0xc7, 0x25, 0x91, 0xb2, 0x59, 0xdd, + 0x1c, 0xf0, 0x9e, 0xef, 0xd3, 0x1c, 0x5d, 0xb6, 0x34, 0xbb, 0x20, 0xd4, 0x52, 0x09, 0xd2, 0x56, + 0xbf, 0xa0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xfd, 0x93, 0x16, 0x38, 0x91, + 0xe1, 0x51, 0x15, 0xde, 0x7f, 0x92, 0x54, 0xb7, 0xfa, 0xba, 0xab, 0x86, 0xa5, 0x37, 0x39, 0x3b, + 0xab, 0xda, 0x0e, 0x7d, 0xd4, 0x61, 0xa9, 0xdb, 0xfb, 0x4e, 0x57, 0x88, 0x02, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x9f, 0x03, 0xfd, 0x15, 0xcd, 0x52, 0x37, 0x43, 0x12, 0xa7, + 0x47, 0xf3, 0x4c, 0x08, 0x25, 0x5f, 0x01, 0xc0, 0xf9, 0x27, 0x07, 0x7a, 0x05, 0x70, 0x44, 0xae, + 0xf1, 0x53, 0xae, 0xdd, 0x90, 0xee, 0x60, 0x03, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x7e, 0xa3, 0xe4, 0xa3, 0x00, 0x82, + 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, 0x40, 0xa2, 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0x82, 0x62, + 0xf0, 0x10, 0x88, 0xa2, 0x20, 0x33, 0x4a, 0xc5, 0x00, 0x10, 0x40, 0x28, 0x2c, 0xa3, 0x00, 0x08, + 0x60, 0x40, 0x40, 0x28, 0x4c, 0x80, 0x00, 0x88, 0x10, 0x40, 0x40, 0xa8, 0x84, 0x80, 0x00, 0x08, + 0xfa, 0xd3, 0x0b, 0x9a, 0xa9, 0x26, 0x2d, 0x4c, 0xa8, 0x2c, 0xbb, 0x5e, 0x96, 0xf9, 0x73, 0x44, + 0x7b, 0x04, 0x8d, 0x06, 0x97, 0x98, 0x1a, 0xc8, 0x58, 0xce, 0xc2, 0x62, 0x43, 0x93, 0xb6, 0xe6, + 0xc4, 0x38, 0x04, 0x40, 0x40, 0x40, 0xa8, 0xb8, 0x80, 0x00, 0x08, 0x70, 0x40, 0x40, 0xa8, 0x20, + 0x81, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0x04, 0xa4, 0x00, 0x82, 0xf4, 0x50, 0x8a, 0x24, 0x00, + 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x60, 0x10, 0x40, 0x28, 0x1c, 0x9f, 0x00, 0x08, 0x61, + 0x10, 0x40, 0xa8, 0x1c, 0x9f, 0x00, 0x08, 0x62, 0x10, 0x40, 0xa8, 0xa4, 0x9f, 0x00, 0x08, 0x63, + 0x10, 0x40, 0x28, 0xb0, 0xa0, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0xf3, + 0x50, 0x8a, 0xa4, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x11, 0x10, 0x40, 0x28, 0x60, + 0xa2, 0x00, 0x08, 0x12, 0x10, 0x40, 0x28, 0x9c, 0xa2, 0x00, 0x08, 0x13, 0x10, 0x40, 0xa8, 0xbc, + 0xa2, 0x00, 0x88, 0x14, 0x10, 0x40, 0x28, 0xe0, 0xa2, 0x00, 0x88, 0x40, 0x81, 0x00, 0x98, 0xa8, + 0xa4, 0x00, 0x18, 0x04, 0xa4, 0x00, 0x82, 0xf2, 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, + 0x05, 0x4a, 0x49, 0x41, 0x10, 0x40, 0x28, 0x94, 0x8f, 0x00, 0x88, 0x42, 0x10, 0x40, 0x28, 0xac, + 0x90, 0x00, 0x88, 0x43, 0x10, 0x40, 0xa8, 0xd4, 0x90, 0x00, 0x88, 0x44, 0x10, 0x40, 0x28, 0x04, + 0x91, 0x00, 0x88, 0x45, 0x10, 0x40, 0xa8, 0xfc, 0x91, 0x00, 0x08, 0x46, 0x10, 0x40, 0xa8, 0xa0, + 0x92, 0x00, 0x08, 0x47, 0x10, 0x40, 0x28, 0xf4, 0x92, 0x00, 0x88, 0x48, 0x10, 0x40, 0x28, 0x30, + 0x93, 0x00, 0x88, 0x49, 0x10, 0x40, 0xa8, 0x48, 0x93, 0x00, 0x88, 0xfa, 0xdd, 0x34, 0x32, 0x10, + 0xea, 0xae, 0x70, 0x34, 0x9b, 0x88, 0xd3, 0xdf, 0x44, 0xa4, 0xb5, 0xb9, 0x34, 0xf1, 0x53, 0x3f, + 0x0c, 0xcf, 0x42, 0x4d, 0x35, 0x5a, 0xc6, 0xa8, 0x18, 0x41, 0xd2, 0x8e, 0x10, 0x05, 0x4a, 0x10, + 0x40, 0xa8, 0x18, 0x94, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x04, 0xa4, + 0x00, 0x82, 0xf1, 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x70, 0x10, + 0x40, 0xa8, 0x1c, 0xa1, 0x00, 0x88, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x02, 0x00, + 0x44, 0x23, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x44, 0x69, 0x00, 0x00, 0x42, 0xa3, 0xf3, 0x00, + 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x40, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x00, + 0x00, 0x84, 0x50, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x01, + 0x40, 0xc5, 0x00, 0x00, 0x00, 0xf5, 0x00, 0x00, 0x00, 0xf5, 0xff, 0x00, 0x42, 0xa3, 0x00, 0x10, + 0x02, 0xf3, 0xff, 0x10, 0x82, 0xa4, 0x80, 0x00, 0x80, 0xe2, 0x00, 0x00, 0x00, 0x84, 0xa8, 0xa4, + 0x00, 0x18, 0x00, 0x10, 0x02, 0xf3, 0x00, 0x10, 0x02, 0xf3, 0x80, 0x00, 0x40, 0xe2, 0x00, 0x11, + 0x40, 0x49, 0x00, 0x00, 0xc0, 0x93, 0x80, 0x10, 0x84, 0xff, 0x80, 0x20, 0x86, 0x7f, 0x80, 0x31, + 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x80, 0x41, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, + 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, + 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x06, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, + 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0xfa, 0x4f, 0xea, 0x9d, 0xdc, 0xe0, 0x34, 0x82, 0xd0, 0xc3, + 0xee, 0xb7, 0x4c, 0x55, 0xcd, 0x62, 0xb3, 0xd3, 0xc9, 0x08, 0x09, 0xcc, 0xb3, 0xca, 0x13, 0xcd, + 0x0c, 0xd4, 0xa8, 0x78, 0x10, 0x18, 0x47, 0xe8, 0x05, 0x03, 0xe0, 0x7d, 0xa4, 0xdc, 0x81, 0x00, + 0x8a, 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x0f, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, + 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0xfc, 0x81, 0x00, + 0x0a, 0x80, 0x42, 0x8c, 0xff, 0x00, 0x63, 0x88, 0xff, 0x3f, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, + 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0x1c, 0x82, 0x00, + 0x8a, 0x00, 0x43, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x1e, 0x00, 0x7c, + 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, + 0xa4, 0x40, 0x82, 0x00, 0x8a, 0x00, 0x43, 0x88, 0x7f, 0x40, 0x30, 0x4a, 0xc5, 0x80, 0x00, 0x7c, + 0xa3, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x50, 0x0a, 0x63, 0x80, 0x82, 0x00, + 0x8c, 0x00, 0x50, 0x0a, 0x63, 0x94, 0x82, 0x00, 0x0e, 0x80, 0x40, 0x88, 0xff, 0x94, 0x82, 0x00, + 0x98, 0x00, 0x50, 0x0a, 0x63, 0x90, 0x82, 0x00, 0x0c, 0x00, 0x41, 0x88, 0xff, 0x94, 0x82, 0x00, + 0x98, 0x80, 0x41, 0x88, 0x7f, 0x02, 0xe0, 0x7d, 0x24, 0x60, 0x82, 0x00, 0x0a, 0x00, 0x40, 0x42, + 0xe3, 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x86, 0xef, 0x80, 0x30, 0x88, 0xef, 0x00, 0x42, 0x86, + 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, 0x80, 0x31, 0x86, + 0xef, 0xfa, 0x2f, 0x9b, 0xfc, 0xe2, 0x69, 0xc7, 0xa1, 0x8b, 0xf0, 0x54, 0x4c, 0xfa, 0x69, 0x81, + 0x47, 0x1c, 0x54, 0xcd, 0x22, 0x21, 0xaa, 0x59, 0x3a, 0xc5, 0x61, 0x9d, 0xd7, 0x95, 0x94, 0x0b, + 0x78, 0x3e, 0xc0, 0x06, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x31, 0x86, 0x6f, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x8a, 0x6f, 0x80, 0x52, 0x86, 0xef, + 0x09, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x01, 0xe0, 0x7d, 0x24, 0xe0, 0x82, 0x00, 0x8a, + 0x80, 0x32, 0x86, 0xef, 0x0a, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, + 0x02, 0xe0, 0x7d, 0x24, 0xf4, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x8a, 0xef, 0x80, 0x52, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, + 0x1e, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, + 0x03, 0xe0, 0x7d, 0xa4, 0x20, 0x83, 0x00, 0x0a, 0x80, 0x30, 0x86, 0x6f, 0x80, 0x00, 0x7c, 0xa3, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, + 0x04, 0xe0, 0x7d, 0x24, 0x3c, 0x83, 0x00, 0x8a, 0x00, 0x31, 0x86, 0x6f, 0x20, 0x00, 0x7c, 0xa3, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, + 0x04, 0xe0, 0x7d, 0x24, 0x5c, 0x83, 0x00, 0x8a, 0x00, 0x31, 0x86, 0x6f, 0x1e, 0x00, 0x7c, 0x23, + 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, + 0x7c, 0x83, 0x00, 0x0a, 0x80, 0x32, 0x86, 0xef, 0x00, 0x00, 0x00, 0x84, 0xfa, 0x31, 0x53, 0x84, + 0xc5, 0x65, 0xd8, 0x2d, 0x6a, 0xd2, 0xe6, 0x0e, 0x92, 0x2a, 0xc4, 0xd1, 0x51, 0x88, 0x21, 0x8f, + 0x06, 0xfd, 0xe9, 0x5f, 0x07, 0x37, 0xe1, 0xa8, 0x63, 0x7d, 0x14, 0x7d, 0x65, 0x98, 0x07, 0xa4, + 0x82, 0x00, 0x02, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x30, 0x82, 0xef, 0x00, + 0x00, 0x00, 0x84, 0x80, 0x10, 0x84, 0xe7, 0x80, 0x20, 0x88, 0xe7, 0x00, 0x42, 0x86, 0x67, 0x80, + 0x31, 0x86, 0x67, 0x80, 0x41, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, + 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x07, + 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xdc, 0x83, 0x00, 0x0a, 0x80, + 0x21, 0x8a, 0xe7, 0x80, 0x52, 0x86, 0x67, 0x0f, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, + 0xe0, 0x7d, 0x24, 0xf4, 0x83, 0x00, 0x0a, 0x80, 0x51, 0x84, 0xe7, 0x00, 0x21, 0x86, 0x67, 0x0f, + 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x0c, 0x84, 0x00, 0x0a, 0x80, + 0x51, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x22, 0x8a, 0x67, 0x80, + 0x52, 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x30, + 0x84, 0x00, 0x0a, 0x80, 0x51, 0x84, 0xe7, 0x00, 0x21, 0x86, 0x67, 0x63, 0x00, 0x7c, 0x23, 0x80, + 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x48, 0x84, 0x00, 0x0a, 0x80, 0x21, 0x84, 0x67, 0x00, + 0x21, 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x60, + 0x84, 0x00, 0x0a, 0x80, 0x32, 0x84, 0xe7, 0xfa, 0x8d, 0xc0, 0xa9, 0x35, 0x3b, 0x01, 0x45, 0xdb, + 0xba, 0xa4, 0x31, 0x7d, 0x18, 0xd6, 0x32, 0xa6, 0xa8, 0xa7, 0x9e, 0xc6, 0x21, 0xf0, 0xd9, 0x61, + 0xea, 0x71, 0x3c, 0xeb, 0xb0, 0x4f, 0xac, 0x1c, 0x70, 0x08, 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, + 0x00, 0x02, 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x30, 0x86, 0xe7, 0x80, 0x31, + 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x00, 0x32, 0x82, 0x67, 0x00, 0x00, + 0x00, 0x84, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0x80, 0x67, 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, + 0x80, 0xe7, 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x00, 0x80, 0x67, 0x00, 0x21, + 0x84, 0xe7, 0x80, 0x20, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x32, 0x48, 0x45, 0x00, 0x22, + 0x86, 0x67, 0x00, 0x21, 0x88, 0xe7, 0x80, 0x40, 0x88, 0xe8, 0xdc, 0x84, 0x00, 0x8a, 0x00, 0x20, + 0x42, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x30, 0x42, 0x63, 0x00, 0x00, 0x00, 0x84, 0x00, 0x90, + 0x42, 0x63, 0x74, 0x84, 0x00, 0x82, 0x80, 0x70, 0x8e, 0xe7, 0x80, 0x80, 0x90, 0xe7, 0x01, 0x00, + 0x42, 0x23, 0x80, 0x70, 0x8e, 0xe2, 0x00, 0x80, 0x10, 0xeb, 0x80, 0x83, 0x90, 0xe4, 0x00, 0x80, + 0x10, 0xed, 0x00, 0x80, 0x10, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0xc0, 0x60, 0x63, 0x00, 0x00, + 0x21, 0x63, 0x24, 0x85, 0x00, 0x8c, 0x00, 0x00, 0x6c, 0xa3, 0x2c, 0x85, 0x00, 0x18, 0x01, 0x00, + 0x6c, 0x23, 0x2c, 0x85, 0x00, 0x18, 0x00, 0x00, 0x21, 0x65, 0x00, 0x00, 0x59, 0x63, 0x00, 0x08, + 0xa1, 0xe7, 0x01, 0x00, 0x42, 0x23, 0x80, 0x00, 0xa9, 0xfd, 0x00, 0x03, 0xa1, 0x67, 0x80, 0x00, + 0xab, 0x7b, 0xfa, 0xa8, 0xaf, 0xdd, 0xb8, 0xba, 0xaa, 0x08, 0x6c, 0xd4, 0x88, 0xf3, 0x77, 0x9b, + 0x7e, 0xa7, 0xf8, 0x8f, 0x4b, 0xdd, 0xf9, 0xbe, 0x8d, 0x63, 0xb9, 0x23, 0x90, 0x0f, 0xef, 0x9f, + 0x88, 0x37, 0x9e, 0x48, 0x09, 0x80, 0x5a, 0xa5, 0x67, 0x80, 0x2a, 0xa5, 0xe7, 0x00, 0x2a, 0xa7, + 0xe7, 0x00, 0x29, 0xa5, 0x67, 0x80, 0x2a, 0xa5, 0xe7, 0x00, 0x2a, 0x83, 0xe7, 0x00, 0x10, 0x60, + 0xe3, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0xa4, 0x67, 0x00, 0x29, 0xa5, 0x67, 0x00, 0x28, 0xa5, + 0xe7, 0x80, 0x29, 0xa5, 0xe7, 0x00, 0x29, 0xa1, 0xe7, 0x80, 0x0a, 0xa1, 0xe7, 0x00, 0x32, 0x42, + 0x45, 0x80, 0x20, 0xa3, 0xe7, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x0a, 0xbd, 0xe8, 0x9c, 0x85, 0x00, + 0x8a, 0x00, 0x20, 0x41, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x7c, 0x23, 0x00, 0xea, 0xa9, + 0xfd, 0x00, 0x0a, 0xbd, 0xe8, 0xb4, 0x85, 0x00, 0x8a, 0x00, 0x10, 0x41, 0xe3, 0x01, 0x00, 0x42, + 0x23, 0x00, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, 0x88, 0x00, 0x00, 0x42, 0xa3, 0x00, 0xe0, 0xbd, + 0x68, 0xcc, 0x85, 0x00, 0x8a, 0x01, 0x10, 0x82, 0x24, 0x01, 0x60, 0x41, 0xa8, 0xd8, 0x85, 0x00, + 0x8a, 0x02, 0x10, 0x82, 0x24, 0x03, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, 0x88, 0x00, 0x00, 0x46, + 0x23, 0x00, 0x30, 0x86, 0xfd, 0x01, 0x00, 0x7c, 0xa3, 0x00, 0x0f, 0x82, 0xe2, 0x00, 0x1b, 0x40, + 0x68, 0x00, 0x86, 0x00, 0x8a, 0x00, 0x00, 0x56, 0x63, 0x08, 0x86, 0x00, 0x18, 0x00, 0x30, 0x56, + 0x63, 0x08, 0x86, 0x00, 0x18, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x00, 0x84, 0xff, 0x0f, 0x42, + 0xa3, 0x00, 0x00, 0x00, 0x84, 0x80, 0x83, 0x80, 0xfd, 0x80, 0xc5, 0x82, 0xfd, 0xfa, 0x2d, 0xe4, + 0xc2, 0x35, 0x0d, 0x09, 0x7b, 0xcf, 0xa5, 0x80, 0x6c, 0x50, 0x37, 0x0f, 0x88, 0xc8, 0xb2, 0x30, + 0x17, 0x0b, 0x0c, 0x73, 0x25, 0x9c, 0x3c, 0x35, 0xa7, 0xd8, 0xd8, 0xd6, 0x70, 0x2f, 0x20, 0x0a, + 0x80, 0x00, 0x80, 0xe7, 0x80, 0x83, 0x82, 0x7b, 0x80, 0xc5, 0x84, 0xfb, 0x00, 0x11, 0x82, 0xe7, + 0x00, 0xa7, 0x84, 0x67, 0x00, 0x23, 0x84, 0x67, 0x00, 0x21, 0x84, 0x7b, 0x80, 0x96, 0x86, 0xe7, + 0x80, 0x31, 0x86, 0xfb, 0x00, 0x10, 0x88, 0xfd, 0x00, 0x10, 0x80, 0x7b, 0x00, 0x31, 0x82, 0xfd, + 0x00, 0x31, 0x84, 0xfb, 0x80, 0x40, 0x96, 0xe7, 0x00, 0x40, 0x9c, 0x67, 0x00, 0x20, 0x98, 0xe7, + 0x80, 0x20, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x80, 0x73, 0x80, 0x67, 0x00, 0x84, 0x82, 0xe7, + 0x80, 0x94, 0x84, 0xe7, 0x00, 0x21, 0x84, 0x7b, 0x80, 0x00, 0x86, 0x7b, 0x00, 0x74, 0x88, 0x7b, + 0x00, 0x42, 0x88, 0xe7, 0x00, 0x32, 0x88, 0xfd, 0x80, 0x00, 0x80, 0x7d, 0x00, 0x20, 0x82, 0xfb, + 0x80, 0x40, 0x8e, 0xe7, 0x80, 0x00, 0x92, 0xe7, 0x80, 0x01, 0x90, 0xe7, 0x80, 0x41, 0x94, 0xe7, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x4e, 0xa3, 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, 0xa3, + 0x00, 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xb0, 0x4e, 0x67, + 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, + 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, + 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0xb8, 0x86, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x05, 0x56, 0xc9, 0x20, 0x05, 0x58, 0xc9, 0xfa, 0x0f, 0xee, 0x07, 0xd2, 0xf4, 0xa2, 0x2d, + 0x0d, 0x40, 0x79, 0xfa, 0x2d, 0x57, 0x83, 0x0f, 0x41, 0x07, 0x75, 0xb7, 0xe5, 0xd5, 0xd7, 0xac, + 0x9b, 0xf8, 0x00, 0x5e, 0xf4, 0x04, 0xe4, 0xcf, 0xf4, 0xf8, 0x0a, 0x40, 0x05, 0x5a, 0x49, 0x00, + 0x00, 0x4e, 0xa3, 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x00, + 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xde, 0xf3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, 0x00, + 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, + 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, + 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x14, 0x87, 0x00, 0x0a, 0x00, + 0x01, 0x7c, 0xa3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xb0, 0x4e, 0x67, 0x00, + 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, 0x68, + 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, + 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x50, 0x87, 0x00, 0x0a, 0x00, 0x00, 0x7c, 0x23, 0x80, + 0xe3, 0x8f, 0xfd, 0x00, 0xe5, 0x95, 0xfd, 0x18, 0x86, 0x00, 0x02, 0x80, 0xe3, 0x8f, 0xfd, 0x00, + 0xe5, 0x95, 0xfd, 0x00, 0x05, 0x40, 0x45, 0x20, 0x05, 0x42, 0x45, 0x40, 0x05, 0x44, 0x45, 0x80, + 0x06, 0x80, 0xe7, 0x80, 0x16, 0x82, 0xe7, 0x00, 0xb1, 0x96, 0xe7, 0x00, 0xc1, 0x98, 0xe7, 0x80, + 0x05, 0xbc, 0xe8, 0xd4, 0x87, 0x00, 0x0a, 0x00, 0x16, 0xbc, 0xe8, 0xd4, 0x87, 0x00, 0x0a, 0x00, + 0x00, 0x40, 0x23, 0xfa, 0xfe, 0x14, 0x49, 0x21, 0x60, 0xff, 0x7e, 0x5d, 0x00, 0x19, 0x5b, 0xd4, + 0x90, 0x1b, 0xdc, 0x48, 0x41, 0x2e, 0x9c, 0x5b, 0x19, 0xcb, 0xc0, 0x02, 0x1c, 0x36, 0x73, 0x88, + 0x29, 0x18, 0xc8, 0x17, 0xd0, 0x0b, 0x00, 0x00, 0x00, 0x84, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, + 0x00, 0x84, 0x40, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, + 0x00, 0x82, 0x01, 0x00, 0xae, 0x24, 0x80, 0x5b, 0xab, 0x67, 0x00, 0x5b, 0xb1, 0x67, 0x80, 0x6b, + 0xad, 0x67, 0x98, 0x96, 0x00, 0x02, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, + 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0x02, 0x56, 0x49, 0x20, 0x02, + 0x58, 0x49, 0x40, 0x02, 0x5a, 0xc9, 0x60, 0x02, 0x5c, 0x49, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, + 0x40, 0xa8, 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0x02, + 0x56, 0x45, 0x20, 0x02, 0x58, 0x45, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, 0x45, 0x00, 0x02, + 0x4e, 0x49, 0x20, 0x02, 0x50, 0xc9, 0x40, 0x02, 0x52, 0x49, 0x60, 0x02, 0x54, 0xc9, 0x00, 0x50, + 0x4f, 0xe3, 0x00, 0x60, 0x51, 0xe3, 0x00, 0x70, 0x53, 0xe3, 0x00, 0x80, 0x55, 0xe3, 0x00, 0x00, + 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, 0x00, 0x07, 0x9c, 0xfd, 0x18, 0x86, 0x00, 0x02, 0x80, 0x31, + 0x7e, 0xc5, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, + 0x4c, 0xc5, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, + 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0x02, 0x56, 0x45, 0x20, 0x02, 0x58, 0x45, 0xfa, 0x31, + 0x1e, 0xae, 0xa7, 0x68, 0x3e, 0x48, 0xa1, 0xb0, 0x5d, 0x94, 0x7f, 0x0e, 0x69, 0x39, 0x45, 0xe9, + 0x26, 0x00, 0x27, 0xa6, 0xd1, 0x0f, 0xb4, 0x49, 0x35, 0xc6, 0x1f, 0x18, 0xd4, 0x55, 0xc1, 0xa8, + 0x0c, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, 0x45, 0x18, 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, + 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0x00, 0xe0, 0x54, 0x63, 0x10, 0x89, 0x00, + 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, 0x74, 0x84, 0x00, 0x82, 0x80, 0xb0, 0xaa, + 0xe7, 0x80, 0xc0, 0xac, 0x67, 0x80, 0x5a, 0x83, 0xe7, 0x00, 0x6b, 0x85, 0xe7, 0x80, 0x20, 0x86, + 0xfd, 0x00, 0x11, 0x88, 0xe7, 0x00, 0x43, 0x88, 0x67, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x40, 0x88, + 0xfb, 0x00, 0x32, 0x80, 0xe8, 0x08, 0x89, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, + 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x80, 0x73, 0x80, 0x67, 0x00, 0x84, 0x82, + 0xe7, 0x80, 0x94, 0x84, 0xe7, 0x00, 0x10, 0x86, 0x7d, 0x00, 0x31, 0x86, 0xe7, 0x00, 0x21, 0x84, + 0xe7, 0x00, 0x03, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x01, 0x80, 0x7b, 0x00, 0x30, 0x86, + 0x68, 0x48, 0x89, 0x00, 0x8a, 0x00, 0x74, 0x80, 0x67, 0x00, 0x95, 0x86, 0x67, 0x00, 0x30, 0x86, + 0x68, 0x00, 0x00, 0x00, 0x84, 0x00, 0x96, 0x80, 0xef, 0x80, 0xa6, 0x82, 0xef, 0x00, 0xb7, 0x84, + 0x6f, 0x00, 0x95, 0x86, 0xfb, 0x80, 0xc6, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x6f, 0x80, 0x00, 0x88, + 0xfb, 0x00, 0x32, 0x86, 0x7d, 0x80, 0xa5, 0x88, 0xfb, 0x00, 0xd7, 0x8a, 0xfb, 0x80, 0x42, 0x88, + 0xef, 0x00, 0x11, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xfd, 0xfa, 0x94, 0x96, 0xe3, 0x85, 0x52, 0x4e, + 0xab, 0x44, 0xf3, 0xe1, 0x73, 0xcf, 0x77, 0xf0, 0x1b, 0x15, 0x54, 0xff, 0x6b, 0xb7, 0x2a, 0x1c, + 0x22, 0xdb, 0x15, 0xa7, 0x65, 0x7f, 0x14, 0xfb, 0x89, 0x41, 0x80, 0x0d, 0x80, 0x95, 0x8a, 0x7b, + 0x00, 0xc7, 0x8c, 0x7b, 0x00, 0x53, 0x8a, 0xef, 0x00, 0x01, 0x8c, 0x7b, 0x00, 0x53, 0x8c, 0xfd, + 0x00, 0x81, 0x8e, 0x6f, 0x80, 0x63, 0x8a, 0x7d, 0x80, 0x52, 0x8e, 0x7b, 0x80, 0x53, 0x8a, 0x7b, + 0x80, 0x12, 0x8e, 0xfd, 0x80, 0x12, 0x8a, 0x7b, 0x00, 0x83, 0x8c, 0x6f, 0x00, 0x21, 0x82, 0x7b, + 0x00, 0x11, 0x84, 0x7b, 0x00, 0x61, 0x8c, 0x7d, 0x00, 0x60, 0x8c, 0xfd, 0x00, 0x63, 0x82, 0x7b, + 0x00, 0x13, 0x8c, 0x7b, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x80, 0x7b, 0x00, 0x01, 0x80, 0x7d, + 0x00, 0x43, 0x82, 0xef, 0x00, 0x03, 0x84, 0x6f, 0x80, 0x53, 0x8c, 0x6f, 0x00, 0x61, 0x9a, 0xfb, + 0x80, 0x32, 0x8a, 0xef, 0x80, 0x50, 0x98, 0x7d, 0x80, 0x43, 0x8e, 0x6f, 0x00, 0x30, 0x82, 0x6f, + 0x80, 0x70, 0x9c, 0x7b, 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0xef, 0x00, 0xa5, 0x82, 0x6f, + 0x80, 0xb5, 0x84, 0x6f, 0x00, 0x95, 0x86, 0xef, 0x80, 0x31, 0x86, 0xfb, 0x80, 0x95, 0x8e, 0xef, + 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x81, 0x8c, 0xef, 0x80, 0x63, 0x8c, 0x7d, 0x00, 0x63, 0x8a, 0xfb, + 0x00, 0x53, 0x8c, 0xfb, 0x00, 0x13, 0x8a, 0x7d, 0x00, 0x13, 0x8c, 0x7b, 0x00, 0x53, 0x8c, 0xef, + 0x80, 0x51, 0x8a, 0xef, 0x00, 0x21, 0x86, 0xfb, 0x80, 0x21, 0x84, 0xfb, 0x80, 0x83, 0x8e, 0x6f, + 0x00, 0x71, 0x8e, 0x7d, 0x00, 0x70, 0x8e, 0xfd, 0x80, 0x73, 0x86, 0xfb, 0x80, 0x71, 0x8e, 0xfb, + 0x00, 0x00, 0x86, 0xfb, 0xfa, 0xcc, 0x6d, 0xcb, 0xad, 0x89, 0x62, 0xc2, 0x58, 0xe9, 0x5c, 0x59, + 0x07, 0x1d, 0x65, 0xa8, 0x3c, 0x07, 0x36, 0xba, 0x80, 0x63, 0x10, 0x99, 0x09, 0x91, 0xf7, 0x4f, + 0x15, 0xc5, 0x6f, 0x0d, 0xfe, 0x58, 0x0e, 0x00, 0x30, 0x80, 0xfb, 0x00, 0x01, 0x80, 0x7d, 0x80, + 0x03, 0x80, 0x6f, 0x00, 0x60, 0x8c, 0xfb, 0x80, 0xa5, 0x80, 0x6f, 0x00, 0x00, 0x80, 0xfb, 0x80, + 0x03, 0x8e, 0xef, 0x80, 0x53, 0x8a, 0x7d, 0x80, 0x00, 0x8e, 0xef, 0x80, 0x73, 0x8e, 0x7b, 0x80, + 0x73, 0x8e, 0x7b, 0x00, 0x50, 0x52, 0xe3, 0x00, 0x60, 0x54, 0xe3, 0x00, 0x70, 0x56, 0xe3, 0x00, + 0x00, 0x00, 0x84, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, 0x00, 0x56, 0xa3, 0x00, + 0x01, 0x7c, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, + 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, + 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xa8, + 0x8a, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x58, 0x49, 0x20, 0x05, 0x5a, 0x49, 0x40, + 0x05, 0x5c, 0x49, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, 0x00, 0x56, 0xa3, 0x00, + 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xde, 0xf3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, 0x00, + 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, + 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, + 0xe0, 0x7d, 0x24, 0xf8, 0x8a, 0x00, 0x0a, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xf0, 0x1e, 0xeb, 0xfa, + 0x54, 0x1c, 0x74, 0x4c, 0x9b, 0x90, 0x65, 0x7b, 0xde, 0x1d, 0x55, 0xf8, 0x5f, 0x85, 0xe3, 0x39, + 0x91, 0xe4, 0xa1, 0x0a, 0xf7, 0xf7, 0x97, 0x01, 0x79, 0xc4, 0x5a, 0x0e, 0x20, 0x84, 0xb7, 0xb1, + 0x30, 0x0f, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, + 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, + 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x2c, 0x8b, 0x00, 0x8a, 0x00, 0x00, + 0x7c, 0x23, 0x00, 0xe5, 0x95, 0xfd, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe5, 0x95, 0xfd, 0x00, 0x05, + 0x40, 0x45, 0x20, 0x05, 0x42, 0x45, 0x40, 0x05, 0x44, 0x45, 0x00, 0x07, 0x80, 0x6f, 0x00, 0x17, + 0x82, 0x6f, 0x00, 0xc1, 0x98, 0x6f, 0x00, 0xd1, 0x9a, 0x6f, 0x00, 0x06, 0xbc, 0x68, 0xa0, 0x8b, + 0x00, 0x0a, 0x80, 0x16, 0xbc, 0x68, 0xa0, 0x8b, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, + 0x00, 0x84, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x30, 0x7e, 0xc5, 0x00, 0x00, + 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xb0, 0x24, 0x00, 0x6c, + 0xad, 0xef, 0x00, 0x7c, 0xaf, 0xef, 0xc8, 0x97, 0x00, 0x82, 0x00, 0x10, 0x53, 0xe3, 0x00, 0x20, + 0x55, 0xe3, 0x00, 0x30, 0x57, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x20, 0x30, + 0x7e, 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0x80, 0x30, + 0x50, 0x45, 0x00, 0x10, 0x59, 0xe3, 0x00, 0x20, 0x5b, 0x63, 0x00, 0x30, 0x5d, 0xe3, 0xd8, 0x8a, + 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x94, 0x8c, 0x00, 0x0a, 0xfa, 0x62, 0x58, 0xee, 0x51, 0x13, + 0xf7, 0x00, 0x08, 0xe6, 0x1c, 0x79, 0xd4, 0x2f, 0xce, 0xb8, 0xa2, 0x58, 0x88, 0x20, 0x1a, 0xab, + 0xa7, 0x23, 0x41, 0x0c, 0xd8, 0xb6, 0x30, 0xa9, 0x01, 0xba, 0x1e, 0x08, 0x10, 0x9c, 0x8c, 0x00, + 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0x00, 0x80, 0x68, 0x00, 0x60, 0x53, 0x6f, 0x00, 0x70, 0x55, + 0xef, 0x00, 0x80, 0x57, 0x6f, 0x00, 0x10, 0x59, 0xe3, 0x00, 0x20, 0x5b, 0x63, 0x00, 0x30, 0x5d, + 0xe3, 0x80, 0x06, 0x9a, 0xfd, 0x4c, 0x89, 0x00, 0x82, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xfc, + 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, + 0xa8, 0x94, 0x8c, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0x60, 0x59, + 0x63, 0x00, 0x70, 0x5b, 0x63, 0x00, 0x80, 0x5d, 0x63, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xc0, 0x52, + 0xe3, 0x00, 0xd0, 0x54, 0x63, 0x00, 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, + 0x0a, 0x00, 0xe0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0xc0, 0xac, 0xef, 0x80, 0xd0, 0xae, + 0xef, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, + 0x84, 0x60, 0x30, 0x40, 0x45, 0x80, 0x30, 0x42, 0x45, 0x00, 0xa5, 0x86, 0xef, 0x80, 0x35, 0x86, + 0x6f, 0x80, 0x94, 0x84, 0x6f, 0x80, 0x24, 0x84, 0xef, 0x80, 0xb5, 0x88, 0x6f, 0x80, 0x45, 0x8a, + 0xef, 0x80, 0x04, 0x80, 0xef, 0x00, 0x02, 0x80, 0x6f, 0x80, 0x12, 0x82, 0xef, 0x80, 0x00, 0x80, + 0x7b, 0x00, 0x01, 0x80, 0x7b, 0x80, 0x01, 0x80, 0x68, 0x00, 0x00, 0x00, 0x84, 0x60, 0x32, 0x40, + 0xc5, 0x00, 0x08, 0x80, 0xe7, 0xfa, 0x3e, 0xf3, 0xbf, 0xbf, 0x4c, 0x33, 0x5d, 0x93, 0x4b, 0xf4, + 0x1a, 0xe2, 0x89, 0xc8, 0xee, 0x37, 0xf4, 0x14, 0xbb, 0x8b, 0x11, 0xf8, 0x95, 0x9e, 0x50, 0x8a, + 0x70, 0x17, 0x27, 0x33, 0x81, 0x07, 0xe0, 0x10, 0x00, 0x08, 0x83, 0xe7, 0x00, 0x10, 0x82, 0xfb, + 0x01, 0x00, 0x40, 0xa3, 0x00, 0x10, 0x82, 0xfb, 0x00, 0x18, 0x82, 0xe7, 0x98, 0x84, 0x00, 0x02, + 0x00, 0x10, 0x62, 0x63, 0x01, 0x00, 0x44, 0x23, 0x00, 0x20, 0x84, 0x70, 0x00, 0x01, 0x84, 0x62, + 0x00, 0x00, 0x00, 0x84, 0xc0, 0x32, 0x68, 0xc5, 0xe0, 0x32, 0x6a, 0xc5, 0xa0, 0x32, 0x6c, 0x45, + 0x00, 0x64, 0x8b, 0x67, 0x80, 0x53, 0x8a, 0x7b, 0x00, 0x66, 0x8d, 0xe7, 0x80, 0x65, 0x8c, 0x7b, + 0x00, 0x53, 0x80, 0x67, 0x80, 0x96, 0x82, 0x67, 0x00, 0x86, 0x84, 0x67, 0x80, 0x54, 0x86, 0xfb, + 0x80, 0x66, 0x88, 0xfb, 0x00, 0x32, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x7d, + 0x00, 0x54, 0x88, 0xfb, 0x00, 0x66, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0x67, 0x00, 0x01, 0x8a, 0x7b, + 0x80, 0x42, 0x88, 0xfd, 0x00, 0x94, 0x8a, 0x7b, 0x00, 0xd6, 0x96, 0xfb, 0x80, 0x55, 0x8a, 0xe7, + 0x00, 0x11, 0x96, 0x7b, 0x80, 0x55, 0x8a, 0x7d, 0x00, 0x42, 0x99, 0xe7, 0x00, 0x51, 0x97, 0xe7, + 0x00, 0xb6, 0x98, 0x7b, 0x00, 0x16, 0x96, 0xfd, 0x00, 0x16, 0x98, 0x7b, 0x00, 0xb6, 0x9a, 0x67, + 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x82, 0xfb, 0x00, 0x41, 0x85, 0x67, 0x00, 0x52, 0x89, 0xe7, + 0x00, 0x11, 0x82, 0x7b, 0x00, 0x01, 0x84, 0xfd, 0x00, 0x41, 0x85, 0x67, 0x00, 0x41, 0x88, 0x7b, + 0x00, 0x12, 0x80, 0x67, 0x00, 0xd0, 0x9a, 0xfb, 0x00, 0x52, 0x80, 0xe7, 0x80, 0x35, 0x96, 0x67, + 0xfa, 0x18, 0x32, 0x64, 0x6f, 0xd5, 0xa3, 0xde, 0x72, 0x05, 0x43, 0x4c, 0xae, 0x7c, 0x7f, 0xa8, + 0xf8, 0x61, 0x9c, 0x4c, 0x8a, 0x5d, 0x4e, 0x55, 0xfc, 0x27, 0x39, 0xd7, 0xa8, 0x28, 0x99, 0x39, + 0xe1, 0xb8, 0x11, 0x00, 0xb0, 0x96, 0xfd, 0x80, 0x30, 0x80, 0xe7, 0x00, 0x56, 0x98, 0x67, 0x00, + 0xc0, 0x98, 0xfb, 0x00, 0x66, 0xad, 0x67, 0x00, 0xbb, 0x96, 0x7d, 0x00, 0x00, 0x00, 0x84, 0x80, + 0x94, 0x80, 0x67, 0x00, 0x04, 0x80, 0xe7, 0x60, 0x32, 0x42, 0x45, 0x80, 0x13, 0x82, 0xe7, 0x00, + 0x14, 0x82, 0x7b, 0x00, 0x14, 0x82, 0xe7, 0x80, 0x73, 0x84, 0xe7, 0x00, 0x11, 0x82, 0x7b, 0x80, + 0x13, 0x82, 0xe7, 0x80, 0x00, 0x80, 0xe8, 0x00, 0x00, 0x00, 0x84, 0x00, 0x74, 0x80, 0xfb, 0x00, + 0x95, 0x82, 0x7d, 0x00, 0x10, 0x82, 0x67, 0x00, 0x74, 0x80, 0xfd, 0x00, 0x95, 0x84, 0x7b, 0x00, + 0x20, 0x84, 0x67, 0x00, 0x11, 0x86, 0xfb, 0x80, 0x31, 0x86, 0x67, 0x00, 0x11, 0x88, 0x7d, 0x00, + 0x42, 0x88, 0xe7, 0x00, 0x36, 0x92, 0x67, 0x00, 0xb2, 0x94, 0x67, 0x00, 0x00, 0x00, 0x84, 0x00, + 0x74, 0x82, 0x7b, 0x80, 0x10, 0x82, 0xe7, 0x00, 0x74, 0x84, 0x7d, 0x00, 0x21, 0x84, 0xe7, 0x00, + 0x11, 0x8e, 0xe7, 0x00, 0x11, 0x82, 0x7d, 0x80, 0x60, 0x86, 0xe7, 0x00, 0x31, 0x86, 0x7b, 0x80, + 0x11, 0x90, 0x67, 0x00, 0x00, 0x00, 0x84, 0x80, 0x32, 0x4c, 0x45, 0x00, 0xb0, 0x52, 0x63, 0x00, + 0xc0, 0x54, 0xe3, 0x01, 0x00, 0x4e, 0x23, 0x00, 0x00, 0x50, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, + 0x00, 0xf6, 0xf3, 0x00, 0xb0, 0x37, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, 0x00, 0x90, 0x4e, 0xe7, 0x00, + 0xa0, 0x50, 0xe7, 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, 0x00, 0x02, 0xfa, 0xe9, 0xae, 0x32, 0x50, + 0xc8, 0x40, 0xd2, 0x58, 0xb8, 0x9c, 0x34, 0x8f, 0x8c, 0x09, 0xce, 0x7a, 0x6f, 0xcb, 0x67, 0xaa, + 0x17, 0x48, 0x18, 0x37, 0xb0, 0x34, 0x59, 0x82, 0x25, 0x28, 0xde, 0x83, 0x90, 0x12, 0x00, 0x90, + 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x78, 0x8e, 0x00, 0x0a, 0x00, 0x01, + 0x7c, 0xa3, 0x00, 0xb0, 0x37, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, + 0x50, 0xe7, 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, 0x00, 0x02, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, + 0x50, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0xa4, 0x8e, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x76, + 0x80, 0xe7, 0x00, 0xb4, 0x82, 0xe7, 0x00, 0x86, 0x84, 0x67, 0x60, 0x32, 0x4c, 0xc5, 0x00, 0x63, + 0x86, 0xfb, 0x00, 0x31, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, 0x80, 0x41, 0x88, 0xfb, 0x80, 0xb3, + 0x8a, 0x67, 0x00, 0x51, 0x8a, 0x7b, 0x80, 0x42, 0x88, 0x67, 0x00, 0x31, 0x86, 0xe7, 0x80, 0x41, + 0x88, 0xfd, 0x00, 0x45, 0x88, 0x67, 0x80, 0x00, 0x82, 0xfd, 0x80, 0x10, 0x82, 0xe7, 0x80, 0x14, + 0x82, 0x67, 0x80, 0x40, 0x92, 0xfd, 0x80, 0xd6, 0x86, 0xfb, 0x00, 0x34, 0x86, 0xe7, 0x00, 0x35, + 0x86, 0x67, 0x00, 0x30, 0x8e, 0xe7, 0x00, 0x31, 0x90, 0x67, 0x00, 0x00, 0x00, 0x84, 0x58, 0x81, + 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0x00, 0x42, 0xa3, 0x00, 0xe0, 0x45, 0x65, 0x20, 0xe0, + 0x7d, 0x22, 0x00, 0xe0, 0x47, 0xe5, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x49, 0x65, 0x20, 0xe0, + 0x7d, 0x22, 0x00, 0xe0, 0x4b, 0xe5, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4d, 0xe5, 0x00, 0x20, + 0x04, 0xf9, 0x00, 0x30, 0x06, 0xf9, 0xfa, 0xb4, 0x5b, 0xaa, 0xcc, 0x50, 0x15, 0xa8, 0x18, 0xac, + 0x58, 0x09, 0x38, 0xf8, 0x85, 0xb6, 0x6d, 0x04, 0x24, 0x75, 0x55, 0xc9, 0xa7, 0x1a, 0xb5, 0xe2, + 0xd4, 0x12, 0x23, 0x35, 0x67, 0x99, 0xf9, 0x68, 0x13, 0x00, 0x40, 0x08, 0xf9, 0x00, 0x50, 0x0a, + 0xf9, 0x00, 0x60, 0x0c, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x11, 0x02, 0xfd, 0x80, 0x21, 0x04, + 0x7d, 0x00, 0x32, 0x06, 0xfd, 0x80, 0x42, 0x08, 0x7d, 0x00, 0x53, 0x0a, 0x7d, 0x00, 0x60, 0x0c, + 0xf3, 0x00, 0x00, 0x00, 0x84, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, 0x22, 0x00, 0x40, 0x44, + 0xe5, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x20, 0x2c, 0x63, 0x01, 0x60, 0x6b, 0x22, 0x00, 0x00, 0x42, + 0xa3, 0x04, 0x54, 0xe1, 0x35, 0x88, 0x90, 0x00, 0x9c, 0xff, 0x00, 0x40, 0x23, 0x00, 0x00, 0xa3, + 0xe2, 0x02, 0x10, 0x41, 0x28, 0x94, 0x90, 0x00, 0x8a, 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0x21, + 0xf5, 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0xa3, 0xe2, 0x00, 0x20, 0x84, 0x62, 0x00, 0x11, 0x41, + 0xe8, 0xa0, 0x90, 0x00, 0x0a, 0x05, 0x54, 0xf3, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x00, 0x03, 0x72, + 0xc9, 0x05, 0x54, 0xc1, 0x39, 0x88, 0x90, 0x00, 0x9c, 0x00, 0x60, 0x6b, 0xe3, 0x00, 0x54, 0xf5, + 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x01, 0x54, 0xef, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x02, 0x54, 0xfb, + 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x03, 0x54, 0xfd, 0x35, 0x88, 0x90, 0x00, 0x9c, 0x05, 0x54, 0xc1, + 0x39, 0x88, 0x90, 0x00, 0x9c, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, + 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, 0x00, 0xd0, 0xbb, 0xfb, 0x00, 0x00, 0xc4, + 0x73, 0xfa, 0x89, 0xb0, 0x12, 0x7e, 0xd4, 0x5a, 0x36, 0xa6, 0xbb, 0x5c, 0x83, 0x6e, 0x7f, 0xf5, + 0x0a, 0x62, 0x09, 0x8c, 0x99, 0xb6, 0xae, 0x58, 0xe0, 0x2e, 0xbc, 0x6b, 0xe9, 0x52, 0x86, 0xe5, + 0x8a, 0xc4, 0x40, 0x14, 0x00, 0x71, 0xaf, 0xe8, 0x00, 0xe1, 0xbd, 0xe8, 0x00, 0x7f, 0xa9, 0x68, + 0xe0, 0x03, 0x74, 0x49, 0x00, 0x04, 0x7a, 0xc9, 0xa0, 0x00, 0x60, 0xc5, 0x00, 0x00, 0x21, 0xf9, + 0xc0, 0x00, 0x62, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, + 0x05, 0x54, 0xc1, 0x39, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x12, 0x00, 0x44, 0xa3, + 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x00, 0x84, 0x6c, 0x90, 0x00, 0x82, + 0xf2, 0x00, 0x40, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x6c, 0x90, 0x00, 0x82, 0xf4, 0x00, 0x40, 0xa3, + 0x94, 0x81, 0x00, 0x98, 0x6c, 0x90, 0x00, 0x82, 0xf6, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, + 0x00, 0x00, 0xce, 0x73, 0x00, 0x00, 0xd0, 0x73, 0x00, 0x00, 0xd2, 0xf3, 0x00, 0x00, 0xd4, 0xf3, + 0x00, 0x70, 0xc0, 0xe3, 0x0c, 0x40, 0xc1, 0xa5, 0x4c, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x42, 0xa3, + 0x00, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x30, 0x8f, 0x00, 0x02, 0x08, 0x00, 0x56, 0x23, + 0x12, 0x00, 0x58, 0x23, 0x78, 0x8f, 0x00, 0x02, 0x01, 0xc0, 0x58, 0x24, 0xe0, 0x90, 0x00, 0x8a, + 0x00, 0x10, 0xc0, 0xe9, 0x01, 0xb0, 0x56, 0x24, 0xdc, 0x90, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, + 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, + 0x30, 0x8f, 0x00, 0x02, 0x80, 0x00, 0x5e, 0xa3, 0x00, 0xf0, 0x1e, 0xf3, 0xfa, 0x24, 0x2a, 0xdc, + 0xd0, 0xb7, 0xb4, 0xcb, 0x7c, 0x3b, 0x7c, 0x58, 0x44, 0xd0, 0x96, 0xf0, 0x18, 0x08, 0xbf, 0x69, + 0x25, 0xf8, 0x73, 0x8f, 0x1e, 0xa7, 0xa0, 0x9c, 0x57, 0x88, 0x6a, 0xdc, 0xfe, 0x18, 0x15, 0x00, + 0xf0, 0x1e, 0xf3, 0x00, 0xf0, 0x1e, 0xf3, 0x12, 0xb0, 0x56, 0xa4, 0x80, 0xb7, 0xa0, 0x62, 0x44, + 0x91, 0x00, 0x8a, 0x12, 0x00, 0x58, 0x23, 0x78, 0x8f, 0x00, 0x02, 0x01, 0xc0, 0x58, 0x24, 0x30, + 0x91, 0x00, 0x8a, 0x00, 0x10, 0xc0, 0xe9, 0x20, 0x91, 0x00, 0x18, 0x12, 0xb0, 0x56, 0xa2, 0x88, + 0x91, 0x00, 0x08, 0x12, 0x00, 0x58, 0x23, 0x80, 0xc5, 0x58, 0xe4, 0x78, 0x8f, 0x00, 0x02, 0x01, + 0xb0, 0x56, 0x24, 0x54, 0x91, 0x00, 0x0a, 0x01, 0xc0, 0x40, 0x28, 0x9c, 0x91, 0x00, 0x08, 0x04, + 0x00, 0x44, 0x23, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x11, 0x02, 0xfd, 0x00, 0x20, 0x04, 0xf3, 0x01, + 0xc0, 0x58, 0x24, 0x70, 0x91, 0x00, 0x0a, 0x80, 0x10, 0x82, 0x24, 0xac, 0x91, 0x00, 0x98, 0x00, + 0x00, 0x42, 0xa3, 0x8a, 0x00, 0x46, 0xa3, 0x80, 0x11, 0xc2, 0xe2, 0x80, 0x10, 0x82, 0x24, 0xac, + 0x91, 0x00, 0x98, 0x84, 0x00, 0x44, 0xa3, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x11, 0x02, 0xfd, 0xac, + 0x91, 0x00, 0x98, 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf6, 0x71, 0x00, 0x00, 0xc0, 0x2d, 0x00, + 0x70, 0xce, 0xeb, 0x00, 0x70, 0xd2, 0x6b, 0x00, 0x70, 0xc0, 0xe3, 0x0c, 0xb0, 0xc1, 0xa5, 0x04, + 0x00, 0x42, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xd0, + 0x91, 0x00, 0x0a, 0x80, 0x10, 0x82, 0x24, 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf8, 0xf1, 0x60, + 0x31, 0x7e, 0x45, 0x80, 0xcd, 0xb7, 0xf9, 0xfa, 0x95, 0x77, 0x24, 0x3c, 0xa0, 0x62, 0x4b, 0x4b, + 0x0d, 0xf5, 0xd3, 0xd7, 0xca, 0xc8, 0x5c, 0x12, 0xa8, 0x07, 0x23, 0x4c, 0x32, 0x13, 0x89, 0x83, + 0xe0, 0xa0, 0x5a, 0x97, 0xcc, 0x3f, 0x0a, 0xc7, 0xf0, 0x15, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, + 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x40, 0x31, 0x7e, 0xc5, 0xc0, 0x31, 0x6a, 0x45, 0xe0, 0x31, + 0x6c, 0xc5, 0xdc, 0x87, 0x00, 0x02, 0x01, 0x00, 0x42, 0x23, 0x80, 0x50, 0xab, 0xe2, 0x00, 0x50, + 0x2b, 0xed, 0x80, 0x6a, 0xad, 0xe4, 0x00, 0x60, 0x2d, 0xf9, 0x20, 0x03, 0x6c, 0x49, 0x00, 0x00, + 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, + 0x6b, 0x65, 0x00, 0x50, 0x2b, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x69, 0xe5, 0x00, 0x40, + 0x29, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x67, 0x65, 0x00, 0x30, 0x27, 0xf9, 0x20, 0xe0, + 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x20, 0x25, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, + 0x4c, 0x23, 0x00, 0x60, 0x8a, 0x70, 0x60, 0xb0, 0x92, 0x22, 0x1f, 0xb0, 0x90, 0x22, 0x20, 0x00, + 0x4e, 0x23, 0x00, 0x74, 0x50, 0xe4, 0x00, 0x80, 0x4e, 0xe3, 0x00, 0x70, 0x0e, 0x63, 0x00, 0x70, + 0x0e, 0x63, 0x00, 0x70, 0x0e, 0x63, 0x01, 0x70, 0x4e, 0x24, 0x00, 0x53, 0x0a, 0x7d, 0x01, 0x80, + 0x50, 0x24, 0x90, 0x92, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, + 0x56, 0x63, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x67, 0x65, 0x20, 0xe0, + 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x20, 0x25, 0xf9, 0x00, 0x03, + 0x68, 0x45, 0xfa, 0x94, 0x00, 0xcb, 0x53, 0xaa, 0xfc, 0x6e, 0x75, 0x94, 0xff, 0xb2, 0xed, 0x06, + 0x75, 0x8b, 0xcf, 0xf5, 0xf9, 0xb5, 0xae, 0x0f, 0x0d, 0x0d, 0x48, 0xa6, 0x9d, 0x77, 0x8c, 0x8b, + 0xdd, 0x53, 0xd1, 0xc8, 0x16, 0x20, 0x03, 0x6a, 0x45, 0x40, 0xb0, 0x7a, 0xa2, 0x00, 0xd0, 0x3b, + 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0x00, 0xc0, 0x2d, 0x64, 0x92, 0x00, + 0x82, 0x20, 0x90, 0x40, 0x28, 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, 0xe3, 0xac, 0x93, 0x00, + 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x67, 0x65, 0x20, 0xe0, 0x7d, + 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x20, 0x25, 0xf9, 0x00, 0x03, 0x68, + 0x45, 0x20, 0x03, 0x6a, 0x45, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x20, 0xe1, 0x6b, 0x80, 0x00, 0x7a, + 0xa3, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x2c, 0x92, 0x00, + 0x82, 0x00, 0x20, 0xe1, 0x6b, 0x80, 0xd0, 0x7b, 0x22, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, + 0xa3, 0x94, 0x81, 0x00, 0x98, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, 0x80, 0xd5, 0x7b, + 0xe2, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x2c, 0x92, 0x00, + 0x82, 0x80, 0xb0, 0x40, 0xa8, 0xdc, 0x93, 0x00, 0x08, 0x64, 0x92, 0x00, 0x82, 0x60, 0x90, 0x40, + 0xa8, 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, 0xe3, 0x40, 0x90, 0x40, 0x28, 0xac, 0x93, 0x00, + 0x88, 0x00, 0x00, 0x66, 0xa3, 0x20, 0x90, 0x40, 0x28, 0xa0, 0x93, 0x00, 0x88, 0x00, 0x00, 0x68, + 0x23, 0x80, 0x52, 0xab, 0x62, 0x80, 0x53, 0xeb, 0x62, 0xf8, 0x93, 0x00, 0x98, 0xfa, 0xc8, 0x41, + 0xc5, 0x5d, 0xc9, 0x24, 0x51, 0x56, 0xbf, 0xc9, 0xa9, 0x64, 0x3f, 0xca, 0x64, 0xda, 0x26, 0xd1, + 0xc6, 0x5a, 0xb4, 0x61, 0x44, 0x9c, 0x75, 0x00, 0x39, 0xb9, 0x94, 0x2f, 0x9f, 0x38, 0xa0, 0x17, + 0x80, 0x42, 0xa9, 0x62, 0x80, 0x43, 0xe9, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x32, 0xa7, 0x62, + 0x80, 0x33, 0xe7, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x22, 0xa5, 0x62, 0x80, 0x23, 0xe5, 0x62, + 0x10, 0xb0, 0x90, 0x22, 0xd0, 0x93, 0x00, 0x8a, 0x80, 0x2e, 0xa5, 0x64, 0xf8, 0x93, 0x00, 0x98, + 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x6a, 0xa3, 0xec, 0x93, 0x00, 0x98, 0x00, 0x20, 0xe1, 0x6b, + 0x00, 0x00, 0x6a, 0xa3, 0xff, 0x00, 0x4e, 0xa3, 0x80, 0x53, 0xeb, 0x62, 0x00, 0x00, 0x68, 0x23, + 0x00, 0x00, 0x66, 0xa3, 0x00, 0xd0, 0x65, 0xe3, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x20, 0xe1, 0x6b, + 0x00, 0x00, 0x21, 0xf9, 0x00, 0x10, 0x23, 0xf9, 0x80, 0x08, 0xb3, 0x79, 0x00, 0x00, 0x40, 0x23, + 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x60, 0x31, 0x7e, 0x45, 0xe0, 0x03, 0x74, 0x45, + 0x00, 0x04, 0x44, 0x45, 0x80, 0xac, 0x83, 0xff, 0x80, 0x2c, 0x84, 0xff, 0x80, 0xb0, 0x87, 0x7b, + 0x00, 0x31, 0x86, 0x7b, 0x40, 0x03, 0x46, 0xc9, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, + 0x00, 0x03, 0x58, 0x45, 0x00, 0xc0, 0x18, 0xf9, 0x10, 0x85, 0x00, 0x82, 0x00, 0x10, 0xbc, 0x28, + 0x10, 0x95, 0x00, 0x8a, 0x01, 0x00, 0x5a, 0x23, 0x00, 0xb6, 0x9c, 0x67, 0x00, 0x90, 0x79, 0xe3, + 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x4e, 0xc9, 0x80, 0x03, 0x50, 0x49, 0xa0, 0x03, 0x52, 0x49, + 0xc0, 0x03, 0x54, 0x49, 0x40, 0x03, 0x78, 0x45, 0xfa, 0xee, 0x1e, 0x5f, 0x3d, 0xb1, 0xc9, 0xcc, + 0xa5, 0x4c, 0x27, 0xa7, 0xdb, 0x16, 0xaa, 0xde, 0x67, 0x74, 0xd3, 0x5b, 0x19, 0x58, 0x54, 0x83, + 0xea, 0x51, 0x85, 0x41, 0x6f, 0xec, 0x68, 0x4b, 0xce, 0x78, 0x18, 0xc0, 0x31, 0x56, 0x45, 0xe0, + 0x31, 0x58, 0x45, 0x01, 0x00, 0x5a, 0x23, 0x00, 0xb6, 0x9c, 0x67, 0xa4, 0x86, 0x00, 0x82, 0x60, + 0x03, 0x56, 0xc5, 0x80, 0x03, 0x58, 0xc5, 0xa0, 0x03, 0x5a, 0xc5, 0xc0, 0x03, 0x5c, 0xc5, 0x00, + 0x00, 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, 0x00, 0x07, 0x9c, 0xfd, 0x18, 0x86, 0x00, 0x02, 0x00, + 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0xe4, 0x84, 0x00, 0x82, 0x64, + 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x20, 0x03, 0x48, 0x45, 0xff, 0x0f, 0x7e, 0xa3, 0x00, + 0xf0, 0x41, 0x28, 0x00, 0x82, 0x84, 0xe8, 0x18, 0x95, 0x00, 0x0a, 0x00, 0xf0, 0x41, 0x28, 0x00, + 0x82, 0x84, 0xe8, 0x18, 0x95, 0x00, 0x0a, 0xc3, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x10, + 0x00, 0x7c, 0x22, 0x40, 0x03, 0x4a, 0xc5, 0x00, 0x40, 0x08, 0xf9, 0x00, 0xe0, 0x49, 0x69, 0x20, + 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4b, 0xe9, 0x00, 0x00, 0x40, 0x23, 0x50, 0x00, 0x42, 0xa3, 0x2c, + 0x95, 0x00, 0x98, 0x36, 0x00, 0x40, 0x23, 0x1c, 0x95, 0x00, 0x98, 0x36, 0x00, 0x40, 0x23, 0x3c, + 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, 0x42, 0x23, 0x2c, 0x95, 0x00, 0x98, 0x00, + 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x94, 0x81, 0x00, 0x98, 0x00, 0x00, 0x8c, 0x67, 0x00, + 0x63, 0x8c, 0xfb, 0x01, 0x00, 0x7c, 0xa3, 0x00, 0x6f, 0x8e, 0x7b, 0x00, 0x70, 0xbc, 0x28, 0x6c, + 0x96, 0x00, 0x88, 0xfa, 0xf5, 0xad, 0x23, 0xf7, 0x3d, 0x20, 0xa5, 0xfe, 0x69, 0xe0, 0xd6, 0xbf, + 0x89, 0xf0, 0x4d, 0x23, 0xcb, 0x7f, 0xa7, 0x17, 0x64, 0xb3, 0xab, 0x19, 0x99, 0x6f, 0x64, 0x6a, + 0xb4, 0xa3, 0x85, 0x57, 0x50, 0x19, 0x60, 0x32, 0x50, 0x45, 0x00, 0x00, 0x7c, 0x23, 0x00, 0xe4, + 0x93, 0x7d, 0x00, 0x83, 0x90, 0x67, 0x80, 0x73, 0x94, 0x67, 0x80, 0xa3, 0x96, 0x67, 0x80, 0x84, + 0x90, 0x67, 0x00, 0x85, 0x90, 0xfb, 0x80, 0x84, 0x90, 0x67, 0x80, 0xb5, 0x98, 0x67, 0x00, 0xc6, + 0x94, 0x67, 0x80, 0xc5, 0x98, 0xe7, 0x00, 0xc4, 0x98, 0xe7, 0x00, 0xa6, 0x94, 0x67, 0x00, 0xa0, + 0x42, 0x63, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x25, + 0x9a, 0x67, 0x00, 0xd6, 0x9a, 0x67, 0x00, 0x32, 0x7c, 0xc5, 0x00, 0xdf, 0x9c, 0x67, 0x80, 0xd6, + 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa4, 0x88, 0x68, 0xc0, 0x95, 0x00, 0x0a, 0x00, 0xd0, + 0x42, 0xe3, 0xc8, 0x95, 0x00, 0x98, 0x00, 0xe0, 0x42, 0xe3, 0xc8, 0x95, 0x00, 0x98, 0x00, 0x93, + 0x84, 0xe7, 0x00, 0xd0, 0x86, 0xe7, 0x01, 0xe0, 0x89, 0xa4, 0x00, 0x32, 0x86, 0xe7, 0x00, 0x3f, + 0x88, 0xe7, 0x00, 0x83, 0x8c, 0xe7, 0x80, 0x31, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa3, + 0xbc, 0xfd, 0x00, 0xe0, 0xbd, 0xa8, 0xfc, 0x95, 0x00, 0x0a, 0x00, 0x30, 0x40, 0xe3, 0x04, 0x96, + 0x00, 0x98, 0x00, 0x40, 0x40, 0x63, 0x04, 0x96, 0x00, 0x98, 0x80, 0x10, 0x94, 0x67, 0x80, 0xa5, + 0x94, 0xe7, 0x00, 0xa4, 0xbc, 0x7d, 0x00, 0xe0, 0xbd, 0xa8, 0x20, 0x96, 0x00, 0x8a, 0x00, 0x90, + 0x46, 0xe3, 0x28, 0x96, 0x00, 0x18, 0x00, 0x20, 0x46, 0x63, 0x28, 0x96, 0x00, 0x18, 0xfa, 0xfd, + 0x83, 0xd3, 0x73, 0x71, 0xfe, 0x2c, 0xbc, 0x12, 0xe4, 0x48, 0xaa, 0x70, 0xb8, 0xf5, 0xa9, 0xe4, + 0x29, 0x65, 0xf1, 0x21, 0x20, 0xc5, 0x4d, 0x6f, 0x9c, 0x37, 0x2a, 0xa4, 0x7c, 0x59, 0xcc, 0x28, + 0x1a, 0x38, 0x96, 0x00, 0x8a, 0x00, 0x10, 0x44, 0xe3, 0x01, 0x00, 0x7c, 0xa3, 0x44, 0x96, 0x00, + 0x18, 0x00, 0x00, 0x44, 0x63, 0x00, 0x00, 0x7c, 0x23, 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, 0x40, + 0x23, 0x00, 0x01, 0x82, 0xfd, 0x01, 0x00, 0x50, 0x23, 0x00, 0x24, 0x8c, 0x62, 0x00, 0xe3, 0xbd, + 0x68, 0x64, 0x96, 0x00, 0x08, 0x00, 0x10, 0x56, 0xe3, 0x6c, 0x96, 0x00, 0x18, 0x00, 0x20, 0x56, + 0xe3, 0x6c, 0x96, 0x00, 0x18, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, + 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, 0x02, 0x00, 0x70, 0xbc, 0x28, 0x70, 0x96, 0x00, + 0x08, 0x80, 0xb3, 0x9a, 0xe7, 0x00, 0x30, 0x56, 0x63, 0x00, 0x70, 0x58, 0x63, 0x00, 0x00, 0x00, + 0x84, 0x40, 0x31, 0x7e, 0xc5, 0x00, 0x05, 0x42, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0xb4, 0xa3, 0x00, + 0x82, 0x38, 0x95, 0x00, 0x02, 0x00, 0x70, 0xbc, 0x28, 0x98, 0x96, 0x00, 0x08, 0x00, 0x33, 0x7c, + 0x45, 0x00, 0x3f, 0x94, 0x67, 0x80, 0x75, 0x9a, 0xe7, 0x80, 0x33, 0x98, 0x7d, 0x80, 0x33, 0x9c, + 0xfb, 0x00, 0xd7, 0x80, 0x67, 0x00, 0x00, 0xbc, 0xa8, 0x98, 0x96, 0x00, 0x08, 0x00, 0xa7, 0x96, + 0x67, 0x80, 0xc6, 0x98, 0xe7, 0x00, 0xb6, 0x9c, 0x67, 0x00, 0xb0, 0x96, 0x67, 0x00, 0xc0, 0x98, + 0x67, 0x00, 0x00, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x00, 0x08, 0x8d, 0xef, 0x00, 0x06, 0x8f, + 0xef, 0x80, 0x63, 0x8c, 0x6f, 0x00, 0x60, 0x42, 0x63, 0xfa, 0xef, 0xdf, 0xf8, 0xe0, 0x42, 0x0a, + 0x57, 0x90, 0x1c, 0x19, 0x51, 0x02, 0x57, 0x93, 0xa8, 0xee, 0x16, 0x63, 0x4b, 0x79, 0xb3, 0xcb, + 0x28, 0x09, 0xab, 0x02, 0xea, 0xb2, 0x15, 0xed, 0x35, 0x27, 0x00, 0x1b, 0xa4, 0x82, 0x00, 0x02, + 0x00, 0x30, 0x52, 0xe3, 0x80, 0x93, 0x92, 0x6f, 0x00, 0x31, 0x40, 0xc5, 0x00, 0x90, 0x94, 0xef, + 0x80, 0x94, 0x90, 0x6f, 0x00, 0x88, 0x90, 0x6f, 0x00, 0x86, 0x80, 0xe8, 0x00, 0x90, 0x54, 0xef, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x68, 0xe3, 0x20, 0x31, 0x40, 0x45, 0x60, 0x30, 0x42, 0xc5, + 0x80, 0x30, 0x44, 0x45, 0x00, 0x4a, 0x97, 0x6f, 0x80, 0x05, 0x96, 0xef, 0x80, 0xb5, 0x98, 0xef, + 0x80, 0xc5, 0x98, 0x7b, 0x01, 0x00, 0x48, 0x23, 0x00, 0xc2, 0x9a, 0xfb, 0x80, 0x26, 0x9a, 0x6f, + 0x00, 0x00, 0x48, 0xa3, 0x00, 0x46, 0x9c, 0xfd, 0x00, 0xc0, 0x80, 0xa8, 0x00, 0xe0, 0x40, 0x6f, + 0x00, 0x17, 0x9c, 0x6f, 0x80, 0xd6, 0x98, 0xef, 0x00, 0xe7, 0xa0, 0x6f, 0x00, 0x18, 0x9e, 0xef, + 0x80, 0xc7, 0x98, 0xfb, 0x80, 0xc6, 0x98, 0x6f, 0x00, 0x07, 0xa1, 0x6f, 0x00, 0x28, 0x9e, 0xef, + 0x80, 0xc7, 0x98, 0xfb, 0x80, 0xb6, 0xa2, 0xef, 0xf0, 0x96, 0x00, 0x82, 0x00, 0xba, 0xa4, 0x6f, + 0x00, 0x25, 0xa5, 0xef, 0x00, 0xd0, 0x62, 0x6f, 0x00, 0xa0, 0x64, 0xef, 0x00, 0x00, 0x42, 0xa3, + 0x00, 0x19, 0x82, 0xfd, 0x00, 0x49, 0x81, 0x68, 0x01, 0x00, 0x44, 0x23, 0x00, 0x01, 0x80, 0xe2, + 0x00, 0x10, 0x64, 0x6f, 0x00, 0x10, 0x64, 0x63, 0x00, 0x27, 0xa5, 0x6f, 0x00, 0xe0, 0x66, 0xe3, + 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x42, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0xb4, 0xa3, 0x00, 0x82, + 0x28, 0x97, 0x00, 0x02, 0xfa, 0x5f, 0xa4, 0x00, 0x8c, 0xc3, 0xac, 0x26, 0x42, 0xb5, 0x43, 0x7a, + 0x37, 0x49, 0x9c, 0x12, 0xb3, 0xd4, 0x14, 0x38, 0xa2, 0xbe, 0x25, 0xdf, 0x86, 0x12, 0x08, 0xf5, + 0x99, 0x66, 0x3b, 0x7d, 0x41, 0xd8, 0x1b, 0x00, 0x30, 0xbd, 0x28, 0xc8, 0x97, 0x00, 0x88, 0x00, + 0x00, 0x00, 0x84, 0x20, 0x30, 0x7e, 0x45, 0x60, 0x10, 0x40, 0x28, 0x18, 0x98, 0x00, 0x08, 0x10, + 0x00, 0x48, 0xa2, 0x00, 0x40, 0x66, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x00, 0x68, 0x23, 0x80, + 0x49, 0xb9, 0x79, 0x80, 0xc9, 0x83, 0xe8, 0xb4, 0x99, 0x00, 0x0a, 0x00, 0xc0, 0x83, 0xa8, 0xb4, + 0x99, 0x00, 0x88, 0x2c, 0x98, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, 0x00, 0x00, 0xe8, 0xf3, 0x80, + 0x49, 0xb9, 0x79, 0x00, 0xc0, 0x83, 0xa8, 0xb4, 0x99, 0x00, 0x88, 0x00, 0x00, 0xc0, 0xf3, 0x00, + 0x00, 0xc2, 0x73, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x00, 0xc6, 0xf3, 0x00, 0x00, 0xc0, 0x63, 0x0a, + 0xc0, 0xc1, 0x25, 0x04, 0x00, 0x44, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x04, 0xf3, 0x01, + 0xe0, 0x7d, 0x24, 0x4c, 0x98, 0x00, 0x0a, 0x80, 0x20, 0x84, 0x24, 0x00, 0x20, 0xc0, 0xe9, 0x00, + 0x00, 0xfa, 0x71, 0x20, 0x01, 0x78, 0xc9, 0x40, 0x01, 0x7a, 0x49, 0x20, 0x30, 0x7e, 0x45, 0x00, + 0x00, 0xfc, 0xf3, 0x00, 0xcf, 0xf9, 0xff, 0x00, 0x30, 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, 0xc0, + 0x30, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, + 0xa3, 0x00, 0x82, 0x01, 0x00, 0x9c, 0xa4, 0x00, 0xc7, 0x98, 0x6f, 0x00, 0xd7, 0x9a, 0x6f, 0x00, + 0xc0, 0x52, 0xe3, 0x00, 0xd0, 0x54, 0x63, 0x00, 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0xfa, + 0x3b, 0xbd, 0x2a, 0xed, 0x5b, 0x43, 0x55, 0x15, 0x85, 0x4e, 0x90, 0xc3, 0x5d, 0x5b, 0xee, 0x00, + 0x81, 0xb1, 0x16, 0x4d, 0x1a, 0xda, 0x4c, 0x2f, 0xbd, 0x46, 0x4b, 0x0e, 0xa8, 0xf3, 0x70, 0xf5, + 0xb0, 0x1c, 0xc0, 0x99, 0x00, 0x0a, 0x80, 0x30, 0x50, 0x45, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, + 0x40, 0xa8, 0xc0, 0x99, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0xc0, 0x99, 0x00, 0x0a, 0x00, 0xb0, + 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0x90, 0x92, 0x6f, 0x80, 0xa0, 0x94, 0x6f, 0x00, 0x90, + 0x19, 0x6d, 0x00, 0xc0, 0x18, 0xf3, 0xaa, 0xc0, 0x98, 0xa4, 0x00, 0xc0, 0x18, 0xf3, 0x00, 0x01, + 0x40, 0xc5, 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0xa8, 0xe2, 0x60, 0x40, 0x41, 0xa8, 0x08, 0x99, + 0x00, 0x08, 0x02, 0xc0, 0x98, 0x24, 0x0c, 0x99, 0x00, 0x18, 0x01, 0xc0, 0x98, 0x24, 0x00, 0xc0, + 0x18, 0xf3, 0x01, 0xc0, 0x98, 0x24, 0x04, 0xa4, 0xd9, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, + 0xd3, 0xb7, 0xb4, 0x99, 0x00, 0x9c, 0x06, 0xa4, 0xd5, 0xb7, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, + 0xc1, 0xb9, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, 0x00, 0x9c, 0x20, 0x01, + 0x78, 0xc5, 0x40, 0x01, 0x7a, 0x45, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, + 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xc0, 0xb9, 0xfd, 0x00, 0x00, 0xc4, 0x73, 0x00, 0xd1, + 0xbb, 0xe8, 0x00, 0x90, 0x75, 0xe3, 0xff, 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, + 0x12, 0xf3, 0x80, 0xc4, 0x94, 0x68, 0x00, 0xa4, 0xf9, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x01, 0xa4, + 0xfb, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0x37, 0xfa, 0x45, 0xd4, 0x14, 0xe9, 0x9f, + 0xd9, 0x0e, 0x80, 0xa8, 0xb7, 0xfa, 0xe2, 0x4c, 0xc3, 0x28, 0xc7, 0xdb, 0x2b, 0xcf, 0xe3, 0x57, + 0x92, 0x30, 0x13, 0x88, 0x36, 0x66, 0x56, 0x5a, 0x6d, 0x6c, 0x6d, 0x88, 0x1d, 0xb4, 0x99, 0x00, + 0x9c, 0x03, 0xa4, 0xc5, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x04, 0xa4, 0xd5, 0x37, 0xb4, 0x99, 0x00, + 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, 0x00, + 0x9c, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0xf2, 0x00, 0x46, + 0xa3, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0x41, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, + 0x84, 0x60, 0x10, 0x40, 0x28, 0xe0, 0x99, 0x00, 0x08, 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x66, + 0xe5, 0xe4, 0x99, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, 0x01, 0x00, 0x64, 0xa3, 0x00, 0x20, 0x25, + 0xed, 0x00, 0x00, 0x62, 0x23, 0x00, 0x01, 0x60, 0x23, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x00, 0xc0, + 0x2d, 0x00, 0x00, 0xf9, 0xeb, 0x00, 0xd0, 0x3b, 0xf9, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, + 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x0e, 0xba, 0x62, 0xfe, 0x00, 0x42, + 0x23, 0x80, 0xd0, 0xfb, 0x62, 0x00, 0xc0, 0x39, 0xf9, 0x20, 0x01, 0x7a, 0x49, 0x40, 0x01, 0x78, + 0xc9, 0x00, 0x00, 0xfc, 0xf3, 0x60, 0x31, 0x7e, 0x45, 0x00, 0xdf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, + 0xc5, 0xc0, 0x31, 0x56, 0x45, 0xe0, 0x31, 0x58, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, + 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x9a, 0xa4, 0x80, 0xb6, 0x96, 0xe7, 0x00, 0xb6, 0x9c, + 0x67, 0x80, 0xc6, 0x98, 0xe7, 0xfa, 0xf3, 0xe9, 0x29, 0x44, 0x9c, 0x55, 0x88, 0x7a, 0x3f, 0xb9, + 0xcf, 0x5a, 0xf9, 0x23, 0xfa, 0xaf, 0x40, 0xef, 0xd0, 0xb2, 0xa3, 0x3c, 0x61, 0xb8, 0xd7, 0x76, + 0xf0, 0x28, 0x83, 0xd1, 0x75, 0x80, 0x60, 0x1e, 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0xb0, 0x4e, 0xe3, + 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0x00, 0xe0, 0x54, 0x63, 0x10, 0x89, 0x00, 0x82, + 0x70, 0x9b, 0x00, 0x0a, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x70, 0x9b, 0x00, 0x0a, + 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, 0xe4, 0x84, 0x00, 0x82, 0x00, 0x90, 0x15, 0x6d, + 0x00, 0xa0, 0x14, 0xf3, 0xaa, 0xa0, 0x94, 0xa4, 0x00, 0xa0, 0x14, 0xf3, 0x00, 0x01, 0x40, 0xc5, + 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0x92, 0xe2, 0x60, 0x90, 0x40, 0xa8, 0xc0, 0x9a, 0x00, 0x88, + 0x02, 0xa0, 0x94, 0x24, 0xc4, 0x9a, 0x00, 0x98, 0x01, 0xa0, 0x94, 0x24, 0x00, 0xa0, 0x14, 0xf3, + 0x02, 0xa0, 0x94, 0x24, 0x04, 0xa4, 0xd5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xd1, 0x37, + 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, + 0x7c, 0x9b, 0x00, 0x9c, 0x20, 0x01, 0x78, 0xc5, 0x40, 0x01, 0x7a, 0x45, 0x00, 0x00, 0x40, 0x23, + 0x60, 0x31, 0x7e, 0x45, 0x00, 0x0e, 0xbc, 0xf9, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, + 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x80, 0x24, 0x00, 0xe0, 0xb9, 0x7d, 0x00, 0x00, 0xc4, 0x73, + 0x00, 0xd1, 0xbb, 0xe8, 0x00, 0x90, 0x75, 0xe3, 0xff, 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, + 0x00, 0x90, 0x12, 0xf3, 0x80, 0xa4, 0x94, 0x68, 0x00, 0xa4, 0xf9, 0x37, 0x7c, 0x9b, 0x00, 0x9c, + 0xfa, 0xad, 0x56, 0x9d, 0x5b, 0x5e, 0x2b, 0xc5, 0x13, 0xfa, 0x8b, 0x0e, 0x56, 0x14, 0xa5, 0xf3, + 0xd4, 0xfd, 0x10, 0xfa, 0xc4, 0xf4, 0xbc, 0x0c, 0xaa, 0x96, 0x7a, 0x7e, 0xd4, 0x5f, 0x98, 0xd1, + 0x37, 0x38, 0x1f, 0x01, 0xa4, 0xfb, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0x37, 0x7c, + 0x9b, 0x00, 0x9c, 0x03, 0xa4, 0xc5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x04, 0xa4, 0xd5, 0x37, 0x7c, + 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0x7c, + 0x9b, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0x41, + 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, + 0x00, 0x00, 0x84, 0x00, 0x00, 0xc6, 0xf3, 0x00, 0x00, 0xc8, 0x73, 0x00, 0x00, 0xca, 0xf3, 0x00, + 0x00, 0xcc, 0xf3, 0x00, 0x30, 0xc0, 0x63, 0x0b, 0x40, 0xc1, 0x25, 0x4c, 0xa3, 0x00, 0x02, 0x00, + 0x00, 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x43, 0x63, 0x80, 0x00, 0x00, 0xfd, 0x00, + 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xb0, 0x9b, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, 0x0e, + 0x00, 0x7c, 0xa3, 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xc8, + 0x9b, 0x00, 0x0a, 0x04, 0x00, 0x7c, 0xa3, 0x00, 0x00, 0x42, 0xa3, 0x80, 0x00, 0x00, 0xfd, 0x00, + 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xe0, 0x9b, 0x00, 0x0a, 0x1a, 0x00, 0x7c, 0xa3, 0x00, + 0x0f, 0xc0, 0xe2, 0x80, 0x00, 0x80, 0x24, 0x00, 0x00, 0xc0, 0x69, 0x00, 0x00, 0xf6, 0x71, 0x00, + 0x00, 0xc0, 0x2d, 0x00, 0x30, 0xc6, 0xeb, 0x00, 0x30, 0xca, 0xeb, 0xfa, 0x0c, 0xb2, 0x39, 0xf3, + 0xa2, 0xe5, 0x7c, 0xb2, 0x21, 0x30, 0xee, 0xdd, 0x77, 0x8b, 0x10, 0x23, 0x20, 0x70, 0x11, 0xd4, + 0x62, 0x1e, 0xca, 0xca, 0xbd, 0xab, 0xe7, 0x53, 0x29, 0xf5, 0x60, 0xa6, 0x10, 0x20, 0x00, 0x30, + 0xc0, 0x63, 0x0b, 0xb0, 0xc1, 0x25, 0x04, 0x00, 0x42, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x10, + 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x20, 0x9c, 0x00, 0x8a, 0x80, 0x10, 0x82, 0x24, 0x00, 0x10, + 0xc0, 0xe9, 0x00, 0x00, 0xf8, 0xf1, 0x20, 0x01, 0x64, 0x49, 0x20, 0x30, 0x7e, 0x45, 0x80, 0xcd, + 0xb7, 0xf9, 0x00, 0xb0, 0x81, 0xa8, 0xdc, 0x9d, 0x00, 0x88, 0xa0, 0x30, 0x6c, 0xc5, 0xc0, 0x30, + 0x6e, 0x45, 0xa8, 0x8b, 0x00, 0x02, 0x00, 0x00, 0x46, 0xe3, 0x00, 0x00, 0x40, 0xa8, 0xfc, 0x9d, + 0x00, 0x8a, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x0b, 0xac, 0x79, 0x00, 0x60, + 0x81, 0x28, 0xe4, 0x9d, 0x00, 0x08, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, + 0x00, 0x82, 0x00, 0x00, 0x72, 0x63, 0x01, 0x90, 0xb3, 0x24, 0x80, 0x9d, 0x83, 0x7f, 0xa8, 0x81, + 0x00, 0x02, 0x20, 0x01, 0x64, 0x45, 0x80, 0x2c, 0x95, 0xff, 0x80, 0x6c, 0x97, 0xff, 0x80, 0xa5, + 0x99, 0x7f, 0x80, 0x55, 0x9b, 0xff, 0x80, 0xc6, 0x96, 0xfb, 0x80, 0xa5, 0x94, 0x7b, 0x00, 0x15, + 0x94, 0xff, 0x00, 0xa0, 0x80, 0xa8, 0xec, 0x9d, 0x00, 0x88, 0x40, 0x01, 0x54, 0x49, 0x00, 0xa0, + 0x42, 0x63, 0xa8, 0x81, 0x00, 0x02, 0x80, 0x20, 0xb9, 0x7f, 0x80, 0x60, 0xb7, 0x7f, 0x00, 0x30, + 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, 0xc0, 0x30, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x94, 0x8a, + 0x00, 0x82, 0x00, 0x90, 0x5e, 0xe3, 0xfa, 0x2d, 0x2b, 0x3c, 0x7a, 0xab, 0xd9, 0xd4, 0x8f, 0x2e, + 0x43, 0xd9, 0xfb, 0x55, 0xc9, 0xc1, 0x31, 0x8e, 0xa8, 0x98, 0xad, 0xc1, 0x02, 0x10, 0xd2, 0xd3, + 0x6d, 0xe5, 0x5d, 0xfd, 0x4f, 0x8b, 0xe2, 0xe8, 0x20, 0x00, 0xa0, 0x60, 0x63, 0x00, 0xb0, 0x62, + 0x63, 0x60, 0x01, 0x58, 0xc5, 0x80, 0x01, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0xb0, 0x79, + 0x63, 0x94, 0x8a, 0x00, 0x82, 0x80, 0xf5, 0x84, 0xef, 0x80, 0x98, 0x86, 0xef, 0x80, 0x21, 0x80, + 0xe8, 0x38, 0x9d, 0x00, 0x0a, 0x80, 0x05, 0x85, 0x6f, 0x80, 0xa8, 0x86, 0xef, 0x80, 0x21, 0x80, + 0xe8, 0xf4, 0x9d, 0x00, 0x0a, 0xfc, 0x89, 0x00, 0x02, 0x00, 0x90, 0x58, 0xe3, 0x00, 0xa0, 0x5a, + 0x63, 0x00, 0xb0, 0x5c, 0xe3, 0x48, 0x9d, 0x00, 0x98, 0x00, 0xf0, 0x58, 0xe3, 0x00, 0x00, 0x5b, + 0xe3, 0x00, 0x10, 0x5d, 0x63, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe0, 0x42, 0xe3, 0x98, 0x83, 0x00, + 0x82, 0x80, 0xc0, 0x98, 0x6f, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x06, 0x98, + 0x79, 0x00, 0x00, 0x7e, 0xa3, 0x00, 0xf0, 0x41, 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, 0x9d, 0x00, + 0x0a, 0x00, 0xf0, 0x41, 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, 0x9d, 0x00, 0x0a, 0x00, 0x00, 0x46, + 0x23, 0xc3, 0x00, 0x44, 0xa3, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x45, + 0x69, 0x00, 0x30, 0x40, 0xa8, 0x01, 0x00, 0x42, 0x23, 0xbc, 0x9d, 0x00, 0x0a, 0x50, 0x00, 0x42, + 0xa3, 0x10, 0x00, 0x7c, 0x22, 0x00, 0x60, 0x2d, 0xf9, 0x00, 0xe0, 0x6d, 0x69, 0x20, 0xe0, 0x7d, + 0x22, 0x40, 0x01, 0x54, 0x45, 0x00, 0xa0, 0x14, 0xf9, 0x00, 0xe0, 0x55, 0xe9, 0x00, 0x30, 0x40, + 0xe3, 0xfa, 0x50, 0x17, 0xdd, 0xae, 0x37, 0x2e, 0xa3, 0x8e, 0x0a, 0x04, 0xd0, 0x65, 0x48, 0x11, + 0x5d, 0xa6, 0x97, 0xda, 0x82, 0x32, 0x82, 0x11, 0x54, 0xaf, 0xd8, 0x29, 0x34, 0x53, 0x60, 0x73, + 0x91, 0x54, 0xc0, 0x21, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x74, 0xa3, + 0x00, 0x00, 0x76, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x94, 0x81, 0x00, 0x98, + 0x21, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, 0x22, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, + 0x23, 0x00, 0x46, 0xa3, 0xfc, 0x9d, 0x00, 0x98, 0x24, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, + 0x3c, 0x00, 0x44, 0xa3, 0x01, 0x00, 0x42, 0x23, 0x84, 0x9d, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, + 0x40, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0x40, 0x23, 0x00, 0x08, 0x80, 0xf9, 0x00, 0x08, 0x80, 0xe8, + 0xdc, 0x9e, 0x00, 0x0a, 0xd8, 0x8c, 0x00, 0x02, 0xdc, 0x9e, 0x00, 0x0a, 0x00, 0x00, 0xc4, 0x73, + 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xa4, 0x24, 0x00, 0x09, 0xa1, 0x67, + 0x00, 0x19, 0xa3, 0x67, 0x00, 0x00, 0xfc, 0xf3, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x3f, 0xf9, 0xff, + 0x40, 0x31, 0x7e, 0xc5, 0x70, 0x96, 0x00, 0x02, 0x5c, 0x8e, 0x00, 0x82, 0xd0, 0x8e, 0x00, 0x02, + 0x00, 0x70, 0x6e, 0x63, 0x00, 0x80, 0x70, 0x63, 0x00, 0x90, 0x72, 0x63, 0xd4, 0x8d, 0x00, 0x82, + 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x4f, 0xe3, 0x00, 0x20, 0x51, 0x63, 0x00, 0x10, 0x53, 0xe3, + 0x0c, 0x8d, 0x00, 0x82, 0x00, 0x00, 0xfc, 0xf3, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x3f, 0xf9, 0xff, + 0x40, 0x31, 0x7e, 0xc5, 0x5c, 0x8e, 0x00, 0x82, 0xd0, 0x8e, 0x00, 0x02, 0xfa, 0x3b, 0x0b, 0xc2, + 0x9a, 0xbf, 0xc1, 0x56, 0x52, 0x87, 0x47, 0x29, 0xe6, 0x7f, 0x67, 0x7a, 0x11, 0xa5, 0x6b, 0x91, + 0x03, 0xf7, 0xa8, 0xa5, 0xdb, 0x49, 0x07, 0x8c, 0xc0, 0x40, 0x6b, 0xf2, 0xf8, 0x98, 0x22, 0xd4, + 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x80, 0x04, 0x92, 0xfd, 0x00, + 0x70, 0x57, 0x63, 0x00, 0x80, 0x59, 0xe3, 0x00, 0x90, 0x5b, 0xe3, 0x0c, 0x8d, 0x00, 0x82, 0x00, + 0xc0, 0x42, 0x63, 0x74, 0x84, 0x00, 0x82, 0x80, 0xb0, 0x96, 0xe7, 0x80, 0xd0, 0x9a, 0xe7, 0x01, + 0x00, 0x58, 0xa3, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, + 0x00, 0x00, 0x84, 0x12, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, + 0x00, 0x00, 0x84, 0xa8, 0xa4, 0x00, 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, 0x22, 0x00, + 0x40, 0x48, 0xe5, 0xff, 0x00, 0x44, 0xa3, 0x00, 0x41, 0x82, 0xe2, 0x00, 0x40, 0x32, 0xf5, 0x00, + 0x90, 0x09, 0xf5, 0x00, 0x40, 0x08, 0xf5, 0x00, 0x91, 0xb3, 0xe2, 0x00, 0x41, 0x88, 0xe2, 0x00, + 0x00, 0x00, 0x84, 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x33, 0x63, 0x04, 0x94, 0xc1, 0xb9, 0x7c, + 0xa0, 0x00, 0x1c, 0x01, 0x90, 0x75, 0x22, 0x04, 0xa4, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x02, + 0x40, 0x40, 0xa8, 0x54, 0x9f, 0x00, 0x08, 0x01, 0x40, 0x40, 0xa8, 0x70, 0x9f, 0x00, 0x08, 0xf4, + 0x00, 0x46, 0xa3, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xcc, 0x99, 0x00, 0x82, 0x00, + 0x30, 0x40, 0xa8, 0x68, 0x9f, 0x00, 0x08, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xc3, + 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xfa, 0x11, 0x0b, 0x0b, 0xbf, 0xbd, 0x78, 0xa8, 0x06, + 0x83, 0xf6, 0xb6, 0x4f, 0x3e, 0x39, 0x17, 0x95, 0x92, 0x10, 0x13, 0x6c, 0xed, 0xec, 0xda, 0xe2, + 0x2c, 0x65, 0xcb, 0x8d, 0x0b, 0xa7, 0x91, 0xef, 0x70, 0x23, 0xe4, 0x97, 0x00, 0x02, 0x00, 0x30, + 0x40, 0xa8, 0x84, 0x9f, 0x00, 0x88, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xc3, 0x00, + 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa2, 0x01, 0x00, + 0x42, 0x23, 0x00, 0x00, 0x44, 0x69, 0x00, 0x30, 0x40, 0xe3, 0x00, 0xa1, 0x00, 0x98, 0x64, 0x81, + 0x00, 0x02, 0x00, 0x00, 0x68, 0xe3, 0x00, 0x40, 0x6b, 0x22, 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, + 0x35, 0x63, 0x01, 0xa0, 0x75, 0x22, 0xf2, 0x00, 0x46, 0xa3, 0x04, 0xa4, 0xc1, 0xb9, 0x70, 0xa0, + 0x00, 0x9e, 0x04, 0xa4, 0xc5, 0x35, 0x7c, 0xa0, 0x00, 0x1c, 0xf6, 0x00, 0x46, 0x23, 0xff, 0x00, + 0x7c, 0x23, 0x00, 0x20, 0x4a, 0x63, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0x01, 0x40, + 0x40, 0xa8, 0xf4, 0x9f, 0x00, 0x08, 0x02, 0x40, 0x40, 0xa8, 0x70, 0xa0, 0x00, 0x8a, 0x00, 0x50, + 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0xaa, 0x40, 0x40, 0x28, 0x70, 0xa0, 0x00, 0x8a, 0x00, 0x50, + 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0x80, 0x4c, 0x40, 0x68, 0x70, 0xa0, 0x00, 0x8a, 0xf4, 0x00, + 0x46, 0xa3, 0x00, 0xe1, 0xbd, 0xe2, 0x02, 0xe0, 0x41, 0x28, 0x44, 0xa0, 0x00, 0x88, 0x01, 0xe0, + 0x41, 0x28, 0x70, 0xa0, 0x00, 0x8a, 0x50, 0x00, 0x42, 0xa3, 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, + 0x00, 0x1c, 0x06, 0xa4, 0xe3, 0x35, 0x7c, 0xa0, 0x00, 0x1c, 0x50, 0xa0, 0x00, 0x18, 0x30, 0x00, + 0x42, 0xa3, 0xfa, 0x4e, 0xad, 0x37, 0xa9, 0x48, 0x0f, 0x6d, 0xa3, 0xed, 0x43, 0xbb, 0xa1, 0xef, + 0x8b, 0xac, 0x8a, 0xef, 0xee, 0x61, 0x82, 0xb1, 0x59, 0xc9, 0xff, 0x7c, 0x80, 0xe9, 0x51, 0xe7, + 0xcd, 0x32, 0x86, 0x48, 0x24, 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, 0x00, 0x1c, 0x05, 0xa4, 0xc1, + 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0xff, 0x0f, 0x4a, 0x23, 0x80, 0x22, 0x84, 0x62, 0x00, 0x20, 0x04, + 0xf3, 0xc3, 0x20, 0x84, 0xa4, 0x00, 0x00, 0x40, 0x23, 0x8c, 0xa0, 0x00, 0x98, 0x12, 0x00, 0x44, + 0xa3, 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, 0x00, 0x98, 0x3c, 0x00, 0x44, 0xa3, 0xf2, 0x00, 0x46, + 0xa3, 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, 0x00, 0x98, 0x00, 0x50, 0x45, 0xe9, 0x10, 0x40, 0x6d, + 0xa2, 0x00, 0x00, 0x21, 0xf9, 0x00, 0x60, 0x61, 0xe9, 0x20, 0x60, 0x6d, 0x22, 0x00, 0x10, 0x23, + 0xf9, 0x00, 0x60, 0x63, 0x69, 0x00, 0x00, 0x40, 0x23, 0x00, 0xa1, 0x00, 0x98, 0xf0, 0x9e, 0x00, + 0x02, 0x00, 0x90, 0x33, 0x63, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x6a, 0x22, 0x03, 0x94, 0xc1, + 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x05, 0x94, 0xc1, + 0x39, 0x01, 0x90, 0x73, 0x22, 0x03, 0x94, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0x04, 0x94, 0xc1, + 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x05, 0x94, 0xc1, 0x39, 0xc3, 0x00, 0x44, 0xa3, 0x00, 0x50, 0x45, + 0xe9, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x40, 0x23, 0x00, 0xa1, 0x00, 0x98, 0x00, 0x00, 0x7e, + 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x44, + 0xa3, 0x00, 0x00, 0x54, 0x23, 0x94, 0x81, 0x00, 0x98, 0x58, 0x81, 0x00, 0x02, 0xfa, 0x43, 0xa1, + 0xb7, 0x84, 0x50, 0xf7, 0x72, 0x45, 0x64, 0xe7, 0x10, 0x4e, 0x30, 0x56, 0xae, 0x1f, 0x5f, 0xf8, + 0x4b, 0x57, 0x00, 0x14, 0x6c, 0xaf, 0xae, 0xa9, 0xfb, 0xc5, 0x15, 0xf1, 0x2a, 0x42, 0x20, 0x25, + 0x00, 0x00, 0x48, 0x22, 0x00, 0x40, 0x48, 0xe5, 0x00, 0x40, 0x04, 0xf5, 0xff, 0x00, 0x4c, 0x23, + 0x00, 0x23, 0x84, 0x62, 0x00, 0x20, 0x32, 0x63, 0x01, 0x90, 0xb3, 0x24, 0x04, 0x94, 0xcb, 0xb5, + 0x0c, 0xa2, 0x00, 0x1c, 0xff, 0x00, 0x4c, 0x23, 0x00, 0x53, 0x8e, 0xe2, 0x01, 0x70, 0x40, 0xa8, + 0x00, 0xa2, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x50, 0x0a, 0xf5, + 0x00, 0x53, 0x8e, 0xe2, 0x00, 0x71, 0x40, 0x68, 0xf4, 0xa1, 0x00, 0x0a, 0x05, 0x94, 0xcb, 0x35, + 0x0c, 0xa2, 0x00, 0x1c, 0x60, 0x01, 0x4a, 0xc9, 0x06, 0x94, 0xcb, 0x35, 0x0c, 0xa2, 0x00, 0x1c, + 0x80, 0x01, 0x4a, 0x49, 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, 0x73, 0x24, 0x00, 0x94, 0xf5, 0xb5, + 0x0c, 0xa2, 0x00, 0x1c, 0x01, 0x94, 0xed, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x02, 0x94, 0xeb, 0x35, + 0x0c, 0xa2, 0x00, 0x1c, 0x03, 0x94, 0xef, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x05, 0x94, 0xc1, 0x39, + 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x64, 0x65, 0x00, 0x20, 0x25, 0xf9, 0x20, 0x30, 0x7e, 0x45, + 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, + 0x00, 0x50, 0xab, 0xfb, 0x00, 0x00, 0xd4, 0xf3, 0x00, 0x65, 0xad, 0x68, 0x00, 0x75, 0xaf, 0x68, + 0x80, 0x6b, 0xa9, 0xe8, 0xa0, 0x00, 0x60, 0xc5, 0x00, 0x00, 0x21, 0xf9, 0xc0, 0x00, 0x62, 0x45, + 0x88, 0x9b, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xfa, 0x9b, 0x81, 0xa2, 0x92, 0x89, 0x54, 0x3f, + 0x38, 0xfd, 0xfd, 0x35, 0x84, 0xd1, 0x73, 0xac, 0x9b, 0xcf, 0xc9, 0xf2, 0x3f, 0x5f, 0xa8, 0x25, + 0x95, 0x4f, 0xf7, 0xa4, 0xa3, 0x71, 0xcc, 0x62, 0x90, 0xf8, 0x25, 0xf6, 0x00, 0x46, 0x23, 0x14, + 0xa2, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf4, 0x00, 0x46, 0xa3, 0x14, 0xa2, 0x00, 0x98, 0x05, + 0x94, 0xc1, 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x05, + 0x94, 0xc1, 0x39, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x12, 0x00, 0x44, 0xa3, 0x00, + 0xe0, 0x45, 0x69, 0x00, 0x30, 0x40, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x68, 0x23, 0x00, + 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x6e, 0x23, 0x94, + 0x81, 0x00, 0x98, 0x20, 0x00, 0x42, 0x23, 0x94, 0x81, 0x00, 0x98, 0xf2, 0x00, 0x40, 0xa3, 0x50, + 0xa2, 0x00, 0x98, 0x00, 0x00, 0xe6, 0x73, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, + 0x00, 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, + 0x30, 0xe7, 0x62, 0x40, 0x00, 0x66, 0x49, 0x09, 0x00, 0x60, 0xa3, 0x0c, 0x9e, 0x00, 0x02, 0x00, + 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x40, + 0x00, 0x66, 0x45, 0x20, 0x00, 0x60, 0x45, 0x60, 0x00, 0x60, 0xc9, 0x0c, 0x9e, 0x00, 0x02, 0x00, + 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x20, + 0x00, 0x42, 0x45, 0x00, 0x12, 0xe0, 0xb5, 0x58, 0xa2, 0x00, 0x9c, 0x40, 0x00, 0x66, 0x45, 0x0c, + 0x9e, 0x00, 0x02, 0xfa, 0x9c, 0xe8, 0x54, 0x98, 0x1b, 0x31, 0x10, 0x46, 0x38, 0xce, 0x34, 0xae, + 0x23, 0x2c, 0x4f, 0x0a, 0x24, 0xf1, 0x80, 0x15, 0xd3, 0x83, 0x23, 0xa5, 0x65, 0xf5, 0xec, 0xbf, + 0x7b, 0x67, 0xa4, 0x6c, 0xd0, 0x26, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, + 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x60, 0x00, 0x60, 0xc5, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x10, + 0xe6, 0x35, 0x58, 0xa2, 0x00, 0x9c, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, + 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0x30, + 0xe7, 0x62, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, + 0x56, 0xc9, 0x00, 0x00, 0x66, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x50, 0xa2, + 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0xe4, 0xa3, 0x00, 0x82, 0x04, 0xa4, + 0x00, 0x82, 0x24, 0xa4, 0x00, 0x02, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xc0, 0x63, 0x94, 0x81, + 0x00, 0x98, 0x1c, 0x00, 0x7c, 0xa3, 0x00, 0x10, 0x23, 0xf9, 0x00, 0x00, 0x40, 0x23, 0x12, 0x00, + 0x7c, 0x23, 0x00, 0x08, 0x00, 0xfd, 0x80, 0x08, 0x21, 0x7d, 0x00, 0x10, 0x23, 0xf3, 0x01, 0xe0, + 0x7d, 0x24, 0x5c, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, + 0x00, 0xfd, 0x00, 0x00, 0x21, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x78, 0xa3, 0x00, 0x0a, 0x00, 0x00, + 0xc0, 0x69, 0x00, 0x00, 0x00, 0x84, 0x54, 0x00, 0x46, 0xa3, 0x00, 0x30, 0x06, 0xf3, 0x53, 0x30, + 0x86, 0xa4, 0x00, 0x30, 0x06, 0xf3, 0x01, 0x30, 0x86, 0x24, 0x00, 0x30, 0x06, 0xf3, 0xfa, 0x40, + 0x33, 0xe1, 0xc2, 0x84, 0xb0, 0xc7, 0xf0, 0xdb, 0xa4, 0x54, 0x80, 0xf8, 0x49, 0x0c, 0x30, 0x82, + 0x86, 0x13, 0x5a, 0x7a, 0x47, 0x82, 0xc1, 0xfe, 0x24, 0xd1, 0x6c, 0x37, 0x7f, 0x1b, 0xdd, 0xa8, + 0x27, 0x80, 0x30, 0x86, 0x24, 0x00, 0x30, 0x06, 0xf5, 0x00, 0x00, 0x00, 0x84, 0x90, 0xa3, 0x00, + 0x82, 0x01, 0x06, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xed, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xc0, + 0xeb, 0x00, 0x10, 0x80, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x08, 0x4c, 0xa3, 0x20, 0x60, 0x4c, + 0x24, 0x00, 0x60, 0x7e, 0x69, 0xd4, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x02, 0x4c, + 0xa3, 0x10, 0x00, 0x44, 0x23, 0x00, 0x20, 0x04, 0xf3, 0x00, 0x61, 0x86, 0xe4, 0x20, 0x60, 0x4c, + 0x24, 0x00, 0x30, 0x7e, 0x69, 0xf0, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x80, 0x00, 0x4c, + 0xa3, 0x50, 0x00, 0x44, 0xa3, 0x00, 0x20, 0x04, 0xf3, 0x00, 0x61, 0x86, 0xe4, 0x20, 0x60, 0x4c, + 0x24, 0x00, 0x30, 0x7e, 0x69, 0x10, 0xa4, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x40, + 0x23, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x44, 0xa3, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x48, + 0xa3, 0x00, 0x00, 0x4a, 0x23, 0x00, 0x00, 0x4c, 0x23, 0x00, 0x00, 0x4e, 0xa3, 0x00, 0x00, 0x50, + 0xa3, 0x00, 0x00, 0x52, 0x23, 0x00, 0x00, 0x54, 0x23, 0x00, 0x00, 0x56, 0xa3, 0x00, 0x00, 0x58, + 0x23, 0x00, 0x00, 0x5a, 0xa3, 0x00, 0x00, 0x5c, 0xa3, 0x00, 0x00, 0x5e, 0x23, 0x00, 0x00, 0x60, + 0xa3, 0x00, 0x00, 0x62, 0x23, 0x00, 0x00, 0x64, 0x23, 0x00, 0x00, 0x66, 0xa3, 0x00, 0x00, 0x68, + 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x28, 0x00, 0x00, 0x6e, 0x23, + 0x00, 0x00, 0x70, 0x23, 0x00, 0x00, 0x72, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x76, 0x23, + 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x7c, 0x23, 0x00, 0x00, 0x7e, 0xa3, + 0x00, 0x00, 0x00, 0x84}; \ No newline at end of file diff --git a/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_1_0_1/fw_CPU.h b/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_1_0_1/fw_CPU.h index 1a70ca638..a06902508 100644 --- a/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_1_0_1/fw_CPU.h +++ b/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_1_0_1/fw_CPU.h @@ -5,1414 +5,1678 @@ /** * @brief CPU firmware version fw_v1.0.1.hex32_signed_chunks.bin for bootloader v2.0.1 */ -const uint8_t fw_CPU[] - = {0x68, 0x70, 0xb1, 0xbb, 0x03, 0x76, 0xd3, 0xeb, 0xa3, 0x1f, 0x17, 0x0b, 0xd6, 0xe9, 0xa7, 0x71, 0x9a, 0x6b, 0x56, - 0x39, 0x0d, 0xb1, 0xde, 0x1a, 0xca, 0x8e, 0x49, 0x6c, 0xa5, 0x44, 0x3d, 0x07, 0x20, 0x22, 0x52, 0xe9, 0x7b, 0x4e, - 0x73, 0x3e, 0xe8, 0xb5, 0x17, 0xc2, 0x78, 0x17, 0xb9, 0x38, 0xd0, 0xc7, 0x0d, 0x59, 0xb0, 0x8a, 0x12, 0x8e, 0x5f, - 0x73, 0xc0, 0xe8, 0x98, 0xac, 0x2c, 0x99, 0x09, 0x57, 0x63, 0xe5, 0xd8, 0x66, 0xf0, 0xa5, 0x9a, 0x74, 0xbe, 0x1e, - 0xc9, 0x13, 0x20, 0xfc, 0xfd, 0xf1, 0xdf, 0x89, 0x0f, 0x12, 0xbf, 0xbe, 0x6e, 0x3f, 0xed, 0x34, 0x15, 0xc4, 0x48, - 0xef, 0x99, 0x01, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x62, 0xa8, 0xa4, 0xc9, 0x1e, 0x08, 0x14, 0xcf, 0xde, - 0xa6, 0xfa, 0xcd, 0x68, 0xf9, 0x5f, 0x86, 0x6d, 0xa5, 0xf9, 0xa8, 0xc9, 0x2c, 0x23, 0xbd, 0x15, 0x9a, 0x49, 0x59, - 0xdd, 0x24, 0x00, 0x8a, 0xdd, 0x00, 0x00, 0xef, 0x25, 0x51, 0xc4, 0x62, 0x58, 0xf3, 0xef, 0x90, 0x39, 0x9c, 0x53, - 0x1e, 0xfb, 0x13, 0x4c, 0x20, 0x31, 0x9f, 0xa7, 0x2c, 0xa3, 0xef, 0xf8, 0x27, 0x71, 0xad, 0xbb, 0x2b, 0x6c, 0x99, - 0x5d, 0x2c, 0x99, 0x93, 0xbc, 0xc3, 0x4e, 0xad, 0x17, 0xae, 0x63, 0xbb, 0x3c, 0xf4, 0xba, 0xc2, 0x74, 0x88, 0x98, - 0xb2, 0xcc, 0xd9, 0x5d, 0xcd, 0xe5, 0x58, 0xd9, 0x90, 0x58, 0x26, 0x01, 0x68, 0x09, 0xfa, 0x20, 0x91, 0x2a, 0xd6, - 0x43, 0x1d, 0x26, 0x26, 0x85, 0xe3, 0x13, 0x01, 0xd0, 0x99, 0xe9, 0x77, 0x71, 0xf1, 0x77, 0x5c, 0x3e, 0x10, 0x96, - 0xea, 0x64, 0x7f, 0x67, 0xe6, 0x3b, 0x2c, 0xba, 0x09, 0x00, 0x04, 0x6f, 0x30, 0x00, 0x43, 0x6f, 0x30, 0x20, 0x3d, - 0x6f, 0x30, 0xe0, 0x3c, 0x6f, 0x30, 0xa0, 0x3c, 0x6f, 0x30, 0x60, 0x3c, 0x6f, 0x30, 0x20, 0x3c, 0x6f, 0x30, 0xe0, - 0x3b, 0x6f, 0x50, 0x60, 0x04, 0x6f, 0x30, 0x60, 0x3b, 0x6f, 0x30, 0x20, 0x3b, 0x6f, 0x30, 0xe0, 0x3a, 0x6f, 0x30, - 0xa0, 0x7f, 0x6f, 0x30, 0x60, 0x3a, 0x6f, 0x30, 0x20, 0x3a, 0x6f, 0x30, 0xe0, 0x39, 0x6f, 0x30, 0xa0, 0x39, 0x6f, - 0x40, 0xf0, 0x72, 0x6f, 0x30, 0x20, 0x26, 0x6f, 0x30, 0x50, 0x20, 0x6f, 0x40, 0x30, 0x22, 0x6f, 0x40, 0xf0, 0x21, - 0x6f, 0x40, 0xb0, 0x21, 0x6f, 0x30, 0xa0, 0x4c, 0x6f, 0x30, 0xa0, 0x4d, 0x6f, 0x30, 0xf0, 0x42, 0x6f, 0x40, 0x50, - 0x56, 0x6f, 0x30, 0x20, 0x4e, 0x6f, 0x20, 0x30, 0x1f, 0x6f, 0x40, 0x70, 0x0a, 0x6f, 0x30, 0xa0, 0x4e, 0x6f, 0x30, - 0x00, 0x5b, 0x6f, 0x30, 0x00, 0x3f, 0x93, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x93, 0x01, 0x00, 0x00, 0x13, - 0x02, 0x00, 0x00, 0x93, 0x02, 0x00, 0x00, 0x13, 0x03, 0x00, 0x00, 0x93, 0x03, 0x00, 0x00, 0x13, 0x04, 0x00, 0x00, - 0x93, 0x04, 0x00, 0x00, 0x13, 0x05, 0x00, 0x00, 0x93, 0x05, 0x00, 0x00, 0x13, 0x06, 0x00, 0x00, 0x93, 0x06, 0x00, - 0x00, 0x13, 0x07, 0x00, 0x00, 0x93, 0x07, 0x00, 0x00, 0x13, 0x08, 0x00, 0x00, 0x93, 0x08, 0x00, 0x00, 0x13, 0x09, - 0x00, 0x00, 0x93, 0x09, 0x00, 0x00, 0x13, 0x0a, 0x00, 0x00, 0x93, 0x0a, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0xfa, - 0x9c, 0xe5, 0xf5, 0x8c, 0x84, 0x0f, 0x0e, 0x2a, 0x87, 0xe6, 0x25, 0xcf, 0xef, 0xeb, 0x37, 0xdd, 0x0a, 0x5b, 0x91, - 0x11, 0xbf, 0x46, 0x5a, 0xbf, 0x10, 0x51, 0x9d, 0xa5, 0x6d, 0x07, 0x89, 0xcf, 0xd8, 0x04, 0x93, 0x0b, 0x00, 0x00, - 0x13, 0x0c, 0x00, 0x00, 0x93, 0x0c, 0x00, 0x00, 0x13, 0x0d, 0x00, 0x00, 0x93, 0x0d, 0x00, 0x00, 0x13, 0x0e, 0x00, - 0x00, 0x93, 0x0e, 0x00, 0x00, 0x13, 0x0f, 0x00, 0x00, 0x93, 0x0f, 0x00, 0x00, 0x97, 0x00, 0x00, 0x00, 0x93, 0x80, - 0x40, 0xf0, 0x73, 0x90, 0x50, 0x30, 0x93, 0x00, 0x00, 0x00, 0x17, 0x41, 0x10, 0x00, 0x13, 0x01, 0x41, 0xcf, 0x33, - 0x04, 0x01, 0x00, 0x17, 0x0d, 0x10, 0x00, 0x13, 0x0d, 0x8d, 0xee, 0x97, 0x4d, 0x10, 0x00, 0x93, 0x8d, 0x0d, 0xce, - 0x63, 0x57, 0xbd, 0x01, 0x23, 0x20, 0x0d, 0x00, 0x11, 0x0d, 0xe3, 0x4d, 0xbd, 0xff, 0xef, 0x00, 0xf0, 0x60, 0x73, - 0x00, 0x50, 0x10, 0xf5, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa6, 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, - 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0x07, 0xf2, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0x07, 0xf2, 0xb7, - 0x37, 0x20, 0x00, 0x23, 0x88, 0x07, 0xf2, 0x82, 0x80, 0x18, 0x41, 0xfd, 0x57, 0x63, 0x02, 0xf7, 0x06, 0x13, 0x07, - 0x45, 0x00, 0x81, 0x47, 0x13, 0x06, 0xf0, 0x07, 0x14, 0x43, 0x81, 0xea, 0x85, 0x07, 0x11, 0x07, 0xe3, 0x9c, 0xc7, - 0xfe, 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x01, 0x47, 0x93, 0x05, 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, 0x05, 0x8a, - 0x19, 0xca, 0x93, 0x05, 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, 0x05, 0x8a, 0x15, 0xc6, 0x05, 0x07, 0xe3, 0x1b, 0xb7, - 0xfe, 0x21, 0xa0, 0xfa, 0x57, 0xdb, 0x24, 0xb7, 0xdb, 0xed, 0x73, 0x27, 0xf3, 0x7d, 0xf6, 0x3d, 0xa0, 0xc4, 0x32, - 0x90, 0x77, 0x37, 0xaa, 0xce, 0xf8, 0xf0, 0x28, 0x21, 0xbd, 0x40, 0x3b, 0x80, 0xc3, 0xee, 0x3c, 0xd2, 0xb0, 0x05, - 0x05, 0x07, 0xe3, 0x11, 0xb7, 0xfe, 0x89, 0x07, 0x93, 0x06, 0x00, 0x08, 0x7d, 0x56, 0xe3, 0x85, 0xd7, 0xfc, 0x85, - 0x07, 0x13, 0x97, 0x27, 0x00, 0x2a, 0x97, 0x03, 0x27, 0xc7, 0xff, 0xe3, 0x08, 0xc7, 0xfe, 0x13, 0x05, 0x50, 0x05, - 0x82, 0x80, 0x05, 0x67, 0xaa, 0x87, 0x01, 0x17, 0x01, 0x45, 0x94, 0x43, 0x99, 0xe6, 0x13, 0x05, 0x05, 0x02, 0x91, - 0x07, 0xe3, 0x1b, 0xe5, 0xfe, 0x82, 0x80, 0x81, 0x47, 0x13, 0x06, 0x00, 0x02, 0x33, 0xd7, 0xf6, 0x00, 0x05, 0x8b, - 0x09, 0xe7, 0x85, 0x07, 0x05, 0x05, 0xe3, 0x9a, 0xc7, 0xfe, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x14, 0x20, - 0x00, 0x13, 0x04, 0x04, 0x00, 0x83, 0x46, 0x94, 0x07, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, - 0x10, 0x00, 0x13, 0x05, 0x45, 0x64, 0x13, 0x06, 0x06, 0x3d, 0x93, 0x85, 0xc5, 0x3d, 0x06, 0xc6, 0xef, 0x10, 0x30, - 0x4c, 0x03, 0x45, 0x94, 0x07, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x40, - 0x90, 0x0b, 0xef, 0x20, 0xc0, 0x58, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x00, 0xb2, 0x40, 0x41, 0x01, 0x6f, - 0x40, 0x50, 0x0c, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x05, 0x05, 0x10, 0x2a, 0x84, - 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, 0x3e, 0x06, 0xc6, 0xef, 0x10, 0x30, 0x4f, 0x37, 0x37, 0x20, 0x00, 0x13, - 0x07, 0x47, 0xf5, 0x14, 0x43, 0x85, 0x47, 0xfa, 0x59, 0xbf, 0xf4, 0xad, 0x63, 0x04, 0x46, 0x53, 0xa5, 0x44, 0xcc, - 0x31, 0x35, 0x24, 0xa1, 0x6a, 0xd3, 0x8c, 0xa1, 0x62, 0x62, 0xb6, 0x3f, 0xb7, 0x22, 0x80, 0xea, 0x6b, 0xe8, 0x81, - 0x18, 0xe2, 0x88, 0x06, 0xb3, 0x97, 0x87, 0x00, 0xb2, 0x40, 0x22, 0x44, 0x93, 0xc7, 0xf7, 0xff, 0xf5, 0x8f, 0x1c, - 0xc3, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x2a, 0x84, 0x93, 0x04, 0xa0, 0x0a, - 0xef, 0x20, 0x10, 0x76, 0x63, 0x19, 0x95, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, - 0x01, 0x82, 0x80, 0x22, 0x85, 0xef, 0x20, 0x90, 0x78, 0x22, 0x85, 0xef, 0x20, 0x30, 0x74, 0xe3, 0x03, 0x95, 0xfe, - 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, 0x3e, 0x85, 0x45, 0xef, 0x10, 0x10, 0x49, 0x13, 0x05, 0x50, 0x05, 0xd1, - 0xbf, 0x01, 0x11, 0x22, 0xcc, 0x2a, 0x84, 0x37, 0x35, 0x00, 0x08, 0x06, 0xce, 0x2e, 0xc6, 0xef, 0x30, 0x10, 0x0a, - 0x32, 0x46, 0xa2, 0x85, 0x37, 0x35, 0x00, 0x08, 0xef, 0x30, 0x50, 0x0e, 0x62, 0x44, 0xf2, 0x40, 0x37, 0x35, 0x00, - 0x08, 0x05, 0x61, 0x6f, 0x30, 0xb0, 0x0b, 0x6d, 0x71, 0x23, 0x24, 0x81, 0x10, 0x2a, 0x84, 0x0a, 0x85, 0x23, 0x26, - 0x11, 0x10, 0xef, 0x10, 0x50, 0x63, 0x0a, 0x85, 0x23, 0x00, 0x81, 0x00, 0xef, 0x20, 0xc0, 0x3e, 0x83, 0x20, 0xc1, - 0x10, 0x03, 0x24, 0x81, 0x10, 0x51, 0x61, 0x82, 0x80, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0x2e, 0xc4, 0xef, 0x20, - 0xd0, 0x1a, 0xa2, 0x45, 0x32, 0x45, 0xef, 0x20, 0xd0, 0x32, 0x2a, 0xc4, 0xef, 0x20, 0x90, 0x1b, 0xf2, 0x40, 0x22, - 0x45, 0x05, 0x61, 0x82, 0x80, 0x13, 0x01, 0x01, 0xde, 0x23, 0x2c, 0xfa, 0xc6, 0x03, 0x29, 0x4e, 0xde, 0x34, 0xe2, - 0xc9, 0xfa, 0x6b, 0x81, 0xdb, 0x3a, 0x6a, 0xb6, 0x96, 0x0e, 0xf4, 0x01, 0xb5, 0xb0, 0xb1, 0xe3, 0x75, 0xb9, 0x0d, - 0xd1, 0xfc, 0x48, 0x06, 0xdc, 0xf7, 0x60, 0x07, 0x81, 0x20, 0x2e, 0x84, 0xaa, 0x05, 0x23, 0x28, 0x21, 0x21, 0x93, - 0x85, 0x05, 0x20, 0x2a, 0x89, 0x08, 0x08, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x2a, 0x91, 0x20, 0x7d, 0x3f, 0x93, 0x07, - 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x04, 0xaa, 0x84, 0x08, 0x08, 0xcd, 0x33, 0x63, 0x00, 0x95, 0x02, 0x22, 0x85, 0xd1, - 0x3d, 0x09, 0x45, 0x83, 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, 0x41, 0x21, 0x03, 0x29, 0x01, 0x21, - 0x13, 0x01, 0x01, 0x22, 0x82, 0x80, 0x42, 0x44, 0x48, 0x08, 0x22, 0xc6, 0x25, 0x35, 0x09, 0x8c, 0x11, 0x46, 0x6c, - 0x00, 0x4a, 0x85, 0x22, 0xc6, 0xef, 0x40, 0x70, 0x7c, 0x05, 0x45, 0xc9, 0xbf, 0x01, 0x45, 0xf9, 0xb7, 0x41, 0x11, - 0x4a, 0xc0, 0x03, 0xa9, 0x05, 0x00, 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0x2e, 0x84, 0xaa, 0x84, 0xef, 0x20, 0x10, - 0x67, 0xca, 0x85, 0x26, 0x85, 0xef, 0x20, 0x70, 0x1e, 0xa6, 0x85, 0x22, 0x85, 0xef, 0x20, 0xb0, 0x28, 0x93, 0x07, - 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x02, 0x1c, 0x40, 0x63, 0x93, 0x27, 0x03, 0x93, 0x07, 0x44, 0x00, 0x7d, 0x57, 0x13, - 0x04, 0x04, 0x20, 0x94, 0x43, 0x63, 0x9b, 0xe6, 0x00, 0x91, 0x07, 0xe3, 0x9c, 0x87, 0xfe, 0xb2, 0x40, 0x22, 0x44, - 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0xc5, 0xbf, 0x13, 0x01, 0x01, 0xde, 0x23, - 0x26, 0x31, 0x21, 0x93, 0x19, 0xa5, 0x00, 0x23, 0x2a, 0x91, 0x20, 0x93, 0x84, 0x09, 0x20, 0xfa, 0x2c, 0x73, 0xd8, - 0x55, 0xaa, 0x7e, 0x1d, 0xe9, 0x05, 0x57, 0xf7, 0x39, 0x87, 0xb7, 0xf1, 0xe9, 0x81, 0xb7, 0x1d, 0x0b, 0x60, 0x90, - 0x74, 0x01, 0x6d, 0x25, 0xb4, 0x2b, 0xe5, 0xec, 0x18, 0xf2, 0x38, 0x08, 0x23, 0x2c, 0x81, 0x20, 0xa6, 0x85, 0x2a, - 0x84, 0x0a, 0x85, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x28, 0x21, 0x21, 0xfd, 0x35, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x00, - 0xf5, 0x02, 0x01, 0x45, 0x83, 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, 0x41, 0x21, 0x03, 0x29, 0x01, - 0x21, 0x83, 0x29, 0xc1, 0x20, 0x13, 0x01, 0x01, 0x22, 0x82, 0x80, 0x2a, 0x89, 0x0a, 0x85, 0xdd, 0x39, 0x63, 0x06, - 0x25, 0x01, 0x22, 0x85, 0xe5, 0x33, 0x09, 0x45, 0xd9, 0xbf, 0x02, 0x44, 0x48, 0x00, 0x89, 0x3b, 0xaa, 0x87, 0x33, - 0x06, 0xa4, 0x40, 0x0d, 0x45, 0xe3, 0x03, 0xf4, 0xfc, 0x09, 0x45, 0xe3, 0x60, 0xc4, 0xfc, 0x5c, 0x00, 0x01, 0x44, - 0x13, 0x08, 0x00, 0x02, 0x13, 0x05, 0xf0, 0x07, 0x8c, 0x43, 0x89, 0xc9, 0x81, 0x46, 0x33, 0xd7, 0xd5, 0x00, 0x05, - 0x8b, 0x05, 0xeb, 0x85, 0x06, 0xe3, 0x9b, 0x06, 0xff, 0x05, 0x04, 0x91, 0x07, 0xe3, 0x14, 0xa4, 0xfe, 0x7d, 0x16, - 0x8a, 0x85, 0x13, 0x85, 0x09, 0x40, 0x32, 0xc0, 0xf5, 0x3d, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x11, 0xf5, 0xf8, 0x8a, - 0x85, 0x26, 0x85, 0xfd, 0x35, 0x13, 0x05, 0x65, 0xf5, 0x1d, 0xa8, 0x05, 0x47, 0x33, 0x17, 0xd7, 0x00, 0x13, 0x47, - 0xf7, 0xff, 0x6d, 0x8f, 0x98, 0xc3, 0xef, 0x20, 0xc0, 0x7f, 0x18, 0x04, 0x93, 0x17, 0x24, 0x00, 0xba, 0x97, 0x83, - 0xa5, 0x47, 0xe0, 0x13, 0x05, 0x14, 0x00, 0x0a, 0x05, 0x26, 0x95, 0xef, 0x20, 0x50, 0x10, 0x2a, 0x84, 0xef, 0x20, - 0xfa, 0xbd, 0x19, 0x5d, 0x49, 0xa5, 0xda, 0x4f, 0x06, 0x0c, 0xf7, 0x78, 0xfd, 0x53, 0x5d, 0xbc, 0xcd, 0xd1, 0x76, - 0x98, 0x49, 0xe3, 0xf0, 0x8d, 0xb0, 0xae, 0xd2, 0x74, 0x74, 0x22, 0x6c, 0x53, 0x59, 0x10, 0x09, 0x80, 0x7f, 0x13, - 0x05, 0x64, 0xf5, 0x13, 0x35, 0x15, 0x00, 0x35, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x07, 0x30, 0x0c, - 0x2a, 0x84, 0x63, 0x04, 0xf5, 0x00, 0xef, 0x20, 0xc0, 0x4b, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x05, - 0x67, 0x23, 0x80, 0x87, 0x00, 0xba, 0x97, 0xf8, 0x5b, 0x19, 0xe3, 0x05, 0x47, 0xf8, 0xdb, 0xb2, 0x40, 0x22, 0x44, - 0x41, 0x01, 0x82, 0x80, 0x05, 0x66, 0x37, 0x05, 0x20, 0x00, 0x41, 0x11, 0x13, 0x06, 0xc6, 0x07, 0x81, 0x45, 0x13, - 0x05, 0x05, 0x00, 0x06, 0xc6, 0xef, 0x40, 0xb0, 0x65, 0xef, 0x20, 0x80, 0x41, 0xef, 0x40, 0x80, 0x39, 0xb2, 0x40, - 0x41, 0x01, 0x6f, 0x20, 0x00, 0x38, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x20, 0x00, 0x55, 0xef, 0x20, 0x90, 0x7f, 0xef, - 0x40, 0xa0, 0x0c, 0xef, 0x40, 0x00, 0x65, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x30, 0xe0, 0x15, 0x69, 0x71, 0x08, 0x08, - 0x23, 0x22, 0x91, 0x12, 0x23, 0x20, 0x21, 0x13, 0x23, 0x2c, 0x41, 0x11, 0x23, 0x26, 0x11, 0x12, 0x23, 0x24, 0x81, - 0x12, 0x23, 0x2e, 0x31, 0x11, 0x23, 0x2a, 0x51, 0x11, 0xef, 0x10, 0xf0, 0x39, 0x91, 0x47, 0x37, 0x39, 0x20, 0x00, - 0x23, 0x08, 0xf1, 0x00, 0x83, 0x27, 0xc9, 0xf4, 0x37, 0x1a, 0x20, 0x00, 0xb7, 0x34, 0x20, 0x00, 0x13, 0x09, 0xc9, - 0xf4, 0x13, 0x0a, 0x0a, 0x00, 0x93, 0x84, 0x84, 0xf4, 0xc5, 0xe7, 0x83, 0x27, 0x4a, 0x07, 0x09, 0x46, 0x6c, 0x00, - 0x23, 0x20, 0xf9, 0x00, 0xfa, 0xf1, 0xae, 0x16, 0x45, 0x1a, 0xc9, 0x45, 0x3f, 0x22, 0x04, 0x4e, 0x6b, 0x88, 0x02, - 0x1d, 0xc5, 0xd3, 0x95, 0xba, 0xc3, 0x14, 0xed, 0xa4, 0x46, 0x9e, 0x09, 0x95, 0xcf, 0xd6, 0x78, 0xf6, 0x18, 0xe8, - 0x09, 0x13, 0x05, 0x21, 0x01, 0xc1, 0x17, 0x3e, 0xc6, 0x23, 0xa0, 0x04, 0x00, 0xef, 0x40, 0xf0, 0x58, 0x89, 0x47, - 0xa3, 0x08, 0xf1, 0x00, 0x13, 0x04, 0xe0, 0x07, 0x93, 0x09, 0x41, 0x01, 0x03, 0x27, 0x09, 0x00, 0x94, 0x40, 0xb3, - 0x07, 0xd7, 0x40, 0x63, 0xf3, 0x87, 0x00, 0x3e, 0x84, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x5a, 0x10, 0x00, 0x37, 0x55, - 0x10, 0x00, 0xa2, 0x87, 0x93, 0x85, 0xca, 0x3f, 0x13, 0x06, 0xc6, 0x3e, 0x13, 0x05, 0x45, 0x40, 0xef, 0x10, 0x50, - 0x0c, 0x8c, 0x40, 0x83, 0x27, 0x4a, 0x07, 0x33, 0x07, 0xb4, 0x00, 0x63, 0xf7, 0xe7, 0x04, 0x8d, 0x45, 0x13, 0x85, - 0xca, 0x3f, 0xef, 0x10, 0x30, 0x12, 0x13, 0x04, 0x50, 0x05, 0xc5, 0x3c, 0xef, 0x40, 0x60, 0x2a, 0xef, 0x20, 0xa0, - 0x32, 0xef, 0x20, 0xa0, 0x29, 0x29, 0x3f, 0x83, 0x20, 0xc1, 0x12, 0x22, 0x85, 0x03, 0x24, 0x81, 0x12, 0x83, 0x24, - 0x41, 0x12, 0x03, 0x29, 0x01, 0x12, 0x83, 0x29, 0xc1, 0x11, 0x03, 0x2a, 0x81, 0x11, 0x83, 0x2a, 0x41, 0x11, 0x55, - 0x61, 0x82, 0x80, 0x13, 0x04, 0x00, 0x08, 0x93, 0x09, 0x21, 0x01, 0xb5, 0xbf, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, - 0x07, 0x00, 0x22, 0x86, 0xbe, 0x95, 0x4e, 0x85, 0xef, 0x40, 0x90, 0x4e, 0x83, 0x47, 0x11, 0x01, 0x98, 0x40, 0x22, - 0x97, 0x3e, 0x94, 0x83, 0x27, 0x09, 0x00, 0xa3, 0x08, 0x81, 0x00, 0x98, 0xc0, 0x13, 0x04, 0x50, 0x05, 0x63, 0x17, - 0xf7, 0x00, 0x89, 0x47, 0x23, 0x08, 0xf1, 0x00, 0xfa, 0x86, 0x2e, 0x0a, 0x72, 0xca, 0x02, 0xc4, 0x19, 0x01, 0x39, - 0xe4, 0x81, 0x08, 0xe3, 0x39, 0xdd, 0x8f, 0xc6, 0x5c, 0xec, 0x85, 0x7d, 0xc5, 0x2b, 0x95, 0xa8, 0xa0, 0xf1, 0xa3, - 0x6a, 0xcc, 0x9e, 0xc0, 0x0a, 0x13, 0x04, 0xa0, 0x0a, 0x08, 0x08, 0xef, 0x20, 0xe0, 0x04, 0x59, 0xbf, 0x41, 0x11, - 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x06, 0xc6, 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x20, 0xe0, 0x26, 0x85, - 0x3d, 0xb9, 0x3c, 0xef, 0x30, 0x20, 0x07, 0x41, 0x3d, 0xb2, 0x40, 0x1d, 0x65, 0x13, 0x05, 0x05, 0x6c, 0x41, 0x01, - 0x6f, 0x30, 0x00, 0x0f, 0x41, 0x11, 0x26, 0xc2, 0xae, 0x84, 0xb6, 0x85, 0x06, 0xc6, 0x22, 0xc4, 0x4a, 0xc0, 0x36, - 0x84, 0x32, 0x89, 0xef, 0x40, 0x40, 0x4f, 0x22, 0x86, 0xca, 0x85, 0x13, 0x05, 0x00, 0x02, 0xef, 0x40, 0x00, 0x58, - 0xef, 0x40, 0x60, 0x4c, 0xef, 0x40, 0xe0, 0x67, 0x93, 0x07, 0xa0, 0x0a, 0x13, 0x04, 0x50, 0x05, 0x63, 0x1a, 0xf5, - 0x00, 0x2a, 0x84, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0x00, 0x02, 0x26, 0x85, 0xef, 0x40, 0xe0, 0x50, 0xb2, 0x40, - 0x22, 0x85, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x85, 0x67, 0xc1, 0x07, 0x63, 0xee, 0xb7, - 0x02, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xae, 0x84, 0x37, 0x04, 0x20, 0x00, 0x19, 0xc5, 0x2e, 0x86, - 0xaa, 0x85, 0x13, 0x05, 0x04, 0x00, 0xef, 0x40, 0xd0, 0x42, 0x13, 0x04, 0x04, 0x00, 0x93, 0x07, 0x30, 0xfc, 0x23, - 0x00, 0xf4, 0x00, 0x85, 0x67, 0x3e, 0x94, 0x64, 0xd8, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, - 0x82, 0x80, 0x13, 0x01, 0x01, 0xdd, 0x23, 0x24, 0x81, 0x22, 0x23, 0x22, 0xfa, 0x54, 0x8d, 0x08, 0xe6, 0xc4, 0x7c, - 0xba, 0xd3, 0xc6, 0xc6, 0xba, 0x82, 0x12, 0x09, 0xe3, 0x34, 0x53, 0xf0, 0xdc, 0x14, 0x07, 0x20, 0xe4, 0x63, 0xd2, - 0x89, 0x86, 0xea, 0x9a, 0xd9, 0xc6, 0x50, 0x98, 0x0b, 0x91, 0x22, 0x23, 0x20, 0x21, 0x23, 0x23, 0x2e, 0x31, 0x21, - 0x23, 0x2c, 0x41, 0x21, 0x23, 0x2a, 0x51, 0x21, 0x23, 0x28, 0x61, 0x21, 0x23, 0x26, 0x71, 0x21, 0x23, 0x24, 0x81, - 0x21, 0x23, 0x26, 0x11, 0x22, 0x13, 0x04, 0x00, 0x20, 0x01, 0x49, 0x93, 0x04, 0xa0, 0x0a, 0x37, 0x3a, 0x20, 0x00, - 0x85, 0x4a, 0x37, 0x5b, 0x10, 0x00, 0xb7, 0x5b, 0x10, 0x00, 0x37, 0x5c, 0x10, 0x00, 0xc1, 0x49, 0xa2, 0x85, 0x0a, - 0x85, 0xb1, 0x3e, 0x63, 0x16, 0x95, 0x02, 0x0a, 0x85, 0x59, 0x32, 0x63, 0x1e, 0x95, 0x04, 0x13, 0x07, 0x4a, 0xf5, - 0x14, 0x43, 0xb3, 0x97, 0x2a, 0x01, 0x13, 0x06, 0x8b, 0x40, 0xd5, 0x8f, 0x93, 0x85, 0x4b, 0x3e, 0xca, 0x86, 0x13, - 0x05, 0x4c, 0x64, 0x1c, 0xc3, 0xef, 0x10, 0xe0, 0x6e, 0x05, 0x09, 0x13, 0x04, 0x04, 0x40, 0xe3, 0x14, 0x39, 0xfd, - 0x83, 0x20, 0xc1, 0x22, 0x03, 0x24, 0x81, 0x22, 0x83, 0x24, 0x41, 0x22, 0x03, 0x29, 0x01, 0x22, 0x83, 0x29, 0xc1, - 0x21, 0x03, 0x2a, 0x81, 0x21, 0x83, 0x2a, 0x41, 0x21, 0x03, 0x2b, 0x01, 0x21, 0x83, 0x2b, 0xc1, 0x20, 0x03, 0x2c, - 0x81, 0x20, 0x13, 0x01, 0x01, 0x23, 0x82, 0x80, 0x93, 0x05, 0x04, 0x20, 0x0a, 0x85, 0xc5, 0x3c, 0xe3, 0x10, 0x95, - 0xfc, 0x0a, 0x85, 0xef, 0xf0, 0xbf, 0x91, 0xe3, 0x1b, 0x95, 0xfa, 0x22, 0x85, 0xef, 0x20, 0x10, 0x1f, 0x8a, 0x85, - 0x22, 0x85, 0xef, 0x20, 0x70, 0x06, 0xa2, 0x85, 0x0a, 0x85, 0xf9, 0x34, 0xe3, 0x1f, 0x95, 0xf8, 0xfa, 0x3e, 0x69, - 0x40, 0xa9, 0xce, 0x29, 0x6c, 0x9d, 0x5e, 0x24, 0xaa, 0x13, 0x12, 0x1f, 0x4a, 0x1d, 0x17, 0x21, 0x1f, 0xa9, 0xc5, - 0xbb, 0x64, 0xbe, 0x0a, 0x52, 0xd8, 0x35, 0xeb, 0x84, 0xa8, 0xd1, 0x70, 0x0c, 0x0a, 0x85, 0xef, 0xf0, 0x9f, 0x8f, - 0xe3, 0x0a, 0x95, 0xf6, 0x41, 0xbf, 0xb7, 0x05, 0x00, 0x80, 0x37, 0x55, 0x10, 0x00, 0x86, 0x87, 0x6d, 0x71, 0xbe, - 0x95, 0x13, 0x05, 0x45, 0x41, 0x23, 0x26, 0x11, 0x10, 0xef, 0x10, 0x80, 0x6d, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, - 0x87, 0xf2, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x1e, 0xf7, 0x02, 0x37, 0x15, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x9a, 0xef, - 0x10, 0xf0, 0x5f, 0x13, 0x05, 0xc0, 0x0f, 0xef, 0x10, 0xa0, 0x5a, 0x0a, 0x85, 0xef, 0x10, 0x70, 0x09, 0x93, 0x07, - 0xf0, 0x07, 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x00, 0x23, 0x00, 0xf1, 0x00, 0xef, 0x10, 0x00, 0x54, 0xa3, - 0x00, 0xa1, 0x00, 0x0a, 0x85, 0xef, 0x10, 0x70, 0x60, 0x05, 0x45, 0xef, 0x40, 0x00, 0x67, 0xef, 0x40, 0x00, 0x66, - 0xd5, 0x33, 0xef, 0x10, 0x50, 0x2d, 0xf5, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0x40, 0x60, 0x4c, 0x93, - 0x07, 0x00, 0x08, 0x63, 0xf3, 0xa7, 0x00, 0xad, 0x3f, 0x2a, 0x84, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0x50, 0x7e, - 0xb7, 0x17, 0x20, 0x00, 0xb2, 0x40, 0x23, 0xaa, 0x87, 0x06, 0x22, 0x44, 0x13, 0x05, 0x30, 0x0c, 0x41, 0x01, 0x82, - 0x80, 0x93, 0x07, 0xf0, 0x17, 0x63, 0xf5, 0xa7, 0x00, 0x41, 0x11, 0x06, 0xc6, 0xb9, 0x37, 0x6f, 0x10, 0xb0, 0x3e, - 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x4a, 0xc0, 0x2e, 0x84, 0x06, 0xc6, 0xaa, 0x84, 0xc5, 0x37, 0x61, 0x8d, 0x13, - 0x09, 0xfa, 0x7c, 0x26, 0x5d, 0xf8, 0x44, 0x1b, 0xef, 0x93, 0x9f, 0xcb, 0x8c, 0xb2, 0xdc, 0xfb, 0xf9, 0x24, 0xc8, - 0xc5, 0x20, 0x3e, 0xf7, 0xd6, 0x32, 0x8d, 0x5d, 0xaa, 0x96, 0x88, 0x95, 0xf9, 0x54, 0xfd, 0x48, 0x0d, 0x50, 0x05, - 0x19, 0xc1, 0x13, 0x09, 0xa0, 0x0a, 0x26, 0x85, 0xc1, 0x3f, 0x69, 0x8c, 0x13, 0x05, 0xa0, 0x0a, 0x19, 0xe0, 0x13, - 0x05, 0x50, 0x05, 0x63, 0x03, 0x25, 0x01, 0x21, 0x3f, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, - 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x8d, 0x47, 0x63, 0xf3, 0xa7, 0x00, 0x01, 0x37, 0x89, 0x67, 0x93, 0x87, 0x07, - 0xbf, 0x0a, 0x05, 0x3e, 0x95, 0xef, 0x30, 0xe0, 0x02, 0xaa, 0x87, 0x13, 0x07, 0xf0, 0x0f, 0x55, 0x45, 0x63, 0x89, - 0xe7, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x59, 0x45, 0x63, 0x94, 0xe7, 0x00, 0x13, 0x05, 0x30, 0x0c, 0xb2, 0x40, 0x41, - 0x01, 0x82, 0x80, 0x21, 0x71, 0x23, 0x2c, 0x81, 0x1a, 0x2a, 0x84, 0x08, 0x09, 0x23, 0x2e, 0x11, 0x1a, 0x23, 0x2a, - 0x91, 0x1a, 0x23, 0x28, 0x21, 0x1b, 0x23, 0x26, 0x31, 0x1b, 0x23, 0x24, 0x41, 0x1b, 0x23, 0x22, 0x51, 0x1b, 0x23, - 0x20, 0x61, 0x1b, 0x23, 0x2e, 0x71, 0x19, 0x23, 0x2c, 0x81, 0x19, 0x23, 0x2a, 0x91, 0x19, 0xef, 0x10, 0x40, 0x77, - 0x83, 0x47, 0x04, 0x00, 0x05, 0x47, 0x23, 0x18, 0xe1, 0x08, 0xc1, 0x46, 0x63, 0x80, 0xd7, 0x46, 0x63, 0xee, 0xf6, - 0x02, 0x91, 0x46, 0x63, 0x88, 0xd7, 0x34, 0x63, 0xe1, 0xf6, 0x02, 0x63, 0x86, 0xe7, 0x06, 0x09, 0x47, 0x63, 0x81, - 0xe7, 0x0e, 0x93, 0x07, 0xe0, 0x07, 0x23, 0x08, 0xf1, 0x08, 0x08, 0x09, 0xef, 0x10, 0xd0, 0x4c, 0x93, 0x07, 0x50, - 0x05, 0x99, 0xa1, 0x21, 0x47, 0xfa, 0xc2, 0x50, 0xe2, 0x87, 0xc6, 0x56, 0xaa, 0x46, 0x98, 0xc9, 0x9c, 0x66, 0x12, - 0xce, 0x5b, 0x95, 0xae, 0x41, 0x9c, 0xe1, 0x9c, 0xee, 0xe2, 0x06, 0x59, 0x26, 0xfe, 0xd7, 0x3d, 0x69, 0x51, 0x8f, - 0x20, 0x0e, 0xe3, 0x95, 0xe7, 0xfe, 0x83, 0x47, 0x14, 0x00, 0xd1, 0xeb, 0x4d, 0x31, 0x39, 0xa9, 0x93, 0x06, 0x20, - 0x0a, 0x63, 0x85, 0xd7, 0x4c, 0x93, 0x06, 0x30, 0x0b, 0x63, 0x82, 0xd7, 0x46, 0x93, 0x06, 0x00, 0x02, 0xe3, 0x94, - 0xd7, 0xfc, 0x83, 0x47, 0x14, 0x00, 0x63, 0x99, 0xe7, 0x06, 0x03, 0x47, 0x24, 0x00, 0x95, 0x47, 0x63, 0x14, 0xf7, - 0x06, 0x85, 0x45, 0x61, 0x45, 0xe1, 0x3d, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x09, 0xf5, 0x42, 0x13, 0x04, 0x80, 0xf8, - 0x7d, 0xa0, 0x03, 0x47, 0x14, 0x00, 0x89, 0x47, 0x63, 0x15, 0xf7, 0x04, 0x83, 0x47, 0x24, 0x00, 0x63, 0x8a, 0xe7, - 0x04, 0x63, 0x6b, 0xf7, 0x02, 0xa1, 0xe3, 0x83, 0x45, 0x34, 0x00, 0xf5, 0x47, 0x63, 0xe9, 0xb7, 0x02, 0x9e, 0x05, - 0x13, 0x06, 0x00, 0x08, 0x93, 0x85, 0x05, 0x10, 0x13, 0x05, 0x21, 0x09, 0xef, 0x20, 0x30, 0x6d, 0x13, 0x04, 0x00, - 0x08, 0x08, 0x09, 0xa3, 0x08, 0x81, 0x08, 0xef, 0x10, 0x70, 0x43, 0x93, 0x07, 0xa0, 0x0a, 0x45, 0xae, 0x13, 0x05, - 0x80, 0x1e, 0x63, 0x8d, 0xd7, 0x00, 0x13, 0x04, 0x10, 0xf8, 0xa1, 0xa8, 0x89, 0x65, 0x13, 0x06, 0x00, 0x08, 0x93, - 0x85, 0x05, 0x90, 0xf1, 0xb7, 0x13, 0x05, 0x00, 0x1f, 0xef, 0x10, 0x90, 0x24, 0x2a, 0xc6, 0x11, 0x46, 0x6c, 0x00, - 0x13, 0x05, 0x21, 0x09, 0xef, 0x40, 0x30, 0x0a, 0x11, 0x44, 0x7d, 0xbf, 0x83, 0x44, 0x14, 0x00, 0xc5, 0x36, 0x93, - 0x07, 0x10, 0x02, 0xe3, 0x95, 0xf4, 0xfc, 0xef, 0x10, 0xfa, 0x38, 0xbf, 0x38, 0x42, 0x43, 0x1e, 0xae, 0xfb, 0xb2, - 0xbd, 0xd1, 0x41, 0xd6, 0x50, 0x6d, 0x7f, 0x57, 0xac, 0x3e, 0x30, 0x88, 0x61, 0x82, 0x7f, 0xa8, 0x1e, 0xe6, 0xb8, - 0xb2, 0x1d, 0xba, 0x72, 0xf8, 0x0e, 0x10, 0x7d, 0xef, 0x20, 0x90, 0x27, 0xef, 0x30, 0x90, 0x38, 0xef, 0x40, 0x60, - 0x07, 0x03, 0x45, 0x24, 0x02, 0xa5, 0x35, 0x93, 0x07, 0x30, 0x0c, 0x63, 0x0b, 0xf5, 0x02, 0x13, 0x04, 0x70, 0xf8, - 0xb3, 0x06, 0x80, 0x40, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0xf6, 0xf6, - 0x0f, 0x13, 0x06, 0x86, 0x42, 0x93, 0x85, 0x45, 0x41, 0x13, 0x05, 0x45, 0x64, 0x23, 0x08, 0xd1, 0x08, 0xef, 0x10, - 0x80, 0x3b, 0xa3, 0x08, 0x01, 0x08, 0xf9, 0xb5, 0x83, 0x44, 0x24, 0x02, 0x19, 0x34, 0x8d, 0x47, 0xe3, 0xe3, 0x97, - 0xfc, 0x13, 0x06, 0x10, 0x08, 0x81, 0x45, 0x68, 0x00, 0xef, 0x40, 0x50, 0x06, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, - 0x24, 0x00, 0x13, 0x05, 0xd1, 0x00, 0x23, 0x06, 0x91, 0x00, 0xef, 0x40, 0x50, 0x01, 0xef, 0x40, 0x60, 0x00, 0x37, - 0x25, 0x00, 0x08, 0xef, 0x30, 0x80, 0x01, 0x81, 0x46, 0x01, 0x46, 0x93, 0x05, 0xd1, 0x02, 0x45, 0x45, 0x85, 0x3e, - 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x13, 0xf5, 0xf8, 0x81, 0x45, 0x68, 0x00, 0xef, 0x30, 0x50, 0x2f, 0x93, 0x07, 0xa0, - 0x0a, 0x2a, 0x89, 0xe3, 0x1a, 0xf5, 0xf6, 0x93, 0x06, 0x00, 0x02, 0x13, 0x06, 0xd1, 0x00, 0x93, 0x05, 0xd1, 0x04, - 0x49, 0x45, 0x99, 0x36, 0xaa, 0x84, 0xe3, 0x1f, 0x25, 0xf5, 0x85, 0x45, 0x68, 0x00, 0xef, 0x30, 0xd0, 0x2c, 0x2a, - 0x89, 0xe3, 0x18, 0x95, 0xf4, 0x83, 0x47, 0xc1, 0x00, 0x85, 0x46, 0x13, 0x06, 0xfa, 0xf5, 0x53, 0x51, 0x24, 0x0b, - 0xd3, 0xb5, 0x0a, 0xb7, 0x01, 0x6b, 0x74, 0x3d, 0x7f, 0xf5, 0x00, 0x28, 0x14, 0x8f, 0xcc, 0x90, 0x4b, 0x85, 0xce, - 0x81, 0xe4, 0x59, 0x41, 0x71, 0xfb, 0xad, 0x60, 0xd0, 0x0f, 0xb1, 0x00, 0x93, 0x05, 0xd1, 0x04, 0x4d, 0x45, 0xa3, - 0x05, 0xf1, 0x00, 0x31, 0x3e, 0xaa, 0x84, 0xe3, 0x1a, 0x25, 0xf3, 0x89, 0x45, 0x68, 0x00, 0xef, 0x30, 0x30, 0x2a, - 0x2a, 0x89, 0xe3, 0x13, 0x95, 0xf2, 0x81, 0x46, 0x01, 0x46, 0x93, 0x05, 0xd1, 0x04, 0x51, 0x45, 0xf5, 0x3c, 0xaa, - 0x84, 0xe3, 0x1a, 0x25, 0xf1, 0x8d, 0x45, 0x68, 0x00, 0xef, 0x30, 0x30, 0x28, 0x2a, 0x89, 0xe3, 0x13, 0x95, 0xf0, - 0x91, 0x45, 0x68, 0x00, 0xef, 0x30, 0x50, 0x27, 0xaa, 0x84, 0xe3, 0x1c, 0x25, 0xef, 0x95, 0x45, 0x68, 0x00, 0xef, - 0x30, 0x70, 0x26, 0xe3, 0x16, 0x95, 0xee, 0xb7, 0x19, 0x20, 0x00, 0x13, 0x85, 0x09, 0x02, 0xef, 0x30, 0x70, 0x29, - 0xb7, 0x14, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0xd1, 0x02, 0x13, 0x85, 0x04, 0x03, 0xef, 0x40, 0xa0, - 0x73, 0x37, 0x15, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0xd1, 0x06, 0x13, 0x05, 0x05, 0x05, 0xef, 0x40, - 0x60, 0x72, 0x03, 0x49, 0x24, 0x02, 0x8d, 0x47, 0x4e, 0x84, 0x63, 0xf3, 0x27, 0x01, 0x01, 0x39, 0x37, 0x5c, 0x10, - 0x00, 0xef, 0x10, 0x10, 0x49, 0x81, 0x4c, 0x13, 0x0c, 0x8c, 0x58, 0x8d, 0x49, 0xfd, 0x5a, 0x13, 0x0a, 0x00, 0x0f, - 0x41, 0x6b, 0xb7, 0x0b, 0x00, 0x01, 0x03, 0x25, 0x0c, 0x00, 0x51, 0x81, 0x49, 0x39, 0x03, 0x27, 0x0c, 0x00, 0x93, - 0x57, 0x07, 0x01, 0xbd, 0x8b, 0x63, 0xe8, 0xf9, 0x00, 0x8e, 0x07, 0xb3, 0x97, 0xfa, 0x00, 0x93, 0xc7, 0xfa, 0x81, - 0x1f, 0x4d, 0x25, 0xcd, 0x61, 0x74, 0xa3, 0x01, 0xb9, 0x19, 0x8a, 0xd6, 0x7c, 0xcb, 0x09, 0x01, 0xb4, 0x53, 0x17, - 0x82, 0xe9, 0x76, 0xc7, 0x70, 0x48, 0x00, 0x27, 0x53, 0x08, 0x25, 0x4a, 0xa8, 0x10, 0xf7, 0xff, 0x7d, 0x8d, 0x83, - 0x46, 0x1c, 0x00, 0x33, 0x55, 0x25, 0x01, 0x93, 0x77, 0x15, 0x00, 0x93, 0xf6, 0x06, 0x0f, 0x63, 0x96, 0x46, 0x07, - 0x99, 0xc3, 0x93, 0x07, 0xf0, 0x0f, 0xbd, 0x65, 0xf9, 0x8d, 0x21, 0x83, 0x3d, 0x8b, 0x22, 0x07, 0x4d, 0x8f, 0x83, - 0x45, 0x0c, 0x00, 0xc2, 0x07, 0x66, 0x85, 0xd9, 0x8d, 0xdd, 0x8d, 0xef, 0x10, 0xd0, 0x43, 0x83, 0x47, 0x4c, 0x00, - 0x11, 0x0c, 0x85, 0x0c, 0xc5, 0xf3, 0xef, 0x10, 0x90, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x13, - 0x06, 0x00, 0x02, 0x93, 0x85, 0x04, 0x03, 0x13, 0x05, 0x21, 0x09, 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x40, 0xa0, 0x67, - 0x93, 0x05, 0x04, 0x02, 0x41, 0x46, 0x13, 0x05, 0x21, 0x0b, 0xef, 0x40, 0xc0, 0x66, 0xef, 0x30, 0xf0, 0x6b, 0x13, - 0x04, 0x00, 0x03, 0xef, 0xf0, 0x7f, 0x85, 0xbd, 0xbb, 0x93, 0x76, 0x05, 0x10, 0x99, 0xc2, 0x93, 0xe7, 0x27, 0x00, - 0xb3, 0x76, 0x65, 0x01, 0x99, 0xc2, 0x93, 0xe7, 0x47, 0x00, 0x33, 0x75, 0x75, 0x01, 0x59, 0xd1, 0x93, 0xe7, 0x87, - 0x00, 0x41, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0xc7, 0xf3, 0x93, 0x07, 0xa0, 0x0a, 0x83, 0x44, 0x14, 0x00, - 0x63, 0x14, 0xf7, 0x0e, 0x91, 0xe4, 0x13, 0x04, 0x10, 0xf8, 0xef, 0xf0, 0xbf, 0x96, 0x4d, 0xbb, 0xb7, 0x39, 0x20, - 0x00, 0x83, 0xa7, 0x89, 0xf3, 0x93, 0x89, 0x89, 0xf3, 0xad, 0xcb, 0x09, 0x04, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, - 0x49, 0xf3, 0xfa, 0x72, 0x9a, 0x0e, 0x9c, 0x42, 0x00, 0x4f, 0x8e, 0x99, 0x54, 0xe9, 0x2d, 0x4a, 0xff, 0x60, 0xcd, - 0x2f, 0xac, 0x96, 0xa7, 0x1c, 0xe9, 0x43, 0xb3, 0xa8, 0x47, 0xea, 0x15, 0xe8, 0x82, 0xf7, 0x8e, 0x80, 0x11, 0x83, - 0x26, 0x09, 0x00, 0x03, 0xa7, 0x09, 0x00, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, - 0x13, 0x05, 0x45, 0x64, 0xa6, 0x96, 0x13, 0x06, 0xc6, 0x41, 0x93, 0x85, 0xc5, 0x3f, 0xef, 0x10, 0x20, 0x15, 0x03, - 0x25, 0x09, 0x00, 0x83, 0xa7, 0x09, 0x00, 0x33, 0x87, 0xa4, 0x00, 0xe3, 0xe6, 0xe7, 0xfa, 0x85, 0x67, 0x93, 0x87, - 0x07, 0x02, 0xe3, 0xe1, 0xe7, 0xfa, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x26, 0x86, 0x3e, 0x95, 0xa2, - 0x85, 0xef, 0x40, 0x40, 0x5b, 0x83, 0x27, 0x09, 0x00, 0xbe, 0x94, 0x83, 0xa7, 0x09, 0x00, 0x23, 0x20, 0x99, 0x00, - 0xbd, 0xe3, 0x75, 0x54, 0x15, 0xbb, 0x89, 0x47, 0xe3, 0xfb, 0x97, 0xf6, 0x03, 0x49, 0x34, 0x00, 0x83, 0x47, 0x24, - 0x00, 0xf9, 0x14, 0x22, 0x09, 0x3e, 0x99, 0x85, 0x67, 0x93, 0x06, 0xf9, 0xff, 0x13, 0x87, 0xf7, 0x00, 0x11, 0x04, - 0xe3, 0x6c, 0xd7, 0xf4, 0x37, 0x0a, 0x20, 0x00, 0x13, 0x0a, 0x0a, 0x00, 0x3e, 0x9a, 0x41, 0x09, 0x93, 0x07, 0xf0, - 0x07, 0xa3, 0x0c, 0xfa, 0x06, 0x23, 0xa0, 0x29, 0x01, 0xef, 0x10, 0x50, 0x4a, 0xef, 0x20, 0xc0, 0x74, 0xef, 0x30, - 0xd0, 0x05, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x28, 0x2a, 0x07, 0x23, 0x2a, 0x0a, 0x06, 0x23, 0xaa, 0x07, 0xf2, 0x2d, - 0xbf, 0x13, 0x04, 0x60, 0xf8, 0x39, 0xbf, 0xe3, 0x9e, 0xf4, 0xf8, 0x01, 0x44, 0xa1, 0xb9, 0x83, 0x47, 0x14, 0x00, - 0xe3, 0x95, 0x07, 0xc6, 0xef, 0x10, 0xfa, 0x58, 0xea, 0x71, 0xc5, 0xc3, 0xe9, 0x10, 0x85, 0x12, 0x25, 0x54, 0x01, - 0xb8, 0xf5, 0x82, 0x91, 0xb1, 0x65, 0xbe, 0xdb, 0xb9, 0xfd, 0xeb, 0x77, 0xcb, 0xa1, 0x6c, 0xec, 0x14, 0x54, 0x92, - 0xdc, 0x58, 0x12, 0x30, 0x15, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x0f, 0x05, 0xc4, 0x83, 0x20, 0xc1, 0x1b, 0x03, 0x24, - 0x81, 0x1b, 0x83, 0x24, 0x41, 0x1b, 0x03, 0x29, 0x01, 0x1b, 0x83, 0x29, 0xc1, 0x1a, 0x03, 0x2a, 0x81, 0x1a, 0x83, - 0x2a, 0x41, 0x1a, 0x03, 0x2b, 0x01, 0x1a, 0x83, 0x2b, 0xc1, 0x19, 0x03, 0x2c, 0x81, 0x19, 0x83, 0x2c, 0x41, 0x19, - 0x3e, 0x85, 0x39, 0x61, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa2, 0xa7, 0xf4, 0x7d, 0xb7, 0x83, 0x46, 0x14, - 0x00, 0xe3, 0x9d, 0xe6, 0xc0, 0x83, 0x47, 0x24, 0x00, 0x63, 0x8a, 0xd7, 0x02, 0x0d, 0x47, 0xe3, 0x96, 0xe7, 0xc0, - 0xa1, 0x45, 0x01, 0x45, 0xb5, 0x3c, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0xe3, 0x13, 0xf5, 0xba, 0xb7, 0xb5, 0xb5, - 0x61, 0x93, 0x85, 0x55, 0x49, 0x13, 0x05, 0x80, 0x1f, 0xef, 0x10, 0x40, 0x6b, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa6, - 0x87, 0xf2, 0xbd, 0xb7, 0xb7, 0x15, 0x78, 0x4a, 0x93, 0x85, 0x95, 0x21, 0x13, 0x05, 0x80, 0x1f, 0xef, 0x10, 0xa0, - 0x69, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf2, 0x81, 0xbf, 0xb7, 0x37, 0x20, 0x00, - 0x03, 0xa7, 0x87, 0xf2, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1f, 0xf7, 0xb4, 0x83, 0x47, 0x14, 0x00, 0xe3, 0x96, 0x07, - 0xba, 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x09, 0xef, 0x00, 0x50, 0x6f, 0x2a, 0x84, 0xe3, 0x51, 0x05, 0xb8, - 0xcd, 0xbe, 0x41, 0x11, 0x05, 0x45, 0x06, 0xc6, 0xef, 0x40, 0xfa, 0x86, 0xf7, 0xda, 0x79, 0x19, 0xcd, 0xd6, 0x8d, - 0x4b, 0xfc, 0xee, 0x71, 0x80, 0x8a, 0xb4, 0x7e, 0xc1, 0x4c, 0x54, 0x2b, 0x0b, 0xd3, 0x52, 0x13, 0xb4, 0x0a, 0xdc, - 0x9f, 0x91, 0x1e, 0xd8, 0x55, 0x30, 0x13, 0x20, 0x02, 0xb2, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, - 0x23, 0xa0, 0xe7, 0xf4, 0x41, 0x01, 0x82, 0x80, 0x31, 0x71, 0x22, 0xdd, 0x37, 0x34, 0x20, 0x00, 0x93, 0x07, 0x50, - 0x05, 0x06, 0xdf, 0x4a, 0xd9, 0x52, 0xd5, 0x56, 0xd3, 0x62, 0xcd, 0x26, 0xdb, 0x4e, 0xd7, 0x5a, 0xd1, 0x5e, 0xcf, - 0x66, 0xcb, 0x6a, 0xc9, 0x6e, 0xc7, 0xb7, 0x3a, 0x20, 0x00, 0x37, 0x3a, 0x20, 0x00, 0x37, 0x39, 0x20, 0x00, 0x13, - 0x04, 0x84, 0xf2, 0x23, 0xa0, 0xfa, 0xf4, 0x23, 0x26, 0xfa, 0xf2, 0x23, 0x22, 0xf9, 0xf4, 0x1c, 0xc0, 0xef, 0x10, - 0x60, 0x3d, 0xef, 0x10, 0xc0, 0x55, 0x13, 0x87, 0x0a, 0xf4, 0x3a, 0xc8, 0x13, 0x07, 0xca, 0xf2, 0x3a, 0xca, 0x13, - 0x07, 0x49, 0xf4, 0x93, 0x07, 0xa0, 0x0a, 0x3a, 0xc6, 0x37, 0x5c, 0x10, 0x00, 0x85, 0x45, 0x63, 0x0a, 0xf5, 0x00, - 0x13, 0x05, 0x4c, 0x41, 0xef, 0x00, 0x90, 0x7b, 0xef, 0x10, 0x80, 0x4f, 0xef, 0xf0, 0x3f, 0x8c, 0x41, 0x45, 0xef, - 0xf0, 0x5f, 0x97, 0x08, 0xc0, 0xb7, 0x07, 0x01, 0x02, 0x80, 0x57, 0x98, 0x5b, 0x29, 0x45, 0x59, 0x8c, 0x98, 0x5f, - 0x59, 0x8c, 0x13, 0x77, 0xf4, 0x87, 0x98, 0xd7, 0x98, 0xdb, 0x98, 0xdf, 0xd8, 0x43, 0x13, 0x67, 0x87, 0x00, 0xd8, - 0xc3, 0xef, 0x10, 0x00, 0x38, 0xef, 0x30, 0x30, 0x22, 0x13, 0x75, 0x05, 0x78, 0x11, 0xc5, 0x13, 0x05, 0x00, 0x78, - 0x81, 0x45, 0xef, 0x30, 0x90, 0x1a, 0xb7, 0x07, 0x01, 0x02, 0x80, 0xd7, 0x80, 0xdb, 0xfa, 0x0a, 0x6d, 0x3a, 0xa3, - 0xdb, 0xe7, 0x9a, 0xb0, 0xfa, 0x32, 0x67, 0x83, 0x8f, 0x4c, 0xed, 0xea, 0x46, 0xa4, 0x1d, 0x79, 0x17, 0x1b, 0x11, - 0x8e, 0x3f, 0xcb, 0xe0, 0x37, 0x67, 0xed, 0xfe, 0xbf, 0x08, 0x14, 0x37, 0x15, 0x10, 0x00, 0x80, 0xdf, 0x13, 0x05, - 0xc5, 0x9a, 0xef, 0x10, 0xa0, 0x69, 0x37, 0x56, 0x10, 0x00, 0x37, 0x59, 0x10, 0x00, 0x81, 0x47, 0x01, 0x47, 0x85, - 0x46, 0x13, 0x06, 0x06, 0x43, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x50, 0x6c, 0xef, 0x30, - 0x50, 0x1e, 0x93, 0x07, 0x50, 0x05, 0x63, 0x1e, 0xf5, 0x00, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, - 0x06, 0x46, 0x44, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x45, 0x40, 0xef, 0x00, 0x10, 0x6a, 0xef, 0x20, 0xa0, 0x2f, - 0x51, 0x45, 0xef, 0x10, 0xc0, 0x4b, 0x1d, 0x89, 0xef, 0x20, 0xc0, 0x2f, 0xef, 0x20, 0xa0, 0x03, 0xef, 0x20, 0x10, - 0x03, 0xef, 0x20, 0x30, 0x31, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0xb0, 0x31, 0x11, 0x46, 0x6c, 0x10, 0x37, 0x35, - 0x00, 0x08, 0xef, 0x20, 0xf0, 0x35, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0xb0, 0x33, 0x32, 0x55, 0xc1, 0x7a, 0x37, - 0x0b, 0x01, 0xff, 0xb7, 0x0b, 0x00, 0x01, 0xef, 0x20, 0x70, 0x22, 0x05, 0x64, 0x01, 0x4a, 0x93, 0x8a, 0xfa, 0x0f, - 0x7d, 0x1b, 0xfd, 0x1b, 0x13, 0x0d, 0x00, 0x18, 0x52, 0x85, 0xef, 0xf0, 0x1f, 0x87, 0xaa, 0x8c, 0x22, 0x85, 0xef, - 0x20, 0xd0, 0x0f, 0x93, 0xf9, 0x09, 0xf0, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, 0x44, 0x00, 0xef, 0x20, 0xd0, 0x0e, - 0x22, 0x05, 0xb3, 0xf9, 0x59, 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, 0x84, 0x00, 0xef, 0x20, 0xb0, 0x0d, 0xfa, - 0x9a, 0x3e, 0xdc, 0x7f, 0x1d, 0xf9, 0x15, 0x5a, 0xd7, 0x9c, 0x7e, 0x6d, 0x2c, 0xc4, 0x65, 0xf0, 0x94, 0x00, 0x42, - 0xd2, 0x44, 0x5f, 0xbf, 0x87, 0xab, 0x27, 0xd8, 0xab, 0x71, 0xe7, 0xd7, 0x8a, 0xe0, 0x14, 0x42, 0x05, 0xb3, 0xf9, - 0x69, 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, 0xc4, 0x00, 0xef, 0x20, 0x90, 0x0c, 0x62, 0x05, 0xb3, 0xf9, 0x79, - 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x93, 0xc7, 0xf9, 0xff, 0x33, 0xf5, 0x97, 0x01, 0xe3, 0x1b, 0x05, 0xea, 0x11, 0x0a, - 0x41, 0x04, 0xe3, 0x12, 0xaa, 0xfb, 0x37, 0x55, 0x10, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x13, - 0x05, 0x85, 0x5e, 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x10, 0xf0, 0x1a, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x40, 0x05, - 0x93, 0x85, 0x45, 0x53, 0x68, 0x10, 0xef, 0x40, 0xc0, 0x24, 0x60, 0x10, 0x48, 0x40, 0x01, 0xc5, 0xef, 0x20, 0xa0, - 0x7f, 0x48, 0xc0, 0x31, 0x04, 0x1c, 0x01, 0xe3, 0x99, 0x87, 0xfe, 0x37, 0x55, 0x10, 0x00, 0x1d, 0x46, 0x6c, 0x10, - 0x13, 0x05, 0xc5, 0x5f, 0xef, 0x20, 0x40, 0x42, 0xef, 0xf0, 0x0f, 0xe3, 0x05, 0x45, 0xef, 0x10, 0xd0, 0x02, 0xef, - 0x30, 0xa0, 0x4e, 0xef, 0x30, 0x50, 0x21, 0x01, 0x45, 0xef, 0x30, 0xf0, 0x5d, 0xb7, 0x0a, 0x20, 0x00, 0x93, 0x87, - 0x0a, 0x00, 0x05, 0x6b, 0xb3, 0x8b, 0x67, 0x01, 0xb7, 0x17, 0x20, 0x00, 0x13, 0x8a, 0xc7, 0x07, 0xef, 0x10, 0x40, - 0x66, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x87, 0xf3, 0x63, 0x82, 0x07, 0x10, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, - 0x47, 0xf3, 0x63, 0x9c, 0xe7, 0x0e, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xc7, 0x07, 0xf3, 0x93, 0x87, 0x07, 0xf3, 0x3e, - 0xcc, 0xe3, 0x1d, 0xfa, 0x09, 0xd6, 0xcc, 0x36, 0xb2, 0x10, 0xd6, 0x5d, 0x86, 0xce, 0xa4, 0x0a, 0x41, 0x3d, 0x63, - 0x5f, 0x30, 0x52, 0x3e, 0x42, 0x3f, 0x54, 0x30, 0x74, 0x12, 0xcf, 0x11, 0xf8, 0x4e, 0xc0, 0x1e, 0x3e, 0xb8, 0x15, - 0x07, 0x36, 0x03, 0xa6, 0x0b, 0x07, 0x93, 0x07, 0xf0, 0x07, 0xb7, 0x19, 0x20, 0x00, 0xa3, 0x8c, 0xfb, 0x06, 0xc1, - 0x4c, 0x13, 0x8d, 0x0a, 0x00, 0x93, 0x89, 0x09, 0x00, 0x63, 0xfe, 0xcc, 0x0a, 0x13, 0x04, 0x06, 0xff, 0xef, 0x10, - 0x60, 0x72, 0x01, 0x45, 0xef, 0x30, 0x60, 0x4f, 0x22, 0x86, 0x63, 0xf3, 0x8c, 0x00, 0x41, 0x46, 0x93, 0x85, 0x0a, - 0x00, 0x68, 0x10, 0xef, 0x30, 0x20, 0x50, 0xef, 0x10, 0xc0, 0x77, 0xb7, 0x57, 0x10, 0x00, 0x23, 0x8c, 0xa9, 0x06, - 0x93, 0x87, 0x87, 0x58, 0x03, 0xc7, 0x07, 0x00, 0x63, 0x1b, 0x07, 0x12, 0x03, 0xa4, 0x09, 0x07, 0xc1, 0x47, 0xe3, - 0xf2, 0x87, 0xda, 0x01, 0x45, 0xef, 0x30, 0xc0, 0x4b, 0x41, 0x14, 0x22, 0x86, 0x93, 0x85, 0x0a, 0x00, 0x13, 0x85, - 0x0a, 0x00, 0xef, 0x30, 0xa0, 0x4c, 0xb7, 0x1c, 0x20, 0x00, 0x13, 0x85, 0x0c, 0x02, 0xef, 0x30, 0xa0, 0x68, 0xef, - 0x30, 0x20, 0x6d, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x5d, 0x10, 0x00, 0xaa, 0x86, 0x13, 0x06, 0x46, 0x45, 0x93, 0x85, - 0xcd, 0x3d, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0xf0, 0x49, 0x93, 0x85, 0x0c, 0x02, 0x41, 0x46, 0x33, 0x05, 0x8d, - 0x00, 0xef, 0x00, 0x30, 0x38, 0xaa, 0x8c, 0xc1, 0x47, 0x63, 0x09, 0x05, 0x0e, 0x89, 0x45, 0x13, 0x85, 0xcd, 0x3d, - 0xef, 0x00, 0x50, 0x4f, 0x37, 0x55, 0x10, 0x00, 0x93, 0x07, 0xb0, 0x07, 0x91, 0x45, 0x13, 0x05, 0xc5, 0x3f, 0xa3, - 0x8c, 0xf9, 0x06, 0xef, 0x00, 0xf0, 0x4d, 0xfa, 0xce, 0xbf, 0xd7, 0x63, 0x4e, 0x22, 0xa4, 0x2f, 0x18, 0x62, 0x10, - 0xe7, 0xb8, 0x9f, 0x42, 0xca, 0x1a, 0xb8, 0xd9, 0x8f, 0xcb, 0x1b, 0xfe, 0xd8, 0x41, 0x41, 0xba, 0x73, 0x22, 0x84, - 0x8f, 0xe8, 0x90, 0x16, 0xef, 0xe0, 0x9f, 0xf7, 0xef, 0xf0, 0xcf, 0x87, 0xef, 0xf0, 0x4f, 0xc3, 0xef, 0x10, 0xa0, - 0x53, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x17, 0xf5, 0x08, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xc7, 0x07, 0xf3, - 0xc9, 0xe3, 0xef, 0x10, 0xa0, 0x02, 0xe3, 0x15, 0x85, 0x20, 0xd2, 0x47, 0x9c, 0x43, 0x63, 0x94, 0xa7, 0x00, 0xef, - 0x10, 0xc0, 0x18, 0xb2, 0x47, 0x98, 0x43, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x13, 0xf7, 0x1e, 0x37, 0x56, 0x10, 0x00, - 0x13, 0x06, 0x86, 0x4d, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x10, 0x41, 0xef, 0xf0, 0x4f, - 0xbe, 0x37, 0x25, 0x00, 0x08, 0xef, 0x20, 0x70, 0x0d, 0xef, 0xf0, 0x4f, 0xa8, 0xef, 0x20, 0x60, 0x5f, 0xef, 0x10, - 0x50, 0x1c, 0xef, 0x20, 0x30, 0x21, 0xef, 0xe0, 0xff, 0xf3, 0x32, 0x47, 0x37, 0x56, 0x10, 0x00, 0x93, 0x07, 0x50, - 0x05, 0x13, 0x06, 0x46, 0x4e, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, 0x64, 0x1c, 0xc3, 0xef, 0x00, 0x50, 0x3d, - 0xef, 0x20, 0x10, 0x21, 0xef, 0x10, 0x70, 0x48, 0xef, 0x20, 0x20, 0x5f, 0xef, 0x30, 0x90, 0x00, 0xc2, 0x47, 0x98, - 0x43, 0x93, 0x07, 0x50, 0x05, 0xe3, 0x08, 0xf7, 0xe4, 0xad, 0xb9, 0x63, 0x1c, 0xe5, 0x00, 0x83, 0xc7, 0x17, 0x00, - 0xbd, 0x8b, 0xe3, 0x82, 0x07, 0xec, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0xa0, 0x59, 0x65, 0xbd, 0x91, 0x07, 0x75, - 0xb5, 0x03, 0xa4, 0x09, 0x07, 0xe3, 0xe4, 0x87, 0x16, 0x37, 0x55, 0xfa, 0x77, 0x99, 0x22, 0x2f, 0x4d, 0xca, 0xf6, - 0x83, 0x0f, 0x59, 0x69, 0xe8, 0xfb, 0x06, 0x09, 0x3e, 0xc9, 0x5d, 0x8f, 0xbd, 0x32, 0xc0, 0x74, 0x8c, 0x40, 0xd5, - 0xfa, 0xdf, 0x85, 0x01, 0x1a, 0x9a, 0x68, 0x17, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0xc5, 0x3f, 0xef, 0x00, 0xb0, - 0x3f, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x3f, 0x95, 0x45, 0xef, 0x00, 0xd0, 0x3e, 0x13, 0x05, 0xf0, 0x07, - 0x39, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xf5, 0x94, 0x43, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, - 0x00, 0x13, 0x87, 0x16, 0x00, 0x98, 0xc3, 0x03, 0xc7, 0x89, 0x07, 0xa2, 0x87, 0x13, 0x06, 0x46, 0x46, 0x93, 0x85, - 0xc5, 0x3f, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x30, 0x34, 0xb7, 0x17, 0x20, 0x00, 0x13, 0x85, 0xc7, 0x07, 0x3d, - 0x46, 0x81, 0x45, 0xef, 0x30, 0xd0, 0x7f, 0x83, 0xc7, 0x89, 0x07, 0x13, 0x07, 0x20, 0x04, 0x63, 0x80, 0xe7, 0x56, - 0x63, 0x69, 0xf7, 0x16, 0x13, 0x07, 0x10, 0x02, 0x63, 0x89, 0xe7, 0x3e, 0x63, 0x60, 0xf7, 0x08, 0x45, 0x47, 0x63, - 0x82, 0xe7, 0x30, 0x63, 0x69, 0xf7, 0x02, 0x05, 0x47, 0x63, 0x85, 0xe7, 0x24, 0x41, 0x47, 0x63, 0x8d, 0xe7, 0x26, - 0x89, 0x49, 0x3d, 0xa3, 0x93, 0x87, 0x07, 0xfa, 0x93, 0xf7, 0xf7, 0x0f, 0x45, 0x47, 0xe3, 0x69, 0xf7, 0xfe, 0x37, - 0x57, 0x10, 0x00, 0x8a, 0x07, 0x13, 0x07, 0xc7, 0x4e, 0xba, 0x97, 0x9c, 0x43, 0x82, 0x87, 0x49, 0x47, 0x63, 0x82, - 0xe7, 0x34, 0x13, 0x07, 0x00, 0x02, 0xe3, 0x9a, 0xe7, 0xfc, 0x42, 0x04, 0x41, 0x80, 0xa1, 0x47, 0xe3, 0x13, 0xf4, - 0xf4, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x81, 0xfa, 0xe5, 0x41, 0x75, - 0x45, 0xea, 0xba, 0xc3, 0xbb, 0x97, 0x2f, 0x92, 0xb4, 0x71, 0x56, 0xba, 0xd0, 0xa0, 0xbc, 0x5e, 0xbd, 0xea, 0xe4, - 0x2c, 0xbd, 0xc4, 0x6a, 0x38, 0xb0, 0x96, 0x27, 0xd0, 0xdc, 0x40, 0x18, 0x63, 0x97, 0x07, 0x54, 0x93, 0x07, 0xf0, - 0x1f, 0x63, 0xe3, 0xa7, 0x54, 0x83, 0x25, 0x4d, 0x00, 0xef, 0x10, 0x90, 0x1e, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x1b, - 0xf5, 0x52, 0xad, 0xa6, 0x13, 0x07, 0x10, 0x03, 0x63, 0x86, 0xe7, 0x3a, 0x63, 0x6f, 0xf7, 0x04, 0x13, 0x07, 0x20, - 0x02, 0x63, 0x87, 0xe7, 0x38, 0x13, 0x07, 0x00, 0x03, 0xe3, 0x91, 0xe7, 0xf8, 0x42, 0x04, 0x41, 0x80, 0x91, 0x47, - 0xe3, 0x1a, 0xf4, 0xee, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x97, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x83, 0x63, - 0x9e, 0x07, 0x4e, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xea, 0xe7, 0x4e, 0x03, 0x45, 0x3d, 0x00, 0xfd, 0x47, 0x63, 0xe5, - 0xa7, 0x4e, 0x93, 0x15, 0x25, 0x00, 0x0d, 0x81, 0x93, 0xf7, 0xc5, 0x01, 0x3a, 0x95, 0xbd, 0x45, 0xb3, 0x95, 0xf5, - 0x00, 0x0a, 0x05, 0x93, 0xc5, 0xf5, 0xff, 0x5a, 0x95, 0x05, 0xa4, 0x13, 0x07, 0x00, 0x04, 0x63, 0x8f, 0xe7, 0x3a, - 0x13, 0x07, 0x10, 0x04, 0xe3, 0x94, 0xe7, 0xf2, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x1d, 0xf4, 0xe8, 0x83, - 0x26, 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0xa1, 0x82, 0xc2, 0x06, 0xc1, 0x82, 0x63, 0xe1, 0xd7, 0x4a, 0x37, 0x56, - 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x86, 0x4b, 0x93, 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, - 0x00, 0x10, 0x1f, 0xef, 0x10, 0x50, 0x57, 0xef, 0x20, 0x00, 0x75, 0x83, 0x27, 0x0d, 0x00, 0x91, 0x65, 0x93, 0x85, - 0xfa, 0x47, 0x17, 0x25, 0x1e, 0x43, 0xe9, 0x33, 0xd8, 0x02, 0x03, 0xae, 0xcf, 0x84, 0xf2, 0x8b, 0xcd, 0x3c, 0x10, - 0xd2, 0xc0, 0x1f, 0xb2, 0x47, 0xd3, 0xbe, 0xe3, 0xe4, 0xe8, 0x12, 0xc3, 0xc8, 0x45, 0x18, 0x19, 0x05, 0x20, 0xa1, - 0x83, 0xc2, 0x07, 0xc1, 0x83, 0xa6, 0x07, 0x37, 0x15, 0x20, 0x00, 0xbe, 0x95, 0x13, 0x05, 0x05, 0x08, 0xef, 0x10, - 0x30, 0x19, 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x74, 0x93, 0x07, 0xc0, 0x1b, 0xe3, 0xe0, 0x87, 0xa8, 0x93, 0x05, 0x44, - 0x00, 0x29, 0xac, 0x13, 0x07, 0x10, 0x07, 0x63, 0x69, 0xf7, 0x02, 0x13, 0x07, 0xf0, 0x05, 0xe3, 0x66, 0xf7, 0xea, - 0x13, 0x07, 0x00, 0x05, 0xe3, 0x90, 0xe7, 0xea, 0x42, 0x04, 0x41, 0x80, 0x89, 0x47, 0xe3, 0x19, 0xf4, 0xe0, 0x03, - 0x44, 0x1d, 0x00, 0x37, 0x15, 0x20, 0x00, 0x13, 0x05, 0x05, 0x08, 0xa2, 0x85, 0xef, 0xe0, 0x1f, 0xd7, 0xd9, 0xb7, - 0x13, 0x07, 0x20, 0x08, 0x63, 0x8b, 0xe7, 0x6e, 0x63, 0x6d, 0xf7, 0x04, 0x13, 0x07, 0x00, 0x08, 0x63, 0x82, 0xe7, - 0x68, 0x13, 0x07, 0x10, 0x08, 0xe3, 0x93, 0xe7, 0xe6, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x1c, 0xf4, 0xdc, - 0x03, 0x45, 0x1d, 0x00, 0x3d, 0x47, 0x81, 0x47, 0x63, 0x6e, 0xa7, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x47, - 0xf5, 0x89, 0x47, 0x33, 0x57, 0xa7, 0x00, 0x05, 0x8b, 0x01, 0xc7, 0xef, 0xe0, 0x7f, 0xe6, 0xaa, 0x87, 0xfd, 0x17, - 0x09, 0x47, 0x63, 0x63, 0xf7, 0x3c, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x72, 0xaa, 0x97, 0x83, 0xc9, 0x07, - 0x00, 0x1d, 0xaa, 0x13, 0x07, 0x00, 0x09, 0xe3, 0x9c, 0xe7, 0xe0, 0x93, 0x17, 0x04, 0x01, 0xc1, 0x83, 0x13, 0x07, - 0x30, 0x02, 0xe3, 0x73, 0xfa, 0xa8, 0x14, 0x54, 0xc7, 0x06, 0x88, 0x1f, 0x45, 0xef, 0x40, 0x7a, 0x35, 0xc3, 0x1e, - 0x47, 0x8b, 0x03, 0x2a, 0xa2, 0xde, 0x0c, 0xb1, 0x25, 0x57, 0x1a, 0x89, 0xfd, 0xa3, 0x0a, 0xd1, 0xfb, 0xfa, 0xf0, - 0x19, 0xf7, 0xd8, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0xbe, 0x86, 0x13, 0x06, 0x06, 0x4c, 0x93, 0x85, - 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0xd0, 0x0e, 0xef, 0x20, 0xa0, 0x0d, 0xef, 0x20, 0xc0, 0x64, 0xef, - 0x20, 0x20, 0x0e, 0x2a, 0x84, 0xef, 0x20, 0x40, 0x0d, 0xef, 0x20, 0x00, 0x66, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x14, - 0xf4, 0x36, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0x00, 0x2c, 0x93, 0x07, 0x40, 0x02, 0x81, 0xa3, 0x93, 0x19, 0x04, - 0x01, 0x93, 0xd9, 0x09, 0x01, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0xce, 0x86, 0x13, 0x06, 0x06, 0x4a, - 0x93, 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0xf0, 0x09, 0x93, 0x07, 0x1b, 0x00, 0xe3, 0xeb, 0x37, - 0xd1, 0xce, 0x85, 0x13, 0x85, 0x0a, 0x00, 0xef, 0xf0, 0x4f, 0x8e, 0xa9, 0xaa, 0x42, 0x04, 0x41, 0x80, 0x93, 0x07, - 0x40, 0x02, 0xe3, 0x1f, 0xf4, 0xce, 0x03, 0x25, 0x0d, 0x00, 0x0d, 0x44, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, - 0x64, 0xa4, 0x30, 0xef, 0xf0, 0x8f, 0xae, 0xd5, 0x47, 0x63, 0x1f, 0xf5, 0x2e, 0x83, 0x29, 0x0d, 0x00, 0x93, 0xd9, - 0x89, 0x00, 0xc2, 0x09, 0x93, 0xd9, 0x09, 0x01, 0xe3, 0x6c, 0x34, 0x91, 0x13, 0x84, 0x09, 0x0e, 0x16, 0x04, 0x91, - 0x4c, 0x71, 0x14, 0x93, 0x0d, 0x40, 0x02, 0xb3, 0x05, 0x9d, 0x01, 0x11, 0x46, 0x68, 0x10, 0xef, 0x30, 0x70, 0x4c, - 0xb2, 0x55, 0x33, 0x05, 0x94, 0x01, 0x91, 0x0c, 0xfa, 0x4f, 0x60, 0xde, 0x6f, 0x1c, 0xa4, 0x15, 0x4a, 0xa0, 0x12, - 0xa0, 0x2b, 0x4e, 0x49, 0x39, 0x13, 0x4a, 0xa9, 0xb3, 0x69, 0x99, 0xb7, 0xa8, 0xd8, 0x9c, 0x2b, 0x00, 0x69, 0xcf, - 0xcd, 0x41, 0x86, 0xc8, 0x1a, 0xef, 0x20, 0x20, 0x33, 0xe3, 0x94, 0xbc, 0xff, 0x09, 0x65, 0x8a, 0x09, 0xb7, 0xf5, - 0xf0, 0xf0, 0x13, 0x05, 0x05, 0xbf, 0x93, 0x85, 0x05, 0x0f, 0x4e, 0x95, 0xef, 0x20, 0x80, 0x31, 0xc5, 0xa0, 0x42, - 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x13, 0xf4, 0xc8, 0x03, 0x25, 0x0d, 0x00, 0x0d, 0x44, 0x21, 0x81, 0x42, 0x05, - 0x41, 0x81, 0x63, 0x68, 0xa4, 0x28, 0xef, 0xf0, 0x0f, 0xa7, 0x93, 0x07, 0x30, 0x0c, 0x63, 0x08, 0xf5, 0x00, 0xaa, - 0x89, 0x93, 0x07, 0x00, 0x08, 0x63, 0x9a, 0xf9, 0x20, 0xb1, 0xb9, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0xc2, 0x07, - 0xc1, 0x83, 0xe3, 0x6b, 0xf4, 0x88, 0x93, 0x87, 0x07, 0x0e, 0x13, 0x94, 0x57, 0x00, 0x93, 0x09, 0x00, 0x02, 0x33, - 0x05, 0x94, 0x01, 0xef, 0x20, 0x20, 0x20, 0xb7, 0x17, 0x20, 0x00, 0x93, 0x87, 0x07, 0x08, 0x2a, 0xd6, 0x11, 0x46, - 0x33, 0x85, 0x97, 0x01, 0x6c, 0x10, 0x91, 0x0c, 0xef, 0x30, 0x30, 0x43, 0xe3, 0x90, 0x3c, 0xff, 0x93, 0x05, 0x40, - 0x02, 0x52, 0x85, 0x29, 0xb7, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x17, 0xf4, 0xc0, 0x03, 0x25, 0x0d, 0x00, - 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0x6d, 0xa4, 0x20, 0xef, 0xf0, 0xaf, 0x9f, 0xd5, 0x47, 0x63, 0x08, 0xf5, - 0x20, 0xd9, 0x47, 0x63, 0x01, 0xf5, 0x04, 0x83, 0x29, 0x0d, 0x00, 0x93, 0xd9, 0x89, 0x00, 0xc2, 0x09, 0x93, 0xd9, - 0x09, 0x01, 0xe3, 0x62, 0x34, 0x83, 0x89, 0x67, 0x13, 0x95, 0x29, 0x00, 0xfa, 0xc6, 0xb1, 0xbc, 0xdc, 0xf5, 0x78, - 0x3d, 0x7b, 0x6e, 0x77, 0xac, 0x36, 0x62, 0xeb, 0xbe, 0xa1, 0xde, 0xcf, 0xdf, 0xdc, 0xb7, 0x77, 0x63, 0x5d, 0xc2, - 0x2b, 0x22, 0x81, 0x84, 0x61, 0x48, 0x53, 0xa0, 0x1b, 0x93, 0x87, 0x07, 0xbf, 0x81, 0x45, 0x3e, 0x95, 0x93, 0x89, - 0x09, 0x0e, 0xef, 0x20, 0xe0, 0x24, 0x96, 0x09, 0x13, 0x04, 0x00, 0x02, 0x33, 0x85, 0x99, 0x01, 0x81, 0x45, 0x91, - 0x0c, 0xef, 0x20, 0xc0, 0x23, 0xe3, 0x9a, 0x8c, 0xfe, 0x93, 0x09, 0x30, 0x0c, 0xb9, 0xaa, 0x42, 0x04, 0x41, 0x80, - 0x8d, 0x47, 0xe3, 0x11, 0xf4, 0xba, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, 0x07, 0x01, 0x8d, 0x8b, 0x41, - 0x81, 0x63, 0x95, 0x07, 0x1a, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe1, 0xa7, 0x1a, 0xef, 0x10, 0x60, 0x5b, 0x23, 0x22, - 0xaa, 0x00, 0xa1, 0x45, 0x8d, 0xb7, 0x42, 0x04, 0x41, 0x80, 0x85, 0x47, 0x01, 0x45, 0xe3, 0x18, 0xf4, 0xb6, 0xef, - 0x10, 0x30, 0x24, 0x6d, 0xbf, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x10, 0xf4, 0xb6, 0x83, 0x27, 0x0d, 0x00, - 0xa1, 0x83, 0x13, 0x94, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x80, 0x63, 0x94, 0x07, 0x16, 0x93, 0x07, 0xf0, 0x1f, 0x63, - 0xe0, 0x87, 0x16, 0x0a, 0x04, 0x33, 0x05, 0x64, 0x01, 0xef, 0x20, 0xe0, 0x17, 0x93, 0xf4, 0x04, 0xf0, 0xc9, 0x8c, - 0x13, 0x05, 0x4b, 0x00, 0x22, 0x95, 0xef, 0x20, 0xe0, 0x16, 0xc1, 0x77, 0x93, 0x87, 0xf7, 0x0f, 0xfd, 0x8c, 0x22, - 0x05, 0xc9, 0x8c, 0x13, 0x05, 0x8b, 0x00, 0x22, 0x95, 0xef, 0x20, 0x80, 0x15, 0xb7, 0x07, 0x01, 0xff, 0xfd, 0x17, - 0x42, 0x05, 0xfd, 0x8c, 0xc9, 0x8c, 0x13, 0x05, 0xcb, 0x00, 0x22, 0x95, 0xef, 0x20, 0x20, 0x14, 0xfa, 0x70, 0x68, - 0x99, 0xc9, 0x5d, 0xfd, 0x77, 0x78, 0x7f, 0xb8, 0xac, 0xfa, 0xbe, 0x98, 0xb8, 0xcd, 0x0f, 0x4a, 0x71, 0x9f, 0x66, - 0x0d, 0x8e, 0x25, 0xd8, 0xd6, 0xc6, 0x08, 0x96, 0xb2, 0x8f, 0xe1, 0x78, 0x1c, 0xa2, 0x04, 0x62, 0x05, 0xa1, 0x80, - 0xc9, 0x8c, 0x23, 0x22, 0x9a, 0x00, 0x95, 0xbf, 0x93, 0x07, 0xb4, 0xff, 0xc2, 0x07, 0xc1, 0x83, 0x13, 0x07, 0xb0, - 0x1b, 0xe3, 0x61, 0xf7, 0xae, 0x83, 0x26, 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0x93, 0x09, 0xc0, 0x03, 0xa1, 0x82, - 0xc2, 0x06, 0xc1, 0x82, 0x63, 0xe0, 0xd7, 0x08, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x06, - 0x4b, 0x93, 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x40, 0x63, 0x03, 0x25, 0x0d, 0x00, 0x91, 0x69, - 0x93, 0x89, 0x09, 0x20, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x26, 0x05, 0x4e, 0x95, 0xef, 0x10, 0x30, 0x13, 0x93, - 0x07, 0xa0, 0x0a, 0xaa, 0x8c, 0x63, 0x12, 0xf5, 0x04, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0xbf, 0x9f, 0xef, 0x20, - 0xe0, 0x36, 0x83, 0x27, 0x0d, 0x00, 0x42, 0x04, 0x41, 0x80, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, 0xa6, 0x07, 0xb7, - 0x05, 0x20, 0x00, 0x13, 0x06, 0xc4, 0xff, 0x33, 0x85, 0x37, 0x01, 0x74, 0x10, 0x93, 0x85, 0x45, 0x00, 0xef, 0x10, - 0xf0, 0x02, 0x2a, 0x84, 0x93, 0x09, 0x30, 0x0c, 0xef, 0x20, 0x00, 0x36, 0x63, 0x03, 0x94, 0x01, 0xc1, 0x49, 0x13, - 0xf5, 0xf9, 0x0f, 0xe5, 0xae, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x10, 0xf4, 0xa4, 0x03, 0x25, 0x0d, 0x00, - 0x93, 0x07, 0xf0, 0x1f, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0xe4, 0xa7, 0x04, 0x91, 0x67, 0x26, 0x05, 0x93, - 0x87, 0xfa, 0xbf, 0xc2, 0xb6, 0x88, 0x6b, 0x7a, 0xb9, 0x24, 0x77, 0x28, 0x7d, 0x46, 0x0c, 0x86, 0x80, 0x0a, 0x92, - 0x4e, 0xbe, 0x91, 0xb2, 0x27, 0xca, 0x3c, 0x70, 0xba, 0xff, 0xfc, 0x2f, 0x5a, 0xaf, 0xa6, 0x50, 0x1d, 0x07, 0x20, - 0x3e, 0x95, 0x55, 0xbd, 0x42, 0x04, 0x41, 0x80, 0x91, 0x47, 0xe3, 0x1c, 0xf4, 0xa0, 0xc1, 0x45, 0x68, 0x10, 0xef, - 0xe0, 0x1f, 0x98, 0x68, 0x10, 0xef, 0x10, 0x80, 0x7c, 0xef, 0x30, 0xa0, 0x20, 0xef, 0x20, 0xa0, 0x2e, 0x91, 0x45, - 0x13, 0x05, 0x00, 0x06, 0xef, 0x30, 0xc0, 0x42, 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x2f, 0x93, 0x07, 0xa0, 0x0a, 0xe3, - 0x0e, 0xf4, 0xe2, 0x93, 0x09, 0xc0, 0x03, 0x59, 0xbf, 0x42, 0x04, 0x41, 0x80, 0x93, 0x07, 0x00, 0x03, 0xe3, 0x1c, - 0xf4, 0x9c, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0x1f, 0x94, 0x68, 0x10, 0xef, 0x10, 0x80, 0x78, 0xef, 0x30, 0xa0, - 0x1c, 0xef, 0x20, 0xa0, 0x2a, 0x93, 0x05, 0x00, 0x03, 0x13, 0x05, 0x10, 0x06, 0x7d, 0xbf, 0x42, 0x04, 0x41, 0x80, - 0x8d, 0x47, 0xe3, 0x17, 0xf4, 0x9a, 0xef, 0x30, 0xe0, 0x1a, 0xef, 0x20, 0xe0, 0x28, 0x8d, 0x45, 0x13, 0x05, 0x20, - 0x06, 0xef, 0x30, 0x00, 0x3d, 0x2a, 0x84, 0xef, 0x20, 0x00, 0x2a, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x14, 0xf4, 0xfa, - 0xef, 0xe0, 0x7f, 0xf0, 0x05, 0xb3, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x1f, 0xf4, 0x96, 0xef, 0x30, 0xe0, - 0x17, 0x8d, 0x45, 0x13, 0x05, 0x30, 0x06, 0xef, 0x30, 0x40, 0x3a, 0xb1, 0xb4, 0x42, 0x04, 0x41, 0x80, 0x93, 0x07, - 0x00, 0x03, 0xe3, 0x11, 0xf4, 0x96, 0xef, 0x30, 0x20, 0x16, 0xef, 0x20, 0x50, 0x6f, 0xb7, 0x15, 0x20, 0x00, 0x2a, - 0xd6, 0x13, 0x06, 0x00, 0x02, 0xfa, 0x99, 0x17, 0x50, 0x16, 0x19, 0x46, 0x96, 0xdc, 0x78, 0x56, 0x08, 0x95, 0x3d, - 0xa2, 0x26, 0xe3, 0x09, 0xc9, 0x14, 0x35, 0x00, 0x41, 0x0c, 0xd8, 0x2e, 0x4f, 0x6c, 0xcf, 0xe4, 0x6a, 0x93, 0x3b, - 0x28, 0x1e, 0x93, 0x85, 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, 0xef, 0x30, 0x60, 0x26, 0x11, 0x46, 0x6c, 0x10, 0x13, - 0x05, 0x00, 0x0c, 0xef, 0x30, 0xa0, 0x25, 0xef, 0x20, 0xc0, 0x21, 0x93, 0x05, 0x00, 0x03, 0x13, 0x05, 0x00, 0x07, - 0xef, 0x30, 0xc0, 0x35, 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x22, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1a, 0xf4, 0xf2, 0xef, - 0xe0, 0x3f, 0xe9, 0x75, 0xb1, 0x93, 0x17, 0x04, 0x01, 0xc1, 0x83, 0x3d, 0x47, 0xe3, 0x74, 0xf7, 0x90, 0xef, 0x30, - 0x80, 0x10, 0xef, 0x20, 0xb0, 0x69, 0xaa, 0x8c, 0x01, 0x45, 0xef, 0x20, 0xd0, 0x45, 0x41, 0x46, 0x93, 0x85, 0x0a, - 0x00, 0x01, 0x45, 0xef, 0x20, 0xf0, 0x46, 0xef, 0x20, 0x00, 0x1d, 0xb7, 0x15, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, - 0x93, 0x85, 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, 0x66, 0xd6, 0xef, 0x30, 0x40, 0x1f, 0x11, 0x46, 0x6c, 0x10, 0x13, - 0x05, 0x00, 0x0c, 0xef, 0x30, 0x80, 0x1e, 0x85, 0x45, 0x13, 0x05, 0x10, 0x04, 0xef, 0x30, 0x00, 0x2f, 0x93, 0x07, - 0xa0, 0x0a, 0xaa, 0x8c, 0x63, 0x19, 0xf5, 0x00, 0x81, 0x45, 0x13, 0x05, 0x20, 0x04, 0xef, 0x30, 0xc0, 0x2d, 0x63, - 0x05, 0x95, 0x01, 0xef, 0x20, 0xa0, 0x1a, 0x5d, 0xbd, 0x42, 0x04, 0x41, 0x80, 0x93, 0x0d, 0x04, 0xff, 0xef, 0x20, - 0xc0, 0x19, 0xee, 0x8c, 0x22, 0x9d, 0x93, 0x07, 0x00, 0x09, 0xb3, 0x05, 0x9d, 0x41, 0x63, 0xe5, 0x97, 0x09, 0x66, - 0x86, 0x01, 0x45, 0xef, 0x20, 0xd0, 0x3f, 0xe6, 0x85, 0xfa, 0xad, 0xd6, 0x41, 0x0d, 0x03, 0xf4, 0x73, 0xe9, 0x9c, - 0xda, 0xe7, 0x57, 0x9b, 0xd1, 0xa0, 0x7e, 0xea, 0xc1, 0xb9, 0xb2, 0x46, 0xe5, 0xc2, 0x44, 0xbc, 0x06, 0xc5, 0x55, - 0xf5, 0x63, 0xed, 0x7f, 0x00, 0x1f, 0x13, 0x05, 0x40, 0x04, 0xef, 0x30, 0x40, 0x2a, 0x13, 0x07, 0xa0, 0x0a, 0xe3, - 0x11, 0xe5, 0xe8, 0x2a, 0xce, 0x81, 0x45, 0x13, 0x05, 0x50, 0x04, 0xef, 0x30, 0x00, 0x29, 0xf2, 0x47, 0xaa, 0x8c, - 0xe3, 0x17, 0xf5, 0xe6, 0x01, 0x45, 0xef, 0x20, 0x30, 0x3b, 0x93, 0x85, 0x0a, 0x00, 0x41, 0x46, 0x01, 0x45, 0xef, - 0x20, 0x50, 0x3c, 0x93, 0x07, 0xf0, 0x03, 0xb7, 0x05, 0x20, 0x00, 0x63, 0xe1, 0xb7, 0x07, 0x93, 0x85, 0x05, 0x01, - 0x01, 0x45, 0x6e, 0x86, 0xef, 0x20, 0xd0, 0x3a, 0xee, 0x85, 0x13, 0x05, 0x60, 0x04, 0xef, 0x30, 0x40, 0x25, 0xe3, - 0x1b, 0x95, 0xe3, 0x81, 0x45, 0x13, 0x05, 0xa0, 0x04, 0xef, 0x30, 0x60, 0x24, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x12, - 0xf5, 0xe2, 0xef, 0x20, 0x10, 0x58, 0x93, 0x07, 0x00, 0x05, 0x23, 0xaa, 0xf9, 0x06, 0xb1, 0xb1, 0x13, 0x06, 0x00, - 0x09, 0x01, 0x45, 0xef, 0x20, 0x50, 0x37, 0x93, 0x05, 0x00, 0x09, 0x13, 0x05, 0x30, 0x04, 0xef, 0x30, 0xa0, 0x21, - 0x13, 0x07, 0xa0, 0x0a, 0xe3, 0x1c, 0xe5, 0xde, 0x93, 0x8c, 0x0c, 0xf7, 0xb1, 0xb7, 0x93, 0x85, 0x05, 0x01, 0x01, - 0x45, 0x13, 0x06, 0x00, 0x04, 0xef, 0x20, 0xd0, 0x34, 0x93, 0x05, 0x00, 0x04, 0x13, 0x05, 0x70, 0x04, 0xef, 0x30, - 0x20, 0x1f, 0xe3, 0x1a, 0x95, 0xdd, 0x13, 0x04, 0x04, 0xfb, 0x93, 0x0c, 0x00, 0x08, 0x93, 0x0d, 0xa0, 0x0a, 0xb3, - 0x05, 0x8d, 0x40, 0x63, 0xe0, 0x8c, 0x02, 0x22, 0x86, 0x01, 0x45, 0xef, 0x20, 0xfa, 0xc6, 0xa6, 0xe5, 0xa7, 0x78, - 0x93, 0x9b, 0x9b, 0xb3, 0x5c, 0x39, 0x4b, 0x4d, 0xf4, 0x49, 0x81, 0x0e, 0x08, 0x21, 0xa9, 0xeb, 0x94, 0x1d, 0x2a, - 0x02, 0x3f, 0x7d, 0x8c, 0xf9, 0xb6, 0x0e, 0xe8, 0xd8, 0x1f, 0x10, 0x32, 0xa2, 0x85, 0x13, 0x05, 0x90, 0x04, 0xef, - 0x30, 0x80, 0x1c, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x13, 0xf5, 0xda, 0x85, 0xbf, 0x01, 0x45, 0x13, 0x06, 0x00, 0x08, - 0xef, 0x20, 0x30, 0x30, 0x93, 0x05, 0x00, 0x08, 0x13, 0x05, 0x80, 0x04, 0xef, 0x30, 0x80, 0x1a, 0xe3, 0x15, 0xb5, - 0xd9, 0x13, 0x04, 0x04, 0xf8, 0x7d, 0xbf, 0x42, 0x04, 0x41, 0x80, 0xa1, 0x47, 0x63, 0x10, 0xf4, 0xf6, 0x03, 0x44, - 0x1d, 0x00, 0xbd, 0x47, 0xe3, 0xe8, 0x87, 0xd6, 0x83, 0x2c, 0x4d, 0x00, 0xfd, 0x57, 0xe3, 0x83, 0xfc, 0xd6, 0x93, - 0x19, 0xa4, 0x00, 0x13, 0x85, 0x09, 0x40, 0xef, 0xe0, 0x8f, 0xe6, 0x13, 0x07, 0xa0, 0x0a, 0x2a, 0x8d, 0xe3, 0x18, - 0xe5, 0xd4, 0x93, 0x89, 0x09, 0x20, 0x4e, 0x85, 0xef, 0xe0, 0x4f, 0xe5, 0xaa, 0x8d, 0xe3, 0x10, 0xa5, 0xd5, 0xe6, - 0x85, 0x4e, 0x85, 0xef, 0x10, 0x60, 0x1b, 0xe3, 0x1a, 0xb5, 0xd3, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf5, - 0x85, 0x47, 0x33, 0x94, 0x87, 0x00, 0x1c, 0x43, 0x5d, 0x8c, 0x00, 0xc3, 0x91, 0xbe, 0x42, 0x04, 0x41, 0x80, 0x8d, - 0x47, 0x63, 0x1d, 0xf4, 0xee, 0x83, 0x45, 0x1d, 0x00, 0xbd, 0x47, 0xe3, 0xe5, 0xb7, 0xd0, 0xb7, 0x37, 0x20, 0x00, - 0x83, 0xa7, 0x47, 0xf5, 0xd1, 0x49, 0xb3, 0xd7, 0xb7, 0x00, 0x85, 0x8b, 0xe3, 0x88, 0x07, 0xc8, 0x37, 0x15, 0x20, - 0x00, 0x13, 0x05, 0x05, 0x08, 0xef, 0xe0, 0x6f, 0xeb, 0x85, 0x47, 0xe3, 0x07, 0xf5, 0xb4, 0x89, 0x47, 0xfa, 0x0c, - 0xba, 0xfe, 0x6a, 0x14, 0xb4, 0x28, 0xdf, 0x3d, 0xa4, 0xcc, 0x03, 0x78, 0x79, 0x42, 0xf4, 0x1e, 0x02, 0x54, 0xb1, - 0xd2, 0x31, 0x8d, 0x58, 0x22, 0x6b, 0xea, 0x4d, 0xf1, 0x80, 0x9a, 0x12, 0xb0, 0x20, 0xe3, 0x0c, 0xf5, 0xc6, 0xe9, - 0xb9, 0xef, 0x10, 0x90, 0x43, 0xef, 0xe0, 0x8f, 0xd8, 0x6f, 0xf0, 0xef, 0xe6, 0xef, 0x00, 0xc0, 0x6f, 0x6f, 0xf0, - 0xef, 0xe6, 0xef, 0x00, 0x30, 0x4e, 0x41, 0x14, 0xaa, 0x86, 0x63, 0x0b, 0x05, 0xea, 0x8d, 0x45, 0x13, 0x85, 0xcd, - 0x3d, 0x36, 0xce, 0x71, 0x24, 0xf2, 0x46, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x45, 0x93, 0x85, 0xcd, 0x3d, - 0x13, 0x05, 0x49, 0x64, 0x09, 0x24, 0xf2, 0x46, 0x09, 0x47, 0x85, 0x47, 0x63, 0x83, 0xe6, 0x00, 0x89, 0x47, 0x83, - 0xc6, 0x89, 0x07, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x22, 0x87, 0x13, 0x06, 0xc6, 0x47, 0x93, 0x85, - 0xc5, 0x3f, 0x13, 0x05, 0x49, 0x64, 0xa3, 0x8c, 0xf9, 0x06, 0xd9, 0x2a, 0xef, 0xe0, 0x8f, 0xce, 0xef, 0xe0, 0x8f, - 0xff, 0x62, 0x47, 0x85, 0x47, 0x23, 0x00, 0xf7, 0x00, 0xef, 0x00, 0xe0, 0x5a, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, - 0x63, 0x11, 0xf5, 0xd6, 0x25, 0x29, 0x63, 0x1e, 0x85, 0xd4, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xf4, 0xb1, - 0xeb, 0x83, 0xa7, 0x4b, 0x07, 0x13, 0x07, 0xfb, 0x00, 0xfd, 0x17, 0x63, 0x64, 0xf7, 0x04, 0x05, 0x45, 0xef, 0x20, - 0xb0, 0x17, 0x03, 0xa6, 0x4b, 0x07, 0xb7, 0x09, 0x20, 0x00, 0x93, 0x85, 0x09, 0x00, 0x13, 0x85, 0x09, 0x00, 0xef, - 0x20, 0xf0, 0x25, 0x37, 0x14, 0x20, 0x00, 0x13, 0x05, 0x04, 0x02, 0xef, 0x20, 0x50, 0x34, 0x03, 0xa5, 0x4b, 0x07, - 0x93, 0x87, 0xfa, 0xa0, 0x7d, 0x2a, 0xc4, 0x55, 0xe9, 0x30, 0x6c, 0xe0, 0xc1, 0xd6, 0x46, 0x56, 0x79, 0x5b, 0xe3, - 0x6f, 0x7e, 0x82, 0x9f, 0xf4, 0xc8, 0xb3, 0xe7, 0xaf, 0x30, 0xe1, 0x6a, 0x50, 0x29, 0x09, 0x4f, 0x88, 0x21, 0x09, - 0x00, 0x41, 0x46, 0x3e, 0x95, 0x93, 0x05, 0x04, 0x02, 0xef, 0x30, 0x00, 0x5f, 0x83, 0xa7, 0x4b, 0x07, 0xc1, 0x07, - 0x23, 0xaa, 0xfb, 0x06, 0xef, 0x00, 0xf0, 0x1b, 0x13, 0x04, 0xa0, 0x0a, 0x63, 0x0a, 0x85, 0xce, 0xef, 0xe0, 0x8f, - 0xfe, 0x63, 0x16, 0x85, 0xce, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, - 0x06, 0x4d, 0x93, 0x85, 0xc5, 0x3f, 0x13, 0x05, 0x45, 0x40, 0x25, 0x22, 0xef, 0xe0, 0x2f, 0xb7, 0xef, 0x20, 0x70, - 0x32, 0xef, 0x00, 0xb0, 0x3a, 0xef, 0x00, 0xb0, 0x31, 0xef, 0xe0, 0xaf, 0xf9, 0x6f, 0xf0, 0xaf, 0xcb, 0x2a, 0x87, - 0x81, 0x47, 0x01, 0x45, 0x63, 0x93, 0xc7, 0x00, 0x82, 0x80, 0xb3, 0x06, 0xf7, 0x00, 0x33, 0x88, 0xf5, 0x00, 0x83, - 0xc6, 0x06, 0x00, 0x03, 0x48, 0x08, 0x00, 0x85, 0x07, 0xb3, 0xc6, 0x06, 0x01, 0x55, 0x8d, 0x13, 0x75, 0xf5, 0x0f, - 0xf9, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x37, 0x37, 0x20, 0x00, 0x03, 0xa8, 0xc7, 0xf5, 0x83, 0x27, 0x87, 0xf5, 0xaa, - 0x86, 0x13, 0x07, 0x87, 0xf5, 0x01, 0x45, 0x63, 0x13, 0xf8, 0x00, 0x82, 0x80, 0x37, 0x26, 0x20, 0x00, 0x13, 0x06, - 0xc6, 0x08, 0x93, 0x08, 0xf0, 0x7f, 0x63, 0x01, 0xb5, 0x02, 0x33, 0x0e, 0xf6, 0x00, 0x03, 0x4e, 0x0e, 0x00, 0x05, - 0x05, 0x33, 0x83, 0xa6, 0x00, 0xa3, 0x0f, 0xc3, 0xff, 0x85, 0x07, 0x63, 0xf3, 0xf8, 0x00, 0x81, 0x47, 0xe3, 0x11, - 0xf8, 0xfe, 0x1c, 0xc3, 0x82, 0x80, 0xfa, 0xb6, 0x4e, 0x6d, 0xcc, 0xa5, 0x5a, 0x86, 0x69, 0x4a, 0xed, 0x3b, 0x6d, - 0x72, 0xbf, 0x67, 0xbc, 0x76, 0xd6, 0xf5, 0xb3, 0x28, 0x14, 0xf7, 0xad, 0x82, 0x7d, 0xe7, 0x43, 0x20, 0xa6, 0x8a, - 0x9e, 0x60, 0x22, 0xb7, 0x36, 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x86, 0xf5, 0x83, 0xa7, 0xc7, 0xf5, - 0x93, 0x86, 0x86, 0xf5, 0x33, 0x87, 0xe7, 0x40, 0x63, 0x56, 0x07, 0x00, 0x05, 0x66, 0x13, 0x06, 0x06, 0x80, 0x32, - 0x97, 0x63, 0x5b, 0xe5, 0x00, 0x33, 0x85, 0xa7, 0x40, 0x85, 0x67, 0x93, 0x87, 0x07, 0x80, 0x63, 0xf3, 0xa7, 0x00, - 0x3e, 0x95, 0x88, 0xc2, 0x82, 0x80, 0xb7, 0x36, 0x20, 0x00, 0x03, 0xa8, 0xc6, 0xf5, 0x13, 0x07, 0xf0, 0x7f, 0x13, - 0x86, 0xc6, 0xf5, 0x93, 0x07, 0x18, 0x00, 0x63, 0x73, 0xf7, 0x00, 0x81, 0x47, 0xb7, 0x36, 0x20, 0x00, 0x83, 0xa8, - 0x86, 0xf5, 0x37, 0x27, 0x20, 0x00, 0x93, 0x85, 0x86, 0xf5, 0x13, 0x07, 0xc7, 0x08, 0x63, 0x9f, 0xf8, 0x00, 0x93, - 0x88, 0x17, 0x80, 0x93, 0x86, 0x17, 0x00, 0x63, 0x93, 0x08, 0x00, 0x81, 0x46, 0x94, 0xc1, 0xba, 0x96, 0x93, 0x05, - 0xa0, 0x02, 0x23, 0x80, 0xb6, 0x00, 0x42, 0x97, 0x23, 0x00, 0xa7, 0x00, 0x1c, 0xc2, 0x82, 0x80, 0x82, 0x80, 0x39, - 0x71, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x06, 0xce, 0x36, 0xd6, 0x3a, 0xd8, 0x3e, 0xda, 0x42, 0xdc, 0x46, 0xde, - 0xaa, 0x84, 0x2e, 0x89, 0x32, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0xdf, 0x96, 0x63, 0x14, 0x09, 0x00, 0xef, 0xe0, 0x5f, - 0x96, 0x19, 0xe0, 0xef, 0xe0, 0xff, 0x95, 0x7c, 0x10, 0x3e, 0xc6, 0xef, 0x30, 0x20, 0x13, 0xaa, 0x85, 0x37, 0x55, - 0x10, 0x00, 0x13, 0x05, 0x85, 0x60, 0xef, 0x30, 0x20, 0x38, 0xfa, 0xe6, 0x62, 0x71, 0xcb, 0xf2, 0x2f, 0x27, 0x8e, - 0xdf, 0x6e, 0x14, 0xc9, 0x9a, 0x2d, 0x20, 0x9a, 0x04, 0x69, 0x18, 0x79, 0xa3, 0xfa, 0x80, 0x66, 0xb7, 0x7f, 0xb3, - 0xb8, 0xe0, 0xca, 0x8e, 0x89, 0x38, 0x23, 0x37, 0x55, 0x10, 0x00, 0x4a, 0x86, 0xa6, 0x85, 0x13, 0x05, 0x05, 0x61, - 0xef, 0x30, 0x20, 0x37, 0xb2, 0x45, 0x22, 0x85, 0xef, 0x30, 0x80, 0x33, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0xc5, - 0x61, 0xef, 0x30, 0xe0, 0x35, 0xb9, 0x29, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0x21, 0x61, 0x82, 0x80, - 0xae, 0x86, 0x37, 0x56, 0x10, 0x00, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x4b, 0x13, 0x05, 0x05, - 0x62, 0x9d, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, 0x83, 0xa6, 0x47, 0x10, - 0x63, 0x7e, 0xd7, 0x00, 0x0a, 0x07, 0x3e, 0x97, 0x18, 0x43, 0x18, 0xc1, 0x03, 0xa7, 0x07, 0x10, 0x13, 0x05, 0xa0, - 0x0a, 0x05, 0x07, 0x23, 0xa0, 0xe7, 0x10, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, 0x26, 0xca, - 0xb7, 0x34, 0x20, 0x00, 0x83, 0xa7, 0x04, 0xf6, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x11, - 0x47, 0x63, 0x6f, 0xf7, 0x0c, 0x37, 0x57, 0x10, 0x00, 0x8a, 0x07, 0x13, 0x07, 0x87, 0x64, 0xba, 0x97, 0x9c, 0x43, - 0x2a, 0x84, 0x93, 0x84, 0x04, 0xf6, 0x82, 0x87, 0x81, 0x45, 0xef, 0x30, 0x20, 0x31, 0xb7, 0x37, 0x20, 0x00, 0x23, - 0x92, 0xa7, 0xf6, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x86, 0x87, 0x88, 0xef, 0x20, 0xd0, 0x6f, 0x9c, 0x40, 0x85, 0x07, - 0x81, 0xa8, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0x07, 0xf6, 0x93, 0x07, 0xc0, 0x0f, 0xfa, 0xf3, 0x20, 0x9b, 0xa9, - 0x6c, 0x78, 0x02, 0x6c, 0xf9, 0x1a, 0x32, 0x3a, 0xc8, 0x02, 0x82, 0xbf, 0x2d, 0x91, 0x1b, 0x66, 0x20, 0x0c, 0x9b, - 0x2b, 0x3e, 0x63, 0xfe, 0xf3, 0x65, 0x4d, 0x49, 0x13, 0x10, 0x24, 0x63, 0xf1, 0xa7, 0x02, 0x62, 0x44, 0x9d, 0x47, - 0xf2, 0x40, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x9c, 0xc0, 0xd2, 0x44, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, - 0x05, 0x45, 0x62, 0x05, 0x61, 0x2d, 0xbf, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x49, 0xf6, 0x83, 0x55, 0x09, 0x00, - 0xef, 0x30, 0xa0, 0x2b, 0xb7, 0x37, 0x20, 0x00, 0xa3, 0x86, 0x87, 0x88, 0x23, 0x10, 0xa9, 0x00, 0x8d, 0x47, 0x5d, - 0xf4, 0x9c, 0xc0, 0x91, 0xa8, 0x37, 0x39, 0x20, 0x00, 0x03, 0x27, 0x89, 0xf6, 0x93, 0x07, 0xb0, 0x0f, 0x13, 0x09, - 0x89, 0xf6, 0x63, 0xf4, 0xe7, 0x00, 0xef, 0xe0, 0x3f, 0x81, 0x83, 0x27, 0x09, 0x00, 0x37, 0x3a, 0x20, 0x00, 0x13, - 0x0a, 0x4a, 0xf6, 0xb7, 0x39, 0x20, 0x00, 0x93, 0x89, 0xc9, 0x88, 0x83, 0x55, 0x0a, 0x00, 0xce, 0x97, 0x23, 0x81, - 0x87, 0x00, 0x22, 0x85, 0xef, 0x30, 0xa0, 0x26, 0x83, 0x27, 0x09, 0x00, 0x03, 0xc7, 0x19, 0x00, 0x23, 0x10, 0xaa, - 0x00, 0x85, 0x07, 0x23, 0x20, 0xf9, 0x00, 0xe3, 0xfd, 0xe7, 0xf4, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, - 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x93, 0xa7, 0xf6, 0x3d, 0xbf, 0x37, - 0x39, 0x20, 0x00, 0x13, 0x09, 0x69, 0xf6, 0x13, 0x14, 0x85, 0x00, 0xb7, 0x39, 0x20, 0x00, 0x03, 0x55, 0x09, 0x00, - 0x93, 0x89, 0x49, 0xf6, 0x83, 0xd7, 0x09, 0x00, 0x49, 0x8c, 0x23, 0x10, 0x89, 0x00, 0xe3, 0x8d, 0x87, 0xf0, 0xfa, - 0xd1, 0x60, 0x17, 0x0a, 0xe7, 0x71, 0xb2, 0x7f, 0xb2, 0xb8, 0x67, 0x0a, 0x5d, 0x9c, 0xb8, 0x5d, 0xc9, 0x9c, 0x96, - 0xa9, 0xa7, 0x58, 0x62, 0x5e, 0x17, 0x4f, 0xcd, 0xd8, 0xcc, 0xa3, 0x23, 0x76, 0xe8, 0x24, 0x37, 0x54, 0x10, 0x00, - 0x13, 0x05, 0x44, 0x62, 0x99, 0x47, 0x89, 0x45, 0x9c, 0xc0, 0x95, 0x3d, 0x93, 0x05, 0x44, 0x62, 0x62, 0x44, 0x03, - 0xd7, 0x09, 0x00, 0x83, 0x56, 0x09, 0x00, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x37, 0x56, - 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x86, 0x62, 0x13, 0x05, 0x45, 0x64, 0x05, 0x61, 0x6f, 0xf0, 0x3f, - 0xdd, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0xb7, 0x25, 0x10, 0x00, 0x37, 0x25, 0x10, 0x00, 0x23, 0xa0, - 0x07, 0x10, 0x23, 0xa2, 0x07, 0x10, 0x93, 0x85, 0x05, 0xf8, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x05, 0x25, 0xfb, 0x23, - 0xa0, 0x07, 0xf6, 0x6f, 0x20, 0xb0, 0x52, 0x11, 0xed, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0xef, 0xe0, 0x2f, 0xf2, - 0x32, 0x45, 0xf2, 0x40, 0x13, 0x06, 0xe0, 0x0f, 0x81, 0x45, 0x05, 0x61, 0x6f, 0x30, 0x40, 0x25, 0x13, 0x06, 0xe0, - 0x0f, 0x81, 0x45, 0xdd, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xf6, 0x13, 0x05, 0xa0, 0x0a, 0x99, 0xc3, - 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, 0xf6, 0x1c, - 0x40, 0x06, 0xc6, 0x15, 0x47, 0x63, 0x98, 0xe7, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, - 0x82, 0x80, 0x81, 0xe7, 0x13, 0x05, 0x50, 0x05, 0xcd, 0xbf, 0xef, 0x20, 0x90, 0x50, 0x93, 0x07, 0xa0, 0x0a, 0xe3, - 0x19, 0xf5, 0xfe, 0xfa, 0xd4, 0x25, 0x1b, 0xf5, 0x09, 0x66, 0x96, 0x8d, 0x27, 0x3d, 0x08, 0x18, 0xc9, 0x1f, 0xb0, - 0xfe, 0xa7, 0xd9, 0xcd, 0x47, 0xa5, 0x5b, 0x8f, 0x35, 0xfe, 0x20, 0x93, 0x2e, 0x34, 0x48, 0xa0, 0xe6, 0xc0, 0x25, - 0x01, 0x00, 0x18, 0x40, 0x91, 0x47, 0xe3, 0xcd, 0xe7, 0xfc, 0x99, 0x47, 0x1c, 0xc0, 0xd9, 0xbf, 0x41, 0x11, 0x06, - 0xc6, 0xef, 0x20, 0x10, 0x50, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xf5, 0x00, 0xef, 0x20, 0x70, 0x51, 0xb7, 0x37, - 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x95, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, - 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x99, 0x47, 0x13, 0x05, - 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, - 0xf6, 0x9d, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x37, 0x35, - 0x20, 0x00, 0x13, 0x05, 0xc5, 0x88, 0x82, 0x80, 0x01, 0x11, 0x26, 0xca, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, - 0xc6, 0xaa, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, 0xe3, 0x83, 0xc7, 0x14, 0x00, 0x13, 0x07, 0xc0, 0x0f, 0x13, 0x05, - 0x50, 0x05, 0x63, 0x65, 0xf7, 0x06, 0x37, 0x39, 0x20, 0x00, 0x13, 0x04, 0xc9, 0x98, 0x23, 0x20, 0x04, 0x10, 0x03, - 0xc7, 0x04, 0x00, 0xa3, 0x00, 0xf4, 0x00, 0x03, 0xc6, 0x14, 0x00, 0x23, 0x00, 0xe4, 0x00, 0x93, 0x85, 0x24, 0x00, - 0x13, 0x05, 0x24, 0x00, 0xef, 0x30, 0x00, 0x10, 0x83, 0xc9, 0x14, 0x00, 0x13, 0x05, 0xc9, 0x98, 0x13, 0x09, 0xc9, - 0x98, 0x93, 0x84, 0x29, 0x00, 0xa6, 0x85, 0xfa, 0xe8, 0x86, 0x27, 0x2c, 0xd4, 0x07, 0xc4, 0xd6, 0x64, 0x9d, 0x0b, - 0xb6, 0x00, 0x19, 0x2a, 0x6d, 0x30, 0x08, 0xeb, 0xd3, 0x3a, 0x93, 0xc5, 0xc0, 0x89, 0x8d, 0xce, 0x94, 0x48, 0xc1, - 0x24, 0x5e, 0x98, 0x26, 0xef, 0x30, 0x60, 0x08, 0xa2, 0x94, 0x23, 0x80, 0xa4, 0x00, 0x4e, 0x94, 0x21, 0x81, 0x93, - 0x87, 0x49, 0x00, 0xa3, 0x01, 0xa4, 0x00, 0xfd, 0x56, 0x13, 0xf7, 0x37, 0x00, 0x19, 0xef, 0x89, 0x83, 0x23, 0x22, - 0xf9, 0x10, 0xef, 0x20, 0xb0, 0x45, 0x13, 0x05, 0xa0, 0x0a, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, - 0x49, 0x05, 0x61, 0x82, 0x80, 0x33, 0x07, 0xf9, 0x00, 0x23, 0x00, 0xd7, 0x00, 0x85, 0x07, 0xd1, 0xbf, 0xb7, 0x37, - 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, 0x83, 0xa7, 0x47, 0x10, 0x63, 0x14, 0xf7, 0x00, 0x6f, - 0x20, 0x30, 0x3e, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa0, 0x07, 0xf6, 0x82, 0x80, - 0x41, 0x11, 0x06, 0xc6, 0x93, 0x07, 0x00, 0x08, 0x73, 0xa0, 0x47, 0x30, 0x93, 0x06, 0x70, 0x3e, 0x09, 0x46, 0x93, - 0x05, 0x60, 0x04, 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, 0x30, 0x52, 0x8d, 0x45, 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, - 0x70, 0x52, 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, 0xf0, 0x4f, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x10, 0x50, 0xfd, - 0x56, 0x01, 0x46, 0x93, 0x05, 0x60, 0x04, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x90, 0x4f, 0xb2, 0x40, 0xb7, 0x07, - 0x20, 0x01, 0x23, 0xac, 0x07, 0x00, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x89, 0x2c, 0xb2, 0x40, 0x41, - 0x01, 0x45, 0xb7, 0x41, 0x11, 0x22, 0xc4, 0xb7, 0x07, 0x20, 0x01, 0xfa, 0x40, 0xba, 0x84, 0x16, 0x6e, 0xb2, 0xc7, - 0x1b, 0x8d, 0x50, 0x32, 0x51, 0x91, 0x7e, 0x99, 0x62, 0x34, 0x87, 0xa9, 0x5e, 0x21, 0x4a, 0x7e, 0x9b, 0x4a, 0x34, - 0xb0, 0x61, 0x1f, 0x9c, 0xab, 0x3f, 0x70, 0x27, 0x06, 0xc6, 0x23, 0xac, 0x07, 0x00, 0x2a, 0x84, 0x37, 0x05, 0x20, - 0x01, 0xef, 0x20, 0x50, 0x4b, 0x93, 0x07, 0x80, 0x3e, 0x13, 0x05, 0x80, 0x3e, 0x63, 0xe3, 0x87, 0x00, 0x22, 0x85, - 0xb7, 0x07, 0x20, 0x01, 0x98, 0x4f, 0x13, 0x84, 0x87, 0x01, 0xe3, 0x6d, 0xa7, 0xfe, 0x37, 0x05, 0x20, 0x01, 0xef, - 0x20, 0xb0, 0x49, 0xb2, 0x40, 0x23, 0x20, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x11, 0xe1, 0x82, 0x80, - 0x01, 0x00, 0x7d, 0x15, 0xe5, 0xbf, 0x6f, 0xf0, 0x9f, 0xb3, 0x39, 0xa4, 0x01, 0x11, 0x26, 0xca, 0xaa, 0x84, 0x37, - 0x05, 0x20, 0x01, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x56, 0xc2, 0x06, 0xce, 0x22, 0xcc, 0x2e, 0x89, 0x93, 0x09, - 0xa0, 0x0a, 0xef, 0x20, 0x50, 0x45, 0x37, 0x0a, 0x20, 0x01, 0x93, 0x0a, 0x80, 0x3e, 0x82, 0x94, 0x2a, 0x84, 0x63, - 0x0c, 0x35, 0x03, 0x83, 0x27, 0x8a, 0x01, 0x63, 0x7a, 0xf9, 0x04, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0xc4, 0x65, - 0x85, 0x45, 0xef, 0xf0, 0x9f, 0xb6, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0x05, 0xc4, 0x65, 0xa6, - 0x86, 0x13, 0x06, 0x06, 0x66, 0x13, 0x05, 0x45, 0x64, 0xef, 0xf0, 0x9f, 0xad, 0x13, 0x04, 0x50, 0x05, 0x37, 0x05, - 0x20, 0x01, 0xef, 0x20, 0x30, 0x41, 0xf2, 0x40, 0x22, 0x85, 0x62, 0x44, 0xb7, 0x07, 0x20, 0x01, 0x23, 0xac, 0x07, - 0x00, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xfa, 0x94, 0x9b, 0xa0, - 0xf0, 0x1f, 0x46, 0x59, 0x3e, 0x26, 0x93, 0x73, 0x96, 0xd2, 0xec, 0x9b, 0xdb, 0x12, 0x31, 0x44, 0xdd, 0xbd, 0x4c, - 0x46, 0x7f, 0x05, 0xc1, 0xc0, 0x61, 0xbb, 0x9e, 0x40, 0xea, 0x48, 0x28, 0xe3, 0xf0, 0x2a, 0xfb, 0x41, 0x22, 0x69, - 0xbf, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x87, 0x00, 0x1c, 0xc7, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, - 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, 0xc1, 0xa9, 0x44, 0x03, 0x45, 0x04, 0x00, 0x11, - 0xe5, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xef, 0xf0, 0xdf, 0xa1, 0x83, 0x47, 0x04, 0x00, - 0x63, 0x94, 0x97, 0x00, 0xef, 0xf0, 0x7f, 0xa6, 0x05, 0x04, 0xf9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0x25, 0x37, 0x93, - 0x07, 0xa0, 0x0a, 0x63, 0x05, 0xf5, 0x00, 0xef, 0xe0, 0xaf, 0xbd, 0x01, 0xa0, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, - 0x41, 0x11, 0x22, 0xc4, 0x37, 0x44, 0x20, 0x00, 0x13, 0x06, 0xc0, 0x1f, 0x81, 0x45, 0x13, 0x05, 0x04, 0xe0, 0x06, - 0xc6, 0x26, 0xc2, 0xef, 0x20, 0xb0, 0x6f, 0x13, 0x05, 0x04, 0xe0, 0x93, 0x05, 0xc0, 0x1f, 0xef, 0x20, 0xb0, 0x67, - 0x93, 0x04, 0x04, 0xe0, 0xb2, 0x40, 0x22, 0x44, 0x23, 0xae, 0xa4, 0x1e, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, - 0x11, 0x37, 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, 0xc0, 0x1f, 0x13, 0x04, 0x05, 0xe0, 0x13, 0x05, 0x05, 0xe0, - 0x06, 0xc6, 0xef, 0x20, 0xf0, 0x64, 0x03, 0x27, 0xc4, 0x1f, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xa7, 0x00, 0x93, - 0x07, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x3e, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, 0xaa, 0x87, - 0xfa, 0x44, 0x18, 0x96, 0x2e, 0x9f, 0xb7, 0x58, 0xfe, 0x45, 0xa6, 0x7d, 0x48, 0x81, 0x2a, 0x61, 0x1b, 0x41, 0x18, - 0x2b, 0xff, 0x58, 0xa1, 0x89, 0x00, 0xae, 0xfc, 0x78, 0x0c, 0x67, 0x2e, 0xf1, 0xb8, 0x20, 0x29, 0x63, 0x6e, 0xa7, - 0x00, 0x13, 0x77, 0x35, 0x00, 0x01, 0x45, 0x11, 0xeb, 0x37, 0x45, 0x20, 0x00, 0x13, 0x05, 0x05, 0xe0, 0xf1, 0x9b, - 0xaa, 0x97, 0x88, 0x43, 0x82, 0x80, 0x01, 0x45, 0x82, 0x80, 0x93, 0x07, 0xb0, 0x1f, 0x63, 0xec, 0xa7, 0x00, 0x93, - 0x77, 0x35, 0x00, 0x81, 0xeb, 0xb7, 0x47, 0x20, 0x00, 0x71, 0x99, 0x93, 0x87, 0x07, 0xe0, 0x3e, 0x95, 0x0c, 0xc1, - 0x82, 0x80, 0x41, 0x11, 0x37, 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, 0xc0, 0x1f, 0x13, 0x04, 0x05, 0xe0, 0x13, - 0x05, 0x05, 0xe0, 0x06, 0xc6, 0xef, 0x20, 0x70, 0x5d, 0xb2, 0x40, 0x23, 0x2e, 0xa4, 0x1e, 0x22, 0x44, 0x41, 0x01, - 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, 0x63, 0x61, 0xa7, 0x02, 0x93, 0x77, 0x35, 0x00, 0x13, 0x07, 0x50, 0x05, 0x89, - 0xef, 0x41, 0x11, 0x06, 0xc6, 0x5d, 0x37, 0xc9, 0x37, 0xb2, 0x40, 0x13, 0x07, 0xa0, 0x0a, 0x3a, 0x85, 0x41, 0x01, - 0x82, 0x80, 0x13, 0x07, 0x50, 0x05, 0x3a, 0x85, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x00, 0x10, 0x71, 0xb2, - 0x40, 0xb7, 0x07, 0x00, 0x02, 0x0d, 0x47, 0xf8, 0xcb, 0x13, 0x05, 0xa0, 0x0a, 0x41, 0x01, 0x82, 0x80, 0x73, 0x00, - 0x50, 0x10, 0x82, 0x80, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x52, 0xcc, 0x06, 0xd6, 0x2a, - 0x84, 0xae, 0x84, 0x32, 0x89, 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x07, 0x39, 0x41, 0x33, 0x05, 0x34, 0x01, 0x63, 0x6c, - 0xfa, 0x02, 0x71, 0x56, 0xfa, 0xda, 0xc8, 0xbe, 0xfc, 0x19, 0xff, 0xf1, 0x80, 0xc3, 0xb9, 0x24, 0x40, 0x93, 0x38, - 0x69, 0x94, 0xdc, 0x5e, 0x47, 0x09, 0xf7, 0xd1, 0xab, 0x59, 0xa5, 0x8b, 0x07, 0xe6, 0xbc, 0xa8, 0x92, 0x5d, 0xf8, - 0x29, 0x93, 0x57, 0x29, 0x00, 0xb3, 0x87, 0xc7, 0x02, 0x93, 0x75, 0xc9, 0xff, 0x33, 0x05, 0xb4, 0x00, 0xae, 0x94, - 0x33, 0x86, 0x27, 0x01, 0x11, 0xc6, 0x9c, 0x40, 0x6c, 0x00, 0x3e, 0xc6, 0xef, 0x20, 0xd0, 0x56, 0xb2, 0x50, 0x22, - 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0xb3, 0x87, 0x34, 0x01, 0x9c, 0x43, - 0x11, 0x46, 0x6c, 0x00, 0x3e, 0xc6, 0x91, 0x09, 0xef, 0x20, 0xb0, 0x54, 0x7d, 0xb7, 0x79, 0x71, 0x22, 0xd4, 0x26, - 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x52, 0xcc, 0x06, 0xd6, 0x2a, 0x84, 0xae, 0x84, 0x32, 0x89, 0x81, 0x49, 0x0d, 0x4a, - 0xb3, 0x07, 0x39, 0x41, 0xb3, 0x85, 0x34, 0x01, 0x63, 0x6d, 0xfa, 0x02, 0x71, 0x56, 0x93, 0x57, 0x29, 0x00, 0xb3, - 0x87, 0xc7, 0x02, 0x93, 0x75, 0xc9, 0xff, 0x2e, 0x94, 0xa6, 0x95, 0x33, 0x86, 0x27, 0x01, 0x01, 0xca, 0x1c, 0x40, - 0x68, 0x00, 0x3e, 0xc6, 0xef, 0x20, 0x30, 0x50, 0xb2, 0x47, 0x1c, 0xc0, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, - 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0x11, 0x46, 0x68, 0x00, 0xef, 0x20, 0x70, 0x4e, 0x32, 0x47, - 0xb3, 0x07, 0x34, 0x01, 0x91, 0x09, 0x98, 0xc3, 0x75, 0xb7, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, - 0xe1, 0xef, 0xe0, 0x6f, 0x9c, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa6, 0xe7, 0xf6, 0xb7, 0x37, - 0x20, 0x00, 0x23, 0xa8, 0x87, 0xf6, 0x22, 0x44, 0xfa, 0x18, 0x05, 0x19, 0xc5, 0x33, 0xbb, 0xae, 0xaa, 0xf1, 0x81, - 0x66, 0xb4, 0xa2, 0x1d, 0x46, 0x9b, 0x70, 0xd9, 0x61, 0xfe, 0x2b, 0x91, 0x1e, 0xc0, 0xa2, 0x1d, 0x8a, 0x59, 0x06, - 0xd2, 0xf0, 0x81, 0xd0, 0x2a, 0xb2, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x8a, 0x07, 0xa8, 0x41, 0x01, 0x6f, 0xf0, - 0xbf, 0xa4, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, 0x99, 0x37, 0x35, 0x20, - 0x00, 0xb7, 0x37, 0x20, 0x00, 0xa2, 0x85, 0x13, 0x06, 0xe0, 0x0f, 0x13, 0x05, 0x45, 0xa9, 0x23, 0x8a, 0x07, 0xb8, - 0xef, 0x20, 0xf0, 0x47, 0x22, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xb2, 0x41, 0x11, 0x22, - 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0xcf, 0x95, 0xb7, 0x34, 0x20, 0x00, 0x83, 0xc7, - 0x44, 0xb9, 0x99, 0xcb, 0x37, 0x35, 0x20, 0x00, 0x13, 0x06, 0xe0, 0x0f, 0x93, 0x85, 0x44, 0xb9, 0x13, 0x05, 0x45, - 0xa9, 0xef, 0x20, 0x50, 0x44, 0xa2, 0x85, 0x13, 0x85, 0x44, 0xb9, 0x13, 0x06, 0xe0, 0x0f, 0xef, 0x20, 0x70, 0x43, - 0x22, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x92, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0x1f, 0xae, 0xb7, 0x37, 0x20, 0x00, 0x03, - 0xa5, 0xc7, 0xf6, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0xc4, 0xf6, 0x26, 0xc2, - 0x04, 0x40, 0x06, 0xc6, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x89, 0xf4, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, - 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x37, 0x35, 0x20, 0x00, 0x13, 0x05, 0x45, 0xb9, 0xef, 0xf0, 0x3f, 0xaa, - 0xe3, 0x13, 0x95, 0xfe, 0x93, 0x07, 0x50, 0x05, 0x1c, 0xc0, 0xc5, 0xb7, 0xfa, 0x78, 0x17, 0x15, 0x3a, 0x55, 0xa5, - 0xc3, 0x0a, 0xbf, 0x4c, 0xcf, 0x2e, 0x59, 0xba, 0xa5, 0xa3, 0x30, 0xb2, 0xaf, 0xe2, 0xbc, 0x57, 0x06, 0xa8, 0xca, - 0x4a, 0x47, 0xa2, 0x41, 0xa9, 0xbb, 0x73, 0xa8, 0x2b, 0x37, 0x35, 0x20, 0x00, 0x83, 0x47, 0x45, 0xa9, 0x85, 0xc3, - 0xb7, 0x37, 0x20, 0x00, 0x83, 0xc7, 0x47, 0xb9, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, - 0xa6, 0xe7, 0xf6, 0x13, 0x05, 0x45, 0xa9, 0x6f, 0xf0, 0xff, 0xa6, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, - 0x06, 0xc6, 0xef, 0xf0, 0xdf, 0x99, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xf5, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, - 0x40, 0x41, 0x01, 0x82, 0x80, 0x6d, 0x71, 0x23, 0x26, 0x11, 0x10, 0x23, 0x24, 0x81, 0x10, 0x23, 0x22, 0x91, 0x10, - 0xef, 0xf0, 0xdf, 0x98, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x04, 0x2a, 0x84, 0xef, 0xf0, 0x5f, 0x9c, 0x63, - 0x1b, 0x85, 0x06, 0xef, 0xf0, 0xdf, 0xa1, 0x83, 0x46, 0x05, 0x00, 0x93, 0x07, 0x20, 0x0a, 0x2a, 0x84, 0x63, 0x80, - 0xf6, 0x02, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x66, 0x93, - 0x85, 0xc5, 0x67, 0x13, 0x05, 0x45, 0x64, 0xef, 0xf0, 0x6f, 0xeb, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xf7, - 0x22, 0x85, 0x82, 0x97, 0xef, 0xf0, 0xff, 0xaa, 0xef, 0xf0, 0xdf, 0xa8, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, - 0x14, 0xf5, 0x08, 0xef, 0xf0, 0x7f, 0x91, 0x63, 0x10, 0x85, 0x08, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xf6, - 0x63, 0x94, 0xa7, 0x04, 0x03, 0x24, 0x81, 0x10, 0x83, 0x20, 0xc1, 0x10, 0x83, 0x24, 0x41, 0x10, 0xfa, 0x38, 0x47, - 0x69, 0x59, 0x85, 0x64, 0xca, 0xeb, 0xaa, 0x4a, 0x92, 0x8d, 0xec, 0x14, 0xa7, 0xd0, 0xda, 0x70, 0xdf, 0x52, 0x6e, - 0xb7, 0xe1, 0xfe, 0x04, 0x3a, 0x70, 0xff, 0x96, 0x8a, 0x22, 0x4c, 0x80, 0x2c, 0x51, 0x61, 0x6f, 0xf0, 0x7f, 0xee, - 0xef, 0xf0, 0xbf, 0x97, 0x81, 0x44, 0x63, 0x14, 0x85, 0x00, 0x93, 0x04, 0xc0, 0x07, 0xef, 0xf0, 0x5f, 0x98, 0x93, - 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0xdd, 0xd4, 0x0a, 0x85, 0x23, 0x00, 0x91, 0x00, 0xa3, 0x00, 0x01, 0x00, - 0xef, 0xf0, 0x5f, 0xe3, 0x79, 0xbf, 0x93, 0x04, 0xc0, 0x07, 0xf5, 0xb7, 0xb7, 0x35, 0x20, 0x00, 0x83, 0xc7, 0x45, - 0xb9, 0x95, 0xc3, 0x03, 0x24, 0x81, 0x10, 0x83, 0x20, 0xc1, 0x10, 0x83, 0x24, 0x41, 0x10, 0x37, 0x35, 0x20, 0x00, - 0x13, 0x06, 0xe0, 0x0f, 0x93, 0x85, 0x45, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0x51, 0x61, 0x6f, 0x20, 0x30, 0x2a, 0x83, - 0x20, 0xc1, 0x10, 0x03, 0x24, 0x81, 0x10, 0x83, 0x24, 0x41, 0x10, 0x51, 0x61, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, - 0x23, 0xa2, 0x07, 0x00, 0x21, 0x65, 0x6f, 0x20, 0xc0, 0x1c, 0x41, 0x11, 0x21, 0x65, 0x06, 0xc6, 0xef, 0x20, 0x60, - 0x1b, 0xb2, 0x40, 0xb7, 0x07, 0x01, 0x04, 0x05, 0x47, 0xd8, 0xc3, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, - 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x07, 0x70, 0x02, 0x2a, 0x84, 0xae, 0x84, 0x63, 0xf4, 0xa7, 0x00, 0xef, 0xd0, 0xff, - 0xf4, 0x37, 0x05, 0x01, 0x04, 0x0a, 0x04, 0x13, 0x05, 0x05, 0x10, 0x2a, 0x94, 0x04, 0xc0, 0xb2, 0x40, 0x22, 0x44, - 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x13, 0x87, 0x07, 0x10, 0x93, 0x87, 0x07, 0x1a, 0x23, - 0x20, 0xfa, 0x6d, 0x11, 0x2f, 0x07, 0xc3, 0x1f, 0x9b, 0xe3, 0x52, 0x05, 0x0c, 0x31, 0xe3, 0x79, 0xdb, 0x6f, 0xad, - 0xe0, 0x87, 0x06, 0x72, 0xe2, 0x66, 0x8f, 0x37, 0x7e, 0x4d, 0x76, 0xb0, 0xa9, 0x92, 0xe7, 0x58, 0x2d, 0x07, 0x00, - 0x11, 0x07, 0xe3, 0x1d, 0xf7, 0xfe, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0xc8, 0xcb, 0x82, 0x80, 0x42, 0x05, 0xb7, - 0x07, 0x01, 0x04, 0xc8, 0xcb, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x88, 0x4b, 0x13, 0x75, 0xf5, 0x0f, 0x82, 0x80, - 0x89, 0x67, 0x37, 0x07, 0x01, 0x04, 0x8d, 0x07, 0x1c, 0xc7, 0x23, 0x2a, 0x07, 0x00, 0x82, 0x80, 0x41, 0x11, 0x06, - 0xc6, 0x22, 0xc4, 0x2a, 0x84, 0xad, 0x37, 0xb7, 0x07, 0x01, 0x04, 0x80, 0xcf, 0xc5, 0x37, 0x65, 0x37, 0x22, 0x44, - 0xb2, 0x40, 0x41, 0x01, 0xa9, 0xb7, 0xb7, 0x06, 0x01, 0x04, 0x9c, 0x46, 0x05, 0x45, 0x13, 0xf7, 0x17, 0x00, 0x1d, - 0xc7, 0x13, 0xf7, 0x07, 0x40, 0x0d, 0x45, 0x1d, 0xe3, 0x98, 0x4a, 0x13, 0x77, 0xf7, 0x0f, 0x19, 0xcf, 0x13, 0xf7, - 0x27, 0x20, 0x09, 0x45, 0x19, 0xeb, 0x13, 0xd7, 0xb7, 0x00, 0x05, 0x8b, 0x11, 0x45, 0x11, 0xe7, 0x13, 0xd5, 0x87, - 0x00, 0x13, 0x45, 0x15, 0x00, 0x05, 0x89, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x88, 0xcf, 0x82, 0x80, 0x01, 0x11, - 0x22, 0xcc, 0x06, 0xce, 0x33, 0x07, 0xb6, 0x00, 0x93, 0x07, 0x00, 0x09, 0x2e, 0x84, 0x63, 0xf8, 0xe7, 0x00, 0x32, - 0xc6, 0x2a, 0xc4, 0xef, 0xd0, 0x5f, 0xe7, 0x32, 0x46, 0x22, 0x45, 0xb7, 0x15, 0x01, 0x04, 0xa2, 0x95, 0xef, 0xf0, - 0xdf, 0xbb, 0xf2, 0x40, 0x62, 0x44, 0x13, 0x05, 0xa0, 0x0a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, 0x26, - 0xca, 0x06, 0xce, 0x33, 0x07, 0xfa, 0xb6, 0xbb, 0xbe, 0x4b, 0xcc, 0xe1, 0x00, 0x6d, 0x5a, 0x44, 0x4a, 0x88, 0xc0, - 0xdf, 0x12, 0x8b, 0x8d, 0x54, 0x2f, 0xa7, 0x7c, 0x41, 0x60, 0x8b, 0x58, 0xbf, 0x5c, 0x20, 0x9e, 0xae, 0x13, 0xdf, - 0x30, 0x2e, 0xb6, 0x00, 0x93, 0x07, 0x00, 0x08, 0xaa, 0x84, 0x2e, 0x84, 0x63, 0xf6, 0xe7, 0x00, 0x32, 0xc6, 0xef, - 0xd0, 0xdf, 0xe3, 0x32, 0x46, 0x37, 0x25, 0x01, 0x04, 0x13, 0x05, 0x05, 0x80, 0x22, 0x95, 0x62, 0x44, 0xf2, 0x40, - 0xa6, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x6f, 0xf0, 0x5f, 0xbe, 0x39, 0x71, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0xb7, - 0x55, 0x10, 0x00, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x06, 0x68, 0x93, 0x85, 0x05, 0x69, - 0x13, 0x05, 0x45, 0x69, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, - 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xf0, 0xcf, 0xc5, 0xef, 0xe0, 0xcf, 0xc8, - 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, - 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, - 0x09, 0x65, 0x6f, 0x10, 0x70, 0x7f, 0x09, 0x65, 0x6f, 0x10, 0xd0, 0x7f, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, - 0x84, 0x19, 0xe1, 0xef, 0xd0, 0x1f, 0xda, 0xdd, 0x37, 0xb7, 0x07, 0x00, 0x07, 0x83, 0x46, 0x14, 0x00, 0xd8, 0x43, - 0x83, 0x47, 0x04, 0x00, 0xa2, 0x06, 0xdd, 0x8e, 0x83, 0x47, 0x24, 0x00, 0xc2, 0x07, 0xdd, 0x8e, 0x83, 0x47, 0x34, - 0x00, 0xe2, 0x07, 0xd5, 0x8f, 0x93, 0x06, 0xf0, 0x0f, 0xfa, 0x95, 0x26, 0xce, 0x7e, 0x38, 0xc4, 0x24, 0x38, 0xce, - 0xb6, 0xd6, 0xa3, 0x70, 0x26, 0x3c, 0x10, 0x03, 0x06, 0x59, 0x19, 0xbe, 0x61, 0x9d, 0xb7, 0x92, 0xe5, 0x61, 0x0d, - 0x21, 0x66, 0x74, 0x53, 0x08, 0x2f, 0x63, 0x85, 0xd7, 0x00, 0x61, 0x9b, 0x9d, 0x8b, 0x5d, 0x8f, 0x93, 0x77, 0x77, - 0xff, 0x03, 0x47, 0x44, 0x00, 0x83, 0x46, 0x94, 0x00, 0xb2, 0x40, 0x0e, 0x07, 0x21, 0x8b, 0x5d, 0x8f, 0xfd, 0x77, - 0xbd, 0x07, 0x7d, 0x8f, 0x83, 0x47, 0x54, 0x00, 0x92, 0x07, 0x5d, 0x8f, 0xb7, 0x17, 0x80, 0xff, 0xfd, 0x17, 0x7d, - 0x8f, 0x83, 0x47, 0xa4, 0x00, 0xa2, 0x07, 0xd5, 0x8f, 0xb2, 0x07, 0xb7, 0xf6, 0x7f, 0x00, 0xf5, 0x8f, 0xd9, 0x8f, - 0x37, 0x07, 0x80, 0xf8, 0x7d, 0x17, 0xf9, 0x8f, 0x03, 0x47, 0x74, 0x00, 0xb7, 0x06, 0x80, 0x07, 0x5e, 0x07, 0x75, - 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x00, 0x88, 0x7d, 0x17, 0xf9, 0x8f, 0x03, 0x47, 0x64, 0x00, 0xb7, 0x06, 0x00, 0x78, - 0x22, 0x44, 0x6e, 0x07, 0x75, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x00, 0x07, 0x5c, 0xc3, 0x41, 0x01, 0x82, 0x80, 0xb7, - 0x37, 0x20, 0x00, 0x03, 0xa5, 0x87, 0xf7, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x13, 0x05, - 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, - 0x20, 0x13, 0x05, 0xa0, 0x0a, 0x89, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x89, 0x65, 0x37, 0x35, - 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x65, 0xba, 0x6f, 0xf0, 0xbf, 0x8c, 0x41, 0x11, 0xb7, 0x07, 0x08, - 0x05, 0x22, 0xc4, 0x03, 0xa4, 0xc7, 0x20, 0x37, 0x07, 0x00, 0x04, 0x06, 0xc6, 0xfa, 0x88, 0x8b, 0xd0, 0x34, 0x62, - 0xf6, 0xa2, 0x84, 0xda, 0xf2, 0x4d, 0x73, 0xc7, 0x42, 0x72, 0xad, 0xfe, 0xfa, 0xa9, 0xe0, 0x34, 0x85, 0xbf, 0xfc, - 0x28, 0xa2, 0x78, 0x1f, 0x55, 0xb0, 0x29, 0xc8, 0xe0, 0x2f, 0x26, 0xc2, 0xb3, 0x76, 0xe4, 0x00, 0x91, 0xca, 0x37, - 0x55, 0x10, 0x00, 0x23, 0xa6, 0xe7, 0x20, 0xa5, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xf0, 0x4f, 0xb7, 0xb7, 0x07, - 0x80, 0x6b, 0xe1, 0x8f, 0x95, 0xcb, 0x37, 0x07, 0x08, 0x05, 0x23, 0x26, 0xf7, 0x20, 0xb7, 0x07, 0x00, 0x68, 0x7d, - 0x8c, 0x93, 0x04, 0x50, 0x05, 0x11, 0xc8, 0x37, 0x55, 0x10, 0x00, 0x9d, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xf0, - 0xaf, 0xb4, 0xef, 0xd0, 0x9f, 0xc5, 0xb2, 0x40, 0x22, 0x44, 0x26, 0x85, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, - 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0xf7, 0x84, 0x43, 0x13, 0x07, 0xa0, 0x0a, 0x63, 0x96, 0xe4, 0x00, 0x13, 0x07, - 0x50, 0x05, 0x98, 0xc3, 0xe1, 0xbf, 0x93, 0x04, 0xa0, 0x0a, 0xd9, 0xbf, 0x81, 0x47, 0xb7, 0x05, 0x08, 0x05, 0x13, - 0x07, 0x00, 0x20, 0xb3, 0x86, 0xb7, 0x00, 0x90, 0x42, 0xb3, 0x06, 0xf5, 0x00, 0x91, 0x07, 0x90, 0xc2, 0xe3, 0x99, - 0xe7, 0xfe, 0x6f, 0xf0, 0xff, 0xf5, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0x2a, 0x84, 0xef, 0xf0, 0x1f, 0xf4, 0xb7, - 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf6, 0x8d, 0x47, 0x33, 0x95, 0x87, 0x00, 0xb7, 0xb7, - 0xaa, 0x02, 0x93, 0x87, 0xa7, 0xaa, 0x3d, 0x8d, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xa4, 0xa7, 0x20, 0x89, 0x65, 0x37, - 0x35, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x65, 0xb8, 0xef, 0xf0, 0x2f, 0xfe, 0x22, 0x44, 0xfa, 0x1a, - 0x63, 0x25, 0x90, 0x88, 0x74, 0xb1, 0x43, 0xbe, 0x41, 0x10, 0x74, 0x98, 0xaa, 0xbb, 0x41, 0x30, 0x3a, 0xe0, 0xf3, - 0xda, 0x33, 0xc8, 0x64, 0x91, 0x18, 0x1d, 0x8b, 0x47, 0x59, 0xf3, 0xb6, 0xb8, 0x30, 0xb2, 0x40, 0x41, 0x01, 0x6f, - 0xf0, 0x3f, 0xf1, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x9f, 0xef, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf7, - 0x37, 0x07, 0x08, 0x05, 0x13, 0x05, 0x00, 0x20, 0xf9, 0x9b, 0x23, 0x22, 0xf7, 0x20, 0xef, 0x10, 0xd0, 0x5e, 0xb2, - 0x40, 0x39, 0x45, 0x41, 0x01, 0x6f, 0x10, 0xf0, 0x5f, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf7, 0x1c, 0x43, - 0x93, 0xf7, 0xf7, 0xfd, 0x1c, 0xc3, 0x37, 0x07, 0x08, 0x05, 0x23, 0x22, 0xf7, 0x20, 0x82, 0x80, 0x37, 0x37, 0x20, - 0x00, 0x13, 0x07, 0x47, 0xf7, 0x1c, 0x43, 0x93, 0xe7, 0x07, 0x02, 0x1c, 0xc3, 0x37, 0x07, 0x08, 0x05, 0x23, 0x22, - 0xf7, 0x20, 0x82, 0x80, 0x33, 0x87, 0xc5, 0x00, 0xb7, 0x07, 0x08, 0x00, 0x63, 0x7c, 0xf7, 0x06, 0x01, 0x11, 0x22, - 0xcc, 0x26, 0xca, 0x4e, 0xc6, 0x06, 0xce, 0x4a, 0xc8, 0x93, 0xf4, 0x35, 0x00, 0xaa, 0x89, 0x2e, 0x84, 0x13, 0x05, - 0x50, 0x05, 0x9d, 0xec, 0x32, 0x89, 0xef, 0xf0, 0x5f, 0xe7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x47, 0xf7, 0xb7, - 0x06, 0x08, 0x05, 0xb7, 0x05, 0x00, 0x05, 0x13, 0x67, 0x27, 0x00, 0x23, 0xa2, 0xe6, 0x20, 0x93, 0x87, 0x47, 0xf7, - 0x0d, 0x47, 0x2e, 0x94, 0xb3, 0x06, 0x99, 0x40, 0x63, 0x60, 0xd7, 0x02, 0x98, 0x43, 0xb7, 0x07, 0x08, 0x05, 0x13, - 0x05, 0xa0, 0x0a, 0x23, 0xa2, 0xe7, 0x20, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, - 0x82, 0x80, 0xfa, 0x3b, 0x8a, 0x2e, 0xdc, 0xb8, 0x48, 0x65, 0x49, 0xab, 0xc4, 0x7a, 0xf3, 0x88, 0x67, 0xef, 0x4f, - 0x5f, 0x6e, 0xac, 0xe9, 0xe9, 0x77, 0x77, 0xec, 0xb9, 0xeb, 0x76, 0x12, 0x5f, 0x26, 0x4d, 0x18, 0x90, 0x31, 0xb3, - 0x06, 0x94, 0x00, 0x90, 0x42, 0xb3, 0x86, 0x99, 0x00, 0x91, 0x04, 0x90, 0xc2, 0xf9, 0xb7, 0x13, 0x05, 0x50, 0x05, - 0x82, 0x80, 0x01, 0x11, 0xaa, 0x85, 0x11, 0x46, 0x68, 0x00, 0x06, 0xce, 0xef, 0xf0, 0x1f, 0xf7, 0x93, 0x07, 0xa0, - 0x0a, 0x63, 0x16, 0xf5, 0x00, 0x32, 0x45, 0xf2, 0x40, 0x05, 0x61, 0x82, 0x80, 0x01, 0x45, 0xe5, 0xbf, 0xb7, 0x07, - 0x08, 0x00, 0x63, 0xef, 0xa7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x93, 0x77, 0x35, 0x00, 0x2a, - 0x84, 0x8d, 0xe3, 0xae, 0x84, 0xef, 0xf0, 0xbf, 0xdd, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x22, 0x44, - 0xb2, 0x40, 0x23, 0xaa, 0x97, 0x20, 0x92, 0x44, 0x01, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x9f, 0xe7, 0xb2, 0x40, 0x22, - 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xaa, 0x84, - 0x2e, 0x84, 0x45, 0x3f, 0x26, 0x85, 0xef, 0xf0, 0xbf, 0xf8, 0x63, 0x09, 0x85, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, - 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xcd, 0xbf, 0x01, 0x11, 0x22, 0xcc, - 0x2e, 0xc6, 0x06, 0xce, 0x2a, 0x84, 0xef, 0xf0, 0x5f, 0xf6, 0xb2, 0x45, 0x63, 0x03, 0xb5, 0x02, 0xfd, 0x57, 0x63, - 0x1a, 0xf5, 0x00, 0x63, 0x8e, 0xa5, 0x00, 0x22, 0x85, 0x62, 0x44, 0xf2, 0x40, 0x05, 0x61, 0x6f, 0xf0, 0xff, 0xfa, - 0x13, 0x05, 0x50, 0x05, 0xf2, 0x40, 0xfa, 0xa4, 0xc1, 0x41, 0xb4, 0x46, 0x93, 0x4a, 0xa4, 0xda, 0x59, 0x17, 0x81, - 0xe3, 0x3f, 0x46, 0x01, 0x0d, 0x5f, 0x1e, 0x72, 0x07, 0x6e, 0x42, 0x96, 0x9f, 0x71, 0xfb, 0x76, 0x34, 0x41, 0x9a, - 0x74, 0x68, 0x32, 0x62, 0x44, 0x05, 0x61, 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xd5, 0xbf, 0xb7, 0x07, 0x08, 0x00, - 0x63, 0xe0, 0xb7, 0x04, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0xf7, 0xf5, 0x1f, 0xaa, 0x84, 0x2e, - 0x84, 0x13, 0x05, 0x50, 0x05, 0x99, 0xef, 0xef, 0xf0, 0xbf, 0xd2, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, - 0x39, 0x45, 0xef, 0xf0, 0x5f, 0xdd, 0x26, 0x85, 0xef, 0xf0, 0xff, 0xda, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, - 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, - 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xfb, 0xb7, 0x00, 0x81, 0x44, 0xf2, 0x40, 0x62, - 0x44, 0x42, 0x49, 0xb2, 0x49, 0x26, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x82, 0x80, 0x93, 0xf4, 0xf5, 0x1f, 0x2e, 0x84, - 0xe5, 0xf4, 0x2a, 0x89, 0xef, 0xf0, 0xff, 0xcc, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x41, 0x45, 0xef, - 0xf0, 0x9f, 0xd7, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x17, 0xf5, 0xfc, 0x37, 0x34, 0x20, 0x00, 0x13, 0x05, 0x44, 0xc9, - 0xef, 0xf0, 0x5f, 0xd4, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x87, 0x07, 0x20, 0x23, 0xa0, 0x07, 0x00, 0x91, 0x07, 0xe3, - 0x9d, 0xe7, 0xfe, 0x93, 0x09, 0x44, 0xc9, 0x03, 0xd6, 0xc9, 0x1f, 0x93, 0x07, 0xc0, 0x1d, 0x63, 0xfa, 0xc7, 0x00, - 0x37, 0x55, 0x10, 0x00, 0x99, 0x45, 0x13, 0x05, 0x85, 0x69, 0xfa, 0x87, 0xd6, 0x01, 0xc6, 0x86, 0x57, 0xeb, 0x97, - 0xe7, 0x5f, 0x8b, 0x28, 0x38, 0xd1, 0xb8, 0xbf, 0xf6, 0x15, 0xda, 0x1b, 0x1b, 0x73, 0xbb, 0x60, 0xc2, 0x24, 0x8f, - 0x16, 0xfd, 0x04, 0x4d, 0x44, 0x40, 0x33, 0xef, 0xf0, 0xaf, 0x82, 0x41, 0xbf, 0x93, 0x05, 0x44, 0xc9, 0x4a, 0x85, - 0xef, 0x20, 0x60, 0x43, 0x83, 0xd4, 0xc9, 0x1f, 0x41, 0xb7, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe7, 0xa7, 0x04, 0x41, - 0x11, 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x13, 0x05, 0x50, 0x05, 0x9d, 0xe7, - 0xef, 0xf0, 0xbf, 0xc4, 0x85, 0x67, 0xb7, 0x04, 0x08, 0x05, 0x93, 0x87, 0x97, 0x82, 0x23, 0xa2, 0xf4, 0x20, 0x23, - 0xac, 0x84, 0x20, 0x39, 0x45, 0xef, 0xf0, 0xbf, 0xce, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf7, 0x13, 0x05, - 0xa0, 0x0a, 0x23, 0xa2, 0xf4, 0x20, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, - 0x05, 0x82, 0x80, 0x0d, 0x65, 0x01, 0x11, 0x13, 0x05, 0x05, 0x20, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, - 0x4e, 0xc6, 0xef, 0x10, 0xf0, 0x2f, 0x39, 0x45, 0xef, 0x10, 0x50, 0x31, 0x13, 0x05, 0x80, 0x07, 0x37, 0x39, 0x20, - 0x00, 0xef, 0xf0, 0x6f, 0xb9, 0x93, 0x09, 0x49, 0xf7, 0x83, 0xa7, 0x09, 0x00, 0x37, 0x04, 0x08, 0x05, 0x93, 0x04, - 0x04, 0x20, 0xdc, 0xc0, 0xb7, 0x07, 0x46, 0x00, 0x85, 0x07, 0xdc, 0xcc, 0x85, 0x67, 0x93, 0x87, 0x57, 0x86, 0x89, - 0x65, 0x37, 0x35, 0x10, 0x00, 0xdc, 0xc0, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x05, 0xb9, 0xef, 0xf0, 0xef, 0xc8, - 0xb7, 0x07, 0x40, 0x08, 0x9c, 0xc8, 0xdc, 0x40, 0x01, 0x45, 0x13, 0x09, 0x49, 0xf7, 0xfa, 0x24, 0x90, 0x58, 0x5a, - 0x4c, 0x24, 0x94, 0x96, 0x0f, 0x8f, 0xe0, 0x4e, 0xa1, 0x7b, 0x97, 0xdb, 0x3a, 0xa4, 0x2b, 0xbb, 0xed, 0x68, 0x5b, - 0x31, 0x18, 0xf3, 0xc2, 0x88, 0xd7, 0xe1, 0xbe, 0x09, 0x18, 0x34, 0x93, 0xe7, 0x07, 0x18, 0x23, 0xa0, 0xf9, 0x00, - 0xef, 0xf0, 0x7f, 0xf3, 0x93, 0x07, 0x04, 0x10, 0x98, 0x43, 0xb7, 0x67, 0xa5, 0xf0, 0x93, 0x87, 0xf7, 0xa0, 0x63, - 0x05, 0xf7, 0x02, 0x37, 0x55, 0x10, 0x00, 0x95, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, 0xbf, 0xf2, 0x41, 0x67, - 0x7d, 0x17, 0x93, 0x07, 0x04, 0x18, 0xb8, 0xd3, 0xf8, 0xd3, 0xb8, 0xd7, 0xf8, 0xd7, 0xb8, 0xdb, 0xf8, 0xdb, 0xb8, - 0xdf, 0xf8, 0xdf, 0x51, 0x45, 0xef, 0xf0, 0x7f, 0xc1, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x91, 0x8b, - 0x91, 0xeb, 0x37, 0x55, 0x10, 0x00, 0x91, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, 0x3f, 0xef, 0xef, 0xd0, 0x1f, - 0x80, 0xb7, 0x07, 0x08, 0x05, 0x37, 0x07, 0x40, 0x00, 0x23, 0xa6, 0xe7, 0x20, 0x03, 0x27, 0x09, 0x00, 0xf2, 0x40, - 0x62, 0x44, 0x23, 0xa2, 0xe7, 0x20, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, 0x85, 0x67, 0x37, - 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0x86, 0x23, 0x2a, 0xf7, 0xf6, 0x37, 0x37, 0x20, 0x00, 0x93, 0x07, 0x50, 0x05, - 0x23, 0x2c, 0xf7, 0xf6, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2e, 0xf7, 0xf6, 0x6f, 0xf0, 0xbf, 0xee, 0xb7, 0x07, 0x08, - 0x00, 0x63, 0xe0, 0xa7, 0x06, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, - 0x13, 0x05, 0x50, 0x05, 0xa1, 0xe3, 0xae, 0x84, 0xef, 0xf0, 0x7f, 0xad, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0xfa, - 0xcc, 0xb7, 0xcb, 0x99, 0x87, 0x50, 0x69, 0xb1, 0xf9, 0x94, 0xfc, 0x0a, 0x9c, 0x81, 0x0c, 0x13, 0x9e, 0x7e, 0x4c, - 0x8f, 0xef, 0x6f, 0xb7, 0x41, 0x54, 0x55, 0xca, 0x5f, 0xed, 0x41, 0xf0, 0x95, 0xf0, 0x34, 0x87, 0x20, 0x01, 0x47, - 0x93, 0x06, 0x00, 0x20, 0xb3, 0x85, 0xe4, 0x00, 0x8c, 0x41, 0x33, 0x06, 0xf7, 0x00, 0x11, 0x07, 0x0c, 0xc2, 0xe3, - 0x19, 0xd7, 0xfe, 0x7d, 0x57, 0x93, 0x87, 0x07, 0x20, 0xf8, 0xc3, 0xb8, 0xc7, 0xf8, 0xc7, 0xb8, 0xcb, 0x29, 0x45, - 0xef, 0xf0, 0xbf, 0xb5, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, - 0x05, 0x50, 0x05, 0x82, 0x80, 0xaa, 0x85, 0x37, 0x05, 0x08, 0x05, 0x41, 0x46, 0x13, 0x05, 0x05, 0x26, 0x6f, 0xf0, - 0x0f, 0xd0, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xef, 0xa7, 0x0a, 0x01, 0x11, 0x26, 0xca, 0x93, 0x77, 0xf5, 0x1f, 0x06, - 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x56, 0xc2, 0xaa, 0x84, 0x13, 0x05, 0x50, 0x05, 0xd9, 0xe7, - 0x93, 0x07, 0xc0, 0x1d, 0x32, 0x89, 0x63, 0xe3, 0xc7, 0x08, 0xb6, 0x89, 0x37, 0x34, 0x20, 0x00, 0x2e, 0x8a, 0xef, - 0xf0, 0x5f, 0xa4, 0x13, 0x06, 0x00, 0x20, 0x81, 0x45, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x80, 0x23, 0x4a, 0x86, - 0xd2, 0x85, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x00, 0x1f, 0x4e, 0x85, 0xef, 0xf0, 0xbf, 0xf9, 0x93, 0x0a, 0x44, - 0xc9, 0xb7, 0x07, 0x08, 0x05, 0x23, 0x9e, 0x2a, 0x1f, 0x13, 0x07, 0x44, 0xc9, 0x93, 0x86, 0x07, 0x20, 0x10, 0x43, - 0x11, 0x07, 0x90, 0xc3, 0x91, 0x07, 0xe3, 0x9c, 0xd7, 0xfe, 0x13, 0x06, 0x00, 0x20, 0x81, 0x45, 0x13, 0x05, 0x44, - 0xc9, 0xef, 0x20, 0xfa, 0xcd, 0x17, 0x3b, 0x60, 0x95, 0xd6, 0x31, 0x79, 0xac, 0x58, 0x84, 0x4c, 0x84, 0x77, 0x62, - 0xf5, 0x10, 0x21, 0x64, 0xf5, 0xdc, 0xaa, 0x02, 0x69, 0x6c, 0x97, 0xd5, 0x27, 0xe0, 0xab, 0x0a, 0xec, 0xc8, 0x35, - 0x80, 0x1f, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x97, 0x20, 0x31, 0x45, 0xef, 0xf0, 0x1f, 0xaa, 0x93, 0x07, 0xa0, - 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x69, 0x8d, 0x45, 0xef, 0xe0, 0x1f, 0xd8, - 0x13, 0x05, 0x50, 0x05, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, - 0x61, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xeb, 0xa7, 0x02, 0x41, 0x11, - 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0xf5, 0x1f, 0x2a, 0x84, 0x89, 0xef, 0xef, 0xf0, 0xdf, 0x99, 0xb7, 0x07, 0x08, - 0x05, 0x23, 0xac, 0x87, 0x20, 0x22, 0x44, 0xb2, 0x40, 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x1f, 0xa4, 0xb2, 0x40, - 0x22, 0x44, 0x13, 0x05, 0x50, 0x05, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, - 0xc4, 0x06, 0xc6, 0x37, 0x04, 0x08, 0x05, 0x23, 0x2c, 0xa4, 0x20, 0xef, 0xf0, 0x5f, 0x96, 0xb7, 0x37, 0x20, 0x00, - 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf6, 0xb7, 0xb7, 0xaa, 0x02, 0x93, 0x87, 0x67, 0xaa, 0xb2, 0x40, 0x23, - 0x24, 0xf4, 0x20, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xdf, 0x93, 0xb7, 0x37, - 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf6, 0xb2, 0x40, 0xb7, 0xb7, 0xa6, 0x02, 0x37, 0x07, 0x08, - 0x05, 0x93, 0x87, 0xa7, 0xaa, 0x23, 0x24, 0xfa, 0x95, 0x37, 0xbf, 0x20, 0x50, 0xa1, 0x69, 0x7a, 0xe0, 0xf3, 0x6d, - 0x53, 0xad, 0x26, 0x31, 0xe0, 0x51, 0x92, 0x34, 0x39, 0x79, 0x78, 0xf1, 0x1e, 0x1b, 0x7d, 0x2e, 0xd6, 0x93, 0xf7, - 0x2f, 0x6d, 0xa0, 0x36, 0xf7, 0x20, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x3e, 0xcc, 0xb7, 0x07, 0x08, 0x05, 0x3a, - 0xce, 0x03, 0xa7, 0xc7, 0x20, 0x36, 0xd0, 0xb7, 0x06, 0x40, 0x00, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, - 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0x75, - 0x8f, 0x05, 0xcf, 0x23, 0xa6, 0xd7, 0x20, 0x13, 0x07, 0xa0, 0x0a, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0xe7, 0xf6, - 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, - 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, - 0x03, 0xa7, 0xc7, 0x20, 0xb7, 0x06, 0x00, 0x08, 0x37, 0x55, 0x10, 0x00, 0x75, 0x8f, 0x0d, 0xc3, 0x23, 0xa6, 0xd7, - 0x20, 0x85, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, 0x3f, 0xc4, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, - 0x23, 0xae, 0xe7, 0xf6, 0xef, 0xd0, 0x1f, 0xbf, 0x75, 0xb7, 0x89, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, 0x7f, - 0xc2, 0xb7, 0x07, 0x02, 0x00, 0x73, 0xb0, 0x47, 0x30, 0xe5, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, - 0x23, 0xa0, 0xe7, 0xf8, 0x82, 0x80, 0x99, 0x47, 0x63, 0x05, 0xf5, 0x02, 0x9d, 0x47, 0x63, 0x0b, 0xf5, 0x00, 0x95, - 0x47, 0x63, 0x15, 0xf5, 0x02, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0xfa, 0xa3, 0x09, 0xcb, 0x2d, 0xb6, 0x5d, 0xc5, - 0x70, 0x27, 0xa3, 0xec, 0xa9, 0x20, 0x7b, 0x42, 0x3e, 0x1d, 0x30, 0xa7, 0x02, 0x0f, 0x2e, 0x25, 0x5e, 0x60, 0xc0, - 0x2e, 0xd5, 0xd5, 0xe5, 0x8c, 0xd5, 0x78, 0x37, 0x93, 0xf7, 0xf7, 0xf7, 0x29, 0xa8, 0xb7, 0x37, 0x20, 0x00, 0x13, - 0x07, 0xa0, 0x0a, 0x23, 0xa0, 0xe7, 0xf8, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xe7, 0x07, 0x08, - 0x7c, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf8, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, 0xf7, - 0x00, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xe7, 0x07, 0x08, 0x7c, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, - 0x03, 0xa7, 0x07, 0xf8, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, 0xf7, 0x00, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, - 0xf7, 0xf7, 0xf7, 0x7c, 0xc3, 0x82, 0x80, 0x39, 0x71, 0x2a, 0xd6, 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, 0x13, 0x05, - 0xc5, 0x69, 0x85, 0x45, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, - 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0x9f, 0xb6, 0xef, 0xd0, - 0x3f, 0xb2, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, - 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, - 0x20, 0x30, 0x39, 0x71, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, - 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0xfa, 0xa8, 0xed, 0xde, - 0xce, 0x91, 0xc3, 0x7a, 0x31, 0xd3, 0xa0, 0xfc, 0x59, 0x91, 0xba, 0x61, 0x15, 0xe2, 0x5a, 0x4b, 0x2a, 0xc3, 0xa6, - 0xc6, 0x96, 0xb4, 0xbe, 0x15, 0x50, 0xd2, 0xfe, 0x4a, 0x6f, 0x50, 0x38, 0x7e, 0xc0, 0xf3, 0x25, 0x20, 0x34, 0xc1, - 0x67, 0x37, 0x55, 0x10, 0x00, 0xdd, 0x8d, 0x13, 0x05, 0xc5, 0x69, 0xef, 0xe0, 0x9f, 0xb0, 0xef, 0xd0, 0x3f, 0xac, - 0x01, 0xa0, 0x39, 0x71, 0x2a, 0xd6, 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, 0x13, 0x05, 0xc5, 0x69, 0x89, 0x45, 0x06, - 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, - 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0x3f, 0xad, 0xef, 0xd0, 0xdf, 0xa8, 0xf2, 0x50, 0xe2, - 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, - 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x07, 0x01, - 0x01, 0xb7, 0x07, 0x00, 0x01, 0x13, 0x07, 0x17, 0x10, 0x98, 0xd3, 0x37, 0x07, 0x03, 0x04, 0x09, 0x07, 0xd8, 0xd3, - 0x13, 0x07, 0x50, 0x60, 0x98, 0xd7, 0x37, 0x17, 0x09, 0x00, 0x13, 0x07, 0x77, 0x80, 0xd8, 0xd7, 0x37, 0x17, 0x0b, - 0x0b, 0x13, 0x07, 0xa7, 0xa0, 0x98, 0xdb, 0x37, 0x17, 0x0c, 0x00, 0x13, 0x07, 0xb7, 0xc0, 0xd8, 0xdb, 0x37, 0x17, - 0x0f, 0x00, 0x13, 0x07, 0xd7, 0xe0, 0x98, 0xdf, 0x05, 0x67, 0xd8, 0xdf, 0xb7, 0x17, 0xff, 0x7f, 0x93, 0x87, 0x07, - 0x80, 0x73, 0xa0, 0x47, 0x30, 0xa1, 0x47, 0x73, 0xa0, 0x07, 0x30, 0x82, 0x80, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, - 0xfa, 0xa7, 0xdf, 0xe3, 0x6f, 0x1f, 0x27, 0xc4, 0xb4, 0x23, 0x41, 0x8d, 0xb3, 0x9a, 0xf0, 0xe8, 0x23, 0x52, 0xdf, - 0xf5, 0x4e, 0x5a, 0x24, 0x0c, 0xbd, 0x11, 0xdd, 0x0f, 0xce, 0x1c, 0xd8, 0xa8, 0x15, 0x28, 0x39, 0x40, 0x00, 0x73, - 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x80, 0x00, - 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x00, - 0x04, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, - 0x00, 0x20, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x05, 0x65, 0x6f, 0x10, 0xa0, - 0x54, 0x05, 0x65, 0x6f, 0x10, 0x00, 0x55, 0x01, 0x11, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x06, 0xce, 0x26, 0xca, - 0x52, 0xc4, 0x56, 0xc2, 0x9d, 0x47, 0x2a, 0x84, 0xae, 0x89, 0x32, 0x89, 0x63, 0xd4, 0xc7, 0x00, 0xef, 0xd0, 0x2f, - 0xae, 0xef, 0xf0, 0x5f, 0xfd, 0xb7, 0x07, 0x01, 0x07, 0x18, 0x40, 0xdc, 0x43, 0x93, 0x06, 0xf0, 0x0f, 0x63, 0x05, - 0xd7, 0x00, 0xf1, 0x9b, 0x0d, 0x8b, 0xd9, 0x8f, 0x13, 0xf7, 0xb7, 0xff, 0x83, 0x47, 0x44, 0x00, 0x81, 0x44, 0x31, - 0x4a, 0x8a, 0x07, 0x91, 0x8b, 0xd9, 0x8f, 0x37, 0x07, 0x01, 0x07, 0x5c, 0xc3, 0xb7, 0x1a, 0x01, 0x07, 0x63, 0xcf, - 0x24, 0x03, 0x14, 0x40, 0x05, 0x47, 0xad, 0x47, 0x63, 0x9e, 0xe6, 0x00, 0x83, 0x46, 0x44, 0x00, 0x13, 0x07, 0xa0, - 0x0a, 0xbd, 0x47, 0x63, 0x97, 0xe6, 0x00, 0x14, 0x44, 0x37, 0x37, 0x20, 0x00, 0x23, 0x22, 0xd7, 0xf8, 0xf2, 0x40, - 0x62, 0x44, 0x37, 0x07, 0xfa, 0xf7, 0xe0, 0x1d, 0x32, 0x97, 0x3d, 0xae, 0x6c, 0x96, 0xc3, 0xf5, 0x4e, 0x47, 0x73, - 0x53, 0x67, 0x9e, 0x5f, 0xfe, 0x2b, 0xa4, 0x54, 0x4f, 0x7e, 0x9e, 0x92, 0x99, 0xe2, 0x41, 0xf2, 0x1f, 0xa2, 0x00, - 0x3a, 0x01, 0x07, 0x5c, 0xc7, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, - 0xb3, 0x85, 0x44, 0x03, 0x13, 0x95, 0x44, 0x00, 0x31, 0x46, 0x56, 0x95, 0x85, 0x04, 0xce, 0x95, 0xef, 0xf0, 0xcf, - 0x81, 0x7d, 0xb7, 0x1d, 0x71, 0x3e, 0xda, 0xb7, 0x07, 0x01, 0x07, 0xa2, 0xc6, 0x80, 0x47, 0x86, 0xce, 0x96, 0xcc, - 0x9a, 0xca, 0x9e, 0xc8, 0xaa, 0xc4, 0xae, 0xc2, 0xb2, 0xc0, 0x36, 0xde, 0x3a, 0xdc, 0x42, 0xd8, 0x46, 0xd6, 0x72, - 0xd4, 0x76, 0xd2, 0x7a, 0xd0, 0x7e, 0xce, 0x93, 0x77, 0xb4, 0x00, 0x95, 0xc7, 0xb7, 0x07, 0x00, 0x40, 0x73, 0xb0, - 0x47, 0x30, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0xa2, 0x86, 0x13, 0x06, 0x06, - 0x6a, 0x93, 0x85, 0x85, 0x6a, 0x13, 0x05, 0x45, 0x64, 0xef, 0xe0, 0xbf, 0x87, 0xef, 0xd0, 0xbf, 0x8a, 0x93, 0x77, - 0x44, 0x00, 0x99, 0xcf, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf8, 0x91, 0xcb, 0x6c, 0x00, 0x28, 0x00, 0x82, - 0x97, 0x22, 0x47, 0xb7, 0x07, 0x01, 0x07, 0x98, 0xcb, 0x32, 0x47, 0xd8, 0xcb, 0xb7, 0x07, 0x01, 0x07, 0x80, 0xc7, - 0x36, 0x44, 0xf6, 0x40, 0xe6, 0x42, 0x56, 0x43, 0xc6, 0x43, 0x26, 0x45, 0x96, 0x45, 0x06, 0x46, 0xf2, 0x56, 0x62, - 0x57, 0xd2, 0x57, 0x42, 0x58, 0xb2, 0x58, 0x22, 0x5e, 0x92, 0x5e, 0x02, 0x5f, 0xf2, 0x4f, 0x25, 0x61, 0x73, 0x00, - 0x20, 0x30, 0xb7, 0x07, 0x02, 0x04, 0xdc, 0x47, 0xfa, 0x19, 0x45, 0xed, 0xe7, 0x3e, 0x51, 0x13, 0x28, 0x15, 0x3d, - 0x26, 0x00, 0x90, 0x1d, 0xbc, 0x68, 0xc7, 0x3d, 0x17, 0x7c, 0x65, 0xa8, 0x59, 0x68, 0xa1, 0x7f, 0x10, 0xaf, 0xb6, - 0xd3, 0x94, 0xba, 0xd8, 0x3a, 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, - 0x13, 0x05, 0x00, 0x08, 0x6f, 0x10, 0x40, 0x3d, 0x13, 0x05, 0x00, 0x08, 0x6f, 0x10, 0x80, 0x3d, 0x41, 0x11, 0x22, - 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x07, 0xd0, 0x79, 0x37, 0x04, 0x02, 0x04, 0x5c, 0xc4, 0x85, 0x44, 0x95, 0x65, - 0x37, 0x35, 0x10, 0x00, 0x04, 0xc4, 0x93, 0x85, 0x05, 0xe2, 0x13, 0x05, 0x25, 0x6d, 0xef, 0xe0, 0x7f, 0xca, 0x93, - 0x07, 0xa0, 0x0a, 0x63, 0x13, 0xf5, 0x02, 0x54, 0x44, 0x63, 0x82, 0x96, 0x02, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, - 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x6a, 0x93, 0x85, 0x45, 0x6b, 0x13, 0x05, 0x05, 0x62, 0xef, - 0xe0, 0x0f, 0xfb, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, - 0x06, 0xc6, 0xef, 0xf0, 0xdf, 0xf8, 0xb2, 0x40, 0xb7, 0x07, 0x02, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x41, 0x01, 0x82, - 0x80, 0x41, 0x11, 0x05, 0x45, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xef, 0xe0, 0x3f, 0xbf, 0xb7, 0x37, 0x20, 0x00, - 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa4, 0xe7, 0xf8, 0x89, 0x46, 0x37, 0x07, 0x02, 0x02, 0x54, 0xc7, 0x13, 0x84, 0x87, - 0xf8, 0x93, 0x04, 0x50, 0x05, 0xef, 0xe0, 0x9f, 0xc2, 0x1c, 0x40, 0xe3, 0x9d, 0x97, 0xfe, 0xb2, 0x40, 0x22, 0x44, - 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x02, 0x02, 0xc8, 0xcb, 0xfa, 0x86, 0xb6, 0x29, 0x76, 0xdd, 0x40, - 0xe6, 0xef, 0xde, 0x66, 0x81, 0xc3, 0xea, 0x0c, 0xbb, 0xf7, 0xf2, 0x63, 0xe0, 0xc8, 0x05, 0xc7, 0x20, 0xaa, 0xde, - 0x27, 0xdb, 0x4f, 0x80, 0x0b, 0xc1, 0x21, 0xb0, 0x3b, 0x05, 0x47, 0xd8, 0xc7, 0xd8, 0x53, 0x69, 0x8f, 0x63, 0x1e, - 0xa7, 0x00, 0xd4, 0x57, 0x7d, 0x55, 0xf9, 0x8e, 0x91, 0xea, 0x94, 0x57, 0x75, 0x8f, 0x19, 0xe7, 0x88, 0x47, 0x05, - 0x89, 0x33, 0x05, 0xa0, 0x40, 0x82, 0x80, 0x7d, 0x55, 0x82, 0x80, 0x41, 0x45, 0x6f, 0x10, 0x00, 0x2f, 0x41, 0x45, - 0x6f, 0x10, 0xe0, 0x2d, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, 0x2a, 0xc6, 0xef, 0xf0, 0x3f, 0xff, 0x13, 0x07, 0x50, - 0x05, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0xe7, 0xf8, 0x37, 0x04, 0x02, 0x02, 0xa1, 0x47, 0x5c, 0xc4, 0x32, 0x45, - 0x85, 0x47, 0x1c, 0xc8, 0x93, 0x07, 0x10, 0x40, 0x5c, 0xc0, 0xef, 0xf0, 0xbf, 0xf9, 0xef, 0xf0, 0x9f, 0xf5, 0x23, - 0x22, 0x04, 0x00, 0x62, 0x44, 0xf2, 0x40, 0x05, 0x61, 0x6f, 0xf0, 0x7f, 0xfb, 0x41, 0x11, 0x3a, 0xc6, 0x37, 0x07, - 0x02, 0x02, 0x3e, 0xc4, 0x1c, 0x47, 0x1c, 0xc7, 0x85, 0x8b, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, - 0x05, 0x23, 0xa4, 0xe7, 0xf8, 0x32, 0x47, 0xa2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x37, 0x20, 0x00, - 0x03, 0xa5, 0xc7, 0xf8, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x99, - 0xc3, 0xef, 0xd0, 0x6f, 0x81, 0x89, 0x67, 0x63, 0x64, 0xf4, 0x00, 0xef, 0xd0, 0xcf, 0x80, 0x37, 0x27, 0x00, 0x06, - 0x85, 0x46, 0x09, 0x46, 0x1c, 0x47, 0x9d, 0x8b, 0x63, 0x86, 0xd7, 0x00, 0x1c, 0x47, 0x9d, 0x8b, 0xfa, 0x97, 0x2b, - 0xd6, 0x83, 0xbc, 0x49, 0xb7, 0xeb, 0x87, 0x28, 0x24, 0x67, 0x9d, 0x8e, 0x0d, 0x2d, 0xf9, 0xde, 0x55, 0xeb, 0x7a, - 0x15, 0xf8, 0x63, 0x7d, 0x4e, 0xd6, 0x23, 0xe1, 0xc4, 0x4a, 0x8b, 0x88, 0x3c, 0xe3, 0x9a, 0xc7, 0xfe, 0x37, 0x05, - 0x00, 0x06, 0x2a, 0x94, 0x08, 0x40, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x65, 0xb7, 0x37, 0x20, - 0x00, 0x13, 0x07, 0x50, 0x05, 0x41, 0x11, 0x13, 0x05, 0x05, 0x80, 0x23, 0xa6, 0xe7, 0xf8, 0x06, 0xc6, 0xef, 0x10, - 0xc0, 0x20, 0xb7, 0x27, 0x00, 0x06, 0x9c, 0x47, 0x05, 0x47, 0x9d, 0x8b, 0xfd, 0x17, 0x63, 0x7b, 0xf7, 0x00, 0x37, - 0x55, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0x85, 0x6b, 0xef, 0xe0, 0xaf, 0xe9, 0xef, 0xc0, 0x9f, 0xfa, 0xb7, 0x07, - 0x46, 0x00, 0xb2, 0x40, 0x37, 0x27, 0x00, 0x06, 0x85, 0x07, 0x5c, 0xcf, 0x85, 0x47, 0x5c, 0xc7, 0x41, 0x01, 0x82, - 0x80, 0x37, 0x27, 0x00, 0x06, 0x1c, 0x47, 0x85, 0x46, 0x9d, 0x8b, 0x63, 0x8a, 0xd7, 0x00, 0x14, 0xcb, 0xb7, 0x26, - 0x00, 0x06, 0x05, 0x47, 0x9c, 0x46, 0x9d, 0x8b, 0xe3, 0x9e, 0xe7, 0xfe, 0xb7, 0x27, 0x00, 0x06, 0x09, 0x47, 0x05, - 0x65, 0x98, 0xcb, 0x13, 0x05, 0x05, 0x80, 0x6f, 0x10, 0x00, 0x1b, 0x05, 0x65, 0x41, 0x11, 0x13, 0x05, 0x05, 0x80, - 0x06, 0xc6, 0xef, 0x10, 0x60, 0x19, 0xb2, 0x40, 0xb7, 0x27, 0x00, 0x06, 0x21, 0x47, 0x98, 0xcb, 0x41, 0x01, 0x82, - 0x80, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0xaa, 0x84, 0xef, 0xf0, 0x5f, 0xf1, 0x2a, 0x84, 0x49, 0x22, - 0x13, 0x75, 0xf5, 0x0f, 0xef, 0xe0, 0x1f, 0xa6, 0x26, 0x85, 0xef, 0xf0, 0x3f, 0xf0, 0x63, 0x05, 0xa4, 0x00, 0xef, - 0xc0, 0xfa, 0xcd, 0x41, 0x9d, 0xf9, 0xdf, 0xe1, 0xa5, 0x5e, 0xff, 0xb2, 0x14, 0x2c, 0x6a, 0x99, 0xdd, 0x93, 0x5e, - 0x2f, 0x59, 0xea, 0x92, 0x3c, 0xca, 0x18, 0xcf, 0xd8, 0xf6, 0x06, 0x4c, 0x14, 0xf0, 0x52, 0x60, 0x3d, 0xff, 0xf1, - 0x01, 0x45, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, - 0xd0, 0x4e, 0xce, 0x06, 0xd6, 0x52, 0xcc, 0xaa, 0x89, 0x2e, 0x89, 0x93, 0x74, 0xc6, 0xff, 0x01, 0x44, 0x33, 0x8a, - 0x89, 0x00, 0x33, 0x05, 0x89, 0x00, 0x63, 0x1a, 0x94, 0x00, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, - 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0xef, 0xf0, 0x9f, 0xf9, 0x2a, 0xc6, 0x11, 0x46, 0x6c, 0x00, 0x52, 0x85, - 0xef, 0x10, 0x50, 0x1d, 0x11, 0x04, 0xc9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x1f, 0xf8, 0x2a, 0x87, 0x85, - 0x46, 0x01, 0x45, 0x89, 0x45, 0x01, 0xe7, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x93, 0x77, 0xf7, 0x00, 0x01, 0x46, - 0x81, 0xef, 0x63, 0xd3, 0xc5, 0x00, 0xb6, 0x87, 0x5d, 0x8d, 0x86, 0x06, 0x13, 0x75, 0xf5, 0x0f, 0x93, 0xf6, 0xf6, - 0x0f, 0x11, 0x83, 0xf1, 0xbf, 0x13, 0xf8, 0x17, 0x00, 0x85, 0x83, 0x42, 0x96, 0x93, 0xf7, 0xf7, 0x0f, 0xf1, 0xbf, - 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0xae, 0x84, 0x99, 0xc3, 0xef, - 0xc0, 0x1f, 0xe7, 0x89, 0x67, 0x63, 0x64, 0xf4, 0x00, 0xef, 0xc0, 0x7f, 0xe6, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, - 0x50, 0x05, 0x23, 0xa6, 0xe7, 0xf8, 0xb7, 0x27, 0x00, 0x06, 0x84, 0xcf, 0xc0, 0xcb, 0x22, 0x44, 0xb2, 0x40, 0x92, - 0x44, 0x11, 0x47, 0x98, 0xcb, 0xfa, 0xd4, 0xee, 0x37, 0x60, 0x30, 0x32, 0xaa, 0xc3, 0xdc, 0xd8, 0xd4, 0x0d, 0x91, - 0x28, 0xe5, 0x75, 0x0d, 0x3c, 0x6c, 0x96, 0xdc, 0xd9, 0xac, 0xaa, 0x0d, 0x26, 0x5f, 0xce, 0xa6, 0x27, 0xf2, 0xf0, - 0x38, 0x3e, 0x89, 0x65, 0x37, 0x45, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0xe5, 0x84, 0x41, 0x01, 0x6f, - 0xe0, 0xdf, 0xa4, 0x39, 0x71, 0x3a, 0xce, 0x37, 0x27, 0x00, 0x06, 0x3e, 0xcc, 0x1c, 0x47, 0x06, 0xde, 0x16, 0xdc, - 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, - 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xa1, 0x8b, 0x85, 0xcf, 0xa1, 0x47, 0x1c, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, - 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf8, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, - 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, - 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x85, 0x6b, 0xef, 0xe0, 0x2f, - 0xcb, 0xef, 0xd0, 0xcf, 0xc6, 0xe1, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa8, 0xa7, 0xf8, 0x82, 0x80, 0xb7, 0x37, - 0x20, 0x00, 0x93, 0x87, 0x07, 0xf9, 0x88, 0x43, 0x37, 0x67, 0x19, 0x00, 0x13, 0x07, 0xd7, 0x60, 0x33, 0x05, 0xe5, - 0x02, 0x37, 0xf7, 0x6e, 0x3c, 0x13, 0x07, 0xf7, 0x35, 0x3a, 0x95, 0x88, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, - 0x83, 0xa7, 0x47, 0xf9, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0x87, 0xf9, 0x9c, 0x4f, 0x13, 0x05, 0xa0, 0x0a, 0xf9, - 0x8f, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0xc7, 0xf9, 0xfa, 0xa1, 0xb7, 0xd6, 0xda, 0x57, 0x0d, 0x3a, 0x43, 0xed, - 0x10, 0x23, 0x8e, 0xcd, 0x34, 0xf6, 0x49, 0x1d, 0xa6, 0x0d, 0xdd, 0xc1, 0xcb, 0xc4, 0xde, 0x54, 0x9e, 0x41, 0x60, - 0xf8, 0x40, 0x8d, 0x56, 0x10, 0x3f, 0x63, 0x84, 0xe7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xfd, 0x77, 0xfd, - 0x17, 0xe9, 0x8f, 0xb7, 0x26, 0x00, 0x08, 0x2e, 0x87, 0xb2, 0x85, 0x63, 0x94, 0xd7, 0x02, 0xb7, 0x37, 0x20, 0x00, - 0x23, 0xaa, 0xa7, 0xf8, 0xb7, 0x37, 0x20, 0x00, 0x37, 0x45, 0x10, 0x00, 0x23, 0xae, 0xe7, 0xf8, 0x13, 0x05, 0x05, - 0xaf, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0xe7, 0xf8, 0x6f, 0xe0, 0x5f, 0x87, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, - 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0xa7, 0xf8, 0xb7, 0x37, 0x20, 0x00, 0x37, 0x45, 0x10, 0x00, 0x23, 0xae, 0x07, - 0xf8, 0x13, 0x07, 0x00, 0x10, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x05, 0x80, 0x3e, 0x13, 0x05, 0x05, 0xaf, 0x23, 0xac, - 0xe7, 0xf8, 0x6f, 0xe0, 0x3f, 0x84, 0x37, 0x07, 0x01, 0x02, 0x5c, 0x43, 0xb7, 0x06, 0x05, 0x00, 0xd5, 0x8f, 0x5c, - 0xc3, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0xb7, 0x27, 0x00, 0x08, 0x37, 0x05, 0x08, 0x00, - 0x63, 0x14, 0xf4, 0x00, 0x37, 0x05, 0x04, 0x00, 0xef, 0x00, 0x50, 0x71, 0x5c, 0x5c, 0x22, 0x85, 0xb2, 0x40, 0x93, - 0xe7, 0x37, 0x00, 0x5c, 0xdc, 0x23, 0x2c, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0x5f, 0xf9, 0x58, 0x5d, - 0xaa, 0x87, 0x75, 0x9b, 0x58, 0xdd, 0x37, 0x27, 0x00, 0x08, 0x37, 0x05, 0x04, 0x00, 0x63, 0x84, 0xe7, 0x00, 0x37, - 0x05, 0x08, 0x00, 0x6f, 0x00, 0xd0, 0x6e, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0xfa, 0x6a, 0x4e, 0x1e, 0xbd, 0x88, - 0xd6, 0xc1, 0x81, 0x57, 0x43, 0x8c, 0x9e, 0xc7, 0xe8, 0x48, 0x8b, 0x81, 0x91, 0x86, 0xca, 0xc6, 0x9d, 0xba, 0xe4, - 0x37, 0x8f, 0x6a, 0x81, 0xae, 0xa5, 0x37, 0xff, 0xe8, 0x3f, 0x4a, 0xd0, 0x06, 0xd6, 0x4e, 0xce, 0x52, 0xcc, 0x56, - 0xca, 0x2a, 0x89, 0xae, 0x84, 0x32, 0x84, 0x99, 0xe1, 0xef, 0xc0, 0x3f, 0xc8, 0x13, 0x0a, 0xa0, 0x0a, 0x91, 0x4a, - 0x05, 0xe4, 0x83, 0x27, 0x89, 0x01, 0x37, 0x07, 0x11, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x99, 0xc3, 0x13, - 0x05, 0x50, 0x05, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0xd2, 0x4a, 0x45, 0x61, - 0x82, 0x80, 0x13, 0x06, 0x80, 0x3e, 0x85, 0x45, 0x4a, 0x85, 0xef, 0xf0, 0x7f, 0xee, 0xe3, 0x1f, 0x45, 0xfd, 0x83, - 0x27, 0x49, 0x02, 0xa2, 0x89, 0x3e, 0xc6, 0x63, 0xf3, 0x8a, 0x00, 0x91, 0x49, 0x26, 0x85, 0x4e, 0x86, 0x6c, 0x00, - 0xef, 0x10, 0x20, 0x73, 0xce, 0x94, 0x33, 0x04, 0x34, 0x41, 0x6d, 0xb7, 0x41, 0x11, 0x37, 0x05, 0x02, 0x00, 0x06, - 0xc6, 0xef, 0x00, 0xb0, 0x65, 0xb2, 0x40, 0xb7, 0x17, 0x00, 0x08, 0x37, 0x07, 0x07, 0x00, 0x98, 0xd3, 0x13, 0x05, - 0x40, 0x1f, 0x41, 0x01, 0x6f, 0xe0, 0xef, 0xee, 0xb7, 0x17, 0x00, 0x08, 0x23, 0xa0, 0x07, 0x02, 0x37, 0x05, 0x02, - 0x00, 0x6f, 0x00, 0x10, 0x64, 0x39, 0x71, 0x3e, 0xcc, 0xb7, 0x17, 0x00, 0x08, 0x3a, 0xce, 0x98, 0x57, 0x06, 0xde, - 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, - 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0x05, 0x8b, 0x05, 0xcb, 0x98, 0x57, 0x13, 0x67, 0x17, 0x00, 0xfa, 0xf9, - 0xc6, 0xcf, 0x87, 0x82, 0xf6, 0x72, 0x87, 0xe8, 0xae, 0x19, 0x50, 0x52, 0x4c, 0x9c, 0x8a, 0x44, 0x26, 0x36, 0xcc, - 0xdf, 0xa9, 0xcf, 0x8d, 0xe5, 0x78, 0x21, 0x02, 0x35, 0xa0, 0x9b, 0x58, 0xc0, 0x40, 0x98, 0xd7, 0xf2, 0x50, 0xe2, - 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, - 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x98, 0x57, 0x09, - 0x8b, 0x09, 0xc7, 0x98, 0x57, 0x13, 0x67, 0x27, 0x00, 0xf1, 0xb7, 0x98, 0x57, 0x11, 0x8b, 0x09, 0xc7, 0x98, 0x57, - 0x13, 0x67, 0x47, 0x00, 0x7d, 0xbf, 0xb7, 0x07, 0x00, 0x01, 0x73, 0xb0, 0x47, 0x30, 0xef, 0xd0, 0xcf, 0xa1, 0x4d, - 0xbf, 0x37, 0x07, 0x00, 0x02, 0x5c, 0x4f, 0xb7, 0x36, 0x20, 0x00, 0x13, 0xf6, 0x77, 0x00, 0xe1, 0x9b, 0x23, 0xa0, - 0xc6, 0xfa, 0x93, 0xe7, 0x47, 0x00, 0x5c, 0xcf, 0x1c, 0x4f, 0xf9, 0x9b, 0x1c, 0xcf, 0x82, 0x80, 0x41, 0x11, 0x26, - 0xc2, 0xb7, 0x04, 0x00, 0x02, 0x22, 0xc4, 0xc0, 0x4c, 0x9c, 0x4c, 0x06, 0xc6, 0x13, 0x05, 0x80, 0x07, 0x93, 0xe7, - 0x17, 0x00, 0x9c, 0xcc, 0xef, 0xe0, 0xaf, 0xe1, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xfa, 0x61, 0x98, 0xb2, - 0x40, 0x5d, 0x8c, 0xc0, 0xcc, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x17, 0x05, 0x01, 0x93, 0x17, - 0x85, 0x01, 0xba, 0x97, 0x13, 0x17, 0x85, 0x00, 0xba, 0x97, 0x3e, 0x95, 0xb7, 0x07, 0x00, 0x04, 0x88, 0xd3, 0xc8, - 0xd3, 0x88, 0xd7, 0xc8, 0xd7, 0x88, 0xdb, 0xc8, 0xdb, 0x88, 0xdf, 0xc8, 0xdf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, - 0x13, 0x07, 0xfa, 0xf6, 0xaf, 0xe3, 0x8b, 0x16, 0x97, 0x79, 0xba, 0x00, 0xb6, 0x72, 0xe3, 0xd3, 0x75, 0x00, 0x35, - 0x94, 0xbe, 0xa6, 0x3e, 0x52, 0x9a, 0x9f, 0x00, 0x3a, 0xdc, 0x64, 0x32, 0xfd, 0xa3, 0xd7, 0x9d, 0x98, 0x41, 0x00, - 0x08, 0x98, 0xd3, 0x23, 0xa2, 0x07, 0x02, 0x0e, 0x05, 0x23, 0xa4, 0x07, 0x02, 0x42, 0x05, 0x23, 0xa6, 0x07, 0x02, - 0x41, 0x81, 0x23, 0xa8, 0x07, 0x02, 0x13, 0x17, 0x85, 0x00, 0xb7, 0x06, 0xff, 0x00, 0x23, 0xaa, 0x07, 0x02, 0x75, - 0x8f, 0x62, 0x05, 0x23, 0xac, 0x07, 0x02, 0x3a, 0x95, 0xc8, 0xdf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, - 0x00, 0x08, 0x98, 0xd3, 0x23, 0xa2, 0x07, 0x02, 0x23, 0xa4, 0x07, 0x02, 0x23, 0xa6, 0x07, 0x02, 0x23, 0xa8, 0x07, - 0x02, 0x23, 0xaa, 0x07, 0x02, 0x23, 0xac, 0x07, 0x02, 0x23, 0xae, 0x07, 0x02, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, - 0x03, 0xa5, 0x47, 0xea, 0x82, 0x80, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, 0x05, - 0x02, 0x6f, 0xe0, 0x3f, 0x83, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa2, 0xe7, 0xea, 0xb7, 0x07, - 0x00, 0x04, 0xc8, 0xc3, 0x13, 0x07, 0x90, 0x02, 0x85, 0x65, 0x37, 0x45, 0x10, 0x00, 0x98, 0xc7, 0x93, 0x85, 0x85, - 0x38, 0x13, 0x05, 0x45, 0xdf, 0x6f, 0xe0, 0xaf, 0xd8, 0x41, 0x11, 0x22, 0xc4, 0x01, 0x45, 0x37, 0x34, 0x20, 0x00, - 0x06, 0xc6, 0x13, 0x04, 0x44, 0xe9, 0xef, 0xf0, 0x1f, 0xf2, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, - 0xf0, 0xbf, 0xfb, 0x48, 0x44, 0xb7, 0x07, 0x02, 0x00, 0x95, 0x07, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0xbf, 0xfa, - 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0xfa, 0x4d, 0xfd, 0x84, 0x4a, 0xaa, 0xf8, 0x55, 0xcd, 0x6c, 0x63, 0x8f, 0x5e, - 0x04, 0xd6, 0xd4, 0x86, 0x21, 0xdf, 0xf3, 0xf9, 0x31, 0x08, 0x50, 0x8f, 0x7c, 0x8c, 0xe7, 0x33, 0xc8, 0x5f, 0x53, - 0x00, 0x70, 0x42, 0x05, 0x05, 0xef, 0xf0, 0xff, 0xf9, 0x48, 0x44, 0xb7, 0x07, 0x00, 0x10, 0x99, 0x07, 0x7e, 0x05, - 0x5d, 0x8d, 0xef, 0xf0, 0xff, 0xf8, 0x48, 0x44, 0xb7, 0x07, 0x01, 0x10, 0x99, 0x07, 0x7e, 0x05, 0x5d, 0x8d, 0xef, - 0xf0, 0xff, 0xf7, 0x22, 0x44, 0xb2, 0x40, 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0xf7, 0x7d, 0x47, 0x63, 0x7e, - 0xb7, 0x04, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0x6f, 0xe0, 0x8f, - 0xf8, 0xb3, 0x06, 0xf5, 0x00, 0x83, 0xc6, 0x06, 0x00, 0x33, 0x07, 0xf1, 0x00, 0x85, 0x07, 0x23, 0x00, 0xd7, 0x00, - 0xe3, 0x97, 0xf5, 0xfe, 0x18, 0x10, 0x93, 0x87, 0x15, 0x00, 0xba, 0x95, 0x13, 0x07, 0x00, 0xf8, 0x23, 0x80, 0xe5, - 0xfe, 0x13, 0x07, 0x00, 0x02, 0x63, 0x92, 0xe7, 0x02, 0x37, 0x05, 0x00, 0x04, 0x8a, 0x85, 0x13, 0x06, 0x00, 0x02, - 0x13, 0x05, 0x05, 0x02, 0xef, 0xe0, 0x8f, 0xf4, 0xb2, 0x50, 0x45, 0x61, 0x82, 0x80, 0x79, 0x71, 0x06, 0xd6, 0x81, - 0x47, 0xd9, 0xb7, 0xb3, 0x06, 0xf1, 0x00, 0x23, 0x80, 0x06, 0x00, 0x85, 0x07, 0xc9, 0xbf, 0x37, 0x55, 0x10, 0x00, - 0x01, 0x11, 0x13, 0x05, 0x45, 0x6c, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x37, - 0x34, 0x20, 0x00, 0xef, 0xf0, 0x1f, 0xed, 0x93, 0x07, 0x44, 0xe9, 0xc8, 0x47, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, - 0xef, 0xf0, 0x3f, 0xed, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x10, 0xfa, 0x80, 0xd8, 0xd2, 0x68, 0x15, 0x02, 0x76, 0x98, - 0xb9, 0x89, 0x46, 0x0c, 0xd4, 0xef, 0xd3, 0xde, 0x43, 0x99, 0xa1, 0x4e, 0x6d, 0x1b, 0xd9, 0x7f, 0x6a, 0xfb, 0x52, - 0x60, 0x97, 0x21, 0x21, 0x71, 0x48, 0x43, 0xf5, 0x2e, 0xaa, 0x84, 0x13, 0x05, 0x00, 0x02, 0xef, 0xf0, 0x3f, 0xe4, - 0x13, 0x04, 0x44, 0xe9, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x1f, 0xeb, 0xaa, 0x89, 0x63, - 0x10, 0x95, 0x2c, 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0xbf, 0xe9, - 0xaa, 0x84, 0x63, 0x15, 0x35, 0x2b, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x9f, 0xe8, 0xaa, - 0x89, 0x63, 0x1c, 0x95, 0x28, 0x1c, 0x40, 0x48, 0x44, 0x37, 0x0a, 0x00, 0x04, 0x83, 0xc7, 0x07, 0x00, 0x7e, 0x05, - 0x13, 0x65, 0x15, 0x00, 0x93, 0xe7, 0x07, 0x20, 0x23, 0x2c, 0xfa, 0x00, 0xef, 0xf0, 0x5f, 0xe6, 0xaa, 0x84, 0x63, - 0x1a, 0x35, 0x27, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x3f, 0xe5, 0x2a, 0x89, 0x63, 0x11, - 0x95, 0x26, 0xef, 0xf0, 0x5f, 0xe0, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xdf, 0xe3, 0xaa, - 0x84, 0x63, 0x16, 0x25, 0x25, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x1f, 0xdb, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, - 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xff, 0xe1, 0x2a, 0x89, 0x63, 0x17, 0x95, 0x22, 0x48, 0x44, 0x7e, - 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xdf, 0xe0, 0xaa, 0x84, 0x63, 0x1e, 0x25, 0x21, 0x48, 0x44, 0x7e, 0x05, - 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xbf, 0xdf, 0x63, 0x16, 0x95, 0x20, 0x48, 0x44, 0xfa, 0x15, 0x72, 0x62, 0x71, - 0x13, 0x81, 0x5b, 0x9e, 0xe3, 0xd8, 0x52, 0xf3, 0xef, 0x12, 0x00, 0x02, 0x6d, 0xaf, 0x13, 0x6a, 0xd2, 0x2d, 0xb4, - 0x63, 0x23, 0x41, 0x6e, 0x23, 0x57, 0x68, 0xc2, 0x7f, 0x20, 0x44, 0x93, 0x07, 0x00, 0x10, 0x23, 0x2c, 0xfa, 0x00, - 0x7e, 0x05, 0x13, 0x65, 0x15, 0x00, 0xef, 0xf0, 0x3f, 0xde, 0x93, 0x07, 0xa0, 0x0a, 0xaa, 0x84, 0x63, 0x17, 0xf5, - 0x1e, 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x9f, 0xdc, 0xaa, 0x89, - 0x63, 0x1c, 0x95, 0x1c, 0xef, 0xf0, 0xbf, 0xd7, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x3f, - 0xdb, 0xaa, 0x84, 0x63, 0x11, 0x35, 0x1d, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x7f, 0xd2, 0x48, 0x44, 0x23, 0x20, - 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x5f, 0xd9, 0xaa, 0x89, 0x63, 0x12, 0x95, 0x1a, 0x48, - 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x3f, 0xd8, 0xaa, 0x84, 0x63, 0x19, 0x35, 0x19, 0x48, 0x44, - 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x1f, 0xd7, 0xaa, 0x89, 0x63, 0x10, 0x95, 0x18, 0x08, 0x40, 0x05, - 0x05, 0xef, 0xf0, 0x1f, 0xd5, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x7f, 0xd5, 0xaa, 0x84, - 0x63, 0x13, 0x35, 0x17, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x5f, 0xd4, 0x2a, 0x89, 0x63, - 0x1a, 0x95, 0x14, 0xef, 0xf0, 0x7f, 0xcf, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xff, 0xd2, - 0xaa, 0x84, 0x63, 0x1f, 0x25, 0x13, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x3f, 0xca, 0x48, 0x44, 0x23, 0x20, 0xfa, - 0xea, 0x55, 0x06, 0x58, 0x77, 0x50, 0xaa, 0x9d, 0x15, 0x27, 0x63, 0x2b, 0x1e, 0xa2, 0xab, 0x09, 0x47, 0xd8, 0x92, - 0x1e, 0xa6, 0xd0, 0x0a, 0xfa, 0x58, 0x67, 0xf7, 0x90, 0x84, 0xd0, 0x2a, 0x2b, 0xf8, 0x44, 0x0a, 0x02, 0x7e, 0x05, - 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x1f, 0xd1, 0x63, 0x11, 0x95, 0x12, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, - 0x00, 0xef, 0xf0, 0x1f, 0xd0, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0x63, 0x16, 0xf5, 0x10, 0x48, 0x44, 0x7e, 0x05, - 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xbf, 0xce, 0xaa, 0x84, 0x63, 0x1d, 0x25, 0x0f, 0x13, 0x05, 0x10, 0x02, 0xef, - 0xf0, 0xff, 0xc5, 0x1c, 0x40, 0x48, 0x44, 0x21, 0x67, 0x83, 0xc7, 0x07, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, - 0xd9, 0x8f, 0x23, 0x20, 0xfa, 0x02, 0xef, 0xf0, 0x3f, 0xcc, 0xaa, 0x89, 0x63, 0x19, 0x95, 0x0c, 0x48, 0x44, 0x89, - 0x64, 0x8d, 0x04, 0x7e, 0x05, 0x45, 0x8d, 0xef, 0xf0, 0xff, 0xca, 0x2a, 0x89, 0x63, 0x1f, 0x35, 0x0b, 0x48, 0x44, - 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xdf, 0xc9, 0xaa, 0x89, 0x63, 0x16, 0x25, 0x0b, 0x08, 0x40, 0x13, - 0x05, 0x15, 0x02, 0xef, 0xf0, 0xbf, 0xc7, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x1f, 0xc8, - 0x2a, 0x89, 0x63, 0x18, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, 0x45, 0x8d, 0xef, 0xf0, 0x1f, 0xc7, 0xaa, 0x84, 0x63, - 0x10, 0x25, 0x09, 0xef, 0xf0, 0x3f, 0xc2, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0xc5, - 0x2a, 0x89, 0x63, 0x15, 0x95, 0x06, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0xff, 0xbc, 0x48, 0x44, 0x23, 0x20, 0x0a, - 0x02, 0x7e, 0x05, 0xfa, 0x90, 0x03, 0xeb, 0x09, 0x5a, 0xe9, 0x5d, 0xd5, 0x9b, 0xc6, 0x03, 0x55, 0x41, 0x8e, 0xe6, - 0x78, 0x37, 0x05, 0x10, 0x74, 0x1a, 0x20, 0x86, 0x04, 0x8e, 0xdd, 0x39, 0x7b, 0x7f, 0x7b, 0x4a, 0xd8, 0xd0, 0x45, - 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xc3, 0xaa, 0x84, 0x63, 0x16, 0x25, 0x05, 0x48, 0x44, 0x7e, 0x05, 0x13, - 0x65, 0x35, 0x00, 0xef, 0xf0, 0xbf, 0xc2, 0x63, 0x1e, 0x95, 0x02, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x52, - 0xef, 0xf0, 0xbf, 0xc1, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x14, 0xf5, 0x02, 0x08, 0x40, 0x62, 0x44, 0xf2, 0x40, 0xd2, - 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x06, - 0x13, 0x05, 0x15, 0x06, 0x05, 0x61, 0x6f, 0xe0, 0x0f, 0xbb, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, - 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x4e, 0xc6, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, - 0x52, 0xc4, 0x93, 0x09, 0x00, 0x04, 0x63, 0xeb, 0xb9, 0x08, 0x37, 0x3a, 0x20, 0x00, 0xaa, 0x84, 0x2e, 0x84, 0x13, - 0x09, 0x4a, 0xe9, 0xef, 0xf0, 0xbf, 0xc4, 0x03, 0x25, 0xc9, 0x00, 0x13, 0x0a, 0x4a, 0xe9, 0x7e, 0x05, 0x13, 0x65, - 0x05, 0x07, 0xef, 0xf0, 0x7f, 0xba, 0x13, 0x85, 0x04, 0x02, 0x63, 0x19, 0x34, 0x03, 0xaa, 0x85, 0x37, 0x05, 0x00, - 0x04, 0x13, 0x05, 0x05, 0x02, 0x13, 0x06, 0x00, 0x02, 0xef, 0xe0, 0xaf, 0xbb, 0x03, 0x25, 0xc9, 0x00, 0x62, 0x44, - 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0x05, 0x61, 0x6f, - 0xf0, 0x1f, 0xb7, 0xfd, 0x47, 0x63, 0xf8, 0xfa, 0xbc, 0x85, 0x10, 0x91, 0x20, 0xef, 0xcc, 0xb0, 0x91, 0x46, 0x83, - 0xa9, 0xf3, 0xf1, 0x73, 0xba, 0xc5, 0x74, 0xcd, 0xa3, 0xfe, 0xcc, 0x3c, 0x06, 0xd5, 0xb8, 0xac, 0xe8, 0x7c, 0x21, - 0xe8, 0xd2, 0xa8, 0x46, 0x87, 0x02, 0x93, 0x05, 0x04, 0xfe, 0xef, 0xf0, 0x5f, 0xbf, 0x13, 0x04, 0x04, 0x04, 0x0e, - 0x04, 0x42, 0x04, 0x41, 0x80, 0x93, 0x17, 0x84, 0x00, 0x37, 0x07, 0xff, 0x00, 0xf9, 0x8f, 0x62, 0x04, 0x3e, 0x94, - 0xb7, 0x07, 0x00, 0x04, 0x03, 0x25, 0xca, 0x00, 0xc0, 0xdf, 0x65, 0xbf, 0x01, 0x45, 0xef, 0xf0, 0x3f, 0xa9, 0xd9, - 0xbf, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, - 0x22, 0xcc, 0x37, 0x34, 0x20, 0x00, 0x93, 0x07, 0x44, 0xe9, 0x52, 0xc4, 0x2a, 0x8a, 0xc8, 0x47, 0x56, 0xc2, 0x06, - 0xce, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x30, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xae, 0x8a, 0xef, 0xf0, 0xff, 0xaf, - 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x11, 0xf5, 0x12, 0xaa, 0x84, 0x13, 0x05, 0x60, 0x03, 0xef, 0xf0, 0x7f, 0xa4, 0x13, - 0x04, 0x44, 0xe9, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x45, 0x00, 0xef, 0xf0, 0xdf, 0xad, 0x2a, 0x89, 0x63, 0x11, - 0x95, 0x10, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xbf, 0xac, 0xaa, 0x84, 0x63, 0x18, 0x25, - 0x0f, 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x5f, 0xab, 0xaa, 0x89, - 0x63, 0x1d, 0x95, 0x0c, 0xd6, 0x85, 0x52, 0x85, 0xef, 0xf0, 0xdf, 0xec, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, - 0x00, 0xef, 0xf0, 0xbf, 0xa9, 0xaa, 0x84, 0x63, 0x10, 0x35, 0x0d, 0xfa, 0xab, 0x09, 0x27, 0x1b, 0x55, 0x5e, 0xb7, - 0xc9, 0x30, 0x9f, 0x6c, 0x92, 0x16, 0x6d, 0x22, 0xa6, 0xd3, 0x01, 0xeb, 0x38, 0xc6, 0x3e, 0x44, 0x3c, 0x37, 0xaa, - 0xb3, 0x5d, 0xe2, 0x52, 0xf0, 0x6e, 0x80, 0x47, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x03, 0xef, 0xf0, 0x9f, - 0xa8, 0xaa, 0x89, 0x63, 0x17, 0x95, 0x0a, 0x13, 0x05, 0xc0, 0x05, 0xef, 0xf0, 0x5f, 0x9d, 0x48, 0x44, 0x7e, 0x05, - 0x13, 0x65, 0x45, 0x00, 0xef, 0xf0, 0xff, 0xa6, 0xaa, 0x84, 0x63, 0x1a, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, 0x13, - 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xa5, 0xaa, 0x89, 0x63, 0x11, 0x95, 0x08, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, - 0x05, 0x32, 0xef, 0xf0, 0xbf, 0xa4, 0xaa, 0x84, 0x63, 0x18, 0x35, 0x07, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, - 0x01, 0xef, 0xf0, 0x9f, 0xa3, 0x63, 0x10, 0x95, 0x06, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x03, 0xef, 0xf0, - 0x9f, 0xa2, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0x63, 0x15, 0xf5, 0x04, 0x13, 0x05, 0x00, 0x06, 0xef, 0xf0, 0x9f, - 0x99, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xbf, 0xa0, 0xaa, 0x84, 0x63, 0x18, 0x25, 0x03, - 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x9f, 0x9f, 0x63, 0x10, 0x95, 0x02, 0x48, 0x44, 0x62, - 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, - 0x05, 0x61, 0x6f, 0xf0, 0x9f, 0x9d, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, - 0x4a, 0x05, 0x61, 0x82, 0x80, 0x39, 0x71, 0x22, 0xdc, 0x37, 0x34, 0x20, 0x00, 0x06, 0xde, 0xfa, 0x02, 0xe1, 0xc9, - 0x92, 0x79, 0x5c, 0xcb, 0xdd, 0x01, 0xb4, 0x9e, 0x82, 0x4f, 0x49, 0xb3, 0x97, 0x6d, 0x99, 0xd3, 0x06, 0xf0, 0x3c, - 0xe9, 0x95, 0x01, 0x13, 0xeb, 0xdc, 0x5c, 0x7e, 0xc0, 0x40, 0x58, 0x48, 0x4a, 0xd8, 0x26, 0xda, 0x32, 0x89, 0x13, - 0x04, 0x44, 0xe9, 0xef, 0xf0, 0xdf, 0xe8, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x40, 0xef, 0xf0, 0x3f, 0x9a, - 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x0a, 0xaa, 0x84, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0xc5, - 0x6b, 0xef, 0xf0, 0x9f, 0xe6, 0x85, 0x47, 0x63, 0x07, 0xf9, 0x08, 0x48, 0x44, 0x85, 0x67, 0x93, 0x87, 0x07, 0x80, - 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0x5f, 0x97, 0x2a, 0x89, 0x63, 0x1c, 0x95, 0x06, 0xb7, 0x05, 0x00, 0x04, 0x13, - 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x04, 0x68, 0x00, 0xef, 0xe0, 0xef, 0x91, 0x48, 0x44, 0x89, 0x47, 0x23, 0x06, - 0xf1, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x20, 0xef, 0xf0, 0xbf, 0x94, 0xaa, 0x84, 0x63, 0x17, 0x25, 0x05, 0x48, - 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0x9f, 0x93, 0x2a, 0x89, 0x63, 0x1e, 0x95, 0x02, 0x48, 0x44, - 0x7e, 0x05, 0x13, 0x65, 0x05, 0x42, 0xef, 0xf0, 0x7f, 0x92, 0xaa, 0x84, 0x63, 0x15, 0x25, 0x03, 0x68, 0x00, 0x93, - 0x05, 0x10, 0x02, 0xef, 0xf0, 0x5f, 0xdf, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x10, 0xef, 0xf0, 0xbf, 0x90, - 0x63, 0x18, 0x95, 0x00, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xbf, 0x8f, 0xf2, 0x50, 0x62, - 0x54, 0xd2, 0x54, 0x42, 0x59, 0x21, 0x61, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, - 0xfa, 0xb9, 0xbb, 0x5f, 0xe7, 0xb7, 0x8d, 0xe1, 0xb9, 0xc7, 0x35, 0x55, 0x67, 0x8f, 0x3b, 0xc0, 0xc1, 0x5a, 0x87, - 0xd4, 0xa2, 0x90, 0x0b, 0xf8, 0x14, 0xca, 0xd0, 0x6a, 0xef, 0x0d, 0xef, 0x3d, 0xb0, 0x30, 0x49, 0x44, 0xe9, 0x08, - 0x40, 0x09, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x06, 0xc6, 0xef, 0xf0, 0xff, 0xf0, 0x48, 0x44, - 0x7e, 0x05, 0x13, 0x65, 0x05, 0x71, 0xef, 0xf0, 0x5f, 0x8c, 0x48, 0x44, 0x22, 0x44, 0xb2, 0x40, 0x7e, 0x05, 0x13, - 0x65, 0x05, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0x8b, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x47, 0xe9, 0x05, 0x46, - 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x6f, 0xf0, 0xbf, 0xed, 0x41, 0x11, 0xb7, 0x55, 0x10, 0x00, 0x37, - 0x05, 0x00, 0x04, 0x22, 0xc4, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x45, 0x6c, 0x13, 0x05, 0x05, 0x02, 0x37, 0x34, - 0x20, 0x00, 0x06, 0xc6, 0x13, 0x04, 0x44, 0xe9, 0xef, 0xe0, 0x4f, 0x8a, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, - 0x07, 0xef, 0xf0, 0xbf, 0x86, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x1d, 0xf5, 0x00, 0x08, 0x40, 0x22, 0x44, 0xb2, 0x40, - 0x05, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xe8, 0xb2, 0x40, 0x22, - 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x44, 0xe9, 0x48, 0x44, - 0x06, 0xc6, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xbf, 0x82, 0x08, 0x40, 0x13, 0x06, 0x00, 0x02, 0x81, - 0x45, 0x13, 0x05, 0x15, 0x04, 0xef, 0x00, 0x90, 0x5c, 0x08, 0x40, 0x09, 0x46, 0x81, 0x45, 0x13, 0x05, 0x15, 0x04, - 0xef, 0xf0, 0xbf, 0xe4, 0xfa, 0x18, 0x33, 0xd3, 0x14, 0xca, 0x58, 0x0a, 0x84, 0xb2, 0xd9, 0x9a, 0x2b, 0xb2, 0xdb, - 0xf9, 0xea, 0xab, 0x07, 0x45, 0x8e, 0x10, 0x06, 0xc1, 0x17, 0x86, 0x02, 0x2b, 0xf6, 0x28, 0x66, 0xac, 0xd9, 0x08, - 0x4a, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x60, 0xef, 0xf0, 0x1f, 0x80, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, - 0x05, 0x71, 0xef, 0xf0, 0x4f, 0xff, 0x01, 0x45, 0xef, 0xf0, 0x8f, 0xf4, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, - 0x07, 0xef, 0xf0, 0x2f, 0xfe, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x6f, 0xfd, 0xb2, 0x40, - 0x22, 0x44, 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, 0x98, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x11, 0x65, 0xad, 0xa9, 0x37, - 0x35, 0x20, 0x00, 0x41, 0x11, 0x51, 0x46, 0x81, 0x45, 0x13, 0x05, 0x45, 0xe9, 0x06, 0xc6, 0xef, 0x00, 0xd0, 0x55, - 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x1d, 0x65, 0x23, 0xa2, 0xe7, 0xfa, 0xa9, 0x21, 0xb2, 0x40, 0xb7, - 0x07, 0x00, 0x04, 0x05, 0x47, 0x98, 0xcb, 0x41, 0x01, 0x6f, 0xf0, 0xdf, 0xfc, 0x11, 0x65, 0x1d, 0xa9, 0x95, 0x47, - 0x63, 0xec, 0xb7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x44, 0xe9, 0x85, 0x47, 0x5c, - 0xc0, 0xb7, 0x57, 0x10, 0x00, 0x0c, 0xc4, 0x93, 0x87, 0x87, 0x6e, 0x8a, 0x05, 0xbe, 0x95, 0x9c, 0x41, 0x06, 0xc6, - 0x08, 0xc0, 0x82, 0x97, 0x08, 0x48, 0xb2, 0x40, 0x23, 0x22, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, - 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x05, 0x00, 0x04, 0x41, 0x46, 0x93, 0x85, 0x05, 0x08, 0x6f, 0xd0, 0xff, 0xef, - 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xe9, 0xfa, 0xe7, 0x1e, 0x39, 0x42, 0x20, 0x37, 0x3f, 0x9e, 0x0c, 0xf4, - 0xe2, 0x6b, 0x43, 0x12, 0xb1, 0x85, 0x4d, 0x1e, 0xe7, 0xde, 0x66, 0x08, 0x3a, 0xb4, 0x88, 0x45, 0x6a, 0x52, 0xdc, - 0x71, 0x2b, 0xf9, 0xe0, 0x4a, 0x89, 0x47, 0x5c, 0xc3, 0x5c, 0x47, 0x46, 0x05, 0xfe, 0x07, 0xc9, 0x8f, 0x21, 0x65, - 0x15, 0x05, 0x5d, 0x8d, 0x6f, 0xf0, 0xef, 0xf1, 0x39, 0x71, 0x4e, 0xd6, 0x5e, 0xce, 0x62, 0xcc, 0xb7, 0x0b, 0x00, - 0x04, 0xb7, 0x39, 0x20, 0x00, 0x05, 0x6c, 0x22, 0xdc, 0x26, 0xda, 0x4a, 0xd8, 0x56, 0xd2, 0x5a, 0xd0, 0x66, 0xca, - 0x6a, 0xc8, 0x06, 0xde, 0x52, 0xd4, 0x2a, 0x84, 0x2e, 0x8b, 0xb2, 0x8a, 0x81, 0x44, 0x01, 0x49, 0xc1, 0x4c, 0x93, - 0x8b, 0x0b, 0x02, 0x93, 0x89, 0x49, 0xe9, 0x09, 0x0c, 0x37, 0x3d, 0x20, 0x00, 0xb3, 0x05, 0x9b, 0x00, 0x63, 0xe0, - 0x54, 0x03, 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, - 0x4b, 0x62, 0x4c, 0xd2, 0x4c, 0x42, 0x4d, 0x21, 0x61, 0x82, 0x80, 0x33, 0x8a, 0x9a, 0x40, 0x63, 0xd3, 0x4c, 0x01, - 0x41, 0x4a, 0x4a, 0x85, 0x2e, 0xc6, 0xef, 0xe0, 0xcf, 0x9f, 0xb2, 0x45, 0x13, 0x06, 0x3a, 0x00, 0x71, 0x9a, 0x5e, - 0x85, 0xef, 0xd0, 0xbf, 0xec, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xef, 0xe8, - 0x03, 0xa5, 0xc9, 0x00, 0x93, 0x17, 0x8a, 0x01, 0x7e, 0x05, 0x5d, 0x8d, 0x13, 0x65, 0x75, 0x00, 0xef, 0xf0, 0xaf, - 0xe7, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x33, 0x65, 0x85, 0x01, 0xef, 0xf0, 0xcf, 0xe6, 0x03, 0x27, 0x4d, 0xfa, - 0x93, 0x07, 0x50, 0x05, 0x63, 0x19, 0xf7, 0x00, 0x19, 0xc4, 0x22, 0x85, 0xfa, 0x3c, 0xae, 0x19, 0xac, 0xfb, 0xb8, - 0x83, 0x52, 0x52, 0x69, 0x6e, 0x53, 0xf0, 0x45, 0x80, 0x19, 0x4e, 0x2a, 0x14, 0x04, 0x31, 0x97, 0x11, 0x25, 0x01, - 0xab, 0x18, 0x92, 0xe0, 0xa7, 0x95, 0xef, 0xb8, 0x4b, 0x52, 0x86, 0xca, 0x85, 0xef, 0xe0, 0x4f, 0xa3, 0x41, 0x04, - 0x93, 0x07, 0x00, 0x07, 0x63, 0xe3, 0x27, 0x01, 0x41, 0x09, 0xc1, 0x04, 0x9d, 0xb7, 0x39, 0x71, 0x4e, 0xd6, 0x5a, - 0xd0, 0x5e, 0xce, 0xb7, 0x39, 0x20, 0x00, 0x37, 0x0b, 0x02, 0x00, 0x85, 0x6b, 0x26, 0xda, 0x4a, 0xd8, 0x52, 0xd4, - 0x56, 0xd2, 0x62, 0xcc, 0x6a, 0xc8, 0x6e, 0xc6, 0x06, 0xde, 0x22, 0xdc, 0x66, 0xca, 0xaa, 0x8a, 0xae, 0x84, 0x32, - 0x8a, 0x01, 0x49, 0x81, 0x4d, 0x37, 0x3c, 0x20, 0x00, 0x41, 0x4d, 0x93, 0x89, 0x49, 0xe9, 0x1d, 0x0b, 0x93, 0x8b, - 0x0b, 0x82, 0xb3, 0x8c, 0x2a, 0x01, 0x93, 0x07, 0x4c, 0xfa, 0x63, 0x64, 0x49, 0x03, 0xf2, 0x50, 0x62, 0x54, 0x13, - 0x07, 0x50, 0x05, 0x98, 0xc3, 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, 0x4b, - 0x62, 0x4c, 0xd2, 0x4c, 0x42, 0x4d, 0xb2, 0x4d, 0x21, 0x61, 0x82, 0x80, 0x33, 0x04, 0x2a, 0x41, 0x63, 0x73, 0x8d, - 0x00, 0x41, 0x44, 0x6e, 0x85, 0xef, 0xe0, 0xef, 0x91, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0xfa, 0x98, 0x43, - 0x93, 0x07, 0x50, 0x05, 0x63, 0x19, 0xf7, 0x00, 0x99, 0xc4, 0x26, 0x85, 0x22, 0x86, 0xee, 0x85, 0xef, 0xe0, 0xcf, - 0x9b, 0xc1, 0x04, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x25, 0x00, 0xef, 0xf0, 0x6f, 0xd9, 0x03, 0xa5, - 0xc9, 0x00, 0x93, 0x17, 0x84, 0x01, 0x0d, 0x04, 0x7e, 0x05, 0x5d, 0x8d, 0x33, 0x65, 0x65, 0x01, 0xfa, 0x5f, 0xad, - 0xee, 0x47, 0xf2, 0x69, 0x0f, 0x6f, 0x9e, 0xf9, 0x1a, 0x54, 0x5f, 0xf8, 0xa6, 0x61, 0xae, 0xca, 0xc4, 0x1b, 0xcf, - 0xd7, 0xfe, 0xc3, 0x77, 0x79, 0x8d, 0x99, 0x81, 0x6f, 0xb5, 0x53, 0x90, 0x4c, 0xef, 0xf0, 0x0f, 0xd8, 0x03, 0xa5, - 0xc9, 0x00, 0x7e, 0x05, 0x33, 0x65, 0x75, 0x01, 0xef, 0xf0, 0x2f, 0xd7, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x76, 0xc4, - 0xff, 0x93, 0x85, 0x05, 0x04, 0x66, 0x85, 0xef, 0xd0, 0x3f, 0xd2, 0x93, 0x07, 0x00, 0x06, 0x63, 0xe3, 0xb7, 0x01, - 0xc1, 0x0d, 0x41, 0x09, 0x81, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x2a, 0x84, 0x21, 0x45, 0x06, 0xc6, 0xef, 0xf0, 0x4f, - 0xd4, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x19, 0xf5, 0x00, 0x22, 0x85, 0xef, 0xf0, 0x1f, 0xdf, 0xb7, 0x37, 0x20, 0x00, - 0x23, 0xac, 0x07, 0xe8, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa2, 0xa7, - 0xfa, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x60, 0x02, 0x98, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, - 0x69, 0x47, 0x98, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0xc8, 0x4b, 0x82, 0x80, 0x39, 0x71, 0x36, 0xd0, 0x3a, - 0xce, 0x3e, 0xcc, 0x05, 0x47, 0xb7, 0x07, 0x00, 0x04, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, - 0x2e, 0xd4, 0x32, 0xd2, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xd8, 0xc7, 0xb7, - 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0xe9, 0xd8, 0x43, 0x89, 0x46, 0x7d, 0x17, 0x63, 0xfe, 0xe6, 0x02, 0x37, 0x55, - 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x05, 0x6c, 0xef, 0xd0, 0xef, 0xe0, 0xef, 0xc0, 0x8f, 0xdc, 0xf2, 0x50, 0xe2, - 0x52, 0xfa, 0xd8, 0x85, 0xa9, 0xef, 0xad, 0x4e, 0xfd, 0xc1, 0x5f, 0xa3, 0x84, 0x3a, 0x97, 0xdc, 0xca, 0xf9, 0x18, - 0x5e, 0xc8, 0x75, 0xd0, 0x22, 0xfc, 0x2c, 0xbf, 0x89, 0x58, 0xe8, 0xb4, 0xb3, 0x78, 0x7c, 0x68, 0x4d, 0x52, 0x53, - 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, - 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x13, 0x07, 0xa0, 0x0a, 0x98, 0xcb, - 0xd1, 0xbf, 0xb7, 0x07, 0x01, 0x02, 0x88, 0xd7, 0xcc, 0xd7, 0x88, 0xdb, 0xcc, 0xdb, 0x88, 0xdf, 0xcc, 0xdf, 0x82, - 0x80, 0x01, 0x11, 0x26, 0xca, 0xb7, 0x04, 0x01, 0x02, 0x22, 0xcc, 0xc0, 0x40, 0xf5, 0x77, 0x93, 0x87, 0xf7, 0xa5, - 0x7d, 0x8c, 0x89, 0x67, 0x93, 0x87, 0x07, 0x1a, 0x06, 0xce, 0x4a, 0xc8, 0x4e, 0xc6, 0xc1, 0x8f, 0xaa, 0x89, 0xdc, - 0xc0, 0x05, 0x45, 0x2e, 0x89, 0xef, 0xd0, 0xbf, 0x99, 0x93, 0x67, 0x04, 0x40, 0xdc, 0xc0, 0x05, 0x45, 0xef, 0xd0, - 0xff, 0x98, 0x85, 0x67, 0x93, 0x87, 0x07, 0x40, 0x5d, 0x8c, 0xc0, 0xc0, 0xb7, 0x47, 0x00, 0x08, 0x23, 0xa4, 0x07, - 0x00, 0xb7, 0x57, 0x00, 0x08, 0x23, 0xa4, 0x07, 0x00, 0xf2, 0x40, 0x62, 0x44, 0x23, 0xa0, 0x34, 0x03, 0x23, 0xa2, - 0x24, 0x03, 0xb2, 0x49, 0xd2, 0x44, 0x42, 0x49, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x02, 0x88, 0x53, 0xcc, - 0x53, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x02, 0x88, 0x47, 0x21, 0x81, 0x13, 0x75, 0xf5, 0x0f, 0x82, 0x80, 0x41, 0x11, - 0x01, 0x45, 0x81, 0x45, 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0xef, 0xf0, 0x1f, 0xf6, 0xef, 0xf0, 0x9f, 0xfd, 0xaa, - 0x84, 0x2e, 0x84, 0x2a, 0x87, 0xfa, 0x8c, 0xc9, 0x53, 0x60, 0x55, 0x97, 0x5f, 0xd1, 0x7c, 0xa5, 0x19, 0x5a, 0xc2, - 0x78, 0x00, 0x3c, 0x73, 0xbd, 0x82, 0x27, 0x5d, 0x21, 0x74, 0xf8, 0xfd, 0x8b, 0x7e, 0xcc, 0xf2, 0x88, 0x62, 0x40, - 0x40, 0x4e, 0xae, 0x86, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0x85, 0x85, - 0x71, 0x13, 0x05, 0x45, 0x64, 0x13, 0x06, 0x06, 0x70, 0xef, 0xd0, 0xaf, 0xc9, 0xa2, 0x85, 0x22, 0x44, 0xb2, 0x40, - 0x26, 0x85, 0x92, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xf3, 0x39, 0x71, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, - 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, - 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xf0, 0x7f, 0xf9, 0xef, 0xc0, 0x4f, 0xc9, 0xf2, 0x50, 0xe2, 0x52, 0x52, - 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, - 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x07, 0x00, 0x02, 0x5c, - 0x47, 0xc9, 0x8f, 0x5c, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0xd8, 0x47, 0x13, 0x45, 0xf5, 0xff, 0x79, 0x8d, - 0xc8, 0xc7, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x4f, 0xc9, 0x8f, 0x1c, 0xcf, 0x82, 0x80, 0xb7, 0x07, 0x00, - 0x02, 0x98, 0x4f, 0x13, 0x45, 0xf5, 0xff, 0x79, 0x8d, 0x88, 0xcf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0xc8, 0xcb, - 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x47, 0x00, 0x1c, 0xc7, 0xb7, 0x07, 0x00, 0x03, 0x94, - 0x4b, 0x37, 0x37, 0x20, 0x00, 0x23, 0x24, 0xd7, 0xfa, 0xfa, 0x51, 0xb5, 0xe0, 0x05, 0x62, 0xbf, 0xb1, 0x63, 0xbc, - 0x82, 0xd5, 0x71, 0x63, 0x6e, 0x4f, 0xf4, 0xa6, 0x1f, 0x6e, 0x30, 0xd3, 0x8e, 0x91, 0xce, 0x99, 0x44, 0x80, 0x4a, - 0x50, 0xc8, 0x7b, 0xb1, 0x18, 0x4f, 0x23, 0xa8, 0x07, 0x00, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0xb7, - 0x06, 0x00, 0x03, 0xf9, 0x9b, 0x1c, 0xc7, 0x37, 0x07, 0x08, 0x00, 0x9c, 0x46, 0xf9, 0x8f, 0xf5, 0xff, 0x82, 0x80, - 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x17, 0x00, 0x1c, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x87, - 0xfa, 0xb7, 0x07, 0x00, 0x03, 0x98, 0xcb, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0xc7, 0xfa, 0x93, 0x07, - 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0xb7, 0x27, 0x03, 0x04, 0x9c, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, - 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x13, 0x05, 0x00, 0x10, 0x6f, 0xf0, 0x3f, 0xf4, 0x93, 0x07, 0x50, 0x05, - 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0x41, 0x11, 0x37, 0x37, 0x20, 0x00, 0x23, 0x28, 0xf7, 0xfa, 0x06, - 0xc6, 0xef, 0xf0, 0x1f, 0xfe, 0xb7, 0x27, 0x03, 0x04, 0x09, 0x47, 0xd8, 0xc3, 0x37, 0x17, 0x03, 0x04, 0xb7, 0x07, - 0x03, 0x04, 0x13, 0x07, 0x07, 0x80, 0x23, 0xa0, 0x07, 0x00, 0x91, 0x07, 0xe3, 0x9d, 0xe7, 0xfe, 0xb7, 0x27, 0x03, - 0x04, 0x0d, 0x47, 0xd8, 0xc7, 0x98, 0x47, 0x85, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, - 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x00, 0x10, 0x6f, 0xf0, 0xff, 0xee, 0x93, 0x07, 0x50, - 0x05, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0x37, 0x37, 0x20, 0x00, 0xfa, 0xd6, 0x0e, 0x4f, 0xca, 0x68, - 0x7b, 0xef, 0x7e, 0x3d, 0x77, 0x0a, 0x90, 0xa0, 0x67, 0x67, 0x16, 0xb2, 0xed, 0x36, 0x5e, 0xe5, 0xc6, 0xbb, 0x6c, - 0x30, 0xc1, 0x4f, 0x8b, 0xfd, 0xc6, 0x35, 0x03, 0xf0, 0x4f, 0x23, 0x28, 0xf7, 0xfa, 0xb7, 0x27, 0x03, 0x04, 0x05, - 0x47, 0xd8, 0xc3, 0x82, 0x80, 0xc2, 0x05, 0xc9, 0x8d, 0x93, 0xe5, 0x05, 0x10, 0xb7, 0x07, 0x03, 0x04, 0x23, 0xa0, - 0xb7, 0x10, 0x82, 0x80, 0xc2, 0x05, 0xc9, 0x8d, 0x11, 0x65, 0x13, 0x05, 0x05, 0x50, 0xc9, 0x8d, 0xb7, 0x07, 0x03, - 0x04, 0x23, 0xa0, 0xb7, 0x10, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, - 0x99, 0xc3, 0xef, 0xb0, 0x9f, 0xc4, 0x37, 0x15, 0x03, 0x04, 0x2a, 0x94, 0x08, 0x40, 0xb2, 0x40, 0x22, 0x44, 0x41, - 0x01, 0x82, 0x80, 0x79, 0x71, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x06, 0xd6, 0x22, 0xd4, 0xaa, 0x84, 0x2e, 0x89, - 0xb2, 0x89, 0x19, 0xe1, 0xef, 0xb0, 0x1f, 0xc2, 0x93, 0x77, 0x39, 0x00, 0x99, 0xc3, 0xef, 0xb0, 0x7f, 0xc1, 0x01, - 0x44, 0x63, 0x69, 0x34, 0x01, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x45, 0x61, 0x82, 0x80, - 0x33, 0x05, 0x24, 0x01, 0xef, 0xf0, 0x5f, 0xfa, 0x2a, 0xc6, 0x11, 0x46, 0x33, 0x85, 0x84, 0x00, 0x6c, 0x00, 0xcd, - 0x2d, 0x11, 0x04, 0xe1, 0xbf, 0x79, 0x71, 0x22, 0xd4, 0x4a, 0xd0, 0x4e, 0xce, 0x56, 0xca, 0x06, 0xd6, 0x26, 0xd2, - 0x52, 0xcc, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0xae, 0x89, 0x32, 0x89, 0x93, 0x7a, 0xc6, 0xff, 0x99, 0xc3, 0xef, - 0xb0, 0x7f, 0xbc, 0x37, 0x0a, 0x03, 0x04, 0x81, 0x44, 0x22, 0x9a, 0x63, 0xe9, 0x54, 0x03, 0x13, 0x76, 0xfa, 0x8b, - 0x83, 0x5c, 0xa5, 0x90, 0x36, 0x78, 0x3c, 0xaf, 0x8e, 0xce, 0x0a, 0x76, 0xa1, 0xa0, 0x33, 0xd9, 0xfb, 0x38, 0xc6, - 0x37, 0xca, 0x98, 0xbd, 0xaf, 0xe7, 0x29, 0xb1, 0xc4, 0x8a, 0x12, 0x2b, 0xc8, 0x50, 0x39, 0x00, 0x01, 0xce, 0xb3, - 0x85, 0x99, 0x00, 0x68, 0x00, 0x02, 0xc6, 0x7d, 0x25, 0xb2, 0x47, 0x37, 0x05, 0x03, 0x04, 0x2a, 0x94, 0x26, 0x94, - 0x1c, 0xc0, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0xd2, 0x4a, 0x45, 0x61, 0x82, - 0x80, 0x63, 0x94, 0x09, 0x00, 0xef, 0xb0, 0x5f, 0xb8, 0xb3, 0x85, 0x99, 0x00, 0x11, 0x46, 0x68, 0x00, 0xbd, 0x2d, - 0x32, 0x47, 0xb3, 0x07, 0x9a, 0x00, 0x91, 0x04, 0x98, 0xc3, 0x4d, 0xbf, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x41, - 0x11, 0x13, 0x05, 0x45, 0xb5, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0xd0, 0xef, 0xe9, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0f, - 0xf5, 0x00, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x05, 0x72, 0xef, 0xd0, 0x2f, 0xa3, 0x13, 0x05, 0x50, - 0x05, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x17, 0x03, 0x04, 0x83, 0xa7, 0x07, 0x10, 0x37, 0x34, - 0x20, 0x00, 0x13, 0x04, 0x04, 0xfb, 0x93, 0xf7, 0xf7, 0x0f, 0x81, 0xe7, 0x1c, 0x40, 0x63, 0x9d, 0xa7, 0x00, 0x37, - 0x55, 0x10, 0x00, 0x8d, 0x45, 0x13, 0x05, 0x05, 0x72, 0xef, 0xd0, 0xcf, 0x9f, 0x93, 0x07, 0xa0, 0x0a, 0x1c, 0xc0, - 0xd1, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0xc7, 0xfa, 0x13, 0x84, 0xc7, 0xfa, 0x63, 0x09, 0xa7, 0x00, 0x37, - 0x55, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0x05, 0x72, 0xef, 0xd0, 0x6f, 0x9d, 0x08, 0x40, 0x5d, 0xb7, 0x37, 0x95, - 0x04, 0x00, 0xfa, 0x2e, 0x5a, 0xf4, 0xe1, 0x40, 0xb6, 0x8a, 0x0c, 0x02, 0x02, 0x42, 0x33, 0x0a, 0x0f, 0x83, 0x05, - 0x33, 0xde, 0x08, 0x3a, 0xec, 0xd7, 0x1b, 0xe0, 0x0d, 0x55, 0x64, 0x53, 0x08, 0x1b, 0xf1, 0x9f, 0xa0, 0x51, 0x13, - 0x05, 0x05, 0x3e, 0x6f, 0xf0, 0xff, 0xf6, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x5f, 0xe6, 0xef, 0xf0, 0x1f, 0xe3, - 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x5f, 0xfe, 0xb7, 0x17, 0x03, 0x04, 0x03, 0xa5, 0x07, 0x10, 0x41, 0x81, 0x82, - 0x80, 0x41, 0x11, 0x3a, 0xc4, 0x37, 0x27, 0x03, 0x04, 0x3e, 0xc2, 0x1c, 0x47, 0x36, 0xc6, 0x93, 0xf6, 0x27, 0x00, - 0x89, 0xca, 0x89, 0x46, 0x14, 0xc7, 0x37, 0x37, 0x20, 0x00, 0x93, 0x06, 0xa0, 0x0a, 0x23, 0x26, 0xd7, 0xfa, 0x91, - 0x8b, 0x99, 0xcf, 0xb7, 0x27, 0x03, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x93, 0x07, 0xa0, 0x0a, 0x37, 0x37, 0x20, 0x00, - 0x23, 0x28, 0xf7, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0xb2, 0x46, 0x22, 0x47, 0x92, 0x47, 0x41, - 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x04, 0x00, 0x03, 0x1c, 0x48, 0x06, 0xc6, 0xdd, 0x9b, - 0x1c, 0xc8, 0xef, 0xe0, 0x0f, 0xd9, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x02, 0x5c, 0xcc, 0xb2, 0x40, 0x22, - 0x44, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x8c, 0x07, 0xfa, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x2a, 0x84, - 0x21, 0x45, 0x06, 0xc6, 0xef, 0xf0, 0x7f, 0xca, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x7f, 0xc6, 0x22, 0x04, 0x13, - 0x64, 0x04, 0x03, 0x37, 0x07, 0x00, 0x03, 0x40, 0xc3, 0xb2, 0x40, 0x22, 0x44, 0xc1, 0x67, 0x93, 0x87, 0xa7, 0xfa, - 0x1c, 0xcf, 0x41, 0x01, 0x82, 0x80, 0xfa, 0xd6, 0xdd, 0xf6, 0xa9, 0x68, 0x89, 0x40, 0x5e, 0x01, 0x20, 0x1f, 0x9d, - 0x67, 0xb3, 0xb0, 0xe7, 0x4b, 0x3f, 0x08, 0x0a, 0x8a, 0x43, 0x28, 0xd8, 0x5d, 0xb6, 0x1a, 0x6b, 0x32, 0xe4, 0xe9, - 0xaf, 0x78, 0x52, 0x41, 0x11, 0x26, 0xc2, 0xaa, 0x84, 0x09, 0x45, 0x22, 0xc4, 0x06, 0xc6, 0x2e, 0x84, 0xef, 0xf0, - 0x1f, 0xfc, 0x37, 0x07, 0x20, 0x00, 0xb7, 0x07, 0x00, 0x03, 0x13, 0x07, 0x07, 0x02, 0xd8, 0xcf, 0x37, 0x37, 0x20, - 0x00, 0x23, 0x2a, 0x97, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2e, 0x87, 0xfa, 0xb2, 0x40, 0x22, 0x44, 0x05, 0x47, - 0x98, 0xcb, 0x37, 0x07, 0x08, 0x00, 0x98, 0xc7, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x03, 0x9c, - 0x47, 0x37, 0x07, 0x04, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, - 0x37, 0x07, 0x00, 0x03, 0x5c, 0x53, 0x13, 0x05, 0x50, 0x05, 0x93, 0x96, 0x07, 0x01, 0xc1, 0x82, 0xc1, 0x83, 0x63, - 0x97, 0xf6, 0x00, 0x1c, 0x47, 0x91, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, - 0xef, 0xf0, 0xff, 0xf1, 0x37, 0x07, 0x00, 0x03, 0x5c, 0x47, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc7, 0x5c, 0x47, 0x85, - 0x8b, 0xf5, 0xff, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xfb, 0x95, 0xc3, - 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x5f, 0xef, 0xb7, 0x07, 0x00, 0x03, 0x98, 0x4b, 0xb2, 0x40, 0x13, 0x67, 0x87, - 0x00, 0x98, 0xcb, 0x37, 0x07, 0x08, 0x00, 0x98, 0xc7, 0x41, 0x01, 0x6f, 0xe0, 0xcf, 0xc5, 0x82, 0x80, 0x37, 0x07, - 0x00, 0x03, 0x1c, 0x4b, 0xf9, 0x9b, 0x1c, 0xcb, 0x82, 0x80, 0xfa, 0xd9, 0x71, 0x17, 0x73, 0x0c, 0x81, 0x2d, 0x69, - 0x83, 0xc8, 0xfb, 0x9a, 0x55, 0xf5, 0x79, 0x51, 0xc7, 0x04, 0x8c, 0xb4, 0x8a, 0xc9, 0x02, 0x9d, 0x3c, 0x4a, 0x76, - 0xcd, 0x59, 0x8d, 0x86, 0x55, 0x50, 0x53, 0xb7, 0x06, 0x00, 0x03, 0xdc, 0x42, 0x7d, 0x77, 0x13, 0x07, 0xf7, 0x0f, - 0xf9, 0x8f, 0x05, 0x67, 0x22, 0x05, 0x13, 0x07, 0x07, 0xf0, 0x79, 0x8d, 0x5d, 0x8d, 0xc8, 0xc2, 0x82, 0x80, 0x1d, - 0x71, 0x3a, 0xda, 0x37, 0x07, 0x00, 0x03, 0x3e, 0xd8, 0x1c, 0x47, 0x86, 0xce, 0x96, 0xcc, 0x9a, 0xca, 0x9e, 0xc8, - 0xa2, 0xc6, 0xa6, 0xc4, 0xaa, 0xc2, 0xae, 0xc0, 0x32, 0xde, 0x36, 0xdc, 0x42, 0xd6, 0x46, 0xd4, 0x4a, 0xd2, 0x4e, - 0xd0, 0x72, 0xce, 0x76, 0xcc, 0x7a, 0xca, 0x7e, 0xc8, 0x85, 0x8b, 0xa1, 0xc7, 0x04, 0x57, 0x11, 0x44, 0x37, 0x39, - 0x20, 0x00, 0x83, 0x27, 0x49, 0xfb, 0x13, 0xf5, 0xf4, 0x0f, 0x7d, 0x14, 0x82, 0x97, 0xa1, 0x80, 0x6d, 0xf8, 0x36, - 0x44, 0xf6, 0x40, 0xe6, 0x42, 0x56, 0x43, 0xc6, 0x43, 0xa6, 0x44, 0x16, 0x45, 0x86, 0x45, 0x72, 0x56, 0xe2, 0x56, - 0x52, 0x57, 0xc2, 0x57, 0x32, 0x58, 0xa2, 0x58, 0x12, 0x59, 0x82, 0x59, 0x72, 0x4e, 0xe2, 0x4e, 0x52, 0x4f, 0xc2, - 0x4f, 0x25, 0x61, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xc7, 0x87, 0xfb, 0x13, 0x84, 0x87, 0xfb, - 0x05, 0xeb, 0xb7, 0x04, 0x00, 0x03, 0x37, 0x39, 0x20, 0x00, 0x93, 0x09, 0xa0, 0x0a, 0x9c, 0x44, 0x91, 0x8b, 0xd5, - 0xfb, 0x83, 0x27, 0xc9, 0xfb, 0x68, 0x00, 0x82, 0x97, 0x63, 0x0d, 0x35, 0x01, 0x85, 0x47, 0x23, 0x00, 0xf4, 0x00, - 0xc1, 0x67, 0x93, 0x87, 0x07, 0x02, 0xdc, 0xcc, 0x61, 0xbf, 0xef, 0xf0, 0x5f, 0xdf, 0xfa, 0x13, 0xcd, 0x54, 0x98, - 0x6f, 0x53, 0x7c, 0x10, 0x70, 0xc1, 0x39, 0x0d, 0x95, 0x14, 0x27, 0x71, 0xdd, 0xb5, 0x71, 0x98, 0x20, 0x76, 0xaf, - 0x3b, 0x55, 0x38, 0xfb, 0x9c, 0xdd, 0x4a, 0x6d, 0xd9, 0x28, 0x54, 0x49, 0xbf, 0xb2, 0x47, 0x9c, 0xd8, 0xd1, 0xbf, - 0x5c, 0x41, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc1, 0x82, 0x80, 0x5c, 0x41, 0xf9, 0x9b, 0x5c, 0xc1, 0x82, 0x80, 0x5c, - 0x41, 0xf5, 0x9b, 0xd1, 0x8f, 0x5c, 0xc1, 0x14, 0xc9, 0x4c, 0xc9, 0x82, 0x80, 0x5c, 0x45, 0xcd, 0x8f, 0x5c, 0xc5, - 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x07, 0xfc, 0x82, 0x80, 0x39, 0x71, 0x3a, 0xce, 0x37, 0x07, 0x10, - 0x01, 0x3e, 0xcc, 0x1c, 0x47, 0x58, 0x47, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, - 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xf9, 0x8f, 0x91, - 0xcf, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xfc, 0x98, 0x43, 0x05, 0x07, 0x98, 0xc3, 0xb7, 0x07, 0x10, 0x01, - 0x98, 0x47, 0x0d, 0x8b, 0x98, 0xc7, 0x19, 0xa8, 0xb7, 0x07, 0x20, 0x01, 0x98, 0x47, 0xdc, 0x47, 0x7d, 0x8f, 0xb7, - 0x07, 0x20, 0x01, 0x6d, 0xf7, 0xef, 0xb0, 0xff, 0xe6, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, - 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, - 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x1c, 0x41, 0x63, 0xf7, 0xb7, 0x00, 0x23, 0x80, 0xc7, 0x00, - 0x1c, 0x41, 0x85, 0x07, 0x1c, 0xc1, 0x82, 0x80, 0x1d, 0x71, 0xa2, 0xcc, 0xa6, 0xca, 0xca, 0xc8, 0x86, 0xce, 0xfa, - 0xcb, 0x8a, 0xed, 0x7b, 0xbd, 0xaa, 0x12, 0x35, 0x5f, 0xaf, 0x78, 0xaa, 0x2a, 0x47, 0x6d, 0xec, 0x5f, 0x4d, 0x37, - 0xe1, 0xaf, 0xbd, 0xd8, 0x7e, 0x11, 0xa2, 0xb7, 0xa2, 0xbf, 0x34, 0xe7, 0xf4, 0x00, 0x55, 0xce, 0xc6, 0xd2, 0xc4, - 0xd6, 0xc2, 0xda, 0xc0, 0x5e, 0xde, 0x62, 0xdc, 0x66, 0xda, 0x6a, 0xd8, 0x6e, 0xd6, 0x2a, 0xc6, 0x2e, 0x84, 0x32, - 0x89, 0xb6, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x0f, 0xf6, 0x63, 0x14, 0x09, 0x00, 0xef, 0xb0, 0x8f, 0xf5, 0x01, 0x45, - 0x05, 0xc4, 0xb2, 0x4a, 0x7d, 0x14, 0x25, 0x4a, 0x56, 0x94, 0x93, 0x0c, 0xc0, 0x06, 0x13, 0x0b, 0x30, 0x07, 0xa9, - 0x4b, 0x1d, 0x4d, 0x03, 0x46, 0x09, 0x00, 0x15, 0xe6, 0xb2, 0x47, 0x23, 0x80, 0x07, 0x00, 0x32, 0x45, 0x33, 0x05, - 0x55, 0x41, 0xf6, 0x40, 0x66, 0x44, 0xd6, 0x44, 0x46, 0x49, 0xb6, 0x49, 0x26, 0x4a, 0x96, 0x4a, 0x06, 0x4b, 0xf2, - 0x5b, 0x62, 0x5c, 0xd2, 0x5c, 0x42, 0x5d, 0xb2, 0x5d, 0x25, 0x61, 0x82, 0x80, 0x93, 0x07, 0x50, 0x02, 0x63, 0x1f, - 0xf6, 0x02, 0x93, 0x07, 0x19, 0x00, 0x83, 0xc6, 0x07, 0x00, 0x3e, 0x89, 0x85, 0x07, 0x13, 0x87, 0x06, 0xfd, 0x13, - 0x77, 0xf7, 0x0f, 0xe3, 0x78, 0xea, 0xfe, 0x63, 0x93, 0x96, 0x01, 0x3e, 0x89, 0x03, 0x46, 0x09, 0x00, 0x63, 0x06, - 0x66, 0x0d, 0x63, 0x60, 0xcb, 0x02, 0x93, 0x07, 0x30, 0x06, 0x63, 0x05, 0xf6, 0x06, 0x93, 0x07, 0x40, 0x06, 0x63, - 0x0c, 0xf6, 0x06, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, 0xf2, 0xa6, 0x89, 0x95, 0xa0, 0x93, 0x07, 0x50, 0x07, - 0x63, 0x02, 0xf6, 0x06, 0x93, 0x07, 0x80, 0x07, 0xe3, 0x14, 0xf6, 0xfe, 0x98, 0x40, 0x93, 0x89, 0x44, 0x00, 0x81, - 0x46, 0x37, 0x06, 0xfa, 0x4c, 0x87, 0xca, 0x4e, 0x13, 0x0b, 0xd1, 0x0d, 0x64, 0xd2, 0x11, 0x47, 0xb5, 0x47, 0xd8, - 0xc9, 0xd4, 0x74, 0x1f, 0x62, 0xdc, 0x60, 0x38, 0xbb, 0x72, 0xf0, 0x4f, 0x0a, 0xc5, 0x13, 0xd9, 0xc3, 0xd8, 0x55, - 0x00, 0xf0, 0xb3, 0x75, 0xc7, 0x00, 0xba, 0x84, 0x36, 0x8c, 0x12, 0x07, 0x85, 0x06, 0x89, 0xe5, 0xe3, 0x99, 0xa6, - 0xff, 0x1d, 0x4c, 0xba, 0x84, 0xa1, 0x4d, 0x13, 0xd7, 0xc4, 0x01, 0x63, 0x74, 0xea, 0x08, 0x13, 0x06, 0x77, 0x05, - 0xa2, 0x85, 0x68, 0x00, 0x05, 0x0c, 0xef, 0xf0, 0x1f, 0xee, 0x92, 0x04, 0xe3, 0x14, 0xbc, 0xff, 0x09, 0xa8, 0x03, - 0xc6, 0x04, 0x00, 0xa2, 0x85, 0x68, 0x00, 0x93, 0x89, 0x44, 0x00, 0xef, 0xf0, 0x9f, 0xec, 0x05, 0x09, 0xce, 0x84, - 0x31, 0xbf, 0x5c, 0x08, 0x98, 0x40, 0x93, 0x89, 0x44, 0x00, 0x3e, 0x8c, 0x81, 0x44, 0xb3, 0x76, 0x77, 0x03, 0x85, - 0x04, 0x85, 0x07, 0x93, 0x86, 0x06, 0x03, 0xa3, 0x8f, 0xd7, 0xfe, 0xba, 0x86, 0x33, 0x57, 0x77, 0x03, 0xe3, 0x65, - 0xda, 0xfe, 0xfd, 0x5d, 0xfd, 0x14, 0xe3, 0x88, 0xb4, 0xfd, 0xb3, 0x07, 0x9c, 0x00, 0x03, 0xc6, 0x07, 0x00, 0xa2, - 0x85, 0x68, 0x00, 0xef, 0xf0, 0x5f, 0xe8, 0xed, 0xb7, 0x93, 0x89, 0x44, 0x00, 0x84, 0x40, 0x03, 0xc6, 0x04, 0x00, - 0x45, 0xda, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, 0xe6, 0x85, 0x04, 0xc5, 0xbf, 0x13, 0x06, 0x07, 0x03, 0xb5, - 0xbf, 0x41, 0x11, 0x26, 0xc2, 0xb7, 0x34, 0x20, 0x00, 0x2a, 0x86, 0xae, 0x86, 0x13, 0x85, 0x84, 0xea, 0x93, 0x05, - 0x00, 0x08, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0xf0, 0xbf, 0xe5, 0x2a, 0x84, 0x13, 0x85, 0x84, 0xea, 0xef, 0xd0, 0x8f, - 0x9b, 0xb2, 0x40, 0x22, 0x85, 0x22, 0x44, 0xfa, 0x77, 0x25, 0x15, 0xa5, 0x40, 0xb8, 0x46, 0xd0, 0x99, 0xaa, 0x4d, - 0x3a, 0x4d, 0xdc, 0xe4, 0xd3, 0xb8, 0xb9, 0x2c, 0xd5, 0x88, 0x4e, 0xc5, 0x22, 0xc0, 0xd2, 0xa7, 0x93, 0x05, 0x87, - 0x6b, 0x88, 0xb0, 0x56, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x26, 0xca, 0xb7, 0x34, 0x20, 0x00, 0x2e, - 0xd2, 0x32, 0xd4, 0x36, 0xd6, 0x2a, 0x86, 0x54, 0x10, 0x93, 0x05, 0x00, 0x08, 0x13, 0x85, 0x84, 0xea, 0x06, 0xce, - 0x22, 0xcc, 0x3a, 0xd8, 0x3e, 0xda, 0x42, 0xdc, 0x46, 0xde, 0x36, 0xc6, 0xef, 0xf0, 0x9f, 0xe1, 0x2a, 0x84, 0x13, - 0x85, 0x84, 0xea, 0xef, 0xd0, 0x6f, 0x97, 0xf2, 0x40, 0x22, 0x85, 0x62, 0x44, 0xd2, 0x44, 0x21, 0x61, 0x82, 0x80, - 0x22, 0x05, 0x61, 0x77, 0x2d, 0x8d, 0xa1, 0x47, 0x15, 0x07, 0x93, 0x16, 0x05, 0x01, 0x06, 0x05, 0x42, 0x05, 0xc1, - 0x86, 0x41, 0x81, 0x63, 0xd5, 0x06, 0x00, 0x39, 0x8d, 0x42, 0x05, 0x41, 0x81, 0xfd, 0x17, 0xe5, 0xf7, 0x82, 0x80, - 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x2a, 0x84, 0xb3, 0x04, 0xb5, 0x00, 0x06, 0xc6, 0x01, 0x45, 0x63, 0x97, 0x84, - 0x00, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x04, 0xaa, 0x85, 0x03, 0x45, 0xf4, 0xff, - 0xef, 0xf0, 0x5f, 0xfb, 0xdd, 0xb7, 0xb7, 0x86, 0xb8, 0xed, 0x01, 0x47, 0xfd, 0x57, 0x93, 0x86, 0x06, 0x32, 0x63, - 0x15, 0xb7, 0x00, 0x13, 0xc5, 0xf7, 0xff, 0x82, 0x80, 0x33, 0x06, 0xe5, 0x00, 0x03, 0x46, 0x06, 0x00, 0xb1, 0x8f, - 0x21, 0x46, 0x13, 0xd8, 0x17, 0x00, 0x85, 0x8b, 0x91, 0xc3, 0xb6, 0x87, 0x7d, 0x16, 0xb3, 0x47, 0xf8, 0x00, 0x65, - 0xfa, 0x05, 0x07, 0xd9, 0xbf, 0x2a, 0x83, 0x09, 0xca, 0x83, 0x83, 0xfa, 0xb3, 0xc7, 0xe1, 0x28, 0x25, 0xd4, 0xa1, - 0xe8, 0xd0, 0x44, 0xbf, 0x8d, 0x35, 0x9f, 0xf3, 0x28, 0x04, 0x1e, 0xbe, 0xd4, 0x02, 0xad, 0xea, 0x20, 0x5e, 0xe0, - 0xcd, 0x00, 0xea, 0xb7, 0xed, 0xd1, 0x88, 0x57, 0x05, 0x00, 0x23, 0x00, 0x73, 0x00, 0x7d, 0x16, 0x05, 0x03, 0x85, - 0x05, 0x6d, 0xfa, 0x82, 0x80, 0x15, 0xc2, 0x2a, 0x83, 0x85, 0x46, 0x63, 0x67, 0xb5, 0x00, 0xfd, 0x56, 0x13, 0x07, - 0xf6, 0xff, 0x3a, 0x93, 0xba, 0x95, 0x83, 0x83, 0x05, 0x00, 0x23, 0x00, 0x73, 0x00, 0x7d, 0x16, 0x36, 0x93, 0xb6, - 0x95, 0x6d, 0xfa, 0x82, 0x80, 0x2a, 0x83, 0x11, 0xc6, 0x23, 0x00, 0xb3, 0x00, 0x7d, 0x16, 0x05, 0x03, 0x65, 0xfe, - 0x82, 0x80, 0x00, 0x00, 0x63, 0x6f, 0x64, 0x65, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, 0x53, 0x45, 0x43, - 0x43, 0x48, 0x4e, 0x4c, 0x00, 0x4d, 0x43, 0x4e, 0x54, 0x00, 0x00, 0x00, 0x00, 0x54, 0x58, 0x3a, 0x20, 0x25, 0x64, - 0x2f, 0x25, 0x64, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x43, 0x4d, 0x44, 0x33, 0x00, 0x00, 0x00, 0x00, 0x49, - 0x00, 0x00, 0x00, 0x65, 0x6e, 0x61, 0x62, 0x6c, 0x65, 0x64, 0x20, 0x25, 0x64, 0x00, 0x00, 0x4d, 0x41, 0x49, 0x4e, - 0x00, 0x00, 0x00, 0x00, 0x6c, 0x65, 0x6e, 0x20, 0x25, 0x64, 0x2f, 0x25, 0x64, 0x00, 0x00, 0x00, 0x72, 0x73, 0x70, - 0x3d, 0x25, 0x78, 0x00, 0x00, 0x73, 0x74, 0x61, 0x72, 0x74, 0x2c, 0x20, 0x76, 0x25, 0x75, 0x2e, 0x25, 0x75, 0x2e, - 0x25, 0x75, 0x00, 0x00, 0x00, 0x00, 0x50, 0x52, 0x4f, 0x56, 0x49, 0x53, 0x49, 0x4f, 0x4e, 0x20, 0x4f, 0x4b, 0x00, - 0x00, 0x00, 0x00, 0x4e, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x43, 0x50, 0x42, 0x3a, 0xfa, 0x73, 0x3a, 0xfa, - 0x5a, 0xd6, 0xf0, 0x73, 0xa2, 0xda, 0x98, 0x8a, 0x7e, 0x8e, 0x52, 0x63, 0x08, 0x47, 0x24, 0xce, 0x4a, 0x46, 0x93, - 0xfa, 0xc5, 0x59, 0x97, 0x8b, 0xa7, 0x86, 0x9a, 0x19, 0xb0, 0x60, 0x58, 0x20, 0x25, 0x64, 0x00, 0x4c, 0x33, 0x20, - 0x63, 0x6d, 0x64, 0x20, 0x25, 0x64, 0x3a, 0x20, 0x25, 0x78, 0x2c, 0x20, 0x6c, 0x65, 0x6e, 0x3a, 0x20, 0x25, 0x64, - 0x00, 0x00, 0x4c, 0x33, 0x20, 0x61, 0x63, 0x63, 0x65, 0x73, 0x73, 0x20, 0x66, 0x61, 0x69, 0x6c, 0x65, 0x64, 0x2c, - 0x20, 0x63, 0x6d, 0x64, 0x3a, 0x20, 0x25, 0x64, 0x2c, 0x20, 0x6c, 0x65, 0x6e, 0x3a, 0x20, 0x25, 0x64, 0x20, 0x00, - 0x70, 0x69, 0x6e, 0x67, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x00, 0x4c, 0x33, 0x00, 0x00, 0x57, 0x52, 0x3a, - 0x20, 0x25, 0x64, 0x00, 0x00, 0x52, 0x44, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x00, 0x6d, 0x61, 0x63, 0x61, 0x6e, 0x64, - 0x64, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x00, 0x00, 0x73, 0x65, 0x6e, 0x74, 0x00, 0x00, 0x00, 0x00, 0x65, - 0x6e, 0x74, 0x65, 0x72, 0x20, 0x73, 0x6c, 0x65, 0x65, 0x70, 0x00, 0x77, 0x61, 0x6b, 0x65, 0x75, 0x70, 0x00, 0x00, - 0x56, 0x19, 0x10, 0x00, 0x94, 0x19, 0x10, 0x00, 0xc0, 0x19, 0x10, 0x00, 0xf0, 0x19, 0x10, 0x00, 0xf8, 0x13, 0x10, - 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, - 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, - 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0x0a, 0x1a, 0x10, 0x00, 0x64, 0x1a, 0x10, 0x00, 0x00, 0x00, 0x00, 0x01, - 0xfa, 0x5b, 0xe6, 0x65, 0x94, 0x14, 0x19, 0x43, 0x12, 0xb5, 0x4a, 0x89, 0x52, 0xb3, 0x04, 0x67, 0x99, 0xc7, 0xe2, - 0xaa, 0x16, 0xfd, 0x02, 0x6b, 0x91, 0x91, 0x34, 0xe8, 0x29, 0x9a, 0x23, 0x69, 0x70, 0x38, 0x59, 0x00, 0x00, 0x00, - 0x00, 0x80, 0x1f, 0x00, 0x06, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x1f, 0x00, 0x06, 0x02, 0x00, - 0x05, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x06, 0x03, 0x10, 0x08, 0x00, 0x00, 0x18, 0x00, 0x00, 0x40, - 0x1f, 0x00, 0x06, 0x06, 0x10, 0x08, 0x00, 0x04, 0x18, 0x00, 0x00, 0x60, 0x1f, 0x00, 0x06, 0x04, 0x00, 0x09, 0x01, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x06, 0x05, 0x05, 0x7f, 0x07, 0x01, 0x08, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x01, 0xf0, 0x01, 0x10, 0x10, 0x00, 0x04, 0x02, 0x11, 0x00, 0x44, 0x02, 0x12, 0x00, 0x84, 0x02, 0x20, 0x90, - 0x01, 0x03, 0x21, 0x80, 0x42, 0x03, 0x22, 0xf0, 0x01, 0x03, 0x30, 0x80, 0x02, 0x04, 0x31, 0x80, 0x42, 0x04, 0x40, - 0x70, 0x04, 0x11, 0x41, 0x70, 0x44, 0x11, 0x42, 0x70, 0x84, 0x11, 0x50, 0xf0, 0x01, 0x12, 0x60, 0x32, 0x04, 0x13, - 0x61, 0x32, 0x44, 0x13, 0x62, 0x32, 0x84, 0x13, 0x63, 0x32, 0xc4, 0x13, 0x70, 0x32, 0x04, 0x14, 0x71, 0x32, 0x44, - 0x14, 0x80, 0x20, 0x04, 0x15, 0x81, 0x20, 0x84, 0x15, 0x82, 0x20, 0x44, 0x15, 0x90, 0x51, 0x04, 0x16, 0x00, 0x00, - 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x14, 0x04, 0x04, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x20, 0x25, 0x6c, - 0x75, 0x20, 0x00, 0x00, 0xfa, 0xb6, 0x2d, 0x6e, 0x05, 0x7e, 0xb5, 0xdf, 0x94, 0xaf, 0xa1, 0xd8, 0xee, 0x79, 0x63, - 0x84, 0xef, 0x03, 0xc2, 0xf2, 0x80, 0x3b, 0x5e, 0xa0, 0x22, 0x75, 0xe1, 0x42, 0xaf, 0xae, 0xbe, 0xe6, 0xb2, 0x10, - 0x5a, 0x25, 0x73, 0x28, 0x25, 0x73, 0x29, 0x3a, 0x20, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x45, 0x00, - 0x00, 0x00, 0x4d, 0x53, 0x47, 0x00, 0x43, 0x52, 0x43, 0x20, 0x72, 0x78, 0x3a, 0x20, 0x25, 0x30, 0x34, 0x78, 0x2c, - 0x20, 0x63, 0x61, 0x6c, 0x63, 0x3a, 0x20, 0x25, 0x30, 0x34, 0x78, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, - 0xe4, 0x1f, 0x10, 0x00, 0x04, 0x20, 0x10, 0x00, 0x56, 0x20, 0x10, 0x00, 0xb8, 0x20, 0x10, 0x00, 0xc2, 0x20, 0x10, - 0x00, 0x4f, 0x53, 0x00, 0x00, 0x63, 0x6f, 0x6e, 0x64, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, 0x52, 0x58, - 0x3a, 0x20, 0x63, 0x6d, 0x64, 0x3d, 0x30, 0x78, 0x25, 0x30, 0x32, 0x78, 0x00, 0x00, 0x55, 0x49, 0x00, 0x00, 0x43, - 0x50, 0x42, 0x20, 0x49, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x20, 0x21, 0x00, 0x43, 0x50, 0x42, 0x00, - 0x57, 0x00, 0x00, 0x00, 0x46, 0x53, 0x53, 0x00, 0x49, 0x52, 0x51, 0x00, 0x53, 0x54, 0x3a, 0x20, 0x25, 0x78, 0x00, - 0x00, 0x4b, 0x44, 0x42, 0x00, 0x73, 0x74, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x4d, 0x41, 0x44, 0x00, 0x4f, 0x54, - 0x50, 0x00, 0x01, 0x00, 0x00, 0x00, 0x53, 0x43, 0x42, 0x00, 0x4e, 0x6f, 0x69, 0x73, 0x65, 0x5f, 0x4b, 0x4b, 0x31, - 0x5f, 0x32, 0x35, 0x35, 0x31, 0x39, 0x5f, 0x41, 0x45, 0x53, 0x47, 0x43, 0x4d, 0x5f, 0x53, 0x48, 0x41, 0x32, 0x35, - 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x66, 0x44, 0x14, 0xb7, 0x22, 0xdd, 0xc6, 0xc7, 0x09, 0xcf, 0xf2, - 0x78, 0x85, 0xe2, 0xdd, 0x16, 0xc4, 0x1f, 0xc9, 0x7b, 0x3f, 0x7a, 0x99, 0xc1, 0x2c, 0x16, 0xd4, 0x73, 0x2e, 0xed, - 0x78, 0x5a, 0xff, 0xe8, 0x5a, 0x14, 0x3f, 0x10, 0x00, 0x78, 0x45, 0x10, 0x00, 0x62, 0x45, 0x10, 0x00, 0x26, 0x45, - 0x10, 0x00, 0x3a, 0x3e, 0x10, 0x00, 0xd0, 0x45, 0x10, 0x00, 0x41, 0x4c, 0x41, 0x52, 0x4d, 0x20, 0x43, 0x48, 0x41, - 0x4e, 0x4e, 0x45, 0x4c, 0x53, 0x3a, 0x20, 0x25, 0x78, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x53, 0x43, 0x4e, 0x54, - 0x52, 0x00, 0x00, 0x00, 0x53, 0x50, 0x45, 0x43, 0x54, 0x00, 0x00, 0x00, 0xc3, 0x14, 0x13, 0x00, 0x72, 0xfc, 0x3d, - 0xf3, 0x51, 0xe5, 0x58, 0x83, 0x96, 0x66, 0x17, 0xb2, 0x9a, 0x92, 0xf7, 0x4e, 0x0e, 0x13, 0x7e, 0x2f, 0xa3, 0x4c, - 0x0c, 0x45, 0xe8, 0xcb, 0x26, 0x6e, 0x13, 0xb4, 0x0e, 0x4e, 0x05, 0xb0, 0x03, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x35, - 0xb7, 0x8a, 0xb8, 0x90, 0xb0, 0x09, 0xa1, 0xac, 0x6b, 0xa4, 0xc9, 0x67, 0xda, 0xee, 0xfd, 0xce, 0x9b, 0x31, 0x82, - 0x74, 0x2b, 0x6f, 0x6d, 0x61, 0x8b, 0x8e, 0x69, 0xa3, 0x6e, 0xb1, 0xf8, 0xd8, 0x02, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xfa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x01, - 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x2c, 0x57, 0x00, 0x00, 0x02, 0x41, 0xc9, 0x04, 0xe3, 0x51, 0x85, 0x8b, - 0x68, 0x79, 0xed, 0x3f, 0x06, 0xb0, 0xa3, 0x97, 0x8e, 0x8a, 0x18, 0xd6, 0x4d, 0x72, 0xb4, 0xcc, 0xb2, 0x13, 0xc3, - 0x64, 0x76, 0x30, 0xf7, 0x31, 0x82, 0x64, 0x8f, 0xda, 0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; \ No newline at end of file +const uint8_t fw_CPU[] = { + 0x68, 0x70, 0xb1, 0xbb, 0x03, 0x76, 0xd3, 0xeb, 0xa3, 0x1f, 0x17, 0x0b, 0xd6, 0xe9, 0xa7, 0x71, + 0x9a, 0x6b, 0x56, 0x39, 0x0d, 0xb1, 0xde, 0x1a, 0xca, 0x8e, 0x49, 0x6c, 0xa5, 0x44, 0x3d, 0x07, + 0x20, 0x22, 0x52, 0xe9, 0x7b, 0x4e, 0x73, 0x3e, 0xe8, 0xb5, 0x17, 0xc2, 0x78, 0x17, 0xb9, 0x38, + 0xd0, 0xc7, 0x0d, 0x59, 0xb0, 0x8a, 0x12, 0x8e, 0x5f, 0x73, 0xc0, 0xe8, 0x98, 0xac, 0x2c, 0x99, + 0x09, 0x57, 0x63, 0xe5, 0xd8, 0x66, 0xf0, 0xa5, 0x9a, 0x74, 0xbe, 0x1e, 0xc9, 0x13, 0x20, 0xfc, + 0xfd, 0xf1, 0xdf, 0x89, 0x0f, 0x12, 0xbf, 0xbe, 0x6e, 0x3f, 0xed, 0x34, 0x15, 0xc4, 0x48, 0xef, + 0x99, 0x01, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x62, 0xa8, 0xa4, 0xc9, 0x1e, 0x08, 0x14, + 0xcf, 0xde, 0xa6, 0xfa, 0xcd, 0x68, 0xf9, 0x5f, 0x86, 0x6d, 0xa5, 0xf9, 0xa8, 0xc9, 0x2c, 0x23, + 0xbd, 0x15, 0x9a, 0x49, 0x59, 0xdd, 0x24, 0x00, 0x8a, 0xdd, 0x00, 0x00, 0xef, 0x25, 0x51, 0xc4, + 0x62, 0x58, 0xf3, 0xef, 0x90, 0x39, 0x9c, 0x53, 0x1e, 0xfb, 0x13, 0x4c, 0x20, 0x31, 0x9f, 0xa7, + 0x2c, 0xa3, 0xef, 0xf8, 0x27, 0x71, 0xad, 0xbb, 0x2b, 0x6c, 0x99, 0x5d, 0x2c, 0x99, 0x93, 0xbc, + 0xc3, 0x4e, 0xad, 0x17, 0xae, 0x63, 0xbb, 0x3c, 0xf4, 0xba, 0xc2, 0x74, 0x88, 0x98, 0xb2, 0xcc, + 0xd9, 0x5d, 0xcd, 0xe5, 0x58, 0xd9, 0x90, 0x58, 0x26, 0x01, 0x68, 0x09, 0xfa, 0x20, 0x91, 0x2a, + 0xd6, 0x43, 0x1d, 0x26, 0x26, 0x85, 0xe3, 0x13, 0x01, 0xd0, 0x99, 0xe9, 0x77, 0x71, 0xf1, 0x77, + 0x5c, 0x3e, 0x10, 0x96, 0xea, 0x64, 0x7f, 0x67, 0xe6, 0x3b, 0x2c, 0xba, 0x09, 0x00, 0x04, 0x6f, + 0x30, 0x00, 0x43, 0x6f, 0x30, 0x20, 0x3d, 0x6f, 0x30, 0xe0, 0x3c, 0x6f, 0x30, 0xa0, 0x3c, 0x6f, + 0x30, 0x60, 0x3c, 0x6f, 0x30, 0x20, 0x3c, 0x6f, 0x30, 0xe0, 0x3b, 0x6f, 0x50, 0x60, 0x04, 0x6f, + 0x30, 0x60, 0x3b, 0x6f, 0x30, 0x20, 0x3b, 0x6f, 0x30, 0xe0, 0x3a, 0x6f, 0x30, 0xa0, 0x7f, 0x6f, + 0x30, 0x60, 0x3a, 0x6f, 0x30, 0x20, 0x3a, 0x6f, 0x30, 0xe0, 0x39, 0x6f, 0x30, 0xa0, 0x39, 0x6f, + 0x40, 0xf0, 0x72, 0x6f, 0x30, 0x20, 0x26, 0x6f, 0x30, 0x50, 0x20, 0x6f, 0x40, 0x30, 0x22, 0x6f, + 0x40, 0xf0, 0x21, 0x6f, 0x40, 0xb0, 0x21, 0x6f, 0x30, 0xa0, 0x4c, 0x6f, 0x30, 0xa0, 0x4d, 0x6f, + 0x30, 0xf0, 0x42, 0x6f, 0x40, 0x50, 0x56, 0x6f, 0x30, 0x20, 0x4e, 0x6f, 0x20, 0x30, 0x1f, 0x6f, + 0x40, 0x70, 0x0a, 0x6f, 0x30, 0xa0, 0x4e, 0x6f, 0x30, 0x00, 0x5b, 0x6f, 0x30, 0x00, 0x3f, 0x93, + 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x93, 0x01, 0x00, 0x00, 0x13, 0x02, 0x00, 0x00, 0x93, + 0x02, 0x00, 0x00, 0x13, 0x03, 0x00, 0x00, 0x93, 0x03, 0x00, 0x00, 0x13, 0x04, 0x00, 0x00, 0x93, + 0x04, 0x00, 0x00, 0x13, 0x05, 0x00, 0x00, 0x93, 0x05, 0x00, 0x00, 0x13, 0x06, 0x00, 0x00, 0x93, + 0x06, 0x00, 0x00, 0x13, 0x07, 0x00, 0x00, 0x93, 0x07, 0x00, 0x00, 0x13, 0x08, 0x00, 0x00, 0x93, + 0x08, 0x00, 0x00, 0x13, 0x09, 0x00, 0x00, 0x93, 0x09, 0x00, 0x00, 0x13, 0x0a, 0x00, 0x00, 0x93, + 0x0a, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0xfa, 0x9c, 0xe5, 0xf5, 0x8c, 0x84, 0x0f, 0x0e, 0x2a, + 0x87, 0xe6, 0x25, 0xcf, 0xef, 0xeb, 0x37, 0xdd, 0x0a, 0x5b, 0x91, 0x11, 0xbf, 0x46, 0x5a, 0xbf, + 0x10, 0x51, 0x9d, 0xa5, 0x6d, 0x07, 0x89, 0xcf, 0xd8, 0x04, 0x93, 0x0b, 0x00, 0x00, 0x13, 0x0c, + 0x00, 0x00, 0x93, 0x0c, 0x00, 0x00, 0x13, 0x0d, 0x00, 0x00, 0x93, 0x0d, 0x00, 0x00, 0x13, 0x0e, + 0x00, 0x00, 0x93, 0x0e, 0x00, 0x00, 0x13, 0x0f, 0x00, 0x00, 0x93, 0x0f, 0x00, 0x00, 0x97, 0x00, + 0x00, 0x00, 0x93, 0x80, 0x40, 0xf0, 0x73, 0x90, 0x50, 0x30, 0x93, 0x00, 0x00, 0x00, 0x17, 0x41, + 0x10, 0x00, 0x13, 0x01, 0x41, 0xcf, 0x33, 0x04, 0x01, 0x00, 0x17, 0x0d, 0x10, 0x00, 0x13, 0x0d, + 0x8d, 0xee, 0x97, 0x4d, 0x10, 0x00, 0x93, 0x8d, 0x0d, 0xce, 0x63, 0x57, 0xbd, 0x01, 0x23, 0x20, + 0x0d, 0x00, 0x11, 0x0d, 0xe3, 0x4d, 0xbd, 0xff, 0xef, 0x00, 0xf0, 0x60, 0x73, 0x00, 0x50, 0x10, + 0xf5, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa6, 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, + 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0x07, 0xf2, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, + 0x07, 0xf2, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x88, 0x07, 0xf2, 0x82, 0x80, 0x18, 0x41, 0xfd, 0x57, + 0x63, 0x02, 0xf7, 0x06, 0x13, 0x07, 0x45, 0x00, 0x81, 0x47, 0x13, 0x06, 0xf0, 0x07, 0x14, 0x43, + 0x81, 0xea, 0x85, 0x07, 0x11, 0x07, 0xe3, 0x9c, 0xc7, 0xfe, 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, + 0x01, 0x47, 0x93, 0x05, 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, 0x05, 0x8a, 0x19, 0xca, 0x93, 0x05, + 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, 0x05, 0x8a, 0x15, 0xc6, 0x05, 0x07, 0xe3, 0x1b, 0xb7, 0xfe, + 0x21, 0xa0, 0xfa, 0x57, 0xdb, 0x24, 0xb7, 0xdb, 0xed, 0x73, 0x27, 0xf3, 0x7d, 0xf6, 0x3d, 0xa0, + 0xc4, 0x32, 0x90, 0x77, 0x37, 0xaa, 0xce, 0xf8, 0xf0, 0x28, 0x21, 0xbd, 0x40, 0x3b, 0x80, 0xc3, + 0xee, 0x3c, 0xd2, 0xb0, 0x05, 0x05, 0x07, 0xe3, 0x11, 0xb7, 0xfe, 0x89, 0x07, 0x93, 0x06, 0x00, + 0x08, 0x7d, 0x56, 0xe3, 0x85, 0xd7, 0xfc, 0x85, 0x07, 0x13, 0x97, 0x27, 0x00, 0x2a, 0x97, 0x03, + 0x27, 0xc7, 0xff, 0xe3, 0x08, 0xc7, 0xfe, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x05, 0x67, 0xaa, + 0x87, 0x01, 0x17, 0x01, 0x45, 0x94, 0x43, 0x99, 0xe6, 0x13, 0x05, 0x05, 0x02, 0x91, 0x07, 0xe3, + 0x1b, 0xe5, 0xfe, 0x82, 0x80, 0x81, 0x47, 0x13, 0x06, 0x00, 0x02, 0x33, 0xd7, 0xf6, 0x00, 0x05, + 0x8b, 0x09, 0xe7, 0x85, 0x07, 0x05, 0x05, 0xe3, 0x9a, 0xc7, 0xfe, 0x82, 0x80, 0x41, 0x11, 0x22, + 0xc4, 0x37, 0x14, 0x20, 0x00, 0x13, 0x04, 0x04, 0x00, 0x83, 0x46, 0x94, 0x07, 0x37, 0x56, 0x10, + 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, 0x64, 0x13, 0x06, 0x06, + 0x3d, 0x93, 0x85, 0xc5, 0x3d, 0x06, 0xc6, 0xef, 0x10, 0x30, 0x4c, 0x03, 0x45, 0x94, 0x07, 0xb2, + 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x40, 0x90, 0x0b, 0xef, + 0x20, 0xc0, 0x58, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x00, 0xb2, 0x40, 0x41, 0x01, 0x6f, + 0x40, 0x50, 0x0c, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x05, 0x05, + 0x10, 0x2a, 0x84, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, 0x3e, 0x06, 0xc6, 0xef, 0x10, 0x30, + 0x4f, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf5, 0x14, 0x43, 0x85, 0x47, 0xfa, 0x59, 0xbf, + 0xf4, 0xad, 0x63, 0x04, 0x46, 0x53, 0xa5, 0x44, 0xcc, 0x31, 0x35, 0x24, 0xa1, 0x6a, 0xd3, 0x8c, + 0xa1, 0x62, 0x62, 0xb6, 0x3f, 0xb7, 0x22, 0x80, 0xea, 0x6b, 0xe8, 0x81, 0x18, 0xe2, 0x88, 0x06, + 0xb3, 0x97, 0x87, 0x00, 0xb2, 0x40, 0x22, 0x44, 0x93, 0xc7, 0xf7, 0xff, 0xf5, 0x8f, 0x1c, 0xc3, + 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x2a, 0x84, 0x93, 0x04, + 0xa0, 0x0a, 0xef, 0x20, 0x10, 0x76, 0x63, 0x19, 0x95, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, + 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x22, 0x85, 0xef, 0x20, 0x90, 0x78, 0x22, 0x85, + 0xef, 0x20, 0x30, 0x74, 0xe3, 0x03, 0x95, 0xfe, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, 0x3e, + 0x85, 0x45, 0xef, 0x10, 0x10, 0x49, 0x13, 0x05, 0x50, 0x05, 0xd1, 0xbf, 0x01, 0x11, 0x22, 0xcc, + 0x2a, 0x84, 0x37, 0x35, 0x00, 0x08, 0x06, 0xce, 0x2e, 0xc6, 0xef, 0x30, 0x10, 0x0a, 0x32, 0x46, + 0xa2, 0x85, 0x37, 0x35, 0x00, 0x08, 0xef, 0x30, 0x50, 0x0e, 0x62, 0x44, 0xf2, 0x40, 0x37, 0x35, + 0x00, 0x08, 0x05, 0x61, 0x6f, 0x30, 0xb0, 0x0b, 0x6d, 0x71, 0x23, 0x24, 0x81, 0x10, 0x2a, 0x84, + 0x0a, 0x85, 0x23, 0x26, 0x11, 0x10, 0xef, 0x10, 0x50, 0x63, 0x0a, 0x85, 0x23, 0x00, 0x81, 0x00, + 0xef, 0x20, 0xc0, 0x3e, 0x83, 0x20, 0xc1, 0x10, 0x03, 0x24, 0x81, 0x10, 0x51, 0x61, 0x82, 0x80, + 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0x2e, 0xc4, 0xef, 0x20, 0xd0, 0x1a, 0xa2, 0x45, 0x32, 0x45, + 0xef, 0x20, 0xd0, 0x32, 0x2a, 0xc4, 0xef, 0x20, 0x90, 0x1b, 0xf2, 0x40, 0x22, 0x45, 0x05, 0x61, + 0x82, 0x80, 0x13, 0x01, 0x01, 0xde, 0x23, 0x2c, 0xfa, 0xc6, 0x03, 0x29, 0x4e, 0xde, 0x34, 0xe2, + 0xc9, 0xfa, 0x6b, 0x81, 0xdb, 0x3a, 0x6a, 0xb6, 0x96, 0x0e, 0xf4, 0x01, 0xb5, 0xb0, 0xb1, 0xe3, + 0x75, 0xb9, 0x0d, 0xd1, 0xfc, 0x48, 0x06, 0xdc, 0xf7, 0x60, 0x07, 0x81, 0x20, 0x2e, 0x84, 0xaa, + 0x05, 0x23, 0x28, 0x21, 0x21, 0x93, 0x85, 0x05, 0x20, 0x2a, 0x89, 0x08, 0x08, 0x23, 0x2e, 0x11, + 0x20, 0x23, 0x2a, 0x91, 0x20, 0x7d, 0x3f, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x04, 0xaa, + 0x84, 0x08, 0x08, 0xcd, 0x33, 0x63, 0x00, 0x95, 0x02, 0x22, 0x85, 0xd1, 0x3d, 0x09, 0x45, 0x83, + 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, 0x41, 0x21, 0x03, 0x29, 0x01, 0x21, 0x13, + 0x01, 0x01, 0x22, 0x82, 0x80, 0x42, 0x44, 0x48, 0x08, 0x22, 0xc6, 0x25, 0x35, 0x09, 0x8c, 0x11, + 0x46, 0x6c, 0x00, 0x4a, 0x85, 0x22, 0xc6, 0xef, 0x40, 0x70, 0x7c, 0x05, 0x45, 0xc9, 0xbf, 0x01, + 0x45, 0xf9, 0xb7, 0x41, 0x11, 0x4a, 0xc0, 0x03, 0xa9, 0x05, 0x00, 0x06, 0xc6, 0x22, 0xc4, 0x26, + 0xc2, 0x2e, 0x84, 0xaa, 0x84, 0xef, 0x20, 0x10, 0x67, 0xca, 0x85, 0x26, 0x85, 0xef, 0x20, 0x70, + 0x1e, 0xa6, 0x85, 0x22, 0x85, 0xef, 0x20, 0xb0, 0x28, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, + 0x02, 0x1c, 0x40, 0x63, 0x93, 0x27, 0x03, 0x93, 0x07, 0x44, 0x00, 0x7d, 0x57, 0x13, 0x04, 0x04, + 0x20, 0x94, 0x43, 0x63, 0x9b, 0xe6, 0x00, 0x91, 0x07, 0xe3, 0x9c, 0x87, 0xfe, 0xb2, 0x40, 0x22, + 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0xc5, 0xbf, 0x13, + 0x01, 0x01, 0xde, 0x23, 0x26, 0x31, 0x21, 0x93, 0x19, 0xa5, 0x00, 0x23, 0x2a, 0x91, 0x20, 0x93, + 0x84, 0x09, 0x20, 0xfa, 0x2c, 0x73, 0xd8, 0x55, 0xaa, 0x7e, 0x1d, 0xe9, 0x05, 0x57, 0xf7, 0x39, + 0x87, 0xb7, 0xf1, 0xe9, 0x81, 0xb7, 0x1d, 0x0b, 0x60, 0x90, 0x74, 0x01, 0x6d, 0x25, 0xb4, 0x2b, + 0xe5, 0xec, 0x18, 0xf2, 0x38, 0x08, 0x23, 0x2c, 0x81, 0x20, 0xa6, 0x85, 0x2a, 0x84, 0x0a, 0x85, + 0x23, 0x2e, 0x11, 0x20, 0x23, 0x28, 0x21, 0x21, 0xfd, 0x35, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x00, + 0xf5, 0x02, 0x01, 0x45, 0x83, 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, 0x41, 0x21, + 0x03, 0x29, 0x01, 0x21, 0x83, 0x29, 0xc1, 0x20, 0x13, 0x01, 0x01, 0x22, 0x82, 0x80, 0x2a, 0x89, + 0x0a, 0x85, 0xdd, 0x39, 0x63, 0x06, 0x25, 0x01, 0x22, 0x85, 0xe5, 0x33, 0x09, 0x45, 0xd9, 0xbf, + 0x02, 0x44, 0x48, 0x00, 0x89, 0x3b, 0xaa, 0x87, 0x33, 0x06, 0xa4, 0x40, 0x0d, 0x45, 0xe3, 0x03, + 0xf4, 0xfc, 0x09, 0x45, 0xe3, 0x60, 0xc4, 0xfc, 0x5c, 0x00, 0x01, 0x44, 0x13, 0x08, 0x00, 0x02, + 0x13, 0x05, 0xf0, 0x07, 0x8c, 0x43, 0x89, 0xc9, 0x81, 0x46, 0x33, 0xd7, 0xd5, 0x00, 0x05, 0x8b, + 0x05, 0xeb, 0x85, 0x06, 0xe3, 0x9b, 0x06, 0xff, 0x05, 0x04, 0x91, 0x07, 0xe3, 0x14, 0xa4, 0xfe, + 0x7d, 0x16, 0x8a, 0x85, 0x13, 0x85, 0x09, 0x40, 0x32, 0xc0, 0xf5, 0x3d, 0x93, 0x07, 0xa0, 0x0a, + 0xe3, 0x11, 0xf5, 0xf8, 0x8a, 0x85, 0x26, 0x85, 0xfd, 0x35, 0x13, 0x05, 0x65, 0xf5, 0x1d, 0xa8, + 0x05, 0x47, 0x33, 0x17, 0xd7, 0x00, 0x13, 0x47, 0xf7, 0xff, 0x6d, 0x8f, 0x98, 0xc3, 0xef, 0x20, + 0xc0, 0x7f, 0x18, 0x04, 0x93, 0x17, 0x24, 0x00, 0xba, 0x97, 0x83, 0xa5, 0x47, 0xe0, 0x13, 0x05, + 0x14, 0x00, 0x0a, 0x05, 0x26, 0x95, 0xef, 0x20, 0x50, 0x10, 0x2a, 0x84, 0xef, 0x20, 0xfa, 0xbd, + 0x19, 0x5d, 0x49, 0xa5, 0xda, 0x4f, 0x06, 0x0c, 0xf7, 0x78, 0xfd, 0x53, 0x5d, 0xbc, 0xcd, 0xd1, + 0x76, 0x98, 0x49, 0xe3, 0xf0, 0x8d, 0xb0, 0xae, 0xd2, 0x74, 0x74, 0x22, 0x6c, 0x53, 0x59, 0x10, + 0x09, 0x80, 0x7f, 0x13, 0x05, 0x64, 0xf5, 0x13, 0x35, 0x15, 0x00, 0x35, 0xbf, 0x41, 0x11, 0x22, + 0xc4, 0x06, 0xc6, 0x93, 0x07, 0x30, 0x0c, 0x2a, 0x84, 0x63, 0x04, 0xf5, 0x00, 0xef, 0x20, 0xc0, + 0x4b, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x05, 0x67, 0x23, 0x80, 0x87, 0x00, 0xba, + 0x97, 0xf8, 0x5b, 0x19, 0xe3, 0x05, 0x47, 0xf8, 0xdb, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, + 0x80, 0x05, 0x66, 0x37, 0x05, 0x20, 0x00, 0x41, 0x11, 0x13, 0x06, 0xc6, 0x07, 0x81, 0x45, 0x13, + 0x05, 0x05, 0x00, 0x06, 0xc6, 0xef, 0x40, 0xb0, 0x65, 0xef, 0x20, 0x80, 0x41, 0xef, 0x40, 0x80, + 0x39, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x20, 0x00, 0x38, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x20, 0x00, + 0x55, 0xef, 0x20, 0x90, 0x7f, 0xef, 0x40, 0xa0, 0x0c, 0xef, 0x40, 0x00, 0x65, 0xb2, 0x40, 0x41, + 0x01, 0x6f, 0x30, 0xe0, 0x15, 0x69, 0x71, 0x08, 0x08, 0x23, 0x22, 0x91, 0x12, 0x23, 0x20, 0x21, + 0x13, 0x23, 0x2c, 0x41, 0x11, 0x23, 0x26, 0x11, 0x12, 0x23, 0x24, 0x81, 0x12, 0x23, 0x2e, 0x31, + 0x11, 0x23, 0x2a, 0x51, 0x11, 0xef, 0x10, 0xf0, 0x39, 0x91, 0x47, 0x37, 0x39, 0x20, 0x00, 0x23, + 0x08, 0xf1, 0x00, 0x83, 0x27, 0xc9, 0xf4, 0x37, 0x1a, 0x20, 0x00, 0xb7, 0x34, 0x20, 0x00, 0x13, + 0x09, 0xc9, 0xf4, 0x13, 0x0a, 0x0a, 0x00, 0x93, 0x84, 0x84, 0xf4, 0xc5, 0xe7, 0x83, 0x27, 0x4a, + 0x07, 0x09, 0x46, 0x6c, 0x00, 0x23, 0x20, 0xf9, 0x00, 0xfa, 0xf1, 0xae, 0x16, 0x45, 0x1a, 0xc9, + 0x45, 0x3f, 0x22, 0x04, 0x4e, 0x6b, 0x88, 0x02, 0x1d, 0xc5, 0xd3, 0x95, 0xba, 0xc3, 0x14, 0xed, + 0xa4, 0x46, 0x9e, 0x09, 0x95, 0xcf, 0xd6, 0x78, 0xf6, 0x18, 0xe8, 0x09, 0x13, 0x05, 0x21, 0x01, + 0xc1, 0x17, 0x3e, 0xc6, 0x23, 0xa0, 0x04, 0x00, 0xef, 0x40, 0xf0, 0x58, 0x89, 0x47, 0xa3, 0x08, + 0xf1, 0x00, 0x13, 0x04, 0xe0, 0x07, 0x93, 0x09, 0x41, 0x01, 0x03, 0x27, 0x09, 0x00, 0x94, 0x40, + 0xb3, 0x07, 0xd7, 0x40, 0x63, 0xf3, 0x87, 0x00, 0x3e, 0x84, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x5a, + 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0xa2, 0x87, 0x93, 0x85, 0xca, 0x3f, 0x13, 0x06, 0xc6, 0x3e, + 0x13, 0x05, 0x45, 0x40, 0xef, 0x10, 0x50, 0x0c, 0x8c, 0x40, 0x83, 0x27, 0x4a, 0x07, 0x33, 0x07, + 0xb4, 0x00, 0x63, 0xf7, 0xe7, 0x04, 0x8d, 0x45, 0x13, 0x85, 0xca, 0x3f, 0xef, 0x10, 0x30, 0x12, + 0x13, 0x04, 0x50, 0x05, 0xc5, 0x3c, 0xef, 0x40, 0x60, 0x2a, 0xef, 0x20, 0xa0, 0x32, 0xef, 0x20, + 0xa0, 0x29, 0x29, 0x3f, 0x83, 0x20, 0xc1, 0x12, 0x22, 0x85, 0x03, 0x24, 0x81, 0x12, 0x83, 0x24, + 0x41, 0x12, 0x03, 0x29, 0x01, 0x12, 0x83, 0x29, 0xc1, 0x11, 0x03, 0x2a, 0x81, 0x11, 0x83, 0x2a, + 0x41, 0x11, 0x55, 0x61, 0x82, 0x80, 0x13, 0x04, 0x00, 0x08, 0x93, 0x09, 0x21, 0x01, 0xb5, 0xbf, + 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x22, 0x86, 0xbe, 0x95, 0x4e, 0x85, 0xef, 0x40, + 0x90, 0x4e, 0x83, 0x47, 0x11, 0x01, 0x98, 0x40, 0x22, 0x97, 0x3e, 0x94, 0x83, 0x27, 0x09, 0x00, + 0xa3, 0x08, 0x81, 0x00, 0x98, 0xc0, 0x13, 0x04, 0x50, 0x05, 0x63, 0x17, 0xf7, 0x00, 0x89, 0x47, + 0x23, 0x08, 0xf1, 0x00, 0xfa, 0x86, 0x2e, 0x0a, 0x72, 0xca, 0x02, 0xc4, 0x19, 0x01, 0x39, 0xe4, + 0x81, 0x08, 0xe3, 0x39, 0xdd, 0x8f, 0xc6, 0x5c, 0xec, 0x85, 0x7d, 0xc5, 0x2b, 0x95, 0xa8, 0xa0, + 0xf1, 0xa3, 0x6a, 0xcc, 0x9e, 0xc0, 0x0a, 0x13, 0x04, 0xa0, 0x0a, 0x08, 0x08, 0xef, 0x20, 0xe0, + 0x04, 0x59, 0xbf, 0x41, 0x11, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x06, 0xc6, 0x23, + 0xae, 0xe7, 0xf2, 0xef, 0x20, 0xe0, 0x26, 0x85, 0x3d, 0xb9, 0x3c, 0xef, 0x30, 0x20, 0x07, 0x41, + 0x3d, 0xb2, 0x40, 0x1d, 0x65, 0x13, 0x05, 0x05, 0x6c, 0x41, 0x01, 0x6f, 0x30, 0x00, 0x0f, 0x41, + 0x11, 0x26, 0xc2, 0xae, 0x84, 0xb6, 0x85, 0x06, 0xc6, 0x22, 0xc4, 0x4a, 0xc0, 0x36, 0x84, 0x32, + 0x89, 0xef, 0x40, 0x40, 0x4f, 0x22, 0x86, 0xca, 0x85, 0x13, 0x05, 0x00, 0x02, 0xef, 0x40, 0x00, + 0x58, 0xef, 0x40, 0x60, 0x4c, 0xef, 0x40, 0xe0, 0x67, 0x93, 0x07, 0xa0, 0x0a, 0x13, 0x04, 0x50, + 0x05, 0x63, 0x1a, 0xf5, 0x00, 0x2a, 0x84, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0x00, 0x02, 0x26, + 0x85, 0xef, 0x40, 0xe0, 0x50, 0xb2, 0x40, 0x22, 0x85, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, + 0x01, 0x82, 0x80, 0x85, 0x67, 0xc1, 0x07, 0x63, 0xee, 0xb7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x26, + 0xc2, 0x06, 0xc6, 0xae, 0x84, 0x37, 0x04, 0x20, 0x00, 0x19, 0xc5, 0x2e, 0x86, 0xaa, 0x85, 0x13, + 0x05, 0x04, 0x00, 0xef, 0x40, 0xd0, 0x42, 0x13, 0x04, 0x04, 0x00, 0x93, 0x07, 0x30, 0xfc, 0x23, + 0x00, 0xf4, 0x00, 0x85, 0x67, 0x3e, 0x94, 0x64, 0xd8, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, + 0x01, 0x82, 0x80, 0x82, 0x80, 0x13, 0x01, 0x01, 0xdd, 0x23, 0x24, 0x81, 0x22, 0x23, 0x22, 0xfa, + 0x54, 0x8d, 0x08, 0xe6, 0xc4, 0x7c, 0xba, 0xd3, 0xc6, 0xc6, 0xba, 0x82, 0x12, 0x09, 0xe3, 0x34, + 0x53, 0xf0, 0xdc, 0x14, 0x07, 0x20, 0xe4, 0x63, 0xd2, 0x89, 0x86, 0xea, 0x9a, 0xd9, 0xc6, 0x50, + 0x98, 0x0b, 0x91, 0x22, 0x23, 0x20, 0x21, 0x23, 0x23, 0x2e, 0x31, 0x21, 0x23, 0x2c, 0x41, 0x21, + 0x23, 0x2a, 0x51, 0x21, 0x23, 0x28, 0x61, 0x21, 0x23, 0x26, 0x71, 0x21, 0x23, 0x24, 0x81, 0x21, + 0x23, 0x26, 0x11, 0x22, 0x13, 0x04, 0x00, 0x20, 0x01, 0x49, 0x93, 0x04, 0xa0, 0x0a, 0x37, 0x3a, + 0x20, 0x00, 0x85, 0x4a, 0x37, 0x5b, 0x10, 0x00, 0xb7, 0x5b, 0x10, 0x00, 0x37, 0x5c, 0x10, 0x00, + 0xc1, 0x49, 0xa2, 0x85, 0x0a, 0x85, 0xb1, 0x3e, 0x63, 0x16, 0x95, 0x02, 0x0a, 0x85, 0x59, 0x32, + 0x63, 0x1e, 0x95, 0x04, 0x13, 0x07, 0x4a, 0xf5, 0x14, 0x43, 0xb3, 0x97, 0x2a, 0x01, 0x13, 0x06, + 0x8b, 0x40, 0xd5, 0x8f, 0x93, 0x85, 0x4b, 0x3e, 0xca, 0x86, 0x13, 0x05, 0x4c, 0x64, 0x1c, 0xc3, + 0xef, 0x10, 0xe0, 0x6e, 0x05, 0x09, 0x13, 0x04, 0x04, 0x40, 0xe3, 0x14, 0x39, 0xfd, 0x83, 0x20, + 0xc1, 0x22, 0x03, 0x24, 0x81, 0x22, 0x83, 0x24, 0x41, 0x22, 0x03, 0x29, 0x01, 0x22, 0x83, 0x29, + 0xc1, 0x21, 0x03, 0x2a, 0x81, 0x21, 0x83, 0x2a, 0x41, 0x21, 0x03, 0x2b, 0x01, 0x21, 0x83, 0x2b, + 0xc1, 0x20, 0x03, 0x2c, 0x81, 0x20, 0x13, 0x01, 0x01, 0x23, 0x82, 0x80, 0x93, 0x05, 0x04, 0x20, + 0x0a, 0x85, 0xc5, 0x3c, 0xe3, 0x10, 0x95, 0xfc, 0x0a, 0x85, 0xef, 0xf0, 0xbf, 0x91, 0xe3, 0x1b, + 0x95, 0xfa, 0x22, 0x85, 0xef, 0x20, 0x10, 0x1f, 0x8a, 0x85, 0x22, 0x85, 0xef, 0x20, 0x70, 0x06, + 0xa2, 0x85, 0x0a, 0x85, 0xf9, 0x34, 0xe3, 0x1f, 0x95, 0xf8, 0xfa, 0x3e, 0x69, 0x40, 0xa9, 0xce, + 0x29, 0x6c, 0x9d, 0x5e, 0x24, 0xaa, 0x13, 0x12, 0x1f, 0x4a, 0x1d, 0x17, 0x21, 0x1f, 0xa9, 0xc5, + 0xbb, 0x64, 0xbe, 0x0a, 0x52, 0xd8, 0x35, 0xeb, 0x84, 0xa8, 0xd1, 0x70, 0x0c, 0x0a, 0x85, 0xef, + 0xf0, 0x9f, 0x8f, 0xe3, 0x0a, 0x95, 0xf6, 0x41, 0xbf, 0xb7, 0x05, 0x00, 0x80, 0x37, 0x55, 0x10, + 0x00, 0x86, 0x87, 0x6d, 0x71, 0xbe, 0x95, 0x13, 0x05, 0x45, 0x41, 0x23, 0x26, 0x11, 0x10, 0xef, + 0x10, 0x80, 0x6d, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x87, 0xf2, 0x93, 0x07, 0xa0, 0x0a, 0x63, + 0x1e, 0xf7, 0x02, 0x37, 0x15, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x9a, 0xef, 0x10, 0xf0, 0x5f, 0x13, + 0x05, 0xc0, 0x0f, 0xef, 0x10, 0xa0, 0x5a, 0x0a, 0x85, 0xef, 0x10, 0x70, 0x09, 0x93, 0x07, 0xf0, + 0x07, 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x00, 0x23, 0x00, 0xf1, 0x00, 0xef, 0x10, 0x00, + 0x54, 0xa3, 0x00, 0xa1, 0x00, 0x0a, 0x85, 0xef, 0x10, 0x70, 0x60, 0x05, 0x45, 0xef, 0x40, 0x00, + 0x67, 0xef, 0x40, 0x00, 0x66, 0xd5, 0x33, 0xef, 0x10, 0x50, 0x2d, 0xf5, 0xbf, 0x41, 0x11, 0x06, + 0xc6, 0x22, 0xc4, 0xef, 0x40, 0x60, 0x4c, 0x93, 0x07, 0x00, 0x08, 0x63, 0xf3, 0xa7, 0x00, 0xad, + 0x3f, 0x2a, 0x84, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0x50, 0x7e, 0xb7, 0x17, 0x20, 0x00, 0xb2, + 0x40, 0x23, 0xaa, 0x87, 0x06, 0x22, 0x44, 0x13, 0x05, 0x30, 0x0c, 0x41, 0x01, 0x82, 0x80, 0x93, + 0x07, 0xf0, 0x17, 0x63, 0xf5, 0xa7, 0x00, 0x41, 0x11, 0x06, 0xc6, 0xb9, 0x37, 0x6f, 0x10, 0xb0, + 0x3e, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x4a, 0xc0, 0x2e, 0x84, 0x06, 0xc6, 0xaa, 0x84, 0xc5, + 0x37, 0x61, 0x8d, 0x13, 0x09, 0xfa, 0x7c, 0x26, 0x5d, 0xf8, 0x44, 0x1b, 0xef, 0x93, 0x9f, 0xcb, + 0x8c, 0xb2, 0xdc, 0xfb, 0xf9, 0x24, 0xc8, 0xc5, 0x20, 0x3e, 0xf7, 0xd6, 0x32, 0x8d, 0x5d, 0xaa, + 0x96, 0x88, 0x95, 0xf9, 0x54, 0xfd, 0x48, 0x0d, 0x50, 0x05, 0x19, 0xc1, 0x13, 0x09, 0xa0, 0x0a, + 0x26, 0x85, 0xc1, 0x3f, 0x69, 0x8c, 0x13, 0x05, 0xa0, 0x0a, 0x19, 0xe0, 0x13, 0x05, 0x50, 0x05, + 0x63, 0x03, 0x25, 0x01, 0x21, 0x3f, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, + 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x8d, 0x47, 0x63, 0xf3, 0xa7, 0x00, 0x01, 0x37, 0x89, 0x67, + 0x93, 0x87, 0x07, 0xbf, 0x0a, 0x05, 0x3e, 0x95, 0xef, 0x30, 0xe0, 0x02, 0xaa, 0x87, 0x13, 0x07, + 0xf0, 0x0f, 0x55, 0x45, 0x63, 0x89, 0xe7, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x59, 0x45, 0x63, 0x94, + 0xe7, 0x00, 0x13, 0x05, 0x30, 0x0c, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x21, 0x71, 0x23, 0x2c, + 0x81, 0x1a, 0x2a, 0x84, 0x08, 0x09, 0x23, 0x2e, 0x11, 0x1a, 0x23, 0x2a, 0x91, 0x1a, 0x23, 0x28, + 0x21, 0x1b, 0x23, 0x26, 0x31, 0x1b, 0x23, 0x24, 0x41, 0x1b, 0x23, 0x22, 0x51, 0x1b, 0x23, 0x20, + 0x61, 0x1b, 0x23, 0x2e, 0x71, 0x19, 0x23, 0x2c, 0x81, 0x19, 0x23, 0x2a, 0x91, 0x19, 0xef, 0x10, + 0x40, 0x77, 0x83, 0x47, 0x04, 0x00, 0x05, 0x47, 0x23, 0x18, 0xe1, 0x08, 0xc1, 0x46, 0x63, 0x80, + 0xd7, 0x46, 0x63, 0xee, 0xf6, 0x02, 0x91, 0x46, 0x63, 0x88, 0xd7, 0x34, 0x63, 0xe1, 0xf6, 0x02, + 0x63, 0x86, 0xe7, 0x06, 0x09, 0x47, 0x63, 0x81, 0xe7, 0x0e, 0x93, 0x07, 0xe0, 0x07, 0x23, 0x08, + 0xf1, 0x08, 0x08, 0x09, 0xef, 0x10, 0xd0, 0x4c, 0x93, 0x07, 0x50, 0x05, 0x99, 0xa1, 0x21, 0x47, + 0xfa, 0xc2, 0x50, 0xe2, 0x87, 0xc6, 0x56, 0xaa, 0x46, 0x98, 0xc9, 0x9c, 0x66, 0x12, 0xce, 0x5b, + 0x95, 0xae, 0x41, 0x9c, 0xe1, 0x9c, 0xee, 0xe2, 0x06, 0x59, 0x26, 0xfe, 0xd7, 0x3d, 0x69, 0x51, + 0x8f, 0x20, 0x0e, 0xe3, 0x95, 0xe7, 0xfe, 0x83, 0x47, 0x14, 0x00, 0xd1, 0xeb, 0x4d, 0x31, 0x39, + 0xa9, 0x93, 0x06, 0x20, 0x0a, 0x63, 0x85, 0xd7, 0x4c, 0x93, 0x06, 0x30, 0x0b, 0x63, 0x82, 0xd7, + 0x46, 0x93, 0x06, 0x00, 0x02, 0xe3, 0x94, 0xd7, 0xfc, 0x83, 0x47, 0x14, 0x00, 0x63, 0x99, 0xe7, + 0x06, 0x03, 0x47, 0x24, 0x00, 0x95, 0x47, 0x63, 0x14, 0xf7, 0x06, 0x85, 0x45, 0x61, 0x45, 0xe1, + 0x3d, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x09, 0xf5, 0x42, 0x13, 0x04, 0x80, 0xf8, 0x7d, 0xa0, 0x03, + 0x47, 0x14, 0x00, 0x89, 0x47, 0x63, 0x15, 0xf7, 0x04, 0x83, 0x47, 0x24, 0x00, 0x63, 0x8a, 0xe7, + 0x04, 0x63, 0x6b, 0xf7, 0x02, 0xa1, 0xe3, 0x83, 0x45, 0x34, 0x00, 0xf5, 0x47, 0x63, 0xe9, 0xb7, + 0x02, 0x9e, 0x05, 0x13, 0x06, 0x00, 0x08, 0x93, 0x85, 0x05, 0x10, 0x13, 0x05, 0x21, 0x09, 0xef, + 0x20, 0x30, 0x6d, 0x13, 0x04, 0x00, 0x08, 0x08, 0x09, 0xa3, 0x08, 0x81, 0x08, 0xef, 0x10, 0x70, + 0x43, 0x93, 0x07, 0xa0, 0x0a, 0x45, 0xae, 0x13, 0x05, 0x80, 0x1e, 0x63, 0x8d, 0xd7, 0x00, 0x13, + 0x04, 0x10, 0xf8, 0xa1, 0xa8, 0x89, 0x65, 0x13, 0x06, 0x00, 0x08, 0x93, 0x85, 0x05, 0x90, 0xf1, + 0xb7, 0x13, 0x05, 0x00, 0x1f, 0xef, 0x10, 0x90, 0x24, 0x2a, 0xc6, 0x11, 0x46, 0x6c, 0x00, 0x13, + 0x05, 0x21, 0x09, 0xef, 0x40, 0x30, 0x0a, 0x11, 0x44, 0x7d, 0xbf, 0x83, 0x44, 0x14, 0x00, 0xc5, + 0x36, 0x93, 0x07, 0x10, 0x02, 0xe3, 0x95, 0xf4, 0xfc, 0xef, 0x10, 0xfa, 0x38, 0xbf, 0x38, 0x42, + 0x43, 0x1e, 0xae, 0xfb, 0xb2, 0xbd, 0xd1, 0x41, 0xd6, 0x50, 0x6d, 0x7f, 0x57, 0xac, 0x3e, 0x30, + 0x88, 0x61, 0x82, 0x7f, 0xa8, 0x1e, 0xe6, 0xb8, 0xb2, 0x1d, 0xba, 0x72, 0xf8, 0x0e, 0x10, 0x7d, + 0xef, 0x20, 0x90, 0x27, 0xef, 0x30, 0x90, 0x38, 0xef, 0x40, 0x60, 0x07, 0x03, 0x45, 0x24, 0x02, + 0xa5, 0x35, 0x93, 0x07, 0x30, 0x0c, 0x63, 0x0b, 0xf5, 0x02, 0x13, 0x04, 0x70, 0xf8, 0xb3, 0x06, + 0x80, 0x40, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0xf6, + 0xf6, 0x0f, 0x13, 0x06, 0x86, 0x42, 0x93, 0x85, 0x45, 0x41, 0x13, 0x05, 0x45, 0x64, 0x23, 0x08, + 0xd1, 0x08, 0xef, 0x10, 0x80, 0x3b, 0xa3, 0x08, 0x01, 0x08, 0xf9, 0xb5, 0x83, 0x44, 0x24, 0x02, + 0x19, 0x34, 0x8d, 0x47, 0xe3, 0xe3, 0x97, 0xfc, 0x13, 0x06, 0x10, 0x08, 0x81, 0x45, 0x68, 0x00, + 0xef, 0x40, 0x50, 0x06, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0x24, 0x00, 0x13, 0x05, 0xd1, 0x00, + 0x23, 0x06, 0x91, 0x00, 0xef, 0x40, 0x50, 0x01, 0xef, 0x40, 0x60, 0x00, 0x37, 0x25, 0x00, 0x08, + 0xef, 0x30, 0x80, 0x01, 0x81, 0x46, 0x01, 0x46, 0x93, 0x05, 0xd1, 0x02, 0x45, 0x45, 0x85, 0x3e, + 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x13, 0xf5, 0xf8, 0x81, 0x45, 0x68, 0x00, 0xef, 0x30, 0x50, 0x2f, + 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0xe3, 0x1a, 0xf5, 0xf6, 0x93, 0x06, 0x00, 0x02, 0x13, 0x06, + 0xd1, 0x00, 0x93, 0x05, 0xd1, 0x04, 0x49, 0x45, 0x99, 0x36, 0xaa, 0x84, 0xe3, 0x1f, 0x25, 0xf5, + 0x85, 0x45, 0x68, 0x00, 0xef, 0x30, 0xd0, 0x2c, 0x2a, 0x89, 0xe3, 0x18, 0x95, 0xf4, 0x83, 0x47, + 0xc1, 0x00, 0x85, 0x46, 0x13, 0x06, 0xfa, 0xf5, 0x53, 0x51, 0x24, 0x0b, 0xd3, 0xb5, 0x0a, 0xb7, + 0x01, 0x6b, 0x74, 0x3d, 0x7f, 0xf5, 0x00, 0x28, 0x14, 0x8f, 0xcc, 0x90, 0x4b, 0x85, 0xce, 0x81, + 0xe4, 0x59, 0x41, 0x71, 0xfb, 0xad, 0x60, 0xd0, 0x0f, 0xb1, 0x00, 0x93, 0x05, 0xd1, 0x04, 0x4d, + 0x45, 0xa3, 0x05, 0xf1, 0x00, 0x31, 0x3e, 0xaa, 0x84, 0xe3, 0x1a, 0x25, 0xf3, 0x89, 0x45, 0x68, + 0x00, 0xef, 0x30, 0x30, 0x2a, 0x2a, 0x89, 0xe3, 0x13, 0x95, 0xf2, 0x81, 0x46, 0x01, 0x46, 0x93, + 0x05, 0xd1, 0x04, 0x51, 0x45, 0xf5, 0x3c, 0xaa, 0x84, 0xe3, 0x1a, 0x25, 0xf1, 0x8d, 0x45, 0x68, + 0x00, 0xef, 0x30, 0x30, 0x28, 0x2a, 0x89, 0xe3, 0x13, 0x95, 0xf0, 0x91, 0x45, 0x68, 0x00, 0xef, + 0x30, 0x50, 0x27, 0xaa, 0x84, 0xe3, 0x1c, 0x25, 0xef, 0x95, 0x45, 0x68, 0x00, 0xef, 0x30, 0x70, + 0x26, 0xe3, 0x16, 0x95, 0xee, 0xb7, 0x19, 0x20, 0x00, 0x13, 0x85, 0x09, 0x02, 0xef, 0x30, 0x70, + 0x29, 0xb7, 0x14, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0xd1, 0x02, 0x13, 0x85, 0x04, + 0x03, 0xef, 0x40, 0xa0, 0x73, 0x37, 0x15, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0xd1, + 0x06, 0x13, 0x05, 0x05, 0x05, 0xef, 0x40, 0x60, 0x72, 0x03, 0x49, 0x24, 0x02, 0x8d, 0x47, 0x4e, + 0x84, 0x63, 0xf3, 0x27, 0x01, 0x01, 0x39, 0x37, 0x5c, 0x10, 0x00, 0xef, 0x10, 0x10, 0x49, 0x81, + 0x4c, 0x13, 0x0c, 0x8c, 0x58, 0x8d, 0x49, 0xfd, 0x5a, 0x13, 0x0a, 0x00, 0x0f, 0x41, 0x6b, 0xb7, + 0x0b, 0x00, 0x01, 0x03, 0x25, 0x0c, 0x00, 0x51, 0x81, 0x49, 0x39, 0x03, 0x27, 0x0c, 0x00, 0x93, + 0x57, 0x07, 0x01, 0xbd, 0x8b, 0x63, 0xe8, 0xf9, 0x00, 0x8e, 0x07, 0xb3, 0x97, 0xfa, 0x00, 0x93, + 0xc7, 0xfa, 0x81, 0x1f, 0x4d, 0x25, 0xcd, 0x61, 0x74, 0xa3, 0x01, 0xb9, 0x19, 0x8a, 0xd6, 0x7c, + 0xcb, 0x09, 0x01, 0xb4, 0x53, 0x17, 0x82, 0xe9, 0x76, 0xc7, 0x70, 0x48, 0x00, 0x27, 0x53, 0x08, + 0x25, 0x4a, 0xa8, 0x10, 0xf7, 0xff, 0x7d, 0x8d, 0x83, 0x46, 0x1c, 0x00, 0x33, 0x55, 0x25, 0x01, + 0x93, 0x77, 0x15, 0x00, 0x93, 0xf6, 0x06, 0x0f, 0x63, 0x96, 0x46, 0x07, 0x99, 0xc3, 0x93, 0x07, + 0xf0, 0x0f, 0xbd, 0x65, 0xf9, 0x8d, 0x21, 0x83, 0x3d, 0x8b, 0x22, 0x07, 0x4d, 0x8f, 0x83, 0x45, + 0x0c, 0x00, 0xc2, 0x07, 0x66, 0x85, 0xd9, 0x8d, 0xdd, 0x8d, 0xef, 0x10, 0xd0, 0x43, 0x83, 0x47, + 0x4c, 0x00, 0x11, 0x0c, 0x85, 0x0c, 0xc5, 0xf3, 0xef, 0x10, 0x90, 0x40, 0xb7, 0x37, 0x20, 0x00, + 0x13, 0x07, 0xa0, 0x0a, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x04, 0x03, 0x13, 0x05, 0x21, 0x09, + 0x23, 0xae, 0xe7, 0xf2, 0xef, 0x40, 0xa0, 0x67, 0x93, 0x05, 0x04, 0x02, 0x41, 0x46, 0x13, 0x05, + 0x21, 0x0b, 0xef, 0x40, 0xc0, 0x66, 0xef, 0x30, 0xf0, 0x6b, 0x13, 0x04, 0x00, 0x03, 0xef, 0xf0, + 0x7f, 0x85, 0xbd, 0xbb, 0x93, 0x76, 0x05, 0x10, 0x99, 0xc2, 0x93, 0xe7, 0x27, 0x00, 0xb3, 0x76, + 0x65, 0x01, 0x99, 0xc2, 0x93, 0xe7, 0x47, 0x00, 0x33, 0x75, 0x75, 0x01, 0x59, 0xd1, 0x93, 0xe7, + 0x87, 0x00, 0x41, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0xc7, 0xf3, 0x93, 0x07, 0xa0, 0x0a, + 0x83, 0x44, 0x14, 0x00, 0x63, 0x14, 0xf7, 0x0e, 0x91, 0xe4, 0x13, 0x04, 0x10, 0xf8, 0xef, 0xf0, + 0xbf, 0x96, 0x4d, 0xbb, 0xb7, 0x39, 0x20, 0x00, 0x83, 0xa7, 0x89, 0xf3, 0x93, 0x89, 0x89, 0xf3, + 0xad, 0xcb, 0x09, 0x04, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x49, 0xf3, 0xfa, 0x72, 0x9a, 0x0e, + 0x9c, 0x42, 0x00, 0x4f, 0x8e, 0x99, 0x54, 0xe9, 0x2d, 0x4a, 0xff, 0x60, 0xcd, 0x2f, 0xac, 0x96, + 0xa7, 0x1c, 0xe9, 0x43, 0xb3, 0xa8, 0x47, 0xea, 0x15, 0xe8, 0x82, 0xf7, 0x8e, 0x80, 0x11, 0x83, + 0x26, 0x09, 0x00, 0x03, 0xa7, 0x09, 0x00, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, + 0x55, 0x10, 0x00, 0x13, 0x05, 0x45, 0x64, 0xa6, 0x96, 0x13, 0x06, 0xc6, 0x41, 0x93, 0x85, 0xc5, + 0x3f, 0xef, 0x10, 0x20, 0x15, 0x03, 0x25, 0x09, 0x00, 0x83, 0xa7, 0x09, 0x00, 0x33, 0x87, 0xa4, + 0x00, 0xe3, 0xe6, 0xe7, 0xfa, 0x85, 0x67, 0x93, 0x87, 0x07, 0x02, 0xe3, 0xe1, 0xe7, 0xfa, 0xb7, + 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x26, 0x86, 0x3e, 0x95, 0xa2, 0x85, 0xef, 0x40, 0x40, + 0x5b, 0x83, 0x27, 0x09, 0x00, 0xbe, 0x94, 0x83, 0xa7, 0x09, 0x00, 0x23, 0x20, 0x99, 0x00, 0xbd, + 0xe3, 0x75, 0x54, 0x15, 0xbb, 0x89, 0x47, 0xe3, 0xfb, 0x97, 0xf6, 0x03, 0x49, 0x34, 0x00, 0x83, + 0x47, 0x24, 0x00, 0xf9, 0x14, 0x22, 0x09, 0x3e, 0x99, 0x85, 0x67, 0x93, 0x06, 0xf9, 0xff, 0x13, + 0x87, 0xf7, 0x00, 0x11, 0x04, 0xe3, 0x6c, 0xd7, 0xf4, 0x37, 0x0a, 0x20, 0x00, 0x13, 0x0a, 0x0a, + 0x00, 0x3e, 0x9a, 0x41, 0x09, 0x93, 0x07, 0xf0, 0x07, 0xa3, 0x0c, 0xfa, 0x06, 0x23, 0xa0, 0x29, + 0x01, 0xef, 0x10, 0x50, 0x4a, 0xef, 0x20, 0xc0, 0x74, 0xef, 0x30, 0xd0, 0x05, 0xb7, 0x37, 0x20, + 0x00, 0x23, 0x28, 0x2a, 0x07, 0x23, 0x2a, 0x0a, 0x06, 0x23, 0xaa, 0x07, 0xf2, 0x2d, 0xbf, 0x13, + 0x04, 0x60, 0xf8, 0x39, 0xbf, 0xe3, 0x9e, 0xf4, 0xf8, 0x01, 0x44, 0xa1, 0xb9, 0x83, 0x47, 0x14, + 0x00, 0xe3, 0x95, 0x07, 0xc6, 0xef, 0x10, 0xfa, 0x58, 0xea, 0x71, 0xc5, 0xc3, 0xe9, 0x10, 0x85, + 0x12, 0x25, 0x54, 0x01, 0xb8, 0xf5, 0x82, 0x91, 0xb1, 0x65, 0xbe, 0xdb, 0xb9, 0xfd, 0xeb, 0x77, + 0xcb, 0xa1, 0x6c, 0xec, 0x14, 0x54, 0x92, 0xdc, 0x58, 0x12, 0x30, 0x15, 0x93, 0x07, 0xa0, 0x0a, + 0xe3, 0x0f, 0x05, 0xc4, 0x83, 0x20, 0xc1, 0x1b, 0x03, 0x24, 0x81, 0x1b, 0x83, 0x24, 0x41, 0x1b, + 0x03, 0x29, 0x01, 0x1b, 0x83, 0x29, 0xc1, 0x1a, 0x03, 0x2a, 0x81, 0x1a, 0x83, 0x2a, 0x41, 0x1a, + 0x03, 0x2b, 0x01, 0x1a, 0x83, 0x2b, 0xc1, 0x19, 0x03, 0x2c, 0x81, 0x19, 0x83, 0x2c, 0x41, 0x19, + 0x3e, 0x85, 0x39, 0x61, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa2, 0xa7, 0xf4, 0x7d, 0xb7, + 0x83, 0x46, 0x14, 0x00, 0xe3, 0x9d, 0xe6, 0xc0, 0x83, 0x47, 0x24, 0x00, 0x63, 0x8a, 0xd7, 0x02, + 0x0d, 0x47, 0xe3, 0x96, 0xe7, 0xc0, 0xa1, 0x45, 0x01, 0x45, 0xb5, 0x3c, 0x93, 0x07, 0xa0, 0x0a, + 0x2a, 0x84, 0xe3, 0x13, 0xf5, 0xba, 0xb7, 0xb5, 0xb5, 0x61, 0x93, 0x85, 0x55, 0x49, 0x13, 0x05, + 0x80, 0x1f, 0xef, 0x10, 0x40, 0x6b, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa6, 0x87, 0xf2, 0xbd, 0xb7, + 0xb7, 0x15, 0x78, 0x4a, 0x93, 0x85, 0x95, 0x21, 0x13, 0x05, 0x80, 0x1f, 0xef, 0x10, 0xa0, 0x69, + 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf2, 0x81, 0xbf, 0xb7, 0x37, + 0x20, 0x00, 0x03, 0xa7, 0x87, 0xf2, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1f, 0xf7, 0xb4, 0x83, 0x47, + 0x14, 0x00, 0xe3, 0x96, 0x07, 0xba, 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x09, 0xef, 0x00, + 0x50, 0x6f, 0x2a, 0x84, 0xe3, 0x51, 0x05, 0xb8, 0xcd, 0xbe, 0x41, 0x11, 0x05, 0x45, 0x06, 0xc6, + 0xef, 0x40, 0xfa, 0x86, 0xf7, 0xda, 0x79, 0x19, 0xcd, 0xd6, 0x8d, 0x4b, 0xfc, 0xee, 0x71, 0x80, + 0x8a, 0xb4, 0x7e, 0xc1, 0x4c, 0x54, 0x2b, 0x0b, 0xd3, 0x52, 0x13, 0xb4, 0x0a, 0xdc, 0x9f, 0x91, + 0x1e, 0xd8, 0x55, 0x30, 0x13, 0x20, 0x02, 0xb2, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, + 0x0a, 0x23, 0xa0, 0xe7, 0xf4, 0x41, 0x01, 0x82, 0x80, 0x31, 0x71, 0x22, 0xdd, 0x37, 0x34, 0x20, + 0x00, 0x93, 0x07, 0x50, 0x05, 0x06, 0xdf, 0x4a, 0xd9, 0x52, 0xd5, 0x56, 0xd3, 0x62, 0xcd, 0x26, + 0xdb, 0x4e, 0xd7, 0x5a, 0xd1, 0x5e, 0xcf, 0x66, 0xcb, 0x6a, 0xc9, 0x6e, 0xc7, 0xb7, 0x3a, 0x20, + 0x00, 0x37, 0x3a, 0x20, 0x00, 0x37, 0x39, 0x20, 0x00, 0x13, 0x04, 0x84, 0xf2, 0x23, 0xa0, 0xfa, + 0xf4, 0x23, 0x26, 0xfa, 0xf2, 0x23, 0x22, 0xf9, 0xf4, 0x1c, 0xc0, 0xef, 0x10, 0x60, 0x3d, 0xef, + 0x10, 0xc0, 0x55, 0x13, 0x87, 0x0a, 0xf4, 0x3a, 0xc8, 0x13, 0x07, 0xca, 0xf2, 0x3a, 0xca, 0x13, + 0x07, 0x49, 0xf4, 0x93, 0x07, 0xa0, 0x0a, 0x3a, 0xc6, 0x37, 0x5c, 0x10, 0x00, 0x85, 0x45, 0x63, + 0x0a, 0xf5, 0x00, 0x13, 0x05, 0x4c, 0x41, 0xef, 0x00, 0x90, 0x7b, 0xef, 0x10, 0x80, 0x4f, 0xef, + 0xf0, 0x3f, 0x8c, 0x41, 0x45, 0xef, 0xf0, 0x5f, 0x97, 0x08, 0xc0, 0xb7, 0x07, 0x01, 0x02, 0x80, + 0x57, 0x98, 0x5b, 0x29, 0x45, 0x59, 0x8c, 0x98, 0x5f, 0x59, 0x8c, 0x13, 0x77, 0xf4, 0x87, 0x98, + 0xd7, 0x98, 0xdb, 0x98, 0xdf, 0xd8, 0x43, 0x13, 0x67, 0x87, 0x00, 0xd8, 0xc3, 0xef, 0x10, 0x00, + 0x38, 0xef, 0x30, 0x30, 0x22, 0x13, 0x75, 0x05, 0x78, 0x11, 0xc5, 0x13, 0x05, 0x00, 0x78, 0x81, + 0x45, 0xef, 0x30, 0x90, 0x1a, 0xb7, 0x07, 0x01, 0x02, 0x80, 0xd7, 0x80, 0xdb, 0xfa, 0x0a, 0x6d, + 0x3a, 0xa3, 0xdb, 0xe7, 0x9a, 0xb0, 0xfa, 0x32, 0x67, 0x83, 0x8f, 0x4c, 0xed, 0xea, 0x46, 0xa4, + 0x1d, 0x79, 0x17, 0x1b, 0x11, 0x8e, 0x3f, 0xcb, 0xe0, 0x37, 0x67, 0xed, 0xfe, 0xbf, 0x08, 0x14, + 0x37, 0x15, 0x10, 0x00, 0x80, 0xdf, 0x13, 0x05, 0xc5, 0x9a, 0xef, 0x10, 0xa0, 0x69, 0x37, 0x56, + 0x10, 0x00, 0x37, 0x59, 0x10, 0x00, 0x81, 0x47, 0x01, 0x47, 0x85, 0x46, 0x13, 0x06, 0x06, 0x43, + 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x50, 0x6c, 0xef, 0x30, 0x50, 0x1e, + 0x93, 0x07, 0x50, 0x05, 0x63, 0x1e, 0xf5, 0x00, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, + 0x13, 0x06, 0x46, 0x44, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x45, 0x40, 0xef, 0x00, 0x10, 0x6a, + 0xef, 0x20, 0xa0, 0x2f, 0x51, 0x45, 0xef, 0x10, 0xc0, 0x4b, 0x1d, 0x89, 0xef, 0x20, 0xc0, 0x2f, + 0xef, 0x20, 0xa0, 0x03, 0xef, 0x20, 0x10, 0x03, 0xef, 0x20, 0x30, 0x31, 0x37, 0x35, 0x00, 0x08, + 0xef, 0x20, 0xb0, 0x31, 0x11, 0x46, 0x6c, 0x10, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0xf0, 0x35, + 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0xb0, 0x33, 0x32, 0x55, 0xc1, 0x7a, 0x37, 0x0b, 0x01, 0xff, + 0xb7, 0x0b, 0x00, 0x01, 0xef, 0x20, 0x70, 0x22, 0x05, 0x64, 0x01, 0x4a, 0x93, 0x8a, 0xfa, 0x0f, + 0x7d, 0x1b, 0xfd, 0x1b, 0x13, 0x0d, 0x00, 0x18, 0x52, 0x85, 0xef, 0xf0, 0x1f, 0x87, 0xaa, 0x8c, + 0x22, 0x85, 0xef, 0x20, 0xd0, 0x0f, 0x93, 0xf9, 0x09, 0xf0, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, + 0x44, 0x00, 0xef, 0x20, 0xd0, 0x0e, 0x22, 0x05, 0xb3, 0xf9, 0x59, 0x01, 0xb3, 0xe9, 0xa9, 0x00, + 0x13, 0x05, 0x84, 0x00, 0xef, 0x20, 0xb0, 0x0d, 0xfa, 0x9a, 0x3e, 0xdc, 0x7f, 0x1d, 0xf9, 0x15, + 0x5a, 0xd7, 0x9c, 0x7e, 0x6d, 0x2c, 0xc4, 0x65, 0xf0, 0x94, 0x00, 0x42, 0xd2, 0x44, 0x5f, 0xbf, + 0x87, 0xab, 0x27, 0xd8, 0xab, 0x71, 0xe7, 0xd7, 0x8a, 0xe0, 0x14, 0x42, 0x05, 0xb3, 0xf9, 0x69, + 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x13, 0x05, 0xc4, 0x00, 0xef, 0x20, 0x90, 0x0c, 0x62, 0x05, 0xb3, + 0xf9, 0x79, 0x01, 0xb3, 0xe9, 0xa9, 0x00, 0x93, 0xc7, 0xf9, 0xff, 0x33, 0xf5, 0x97, 0x01, 0xe3, + 0x1b, 0x05, 0xea, 0x11, 0x0a, 0x41, 0x04, 0xe3, 0x12, 0xaa, 0xfb, 0x37, 0x55, 0x10, 0x00, 0xb7, + 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x13, 0x05, 0x85, 0x5e, 0x23, 0xae, 0xe7, 0xf2, 0xef, + 0x10, 0xf0, 0x1a, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x40, 0x05, 0x93, 0x85, 0x45, 0x53, 0x68, + 0x10, 0xef, 0x40, 0xc0, 0x24, 0x60, 0x10, 0x48, 0x40, 0x01, 0xc5, 0xef, 0x20, 0xa0, 0x7f, 0x48, + 0xc0, 0x31, 0x04, 0x1c, 0x01, 0xe3, 0x99, 0x87, 0xfe, 0x37, 0x55, 0x10, 0x00, 0x1d, 0x46, 0x6c, + 0x10, 0x13, 0x05, 0xc5, 0x5f, 0xef, 0x20, 0x40, 0x42, 0xef, 0xf0, 0x0f, 0xe3, 0x05, 0x45, 0xef, + 0x10, 0xd0, 0x02, 0xef, 0x30, 0xa0, 0x4e, 0xef, 0x30, 0x50, 0x21, 0x01, 0x45, 0xef, 0x30, 0xf0, + 0x5d, 0xb7, 0x0a, 0x20, 0x00, 0x93, 0x87, 0x0a, 0x00, 0x05, 0x6b, 0xb3, 0x8b, 0x67, 0x01, 0xb7, + 0x17, 0x20, 0x00, 0x13, 0x8a, 0xc7, 0x07, 0xef, 0x10, 0x40, 0x66, 0xb7, 0x37, 0x20, 0x00, 0x83, + 0xa7, 0x87, 0xf3, 0x63, 0x82, 0x07, 0x10, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0x47, 0xf3, 0x63, + 0x9c, 0xe7, 0x0e, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xc7, 0x07, 0xf3, 0x93, 0x87, 0x07, 0xf3, 0x3e, + 0xcc, 0xe3, 0x1d, 0xfa, 0x09, 0xd6, 0xcc, 0x36, 0xb2, 0x10, 0xd6, 0x5d, 0x86, 0xce, 0xa4, 0x0a, + 0x41, 0x3d, 0x63, 0x5f, 0x30, 0x52, 0x3e, 0x42, 0x3f, 0x54, 0x30, 0x74, 0x12, 0xcf, 0x11, 0xf8, + 0x4e, 0xc0, 0x1e, 0x3e, 0xb8, 0x15, 0x07, 0x36, 0x03, 0xa6, 0x0b, 0x07, 0x93, 0x07, 0xf0, 0x07, + 0xb7, 0x19, 0x20, 0x00, 0xa3, 0x8c, 0xfb, 0x06, 0xc1, 0x4c, 0x13, 0x8d, 0x0a, 0x00, 0x93, 0x89, + 0x09, 0x00, 0x63, 0xfe, 0xcc, 0x0a, 0x13, 0x04, 0x06, 0xff, 0xef, 0x10, 0x60, 0x72, 0x01, 0x45, + 0xef, 0x30, 0x60, 0x4f, 0x22, 0x86, 0x63, 0xf3, 0x8c, 0x00, 0x41, 0x46, 0x93, 0x85, 0x0a, 0x00, + 0x68, 0x10, 0xef, 0x30, 0x20, 0x50, 0xef, 0x10, 0xc0, 0x77, 0xb7, 0x57, 0x10, 0x00, 0x23, 0x8c, + 0xa9, 0x06, 0x93, 0x87, 0x87, 0x58, 0x03, 0xc7, 0x07, 0x00, 0x63, 0x1b, 0x07, 0x12, 0x03, 0xa4, + 0x09, 0x07, 0xc1, 0x47, 0xe3, 0xf2, 0x87, 0xda, 0x01, 0x45, 0xef, 0x30, 0xc0, 0x4b, 0x41, 0x14, + 0x22, 0x86, 0x93, 0x85, 0x0a, 0x00, 0x13, 0x85, 0x0a, 0x00, 0xef, 0x30, 0xa0, 0x4c, 0xb7, 0x1c, + 0x20, 0x00, 0x13, 0x85, 0x0c, 0x02, 0xef, 0x30, 0xa0, 0x68, 0xef, 0x30, 0x20, 0x6d, 0x37, 0x56, + 0x10, 0x00, 0xb7, 0x5d, 0x10, 0x00, 0xaa, 0x86, 0x13, 0x06, 0x46, 0x45, 0x93, 0x85, 0xcd, 0x3d, + 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0xf0, 0x49, 0x93, 0x85, 0x0c, 0x02, 0x41, 0x46, 0x33, 0x05, + 0x8d, 0x00, 0xef, 0x00, 0x30, 0x38, 0xaa, 0x8c, 0xc1, 0x47, 0x63, 0x09, 0x05, 0x0e, 0x89, 0x45, + 0x13, 0x85, 0xcd, 0x3d, 0xef, 0x00, 0x50, 0x4f, 0x37, 0x55, 0x10, 0x00, 0x93, 0x07, 0xb0, 0x07, + 0x91, 0x45, 0x13, 0x05, 0xc5, 0x3f, 0xa3, 0x8c, 0xf9, 0x06, 0xef, 0x00, 0xf0, 0x4d, 0xfa, 0xce, + 0xbf, 0xd7, 0x63, 0x4e, 0x22, 0xa4, 0x2f, 0x18, 0x62, 0x10, 0xe7, 0xb8, 0x9f, 0x42, 0xca, 0x1a, + 0xb8, 0xd9, 0x8f, 0xcb, 0x1b, 0xfe, 0xd8, 0x41, 0x41, 0xba, 0x73, 0x22, 0x84, 0x8f, 0xe8, 0x90, + 0x16, 0xef, 0xe0, 0x9f, 0xf7, 0xef, 0xf0, 0xcf, 0x87, 0xef, 0xf0, 0x4f, 0xc3, 0xef, 0x10, 0xa0, + 0x53, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x17, 0xf5, 0x08, 0xb7, 0x37, 0x20, 0x00, 0x83, + 0xc7, 0x07, 0xf3, 0xc9, 0xe3, 0xef, 0x10, 0xa0, 0x02, 0xe3, 0x15, 0x85, 0x20, 0xd2, 0x47, 0x9c, + 0x43, 0x63, 0x94, 0xa7, 0x00, 0xef, 0x10, 0xc0, 0x18, 0xb2, 0x47, 0x98, 0x43, 0x93, 0x07, 0xa0, + 0x0a, 0xe3, 0x13, 0xf7, 0x1e, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0x86, 0x4d, 0x93, 0x05, 0x4c, + 0x41, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x10, 0x41, 0xef, 0xf0, 0x4f, 0xbe, 0x37, 0x25, 0x00, + 0x08, 0xef, 0x20, 0x70, 0x0d, 0xef, 0xf0, 0x4f, 0xa8, 0xef, 0x20, 0x60, 0x5f, 0xef, 0x10, 0x50, + 0x1c, 0xef, 0x20, 0x30, 0x21, 0xef, 0xe0, 0xff, 0xf3, 0x32, 0x47, 0x37, 0x56, 0x10, 0x00, 0x93, + 0x07, 0x50, 0x05, 0x13, 0x06, 0x46, 0x4e, 0x93, 0x05, 0x4c, 0x41, 0x13, 0x05, 0x49, 0x64, 0x1c, + 0xc3, 0xef, 0x00, 0x50, 0x3d, 0xef, 0x20, 0x10, 0x21, 0xef, 0x10, 0x70, 0x48, 0xef, 0x20, 0x20, + 0x5f, 0xef, 0x30, 0x90, 0x00, 0xc2, 0x47, 0x98, 0x43, 0x93, 0x07, 0x50, 0x05, 0xe3, 0x08, 0xf7, + 0xe4, 0xad, 0xb9, 0x63, 0x1c, 0xe5, 0x00, 0x83, 0xc7, 0x17, 0x00, 0xbd, 0x8b, 0xe3, 0x82, 0x07, + 0xec, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0xa0, 0x59, 0x65, 0xbd, 0x91, 0x07, 0x75, 0xb5, 0x03, + 0xa4, 0x09, 0x07, 0xe3, 0xe4, 0x87, 0x16, 0x37, 0x55, 0xfa, 0x77, 0x99, 0x22, 0x2f, 0x4d, 0xca, + 0xf6, 0x83, 0x0f, 0x59, 0x69, 0xe8, 0xfb, 0x06, 0x09, 0x3e, 0xc9, 0x5d, 0x8f, 0xbd, 0x32, 0xc0, + 0x74, 0x8c, 0x40, 0xd5, 0xfa, 0xdf, 0x85, 0x01, 0x1a, 0x9a, 0x68, 0x17, 0x10, 0x00, 0x89, 0x45, + 0x13, 0x05, 0xc5, 0x3f, 0xef, 0x00, 0xb0, 0x3f, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x3f, + 0x95, 0x45, 0xef, 0x00, 0xd0, 0x3e, 0x13, 0x05, 0xf0, 0x07, 0x39, 0xb7, 0xb7, 0x37, 0x20, 0x00, + 0x93, 0x87, 0x07, 0xf5, 0x94, 0x43, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x87, + 0x16, 0x00, 0x98, 0xc3, 0x03, 0xc7, 0x89, 0x07, 0xa2, 0x87, 0x13, 0x06, 0x46, 0x46, 0x93, 0x85, + 0xc5, 0x3f, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x30, 0x34, 0xb7, 0x17, 0x20, 0x00, 0x13, 0x85, + 0xc7, 0x07, 0x3d, 0x46, 0x81, 0x45, 0xef, 0x30, 0xd0, 0x7f, 0x83, 0xc7, 0x89, 0x07, 0x13, 0x07, + 0x20, 0x04, 0x63, 0x80, 0xe7, 0x56, 0x63, 0x69, 0xf7, 0x16, 0x13, 0x07, 0x10, 0x02, 0x63, 0x89, + 0xe7, 0x3e, 0x63, 0x60, 0xf7, 0x08, 0x45, 0x47, 0x63, 0x82, 0xe7, 0x30, 0x63, 0x69, 0xf7, 0x02, + 0x05, 0x47, 0x63, 0x85, 0xe7, 0x24, 0x41, 0x47, 0x63, 0x8d, 0xe7, 0x26, 0x89, 0x49, 0x3d, 0xa3, + 0x93, 0x87, 0x07, 0xfa, 0x93, 0xf7, 0xf7, 0x0f, 0x45, 0x47, 0xe3, 0x69, 0xf7, 0xfe, 0x37, 0x57, + 0x10, 0x00, 0x8a, 0x07, 0x13, 0x07, 0xc7, 0x4e, 0xba, 0x97, 0x9c, 0x43, 0x82, 0x87, 0x49, 0x47, + 0x63, 0x82, 0xe7, 0x34, 0x13, 0x07, 0x00, 0x02, 0xe3, 0x9a, 0xe7, 0xfc, 0x42, 0x04, 0x41, 0x80, + 0xa1, 0x47, 0xe3, 0x13, 0xf4, 0xf4, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, 0x07, 0x01, + 0x8d, 0x8b, 0x41, 0x81, 0xfa, 0xe5, 0x41, 0x75, 0x45, 0xea, 0xba, 0xc3, 0xbb, 0x97, 0x2f, 0x92, + 0xb4, 0x71, 0x56, 0xba, 0xd0, 0xa0, 0xbc, 0x5e, 0xbd, 0xea, 0xe4, 0x2c, 0xbd, 0xc4, 0x6a, 0x38, + 0xb0, 0x96, 0x27, 0xd0, 0xdc, 0x40, 0x18, 0x63, 0x97, 0x07, 0x54, 0x93, 0x07, 0xf0, 0x1f, 0x63, + 0xe3, 0xa7, 0x54, 0x83, 0x25, 0x4d, 0x00, 0xef, 0x10, 0x90, 0x1e, 0x93, 0x07, 0xa0, 0x0a, 0x63, + 0x1b, 0xf5, 0x52, 0xad, 0xa6, 0x13, 0x07, 0x10, 0x03, 0x63, 0x86, 0xe7, 0x3a, 0x63, 0x6f, 0xf7, + 0x04, 0x13, 0x07, 0x20, 0x02, 0x63, 0x87, 0xe7, 0x38, 0x13, 0x07, 0x00, 0x03, 0xe3, 0x91, 0xe7, + 0xf8, 0x42, 0x04, 0x41, 0x80, 0x91, 0x47, 0xe3, 0x1a, 0xf4, 0xee, 0x83, 0x27, 0x0d, 0x00, 0xa1, + 0x83, 0x13, 0x97, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x83, 0x63, 0x9e, 0x07, 0x4e, 0x93, 0x07, 0xf0, + 0x1f, 0x63, 0xea, 0xe7, 0x4e, 0x03, 0x45, 0x3d, 0x00, 0xfd, 0x47, 0x63, 0xe5, 0xa7, 0x4e, 0x93, + 0x15, 0x25, 0x00, 0x0d, 0x81, 0x93, 0xf7, 0xc5, 0x01, 0x3a, 0x95, 0xbd, 0x45, 0xb3, 0x95, 0xf5, + 0x00, 0x0a, 0x05, 0x93, 0xc5, 0xf5, 0xff, 0x5a, 0x95, 0x05, 0xa4, 0x13, 0x07, 0x00, 0x04, 0x63, + 0x8f, 0xe7, 0x3a, 0x13, 0x07, 0x10, 0x04, 0xe3, 0x94, 0xe7, 0xf2, 0x42, 0x04, 0x41, 0x80, 0x8d, + 0x47, 0xe3, 0x1d, 0xf4, 0xe8, 0x83, 0x26, 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0xa1, 0x82, 0xc2, + 0x06, 0xc1, 0x82, 0x63, 0xe1, 0xd7, 0x4a, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x13, + 0x06, 0x86, 0x4b, 0x93, 0x85, 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x10, 0x1f, 0xef, + 0x10, 0x50, 0x57, 0xef, 0x20, 0x00, 0x75, 0x83, 0x27, 0x0d, 0x00, 0x91, 0x65, 0x93, 0x85, 0xfa, + 0x47, 0x17, 0x25, 0x1e, 0x43, 0xe9, 0x33, 0xd8, 0x02, 0x03, 0xae, 0xcf, 0x84, 0xf2, 0x8b, 0xcd, + 0x3c, 0x10, 0xd2, 0xc0, 0x1f, 0xb2, 0x47, 0xd3, 0xbe, 0xe3, 0xe4, 0xe8, 0x12, 0xc3, 0xc8, 0x45, + 0x18, 0x19, 0x05, 0x20, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, 0xa6, 0x07, 0x37, 0x15, 0x20, 0x00, + 0xbe, 0x95, 0x13, 0x05, 0x05, 0x08, 0xef, 0x10, 0x30, 0x19, 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x74, + 0x93, 0x07, 0xc0, 0x1b, 0xe3, 0xe0, 0x87, 0xa8, 0x93, 0x05, 0x44, 0x00, 0x29, 0xac, 0x13, 0x07, + 0x10, 0x07, 0x63, 0x69, 0xf7, 0x02, 0x13, 0x07, 0xf0, 0x05, 0xe3, 0x66, 0xf7, 0xea, 0x13, 0x07, + 0x00, 0x05, 0xe3, 0x90, 0xe7, 0xea, 0x42, 0x04, 0x41, 0x80, 0x89, 0x47, 0xe3, 0x19, 0xf4, 0xe0, + 0x03, 0x44, 0x1d, 0x00, 0x37, 0x15, 0x20, 0x00, 0x13, 0x05, 0x05, 0x08, 0xa2, 0x85, 0xef, 0xe0, + 0x1f, 0xd7, 0xd9, 0xb7, 0x13, 0x07, 0x20, 0x08, 0x63, 0x8b, 0xe7, 0x6e, 0x63, 0x6d, 0xf7, 0x04, + 0x13, 0x07, 0x00, 0x08, 0x63, 0x82, 0xe7, 0x68, 0x13, 0x07, 0x10, 0x08, 0xe3, 0x93, 0xe7, 0xe6, + 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x1c, 0xf4, 0xdc, 0x03, 0x45, 0x1d, 0x00, 0x3d, 0x47, + 0x81, 0x47, 0x63, 0x6e, 0xa7, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x47, 0xf5, 0x89, 0x47, + 0x33, 0x57, 0xa7, 0x00, 0x05, 0x8b, 0x01, 0xc7, 0xef, 0xe0, 0x7f, 0xe6, 0xaa, 0x87, 0xfd, 0x17, + 0x09, 0x47, 0x63, 0x63, 0xf7, 0x3c, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x72, 0xaa, 0x97, + 0x83, 0xc9, 0x07, 0x00, 0x1d, 0xaa, 0x13, 0x07, 0x00, 0x09, 0xe3, 0x9c, 0xe7, 0xe0, 0x93, 0x17, + 0x04, 0x01, 0xc1, 0x83, 0x13, 0x07, 0x30, 0x02, 0xe3, 0x73, 0xfa, 0xa8, 0x14, 0x54, 0xc7, 0x06, + 0x88, 0x1f, 0x45, 0xef, 0x40, 0x7a, 0x35, 0xc3, 0x1e, 0x47, 0x8b, 0x03, 0x2a, 0xa2, 0xde, 0x0c, + 0xb1, 0x25, 0x57, 0x1a, 0x89, 0xfd, 0xa3, 0x0a, 0xd1, 0xfb, 0xfa, 0xf0, 0x19, 0xf7, 0xd8, 0x37, + 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0xbe, 0x86, 0x13, 0x06, 0x06, 0x4c, 0x93, 0x85, 0xc5, + 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0xd0, 0x0e, 0xef, 0x20, 0xa0, 0x0d, 0xef, 0x20, 0xc0, + 0x64, 0xef, 0x20, 0x20, 0x0e, 0x2a, 0x84, 0xef, 0x20, 0x40, 0x0d, 0xef, 0x20, 0x00, 0x66, 0x93, + 0x07, 0xa0, 0x0a, 0x63, 0x14, 0xf4, 0x36, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0x00, 0x2c, 0x93, + 0x07, 0x40, 0x02, 0x81, 0xa3, 0x93, 0x19, 0x04, 0x01, 0x93, 0xd9, 0x09, 0x01, 0x37, 0x56, 0x10, + 0x00, 0xb7, 0x55, 0x10, 0x00, 0xce, 0x86, 0x13, 0x06, 0x06, 0x4a, 0x93, 0x85, 0xc5, 0x4a, 0x13, + 0x05, 0x49, 0x64, 0xef, 0x00, 0xf0, 0x09, 0x93, 0x07, 0x1b, 0x00, 0xe3, 0xeb, 0x37, 0xd1, 0xce, + 0x85, 0x13, 0x85, 0x0a, 0x00, 0xef, 0xf0, 0x4f, 0x8e, 0xa9, 0xaa, 0x42, 0x04, 0x41, 0x80, 0x93, + 0x07, 0x40, 0x02, 0xe3, 0x1f, 0xf4, 0xce, 0x03, 0x25, 0x0d, 0x00, 0x0d, 0x44, 0x21, 0x81, 0x42, + 0x05, 0x41, 0x81, 0x63, 0x64, 0xa4, 0x30, 0xef, 0xf0, 0x8f, 0xae, 0xd5, 0x47, 0x63, 0x1f, 0xf5, + 0x2e, 0x83, 0x29, 0x0d, 0x00, 0x93, 0xd9, 0x89, 0x00, 0xc2, 0x09, 0x93, 0xd9, 0x09, 0x01, 0xe3, + 0x6c, 0x34, 0x91, 0x13, 0x84, 0x09, 0x0e, 0x16, 0x04, 0x91, 0x4c, 0x71, 0x14, 0x93, 0x0d, 0x40, + 0x02, 0xb3, 0x05, 0x9d, 0x01, 0x11, 0x46, 0x68, 0x10, 0xef, 0x30, 0x70, 0x4c, 0xb2, 0x55, 0x33, + 0x05, 0x94, 0x01, 0x91, 0x0c, 0xfa, 0x4f, 0x60, 0xde, 0x6f, 0x1c, 0xa4, 0x15, 0x4a, 0xa0, 0x12, + 0xa0, 0x2b, 0x4e, 0x49, 0x39, 0x13, 0x4a, 0xa9, 0xb3, 0x69, 0x99, 0xb7, 0xa8, 0xd8, 0x9c, 0x2b, + 0x00, 0x69, 0xcf, 0xcd, 0x41, 0x86, 0xc8, 0x1a, 0xef, 0x20, 0x20, 0x33, 0xe3, 0x94, 0xbc, 0xff, + 0x09, 0x65, 0x8a, 0x09, 0xb7, 0xf5, 0xf0, 0xf0, 0x13, 0x05, 0x05, 0xbf, 0x93, 0x85, 0x05, 0x0f, + 0x4e, 0x95, 0xef, 0x20, 0x80, 0x31, 0xc5, 0xa0, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x13, + 0xf4, 0xc8, 0x03, 0x25, 0x0d, 0x00, 0x0d, 0x44, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0x68, + 0xa4, 0x28, 0xef, 0xf0, 0x0f, 0xa7, 0x93, 0x07, 0x30, 0x0c, 0x63, 0x08, 0xf5, 0x00, 0xaa, 0x89, + 0x93, 0x07, 0x00, 0x08, 0x63, 0x9a, 0xf9, 0x20, 0xb1, 0xb9, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, + 0xc2, 0x07, 0xc1, 0x83, 0xe3, 0x6b, 0xf4, 0x88, 0x93, 0x87, 0x07, 0x0e, 0x13, 0x94, 0x57, 0x00, + 0x93, 0x09, 0x00, 0x02, 0x33, 0x05, 0x94, 0x01, 0xef, 0x20, 0x20, 0x20, 0xb7, 0x17, 0x20, 0x00, + 0x93, 0x87, 0x07, 0x08, 0x2a, 0xd6, 0x11, 0x46, 0x33, 0x85, 0x97, 0x01, 0x6c, 0x10, 0x91, 0x0c, + 0xef, 0x30, 0x30, 0x43, 0xe3, 0x90, 0x3c, 0xff, 0x93, 0x05, 0x40, 0x02, 0x52, 0x85, 0x29, 0xb7, + 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x17, 0xf4, 0xc0, 0x03, 0x25, 0x0d, 0x00, 0x21, 0x81, + 0x42, 0x05, 0x41, 0x81, 0x63, 0x6d, 0xa4, 0x20, 0xef, 0xf0, 0xaf, 0x9f, 0xd5, 0x47, 0x63, 0x08, + 0xf5, 0x20, 0xd9, 0x47, 0x63, 0x01, 0xf5, 0x04, 0x83, 0x29, 0x0d, 0x00, 0x93, 0xd9, 0x89, 0x00, + 0xc2, 0x09, 0x93, 0xd9, 0x09, 0x01, 0xe3, 0x62, 0x34, 0x83, 0x89, 0x67, 0x13, 0x95, 0x29, 0x00, + 0xfa, 0xc6, 0xb1, 0xbc, 0xdc, 0xf5, 0x78, 0x3d, 0x7b, 0x6e, 0x77, 0xac, 0x36, 0x62, 0xeb, 0xbe, + 0xa1, 0xde, 0xcf, 0xdf, 0xdc, 0xb7, 0x77, 0x63, 0x5d, 0xc2, 0x2b, 0x22, 0x81, 0x84, 0x61, 0x48, + 0x53, 0xa0, 0x1b, 0x93, 0x87, 0x07, 0xbf, 0x81, 0x45, 0x3e, 0x95, 0x93, 0x89, 0x09, 0x0e, 0xef, + 0x20, 0xe0, 0x24, 0x96, 0x09, 0x13, 0x04, 0x00, 0x02, 0x33, 0x85, 0x99, 0x01, 0x81, 0x45, 0x91, + 0x0c, 0xef, 0x20, 0xc0, 0x23, 0xe3, 0x9a, 0x8c, 0xfe, 0x93, 0x09, 0x30, 0x0c, 0xb9, 0xaa, 0x42, + 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x11, 0xf4, 0xba, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, + 0x95, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x81, 0x63, 0x95, 0x07, 0x1a, 0x93, 0x07, 0xf0, 0x1f, 0x63, + 0xe1, 0xa7, 0x1a, 0xef, 0x10, 0x60, 0x5b, 0x23, 0x22, 0xaa, 0x00, 0xa1, 0x45, 0x8d, 0xb7, 0x42, + 0x04, 0x41, 0x80, 0x85, 0x47, 0x01, 0x45, 0xe3, 0x18, 0xf4, 0xb6, 0xef, 0x10, 0x30, 0x24, 0x6d, + 0xbf, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x10, 0xf4, 0xb6, 0x83, 0x27, 0x0d, 0x00, 0xa1, + 0x83, 0x13, 0x94, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x80, 0x63, 0x94, 0x07, 0x16, 0x93, 0x07, 0xf0, + 0x1f, 0x63, 0xe0, 0x87, 0x16, 0x0a, 0x04, 0x33, 0x05, 0x64, 0x01, 0xef, 0x20, 0xe0, 0x17, 0x93, + 0xf4, 0x04, 0xf0, 0xc9, 0x8c, 0x13, 0x05, 0x4b, 0x00, 0x22, 0x95, 0xef, 0x20, 0xe0, 0x16, 0xc1, + 0x77, 0x93, 0x87, 0xf7, 0x0f, 0xfd, 0x8c, 0x22, 0x05, 0xc9, 0x8c, 0x13, 0x05, 0x8b, 0x00, 0x22, + 0x95, 0xef, 0x20, 0x80, 0x15, 0xb7, 0x07, 0x01, 0xff, 0xfd, 0x17, 0x42, 0x05, 0xfd, 0x8c, 0xc9, + 0x8c, 0x13, 0x05, 0xcb, 0x00, 0x22, 0x95, 0xef, 0x20, 0x20, 0x14, 0xfa, 0x70, 0x68, 0x99, 0xc9, + 0x5d, 0xfd, 0x77, 0x78, 0x7f, 0xb8, 0xac, 0xfa, 0xbe, 0x98, 0xb8, 0xcd, 0x0f, 0x4a, 0x71, 0x9f, + 0x66, 0x0d, 0x8e, 0x25, 0xd8, 0xd6, 0xc6, 0x08, 0x96, 0xb2, 0x8f, 0xe1, 0x78, 0x1c, 0xa2, 0x04, + 0x62, 0x05, 0xa1, 0x80, 0xc9, 0x8c, 0x23, 0x22, 0x9a, 0x00, 0x95, 0xbf, 0x93, 0x07, 0xb4, 0xff, + 0xc2, 0x07, 0xc1, 0x83, 0x13, 0x07, 0xb0, 0x1b, 0xe3, 0x61, 0xf7, 0xae, 0x83, 0x26, 0x0d, 0x00, + 0x93, 0x07, 0xf0, 0x1f, 0x93, 0x09, 0xc0, 0x03, 0xa1, 0x82, 0xc2, 0x06, 0xc1, 0x82, 0x63, 0xe0, + 0xd7, 0x08, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x06, 0x4b, 0x93, 0x85, + 0xc5, 0x4a, 0x13, 0x05, 0x49, 0x64, 0xef, 0x00, 0x40, 0x63, 0x03, 0x25, 0x0d, 0x00, 0x91, 0x69, + 0x93, 0x89, 0x09, 0x20, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x26, 0x05, 0x4e, 0x95, 0xef, 0x10, + 0x30, 0x13, 0x93, 0x07, 0xa0, 0x0a, 0xaa, 0x8c, 0x63, 0x12, 0xf5, 0x04, 0xc1, 0x45, 0x68, 0x10, + 0xef, 0xe0, 0xbf, 0x9f, 0xef, 0x20, 0xe0, 0x36, 0x83, 0x27, 0x0d, 0x00, 0x42, 0x04, 0x41, 0x80, + 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, 0xa6, 0x07, 0xb7, 0x05, 0x20, 0x00, 0x13, 0x06, 0xc4, 0xff, + 0x33, 0x85, 0x37, 0x01, 0x74, 0x10, 0x93, 0x85, 0x45, 0x00, 0xef, 0x10, 0xf0, 0x02, 0x2a, 0x84, + 0x93, 0x09, 0x30, 0x0c, 0xef, 0x20, 0x00, 0x36, 0x63, 0x03, 0x94, 0x01, 0xc1, 0x49, 0x13, 0xf5, + 0xf9, 0x0f, 0xe5, 0xae, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, 0x10, 0xf4, 0xa4, 0x03, 0x25, + 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0xe4, 0xa7, 0x04, + 0x91, 0x67, 0x26, 0x05, 0x93, 0x87, 0xfa, 0xbf, 0xc2, 0xb6, 0x88, 0x6b, 0x7a, 0xb9, 0x24, 0x77, + 0x28, 0x7d, 0x46, 0x0c, 0x86, 0x80, 0x0a, 0x92, 0x4e, 0xbe, 0x91, 0xb2, 0x27, 0xca, 0x3c, 0x70, + 0xba, 0xff, 0xfc, 0x2f, 0x5a, 0xaf, 0xa6, 0x50, 0x1d, 0x07, 0x20, 0x3e, 0x95, 0x55, 0xbd, 0x42, + 0x04, 0x41, 0x80, 0x91, 0x47, 0xe3, 0x1c, 0xf4, 0xa0, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0x1f, + 0x98, 0x68, 0x10, 0xef, 0x10, 0x80, 0x7c, 0xef, 0x30, 0xa0, 0x20, 0xef, 0x20, 0xa0, 0x2e, 0x91, + 0x45, 0x13, 0x05, 0x00, 0x06, 0xef, 0x30, 0xc0, 0x42, 0x2a, 0x84, 0xef, 0x20, 0xc0, 0x2f, 0x93, + 0x07, 0xa0, 0x0a, 0xe3, 0x0e, 0xf4, 0xe2, 0x93, 0x09, 0xc0, 0x03, 0x59, 0xbf, 0x42, 0x04, 0x41, + 0x80, 0x93, 0x07, 0x00, 0x03, 0xe3, 0x1c, 0xf4, 0x9c, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0x1f, + 0x94, 0x68, 0x10, 0xef, 0x10, 0x80, 0x78, 0xef, 0x30, 0xa0, 0x1c, 0xef, 0x20, 0xa0, 0x2a, 0x93, + 0x05, 0x00, 0x03, 0x13, 0x05, 0x10, 0x06, 0x7d, 0xbf, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, + 0x17, 0xf4, 0x9a, 0xef, 0x30, 0xe0, 0x1a, 0xef, 0x20, 0xe0, 0x28, 0x8d, 0x45, 0x13, 0x05, 0x20, + 0x06, 0xef, 0x30, 0x00, 0x3d, 0x2a, 0x84, 0xef, 0x20, 0x00, 0x2a, 0x93, 0x07, 0xa0, 0x0a, 0xe3, + 0x14, 0xf4, 0xfa, 0xef, 0xe0, 0x7f, 0xf0, 0x05, 0xb3, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0xe3, + 0x1f, 0xf4, 0x96, 0xef, 0x30, 0xe0, 0x17, 0x8d, 0x45, 0x13, 0x05, 0x30, 0x06, 0xef, 0x30, 0x40, + 0x3a, 0xb1, 0xb4, 0x42, 0x04, 0x41, 0x80, 0x93, 0x07, 0x00, 0x03, 0xe3, 0x11, 0xf4, 0x96, 0xef, + 0x30, 0x20, 0x16, 0xef, 0x20, 0x50, 0x6f, 0xb7, 0x15, 0x20, 0x00, 0x2a, 0xd6, 0x13, 0x06, 0x00, + 0x02, 0xfa, 0x99, 0x17, 0x50, 0x16, 0x19, 0x46, 0x96, 0xdc, 0x78, 0x56, 0x08, 0x95, 0x3d, 0xa2, + 0x26, 0xe3, 0x09, 0xc9, 0x14, 0x35, 0x00, 0x41, 0x0c, 0xd8, 0x2e, 0x4f, 0x6c, 0xcf, 0xe4, 0x6a, + 0x93, 0x3b, 0x28, 0x1e, 0x93, 0x85, 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, 0xef, 0x30, 0x60, 0x26, + 0x11, 0x46, 0x6c, 0x10, 0x13, 0x05, 0x00, 0x0c, 0xef, 0x30, 0xa0, 0x25, 0xef, 0x20, 0xc0, 0x21, + 0x93, 0x05, 0x00, 0x03, 0x13, 0x05, 0x00, 0x07, 0xef, 0x30, 0xc0, 0x35, 0x2a, 0x84, 0xef, 0x20, + 0xc0, 0x22, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1a, 0xf4, 0xf2, 0xef, 0xe0, 0x3f, 0xe9, 0x75, 0xb1, + 0x93, 0x17, 0x04, 0x01, 0xc1, 0x83, 0x3d, 0x47, 0xe3, 0x74, 0xf7, 0x90, 0xef, 0x30, 0x80, 0x10, + 0xef, 0x20, 0xb0, 0x69, 0xaa, 0x8c, 0x01, 0x45, 0xef, 0x20, 0xd0, 0x45, 0x41, 0x46, 0x93, 0x85, + 0x0a, 0x00, 0x01, 0x45, 0xef, 0x20, 0xf0, 0x46, 0xef, 0x20, 0x00, 0x1d, 0xb7, 0x15, 0x20, 0x00, + 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, 0x66, 0xd6, 0xef, 0x30, + 0x40, 0x1f, 0x11, 0x46, 0x6c, 0x10, 0x13, 0x05, 0x00, 0x0c, 0xef, 0x30, 0x80, 0x1e, 0x85, 0x45, + 0x13, 0x05, 0x10, 0x04, 0xef, 0x30, 0x00, 0x2f, 0x93, 0x07, 0xa0, 0x0a, 0xaa, 0x8c, 0x63, 0x19, + 0xf5, 0x00, 0x81, 0x45, 0x13, 0x05, 0x20, 0x04, 0xef, 0x30, 0xc0, 0x2d, 0x63, 0x05, 0x95, 0x01, + 0xef, 0x20, 0xa0, 0x1a, 0x5d, 0xbd, 0x42, 0x04, 0x41, 0x80, 0x93, 0x0d, 0x04, 0xff, 0xef, 0x20, + 0xc0, 0x19, 0xee, 0x8c, 0x22, 0x9d, 0x93, 0x07, 0x00, 0x09, 0xb3, 0x05, 0x9d, 0x41, 0x63, 0xe5, + 0x97, 0x09, 0x66, 0x86, 0x01, 0x45, 0xef, 0x20, 0xd0, 0x3f, 0xe6, 0x85, 0xfa, 0xad, 0xd6, 0x41, + 0x0d, 0x03, 0xf4, 0x73, 0xe9, 0x9c, 0xda, 0xe7, 0x57, 0x9b, 0xd1, 0xa0, 0x7e, 0xea, 0xc1, 0xb9, + 0xb2, 0x46, 0xe5, 0xc2, 0x44, 0xbc, 0x06, 0xc5, 0x55, 0xf5, 0x63, 0xed, 0x7f, 0x00, 0x1f, 0x13, + 0x05, 0x40, 0x04, 0xef, 0x30, 0x40, 0x2a, 0x13, 0x07, 0xa0, 0x0a, 0xe3, 0x11, 0xe5, 0xe8, 0x2a, + 0xce, 0x81, 0x45, 0x13, 0x05, 0x50, 0x04, 0xef, 0x30, 0x00, 0x29, 0xf2, 0x47, 0xaa, 0x8c, 0xe3, + 0x17, 0xf5, 0xe6, 0x01, 0x45, 0xef, 0x20, 0x30, 0x3b, 0x93, 0x85, 0x0a, 0x00, 0x41, 0x46, 0x01, + 0x45, 0xef, 0x20, 0x50, 0x3c, 0x93, 0x07, 0xf0, 0x03, 0xb7, 0x05, 0x20, 0x00, 0x63, 0xe1, 0xb7, + 0x07, 0x93, 0x85, 0x05, 0x01, 0x01, 0x45, 0x6e, 0x86, 0xef, 0x20, 0xd0, 0x3a, 0xee, 0x85, 0x13, + 0x05, 0x60, 0x04, 0xef, 0x30, 0x40, 0x25, 0xe3, 0x1b, 0x95, 0xe3, 0x81, 0x45, 0x13, 0x05, 0xa0, + 0x04, 0xef, 0x30, 0x60, 0x24, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x12, 0xf5, 0xe2, 0xef, 0x20, 0x10, + 0x58, 0x93, 0x07, 0x00, 0x05, 0x23, 0xaa, 0xf9, 0x06, 0xb1, 0xb1, 0x13, 0x06, 0x00, 0x09, 0x01, + 0x45, 0xef, 0x20, 0x50, 0x37, 0x93, 0x05, 0x00, 0x09, 0x13, 0x05, 0x30, 0x04, 0xef, 0x30, 0xa0, + 0x21, 0x13, 0x07, 0xa0, 0x0a, 0xe3, 0x1c, 0xe5, 0xde, 0x93, 0x8c, 0x0c, 0xf7, 0xb1, 0xb7, 0x93, + 0x85, 0x05, 0x01, 0x01, 0x45, 0x13, 0x06, 0x00, 0x04, 0xef, 0x20, 0xd0, 0x34, 0x93, 0x05, 0x00, + 0x04, 0x13, 0x05, 0x70, 0x04, 0xef, 0x30, 0x20, 0x1f, 0xe3, 0x1a, 0x95, 0xdd, 0x13, 0x04, 0x04, + 0xfb, 0x93, 0x0c, 0x00, 0x08, 0x93, 0x0d, 0xa0, 0x0a, 0xb3, 0x05, 0x8d, 0x40, 0x63, 0xe0, 0x8c, + 0x02, 0x22, 0x86, 0x01, 0x45, 0xef, 0x20, 0xfa, 0xc6, 0xa6, 0xe5, 0xa7, 0x78, 0x93, 0x9b, 0x9b, + 0xb3, 0x5c, 0x39, 0x4b, 0x4d, 0xf4, 0x49, 0x81, 0x0e, 0x08, 0x21, 0xa9, 0xeb, 0x94, 0x1d, 0x2a, + 0x02, 0x3f, 0x7d, 0x8c, 0xf9, 0xb6, 0x0e, 0xe8, 0xd8, 0x1f, 0x10, 0x32, 0xa2, 0x85, 0x13, 0x05, + 0x90, 0x04, 0xef, 0x30, 0x80, 0x1c, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x13, 0xf5, 0xda, 0x85, 0xbf, + 0x01, 0x45, 0x13, 0x06, 0x00, 0x08, 0xef, 0x20, 0x30, 0x30, 0x93, 0x05, 0x00, 0x08, 0x13, 0x05, + 0x80, 0x04, 0xef, 0x30, 0x80, 0x1a, 0xe3, 0x15, 0xb5, 0xd9, 0x13, 0x04, 0x04, 0xf8, 0x7d, 0xbf, + 0x42, 0x04, 0x41, 0x80, 0xa1, 0x47, 0x63, 0x10, 0xf4, 0xf6, 0x03, 0x44, 0x1d, 0x00, 0xbd, 0x47, + 0xe3, 0xe8, 0x87, 0xd6, 0x83, 0x2c, 0x4d, 0x00, 0xfd, 0x57, 0xe3, 0x83, 0xfc, 0xd6, 0x93, 0x19, + 0xa4, 0x00, 0x13, 0x85, 0x09, 0x40, 0xef, 0xe0, 0x8f, 0xe6, 0x13, 0x07, 0xa0, 0x0a, 0x2a, 0x8d, + 0xe3, 0x18, 0xe5, 0xd4, 0x93, 0x89, 0x09, 0x20, 0x4e, 0x85, 0xef, 0xe0, 0x4f, 0xe5, 0xaa, 0x8d, + 0xe3, 0x10, 0xa5, 0xd5, 0xe6, 0x85, 0x4e, 0x85, 0xef, 0x10, 0x60, 0x1b, 0xe3, 0x1a, 0xb5, 0xd3, + 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf5, 0x85, 0x47, 0x33, 0x94, 0x87, 0x00, 0x1c, 0x43, + 0x5d, 0x8c, 0x00, 0xc3, 0x91, 0xbe, 0x42, 0x04, 0x41, 0x80, 0x8d, 0x47, 0x63, 0x1d, 0xf4, 0xee, + 0x83, 0x45, 0x1d, 0x00, 0xbd, 0x47, 0xe3, 0xe5, 0xb7, 0xd0, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, + 0x47, 0xf5, 0xd1, 0x49, 0xb3, 0xd7, 0xb7, 0x00, 0x85, 0x8b, 0xe3, 0x88, 0x07, 0xc8, 0x37, 0x15, + 0x20, 0x00, 0x13, 0x05, 0x05, 0x08, 0xef, 0xe0, 0x6f, 0xeb, 0x85, 0x47, 0xe3, 0x07, 0xf5, 0xb4, + 0x89, 0x47, 0xfa, 0x0c, 0xba, 0xfe, 0x6a, 0x14, 0xb4, 0x28, 0xdf, 0x3d, 0xa4, 0xcc, 0x03, 0x78, + 0x79, 0x42, 0xf4, 0x1e, 0x02, 0x54, 0xb1, 0xd2, 0x31, 0x8d, 0x58, 0x22, 0x6b, 0xea, 0x4d, 0xf1, + 0x80, 0x9a, 0x12, 0xb0, 0x20, 0xe3, 0x0c, 0xf5, 0xc6, 0xe9, 0xb9, 0xef, 0x10, 0x90, 0x43, 0xef, + 0xe0, 0x8f, 0xd8, 0x6f, 0xf0, 0xef, 0xe6, 0xef, 0x00, 0xc0, 0x6f, 0x6f, 0xf0, 0xef, 0xe6, 0xef, + 0x00, 0x30, 0x4e, 0x41, 0x14, 0xaa, 0x86, 0x63, 0x0b, 0x05, 0xea, 0x8d, 0x45, 0x13, 0x85, 0xcd, + 0x3d, 0x36, 0xce, 0x71, 0x24, 0xf2, 0x46, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x45, 0x93, + 0x85, 0xcd, 0x3d, 0x13, 0x05, 0x49, 0x64, 0x09, 0x24, 0xf2, 0x46, 0x09, 0x47, 0x85, 0x47, 0x63, + 0x83, 0xe6, 0x00, 0x89, 0x47, 0x83, 0xc6, 0x89, 0x07, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, + 0x00, 0x22, 0x87, 0x13, 0x06, 0xc6, 0x47, 0x93, 0x85, 0xc5, 0x3f, 0x13, 0x05, 0x49, 0x64, 0xa3, + 0x8c, 0xf9, 0x06, 0xd9, 0x2a, 0xef, 0xe0, 0x8f, 0xce, 0xef, 0xe0, 0x8f, 0xff, 0x62, 0x47, 0x85, + 0x47, 0x23, 0x00, 0xf7, 0x00, 0xef, 0x00, 0xe0, 0x5a, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, + 0x11, 0xf5, 0xd6, 0x25, 0x29, 0x63, 0x1e, 0x85, 0xd4, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, + 0xf4, 0xb1, 0xeb, 0x83, 0xa7, 0x4b, 0x07, 0x13, 0x07, 0xfb, 0x00, 0xfd, 0x17, 0x63, 0x64, 0xf7, + 0x04, 0x05, 0x45, 0xef, 0x20, 0xb0, 0x17, 0x03, 0xa6, 0x4b, 0x07, 0xb7, 0x09, 0x20, 0x00, 0x93, + 0x85, 0x09, 0x00, 0x13, 0x85, 0x09, 0x00, 0xef, 0x20, 0xf0, 0x25, 0x37, 0x14, 0x20, 0x00, 0x13, + 0x05, 0x04, 0x02, 0xef, 0x20, 0x50, 0x34, 0x03, 0xa5, 0x4b, 0x07, 0x93, 0x87, 0xfa, 0xa0, 0x7d, + 0x2a, 0xc4, 0x55, 0xe9, 0x30, 0x6c, 0xe0, 0xc1, 0xd6, 0x46, 0x56, 0x79, 0x5b, 0xe3, 0x6f, 0x7e, + 0x82, 0x9f, 0xf4, 0xc8, 0xb3, 0xe7, 0xaf, 0x30, 0xe1, 0x6a, 0x50, 0x29, 0x09, 0x4f, 0x88, 0x21, + 0x09, 0x00, 0x41, 0x46, 0x3e, 0x95, 0x93, 0x05, 0x04, 0x02, 0xef, 0x30, 0x00, 0x5f, 0x83, 0xa7, + 0x4b, 0x07, 0xc1, 0x07, 0x23, 0xaa, 0xfb, 0x06, 0xef, 0x00, 0xf0, 0x1b, 0x13, 0x04, 0xa0, 0x0a, + 0x63, 0x0a, 0x85, 0xce, 0xef, 0xe0, 0x8f, 0xfe, 0x63, 0x16, 0x85, 0xce, 0x37, 0x56, 0x10, 0x00, + 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x06, 0x4d, 0x93, 0x85, 0xc5, 0x3f, + 0x13, 0x05, 0x45, 0x40, 0x25, 0x22, 0xef, 0xe0, 0x2f, 0xb7, 0xef, 0x20, 0x70, 0x32, 0xef, 0x00, + 0xb0, 0x3a, 0xef, 0x00, 0xb0, 0x31, 0xef, 0xe0, 0xaf, 0xf9, 0x6f, 0xf0, 0xaf, 0xcb, 0x2a, 0x87, + 0x81, 0x47, 0x01, 0x45, 0x63, 0x93, 0xc7, 0x00, 0x82, 0x80, 0xb3, 0x06, 0xf7, 0x00, 0x33, 0x88, + 0xf5, 0x00, 0x83, 0xc6, 0x06, 0x00, 0x03, 0x48, 0x08, 0x00, 0x85, 0x07, 0xb3, 0xc6, 0x06, 0x01, + 0x55, 0x8d, 0x13, 0x75, 0xf5, 0x0f, 0xf9, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x37, 0x37, 0x20, 0x00, + 0x03, 0xa8, 0xc7, 0xf5, 0x83, 0x27, 0x87, 0xf5, 0xaa, 0x86, 0x13, 0x07, 0x87, 0xf5, 0x01, 0x45, + 0x63, 0x13, 0xf8, 0x00, 0x82, 0x80, 0x37, 0x26, 0x20, 0x00, 0x13, 0x06, 0xc6, 0x08, 0x93, 0x08, + 0xf0, 0x7f, 0x63, 0x01, 0xb5, 0x02, 0x33, 0x0e, 0xf6, 0x00, 0x03, 0x4e, 0x0e, 0x00, 0x05, 0x05, + 0x33, 0x83, 0xa6, 0x00, 0xa3, 0x0f, 0xc3, 0xff, 0x85, 0x07, 0x63, 0xf3, 0xf8, 0x00, 0x81, 0x47, + 0xe3, 0x11, 0xf8, 0xfe, 0x1c, 0xc3, 0x82, 0x80, 0xfa, 0xb6, 0x4e, 0x6d, 0xcc, 0xa5, 0x5a, 0x86, + 0x69, 0x4a, 0xed, 0x3b, 0x6d, 0x72, 0xbf, 0x67, 0xbc, 0x76, 0xd6, 0xf5, 0xb3, 0x28, 0x14, 0xf7, + 0xad, 0x82, 0x7d, 0xe7, 0x43, 0x20, 0xa6, 0x8a, 0x9e, 0x60, 0x22, 0xb7, 0x36, 0x20, 0x00, 0xb7, + 0x37, 0x20, 0x00, 0x03, 0xa7, 0x86, 0xf5, 0x83, 0xa7, 0xc7, 0xf5, 0x93, 0x86, 0x86, 0xf5, 0x33, + 0x87, 0xe7, 0x40, 0x63, 0x56, 0x07, 0x00, 0x05, 0x66, 0x13, 0x06, 0x06, 0x80, 0x32, 0x97, 0x63, + 0x5b, 0xe5, 0x00, 0x33, 0x85, 0xa7, 0x40, 0x85, 0x67, 0x93, 0x87, 0x07, 0x80, 0x63, 0xf3, 0xa7, + 0x00, 0x3e, 0x95, 0x88, 0xc2, 0x82, 0x80, 0xb7, 0x36, 0x20, 0x00, 0x03, 0xa8, 0xc6, 0xf5, 0x13, + 0x07, 0xf0, 0x7f, 0x13, 0x86, 0xc6, 0xf5, 0x93, 0x07, 0x18, 0x00, 0x63, 0x73, 0xf7, 0x00, 0x81, + 0x47, 0xb7, 0x36, 0x20, 0x00, 0x83, 0xa8, 0x86, 0xf5, 0x37, 0x27, 0x20, 0x00, 0x93, 0x85, 0x86, + 0xf5, 0x13, 0x07, 0xc7, 0x08, 0x63, 0x9f, 0xf8, 0x00, 0x93, 0x88, 0x17, 0x80, 0x93, 0x86, 0x17, + 0x00, 0x63, 0x93, 0x08, 0x00, 0x81, 0x46, 0x94, 0xc1, 0xba, 0x96, 0x93, 0x05, 0xa0, 0x02, 0x23, + 0x80, 0xb6, 0x00, 0x42, 0x97, 0x23, 0x00, 0xa7, 0x00, 0x1c, 0xc2, 0x82, 0x80, 0x82, 0x80, 0x39, + 0x71, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x06, 0xce, 0x36, 0xd6, 0x3a, 0xd8, 0x3e, 0xda, 0x42, + 0xdc, 0x46, 0xde, 0xaa, 0x84, 0x2e, 0x89, 0x32, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0xdf, 0x96, 0x63, + 0x14, 0x09, 0x00, 0xef, 0xe0, 0x5f, 0x96, 0x19, 0xe0, 0xef, 0xe0, 0xff, 0x95, 0x7c, 0x10, 0x3e, + 0xc6, 0xef, 0x30, 0x20, 0x13, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x60, 0xef, + 0x30, 0x20, 0x38, 0xfa, 0xe6, 0x62, 0x71, 0xcb, 0xf2, 0x2f, 0x27, 0x8e, 0xdf, 0x6e, 0x14, 0xc9, + 0x9a, 0x2d, 0x20, 0x9a, 0x04, 0x69, 0x18, 0x79, 0xa3, 0xfa, 0x80, 0x66, 0xb7, 0x7f, 0xb3, 0xb8, + 0xe0, 0xca, 0x8e, 0x89, 0x38, 0x23, 0x37, 0x55, 0x10, 0x00, 0x4a, 0x86, 0xa6, 0x85, 0x13, 0x05, + 0x05, 0x61, 0xef, 0x30, 0x20, 0x37, 0xb2, 0x45, 0x22, 0x85, 0xef, 0x30, 0x80, 0x33, 0x37, 0x55, + 0x10, 0x00, 0x13, 0x05, 0xc5, 0x61, 0xef, 0x30, 0xe0, 0x35, 0xb9, 0x29, 0xf2, 0x40, 0x62, 0x44, + 0xd2, 0x44, 0x42, 0x49, 0x21, 0x61, 0x82, 0x80, 0xae, 0x86, 0x37, 0x56, 0x10, 0x00, 0xaa, 0x85, + 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x4b, 0x13, 0x05, 0x05, 0x62, 0x9d, 0xbf, 0xb7, 0x37, + 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, 0x83, 0xa6, 0x47, 0x10, 0x63, 0x7e, + 0xd7, 0x00, 0x0a, 0x07, 0x3e, 0x97, 0x18, 0x43, 0x18, 0xc1, 0x03, 0xa7, 0x07, 0x10, 0x13, 0x05, + 0xa0, 0x0a, 0x05, 0x07, 0x23, 0xa0, 0xe7, 0x10, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, + 0x01, 0x11, 0x26, 0xca, 0xb7, 0x34, 0x20, 0x00, 0x83, 0xa7, 0x04, 0xf6, 0x06, 0xce, 0x22, 0xcc, + 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x11, 0x47, 0x63, 0x6f, 0xf7, 0x0c, 0x37, 0x57, 0x10, 0x00, + 0x8a, 0x07, 0x13, 0x07, 0x87, 0x64, 0xba, 0x97, 0x9c, 0x43, 0x2a, 0x84, 0x93, 0x84, 0x04, 0xf6, + 0x82, 0x87, 0x81, 0x45, 0xef, 0x30, 0x20, 0x31, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x92, 0xa7, 0xf6, + 0xb7, 0x37, 0x20, 0x00, 0x23, 0x86, 0x87, 0x88, 0xef, 0x20, 0xd0, 0x6f, 0x9c, 0x40, 0x85, 0x07, + 0x81, 0xa8, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0x07, 0xf6, 0x93, 0x07, 0xc0, 0x0f, 0xfa, 0xf3, + 0x20, 0x9b, 0xa9, 0x6c, 0x78, 0x02, 0x6c, 0xf9, 0x1a, 0x32, 0x3a, 0xc8, 0x02, 0x82, 0xbf, 0x2d, + 0x91, 0x1b, 0x66, 0x20, 0x0c, 0x9b, 0x2b, 0x3e, 0x63, 0xfe, 0xf3, 0x65, 0x4d, 0x49, 0x13, 0x10, + 0x24, 0x63, 0xf1, 0xa7, 0x02, 0x62, 0x44, 0x9d, 0x47, 0xf2, 0x40, 0x42, 0x49, 0xb2, 0x49, 0x22, + 0x4a, 0x9c, 0xc0, 0xd2, 0x44, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x45, 0x62, 0x05, + 0x61, 0x2d, 0xbf, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x49, 0xf6, 0x83, 0x55, 0x09, 0x00, 0xef, + 0x30, 0xa0, 0x2b, 0xb7, 0x37, 0x20, 0x00, 0xa3, 0x86, 0x87, 0x88, 0x23, 0x10, 0xa9, 0x00, 0x8d, + 0x47, 0x5d, 0xf4, 0x9c, 0xc0, 0x91, 0xa8, 0x37, 0x39, 0x20, 0x00, 0x03, 0x27, 0x89, 0xf6, 0x93, + 0x07, 0xb0, 0x0f, 0x13, 0x09, 0x89, 0xf6, 0x63, 0xf4, 0xe7, 0x00, 0xef, 0xe0, 0x3f, 0x81, 0x83, + 0x27, 0x09, 0x00, 0x37, 0x3a, 0x20, 0x00, 0x13, 0x0a, 0x4a, 0xf6, 0xb7, 0x39, 0x20, 0x00, 0x93, + 0x89, 0xc9, 0x88, 0x83, 0x55, 0x0a, 0x00, 0xce, 0x97, 0x23, 0x81, 0x87, 0x00, 0x22, 0x85, 0xef, + 0x30, 0xa0, 0x26, 0x83, 0x27, 0x09, 0x00, 0x03, 0xc7, 0x19, 0x00, 0x23, 0x10, 0xaa, 0x00, 0x85, + 0x07, 0x23, 0x20, 0xf9, 0x00, 0xe3, 0xfd, 0xe7, 0xf4, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, + 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x93, 0xa7, + 0xf6, 0x3d, 0xbf, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x69, 0xf6, 0x13, 0x14, 0x85, 0x00, 0xb7, + 0x39, 0x20, 0x00, 0x03, 0x55, 0x09, 0x00, 0x93, 0x89, 0x49, 0xf6, 0x83, 0xd7, 0x09, 0x00, 0x49, + 0x8c, 0x23, 0x10, 0x89, 0x00, 0xe3, 0x8d, 0x87, 0xf0, 0xfa, 0xd1, 0x60, 0x17, 0x0a, 0xe7, 0x71, + 0xb2, 0x7f, 0xb2, 0xb8, 0x67, 0x0a, 0x5d, 0x9c, 0xb8, 0x5d, 0xc9, 0x9c, 0x96, 0xa9, 0xa7, 0x58, + 0x62, 0x5e, 0x17, 0x4f, 0xcd, 0xd8, 0xcc, 0xa3, 0x23, 0x76, 0xe8, 0x24, 0x37, 0x54, 0x10, 0x00, + 0x13, 0x05, 0x44, 0x62, 0x99, 0x47, 0x89, 0x45, 0x9c, 0xc0, 0x95, 0x3d, 0x93, 0x05, 0x44, 0x62, + 0x62, 0x44, 0x03, 0xd7, 0x09, 0x00, 0x83, 0x56, 0x09, 0x00, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, + 0xb2, 0x49, 0x22, 0x4a, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x86, 0x62, + 0x13, 0x05, 0x45, 0x64, 0x05, 0x61, 0x6f, 0xf0, 0x3f, 0xdd, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, + 0xc7, 0x98, 0xb7, 0x25, 0x10, 0x00, 0x37, 0x25, 0x10, 0x00, 0x23, 0xa0, 0x07, 0x10, 0x23, 0xa2, + 0x07, 0x10, 0x93, 0x85, 0x05, 0xf8, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x05, 0x25, 0xfb, 0x23, 0xa0, + 0x07, 0xf6, 0x6f, 0x20, 0xb0, 0x52, 0x11, 0xed, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0xef, 0xe0, + 0x2f, 0xf2, 0x32, 0x45, 0xf2, 0x40, 0x13, 0x06, 0xe0, 0x0f, 0x81, 0x45, 0x05, 0x61, 0x6f, 0x30, + 0x40, 0x25, 0x13, 0x06, 0xe0, 0x0f, 0x81, 0x45, 0xdd, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, + 0x07, 0xf6, 0x13, 0x05, 0xa0, 0x0a, 0x99, 0xc3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, + 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, 0xf6, 0x1c, 0x40, 0x06, 0xc6, 0x15, 0x47, + 0x63, 0x98, 0xe7, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, + 0x81, 0xe7, 0x13, 0x05, 0x50, 0x05, 0xcd, 0xbf, 0xef, 0x20, 0x90, 0x50, 0x93, 0x07, 0xa0, 0x0a, + 0xe3, 0x19, 0xf5, 0xfe, 0xfa, 0xd4, 0x25, 0x1b, 0xf5, 0x09, 0x66, 0x96, 0x8d, 0x27, 0x3d, 0x08, + 0x18, 0xc9, 0x1f, 0xb0, 0xfe, 0xa7, 0xd9, 0xcd, 0x47, 0xa5, 0x5b, 0x8f, 0x35, 0xfe, 0x20, 0x93, + 0x2e, 0x34, 0x48, 0xa0, 0xe6, 0xc0, 0x25, 0x01, 0x00, 0x18, 0x40, 0x91, 0x47, 0xe3, 0xcd, 0xe7, + 0xfc, 0x99, 0x47, 0x1c, 0xc0, 0xd9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x20, 0x10, 0x50, 0x93, + 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xf5, 0x00, 0xef, 0x20, 0x70, 0x51, 0xb7, 0x37, 0x20, 0x00, 0x03, + 0xa7, 0x07, 0xf6, 0x95, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, + 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x99, + 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, + 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x9d, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, + 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x37, 0x35, 0x20, 0x00, 0x13, 0x05, 0xc5, 0x88, 0x82, + 0x80, 0x01, 0x11, 0x26, 0xca, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0xaa, 0x84, 0x19, + 0xe1, 0xef, 0xe0, 0x2f, 0xe3, 0x83, 0xc7, 0x14, 0x00, 0x13, 0x07, 0xc0, 0x0f, 0x13, 0x05, 0x50, + 0x05, 0x63, 0x65, 0xf7, 0x06, 0x37, 0x39, 0x20, 0x00, 0x13, 0x04, 0xc9, 0x98, 0x23, 0x20, 0x04, + 0x10, 0x03, 0xc7, 0x04, 0x00, 0xa3, 0x00, 0xf4, 0x00, 0x03, 0xc6, 0x14, 0x00, 0x23, 0x00, 0xe4, + 0x00, 0x93, 0x85, 0x24, 0x00, 0x13, 0x05, 0x24, 0x00, 0xef, 0x30, 0x00, 0x10, 0x83, 0xc9, 0x14, + 0x00, 0x13, 0x05, 0xc9, 0x98, 0x13, 0x09, 0xc9, 0x98, 0x93, 0x84, 0x29, 0x00, 0xa6, 0x85, 0xfa, + 0xe8, 0x86, 0x27, 0x2c, 0xd4, 0x07, 0xc4, 0xd6, 0x64, 0x9d, 0x0b, 0xb6, 0x00, 0x19, 0x2a, 0x6d, + 0x30, 0x08, 0xeb, 0xd3, 0x3a, 0x93, 0xc5, 0xc0, 0x89, 0x8d, 0xce, 0x94, 0x48, 0xc1, 0x24, 0x5e, + 0x98, 0x26, 0xef, 0x30, 0x60, 0x08, 0xa2, 0x94, 0x23, 0x80, 0xa4, 0x00, 0x4e, 0x94, 0x21, 0x81, + 0x93, 0x87, 0x49, 0x00, 0xa3, 0x01, 0xa4, 0x00, 0xfd, 0x56, 0x13, 0xf7, 0x37, 0x00, 0x19, 0xef, + 0x89, 0x83, 0x23, 0x22, 0xf9, 0x10, 0xef, 0x20, 0xb0, 0x45, 0x13, 0x05, 0xa0, 0x0a, 0xf2, 0x40, + 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, 0x33, 0x07, 0xf9, 0x00, + 0x23, 0x00, 0xd7, 0x00, 0x85, 0x07, 0xd1, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, + 0x03, 0xa7, 0x07, 0x10, 0x83, 0xa7, 0x47, 0x10, 0x63, 0x14, 0xf7, 0x00, 0x6f, 0x20, 0x30, 0x3e, + 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa0, 0x07, 0xf6, 0x82, 0x80, + 0x41, 0x11, 0x06, 0xc6, 0x93, 0x07, 0x00, 0x08, 0x73, 0xa0, 0x47, 0x30, 0x93, 0x06, 0x70, 0x3e, + 0x09, 0x46, 0x93, 0x05, 0x60, 0x04, 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, 0x30, 0x52, 0x8d, 0x45, + 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, 0x70, 0x52, 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, 0xf0, 0x4f, + 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x10, 0x50, 0xfd, 0x56, 0x01, 0x46, 0x93, 0x05, 0x60, 0x04, + 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x90, 0x4f, 0xb2, 0x40, 0xb7, 0x07, 0x20, 0x01, 0x23, 0xac, + 0x07, 0x00, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x89, 0x2c, 0xb2, 0x40, 0x41, 0x01, + 0x45, 0xb7, 0x41, 0x11, 0x22, 0xc4, 0xb7, 0x07, 0x20, 0x01, 0xfa, 0x40, 0xba, 0x84, 0x16, 0x6e, + 0xb2, 0xc7, 0x1b, 0x8d, 0x50, 0x32, 0x51, 0x91, 0x7e, 0x99, 0x62, 0x34, 0x87, 0xa9, 0x5e, 0x21, + 0x4a, 0x7e, 0x9b, 0x4a, 0x34, 0xb0, 0x61, 0x1f, 0x9c, 0xab, 0x3f, 0x70, 0x27, 0x06, 0xc6, 0x23, + 0xac, 0x07, 0x00, 0x2a, 0x84, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x50, 0x4b, 0x93, 0x07, 0x80, + 0x3e, 0x13, 0x05, 0x80, 0x3e, 0x63, 0xe3, 0x87, 0x00, 0x22, 0x85, 0xb7, 0x07, 0x20, 0x01, 0x98, + 0x4f, 0x13, 0x84, 0x87, 0x01, 0xe3, 0x6d, 0xa7, 0xfe, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0xb0, + 0x49, 0xb2, 0x40, 0x23, 0x20, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x11, 0xe1, 0x82, + 0x80, 0x01, 0x00, 0x7d, 0x15, 0xe5, 0xbf, 0x6f, 0xf0, 0x9f, 0xb3, 0x39, 0xa4, 0x01, 0x11, 0x26, + 0xca, 0xaa, 0x84, 0x37, 0x05, 0x20, 0x01, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x56, 0xc2, 0x06, + 0xce, 0x22, 0xcc, 0x2e, 0x89, 0x93, 0x09, 0xa0, 0x0a, 0xef, 0x20, 0x50, 0x45, 0x37, 0x0a, 0x20, + 0x01, 0x93, 0x0a, 0x80, 0x3e, 0x82, 0x94, 0x2a, 0x84, 0x63, 0x0c, 0x35, 0x03, 0x83, 0x27, 0x8a, + 0x01, 0x63, 0x7a, 0xf9, 0x04, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0xc4, 0x65, 0x85, 0x45, 0xef, + 0xf0, 0x9f, 0xb6, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0x05, 0xc4, 0x65, 0xa6, + 0x86, 0x13, 0x06, 0x06, 0x66, 0x13, 0x05, 0x45, 0x64, 0xef, 0xf0, 0x9f, 0xad, 0x13, 0x04, 0x50, + 0x05, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x30, 0x41, 0xf2, 0x40, 0x22, 0x85, 0x62, 0x44, 0xb7, + 0x07, 0x20, 0x01, 0x23, 0xac, 0x07, 0x00, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, + 0x4a, 0x05, 0x61, 0x82, 0x80, 0xfa, 0x94, 0x9b, 0xa0, 0xf0, 0x1f, 0x46, 0x59, 0x3e, 0x26, 0x93, + 0x73, 0x96, 0xd2, 0xec, 0x9b, 0xdb, 0x12, 0x31, 0x44, 0xdd, 0xbd, 0x4c, 0x46, 0x7f, 0x05, 0xc1, + 0xc0, 0x61, 0xbb, 0x9e, 0x40, 0xea, 0x48, 0x28, 0xe3, 0xf0, 0x2a, 0xfb, 0x41, 0x22, 0x69, 0xbf, + 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x87, 0x00, 0x1c, 0xc7, 0x82, 0x80, 0x41, 0x11, + 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, 0xc1, 0xa9, 0x44, + 0x03, 0x45, 0x04, 0x00, 0x11, 0xe5, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, + 0xef, 0xf0, 0xdf, 0xa1, 0x83, 0x47, 0x04, 0x00, 0x63, 0x94, 0x97, 0x00, 0xef, 0xf0, 0x7f, 0xa6, + 0x05, 0x04, 0xf9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0x25, 0x37, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x05, + 0xf5, 0x00, 0xef, 0xe0, 0xaf, 0xbd, 0x01, 0xa0, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, + 0x22, 0xc4, 0x37, 0x44, 0x20, 0x00, 0x13, 0x06, 0xc0, 0x1f, 0x81, 0x45, 0x13, 0x05, 0x04, 0xe0, + 0x06, 0xc6, 0x26, 0xc2, 0xef, 0x20, 0xb0, 0x6f, 0x13, 0x05, 0x04, 0xe0, 0x93, 0x05, 0xc0, 0x1f, + 0xef, 0x20, 0xb0, 0x67, 0x93, 0x04, 0x04, 0xe0, 0xb2, 0x40, 0x22, 0x44, 0x23, 0xae, 0xa4, 0x1e, + 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x37, 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, + 0xc0, 0x1f, 0x13, 0x04, 0x05, 0xe0, 0x13, 0x05, 0x05, 0xe0, 0x06, 0xc6, 0xef, 0x20, 0xf0, 0x64, + 0x03, 0x27, 0xc4, 0x1f, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xa7, 0x00, 0x93, 0x07, 0x50, 0x05, + 0xb2, 0x40, 0x22, 0x44, 0x3e, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, 0xaa, 0x87, + 0xfa, 0x44, 0x18, 0x96, 0x2e, 0x9f, 0xb7, 0x58, 0xfe, 0x45, 0xa6, 0x7d, 0x48, 0x81, 0x2a, 0x61, + 0x1b, 0x41, 0x18, 0x2b, 0xff, 0x58, 0xa1, 0x89, 0x00, 0xae, 0xfc, 0x78, 0x0c, 0x67, 0x2e, 0xf1, + 0xb8, 0x20, 0x29, 0x63, 0x6e, 0xa7, 0x00, 0x13, 0x77, 0x35, 0x00, 0x01, 0x45, 0x11, 0xeb, 0x37, + 0x45, 0x20, 0x00, 0x13, 0x05, 0x05, 0xe0, 0xf1, 0x9b, 0xaa, 0x97, 0x88, 0x43, 0x82, 0x80, 0x01, + 0x45, 0x82, 0x80, 0x93, 0x07, 0xb0, 0x1f, 0x63, 0xec, 0xa7, 0x00, 0x93, 0x77, 0x35, 0x00, 0x81, + 0xeb, 0xb7, 0x47, 0x20, 0x00, 0x71, 0x99, 0x93, 0x87, 0x07, 0xe0, 0x3e, 0x95, 0x0c, 0xc1, 0x82, + 0x80, 0x41, 0x11, 0x37, 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, 0xc0, 0x1f, 0x13, 0x04, 0x05, + 0xe0, 0x13, 0x05, 0x05, 0xe0, 0x06, 0xc6, 0xef, 0x20, 0x70, 0x5d, 0xb2, 0x40, 0x23, 0x2e, 0xa4, + 0x1e, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, 0x63, 0x61, 0xa7, 0x02, 0x93, + 0x77, 0x35, 0x00, 0x13, 0x07, 0x50, 0x05, 0x89, 0xef, 0x41, 0x11, 0x06, 0xc6, 0x5d, 0x37, 0xc9, + 0x37, 0xb2, 0x40, 0x13, 0x07, 0xa0, 0x0a, 0x3a, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0x50, + 0x05, 0x3a, 0x85, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x00, 0x10, 0x71, 0xb2, 0x40, 0xb7, + 0x07, 0x00, 0x02, 0x0d, 0x47, 0xf8, 0xcb, 0x13, 0x05, 0xa0, 0x0a, 0x41, 0x01, 0x82, 0x80, 0x73, + 0x00, 0x50, 0x10, 0x82, 0x80, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x52, + 0xcc, 0x06, 0xd6, 0x2a, 0x84, 0xae, 0x84, 0x32, 0x89, 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x07, 0x39, + 0x41, 0x33, 0x05, 0x34, 0x01, 0x63, 0x6c, 0xfa, 0x02, 0x71, 0x56, 0xfa, 0xda, 0xc8, 0xbe, 0xfc, + 0x19, 0xff, 0xf1, 0x80, 0xc3, 0xb9, 0x24, 0x40, 0x93, 0x38, 0x69, 0x94, 0xdc, 0x5e, 0x47, 0x09, + 0xf7, 0xd1, 0xab, 0x59, 0xa5, 0x8b, 0x07, 0xe6, 0xbc, 0xa8, 0x92, 0x5d, 0xf8, 0x29, 0x93, 0x57, + 0x29, 0x00, 0xb3, 0x87, 0xc7, 0x02, 0x93, 0x75, 0xc9, 0xff, 0x33, 0x05, 0xb4, 0x00, 0xae, 0x94, + 0x33, 0x86, 0x27, 0x01, 0x11, 0xc6, 0x9c, 0x40, 0x6c, 0x00, 0x3e, 0xc6, 0xef, 0x20, 0xd0, 0x56, + 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, + 0xb3, 0x87, 0x34, 0x01, 0x9c, 0x43, 0x11, 0x46, 0x6c, 0x00, 0x3e, 0xc6, 0x91, 0x09, 0xef, 0x20, + 0xb0, 0x54, 0x7d, 0xb7, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x52, 0xcc, + 0x06, 0xd6, 0x2a, 0x84, 0xae, 0x84, 0x32, 0x89, 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x07, 0x39, 0x41, + 0xb3, 0x85, 0x34, 0x01, 0x63, 0x6d, 0xfa, 0x02, 0x71, 0x56, 0x93, 0x57, 0x29, 0x00, 0xb3, 0x87, + 0xc7, 0x02, 0x93, 0x75, 0xc9, 0xff, 0x2e, 0x94, 0xa6, 0x95, 0x33, 0x86, 0x27, 0x01, 0x01, 0xca, + 0x1c, 0x40, 0x68, 0x00, 0x3e, 0xc6, 0xef, 0x20, 0x30, 0x50, 0xb2, 0x47, 0x1c, 0xc0, 0xb2, 0x50, + 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0x11, 0x46, + 0x68, 0x00, 0xef, 0x20, 0x70, 0x4e, 0x32, 0x47, 0xb3, 0x07, 0x34, 0x01, 0x91, 0x09, 0x98, 0xc3, + 0x75, 0xb7, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x6f, 0x9c, + 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa6, 0xe7, 0xf6, 0xb7, 0x37, 0x20, 0x00, + 0x23, 0xa8, 0x87, 0xf6, 0x22, 0x44, 0xfa, 0x18, 0x05, 0x19, 0xc5, 0x33, 0xbb, 0xae, 0xaa, 0xf1, + 0x81, 0x66, 0xb4, 0xa2, 0x1d, 0x46, 0x9b, 0x70, 0xd9, 0x61, 0xfe, 0x2b, 0x91, 0x1e, 0xc0, 0xa2, + 0x1d, 0x8a, 0x59, 0x06, 0xd2, 0xf0, 0x81, 0xd0, 0x2a, 0xb2, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x23, + 0x8a, 0x07, 0xa8, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xa4, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, + 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x2f, 0x99, 0x37, 0x35, 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0xa2, + 0x85, 0x13, 0x06, 0xe0, 0x0f, 0x13, 0x05, 0x45, 0xa9, 0x23, 0x8a, 0x07, 0xb8, 0xef, 0x20, 0xf0, + 0x47, 0x22, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xb2, 0x41, 0x11, 0x22, + 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0xcf, 0x95, 0xb7, 0x34, 0x20, + 0x00, 0x83, 0xc7, 0x44, 0xb9, 0x99, 0xcb, 0x37, 0x35, 0x20, 0x00, 0x13, 0x06, 0xe0, 0x0f, 0x93, + 0x85, 0x44, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0xef, 0x20, 0x50, 0x44, 0xa2, 0x85, 0x13, 0x85, 0x44, + 0xb9, 0x13, 0x06, 0xe0, 0x0f, 0xef, 0x20, 0x70, 0x43, 0x22, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x92, + 0x44, 0x41, 0x01, 0x6f, 0xf0, 0x1f, 0xae, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0xc7, 0xf6, 0x82, + 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0xc4, 0xf6, 0x26, 0xc2, 0x04, + 0x40, 0x06, 0xc6, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x89, 0xf4, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, + 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x37, 0x35, 0x20, 0x00, 0x13, 0x05, 0x45, + 0xb9, 0xef, 0xf0, 0x3f, 0xaa, 0xe3, 0x13, 0x95, 0xfe, 0x93, 0x07, 0x50, 0x05, 0x1c, 0xc0, 0xc5, + 0xb7, 0xfa, 0x78, 0x17, 0x15, 0x3a, 0x55, 0xa5, 0xc3, 0x0a, 0xbf, 0x4c, 0xcf, 0x2e, 0x59, 0xba, + 0xa5, 0xa3, 0x30, 0xb2, 0xaf, 0xe2, 0xbc, 0x57, 0x06, 0xa8, 0xca, 0x4a, 0x47, 0xa2, 0x41, 0xa9, + 0xbb, 0x73, 0xa8, 0x2b, 0x37, 0x35, 0x20, 0x00, 0x83, 0x47, 0x45, 0xa9, 0x85, 0xc3, 0xb7, 0x37, + 0x20, 0x00, 0x83, 0xc7, 0x47, 0xb9, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, + 0x23, 0xa6, 0xe7, 0xf6, 0x13, 0x05, 0x45, 0xa9, 0x6f, 0xf0, 0xff, 0xa6, 0x13, 0x05, 0x50, 0x05, + 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xdf, 0x99, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, + 0xf5, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x6d, 0x71, 0x23, 0x26, + 0x11, 0x10, 0x23, 0x24, 0x81, 0x10, 0x23, 0x22, 0x91, 0x10, 0xef, 0xf0, 0xdf, 0x98, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x04, 0x2a, 0x84, 0xef, 0xf0, 0x5f, 0x9c, 0x63, 0x1b, 0x85, 0x06, + 0xef, 0xf0, 0xdf, 0xa1, 0x83, 0x46, 0x05, 0x00, 0x93, 0x07, 0x20, 0x0a, 0x2a, 0x84, 0x63, 0x80, + 0xf6, 0x02, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, + 0xc6, 0x66, 0x93, 0x85, 0xc5, 0x67, 0x13, 0x05, 0x45, 0x64, 0xef, 0xf0, 0x6f, 0xeb, 0xb7, 0x37, + 0x20, 0x00, 0x83, 0xa7, 0x07, 0xf7, 0x22, 0x85, 0x82, 0x97, 0xef, 0xf0, 0xff, 0xaa, 0xef, 0xf0, + 0xdf, 0xa8, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x14, 0xf5, 0x08, 0xef, 0xf0, 0x7f, 0x91, + 0x63, 0x10, 0x85, 0x08, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xf6, 0x63, 0x94, 0xa7, 0x04, + 0x03, 0x24, 0x81, 0x10, 0x83, 0x20, 0xc1, 0x10, 0x83, 0x24, 0x41, 0x10, 0xfa, 0x38, 0x47, 0x69, + 0x59, 0x85, 0x64, 0xca, 0xeb, 0xaa, 0x4a, 0x92, 0x8d, 0xec, 0x14, 0xa7, 0xd0, 0xda, 0x70, 0xdf, + 0x52, 0x6e, 0xb7, 0xe1, 0xfe, 0x04, 0x3a, 0x70, 0xff, 0x96, 0x8a, 0x22, 0x4c, 0x80, 0x2c, 0x51, + 0x61, 0x6f, 0xf0, 0x7f, 0xee, 0xef, 0xf0, 0xbf, 0x97, 0x81, 0x44, 0x63, 0x14, 0x85, 0x00, 0x93, + 0x04, 0xc0, 0x07, 0xef, 0xf0, 0x5f, 0x98, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0xdd, + 0xd4, 0x0a, 0x85, 0x23, 0x00, 0x91, 0x00, 0xa3, 0x00, 0x01, 0x00, 0xef, 0xf0, 0x5f, 0xe3, 0x79, + 0xbf, 0x93, 0x04, 0xc0, 0x07, 0xf5, 0xb7, 0xb7, 0x35, 0x20, 0x00, 0x83, 0xc7, 0x45, 0xb9, 0x95, + 0xc3, 0x03, 0x24, 0x81, 0x10, 0x83, 0x20, 0xc1, 0x10, 0x83, 0x24, 0x41, 0x10, 0x37, 0x35, 0x20, + 0x00, 0x13, 0x06, 0xe0, 0x0f, 0x93, 0x85, 0x45, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0x51, 0x61, 0x6f, + 0x20, 0x30, 0x2a, 0x83, 0x20, 0xc1, 0x10, 0x03, 0x24, 0x81, 0x10, 0x83, 0x24, 0x41, 0x10, 0x51, + 0x61, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x23, 0xa2, 0x07, 0x00, 0x21, 0x65, 0x6f, 0x20, 0xc0, + 0x1c, 0x41, 0x11, 0x21, 0x65, 0x06, 0xc6, 0xef, 0x20, 0x60, 0x1b, 0xb2, 0x40, 0xb7, 0x07, 0x01, + 0x04, 0x05, 0x47, 0xd8, 0xc3, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, + 0xc6, 0x93, 0x07, 0x70, 0x02, 0x2a, 0x84, 0xae, 0x84, 0x63, 0xf4, 0xa7, 0x00, 0xef, 0xd0, 0xff, + 0xf4, 0x37, 0x05, 0x01, 0x04, 0x0a, 0x04, 0x13, 0x05, 0x05, 0x10, 0x2a, 0x94, 0x04, 0xc0, 0xb2, + 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x13, 0x87, 0x07, + 0x10, 0x93, 0x87, 0x07, 0x1a, 0x23, 0x20, 0xfa, 0x6d, 0x11, 0x2f, 0x07, 0xc3, 0x1f, 0x9b, 0xe3, + 0x52, 0x05, 0x0c, 0x31, 0xe3, 0x79, 0xdb, 0x6f, 0xad, 0xe0, 0x87, 0x06, 0x72, 0xe2, 0x66, 0x8f, + 0x37, 0x7e, 0x4d, 0x76, 0xb0, 0xa9, 0x92, 0xe7, 0x58, 0x2d, 0x07, 0x00, 0x11, 0x07, 0xe3, 0x1d, + 0xf7, 0xfe, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0xc8, 0xcb, 0x82, 0x80, 0x42, 0x05, 0xb7, 0x07, + 0x01, 0x04, 0xc8, 0xcb, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x88, 0x4b, 0x13, 0x75, 0xf5, 0x0f, + 0x82, 0x80, 0x89, 0x67, 0x37, 0x07, 0x01, 0x04, 0x8d, 0x07, 0x1c, 0xc7, 0x23, 0x2a, 0x07, 0x00, + 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0x2a, 0x84, 0xad, 0x37, 0xb7, 0x07, 0x01, 0x04, + 0x80, 0xcf, 0xc5, 0x37, 0x65, 0x37, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0xa9, 0xb7, 0xb7, 0x06, + 0x01, 0x04, 0x9c, 0x46, 0x05, 0x45, 0x13, 0xf7, 0x17, 0x00, 0x1d, 0xc7, 0x13, 0xf7, 0x07, 0x40, + 0x0d, 0x45, 0x1d, 0xe3, 0x98, 0x4a, 0x13, 0x77, 0xf7, 0x0f, 0x19, 0xcf, 0x13, 0xf7, 0x27, 0x20, + 0x09, 0x45, 0x19, 0xeb, 0x13, 0xd7, 0xb7, 0x00, 0x05, 0x8b, 0x11, 0x45, 0x11, 0xe7, 0x13, 0xd5, + 0x87, 0x00, 0x13, 0x45, 0x15, 0x00, 0x05, 0x89, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x88, 0xcf, + 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, 0x06, 0xce, 0x33, 0x07, 0xb6, 0x00, 0x93, 0x07, 0x00, 0x09, + 0x2e, 0x84, 0x63, 0xf8, 0xe7, 0x00, 0x32, 0xc6, 0x2a, 0xc4, 0xef, 0xd0, 0x5f, 0xe7, 0x32, 0x46, + 0x22, 0x45, 0xb7, 0x15, 0x01, 0x04, 0xa2, 0x95, 0xef, 0xf0, 0xdf, 0xbb, 0xf2, 0x40, 0x62, 0x44, + 0x13, 0x05, 0xa0, 0x0a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, 0x26, 0xca, 0x06, 0xce, + 0x33, 0x07, 0xfa, 0xb6, 0xbb, 0xbe, 0x4b, 0xcc, 0xe1, 0x00, 0x6d, 0x5a, 0x44, 0x4a, 0x88, 0xc0, + 0xdf, 0x12, 0x8b, 0x8d, 0x54, 0x2f, 0xa7, 0x7c, 0x41, 0x60, 0x8b, 0x58, 0xbf, 0x5c, 0x20, 0x9e, + 0xae, 0x13, 0xdf, 0x30, 0x2e, 0xb6, 0x00, 0x93, 0x07, 0x00, 0x08, 0xaa, 0x84, 0x2e, 0x84, 0x63, + 0xf6, 0xe7, 0x00, 0x32, 0xc6, 0xef, 0xd0, 0xdf, 0xe3, 0x32, 0x46, 0x37, 0x25, 0x01, 0x04, 0x13, + 0x05, 0x05, 0x80, 0x22, 0x95, 0x62, 0x44, 0xf2, 0x40, 0xa6, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x6f, + 0xf0, 0x5f, 0xbe, 0x39, 0x71, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0xb7, 0x55, 0x10, 0x00, 0x37, + 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x06, 0x68, 0x93, 0x85, 0x05, 0x69, 0x13, + 0x05, 0x45, 0x69, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x36, 0xd0, 0x3a, 0xce, 0x3e, + 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xf0, 0xcf, + 0xc5, 0xef, 0xe0, 0xcf, 0xc8, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, + 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, + 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x09, 0x65, 0x6f, 0x10, 0x70, + 0x7f, 0x09, 0x65, 0x6f, 0x10, 0xd0, 0x7f, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, + 0xe1, 0xef, 0xd0, 0x1f, 0xda, 0xdd, 0x37, 0xb7, 0x07, 0x00, 0x07, 0x83, 0x46, 0x14, 0x00, 0xd8, + 0x43, 0x83, 0x47, 0x04, 0x00, 0xa2, 0x06, 0xdd, 0x8e, 0x83, 0x47, 0x24, 0x00, 0xc2, 0x07, 0xdd, + 0x8e, 0x83, 0x47, 0x34, 0x00, 0xe2, 0x07, 0xd5, 0x8f, 0x93, 0x06, 0xf0, 0x0f, 0xfa, 0x95, 0x26, + 0xce, 0x7e, 0x38, 0xc4, 0x24, 0x38, 0xce, 0xb6, 0xd6, 0xa3, 0x70, 0x26, 0x3c, 0x10, 0x03, 0x06, + 0x59, 0x19, 0xbe, 0x61, 0x9d, 0xb7, 0x92, 0xe5, 0x61, 0x0d, 0x21, 0x66, 0x74, 0x53, 0x08, 0x2f, + 0x63, 0x85, 0xd7, 0x00, 0x61, 0x9b, 0x9d, 0x8b, 0x5d, 0x8f, 0x93, 0x77, 0x77, 0xff, 0x03, 0x47, + 0x44, 0x00, 0x83, 0x46, 0x94, 0x00, 0xb2, 0x40, 0x0e, 0x07, 0x21, 0x8b, 0x5d, 0x8f, 0xfd, 0x77, + 0xbd, 0x07, 0x7d, 0x8f, 0x83, 0x47, 0x54, 0x00, 0x92, 0x07, 0x5d, 0x8f, 0xb7, 0x17, 0x80, 0xff, + 0xfd, 0x17, 0x7d, 0x8f, 0x83, 0x47, 0xa4, 0x00, 0xa2, 0x07, 0xd5, 0x8f, 0xb2, 0x07, 0xb7, 0xf6, + 0x7f, 0x00, 0xf5, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x80, 0xf8, 0x7d, 0x17, 0xf9, 0x8f, 0x03, 0x47, + 0x74, 0x00, 0xb7, 0x06, 0x80, 0x07, 0x5e, 0x07, 0x75, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x00, 0x88, + 0x7d, 0x17, 0xf9, 0x8f, 0x03, 0x47, 0x64, 0x00, 0xb7, 0x06, 0x00, 0x78, 0x22, 0x44, 0x6e, 0x07, + 0x75, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x00, 0x07, 0x5c, 0xc3, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, + 0x20, 0x00, 0x03, 0xa5, 0x87, 0xf7, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, + 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x07, + 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x13, 0x05, 0xa0, 0x0a, 0x89, 0x8b, 0x99, 0xe3, 0x13, 0x05, + 0x50, 0x05, 0x82, 0x80, 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, + 0x65, 0xba, 0x6f, 0xf0, 0xbf, 0x8c, 0x41, 0x11, 0xb7, 0x07, 0x08, 0x05, 0x22, 0xc4, 0x03, 0xa4, + 0xc7, 0x20, 0x37, 0x07, 0x00, 0x04, 0x06, 0xc6, 0xfa, 0x88, 0x8b, 0xd0, 0x34, 0x62, 0xf6, 0xa2, + 0x84, 0xda, 0xf2, 0x4d, 0x73, 0xc7, 0x42, 0x72, 0xad, 0xfe, 0xfa, 0xa9, 0xe0, 0x34, 0x85, 0xbf, + 0xfc, 0x28, 0xa2, 0x78, 0x1f, 0x55, 0xb0, 0x29, 0xc8, 0xe0, 0x2f, 0x26, 0xc2, 0xb3, 0x76, 0xe4, + 0x00, 0x91, 0xca, 0x37, 0x55, 0x10, 0x00, 0x23, 0xa6, 0xe7, 0x20, 0xa5, 0x45, 0x13, 0x05, 0x85, + 0x69, 0xef, 0xf0, 0x4f, 0xb7, 0xb7, 0x07, 0x80, 0x6b, 0xe1, 0x8f, 0x95, 0xcb, 0x37, 0x07, 0x08, + 0x05, 0x23, 0x26, 0xf7, 0x20, 0xb7, 0x07, 0x00, 0x68, 0x7d, 0x8c, 0x93, 0x04, 0x50, 0x05, 0x11, + 0xc8, 0x37, 0x55, 0x10, 0x00, 0x9d, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xf0, 0xaf, 0xb4, 0xef, + 0xd0, 0x9f, 0xc5, 0xb2, 0x40, 0x22, 0x44, 0x26, 0x85, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, + 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0xf7, 0x84, 0x43, 0x13, 0x07, 0xa0, 0x0a, 0x63, 0x96, 0xe4, + 0x00, 0x13, 0x07, 0x50, 0x05, 0x98, 0xc3, 0xe1, 0xbf, 0x93, 0x04, 0xa0, 0x0a, 0xd9, 0xbf, 0x81, + 0x47, 0xb7, 0x05, 0x08, 0x05, 0x13, 0x07, 0x00, 0x20, 0xb3, 0x86, 0xb7, 0x00, 0x90, 0x42, 0xb3, + 0x06, 0xf5, 0x00, 0x91, 0x07, 0x90, 0xc2, 0xe3, 0x99, 0xe7, 0xfe, 0x6f, 0xf0, 0xff, 0xf5, 0x41, + 0x11, 0x06, 0xc6, 0x22, 0xc4, 0x2a, 0x84, 0xef, 0xf0, 0x1f, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x13, + 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf6, 0x8d, 0x47, 0x33, 0x95, 0x87, 0x00, 0xb7, 0xb7, 0xaa, + 0x02, 0x93, 0x87, 0xa7, 0xaa, 0x3d, 0x8d, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xa4, 0xa7, 0x20, 0x89, + 0x65, 0x37, 0x35, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x65, 0xb8, 0xef, 0xf0, 0x2f, + 0xfe, 0x22, 0x44, 0xfa, 0x1a, 0x63, 0x25, 0x90, 0x88, 0x74, 0xb1, 0x43, 0xbe, 0x41, 0x10, 0x74, + 0x98, 0xaa, 0xbb, 0x41, 0x30, 0x3a, 0xe0, 0xf3, 0xda, 0x33, 0xc8, 0x64, 0x91, 0x18, 0x1d, 0x8b, + 0x47, 0x59, 0xf3, 0xb6, 0xb8, 0x30, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0xf1, 0x41, 0x11, + 0x06, 0xc6, 0xef, 0xf0, 0x9f, 0xef, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf7, 0x37, 0x07, + 0x08, 0x05, 0x13, 0x05, 0x00, 0x20, 0xf9, 0x9b, 0x23, 0x22, 0xf7, 0x20, 0xef, 0x10, 0xd0, 0x5e, + 0xb2, 0x40, 0x39, 0x45, 0x41, 0x01, 0x6f, 0x10, 0xf0, 0x5f, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, + 0x47, 0xf7, 0x1c, 0x43, 0x93, 0xf7, 0xf7, 0xfd, 0x1c, 0xc3, 0x37, 0x07, 0x08, 0x05, 0x23, 0x22, + 0xf7, 0x20, 0x82, 0x80, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf7, 0x1c, 0x43, 0x93, 0xe7, + 0x07, 0x02, 0x1c, 0xc3, 0x37, 0x07, 0x08, 0x05, 0x23, 0x22, 0xf7, 0x20, 0x82, 0x80, 0x33, 0x87, + 0xc5, 0x00, 0xb7, 0x07, 0x08, 0x00, 0x63, 0x7c, 0xf7, 0x06, 0x01, 0x11, 0x22, 0xcc, 0x26, 0xca, + 0x4e, 0xc6, 0x06, 0xce, 0x4a, 0xc8, 0x93, 0xf4, 0x35, 0x00, 0xaa, 0x89, 0x2e, 0x84, 0x13, 0x05, + 0x50, 0x05, 0x9d, 0xec, 0x32, 0x89, 0xef, 0xf0, 0x5f, 0xe7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, + 0x47, 0xf7, 0xb7, 0x06, 0x08, 0x05, 0xb7, 0x05, 0x00, 0x05, 0x13, 0x67, 0x27, 0x00, 0x23, 0xa2, + 0xe6, 0x20, 0x93, 0x87, 0x47, 0xf7, 0x0d, 0x47, 0x2e, 0x94, 0xb3, 0x06, 0x99, 0x40, 0x63, 0x60, + 0xd7, 0x02, 0x98, 0x43, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x05, 0xa0, 0x0a, 0x23, 0xa2, 0xe7, 0x20, + 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, 0xfa, 0x3b, + 0x8a, 0x2e, 0xdc, 0xb8, 0x48, 0x65, 0x49, 0xab, 0xc4, 0x7a, 0xf3, 0x88, 0x67, 0xef, 0x4f, 0x5f, + 0x6e, 0xac, 0xe9, 0xe9, 0x77, 0x77, 0xec, 0xb9, 0xeb, 0x76, 0x12, 0x5f, 0x26, 0x4d, 0x18, 0x90, + 0x31, 0xb3, 0x06, 0x94, 0x00, 0x90, 0x42, 0xb3, 0x86, 0x99, 0x00, 0x91, 0x04, 0x90, 0xc2, 0xf9, + 0xb7, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, 0xaa, 0x85, 0x11, 0x46, 0x68, 0x00, 0x06, + 0xce, 0xef, 0xf0, 0x1f, 0xf7, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x00, 0x32, 0x45, 0xf2, + 0x40, 0x05, 0x61, 0x82, 0x80, 0x01, 0x45, 0xe5, 0xbf, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xef, 0xa7, + 0x02, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x8d, + 0xe3, 0xae, 0x84, 0xef, 0xf0, 0xbf, 0xdd, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x22, + 0x44, 0xb2, 0x40, 0x23, 0xaa, 0x97, 0x20, 0x92, 0x44, 0x01, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x9f, + 0xe7, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x82, 0x80, 0x41, 0x11, 0x22, + 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xaa, 0x84, 0x2e, 0x84, 0x45, 0x3f, 0x26, 0x85, 0xef, 0xf0, 0xbf, + 0xf8, 0x63, 0x09, 0x85, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, + 0x01, 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xcd, 0xbf, 0x01, 0x11, 0x22, 0xcc, 0x2e, 0xc6, 0x06, + 0xce, 0x2a, 0x84, 0xef, 0xf0, 0x5f, 0xf6, 0xb2, 0x45, 0x63, 0x03, 0xb5, 0x02, 0xfd, 0x57, 0x63, + 0x1a, 0xf5, 0x00, 0x63, 0x8e, 0xa5, 0x00, 0x22, 0x85, 0x62, 0x44, 0xf2, 0x40, 0x05, 0x61, 0x6f, + 0xf0, 0xff, 0xfa, 0x13, 0x05, 0x50, 0x05, 0xf2, 0x40, 0xfa, 0xa4, 0xc1, 0x41, 0xb4, 0x46, 0x93, + 0x4a, 0xa4, 0xda, 0x59, 0x17, 0x81, 0xe3, 0x3f, 0x46, 0x01, 0x0d, 0x5f, 0x1e, 0x72, 0x07, 0x6e, + 0x42, 0x96, 0x9f, 0x71, 0xfb, 0x76, 0x34, 0x41, 0x9a, 0x74, 0x68, 0x32, 0x62, 0x44, 0x05, 0x61, + 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xd5, 0xbf, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe0, 0xb7, 0x04, + 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0xf7, 0xf5, 0x1f, 0xaa, 0x84, 0x2e, 0x84, + 0x13, 0x05, 0x50, 0x05, 0x99, 0xef, 0xef, 0xf0, 0xbf, 0xd2, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, + 0x87, 0x20, 0x39, 0x45, 0xef, 0xf0, 0x5f, 0xdd, 0x26, 0x85, 0xef, 0xf0, 0xff, 0xda, 0x13, 0x05, + 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, + 0x82, 0x80, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xb7, 0x07, + 0x08, 0x00, 0x63, 0xfb, 0xb7, 0x00, 0x81, 0x44, 0xf2, 0x40, 0x62, 0x44, 0x42, 0x49, 0xb2, 0x49, + 0x26, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x82, 0x80, 0x93, 0xf4, 0xf5, 0x1f, 0x2e, 0x84, 0xe5, 0xf4, + 0x2a, 0x89, 0xef, 0xf0, 0xff, 0xcc, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x41, 0x45, + 0xef, 0xf0, 0x9f, 0xd7, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x17, 0xf5, 0xfc, 0x37, 0x34, 0x20, 0x00, + 0x13, 0x05, 0x44, 0xc9, 0xef, 0xf0, 0x5f, 0xd4, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x87, 0x07, 0x20, + 0x23, 0xa0, 0x07, 0x00, 0x91, 0x07, 0xe3, 0x9d, 0xe7, 0xfe, 0x93, 0x09, 0x44, 0xc9, 0x03, 0xd6, + 0xc9, 0x1f, 0x93, 0x07, 0xc0, 0x1d, 0x63, 0xfa, 0xc7, 0x00, 0x37, 0x55, 0x10, 0x00, 0x99, 0x45, + 0x13, 0x05, 0x85, 0x69, 0xfa, 0x87, 0xd6, 0x01, 0xc6, 0x86, 0x57, 0xeb, 0x97, 0xe7, 0x5f, 0x8b, + 0x28, 0x38, 0xd1, 0xb8, 0xbf, 0xf6, 0x15, 0xda, 0x1b, 0x1b, 0x73, 0xbb, 0x60, 0xc2, 0x24, 0x8f, + 0x16, 0xfd, 0x04, 0x4d, 0x44, 0x40, 0x33, 0xef, 0xf0, 0xaf, 0x82, 0x41, 0xbf, 0x93, 0x05, 0x44, + 0xc9, 0x4a, 0x85, 0xef, 0x20, 0x60, 0x43, 0x83, 0xd4, 0xc9, 0x1f, 0x41, 0xb7, 0xb7, 0x07, 0x08, + 0x00, 0x63, 0xe7, 0xa7, 0x04, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xc6, 0x26, + 0xc2, 0x2a, 0x84, 0x13, 0x05, 0x50, 0x05, 0x9d, 0xe7, 0xef, 0xf0, 0xbf, 0xc4, 0x85, 0x67, 0xb7, + 0x04, 0x08, 0x05, 0x93, 0x87, 0x97, 0x82, 0x23, 0xa2, 0xf4, 0x20, 0x23, 0xac, 0x84, 0x20, 0x39, + 0x45, 0xef, 0xf0, 0xbf, 0xce, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf7, 0x13, 0x05, 0xa0, + 0x0a, 0x23, 0xa2, 0xf4, 0x20, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, + 0x05, 0x50, 0x05, 0x82, 0x80, 0x0d, 0x65, 0x01, 0x11, 0x13, 0x05, 0x05, 0x20, 0x06, 0xce, 0x22, + 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xef, 0x10, 0xf0, 0x2f, 0x39, 0x45, 0xef, 0x10, 0x50, + 0x31, 0x13, 0x05, 0x80, 0x07, 0x37, 0x39, 0x20, 0x00, 0xef, 0xf0, 0x6f, 0xb9, 0x93, 0x09, 0x49, + 0xf7, 0x83, 0xa7, 0x09, 0x00, 0x37, 0x04, 0x08, 0x05, 0x93, 0x04, 0x04, 0x20, 0xdc, 0xc0, 0xb7, + 0x07, 0x46, 0x00, 0x85, 0x07, 0xdc, 0xcc, 0x85, 0x67, 0x93, 0x87, 0x57, 0x86, 0x89, 0x65, 0x37, + 0x35, 0x10, 0x00, 0xdc, 0xc0, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x05, 0xb9, 0xef, 0xf0, 0xef, + 0xc8, 0xb7, 0x07, 0x40, 0x08, 0x9c, 0xc8, 0xdc, 0x40, 0x01, 0x45, 0x13, 0x09, 0x49, 0xf7, 0xfa, + 0x24, 0x90, 0x58, 0x5a, 0x4c, 0x24, 0x94, 0x96, 0x0f, 0x8f, 0xe0, 0x4e, 0xa1, 0x7b, 0x97, 0xdb, + 0x3a, 0xa4, 0x2b, 0xbb, 0xed, 0x68, 0x5b, 0x31, 0x18, 0xf3, 0xc2, 0x88, 0xd7, 0xe1, 0xbe, 0x09, + 0x18, 0x34, 0x93, 0xe7, 0x07, 0x18, 0x23, 0xa0, 0xf9, 0x00, 0xef, 0xf0, 0x7f, 0xf3, 0x93, 0x07, + 0x04, 0x10, 0x98, 0x43, 0xb7, 0x67, 0xa5, 0xf0, 0x93, 0x87, 0xf7, 0xa0, 0x63, 0x05, 0xf7, 0x02, + 0x37, 0x55, 0x10, 0x00, 0x95, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, 0xbf, 0xf2, 0x41, 0x67, + 0x7d, 0x17, 0x93, 0x07, 0x04, 0x18, 0xb8, 0xd3, 0xf8, 0xd3, 0xb8, 0xd7, 0xf8, 0xd7, 0xb8, 0xdb, + 0xf8, 0xdb, 0xb8, 0xdf, 0xf8, 0xdf, 0x51, 0x45, 0xef, 0xf0, 0x7f, 0xc1, 0xb7, 0x07, 0x08, 0x05, + 0x83, 0xa7, 0xc7, 0x20, 0x91, 0x8b, 0x91, 0xeb, 0x37, 0x55, 0x10, 0x00, 0x91, 0x45, 0x13, 0x05, + 0x85, 0x69, 0xef, 0xe0, 0x3f, 0xef, 0xef, 0xd0, 0x1f, 0x80, 0xb7, 0x07, 0x08, 0x05, 0x37, 0x07, + 0x40, 0x00, 0x23, 0xa6, 0xe7, 0x20, 0x03, 0x27, 0x09, 0x00, 0xf2, 0x40, 0x62, 0x44, 0x23, 0xa2, + 0xe7, 0x20, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, 0x85, 0x67, 0x37, 0x37, + 0x20, 0x00, 0x93, 0x87, 0x47, 0x86, 0x23, 0x2a, 0xf7, 0xf6, 0x37, 0x37, 0x20, 0x00, 0x93, 0x07, + 0x50, 0x05, 0x23, 0x2c, 0xf7, 0xf6, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2e, 0xf7, 0xf6, 0x6f, 0xf0, + 0xbf, 0xee, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe0, 0xa7, 0x06, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x77, + 0xf5, 0x1f, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x13, 0x05, 0x50, 0x05, 0xa1, 0xe3, 0xae, 0x84, + 0xef, 0xf0, 0x7f, 0xad, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0xfa, 0xcc, 0xb7, 0xcb, 0x99, 0x87, + 0x50, 0x69, 0xb1, 0xf9, 0x94, 0xfc, 0x0a, 0x9c, 0x81, 0x0c, 0x13, 0x9e, 0x7e, 0x4c, 0x8f, 0xef, + 0x6f, 0xb7, 0x41, 0x54, 0x55, 0xca, 0x5f, 0xed, 0x41, 0xf0, 0x95, 0xf0, 0x34, 0x87, 0x20, 0x01, + 0x47, 0x93, 0x06, 0x00, 0x20, 0xb3, 0x85, 0xe4, 0x00, 0x8c, 0x41, 0x33, 0x06, 0xf7, 0x00, 0x11, + 0x07, 0x0c, 0xc2, 0xe3, 0x19, 0xd7, 0xfe, 0x7d, 0x57, 0x93, 0x87, 0x07, 0x20, 0xf8, 0xc3, 0xb8, + 0xc7, 0xf8, 0xc7, 0xb8, 0xcb, 0x29, 0x45, 0xef, 0xf0, 0xbf, 0xb5, 0x13, 0x05, 0xa0, 0x0a, 0xb2, + 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xaa, + 0x85, 0x37, 0x05, 0x08, 0x05, 0x41, 0x46, 0x13, 0x05, 0x05, 0x26, 0x6f, 0xf0, 0x0f, 0xd0, 0xb7, + 0x07, 0x08, 0x00, 0x63, 0xef, 0xa7, 0x0a, 0x01, 0x11, 0x26, 0xca, 0x93, 0x77, 0xf5, 0x1f, 0x06, + 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x56, 0xc2, 0xaa, 0x84, 0x13, 0x05, 0x50, + 0x05, 0xd9, 0xe7, 0x93, 0x07, 0xc0, 0x1d, 0x32, 0x89, 0x63, 0xe3, 0xc7, 0x08, 0xb6, 0x89, 0x37, + 0x34, 0x20, 0x00, 0x2e, 0x8a, 0xef, 0xf0, 0x5f, 0xa4, 0x13, 0x06, 0x00, 0x20, 0x81, 0x45, 0x13, + 0x05, 0x44, 0xc9, 0xef, 0x20, 0x80, 0x23, 0x4a, 0x86, 0xd2, 0x85, 0x13, 0x05, 0x44, 0xc9, 0xef, + 0x20, 0x00, 0x1f, 0x4e, 0x85, 0xef, 0xf0, 0xbf, 0xf9, 0x93, 0x0a, 0x44, 0xc9, 0xb7, 0x07, 0x08, + 0x05, 0x23, 0x9e, 0x2a, 0x1f, 0x13, 0x07, 0x44, 0xc9, 0x93, 0x86, 0x07, 0x20, 0x10, 0x43, 0x11, + 0x07, 0x90, 0xc3, 0x91, 0x07, 0xe3, 0x9c, 0xd7, 0xfe, 0x13, 0x06, 0x00, 0x20, 0x81, 0x45, 0x13, + 0x05, 0x44, 0xc9, 0xef, 0x20, 0xfa, 0xcd, 0x17, 0x3b, 0x60, 0x95, 0xd6, 0x31, 0x79, 0xac, 0x58, + 0x84, 0x4c, 0x84, 0x77, 0x62, 0xf5, 0x10, 0x21, 0x64, 0xf5, 0xdc, 0xaa, 0x02, 0x69, 0x6c, 0x97, + 0xd5, 0x27, 0xe0, 0xab, 0x0a, 0xec, 0xc8, 0x35, 0x80, 0x1f, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, + 0x97, 0x20, 0x31, 0x45, 0xef, 0xf0, 0x1f, 0xaa, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, + 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x69, 0x8d, 0x45, 0xef, 0xe0, 0x1f, 0xd8, 0x13, 0x05, + 0x50, 0x05, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, + 0x05, 0x61, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xeb, + 0xa7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0xf5, 0x1f, 0x2a, 0x84, 0x89, 0xef, + 0xef, 0xf0, 0xdf, 0x99, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x22, 0x44, 0xb2, 0x40, + 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x1f, 0xa4, 0xb2, 0x40, 0x22, 0x44, 0x13, 0x05, 0x50, 0x05, + 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, + 0x37, 0x04, 0x08, 0x05, 0x23, 0x2c, 0xa4, 0x20, 0xef, 0xf0, 0x5f, 0x96, 0xb7, 0x37, 0x20, 0x00, + 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf6, 0xb7, 0xb7, 0xaa, 0x02, 0x93, 0x87, 0x67, 0xaa, + 0xb2, 0x40, 0x23, 0x24, 0xf4, 0x20, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, + 0xef, 0xf0, 0xdf, 0x93, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf6, + 0xb2, 0x40, 0xb7, 0xb7, 0xa6, 0x02, 0x37, 0x07, 0x08, 0x05, 0x93, 0x87, 0xa7, 0xaa, 0x23, 0x24, + 0xfa, 0x95, 0x37, 0xbf, 0x20, 0x50, 0xa1, 0x69, 0x7a, 0xe0, 0xf3, 0x6d, 0x53, 0xad, 0x26, 0x31, + 0xe0, 0x51, 0x92, 0x34, 0x39, 0x79, 0x78, 0xf1, 0x1e, 0x1b, 0x7d, 0x2e, 0xd6, 0x93, 0xf7, 0x2f, + 0x6d, 0xa0, 0x36, 0xf7, 0x20, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x3e, 0xcc, 0xb7, 0x07, 0x08, + 0x05, 0x3a, 0xce, 0x03, 0xa7, 0xc7, 0x20, 0x36, 0xd0, 0xb7, 0x06, 0x40, 0x00, 0x06, 0xde, 0x16, + 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x42, 0xca, 0x46, 0xc8, 0x72, + 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0x75, 0x8f, 0x05, 0xcf, 0x23, 0xa6, 0xd7, 0x20, 0x13, + 0x07, 0xa0, 0x0a, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0xe7, 0xf6, 0xf2, 0x50, 0xe2, 0x52, 0x52, + 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, + 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, + 0x30, 0x03, 0xa7, 0xc7, 0x20, 0xb7, 0x06, 0x00, 0x08, 0x37, 0x55, 0x10, 0x00, 0x75, 0x8f, 0x0d, + 0xc3, 0x23, 0xa6, 0xd7, 0x20, 0x85, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, 0x3f, 0xc4, 0xb7, + 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xae, 0xe7, 0xf6, 0xef, 0xd0, 0x1f, 0xbf, 0x75, + 0xb7, 0x89, 0x45, 0x13, 0x05, 0x85, 0x69, 0xef, 0xe0, 0x7f, 0xc2, 0xb7, 0x07, 0x02, 0x00, 0x73, + 0xb0, 0x47, 0x30, 0xe5, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa0, 0xe7, + 0xf8, 0x82, 0x80, 0x99, 0x47, 0x63, 0x05, 0xf5, 0x02, 0x9d, 0x47, 0x63, 0x0b, 0xf5, 0x00, 0x95, + 0x47, 0x63, 0x15, 0xf5, 0x02, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0xfa, 0xa3, 0x09, 0xcb, 0x2d, + 0xb6, 0x5d, 0xc5, 0x70, 0x27, 0xa3, 0xec, 0xa9, 0x20, 0x7b, 0x42, 0x3e, 0x1d, 0x30, 0xa7, 0x02, + 0x0f, 0x2e, 0x25, 0x5e, 0x60, 0xc0, 0x2e, 0xd5, 0xd5, 0xe5, 0x8c, 0xd5, 0x78, 0x37, 0x93, 0xf7, + 0xf7, 0xf7, 0x29, 0xa8, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa0, 0xe7, 0xf8, + 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xe7, 0x07, 0x08, 0x7c, 0xc3, 0x82, 0x80, + 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf8, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, 0xf7, 0x00, + 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xe7, 0x07, 0x08, 0x7c, 0xc3, 0x82, 0x80, 0xb7, 0x37, + 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf8, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, 0xf7, 0x00, 0x37, 0x07, + 0x00, 0x02, 0x7c, 0x43, 0x93, 0xf7, 0xf7, 0xf7, 0x7c, 0xc3, 0x82, 0x80, 0x39, 0x71, 0x2a, 0xd6, + 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, 0x13, 0x05, 0xc5, 0x69, 0x85, 0x45, 0x06, 0xde, 0x16, 0xdc, + 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, + 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0x9f, 0xb6, 0xef, 0xd0, 0x3f, 0xb2, + 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, + 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, + 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x39, 0x71, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, + 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, + 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0xfa, 0xa8, 0xed, 0xde, 0xce, 0x91, 0xc3, 0x7a, 0x31, 0xd3, + 0xa0, 0xfc, 0x59, 0x91, 0xba, 0x61, 0x15, 0xe2, 0x5a, 0x4b, 0x2a, 0xc3, 0xa6, 0xc6, 0x96, 0xb4, + 0xbe, 0x15, 0x50, 0xd2, 0xfe, 0x4a, 0x6f, 0x50, 0x38, 0x7e, 0xc0, 0xf3, 0x25, 0x20, 0x34, 0xc1, + 0x67, 0x37, 0x55, 0x10, 0x00, 0xdd, 0x8d, 0x13, 0x05, 0xc5, 0x69, 0xef, 0xe0, 0x9f, 0xb0, 0xef, + 0xd0, 0x3f, 0xac, 0x01, 0xa0, 0x39, 0x71, 0x2a, 0xd6, 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, 0x13, + 0x05, 0xc5, 0x69, 0x89, 0x45, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, 0x36, + 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, + 0xc0, 0xef, 0xe0, 0x3f, 0xad, 0xef, 0xd0, 0xdf, 0xa8, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, + 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, + 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, + 0x07, 0x01, 0x01, 0xb7, 0x07, 0x00, 0x01, 0x13, 0x07, 0x17, 0x10, 0x98, 0xd3, 0x37, 0x07, 0x03, + 0x04, 0x09, 0x07, 0xd8, 0xd3, 0x13, 0x07, 0x50, 0x60, 0x98, 0xd7, 0x37, 0x17, 0x09, 0x00, 0x13, + 0x07, 0x77, 0x80, 0xd8, 0xd7, 0x37, 0x17, 0x0b, 0x0b, 0x13, 0x07, 0xa7, 0xa0, 0x98, 0xdb, 0x37, + 0x17, 0x0c, 0x00, 0x13, 0x07, 0xb7, 0xc0, 0xd8, 0xdb, 0x37, 0x17, 0x0f, 0x00, 0x13, 0x07, 0xd7, + 0xe0, 0x98, 0xdf, 0x05, 0x67, 0xd8, 0xdf, 0xb7, 0x17, 0xff, 0x7f, 0x93, 0x87, 0x07, 0x80, 0x73, + 0xa0, 0x47, 0x30, 0xa1, 0x47, 0x73, 0xa0, 0x07, 0x30, 0x82, 0x80, 0x41, 0x11, 0x3e, 0xc6, 0xb7, + 0x07, 0xfa, 0xa7, 0xdf, 0xe3, 0x6f, 0x1f, 0x27, 0xc4, 0xb4, 0x23, 0x41, 0x8d, 0xb3, 0x9a, 0xf0, + 0xe8, 0x23, 0x52, 0xdf, 0xf5, 0x4e, 0x5a, 0x24, 0x0c, 0xbd, 0x11, 0xdd, 0x0f, 0xce, 0x1c, 0xd8, + 0xa8, 0x15, 0x28, 0x39, 0x40, 0x00, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, + 0x20, 0x30, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x80, 0x00, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, + 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x00, 0x04, 0x73, 0xb0, + 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, + 0x00, 0x20, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x05, 0x65, + 0x6f, 0x10, 0xa0, 0x54, 0x05, 0x65, 0x6f, 0x10, 0x00, 0x55, 0x01, 0x11, 0x22, 0xcc, 0x4a, 0xc8, + 0x4e, 0xc6, 0x06, 0xce, 0x26, 0xca, 0x52, 0xc4, 0x56, 0xc2, 0x9d, 0x47, 0x2a, 0x84, 0xae, 0x89, + 0x32, 0x89, 0x63, 0xd4, 0xc7, 0x00, 0xef, 0xd0, 0x2f, 0xae, 0xef, 0xf0, 0x5f, 0xfd, 0xb7, 0x07, + 0x01, 0x07, 0x18, 0x40, 0xdc, 0x43, 0x93, 0x06, 0xf0, 0x0f, 0x63, 0x05, 0xd7, 0x00, 0xf1, 0x9b, + 0x0d, 0x8b, 0xd9, 0x8f, 0x13, 0xf7, 0xb7, 0xff, 0x83, 0x47, 0x44, 0x00, 0x81, 0x44, 0x31, 0x4a, + 0x8a, 0x07, 0x91, 0x8b, 0xd9, 0x8f, 0x37, 0x07, 0x01, 0x07, 0x5c, 0xc3, 0xb7, 0x1a, 0x01, 0x07, + 0x63, 0xcf, 0x24, 0x03, 0x14, 0x40, 0x05, 0x47, 0xad, 0x47, 0x63, 0x9e, 0xe6, 0x00, 0x83, 0x46, + 0x44, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0xbd, 0x47, 0x63, 0x97, 0xe6, 0x00, 0x14, 0x44, 0x37, 0x37, + 0x20, 0x00, 0x23, 0x22, 0xd7, 0xf8, 0xf2, 0x40, 0x62, 0x44, 0x37, 0x07, 0xfa, 0xf7, 0xe0, 0x1d, + 0x32, 0x97, 0x3d, 0xae, 0x6c, 0x96, 0xc3, 0xf5, 0x4e, 0x47, 0x73, 0x53, 0x67, 0x9e, 0x5f, 0xfe, + 0x2b, 0xa4, 0x54, 0x4f, 0x7e, 0x9e, 0x92, 0x99, 0xe2, 0x41, 0xf2, 0x1f, 0xa2, 0x00, 0x3a, 0x01, + 0x07, 0x5c, 0xc7, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, + 0x80, 0xb3, 0x85, 0x44, 0x03, 0x13, 0x95, 0x44, 0x00, 0x31, 0x46, 0x56, 0x95, 0x85, 0x04, 0xce, + 0x95, 0xef, 0xf0, 0xcf, 0x81, 0x7d, 0xb7, 0x1d, 0x71, 0x3e, 0xda, 0xb7, 0x07, 0x01, 0x07, 0xa2, + 0xc6, 0x80, 0x47, 0x86, 0xce, 0x96, 0xcc, 0x9a, 0xca, 0x9e, 0xc8, 0xaa, 0xc4, 0xae, 0xc2, 0xb2, + 0xc0, 0x36, 0xde, 0x3a, 0xdc, 0x42, 0xd8, 0x46, 0xd6, 0x72, 0xd4, 0x76, 0xd2, 0x7a, 0xd0, 0x7e, + 0xce, 0x93, 0x77, 0xb4, 0x00, 0x95, 0xc7, 0xb7, 0x07, 0x00, 0x40, 0x73, 0xb0, 0x47, 0x30, 0x37, + 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0xa2, 0x86, 0x13, 0x06, 0x06, + 0x6a, 0x93, 0x85, 0x85, 0x6a, 0x13, 0x05, 0x45, 0x64, 0xef, 0xe0, 0xbf, 0x87, 0xef, 0xd0, 0xbf, + 0x8a, 0x93, 0x77, 0x44, 0x00, 0x99, 0xcf, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf8, 0x91, + 0xcb, 0x6c, 0x00, 0x28, 0x00, 0x82, 0x97, 0x22, 0x47, 0xb7, 0x07, 0x01, 0x07, 0x98, 0xcb, 0x32, + 0x47, 0xd8, 0xcb, 0xb7, 0x07, 0x01, 0x07, 0x80, 0xc7, 0x36, 0x44, 0xf6, 0x40, 0xe6, 0x42, 0x56, + 0x43, 0xc6, 0x43, 0x26, 0x45, 0x96, 0x45, 0x06, 0x46, 0xf2, 0x56, 0x62, 0x57, 0xd2, 0x57, 0x42, + 0x58, 0xb2, 0x58, 0x22, 0x5e, 0x92, 0x5e, 0x02, 0x5f, 0xf2, 0x4f, 0x25, 0x61, 0x73, 0x00, 0x20, + 0x30, 0xb7, 0x07, 0x02, 0x04, 0xdc, 0x47, 0xfa, 0x19, 0x45, 0xed, 0xe7, 0x3e, 0x51, 0x13, 0x28, + 0x15, 0x3d, 0x26, 0x00, 0x90, 0x1d, 0xbc, 0x68, 0xc7, 0x3d, 0x17, 0x7c, 0x65, 0xa8, 0x59, 0x68, + 0xa1, 0x7f, 0x10, 0xaf, 0xb6, 0xd3, 0x94, 0xba, 0xd8, 0x3a, 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, + 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x13, 0x05, 0x00, 0x08, 0x6f, 0x10, 0x40, 0x3d, + 0x13, 0x05, 0x00, 0x08, 0x6f, 0x10, 0x80, 0x3d, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, + 0x93, 0x07, 0xd0, 0x79, 0x37, 0x04, 0x02, 0x04, 0x5c, 0xc4, 0x85, 0x44, 0x95, 0x65, 0x37, 0x35, + 0x10, 0x00, 0x04, 0xc4, 0x93, 0x85, 0x05, 0xe2, 0x13, 0x05, 0x25, 0x6d, 0xef, 0xe0, 0x7f, 0xca, + 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x13, 0xf5, 0x02, 0x54, 0x44, 0x63, 0x82, 0x96, 0x02, 0x37, 0x56, + 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x6a, 0x93, 0x85, + 0x45, 0x6b, 0x13, 0x05, 0x05, 0x62, 0xef, 0xe0, 0x0f, 0xfb, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, + 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xdf, 0xf8, + 0xb2, 0x40, 0xb7, 0x07, 0x02, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, + 0x05, 0x45, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xef, 0xe0, 0x3f, 0xbf, 0xb7, 0x37, 0x20, 0x00, + 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa4, 0xe7, 0xf8, 0x89, 0x46, 0x37, 0x07, 0x02, 0x02, 0x54, 0xc7, + 0x13, 0x84, 0x87, 0xf8, 0x93, 0x04, 0x50, 0x05, 0xef, 0xe0, 0x9f, 0xc2, 0x1c, 0x40, 0xe3, 0x9d, + 0x97, 0xfe, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x02, 0x02, + 0xc8, 0xcb, 0xfa, 0x86, 0xb6, 0x29, 0x76, 0xdd, 0x40, 0xe6, 0xef, 0xde, 0x66, 0x81, 0xc3, 0xea, + 0x0c, 0xbb, 0xf7, 0xf2, 0x63, 0xe0, 0xc8, 0x05, 0xc7, 0x20, 0xaa, 0xde, 0x27, 0xdb, 0x4f, 0x80, + 0x0b, 0xc1, 0x21, 0xb0, 0x3b, 0x05, 0x47, 0xd8, 0xc7, 0xd8, 0x53, 0x69, 0x8f, 0x63, 0x1e, 0xa7, + 0x00, 0xd4, 0x57, 0x7d, 0x55, 0xf9, 0x8e, 0x91, 0xea, 0x94, 0x57, 0x75, 0x8f, 0x19, 0xe7, 0x88, + 0x47, 0x05, 0x89, 0x33, 0x05, 0xa0, 0x40, 0x82, 0x80, 0x7d, 0x55, 0x82, 0x80, 0x41, 0x45, 0x6f, + 0x10, 0x00, 0x2f, 0x41, 0x45, 0x6f, 0x10, 0xe0, 0x2d, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, 0x2a, + 0xc6, 0xef, 0xf0, 0x3f, 0xff, 0x13, 0x07, 0x50, 0x05, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0xe7, + 0xf8, 0x37, 0x04, 0x02, 0x02, 0xa1, 0x47, 0x5c, 0xc4, 0x32, 0x45, 0x85, 0x47, 0x1c, 0xc8, 0x93, + 0x07, 0x10, 0x40, 0x5c, 0xc0, 0xef, 0xf0, 0xbf, 0xf9, 0xef, 0xf0, 0x9f, 0xf5, 0x23, 0x22, 0x04, + 0x00, 0x62, 0x44, 0xf2, 0x40, 0x05, 0x61, 0x6f, 0xf0, 0x7f, 0xfb, 0x41, 0x11, 0x3a, 0xc6, 0x37, + 0x07, 0x02, 0x02, 0x3e, 0xc4, 0x1c, 0x47, 0x1c, 0xc7, 0x85, 0x8b, 0x99, 0xc7, 0xb7, 0x37, 0x20, + 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa4, 0xe7, 0xf8, 0x32, 0x47, 0xa2, 0x47, 0x41, 0x01, 0x73, + 0x00, 0x20, 0x30, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0xc7, 0xf8, 0x82, 0x80, 0x41, 0x11, 0x22, + 0xc4, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xd0, 0x6f, 0x81, 0x89, + 0x67, 0x63, 0x64, 0xf4, 0x00, 0xef, 0xd0, 0xcf, 0x80, 0x37, 0x27, 0x00, 0x06, 0x85, 0x46, 0x09, + 0x46, 0x1c, 0x47, 0x9d, 0x8b, 0x63, 0x86, 0xd7, 0x00, 0x1c, 0x47, 0x9d, 0x8b, 0xfa, 0x97, 0x2b, + 0xd6, 0x83, 0xbc, 0x49, 0xb7, 0xeb, 0x87, 0x28, 0x24, 0x67, 0x9d, 0x8e, 0x0d, 0x2d, 0xf9, 0xde, + 0x55, 0xeb, 0x7a, 0x15, 0xf8, 0x63, 0x7d, 0x4e, 0xd6, 0x23, 0xe1, 0xc4, 0x4a, 0x8b, 0x88, 0x3c, + 0xe3, 0x9a, 0xc7, 0xfe, 0x37, 0x05, 0x00, 0x06, 0x2a, 0x94, 0x08, 0x40, 0xb2, 0x40, 0x22, 0x44, + 0x41, 0x01, 0x82, 0x80, 0x05, 0x65, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x41, 0x11, + 0x13, 0x05, 0x05, 0x80, 0x23, 0xa6, 0xe7, 0xf8, 0x06, 0xc6, 0xef, 0x10, 0xc0, 0x20, 0xb7, 0x27, + 0x00, 0x06, 0x9c, 0x47, 0x05, 0x47, 0x9d, 0x8b, 0xfd, 0x17, 0x63, 0x7b, 0xf7, 0x00, 0x37, 0x55, + 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0x85, 0x6b, 0xef, 0xe0, 0xaf, 0xe9, 0xef, 0xc0, 0x9f, 0xfa, + 0xb7, 0x07, 0x46, 0x00, 0xb2, 0x40, 0x37, 0x27, 0x00, 0x06, 0x85, 0x07, 0x5c, 0xcf, 0x85, 0x47, + 0x5c, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x37, 0x27, 0x00, 0x06, 0x1c, 0x47, 0x85, 0x46, 0x9d, 0x8b, + 0x63, 0x8a, 0xd7, 0x00, 0x14, 0xcb, 0xb7, 0x26, 0x00, 0x06, 0x05, 0x47, 0x9c, 0x46, 0x9d, 0x8b, + 0xe3, 0x9e, 0xe7, 0xfe, 0xb7, 0x27, 0x00, 0x06, 0x09, 0x47, 0x05, 0x65, 0x98, 0xcb, 0x13, 0x05, + 0x05, 0x80, 0x6f, 0x10, 0x00, 0x1b, 0x05, 0x65, 0x41, 0x11, 0x13, 0x05, 0x05, 0x80, 0x06, 0xc6, + 0xef, 0x10, 0x60, 0x19, 0xb2, 0x40, 0xb7, 0x27, 0x00, 0x06, 0x21, 0x47, 0x98, 0xcb, 0x41, 0x01, + 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0xaa, 0x84, 0xef, 0xf0, 0x5f, 0xf1, + 0x2a, 0x84, 0x49, 0x22, 0x13, 0x75, 0xf5, 0x0f, 0xef, 0xe0, 0x1f, 0xa6, 0x26, 0x85, 0xef, 0xf0, + 0x3f, 0xf0, 0x63, 0x05, 0xa4, 0x00, 0xef, 0xc0, 0xfa, 0xcd, 0x41, 0x9d, 0xf9, 0xdf, 0xe1, 0xa5, + 0x5e, 0xff, 0xb2, 0x14, 0x2c, 0x6a, 0x99, 0xdd, 0x93, 0x5e, 0x2f, 0x59, 0xea, 0x92, 0x3c, 0xca, + 0x18, 0xcf, 0xd8, 0xf6, 0x06, 0x4c, 0x14, 0xf0, 0x52, 0x60, 0x3d, 0xff, 0xf1, 0x01, 0x45, 0xb2, + 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, + 0xd0, 0x4e, 0xce, 0x06, 0xd6, 0x52, 0xcc, 0xaa, 0x89, 0x2e, 0x89, 0x93, 0x74, 0xc6, 0xff, 0x01, + 0x44, 0x33, 0x8a, 0x89, 0x00, 0x33, 0x05, 0x89, 0x00, 0x63, 0x1a, 0x94, 0x00, 0xb2, 0x50, 0x22, + 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0xef, 0xf0, 0x9f, + 0xf9, 0x2a, 0xc6, 0x11, 0x46, 0x6c, 0x00, 0x52, 0x85, 0xef, 0x10, 0x50, 0x1d, 0x11, 0x04, 0xc9, + 0xbf, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x1f, 0xf8, 0x2a, 0x87, 0x85, 0x46, 0x01, 0x45, 0x89, + 0x45, 0x01, 0xe7, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x93, 0x77, 0xf7, 0x00, 0x01, 0x46, 0x81, + 0xef, 0x63, 0xd3, 0xc5, 0x00, 0xb6, 0x87, 0x5d, 0x8d, 0x86, 0x06, 0x13, 0x75, 0xf5, 0x0f, 0x93, + 0xf6, 0xf6, 0x0f, 0x11, 0x83, 0xf1, 0xbf, 0x13, 0xf8, 0x17, 0x00, 0x85, 0x83, 0x42, 0x96, 0x93, + 0xf7, 0xf7, 0x0f, 0xf1, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x77, 0x35, + 0x00, 0x2a, 0x84, 0xae, 0x84, 0x99, 0xc3, 0xef, 0xc0, 0x1f, 0xe7, 0x89, 0x67, 0x63, 0x64, 0xf4, + 0x00, 0xef, 0xc0, 0x7f, 0xe6, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa6, 0xe7, + 0xf8, 0xb7, 0x27, 0x00, 0x06, 0x84, 0xcf, 0xc0, 0xcb, 0x22, 0x44, 0xb2, 0x40, 0x92, 0x44, 0x11, + 0x47, 0x98, 0xcb, 0xfa, 0xd4, 0xee, 0x37, 0x60, 0x30, 0x32, 0xaa, 0xc3, 0xdc, 0xd8, 0xd4, 0x0d, + 0x91, 0x28, 0xe5, 0x75, 0x0d, 0x3c, 0x6c, 0x96, 0xdc, 0xd9, 0xac, 0xaa, 0x0d, 0x26, 0x5f, 0xce, + 0xa6, 0x27, 0xf2, 0xf0, 0x38, 0x3e, 0x89, 0x65, 0x37, 0x45, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, + 0x13, 0x05, 0xe5, 0x84, 0x41, 0x01, 0x6f, 0xe0, 0xdf, 0xa4, 0x39, 0x71, 0x3a, 0xce, 0x37, 0x27, + 0x00, 0x06, 0x3e, 0xcc, 0x1c, 0x47, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, + 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, + 0x7e, 0xc0, 0xa1, 0x8b, 0x85, 0xcf, 0xa1, 0x47, 0x1c, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, + 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf8, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, + 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, + 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x55, 0x10, 0x00, + 0x85, 0x45, 0x13, 0x05, 0x85, 0x6b, 0xef, 0xe0, 0x2f, 0xcb, 0xef, 0xd0, 0xcf, 0xc6, 0xe1, 0xb7, + 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa8, 0xa7, 0xf8, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, + 0x07, 0xf9, 0x88, 0x43, 0x37, 0x67, 0x19, 0x00, 0x13, 0x07, 0xd7, 0x60, 0x33, 0x05, 0xe5, 0x02, + 0x37, 0xf7, 0x6e, 0x3c, 0x13, 0x07, 0xf7, 0x35, 0x3a, 0x95, 0x88, 0xc3, 0x82, 0x80, 0xb7, 0x37, + 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf9, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0x87, 0xf9, 0x9c, 0x4f, + 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0xc7, 0xf9, 0xfa, 0xa1, + 0xb7, 0xd6, 0xda, 0x57, 0x0d, 0x3a, 0x43, 0xed, 0x10, 0x23, 0x8e, 0xcd, 0x34, 0xf6, 0x49, 0x1d, + 0xa6, 0x0d, 0xdd, 0xc1, 0xcb, 0xc4, 0xde, 0x54, 0x9e, 0x41, 0x60, 0xf8, 0x40, 0x8d, 0x56, 0x10, + 0x3f, 0x63, 0x84, 0xe7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xfd, 0x77, 0xfd, 0x17, 0xe9, + 0x8f, 0xb7, 0x26, 0x00, 0x08, 0x2e, 0x87, 0xb2, 0x85, 0x63, 0x94, 0xd7, 0x02, 0xb7, 0x37, 0x20, + 0x00, 0x23, 0xaa, 0xa7, 0xf8, 0xb7, 0x37, 0x20, 0x00, 0x37, 0x45, 0x10, 0x00, 0x23, 0xae, 0xe7, + 0xf8, 0x13, 0x05, 0x05, 0xaf, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0xe7, 0xf8, 0x6f, 0xe0, 0x5f, + 0x87, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0xa7, 0xf8, 0xb7, + 0x37, 0x20, 0x00, 0x37, 0x45, 0x10, 0x00, 0x23, 0xae, 0x07, 0xf8, 0x13, 0x07, 0x00, 0x10, 0xb7, + 0x37, 0x20, 0x00, 0x93, 0x05, 0x80, 0x3e, 0x13, 0x05, 0x05, 0xaf, 0x23, 0xac, 0xe7, 0xf8, 0x6f, + 0xe0, 0x3f, 0x84, 0x37, 0x07, 0x01, 0x02, 0x5c, 0x43, 0xb7, 0x06, 0x05, 0x00, 0xd5, 0x8f, 0x5c, + 0xc3, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0xb7, 0x27, 0x00, 0x08, 0x37, + 0x05, 0x08, 0x00, 0x63, 0x14, 0xf4, 0x00, 0x37, 0x05, 0x04, 0x00, 0xef, 0x00, 0x50, 0x71, 0x5c, + 0x5c, 0x22, 0x85, 0xb2, 0x40, 0x93, 0xe7, 0x37, 0x00, 0x5c, 0xdc, 0x23, 0x2c, 0x04, 0x00, 0x22, + 0x44, 0x41, 0x01, 0x6f, 0xf0, 0x5f, 0xf9, 0x58, 0x5d, 0xaa, 0x87, 0x75, 0x9b, 0x58, 0xdd, 0x37, + 0x27, 0x00, 0x08, 0x37, 0x05, 0x04, 0x00, 0x63, 0x84, 0xe7, 0x00, 0x37, 0x05, 0x08, 0x00, 0x6f, + 0x00, 0xd0, 0x6e, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0xfa, 0x6a, 0x4e, 0x1e, 0xbd, 0x88, 0xd6, + 0xc1, 0x81, 0x57, 0x43, 0x8c, 0x9e, 0xc7, 0xe8, 0x48, 0x8b, 0x81, 0x91, 0x86, 0xca, 0xc6, 0x9d, + 0xba, 0xe4, 0x37, 0x8f, 0x6a, 0x81, 0xae, 0xa5, 0x37, 0xff, 0xe8, 0x3f, 0x4a, 0xd0, 0x06, 0xd6, + 0x4e, 0xce, 0x52, 0xcc, 0x56, 0xca, 0x2a, 0x89, 0xae, 0x84, 0x32, 0x84, 0x99, 0xe1, 0xef, 0xc0, + 0x3f, 0xc8, 0x13, 0x0a, 0xa0, 0x0a, 0x91, 0x4a, 0x05, 0xe4, 0x83, 0x27, 0x89, 0x01, 0x37, 0x07, + 0x11, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x99, 0xc3, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x50, + 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0xd2, 0x4a, 0x45, 0x61, 0x82, 0x80, + 0x13, 0x06, 0x80, 0x3e, 0x85, 0x45, 0x4a, 0x85, 0xef, 0xf0, 0x7f, 0xee, 0xe3, 0x1f, 0x45, 0xfd, + 0x83, 0x27, 0x49, 0x02, 0xa2, 0x89, 0x3e, 0xc6, 0x63, 0xf3, 0x8a, 0x00, 0x91, 0x49, 0x26, 0x85, + 0x4e, 0x86, 0x6c, 0x00, 0xef, 0x10, 0x20, 0x73, 0xce, 0x94, 0x33, 0x04, 0x34, 0x41, 0x6d, 0xb7, + 0x41, 0x11, 0x37, 0x05, 0x02, 0x00, 0x06, 0xc6, 0xef, 0x00, 0xb0, 0x65, 0xb2, 0x40, 0xb7, 0x17, + 0x00, 0x08, 0x37, 0x07, 0x07, 0x00, 0x98, 0xd3, 0x13, 0x05, 0x40, 0x1f, 0x41, 0x01, 0x6f, 0xe0, + 0xef, 0xee, 0xb7, 0x17, 0x00, 0x08, 0x23, 0xa0, 0x07, 0x02, 0x37, 0x05, 0x02, 0x00, 0x6f, 0x00, + 0x10, 0x64, 0x39, 0x71, 0x3e, 0xcc, 0xb7, 0x17, 0x00, 0x08, 0x3a, 0xce, 0x98, 0x57, 0x06, 0xde, + 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, + 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0x05, 0x8b, 0x05, 0xcb, 0x98, 0x57, + 0x13, 0x67, 0x17, 0x00, 0xfa, 0xf9, 0xc6, 0xcf, 0x87, 0x82, 0xf6, 0x72, 0x87, 0xe8, 0xae, 0x19, + 0x50, 0x52, 0x4c, 0x9c, 0x8a, 0x44, 0x26, 0x36, 0xcc, 0xdf, 0xa9, 0xcf, 0x8d, 0xe5, 0x78, 0x21, + 0x02, 0x35, 0xa0, 0x9b, 0x58, 0xc0, 0x40, 0x98, 0xd7, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, + 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, + 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x98, + 0x57, 0x09, 0x8b, 0x09, 0xc7, 0x98, 0x57, 0x13, 0x67, 0x27, 0x00, 0xf1, 0xb7, 0x98, 0x57, 0x11, + 0x8b, 0x09, 0xc7, 0x98, 0x57, 0x13, 0x67, 0x47, 0x00, 0x7d, 0xbf, 0xb7, 0x07, 0x00, 0x01, 0x73, + 0xb0, 0x47, 0x30, 0xef, 0xd0, 0xcf, 0xa1, 0x4d, 0xbf, 0x37, 0x07, 0x00, 0x02, 0x5c, 0x4f, 0xb7, + 0x36, 0x20, 0x00, 0x13, 0xf6, 0x77, 0x00, 0xe1, 0x9b, 0x23, 0xa0, 0xc6, 0xfa, 0x93, 0xe7, 0x47, + 0x00, 0x5c, 0xcf, 0x1c, 0x4f, 0xf9, 0x9b, 0x1c, 0xcf, 0x82, 0x80, 0x41, 0x11, 0x26, 0xc2, 0xb7, + 0x04, 0x00, 0x02, 0x22, 0xc4, 0xc0, 0x4c, 0x9c, 0x4c, 0x06, 0xc6, 0x13, 0x05, 0x80, 0x07, 0x93, + 0xe7, 0x17, 0x00, 0x9c, 0xcc, 0xef, 0xe0, 0xaf, 0xe1, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, + 0xfa, 0x61, 0x98, 0xb2, 0x40, 0x5d, 0x8c, 0xc0, 0xcc, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, + 0x80, 0x13, 0x17, 0x05, 0x01, 0x93, 0x17, 0x85, 0x01, 0xba, 0x97, 0x13, 0x17, 0x85, 0x00, 0xba, + 0x97, 0x3e, 0x95, 0xb7, 0x07, 0x00, 0x04, 0x88, 0xd3, 0xc8, 0xd3, 0x88, 0xd7, 0xc8, 0xd7, 0x88, + 0xdb, 0xc8, 0xdb, 0x88, 0xdf, 0xc8, 0xdf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0xfa, + 0xf6, 0xaf, 0xe3, 0x8b, 0x16, 0x97, 0x79, 0xba, 0x00, 0xb6, 0x72, 0xe3, 0xd3, 0x75, 0x00, 0x35, + 0x94, 0xbe, 0xa6, 0x3e, 0x52, 0x9a, 0x9f, 0x00, 0x3a, 0xdc, 0x64, 0x32, 0xfd, 0xa3, 0xd7, 0x9d, + 0x98, 0x41, 0x00, 0x08, 0x98, 0xd3, 0x23, 0xa2, 0x07, 0x02, 0x0e, 0x05, 0x23, 0xa4, 0x07, 0x02, + 0x42, 0x05, 0x23, 0xa6, 0x07, 0x02, 0x41, 0x81, 0x23, 0xa8, 0x07, 0x02, 0x13, 0x17, 0x85, 0x00, + 0xb7, 0x06, 0xff, 0x00, 0x23, 0xaa, 0x07, 0x02, 0x75, 0x8f, 0x62, 0x05, 0x23, 0xac, 0x07, 0x02, + 0x3a, 0x95, 0xc8, 0xdf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x00, 0x08, 0x98, 0xd3, + 0x23, 0xa2, 0x07, 0x02, 0x23, 0xa4, 0x07, 0x02, 0x23, 0xa6, 0x07, 0x02, 0x23, 0xa8, 0x07, 0x02, + 0x23, 0xaa, 0x07, 0x02, 0x23, 0xac, 0x07, 0x02, 0x23, 0xae, 0x07, 0x02, 0x82, 0x80, 0xb7, 0x37, + 0x20, 0x00, 0x03, 0xa5, 0x47, 0xea, 0x82, 0x80, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, + 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0x6f, 0xe0, 0x3f, 0x83, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, + 0x50, 0x05, 0x23, 0xa2, 0xe7, 0xea, 0xb7, 0x07, 0x00, 0x04, 0xc8, 0xc3, 0x13, 0x07, 0x90, 0x02, + 0x85, 0x65, 0x37, 0x45, 0x10, 0x00, 0x98, 0xc7, 0x93, 0x85, 0x85, 0x38, 0x13, 0x05, 0x45, 0xdf, + 0x6f, 0xe0, 0xaf, 0xd8, 0x41, 0x11, 0x22, 0xc4, 0x01, 0x45, 0x37, 0x34, 0x20, 0x00, 0x06, 0xc6, + 0x13, 0x04, 0x44, 0xe9, 0xef, 0xf0, 0x1f, 0xf2, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, + 0xef, 0xf0, 0xbf, 0xfb, 0x48, 0x44, 0xb7, 0x07, 0x02, 0x00, 0x95, 0x07, 0x7e, 0x05, 0x5d, 0x8d, + 0xef, 0xf0, 0xbf, 0xfa, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0xfa, 0x4d, 0xfd, 0x84, 0x4a, 0xaa, + 0xf8, 0x55, 0xcd, 0x6c, 0x63, 0x8f, 0x5e, 0x04, 0xd6, 0xd4, 0x86, 0x21, 0xdf, 0xf3, 0xf9, 0x31, + 0x08, 0x50, 0x8f, 0x7c, 0x8c, 0xe7, 0x33, 0xc8, 0x5f, 0x53, 0x00, 0x70, 0x42, 0x05, 0x05, 0xef, + 0xf0, 0xff, 0xf9, 0x48, 0x44, 0xb7, 0x07, 0x00, 0x10, 0x99, 0x07, 0x7e, 0x05, 0x5d, 0x8d, 0xef, + 0xf0, 0xff, 0xf8, 0x48, 0x44, 0xb7, 0x07, 0x01, 0x10, 0x99, 0x07, 0x7e, 0x05, 0x5d, 0x8d, 0xef, + 0xf0, 0xff, 0xf7, 0x22, 0x44, 0xb2, 0x40, 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0xf7, 0x7d, + 0x47, 0x63, 0x7e, 0xb7, 0x04, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x13, + 0x05, 0x05, 0x02, 0x6f, 0xe0, 0x8f, 0xf8, 0xb3, 0x06, 0xf5, 0x00, 0x83, 0xc6, 0x06, 0x00, 0x33, + 0x07, 0xf1, 0x00, 0x85, 0x07, 0x23, 0x00, 0xd7, 0x00, 0xe3, 0x97, 0xf5, 0xfe, 0x18, 0x10, 0x93, + 0x87, 0x15, 0x00, 0xba, 0x95, 0x13, 0x07, 0x00, 0xf8, 0x23, 0x80, 0xe5, 0xfe, 0x13, 0x07, 0x00, + 0x02, 0x63, 0x92, 0xe7, 0x02, 0x37, 0x05, 0x00, 0x04, 0x8a, 0x85, 0x13, 0x06, 0x00, 0x02, 0x13, + 0x05, 0x05, 0x02, 0xef, 0xe0, 0x8f, 0xf4, 0xb2, 0x50, 0x45, 0x61, 0x82, 0x80, 0x79, 0x71, 0x06, + 0xd6, 0x81, 0x47, 0xd9, 0xb7, 0xb3, 0x06, 0xf1, 0x00, 0x23, 0x80, 0x06, 0x00, 0x85, 0x07, 0xc9, + 0xbf, 0x37, 0x55, 0x10, 0x00, 0x01, 0x11, 0x13, 0x05, 0x45, 0x6c, 0x06, 0xce, 0x22, 0xcc, 0x26, + 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x37, 0x34, 0x20, 0x00, 0xef, 0xf0, 0x1f, 0xed, 0x93, + 0x07, 0x44, 0xe9, 0xc8, 0x47, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x3f, 0xed, 0x93, + 0x07, 0xa0, 0x0a, 0x63, 0x10, 0xfa, 0x80, 0xd8, 0xd2, 0x68, 0x15, 0x02, 0x76, 0x98, 0xb9, 0x89, + 0x46, 0x0c, 0xd4, 0xef, 0xd3, 0xde, 0x43, 0x99, 0xa1, 0x4e, 0x6d, 0x1b, 0xd9, 0x7f, 0x6a, 0xfb, + 0x52, 0x60, 0x97, 0x21, 0x21, 0x71, 0x48, 0x43, 0xf5, 0x2e, 0xaa, 0x84, 0x13, 0x05, 0x00, 0x02, + 0xef, 0xf0, 0x3f, 0xe4, 0x13, 0x04, 0x44, 0xe9, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, + 0xef, 0xf0, 0x1f, 0xeb, 0xaa, 0x89, 0x63, 0x10, 0x95, 0x2c, 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, + 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0xbf, 0xe9, 0xaa, 0x84, 0x63, 0x15, 0x35, 0x2b, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x9f, 0xe8, 0xaa, 0x89, 0x63, 0x1c, + 0x95, 0x28, 0x1c, 0x40, 0x48, 0x44, 0x37, 0x0a, 0x00, 0x04, 0x83, 0xc7, 0x07, 0x00, 0x7e, 0x05, + 0x13, 0x65, 0x15, 0x00, 0x93, 0xe7, 0x07, 0x20, 0x23, 0x2c, 0xfa, 0x00, 0xef, 0xf0, 0x5f, 0xe6, + 0xaa, 0x84, 0x63, 0x1a, 0x35, 0x27, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, + 0x3f, 0xe5, 0x2a, 0x89, 0x63, 0x11, 0x95, 0x26, 0xef, 0xf0, 0x5f, 0xe0, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xdf, 0xe3, 0xaa, 0x84, 0x63, 0x16, 0x25, 0x25, 0x13, 0x05, + 0x00, 0x04, 0xef, 0xf0, 0x1f, 0xdb, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x17, 0xef, 0xf0, 0xff, 0xe1, 0x2a, 0x89, 0x63, 0x17, 0x95, 0x22, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xdf, 0xe0, 0xaa, 0x84, 0x63, 0x1e, 0x25, 0x21, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xbf, 0xdf, 0x63, 0x16, 0x95, 0x20, 0x48, 0x44, + 0xfa, 0x15, 0x72, 0x62, 0x71, 0x13, 0x81, 0x5b, 0x9e, 0xe3, 0xd8, 0x52, 0xf3, 0xef, 0x12, 0x00, + 0x02, 0x6d, 0xaf, 0x13, 0x6a, 0xd2, 0x2d, 0xb4, 0x63, 0x23, 0x41, 0x6e, 0x23, 0x57, 0x68, 0xc2, + 0x7f, 0x20, 0x44, 0x93, 0x07, 0x00, 0x10, 0x23, 0x2c, 0xfa, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x15, + 0x00, 0xef, 0xf0, 0x3f, 0xde, 0x93, 0x07, 0xa0, 0x0a, 0xaa, 0x84, 0x63, 0x17, 0xf5, 0x1e, 0x48, + 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x9f, 0xdc, 0xaa, + 0x89, 0x63, 0x1c, 0x95, 0x1c, 0xef, 0xf0, 0xbf, 0xd7, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, + 0x07, 0xef, 0xf0, 0x3f, 0xdb, 0xaa, 0x84, 0x63, 0x11, 0x35, 0x1d, 0x13, 0x05, 0x00, 0x04, 0xef, + 0xf0, 0x7f, 0xd2, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, + 0xf0, 0x5f, 0xd9, 0xaa, 0x89, 0x63, 0x12, 0x95, 0x1a, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, + 0x00, 0xef, 0xf0, 0x3f, 0xd8, 0xaa, 0x84, 0x63, 0x19, 0x35, 0x19, 0x48, 0x44, 0x7e, 0x05, 0x13, + 0x65, 0x05, 0x02, 0xef, 0xf0, 0x1f, 0xd7, 0xaa, 0x89, 0x63, 0x10, 0x95, 0x18, 0x08, 0x40, 0x05, + 0x05, 0xef, 0xf0, 0x1f, 0xd5, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x7f, + 0xd5, 0xaa, 0x84, 0x63, 0x13, 0x35, 0x17, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, + 0xf0, 0x5f, 0xd4, 0x2a, 0x89, 0x63, 0x1a, 0x95, 0x14, 0xef, 0xf0, 0x7f, 0xcf, 0x48, 0x44, 0x7e, + 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xff, 0xd2, 0xaa, 0x84, 0x63, 0x1f, 0x25, 0x13, 0x13, + 0x05, 0x00, 0x04, 0xef, 0xf0, 0x3f, 0xca, 0x48, 0x44, 0x23, 0x20, 0xfa, 0xea, 0x55, 0x06, 0x58, + 0x77, 0x50, 0xaa, 0x9d, 0x15, 0x27, 0x63, 0x2b, 0x1e, 0xa2, 0xab, 0x09, 0x47, 0xd8, 0x92, 0x1e, + 0xa6, 0xd0, 0x0a, 0xfa, 0x58, 0x67, 0xf7, 0x90, 0x84, 0xd0, 0x2a, 0x2b, 0xf8, 0x44, 0x0a, 0x02, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x1f, 0xd1, 0x63, 0x11, 0x95, 0x12, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x1f, 0xd0, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, + 0x63, 0x16, 0xf5, 0x10, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xbf, 0xce, + 0xaa, 0x84, 0x63, 0x1d, 0x25, 0x0f, 0x13, 0x05, 0x10, 0x02, 0xef, 0xf0, 0xff, 0xc5, 0x1c, 0x40, + 0x48, 0x44, 0x21, 0x67, 0x83, 0xc7, 0x07, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xd9, 0x8f, + 0x23, 0x20, 0xfa, 0x02, 0xef, 0xf0, 0x3f, 0xcc, 0xaa, 0x89, 0x63, 0x19, 0x95, 0x0c, 0x48, 0x44, + 0x89, 0x64, 0x8d, 0x04, 0x7e, 0x05, 0x45, 0x8d, 0xef, 0xf0, 0xff, 0xca, 0x2a, 0x89, 0x63, 0x1f, + 0x35, 0x0b, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xdf, 0xc9, 0xaa, 0x89, + 0x63, 0x16, 0x25, 0x0b, 0x08, 0x40, 0x13, 0x05, 0x15, 0x02, 0xef, 0xf0, 0xbf, 0xc7, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x1f, 0xc8, 0x2a, 0x89, 0x63, 0x18, 0x35, 0x09, + 0x48, 0x44, 0x7e, 0x05, 0x45, 0x8d, 0xef, 0xf0, 0x1f, 0xc7, 0xaa, 0x84, 0x63, 0x10, 0x25, 0x09, + 0xef, 0xf0, 0x3f, 0xc2, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0xc5, + 0x2a, 0x89, 0x63, 0x15, 0x95, 0x06, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0xff, 0xbc, 0x48, 0x44, + 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0xfa, 0x90, 0x03, 0xeb, 0x09, 0x5a, 0xe9, 0x5d, 0xd5, 0x9b, + 0xc6, 0x03, 0x55, 0x41, 0x8e, 0xe6, 0x78, 0x37, 0x05, 0x10, 0x74, 0x1a, 0x20, 0x86, 0x04, 0x8e, + 0xdd, 0x39, 0x7b, 0x7f, 0x7b, 0x4a, 0xd8, 0xd0, 0x45, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, + 0xc3, 0xaa, 0x84, 0x63, 0x16, 0x25, 0x05, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, + 0xf0, 0xbf, 0xc2, 0x63, 0x1e, 0x95, 0x02, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x52, 0xef, + 0xf0, 0xbf, 0xc1, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x14, 0xf5, 0x02, 0x08, 0x40, 0x62, 0x44, 0xf2, + 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, + 0x02, 0x93, 0x85, 0x05, 0x06, 0x13, 0x05, 0x15, 0x06, 0x05, 0x61, 0x6f, 0xe0, 0x0f, 0xbb, 0xf2, + 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x01, + 0x11, 0x4e, 0xc6, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x52, 0xc4, 0x93, 0x09, 0x00, + 0x04, 0x63, 0xeb, 0xb9, 0x08, 0x37, 0x3a, 0x20, 0x00, 0xaa, 0x84, 0x2e, 0x84, 0x13, 0x09, 0x4a, + 0xe9, 0xef, 0xf0, 0xbf, 0xc4, 0x03, 0x25, 0xc9, 0x00, 0x13, 0x0a, 0x4a, 0xe9, 0x7e, 0x05, 0x13, + 0x65, 0x05, 0x07, 0xef, 0xf0, 0x7f, 0xba, 0x13, 0x85, 0x04, 0x02, 0x63, 0x19, 0x34, 0x03, 0xaa, + 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x05, 0x05, 0x02, 0x13, 0x06, 0x00, 0x02, 0xef, 0xe0, 0xaf, + 0xbb, 0x03, 0x25, 0xc9, 0x00, 0x62, 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, + 0x4a, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0x05, 0x61, 0x6f, 0xf0, 0x1f, 0xb7, 0xfd, 0x47, 0x63, + 0xf8, 0xfa, 0xbc, 0x85, 0x10, 0x91, 0x20, 0xef, 0xcc, 0xb0, 0x91, 0x46, 0x83, 0xa9, 0xf3, 0xf1, + 0x73, 0xba, 0xc5, 0x74, 0xcd, 0xa3, 0xfe, 0xcc, 0x3c, 0x06, 0xd5, 0xb8, 0xac, 0xe8, 0x7c, 0x21, + 0xe8, 0xd2, 0xa8, 0x46, 0x87, 0x02, 0x93, 0x05, 0x04, 0xfe, 0xef, 0xf0, 0x5f, 0xbf, 0x13, 0x04, + 0x04, 0x04, 0x0e, 0x04, 0x42, 0x04, 0x41, 0x80, 0x93, 0x17, 0x84, 0x00, 0x37, 0x07, 0xff, 0x00, + 0xf9, 0x8f, 0x62, 0x04, 0x3e, 0x94, 0xb7, 0x07, 0x00, 0x04, 0x03, 0x25, 0xca, 0x00, 0xc0, 0xdf, + 0x65, 0xbf, 0x01, 0x45, 0xef, 0xf0, 0x3f, 0xa9, 0xd9, 0xbf, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, + 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, 0x37, 0x34, + 0x20, 0x00, 0x93, 0x07, 0x44, 0xe9, 0x52, 0xc4, 0x2a, 0x8a, 0xc8, 0x47, 0x56, 0xc2, 0x06, 0xce, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x30, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xae, 0x8a, 0xef, 0xf0, + 0xff, 0xaf, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x11, 0xf5, 0x12, 0xaa, 0x84, 0x13, 0x05, 0x60, 0x03, + 0xef, 0xf0, 0x7f, 0xa4, 0x13, 0x04, 0x44, 0xe9, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x45, 0x00, + 0xef, 0xf0, 0xdf, 0xad, 0x2a, 0x89, 0x63, 0x11, 0x95, 0x10, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x17, 0xef, 0xf0, 0xbf, 0xac, 0xaa, 0x84, 0x63, 0x18, 0x25, 0x0f, 0x48, 0x44, 0x09, 0x69, + 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x5f, 0xab, 0xaa, 0x89, 0x63, 0x1d, + 0x95, 0x0c, 0xd6, 0x85, 0x52, 0x85, 0xef, 0xf0, 0xdf, 0xec, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x35, 0x00, 0xef, 0xf0, 0xbf, 0xa9, 0xaa, 0x84, 0x63, 0x10, 0x35, 0x0d, 0xfa, 0xab, 0x09, 0x27, + 0x1b, 0x55, 0x5e, 0xb7, 0xc9, 0x30, 0x9f, 0x6c, 0x92, 0x16, 0x6d, 0x22, 0xa6, 0xd3, 0x01, 0xeb, + 0x38, 0xc6, 0x3e, 0x44, 0x3c, 0x37, 0xaa, 0xb3, 0x5d, 0xe2, 0x52, 0xf0, 0x6e, 0x80, 0x47, 0x48, + 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x03, 0xef, 0xf0, 0x9f, 0xa8, 0xaa, 0x89, 0x63, 0x17, 0x95, + 0x0a, 0x13, 0x05, 0xc0, 0x05, 0xef, 0xf0, 0x5f, 0x9d, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x45, + 0x00, 0xef, 0xf0, 0xff, 0xa6, 0xaa, 0x84, 0x63, 0x1a, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, 0x13, + 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xa5, 0xaa, 0x89, 0x63, 0x11, 0x95, 0x08, 0x48, 0x44, 0x7e, + 0x05, 0x13, 0x65, 0x05, 0x32, 0xef, 0xf0, 0xbf, 0xa4, 0xaa, 0x84, 0x63, 0x18, 0x35, 0x07, 0x48, + 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x9f, 0xa3, 0x63, 0x10, 0x95, 0x06, 0x48, + 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x03, 0xef, 0xf0, 0x9f, 0xa2, 0x93, 0x07, 0xa0, 0x0a, 0x2a, + 0x89, 0x63, 0x15, 0xf5, 0x04, 0x13, 0x05, 0x00, 0x06, 0xef, 0xf0, 0x9f, 0x99, 0x48, 0x44, 0x7e, + 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xbf, 0xa0, 0xaa, 0x84, 0x63, 0x18, 0x25, 0x03, 0x48, + 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x9f, 0x9f, 0x63, 0x10, 0x95, 0x02, 0x48, + 0x44, 0x62, 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x7e, + 0x05, 0x13, 0x65, 0x05, 0x02, 0x05, 0x61, 0x6f, 0xf0, 0x9f, 0x9d, 0xf2, 0x40, 0x62, 0x44, 0xd2, + 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x39, 0x71, 0x22, + 0xdc, 0x37, 0x34, 0x20, 0x00, 0x06, 0xde, 0xfa, 0x02, 0xe1, 0xc9, 0x92, 0x79, 0x5c, 0xcb, 0xdd, + 0x01, 0xb4, 0x9e, 0x82, 0x4f, 0x49, 0xb3, 0x97, 0x6d, 0x99, 0xd3, 0x06, 0xf0, 0x3c, 0xe9, 0x95, + 0x01, 0x13, 0xeb, 0xdc, 0x5c, 0x7e, 0xc0, 0x40, 0x58, 0x48, 0x4a, 0xd8, 0x26, 0xda, 0x32, 0x89, + 0x13, 0x04, 0x44, 0xe9, 0xef, 0xf0, 0xdf, 0xe8, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x40, + 0xef, 0xf0, 0x3f, 0x9a, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x0a, 0xaa, 0x84, 0x37, 0x55, + 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0xc5, 0x6b, 0xef, 0xf0, 0x9f, 0xe6, 0x85, 0x47, 0x63, 0x07, + 0xf9, 0x08, 0x48, 0x44, 0x85, 0x67, 0x93, 0x87, 0x07, 0x80, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, + 0x5f, 0x97, 0x2a, 0x89, 0x63, 0x1c, 0x95, 0x06, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, + 0x93, 0x85, 0x05, 0x04, 0x68, 0x00, 0xef, 0xe0, 0xef, 0x91, 0x48, 0x44, 0x89, 0x47, 0x23, 0x06, + 0xf1, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x20, 0xef, 0xf0, 0xbf, 0x94, 0xaa, 0x84, 0x63, 0x17, + 0x25, 0x05, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0x9f, 0x93, 0x2a, 0x89, + 0x63, 0x1e, 0x95, 0x02, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x42, 0xef, 0xf0, 0x7f, 0x92, + 0xaa, 0x84, 0x63, 0x15, 0x25, 0x03, 0x68, 0x00, 0x93, 0x05, 0x10, 0x02, 0xef, 0xf0, 0x5f, 0xdf, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x10, 0xef, 0xf0, 0xbf, 0x90, 0x63, 0x18, 0x95, 0x00, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xbf, 0x8f, 0xf2, 0x50, 0x62, 0x54, + 0xd2, 0x54, 0x42, 0x59, 0x21, 0x61, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, + 0x13, 0x04, 0xfa, 0xb9, 0xbb, 0x5f, 0xe7, 0xb7, 0x8d, 0xe1, 0xb9, 0xc7, 0x35, 0x55, 0x67, 0x8f, + 0x3b, 0xc0, 0xc1, 0x5a, 0x87, 0xd4, 0xa2, 0x90, 0x0b, 0xf8, 0x14, 0xca, 0xd0, 0x6a, 0xef, 0x0d, + 0xef, 0x3d, 0xb0, 0x30, 0x49, 0x44, 0xe9, 0x08, 0x40, 0x09, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, + 0x05, 0x15, 0x04, 0x06, 0xc6, 0xef, 0xf0, 0xff, 0xf0, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, + 0x71, 0xef, 0xf0, 0x5f, 0x8c, 0x48, 0x44, 0x22, 0x44, 0xb2, 0x40, 0x7e, 0x05, 0x13, 0x65, 0x05, + 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0x8b, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x47, 0xe9, 0x05, + 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x6f, 0xf0, 0xbf, 0xed, 0x41, 0x11, 0xb7, + 0x55, 0x10, 0x00, 0x37, 0x05, 0x00, 0x04, 0x22, 0xc4, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x45, + 0x6c, 0x13, 0x05, 0x05, 0x02, 0x37, 0x34, 0x20, 0x00, 0x06, 0xc6, 0x13, 0x04, 0x44, 0xe9, 0xef, + 0xe0, 0x4f, 0x8a, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0x86, 0x93, + 0x07, 0xa0, 0x0a, 0x63, 0x1d, 0xf5, 0x00, 0x08, 0x40, 0x22, 0x44, 0xb2, 0x40, 0x05, 0x46, 0x93, + 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xe8, 0xb2, 0x40, 0x22, + 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x44, + 0xe9, 0x48, 0x44, 0x06, 0xc6, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xbf, 0x82, 0x08, + 0x40, 0x13, 0x06, 0x00, 0x02, 0x81, 0x45, 0x13, 0x05, 0x15, 0x04, 0xef, 0x00, 0x90, 0x5c, 0x08, + 0x40, 0x09, 0x46, 0x81, 0x45, 0x13, 0x05, 0x15, 0x04, 0xef, 0xf0, 0xbf, 0xe4, 0xfa, 0x18, 0x33, + 0xd3, 0x14, 0xca, 0x58, 0x0a, 0x84, 0xb2, 0xd9, 0x9a, 0x2b, 0xb2, 0xdb, 0xf9, 0xea, 0xab, 0x07, + 0x45, 0x8e, 0x10, 0x06, 0xc1, 0x17, 0x86, 0x02, 0x2b, 0xf6, 0x28, 0x66, 0xac, 0xd9, 0x08, 0x4a, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x60, 0xef, 0xf0, 0x1f, 0x80, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x71, 0xef, 0xf0, 0x4f, 0xff, 0x01, 0x45, 0xef, 0xf0, 0x8f, 0xf4, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x2f, 0xfe, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x17, 0xef, 0xf0, 0x6f, 0xfd, 0xb2, 0x40, 0x22, 0x44, 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, + 0x98, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x11, 0x65, 0xad, 0xa9, 0x37, 0x35, 0x20, 0x00, 0x41, 0x11, + 0x51, 0x46, 0x81, 0x45, 0x13, 0x05, 0x45, 0xe9, 0x06, 0xc6, 0xef, 0x00, 0xd0, 0x55, 0xb7, 0x37, + 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x1d, 0x65, 0x23, 0xa2, 0xe7, 0xfa, 0xa9, 0x21, 0xb2, 0x40, + 0xb7, 0x07, 0x00, 0x04, 0x05, 0x47, 0x98, 0xcb, 0x41, 0x01, 0x6f, 0xf0, 0xdf, 0xfc, 0x11, 0x65, + 0x1d, 0xa9, 0x95, 0x47, 0x63, 0xec, 0xb7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, + 0x13, 0x04, 0x44, 0xe9, 0x85, 0x47, 0x5c, 0xc0, 0xb7, 0x57, 0x10, 0x00, 0x0c, 0xc4, 0x93, 0x87, + 0x87, 0x6e, 0x8a, 0x05, 0xbe, 0x95, 0x9c, 0x41, 0x06, 0xc6, 0x08, 0xc0, 0x82, 0x97, 0x08, 0x48, + 0xb2, 0x40, 0x23, 0x22, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, + 0x82, 0x80, 0xb7, 0x05, 0x00, 0x04, 0x41, 0x46, 0x93, 0x85, 0x05, 0x08, 0x6f, 0xd0, 0xff, 0xef, + 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xe9, 0xfa, 0xe7, 0x1e, 0x39, 0x42, 0x20, 0x37, 0x3f, + 0x9e, 0x0c, 0xf4, 0xe2, 0x6b, 0x43, 0x12, 0xb1, 0x85, 0x4d, 0x1e, 0xe7, 0xde, 0x66, 0x08, 0x3a, + 0xb4, 0x88, 0x45, 0x6a, 0x52, 0xdc, 0x71, 0x2b, 0xf9, 0xe0, 0x4a, 0x89, 0x47, 0x5c, 0xc3, 0x5c, + 0x47, 0x46, 0x05, 0xfe, 0x07, 0xc9, 0x8f, 0x21, 0x65, 0x15, 0x05, 0x5d, 0x8d, 0x6f, 0xf0, 0xef, + 0xf1, 0x39, 0x71, 0x4e, 0xd6, 0x5e, 0xce, 0x62, 0xcc, 0xb7, 0x0b, 0x00, 0x04, 0xb7, 0x39, 0x20, + 0x00, 0x05, 0x6c, 0x22, 0xdc, 0x26, 0xda, 0x4a, 0xd8, 0x56, 0xd2, 0x5a, 0xd0, 0x66, 0xca, 0x6a, + 0xc8, 0x06, 0xde, 0x52, 0xd4, 0x2a, 0x84, 0x2e, 0x8b, 0xb2, 0x8a, 0x81, 0x44, 0x01, 0x49, 0xc1, + 0x4c, 0x93, 0x8b, 0x0b, 0x02, 0x93, 0x89, 0x49, 0xe9, 0x09, 0x0c, 0x37, 0x3d, 0x20, 0x00, 0xb3, + 0x05, 0x9b, 0x00, 0x63, 0xe0, 0x54, 0x03, 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, 0x42, 0x59, 0xb2, + 0x59, 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, 0xd2, 0x4c, 0x42, 0x4d, 0x21, + 0x61, 0x82, 0x80, 0x33, 0x8a, 0x9a, 0x40, 0x63, 0xd3, 0x4c, 0x01, 0x41, 0x4a, 0x4a, 0x85, 0x2e, + 0xc6, 0xef, 0xe0, 0xcf, 0x9f, 0xb2, 0x45, 0x13, 0x06, 0x3a, 0x00, 0x71, 0x9a, 0x5e, 0x85, 0xef, + 0xd0, 0xbf, 0xec, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xef, + 0xe8, 0x03, 0xa5, 0xc9, 0x00, 0x93, 0x17, 0x8a, 0x01, 0x7e, 0x05, 0x5d, 0x8d, 0x13, 0x65, 0x75, + 0x00, 0xef, 0xf0, 0xaf, 0xe7, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x33, 0x65, 0x85, 0x01, 0xef, + 0xf0, 0xcf, 0xe6, 0x03, 0x27, 0x4d, 0xfa, 0x93, 0x07, 0x50, 0x05, 0x63, 0x19, 0xf7, 0x00, 0x19, + 0xc4, 0x22, 0x85, 0xfa, 0x3c, 0xae, 0x19, 0xac, 0xfb, 0xb8, 0x83, 0x52, 0x52, 0x69, 0x6e, 0x53, + 0xf0, 0x45, 0x80, 0x19, 0x4e, 0x2a, 0x14, 0x04, 0x31, 0x97, 0x11, 0x25, 0x01, 0xab, 0x18, 0x92, + 0xe0, 0xa7, 0x95, 0xef, 0xb8, 0x4b, 0x52, 0x86, 0xca, 0x85, 0xef, 0xe0, 0x4f, 0xa3, 0x41, 0x04, + 0x93, 0x07, 0x00, 0x07, 0x63, 0xe3, 0x27, 0x01, 0x41, 0x09, 0xc1, 0x04, 0x9d, 0xb7, 0x39, 0x71, + 0x4e, 0xd6, 0x5a, 0xd0, 0x5e, 0xce, 0xb7, 0x39, 0x20, 0x00, 0x37, 0x0b, 0x02, 0x00, 0x85, 0x6b, + 0x26, 0xda, 0x4a, 0xd8, 0x52, 0xd4, 0x56, 0xd2, 0x62, 0xcc, 0x6a, 0xc8, 0x6e, 0xc6, 0x06, 0xde, + 0x22, 0xdc, 0x66, 0xca, 0xaa, 0x8a, 0xae, 0x84, 0x32, 0x8a, 0x01, 0x49, 0x81, 0x4d, 0x37, 0x3c, + 0x20, 0x00, 0x41, 0x4d, 0x93, 0x89, 0x49, 0xe9, 0x1d, 0x0b, 0x93, 0x8b, 0x0b, 0x82, 0xb3, 0x8c, + 0x2a, 0x01, 0x93, 0x07, 0x4c, 0xfa, 0x63, 0x64, 0x49, 0x03, 0xf2, 0x50, 0x62, 0x54, 0x13, 0x07, + 0x50, 0x05, 0x98, 0xc3, 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, + 0xf2, 0x4b, 0x62, 0x4c, 0xd2, 0x4c, 0x42, 0x4d, 0xb2, 0x4d, 0x21, 0x61, 0x82, 0x80, 0x33, 0x04, + 0x2a, 0x41, 0x63, 0x73, 0x8d, 0x00, 0x41, 0x44, 0x6e, 0x85, 0xef, 0xe0, 0xef, 0x91, 0xb7, 0x37, + 0x20, 0x00, 0x93, 0x87, 0x47, 0xfa, 0x98, 0x43, 0x93, 0x07, 0x50, 0x05, 0x63, 0x19, 0xf7, 0x00, + 0x99, 0xc4, 0x26, 0x85, 0x22, 0x86, 0xee, 0x85, 0xef, 0xe0, 0xcf, 0x9b, 0xc1, 0x04, 0x03, 0xa5, + 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x25, 0x00, 0xef, 0xf0, 0x6f, 0xd9, 0x03, 0xa5, 0xc9, 0x00, + 0x93, 0x17, 0x84, 0x01, 0x0d, 0x04, 0x7e, 0x05, 0x5d, 0x8d, 0x33, 0x65, 0x65, 0x01, 0xfa, 0x5f, + 0xad, 0xee, 0x47, 0xf2, 0x69, 0x0f, 0x6f, 0x9e, 0xf9, 0x1a, 0x54, 0x5f, 0xf8, 0xa6, 0x61, 0xae, + 0xca, 0xc4, 0x1b, 0xcf, 0xd7, 0xfe, 0xc3, 0x77, 0x79, 0x8d, 0x99, 0x81, 0x6f, 0xb5, 0x53, 0x90, + 0x4c, 0xef, 0xf0, 0x0f, 0xd8, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x33, 0x65, 0x75, 0x01, 0xef, + 0xf0, 0x2f, 0xd7, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x76, 0xc4, 0xff, 0x93, 0x85, 0x05, 0x04, 0x66, + 0x85, 0xef, 0xd0, 0x3f, 0xd2, 0x93, 0x07, 0x00, 0x06, 0x63, 0xe3, 0xb7, 0x01, 0xc1, 0x0d, 0x41, + 0x09, 0x81, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x2a, 0x84, 0x21, 0x45, 0x06, 0xc6, 0xef, 0xf0, 0x4f, + 0xd4, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x19, 0xf5, 0x00, 0x22, 0x85, 0xef, 0xf0, 0x1f, 0xdf, 0xb7, + 0x37, 0x20, 0x00, 0x23, 0xac, 0x07, 0xe8, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, + 0x37, 0x20, 0x00, 0x23, 0xa2, 0xa7, 0xfa, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x60, + 0x02, 0x98, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, 0x98, 0xc7, 0x82, 0x80, 0xb7, + 0x07, 0x00, 0x04, 0xc8, 0x4b, 0x82, 0x80, 0x39, 0x71, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x05, + 0x47, 0xb7, 0x07, 0x00, 0x04, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, + 0xd4, 0x32, 0xd2, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xd8, + 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0xe9, 0xd8, 0x43, 0x89, 0x46, 0x7d, 0x17, 0x63, + 0xfe, 0xe6, 0x02, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x05, 0x6c, 0xef, 0xd0, 0xef, + 0xe0, 0xef, 0xc0, 0x8f, 0xdc, 0xf2, 0x50, 0xe2, 0x52, 0xfa, 0xd8, 0x85, 0xa9, 0xef, 0xad, 0x4e, + 0xfd, 0xc1, 0x5f, 0xa3, 0x84, 0x3a, 0x97, 0xdc, 0xca, 0xf9, 0x18, 0x5e, 0xc8, 0x75, 0xd0, 0x22, + 0xfc, 0x2c, 0xbf, 0x89, 0x58, 0xe8, 0xb4, 0xb3, 0x78, 0x7c, 0x68, 0x4d, 0x52, 0x53, 0xc2, 0x53, + 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, + 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x13, 0x07, + 0xa0, 0x0a, 0x98, 0xcb, 0xd1, 0xbf, 0xb7, 0x07, 0x01, 0x02, 0x88, 0xd7, 0xcc, 0xd7, 0x88, 0xdb, + 0xcc, 0xdb, 0x88, 0xdf, 0xcc, 0xdf, 0x82, 0x80, 0x01, 0x11, 0x26, 0xca, 0xb7, 0x04, 0x01, 0x02, + 0x22, 0xcc, 0xc0, 0x40, 0xf5, 0x77, 0x93, 0x87, 0xf7, 0xa5, 0x7d, 0x8c, 0x89, 0x67, 0x93, 0x87, + 0x07, 0x1a, 0x06, 0xce, 0x4a, 0xc8, 0x4e, 0xc6, 0xc1, 0x8f, 0xaa, 0x89, 0xdc, 0xc0, 0x05, 0x45, + 0x2e, 0x89, 0xef, 0xd0, 0xbf, 0x99, 0x93, 0x67, 0x04, 0x40, 0xdc, 0xc0, 0x05, 0x45, 0xef, 0xd0, + 0xff, 0x98, 0x85, 0x67, 0x93, 0x87, 0x07, 0x40, 0x5d, 0x8c, 0xc0, 0xc0, 0xb7, 0x47, 0x00, 0x08, + 0x23, 0xa4, 0x07, 0x00, 0xb7, 0x57, 0x00, 0x08, 0x23, 0xa4, 0x07, 0x00, 0xf2, 0x40, 0x62, 0x44, + 0x23, 0xa0, 0x34, 0x03, 0x23, 0xa2, 0x24, 0x03, 0xb2, 0x49, 0xd2, 0x44, 0x42, 0x49, 0x05, 0x61, + 0x82, 0x80, 0xb7, 0x07, 0x01, 0x02, 0x88, 0x53, 0xcc, 0x53, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x02, + 0x88, 0x47, 0x21, 0x81, 0x13, 0x75, 0xf5, 0x0f, 0x82, 0x80, 0x41, 0x11, 0x01, 0x45, 0x81, 0x45, + 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0xef, 0xf0, 0x1f, 0xf6, 0xef, 0xf0, 0x9f, 0xfd, 0xaa, 0x84, + 0x2e, 0x84, 0x2a, 0x87, 0xfa, 0x8c, 0xc9, 0x53, 0x60, 0x55, 0x97, 0x5f, 0xd1, 0x7c, 0xa5, 0x19, + 0x5a, 0xc2, 0x78, 0x00, 0x3c, 0x73, 0xbd, 0x82, 0x27, 0x5d, 0x21, 0x74, 0xf8, 0xfd, 0x8b, 0x7e, + 0xcc, 0xf2, 0x88, 0x62, 0x40, 0x40, 0x4e, 0xae, 0x86, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, + 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0x85, 0x85, 0x71, 0x13, 0x05, 0x45, 0x64, 0x13, 0x06, 0x06, + 0x70, 0xef, 0xd0, 0xaf, 0xc9, 0xa2, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x26, 0x85, 0x92, 0x44, 0x41, + 0x01, 0x6f, 0xf0, 0xbf, 0xf3, 0x39, 0x71, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, + 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, + 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xf0, 0x7f, 0xf9, 0xef, 0xc0, 0x4f, 0xc9, 0xf2, + 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, + 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, + 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x07, 0x00, 0x02, 0x5c, 0x47, 0xc9, 0x8f, 0x5c, 0xc7, 0x82, + 0x80, 0xb7, 0x07, 0x00, 0x02, 0xd8, 0x47, 0x13, 0x45, 0xf5, 0xff, 0x79, 0x8d, 0xc8, 0xc7, 0x82, + 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x4f, 0xc9, 0x8f, 0x1c, 0xcf, 0x82, 0x80, 0xb7, 0x07, 0x00, + 0x02, 0x98, 0x4f, 0x13, 0x45, 0xf5, 0xff, 0x79, 0x8d, 0x88, 0xcf, 0x82, 0x80, 0xb7, 0x07, 0x00, + 0x02, 0xc8, 0xcb, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x47, 0x00, 0x1c, + 0xc7, 0xb7, 0x07, 0x00, 0x03, 0x94, 0x4b, 0x37, 0x37, 0x20, 0x00, 0x23, 0x24, 0xd7, 0xfa, 0xfa, + 0x51, 0xb5, 0xe0, 0x05, 0x62, 0xbf, 0xb1, 0x63, 0xbc, 0x82, 0xd5, 0x71, 0x63, 0x6e, 0x4f, 0xf4, + 0xa6, 0x1f, 0x6e, 0x30, 0xd3, 0x8e, 0x91, 0xce, 0x99, 0x44, 0x80, 0x4a, 0x50, 0xc8, 0x7b, 0xb1, + 0x18, 0x4f, 0x23, 0xa8, 0x07, 0x00, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0xb7, 0x06, + 0x00, 0x03, 0xf9, 0x9b, 0x1c, 0xc7, 0x37, 0x07, 0x08, 0x00, 0x9c, 0x46, 0xf9, 0x8f, 0xf5, 0xff, + 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x17, 0x00, 0x1c, 0xc7, 0xb7, 0x37, + 0x20, 0x00, 0x03, 0xa7, 0x87, 0xfa, 0xb7, 0x07, 0x00, 0x03, 0x98, 0xcb, 0x82, 0x80, 0xb7, 0x37, + 0x20, 0x00, 0x03, 0xa5, 0xc7, 0xfa, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0xb7, 0x27, + 0x03, 0x04, 0x9c, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, + 0x82, 0x80, 0x13, 0x05, 0x00, 0x10, 0x6f, 0xf0, 0x3f, 0xf4, 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, + 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0x41, 0x11, 0x37, 0x37, 0x20, 0x00, 0x23, 0x28, 0xf7, 0xfa, + 0x06, 0xc6, 0xef, 0xf0, 0x1f, 0xfe, 0xb7, 0x27, 0x03, 0x04, 0x09, 0x47, 0xd8, 0xc3, 0x37, 0x17, + 0x03, 0x04, 0xb7, 0x07, 0x03, 0x04, 0x13, 0x07, 0x07, 0x80, 0x23, 0xa0, 0x07, 0x00, 0x91, 0x07, + 0xe3, 0x9d, 0xe7, 0xfe, 0xb7, 0x27, 0x03, 0x04, 0x0d, 0x47, 0xd8, 0xc7, 0x98, 0x47, 0x85, 0x47, + 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, + 0x82, 0x80, 0x13, 0x05, 0x00, 0x10, 0x6f, 0xf0, 0xff, 0xee, 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, + 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0x37, 0x37, 0x20, 0x00, 0xfa, 0xd6, 0x0e, 0x4f, 0xca, 0x68, + 0x7b, 0xef, 0x7e, 0x3d, 0x77, 0x0a, 0x90, 0xa0, 0x67, 0x67, 0x16, 0xb2, 0xed, 0x36, 0x5e, 0xe5, + 0xc6, 0xbb, 0x6c, 0x30, 0xc1, 0x4f, 0x8b, 0xfd, 0xc6, 0x35, 0x03, 0xf0, 0x4f, 0x23, 0x28, 0xf7, + 0xfa, 0xb7, 0x27, 0x03, 0x04, 0x05, 0x47, 0xd8, 0xc3, 0x82, 0x80, 0xc2, 0x05, 0xc9, 0x8d, 0x93, + 0xe5, 0x05, 0x10, 0xb7, 0x07, 0x03, 0x04, 0x23, 0xa0, 0xb7, 0x10, 0x82, 0x80, 0xc2, 0x05, 0xc9, + 0x8d, 0x11, 0x65, 0x13, 0x05, 0x05, 0x50, 0xc9, 0x8d, 0xb7, 0x07, 0x03, 0x04, 0x23, 0xa0, 0xb7, + 0x10, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x99, + 0xc3, 0xef, 0xb0, 0x9f, 0xc4, 0x37, 0x15, 0x03, 0x04, 0x2a, 0x94, 0x08, 0x40, 0xb2, 0x40, 0x22, + 0x44, 0x41, 0x01, 0x82, 0x80, 0x79, 0x71, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x06, 0xd6, 0x22, + 0xd4, 0xaa, 0x84, 0x2e, 0x89, 0xb2, 0x89, 0x19, 0xe1, 0xef, 0xb0, 0x1f, 0xc2, 0x93, 0x77, 0x39, + 0x00, 0x99, 0xc3, 0xef, 0xb0, 0x7f, 0xc1, 0x01, 0x44, 0x63, 0x69, 0x34, 0x01, 0xb2, 0x50, 0x22, + 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x45, 0x61, 0x82, 0x80, 0x33, 0x05, 0x24, 0x01, 0xef, + 0xf0, 0x5f, 0xfa, 0x2a, 0xc6, 0x11, 0x46, 0x33, 0x85, 0x84, 0x00, 0x6c, 0x00, 0xcd, 0x2d, 0x11, + 0x04, 0xe1, 0xbf, 0x79, 0x71, 0x22, 0xd4, 0x4a, 0xd0, 0x4e, 0xce, 0x56, 0xca, 0x06, 0xd6, 0x26, + 0xd2, 0x52, 0xcc, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0xae, 0x89, 0x32, 0x89, 0x93, 0x7a, 0xc6, + 0xff, 0x99, 0xc3, 0xef, 0xb0, 0x7f, 0xbc, 0x37, 0x0a, 0x03, 0x04, 0x81, 0x44, 0x22, 0x9a, 0x63, + 0xe9, 0x54, 0x03, 0x13, 0x76, 0xfa, 0x8b, 0x83, 0x5c, 0xa5, 0x90, 0x36, 0x78, 0x3c, 0xaf, 0x8e, + 0xce, 0x0a, 0x76, 0xa1, 0xa0, 0x33, 0xd9, 0xfb, 0x38, 0xc6, 0x37, 0xca, 0x98, 0xbd, 0xaf, 0xe7, + 0x29, 0xb1, 0xc4, 0x8a, 0x12, 0x2b, 0xc8, 0x50, 0x39, 0x00, 0x01, 0xce, 0xb3, 0x85, 0x99, 0x00, + 0x68, 0x00, 0x02, 0xc6, 0x7d, 0x25, 0xb2, 0x47, 0x37, 0x05, 0x03, 0x04, 0x2a, 0x94, 0x26, 0x94, + 0x1c, 0xc0, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0xd2, 0x4a, + 0x45, 0x61, 0x82, 0x80, 0x63, 0x94, 0x09, 0x00, 0xef, 0xb0, 0x5f, 0xb8, 0xb3, 0x85, 0x99, 0x00, + 0x11, 0x46, 0x68, 0x00, 0xbd, 0x2d, 0x32, 0x47, 0xb3, 0x07, 0x9a, 0x00, 0x91, 0x04, 0x98, 0xc3, + 0x4d, 0xbf, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x41, 0x11, 0x13, 0x05, 0x45, 0xb5, 0x06, 0xc6, + 0x22, 0xc4, 0xef, 0xd0, 0xef, 0xe9, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0f, 0xf5, 0x00, 0x37, 0x55, + 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x05, 0x72, 0xef, 0xd0, 0x2f, 0xa3, 0x13, 0x05, 0x50, 0x05, + 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x17, 0x03, 0x04, 0x83, 0xa7, 0x07, 0x10, + 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, 0xfb, 0x93, 0xf7, 0xf7, 0x0f, 0x81, 0xe7, 0x1c, 0x40, + 0x63, 0x9d, 0xa7, 0x00, 0x37, 0x55, 0x10, 0x00, 0x8d, 0x45, 0x13, 0x05, 0x05, 0x72, 0xef, 0xd0, + 0xcf, 0x9f, 0x93, 0x07, 0xa0, 0x0a, 0x1c, 0xc0, 0xd1, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, + 0xc7, 0xfa, 0x13, 0x84, 0xc7, 0xfa, 0x63, 0x09, 0xa7, 0x00, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, + 0x13, 0x05, 0x05, 0x72, 0xef, 0xd0, 0x6f, 0x9d, 0x08, 0x40, 0x5d, 0xb7, 0x37, 0x95, 0x04, 0x00, + 0xfa, 0x2e, 0x5a, 0xf4, 0xe1, 0x40, 0xb6, 0x8a, 0x0c, 0x02, 0x02, 0x42, 0x33, 0x0a, 0x0f, 0x83, + 0x05, 0x33, 0xde, 0x08, 0x3a, 0xec, 0xd7, 0x1b, 0xe0, 0x0d, 0x55, 0x64, 0x53, 0x08, 0x1b, 0xf1, + 0x9f, 0xa0, 0x51, 0x13, 0x05, 0x05, 0x3e, 0x6f, 0xf0, 0xff, 0xf6, 0x41, 0x11, 0x06, 0xc6, 0xef, + 0xf0, 0x5f, 0xe6, 0xef, 0xf0, 0x1f, 0xe3, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x5f, 0xfe, 0xb7, + 0x17, 0x03, 0x04, 0x03, 0xa5, 0x07, 0x10, 0x41, 0x81, 0x82, 0x80, 0x41, 0x11, 0x3a, 0xc4, 0x37, + 0x27, 0x03, 0x04, 0x3e, 0xc2, 0x1c, 0x47, 0x36, 0xc6, 0x93, 0xf6, 0x27, 0x00, 0x89, 0xca, 0x89, + 0x46, 0x14, 0xc7, 0x37, 0x37, 0x20, 0x00, 0x93, 0x06, 0xa0, 0x0a, 0x23, 0x26, 0xd7, 0xfa, 0x91, + 0x8b, 0x99, 0xcf, 0xb7, 0x27, 0x03, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x93, 0x07, 0xa0, 0x0a, 0x37, + 0x37, 0x20, 0x00, 0x23, 0x28, 0xf7, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xfa, 0xb2, + 0x46, 0x22, 0x47, 0x92, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x22, 0xc4, 0x37, + 0x04, 0x00, 0x03, 0x1c, 0x48, 0x06, 0xc6, 0xdd, 0x9b, 0x1c, 0xc8, 0xef, 0xe0, 0x0f, 0xd9, 0xb7, + 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x02, 0x5c, 0xcc, 0xb2, 0x40, 0x22, 0x44, 0xb7, 0x37, 0x20, + 0x00, 0x23, 0x8c, 0x07, 0xfa, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x2a, 0x84, 0x21, + 0x45, 0x06, 0xc6, 0xef, 0xf0, 0x7f, 0xca, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x7f, 0xc6, 0x22, + 0x04, 0x13, 0x64, 0x04, 0x03, 0x37, 0x07, 0x00, 0x03, 0x40, 0xc3, 0xb2, 0x40, 0x22, 0x44, 0xc1, + 0x67, 0x93, 0x87, 0xa7, 0xfa, 0x1c, 0xcf, 0x41, 0x01, 0x82, 0x80, 0xfa, 0xd6, 0xdd, 0xf6, 0xa9, + 0x68, 0x89, 0x40, 0x5e, 0x01, 0x20, 0x1f, 0x9d, 0x67, 0xb3, 0xb0, 0xe7, 0x4b, 0x3f, 0x08, 0x0a, + 0x8a, 0x43, 0x28, 0xd8, 0x5d, 0xb6, 0x1a, 0x6b, 0x32, 0xe4, 0xe9, 0xaf, 0x78, 0x52, 0x41, 0x11, + 0x26, 0xc2, 0xaa, 0x84, 0x09, 0x45, 0x22, 0xc4, 0x06, 0xc6, 0x2e, 0x84, 0xef, 0xf0, 0x1f, 0xfc, + 0x37, 0x07, 0x20, 0x00, 0xb7, 0x07, 0x00, 0x03, 0x13, 0x07, 0x07, 0x02, 0xd8, 0xcf, 0x37, 0x37, + 0x20, 0x00, 0x23, 0x2a, 0x97, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2e, 0x87, 0xfa, 0xb2, 0x40, + 0x22, 0x44, 0x05, 0x47, 0x98, 0xcb, 0x37, 0x07, 0x08, 0x00, 0x98, 0xc7, 0x92, 0x44, 0x41, 0x01, + 0x82, 0x80, 0xb7, 0x07, 0x00, 0x03, 0x9c, 0x47, 0x37, 0x07, 0x04, 0x00, 0x13, 0x05, 0xa0, 0x0a, + 0xf9, 0x8f, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x37, 0x07, 0x00, 0x03, 0x5c, 0x53, + 0x13, 0x05, 0x50, 0x05, 0x93, 0x96, 0x07, 0x01, 0xc1, 0x82, 0xc1, 0x83, 0x63, 0x97, 0xf6, 0x00, + 0x1c, 0x47, 0x91, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, + 0xef, 0xf0, 0xff, 0xf1, 0x37, 0x07, 0x00, 0x03, 0x5c, 0x47, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc7, + 0x5c, 0x47, 0x85, 0x8b, 0xf5, 0xff, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, + 0x83, 0xa7, 0xc7, 0xfb, 0x95, 0xc3, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x5f, 0xef, 0xb7, 0x07, + 0x00, 0x03, 0x98, 0x4b, 0xb2, 0x40, 0x13, 0x67, 0x87, 0x00, 0x98, 0xcb, 0x37, 0x07, 0x08, 0x00, + 0x98, 0xc7, 0x41, 0x01, 0x6f, 0xe0, 0xcf, 0xc5, 0x82, 0x80, 0x37, 0x07, 0x00, 0x03, 0x1c, 0x4b, + 0xf9, 0x9b, 0x1c, 0xcb, 0x82, 0x80, 0xfa, 0xd9, 0x71, 0x17, 0x73, 0x0c, 0x81, 0x2d, 0x69, 0x83, + 0xc8, 0xfb, 0x9a, 0x55, 0xf5, 0x79, 0x51, 0xc7, 0x04, 0x8c, 0xb4, 0x8a, 0xc9, 0x02, 0x9d, 0x3c, + 0x4a, 0x76, 0xcd, 0x59, 0x8d, 0x86, 0x55, 0x50, 0x53, 0xb7, 0x06, 0x00, 0x03, 0xdc, 0x42, 0x7d, + 0x77, 0x13, 0x07, 0xf7, 0x0f, 0xf9, 0x8f, 0x05, 0x67, 0x22, 0x05, 0x13, 0x07, 0x07, 0xf0, 0x79, + 0x8d, 0x5d, 0x8d, 0xc8, 0xc2, 0x82, 0x80, 0x1d, 0x71, 0x3a, 0xda, 0x37, 0x07, 0x00, 0x03, 0x3e, + 0xd8, 0x1c, 0x47, 0x86, 0xce, 0x96, 0xcc, 0x9a, 0xca, 0x9e, 0xc8, 0xa2, 0xc6, 0xa6, 0xc4, 0xaa, + 0xc2, 0xae, 0xc0, 0x32, 0xde, 0x36, 0xdc, 0x42, 0xd6, 0x46, 0xd4, 0x4a, 0xd2, 0x4e, 0xd0, 0x72, + 0xce, 0x76, 0xcc, 0x7a, 0xca, 0x7e, 0xc8, 0x85, 0x8b, 0xa1, 0xc7, 0x04, 0x57, 0x11, 0x44, 0x37, + 0x39, 0x20, 0x00, 0x83, 0x27, 0x49, 0xfb, 0x13, 0xf5, 0xf4, 0x0f, 0x7d, 0x14, 0x82, 0x97, 0xa1, + 0x80, 0x6d, 0xf8, 0x36, 0x44, 0xf6, 0x40, 0xe6, 0x42, 0x56, 0x43, 0xc6, 0x43, 0xa6, 0x44, 0x16, + 0x45, 0x86, 0x45, 0x72, 0x56, 0xe2, 0x56, 0x52, 0x57, 0xc2, 0x57, 0x32, 0x58, 0xa2, 0x58, 0x12, + 0x59, 0x82, 0x59, 0x72, 0x4e, 0xe2, 0x4e, 0x52, 0x4f, 0xc2, 0x4f, 0x25, 0x61, 0x73, 0x00, 0x20, + 0x30, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xc7, 0x87, 0xfb, 0x13, 0x84, 0x87, 0xfb, 0x05, 0xeb, 0xb7, + 0x04, 0x00, 0x03, 0x37, 0x39, 0x20, 0x00, 0x93, 0x09, 0xa0, 0x0a, 0x9c, 0x44, 0x91, 0x8b, 0xd5, + 0xfb, 0x83, 0x27, 0xc9, 0xfb, 0x68, 0x00, 0x82, 0x97, 0x63, 0x0d, 0x35, 0x01, 0x85, 0x47, 0x23, + 0x00, 0xf4, 0x00, 0xc1, 0x67, 0x93, 0x87, 0x07, 0x02, 0xdc, 0xcc, 0x61, 0xbf, 0xef, 0xf0, 0x5f, + 0xdf, 0xfa, 0x13, 0xcd, 0x54, 0x98, 0x6f, 0x53, 0x7c, 0x10, 0x70, 0xc1, 0x39, 0x0d, 0x95, 0x14, + 0x27, 0x71, 0xdd, 0xb5, 0x71, 0x98, 0x20, 0x76, 0xaf, 0x3b, 0x55, 0x38, 0xfb, 0x9c, 0xdd, 0x4a, + 0x6d, 0xd9, 0x28, 0x54, 0x49, 0xbf, 0xb2, 0x47, 0x9c, 0xd8, 0xd1, 0xbf, 0x5c, 0x41, 0x93, 0xe7, + 0x17, 0x00, 0x5c, 0xc1, 0x82, 0x80, 0x5c, 0x41, 0xf9, 0x9b, 0x5c, 0xc1, 0x82, 0x80, 0x5c, 0x41, + 0xf5, 0x9b, 0xd1, 0x8f, 0x5c, 0xc1, 0x14, 0xc9, 0x4c, 0xc9, 0x82, 0x80, 0x5c, 0x45, 0xcd, 0x8f, + 0x5c, 0xc5, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x07, 0xfc, 0x82, 0x80, 0x39, 0x71, + 0x3a, 0xce, 0x37, 0x07, 0x10, 0x01, 0x3e, 0xcc, 0x1c, 0x47, 0x58, 0x47, 0x06, 0xde, 0x16, 0xdc, + 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, + 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xf9, 0x8f, 0x91, 0xcf, 0xb7, 0x37, 0x20, 0x00, + 0x93, 0x87, 0x07, 0xfc, 0x98, 0x43, 0x05, 0x07, 0x98, 0xc3, 0xb7, 0x07, 0x10, 0x01, 0x98, 0x47, + 0x0d, 0x8b, 0x98, 0xc7, 0x19, 0xa8, 0xb7, 0x07, 0x20, 0x01, 0x98, 0x47, 0xdc, 0x47, 0x7d, 0x8f, + 0xb7, 0x07, 0x20, 0x01, 0x6d, 0xf7, 0xef, 0xb0, 0xff, 0xe6, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, + 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, + 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, + 0x1c, 0x41, 0x63, 0xf7, 0xb7, 0x00, 0x23, 0x80, 0xc7, 0x00, 0x1c, 0x41, 0x85, 0x07, 0x1c, 0xc1, + 0x82, 0x80, 0x1d, 0x71, 0xa2, 0xcc, 0xa6, 0xca, 0xca, 0xc8, 0x86, 0xce, 0xfa, 0xcb, 0x8a, 0xed, + 0x7b, 0xbd, 0xaa, 0x12, 0x35, 0x5f, 0xaf, 0x78, 0xaa, 0x2a, 0x47, 0x6d, 0xec, 0x5f, 0x4d, 0x37, + 0xe1, 0xaf, 0xbd, 0xd8, 0x7e, 0x11, 0xa2, 0xb7, 0xa2, 0xbf, 0x34, 0xe7, 0xf4, 0x00, 0x55, 0xce, + 0xc6, 0xd2, 0xc4, 0xd6, 0xc2, 0xda, 0xc0, 0x5e, 0xde, 0x62, 0xdc, 0x66, 0xda, 0x6a, 0xd8, 0x6e, + 0xd6, 0x2a, 0xc6, 0x2e, 0x84, 0x32, 0x89, 0xb6, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x0f, 0xf6, 0x63, + 0x14, 0x09, 0x00, 0xef, 0xb0, 0x8f, 0xf5, 0x01, 0x45, 0x05, 0xc4, 0xb2, 0x4a, 0x7d, 0x14, 0x25, + 0x4a, 0x56, 0x94, 0x93, 0x0c, 0xc0, 0x06, 0x13, 0x0b, 0x30, 0x07, 0xa9, 0x4b, 0x1d, 0x4d, 0x03, + 0x46, 0x09, 0x00, 0x15, 0xe6, 0xb2, 0x47, 0x23, 0x80, 0x07, 0x00, 0x32, 0x45, 0x33, 0x05, 0x55, + 0x41, 0xf6, 0x40, 0x66, 0x44, 0xd6, 0x44, 0x46, 0x49, 0xb6, 0x49, 0x26, 0x4a, 0x96, 0x4a, 0x06, + 0x4b, 0xf2, 0x5b, 0x62, 0x5c, 0xd2, 0x5c, 0x42, 0x5d, 0xb2, 0x5d, 0x25, 0x61, 0x82, 0x80, 0x93, + 0x07, 0x50, 0x02, 0x63, 0x1f, 0xf6, 0x02, 0x93, 0x07, 0x19, 0x00, 0x83, 0xc6, 0x07, 0x00, 0x3e, + 0x89, 0x85, 0x07, 0x13, 0x87, 0x06, 0xfd, 0x13, 0x77, 0xf7, 0x0f, 0xe3, 0x78, 0xea, 0xfe, 0x63, + 0x93, 0x96, 0x01, 0x3e, 0x89, 0x03, 0x46, 0x09, 0x00, 0x63, 0x06, 0x66, 0x0d, 0x63, 0x60, 0xcb, + 0x02, 0x93, 0x07, 0x30, 0x06, 0x63, 0x05, 0xf6, 0x06, 0x93, 0x07, 0x40, 0x06, 0x63, 0x0c, 0xf6, + 0x06, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, 0xf2, 0xa6, 0x89, 0x95, 0xa0, 0x93, 0x07, 0x50, + 0x07, 0x63, 0x02, 0xf6, 0x06, 0x93, 0x07, 0x80, 0x07, 0xe3, 0x14, 0xf6, 0xfe, 0x98, 0x40, 0x93, + 0x89, 0x44, 0x00, 0x81, 0x46, 0x37, 0x06, 0xfa, 0x4c, 0x87, 0xca, 0x4e, 0x13, 0x0b, 0xd1, 0x0d, + 0x64, 0xd2, 0x11, 0x47, 0xb5, 0x47, 0xd8, 0xc9, 0xd4, 0x74, 0x1f, 0x62, 0xdc, 0x60, 0x38, 0xbb, + 0x72, 0xf0, 0x4f, 0x0a, 0xc5, 0x13, 0xd9, 0xc3, 0xd8, 0x55, 0x00, 0xf0, 0xb3, 0x75, 0xc7, 0x00, + 0xba, 0x84, 0x36, 0x8c, 0x12, 0x07, 0x85, 0x06, 0x89, 0xe5, 0xe3, 0x99, 0xa6, 0xff, 0x1d, 0x4c, + 0xba, 0x84, 0xa1, 0x4d, 0x13, 0xd7, 0xc4, 0x01, 0x63, 0x74, 0xea, 0x08, 0x13, 0x06, 0x77, 0x05, + 0xa2, 0x85, 0x68, 0x00, 0x05, 0x0c, 0xef, 0xf0, 0x1f, 0xee, 0x92, 0x04, 0xe3, 0x14, 0xbc, 0xff, + 0x09, 0xa8, 0x03, 0xc6, 0x04, 0x00, 0xa2, 0x85, 0x68, 0x00, 0x93, 0x89, 0x44, 0x00, 0xef, 0xf0, + 0x9f, 0xec, 0x05, 0x09, 0xce, 0x84, 0x31, 0xbf, 0x5c, 0x08, 0x98, 0x40, 0x93, 0x89, 0x44, 0x00, + 0x3e, 0x8c, 0x81, 0x44, 0xb3, 0x76, 0x77, 0x03, 0x85, 0x04, 0x85, 0x07, 0x93, 0x86, 0x06, 0x03, + 0xa3, 0x8f, 0xd7, 0xfe, 0xba, 0x86, 0x33, 0x57, 0x77, 0x03, 0xe3, 0x65, 0xda, 0xfe, 0xfd, 0x5d, + 0xfd, 0x14, 0xe3, 0x88, 0xb4, 0xfd, 0xb3, 0x07, 0x9c, 0x00, 0x03, 0xc6, 0x07, 0x00, 0xa2, 0x85, + 0x68, 0x00, 0xef, 0xf0, 0x5f, 0xe8, 0xed, 0xb7, 0x93, 0x89, 0x44, 0x00, 0x84, 0x40, 0x03, 0xc6, + 0x04, 0x00, 0x45, 0xda, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, 0xe6, 0x85, 0x04, 0xc5, 0xbf, + 0x13, 0x06, 0x07, 0x03, 0xb5, 0xbf, 0x41, 0x11, 0x26, 0xc2, 0xb7, 0x34, 0x20, 0x00, 0x2a, 0x86, + 0xae, 0x86, 0x13, 0x85, 0x84, 0xea, 0x93, 0x05, 0x00, 0x08, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0xf0, + 0xbf, 0xe5, 0x2a, 0x84, 0x13, 0x85, 0x84, 0xea, 0xef, 0xd0, 0x8f, 0x9b, 0xb2, 0x40, 0x22, 0x85, + 0x22, 0x44, 0xfa, 0x77, 0x25, 0x15, 0xa5, 0x40, 0xb8, 0x46, 0xd0, 0x99, 0xaa, 0x4d, 0x3a, 0x4d, + 0xdc, 0xe4, 0xd3, 0xb8, 0xb9, 0x2c, 0xd5, 0x88, 0x4e, 0xc5, 0x22, 0xc0, 0xd2, 0xa7, 0x93, 0x05, + 0x87, 0x6b, 0x88, 0xb0, 0x56, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x26, 0xca, 0xb7, + 0x34, 0x20, 0x00, 0x2e, 0xd2, 0x32, 0xd4, 0x36, 0xd6, 0x2a, 0x86, 0x54, 0x10, 0x93, 0x05, 0x00, + 0x08, 0x13, 0x85, 0x84, 0xea, 0x06, 0xce, 0x22, 0xcc, 0x3a, 0xd8, 0x3e, 0xda, 0x42, 0xdc, 0x46, + 0xde, 0x36, 0xc6, 0xef, 0xf0, 0x9f, 0xe1, 0x2a, 0x84, 0x13, 0x85, 0x84, 0xea, 0xef, 0xd0, 0x6f, + 0x97, 0xf2, 0x40, 0x22, 0x85, 0x62, 0x44, 0xd2, 0x44, 0x21, 0x61, 0x82, 0x80, 0x22, 0x05, 0x61, + 0x77, 0x2d, 0x8d, 0xa1, 0x47, 0x15, 0x07, 0x93, 0x16, 0x05, 0x01, 0x06, 0x05, 0x42, 0x05, 0xc1, + 0x86, 0x41, 0x81, 0x63, 0xd5, 0x06, 0x00, 0x39, 0x8d, 0x42, 0x05, 0x41, 0x81, 0xfd, 0x17, 0xe5, + 0xf7, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x2a, 0x84, 0xb3, 0x04, 0xb5, 0x00, 0x06, + 0xc6, 0x01, 0x45, 0x63, 0x97, 0x84, 0x00, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, + 0x80, 0x05, 0x04, 0xaa, 0x85, 0x03, 0x45, 0xf4, 0xff, 0xef, 0xf0, 0x5f, 0xfb, 0xdd, 0xb7, 0xb7, + 0x86, 0xb8, 0xed, 0x01, 0x47, 0xfd, 0x57, 0x93, 0x86, 0x06, 0x32, 0x63, 0x15, 0xb7, 0x00, 0x13, + 0xc5, 0xf7, 0xff, 0x82, 0x80, 0x33, 0x06, 0xe5, 0x00, 0x03, 0x46, 0x06, 0x00, 0xb1, 0x8f, 0x21, + 0x46, 0x13, 0xd8, 0x17, 0x00, 0x85, 0x8b, 0x91, 0xc3, 0xb6, 0x87, 0x7d, 0x16, 0xb3, 0x47, 0xf8, + 0x00, 0x65, 0xfa, 0x05, 0x07, 0xd9, 0xbf, 0x2a, 0x83, 0x09, 0xca, 0x83, 0x83, 0xfa, 0xb3, 0xc7, + 0xe1, 0x28, 0x25, 0xd4, 0xa1, 0xe8, 0xd0, 0x44, 0xbf, 0x8d, 0x35, 0x9f, 0xf3, 0x28, 0x04, 0x1e, + 0xbe, 0xd4, 0x02, 0xad, 0xea, 0x20, 0x5e, 0xe0, 0xcd, 0x00, 0xea, 0xb7, 0xed, 0xd1, 0x88, 0x57, + 0x05, 0x00, 0x23, 0x00, 0x73, 0x00, 0x7d, 0x16, 0x05, 0x03, 0x85, 0x05, 0x6d, 0xfa, 0x82, 0x80, + 0x15, 0xc2, 0x2a, 0x83, 0x85, 0x46, 0x63, 0x67, 0xb5, 0x00, 0xfd, 0x56, 0x13, 0x07, 0xf6, 0xff, + 0x3a, 0x93, 0xba, 0x95, 0x83, 0x83, 0x05, 0x00, 0x23, 0x00, 0x73, 0x00, 0x7d, 0x16, 0x36, 0x93, + 0xb6, 0x95, 0x6d, 0xfa, 0x82, 0x80, 0x2a, 0x83, 0x11, 0xc6, 0x23, 0x00, 0xb3, 0x00, 0x7d, 0x16, + 0x05, 0x03, 0x65, 0xfe, 0x82, 0x80, 0x00, 0x00, 0x63, 0x6f, 0x64, 0x65, 0x3a, 0x20, 0x25, 0x78, + 0x00, 0x00, 0x00, 0x00, 0x53, 0x45, 0x43, 0x43, 0x48, 0x4e, 0x4c, 0x00, 0x4d, 0x43, 0x4e, 0x54, + 0x00, 0x00, 0x00, 0x00, 0x54, 0x58, 0x3a, 0x20, 0x25, 0x64, 0x2f, 0x25, 0x64, 0x2c, 0x20, 0x6c, + 0x3d, 0x25, 0x64, 0x00, 0x43, 0x4d, 0x44, 0x33, 0x00, 0x00, 0x00, 0x00, 0x49, 0x00, 0x00, 0x00, + 0x65, 0x6e, 0x61, 0x62, 0x6c, 0x65, 0x64, 0x20, 0x25, 0x64, 0x00, 0x00, 0x4d, 0x41, 0x49, 0x4e, + 0x00, 0x00, 0x00, 0x00, 0x6c, 0x65, 0x6e, 0x20, 0x25, 0x64, 0x2f, 0x25, 0x64, 0x00, 0x00, 0x00, + 0x72, 0x73, 0x70, 0x3d, 0x25, 0x78, 0x00, 0x00, 0x73, 0x74, 0x61, 0x72, 0x74, 0x2c, 0x20, 0x76, + 0x25, 0x75, 0x2e, 0x25, 0x75, 0x2e, 0x25, 0x75, 0x00, 0x00, 0x00, 0x00, 0x50, 0x52, 0x4f, 0x56, + 0x49, 0x53, 0x49, 0x4f, 0x4e, 0x20, 0x4f, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x4e, 0x3a, 0x20, 0x25, + 0x78, 0x00, 0x00, 0x00, 0x43, 0x50, 0x42, 0x3a, 0xfa, 0x73, 0x3a, 0xfa, 0x5a, 0xd6, 0xf0, 0x73, + 0xa2, 0xda, 0x98, 0x8a, 0x7e, 0x8e, 0x52, 0x63, 0x08, 0x47, 0x24, 0xce, 0x4a, 0x46, 0x93, 0xfa, + 0xc5, 0x59, 0x97, 0x8b, 0xa7, 0x86, 0x9a, 0x19, 0xb0, 0x60, 0x58, 0x20, 0x25, 0x64, 0x00, 0x4c, + 0x33, 0x20, 0x63, 0x6d, 0x64, 0x20, 0x25, 0x64, 0x3a, 0x20, 0x25, 0x78, 0x2c, 0x20, 0x6c, 0x65, + 0x6e, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x00, 0x4c, 0x33, 0x20, 0x61, 0x63, 0x63, 0x65, 0x73, 0x73, + 0x20, 0x66, 0x61, 0x69, 0x6c, 0x65, 0x64, 0x2c, 0x20, 0x63, 0x6d, 0x64, 0x3a, 0x20, 0x25, 0x64, + 0x2c, 0x20, 0x6c, 0x65, 0x6e, 0x3a, 0x20, 0x25, 0x64, 0x20, 0x00, 0x70, 0x69, 0x6e, 0x67, 0x2c, + 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x00, 0x4c, 0x33, 0x00, 0x00, 0x57, 0x52, 0x3a, 0x20, 0x25, + 0x64, 0x00, 0x00, 0x52, 0x44, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x00, 0x6d, 0x61, 0x63, 0x61, 0x6e, + 0x64, 0x64, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x00, 0x00, 0x73, 0x65, 0x6e, 0x74, 0x00, + 0x00, 0x00, 0x00, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x20, 0x73, 0x6c, 0x65, 0x65, 0x70, 0x00, 0x77, + 0x61, 0x6b, 0x65, 0x75, 0x70, 0x00, 0x00, 0x56, 0x19, 0x10, 0x00, 0x94, 0x19, 0x10, 0x00, 0xc0, + 0x19, 0x10, 0x00, 0xf0, 0x19, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, + 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, + 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0xf8, + 0x13, 0x10, 0x00, 0xf8, 0x13, 0x10, 0x00, 0x0a, 0x1a, 0x10, 0x00, 0x64, 0x1a, 0x10, 0x00, 0x00, + 0x00, 0x00, 0x01, 0xfa, 0x5b, 0xe6, 0x65, 0x94, 0x14, 0x19, 0x43, 0x12, 0xb5, 0x4a, 0x89, 0x52, + 0xb3, 0x04, 0x67, 0x99, 0xc7, 0xe2, 0xaa, 0x16, 0xfd, 0x02, 0x6b, 0x91, 0x91, 0x34, 0xe8, 0x29, + 0x9a, 0x23, 0x69, 0x70, 0x38, 0x59, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 0x00, 0x06, 0x01, 0x00, + 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x1f, 0x00, 0x06, 0x02, 0x00, 0x05, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x1c, 0x00, 0x06, 0x03, 0x10, 0x08, 0x00, 0x00, 0x18, 0x00, 0x00, 0x40, 0x1f, + 0x00, 0x06, 0x06, 0x10, 0x08, 0x00, 0x04, 0x18, 0x00, 0x00, 0x60, 0x1f, 0x00, 0x06, 0x04, 0x00, + 0x09, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x06, 0x05, 0x05, 0x7f, 0x07, 0x01, 0x08, 0x18, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xf0, 0x01, 0x10, 0x10, 0x00, 0x04, 0x02, 0x11, 0x00, + 0x44, 0x02, 0x12, 0x00, 0x84, 0x02, 0x20, 0x90, 0x01, 0x03, 0x21, 0x80, 0x42, 0x03, 0x22, 0xf0, + 0x01, 0x03, 0x30, 0x80, 0x02, 0x04, 0x31, 0x80, 0x42, 0x04, 0x40, 0x70, 0x04, 0x11, 0x41, 0x70, + 0x44, 0x11, 0x42, 0x70, 0x84, 0x11, 0x50, 0xf0, 0x01, 0x12, 0x60, 0x32, 0x04, 0x13, 0x61, 0x32, + 0x44, 0x13, 0x62, 0x32, 0x84, 0x13, 0x63, 0x32, 0xc4, 0x13, 0x70, 0x32, 0x04, 0x14, 0x71, 0x32, + 0x44, 0x14, 0x80, 0x20, 0x04, 0x15, 0x81, 0x20, 0x84, 0x15, 0x82, 0x20, 0x44, 0x15, 0x90, 0x51, + 0x04, 0x16, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x14, 0x04, 0x04, 0x00, 0x08, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x20, 0x25, 0x6c, 0x75, 0x20, 0x00, 0x00, 0xfa, 0xb6, + 0x2d, 0x6e, 0x05, 0x7e, 0xb5, 0xdf, 0x94, 0xaf, 0xa1, 0xd8, 0xee, 0x79, 0x63, 0x84, 0xef, 0x03, + 0xc2, 0xf2, 0x80, 0x3b, 0x5e, 0xa0, 0x22, 0x75, 0xe1, 0x42, 0xaf, 0xae, 0xbe, 0xe6, 0xb2, 0x10, + 0x5a, 0x25, 0x73, 0x28, 0x25, 0x73, 0x29, 0x3a, 0x20, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, + 0x00, 0x45, 0x00, 0x00, 0x00, 0x4d, 0x53, 0x47, 0x00, 0x43, 0x52, 0x43, 0x20, 0x72, 0x78, 0x3a, + 0x20, 0x25, 0x30, 0x34, 0x78, 0x2c, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x3a, 0x20, 0x25, 0x30, 0x34, + 0x78, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0xe4, 0x1f, 0x10, 0x00, 0x04, 0x20, 0x10, + 0x00, 0x56, 0x20, 0x10, 0x00, 0xb8, 0x20, 0x10, 0x00, 0xc2, 0x20, 0x10, 0x00, 0x4f, 0x53, 0x00, + 0x00, 0x63, 0x6f, 0x6e, 0x64, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, 0x52, 0x58, 0x3a, + 0x20, 0x63, 0x6d, 0x64, 0x3d, 0x30, 0x78, 0x25, 0x30, 0x32, 0x78, 0x00, 0x00, 0x55, 0x49, 0x00, + 0x00, 0x43, 0x50, 0x42, 0x20, 0x49, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x20, 0x21, + 0x00, 0x43, 0x50, 0x42, 0x00, 0x57, 0x00, 0x00, 0x00, 0x46, 0x53, 0x53, 0x00, 0x49, 0x52, 0x51, + 0x00, 0x53, 0x54, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x4b, 0x44, 0x42, 0x00, 0x73, 0x74, 0x3a, + 0x20, 0x25, 0x78, 0x00, 0x00, 0x4d, 0x41, 0x44, 0x00, 0x4f, 0x54, 0x50, 0x00, 0x01, 0x00, 0x00, + 0x00, 0x53, 0x43, 0x42, 0x00, 0x4e, 0x6f, 0x69, 0x73, 0x65, 0x5f, 0x4b, 0x4b, 0x31, 0x5f, 0x32, + 0x35, 0x35, 0x31, 0x39, 0x5f, 0x41, 0x45, 0x53, 0x47, 0x43, 0x4d, 0x5f, 0x53, 0x48, 0x41, 0x32, + 0x35, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x66, 0x44, 0x14, 0xb7, 0x22, 0xdd, 0xc6, + 0xc7, 0x09, 0xcf, 0xf2, 0x78, 0x85, 0xe2, 0xdd, 0x16, 0xc4, 0x1f, 0xc9, 0x7b, 0x3f, 0x7a, 0x99, + 0xc1, 0x2c, 0x16, 0xd4, 0x73, 0x2e, 0xed, 0x78, 0x5a, 0xff, 0xe8, 0x5a, 0x14, 0x3f, 0x10, 0x00, + 0x78, 0x45, 0x10, 0x00, 0x62, 0x45, 0x10, 0x00, 0x26, 0x45, 0x10, 0x00, 0x3a, 0x3e, 0x10, 0x00, + 0xd0, 0x45, 0x10, 0x00, 0x41, 0x4c, 0x41, 0x52, 0x4d, 0x20, 0x43, 0x48, 0x41, 0x4e, 0x4e, 0x45, + 0x4c, 0x53, 0x3a, 0x20, 0x25, 0x78, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x53, 0x43, 0x4e, 0x54, + 0x52, 0x00, 0x00, 0x00, 0x53, 0x50, 0x45, 0x43, 0x54, 0x00, 0x00, 0x00, 0xc3, 0x14, 0x13, 0x00, + 0x72, 0xfc, 0x3d, 0xf3, 0x51, 0xe5, 0x58, 0x83, 0x96, 0x66, 0x17, 0xb2, 0x9a, 0x92, 0xf7, 0x4e, + 0x0e, 0x13, 0x7e, 0x2f, 0xa3, 0x4c, 0x0c, 0x45, 0xe8, 0xcb, 0x26, 0x6e, 0x13, 0xb4, 0x0e, 0x4e, + 0x05, 0xb0, 0x03, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfa, 0x35, 0xb7, 0x8a, 0xb8, 0x90, 0xb0, 0x09, 0xa1, 0xac, 0x6b, 0xa4, 0xc9, + 0x67, 0xda, 0xee, 0xfd, 0xce, 0x9b, 0x31, 0x82, 0x74, 0x2b, 0x6f, 0x6d, 0x61, 0x8b, 0x8e, 0x69, + 0xa3, 0x6e, 0xb1, 0xf8, 0xd8, 0x02, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x01, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x2c, 0x57, 0x00, 0x00, 0x02, 0x41, 0xc9, + 0x04, 0xe3, 0x51, 0x85, 0x8b, 0x68, 0x79, 0xed, 0x3f, 0x06, 0xb0, 0xa3, 0x97, 0x8e, 0x8a, 0x18, + 0xd6, 0x4d, 0x72, 0xb4, 0xcc, 0xb2, 0x13, 0xc3, 0x64, 0x76, 0x30, 0xf7, 0x31, 0x82, 0x64, 0x8f, + 0xda, 0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; \ No newline at end of file diff --git a/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_1_0_1/fw_SPECT.h b/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_1_0_1/fw_SPECT.h index 13b03ed00..d4f402e6c 100644 --- a/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_1_0_1/fw_SPECT.h +++ b/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_1_0_1/fw_SPECT.h @@ -5,623 +5,739 @@ /** * @brief SPECT firmware version spect_app-v1.0.0_signed_chunks.bin for bootloader v2.0.1 */ -const uint8_t fw_SPECT[] - = {0x68, 0x3c, 0x3b, 0xe7, 0x56, 0x6d, 0x16, 0x60, 0xaf, 0x2b, 0xcd, 0x92, 0x49, 0xa1, 0x2d, 0xb6, 0xa8, 0x51, 0xa3, - 0xc0, 0x5a, 0x72, 0xa2, 0xe7, 0x26, 0x04, 0xed, 0xb0, 0x73, 0x77, 0x9a, 0x3d, 0x23, 0x60, 0x8a, 0xf9, 0xa9, 0xc5, - 0xe2, 0x46, 0xf3, 0xe1, 0xa7, 0x7b, 0xc7, 0x52, 0x28, 0x67, 0x2e, 0x19, 0x97, 0xe9, 0x61, 0x21, 0x3d, 0x85, 0x44, - 0x5e, 0xee, 0x5f, 0x9d, 0x83, 0x01, 0x29, 0x0b, 0x7b, 0x66, 0xdb, 0xa0, 0x72, 0x77, 0x94, 0x20, 0x4a, 0xe5, 0x92, - 0xa3, 0xb6, 0xef, 0xe9, 0x83, 0x1b, 0x6b, 0xfe, 0xcb, 0x9b, 0xba, 0xbd, 0x27, 0xe7, 0x62, 0x51, 0x03, 0x77, 0xac, - 0x6d, 0x69, 0x02, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x62, 0xc2, 0xed, 0xc8, 0x72, 0x5b, 0x29, 0x22, 0x60, - 0xb7, 0x2b, 0xa4, 0x6d, 0x0a, 0xa6, 0xb9, 0x57, 0x63, 0x34, 0xb9, 0x03, 0x95, 0x53, 0x40, 0xa9, 0x96, 0xaa, 0x40, - 0x0f, 0x44, 0x23, 0x70, 0x2c, 0x00, 0x00, 0x2f, 0x82, 0xf0, 0xe9, 0x8a, 0x1d, 0xf3, 0x23, 0x8f, 0x1d, 0xac, 0x6f, - 0x9d, 0xd2, 0x9c, 0x27, 0x32, 0x09, 0x47, 0xf5, 0x59, 0xf3, 0x54, 0x5b, 0xbf, 0x4f, 0x8b, 0x45, 0x79, 0xa9, 0x37, - 0x1e, 0x57, 0xd4, 0x61, 0xa1, 0xa2, 0x21, 0xea, 0x64, 0x27, 0x05, 0xfd, 0x23, 0xa6, 0x3f, 0x98, 0x2a, 0x8c, 0xd9, - 0x68, 0xa0, 0x93, 0x96, 0x98, 0xba, 0x72, 0x85, 0x9c, 0x02, 0x07, 0xc2, 0x59, 0x0e, 0xfa, 0x06, 0x2e, 0xe1, 0xbf, - 0x70, 0xd9, 0x8b, 0x8f, 0xbb, 0x20, 0xcf, 0x7b, 0x24, 0x49, 0xea, 0xa0, 0x75, 0x17, 0x3a, 0x31, 0xe1, 0xfc, 0x14, - 0x6a, 0xcb, 0x08, 0x48, 0x10, 0x22, 0x9a, 0x84, 0xd4, 0x00, 0x04, 0x00, 0x00, 0x7e, 0xa3, 0xe4, 0xa3, 0x00, 0x82, - 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, 0x40, 0xa2, 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0x82, 0x62, 0xf0, 0x10, 0x88, - 0xa2, 0x20, 0x33, 0x4a, 0xc5, 0x00, 0x10, 0x40, 0x28, 0x2c, 0xa3, 0x00, 0x08, 0x60, 0x40, 0x40, 0x28, 0x4c, 0x80, - 0x00, 0x88, 0x10, 0x40, 0x40, 0xa8, 0x84, 0x80, 0x00, 0x08, 0x40, 0x40, 0x40, 0xa8, 0xb8, 0x80, 0x00, 0x08, 0x70, - 0x40, 0x40, 0xa8, 0x20, 0x81, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0x04, 0xa4, 0x00, 0x82, 0xf4, 0x50, 0x8a, 0x24, - 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x60, 0x10, 0x40, 0x28, 0x1c, 0x9f, 0x00, 0x08, 0x61, 0x10, 0x40, - 0xa8, 0x1c, 0x9f, 0x00, 0x08, 0x62, 0x10, 0x40, 0xa8, 0xa4, 0x9f, 0x00, 0x08, 0x63, 0x10, 0x40, 0x28, 0xb0, 0xa0, - 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0xf3, 0x50, 0x8a, 0xa4, 0x00, 0x50, 0x0a, 0xf3, 0x00, - 0x05, 0x4a, 0x49, 0x11, 0x10, 0x40, 0x28, 0x60, 0xa2, 0x00, 0x08, 0x12, 0x10, 0x40, 0x28, 0x9c, 0xa2, 0x00, 0x08, - 0x13, 0x10, 0x40, 0xa8, 0xbc, 0xa2, 0x00, 0x88, 0x14, 0x10, 0x40, 0x28, 0xe0, 0xa2, 0x00, 0x88, 0x40, 0x81, 0x00, - 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x04, 0xa4, 0x00, 0x82, 0xf2, 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, - 0x4a, 0x49, 0x41, 0x10, 0x40, 0x28, 0x94, 0x8f, 0x00, 0x88, 0x42, 0x10, 0x40, 0x28, 0xac, 0x90, 0x00, 0x88, 0xfa, - 0xcc, 0x83, 0xc8, 0x04, 0xf9, 0x3a, 0x0d, 0xb0, 0x7d, 0x4d, 0xa9, 0x0b, 0x9f, 0xe4, 0x7f, 0x61, 0xc0, 0x88, 0xdd, - 0x82, 0x0e, 0x40, 0xed, 0x0e, 0x2b, 0xae, 0xd7, 0x25, 0x3f, 0x99, 0xe5, 0x89, 0xd8, 0x04, 0x43, 0x10, 0x40, 0xa8, - 0xd4, 0x90, 0x00, 0x88, 0x44, 0x10, 0x40, 0x28, 0x04, 0x91, 0x00, 0x88, 0x45, 0x10, 0x40, 0xa8, 0xfc, 0x91, 0x00, - 0x08, 0x46, 0x10, 0x40, 0xa8, 0xa0, 0x92, 0x00, 0x08, 0x47, 0x10, 0x40, 0x28, 0xf4, 0x92, 0x00, 0x88, 0x48, 0x10, - 0x40, 0x28, 0x30, 0x93, 0x00, 0x88, 0x49, 0x10, 0x40, 0xa8, 0x48, 0x93, 0x00, 0x88, 0x4a, 0x10, 0x40, 0xa8, 0x18, - 0x94, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x04, 0xa4, 0x00, 0x82, 0xf1, 0x50, 0x8a, 0x24, - 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x70, 0x10, 0x40, 0xa8, 0x1c, 0xa1, 0x00, 0x88, 0x40, 0x81, 0x00, - 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x02, 0x00, 0x44, 0x23, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x44, 0x69, 0x00, 0x00, - 0x42, 0xa3, 0xf3, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x40, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xf3, 0x00, - 0x00, 0x00, 0x84, 0x50, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x01, 0x40, 0xc5, - 0x00, 0x00, 0x00, 0xf5, 0x00, 0x00, 0x00, 0xf5, 0xff, 0x00, 0x42, 0xa3, 0x00, 0x10, 0x02, 0xf3, 0xff, 0x10, 0x82, - 0xa4, 0x80, 0x00, 0x80, 0xe2, 0x00, 0x00, 0x00, 0x84, 0xa8, 0xa4, 0x00, 0x18, 0x00, 0x10, 0x02, 0xf3, 0x00, 0x10, - 0x02, 0xf3, 0x80, 0x00, 0x40, 0xe2, 0x00, 0x11, 0x40, 0x49, 0x00, 0x00, 0xc0, 0x93, 0x80, 0x10, 0x84, 0xff, 0x80, - 0x20, 0x86, 0x7f, 0xfa, 0xb4, 0x4f, 0xc7, 0x95, 0x2d, 0xf6, 0x63, 0x09, 0x62, 0xc9, 0xe8, 0x68, 0x63, 0x21, 0x84, - 0xad, 0x79, 0xd2, 0xfb, 0x25, 0x50, 0xd4, 0x59, 0x5a, 0xf2, 0x4d, 0x23, 0x6f, 0xf9, 0x0a, 0xda, 0x20, 0xb0, 0x05, - 0x80, 0x31, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x80, 0x41, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, - 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, - 0x88, 0xff, 0x06, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, - 0xe0, 0x7d, 0xa4, 0xdc, 0x81, 0x00, 0x8a, 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x0f, 0x00, 0x7c, 0x23, - 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0xfc, 0x81, 0x00, - 0x0a, 0x80, 0x42, 0x8c, 0xff, 0x00, 0x63, 0x88, 0xff, 0x3f, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, - 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0x1c, 0x82, 0x00, 0x8a, 0x00, 0x43, 0x8a, 0xff, 0x80, - 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x1e, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, - 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0x40, 0x82, 0x00, 0x8a, 0x00, 0x43, 0x88, 0x7f, 0x40, 0x30, 0x4a, - 0xc5, 0x80, 0x00, 0x7c, 0xa3, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x50, 0x0a, 0x63, 0x80, 0x82, - 0x00, 0x8c, 0x00, 0x50, 0x0a, 0x63, 0x94, 0x82, 0x00, 0x0e, 0x80, 0x40, 0x88, 0xff, 0x94, 0x82, 0x00, 0x98, 0x00, - 0x50, 0x0a, 0x63, 0x90, 0x82, 0x00, 0x0c, 0xfa, 0xff, 0xc4, 0xcd, 0xa1, 0x38, 0x8c, 0x9d, 0xc1, 0x79, 0xde, 0xea, - 0xc4, 0x13, 0x04, 0xdb, 0x6f, 0x36, 0x9d, 0xcc, 0x1a, 0xb9, 0xe7, 0x9b, 0x02, 0x46, 0x13, 0x86, 0x23, 0xb7, 0xe6, - 0xde, 0x15, 0x88, 0x06, 0x00, 0x41, 0x88, 0xff, 0x94, 0x82, 0x00, 0x98, 0x80, 0x41, 0x88, 0x7f, 0x02, 0xe0, 0x7d, - 0x24, 0x60, 0x82, 0x00, 0x0a, 0x00, 0x40, 0x42, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x86, 0xef, 0x80, 0x30, - 0x88, 0xef, 0x00, 0x42, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, 0x80, - 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x31, 0x86, 0x6f, 0x80, 0x31, 0x86, 0xef, - 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x8a, 0x6f, 0x80, 0x52, 0x86, 0xef, 0x09, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, - 0xef, 0x01, 0xe0, 0x7d, 0x24, 0xe0, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x86, 0xef, 0x0a, 0x00, 0x7c, 0x23, 0x80, 0x31, - 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x02, 0xe0, 0x7d, 0x24, 0xf4, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x8a, 0xef, 0x80, - 0x52, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, - 0x1e, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, - 0xa4, 0x20, 0x83, 0x00, 0x0a, 0x80, 0x30, 0x86, 0x6f, 0x80, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, - 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x04, 0xe0, 0x7d, 0x24, 0x3c, 0x83, 0x00, 0x8a, 0x00, - 0x31, 0x86, 0x6f, 0x20, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, 0xfa, 0xbf, 0xbc, 0x7c, 0x5f, 0xb1, 0x46, 0xcb, - 0xf3, 0xd8, 0x1d, 0x3d, 0x06, 0x92, 0x4a, 0x99, 0x56, 0xe9, 0x4a, 0x28, 0x36, 0x84, 0xfb, 0x20, 0xca, 0xc0, 0xfb, - 0x43, 0x16, 0x0e, 0xc2, 0xfc, 0xb7, 0x60, 0x07, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, - 0xef, 0x04, 0xe0, 0x7d, 0x24, 0x5c, 0x83, 0x00, 0x8a, 0x00, 0x31, 0x86, 0x6f, 0x1e, 0x00, 0x7c, 0x23, 0x80, 0x31, - 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, 0x7c, 0x83, 0x00, 0x0a, 0x80, - 0x32, 0x86, 0xef, 0x00, 0x00, 0x00, 0x84, 0xa4, 0x82, 0x00, 0x02, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, - 0x80, 0x30, 0x82, 0xef, 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x84, 0xe7, 0x80, 0x20, 0x88, 0xe7, 0x00, 0x42, 0x86, - 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x41, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, - 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x07, 0x00, 0x7c, 0xa3, 0x80, - 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xdc, 0x83, 0x00, 0x0a, 0x80, 0x21, 0x8a, 0xe7, 0x80, 0x52, 0x86, 0x67, - 0x0f, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xf4, 0x83, 0x00, 0x0a, 0x80, 0x51, 0x84, - 0xe7, 0x00, 0x21, 0x86, 0x67, 0x0f, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x0c, 0x84, - 0x00, 0x0a, 0x80, 0x51, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x22, 0x8a, 0x67, 0x80, - 0x52, 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xfa, 0xc0, 0x24, 0xe4, - 0xe7, 0x5b, 0x5f, 0x6b, 0x41, 0xe9, 0x19, 0xa6, 0x89, 0x62, 0x86, 0xff, 0xbd, 0x80, 0x38, 0xf7, 0x1e, 0x02, 0xa0, - 0xbb, 0x29, 0x20, 0xb1, 0xd7, 0x7a, 0x0e, 0x7a, 0x03, 0x71, 0x38, 0x08, 0x30, 0x84, 0x00, 0x0a, 0x80, 0x51, 0x84, - 0xe7, 0x00, 0x21, 0x86, 0x67, 0x63, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x48, 0x84, - 0x00, 0x0a, 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0x67, 0x01, - 0xe0, 0x7d, 0x24, 0x60, 0x84, 0x00, 0x0a, 0x80, 0x32, 0x84, 0xe7, 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, 0x00, 0x02, - 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x30, 0x86, 0xe7, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, - 0x67, 0x80, 0x31, 0x86, 0x67, 0x00, 0x32, 0x82, 0x67, 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, - 0x80, 0x67, 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, - 0x00, 0x80, 0x67, 0x00, 0x21, 0x84, 0xe7, 0x80, 0x20, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x32, 0x48, 0x45, - 0x00, 0x22, 0x86, 0x67, 0x00, 0x21, 0x88, 0xe7, 0x80, 0x40, 0x88, 0xe8, 0xdc, 0x84, 0x00, 0x8a, 0x00, 0x20, 0x42, - 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x30, 0x42, 0x63, 0x00, 0x00, 0x00, 0x84, 0x00, 0x90, 0x42, 0x63, 0x74, 0x84, - 0x00, 0x82, 0x80, 0x70, 0x8e, 0xe7, 0x80, 0x80, 0x90, 0xe7, 0x01, 0x00, 0x42, 0x23, 0x80, 0x70, 0x8e, 0xe2, 0x00, - 0x80, 0x10, 0xeb, 0x80, 0x83, 0x90, 0xe4, 0x00, 0x80, 0x10, 0xed, 0x00, 0x80, 0x10, 0xf9, 0x00, 0x00, 0x00, 0x84, - 0xfa, 0xf1, 0x25, 0xa3, 0x1c, 0x81, 0xe5, 0x61, 0x6e, 0x97, 0xbe, 0x09, 0xcd, 0xfa, 0x69, 0xa9, 0xe3, 0x4f, 0x0c, - 0x6e, 0x6e, 0xc5, 0x16, 0x7c, 0x73, 0x95, 0xa1, 0x1f, 0xf0, 0xd8, 0x76, 0xff, 0x7a, 0x10, 0x09, 0x00, 0xc0, 0x60, - 0x63, 0x00, 0x00, 0x21, 0x63, 0x24, 0x85, 0x00, 0x8c, 0x00, 0x00, 0x6c, 0xa3, 0x2c, 0x85, 0x00, 0x18, 0x01, 0x00, - 0x6c, 0x23, 0x2c, 0x85, 0x00, 0x18, 0x00, 0x00, 0x21, 0x65, 0x00, 0x00, 0x59, 0x63, 0x00, 0x08, 0xa1, 0xe7, 0x01, - 0x00, 0x42, 0x23, 0x80, 0x00, 0xa9, 0xfd, 0x00, 0x03, 0xa1, 0x67, 0x80, 0x00, 0xab, 0x7b, 0x80, 0x5a, 0xa5, 0x67, - 0x80, 0x2a, 0xa5, 0xe7, 0x00, 0x2a, 0xa7, 0xe7, 0x00, 0x29, 0xa5, 0x67, 0x80, 0x2a, 0xa5, 0xe7, 0x00, 0x2a, 0x83, - 0xe7, 0x00, 0x10, 0x60, 0xe3, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0xa4, 0x67, 0x00, 0x29, 0xa5, 0x67, 0x00, 0x28, - 0xa5, 0xe7, 0x80, 0x29, 0xa5, 0xe7, 0x00, 0x29, 0xa1, 0xe7, 0x80, 0x0a, 0xa1, 0xe7, 0x00, 0x32, 0x42, 0x45, 0x80, - 0x20, 0xa3, 0xe7, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x0a, 0xbd, 0xe8, 0x9c, 0x85, 0x00, 0x8a, 0x00, 0x20, 0x41, 0xe3, - 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x7c, 0x23, 0x00, 0xea, 0xa9, 0xfd, 0x00, 0x0a, 0xbd, 0xe8, 0xb4, 0x85, 0x00, - 0x8a, 0x00, 0x10, 0x41, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, 0x88, 0x00, 0x00, - 0x42, 0xa3, 0x00, 0xe0, 0xbd, 0x68, 0xcc, 0x85, 0x00, 0x8a, 0x01, 0x10, 0x82, 0x24, 0x01, 0x60, 0x41, 0xa8, 0xd8, - 0x85, 0x00, 0x8a, 0x02, 0x10, 0x82, 0x24, 0x03, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, 0x88, 0x00, 0x00, 0x46, 0x23, - 0x00, 0x30, 0x86, 0xfd, 0xfa, 0x4f, 0x66, 0x67, 0xf6, 0x00, 0xe1, 0x5b, 0x14, 0xf0, 0x6a, 0x37, 0xf6, 0xd8, 0x91, - 0x81, 0x5b, 0xe4, 0x55, 0xaa, 0x34, 0x3f, 0xfe, 0xb8, 0x3d, 0x89, 0x0a, 0x42, 0x06, 0x3f, 0xfa, 0x89, 0xba, 0xe8, - 0x09, 0x01, 0x00, 0x7c, 0xa3, 0x00, 0x0f, 0x82, 0xe2, 0x00, 0x1b, 0x40, 0x68, 0x00, 0x86, 0x00, 0x8a, 0x00, 0x00, - 0x56, 0x63, 0x08, 0x86, 0x00, 0x18, 0x00, 0x30, 0x56, 0x63, 0x08, 0x86, 0x00, 0x18, 0x00, 0x00, 0x42, 0xa3, 0x00, - 0x00, 0x00, 0x84, 0xff, 0x0f, 0x42, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x80, 0x83, 0x80, 0xfd, 0x80, 0xc5, 0x82, 0xfd, - 0x80, 0x00, 0x80, 0xe7, 0x80, 0x83, 0x82, 0x7b, 0x80, 0xc5, 0x84, 0xfb, 0x00, 0x11, 0x82, 0xe7, 0x00, 0xa7, 0x84, - 0x67, 0x00, 0x23, 0x84, 0x67, 0x00, 0x21, 0x84, 0x7b, 0x80, 0x96, 0x86, 0xe7, 0x80, 0x31, 0x86, 0xfb, 0x00, 0x10, - 0x88, 0xfd, 0x00, 0x10, 0x80, 0x7b, 0x00, 0x31, 0x82, 0xfd, 0x00, 0x31, 0x84, 0xfb, 0x80, 0x40, 0x96, 0xe7, 0x00, - 0x40, 0x9c, 0x67, 0x00, 0x20, 0x98, 0xe7, 0x80, 0x20, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x80, 0x73, 0x80, 0x67, - 0x00, 0x84, 0x82, 0xe7, 0x80, 0x94, 0x84, 0xe7, 0x00, 0x21, 0x84, 0x7b, 0x80, 0x00, 0x86, 0x7b, 0x00, 0x74, 0x88, - 0x7b, 0x00, 0x42, 0x88, 0xe7, 0x00, 0x32, 0x88, 0xfd, 0x80, 0x00, 0x80, 0x7d, 0x00, 0x20, 0x82, 0xfb, 0x80, 0x40, - 0x8e, 0xe7, 0x80, 0x00, 0x92, 0xe7, 0x80, 0x01, 0x90, 0xe7, 0x80, 0x41, 0x94, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x00, - 0x00, 0x4e, 0xa3, 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, 0xa3, - 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xb0, 0x4e, 0x67, 0xfa, 0xdd, 0x19, 0xf8, 0x69, 0x43, 0xbb, 0xb9, 0x84, 0xe0, 0xde, - 0xf4, 0xd2, 0x3f, 0x9e, 0x4d, 0xa8, 0xd6, 0x61, 0xe7, 0x9a, 0x34, 0x04, 0x99, 0xab, 0x79, 0xc9, 0x94, 0x5c, 0x1e, - 0x16, 0xaa, 0x78, 0xc0, 0x0a, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, - 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, - 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0xb8, 0x86, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x56, 0xc9, - 0x20, 0x05, 0x58, 0xc9, 0x40, 0x05, 0x5a, 0x49, 0x00, 0x00, 0x4e, 0xa3, 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, - 0xa3, 0x00, 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xde, 0xf3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xd0, - 0x3b, 0xeb, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, - 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, - 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x14, 0x87, 0x00, 0x0a, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xf0, 0x1e, - 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, - 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, - 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x50, 0x87, 0x00, 0x0a, 0x00, 0x00, 0x7c, 0x23, - 0x80, 0xe3, 0x8f, 0xfd, 0x00, 0xe5, 0x95, 0xfd, 0x18, 0x86, 0x00, 0x02, 0xfa, 0xcb, 0xbe, 0x52, 0xdc, 0x6f, 0xb6, - 0x98, 0x09, 0x99, 0xb7, 0x24, 0xc2, 0x56, 0x10, 0xa9, 0x4c, 0x33, 0x6c, 0x10, 0x4d, 0x7e, 0x8e, 0x10, 0x81, 0x2d, - 0x05, 0xf1, 0x7a, 0xc8, 0xd2, 0xb6, 0x69, 0x98, 0x0b, 0x80, 0xe3, 0x8f, 0xfd, 0x00, 0xe5, 0x95, 0xfd, 0x00, 0x05, - 0x40, 0x45, 0x20, 0x05, 0x42, 0x45, 0x40, 0x05, 0x44, 0x45, 0x80, 0x06, 0x80, 0xe7, 0x80, 0x16, 0x82, 0xe7, 0x00, - 0xb1, 0x96, 0xe7, 0x00, 0xc1, 0x98, 0xe7, 0x80, 0x05, 0xbc, 0xe8, 0xd4, 0x87, 0x00, 0x0a, 0x00, 0x16, 0xbc, 0xe8, - 0xd4, 0x87, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, - 0x84, 0x40, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, - 0xae, 0x24, 0x80, 0x5b, 0xab, 0x67, 0x00, 0x5b, 0xb1, 0x67, 0x80, 0x6b, 0xad, 0x67, 0x98, 0x96, 0x00, 0x02, 0x80, - 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, - 0x00, 0x02, 0x56, 0x49, 0x20, 0x02, 0x58, 0x49, 0x40, 0x02, 0x5a, 0xc9, 0x60, 0x02, 0x5c, 0x49, 0xf0, 0x86, 0x00, - 0x02, 0x00, 0x00, 0x40, 0xa8, 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0x02, - 0x56, 0x45, 0x20, 0x02, 0x58, 0x45, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, 0x45, 0x00, 0x02, 0x4e, 0x49, 0x20, - 0x02, 0x50, 0xc9, 0x40, 0x02, 0x52, 0x49, 0x60, 0x02, 0x54, 0xc9, 0x00, 0x50, 0x4f, 0xe3, 0x00, 0x60, 0x51, 0xe3, - 0x00, 0x70, 0x53, 0xe3, 0x00, 0x80, 0x55, 0xe3, 0x00, 0x00, 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, 0xfa, 0xbd, 0xd2, - 0x17, 0x3a, 0x7e, 0x35, 0x06, 0x80, 0x7c, 0xa9, 0x13, 0x27, 0x2c, 0x51, 0x5b, 0xde, 0xea, 0xe8, 0x1b, 0x60, 0xf7, - 0x53, 0xa7, 0x77, 0xd2, 0xb5, 0x02, 0x33, 0x27, 0x4b, 0x60, 0x2d, 0x70, 0x0c, 0x00, 0x07, 0x9c, 0xfd, 0x18, 0x86, - 0x00, 0x02, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xa0, - 0x31, 0x4c, 0xc5, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, - 0x08, 0x89, 0x00, 0x0a, 0x00, 0x02, 0x56, 0x45, 0x20, 0x02, 0x58, 0x45, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, - 0x45, 0x18, 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0x00, 0xe0, - 0x54, 0x63, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, 0x74, 0x84, 0x00, 0x82, 0x80, - 0xb0, 0xaa, 0xe7, 0x80, 0xc0, 0xac, 0x67, 0x80, 0x5a, 0x83, 0xe7, 0x00, 0x6b, 0x85, 0xe7, 0x80, 0x20, 0x86, 0xfd, - 0x00, 0x11, 0x88, 0xe7, 0x00, 0x43, 0x88, 0x67, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x40, 0x88, 0xfb, 0x00, 0x32, 0x80, - 0xe8, 0x08, 0x89, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, - 0x00, 0x84, 0x80, 0x73, 0x80, 0x67, 0x00, 0x84, 0x82, 0xe7, 0x80, 0x94, 0x84, 0xe7, 0x00, 0x10, 0x86, 0x7d, 0x00, - 0x31, 0x86, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x03, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x01, 0x80, 0x7b, - 0x00, 0x30, 0x86, 0x68, 0x48, 0x89, 0x00, 0x8a, 0x00, 0x74, 0x80, 0x67, 0x00, 0x95, 0x86, 0x67, 0x00, 0x30, 0x86, - 0x68, 0xfa, 0xc8, 0xec, 0x1b, 0x0c, 0x7f, 0xc1, 0xd2, 0x5c, 0x08, 0x1d, 0xda, 0xdb, 0x7c, 0x0d, 0xda, 0xdc, 0x0c, - 0x79, 0x28, 0xdc, 0x82, 0xda, 0xe5, 0x03, 0x70, 0x2a, 0x84, 0x4a, 0xb8, 0xb9, 0xda, 0x91, 0x48, 0x0d, 0x00, 0x00, - 0x00, 0x84, 0x00, 0x96, 0x80, 0xef, 0x80, 0xa6, 0x82, 0xef, 0x00, 0xb7, 0x84, 0x6f, 0x00, 0x95, 0x86, 0xfb, 0x80, - 0xc6, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x6f, 0x80, 0x00, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x7d, 0x80, 0xa5, 0x88, 0xfb, - 0x00, 0xd7, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xef, 0x00, 0x11, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xfd, 0x80, 0x95, 0x8a, - 0x7b, 0x00, 0xc7, 0x8c, 0x7b, 0x00, 0x53, 0x8a, 0xef, 0x00, 0x01, 0x8c, 0x7b, 0x00, 0x53, 0x8c, 0xfd, 0x00, 0x81, - 0x8e, 0x6f, 0x80, 0x63, 0x8a, 0x7d, 0x80, 0x52, 0x8e, 0x7b, 0x80, 0x53, 0x8a, 0x7b, 0x80, 0x12, 0x8e, 0xfd, 0x80, - 0x12, 0x8a, 0x7b, 0x00, 0x83, 0x8c, 0x6f, 0x00, 0x21, 0x82, 0x7b, 0x00, 0x11, 0x84, 0x7b, 0x00, 0x61, 0x8c, 0x7d, - 0x00, 0x60, 0x8c, 0xfd, 0x00, 0x63, 0x82, 0x7b, 0x00, 0x13, 0x8c, 0x7b, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x80, - 0x7b, 0x00, 0x01, 0x80, 0x7d, 0x00, 0x43, 0x82, 0xef, 0x00, 0x03, 0x84, 0x6f, 0x80, 0x53, 0x8c, 0x6f, 0x00, 0x61, - 0x9a, 0xfb, 0x80, 0x32, 0x8a, 0xef, 0x80, 0x50, 0x98, 0x7d, 0x80, 0x43, 0x8e, 0x6f, 0x00, 0x30, 0x82, 0x6f, 0x80, - 0x70, 0x9c, 0x7b, 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0xef, 0x00, 0xa5, 0x82, 0x6f, 0x80, 0xb5, 0x84, 0x6f, - 0x00, 0x95, 0x86, 0xef, 0x80, 0x31, 0x86, 0xfb, 0x80, 0x95, 0x8e, 0xef, 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x81, 0x8c, - 0xef, 0x80, 0x63, 0x8c, 0x7d, 0xfa, 0xb6, 0x33, 0x06, 0x98, 0x5a, 0x9e, 0x93, 0xec, 0x78, 0x10, 0xb5, 0xc0, 0x90, - 0x83, 0x0a, 0xbd, 0x73, 0x2c, 0x54, 0xd0, 0x1b, 0x01, 0xfb, 0x7a, 0xa3, 0xec, 0x5f, 0x89, 0x81, 0xda, 0x3b, 0xc2, - 0x20, 0x0e, 0x00, 0x63, 0x8a, 0xfb, 0x00, 0x53, 0x8c, 0xfb, 0x00, 0x13, 0x8a, 0x7d, 0x00, 0x13, 0x8c, 0x7b, 0x00, - 0x53, 0x8c, 0xef, 0x80, 0x51, 0x8a, 0xef, 0x00, 0x21, 0x86, 0xfb, 0x80, 0x21, 0x84, 0xfb, 0x80, 0x83, 0x8e, 0x6f, - 0x00, 0x71, 0x8e, 0x7d, 0x00, 0x70, 0x8e, 0xfd, 0x80, 0x73, 0x86, 0xfb, 0x80, 0x71, 0x8e, 0xfb, 0x00, 0x00, 0x86, - 0xfb, 0x00, 0x30, 0x80, 0xfb, 0x00, 0x01, 0x80, 0x7d, 0x80, 0x03, 0x80, 0x6f, 0x00, 0x60, 0x8c, 0xfb, 0x80, 0xa5, - 0x80, 0x6f, 0x00, 0x00, 0x80, 0xfb, 0x80, 0x03, 0x8e, 0xef, 0x80, 0x53, 0x8a, 0x7d, 0x80, 0x00, 0x8e, 0xef, 0x80, - 0x73, 0x8e, 0x7b, 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x50, 0x52, 0xe3, 0x00, 0x60, 0x54, 0xe3, 0x00, 0x70, 0x56, 0xe3, - 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, 0x00, 0x56, 0xa3, 0x00, 0x01, 0x7c, - 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, - 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, - 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xa8, 0x8a, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x58, 0x49, - 0x20, 0x05, 0x5a, 0x49, 0x40, 0x05, 0x5c, 0x49, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, 0x00, 0x56, - 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xde, 0xf3, 0xfa, 0xa3, 0xe2, 0x5f, 0x46, 0x88, 0xc2, 0xbe, 0x0e, 0x87, - 0x12, 0x96, 0xe2, 0x9a, 0x63, 0xb1, 0x9c, 0xf3, 0x88, 0x06, 0xd7, 0x2a, 0xa1, 0x58, 0xb4, 0xe7, 0x5f, 0xc7, 0xbf, - 0x2f, 0xc2, 0x63, 0x28, 0xf8, 0x0e, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, - 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, - 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xf8, 0x8a, 0x00, 0x0a, 0x00, 0x01, 0x7c, - 0xa3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, - 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, - 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x2c, 0x8b, 0x00, 0x8a, 0x00, 0x00, 0x7c, 0x23, 0x00, 0xe5, 0x95, 0xfd, - 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe5, 0x95, 0xfd, 0x00, 0x05, 0x40, 0x45, 0x20, 0x05, 0x42, 0x45, 0x40, 0x05, 0x44, - 0x45, 0x00, 0x07, 0x80, 0x6f, 0x00, 0x17, 0x82, 0x6f, 0x00, 0xc1, 0x98, 0x6f, 0x00, 0xd1, 0x9a, 0x6f, 0x00, 0x06, - 0xbc, 0x68, 0xa0, 0x8b, 0x00, 0x0a, 0x80, 0x16, 0xbc, 0x68, 0xa0, 0x8b, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, - 0x00, 0x00, 0x84, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x30, 0x7e, 0xc5, 0x00, 0x00, 0xc4, 0x73, - 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xb0, 0x24, 0x00, 0x6c, 0xad, 0xef, 0x00, 0x7c, 0xaf, - 0xef, 0xc8, 0x97, 0x00, 0x82, 0x00, 0x10, 0x53, 0xe3, 0x00, 0x20, 0x55, 0xe3, 0xfa, 0x70, 0x8b, 0x4d, 0xbb, 0xd1, - 0x84, 0x9b, 0xed, 0x5b, 0xc4, 0xa6, 0x4a, 0xcc, 0x3b, 0xae, 0x49, 0xdd, 0x58, 0x59, 0xc1, 0x52, 0x10, 0x1e, 0xa1, - 0x83, 0x5a, 0x5f, 0x94, 0xb5, 0x32, 0xf7, 0x64, 0xd0, 0x0f, 0x00, 0x30, 0x57, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0x94, - 0x8c, 0x00, 0x0a, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x00, 0x30, 0x7e, 0xc5, - 0x80, 0x30, 0x50, 0x45, 0x00, 0x10, 0x59, 0xe3, 0x00, 0x20, 0x5b, 0x63, 0x00, 0x30, 0x5d, 0xe3, 0xd8, 0x8a, 0x00, - 0x02, 0x00, 0x00, 0x40, 0xa8, 0x94, 0x8c, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0x00, - 0x80, 0x68, 0x00, 0x60, 0x53, 0x6f, 0x00, 0x70, 0x55, 0xef, 0x00, 0x80, 0x57, 0x6f, 0x00, 0x10, 0x59, 0xe3, 0x00, - 0x20, 0x5b, 0x63, 0x00, 0x30, 0x5d, 0xe3, 0x80, 0x06, 0x9a, 0xfd, 0x4c, 0x89, 0x00, 0x82, 0x20, 0x30, 0x7e, 0x45, - 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, - 0xa8, 0x94, 0x8c, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0x60, 0x59, 0x63, 0x00, 0x70, - 0x5b, 0x63, 0x00, 0x80, 0x5d, 0x63, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xc0, 0x52, 0xe3, 0x00, 0xd0, 0x54, 0x63, 0x00, - 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0xe0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, - 0x80, 0xc0, 0xac, 0xef, 0x80, 0xd0, 0xae, 0xef, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, - 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x30, 0x40, 0x45, 0x80, 0x30, 0x42, 0x45, 0x00, 0xa5, 0x86, 0xef, 0xfa, 0x5f, - 0x9e, 0xb7, 0xbe, 0x7e, 0x7c, 0x23, 0x30, 0x8b, 0x71, 0xe9, 0xe3, 0x42, 0x70, 0xb5, 0xc0, 0x51, 0x72, 0x60, 0x89, - 0xae, 0x4e, 0x48, 0x1a, 0xd1, 0x57, 0x0b, 0xd2, 0x9b, 0xfd, 0xbd, 0x4d, 0xa8, 0x10, 0x80, 0x35, 0x86, 0x6f, 0x80, - 0x94, 0x84, 0x6f, 0x80, 0x24, 0x84, 0xef, 0x80, 0xb5, 0x88, 0x6f, 0x80, 0x45, 0x8a, 0xef, 0x80, 0x04, 0x80, 0xef, - 0x00, 0x02, 0x80, 0x6f, 0x80, 0x12, 0x82, 0xef, 0x80, 0x00, 0x80, 0x7b, 0x00, 0x01, 0x80, 0x7b, 0x80, 0x01, 0x80, - 0x68, 0x00, 0x00, 0x00, 0x84, 0x60, 0x32, 0x40, 0xc5, 0x00, 0x08, 0x80, 0xe7, 0x00, 0x08, 0x83, 0xe7, 0x00, 0x10, - 0x82, 0xfb, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x10, 0x82, 0xfb, 0x00, 0x18, 0x82, 0xe7, 0x98, 0x84, 0x00, 0x02, 0x00, - 0x10, 0x62, 0x63, 0x01, 0x00, 0x44, 0x23, 0x00, 0x20, 0x84, 0x70, 0x00, 0x01, 0x84, 0x62, 0x00, 0x00, 0x00, 0x84, - 0xc0, 0x32, 0x68, 0xc5, 0xe0, 0x32, 0x6a, 0xc5, 0xa0, 0x32, 0x6c, 0x45, 0x00, 0x64, 0x8b, 0x67, 0x80, 0x53, 0x8a, - 0x7b, 0x00, 0x66, 0x8d, 0xe7, 0x80, 0x65, 0x8c, 0x7b, 0x00, 0x53, 0x80, 0x67, 0x80, 0x96, 0x82, 0x67, 0x00, 0x86, - 0x84, 0x67, 0x80, 0x54, 0x86, 0xfb, 0x80, 0x66, 0x88, 0xfb, 0x00, 0x32, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, 0x00, - 0x32, 0x86, 0x7d, 0x00, 0x54, 0x88, 0xfb, 0x00, 0x66, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0x67, 0x00, 0x01, 0x8a, 0x7b, - 0x80, 0x42, 0x88, 0xfd, 0x00, 0x94, 0x8a, 0x7b, 0x00, 0xd6, 0x96, 0xfb, 0x80, 0x55, 0x8a, 0xe7, 0x00, 0x11, 0x96, - 0x7b, 0x80, 0x55, 0x8a, 0x7d, 0x00, 0x42, 0x99, 0xe7, 0x00, 0x51, 0x97, 0xe7, 0x00, 0xb6, 0x98, 0x7b, 0x00, 0x16, - 0x96, 0xfd, 0xfa, 0x87, 0x7f, 0x45, 0xce, 0x1d, 0x8c, 0x9a, 0x86, 0x28, 0x4f, 0x1f, 0x3e, 0xb6, 0xb5, 0xf2, 0xe6, - 0xcc, 0xb3, 0xcb, 0x93, 0x0d, 0x0f, 0x85, 0x09, 0x2d, 0xb7, 0x00, 0x21, 0xe1, 0xf5, 0x67, 0x63, 0x80, 0x11, 0x00, - 0x16, 0x98, 0x7b, 0x00, 0xb6, 0x9a, 0x67, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x82, 0xfb, 0x00, 0x41, 0x85, 0x67, - 0x00, 0x52, 0x89, 0xe7, 0x00, 0x11, 0x82, 0x7b, 0x00, 0x01, 0x84, 0xfd, 0x00, 0x41, 0x85, 0x67, 0x00, 0x41, 0x88, - 0x7b, 0x00, 0x12, 0x80, 0x67, 0x00, 0xd0, 0x9a, 0xfb, 0x00, 0x52, 0x80, 0xe7, 0x80, 0x35, 0x96, 0x67, 0x00, 0xb0, - 0x96, 0xfd, 0x80, 0x30, 0x80, 0xe7, 0x00, 0x56, 0x98, 0x67, 0x00, 0xc0, 0x98, 0xfb, 0x00, 0x66, 0xad, 0x67, 0x00, - 0xbb, 0x96, 0x7d, 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0x67, 0x00, 0x04, 0x80, 0xe7, 0x60, 0x32, 0x42, 0x45, - 0x80, 0x13, 0x82, 0xe7, 0x00, 0x14, 0x82, 0x7b, 0x00, 0x14, 0x82, 0xe7, 0x80, 0x73, 0x84, 0xe7, 0x00, 0x11, 0x82, - 0x7b, 0x80, 0x13, 0x82, 0xe7, 0x80, 0x00, 0x80, 0xe8, 0x00, 0x00, 0x00, 0x84, 0x00, 0x74, 0x80, 0xfb, 0x00, 0x95, - 0x82, 0x7d, 0x00, 0x10, 0x82, 0x67, 0x00, 0x74, 0x80, 0xfd, 0x00, 0x95, 0x84, 0x7b, 0x00, 0x20, 0x84, 0x67, 0x00, - 0x11, 0x86, 0xfb, 0x80, 0x31, 0x86, 0x67, 0x00, 0x11, 0x88, 0x7d, 0x00, 0x42, 0x88, 0xe7, 0x00, 0x36, 0x92, 0x67, - 0x00, 0xb2, 0x94, 0x67, 0x00, 0x00, 0x00, 0x84, 0x00, 0x74, 0x82, 0x7b, 0x80, 0x10, 0x82, 0xe7, 0x00, 0x74, 0x84, - 0x7d, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x11, 0x8e, 0xe7, 0x00, 0x11, 0x82, 0x7d, 0x80, 0x60, 0x86, 0xe7, 0x00, 0x31, - 0x86, 0x7b, 0x80, 0x11, 0x90, 0x67, 0xfa, 0x6e, 0xd6, 0x93, 0xd7, 0x8f, 0x36, 0x11, 0x4d, 0x20, 0x25, 0x07, 0x88, - 0x7b, 0x9b, 0x49, 0x49, 0x78, 0xc9, 0x5b, 0xb4, 0x93, 0x04, 0xf0, 0x28, 0xb3, 0x50, 0xe5, 0x88, 0x8a, 0x40, 0x70, - 0x43, 0x58, 0x12, 0x00, 0x00, 0x00, 0x84, 0x80, 0x32, 0x4c, 0x45, 0x00, 0xb0, 0x52, 0x63, 0x00, 0xc0, 0x54, 0xe3, - 0x01, 0x00, 0x4e, 0x23, 0x00, 0x00, 0x50, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xf6, 0xf3, 0x00, 0xb0, 0x37, - 0xeb, 0x00, 0xd0, 0x3b, 0xeb, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, - 0x00, 0x02, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x78, 0x8e, 0x00, 0x0a, 0x00, - 0x01, 0x7c, 0xa3, 0x00, 0xb0, 0x37, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, - 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, 0x00, 0x02, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, - 0x24, 0xa4, 0x8e, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x76, 0x80, 0xe7, 0x00, 0xb4, 0x82, 0xe7, 0x00, 0x86, - 0x84, 0x67, 0x60, 0x32, 0x4c, 0xc5, 0x00, 0x63, 0x86, 0xfb, 0x00, 0x31, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, 0x80, - 0x41, 0x88, 0xfb, 0x80, 0xb3, 0x8a, 0x67, 0x00, 0x51, 0x8a, 0x7b, 0x80, 0x42, 0x88, 0x67, 0x00, 0x31, 0x86, 0xe7, - 0x80, 0x41, 0x88, 0xfd, 0x00, 0x45, 0x88, 0x67, 0x80, 0x00, 0x82, 0xfd, 0x80, 0x10, 0x82, 0xe7, 0x80, 0x14, 0x82, - 0x67, 0x80, 0x40, 0x92, 0xfd, 0x80, 0xd6, 0x86, 0xfb, 0x00, 0x34, 0x86, 0xe7, 0x00, 0x35, 0x86, 0x67, 0x00, 0x30, - 0x8e, 0xe7, 0x00, 0x31, 0x90, 0x67, 0x00, 0x00, 0x00, 0x84, 0xfa, 0xe7, 0x81, 0x25, 0x2d, 0x95, 0xbf, 0x2e, 0xb5, - 0xcc, 0xe0, 0x6a, 0xa2, 0xd1, 0xc6, 0x3a, 0x48, 0xe8, 0x21, 0x75, 0xa9, 0x46, 0x3a, 0xab, 0x75, 0x56, 0xdc, 0xa3, - 0x14, 0x49, 0x6e, 0x41, 0xd3, 0x30, 0x13, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0x00, 0x42, 0xa3, - 0x00, 0xe0, 0x45, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x47, 0xe5, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x49, - 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4b, 0xe5, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4d, 0xe5, 0x00, 0x20, - 0x04, 0xf9, 0x00, 0x30, 0x06, 0xf9, 0x00, 0x40, 0x08, 0xf9, 0x00, 0x50, 0x0a, 0xf9, 0x00, 0x60, 0x0c, 0xf9, 0x00, - 0x00, 0x00, 0x84, 0x00, 0x11, 0x02, 0xfd, 0x80, 0x21, 0x04, 0x7d, 0x00, 0x32, 0x06, 0xfd, 0x80, 0x42, 0x08, 0x7d, - 0x00, 0x53, 0x0a, 0x7d, 0x00, 0x60, 0x0c, 0xf3, 0x00, 0x00, 0x00, 0x84, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, - 0x22, 0x00, 0x40, 0x44, 0xe5, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x20, 0x2c, 0x63, 0x01, 0x60, 0x6b, 0x22, 0x00, 0x00, - 0x42, 0xa3, 0x04, 0x54, 0xe1, 0x35, 0x88, 0x90, 0x00, 0x9c, 0xff, 0x00, 0x40, 0x23, 0x00, 0x00, 0xa3, 0xe2, 0x02, - 0x10, 0x41, 0x28, 0x94, 0x90, 0x00, 0x8a, 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0x21, 0xf5, - 0x00, 0x00, 0xa3, 0xe2, 0x00, 0x20, 0x84, 0x62, 0x00, 0x11, 0x41, 0xe8, 0xa0, 0x90, 0x00, 0x0a, 0x05, 0x54, 0xf3, - 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x00, 0x03, 0x72, 0xc9, 0x05, 0x54, 0xc1, 0x39, 0x88, 0x90, 0x00, 0x9c, 0x00, 0x60, - 0x6b, 0xe3, 0x00, 0x54, 0xf5, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x01, 0x54, 0xef, 0xb5, 0xfa, 0x7e, 0x26, 0x68, 0x69, - 0x51, 0x4e, 0xa7, 0x96, 0xb2, 0x5f, 0x71, 0x3f, 0x4c, 0x46, 0x7d, 0x13, 0xfb, 0xc1, 0xbe, 0x4b, 0xa8, 0x01, 0x84, - 0x85, 0xfc, 0x5d, 0x70, 0x65, 0x0a, 0xb2, 0xb7, 0xeb, 0x08, 0x14, 0x88, 0x90, 0x00, 0x9c, 0x02, 0x54, 0xfb, 0xb5, - 0x88, 0x90, 0x00, 0x9c, 0x03, 0x54, 0xfd, 0x35, 0x88, 0x90, 0x00, 0x9c, 0x05, 0x54, 0xc1, 0x39, 0x88, 0x90, 0x00, - 0x9c, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, - 0xb5, 0xfd, 0x00, 0xd0, 0xbb, 0xfb, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x71, 0xaf, 0xe8, 0x00, 0xe1, 0xbd, 0xe8, 0x00, - 0x7f, 0xa9, 0x68, 0xe0, 0x03, 0x74, 0x49, 0x00, 0x04, 0x7a, 0xc9, 0xa0, 0x00, 0x60, 0xc5, 0x00, 0x00, 0x21, 0xf9, - 0xc0, 0x00, 0x62, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x05, 0x54, 0xc1, - 0x39, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x12, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, - 0x42, 0x23, 0x00, 0x00, 0x00, 0x84, 0x6c, 0x90, 0x00, 0x82, 0xf2, 0x00, 0x40, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x6c, - 0x90, 0x00, 0x82, 0xf4, 0x00, 0x40, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x6c, 0x90, 0x00, 0x82, 0xf6, 0x00, 0x40, 0x23, - 0x94, 0x81, 0x00, 0x98, 0x00, 0x00, 0xce, 0x73, 0x00, 0x00, 0xd0, 0x73, 0x00, 0x00, 0xd2, 0xf3, 0x00, 0x00, 0xd4, - 0xf3, 0x00, 0x70, 0xc0, 0xe3, 0x0c, 0x40, 0xc1, 0xa5, 0x4c, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, - 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x30, 0x8f, 0x00, 0x02, 0x08, 0x00, 0x56, 0x23, 0x12, 0x00, 0x58, 0x23, 0xfa, - 0x64, 0xac, 0x5c, 0xef, 0x3e, 0x6f, 0x1f, 0x4f, 0x50, 0xa6, 0xe6, 0x21, 0xf0, 0xa3, 0xb2, 0x04, 0x0a, 0x90, 0x05, - 0xa1, 0x33, 0x2d, 0xcc, 0x9e, 0xa1, 0x62, 0x55, 0x13, 0x17, 0xc3, 0x9e, 0x97, 0xe0, 0x14, 0x78, 0x8f, 0x00, 0x02, - 0x01, 0xc0, 0x58, 0x24, 0xe0, 0x90, 0x00, 0x8a, 0x00, 0x10, 0xc0, 0xe9, 0x01, 0xb0, 0x56, 0x24, 0xdc, 0x90, 0x00, - 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, - 0x56, 0x63, 0x30, 0x8f, 0x00, 0x02, 0x80, 0x00, 0x5e, 0xa3, 0x00, 0xf0, 0x1e, 0xf3, 0x00, 0xf0, 0x1e, 0xf3, 0x00, - 0xf0, 0x1e, 0xf3, 0x12, 0xb0, 0x56, 0xa4, 0x80, 0xb7, 0xa0, 0x62, 0x44, 0x91, 0x00, 0x8a, 0x12, 0x00, 0x58, 0x23, - 0x78, 0x8f, 0x00, 0x02, 0x01, 0xc0, 0x58, 0x24, 0x30, 0x91, 0x00, 0x8a, 0x00, 0x10, 0xc0, 0xe9, 0x20, 0x91, 0x00, - 0x18, 0x12, 0xb0, 0x56, 0xa2, 0x88, 0x91, 0x00, 0x08, 0x12, 0x00, 0x58, 0x23, 0x80, 0xc5, 0x58, 0xe4, 0x78, 0x8f, - 0x00, 0x02, 0x01, 0xb0, 0x56, 0x24, 0x54, 0x91, 0x00, 0x0a, 0x01, 0xc0, 0x40, 0x28, 0x9c, 0x91, 0x00, 0x08, 0x04, - 0x00, 0x44, 0x23, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x11, 0x02, 0xfd, 0x00, 0x20, 0x04, 0xf3, 0x01, 0xc0, 0x58, 0x24, - 0x70, 0x91, 0x00, 0x0a, 0x80, 0x10, 0x82, 0x24, 0xac, 0x91, 0x00, 0x98, 0x00, 0x00, 0x42, 0xa3, 0x8a, 0x00, 0x46, - 0xa3, 0x80, 0x11, 0xc2, 0xe2, 0x80, 0x10, 0x82, 0x24, 0xac, 0x91, 0x00, 0x98, 0x84, 0x00, 0x44, 0xa3, 0x00, 0x20, - 0x04, 0xf5, 0x00, 0x11, 0x02, 0xfd, 0xac, 0x91, 0x00, 0x98, 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf6, 0x71, 0x00, - 0x00, 0xc0, 0x2d, 0xfa, 0x59, 0x7b, 0x63, 0xc0, 0xee, 0xc6, 0x9b, 0xa0, 0x32, 0x81, 0xa5, 0x59, 0xa2, 0x93, 0xbf, - 0x66, 0xb6, 0xff, 0x12, 0x2d, 0x14, 0xab, 0xf1, 0x1f, 0x0d, 0xfd, 0x47, 0x30, 0xee, 0xff, 0x94, 0xe2, 0xb8, 0x15, - 0x00, 0x70, 0xce, 0xeb, 0x00, 0x70, 0xd2, 0x6b, 0x00, 0x70, 0xc0, 0xe3, 0x0c, 0xb0, 0xc1, 0xa5, 0x04, 0x00, 0x42, - 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xd0, 0x91, 0x00, 0x0a, 0x80, 0x10, - 0x82, 0x24, 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf8, 0xf1, 0x60, 0x31, 0x7e, 0x45, 0x80, 0xcd, 0xb7, 0xf9, 0x00, - 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x40, 0x31, 0x7e, 0xc5, 0xc0, 0x31, 0x6a, 0x45, - 0xe0, 0x31, 0x6c, 0xc5, 0xdc, 0x87, 0x00, 0x02, 0x01, 0x00, 0x42, 0x23, 0x80, 0x50, 0xab, 0xe2, 0x00, 0x50, 0x2b, - 0xed, 0x80, 0x6a, 0xad, 0xe4, 0x00, 0x60, 0x2d, 0xf9, 0x20, 0x03, 0x6c, 0x49, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, - 0x00, 0x98, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x6b, 0x65, 0x00, 0x50, 0x2b, 0xf9, 0x20, - 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x69, 0xe5, 0x00, 0x40, 0x29, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x67, 0x65, - 0x00, 0x30, 0x27, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x20, 0x25, 0xf9, 0x00, 0x00, 0x00, - 0x84, 0x00, 0x00, 0x4c, 0x23, 0x00, 0x60, 0x8a, 0x70, 0x60, 0xb0, 0x92, 0x22, 0x1f, 0xb0, 0x90, 0x22, 0x20, 0x00, - 0x4e, 0x23, 0x00, 0x74, 0x50, 0xe4, 0x00, 0x80, 0x4e, 0xe3, 0x00, 0x70, 0x0e, 0x63, 0x00, 0x70, 0x0e, 0x63, 0x00, - 0x70, 0x0e, 0x63, 0x01, 0x70, 0x4e, 0x24, 0xfa, 0xa9, 0xb2, 0x57, 0x66, 0x9c, 0x35, 0xb5, 0x2a, 0xc5, 0x3e, 0x11, - 0xe4, 0x6f, 0x61, 0x98, 0x2b, 0xb0, 0x7a, 0x0e, 0x8f, 0x17, 0x96, 0x4c, 0xea, 0x5e, 0xfc, 0x49, 0xf1, 0x4c, 0x09, - 0xb4, 0xa2, 0x90, 0x16, 0x00, 0x53, 0x0a, 0x7d, 0x01, 0x80, 0x50, 0x24, 0x90, 0x92, 0x00, 0x8a, 0x00, 0x00, 0x00, - 0x84, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, - 0x67, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x20, 0x25, 0xf9, 0x00, - 0x03, 0x68, 0x45, 0x20, 0x03, 0x6a, 0x45, 0x40, 0xb0, 0x7a, 0xa2, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, - 0x00, 0xd0, 0x3b, 0x63, 0x00, 0x00, 0xc0, 0x2d, 0x64, 0x92, 0x00, 0x82, 0x20, 0x90, 0x40, 0x28, 0xb8, 0x93, 0x00, - 0x88, 0x00, 0xd0, 0x65, 0xe3, 0xac, 0x93, 0x00, 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, - 0x67, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x20, 0x25, 0xf9, 0x00, - 0x03, 0x68, 0x45, 0x20, 0x03, 0x6a, 0x45, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x20, 0xe1, 0x6b, 0x80, 0x00, 0x7a, 0xa3, - 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x2c, 0x92, 0x00, 0x82, 0x00, 0x20, 0xe1, - 0x6b, 0x80, 0xd0, 0x7b, 0x22, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x70, 0x81, - 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, 0x80, 0xd5, 0x7b, 0xe2, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, - 0xd0, 0x3b, 0x63, 0x2c, 0x92, 0x00, 0x82, 0x80, 0xb0, 0x40, 0xa8, 0xfa, 0x75, 0xb0, 0x59, 0x16, 0x9a, 0x8e, 0x4f, - 0x43, 0x63, 0xc7, 0xa3, 0xb3, 0xdd, 0x5d, 0x15, 0xaf, 0x7e, 0xe6, 0xfc, 0xa8, 0x82, 0x2f, 0x74, 0x1c, 0x32, 0x1b, - 0xe5, 0xb2, 0xb0, 0xef, 0xb6, 0x8b, 0x68, 0x17, 0xdc, 0x93, 0x00, 0x08, 0x64, 0x92, 0x00, 0x82, 0x60, 0x90, 0x40, - 0xa8, 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, 0xe3, 0x40, 0x90, 0x40, 0x28, 0xac, 0x93, 0x00, 0x88, 0x00, 0x00, - 0x66, 0xa3, 0x20, 0x90, 0x40, 0x28, 0xa0, 0x93, 0x00, 0x88, 0x00, 0x00, 0x68, 0x23, 0x80, 0x52, 0xab, 0x62, 0x80, - 0x53, 0xeb, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x42, 0xa9, 0x62, 0x80, 0x43, 0xe9, 0x62, 0xf8, 0x93, 0x00, 0x98, - 0x80, 0x32, 0xa7, 0x62, 0x80, 0x33, 0xe7, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x22, 0xa5, 0x62, 0x80, 0x23, 0xe5, - 0x62, 0x10, 0xb0, 0x90, 0x22, 0xd0, 0x93, 0x00, 0x8a, 0x80, 0x2e, 0xa5, 0x64, 0xf8, 0x93, 0x00, 0x98, 0x00, 0x20, - 0xe1, 0x6b, 0x00, 0x00, 0x6a, 0xa3, 0xec, 0x93, 0x00, 0x98, 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x6a, 0xa3, 0xff, - 0x00, 0x4e, 0xa3, 0x80, 0x53, 0xeb, 0x62, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x66, 0xa3, 0x00, 0xd0, 0x65, 0xe3, - 0x60, 0x31, 0x7e, 0x45, 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x21, 0xf9, 0x00, 0x10, 0x23, 0xf9, 0x80, 0x08, 0xb3, - 0x79, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x60, 0x31, 0x7e, 0x45, 0xe0, 0x03, - 0x74, 0x45, 0x00, 0x04, 0x44, 0x45, 0x80, 0xac, 0x83, 0xff, 0x80, 0x2c, 0x84, 0xff, 0x80, 0xb0, 0x87, 0x7b, 0x00, - 0x31, 0x86, 0x7b, 0x40, 0x03, 0x46, 0xc9, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, 0xfa, 0xda, 0xb9, 0xdf, - 0xb9, 0x3a, 0x79, 0x0a, 0xfd, 0xc4, 0x2f, 0x5b, 0x57, 0x99, 0x8f, 0xfa, 0x0f, 0xbe, 0x74, 0xd5, 0x42, 0xb0, 0xe9, - 0x36, 0x5c, 0x51, 0x97, 0xea, 0xe3, 0xcb, 0x5f, 0x40, 0xf8, 0x40, 0x18, 0x00, 0x03, 0x58, 0x45, 0x00, 0xc0, 0x18, - 0xf9, 0x10, 0x85, 0x00, 0x82, 0x00, 0x10, 0xbc, 0x28, 0x10, 0x95, 0x00, 0x8a, 0x01, 0x00, 0x5a, 0x23, 0x00, 0xb6, - 0x9c, 0x67, 0x00, 0x90, 0x79, 0xe3, 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x4e, 0xc9, 0x80, 0x03, 0x50, 0x49, 0xa0, - 0x03, 0x52, 0x49, 0xc0, 0x03, 0x54, 0x49, 0x40, 0x03, 0x78, 0x45, 0xc0, 0x31, 0x56, 0x45, 0xe0, 0x31, 0x58, 0x45, - 0x01, 0x00, 0x5a, 0x23, 0x00, 0xb6, 0x9c, 0x67, 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x56, 0xc5, 0x80, 0x03, 0x58, - 0xc5, 0xa0, 0x03, 0x5a, 0xc5, 0xc0, 0x03, 0x5c, 0xc5, 0x00, 0x00, 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, 0x00, 0x07, - 0x9c, 0xfd, 0x18, 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0xe4, - 0x84, 0x00, 0x82, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x20, 0x03, 0x48, 0x45, 0xff, 0x0f, 0x7e, 0xa3, - 0x00, 0xf0, 0x41, 0x28, 0x00, 0x82, 0x84, 0xe8, 0x18, 0x95, 0x00, 0x0a, 0x00, 0xf0, 0x41, 0x28, 0x00, 0x82, 0x84, - 0xe8, 0x18, 0x95, 0x00, 0x0a, 0xc3, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x10, 0x00, 0x7c, 0x22, 0x40, 0x03, - 0x4a, 0xc5, 0x00, 0x40, 0x08, 0xf9, 0x00, 0xe0, 0x49, 0x69, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4b, 0xe9, 0x00, - 0x00, 0x40, 0x23, 0x50, 0x00, 0x42, 0xa3, 0x2c, 0x95, 0x00, 0x98, 0x36, 0x00, 0x40, 0x23, 0x1c, 0x95, 0x00, 0x98, - 0xfa, 0x30, 0xe6, 0xfb, 0x7f, 0x2a, 0xf0, 0xa2, 0x58, 0xc7, 0xc5, 0xe5, 0x50, 0x92, 0x10, 0x56, 0x96, 0x57, 0x6a, - 0xb8, 0x2d, 0x8b, 0x25, 0xbb, 0x29, 0xc3, 0x3c, 0xfc, 0x27, 0x2d, 0x7d, 0x7d, 0xe0, 0x18, 0x19, 0x36, 0x00, 0x40, - 0x23, 0x3c, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, 0x42, 0x23, 0x2c, 0x95, 0x00, 0x98, 0x00, 0x00, - 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x94, 0x81, 0x00, 0x98, 0x00, 0x00, 0x8c, 0x67, 0x00, 0x63, 0x8c, 0xfb, 0x01, - 0x00, 0x7c, 0xa3, 0x00, 0x6f, 0x8e, 0x7b, 0x00, 0x70, 0xbc, 0x28, 0x6c, 0x96, 0x00, 0x88, 0x60, 0x32, 0x50, 0x45, - 0x00, 0x00, 0x7c, 0x23, 0x00, 0xe4, 0x93, 0x7d, 0x00, 0x83, 0x90, 0x67, 0x80, 0x73, 0x94, 0x67, 0x80, 0xa3, 0x96, - 0x67, 0x80, 0x84, 0x90, 0x67, 0x00, 0x85, 0x90, 0xfb, 0x80, 0x84, 0x90, 0x67, 0x80, 0xb5, 0x98, 0x67, 0x00, 0xc6, - 0x94, 0x67, 0x80, 0xc5, 0x98, 0xe7, 0x00, 0xc4, 0x98, 0xe7, 0x00, 0xa6, 0x94, 0x67, 0x00, 0xa0, 0x42, 0x63, 0xac, - 0x83, 0x00, 0x02, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x25, 0x9a, 0x67, 0x00, 0xd6, 0x9a, 0x67, - 0x00, 0x32, 0x7c, 0xc5, 0x00, 0xdf, 0x9c, 0x67, 0x80, 0xd6, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa4, 0x88, - 0x68, 0xc0, 0x95, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, 0xc8, 0x95, 0x00, 0x98, 0x00, 0xe0, 0x42, 0xe3, 0xc8, 0x95, - 0x00, 0x98, 0x00, 0x93, 0x84, 0xe7, 0x00, 0xd0, 0x86, 0xe7, 0x01, 0xe0, 0x89, 0xa4, 0x00, 0x32, 0x86, 0xe7, 0x00, - 0x3f, 0x88, 0xe7, 0x00, 0x83, 0x8c, 0xe7, 0x80, 0x31, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa3, 0xbc, 0xfd, - 0x00, 0xe0, 0xbd, 0xa8, 0xfa, 0xd4, 0x97, 0xea, 0x47, 0xf7, 0x3e, 0x32, 0x88, 0x67, 0x95, 0x4d, 0x2b, 0xe6, 0x7b, - 0x73, 0xf1, 0x99, 0xfe, 0xdd, 0x52, 0x43, 0x10, 0xdc, 0x8e, 0x91, 0x94, 0xb6, 0x1b, 0xb8, 0xad, 0xd3, 0xbc, 0xf0, - 0x19, 0xfc, 0x95, 0x00, 0x0a, 0x00, 0x30, 0x40, 0xe3, 0x04, 0x96, 0x00, 0x98, 0x00, 0x40, 0x40, 0x63, 0x04, 0x96, - 0x00, 0x98, 0x80, 0x10, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa4, 0xbc, 0x7d, 0x00, 0xe0, 0xbd, 0xa8, 0x20, - 0x96, 0x00, 0x8a, 0x00, 0x90, 0x46, 0xe3, 0x28, 0x96, 0x00, 0x18, 0x00, 0x20, 0x46, 0x63, 0x28, 0x96, 0x00, 0x18, - 0x38, 0x96, 0x00, 0x8a, 0x00, 0x10, 0x44, 0xe3, 0x01, 0x00, 0x7c, 0xa3, 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, 0x44, - 0x63, 0x00, 0x00, 0x7c, 0x23, 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, 0x40, 0x23, 0x00, 0x01, 0x82, 0xfd, 0x01, 0x00, - 0x50, 0x23, 0x00, 0x24, 0x8c, 0x62, 0x00, 0xe3, 0xbd, 0x68, 0x64, 0x96, 0x00, 0x08, 0x00, 0x10, 0x56, 0xe3, 0x6c, - 0x96, 0x00, 0x18, 0x00, 0x20, 0x56, 0xe3, 0x6c, 0x96, 0x00, 0x18, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xc4, 0x73, - 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, 0x02, 0x00, 0x70, 0xbc, 0x28, 0x70, 0x96, 0x00, - 0x08, 0x80, 0xb3, 0x9a, 0xe7, 0x00, 0x30, 0x56, 0x63, 0x00, 0x70, 0x58, 0x63, 0x00, 0x00, 0x00, 0x84, 0x40, 0x31, - 0x7e, 0xc5, 0x00, 0x05, 0x42, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0xb4, 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, 0x02, 0x00, - 0x70, 0xbc, 0x28, 0x98, 0x96, 0x00, 0x08, 0x00, 0x33, 0x7c, 0x45, 0x00, 0x3f, 0x94, 0x67, 0x80, 0x75, 0x9a, 0xe7, - 0x80, 0x33, 0x98, 0x7d, 0x80, 0x33, 0x9c, 0xfb, 0xfa, 0x56, 0xf0, 0x2e, 0x56, 0x18, 0xff, 0xc5, 0x45, 0xfb, 0x61, - 0xa3, 0xf0, 0xb3, 0xa6, 0x3e, 0x19, 0x55, 0x5a, 0x52, 0x42, 0x0b, 0x0d, 0xf5, 0xb1, 0x43, 0x89, 0x14, 0xc7, 0xbe, - 0x58, 0xeb, 0xcd, 0xc8, 0x1a, 0x00, 0xd7, 0x80, 0x67, 0x00, 0x00, 0xbc, 0xa8, 0x98, 0x96, 0x00, 0x08, 0x00, 0xa7, - 0x96, 0x67, 0x80, 0xc6, 0x98, 0xe7, 0x00, 0xb6, 0x9c, 0x67, 0x00, 0xb0, 0x96, 0x67, 0x00, 0xc0, 0x98, 0x67, 0x00, - 0x00, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x00, 0x08, 0x8d, 0xef, 0x00, 0x06, 0x8f, 0xef, 0x80, 0x63, 0x8c, 0x6f, - 0x00, 0x60, 0x42, 0x63, 0xa4, 0x82, 0x00, 0x02, 0x00, 0x30, 0x52, 0xe3, 0x80, 0x93, 0x92, 0x6f, 0x00, 0x31, 0x40, - 0xc5, 0x00, 0x90, 0x94, 0xef, 0x80, 0x94, 0x90, 0x6f, 0x00, 0x88, 0x90, 0x6f, 0x00, 0x86, 0x80, 0xe8, 0x00, 0x90, - 0x54, 0xef, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x68, 0xe3, 0x20, 0x31, 0x40, 0x45, 0x60, 0x30, 0x42, 0xc5, 0x80, - 0x30, 0x44, 0x45, 0x00, 0x4a, 0x97, 0x6f, 0x80, 0x05, 0x96, 0xef, 0x80, 0xb5, 0x98, 0xef, 0x80, 0xc5, 0x98, 0x7b, - 0x01, 0x00, 0x48, 0x23, 0x00, 0xc2, 0x9a, 0xfb, 0x80, 0x26, 0x9a, 0x6f, 0x00, 0x00, 0x48, 0xa3, 0x00, 0x46, 0x9c, - 0xfd, 0x00, 0xc0, 0x80, 0xa8, 0x00, 0xe0, 0x40, 0x6f, 0x00, 0x17, 0x9c, 0x6f, 0x80, 0xd6, 0x98, 0xef, 0x00, 0xe7, - 0xa0, 0x6f, 0x00, 0x18, 0x9e, 0xef, 0x80, 0xc7, 0x98, 0xfb, 0x80, 0xc6, 0x98, 0x6f, 0x00, 0x07, 0xa1, 0x6f, 0x00, - 0x28, 0x9e, 0xef, 0x80, 0xc7, 0x98, 0xfb, 0x80, 0xb6, 0xa2, 0xef, 0xf0, 0x96, 0x00, 0x82, 0x00, 0xba, 0xa4, 0x6f, - 0x00, 0x25, 0xa5, 0xef, 0x00, 0xd0, 0x62, 0x6f, 0x00, 0xa0, 0x64, 0xef, 0xfa, 0xa7, 0x55, 0x48, 0xc0, 0x14, 0xe8, - 0x07, 0x3a, 0x4e, 0x5e, 0x5f, 0xf6, 0x2a, 0xf3, 0x22, 0xe4, 0x64, 0xff, 0x8a, 0x63, 0x2b, 0x04, 0x82, 0xa0, 0x05, - 0x12, 0x9d, 0x6a, 0xd2, 0x46, 0xba, 0x1b, 0xa0, 0x1b, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x19, 0x82, 0xfd, 0x00, 0x49, - 0x81, 0x68, 0x01, 0x00, 0x44, 0x23, 0x00, 0x01, 0x80, 0xe2, 0x00, 0x10, 0x64, 0x6f, 0x00, 0x10, 0x64, 0x63, 0x00, - 0x27, 0xa5, 0x6f, 0x00, 0xe0, 0x66, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x42, 0xc5, 0x00, 0x00, 0xc4, 0x73, - 0xb4, 0xa3, 0x00, 0x82, 0x28, 0x97, 0x00, 0x02, 0x00, 0x30, 0xbd, 0x28, 0xc8, 0x97, 0x00, 0x88, 0x00, 0x00, 0x00, - 0x84, 0x20, 0x30, 0x7e, 0x45, 0x60, 0x10, 0x40, 0x28, 0x18, 0x98, 0x00, 0x08, 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, - 0x66, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x00, 0x68, 0x23, 0x80, 0x49, 0xb9, 0x79, 0x80, 0xc9, 0x83, 0xe8, 0xb4, - 0x99, 0x00, 0x0a, 0x00, 0xc0, 0x83, 0xa8, 0xb4, 0x99, 0x00, 0x88, 0x2c, 0x98, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, - 0x00, 0x00, 0xe8, 0xf3, 0x80, 0x49, 0xb9, 0x79, 0x00, 0xc0, 0x83, 0xa8, 0xb4, 0x99, 0x00, 0x88, 0x00, 0x00, 0xc0, - 0xf3, 0x00, 0x00, 0xc2, 0x73, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x00, 0xc6, 0xf3, 0x00, 0x00, 0xc0, 0x63, 0x0a, 0xc0, - 0xc1, 0x25, 0x04, 0x00, 0x44, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x04, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x4c, - 0x98, 0x00, 0x0a, 0x80, 0x20, 0x84, 0x24, 0x00, 0x20, 0xc0, 0xe9, 0x00, 0x00, 0xfa, 0x71, 0x20, 0x01, 0x78, 0xc9, - 0x40, 0x01, 0x7a, 0x49, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xcf, 0xf9, 0xff, 0xfa, 0x0a, 0x18, - 0x3d, 0xcc, 0x7e, 0x57, 0x62, 0xa1, 0x26, 0x2f, 0xb5, 0x6d, 0x83, 0x49, 0x21, 0x2b, 0x1a, 0xc2, 0x51, 0x01, 0x90, - 0x28, 0x8f, 0x96, 0x8a, 0x2d, 0x24, 0x51, 0x54, 0x84, 0x69, 0x13, 0x78, 0x1c, 0x00, 0x30, 0x7e, 0xc5, 0xa0, 0x30, - 0x58, 0x45, 0xc0, 0x30, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, - 0xa3, 0x00, 0x82, 0x01, 0x00, 0x9c, 0xa4, 0x00, 0xc7, 0x98, 0x6f, 0x00, 0xd7, 0x9a, 0x6f, 0x00, 0xc0, 0x52, 0xe3, - 0x00, 0xd0, 0x54, 0x63, 0x00, 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0xc0, 0x99, 0x00, 0x0a, 0x80, 0x30, 0x50, - 0x45, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0xc0, 0x99, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0xc0, 0x99, - 0x00, 0x0a, 0x00, 0xb0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0x90, 0x92, 0x6f, 0x80, 0xa0, 0x94, 0x6f, 0x00, - 0x90, 0x19, 0x6d, 0x00, 0xc0, 0x18, 0xf3, 0xaa, 0xc0, 0x98, 0xa4, 0x00, 0xc0, 0x18, 0xf3, 0x00, 0x01, 0x40, 0xc5, - 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0xa8, 0xe2, 0x60, 0x40, 0x41, 0xa8, 0x08, 0x99, 0x00, 0x08, 0x02, 0xc0, 0x98, - 0x24, 0x0c, 0x99, 0x00, 0x18, 0x01, 0xc0, 0x98, 0x24, 0x00, 0xc0, 0x18, 0xf3, 0x01, 0xc0, 0x98, 0x24, 0x04, 0xa4, - 0xd9, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xd3, 0xb7, 0xb4, 0x99, 0x00, 0x9c, 0x06, 0xa4, 0xd5, 0xb7, 0xb4, - 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, 0x00, 0x9c, - 0x20, 0x01, 0x78, 0xc5, 0x40, 0x01, 0x7a, 0x45, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, - 0xc5, 0xfa, 0x3c, 0xed, 0xbe, 0x46, 0xd8, 0x59, 0xda, 0x89, 0x4e, 0xc7, 0x62, 0x32, 0x08, 0x45, 0x4a, 0x9d, 0x19, - 0xea, 0x22, 0x0b, 0xa5, 0x85, 0x3b, 0xd2, 0x0f, 0xd1, 0xe1, 0xd9, 0x8b, 0xe6, 0x1c, 0x63, 0x50, 0x1d, 0xb4, 0xa3, - 0x00, 0x82, 0x00, 0xc0, 0xb9, 0xfd, 0x00, 0x00, 0xc4, 0x73, 0x00, 0xd1, 0xbb, 0xe8, 0x00, 0x90, 0x75, 0xe3, 0xff, - 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, 0x80, 0xc4, 0x94, 0x68, 0x00, 0xa4, 0xf9, 0x37, - 0xb4, 0x99, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0x37, 0xb4, 0x99, 0x00, - 0x9c, 0x03, 0xa4, 0xc5, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x04, 0xa4, 0xd5, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, - 0xc1, 0xb9, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, 0x00, - 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, - 0x41, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x10, 0x40, 0x28, 0xe0, 0x99, 0x00, 0x08, 0x10, 0x00, 0x48, - 0xa2, 0x00, 0x40, 0x66, 0xe5, 0xe4, 0x99, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, 0x01, 0x00, 0x64, 0xa3, 0x00, 0x20, - 0x25, 0xed, 0x00, 0x00, 0x62, 0x23, 0x00, 0x01, 0x60, 0x23, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x00, 0xc0, 0x2d, 0x00, - 0x00, 0xf9, 0xeb, 0x00, 0xd0, 0x3b, 0xf9, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, - 0x00, 0x00, 0x80, 0x70, 0x80, 0x0e, 0xba, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0xd0, 0xfb, 0x62, 0x00, 0xc0, 0x39, - 0xf9, 0x20, 0x01, 0x7a, 0x49, 0xfa, 0x74, 0x00, 0x84, 0x6a, 0x47, 0x27, 0x25, 0xea, 0xf0, 0x57, 0xa0, 0x09, 0x22, - 0x76, 0x26, 0x53, 0x1f, 0x98, 0x62, 0x39, 0xfe, 0x8b, 0x22, 0xe1, 0xe7, 0x8a, 0xa7, 0x8e, 0xf9, 0x6f, 0x53, 0xa2, - 0x28, 0x1e, 0x40, 0x01, 0x78, 0xc9, 0x00, 0x00, 0xfc, 0xf3, 0x60, 0x31, 0x7e, 0x45, 0x00, 0xdf, 0xf9, 0x7f, 0x40, - 0x31, 0x7e, 0xc5, 0xc0, 0x31, 0x56, 0x45, 0xe0, 0x31, 0x58, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, - 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x9a, 0xa4, 0x80, 0xb6, 0x96, 0xe7, 0x00, 0xb6, 0x9c, 0x67, 0x80, 0xc6, 0x98, - 0xe7, 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0x00, 0xe0, - 0x54, 0x63, 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x70, - 0x9b, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, 0xe4, 0x84, 0x00, 0x82, 0x00, 0x90, 0x15, 0x6d, - 0x00, 0xa0, 0x14, 0xf3, 0xaa, 0xa0, 0x94, 0xa4, 0x00, 0xa0, 0x14, 0xf3, 0x00, 0x01, 0x40, 0xc5, 0xff, 0x00, 0x48, - 0xa3, 0x00, 0x02, 0x92, 0xe2, 0x60, 0x90, 0x40, 0xa8, 0xc0, 0x9a, 0x00, 0x88, 0x02, 0xa0, 0x94, 0x24, 0xc4, 0x9a, - 0x00, 0x98, 0x01, 0xa0, 0x94, 0x24, 0x00, 0xa0, 0x14, 0xf3, 0x02, 0xa0, 0x94, 0x24, 0x04, 0xa4, 0xd5, 0x37, 0x7c, - 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xd1, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0x7c, 0x9b, 0x00, 0x9c, - 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0x9b, 0x00, 0x9c, 0x20, 0x01, 0x78, 0xc5, 0x40, 0x01, 0x7a, 0x45, 0x00, 0x00, 0x40, - 0x23, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x0e, 0xbc, 0xf9, 0xfa, 0x57, 0xbb, 0x85, 0x1e, 0xd3, 0x3e, 0xdc, 0x5d, 0x59, - 0xf1, 0x6e, 0x06, 0x42, 0x42, 0x57, 0x42, 0xdf, 0xff, 0x6c, 0xd1, 0x5d, 0xf6, 0x9b, 0x8d, 0x29, 0xc1, 0xf8, 0xfc, - 0x13, 0xad, 0xd8, 0x1b, 0x00, 0x1f, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, - 0x00, 0x80, 0x24, 0x00, 0xe0, 0xb9, 0x7d, 0x00, 0x00, 0xc4, 0x73, 0x00, 0xd1, 0xbb, 0xe8, 0x00, 0x90, 0x75, 0xe3, - 0xff, 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, 0x80, 0xa4, 0x94, 0x68, 0x00, 0xa4, 0xf9, - 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0x37, 0x7c, 0x9b, - 0x00, 0x9c, 0x03, 0xa4, 0xc5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x04, 0xa4, 0xd5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, - 0xa4, 0xc1, 0xb9, 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0x9b, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, - 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0x41, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, - 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xc6, 0xf3, 0x00, 0x00, 0xc8, 0x73, 0x00, 0x00, - 0xca, 0xf3, 0x00, 0x00, 0xcc, 0xf3, 0x00, 0x30, 0xc0, 0x63, 0x0b, 0x40, 0xc1, 0x25, 0x4c, 0xa3, 0x00, 0x02, 0x00, - 0x00, 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x43, 0x63, 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, - 0x01, 0xe0, 0x7d, 0x24, 0xb0, 0x9b, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, 0x0e, 0x00, 0x7c, 0xa3, 0x80, 0x00, 0x00, - 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xc8, 0x9b, 0x00, 0x0a, 0xfa, 0xe7, 0x31, 0xf9, 0x5f, 0x54, - 0x95, 0xa3, 0x9a, 0xf5, 0x8b, 0xfb, 0xc1, 0xca, 0x99, 0x0f, 0x83, 0x16, 0xec, 0xa5, 0xe0, 0x60, 0xab, 0xa6, 0x3b, - 0xe4, 0xff, 0xed, 0x0a, 0x83, 0xe6, 0xe2, 0x41, 0xd8, 0x1f, 0x04, 0x00, 0x7c, 0xa3, 0x00, 0x00, 0x42, 0xa3, 0x80, - 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xe0, 0x9b, 0x00, 0x0a, 0x1a, 0x00, 0x7c, 0xa3, - 0x00, 0x0f, 0xc0, 0xe2, 0x80, 0x00, 0x80, 0x24, 0x00, 0x00, 0xc0, 0x69, 0x00, 0x00, 0xf6, 0x71, 0x00, 0x00, 0xc0, - 0x2d, 0x00, 0x30, 0xc6, 0xeb, 0x00, 0x30, 0xca, 0xeb, 0x00, 0x30, 0xc0, 0x63, 0x0b, 0xb0, 0xc1, 0x25, 0x04, 0x00, - 0x42, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x20, 0x9c, 0x00, 0x8a, 0x80, - 0x10, 0x82, 0x24, 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf8, 0xf1, 0x20, 0x01, 0x64, 0x49, 0x20, 0x30, 0x7e, 0x45, - 0x80, 0xcd, 0xb7, 0xf9, 0x00, 0xb0, 0x81, 0xa8, 0xdc, 0x9d, 0x00, 0x88, 0xa0, 0x30, 0x6c, 0xc5, 0xc0, 0x30, 0x6e, - 0x45, 0xa8, 0x8b, 0x00, 0x02, 0x00, 0x00, 0x46, 0xe3, 0x00, 0x00, 0x40, 0xa8, 0xfc, 0x9d, 0x00, 0x8a, 0x20, 0x30, - 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x0b, 0xac, 0x79, 0x00, 0x60, 0x81, 0x28, 0xe4, 0x9d, 0x00, 0x08, 0x00, - 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0x00, 0x72, 0x63, 0x01, 0x90, 0xb3, 0x24, - 0x80, 0x9d, 0x83, 0x7f, 0xa8, 0x81, 0x00, 0x02, 0x20, 0x01, 0x64, 0x45, 0x80, 0x2c, 0x95, 0xff, 0x80, 0x6c, 0x97, - 0xff, 0x80, 0xa5, 0x99, 0x7f, 0x80, 0x55, 0x9b, 0xff, 0x80, 0xc6, 0x96, 0xfb, 0x80, 0xa5, 0x94, 0x7b, 0xfa, 0xb6, - 0x34, 0x55, 0x42, 0x77, 0x97, 0x45, 0x21, 0xc7, 0x79, 0x07, 0x46, 0x3b, 0xe8, 0x68, 0x0d, 0x03, 0x8f, 0x8c, 0xf5, - 0xef, 0xb4, 0x72, 0x02, 0xe7, 0xe8, 0xa9, 0xa6, 0x55, 0x58, 0x19, 0xff, 0xb0, 0x20, 0x00, 0x15, 0x94, 0xff, 0x00, - 0xa0, 0x80, 0xa8, 0xec, 0x9d, 0x00, 0x88, 0x40, 0x01, 0x54, 0x49, 0x00, 0xa0, 0x42, 0x63, 0xa8, 0x81, 0x00, 0x02, - 0x80, 0x20, 0xb9, 0x7f, 0x80, 0x60, 0xb7, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, 0xc0, 0x30, 0x5a, - 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x94, 0x8a, 0x00, 0x82, 0x00, 0x90, 0x5e, 0xe3, 0x00, 0xa0, 0x60, 0x63, 0x00, 0xb0, - 0x62, 0x63, 0x60, 0x01, 0x58, 0xc5, 0x80, 0x01, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0xb0, 0x79, 0x63, 0x94, - 0x8a, 0x00, 0x82, 0x80, 0xf5, 0x84, 0xef, 0x80, 0x98, 0x86, 0xef, 0x80, 0x21, 0x80, 0xe8, 0x38, 0x9d, 0x00, 0x0a, - 0x80, 0x05, 0x85, 0x6f, 0x80, 0xa8, 0x86, 0xef, 0x80, 0x21, 0x80, 0xe8, 0xf4, 0x9d, 0x00, 0x0a, 0xfc, 0x89, 0x00, - 0x02, 0x00, 0x90, 0x58, 0xe3, 0x00, 0xa0, 0x5a, 0x63, 0x00, 0xb0, 0x5c, 0xe3, 0x48, 0x9d, 0x00, 0x98, 0x00, 0xf0, - 0x58, 0xe3, 0x00, 0x00, 0x5b, 0xe3, 0x00, 0x10, 0x5d, 0x63, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe0, 0x42, 0xe3, 0x98, - 0x83, 0x00, 0x82, 0x80, 0xc0, 0x98, 0x6f, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x06, 0x98, 0x79, - 0x00, 0x00, 0x7e, 0xa3, 0x00, 0xf0, 0x41, 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, 0x9d, 0x00, 0x0a, 0x00, 0xf0, 0x41, - 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, 0x9d, 0x00, 0x0a, 0x00, 0x00, 0x46, 0x23, 0xc3, 0x00, 0x44, 0xa3, 0x64, 0x81, - 0x00, 0x02, 0xfa, 0x44, 0x15, 0x4c, 0xfa, 0xd5, 0x8b, 0x7c, 0x6e, 0x02, 0xe0, 0xfc, 0xb0, 0xb4, 0x94, 0x26, 0x22, - 0xd4, 0x1c, 0xba, 0xa2, 0x21, 0xf9, 0xb8, 0x62, 0x7d, 0x95, 0x40, 0xea, 0x98, 0xd9, 0x0a, 0xc4, 0x88, 0x21, 0x00, - 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x45, 0x69, 0x00, 0x30, 0x40, 0xa8, 0x01, 0x00, 0x42, 0x23, 0xbc, 0x9d, 0x00, 0x0a, - 0x50, 0x00, 0x42, 0xa3, 0x10, 0x00, 0x7c, 0x22, 0x00, 0x60, 0x2d, 0xf9, 0x00, 0xe0, 0x6d, 0x69, 0x20, 0xe0, 0x7d, - 0x22, 0x40, 0x01, 0x54, 0x45, 0x00, 0xa0, 0x14, 0xf9, 0x00, 0xe0, 0x55, 0xe9, 0x00, 0x30, 0x40, 0xe3, 0x00, 0x00, - 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x76, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x00, - 0x00, 0x7a, 0x23, 0x94, 0x81, 0x00, 0x98, 0x21, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, 0x22, 0x00, 0x46, 0x23, - 0xfc, 0x9d, 0x00, 0x98, 0x23, 0x00, 0x46, 0xa3, 0xfc, 0x9d, 0x00, 0x98, 0x24, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, - 0x98, 0x3c, 0x00, 0x44, 0xa3, 0x01, 0x00, 0x42, 0x23, 0x84, 0x9d, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x40, 0x31, - 0x7e, 0xc5, 0x00, 0x00, 0x40, 0x23, 0x00, 0x08, 0x80, 0xf9, 0x00, 0x08, 0x80, 0xe8, 0xdc, 0x9e, 0x00, 0x0a, 0xd8, - 0x8c, 0x00, 0x02, 0xdc, 0x9e, 0x00, 0x0a, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, - 0x01, 0x00, 0xa4, 0x24, 0x00, 0x09, 0xa1, 0x67, 0x00, 0x19, 0xa3, 0x67, 0x00, 0x00, 0xfc, 0xf3, 0x80, 0x31, 0x7e, - 0xc5, 0x00, 0x3f, 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, 0x70, 0x96, 0x00, 0x02, 0x5c, 0x8e, 0x00, 0x82, 0xd0, 0x8e, - 0x00, 0x02, 0x00, 0x70, 0x6e, 0x63, 0xfa, 0xc8, 0x1f, 0xb9, 0x96, 0xa7, 0x51, 0x28, 0xba, 0x6c, 0xad, 0x2c, 0x24, - 0xbc, 0xe5, 0x74, 0xab, 0x56, 0x9c, 0x31, 0x38, 0xd5, 0xe3, 0x4d, 0x97, 0xc9, 0x21, 0x13, 0x78, 0xd2, 0x9e, 0xc0, - 0x26, 0x60, 0x22, 0x00, 0x80, 0x70, 0x63, 0x00, 0x90, 0x72, 0x63, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, - 0x00, 0x00, 0x4f, 0xe3, 0x00, 0x20, 0x51, 0x63, 0x00, 0x10, 0x53, 0xe3, 0x0c, 0x8d, 0x00, 0x82, 0x00, 0x00, 0xfc, - 0xf3, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x3f, 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, 0x5c, 0x8e, 0x00, 0x82, 0xd0, 0x8e, - 0x00, 0x02, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x80, 0x04, 0x92, 0xfd, 0x00, - 0x70, 0x57, 0x63, 0x00, 0x80, 0x59, 0xe3, 0x00, 0x90, 0x5b, 0xe3, 0x0c, 0x8d, 0x00, 0x82, 0x00, 0xc0, 0x42, 0x63, - 0x74, 0x84, 0x00, 0x82, 0x80, 0xb0, 0x96, 0xe7, 0x80, 0xd0, 0x9a, 0xe7, 0x01, 0x00, 0x58, 0xa3, 0xd4, 0x8d, 0x00, - 0x82, 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x12, 0x00, 0x40, 0x23, 0x00, 0x00, - 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0xa8, 0xa4, 0x00, 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, - 0x00, 0x48, 0x22, 0x00, 0x40, 0x48, 0xe5, 0xff, 0x00, 0x44, 0xa3, 0x00, 0x41, 0x82, 0xe2, 0x00, 0x40, 0x32, 0xf5, - 0x00, 0x90, 0x09, 0xf5, 0x00, 0x40, 0x08, 0xf5, 0x00, 0x91, 0xb3, 0xe2, 0x00, 0x41, 0x88, 0xe2, 0x00, 0x00, 0x00, - 0x84, 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x33, 0x63, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x01, 0x90, - 0x75, 0x22, 0x04, 0xa4, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0xfa, 0x00, 0x72, 0xd2, 0x6e, 0xd2, 0xe3, 0x5f, 0x40, - 0x84, 0x2d, 0x3e, 0xf2, 0x2d, 0x12, 0xc5, 0xae, 0x85, 0xd7, 0xfe, 0x1b, 0x0e, 0xea, 0xf2, 0x46, 0x6b, 0x3c, 0x05, - 0x44, 0x39, 0x64, 0x1d, 0x3a, 0x38, 0x23, 0x02, 0x40, 0x40, 0xa8, 0x54, 0x9f, 0x00, 0x08, 0x01, 0x40, 0x40, 0xa8, - 0x70, 0x9f, 0x00, 0x08, 0xf4, 0x00, 0x46, 0xa3, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xcc, 0x99, 0x00, - 0x82, 0x00, 0x30, 0x40, 0xa8, 0x68, 0x9f, 0x00, 0x08, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xc3, 0x00, - 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xe4, 0x97, 0x00, 0x02, 0x00, 0x30, 0x40, 0xa8, 0x84, 0x9f, 0x00, 0x88, 0x3c, - 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xc3, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0x64, 0x81, 0x00, 0x02, - 0x00, 0x00, 0x40, 0xa2, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x44, 0x69, 0x00, 0x30, 0x40, 0xe3, 0x00, 0xa1, 0x00, - 0x98, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x68, 0xe3, 0x00, 0x40, 0x6b, 0x22, 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, - 0x35, 0x63, 0x01, 0xa0, 0x75, 0x22, 0xf2, 0x00, 0x46, 0xa3, 0x04, 0xa4, 0xc1, 0xb9, 0x70, 0xa0, 0x00, 0x9e, 0x04, - 0xa4, 0xc5, 0x35, 0x7c, 0xa0, 0x00, 0x1c, 0xf6, 0x00, 0x46, 0x23, 0xff, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x4a, 0x63, - 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0x01, 0x40, 0x40, 0xa8, 0xf4, 0x9f, 0x00, 0x08, 0x02, 0x40, 0x40, - 0xa8, 0x70, 0xa0, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0xaa, 0x40, 0x40, 0x28, 0x70, 0xa0, - 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0x80, 0x4c, 0x40, 0x68, 0xfa, 0xd3, 0x36, 0xc2, 0x83, - 0x56, 0x05, 0x40, 0x8b, 0x12, 0x77, 0x1d, 0xbe, 0x27, 0xd9, 0x8c, 0x73, 0xa0, 0xc2, 0xbf, 0x31, 0xe5, 0xfc, 0x43, - 0x91, 0x4d, 0xd7, 0x5d, 0xf6, 0x8f, 0x2b, 0x7a, 0x53, 0x10, 0x24, 0x70, 0xa0, 0x00, 0x8a, 0xf4, 0x00, 0x46, 0xa3, - 0x00, 0xe1, 0xbd, 0xe2, 0x02, 0xe0, 0x41, 0x28, 0x44, 0xa0, 0x00, 0x88, 0x01, 0xe0, 0x41, 0x28, 0x70, 0xa0, 0x00, - 0x8a, 0x50, 0x00, 0x42, 0xa3, 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, 0x00, 0x1c, 0x06, 0xa4, 0xe3, 0x35, 0x7c, 0xa0, - 0x00, 0x1c, 0x50, 0xa0, 0x00, 0x18, 0x30, 0x00, 0x42, 0xa3, 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, 0x00, 0x1c, 0x05, - 0xa4, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0xff, 0x0f, 0x4a, 0x23, 0x80, 0x22, 0x84, 0x62, 0x00, 0x20, 0x04, 0xf3, - 0xc3, 0x20, 0x84, 0xa4, 0x00, 0x00, 0x40, 0x23, 0x8c, 0xa0, 0x00, 0x98, 0x12, 0x00, 0x44, 0xa3, 0x05, 0xa4, 0xc1, - 0x39, 0x8c, 0x9f, 0x00, 0x98, 0x3c, 0x00, 0x44, 0xa3, 0xf2, 0x00, 0x46, 0xa3, 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, - 0x00, 0x98, 0x00, 0x50, 0x45, 0xe9, 0x10, 0x40, 0x6d, 0xa2, 0x00, 0x00, 0x21, 0xf9, 0x00, 0x60, 0x61, 0xe9, 0x20, - 0x60, 0x6d, 0x22, 0x00, 0x10, 0x23, 0xf9, 0x00, 0x60, 0x63, 0x69, 0x00, 0x00, 0x40, 0x23, 0x00, 0xa1, 0x00, 0x98, - 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x33, 0x63, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x6a, 0x22, 0x03, 0x94, 0xc1, - 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, - 0x73, 0x22, 0x03, 0x94, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0xfa, - 0x09, 0xc7, 0x2d, 0xc3, 0x0b, 0xf5, 0xce, 0x45, 0x87, 0x3e, 0x32, 0x85, 0xdf, 0xd4, 0xa4, 0xa2, 0x3d, 0xf0, 0x8c, - 0xf2, 0xb9, 0x08, 0x5f, 0xfe, 0x0c, 0x86, 0xca, 0xec, 0x0b, 0xab, 0xcb, 0x87, 0xe8, 0x24, 0x05, 0x94, 0xc1, 0x39, - 0xc3, 0x00, 0x44, 0xa3, 0x00, 0x50, 0x45, 0xe9, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x40, 0x23, 0x00, 0xa1, 0x00, - 0x98, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, - 0x44, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x94, 0x81, 0x00, 0x98, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, 0x22, 0x00, - 0x40, 0x48, 0xe5, 0x00, 0x40, 0x04, 0xf5, 0xff, 0x00, 0x4c, 0x23, 0x00, 0x23, 0x84, 0x62, 0x00, 0x20, 0x32, 0x63, - 0x01, 0x90, 0xb3, 0x24, 0x04, 0x94, 0xcb, 0xb5, 0x0c, 0xa2, 0x00, 0x1c, 0xff, 0x00, 0x4c, 0x23, 0x00, 0x53, 0x8e, - 0xe2, 0x01, 0x70, 0x40, 0xa8, 0x00, 0xa2, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x50, - 0x0a, 0xf5, 0x00, 0x53, 0x8e, 0xe2, 0x00, 0x71, 0x40, 0x68, 0xf4, 0xa1, 0x00, 0x0a, 0x05, 0x94, 0xcb, 0x35, 0x0c, - 0xa2, 0x00, 0x1c, 0x60, 0x01, 0x4a, 0xc9, 0x06, 0x94, 0xcb, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x80, 0x01, 0x4a, 0x49, - 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, 0x73, 0x24, 0x00, 0x94, 0xf5, 0xb5, 0x0c, 0xa2, 0x00, 0x1c, 0x01, 0x94, 0xed, - 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x02, 0x94, 0xeb, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x03, 0x94, 0xef, 0x35, 0x0c, 0xa2, - 0x00, 0x1c, 0x05, 0x94, 0xc1, 0x39, 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x64, 0x65, 0x00, 0x20, 0x25, 0xf9, 0x20, - 0x30, 0x7e, 0x45, 0xfa, 0x80, 0x47, 0xdb, 0x27, 0x56, 0xc0, 0x35, 0xe4, 0x63, 0x17, 0xe9, 0x3d, 0xcd, 0xe1, 0x60, - 0x0d, 0x76, 0x37, 0x6f, 0xfd, 0x8a, 0x44, 0x9e, 0xe0, 0x97, 0xa4, 0x33, 0x04, 0xad, 0xc3, 0xcb, 0xa7, 0xc0, 0x25, - 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, 0x00, 0x50, 0xab, - 0xfb, 0x00, 0x00, 0xd4, 0xf3, 0x00, 0x65, 0xad, 0x68, 0x00, 0x75, 0xaf, 0x68, 0x80, 0x6b, 0xa9, 0xe8, 0xa0, 0x00, - 0x60, 0xc5, 0x00, 0x00, 0x21, 0xf9, 0xc0, 0x00, 0x62, 0x45, 0x88, 0x9b, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf6, - 0x00, 0x46, 0x23, 0x14, 0xa2, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf4, 0x00, 0x46, 0xa3, 0x14, 0xa2, 0x00, 0x98, - 0x05, 0x94, 0xc1, 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x05, 0x94, 0xc1, - 0x39, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x12, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x00, 0x30, - 0x40, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, 0x00, - 0x00, 0x74, 0xa3, 0x00, 0x00, 0x6e, 0x23, 0x94, 0x81, 0x00, 0x98, 0x20, 0x00, 0x42, 0x23, 0x94, 0x81, 0x00, 0x98, - 0xf2, 0x00, 0x40, 0xa3, 0x50, 0xa2, 0x00, 0x98, 0x00, 0x00, 0xe6, 0x73, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, - 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0x30, - 0xe7, 0x62, 0x40, 0x00, 0x66, 0x49, 0x09, 0x00, 0x60, 0xa3, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, - 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0xfa, 0xa2, 0x6a, 0x72, 0x0e, 0x01, 0xe7, 0x76, 0x21, 0x13, 0xd9, 0x69, - 0xc0, 0x5d, 0x22, 0x3c, 0x19, 0x25, 0xc9, 0x5d, 0x28, 0x86, 0x4a, 0x64, 0xf9, 0xa1, 0x3c, 0xa1, 0x5b, 0x7b, 0x29, - 0xe0, 0xd6, 0x98, 0x26, 0x50, 0xa2, 0x00, 0x98, 0x40, 0x00, 0x66, 0x45, 0x20, 0x00, 0x60, 0x45, 0x60, 0x00, 0x60, - 0xc9, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, - 0x00, 0x98, 0x20, 0x00, 0x42, 0x45, 0x00, 0x12, 0xe0, 0xb5, 0x58, 0xa2, 0x00, 0x9c, 0x40, 0x00, 0x66, 0x45, 0x0c, - 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, - 0x60, 0x00, 0x60, 0xc5, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x10, 0xe6, 0x35, 0x58, 0xa2, 0x00, 0x9c, 0x07, 0x00, 0x40, - 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, - 0x42, 0x23, 0x80, 0x30, 0xe7, 0x62, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, - 0x10, 0x56, 0xc9, 0x00, 0x00, 0x66, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x50, 0xa2, 0x00, 0x98, - 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0xe4, 0xa3, 0x00, 0x82, 0x04, 0xa4, 0x00, 0x82, 0x24, 0xa4, 0x00, - 0x02, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xc0, 0x63, 0x94, 0x81, 0x00, 0x98, 0x1c, 0x00, 0x7c, 0xa3, 0x00, 0x10, - 0x23, 0xf9, 0x00, 0x00, 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, 0xfd, 0x80, 0x08, 0x21, 0x7d, 0x00, - 0x10, 0x23, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x5c, 0xa3, 0x00, 0x0a, 0xfa, 0x87, 0x2e, 0x85, 0x45, 0x29, 0xe2, 0xca, - 0xea, 0xda, 0x43, 0x4d, 0x7c, 0x08, 0xf2, 0xa2, 0xd2, 0x6e, 0x68, 0x15, 0x93, 0x69, 0x6b, 0x39, 0x75, 0xd2, 0xc8, - 0xe0, 0x85, 0x3d, 0xe8, 0x70, 0x6b, 0x70, 0x27, 0x00, 0x00, 0xc0, 0x69, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, - 0xfd, 0x00, 0x00, 0x21, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x78, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, 0x00, 0x00, - 0x00, 0x84, 0x54, 0x00, 0x46, 0xa3, 0x00, 0x30, 0x06, 0xf3, 0x53, 0x30, 0x86, 0xa4, 0x00, 0x30, 0x06, 0xf3, 0x01, - 0x30, 0x86, 0x24, 0x00, 0x30, 0x06, 0xf3, 0x80, 0x30, 0x86, 0x24, 0x00, 0x30, 0x06, 0xf5, 0x00, 0x00, 0x00, 0x84, - 0x90, 0xa3, 0x00, 0x82, 0x01, 0x06, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xed, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xc0, - 0xeb, 0x00, 0x10, 0x80, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x08, 0x4c, 0xa3, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x60, - 0x7e, 0x69, 0xd4, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x02, 0x4c, 0xa3, 0x10, 0x00, 0x44, 0x23, 0x00, - 0x20, 0x04, 0xf3, 0x00, 0x61, 0x86, 0xe4, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0xf0, 0xa3, 0x00, 0x0a, - 0x00, 0x00, 0x00, 0x84, 0x80, 0x00, 0x4c, 0xa3, 0x50, 0x00, 0x44, 0xa3, 0x00, 0x20, 0x04, 0xf3, 0x00, 0x61, 0x86, - 0xe4, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0x10, 0xa4, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, - 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x44, 0xa3, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x48, 0xa3, 0x00, - 0x00, 0x4a, 0x23, 0x00, 0x00, 0x4c, 0x23, 0x00, 0x00, 0x4e, 0xa3, 0x00, 0x00, 0x50, 0xa3, 0x82, 0x13, 0xfc, 0x70, - 0xa6, 0x40, 0x04, 0xf3, 0xdb, 0xc6, 0xa2, 0x25, 0x6e, 0x69, 0x92, 0xbd, 0xaf, 0x70, 0x27, 0x52, 0x8d, 0xf8, 0x67, - 0x44, 0xa7, 0x79, 0xe3, 0x0f, 0x69, 0x21, 0x84, 0xe9, 0xaa, 0x48, 0x28, 0x00, 0x00, 0x52, 0x23, 0x00, 0x00, 0x54, - 0x23, 0x00, 0x00, 0x56, 0xa3, 0x00, 0x00, 0x58, 0x23, 0x00, 0x00, 0x5a, 0xa3, 0x00, 0x00, 0x5c, 0xa3, 0x00, 0x00, - 0x5e, 0x23, 0x00, 0x00, 0x60, 0xa3, 0x00, 0x00, 0x62, 0x23, 0x00, 0x00, 0x64, 0x23, 0x00, 0x00, 0x66, 0xa3, 0x00, - 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, 0x00, 0x00, 0x6e, 0x23, 0x00, 0x00, 0x70, 0x23, - 0x00, 0x00, 0x72, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x76, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, - 0x23, 0x00, 0x00, 0x7c, 0x23, 0x00, 0x00, 0x7e, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x72, 0x87, 0x8e, 0x25, 0x10, 0x7a, - 0xa9, 0x7c, 0x70, 0x46, 0xa8, 0xcf, 0x82, 0xe7, 0x6a, 0xa2, 0x16, 0xd6, 0x2e, 0xdb, 0x61, 0x19, 0xe2, 0x80, 0x93, - 0x47, 0xe0, 0x4c, 0xf6, 0x7a, 0xfa, 0x4a, 0x54, 0xb0, 0x03, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x58, 0xba, 0xf8, 0xc6, - 0x24, 0x5e, 0x6c, 0x6d, 0x89, 0xc6, 0xe4, 0xf4, 0x69, 0xf0, 0xcc, 0x9a, 0xcc, 0x9f, 0xe3, 0x8a, 0x4e, 0x35, 0xf6, - 0x8c, 0xe1, 0xe2, 0x90, 0x77, 0x82, 0x21, 0x26, 0xdb, 0xd8, 0x02, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x01, - 0x00, 0x00, 0x00, 0x01, 0xa8, 0x24, 0x00, 0x00, 0xd4, 0x7d, 0x50, 0x04, 0x3e, 0x76, 0xee, 0xe1, 0x59, 0xcb, 0x26, - 0x98, 0xc7, 0x25, 0x91, 0xb2, 0x59, 0xdd, 0x1c, 0xf0, 0x9e, 0xef, 0xd3, 0x1c, 0x5d, 0xb6, 0x34, 0xbb, 0x20, 0xd4, - 0x52, 0x09, 0xd2, 0x56, 0xbf, 0xa0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff}; \ No newline at end of file +const uint8_t fw_SPECT[] = { + 0x68, 0x3c, 0x3b, 0xe7, 0x56, 0x6d, 0x16, 0x60, 0xaf, 0x2b, 0xcd, 0x92, 0x49, 0xa1, 0x2d, 0xb6, + 0xa8, 0x51, 0xa3, 0xc0, 0x5a, 0x72, 0xa2, 0xe7, 0x26, 0x04, 0xed, 0xb0, 0x73, 0x77, 0x9a, 0x3d, + 0x23, 0x60, 0x8a, 0xf9, 0xa9, 0xc5, 0xe2, 0x46, 0xf3, 0xe1, 0xa7, 0x7b, 0xc7, 0x52, 0x28, 0x67, + 0x2e, 0x19, 0x97, 0xe9, 0x61, 0x21, 0x3d, 0x85, 0x44, 0x5e, 0xee, 0x5f, 0x9d, 0x83, 0x01, 0x29, + 0x0b, 0x7b, 0x66, 0xdb, 0xa0, 0x72, 0x77, 0x94, 0x20, 0x4a, 0xe5, 0x92, 0xa3, 0xb6, 0xef, 0xe9, + 0x83, 0x1b, 0x6b, 0xfe, 0xcb, 0x9b, 0xba, 0xbd, 0x27, 0xe7, 0x62, 0x51, 0x03, 0x77, 0xac, 0x6d, + 0x69, 0x02, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x62, 0xc2, 0xed, 0xc8, 0x72, 0x5b, 0x29, + 0x22, 0x60, 0xb7, 0x2b, 0xa4, 0x6d, 0x0a, 0xa6, 0xb9, 0x57, 0x63, 0x34, 0xb9, 0x03, 0x95, 0x53, + 0x40, 0xa9, 0x96, 0xaa, 0x40, 0x0f, 0x44, 0x23, 0x70, 0x2c, 0x00, 0x00, 0x2f, 0x82, 0xf0, 0xe9, + 0x8a, 0x1d, 0xf3, 0x23, 0x8f, 0x1d, 0xac, 0x6f, 0x9d, 0xd2, 0x9c, 0x27, 0x32, 0x09, 0x47, 0xf5, + 0x59, 0xf3, 0x54, 0x5b, 0xbf, 0x4f, 0x8b, 0x45, 0x79, 0xa9, 0x37, 0x1e, 0x57, 0xd4, 0x61, 0xa1, + 0xa2, 0x21, 0xea, 0x64, 0x27, 0x05, 0xfd, 0x23, 0xa6, 0x3f, 0x98, 0x2a, 0x8c, 0xd9, 0x68, 0xa0, + 0x93, 0x96, 0x98, 0xba, 0x72, 0x85, 0x9c, 0x02, 0x07, 0xc2, 0x59, 0x0e, 0xfa, 0x06, 0x2e, 0xe1, + 0xbf, 0x70, 0xd9, 0x8b, 0x8f, 0xbb, 0x20, 0xcf, 0x7b, 0x24, 0x49, 0xea, 0xa0, 0x75, 0x17, 0x3a, + 0x31, 0xe1, 0xfc, 0x14, 0x6a, 0xcb, 0x08, 0x48, 0x10, 0x22, 0x9a, 0x84, 0xd4, 0x00, 0x04, 0x00, + 0x00, 0x7e, 0xa3, 0xe4, 0xa3, 0x00, 0x82, 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, 0x40, 0xa2, 0xff, + 0x00, 0x48, 0xa3, 0x00, 0x02, 0x82, 0x62, 0xf0, 0x10, 0x88, 0xa2, 0x20, 0x33, 0x4a, 0xc5, 0x00, + 0x10, 0x40, 0x28, 0x2c, 0xa3, 0x00, 0x08, 0x60, 0x40, 0x40, 0x28, 0x4c, 0x80, 0x00, 0x88, 0x10, + 0x40, 0x40, 0xa8, 0x84, 0x80, 0x00, 0x08, 0x40, 0x40, 0x40, 0xa8, 0xb8, 0x80, 0x00, 0x08, 0x70, + 0x40, 0x40, 0xa8, 0x20, 0x81, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0x04, 0xa4, 0x00, 0x82, 0xf4, + 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x60, 0x10, 0x40, 0x28, 0x1c, + 0x9f, 0x00, 0x08, 0x61, 0x10, 0x40, 0xa8, 0x1c, 0x9f, 0x00, 0x08, 0x62, 0x10, 0x40, 0xa8, 0xa4, + 0x9f, 0x00, 0x08, 0x63, 0x10, 0x40, 0x28, 0xb0, 0xa0, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0xa8, + 0xa4, 0x00, 0x18, 0xf3, 0x50, 0x8a, 0xa4, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x11, + 0x10, 0x40, 0x28, 0x60, 0xa2, 0x00, 0x08, 0x12, 0x10, 0x40, 0x28, 0x9c, 0xa2, 0x00, 0x08, 0x13, + 0x10, 0x40, 0xa8, 0xbc, 0xa2, 0x00, 0x88, 0x14, 0x10, 0x40, 0x28, 0xe0, 0xa2, 0x00, 0x88, 0x40, + 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x04, 0xa4, 0x00, 0x82, 0xf2, 0x50, 0x8a, 0x24, 0x00, + 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x41, 0x10, 0x40, 0x28, 0x94, 0x8f, 0x00, 0x88, 0x42, + 0x10, 0x40, 0x28, 0xac, 0x90, 0x00, 0x88, 0xfa, 0xcc, 0x83, 0xc8, 0x04, 0xf9, 0x3a, 0x0d, 0xb0, + 0x7d, 0x4d, 0xa9, 0x0b, 0x9f, 0xe4, 0x7f, 0x61, 0xc0, 0x88, 0xdd, 0x82, 0x0e, 0x40, 0xed, 0x0e, + 0x2b, 0xae, 0xd7, 0x25, 0x3f, 0x99, 0xe5, 0x89, 0xd8, 0x04, 0x43, 0x10, 0x40, 0xa8, 0xd4, 0x90, + 0x00, 0x88, 0x44, 0x10, 0x40, 0x28, 0x04, 0x91, 0x00, 0x88, 0x45, 0x10, 0x40, 0xa8, 0xfc, 0x91, + 0x00, 0x08, 0x46, 0x10, 0x40, 0xa8, 0xa0, 0x92, 0x00, 0x08, 0x47, 0x10, 0x40, 0x28, 0xf4, 0x92, + 0x00, 0x88, 0x48, 0x10, 0x40, 0x28, 0x30, 0x93, 0x00, 0x88, 0x49, 0x10, 0x40, 0xa8, 0x48, 0x93, + 0x00, 0x88, 0x4a, 0x10, 0x40, 0xa8, 0x18, 0x94, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, + 0x00, 0x18, 0x04, 0xa4, 0x00, 0x82, 0xf1, 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, + 0x4a, 0x49, 0x70, 0x10, 0x40, 0xa8, 0x1c, 0xa1, 0x00, 0x88, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, + 0x00, 0x18, 0x02, 0x00, 0x44, 0x23, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x44, 0x69, 0x00, 0x00, + 0x42, 0xa3, 0xf3, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x40, 0x00, 0x40, 0xa3, 0x00, 0x00, + 0x00, 0xf3, 0x00, 0x00, 0x00, 0x84, 0x50, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x00, + 0x00, 0x84, 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, 0x00, 0xf5, 0x00, 0x00, 0x00, 0xf5, 0xff, 0x00, + 0x42, 0xa3, 0x00, 0x10, 0x02, 0xf3, 0xff, 0x10, 0x82, 0xa4, 0x80, 0x00, 0x80, 0xe2, 0x00, 0x00, + 0x00, 0x84, 0xa8, 0xa4, 0x00, 0x18, 0x00, 0x10, 0x02, 0xf3, 0x00, 0x10, 0x02, 0xf3, 0x80, 0x00, + 0x40, 0xe2, 0x00, 0x11, 0x40, 0x49, 0x00, 0x00, 0xc0, 0x93, 0x80, 0x10, 0x84, 0xff, 0x80, 0x20, + 0x86, 0x7f, 0xfa, 0xb4, 0x4f, 0xc7, 0x95, 0x2d, 0xf6, 0x63, 0x09, 0x62, 0xc9, 0xe8, 0x68, 0x63, + 0x21, 0x84, 0xad, 0x79, 0xd2, 0xfb, 0x25, 0x50, 0xd4, 0x59, 0x5a, 0xf2, 0x4d, 0x23, 0x6f, 0xf9, + 0x0a, 0xda, 0x20, 0xb0, 0x05, 0x80, 0x31, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x80, 0x41, 0x8a, + 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, + 0xff, 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x06, 0x00, 0x7c, + 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, + 0xa4, 0xdc, 0x81, 0x00, 0x8a, 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x0f, 0x00, 0x7c, + 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, + 0xa4, 0xfc, 0x81, 0x00, 0x0a, 0x80, 0x42, 0x8c, 0xff, 0x00, 0x63, 0x88, 0xff, 0x3f, 0x00, 0x7c, + 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, + 0xa4, 0x1c, 0x82, 0x00, 0x8a, 0x00, 0x43, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, + 0xff, 0x1e, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, + 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0x40, 0x82, 0x00, 0x8a, 0x00, 0x43, 0x88, 0x7f, 0x40, 0x30, 0x4a, + 0xc5, 0x80, 0x00, 0x7c, 0xa3, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x50, 0x0a, + 0x63, 0x80, 0x82, 0x00, 0x8c, 0x00, 0x50, 0x0a, 0x63, 0x94, 0x82, 0x00, 0x0e, 0x80, 0x40, 0x88, + 0xff, 0x94, 0x82, 0x00, 0x98, 0x00, 0x50, 0x0a, 0x63, 0x90, 0x82, 0x00, 0x0c, 0xfa, 0xff, 0xc4, + 0xcd, 0xa1, 0x38, 0x8c, 0x9d, 0xc1, 0x79, 0xde, 0xea, 0xc4, 0x13, 0x04, 0xdb, 0x6f, 0x36, 0x9d, + 0xcc, 0x1a, 0xb9, 0xe7, 0x9b, 0x02, 0x46, 0x13, 0x86, 0x23, 0xb7, 0xe6, 0xde, 0x15, 0x88, 0x06, + 0x00, 0x41, 0x88, 0xff, 0x94, 0x82, 0x00, 0x98, 0x80, 0x41, 0x88, 0x7f, 0x02, 0xe0, 0x7d, 0x24, + 0x60, 0x82, 0x00, 0x0a, 0x00, 0x40, 0x42, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x86, 0xef, + 0x80, 0x30, 0x88, 0xef, 0x00, 0x42, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, + 0x00, 0x21, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, + 0x00, 0x31, 0x86, 0x6f, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x8a, 0x6f, + 0x80, 0x52, 0x86, 0xef, 0x09, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x01, 0xe0, 0x7d, 0x24, + 0xe0, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x86, 0xef, 0x0a, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x02, 0xe0, 0x7d, 0x24, 0xf4, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x8a, 0xef, + 0x80, 0x52, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x1e, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, 0x20, 0x83, 0x00, 0x0a, 0x80, 0x30, 0x86, 0x6f, + 0x80, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x04, 0xe0, 0x7d, 0x24, 0x3c, 0x83, 0x00, 0x8a, 0x00, 0x31, 0x86, 0x6f, + 0x20, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, 0xfa, 0xbf, 0xbc, 0x7c, 0x5f, 0xb1, 0x46, 0xcb, + 0xf3, 0xd8, 0x1d, 0x3d, 0x06, 0x92, 0x4a, 0x99, 0x56, 0xe9, 0x4a, 0x28, 0x36, 0x84, 0xfb, 0x20, + 0xca, 0xc0, 0xfb, 0x43, 0x16, 0x0e, 0xc2, 0xfc, 0xb7, 0x60, 0x07, 0x80, 0x31, 0x86, 0xef, 0x80, + 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x04, 0xe0, 0x7d, 0x24, 0x5c, 0x83, 0x00, 0x8a, 0x00, + 0x31, 0x86, 0x6f, 0x1e, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, + 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, 0x7c, 0x83, 0x00, 0x0a, 0x80, 0x32, 0x86, 0xef, 0x00, + 0x00, 0x00, 0x84, 0xa4, 0x82, 0x00, 0x02, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, + 0x30, 0x82, 0xef, 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x84, 0xe7, 0x80, 0x20, 0x88, 0xe7, 0x00, + 0x42, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x41, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x80, + 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x21, 0x84, 0x67, 0x00, + 0x21, 0x86, 0x67, 0x07, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xdc, + 0x83, 0x00, 0x0a, 0x80, 0x21, 0x8a, 0xe7, 0x80, 0x52, 0x86, 0x67, 0x0f, 0x00, 0x7c, 0x23, 0x80, + 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xf4, 0x83, 0x00, 0x0a, 0x80, 0x51, 0x84, 0xe7, 0x00, + 0x21, 0x86, 0x67, 0x0f, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x0c, + 0x84, 0x00, 0x0a, 0x80, 0x51, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, + 0x22, 0x8a, 0x67, 0x80, 0x52, 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0x67, 0x01, + 0xe0, 0x7d, 0x24, 0xfa, 0xc0, 0x24, 0xe4, 0xe7, 0x5b, 0x5f, 0x6b, 0x41, 0xe9, 0x19, 0xa6, 0x89, + 0x62, 0x86, 0xff, 0xbd, 0x80, 0x38, 0xf7, 0x1e, 0x02, 0xa0, 0xbb, 0x29, 0x20, 0xb1, 0xd7, 0x7a, + 0x0e, 0x7a, 0x03, 0x71, 0x38, 0x08, 0x30, 0x84, 0x00, 0x0a, 0x80, 0x51, 0x84, 0xe7, 0x00, 0x21, + 0x86, 0x67, 0x63, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x48, 0x84, + 0x00, 0x0a, 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, 0x80, 0x31, + 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x60, 0x84, 0x00, 0x0a, 0x80, 0x32, 0x84, 0xe7, 0x00, 0x00, + 0x00, 0x84, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x30, + 0x86, 0xe7, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x00, 0x32, + 0x82, 0x67, 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0x80, 0x67, 0x00, 0x00, + 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x00, + 0x80, 0x67, 0x00, 0x21, 0x84, 0xe7, 0x80, 0x20, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x32, + 0x48, 0x45, 0x00, 0x22, 0x86, 0x67, 0x00, 0x21, 0x88, 0xe7, 0x80, 0x40, 0x88, 0xe8, 0xdc, 0x84, + 0x00, 0x8a, 0x00, 0x20, 0x42, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x30, 0x42, 0x63, 0x00, 0x00, + 0x00, 0x84, 0x00, 0x90, 0x42, 0x63, 0x74, 0x84, 0x00, 0x82, 0x80, 0x70, 0x8e, 0xe7, 0x80, 0x80, + 0x90, 0xe7, 0x01, 0x00, 0x42, 0x23, 0x80, 0x70, 0x8e, 0xe2, 0x00, 0x80, 0x10, 0xeb, 0x80, 0x83, + 0x90, 0xe4, 0x00, 0x80, 0x10, 0xed, 0x00, 0x80, 0x10, 0xf9, 0x00, 0x00, 0x00, 0x84, 0xfa, 0xf1, + 0x25, 0xa3, 0x1c, 0x81, 0xe5, 0x61, 0x6e, 0x97, 0xbe, 0x09, 0xcd, 0xfa, 0x69, 0xa9, 0xe3, 0x4f, + 0x0c, 0x6e, 0x6e, 0xc5, 0x16, 0x7c, 0x73, 0x95, 0xa1, 0x1f, 0xf0, 0xd8, 0x76, 0xff, 0x7a, 0x10, + 0x09, 0x00, 0xc0, 0x60, 0x63, 0x00, 0x00, 0x21, 0x63, 0x24, 0x85, 0x00, 0x8c, 0x00, 0x00, 0x6c, + 0xa3, 0x2c, 0x85, 0x00, 0x18, 0x01, 0x00, 0x6c, 0x23, 0x2c, 0x85, 0x00, 0x18, 0x00, 0x00, 0x21, + 0x65, 0x00, 0x00, 0x59, 0x63, 0x00, 0x08, 0xa1, 0xe7, 0x01, 0x00, 0x42, 0x23, 0x80, 0x00, 0xa9, + 0xfd, 0x00, 0x03, 0xa1, 0x67, 0x80, 0x00, 0xab, 0x7b, 0x80, 0x5a, 0xa5, 0x67, 0x80, 0x2a, 0xa5, + 0xe7, 0x00, 0x2a, 0xa7, 0xe7, 0x00, 0x29, 0xa5, 0x67, 0x80, 0x2a, 0xa5, 0xe7, 0x00, 0x2a, 0x83, + 0xe7, 0x00, 0x10, 0x60, 0xe3, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0xa4, 0x67, 0x00, 0x29, 0xa5, + 0x67, 0x00, 0x28, 0xa5, 0xe7, 0x80, 0x29, 0xa5, 0xe7, 0x00, 0x29, 0xa1, 0xe7, 0x80, 0x0a, 0xa1, + 0xe7, 0x00, 0x32, 0x42, 0x45, 0x80, 0x20, 0xa3, 0xe7, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x0a, 0xbd, + 0xe8, 0x9c, 0x85, 0x00, 0x8a, 0x00, 0x20, 0x41, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x7c, + 0x23, 0x00, 0xea, 0xa9, 0xfd, 0x00, 0x0a, 0xbd, 0xe8, 0xb4, 0x85, 0x00, 0x8a, 0x00, 0x10, 0x41, + 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, 0x88, 0x00, 0x00, 0x42, + 0xa3, 0x00, 0xe0, 0xbd, 0x68, 0xcc, 0x85, 0x00, 0x8a, 0x01, 0x10, 0x82, 0x24, 0x01, 0x60, 0x41, + 0xa8, 0xd8, 0x85, 0x00, 0x8a, 0x02, 0x10, 0x82, 0x24, 0x03, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, + 0x88, 0x00, 0x00, 0x46, 0x23, 0x00, 0x30, 0x86, 0xfd, 0xfa, 0x4f, 0x66, 0x67, 0xf6, 0x00, 0xe1, + 0x5b, 0x14, 0xf0, 0x6a, 0x37, 0xf6, 0xd8, 0x91, 0x81, 0x5b, 0xe4, 0x55, 0xaa, 0x34, 0x3f, 0xfe, + 0xb8, 0x3d, 0x89, 0x0a, 0x42, 0x06, 0x3f, 0xfa, 0x89, 0xba, 0xe8, 0x09, 0x01, 0x00, 0x7c, 0xa3, + 0x00, 0x0f, 0x82, 0xe2, 0x00, 0x1b, 0x40, 0x68, 0x00, 0x86, 0x00, 0x8a, 0x00, 0x00, 0x56, 0x63, + 0x08, 0x86, 0x00, 0x18, 0x00, 0x30, 0x56, 0x63, 0x08, 0x86, 0x00, 0x18, 0x00, 0x00, 0x42, 0xa3, + 0x00, 0x00, 0x00, 0x84, 0xff, 0x0f, 0x42, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x80, 0x83, 0x80, 0xfd, + 0x80, 0xc5, 0x82, 0xfd, 0x80, 0x00, 0x80, 0xe7, 0x80, 0x83, 0x82, 0x7b, 0x80, 0xc5, 0x84, 0xfb, + 0x00, 0x11, 0x82, 0xe7, 0x00, 0xa7, 0x84, 0x67, 0x00, 0x23, 0x84, 0x67, 0x00, 0x21, 0x84, 0x7b, + 0x80, 0x96, 0x86, 0xe7, 0x80, 0x31, 0x86, 0xfb, 0x00, 0x10, 0x88, 0xfd, 0x00, 0x10, 0x80, 0x7b, + 0x00, 0x31, 0x82, 0xfd, 0x00, 0x31, 0x84, 0xfb, 0x80, 0x40, 0x96, 0xe7, 0x00, 0x40, 0x9c, 0x67, + 0x00, 0x20, 0x98, 0xe7, 0x80, 0x20, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x80, 0x73, 0x80, 0x67, + 0x00, 0x84, 0x82, 0xe7, 0x80, 0x94, 0x84, 0xe7, 0x00, 0x21, 0x84, 0x7b, 0x80, 0x00, 0x86, 0x7b, + 0x00, 0x74, 0x88, 0x7b, 0x00, 0x42, 0x88, 0xe7, 0x00, 0x32, 0x88, 0xfd, 0x80, 0x00, 0x80, 0x7d, + 0x00, 0x20, 0x82, 0xfb, 0x80, 0x40, 0x8e, 0xe7, 0x80, 0x00, 0x92, 0xe7, 0x80, 0x01, 0x90, 0xe7, + 0x80, 0x41, 0x94, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x4e, 0xa3, 0x01, 0x00, 0x50, 0x23, + 0x01, 0x00, 0x52, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, + 0x00, 0xb0, 0x4e, 0x67, 0xfa, 0xdd, 0x19, 0xf8, 0x69, 0x43, 0xbb, 0xb9, 0x84, 0xe0, 0xde, 0xf4, + 0xd2, 0x3f, 0x9e, 0x4d, 0xa8, 0xd6, 0x61, 0xe7, 0x9a, 0x34, 0x04, 0x99, 0xab, 0x79, 0xc9, 0x94, + 0x5c, 0x1e, 0x16, 0xaa, 0x78, 0xc0, 0x0a, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, + 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, + 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0xb8, + 0x86, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x56, 0xc9, 0x20, 0x05, 0x58, 0xc9, 0x40, + 0x05, 0x5a, 0x49, 0x00, 0x00, 0x4e, 0xa3, 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, 0xa3, 0x00, + 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xde, 0xf3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, + 0xd0, 0x3b, 0xeb, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, + 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, + 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x14, + 0x87, 0x00, 0x0a, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, + 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, + 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, + 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x50, 0x87, 0x00, 0x0a, 0x00, + 0x00, 0x7c, 0x23, 0x80, 0xe3, 0x8f, 0xfd, 0x00, 0xe5, 0x95, 0xfd, 0x18, 0x86, 0x00, 0x02, 0xfa, + 0xcb, 0xbe, 0x52, 0xdc, 0x6f, 0xb6, 0x98, 0x09, 0x99, 0xb7, 0x24, 0xc2, 0x56, 0x10, 0xa9, 0x4c, + 0x33, 0x6c, 0x10, 0x4d, 0x7e, 0x8e, 0x10, 0x81, 0x2d, 0x05, 0xf1, 0x7a, 0xc8, 0xd2, 0xb6, 0x69, + 0x98, 0x0b, 0x80, 0xe3, 0x8f, 0xfd, 0x00, 0xe5, 0x95, 0xfd, 0x00, 0x05, 0x40, 0x45, 0x20, 0x05, + 0x42, 0x45, 0x40, 0x05, 0x44, 0x45, 0x80, 0x06, 0x80, 0xe7, 0x80, 0x16, 0x82, 0xe7, 0x00, 0xb1, + 0x96, 0xe7, 0x00, 0xc1, 0x98, 0xe7, 0x80, 0x05, 0xbc, 0xe8, 0xd4, 0x87, 0x00, 0x0a, 0x00, 0x16, + 0xbc, 0xe8, 0xd4, 0x87, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x01, 0x00, + 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x40, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, + 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xae, 0x24, 0x80, 0x5b, 0xab, 0x67, 0x00, 0x5b, + 0xb1, 0x67, 0x80, 0x6b, 0xad, 0x67, 0x98, 0x96, 0x00, 0x02, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x00, + 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0x02, + 0x56, 0x49, 0x20, 0x02, 0x58, 0x49, 0x40, 0x02, 0x5a, 0xc9, 0x60, 0x02, 0x5c, 0x49, 0xf0, 0x86, + 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, + 0x00, 0x0a, 0x00, 0x02, 0x56, 0x45, 0x20, 0x02, 0x58, 0x45, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, + 0x5c, 0x45, 0x00, 0x02, 0x4e, 0x49, 0x20, 0x02, 0x50, 0xc9, 0x40, 0x02, 0x52, 0x49, 0x60, 0x02, + 0x54, 0xc9, 0x00, 0x50, 0x4f, 0xe3, 0x00, 0x60, 0x51, 0xe3, 0x00, 0x70, 0x53, 0xe3, 0x00, 0x80, + 0x55, 0xe3, 0x00, 0x00, 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, 0xfa, 0xbd, 0xd2, 0x17, 0x3a, 0x7e, + 0x35, 0x06, 0x80, 0x7c, 0xa9, 0x13, 0x27, 0x2c, 0x51, 0x5b, 0xde, 0xea, 0xe8, 0x1b, 0x60, 0xf7, + 0x53, 0xa7, 0x77, 0xd2, 0xb5, 0x02, 0x33, 0x27, 0x4b, 0x60, 0x2d, 0x70, 0x0c, 0x00, 0x07, 0x9c, + 0xfd, 0x18, 0x86, 0x00, 0x02, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, + 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, + 0xa8, 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0x02, 0x56, + 0x45, 0x20, 0x02, 0x58, 0x45, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, 0x45, 0x18, 0x86, 0x00, + 0x02, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0x00, 0xe0, 0x54, + 0x63, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, 0x74, 0x84, 0x00, + 0x82, 0x80, 0xb0, 0xaa, 0xe7, 0x80, 0xc0, 0xac, 0x67, 0x80, 0x5a, 0x83, 0xe7, 0x00, 0x6b, 0x85, + 0xe7, 0x80, 0x20, 0x86, 0xfd, 0x00, 0x11, 0x88, 0xe7, 0x00, 0x43, 0x88, 0x67, 0x01, 0x00, 0x40, + 0xa3, 0x00, 0x40, 0x88, 0xfb, 0x00, 0x32, 0x80, 0xe8, 0x08, 0x89, 0x00, 0x0a, 0x00, 0x00, 0x40, + 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x80, 0x73, 0x80, + 0x67, 0x00, 0x84, 0x82, 0xe7, 0x80, 0x94, 0x84, 0xe7, 0x00, 0x10, 0x86, 0x7d, 0x00, 0x31, 0x86, + 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x03, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x01, 0x80, + 0x7b, 0x00, 0x30, 0x86, 0x68, 0x48, 0x89, 0x00, 0x8a, 0x00, 0x74, 0x80, 0x67, 0x00, 0x95, 0x86, + 0x67, 0x00, 0x30, 0x86, 0x68, 0xfa, 0xc8, 0xec, 0x1b, 0x0c, 0x7f, 0xc1, 0xd2, 0x5c, 0x08, 0x1d, + 0xda, 0xdb, 0x7c, 0x0d, 0xda, 0xdc, 0x0c, 0x79, 0x28, 0xdc, 0x82, 0xda, 0xe5, 0x03, 0x70, 0x2a, + 0x84, 0x4a, 0xb8, 0xb9, 0xda, 0x91, 0x48, 0x0d, 0x00, 0x00, 0x00, 0x84, 0x00, 0x96, 0x80, 0xef, + 0x80, 0xa6, 0x82, 0xef, 0x00, 0xb7, 0x84, 0x6f, 0x00, 0x95, 0x86, 0xfb, 0x80, 0xc6, 0x88, 0xfb, + 0x00, 0x32, 0x86, 0x6f, 0x80, 0x00, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x7d, 0x80, 0xa5, 0x88, 0xfb, + 0x00, 0xd7, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xef, 0x00, 0x11, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xfd, + 0x80, 0x95, 0x8a, 0x7b, 0x00, 0xc7, 0x8c, 0x7b, 0x00, 0x53, 0x8a, 0xef, 0x00, 0x01, 0x8c, 0x7b, + 0x00, 0x53, 0x8c, 0xfd, 0x00, 0x81, 0x8e, 0x6f, 0x80, 0x63, 0x8a, 0x7d, 0x80, 0x52, 0x8e, 0x7b, + 0x80, 0x53, 0x8a, 0x7b, 0x80, 0x12, 0x8e, 0xfd, 0x80, 0x12, 0x8a, 0x7b, 0x00, 0x83, 0x8c, 0x6f, + 0x00, 0x21, 0x82, 0x7b, 0x00, 0x11, 0x84, 0x7b, 0x00, 0x61, 0x8c, 0x7d, 0x00, 0x60, 0x8c, 0xfd, + 0x00, 0x63, 0x82, 0x7b, 0x00, 0x13, 0x8c, 0x7b, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x80, 0x7b, + 0x00, 0x01, 0x80, 0x7d, 0x00, 0x43, 0x82, 0xef, 0x00, 0x03, 0x84, 0x6f, 0x80, 0x53, 0x8c, 0x6f, + 0x00, 0x61, 0x9a, 0xfb, 0x80, 0x32, 0x8a, 0xef, 0x80, 0x50, 0x98, 0x7d, 0x80, 0x43, 0x8e, 0x6f, + 0x00, 0x30, 0x82, 0x6f, 0x80, 0x70, 0x9c, 0x7b, 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0xef, + 0x00, 0xa5, 0x82, 0x6f, 0x80, 0xb5, 0x84, 0x6f, 0x00, 0x95, 0x86, 0xef, 0x80, 0x31, 0x86, 0xfb, + 0x80, 0x95, 0x8e, 0xef, 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x81, 0x8c, 0xef, 0x80, 0x63, 0x8c, 0x7d, + 0xfa, 0xb6, 0x33, 0x06, 0x98, 0x5a, 0x9e, 0x93, 0xec, 0x78, 0x10, 0xb5, 0xc0, 0x90, 0x83, 0x0a, + 0xbd, 0x73, 0x2c, 0x54, 0xd0, 0x1b, 0x01, 0xfb, 0x7a, 0xa3, 0xec, 0x5f, 0x89, 0x81, 0xda, 0x3b, + 0xc2, 0x20, 0x0e, 0x00, 0x63, 0x8a, 0xfb, 0x00, 0x53, 0x8c, 0xfb, 0x00, 0x13, 0x8a, 0x7d, 0x00, + 0x13, 0x8c, 0x7b, 0x00, 0x53, 0x8c, 0xef, 0x80, 0x51, 0x8a, 0xef, 0x00, 0x21, 0x86, 0xfb, 0x80, + 0x21, 0x84, 0xfb, 0x80, 0x83, 0x8e, 0x6f, 0x00, 0x71, 0x8e, 0x7d, 0x00, 0x70, 0x8e, 0xfd, 0x80, + 0x73, 0x86, 0xfb, 0x80, 0x71, 0x8e, 0xfb, 0x00, 0x00, 0x86, 0xfb, 0x00, 0x30, 0x80, 0xfb, 0x00, + 0x01, 0x80, 0x7d, 0x80, 0x03, 0x80, 0x6f, 0x00, 0x60, 0x8c, 0xfb, 0x80, 0xa5, 0x80, 0x6f, 0x00, + 0x00, 0x80, 0xfb, 0x80, 0x03, 0x8e, 0xef, 0x80, 0x53, 0x8a, 0x7d, 0x80, 0x00, 0x8e, 0xef, 0x80, + 0x73, 0x8e, 0x7b, 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x50, 0x52, 0xe3, 0x00, 0x60, 0x54, 0xe3, 0x00, + 0x70, 0x56, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, + 0x00, 0x56, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, 0x00, + 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, + 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, + 0xe0, 0x7d, 0x24, 0xa8, 0x8a, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x58, 0x49, 0x20, + 0x05, 0x5a, 0x49, 0x40, 0x05, 0x5c, 0x49, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, + 0x00, 0x56, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xde, 0xf3, 0xfa, 0xa3, 0xe2, 0x5f, 0x46, + 0x88, 0xc2, 0xbe, 0x0e, 0x87, 0x12, 0x96, 0xe2, 0x9a, 0x63, 0xb1, 0x9c, 0xf3, 0x88, 0x06, 0xd7, + 0x2a, 0xa1, 0x58, 0xb4, 0xe7, 0x5f, 0xc7, 0xbf, 0x2f, 0xc2, 0x63, 0x28, 0xf8, 0x0e, 0x00, 0xf0, + 0x1e, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, + 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, + 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xf8, 0x8a, 0x00, 0x0a, 0x00, 0x01, + 0x7c, 0xa3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, + 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, + 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x2c, 0x8b, + 0x00, 0x8a, 0x00, 0x00, 0x7c, 0x23, 0x00, 0xe5, 0x95, 0xfd, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe5, + 0x95, 0xfd, 0x00, 0x05, 0x40, 0x45, 0x20, 0x05, 0x42, 0x45, 0x40, 0x05, 0x44, 0x45, 0x00, 0x07, + 0x80, 0x6f, 0x00, 0x17, 0x82, 0x6f, 0x00, 0xc1, 0x98, 0x6f, 0x00, 0xd1, 0x9a, 0x6f, 0x00, 0x06, + 0xbc, 0x68, 0xa0, 0x8b, 0x00, 0x0a, 0x80, 0x16, 0xbc, 0x68, 0xa0, 0x8b, 0x00, 0x0a, 0x00, 0x00, + 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x30, + 0x7e, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, + 0xb0, 0x24, 0x00, 0x6c, 0xad, 0xef, 0x00, 0x7c, 0xaf, 0xef, 0xc8, 0x97, 0x00, 0x82, 0x00, 0x10, + 0x53, 0xe3, 0x00, 0x20, 0x55, 0xe3, 0xfa, 0x70, 0x8b, 0x4d, 0xbb, 0xd1, 0x84, 0x9b, 0xed, 0x5b, + 0xc4, 0xa6, 0x4a, 0xcc, 0x3b, 0xae, 0x49, 0xdd, 0x58, 0x59, 0xc1, 0x52, 0x10, 0x1e, 0xa1, 0x83, + 0x5a, 0x5f, 0x94, 0xb5, 0x32, 0xf7, 0x64, 0xd0, 0x0f, 0x00, 0x30, 0x57, 0xe3, 0x9c, 0x8c, 0x00, + 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, + 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0x80, 0x30, 0x50, 0x45, 0x00, 0x10, 0x59, 0xe3, 0x00, 0x20, 0x5b, + 0x63, 0x00, 0x30, 0x5d, 0xe3, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x94, 0x8c, 0x00, + 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0x00, 0x80, 0x68, 0x00, 0x60, 0x53, + 0x6f, 0x00, 0x70, 0x55, 0xef, 0x00, 0x80, 0x57, 0x6f, 0x00, 0x10, 0x59, 0xe3, 0x00, 0x20, 0x5b, + 0x63, 0x00, 0x30, 0x5d, 0xe3, 0x80, 0x06, 0x9a, 0xfd, 0x4c, 0x89, 0x00, 0x82, 0x20, 0x30, 0x7e, + 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0xd8, 0x8a, 0x00, + 0x02, 0x00, 0x00, 0x40, 0xa8, 0x94, 0x8c, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, + 0x0a, 0x00, 0x60, 0x59, 0x63, 0x00, 0x70, 0x5b, 0x63, 0x00, 0x80, 0x5d, 0x63, 0x4c, 0x89, 0x00, + 0x82, 0x00, 0xc0, 0x52, 0xe3, 0x00, 0xd0, 0x54, 0x63, 0x00, 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, + 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0xe0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0xc0, 0xac, + 0xef, 0x80, 0xd0, 0xae, 0xef, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, + 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x30, 0x40, 0x45, 0x80, 0x30, 0x42, 0x45, 0x00, 0xa5, 0x86, + 0xef, 0xfa, 0x5f, 0x9e, 0xb7, 0xbe, 0x7e, 0x7c, 0x23, 0x30, 0x8b, 0x71, 0xe9, 0xe3, 0x42, 0x70, + 0xb5, 0xc0, 0x51, 0x72, 0x60, 0x89, 0xae, 0x4e, 0x48, 0x1a, 0xd1, 0x57, 0x0b, 0xd2, 0x9b, 0xfd, + 0xbd, 0x4d, 0xa8, 0x10, 0x80, 0x35, 0x86, 0x6f, 0x80, 0x94, 0x84, 0x6f, 0x80, 0x24, 0x84, 0xef, + 0x80, 0xb5, 0x88, 0x6f, 0x80, 0x45, 0x8a, 0xef, 0x80, 0x04, 0x80, 0xef, 0x00, 0x02, 0x80, 0x6f, + 0x80, 0x12, 0x82, 0xef, 0x80, 0x00, 0x80, 0x7b, 0x00, 0x01, 0x80, 0x7b, 0x80, 0x01, 0x80, 0x68, + 0x00, 0x00, 0x00, 0x84, 0x60, 0x32, 0x40, 0xc5, 0x00, 0x08, 0x80, 0xe7, 0x00, 0x08, 0x83, 0xe7, + 0x00, 0x10, 0x82, 0xfb, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x10, 0x82, 0xfb, 0x00, 0x18, 0x82, 0xe7, + 0x98, 0x84, 0x00, 0x02, 0x00, 0x10, 0x62, 0x63, 0x01, 0x00, 0x44, 0x23, 0x00, 0x20, 0x84, 0x70, + 0x00, 0x01, 0x84, 0x62, 0x00, 0x00, 0x00, 0x84, 0xc0, 0x32, 0x68, 0xc5, 0xe0, 0x32, 0x6a, 0xc5, + 0xa0, 0x32, 0x6c, 0x45, 0x00, 0x64, 0x8b, 0x67, 0x80, 0x53, 0x8a, 0x7b, 0x00, 0x66, 0x8d, 0xe7, + 0x80, 0x65, 0x8c, 0x7b, 0x00, 0x53, 0x80, 0x67, 0x80, 0x96, 0x82, 0x67, 0x00, 0x86, 0x84, 0x67, + 0x80, 0x54, 0x86, 0xfb, 0x80, 0x66, 0x88, 0xfb, 0x00, 0x32, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, + 0x00, 0x32, 0x86, 0x7d, 0x00, 0x54, 0x88, 0xfb, 0x00, 0x66, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0x67, + 0x00, 0x01, 0x8a, 0x7b, 0x80, 0x42, 0x88, 0xfd, 0x00, 0x94, 0x8a, 0x7b, 0x00, 0xd6, 0x96, 0xfb, + 0x80, 0x55, 0x8a, 0xe7, 0x00, 0x11, 0x96, 0x7b, 0x80, 0x55, 0x8a, 0x7d, 0x00, 0x42, 0x99, 0xe7, + 0x00, 0x51, 0x97, 0xe7, 0x00, 0xb6, 0x98, 0x7b, 0x00, 0x16, 0x96, 0xfd, 0xfa, 0x87, 0x7f, 0x45, + 0xce, 0x1d, 0x8c, 0x9a, 0x86, 0x28, 0x4f, 0x1f, 0x3e, 0xb6, 0xb5, 0xf2, 0xe6, 0xcc, 0xb3, 0xcb, + 0x93, 0x0d, 0x0f, 0x85, 0x09, 0x2d, 0xb7, 0x00, 0x21, 0xe1, 0xf5, 0x67, 0x63, 0x80, 0x11, 0x00, + 0x16, 0x98, 0x7b, 0x00, 0xb6, 0x9a, 0x67, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x82, 0xfb, 0x00, + 0x41, 0x85, 0x67, 0x00, 0x52, 0x89, 0xe7, 0x00, 0x11, 0x82, 0x7b, 0x00, 0x01, 0x84, 0xfd, 0x00, + 0x41, 0x85, 0x67, 0x00, 0x41, 0x88, 0x7b, 0x00, 0x12, 0x80, 0x67, 0x00, 0xd0, 0x9a, 0xfb, 0x00, + 0x52, 0x80, 0xe7, 0x80, 0x35, 0x96, 0x67, 0x00, 0xb0, 0x96, 0xfd, 0x80, 0x30, 0x80, 0xe7, 0x00, + 0x56, 0x98, 0x67, 0x00, 0xc0, 0x98, 0xfb, 0x00, 0x66, 0xad, 0x67, 0x00, 0xbb, 0x96, 0x7d, 0x00, + 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0x67, 0x00, 0x04, 0x80, 0xe7, 0x60, 0x32, 0x42, 0x45, 0x80, + 0x13, 0x82, 0xe7, 0x00, 0x14, 0x82, 0x7b, 0x00, 0x14, 0x82, 0xe7, 0x80, 0x73, 0x84, 0xe7, 0x00, + 0x11, 0x82, 0x7b, 0x80, 0x13, 0x82, 0xe7, 0x80, 0x00, 0x80, 0xe8, 0x00, 0x00, 0x00, 0x84, 0x00, + 0x74, 0x80, 0xfb, 0x00, 0x95, 0x82, 0x7d, 0x00, 0x10, 0x82, 0x67, 0x00, 0x74, 0x80, 0xfd, 0x00, + 0x95, 0x84, 0x7b, 0x00, 0x20, 0x84, 0x67, 0x00, 0x11, 0x86, 0xfb, 0x80, 0x31, 0x86, 0x67, 0x00, + 0x11, 0x88, 0x7d, 0x00, 0x42, 0x88, 0xe7, 0x00, 0x36, 0x92, 0x67, 0x00, 0xb2, 0x94, 0x67, 0x00, + 0x00, 0x00, 0x84, 0x00, 0x74, 0x82, 0x7b, 0x80, 0x10, 0x82, 0xe7, 0x00, 0x74, 0x84, 0x7d, 0x00, + 0x21, 0x84, 0xe7, 0x00, 0x11, 0x8e, 0xe7, 0x00, 0x11, 0x82, 0x7d, 0x80, 0x60, 0x86, 0xe7, 0x00, + 0x31, 0x86, 0x7b, 0x80, 0x11, 0x90, 0x67, 0xfa, 0x6e, 0xd6, 0x93, 0xd7, 0x8f, 0x36, 0x11, 0x4d, + 0x20, 0x25, 0x07, 0x88, 0x7b, 0x9b, 0x49, 0x49, 0x78, 0xc9, 0x5b, 0xb4, 0x93, 0x04, 0xf0, 0x28, + 0xb3, 0x50, 0xe5, 0x88, 0x8a, 0x40, 0x70, 0x43, 0x58, 0x12, 0x00, 0x00, 0x00, 0x84, 0x80, 0x32, + 0x4c, 0x45, 0x00, 0xb0, 0x52, 0x63, 0x00, 0xc0, 0x54, 0xe3, 0x01, 0x00, 0x4e, 0x23, 0x00, 0x00, + 0x50, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xf6, 0xf3, 0x00, 0xb0, 0x37, 0xeb, 0x00, 0xd0, + 0x3b, 0xeb, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, + 0x00, 0x02, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x78, 0x8e, + 0x00, 0x0a, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xb0, 0x37, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0x90, + 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, 0x00, 0x02, 0x00, 0x90, + 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0xa4, 0x8e, 0x00, 0x8a, 0x00, 0x00, + 0x00, 0x84, 0x00, 0x76, 0x80, 0xe7, 0x00, 0xb4, 0x82, 0xe7, 0x00, 0x86, 0x84, 0x67, 0x60, 0x32, + 0x4c, 0xc5, 0x00, 0x63, 0x86, 0xfb, 0x00, 0x31, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, 0x80, 0x41, + 0x88, 0xfb, 0x80, 0xb3, 0x8a, 0x67, 0x00, 0x51, 0x8a, 0x7b, 0x80, 0x42, 0x88, 0x67, 0x00, 0x31, + 0x86, 0xe7, 0x80, 0x41, 0x88, 0xfd, 0x00, 0x45, 0x88, 0x67, 0x80, 0x00, 0x82, 0xfd, 0x80, 0x10, + 0x82, 0xe7, 0x80, 0x14, 0x82, 0x67, 0x80, 0x40, 0x92, 0xfd, 0x80, 0xd6, 0x86, 0xfb, 0x00, 0x34, + 0x86, 0xe7, 0x00, 0x35, 0x86, 0x67, 0x00, 0x30, 0x8e, 0xe7, 0x00, 0x31, 0x90, 0x67, 0x00, 0x00, + 0x00, 0x84, 0xfa, 0xe7, 0x81, 0x25, 0x2d, 0x95, 0xbf, 0x2e, 0xb5, 0xcc, 0xe0, 0x6a, 0xa2, 0xd1, + 0xc6, 0x3a, 0x48, 0xe8, 0x21, 0x75, 0xa9, 0x46, 0x3a, 0xab, 0x75, 0x56, 0xdc, 0xa3, 0x14, 0x49, + 0x6e, 0x41, 0xd3, 0x30, 0x13, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0x00, 0x42, + 0xa3, 0x00, 0xe0, 0x45, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x47, 0xe5, 0x20, 0xe0, 0x7d, + 0x22, 0x00, 0xe0, 0x49, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4b, 0xe5, 0x20, 0xe0, 0x7d, + 0x22, 0x00, 0xe0, 0x4d, 0xe5, 0x00, 0x20, 0x04, 0xf9, 0x00, 0x30, 0x06, 0xf9, 0x00, 0x40, 0x08, + 0xf9, 0x00, 0x50, 0x0a, 0xf9, 0x00, 0x60, 0x0c, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x11, 0x02, + 0xfd, 0x80, 0x21, 0x04, 0x7d, 0x00, 0x32, 0x06, 0xfd, 0x80, 0x42, 0x08, 0x7d, 0x00, 0x53, 0x0a, + 0x7d, 0x00, 0x60, 0x0c, 0xf3, 0x00, 0x00, 0x00, 0x84, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, + 0x22, 0x00, 0x40, 0x44, 0xe5, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x20, 0x2c, 0x63, 0x01, 0x60, 0x6b, + 0x22, 0x00, 0x00, 0x42, 0xa3, 0x04, 0x54, 0xe1, 0x35, 0x88, 0x90, 0x00, 0x9c, 0xff, 0x00, 0x40, + 0x23, 0x00, 0x00, 0xa3, 0xe2, 0x02, 0x10, 0x41, 0x28, 0x94, 0x90, 0x00, 0x8a, 0x00, 0x00, 0x21, + 0xf5, 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0xa3, 0xe2, 0x00, 0x20, 0x84, + 0x62, 0x00, 0x11, 0x41, 0xe8, 0xa0, 0x90, 0x00, 0x0a, 0x05, 0x54, 0xf3, 0xb5, 0x88, 0x90, 0x00, + 0x9c, 0x00, 0x03, 0x72, 0xc9, 0x05, 0x54, 0xc1, 0x39, 0x88, 0x90, 0x00, 0x9c, 0x00, 0x60, 0x6b, + 0xe3, 0x00, 0x54, 0xf5, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x01, 0x54, 0xef, 0xb5, 0xfa, 0x7e, 0x26, + 0x68, 0x69, 0x51, 0x4e, 0xa7, 0x96, 0xb2, 0x5f, 0x71, 0x3f, 0x4c, 0x46, 0x7d, 0x13, 0xfb, 0xc1, + 0xbe, 0x4b, 0xa8, 0x01, 0x84, 0x85, 0xfc, 0x5d, 0x70, 0x65, 0x0a, 0xb2, 0xb7, 0xeb, 0x08, 0x14, + 0x88, 0x90, 0x00, 0x9c, 0x02, 0x54, 0xfb, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x03, 0x54, 0xfd, 0x35, + 0x88, 0x90, 0x00, 0x9c, 0x05, 0x54, 0xc1, 0x39, 0x88, 0x90, 0x00, 0x9c, 0x60, 0x31, 0x7e, 0x45, + 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, + 0x00, 0xd0, 0xbb, 0xfb, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x71, 0xaf, 0xe8, 0x00, 0xe1, 0xbd, 0xe8, + 0x00, 0x7f, 0xa9, 0x68, 0xe0, 0x03, 0x74, 0x49, 0x00, 0x04, 0x7a, 0xc9, 0xa0, 0x00, 0x60, 0xc5, + 0x00, 0x00, 0x21, 0xf9, 0xc0, 0x00, 0x62, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, + 0x94, 0x81, 0x00, 0x98, 0x05, 0x54, 0xc1, 0x39, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, + 0x12, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x00, 0x84, + 0x6c, 0x90, 0x00, 0x82, 0xf2, 0x00, 0x40, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x6c, 0x90, 0x00, 0x82, + 0xf4, 0x00, 0x40, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x6c, 0x90, 0x00, 0x82, 0xf6, 0x00, 0x40, 0x23, + 0x94, 0x81, 0x00, 0x98, 0x00, 0x00, 0xce, 0x73, 0x00, 0x00, 0xd0, 0x73, 0x00, 0x00, 0xd2, 0xf3, + 0x00, 0x00, 0xd4, 0xf3, 0x00, 0x70, 0xc0, 0xe3, 0x0c, 0x40, 0xc1, 0xa5, 0x4c, 0xa3, 0x00, 0x02, + 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x30, 0x8f, 0x00, 0x02, + 0x08, 0x00, 0x56, 0x23, 0x12, 0x00, 0x58, 0x23, 0xfa, 0x64, 0xac, 0x5c, 0xef, 0x3e, 0x6f, 0x1f, + 0x4f, 0x50, 0xa6, 0xe6, 0x21, 0xf0, 0xa3, 0xb2, 0x04, 0x0a, 0x90, 0x05, 0xa1, 0x33, 0x2d, 0xcc, + 0x9e, 0xa1, 0x62, 0x55, 0x13, 0x17, 0xc3, 0x9e, 0x97, 0xe0, 0x14, 0x78, 0x8f, 0x00, 0x02, 0x01, + 0xc0, 0x58, 0x24, 0xe0, 0x90, 0x00, 0x8a, 0x00, 0x10, 0xc0, 0xe9, 0x01, 0xb0, 0x56, 0x24, 0xdc, + 0x90, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x70, + 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, 0x30, 0x8f, 0x00, 0x02, 0x80, 0x00, 0x5e, 0xa3, 0x00, + 0xf0, 0x1e, 0xf3, 0x00, 0xf0, 0x1e, 0xf3, 0x00, 0xf0, 0x1e, 0xf3, 0x12, 0xb0, 0x56, 0xa4, 0x80, + 0xb7, 0xa0, 0x62, 0x44, 0x91, 0x00, 0x8a, 0x12, 0x00, 0x58, 0x23, 0x78, 0x8f, 0x00, 0x02, 0x01, + 0xc0, 0x58, 0x24, 0x30, 0x91, 0x00, 0x8a, 0x00, 0x10, 0xc0, 0xe9, 0x20, 0x91, 0x00, 0x18, 0x12, + 0xb0, 0x56, 0xa2, 0x88, 0x91, 0x00, 0x08, 0x12, 0x00, 0x58, 0x23, 0x80, 0xc5, 0x58, 0xe4, 0x78, + 0x8f, 0x00, 0x02, 0x01, 0xb0, 0x56, 0x24, 0x54, 0x91, 0x00, 0x0a, 0x01, 0xc0, 0x40, 0x28, 0x9c, + 0x91, 0x00, 0x08, 0x04, 0x00, 0x44, 0x23, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x11, 0x02, 0xfd, 0x00, + 0x20, 0x04, 0xf3, 0x01, 0xc0, 0x58, 0x24, 0x70, 0x91, 0x00, 0x0a, 0x80, 0x10, 0x82, 0x24, 0xac, + 0x91, 0x00, 0x98, 0x00, 0x00, 0x42, 0xa3, 0x8a, 0x00, 0x46, 0xa3, 0x80, 0x11, 0xc2, 0xe2, 0x80, + 0x10, 0x82, 0x24, 0xac, 0x91, 0x00, 0x98, 0x84, 0x00, 0x44, 0xa3, 0x00, 0x20, 0x04, 0xf5, 0x00, + 0x11, 0x02, 0xfd, 0xac, 0x91, 0x00, 0x98, 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf6, 0x71, 0x00, + 0x00, 0xc0, 0x2d, 0xfa, 0x59, 0x7b, 0x63, 0xc0, 0xee, 0xc6, 0x9b, 0xa0, 0x32, 0x81, 0xa5, 0x59, + 0xa2, 0x93, 0xbf, 0x66, 0xb6, 0xff, 0x12, 0x2d, 0x14, 0xab, 0xf1, 0x1f, 0x0d, 0xfd, 0x47, 0x30, + 0xee, 0xff, 0x94, 0xe2, 0xb8, 0x15, 0x00, 0x70, 0xce, 0xeb, 0x00, 0x70, 0xd2, 0x6b, 0x00, 0x70, + 0xc0, 0xe3, 0x0c, 0xb0, 0xc1, 0xa5, 0x04, 0x00, 0x42, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x10, + 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xd0, 0x91, 0x00, 0x0a, 0x80, 0x10, 0x82, 0x24, 0x00, 0x10, + 0xc0, 0xe9, 0x00, 0x00, 0xf8, 0xf1, 0x60, 0x31, 0x7e, 0x45, 0x80, 0xcd, 0xb7, 0xf9, 0x00, 0x00, + 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x40, 0x31, 0x7e, 0xc5, 0xc0, 0x31, + 0x6a, 0x45, 0xe0, 0x31, 0x6c, 0xc5, 0xdc, 0x87, 0x00, 0x02, 0x01, 0x00, 0x42, 0x23, 0x80, 0x50, + 0xab, 0xe2, 0x00, 0x50, 0x2b, 0xed, 0x80, 0x6a, 0xad, 0xe4, 0x00, 0x60, 0x2d, 0xf9, 0x20, 0x03, + 0x6c, 0x49, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, + 0x7c, 0xa2, 0x00, 0xe0, 0x6b, 0x65, 0x00, 0x50, 0x2b, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, + 0x69, 0xe5, 0x00, 0x40, 0x29, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x67, 0x65, 0x00, 0x30, + 0x27, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x20, 0x25, 0xf9, 0x00, 0x00, + 0x00, 0x84, 0x00, 0x00, 0x4c, 0x23, 0x00, 0x60, 0x8a, 0x70, 0x60, 0xb0, 0x92, 0x22, 0x1f, 0xb0, + 0x90, 0x22, 0x20, 0x00, 0x4e, 0x23, 0x00, 0x74, 0x50, 0xe4, 0x00, 0x80, 0x4e, 0xe3, 0x00, 0x70, + 0x0e, 0x63, 0x00, 0x70, 0x0e, 0x63, 0x00, 0x70, 0x0e, 0x63, 0x01, 0x70, 0x4e, 0x24, 0xfa, 0xa9, + 0xb2, 0x57, 0x66, 0x9c, 0x35, 0xb5, 0x2a, 0xc5, 0x3e, 0x11, 0xe4, 0x6f, 0x61, 0x98, 0x2b, 0xb0, + 0x7a, 0x0e, 0x8f, 0x17, 0x96, 0x4c, 0xea, 0x5e, 0xfc, 0x49, 0xf1, 0x4c, 0x09, 0xb4, 0xa2, 0x90, + 0x16, 0x00, 0x53, 0x0a, 0x7d, 0x01, 0x80, 0x50, 0x24, 0x90, 0x92, 0x00, 0x8a, 0x00, 0x00, 0x00, + 0x84, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, + 0xa2, 0x00, 0xe0, 0x67, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, + 0xf9, 0x00, 0x20, 0x25, 0xf9, 0x00, 0x03, 0x68, 0x45, 0x20, 0x03, 0x6a, 0x45, 0x40, 0xb0, 0x7a, + 0xa2, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0x00, 0xc0, + 0x2d, 0x64, 0x92, 0x00, 0x82, 0x20, 0x90, 0x40, 0x28, 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, + 0xe3, 0xac, 0x93, 0x00, 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x67, + 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x20, 0x25, + 0xf9, 0x00, 0x03, 0x68, 0x45, 0x20, 0x03, 0x6a, 0x45, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x20, 0xe1, + 0x6b, 0x80, 0x00, 0x7a, 0xa3, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, + 0x98, 0x2c, 0x92, 0x00, 0x82, 0x00, 0x20, 0xe1, 0x6b, 0x80, 0xd0, 0x7b, 0x22, 0x00, 0x00, 0x40, + 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, + 0x63, 0x80, 0xd5, 0x7b, 0xe2, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, + 0x63, 0x2c, 0x92, 0x00, 0x82, 0x80, 0xb0, 0x40, 0xa8, 0xfa, 0x75, 0xb0, 0x59, 0x16, 0x9a, 0x8e, + 0x4f, 0x43, 0x63, 0xc7, 0xa3, 0xb3, 0xdd, 0x5d, 0x15, 0xaf, 0x7e, 0xe6, 0xfc, 0xa8, 0x82, 0x2f, + 0x74, 0x1c, 0x32, 0x1b, 0xe5, 0xb2, 0xb0, 0xef, 0xb6, 0x8b, 0x68, 0x17, 0xdc, 0x93, 0x00, 0x08, + 0x64, 0x92, 0x00, 0x82, 0x60, 0x90, 0x40, 0xa8, 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, 0xe3, + 0x40, 0x90, 0x40, 0x28, 0xac, 0x93, 0x00, 0x88, 0x00, 0x00, 0x66, 0xa3, 0x20, 0x90, 0x40, 0x28, + 0xa0, 0x93, 0x00, 0x88, 0x00, 0x00, 0x68, 0x23, 0x80, 0x52, 0xab, 0x62, 0x80, 0x53, 0xeb, 0x62, + 0xf8, 0x93, 0x00, 0x98, 0x80, 0x42, 0xa9, 0x62, 0x80, 0x43, 0xe9, 0x62, 0xf8, 0x93, 0x00, 0x98, + 0x80, 0x32, 0xa7, 0x62, 0x80, 0x33, 0xe7, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x22, 0xa5, 0x62, + 0x80, 0x23, 0xe5, 0x62, 0x10, 0xb0, 0x90, 0x22, 0xd0, 0x93, 0x00, 0x8a, 0x80, 0x2e, 0xa5, 0x64, + 0xf8, 0x93, 0x00, 0x98, 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x6a, 0xa3, 0xec, 0x93, 0x00, 0x98, + 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x6a, 0xa3, 0xff, 0x00, 0x4e, 0xa3, 0x80, 0x53, 0xeb, 0x62, + 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x66, 0xa3, 0x00, 0xd0, 0x65, 0xe3, 0x60, 0x31, 0x7e, 0x45, + 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x21, 0xf9, 0x00, 0x10, 0x23, 0xf9, 0x80, 0x08, 0xb3, 0x79, + 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x60, 0x31, 0x7e, 0x45, + 0xe0, 0x03, 0x74, 0x45, 0x00, 0x04, 0x44, 0x45, 0x80, 0xac, 0x83, 0xff, 0x80, 0x2c, 0x84, 0xff, + 0x80, 0xb0, 0x87, 0x7b, 0x00, 0x31, 0x86, 0x7b, 0x40, 0x03, 0x46, 0xc9, 0x40, 0x31, 0x7e, 0xc5, + 0xa0, 0x31, 0x4c, 0xc5, 0xfa, 0xda, 0xb9, 0xdf, 0xb9, 0x3a, 0x79, 0x0a, 0xfd, 0xc4, 0x2f, 0x5b, + 0x57, 0x99, 0x8f, 0xfa, 0x0f, 0xbe, 0x74, 0xd5, 0x42, 0xb0, 0xe9, 0x36, 0x5c, 0x51, 0x97, 0xea, + 0xe3, 0xcb, 0x5f, 0x40, 0xf8, 0x40, 0x18, 0x00, 0x03, 0x58, 0x45, 0x00, 0xc0, 0x18, 0xf9, 0x10, + 0x85, 0x00, 0x82, 0x00, 0x10, 0xbc, 0x28, 0x10, 0x95, 0x00, 0x8a, 0x01, 0x00, 0x5a, 0x23, 0x00, + 0xb6, 0x9c, 0x67, 0x00, 0x90, 0x79, 0xe3, 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x4e, 0xc9, 0x80, + 0x03, 0x50, 0x49, 0xa0, 0x03, 0x52, 0x49, 0xc0, 0x03, 0x54, 0x49, 0x40, 0x03, 0x78, 0x45, 0xc0, + 0x31, 0x56, 0x45, 0xe0, 0x31, 0x58, 0x45, 0x01, 0x00, 0x5a, 0x23, 0x00, 0xb6, 0x9c, 0x67, 0xa4, + 0x86, 0x00, 0x82, 0x60, 0x03, 0x56, 0xc5, 0x80, 0x03, 0x58, 0xc5, 0xa0, 0x03, 0x5a, 0xc5, 0xc0, + 0x03, 0x5c, 0xc5, 0x00, 0x00, 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, 0x00, 0x07, 0x9c, 0xfd, 0x18, + 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0xe4, + 0x84, 0x00, 0x82, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x20, 0x03, 0x48, 0x45, 0xff, + 0x0f, 0x7e, 0xa3, 0x00, 0xf0, 0x41, 0x28, 0x00, 0x82, 0x84, 0xe8, 0x18, 0x95, 0x00, 0x0a, 0x00, + 0xf0, 0x41, 0x28, 0x00, 0x82, 0x84, 0xe8, 0x18, 0x95, 0x00, 0x0a, 0xc3, 0x00, 0x44, 0xa3, 0x00, + 0xe0, 0x45, 0x69, 0x10, 0x00, 0x7c, 0x22, 0x40, 0x03, 0x4a, 0xc5, 0x00, 0x40, 0x08, 0xf9, 0x00, + 0xe0, 0x49, 0x69, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4b, 0xe9, 0x00, 0x00, 0x40, 0x23, 0x50, + 0x00, 0x42, 0xa3, 0x2c, 0x95, 0x00, 0x98, 0x36, 0x00, 0x40, 0x23, 0x1c, 0x95, 0x00, 0x98, 0xfa, + 0x30, 0xe6, 0xfb, 0x7f, 0x2a, 0xf0, 0xa2, 0x58, 0xc7, 0xc5, 0xe5, 0x50, 0x92, 0x10, 0x56, 0x96, + 0x57, 0x6a, 0xb8, 0x2d, 0x8b, 0x25, 0xbb, 0x29, 0xc3, 0x3c, 0xfc, 0x27, 0x2d, 0x7d, 0x7d, 0xe0, + 0x18, 0x19, 0x36, 0x00, 0x40, 0x23, 0x3c, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, + 0x42, 0x23, 0x2c, 0x95, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x94, 0x81, + 0x00, 0x98, 0x00, 0x00, 0x8c, 0x67, 0x00, 0x63, 0x8c, 0xfb, 0x01, 0x00, 0x7c, 0xa3, 0x00, 0x6f, + 0x8e, 0x7b, 0x00, 0x70, 0xbc, 0x28, 0x6c, 0x96, 0x00, 0x88, 0x60, 0x32, 0x50, 0x45, 0x00, 0x00, + 0x7c, 0x23, 0x00, 0xe4, 0x93, 0x7d, 0x00, 0x83, 0x90, 0x67, 0x80, 0x73, 0x94, 0x67, 0x80, 0xa3, + 0x96, 0x67, 0x80, 0x84, 0x90, 0x67, 0x00, 0x85, 0x90, 0xfb, 0x80, 0x84, 0x90, 0x67, 0x80, 0xb5, + 0x98, 0x67, 0x00, 0xc6, 0x94, 0x67, 0x80, 0xc5, 0x98, 0xe7, 0x00, 0xc4, 0x98, 0xe7, 0x00, 0xa6, + 0x94, 0x67, 0x00, 0xa0, 0x42, 0x63, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, + 0x84, 0xe7, 0x00, 0x25, 0x9a, 0x67, 0x00, 0xd6, 0x9a, 0x67, 0x00, 0x32, 0x7c, 0xc5, 0x00, 0xdf, + 0x9c, 0x67, 0x80, 0xd6, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa4, 0x88, 0x68, 0xc0, 0x95, + 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, 0xc8, 0x95, 0x00, 0x98, 0x00, 0xe0, 0x42, 0xe3, 0xc8, 0x95, + 0x00, 0x98, 0x00, 0x93, 0x84, 0xe7, 0x00, 0xd0, 0x86, 0xe7, 0x01, 0xe0, 0x89, 0xa4, 0x00, 0x32, + 0x86, 0xe7, 0x00, 0x3f, 0x88, 0xe7, 0x00, 0x83, 0x8c, 0xe7, 0x80, 0x31, 0x94, 0x67, 0x80, 0xa5, + 0x94, 0xe7, 0x00, 0xa3, 0xbc, 0xfd, 0x00, 0xe0, 0xbd, 0xa8, 0xfa, 0xd4, 0x97, 0xea, 0x47, 0xf7, + 0x3e, 0x32, 0x88, 0x67, 0x95, 0x4d, 0x2b, 0xe6, 0x7b, 0x73, 0xf1, 0x99, 0xfe, 0xdd, 0x52, 0x43, + 0x10, 0xdc, 0x8e, 0x91, 0x94, 0xb6, 0x1b, 0xb8, 0xad, 0xd3, 0xbc, 0xf0, 0x19, 0xfc, 0x95, 0x00, + 0x0a, 0x00, 0x30, 0x40, 0xe3, 0x04, 0x96, 0x00, 0x98, 0x00, 0x40, 0x40, 0x63, 0x04, 0x96, 0x00, + 0x98, 0x80, 0x10, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa4, 0xbc, 0x7d, 0x00, 0xe0, 0xbd, + 0xa8, 0x20, 0x96, 0x00, 0x8a, 0x00, 0x90, 0x46, 0xe3, 0x28, 0x96, 0x00, 0x18, 0x00, 0x20, 0x46, + 0x63, 0x28, 0x96, 0x00, 0x18, 0x38, 0x96, 0x00, 0x8a, 0x00, 0x10, 0x44, 0xe3, 0x01, 0x00, 0x7c, + 0xa3, 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, 0x44, 0x63, 0x00, 0x00, 0x7c, 0x23, 0x44, 0x96, 0x00, + 0x18, 0x00, 0x00, 0x40, 0x23, 0x00, 0x01, 0x82, 0xfd, 0x01, 0x00, 0x50, 0x23, 0x00, 0x24, 0x8c, + 0x62, 0x00, 0xe3, 0xbd, 0x68, 0x64, 0x96, 0x00, 0x08, 0x00, 0x10, 0x56, 0xe3, 0x6c, 0x96, 0x00, + 0x18, 0x00, 0x20, 0x56, 0xe3, 0x6c, 0x96, 0x00, 0x18, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xc4, + 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, 0x02, 0x00, 0x70, 0xbc, + 0x28, 0x70, 0x96, 0x00, 0x08, 0x80, 0xb3, 0x9a, 0xe7, 0x00, 0x30, 0x56, 0x63, 0x00, 0x70, 0x58, + 0x63, 0x00, 0x00, 0x00, 0x84, 0x40, 0x31, 0x7e, 0xc5, 0x00, 0x05, 0x42, 0xc5, 0x00, 0x00, 0xc4, + 0x73, 0xb4, 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, 0x02, 0x00, 0x70, 0xbc, 0x28, 0x98, 0x96, 0x00, + 0x08, 0x00, 0x33, 0x7c, 0x45, 0x00, 0x3f, 0x94, 0x67, 0x80, 0x75, 0x9a, 0xe7, 0x80, 0x33, 0x98, + 0x7d, 0x80, 0x33, 0x9c, 0xfb, 0xfa, 0x56, 0xf0, 0x2e, 0x56, 0x18, 0xff, 0xc5, 0x45, 0xfb, 0x61, + 0xa3, 0xf0, 0xb3, 0xa6, 0x3e, 0x19, 0x55, 0x5a, 0x52, 0x42, 0x0b, 0x0d, 0xf5, 0xb1, 0x43, 0x89, + 0x14, 0xc7, 0xbe, 0x58, 0xeb, 0xcd, 0xc8, 0x1a, 0x00, 0xd7, 0x80, 0x67, 0x00, 0x00, 0xbc, 0xa8, + 0x98, 0x96, 0x00, 0x08, 0x00, 0xa7, 0x96, 0x67, 0x80, 0xc6, 0x98, 0xe7, 0x00, 0xb6, 0x9c, 0x67, + 0x00, 0xb0, 0x96, 0x67, 0x00, 0xc0, 0x98, 0x67, 0x00, 0x00, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x08, 0x8d, 0xef, 0x00, 0x06, 0x8f, 0xef, 0x80, 0x63, 0x8c, 0x6f, 0x00, 0x60, 0x42, 0x63, + 0xa4, 0x82, 0x00, 0x02, 0x00, 0x30, 0x52, 0xe3, 0x80, 0x93, 0x92, 0x6f, 0x00, 0x31, 0x40, 0xc5, + 0x00, 0x90, 0x94, 0xef, 0x80, 0x94, 0x90, 0x6f, 0x00, 0x88, 0x90, 0x6f, 0x00, 0x86, 0x80, 0xe8, + 0x00, 0x90, 0x54, 0xef, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x68, 0xe3, 0x20, 0x31, 0x40, 0x45, + 0x60, 0x30, 0x42, 0xc5, 0x80, 0x30, 0x44, 0x45, 0x00, 0x4a, 0x97, 0x6f, 0x80, 0x05, 0x96, 0xef, + 0x80, 0xb5, 0x98, 0xef, 0x80, 0xc5, 0x98, 0x7b, 0x01, 0x00, 0x48, 0x23, 0x00, 0xc2, 0x9a, 0xfb, + 0x80, 0x26, 0x9a, 0x6f, 0x00, 0x00, 0x48, 0xa3, 0x00, 0x46, 0x9c, 0xfd, 0x00, 0xc0, 0x80, 0xa8, + 0x00, 0xe0, 0x40, 0x6f, 0x00, 0x17, 0x9c, 0x6f, 0x80, 0xd6, 0x98, 0xef, 0x00, 0xe7, 0xa0, 0x6f, + 0x00, 0x18, 0x9e, 0xef, 0x80, 0xc7, 0x98, 0xfb, 0x80, 0xc6, 0x98, 0x6f, 0x00, 0x07, 0xa1, 0x6f, + 0x00, 0x28, 0x9e, 0xef, 0x80, 0xc7, 0x98, 0xfb, 0x80, 0xb6, 0xa2, 0xef, 0xf0, 0x96, 0x00, 0x82, + 0x00, 0xba, 0xa4, 0x6f, 0x00, 0x25, 0xa5, 0xef, 0x00, 0xd0, 0x62, 0x6f, 0x00, 0xa0, 0x64, 0xef, + 0xfa, 0xa7, 0x55, 0x48, 0xc0, 0x14, 0xe8, 0x07, 0x3a, 0x4e, 0x5e, 0x5f, 0xf6, 0x2a, 0xf3, 0x22, + 0xe4, 0x64, 0xff, 0x8a, 0x63, 0x2b, 0x04, 0x82, 0xa0, 0x05, 0x12, 0x9d, 0x6a, 0xd2, 0x46, 0xba, + 0x1b, 0xa0, 0x1b, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x19, 0x82, 0xfd, 0x00, 0x49, 0x81, 0x68, 0x01, + 0x00, 0x44, 0x23, 0x00, 0x01, 0x80, 0xe2, 0x00, 0x10, 0x64, 0x6f, 0x00, 0x10, 0x64, 0x63, 0x00, + 0x27, 0xa5, 0x6f, 0x00, 0xe0, 0x66, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x42, 0xc5, 0x00, + 0x00, 0xc4, 0x73, 0xb4, 0xa3, 0x00, 0x82, 0x28, 0x97, 0x00, 0x02, 0x00, 0x30, 0xbd, 0x28, 0xc8, + 0x97, 0x00, 0x88, 0x00, 0x00, 0x00, 0x84, 0x20, 0x30, 0x7e, 0x45, 0x60, 0x10, 0x40, 0x28, 0x18, + 0x98, 0x00, 0x08, 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x66, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, + 0x00, 0x68, 0x23, 0x80, 0x49, 0xb9, 0x79, 0x80, 0xc9, 0x83, 0xe8, 0xb4, 0x99, 0x00, 0x0a, 0x00, + 0xc0, 0x83, 0xa8, 0xb4, 0x99, 0x00, 0x88, 0x2c, 0x98, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, 0x00, + 0x00, 0xe8, 0xf3, 0x80, 0x49, 0xb9, 0x79, 0x00, 0xc0, 0x83, 0xa8, 0xb4, 0x99, 0x00, 0x88, 0x00, + 0x00, 0xc0, 0xf3, 0x00, 0x00, 0xc2, 0x73, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x00, 0xc6, 0xf3, 0x00, + 0x00, 0xc0, 0x63, 0x0a, 0xc0, 0xc1, 0x25, 0x04, 0x00, 0x44, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, + 0x20, 0x04, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x4c, 0x98, 0x00, 0x0a, 0x80, 0x20, 0x84, 0x24, 0x00, + 0x20, 0xc0, 0xe9, 0x00, 0x00, 0xfa, 0x71, 0x20, 0x01, 0x78, 0xc9, 0x40, 0x01, 0x7a, 0x49, 0x20, + 0x30, 0x7e, 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xcf, 0xf9, 0xff, 0xfa, 0x0a, 0x18, 0x3d, 0xcc, + 0x7e, 0x57, 0x62, 0xa1, 0x26, 0x2f, 0xb5, 0x6d, 0x83, 0x49, 0x21, 0x2b, 0x1a, 0xc2, 0x51, 0x01, + 0x90, 0x28, 0x8f, 0x96, 0x8a, 0x2d, 0x24, 0x51, 0x54, 0x84, 0x69, 0x13, 0x78, 0x1c, 0x00, 0x30, + 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, 0xc0, 0x30, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0x00, + 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x9c, 0xa4, 0x00, 0xc7, + 0x98, 0x6f, 0x00, 0xd7, 0x9a, 0x6f, 0x00, 0xc0, 0x52, 0xe3, 0x00, 0xd0, 0x54, 0x63, 0x00, 0xe0, + 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0xc0, 0x99, 0x00, 0x0a, 0x80, 0x30, 0x50, 0x45, 0xd8, 0x8a, + 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0xc0, 0x99, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0xc0, 0x99, + 0x00, 0x0a, 0x00, 0xb0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0x90, 0x92, 0x6f, 0x80, 0xa0, + 0x94, 0x6f, 0x00, 0x90, 0x19, 0x6d, 0x00, 0xc0, 0x18, 0xf3, 0xaa, 0xc0, 0x98, 0xa4, 0x00, 0xc0, + 0x18, 0xf3, 0x00, 0x01, 0x40, 0xc5, 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0xa8, 0xe2, 0x60, 0x40, + 0x41, 0xa8, 0x08, 0x99, 0x00, 0x08, 0x02, 0xc0, 0x98, 0x24, 0x0c, 0x99, 0x00, 0x18, 0x01, 0xc0, + 0x98, 0x24, 0x00, 0xc0, 0x18, 0xf3, 0x01, 0xc0, 0x98, 0x24, 0x04, 0xa4, 0xd9, 0x37, 0xb4, 0x99, + 0x00, 0x9c, 0x05, 0xa4, 0xd3, 0xb7, 0xb4, 0x99, 0x00, 0x9c, 0x06, 0xa4, 0xd5, 0xb7, 0xb4, 0x99, + 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, + 0x00, 0x9c, 0x20, 0x01, 0x78, 0xc5, 0x40, 0x01, 0x7a, 0x45, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, + 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xfa, 0x3c, 0xed, 0xbe, 0x46, 0xd8, 0x59, 0xda, 0x89, 0x4e, + 0xc7, 0x62, 0x32, 0x08, 0x45, 0x4a, 0x9d, 0x19, 0xea, 0x22, 0x0b, 0xa5, 0x85, 0x3b, 0xd2, 0x0f, + 0xd1, 0xe1, 0xd9, 0x8b, 0xe6, 0x1c, 0x63, 0x50, 0x1d, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xc0, 0xb9, + 0xfd, 0x00, 0x00, 0xc4, 0x73, 0x00, 0xd1, 0xbb, 0xe8, 0x00, 0x90, 0x75, 0xe3, 0xff, 0x00, 0x52, + 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, 0x80, 0xc4, 0x94, 0x68, 0x00, 0xa4, 0xf9, + 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, + 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x03, 0xa4, 0xc5, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x04, 0xa4, 0xd5, + 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, + 0x39, 0xb4, 0x99, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, + 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0x41, 0x00, 0x46, + 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x10, 0x40, 0x28, 0xe0, 0x99, 0x00, 0x08, 0x10, 0x00, 0x48, + 0xa2, 0x00, 0x40, 0x66, 0xe5, 0xe4, 0x99, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, 0x01, 0x00, 0x64, + 0xa3, 0x00, 0x20, 0x25, 0xed, 0x00, 0x00, 0x62, 0x23, 0x00, 0x01, 0x60, 0x23, 0x00, 0x30, 0x27, + 0xf9, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xf9, 0xeb, 0x00, 0xd0, 0x3b, 0xf9, 0x07, 0x00, 0x40, + 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x0e, 0xba, + 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0xd0, 0xfb, 0x62, 0x00, 0xc0, 0x39, 0xf9, 0x20, 0x01, 0x7a, + 0x49, 0xfa, 0x74, 0x00, 0x84, 0x6a, 0x47, 0x27, 0x25, 0xea, 0xf0, 0x57, 0xa0, 0x09, 0x22, 0x76, + 0x26, 0x53, 0x1f, 0x98, 0x62, 0x39, 0xfe, 0x8b, 0x22, 0xe1, 0xe7, 0x8a, 0xa7, 0x8e, 0xf9, 0x6f, + 0x53, 0xa2, 0x28, 0x1e, 0x40, 0x01, 0x78, 0xc9, 0x00, 0x00, 0xfc, 0xf3, 0x60, 0x31, 0x7e, 0x45, + 0x00, 0xdf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xc0, 0x31, 0x56, 0x45, 0xe0, 0x31, 0x58, 0x45, + 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x9a, 0xa4, + 0x80, 0xb6, 0x96, 0xe7, 0x00, 0xb6, 0x9c, 0x67, 0x80, 0xc6, 0x98, 0xe7, 0xa0, 0x31, 0x4c, 0xc5, + 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0x00, 0xe0, 0x54, 0x63, + 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, + 0x70, 0x9b, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, 0xe4, 0x84, 0x00, 0x82, + 0x00, 0x90, 0x15, 0x6d, 0x00, 0xa0, 0x14, 0xf3, 0xaa, 0xa0, 0x94, 0xa4, 0x00, 0xa0, 0x14, 0xf3, + 0x00, 0x01, 0x40, 0xc5, 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0x92, 0xe2, 0x60, 0x90, 0x40, 0xa8, + 0xc0, 0x9a, 0x00, 0x88, 0x02, 0xa0, 0x94, 0x24, 0xc4, 0x9a, 0x00, 0x98, 0x01, 0xa0, 0x94, 0x24, + 0x00, 0xa0, 0x14, 0xf3, 0x02, 0xa0, 0x94, 0x24, 0x04, 0xa4, 0xd5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, + 0x05, 0xa4, 0xd1, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0x7c, 0x9b, 0x00, 0x9c, + 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0x9b, 0x00, 0x9c, 0x20, 0x01, 0x78, 0xc5, 0x40, 0x01, 0x7a, 0x45, + 0x00, 0x00, 0x40, 0x23, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x0e, 0xbc, 0xf9, 0xfa, 0x57, 0xbb, 0x85, + 0x1e, 0xd3, 0x3e, 0xdc, 0x5d, 0x59, 0xf1, 0x6e, 0x06, 0x42, 0x42, 0x57, 0x42, 0xdf, 0xff, 0x6c, + 0xd1, 0x5d, 0xf6, 0x9b, 0x8d, 0x29, 0xc1, 0xf8, 0xfc, 0x13, 0xad, 0xd8, 0x1b, 0x00, 0x1f, 0x00, + 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x80, 0x24, 0x00, + 0xe0, 0xb9, 0x7d, 0x00, 0x00, 0xc4, 0x73, 0x00, 0xd1, 0xbb, 0xe8, 0x00, 0x90, 0x75, 0xe3, 0xff, + 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, 0x80, 0xa4, 0x94, 0x68, 0x00, + 0xa4, 0xf9, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, + 0xa4, 0xc1, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x03, 0xa4, 0xc5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x04, + 0xa4, 0xd5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0x7c, 0x9b, 0x00, 0x9c, 0x05, + 0xa4, 0xc1, 0x39, 0x7c, 0x9b, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x05, + 0xa4, 0xc1, 0x39, 0x41, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0xf2, + 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xc6, 0xf3, 0x00, 0x00, 0xc8, 0x73, 0x00, + 0x00, 0xca, 0xf3, 0x00, 0x00, 0xcc, 0xf3, 0x00, 0x30, 0xc0, 0x63, 0x0b, 0x40, 0xc1, 0x25, 0x4c, + 0xa3, 0x00, 0x02, 0x00, 0x00, 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x43, 0x63, 0x80, + 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xb0, 0x9b, 0x00, 0x0a, 0x00, + 0x00, 0xc0, 0x69, 0x0e, 0x00, 0x7c, 0xa3, 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, + 0xe0, 0x7d, 0x24, 0xc8, 0x9b, 0x00, 0x0a, 0xfa, 0xe7, 0x31, 0xf9, 0x5f, 0x54, 0x95, 0xa3, 0x9a, + 0xf5, 0x8b, 0xfb, 0xc1, 0xca, 0x99, 0x0f, 0x83, 0x16, 0xec, 0xa5, 0xe0, 0x60, 0xab, 0xa6, 0x3b, + 0xe4, 0xff, 0xed, 0x0a, 0x83, 0xe6, 0xe2, 0x41, 0xd8, 0x1f, 0x04, 0x00, 0x7c, 0xa3, 0x00, 0x00, + 0x42, 0xa3, 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xe0, 0x9b, + 0x00, 0x0a, 0x1a, 0x00, 0x7c, 0xa3, 0x00, 0x0f, 0xc0, 0xe2, 0x80, 0x00, 0x80, 0x24, 0x00, 0x00, + 0xc0, 0x69, 0x00, 0x00, 0xf6, 0x71, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x30, 0xc6, 0xeb, 0x00, 0x30, + 0xca, 0xeb, 0x00, 0x30, 0xc0, 0x63, 0x0b, 0xb0, 0xc1, 0x25, 0x04, 0x00, 0x42, 0x23, 0x11, 0x00, + 0x7c, 0x23, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x20, 0x9c, 0x00, 0x8a, 0x80, 0x10, + 0x82, 0x24, 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf8, 0xf1, 0x20, 0x01, 0x64, 0x49, 0x20, 0x30, + 0x7e, 0x45, 0x80, 0xcd, 0xb7, 0xf9, 0x00, 0xb0, 0x81, 0xa8, 0xdc, 0x9d, 0x00, 0x88, 0xa0, 0x30, + 0x6c, 0xc5, 0xc0, 0x30, 0x6e, 0x45, 0xa8, 0x8b, 0x00, 0x02, 0x00, 0x00, 0x46, 0xe3, 0x00, 0x00, + 0x40, 0xa8, 0xfc, 0x9d, 0x00, 0x8a, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x0b, + 0xac, 0x79, 0x00, 0x60, 0x81, 0x28, 0xe4, 0x9d, 0x00, 0x08, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, + 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0x00, 0x72, 0x63, 0x01, 0x90, 0xb3, 0x24, 0x80, 0x9d, + 0x83, 0x7f, 0xa8, 0x81, 0x00, 0x02, 0x20, 0x01, 0x64, 0x45, 0x80, 0x2c, 0x95, 0xff, 0x80, 0x6c, + 0x97, 0xff, 0x80, 0xa5, 0x99, 0x7f, 0x80, 0x55, 0x9b, 0xff, 0x80, 0xc6, 0x96, 0xfb, 0x80, 0xa5, + 0x94, 0x7b, 0xfa, 0xb6, 0x34, 0x55, 0x42, 0x77, 0x97, 0x45, 0x21, 0xc7, 0x79, 0x07, 0x46, 0x3b, + 0xe8, 0x68, 0x0d, 0x03, 0x8f, 0x8c, 0xf5, 0xef, 0xb4, 0x72, 0x02, 0xe7, 0xe8, 0xa9, 0xa6, 0x55, + 0x58, 0x19, 0xff, 0xb0, 0x20, 0x00, 0x15, 0x94, 0xff, 0x00, 0xa0, 0x80, 0xa8, 0xec, 0x9d, 0x00, + 0x88, 0x40, 0x01, 0x54, 0x49, 0x00, 0xa0, 0x42, 0x63, 0xa8, 0x81, 0x00, 0x02, 0x80, 0x20, 0xb9, + 0x7f, 0x80, 0x60, 0xb7, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, 0xc0, 0x30, 0x5a, + 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x94, 0x8a, 0x00, 0x82, 0x00, 0x90, 0x5e, 0xe3, 0x00, 0xa0, 0x60, + 0x63, 0x00, 0xb0, 0x62, 0x63, 0x60, 0x01, 0x58, 0xc5, 0x80, 0x01, 0x5a, 0xc5, 0x01, 0x00, 0x5c, + 0x23, 0x00, 0xb0, 0x79, 0x63, 0x94, 0x8a, 0x00, 0x82, 0x80, 0xf5, 0x84, 0xef, 0x80, 0x98, 0x86, + 0xef, 0x80, 0x21, 0x80, 0xe8, 0x38, 0x9d, 0x00, 0x0a, 0x80, 0x05, 0x85, 0x6f, 0x80, 0xa8, 0x86, + 0xef, 0x80, 0x21, 0x80, 0xe8, 0xf4, 0x9d, 0x00, 0x0a, 0xfc, 0x89, 0x00, 0x02, 0x00, 0x90, 0x58, + 0xe3, 0x00, 0xa0, 0x5a, 0x63, 0x00, 0xb0, 0x5c, 0xe3, 0x48, 0x9d, 0x00, 0x98, 0x00, 0xf0, 0x58, + 0xe3, 0x00, 0x00, 0x5b, 0xe3, 0x00, 0x10, 0x5d, 0x63, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe0, 0x42, + 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0xc0, 0x98, 0x6f, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, + 0x23, 0x00, 0x06, 0x98, 0x79, 0x00, 0x00, 0x7e, 0xa3, 0x00, 0xf0, 0x41, 0x28, 0x00, 0xcb, 0x82, + 0x68, 0xf4, 0x9d, 0x00, 0x0a, 0x00, 0xf0, 0x41, 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, 0x9d, 0x00, + 0x0a, 0x00, 0x00, 0x46, 0x23, 0xc3, 0x00, 0x44, 0xa3, 0x64, 0x81, 0x00, 0x02, 0xfa, 0x44, 0x15, + 0x4c, 0xfa, 0xd5, 0x8b, 0x7c, 0x6e, 0x02, 0xe0, 0xfc, 0xb0, 0xb4, 0x94, 0x26, 0x22, 0xd4, 0x1c, + 0xba, 0xa2, 0x21, 0xf9, 0xb8, 0x62, 0x7d, 0x95, 0x40, 0xea, 0x98, 0xd9, 0x0a, 0xc4, 0x88, 0x21, + 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x45, 0x69, 0x00, 0x30, 0x40, 0xa8, 0x01, 0x00, 0x42, 0x23, + 0xbc, 0x9d, 0x00, 0x0a, 0x50, 0x00, 0x42, 0xa3, 0x10, 0x00, 0x7c, 0x22, 0x00, 0x60, 0x2d, 0xf9, + 0x00, 0xe0, 0x6d, 0x69, 0x20, 0xe0, 0x7d, 0x22, 0x40, 0x01, 0x54, 0x45, 0x00, 0xa0, 0x14, 0xf9, + 0x00, 0xe0, 0x55, 0xe9, 0x00, 0x30, 0x40, 0xe3, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, + 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x76, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, + 0x94, 0x81, 0x00, 0x98, 0x21, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, 0x22, 0x00, 0x46, 0x23, + 0xfc, 0x9d, 0x00, 0x98, 0x23, 0x00, 0x46, 0xa3, 0xfc, 0x9d, 0x00, 0x98, 0x24, 0x00, 0x46, 0x23, + 0xfc, 0x9d, 0x00, 0x98, 0x3c, 0x00, 0x44, 0xa3, 0x01, 0x00, 0x42, 0x23, 0x84, 0x9d, 0x00, 0x98, + 0xa8, 0xa4, 0x00, 0x18, 0x40, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0x40, 0x23, 0x00, 0x08, 0x80, 0xf9, + 0x00, 0x08, 0x80, 0xe8, 0xdc, 0x9e, 0x00, 0x0a, 0xd8, 0x8c, 0x00, 0x02, 0xdc, 0x9e, 0x00, 0x0a, + 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xa4, 0x24, + 0x00, 0x09, 0xa1, 0x67, 0x00, 0x19, 0xa3, 0x67, 0x00, 0x00, 0xfc, 0xf3, 0x80, 0x31, 0x7e, 0xc5, + 0x00, 0x3f, 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, 0x70, 0x96, 0x00, 0x02, 0x5c, 0x8e, 0x00, 0x82, + 0xd0, 0x8e, 0x00, 0x02, 0x00, 0x70, 0x6e, 0x63, 0xfa, 0xc8, 0x1f, 0xb9, 0x96, 0xa7, 0x51, 0x28, + 0xba, 0x6c, 0xad, 0x2c, 0x24, 0xbc, 0xe5, 0x74, 0xab, 0x56, 0x9c, 0x31, 0x38, 0xd5, 0xe3, 0x4d, + 0x97, 0xc9, 0x21, 0x13, 0x78, 0xd2, 0x9e, 0xc0, 0x26, 0x60, 0x22, 0x00, 0x80, 0x70, 0x63, 0x00, + 0x90, 0x72, 0x63, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x4f, 0xe3, 0x00, + 0x20, 0x51, 0x63, 0x00, 0x10, 0x53, 0xe3, 0x0c, 0x8d, 0x00, 0x82, 0x00, 0x00, 0xfc, 0xf3, 0x80, + 0x31, 0x7e, 0xc5, 0x00, 0x3f, 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, 0x5c, 0x8e, 0x00, 0x82, 0xd0, + 0x8e, 0x00, 0x02, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x80, + 0x04, 0x92, 0xfd, 0x00, 0x70, 0x57, 0x63, 0x00, 0x80, 0x59, 0xe3, 0x00, 0x90, 0x5b, 0xe3, 0x0c, + 0x8d, 0x00, 0x82, 0x00, 0xc0, 0x42, 0x63, 0x74, 0x84, 0x00, 0x82, 0x80, 0xb0, 0x96, 0xe7, 0x80, + 0xd0, 0x9a, 0xe7, 0x01, 0x00, 0x58, 0xa3, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, 0x00, + 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x12, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, + 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0xa8, 0xa4, 0x00, 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, + 0x00, 0x48, 0x22, 0x00, 0x40, 0x48, 0xe5, 0xff, 0x00, 0x44, 0xa3, 0x00, 0x41, 0x82, 0xe2, 0x00, + 0x40, 0x32, 0xf5, 0x00, 0x90, 0x09, 0xf5, 0x00, 0x40, 0x08, 0xf5, 0x00, 0x91, 0xb3, 0xe2, 0x00, + 0x41, 0x88, 0xe2, 0x00, 0x00, 0x00, 0x84, 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x33, 0x63, 0x04, + 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x01, 0x90, 0x75, 0x22, 0x04, 0xa4, 0xc1, 0xb9, 0x7c, + 0xa0, 0x00, 0x1c, 0xfa, 0x00, 0x72, 0xd2, 0x6e, 0xd2, 0xe3, 0x5f, 0x40, 0x84, 0x2d, 0x3e, 0xf2, + 0x2d, 0x12, 0xc5, 0xae, 0x85, 0xd7, 0xfe, 0x1b, 0x0e, 0xea, 0xf2, 0x46, 0x6b, 0x3c, 0x05, 0x44, + 0x39, 0x64, 0x1d, 0x3a, 0x38, 0x23, 0x02, 0x40, 0x40, 0xa8, 0x54, 0x9f, 0x00, 0x08, 0x01, 0x40, + 0x40, 0xa8, 0x70, 0x9f, 0x00, 0x08, 0xf4, 0x00, 0x46, 0xa3, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, + 0x00, 0x98, 0xcc, 0x99, 0x00, 0x82, 0x00, 0x30, 0x40, 0xa8, 0x68, 0x9f, 0x00, 0x08, 0x3c, 0x00, + 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xc3, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xe4, 0x97, + 0x00, 0x02, 0x00, 0x30, 0x40, 0xa8, 0x84, 0x9f, 0x00, 0x88, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, + 0x00, 0x98, 0xc3, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, + 0x40, 0xa2, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x44, 0x69, 0x00, 0x30, 0x40, 0xe3, 0x00, 0xa1, + 0x00, 0x98, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x68, 0xe3, 0x00, 0x40, 0x6b, 0x22, 0xf0, 0x9e, + 0x00, 0x02, 0x00, 0x90, 0x35, 0x63, 0x01, 0xa0, 0x75, 0x22, 0xf2, 0x00, 0x46, 0xa3, 0x04, 0xa4, + 0xc1, 0xb9, 0x70, 0xa0, 0x00, 0x9e, 0x04, 0xa4, 0xc5, 0x35, 0x7c, 0xa0, 0x00, 0x1c, 0xf6, 0x00, + 0x46, 0x23, 0xff, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x4a, 0x63, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, + 0x88, 0xe2, 0x01, 0x40, 0x40, 0xa8, 0xf4, 0x9f, 0x00, 0x08, 0x02, 0x40, 0x40, 0xa8, 0x70, 0xa0, + 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0xaa, 0x40, 0x40, 0x28, 0x70, 0xa0, + 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0x80, 0x4c, 0x40, 0x68, 0xfa, 0xd3, + 0x36, 0xc2, 0x83, 0x56, 0x05, 0x40, 0x8b, 0x12, 0x77, 0x1d, 0xbe, 0x27, 0xd9, 0x8c, 0x73, 0xa0, + 0xc2, 0xbf, 0x31, 0xe5, 0xfc, 0x43, 0x91, 0x4d, 0xd7, 0x5d, 0xf6, 0x8f, 0x2b, 0x7a, 0x53, 0x10, + 0x24, 0x70, 0xa0, 0x00, 0x8a, 0xf4, 0x00, 0x46, 0xa3, 0x00, 0xe1, 0xbd, 0xe2, 0x02, 0xe0, 0x41, + 0x28, 0x44, 0xa0, 0x00, 0x88, 0x01, 0xe0, 0x41, 0x28, 0x70, 0xa0, 0x00, 0x8a, 0x50, 0x00, 0x42, + 0xa3, 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, 0x00, 0x1c, 0x06, 0xa4, 0xe3, 0x35, 0x7c, 0xa0, 0x00, + 0x1c, 0x50, 0xa0, 0x00, 0x18, 0x30, 0x00, 0x42, 0xa3, 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, 0x00, + 0x1c, 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0xff, 0x0f, 0x4a, 0x23, 0x80, 0x22, 0x84, + 0x62, 0x00, 0x20, 0x04, 0xf3, 0xc3, 0x20, 0x84, 0xa4, 0x00, 0x00, 0x40, 0x23, 0x8c, 0xa0, 0x00, + 0x98, 0x12, 0x00, 0x44, 0xa3, 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, 0x00, 0x98, 0x3c, 0x00, 0x44, + 0xa3, 0xf2, 0x00, 0x46, 0xa3, 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, 0x00, 0x98, 0x00, 0x50, 0x45, + 0xe9, 0x10, 0x40, 0x6d, 0xa2, 0x00, 0x00, 0x21, 0xf9, 0x00, 0x60, 0x61, 0xe9, 0x20, 0x60, 0x6d, + 0x22, 0x00, 0x10, 0x23, 0xf9, 0x00, 0x60, 0x63, 0x69, 0x00, 0x00, 0x40, 0x23, 0x00, 0xa1, 0x00, + 0x98, 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x33, 0x63, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x6a, + 0x22, 0x03, 0x94, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, + 0x1c, 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, 0x73, 0x22, 0x03, 0x94, 0xc1, 0x39, 0x7c, 0xa0, 0x00, + 0x1c, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0xfa, 0x09, 0xc7, 0x2d, 0xc3, 0x0b, 0xf5, + 0xce, 0x45, 0x87, 0x3e, 0x32, 0x85, 0xdf, 0xd4, 0xa4, 0xa2, 0x3d, 0xf0, 0x8c, 0xf2, 0xb9, 0x08, + 0x5f, 0xfe, 0x0c, 0x86, 0xca, 0xec, 0x0b, 0xab, 0xcb, 0x87, 0xe8, 0x24, 0x05, 0x94, 0xc1, 0x39, + 0xc3, 0x00, 0x44, 0xa3, 0x00, 0x50, 0x45, 0xe9, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x40, 0x23, + 0x00, 0xa1, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x78, 0xa3, + 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x44, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x94, 0x81, 0x00, 0x98, + 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, 0x22, 0x00, 0x40, 0x48, 0xe5, 0x00, 0x40, 0x04, 0xf5, + 0xff, 0x00, 0x4c, 0x23, 0x00, 0x23, 0x84, 0x62, 0x00, 0x20, 0x32, 0x63, 0x01, 0x90, 0xb3, 0x24, + 0x04, 0x94, 0xcb, 0xb5, 0x0c, 0xa2, 0x00, 0x1c, 0xff, 0x00, 0x4c, 0x23, 0x00, 0x53, 0x8e, 0xe2, + 0x01, 0x70, 0x40, 0xa8, 0x00, 0xa2, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x50, 0x0a, 0xf5, + 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x53, 0x8e, 0xe2, 0x00, 0x71, 0x40, 0x68, 0xf4, 0xa1, 0x00, 0x0a, + 0x05, 0x94, 0xcb, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x60, 0x01, 0x4a, 0xc9, 0x06, 0x94, 0xcb, 0x35, + 0x0c, 0xa2, 0x00, 0x1c, 0x80, 0x01, 0x4a, 0x49, 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, 0x73, 0x24, + 0x00, 0x94, 0xf5, 0xb5, 0x0c, 0xa2, 0x00, 0x1c, 0x01, 0x94, 0xed, 0x35, 0x0c, 0xa2, 0x00, 0x1c, + 0x02, 0x94, 0xeb, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x03, 0x94, 0xef, 0x35, 0x0c, 0xa2, 0x00, 0x1c, + 0x05, 0x94, 0xc1, 0x39, 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x64, 0x65, 0x00, 0x20, 0x25, 0xf9, + 0x20, 0x30, 0x7e, 0x45, 0xfa, 0x80, 0x47, 0xdb, 0x27, 0x56, 0xc0, 0x35, 0xe4, 0x63, 0x17, 0xe9, + 0x3d, 0xcd, 0xe1, 0x60, 0x0d, 0x76, 0x37, 0x6f, 0xfd, 0x8a, 0x44, 0x9e, 0xe0, 0x97, 0xa4, 0x33, + 0x04, 0xad, 0xc3, 0xcb, 0xa7, 0xc0, 0x25, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, + 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, 0x00, 0x50, 0xab, 0xfb, 0x00, 0x00, 0xd4, 0xf3, 0x00, + 0x65, 0xad, 0x68, 0x00, 0x75, 0xaf, 0x68, 0x80, 0x6b, 0xa9, 0xe8, 0xa0, 0x00, 0x60, 0xc5, 0x00, + 0x00, 0x21, 0xf9, 0xc0, 0x00, 0x62, 0x45, 0x88, 0x9b, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf6, + 0x00, 0x46, 0x23, 0x14, 0xa2, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf4, 0x00, 0x46, 0xa3, 0x14, + 0xa2, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x7e, 0xa3, 0xd0, + 0xa3, 0x00, 0x02, 0x05, 0x94, 0xc1, 0x39, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x12, + 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x00, 0x30, 0x40, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, + 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, + 0x00, 0x6e, 0x23, 0x94, 0x81, 0x00, 0x98, 0x20, 0x00, 0x42, 0x23, 0x94, 0x81, 0x00, 0x98, 0xf2, + 0x00, 0x40, 0xa3, 0x50, 0xa2, 0x00, 0x98, 0x00, 0x00, 0xe6, 0x73, 0x07, 0x00, 0x40, 0xa3, 0xff, + 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, + 0x00, 0x42, 0x23, 0x80, 0x30, 0xe7, 0x62, 0x40, 0x00, 0x66, 0x49, 0x09, 0x00, 0x60, 0xa3, 0x0c, + 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0xfa, + 0xa2, 0x6a, 0x72, 0x0e, 0x01, 0xe7, 0x76, 0x21, 0x13, 0xd9, 0x69, 0xc0, 0x5d, 0x22, 0x3c, 0x19, + 0x25, 0xc9, 0x5d, 0x28, 0x86, 0x4a, 0x64, 0xf9, 0xa1, 0x3c, 0xa1, 0x5b, 0x7b, 0x29, 0xe0, 0xd6, + 0x98, 0x26, 0x50, 0xa2, 0x00, 0x98, 0x40, 0x00, 0x66, 0x45, 0x20, 0x00, 0x60, 0x45, 0x60, 0x00, + 0x60, 0xc9, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, + 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x20, 0x00, 0x42, 0x45, 0x00, 0x12, 0xe0, 0xb5, 0x58, 0xa2, + 0x00, 0x9c, 0x40, 0x00, 0x66, 0x45, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, + 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x60, 0x00, 0x60, 0xc5, 0x00, 0x00, + 0x42, 0xa3, 0x00, 0x10, 0xe6, 0x35, 0x58, 0xa2, 0x00, 0x9c, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, + 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, + 0x42, 0x23, 0x80, 0x30, 0xe7, 0x62, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, + 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x00, 0x00, 0x66, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, + 0x78, 0xa3, 0x50, 0xa2, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0xe4, 0xa3, + 0x00, 0x82, 0x04, 0xa4, 0x00, 0x82, 0x24, 0xa4, 0x00, 0x02, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, + 0xc0, 0x63, 0x94, 0x81, 0x00, 0x98, 0x1c, 0x00, 0x7c, 0xa3, 0x00, 0x10, 0x23, 0xf9, 0x00, 0x00, + 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, 0xfd, 0x80, 0x08, 0x21, 0x7d, 0x00, 0x10, + 0x23, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x5c, 0xa3, 0x00, 0x0a, 0xfa, 0x87, 0x2e, 0x85, 0x45, 0x29, + 0xe2, 0xca, 0xea, 0xda, 0x43, 0x4d, 0x7c, 0x08, 0xf2, 0xa2, 0xd2, 0x6e, 0x68, 0x15, 0x93, 0x69, + 0x6b, 0x39, 0x75, 0xd2, 0xc8, 0xe0, 0x85, 0x3d, 0xe8, 0x70, 0x6b, 0x70, 0x27, 0x00, 0x00, 0xc0, + 0x69, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, 0xfd, 0x00, 0x00, 0x21, 0xf3, 0x01, 0xe0, 0x7d, + 0x24, 0x78, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, 0x00, 0x00, 0x00, 0x84, 0x54, 0x00, 0x46, + 0xa3, 0x00, 0x30, 0x06, 0xf3, 0x53, 0x30, 0x86, 0xa4, 0x00, 0x30, 0x06, 0xf3, 0x01, 0x30, 0x86, + 0x24, 0x00, 0x30, 0x06, 0xf3, 0x80, 0x30, 0x86, 0x24, 0x00, 0x30, 0x06, 0xf5, 0x00, 0x00, 0x00, + 0x84, 0x90, 0xa3, 0x00, 0x82, 0x01, 0x06, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xed, 0x00, 0x00, 0xc0, + 0x2d, 0x00, 0x00, 0xc0, 0xeb, 0x00, 0x10, 0x80, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x08, 0x4c, + 0xa3, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x60, 0x7e, 0x69, 0xd4, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0x00, + 0x84, 0x00, 0x02, 0x4c, 0xa3, 0x10, 0x00, 0x44, 0x23, 0x00, 0x20, 0x04, 0xf3, 0x00, 0x61, 0x86, + 0xe4, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0xf0, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0x00, + 0x84, 0x80, 0x00, 0x4c, 0xa3, 0x50, 0x00, 0x44, 0xa3, 0x00, 0x20, 0x04, 0xf3, 0x00, 0x61, 0x86, + 0xe4, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0x10, 0xa4, 0x00, 0x0a, 0x00, 0x00, 0x00, + 0x84, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x44, 0xa3, 0x00, 0x00, 0x46, + 0x23, 0x00, 0x00, 0x48, 0xa3, 0x00, 0x00, 0x4a, 0x23, 0x00, 0x00, 0x4c, 0x23, 0x00, 0x00, 0x4e, + 0xa3, 0x00, 0x00, 0x50, 0xa3, 0x82, 0x13, 0xfc, 0x70, 0xa6, 0x40, 0x04, 0xf3, 0xdb, 0xc6, 0xa2, + 0x25, 0x6e, 0x69, 0x92, 0xbd, 0xaf, 0x70, 0x27, 0x52, 0x8d, 0xf8, 0x67, 0x44, 0xa7, 0x79, 0xe3, + 0x0f, 0x69, 0x21, 0x84, 0xe9, 0xaa, 0x48, 0x28, 0x00, 0x00, 0x52, 0x23, 0x00, 0x00, 0x54, 0x23, + 0x00, 0x00, 0x56, 0xa3, 0x00, 0x00, 0x58, 0x23, 0x00, 0x00, 0x5a, 0xa3, 0x00, 0x00, 0x5c, 0xa3, + 0x00, 0x00, 0x5e, 0x23, 0x00, 0x00, 0x60, 0xa3, 0x00, 0x00, 0x62, 0x23, 0x00, 0x00, 0x64, 0x23, + 0x00, 0x00, 0x66, 0xa3, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, + 0x00, 0x00, 0x6e, 0x23, 0x00, 0x00, 0x70, 0x23, 0x00, 0x00, 0x72, 0xa3, 0x00, 0x00, 0x74, 0xa3, + 0x00, 0x00, 0x76, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x7c, 0x23, + 0x00, 0x00, 0x7e, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x72, 0x87, 0x8e, 0x25, 0x10, 0x7a, 0xa9, 0x7c, + 0x70, 0x46, 0xa8, 0xcf, 0x82, 0xe7, 0x6a, 0xa2, 0x16, 0xd6, 0x2e, 0xdb, 0x61, 0x19, 0xe2, 0x80, + 0x93, 0x47, 0xe0, 0x4c, 0xf6, 0x7a, 0xfa, 0x4a, 0x54, 0xb0, 0x03, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x58, 0xba, 0xf8, 0xc6, + 0x24, 0x5e, 0x6c, 0x6d, 0x89, 0xc6, 0xe4, 0xf4, 0x69, 0xf0, 0xcc, 0x9a, 0xcc, 0x9f, 0xe3, 0x8a, + 0x4e, 0x35, 0xf6, 0x8c, 0xe1, 0xe2, 0x90, 0x77, 0x82, 0x21, 0x26, 0xdb, 0xd8, 0x02, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x01, 0xa8, 0x24, 0x00, 0x00, 0xd4, 0x7d, 0x50, 0x04, 0x3e, 0x76, 0xee, 0xe1, 0x59, 0xcb, 0x26, + 0x98, 0xc7, 0x25, 0x91, 0xb2, 0x59, 0xdd, 0x1c, 0xf0, 0x9e, 0xef, 0xd3, 0x1c, 0x5d, 0xb6, 0x34, + 0xbb, 0x20, 0xd4, 0x52, 0x09, 0xd2, 0x56, 0xbf, 0xa0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff}; \ No newline at end of file diff --git a/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_2_0_0/fw_CPU.h b/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_2_0_0/fw_CPU.h index ba3d955fa..c402b7782 100644 --- a/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_2_0_0/fw_CPU.h +++ b/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_2_0_0/fw_CPU.h @@ -5,1433 +5,1701 @@ /** * @brief CPU firmware version fw_v2.0.0.hex32_signed_chunks.bin for bootloader v2.0.1 */ -const uint8_t fw_CPU[] - = {0x68, 0xb3, 0xff, 0x2a, 0x22, 0x04, 0xa0, 0x0e, 0x0a, 0xae, 0x96, 0x07, 0x9f, 0x7a, 0x52, 0x12, 0x2c, 0x19, 0x82, - 0x79, 0xf5, 0xbf, 0x06, 0xb4, 0x64, 0xac, 0xf9, 0xce, 0x9d, 0x9f, 0x5d, 0x6a, 0x9c, 0xa4, 0x92, 0xe6, 0x8e, 0x3b, - 0xd1, 0x62, 0xfd, 0x49, 0xf0, 0x35, 0xda, 0x24, 0xd2, 0xde, 0x89, 0x4e, 0xf0, 0x56, 0x8a, 0x10, 0xd2, 0x1e, 0x13, - 0x97, 0xaa, 0x22, 0x5f, 0x6a, 0xb7, 0x52, 0x00, 0xc1, 0xd1, 0x9e, 0x14, 0xd4, 0x87, 0x65, 0x66, 0x02, 0x81, 0x25, - 0x9e, 0xa3, 0x93, 0x51, 0x12, 0x6e, 0xcb, 0x9d, 0xd0, 0xc9, 0x36, 0xe1, 0x30, 0xad, 0x89, 0xe9, 0x6e, 0xed, 0xab, - 0x66, 0x69, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x62, 0xb6, 0xe3, 0x26, 0xc6, 0x32, 0x4d, 0xe1, 0x92, - 0x74, 0xe5, 0x66, 0x7b, 0xf2, 0xdd, 0x73, 0xde, 0xb0, 0xf2, 0x86, 0xc3, 0x6c, 0x58, 0xc4, 0x9a, 0x0e, 0xd3, 0x9f, - 0x6b, 0x50, 0xf5, 0x3b, 0xcb, 0x00, 0x00, 0xc0, 0xb8, 0xfe, 0xb5, 0xef, 0xbc, 0x1c, 0xe1, 0xe1, 0x97, 0xd4, 0x28, - 0xe4, 0x24, 0xc9, 0xe1, 0xb3, 0x4f, 0x66, 0x18, 0x31, 0x8d, 0x09, 0xcd, 0x94, 0xe5, 0xaa, 0x5b, 0x29, 0x16, 0x2a, - 0x59, 0x04, 0x73, 0x93, 0x0e, 0x7a, 0x01, 0x6b, 0xad, 0xd2, 0xbe, 0x0e, 0xdd, 0x69, 0x01, 0x37, 0x81, 0x42, 0x8a, - 0xda, 0x5c, 0xad, 0xd4, 0x19, 0x94, 0x2f, 0x1e, 0x19, 0xc2, 0x93, 0xfe, 0xbf, 0x0d, 0xfa, 0xa4, 0xd5, 0x47, 0xc2, - 0xb4, 0xa2, 0xe2, 0xb2, 0x56, 0x38, 0xed, 0x8b, 0x01, 0xdf, 0xb8, 0x1d, 0x80, 0xfe, 0xe8, 0xc9, 0x5d, 0xfb, 0x4c, - 0x8b, 0x67, 0x4d, 0x22, 0x17, 0x2c, 0x81, 0xd3, 0xb2, 0x00, 0x04, 0x6f, 0x30, 0x40, 0x44, 0x6f, 0x30, 0x60, 0x3e, - 0x6f, 0x30, 0x20, 0x3e, 0x6f, 0x30, 0xe0, 0x3d, 0x6f, 0x30, 0xa0, 0x3d, 0x6f, 0x30, 0x60, 0x3d, 0x6f, 0x30, 0x20, - 0x3d, 0x6f, 0x50, 0x40, 0x18, 0x6f, 0x30, 0xa0, 0x3c, 0x6f, 0x30, 0x60, 0x3c, 0x6f, 0x30, 0x20, 0x3c, 0x6f, 0x30, - 0xb0, 0x00, 0x6f, 0x30, 0xa0, 0x3b, 0x6f, 0x30, 0x60, 0x3b, 0x6f, 0x30, 0x20, 0x3b, 0x6f, 0x30, 0xe0, 0x3a, 0x6f, - 0x40, 0x30, 0x7c, 0x6f, 0x30, 0x60, 0x27, 0x6f, 0x30, 0x90, 0x2d, 0x6f, 0x40, 0x90, 0x37, 0x6f, 0x40, 0x50, 0x37, - 0x6f, 0x40, 0x10, 0x37, 0x6f, 0x30, 0xe0, 0x4d, 0x6f, 0x30, 0xe0, 0x4e, 0x6f, 0x30, 0x70, 0x53, 0x6f, 0x40, 0xd0, - 0x5e, 0x6f, 0x30, 0x60, 0x4f, 0x6f, 0x20, 0xf0, 0x21, 0x6f, 0x40, 0xd0, 0x1f, 0x6f, 0x30, 0xe0, 0x4f, 0x6f, 0x30, - 0x40, 0x5c, 0x6f, 0x30, 0x40, 0x40, 0x93, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x93, 0x01, 0x00, 0x00, 0x13, - 0x02, 0x00, 0x00, 0x93, 0x02, 0x00, 0x00, 0x13, 0x03, 0x00, 0x00, 0x93, 0x03, 0x00, 0x00, 0x13, 0x04, 0x00, 0x00, - 0x93, 0x04, 0x00, 0x00, 0x13, 0x05, 0x00, 0x00, 0x93, 0x05, 0x00, 0x00, 0x13, 0x06, 0x00, 0x00, 0x93, 0x06, 0x00, - 0x00, 0x13, 0x07, 0x00, 0x00, 0x93, 0x07, 0x00, 0x00, 0x13, 0x08, 0x00, 0x00, 0x93, 0x08, 0x00, 0x00, 0x13, 0x09, - 0x00, 0x00, 0x93, 0x09, 0x00, 0x00, 0x13, 0x0a, 0x00, 0x00, 0x93, 0x0a, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0xfa, - 0x77, 0xbf, 0xf1, 0x81, 0xf8, 0x46, 0x9e, 0x62, 0x93, 0x30, 0xef, 0x9c, 0x0e, 0x33, 0x36, 0x23, 0x00, 0x0d, 0x3a, - 0x61, 0xa5, 0x51, 0x8a, 0xcf, 0x63, 0xc4, 0x09, 0xeb, 0xb2, 0x8e, 0xeb, 0xc4, 0xd8, 0x04, 0x93, 0x0b, 0x00, 0x00, - 0x13, 0x0c, 0x00, 0x00, 0x93, 0x0c, 0x00, 0x00, 0x13, 0x0d, 0x00, 0x00, 0x93, 0x0d, 0x00, 0x00, 0x13, 0x0e, 0x00, - 0x00, 0x93, 0x0e, 0x00, 0x00, 0x13, 0x0f, 0x00, 0x00, 0x93, 0x0f, 0x00, 0x00, 0x97, 0x00, 0x00, 0x00, 0x93, 0x80, - 0x40, 0xf0, 0x73, 0x90, 0x50, 0x30, 0x93, 0x00, 0x00, 0x00, 0x17, 0x41, 0x10, 0x00, 0x13, 0x01, 0x41, 0xcf, 0x33, - 0x04, 0x01, 0x00, 0x17, 0x0d, 0x10, 0x00, 0x13, 0x0d, 0x8d, 0xee, 0x97, 0x4d, 0x10, 0x00, 0x93, 0x8d, 0x0d, 0xce, - 0x63, 0x57, 0xbd, 0x01, 0x23, 0x20, 0x0d, 0x00, 0x11, 0x0d, 0xe3, 0x4d, 0xbd, 0xff, 0xef, 0x00, 0x70, 0x71, 0x73, - 0x00, 0x50, 0x10, 0xf5, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, - 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa2, 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa0, 0x07, 0xf4, 0xb7, - 0x37, 0x20, 0x00, 0x23, 0x8e, 0x07, 0xf2, 0x82, 0x80, 0x05, 0x67, 0x93, 0x07, 0x45, 0x00, 0x01, 0x17, 0x01, 0x45, - 0x94, 0x43, 0x99, 0xe6, 0x13, 0x05, 0x05, 0x02, 0x91, 0x07, 0xe3, 0x1b, 0xe5, 0xfe, 0x82, 0x80, 0x81, 0x47, 0x13, - 0x06, 0x00, 0x02, 0x33, 0xd7, 0xf6, 0x00, 0x05, 0x8b, 0x09, 0xe7, 0x85, 0x07, 0x05, 0x05, 0xe3, 0x9a, 0xc7, 0xfe, - 0x82, 0x80, 0x18, 0x41, 0xfd, 0x57, 0x63, 0x02, 0xf7, 0x06, 0x13, 0x07, 0x45, 0x00, 0x81, 0x47, 0x13, 0x06, 0xf0, - 0x07, 0x14, 0x43, 0xfa, 0x0f, 0x39, 0x44, 0x97, 0x31, 0x75, 0x53, 0x6c, 0x83, 0xaf, 0x8d, 0x72, 0x89, 0x9b, 0xa0, - 0x0b, 0x1d, 0x66, 0x59, 0x1d, 0x43, 0xb7, 0x7f, 0xca, 0x69, 0x84, 0xc2, 0xd9, 0xeb, 0xd6, 0x9e, 0x73, 0xb0, 0x05, - 0x81, 0xea, 0x85, 0x07, 0x11, 0x07, 0xe3, 0x9c, 0xc7, 0xfe, 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x01, 0x47, 0x93, - 0x05, 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, 0x05, 0x8a, 0x19, 0xca, 0x93, 0x05, 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, - 0x05, 0x8a, 0x15, 0xc6, 0x05, 0x07, 0xe3, 0x1b, 0xb7, 0xfe, 0x21, 0xa0, 0x05, 0x07, 0xe3, 0x11, 0xb7, 0xfe, 0x89, - 0x07, 0x93, 0x06, 0x00, 0x08, 0x7d, 0x56, 0xe3, 0x85, 0xd7, 0xfc, 0x85, 0x07, 0x13, 0x97, 0x27, 0x00, 0x2a, 0x97, - 0x03, 0x27, 0xc7, 0xff, 0xe3, 0x08, 0xc7, 0xfe, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, - 0x14, 0x20, 0x00, 0x13, 0x04, 0x04, 0x00, 0x83, 0x46, 0x94, 0x07, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, - 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x77, 0x13, 0x06, 0xc6, 0x52, 0x93, 0x85, 0x85, 0x53, 0x06, 0xc6, 0xef, - 0x10, 0xd0, 0x51, 0x03, 0x45, 0x94, 0x07, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, - 0xef, 0x40, 0xd0, 0x21, 0xef, 0x20, 0xa0, 0x5d, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x00, 0xb2, 0x40, 0x41, - 0x01, 0x6f, 0x40, 0x90, 0x22, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x05, 0x05, 0x10, - 0x2a, 0x84, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x05, 0x54, 0x06, 0xc6, 0xef, 0x10, 0xd0, 0x54, 0x37, 0x37, 0x20, - 0x00, 0x13, 0x07, 0x07, 0xf6, 0x14, 0x43, 0xfa, 0x88, 0xa4, 0x89, 0xae, 0x37, 0x34, 0x85, 0x45, 0x28, 0xde, 0xe6, - 0x9a, 0x1c, 0x0c, 0x6f, 0xbe, 0x56, 0x04, 0x28, 0xa3, 0xc8, 0xe3, 0x70, 0xe5, 0x69, 0x61, 0xa7, 0x3c, 0xef, 0xb7, - 0x8e, 0xfb, 0x88, 0x06, 0x85, 0x47, 0xb3, 0x97, 0x87, 0x00, 0xb2, 0x40, 0x22, 0x44, 0x93, 0xc7, 0xf7, 0xff, 0xf5, - 0x8f, 0x1c, 0xc3, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x2a, 0x84, 0x93, 0x04, - 0xa0, 0x0a, 0xef, 0x20, 0x30, 0x77, 0x63, 0x19, 0x95, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, - 0x44, 0x41, 0x01, 0x82, 0x80, 0x22, 0x85, 0xef, 0x20, 0xb0, 0x79, 0x22, 0x85, 0xef, 0x20, 0x50, 0x75, 0xe3, 0x03, - 0x95, 0xfe, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x05, 0x54, 0x85, 0x45, 0xef, 0x10, 0xb0, 0x4e, 0x13, 0x05, 0x50, - 0x05, 0xd1, 0xbf, 0x01, 0x11, 0x22, 0xcc, 0x2a, 0x84, 0x37, 0x35, 0x00, 0x08, 0x06, 0xce, 0x2e, 0xc6, 0xef, 0x30, - 0x50, 0x14, 0x32, 0x46, 0xa2, 0x85, 0x37, 0x35, 0x00, 0x08, 0xef, 0x30, 0x70, 0x1b, 0x62, 0x44, 0xf2, 0x40, 0x37, - 0x35, 0x00, 0x08, 0x05, 0x61, 0x6f, 0x30, 0xf0, 0x16, 0x6d, 0x71, 0x23, 0x24, 0x81, 0x10, 0x2a, 0x84, 0x0a, 0x85, - 0x23, 0x26, 0x11, 0x10, 0xef, 0x10, 0xf0, 0x68, 0x0a, 0x85, 0x23, 0x00, 0x81, 0x00, 0xef, 0x20, 0xa0, 0x47, 0x83, - 0x20, 0xc1, 0x10, 0x03, 0x24, 0x81, 0x10, 0x51, 0x61, 0x82, 0x80, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0x2e, 0xc4, - 0xef, 0x20, 0xd0, 0x1b, 0xa2, 0x45, 0x32, 0x45, 0xef, 0x20, 0xf0, 0x33, 0x2a, 0xc4, 0xef, 0x20, 0x90, 0x1c, 0xf2, - 0x40, 0x22, 0x45, 0x05, 0x61, 0x82, 0x80, 0x13, 0x01, 0x01, 0xde, 0xfa, 0x0f, 0xed, 0xbe, 0x02, 0x0e, 0xe0, 0xf4, - 0x66, 0x4a, 0x48, 0xba, 0xa0, 0x5b, 0xcc, 0x40, 0xb4, 0xd6, 0x52, 0xc1, 0xb1, 0xd8, 0x5b, 0x48, 0xe1, 0x0f, 0x86, - 0x56, 0x2a, 0xdc, 0x98, 0x09, 0x22, 0x60, 0x07, 0x23, 0x2c, 0x81, 0x20, 0x2e, 0x84, 0xaa, 0x05, 0x23, 0x28, 0x21, - 0x21, 0x93, 0x85, 0x05, 0x20, 0x2a, 0x89, 0x08, 0x08, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x2a, 0x91, 0x20, 0x7d, 0x3f, - 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x04, 0xaa, 0x84, 0x08, 0x08, 0x09, 0x3d, 0x63, 0x00, 0x95, 0x02, 0x22, - 0x85, 0xd1, 0x3d, 0x09, 0x45, 0x83, 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, 0x41, 0x21, 0x03, 0x29, - 0x01, 0x21, 0x13, 0x01, 0x01, 0x22, 0x82, 0x80, 0x42, 0x44, 0x08, 0x08, 0x22, 0xc6, 0x65, 0x3b, 0x09, 0x8c, 0x11, - 0x46, 0x6c, 0x00, 0x4a, 0x85, 0x22, 0xc6, 0xef, 0x50, 0x00, 0x12, 0x05, 0x45, 0xc9, 0xbf, 0x01, 0x45, 0xf9, 0xb7, - 0x41, 0x11, 0x4a, 0xc0, 0x03, 0xa9, 0x05, 0x00, 0x06, 0xc6, 0x22, 0xc4, 0x26, 0xc2, 0x2e, 0x84, 0xaa, 0x84, 0xef, - 0x20, 0x30, 0x68, 0xca, 0x85, 0x26, 0x85, 0xef, 0x20, 0x70, 0x1f, 0xa6, 0x85, 0x22, 0x85, 0xef, 0x20, 0xd0, 0x29, - 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x02, 0x1c, 0x40, 0x63, 0x93, 0x27, 0x03, 0x93, 0x07, 0x44, 0x00, 0x7d, - 0x57, 0x13, 0x04, 0x04, 0x20, 0x94, 0x43, 0x63, 0x9b, 0xe6, 0x00, 0x91, 0x07, 0xe3, 0x9c, 0x87, 0xfe, 0xb2, 0x40, - 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0xc5, 0xbf, 0x13, 0x01, 0x01, - 0xde, 0x23, 0x26, 0x31, 0x21, 0x93, 0x19, 0xa5, 0x00, 0x23, 0x2a, 0x91, 0x20, 0x93, 0x84, 0xfa, 0x07, 0x1c, 0x50, - 0x24, 0x69, 0xae, 0xbc, 0x72, 0xfc, 0x73, 0xd6, 0x37, 0x39, 0xe2, 0x73, 0x4b, 0xfd, 0x9b, 0xde, 0x63, 0x21, 0xa4, - 0x34, 0x5a, 0x01, 0x25, 0xb2, 0x0f, 0xa7, 0x9e, 0xa7, 0x0b, 0x38, 0x08, 0x09, 0x20, 0x23, 0x2c, 0x81, 0x20, 0xa6, - 0x85, 0x2a, 0x84, 0x0a, 0x85, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x28, 0x21, 0x21, 0xfd, 0x35, 0x93, 0x07, 0xa0, 0x0a, - 0x63, 0x00, 0xf5, 0x02, 0x01, 0x45, 0x83, 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, 0x41, 0x21, 0x03, - 0x29, 0x01, 0x21, 0x83, 0x29, 0xc1, 0x20, 0x13, 0x01, 0x01, 0x22, 0x82, 0x80, 0x2a, 0x89, 0x0a, 0x85, 0x1d, 0x33, - 0x63, 0x06, 0x25, 0x01, 0x22, 0x85, 0xe5, 0x33, 0x09, 0x45, 0xd9, 0xbf, 0x02, 0x44, 0x0a, 0x85, 0xcd, 0x31, 0xaa, - 0x87, 0xb3, 0x06, 0xa4, 0x40, 0x0d, 0x45, 0xe3, 0x03, 0xf4, 0xfc, 0x09, 0x45, 0xe3, 0x60, 0xd4, 0xfc, 0x50, 0x00, - 0x01, 0x44, 0x13, 0x08, 0x00, 0x02, 0x13, 0x05, 0xf0, 0x07, 0x0c, 0x42, 0xb1, 0xc5, 0x01, 0x47, 0xb3, 0xd7, 0xe5, - 0x00, 0x85, 0x8b, 0x95, 0xcf, 0x85, 0x47, 0xb3, 0x97, 0xe7, 0x00, 0x93, 0xc7, 0xf7, 0xff, 0xed, 0x8f, 0x1c, 0xc2, - 0xef, 0x20, 0xb0, 0x03, 0x18, 0x04, 0x93, 0x17, 0x24, 0x00, 0xba, 0x97, 0x83, 0xa5, 0x47, 0xe0, 0x13, 0x05, 0x14, - 0x00, 0x0a, 0x05, 0x26, 0x95, 0xef, 0x20, 0x30, 0x14, 0x2a, 0x84, 0xef, 0x20, 0x70, 0x03, 0x13, 0x05, 0x64, 0xf5, - 0x13, 0x35, 0x15, 0x00, 0xad, 0xb7, 0x05, 0x07, 0xe3, 0x1e, 0x07, 0xfb, 0x05, 0x04, 0x11, 0x06, 0xe3, 0x17, 0xa4, - 0xfa, 0xfd, 0x16, 0x8a, 0x85, 0x13, 0x85, 0x09, 0x40, 0x36, 0xc0, 0xc9, 0x35, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x14, - 0xfa, 0xd0, 0xe7, 0x63, 0x7c, 0x8e, 0xc7, 0xcf, 0x0c, 0xd3, 0x23, 0x96, 0x82, 0xd4, 0xeb, 0x54, 0xfa, 0xbb, 0xff, - 0xb6, 0xc7, 0x5b, 0x2e, 0x96, 0x3c, 0xef, 0xbf, 0x2e, 0x94, 0x4d, 0xde, 0x4d, 0x61, 0x10, 0x09, 0xf5, 0xf4, 0x8a, - 0x85, 0x26, 0x85, 0x55, 0x3d, 0x13, 0x05, 0x65, 0xf5, 0xf9, 0xb7, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x07, - 0x30, 0x0c, 0x2a, 0x84, 0x63, 0x04, 0xf5, 0x00, 0xef, 0x20, 0x60, 0x4e, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, - 0x00, 0x05, 0x67, 0x23, 0x80, 0x87, 0x00, 0xba, 0x97, 0xf8, 0x5b, 0x19, 0xe3, 0x05, 0x47, 0xf8, 0xdb, 0xb2, 0x40, - 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x66, 0x37, 0x05, 0x20, 0x00, 0x41, 0x11, 0x13, 0x06, 0xc6, 0x07, 0x81, - 0x45, 0x13, 0x05, 0x05, 0x00, 0x06, 0xc6, 0xef, 0x40, 0x50, 0x7b, 0xef, 0x20, 0x00, 0x44, 0xef, 0x40, 0xc0, 0x4e, - 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x20, 0x80, 0x3a, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x20, 0xa0, 0x57, 0xef, 0x30, 0xa0, - 0x00, 0xef, 0x40, 0x40, 0x1c, 0xef, 0x40, 0x40, 0x7b, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x30, 0x20, 0x17, 0x41, 0x11, - 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x06, 0xc6, 0x23, 0xa4, 0xe7, 0xf4, 0xef, 0x20, 0xe0, 0x3c, 0x65, - 0x37, 0x51, 0x3e, 0xef, 0x30, 0xe0, 0x1b, 0xe1, 0x37, 0xb2, 0x40, 0x1d, 0x65, 0x13, 0x05, 0x05, 0x6c, 0x41, 0x01, - 0x6f, 0x30, 0x60, 0x23, 0x41, 0x11, 0x26, 0xc2, 0xae, 0x84, 0xb6, 0x85, 0x06, 0xc6, 0x22, 0xc4, 0x4a, 0xc0, 0x36, - 0x84, 0x32, 0x89, 0xef, 0x40, 0x00, 0x79, 0x22, 0x86, 0xca, 0x85, 0x13, 0x05, 0x00, 0x02, 0xef, 0x40, 0x60, 0x7b, - 0xef, 0x40, 0x20, 0x76, 0xfa, 0x0a, 0xff, 0x35, 0xd1, 0x09, 0x01, 0xdc, 0xdd, 0x42, 0x4c, 0xa2, 0xed, 0x9e, 0x12, - 0xb3, 0x29, 0x73, 0x5c, 0xd5, 0xa3, 0x4b, 0xa3, 0x1c, 0xf9, 0x45, 0x3b, 0x19, 0xb0, 0x84, 0x20, 0x46, 0x68, 0xe8, - 0x09, 0xef, 0x40, 0x80, 0x7b, 0x93, 0x07, 0xa0, 0x0a, 0x13, 0x04, 0x50, 0x05, 0x63, 0x1a, 0xf5, 0x00, 0x2a, 0x84, - 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0x00, 0x02, 0x26, 0x85, 0xef, 0x40, 0x80, 0x78, 0xb2, 0x40, 0x22, 0x85, 0x22, - 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x85, 0x67, 0xc1, 0x07, 0x63, 0xee, 0xb7, 0x02, 0x41, 0x11, - 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xae, 0x84, 0x37, 0x04, 0x20, 0x00, 0x19, 0xc5, 0x2e, 0x86, 0xaa, 0x85, 0x13, - 0x05, 0x04, 0x00, 0xef, 0x40, 0xf0, 0x6b, 0x13, 0x04, 0x04, 0x00, 0x93, 0x07, 0x30, 0xfc, 0x23, 0x00, 0xf4, 0x00, - 0x85, 0x67, 0x3e, 0x94, 0x64, 0xd8, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x82, 0x80, 0x13, - 0x01, 0x01, 0xdd, 0x23, 0x24, 0x81, 0x22, 0x23, 0x22, 0x91, 0x22, 0x23, 0x20, 0x21, 0x23, 0x23, 0x2e, 0x31, 0x21, - 0x23, 0x2c, 0x41, 0x21, 0x23, 0x2a, 0x51, 0x21, 0x23, 0x28, 0x61, 0x21, 0x23, 0x26, 0x71, 0x21, 0x23, 0x24, 0x81, - 0x21, 0x23, 0x26, 0x11, 0x22, 0x13, 0x04, 0x00, 0x20, 0x01, 0x49, 0x93, 0x04, 0xa0, 0x0a, 0x37, 0x3a, 0x20, 0x00, - 0x85, 0x4a, 0x37, 0x5b, 0x10, 0x00, 0xb7, 0x5b, 0x10, 0x00, 0x37, 0x5c, 0x10, 0x00, 0xc1, 0x49, 0xa2, 0x85, 0x0a, - 0x85, 0x51, 0x39, 0x63, 0x16, 0x95, 0x02, 0x0a, 0x85, 0xfd, 0x34, 0x63, 0x1e, 0x95, 0x04, 0x13, 0x07, 0x0a, 0xf6, - 0x14, 0x43, 0xb3, 0x97, 0x2a, 0x01, 0x13, 0x06, 0xfa, 0x9c, 0x67, 0xfe, 0x49, 0x5b, 0xe4, 0x36, 0xd0, 0x26, 0x62, - 0x9e, 0x4e, 0xdb, 0x34, 0x9f, 0xdc, 0x36, 0x12, 0xe2, 0x22, 0xba, 0x2e, 0xbd, 0xfe, 0xea, 0x30, 0x72, 0x01, 0xd8, - 0x78, 0xd4, 0x38, 0xc0, 0x0a, 0x8b, 0x54, 0xd5, 0x8f, 0x93, 0x85, 0x0b, 0x54, 0xca, 0x86, 0x13, 0x05, 0x8c, 0x77, - 0x1c, 0xc3, 0xef, 0x10, 0x10, 0x08, 0x05, 0x09, 0x13, 0x04, 0x04, 0x40, 0xe3, 0x14, 0x39, 0xfd, 0x83, 0x20, 0xc1, - 0x22, 0x03, 0x24, 0x81, 0x22, 0x83, 0x24, 0x41, 0x22, 0x03, 0x29, 0x01, 0x22, 0x83, 0x29, 0xc1, 0x21, 0x03, 0x2a, - 0x81, 0x21, 0x83, 0x2a, 0x41, 0x21, 0x03, 0x2b, 0x01, 0x21, 0x83, 0x2b, 0xc1, 0x20, 0x03, 0x2c, 0x81, 0x20, 0x13, - 0x01, 0x01, 0x23, 0x82, 0x80, 0x93, 0x05, 0x04, 0x20, 0x0a, 0x85, 0x25, 0x31, 0xe3, 0x10, 0x95, 0xfc, 0x0a, 0x85, - 0x49, 0x34, 0xe3, 0x1c, 0x95, 0xfa, 0x22, 0x85, 0xef, 0x20, 0xd0, 0x33, 0x8a, 0x85, 0x22, 0x85, 0xef, 0x20, 0x30, - 0x1b, 0xa2, 0x85, 0x0a, 0x85, 0x21, 0x31, 0xe3, 0x10, 0x95, 0xfa, 0x0a, 0x85, 0x8d, 0x34, 0xe3, 0x0c, 0x95, 0xf6, - 0x51, 0xbf, 0xb7, 0x07, 0x00, 0x80, 0x6d, 0x71, 0x37, 0x55, 0x10, 0x00, 0x23, 0x26, 0x11, 0x10, 0x13, 0x05, 0x45, - 0x55, 0x86, 0x85, 0xbe, 0x95, 0xef, 0x10, 0xf0, 0x06, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x47, 0xf3, 0x93, 0x07, - 0xa0, 0x0a, 0x63, 0x1e, 0xf7, 0x02, 0x37, 0x15, 0x10, 0x00, 0x13, 0x05, 0x85, 0x9f, 0xef, 0x10, 0x70, 0x7b, 0x13, - 0x05, 0xc0, 0x0f, 0xef, 0x10, 0xc0, 0x74, 0x0a, 0x85, 0xef, 0x10, 0xd0, 0x22, 0x93, 0x07, 0xf0, 0x07, 0x93, 0x05, - 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x00, 0x23, 0x00, 0xf1, 0x00, 0xef, 0x10, 0xfa, 0x42, 0x72, 0x52, 0x8e, 0xfd, 0x28, - 0x7d, 0x7d, 0x55, 0xf5, 0xbe, 0xa0, 0xee, 0xbc, 0x2c, 0xfa, 0x20, 0x83, 0x6f, 0x9f, 0xb1, 0xcf, 0x87, 0x58, 0x94, - 0x85, 0x8b, 0x32, 0xc6, 0x19, 0xbf, 0xff, 0x98, 0x0b, 0x20, 0x6e, 0xa3, 0x00, 0xa1, 0x00, 0x0a, 0x85, 0xef, 0x10, - 0x10, 0x7d, 0x05, 0x45, 0xef, 0x40, 0xf0, 0x03, 0xef, 0x40, 0xf0, 0x02, 0xe5, 0x33, 0xef, 0x10, 0xb0, 0x46, 0xf5, - 0xbf, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0x40, 0x80, 0x68, 0x93, 0x07, 0x00, 0x08, 0x63, 0xf3, 0xa7, 0x00, - 0xad, 0x3f, 0x2a, 0x84, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x40, 0x40, 0x27, 0xb7, 0x17, 0x20, 0x00, 0xb2, 0x40, 0x23, - 0xaa, 0x87, 0x06, 0x22, 0x44, 0x13, 0x05, 0x30, 0x0c, 0x41, 0x01, 0x82, 0x80, 0x93, 0x07, 0xf0, 0x17, 0x63, 0xf5, - 0xa7, 0x00, 0x41, 0x11, 0x06, 0xc6, 0xb9, 0x37, 0x6f, 0x10, 0x10, 0x58, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x4a, - 0xc0, 0x2e, 0x84, 0x06, 0xc6, 0xaa, 0x84, 0xc5, 0x37, 0x61, 0x8d, 0x13, 0x09, 0x50, 0x05, 0x19, 0xc1, 0x13, 0x09, - 0xa0, 0x0a, 0x26, 0x85, 0xc1, 0x3f, 0x69, 0x8c, 0x13, 0x05, 0xa0, 0x0a, 0x19, 0xe0, 0x13, 0x05, 0x50, 0x05, 0x63, - 0x03, 0x25, 0x01, 0x21, 0x3f, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x69, 0x71, - 0x08, 0x08, 0x23, 0x22, 0x91, 0x12, 0x23, 0x20, 0x21, 0x13, 0x23, 0x2c, 0x41, 0x11, 0x37, 0x39, 0x20, 0x00, 0x23, - 0x26, 0x11, 0x12, 0x23, 0x24, 0x81, 0x12, 0x23, 0x2e, 0x31, 0x11, 0x23, 0x2a, 0x51, 0x11, 0xef, 0x10, 0x30, 0x15, - 0x91, 0x47, 0x13, 0x07, 0x89, 0xf5, 0x23, 0x08, 0xf1, 0x00, 0x1c, 0x43, 0x37, 0x1a, 0x20, 0x00, 0xfa, 0xd7, 0x18, - 0x94, 0x03, 0x24, 0x8d, 0xf3, 0x32, 0xbe, 0x7c, 0x88, 0xd5, 0x99, 0x57, 0x8a, 0x59, 0x45, 0x08, 0x0a, 0x79, 0xe6, - 0x26, 0xee, 0xd0, 0x90, 0x02, 0x80, 0xde, 0x8d, 0x3b, 0xe0, 0x22, 0x70, 0x0c, 0xb7, 0x34, 0x20, 0x00, 0x13, 0x09, - 0x89, 0xf5, 0x13, 0x0a, 0x0a, 0x00, 0x93, 0x84, 0x44, 0xf5, 0xc5, 0xeb, 0x83, 0x27, 0x4a, 0x07, 0x23, 0xa0, 0x04, - 0x00, 0x1c, 0xc3, 0x3d, 0x47, 0x63, 0x63, 0xf7, 0x00, 0x45, 0x3d, 0xc1, 0x17, 0x09, 0x46, 0x6c, 0x00, 0x13, 0x05, - 0x21, 0x01, 0x3e, 0xc6, 0xef, 0x40, 0xf0, 0x43, 0x89, 0x47, 0xa3, 0x08, 0xf1, 0x00, 0x13, 0x04, 0xe0, 0x07, 0x93, - 0x09, 0x41, 0x01, 0x03, 0x27, 0x09, 0x00, 0x94, 0x40, 0xb3, 0x07, 0xd7, 0x40, 0x63, 0xf3, 0x87, 0x00, 0x3e, 0x84, - 0x37, 0x56, 0x10, 0x00, 0xb7, 0x5a, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0xa2, 0x87, 0x93, 0x85, 0xca, 0x56, 0x13, - 0x06, 0xc6, 0x55, 0x13, 0x05, 0x45, 0x57, 0xef, 0x10, 0x40, 0x67, 0x8c, 0x40, 0x83, 0x27, 0x4a, 0x07, 0x33, 0x07, - 0xb4, 0x00, 0x63, 0xf8, 0xe7, 0x04, 0x8d, 0x45, 0x13, 0x85, 0xca, 0x56, 0xef, 0x10, 0x20, 0x6d, 0x13, 0x04, 0x50, - 0x05, 0xef, 0xf0, 0x5f, 0x84, 0xef, 0x40, 0xe0, 0x14, 0xef, 0x20, 0x60, 0x0a, 0xef, 0x20, 0x60, 0x01, 0xbd, 0x31, - 0x83, 0x20, 0xc1, 0x12, 0x22, 0x85, 0x03, 0x24, 0x81, 0x12, 0x83, 0x24, 0x41, 0x12, 0x03, 0x29, 0x01, 0x12, 0x83, - 0x29, 0xc1, 0x11, 0x03, 0x2a, 0x81, 0x11, 0x83, 0x2a, 0x41, 0x11, 0x55, 0x61, 0x82, 0x80, 0x13, 0x04, 0x00, 0x08, - 0x93, 0x09, 0x21, 0x01, 0xad, 0xbf, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x22, 0x86, 0xbe, 0x95, 0x4e, - 0x85, 0xfa, 0x9e, 0xab, 0x8e, 0xc5, 0xb3, 0x79, 0x08, 0x07, 0xd8, 0x27, 0x87, 0x84, 0xab, 0x38, 0x3a, 0xd4, 0x2a, - 0x51, 0x54, 0x3d, 0x70, 0x65, 0x82, 0xa9, 0xa5, 0x42, 0x26, 0x1d, 0x2b, 0x70, 0x97, 0x72, 0x48, 0x0d, 0xef, 0x40, - 0x70, 0x39, 0x83, 0x47, 0x11, 0x01, 0x98, 0x40, 0x22, 0x97, 0x3e, 0x94, 0x83, 0x27, 0x09, 0x00, 0xa3, 0x08, 0x81, - 0x00, 0x98, 0xc0, 0x13, 0x04, 0x50, 0x05, 0x63, 0x17, 0xf7, 0x00, 0x89, 0x47, 0x23, 0x08, 0xf1, 0x00, 0x13, 0x04, - 0xa0, 0x0a, 0x08, 0x08, 0xef, 0x10, 0x10, 0x63, 0x59, 0xbf, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, - 0xc8, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xf3, 0xa7, 0x00, 0x5d, 0x3b, 0x0a, 0x05, 0x05, 0x64, 0xb3, 0x04, 0x85, 0x00, - 0x41, 0x04, 0x13, 0x09, 0xc1, 0x00, 0x2a, 0x94, 0x26, 0x85, 0xef, 0x30, 0xc0, 0x0b, 0x23, 0x00, 0xa9, 0x00, 0x91, - 0x04, 0x05, 0x09, 0xe3, 0x99, 0x84, 0xfe, 0xf2, 0x40, 0x62, 0x44, 0x32, 0x45, 0xd2, 0x44, 0x42, 0x49, 0x05, 0x61, - 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x8d, 0x47, 0x63, 0xf3, 0xa7, 0x00, 0xad, 0x3b, 0x89, 0x67, 0x93, 0x87, 0x07, - 0xbf, 0x0a, 0x05, 0x3e, 0x95, 0xef, 0x30, 0x80, 0x08, 0xaa, 0x87, 0x13, 0x07, 0xf0, 0x0f, 0x55, 0x45, 0x63, 0x89, - 0xe7, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x59, 0x45, 0x63, 0x94, 0xe7, 0x00, 0x13, 0x05, 0x30, 0x0c, 0xb2, 0x40, 0x41, - 0x01, 0x82, 0x80, 0x05, 0x71, 0x23, 0x2c, 0x81, 0x1c, 0x23, 0x2e, 0x11, 0x1c, 0x23, 0x2a, 0x91, 0x1c, 0x23, 0x28, - 0x21, 0x1d, 0x23, 0x26, 0x31, 0x1d, 0x23, 0x24, 0x41, 0x1d, 0x23, 0x22, 0x51, 0x1d, 0x23, 0x20, 0x61, 0x1d, 0x23, - 0x2e, 0x71, 0x1b, 0x23, 0x2c, 0xfa, 0x88, 0x20, 0x3a, 0x4e, 0xbd, 0x8e, 0x18, 0x09, 0x8a, 0x3f, 0xbf, 0xb7, 0x68, - 0x17, 0x1d, 0x0e, 0xb2, 0x78, 0xfd, 0x8e, 0xbd, 0x9d, 0xb1, 0x09, 0x83, 0xa3, 0x53, 0x75, 0x4b, 0xa6, 0x40, 0xd9, - 0x20, 0x0e, 0x81, 0x1b, 0x23, 0x2a, 0x91, 0x1b, 0x23, 0x28, 0xa1, 0x1b, 0x23, 0x26, 0xb1, 0x1b, 0x83, 0x46, 0x05, - 0x00, 0x93, 0x07, 0x20, 0x0a, 0x2a, 0x84, 0x63, 0x82, 0xf6, 0x02, 0x03, 0x47, 0x15, 0x00, 0x37, 0x56, 0x10, 0x00, - 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x86, 0x57, 0x93, 0x85, 0x45, 0x55, 0x13, 0x05, 0x85, - 0x77, 0xef, 0x10, 0x80, 0x4f, 0x08, 0x11, 0xef, 0x10, 0x00, 0x75, 0x83, 0x47, 0x04, 0x00, 0x05, 0x47, 0x23, 0x10, - 0xe1, 0x0a, 0xc1, 0x46, 0x63, 0x8b, 0xd7, 0x46, 0x63, 0xee, 0xf6, 0x02, 0x91, 0x46, 0x63, 0x83, 0xd7, 0x36, 0x63, - 0xe1, 0xf6, 0x02, 0x63, 0x86, 0xe7, 0x06, 0x09, 0x47, 0x63, 0x81, 0xe7, 0x0e, 0x93, 0x07, 0xe0, 0x07, 0x23, 0x00, - 0xf1, 0x0a, 0x08, 0x11, 0xef, 0x10, 0xd0, 0x4d, 0x93, 0x07, 0x50, 0x05, 0xb1, 0xa9, 0x21, 0x47, 0xe3, 0x95, 0xe7, - 0xfe, 0x83, 0x47, 0x14, 0x00, 0xd1, 0xeb, 0xf5, 0x34, 0x15, 0xa9, 0x93, 0x06, 0x20, 0x0a, 0x63, 0x85, 0xd7, 0x4e, - 0x93, 0x06, 0x30, 0x0b, 0x63, 0x81, 0xd7, 0x48, 0x93, 0x06, 0x00, 0x02, 0xe3, 0x94, 0xd7, 0xfc, 0x83, 0x47, 0x14, - 0x00, 0x63, 0x99, 0xe7, 0x06, 0x03, 0x47, 0x24, 0x00, 0x95, 0x47, 0x63, 0x14, 0xf7, 0x06, 0x85, 0x45, 0x61, 0x45, - 0x39, 0x3b, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x08, 0xf5, 0x44, 0x13, 0x04, 0x80, 0xf8, 0x7d, 0xa0, 0x03, 0x47, 0x14, - 0x00, 0x89, 0x47, 0x63, 0x15, 0xf7, 0x04, 0x83, 0x47, 0xfa, 0xba, 0xc1, 0xe9, 0xda, 0xc3, 0xf5, 0x60, 0x02, 0xb0, - 0xe8, 0x51, 0x83, 0xfa, 0xae, 0x70, 0x5c, 0x43, 0x14, 0x6d, 0xd7, 0x0d, 0xfd, 0xd2, 0xec, 0x31, 0xf7, 0x6b, 0x98, - 0x11, 0xa2, 0x51, 0xba, 0xf8, 0x0e, 0x24, 0x00, 0x63, 0x8a, 0xe7, 0x04, 0x63, 0x6b, 0xf7, 0x02, 0xa1, 0xe3, 0x83, - 0x45, 0x34, 0x00, 0xf5, 0x47, 0x63, 0xe9, 0xb7, 0x02, 0x9e, 0x05, 0x13, 0x06, 0x00, 0x08, 0x93, 0x85, 0x05, 0x10, - 0x13, 0x05, 0x21, 0x0a, 0xef, 0x20, 0x90, 0x6f, 0x13, 0x04, 0x00, 0x08, 0x08, 0x11, 0xa3, 0x00, 0x81, 0x0a, 0xef, - 0x10, 0x70, 0x44, 0x93, 0x07, 0xa0, 0x0a, 0xd9, 0xa6, 0x13, 0x05, 0x80, 0x1e, 0x63, 0x8d, 0xd7, 0x00, 0x13, 0x04, - 0x10, 0xf8, 0xa1, 0xa8, 0x89, 0x65, 0x13, 0x06, 0x00, 0x08, 0x93, 0x85, 0x05, 0x90, 0xf1, 0xb7, 0x13, 0x05, 0x00, - 0x1f, 0xef, 0x10, 0x50, 0x22, 0x2a, 0xce, 0x11, 0x46, 0x6c, 0x08, 0x13, 0x05, 0x21, 0x0a, 0xef, 0x40, 0xf0, 0x17, - 0x11, 0x44, 0x7d, 0xbf, 0x83, 0x44, 0x14, 0x00, 0x2d, 0x34, 0x93, 0x07, 0x10, 0x02, 0xe3, 0x95, 0xf4, 0xfc, 0xef, - 0x10, 0xd0, 0x77, 0xef, 0x20, 0xd0, 0x20, 0xef, 0x30, 0x50, 0x40, 0xef, 0x40, 0xc0, 0x15, 0x03, 0x45, 0x24, 0x02, - 0x15, 0x3d, 0x93, 0x07, 0x30, 0x0c, 0x63, 0x0b, 0xf5, 0x02, 0x13, 0x04, 0x70, 0xf8, 0xb3, 0x06, 0x80, 0x40, 0x37, - 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0xf6, 0xf6, 0x0f, 0x13, 0x06, 0x86, 0x59, - 0x93, 0x85, 0x45, 0x55, 0x13, 0x05, 0x85, 0x77, 0x23, 0x00, 0xd1, 0x0a, 0xef, 0x10, 0x40, 0x39, 0xa3, 0x00, 0x01, - 0x0a, 0xf9, 0xb5, 0x83, 0x44, 0x24, 0x02, 0xef, 0xf0, 0x9f, 0x98, 0x8d, 0x47, 0xfa, 0x70, 0x85, 0x1f, 0x65, 0xc9, - 0x16, 0xf8, 0x25, 0xfd, 0x92, 0xdb, 0x67, 0x98, 0x78, 0x77, 0x06, 0x63, 0x1a, 0x9b, 0xd8, 0x7b, 0x63, 0x50, 0x00, - 0xf5, 0x06, 0x24, 0x91, 0xe6, 0xd7, 0xba, 0xf4, 0xd0, 0x0f, 0xe3, 0xe2, 0x97, 0xfc, 0x13, 0x06, 0x10, 0x08, 0x81, - 0x45, 0x68, 0x08, 0xef, 0x40, 0xf0, 0x13, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0x24, 0x00, 0x13, 0x05, 0xd1, 0x01, - 0x23, 0x0e, 0x91, 0x00, 0xef, 0x40, 0xf0, 0x0e, 0xef, 0x40, 0xa0, 0x0e, 0x37, 0x25, 0x00, 0x08, 0xef, 0x30, 0xc0, - 0x03, 0x81, 0x46, 0x01, 0x46, 0x93, 0x05, 0xd1, 0x03, 0x45, 0x45, 0xef, 0xf0, 0x9f, 0x9b, 0x93, 0x07, 0xa0, 0x0a, - 0xe3, 0x11, 0xf5, 0xf8, 0x81, 0x45, 0x68, 0x08, 0xef, 0x30, 0xd0, 0x36, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0xe3, - 0x18, 0xf5, 0xf6, 0x93, 0x06, 0x00, 0x02, 0x13, 0x06, 0xd1, 0x01, 0x93, 0x05, 0xd1, 0x05, 0x49, 0x45, 0xef, 0xf0, - 0xdf, 0x98, 0xaa, 0x84, 0xe3, 0x1c, 0x25, 0xf5, 0x85, 0x45, 0x68, 0x08, 0xef, 0x30, 0x30, 0x34, 0x2a, 0x89, 0xe3, - 0x15, 0x95, 0xf4, 0x83, 0x47, 0xc1, 0x01, 0x85, 0x46, 0x13, 0x06, 0xb1, 0x01, 0x93, 0x05, 0xd1, 0x05, 0x4d, 0x45, - 0xa3, 0x0d, 0xf1, 0x00, 0xef, 0xf0, 0x1f, 0x96, 0xaa, 0x84, 0xe3, 0x16, 0x25, 0xf3, 0x89, 0x45, 0x68, 0x08, 0xef, - 0x30, 0x70, 0x31, 0x2a, 0x89, 0xe3, 0x1f, 0x95, 0xf0, 0x81, 0x46, 0x01, 0x46, 0x93, 0x05, 0xd1, 0x05, 0x51, 0x45, - 0xef, 0xf0, 0xff, 0x93, 0xaa, 0x84, 0xe3, 0x15, 0x25, 0xf1, 0x8d, 0x45, 0x68, 0x08, 0xef, 0x30, 0x50, 0x2f, 0x2a, - 0x89, 0xe3, 0x1e, 0x95, 0xee, 0x91, 0x45, 0x68, 0x08, 0xef, 0x30, 0x70, 0x2e, 0xaa, 0x84, 0xe3, 0x17, 0xfa, 0xe9, - 0xc0, 0xac, 0x54, 0xf7, 0x6d, 0xf2, 0x67, 0x99, 0x4f, 0x1b, 0xe9, 0xf7, 0x9b, 0x73, 0xf8, 0xfe, 0xb9, 0xd9, 0x90, - 0x0a, 0xcc, 0x61, 0xfd, 0x93, 0x3c, 0xa6, 0x8f, 0x9e, 0xc4, 0x19, 0x6a, 0xa8, 0x10, 0x25, 0xef, 0x95, 0x45, 0x68, - 0x08, 0xef, 0x30, 0x90, 0x2d, 0xe3, 0x11, 0x95, 0xee, 0xb7, 0x14, 0x20, 0x00, 0x13, 0x85, 0x04, 0x02, 0xef, 0x30, - 0xb0, 0x31, 0x37, 0x19, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0xd1, 0x03, 0x13, 0x05, 0x09, 0x03, 0xef, - 0x40, 0xd0, 0x00, 0x37, 0x15, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0xd1, 0x07, 0x13, 0x05, 0x05, 0x05, - 0xef, 0x40, 0x80, 0x7f, 0x83, 0x49, 0x24, 0x02, 0x8d, 0x47, 0x63, 0xf3, 0x37, 0x01, 0xb9, 0x34, 0xb7, 0x5c, 0x10, - 0x00, 0xef, 0x10, 0x30, 0x43, 0x01, 0x4d, 0x93, 0x8c, 0x4c, 0x6c, 0x0d, 0x4a, 0xfd, 0x5a, 0x13, 0x0b, 0x00, 0x0f, - 0xc1, 0x6b, 0x37, 0x0c, 0x00, 0x01, 0x13, 0x17, 0x2d, 0x00, 0xb3, 0x87, 0xec, 0x00, 0x83, 0xcd, 0x07, 0x00, 0x3a, - 0xc6, 0x63, 0x81, 0x0d, 0x08, 0x80, 0x43, 0x13, 0x55, 0x44, 0x01, 0x41, 0x80, 0x75, 0x3c, 0x3d, 0x88, 0x32, 0x47, - 0x63, 0x68, 0x8a, 0x00, 0x0e, 0x04, 0x33, 0x94, 0x8a, 0x00, 0x13, 0x44, 0xf4, 0xff, 0x61, 0x8d, 0xb3, 0x86, 0xec, - 0x00, 0x83, 0xc6, 0x16, 0x00, 0x33, 0x55, 0x35, 0x01, 0x93, 0x77, 0x15, 0x00, 0x93, 0xf6, 0x06, 0x0f, 0x63, 0x82, - 0x66, 0x05, 0x93, 0x76, 0x05, 0x10, 0x99, 0xc2, 0x93, 0xe7, 0x27, 0x00, 0xb3, 0x76, 0x75, 0x01, 0x99, 0xc2, 0x93, - 0xe7, 0x47, 0x00, 0x33, 0x75, 0x85, 0x01, 0x19, 0xc1, 0x93, 0xe7, 0x87, 0x00, 0x66, 0x97, 0x18, 0x43, 0xbd, 0x65, - 0xc2, 0x07, 0xfa, 0x3e, 0x3b, 0xc6, 0x93, 0x30, 0x55, 0x8a, 0x47, 0x35, 0x55, 0x80, 0x92, 0x97, 0xee, 0x43, 0x36, - 0xcf, 0xed, 0xca, 0x7a, 0xe6, 0xec, 0x9c, 0x2b, 0x37, 0xe0, 0xb0, 0xbc, 0x6d, 0x24, 0x15, 0x0b, 0x80, 0x11, 0xf9, - 0x8d, 0x21, 0x83, 0x3d, 0x8b, 0x22, 0x07, 0x4d, 0x8f, 0xb3, 0x65, 0xb7, 0x01, 0x6a, 0x85, 0xdd, 0x8d, 0xef, 0x10, - 0x30, 0x3b, 0x05, 0x0d, 0xad, 0xbf, 0xf9, 0xdf, 0x93, 0x07, 0xf0, 0x0f, 0xe1, 0xbf, 0xef, 0x10, 0xd0, 0x37, 0xb7, - 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0x09, 0x03, 0x13, 0x05, 0x21, 0x0a, - 0x23, 0xa4, 0xe7, 0xf4, 0xef, 0x40, 0x00, 0x72, 0x41, 0x46, 0x93, 0x85, 0x04, 0x02, 0x13, 0x05, 0x21, 0x0c, 0xef, - 0x40, 0x20, 0x71, 0xef, 0x30, 0xf0, 0x76, 0x13, 0x04, 0x00, 0x03, 0xef, 0xf0, 0x2f, 0xfa, 0xa1, 0xb3, 0xb7, 0x37, - 0x20, 0x00, 0x03, 0xa7, 0x87, 0xf4, 0x93, 0x07, 0xa0, 0x0a, 0x83, 0x44, 0x14, 0x00, 0x63, 0x14, 0xf7, 0x0e, 0x91, - 0xe4, 0x13, 0x04, 0x10, 0xf8, 0xef, 0xf0, 0xef, 0xf9, 0x71, 0xbb, 0xb7, 0x39, 0x20, 0x00, 0x83, 0xa7, 0x49, 0xf4, - 0x93, 0x89, 0x49, 0xf4, 0xad, 0xcb, 0x09, 0x04, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x09, 0xf4, 0x83, 0x26, 0x09, - 0x00, 0x03, 0xa7, 0x09, 0x00, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, - 0x85, 0x77, 0xa6, 0x96, 0x13, 0x06, 0xc6, 0x58, 0x93, 0x85, 0xc5, 0x56, 0xef, 0x10, 0x80, 0x11, 0x03, 0x25, 0x09, - 0x00, 0x83, 0xa7, 0x09, 0x00, 0x33, 0x87, 0xa4, 0x00, 0xe3, 0xe6, 0xe7, 0xfa, 0x85, 0x67, 0x93, 0x87, 0x07, 0x02, - 0xe3, 0xe1, 0xe7, 0xfa, 0xb7, 0x07, 0xfa, 0xac, 0x84, 0x67, 0xc1, 0xaa, 0x07, 0x0a, 0x33, 0xa9, 0xd1, 0x33, 0x67, - 0xdc, 0x92, 0x5e, 0x7a, 0xa4, 0x96, 0x1b, 0x4c, 0x9f, 0x3f, 0xa4, 0xfd, 0x91, 0x9e, 0xb6, 0xab, 0x75, 0x8a, 0x97, - 0x50, 0x58, 0x12, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x26, 0x86, 0x3e, 0x95, 0xa2, 0x85, 0xef, 0x40, 0xa0, 0x67, - 0x83, 0x27, 0x09, 0x00, 0xbe, 0x94, 0x83, 0xa7, 0x09, 0x00, 0x23, 0x20, 0x99, 0x00, 0xbd, 0xe3, 0x75, 0x54, 0x39, - 0xbb, 0x89, 0x47, 0xe3, 0xfb, 0x97, 0xf6, 0x03, 0x49, 0x34, 0x00, 0x83, 0x47, 0x24, 0x00, 0xf9, 0x14, 0x22, 0x09, - 0x3e, 0x99, 0x85, 0x67, 0x93, 0x06, 0xf9, 0xff, 0x13, 0x87, 0xf7, 0x00, 0x11, 0x04, 0xe3, 0x6c, 0xd7, 0xf4, 0x37, - 0x0a, 0x20, 0x00, 0x13, 0x0a, 0x0a, 0x00, 0x3e, 0x9a, 0x41, 0x09, 0x93, 0x07, 0xf0, 0x07, 0xa3, 0x0c, 0xfa, 0x06, - 0x23, 0xa0, 0x29, 0x01, 0xef, 0x10, 0xb0, 0x43, 0xef, 0x20, 0xa0, 0x6c, 0xef, 0x30, 0x30, 0x0c, 0xb7, 0x37, 0x20, - 0x00, 0x23, 0x28, 0x2a, 0x07, 0x23, 0x2a, 0x0a, 0x06, 0x23, 0xa0, 0x07, 0xf4, 0x2d, 0xbf, 0x13, 0x04, 0x60, 0xf8, - 0x39, 0xbf, 0xe3, 0x9e, 0xf4, 0xf8, 0x01, 0x44, 0x89, 0xb1, 0x83, 0x47, 0x14, 0x00, 0xe3, 0x9a, 0x07, 0xc4, 0xef, - 0x10, 0xd0, 0x10, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x04, 0x05, 0xc4, 0x83, 0x20, 0xc1, 0x1d, 0x03, 0x24, 0x81, 0x1d, - 0x83, 0x24, 0x41, 0x1d, 0x03, 0x29, 0x01, 0x1d, 0x83, 0x29, 0xc1, 0x1c, 0x03, 0x2a, 0x81, 0x1c, 0x83, 0x2a, 0x41, - 0x1c, 0x03, 0x2b, 0x01, 0x1c, 0x83, 0x2b, 0xc1, 0x1b, 0x03, 0x2c, 0x81, 0x1b, 0x83, 0x2c, 0x41, 0x1b, 0x03, 0x2d, - 0x01, 0x1b, 0x83, 0x2d, 0xc1, 0x1a, 0x3e, 0x85, 0x3d, 0x61, 0xfa, 0x92, 0x00, 0xf8, 0xbc, 0x58, 0x7d, 0x04, 0x0d, - 0xf5, 0x2a, 0xd1, 0x5d, 0xa0, 0xb5, 0x48, 0x9b, 0xa1, 0x1f, 0xda, 0x71, 0x1c, 0x50, 0x11, 0x64, 0xd7, 0x62, 0xab, - 0x2c, 0xc2, 0x2d, 0xa2, 0x3a, 0x30, 0x13, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa8, 0xa7, 0xf4, 0x85, 0xbe, - 0x83, 0x46, 0x14, 0x00, 0xe3, 0x9e, 0xe6, 0xbe, 0x83, 0x47, 0x24, 0x00, 0x63, 0x8b, 0xd7, 0x02, 0x0d, 0x47, 0xe3, - 0x97, 0xe7, 0xbe, 0xa1, 0x45, 0x01, 0x45, 0xef, 0xf0, 0x5f, 0x8a, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0xe3, 0x13, - 0xf5, 0xb8, 0xb7, 0xb5, 0xb5, 0x61, 0x93, 0x85, 0x55, 0x49, 0x13, 0x05, 0x80, 0x1f, 0xef, 0x10, 0x00, 0x67, 0xb7, - 0x37, 0x20, 0x00, 0x23, 0xac, 0x87, 0xf2, 0x95, 0xb7, 0xb7, 0x15, 0x78, 0x4a, 0x93, 0x85, 0x95, 0x21, 0x13, 0x05, - 0x80, 0x1f, 0xef, 0x10, 0x60, 0x65, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xac, 0xe7, 0xf2, 0x99, - 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x47, 0xf3, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1f, 0xf7, 0xb2, 0x83, 0x47, - 0x14, 0x00, 0xe3, 0x96, 0x07, 0xb8, 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x0a, 0xef, 0x00, 0xd0, 0x6b, 0x2a, - 0x84, 0xe3, 0x51, 0x05, 0xb6, 0xc9, 0xbe, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, - 0x8d, 0x47, 0x63, 0xf4, 0xa7, 0x00, 0xef, 0xf0, 0x8f, 0xf6, 0x89, 0x67, 0x2a, 0x84, 0x93, 0x87, 0x07, 0xbf, 0x0a, - 0x05, 0x81, 0x45, 0x3e, 0x95, 0x13, 0x09, 0x04, 0x0e, 0xef, 0x20, 0x10, 0x2b, 0x16, 0x09, 0x81, 0x44, 0x93, 0x09, - 0x00, 0x02, 0x33, 0x05, 0x99, 0x00, 0x81, 0x45, 0x91, 0x04, 0xef, 0x20, 0xd0, 0x29, 0xfa, 0x27, 0x13, 0x9a, 0xf4, - 0x3f, 0x4b, 0xc3, 0x14, 0xa0, 0x31, 0x5e, 0x8f, 0xfd, 0x4a, 0xe8, 0xe2, 0xdc, 0x95, 0xb0, 0x2c, 0xca, 0x71, 0x78, - 0x01, 0x33, 0xb7, 0x79, 0x01, 0x7a, 0x49, 0x68, 0x47, 0x08, 0x14, 0xe3, 0x9a, 0x34, 0xff, 0x22, 0x85, 0xef, 0xf0, - 0x1f, 0x9b, 0x59, 0x47, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xe5, 0x00, 0x93, 0x07, 0x50, 0x05, 0xf2, 0x40, 0x62, - 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x3e, 0x85, 0x05, 0x61, 0x82, 0x80, 0x41, 0x11, 0x05, 0x45, 0x06, 0xc6, - 0xef, 0x30, 0xf0, 0x7a, 0xb2, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf4, 0x41, - 0x01, 0x82, 0x80, 0x31, 0x71, 0x22, 0xdd, 0x37, 0x34, 0x20, 0x00, 0x93, 0x07, 0x50, 0x05, 0x06, 0xdf, 0x26, 0xdb, - 0x4a, 0xd9, 0x56, 0xd3, 0x5e, 0xcf, 0x4e, 0xd7, 0x52, 0xd5, 0x5a, 0xd1, 0x62, 0xcd, 0x66, 0xcb, 0x6a, 0xc9, 0x6e, - 0xc7, 0x37, 0x39, 0x20, 0x00, 0xb7, 0x34, 0x20, 0x00, 0xb7, 0x3b, 0x20, 0x00, 0x13, 0x04, 0x44, 0xf3, 0x23, 0x26, - 0xf9, 0xf4, 0x23, 0xac, 0xf4, 0xf2, 0x23, 0xa8, 0xfb, 0xf4, 0x1c, 0xc0, 0xef, 0x10, 0xa0, 0x32, 0xef, 0x10, 0x00, - 0x4b, 0x13, 0x07, 0xc9, 0xf4, 0x3a, 0xc8, 0x13, 0x87, 0x84, 0xf3, 0x3a, 0xca, 0x13, 0x87, 0x0b, 0xf5, 0x93, 0x07, - 0xa0, 0x0a, 0x3a, 0xc6, 0xb7, 0x5a, 0x10, 0x00, 0x85, 0x45, 0x63, 0x0a, 0xf5, 0x00, 0x13, 0x85, 0x4a, 0x55, 0xef, - 0x00, 0xd0, 0x70, 0xef, 0x10, 0xc0, 0x44, 0xef, 0xf0, 0x0f, 0xe8, 0x41, 0x45, 0xef, 0xf0, 0x2f, 0xf3, 0x08, 0xc0, - 0xb7, 0x07, 0x01, 0x02, 0x80, 0x57, 0x98, 0x5b, 0x29, 0x45, 0x59, 0x8c, 0x98, 0x5f, 0x59, 0x8c, 0x13, 0x77, 0xfa, - 0xe7, 0xa0, 0x47, 0x65, 0x38, 0x4e, 0x10, 0x14, 0xe6, 0x1d, 0x41, 0x20, 0x84, 0x4f, 0xca, 0x4b, 0xac, 0x4e, 0x99, - 0xfe, 0xb6, 0xfe, 0xb3, 0x54, 0x1f, 0xfc, 0x79, 0x6b, 0xa6, 0x58, 0x9d, 0x2f, 0xe0, 0x14, 0xf4, 0x87, 0x98, 0xd7, - 0x98, 0xdb, 0x98, 0xdf, 0xd8, 0x43, 0x13, 0x67, 0x87, 0x00, 0xd8, 0xc3, 0xef, 0x10, 0x40, 0x2d, 0xef, 0x30, 0x10, - 0x27, 0x13, 0x75, 0x05, 0x78, 0x11, 0xc5, 0x13, 0x05, 0x00, 0x78, 0x81, 0x45, 0xef, 0x30, 0x70, 0x1f, 0xb7, 0x07, - 0x01, 0x02, 0x80, 0xd7, 0x80, 0xdb, 0x37, 0x15, 0x10, 0x00, 0x80, 0xdf, 0x13, 0x05, 0x85, 0x9f, 0xef, 0x10, 0x00, - 0x61, 0x13, 0x05, 0x00, 0x1f, 0xef, 0x10, 0x40, 0x45, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x59, 0x10, 0x00, 0xaa, 0x86, - 0x13, 0x06, 0x06, 0x5a, 0x93, 0x85, 0x4a, 0x55, 0x13, 0x85, 0x89, 0x77, 0xef, 0x00, 0x50, 0x61, 0xef, 0x30, 0xf0, - 0x22, 0x93, 0x07, 0x50, 0x05, 0x63, 0x1e, 0xf5, 0x00, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, - 0x06, 0x5b, 0x93, 0x85, 0x4a, 0x55, 0x13, 0x05, 0x45, 0x57, 0xef, 0x00, 0x10, 0x5f, 0xef, 0x20, 0x20, 0x20, 0x51, - 0x45, 0xef, 0x10, 0xc0, 0x40, 0x1d, 0x89, 0xef, 0x20, 0x40, 0x20, 0xef, 0x10, 0x30, 0x74, 0xef, 0x20, 0xa0, 0x76, - 0xef, 0x20, 0x40, 0x7b, 0xef, 0x20, 0x90, 0x2a, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0x10, 0x2b, 0x6c, 0x10, 0x11, - 0x46, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0x30, 0x32, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0x10, 0x2e, 0x32, 0x55, - 0xef, 0x20, 0x50, 0x1f, 0x09, 0x65, 0x13, 0x05, 0x05, 0x98, 0xef, 0x20, 0x50, 0x03, 0xfd, 0x57, 0x8d, 0x45, 0x63, - 0x12, 0xf5, 0x02, 0xfa, 0x56, 0x47, 0xaa, 0x7a, 0xf3, 0xc1, 0x7b, 0x91, 0xf6, 0x2e, 0x4b, 0x52, 0x32, 0xad, 0x1e, - 0x43, 0xeb, 0x5f, 0x75, 0xc9, 0x64, 0x05, 0xce, 0xa1, 0xd5, 0x85, 0xa4, 0xe3, 0xfe, 0xe3, 0x3b, 0x41, 0xb8, 0x15, - 0x01, 0x44, 0x13, 0x09, 0x00, 0x18, 0x22, 0x85, 0xef, 0xf0, 0x8f, 0xe2, 0xaa, 0x84, 0x22, 0x85, 0xef, 0xf0, 0x2f, - 0xfb, 0x93, 0x47, 0xf5, 0xff, 0x33, 0xf5, 0x97, 0x00, 0x19, 0xc5, 0x89, 0x45, 0x13, 0x85, 0x4a, 0x55, 0xef, 0x00, - 0xb0, 0x5e, 0xcd, 0xb5, 0x11, 0x04, 0xe3, 0x1d, 0x24, 0xfd, 0x37, 0x55, 0x10, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x13, - 0x07, 0x50, 0x05, 0x13, 0x05, 0x45, 0x72, 0x23, 0xa4, 0xe7, 0xf4, 0xef, 0x10, 0x30, 0x10, 0xb7, 0x55, 0x10, 0x00, - 0x13, 0x06, 0x40, 0x05, 0x93, 0x85, 0x05, 0x67, 0x68, 0x10, 0xef, 0x40, 0x00, 0x2d, 0x60, 0x10, 0x48, 0x40, 0x01, - 0xc5, 0xef, 0x20, 0x80, 0x7c, 0x48, 0xc0, 0x31, 0x04, 0x1c, 0x01, 0xe3, 0x99, 0x87, 0xfe, 0x37, 0x55, 0x10, 0x00, - 0x1d, 0x46, 0x6c, 0x10, 0x13, 0x05, 0x05, 0x73, 0xef, 0x20, 0x00, 0x36, 0xef, 0x20, 0x40, 0x4c, 0xef, 0xf0, 0xef, - 0xc1, 0x05, 0x45, 0xef, 0x10, 0xa0, 0x77, 0xef, 0x30, 0xa0, 0x50, 0xef, 0x30, 0xf0, 0x29, 0x01, 0x45, 0xef, 0x30, - 0x70, 0x59, 0x37, 0x0a, 0x20, 0x00, 0x05, 0x6c, 0x93, 0x07, 0x0a, 0x00, 0xb7, 0x14, 0x20, 0x00, 0x33, 0x8b, 0x87, - 0x01, 0x93, 0x84, 0xc4, 0x07, 0xef, 0x10, 0x80, 0x5d, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf4, 0x63, 0x81, - 0x07, 0x10, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0x07, 0xf4, 0x63, 0x9b, 0xe7, 0x0e, 0xb7, 0x37, 0x20, 0x00, 0x03, - 0xc7, 0xc7, 0xf3, 0x93, 0x87, 0xc7, 0xf3, 0xfa, 0xdc, 0x0e, 0xdd, 0x7e, 0x5c, 0xb5, 0xff, 0xa9, 0x6d, 0x6c, 0x3a, - 0xac, 0x64, 0x18, 0x57, 0x52, 0x2e, 0xfd, 0xf3, 0x16, 0x80, 0xde, 0xb1, 0x1b, 0xb3, 0xbc, 0xb5, 0xd8, 0x26, 0x58, - 0xca, 0x41, 0x90, 0x16, 0x3e, 0xcc, 0xe3, 0x1e, 0x07, 0x2e, 0x03, 0x26, 0x0b, 0x07, 0x93, 0x07, 0xf0, 0x07, 0x37, - 0x14, 0x20, 0x00, 0xa3, 0x0c, 0xfb, 0x06, 0xc1, 0x4c, 0x13, 0x0d, 0x0a, 0x00, 0x13, 0x04, 0x04, 0x00, 0x63, 0xfd, - 0xcc, 0x0a, 0x13, 0x09, 0x06, 0xff, 0xef, 0x10, 0x40, 0x67, 0x01, 0x45, 0xef, 0x30, 0x60, 0x54, 0x4a, 0x86, 0x63, - 0xf3, 0x2c, 0x01, 0x41, 0x46, 0x93, 0x05, 0x0a, 0x00, 0x68, 0x10, 0xef, 0x30, 0xa0, 0x56, 0xef, 0x10, 0xa0, 0x6c, - 0xb7, 0x57, 0x10, 0x00, 0x23, 0x0c, 0xa4, 0x06, 0x93, 0x87, 0x47, 0x6c, 0x03, 0xc7, 0x07, 0x00, 0x63, 0x10, 0x07, - 0x14, 0x03, 0x29, 0x04, 0x07, 0xc1, 0x4b, 0x63, 0xf5, 0x2b, 0x07, 0x01, 0x45, 0xef, 0x30, 0xc0, 0x50, 0x41, 0x19, - 0x4a, 0x86, 0x93, 0x05, 0x0a, 0x00, 0x13, 0x05, 0x0a, 0x00, 0xef, 0x30, 0x20, 0x53, 0xb7, 0x1c, 0x20, 0x00, 0x13, - 0x85, 0x0c, 0x02, 0xef, 0x30, 0xe0, 0x6f, 0xef, 0x30, 0xc0, 0x74, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x5d, 0x10, 0x00, - 0xaa, 0x86, 0x13, 0x06, 0x06, 0x5c, 0x93, 0x85, 0x8d, 0x53, 0x13, 0x85, 0x89, 0x77, 0xef, 0x00, 0xf0, 0x41, 0x93, - 0x85, 0x0c, 0x02, 0x41, 0x46, 0x33, 0x05, 0x2d, 0x01, 0xef, 0x00, 0xf0, 0x30, 0xaa, 0x8c, 0x63, 0x0f, 0x05, 0x0e, - 0x89, 0x45, 0x13, 0x85, 0x8d, 0x53, 0xef, 0x00, 0x70, 0x47, 0x93, 0x07, 0xb0, 0x07, 0xa3, 0x0c, 0xf4, 0x06, 0x37, - 0x55, 0x10, 0x00, 0x91, 0x45, 0x13, 0x05, 0xc5, 0x56, 0xef, 0x00, 0xfa, 0xa7, 0xea, 0xf6, 0xa0, 0x46, 0x14, 0x4a, - 0xb5, 0xb3, 0x67, 0x42, 0x7c, 0xc9, 0x1b, 0x9f, 0x19, 0x35, 0xe3, 0xc8, 0x59, 0x23, 0x3f, 0x5c, 0x35, 0x7b, 0x50, - 0xbc, 0xfa, 0x28, 0xf9, 0x65, 0xf6, 0x68, 0x17, 0x10, 0x46, 0xef, 0xe0, 0x1f, 0xea, 0xef, 0xe0, 0x5f, 0xfa, 0xef, - 0xf0, 0x4f, 0xa2, 0xef, 0x10, 0x00, 0x4b, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x1d, 0xf5, 0x08, 0xb7, 0x37, - 0x20, 0x00, 0x83, 0xc7, 0xc7, 0xf3, 0xd9, 0xe7, 0xef, 0x00, 0xd0, 0x7a, 0xe3, 0x16, 0x85, 0x18, 0xd2, 0x47, 0x9c, - 0x43, 0x63, 0x9a, 0xa7, 0x00, 0x13, 0x04, 0xa0, 0x0a, 0xef, 0x30, 0xf0, 0x3a, 0xe3, 0x1e, 0x85, 0xfe, 0xef, 0x10, - 0x20, 0x10, 0xb2, 0x47, 0x98, 0x43, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1e, 0xf7, 0x14, 0x37, 0x56, 0x10, 0x00, 0x13, - 0x06, 0x46, 0x61, 0x93, 0x85, 0x4a, 0x55, 0x13, 0x85, 0x89, 0x77, 0xef, 0x00, 0x70, 0x38, 0xef, 0xf0, 0x8f, 0x9c, - 0x37, 0x25, 0x00, 0x08, 0xef, 0x20, 0x70, 0x0a, 0xef, 0xf0, 0x0f, 0x9a, 0xef, 0x20, 0xa0, 0x59, 0xef, 0x10, 0x10, - 0x0f, 0xef, 0x20, 0x50, 0x23, 0xef, 0xe0, 0xbf, 0xe5, 0x32, 0x47, 0x37, 0x56, 0x10, 0x00, 0x93, 0x07, 0x50, 0x05, - 0x13, 0x06, 0x06, 0x62, 0x93, 0x85, 0x4a, 0x55, 0x13, 0x85, 0x89, 0x77, 0x1c, 0xc3, 0xef, 0x00, 0xb0, 0x34, 0xef, - 0x20, 0x30, 0x23, 0xef, 0x10, 0x50, 0x3b, 0xef, 0x20, 0x20, 0x5b, 0xef, 0x30, 0x90, 0x08, 0xc2, 0x47, 0x98, 0x43, - 0x93, 0x07, 0x50, 0x05, 0xe3, 0x03, 0xf7, 0xe4, 0x71, 0xb9, 0x63, 0x1c, 0xe5, 0x00, 0x83, 0xc7, 0x17, 0x00, 0xbd, - 0x8b, 0xe3, 0x8d, 0x07, 0xea, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0xa0, 0x60, 0x7d, 0xb5, 0xfa, 0xca, 0xd6, 0x98, - 0x56, 0xbd, 0xa0, 0x46, 0xd0, 0x15, 0x0a, 0x23, 0x5c, 0x95, 0xab, 0xfd, 0x6d, 0xed, 0x5c, 0x4b, 0x36, 0x06, 0x35, - 0xec, 0x63, 0x82, 0xfc, 0xbc, 0x7d, 0x99, 0x5c, 0x5d, 0x93, 0x40, 0x18, 0x91, 0x07, 0x4d, 0xb5, 0x03, 0x29, 0x04, - 0x07, 0xe3, 0xef, 0x2b, 0x0d, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0xc5, 0x56, 0xef, 0x00, 0x10, 0x37, - 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x56, 0x95, 0x45, 0xef, 0x00, 0x30, 0x36, 0x13, 0x05, 0xf0, 0x07, 0x09, - 0xb7, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0xc7, 0xf5, 0x14, 0x43, 0xb7, 0x55, 0x10, 0x00, 0xde, 0x87, 0x13, 0x86, - 0x16, 0x00, 0x10, 0xc3, 0x03, 0x47, 0x84, 0x07, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0x06, 0x5d, 0x93, 0x85, 0xc5, - 0x56, 0x13, 0x85, 0x89, 0x77, 0xef, 0x00, 0x90, 0x2b, 0x03, 0x47, 0x84, 0x07, 0x93, 0x06, 0x20, 0x04, 0x63, 0x07, - 0xd7, 0x4c, 0x63, 0xeb, 0xe6, 0x18, 0x93, 0x06, 0x10, 0x02, 0x63, 0x0f, 0xd7, 0x3c, 0x63, 0xe3, 0xe6, 0x08, 0xc5, - 0x46, 0x63, 0x04, 0xd7, 0x32, 0x63, 0xe9, 0xe6, 0x02, 0x85, 0x46, 0x63, 0x09, 0xd7, 0x24, 0xc1, 0x46, 0x63, 0x02, - 0xd7, 0x26, 0x89, 0x4c, 0xe5, 0xac, 0x13, 0x07, 0x07, 0xfa, 0x13, 0x77, 0xf7, 0x0f, 0xc5, 0x46, 0xe3, 0xe9, 0xe6, - 0xfe, 0xb7, 0x56, 0x10, 0x00, 0x0a, 0x07, 0x93, 0x86, 0x86, 0x62, 0x36, 0x97, 0x18, 0x43, 0x02, 0x87, 0xc9, 0x46, - 0x63, 0x0e, 0xd7, 0x34, 0x93, 0x06, 0x00, 0x02, 0xe3, 0x1a, 0xd7, 0xfc, 0x21, 0x47, 0x93, 0x0c, 0x00, 0x08, 0x63, - 0x92, 0xeb, 0x2c, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x94, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x80, 0x63, 0x9e, - 0xfa, 0x5d, 0x47, 0x07, 0x49, 0x37, 0x24, 0xf7, 0x27, 0x79, 0xec, 0x31, 0xce, 0x0d, 0xfe, 0x44, 0x29, 0x94, 0xe2, - 0x69, 0xaa, 0xd7, 0xdf, 0xf3, 0x7d, 0xc6, 0xb8, 0xa8, 0x8a, 0x64, 0x94, 0xee, 0xb3, 0x18, 0x19, 0x07, 0x4a, 0x93, - 0x07, 0xf0, 0x1f, 0x63, 0xea, 0x87, 0x4a, 0x22, 0x85, 0xef, 0x10, 0x50, 0x09, 0xfd, 0x57, 0x63, 0x14, 0xf5, 0x4a, - 0x83, 0x25, 0x4d, 0x00, 0x22, 0x85, 0xef, 0x10, 0x90, 0x11, 0x81, 0xae, 0x93, 0x06, 0x10, 0x03, 0x63, 0x08, 0xd7, - 0x38, 0x63, 0xec, 0xe6, 0x08, 0x93, 0x06, 0x20, 0x02, 0x63, 0x09, 0xd7, 0x36, 0x93, 0x06, 0x00, 0x03, 0xe3, 0x1e, - 0xd7, 0xf6, 0x11, 0x47, 0x93, 0x0c, 0x00, 0x08, 0x63, 0x96, 0xeb, 0x26, 0x03, 0x27, 0x0d, 0x00, 0x21, 0x83, 0x93, - 0x16, 0x07, 0x01, 0x0d, 0x8b, 0xc1, 0x82, 0x63, 0x12, 0x07, 0x46, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xee, 0xd7, 0x44, - 0x83, 0x47, 0x3d, 0x00, 0x7d, 0x47, 0x63, 0x69, 0xf7, 0x44, 0x13, 0xd4, 0x37, 0x00, 0x36, 0x94, 0x0a, 0x04, 0x62, - 0x94, 0x93, 0xfd, 0x77, 0x00, 0x22, 0x85, 0x05, 0x49, 0xef, 0x20, 0x60, 0x4c, 0x33, 0x19, 0xb9, 0x01, 0xb3, 0x77, - 0xa9, 0x00, 0xaa, 0x8c, 0x63, 0x80, 0x07, 0x22, 0x8a, 0x0d, 0xbd, 0x45, 0xb3, 0x95, 0xb5, 0x01, 0x93, 0xc5, 0xf5, - 0xff, 0x22, 0x85, 0xef, 0x20, 0xa0, 0x4e, 0x22, 0x85, 0x13, 0x49, 0xf9, 0xff, 0xef, 0x20, 0xc0, 0x49, 0x33, 0x79, - 0x99, 0x01, 0x63, 0x0e, 0x25, 0x1f, 0x09, 0x65, 0x81, 0x45, 0x13, 0x05, 0x05, 0x98, 0xef, 0x20, 0xc0, 0x4c, 0x75, - 0xaa, 0x93, 0x06, 0x00, 0x04, 0x63, 0x0d, 0xd7, 0x30, 0x93, 0x06, 0x10, 0x04, 0xe3, 0x14, 0xd7, 0xee, 0x0d, 0x47, - 0x63, 0x90, 0xeb, 0x72, 0xfa, 0xc8, 0xac, 0x7e, 0x5b, 0x3e, 0x4e, 0x2a, 0x54, 0xb0, 0xb5, 0x35, 0x35, 0x71, 0xe0, - 0xfd, 0x7c, 0x51, 0x88, 0x42, 0x00, 0x53, 0x9a, 0x2c, 0x83, 0x26, 0xb5, 0x77, 0x4b, 0x2b, 0xac, 0x18, 0x22, 0xf0, - 0x19, 0x83, 0x27, 0x0d, 0x00, 0x13, 0x07, 0xf0, 0x1f, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, 0x63, 0x6a, 0xf7, 0x3c, - 0xef, 0x10, 0xf0, 0x48, 0xef, 0x20, 0xe0, 0x75, 0x83, 0x27, 0x0d, 0x00, 0x91, 0x65, 0x93, 0x85, 0x05, 0x20, 0xa1, - 0x83, 0xc2, 0x07, 0xc1, 0x83, 0xa6, 0x07, 0x37, 0x15, 0x20, 0x00, 0xbe, 0x95, 0x13, 0x05, 0x05, 0x08, 0xef, 0x10, - 0xd0, 0x0a, 0x2a, 0x84, 0xef, 0x20, 0xa0, 0x75, 0x93, 0x07, 0xb0, 0x1d, 0xe3, 0xe7, 0x87, 0xa8, 0x93, 0x05, 0x44, - 0x00, 0x39, 0xa4, 0x93, 0x06, 0x10, 0x07, 0x63, 0xe9, 0xe6, 0x02, 0x93, 0x06, 0xf0, 0x05, 0xe3, 0xe4, 0xe6, 0xe8, - 0x93, 0x06, 0x00, 0x05, 0xe3, 0x1e, 0xd7, 0xe6, 0x09, 0x47, 0x93, 0x0c, 0x00, 0x08, 0x63, 0x96, 0xeb, 0x16, 0x03, - 0x44, 0x1d, 0x00, 0x37, 0x15, 0x20, 0x00, 0x13, 0x05, 0x05, 0x08, 0xa2, 0x85, 0xef, 0xe0, 0x9f, 0xc7, 0xd9, 0xb7, - 0x93, 0x06, 0x20, 0x08, 0x63, 0x09, 0xd7, 0x64, 0x63, 0xed, 0xe6, 0x04, 0x93, 0x06, 0x00, 0x08, 0x63, 0x00, 0xd7, - 0x5e, 0x93, 0x06, 0x10, 0x08, 0xe3, 0x11, 0xd7, 0xe4, 0x0d, 0x47, 0x93, 0x0c, 0x00, 0x08, 0x63, 0x99, 0xeb, 0x12, - 0x03, 0x45, 0x1d, 0x00, 0x3d, 0x47, 0x81, 0x47, 0x63, 0x6e, 0xa7, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, - 0xf6, 0x89, 0x47, 0x33, 0x57, 0xa7, 0x00, 0x05, 0x8b, 0x01, 0xc7, 0xef, 0xe0, 0xff, 0xd6, 0xaa, 0x87, 0xfd, 0x17, - 0x09, 0x47, 0x63, 0x68, 0xf7, 0x30, 0x37, 0x65, 0xfa, 0xcc, 0xad, 0x82, 0xbd, 0x2b, 0x90, 0x53, 0x35, 0x2a, 0x42, - 0xc5, 0x83, 0x22, 0x72, 0x80, 0x54, 0x91, 0x8f, 0xa3, 0x7a, 0xd5, 0xdc, 0x0e, 0x5c, 0xa1, 0x05, 0x76, 0xb4, 0xfd, - 0x60, 0x9d, 0x2d, 0xc8, 0x1a, 0x10, 0x00, 0x13, 0x05, 0x85, 0x87, 0xaa, 0x97, 0x83, 0xcc, 0x07, 0x00, 0xd5, 0xa8, - 0x93, 0x06, 0x00, 0x09, 0xe3, 0x1a, 0xd7, 0xde, 0x13, 0x07, 0x40, 0x02, 0x93, 0x0c, 0x00, 0x08, 0x63, 0x91, 0xeb, - 0x0e, 0xef, 0x20, 0x20, 0x01, 0xef, 0x20, 0x60, 0x67, 0xef, 0x20, 0xa0, 0x01, 0x2a, 0x89, 0xef, 0x20, 0xc0, 0x00, - 0xef, 0x20, 0xa0, 0x68, 0x13, 0x07, 0xa0, 0x0a, 0x63, 0x17, 0xe9, 0x2c, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0x80, - 0x33, 0x23, 0x2a, 0x74, 0x07, 0x45, 0xa8, 0x13, 0x07, 0x1c, 0x00, 0x93, 0x0c, 0x00, 0x08, 0x63, 0x65, 0x77, 0x0b, - 0xde, 0x85, 0x13, 0x05, 0x0a, 0x00, 0xef, 0xe0, 0xff, 0xee, 0x61, 0xa8, 0x13, 0x07, 0x40, 0x02, 0x63, 0x9d, 0xeb, - 0x5c, 0x03, 0x25, 0x0d, 0x00, 0x0d, 0x44, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0x68, 0xa4, 0x28, 0xef, 0xf0, - 0x8f, 0xa7, 0xd5, 0x47, 0x63, 0x13, 0xf5, 0x28, 0x03, 0x29, 0x0d, 0x00, 0x13, 0x59, 0x89, 0x00, 0x42, 0x09, 0x13, - 0x59, 0x09, 0x01, 0xe3, 0x62, 0x24, 0x97, 0x13, 0x04, 0x09, 0x0e, 0x16, 0x04, 0x91, 0x4c, 0x71, 0x14, 0x93, 0x0b, - 0xa0, 0x0a, 0x93, 0x0d, 0x40, 0x02, 0xb3, 0x05, 0x9d, 0x01, 0x11, 0x46, 0x68, 0x10, 0xef, 0x30, 0x30, 0x56, 0xb2, - 0x55, 0x33, 0x05, 0x94, 0x01, 0xef, 0x20, 0xc0, 0x36, 0x63, 0x07, 0x75, 0x01, 0x4a, 0x85, 0xef, 0xf0, 0x9f, 0x83, - 0xdd, 0x4c, 0x0d, 0xa8, 0x91, 0x0c, 0xe3, 0x9d, 0xbc, 0xfd, 0x89, 0x67, 0xfa, 0x51, 0xff, 0x8d, 0x38, 0x3c, 0xb7, - 0xe2, 0x1d, 0x58, 0x65, 0x27, 0x3b, 0x01, 0x58, 0x45, 0xd0, 0x2d, 0x69, 0x94, 0xbc, 0x06, 0xee, 0xe3, 0x61, 0xf5, - 0x49, 0xb2, 0xae, 0x2f, 0x0a, 0xce, 0xf4, 0xa0, 0x1b, 0x93, 0x87, 0x07, 0xbf, 0x13, 0x15, 0x29, 0x00, 0xb7, 0xf5, - 0xf0, 0xf0, 0x3e, 0x95, 0x93, 0x85, 0x05, 0x0f, 0xef, 0x20, 0xe0, 0x2e, 0x4a, 0x85, 0xef, 0xf0, 0x6f, 0xa0, 0x93, - 0x07, 0x30, 0x0c, 0xe3, 0x1a, 0xf5, 0xfc, 0x93, 0x0c, 0x30, 0x0c, 0x13, 0x06, 0x0c, 0x01, 0x81, 0x45, 0x26, 0x85, - 0xef, 0x30, 0xb0, 0x54, 0x93, 0x07, 0x00, 0x08, 0xe3, 0x81, 0xfc, 0xc8, 0x13, 0xf5, 0xfc, 0x0f, 0x4d, 0xa3, 0x0d, - 0x47, 0x63, 0x94, 0xeb, 0x52, 0x03, 0x25, 0x0d, 0x00, 0x0d, 0x44, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0x6f, - 0xa4, 0x1c, 0xef, 0xf0, 0x6f, 0x9c, 0x93, 0x07, 0x30, 0x0c, 0x63, 0x04, 0xf5, 0x00, 0xaa, 0x8c, 0xc9, 0xb7, 0x83, - 0x27, 0x0d, 0x00, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, 0xe3, 0x68, 0xf4, 0x8a, 0x93, 0x87, 0x07, 0x0e, 0x13, 0x94, - 0x57, 0x00, 0x13, 0x09, 0x00, 0x02, 0x33, 0x85, 0x8c, 0x00, 0xef, 0x20, 0xa0, 0x1b, 0xb7, 0x17, 0x20, 0x00, 0x93, - 0x87, 0x07, 0x08, 0x2a, 0xd6, 0x11, 0x46, 0x33, 0x85, 0x97, 0x01, 0x6c, 0x10, 0x91, 0x0c, 0xef, 0x30, 0x10, 0x4a, - 0xe3, 0x90, 0x2c, 0xff, 0x93, 0x05, 0x40, 0x02, 0x26, 0x85, 0xf1, 0xbd, 0x0d, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, - 0x9a, 0xeb, 0xf6, 0x03, 0x25, 0x0d, 0x00, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0xe8, 0xab, 0x16, 0xef, 0xf0, - 0x8f, 0x95, 0xd5, 0x47, 0x63, 0x03, 0xf5, 0x16, 0xd9, 0x47, 0x93, 0x0c, 0x30, 0x0c, 0xe3, 0x09, 0xfa, 0x2a, 0x6d, - 0x1c, 0xba, 0x2a, 0x0e, 0x06, 0x18, 0xc4, 0x5f, 0xd4, 0x9d, 0x5d, 0x46, 0x6f, 0x5d, 0x09, 0xc4, 0xd5, 0xf2, 0x20, - 0x95, 0x98, 0x5b, 0x21, 0x74, 0x76, 0x25, 0xb9, 0xb0, 0x8d, 0x4c, 0x78, 0x1c, 0xf5, 0xf4, 0x03, 0x25, 0x0d, 0x00, - 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0xef, 0xf0, 0x4f, 0xf4, 0x93, 0x07, 0xa0, 0x0a, 0x15, 0xbf, 0x0d, 0x47, 0x93, - 0x0c, 0x00, 0x08, 0xe3, 0x9a, 0xeb, 0xf2, 0x83, 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, 0x07, 0x01, 0x8d, 0x8b, - 0x41, 0x81, 0x63, 0x96, 0x07, 0x12, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe2, 0xa7, 0x12, 0xef, 0x10, 0x60, 0x50, 0xc8, - 0xc0, 0xa1, 0x45, 0x41, 0xbf, 0x05, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x93, 0xeb, 0xf0, 0x01, 0x45, 0xef, 0x10, - 0x70, 0x19, 0xe5, 0xbd, 0x0d, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x9a, 0xeb, 0xee, 0x83, 0x27, 0x0d, 0x00, 0xa1, - 0x83, 0x13, 0x95, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x81, 0x63, 0x96, 0x07, 0x0e, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe2, - 0xa7, 0x0e, 0xef, 0xf0, 0x8f, 0x88, 0xc1, 0xb7, 0x93, 0x07, 0xb9, 0xfe, 0x13, 0x07, 0xa0, 0x1d, 0x93, 0x0c, 0x00, - 0x08, 0xe3, 0x62, 0xf7, 0xec, 0x03, 0x25, 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, - 0x63, 0xee, 0xa7, 0x0a, 0x11, 0x64, 0x26, 0x05, 0x13, 0x04, 0x04, 0x20, 0x22, 0x95, 0xef, 0x10, 0xb0, 0x0f, 0x93, - 0x07, 0xa0, 0x0a, 0xaa, 0x8d, 0xc1, 0x4c, 0xe3, 0x1c, 0xf5, 0xe8, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0xff, 0x9a, - 0xef, 0x20, 0x80, 0x42, 0x83, 0x27, 0x0d, 0x00, 0xb7, 0x05, 0x20, 0x00, 0x74, 0x10, 0xa1, 0x83, 0xc2, 0x07, 0xc1, - 0x83, 0xfa, 0xae, 0x20, 0x89, 0x54, 0xcb, 0x4c, 0xf8, 0xd7, 0x3e, 0xde, 0xdc, 0x9f, 0xf4, 0x09, 0x40, 0xcf, 0x42, - 0x9b, 0x8d, 0x5f, 0x6c, 0x9d, 0x47, 0xa1, 0x11, 0xd6, 0x67, 0x24, 0x36, 0xda, 0x53, 0xee, 0x50, 0x1d, 0xa6, 0x07, - 0x33, 0x85, 0x87, 0x00, 0x13, 0x06, 0xc9, 0xfe, 0x93, 0x85, 0x45, 0x00, 0xef, 0x10, 0x80, 0x7f, 0x2a, 0x84, 0x93, - 0x0c, 0x30, 0x0c, 0xef, 0x20, 0xe0, 0x41, 0xe3, 0x14, 0xb4, 0xe3, 0xa1, 0xbd, 0x0d, 0x47, 0x93, 0x0c, 0x00, 0x08, - 0xe3, 0x98, 0xeb, 0xe4, 0x03, 0x25, 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, - 0xe4, 0xa7, 0x04, 0x91, 0x67, 0x26, 0x05, 0x93, 0x87, 0x07, 0x20, 0x3e, 0x95, 0x05, 0xbf, 0x11, 0x47, 0x93, 0x0c, - 0x00, 0x08, 0xe3, 0x94, 0xeb, 0xe2, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, 0xff, 0x93, 0x68, 0x10, 0xef, 0x10, 0x80, - 0x79, 0xef, 0x30, 0xc0, 0x32, 0xef, 0x20, 0xe0, 0x3a, 0x91, 0x45, 0x13, 0x05, 0x00, 0x06, 0xef, 0x30, 0x00, 0x47, - 0x2a, 0x84, 0xef, 0x20, 0x00, 0x3c, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x0b, 0xf4, 0xde, 0x93, 0x0c, 0xc0, 0x03, 0xcd, - 0xbb, 0x13, 0x07, 0x00, 0x03, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x94, 0xeb, 0xde, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, - 0xff, 0x8f, 0x68, 0x10, 0xef, 0x10, 0x80, 0x75, 0xef, 0x30, 0xc0, 0x2e, 0xef, 0x20, 0xe0, 0x36, 0x93, 0x05, 0x00, - 0x03, 0x13, 0x05, 0x10, 0x06, 0x7d, 0xbf, 0x0d, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x9f, 0xeb, 0xda, 0xef, 0x30, - 0x00, 0x2d, 0xef, 0x20, 0x20, 0x35, 0x8d, 0x45, 0x13, 0x05, 0x20, 0x06, 0xef, 0x30, 0x40, 0x41, 0x2a, 0x84, 0xef, - 0x20, 0x40, 0x36, 0x93, 0x07, 0xfa, 0x21, 0x45, 0x84, 0x92, 0x61, 0x6a, 0xbf, 0x01, 0x16, 0xa6, 0xef, 0xb0, 0x10, - 0x26, 0x9d, 0xa1, 0x77, 0x29, 0x5d, 0xd9, 0x0c, 0x08, 0x62, 0x30, 0xc9, 0xd4, 0x20, 0xc6, 0x20, 0x26, 0xce, 0xa5, - 0x28, 0x1e, 0xa0, 0x0a, 0xe3, 0x14, 0xf4, 0xfa, 0xef, 0xe0, 0x9f, 0xd8, 0xc9, 0xbb, 0x0d, 0x47, 0x93, 0x0c, 0x00, - 0x08, 0xe3, 0x97, 0xeb, 0xd8, 0xef, 0x30, 0x00, 0x2a, 0x8d, 0x45, 0x13, 0x05, 0x30, 0x06, 0xef, 0x30, 0x80, 0x3e, - 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x11, 0xf5, 0xf8, 0x85, 0xbb, 0x13, 0x07, 0x00, 0x03, 0x93, 0x0c, 0x00, 0x08, 0xe3, - 0x95, 0xeb, 0xd6, 0xef, 0x30, 0xc0, 0x27, 0xef, 0x20, 0xf0, 0x7f, 0xb7, 0x15, 0x20, 0x00, 0x2a, 0xd6, 0x13, 0x06, - 0x00, 0x02, 0x93, 0x85, 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, 0xef, 0x30, 0xa0, 0x31, 0x11, 0x46, 0x6c, 0x10, 0x13, - 0x05, 0x00, 0x0c, 0xef, 0x30, 0xe0, 0x30, 0xef, 0x20, 0x80, 0x2d, 0x93, 0x05, 0x40, 0x02, 0x13, 0x05, 0x00, 0x07, - 0xef, 0x30, 0x80, 0x39, 0x2a, 0x84, 0xef, 0x20, 0x80, 0x2e, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x16, 0xf4, 0xf2, 0xef, - 0xe0, 0xdf, 0xd0, 0x99, 0xbb, 0x3d, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x79, 0x77, 0xd1, 0xef, 0x30, 0x40, 0x22, - 0xef, 0x20, 0x70, 0x7a, 0xaa, 0x8c, 0x01, 0x45, 0xef, 0x20, 0xf0, 0x53, 0x41, 0x46, 0x93, 0x05, 0x0a, 0x00, 0x01, - 0x45, 0xef, 0x20, 0x90, 0x56, 0xef, 0x20, 0xe0, 0x28, 0xb7, 0x15, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, - 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, 0x66, 0xd6, 0xef, 0x30, 0xa0, 0x2a, 0x11, 0x46, 0x6c, 0x10, 0x13, 0x05, 0x00, - 0x0c, 0xef, 0x30, 0xe0, 0x29, 0x85, 0x45, 0x13, 0x05, 0xfa, 0x78, 0x2b, 0x26, 0x00, 0x24, 0x3b, 0x4f, 0xbc, 0x4a, - 0x35, 0xa8, 0x5b, 0x42, 0xa5, 0x87, 0x80, 0xcf, 0xb4, 0x5c, 0x87, 0x92, 0xd6, 0xd3, 0x48, 0x3c, 0xcc, 0x0c, 0xd0, - 0x17, 0x84, 0x4d, 0x35, 0x00, 0x1f, 0x10, 0x04, 0xef, 0x30, 0xe0, 0x32, 0x93, 0x07, 0xa0, 0x0a, 0xaa, 0x8c, 0x63, - 0x19, 0xf5, 0x00, 0x81, 0x45, 0x13, 0x05, 0x20, 0x04, 0xef, 0x30, 0xa0, 0x31, 0x63, 0x05, 0x95, 0x01, 0xef, 0x20, - 0x80, 0x26, 0x45, 0xbd, 0xef, 0x20, 0x20, 0x26, 0x37, 0x07, 0x20, 0x00, 0x93, 0x0d, 0x09, 0xfe, 0xee, 0x8c, 0x13, - 0x0d, 0x07, 0x01, 0xba, 0x8b, 0x13, 0x07, 0x00, 0x09, 0x63, 0x62, 0x97, 0x09, 0xea, 0x85, 0x66, 0x86, 0x01, 0x45, - 0xef, 0x20, 0x50, 0x4f, 0xe6, 0x85, 0x13, 0x05, 0x40, 0x04, 0xef, 0x30, 0x00, 0x2e, 0x13, 0x07, 0xa0, 0x0a, 0x2a, - 0x8d, 0xe3, 0x1c, 0xe5, 0xe6, 0x81, 0x45, 0x13, 0x05, 0x50, 0x04, 0xef, 0x30, 0xc0, 0x2c, 0xaa, 0x8c, 0xe3, 0x14, - 0xa5, 0xe7, 0x01, 0x45, 0xef, 0x20, 0x50, 0x49, 0x41, 0x46, 0x93, 0x05, 0x0a, 0x00, 0x01, 0x45, 0xef, 0x20, 0xf0, - 0x4b, 0x93, 0x07, 0xf0, 0x03, 0x63, 0xe3, 0xb7, 0x07, 0x93, 0x85, 0x0b, 0x01, 0x01, 0x45, 0x6e, 0x86, 0xef, 0x20, - 0xb0, 0x4a, 0xee, 0x85, 0x13, 0x05, 0x60, 0x04, 0xef, 0x30, 0x60, 0x29, 0xe3, 0x1a, 0x95, 0xe3, 0x81, 0x45, 0x13, - 0x05, 0xa0, 0x04, 0xef, 0x30, 0x80, 0x28, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x11, 0xf5, 0xe2, 0xef, 0x20, 0x10, 0x69, - 0x93, 0x07, 0x00, 0x05, 0x7c, 0xd8, 0x19, 0xb1, 0x13, 0x06, 0x00, 0x09, 0xea, 0x85, 0x01, 0x45, 0xef, 0x20, 0x30, - 0x47, 0x93, 0x05, 0x00, 0x09, 0x13, 0x05, 0x30, 0x04, 0xef, 0x30, 0xc0, 0x25, 0xfa, 0x75, 0xc0, 0xf6, 0xbb, 0x52, - 0x0a, 0x2a, 0xdc, 0x01, 0xf1, 0xee, 0xfb, 0x1b, 0xf3, 0x7a, 0x1d, 0x4d, 0x3b, 0xae, 0xcc, 0x74, 0x12, 0x28, 0xaf, - 0x96, 0x85, 0xf2, 0x67, 0xeb, 0xcf, 0x10, 0x52, 0xd8, 0x1f, 0x93, 0x06, 0xa0, 0x0a, 0xe3, 0x1b, 0xd5, 0xde, 0x93, - 0x8c, 0x0c, 0xf7, 0x13, 0x0d, 0x0d, 0x09, 0x81, 0xbf, 0x93, 0x85, 0x0b, 0x01, 0x01, 0x45, 0x13, 0x06, 0x00, 0x04, - 0xef, 0x20, 0x70, 0x44, 0x93, 0x05, 0x00, 0x04, 0x13, 0x05, 0x70, 0x04, 0xef, 0x30, 0x00, 0x23, 0xe3, 0x17, 0x95, - 0xdd, 0xb7, 0x0c, 0x20, 0x00, 0x13, 0x09, 0x09, 0xfa, 0x93, 0x8c, 0x0c, 0x05, 0x93, 0x0d, 0x00, 0x08, 0x93, 0x0b, - 0xa0, 0x0a, 0x63, 0xe1, 0x2d, 0x03, 0x4a, 0x86, 0xe6, 0x85, 0x01, 0x45, 0xef, 0x20, 0x50, 0x41, 0xca, 0x85, 0x13, - 0x05, 0x90, 0x04, 0xef, 0x30, 0x00, 0x20, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1d, 0xf5, 0xd8, 0x9d, 0xb7, 0xe6, 0x85, - 0x01, 0x45, 0x13, 0x06, 0x00, 0x08, 0xef, 0x20, 0x50, 0x3f, 0x93, 0x05, 0x00, 0x08, 0x13, 0x05, 0x80, 0x04, 0xef, - 0x30, 0xe0, 0x1d, 0xe3, 0x1e, 0x75, 0xd7, 0x13, 0x09, 0x09, 0xf8, 0x93, 0x8c, 0x0c, 0x08, 0x6d, 0xbf, 0x21, 0x47, - 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x9f, 0xeb, 0xb4, 0x03, 0x44, 0x1d, 0x00, 0xbd, 0x47, 0xe3, 0xef, 0x87, 0xd4, 0x83, - 0x2c, 0x4d, 0x00, 0xfd, 0x57, 0xe3, 0x8a, 0xfc, 0xd4, 0x13, 0x19, 0xa4, 0x00, 0x13, 0x05, 0x09, 0x40, 0xef, 0xe0, - 0x4f, 0xe1, 0x13, 0x07, 0xa0, 0x0a, 0xaa, 0x8b, 0xe3, 0x1f, 0xe5, 0xd2, 0x13, 0x09, 0x09, 0x20, 0x4a, 0x85, 0xef, - 0xe0, 0x0f, 0xe0, 0xaa, 0x8d, 0xe3, 0x17, 0x75, 0xd3, 0xe6, 0x85, 0x4a, 0x85, 0xef, 0x10, 0x20, 0x17, 0xfa, 0xcc, - 0x39, 0x15, 0x60, 0xa6, 0x46, 0x3e, 0xc1, 0xd1, 0x79, 0x47, 0xc8, 0x9b, 0xd6, 0x75, 0x4b, 0x47, 0x01, 0xf1, 0x2a, - 0xc2, 0x5b, 0x50, 0xb8, 0xf6, 0x1f, 0xc9, 0xaf, 0xc8, 0x40, 0x80, 0xf6, 0xb0, 0x20, 0xe3, 0x11, 0xb5, 0xd3, 0x37, - 0x37, 0x20, 0x00, 0x13, 0x07, 0x07, 0xf6, 0x85, 0x47, 0x33, 0x94, 0x87, 0x00, 0x1c, 0x43, 0x5d, 0x8c, 0x00, 0xc3, - 0xf5, 0xbc, 0x0d, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x9c, 0xeb, 0xae, 0x83, 0x45, 0x1d, 0x00, 0xbd, 0x47, 0xe3, - 0xec, 0xb7, 0xce, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xf6, 0xd1, 0x4c, 0xb3, 0xd7, 0xb7, 0x00, 0x85, 0x8b, - 0xe3, 0x8d, 0x07, 0xac, 0x37, 0x15, 0x20, 0x00, 0x13, 0x05, 0x05, 0x08, 0xef, 0xe0, 0x2f, 0xe6, 0x85, 0x47, 0xe3, - 0x0c, 0xf5, 0xba, 0x89, 0x47, 0xe3, 0x01, 0xf5, 0xac, 0xe1, 0xb1, 0x93, 0x0c, 0x00, 0x08, 0x65, 0xbc, 0xef, 0x10, - 0x70, 0x46, 0xef, 0xe0, 0xef, 0xd2, 0x6f, 0xf0, 0x8f, 0xef, 0xef, 0x00, 0xc0, 0x6f, 0x6f, 0xf0, 0x8f, 0xef, 0xef, - 0x00, 0x30, 0x4b, 0x93, 0x0b, 0x09, 0xff, 0xaa, 0x86, 0x63, 0x0f, 0x05, 0xf2, 0x8d, 0x45, 0x13, 0x85, 0x8d, 0x53, - 0x36, 0xce, 0x69, 0x24, 0xf2, 0x46, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0x86, 0x5c, 0x93, 0x85, 0x8d, 0x53, 0x13, - 0x85, 0x89, 0x77, 0x01, 0x24, 0xf2, 0x46, 0x09, 0x46, 0x05, 0x47, 0x63, 0x83, 0xc6, 0x00, 0x09, 0x47, 0x83, 0x46, - 0x84, 0x07, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0xa3, 0x0c, 0xe4, 0x06, 0x13, 0x06, 0x86, 0x5e, 0x5e, - 0x87, 0x93, 0x85, 0xc5, 0x56, 0x13, 0x85, 0x89, 0x77, 0xd1, 0x2a, 0xef, 0xe0, 0xcf, 0xc8, 0xef, 0xe0, 0xcf, 0xf9, - 0x62, 0x47, 0xfa, 0x57, 0x37, 0xf4, 0x3b, 0x81, 0x8a, 0x45, 0x6e, 0xf0, 0xcd, 0x0d, 0x91, 0x60, 0xbb, 0x72, 0x97, - 0xc3, 0xe6, 0x19, 0xa8, 0xa5, 0x11, 0x07, 0x3a, 0x66, 0x13, 0x37, 0x87, 0x58, 0x95, 0xb8, 0x83, 0x88, 0x21, 0x85, - 0x47, 0x23, 0x00, 0xf7, 0x00, 0xef, 0x00, 0xc0, 0x5a, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0x63, 0x1f, 0xf5, 0xdc, - 0x1d, 0x29, 0x2a, 0x84, 0x63, 0x1b, 0x25, 0xdd, 0xef, 0x30, 0xc0, 0x1a, 0x63, 0x17, 0x85, 0xdc, 0xb7, 0x37, 0x20, - 0x00, 0x83, 0xa7, 0x87, 0xf5, 0xb1, 0xeb, 0x83, 0x27, 0x4b, 0x07, 0x13, 0x07, 0xfc, 0x00, 0xfd, 0x17, 0x63, 0x64, - 0xf7, 0x04, 0x05, 0x45, 0xef, 0x20, 0xf0, 0x23, 0x03, 0x26, 0x4b, 0x07, 0x37, 0x09, 0x20, 0x00, 0x93, 0x05, 0x09, - 0x00, 0x13, 0x05, 0x09, 0x00, 0xef, 0x20, 0x10, 0x34, 0x37, 0x14, 0x20, 0x00, 0x13, 0x05, 0x04, 0x02, 0xef, 0x20, - 0xd0, 0x42, 0x03, 0x25, 0x4b, 0x07, 0x93, 0x07, 0x09, 0x00, 0x41, 0x46, 0x3e, 0x95, 0x93, 0x05, 0x04, 0x02, 0xef, - 0x30, 0x40, 0x6e, 0x83, 0x27, 0x4b, 0x07, 0xc1, 0x07, 0x23, 0x2a, 0xfb, 0x06, 0xef, 0x00, 0x70, 0x1e, 0x13, 0x04, - 0xa0, 0x0a, 0x63, 0x03, 0x85, 0xd6, 0xef, 0xe0, 0x5f, 0xa2, 0x63, 0x1f, 0x85, 0xd4, 0x37, 0x56, 0x10, 0x00, 0xb7, - 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x60, 0x93, 0x85, 0xc5, 0x56, 0x13, 0x05, 0x45, 0x57, - 0x31, 0x2a, 0xef, 0xe0, 0xaf, 0xb0, 0xef, 0x20, 0x50, 0x41, 0xef, 0x00, 0xd0, 0x36, 0xef, 0x00, 0xd0, 0x2d, 0xef, - 0xe0, 0x4f, 0xf3, 0x6f, 0xf0, 0xcf, 0xd2, 0x2a, 0x87, 0x81, 0x47, 0x01, 0x45, 0x63, 0x93, 0xc7, 0x00, 0x82, 0x80, - 0xb3, 0x06, 0xf7, 0x00, 0x33, 0x88, 0xfa, 0x5f, 0xcd, 0x6c, 0xbf, 0xbc, 0x78, 0x9d, 0xb4, 0xf3, 0xa4, 0xbd, 0x69, - 0xec, 0x25, 0x6b, 0x9c, 0xa5, 0x3b, 0xe9, 0xc0, 0x30, 0x80, 0x75, 0x8b, 0x9c, 0x82, 0x87, 0xc4, 0xa7, 0xbf, 0x17, - 0xa1, 0x60, 0x22, 0xf5, 0x00, 0x83, 0xc6, 0x06, 0x00, 0x03, 0x48, 0x08, 0x00, 0x85, 0x07, 0xb3, 0xc6, 0x06, 0x01, - 0x55, 0x8d, 0x13, 0x75, 0xf5, 0x0f, 0xf9, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x37, 0x37, 0x20, 0x00, 0x03, 0xa8, 0x87, - 0xf6, 0x83, 0x27, 0x47, 0xf6, 0xaa, 0x86, 0x13, 0x07, 0x47, 0xf6, 0x01, 0x45, 0x63, 0x13, 0xf8, 0x00, 0x82, 0x80, - 0x37, 0x26, 0x20, 0x00, 0x13, 0x06, 0xc6, 0x08, 0x93, 0x08, 0xf0, 0x7f, 0x63, 0x01, 0xb5, 0x02, 0x33, 0x0e, 0xf6, - 0x00, 0x03, 0x4e, 0x0e, 0x00, 0x05, 0x05, 0x33, 0x83, 0xa6, 0x00, 0xa3, 0x0f, 0xc3, 0xff, 0x85, 0x07, 0x63, 0xf3, - 0xf8, 0x00, 0x81, 0x47, 0xe3, 0x11, 0xf8, 0xfe, 0x1c, 0xc3, 0x82, 0x80, 0x93, 0x07, 0xf0, 0x7f, 0x63, 0xe5, 0xa7, - 0x02, 0xb7, 0x36, 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x86, 0x46, 0xf6, 0x83, 0xa7, 0x87, 0xf6, 0x98, 0x42, - 0x33, 0x87, 0xe7, 0x40, 0x13, 0x77, 0xf7, 0x7f, 0x63, 0x76, 0xe5, 0x00, 0x89, 0x8f, 0x93, 0xf7, 0xf7, 0x7f, 0x9c, - 0xc2, 0x82, 0x80, 0xb7, 0x36, 0x20, 0x00, 0x03, 0xa8, 0x86, 0xf6, 0x13, 0x07, 0xf0, 0x7f, 0x13, 0x86, 0x86, 0xf6, - 0x93, 0x07, 0x18, 0x00, 0x63, 0x73, 0xf7, 0x00, 0x81, 0x47, 0xb7, 0x36, 0x20, 0x00, 0x83, 0xa8, 0x46, 0xf6, 0x37, - 0x27, 0x20, 0x00, 0x93, 0x85, 0x46, 0xf6, 0x13, 0x07, 0xc7, 0x08, 0x63, 0x9f, 0xf8, 0x00, 0x93, 0x88, 0x17, 0x80, - 0x93, 0x86, 0x17, 0x00, 0x63, 0x93, 0x08, 0x00, 0x81, 0x46, 0xfa, 0xec, 0xae, 0x52, 0x4e, 0x3a, 0xe5, 0xee, 0xa8, - 0x62, 0x06, 0x5f, 0x13, 0x3c, 0x1b, 0x5d, 0x82, 0x5a, 0x18, 0xdd, 0xb7, 0x69, 0x5c, 0x0d, 0xc9, 0x72, 0xd7, 0xda, - 0x51, 0x19, 0x3c, 0x77, 0x32, 0x38, 0x23, 0x94, 0xc1, 0xba, 0x96, 0x93, 0x05, 0xa0, 0x02, 0x23, 0x80, 0xb6, 0x00, - 0x42, 0x97, 0x23, 0x00, 0xa7, 0x00, 0x1c, 0xc2, 0x82, 0x80, 0x82, 0x80, 0x39, 0x71, 0x22, 0xcc, 0x26, 0xca, 0x4a, - 0xc8, 0x06, 0xce, 0x36, 0xd6, 0x3a, 0xd8, 0x3e, 0xda, 0x42, 0xdc, 0x46, 0xde, 0xaa, 0x84, 0x2e, 0x89, 0x32, 0x84, - 0x19, 0xe1, 0xef, 0xe0, 0x6f, 0xfd, 0x63, 0x14, 0x09, 0x00, 0xef, 0xe0, 0xef, 0xfc, 0x19, 0xe0, 0xef, 0xe0, 0x8f, - 0xfc, 0x7c, 0x10, 0x3e, 0xc6, 0xef, 0x30, 0x40, 0x21, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x73, - 0xef, 0x30, 0x40, 0x46, 0x37, 0x55, 0x10, 0x00, 0x4a, 0x86, 0xa6, 0x85, 0x13, 0x05, 0x45, 0x74, 0xef, 0x30, 0x40, - 0x45, 0xb2, 0x45, 0x22, 0x85, 0xef, 0x30, 0xa0, 0x41, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x05, 0x75, 0xef, 0x30, - 0x00, 0x44, 0xb9, 0x29, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0x21, 0x61, 0x82, 0x80, 0xae, 0x86, 0x37, - 0x56, 0x10, 0x00, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0x46, 0x5e, 0x13, 0x05, 0x45, 0x75, 0x9d, 0xbf, - 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, 0x83, 0xa6, 0x47, 0x10, 0x63, 0x7e, 0xd7, - 0x00, 0x0a, 0x07, 0x3e, 0x97, 0x18, 0x43, 0x18, 0xc1, 0x03, 0xa7, 0x07, 0x10, 0x13, 0x05, 0xa0, 0x0a, 0x05, 0x07, - 0x23, 0xa0, 0xe7, 0x10, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, 0xfa, 0xb9, 0x54, 0x2d, 0xce, - 0x33, 0xa4, 0x18, 0x9b, 0xd2, 0x68, 0xf4, 0xba, 0x6f, 0x38, 0x40, 0x92, 0x18, 0x9e, 0x71, 0x02, 0xd5, 0xcd, 0xb2, - 0xba, 0x58, 0xce, 0x29, 0x89, 0x4c, 0xf8, 0xe9, 0x66, 0x10, 0x24, 0x26, 0xca, 0xb7, 0x34, 0x20, 0x00, 0x83, 0xa7, - 0xc4, 0xf6, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x11, 0x47, 0x63, 0x6f, 0xf7, 0x0c, 0x37, - 0x57, 0x10, 0x00, 0x8a, 0x07, 0x13, 0x07, 0xc7, 0x77, 0xba, 0x97, 0x9c, 0x43, 0x2a, 0x84, 0x93, 0x84, 0xc4, 0xf6, - 0x82, 0x87, 0x81, 0x45, 0xef, 0x30, 0x40, 0x3f, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x98, 0xa7, 0xf6, 0xb7, 0x37, 0x20, - 0x00, 0x23, 0x86, 0x87, 0x88, 0xef, 0x20, 0x50, 0x73, 0x9c, 0x40, 0x85, 0x07, 0x81, 0xa8, 0xb7, 0x37, 0x20, 0x00, - 0x23, 0xaa, 0x07, 0xf6, 0x93, 0x07, 0xc0, 0x0f, 0x63, 0xf1, 0xa7, 0x02, 0x62, 0x44, 0x9d, 0x47, 0xf2, 0x40, 0x42, - 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x9c, 0xc0, 0xd2, 0x44, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x85, 0x75, - 0x05, 0x61, 0x2d, 0xbf, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x09, 0xf7, 0x83, 0x55, 0x09, 0x00, 0xef, 0x30, 0xc0, - 0x39, 0xb7, 0x37, 0x20, 0x00, 0xa3, 0x86, 0x87, 0x88, 0x23, 0x10, 0xa9, 0x00, 0x8d, 0x47, 0x5d, 0xf4, 0x9c, 0xc0, - 0x91, 0xa8, 0x37, 0x39, 0x20, 0x00, 0x03, 0x27, 0x49, 0xf7, 0x93, 0x07, 0xb0, 0x0f, 0x13, 0x09, 0x49, 0xf7, 0x63, - 0xf4, 0xe7, 0x00, 0xef, 0xe0, 0xcf, 0xe7, 0x83, 0x27, 0x09, 0x00, 0x37, 0x3a, 0x20, 0x00, 0x13, 0x0a, 0x0a, 0xf7, - 0xb7, 0x39, 0x20, 0x00, 0x93, 0x89, 0xc9, 0x88, 0x83, 0x55, 0x0a, 0x00, 0xce, 0x97, 0x23, 0x81, 0x87, 0x00, 0xfa, - 0x48, 0x91, 0x30, 0x2d, 0xf7, 0xb3, 0x47, 0x07, 0x80, 0x40, 0xde, 0xe7, 0x4a, 0xf1, 0xbc, 0x19, 0x65, 0x02, 0x62, - 0x8a, 0xc3, 0x18, 0xdd, 0xd2, 0x79, 0xc9, 0x21, 0x2b, 0xdf, 0x80, 0x93, 0xe3, 0xe8, 0x24, 0x22, 0x85, 0xef, 0x30, - 0xc0, 0x34, 0x83, 0x27, 0x09, 0x00, 0x03, 0xc7, 0x19, 0x00, 0x23, 0x10, 0xaa, 0x00, 0x85, 0x07, 0x23, 0x20, 0xf9, - 0x00, 0xe3, 0xfd, 0xe7, 0xf4, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, - 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x99, 0xa7, 0xf6, 0x3d, 0xbf, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x29, - 0xf7, 0x13, 0x14, 0x85, 0x00, 0xb7, 0x39, 0x20, 0x00, 0x03, 0x55, 0x09, 0x00, 0x93, 0x89, 0x09, 0xf7, 0x83, 0xd7, - 0x09, 0x00, 0x49, 0x8c, 0x23, 0x10, 0x89, 0x00, 0xe3, 0x8d, 0x87, 0xf0, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0x84, - 0x75, 0x99, 0x47, 0x89, 0x45, 0x9c, 0xc0, 0x95, 0x3d, 0x93, 0x05, 0x84, 0x75, 0x62, 0x44, 0x03, 0xd7, 0x09, 0x00, - 0x83, 0x56, 0x09, 0x00, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x37, 0x56, 0x10, 0x00, 0x37, - 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x75, 0x13, 0x05, 0x85, 0x77, 0x05, 0x61, 0x6f, 0xf0, 0x3f, 0xdd, 0xb7, 0x37, - 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0xb7, 0x25, 0x10, 0x00, 0x37, 0x25, 0x10, 0x00, 0x23, 0xa0, 0x07, 0x10, 0x23, - 0xa2, 0x07, 0x10, 0x93, 0x85, 0xc5, 0xfd, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x05, 0xe5, 0x00, 0x23, 0xa6, 0x07, 0xf6, - 0x6f, 0x20, 0x70, 0x55, 0x11, 0xed, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0xef, 0xe0, 0xcf, 0xd8, 0x32, 0x45, 0xf2, - 0x40, 0x13, 0x06, 0xfa, 0x21, 0xd9, 0xfb, 0xde, 0x39, 0xa5, 0x32, 0x7f, 0x30, 0xad, 0x62, 0x53, 0xc9, 0x4e, 0x61, - 0x3e, 0xe2, 0xd3, 0x58, 0x70, 0xd0, 0x02, 0xd9, 0xd0, 0x95, 0x74, 0xec, 0xf5, 0x97, 0x14, 0x4f, 0x92, 0xc0, 0x25, - 0xe0, 0x0f, 0x81, 0x45, 0x05, 0x61, 0x6f, 0x30, 0x40, 0x35, 0x13, 0x06, 0xe0, 0x0f, 0x81, 0x45, 0xdd, 0xbf, 0xb7, - 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, 0xf6, 0x13, 0x05, 0xa0, 0x0a, 0x99, 0xc3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, - 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0xc4, 0xf6, 0x1c, 0x40, 0x06, 0xc6, 0x15, 0x47, 0x63, - 0x98, 0xe7, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x81, 0xe7, 0x13, 0x05, - 0x50, 0x05, 0xcd, 0xbf, 0xef, 0x20, 0x10, 0x54, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x19, 0xf5, 0xfe, 0x01, 0x00, 0x18, - 0x40, 0x91, 0x47, 0xe3, 0xcd, 0xe7, 0xfc, 0x99, 0x47, 0x1c, 0xc0, 0xd9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x20, - 0x90, 0x53, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xf5, 0x00, 0xef, 0x20, 0xf0, 0x54, 0xb7, 0x37, 0x20, 0x00, 0x03, - 0xa7, 0xc7, 0xf6, 0x95, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, - 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0xc7, 0xf6, 0x99, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, - 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0xc7, 0xf6, 0x9d, 0x47, - 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x37, 0x35, 0x20, 0x00, 0x13, - 0x05, 0xc5, 0x88, 0x82, 0x80, 0x01, 0x11, 0xfa, 0xa3, 0x00, 0x28, 0x5f, 0xca, 0x25, 0x1f, 0xec, 0x1a, 0x16, 0x2f, - 0xc2, 0x42, 0x21, 0xe2, 0xa0, 0x8f, 0x58, 0x40, 0xca, 0xfd, 0x04, 0x39, 0x89, 0x4a, 0xfb, 0xad, 0xf9, 0x66, 0x02, - 0x4b, 0xb9, 0x98, 0x26, 0x26, 0xca, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0xaa, 0x84, 0x19, 0xe1, 0xef, - 0xe0, 0xcf, 0xc9, 0x83, 0xc7, 0x14, 0x00, 0x13, 0x07, 0xc0, 0x0f, 0x13, 0x05, 0x50, 0x05, 0x63, 0x65, 0xf7, 0x06, - 0x37, 0x39, 0x20, 0x00, 0x13, 0x04, 0xc9, 0x98, 0x23, 0x20, 0x04, 0x10, 0x03, 0xc7, 0x04, 0x00, 0xa3, 0x00, 0xf4, - 0x00, 0x03, 0xc6, 0x14, 0x00, 0x23, 0x00, 0xe4, 0x00, 0x93, 0x85, 0x24, 0x00, 0x13, 0x05, 0x24, 0x00, 0xef, 0x30, - 0x00, 0x20, 0x83, 0xc9, 0x14, 0x00, 0x13, 0x05, 0xc9, 0x98, 0x13, 0x09, 0xc9, 0x98, 0x93, 0x84, 0x29, 0x00, 0xa6, - 0x85, 0xef, 0x30, 0x80, 0x16, 0xa2, 0x94, 0x23, 0x80, 0xa4, 0x00, 0x4e, 0x94, 0x21, 0x81, 0x93, 0x87, 0x49, 0x00, - 0xa3, 0x01, 0xa4, 0x00, 0xfd, 0x56, 0x13, 0xf7, 0x37, 0x00, 0x19, 0xef, 0x89, 0x83, 0x23, 0x22, 0xf9, 0x10, 0xef, - 0x20, 0x30, 0x49, 0x13, 0x05, 0xa0, 0x0a, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, - 0x82, 0x80, 0x33, 0x07, 0xf9, 0x00, 0x23, 0x00, 0xd7, 0x00, 0x85, 0x07, 0xd1, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x93, - 0x87, 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, 0x83, 0xa7, 0x47, 0x10, 0x63, 0x14, 0xf7, 0x00, 0x6f, 0x20, 0xb0, 0x41, - 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa6, 0x07, 0xf6, 0x82, 0x80, 0x41, 0x11, 0x06, - 0xc6, 0x93, 0x07, 0x00, 0x08, 0x73, 0xa0, 0x47, 0x30, 0x93, 0x06, 0xfa, 0xfe, 0xc7, 0x49, 0x54, 0x80, 0xb7, 0x8b, - 0x81, 0x3f, 0x08, 0xfb, 0x59, 0x05, 0x42, 0x07, 0x1c, 0x3c, 0x34, 0x71, 0xae, 0x7f, 0x67, 0xc4, 0x98, 0x29, 0x50, - 0x3b, 0x48, 0x1e, 0xe3, 0x83, 0x5b, 0x70, 0x27, 0x70, 0x3e, 0x09, 0x46, 0x93, 0x05, 0x60, 0x04, 0x37, 0x05, 0x10, - 0x01, 0xef, 0x20, 0xf0, 0x59, 0x8d, 0x45, 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, 0xf0, 0x5d, 0x37, 0x05, 0x10, 0x01, - 0xef, 0x20, 0x70, 0x53, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0xb0, 0x55, 0xfd, 0x56, 0x01, 0x46, 0x93, 0x05, 0x60, - 0x04, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x50, 0x57, 0xb2, 0x40, 0xb7, 0x07, 0x20, 0x01, 0x23, 0xac, 0x07, 0x00, - 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x89, 0x2c, 0xb2, 0x40, 0x41, 0x01, 0x45, 0xb7, 0x41, 0x11, 0x22, - 0xc4, 0xb7, 0x07, 0x20, 0x01, 0x06, 0xc6, 0x23, 0xac, 0x07, 0x00, 0x2a, 0x84, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, - 0xd0, 0x4e, 0x93, 0x07, 0x80, 0x3e, 0x13, 0x05, 0x80, 0x3e, 0x63, 0xe3, 0x87, 0x00, 0x22, 0x85, 0xb7, 0x07, 0x20, - 0x01, 0x98, 0x4f, 0x13, 0x84, 0x87, 0x01, 0xe3, 0x6d, 0xa7, 0xfe, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x50, 0x4f, - 0xb2, 0x40, 0x23, 0x20, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x11, 0xe1, 0x82, 0x80, 0x01, 0x00, 0x7d, - 0x15, 0xe5, 0xbf, 0x6f, 0xf0, 0x9f, 0xb3, 0x29, 0xa4, 0x01, 0x11, 0x26, 0xca, 0xaa, 0x84, 0x37, 0x05, 0x20, 0x01, - 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x56, 0xc2, 0x06, 0xce, 0x22, 0xcc, 0x2e, 0x89, 0x93, 0x09, 0xa0, 0x0a, 0xef, - 0x20, 0xd0, 0x48, 0x37, 0x0a, 0x20, 0x01, 0x93, 0x0a, 0x80, 0x3e, 0x82, 0x94, 0x2a, 0x84, 0xfa, 0xa5, 0x11, 0x96, - 0x8a, 0x77, 0x48, 0x86, 0x75, 0x28, 0xdb, 0x6f, 0x4d, 0xf2, 0x67, 0xcd, 0x0c, 0xfe, 0xd2, 0xa4, 0x19, 0x55, 0x6f, - 0xbc, 0x12, 0x6c, 0x23, 0x5f, 0xa1, 0x35, 0xa6, 0x77, 0x0c, 0x48, 0x28, 0x63, 0x0c, 0x35, 0x03, 0x83, 0x27, 0x8a, - 0x01, 0x63, 0x7a, 0xf9, 0x04, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0x04, 0x79, 0x85, 0x45, 0xef, 0xf0, 0x9f, 0xb6, - 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0x05, 0x04, 0x79, 0xa6, 0x86, 0x13, 0x06, 0x46, 0x79, 0x13, - 0x05, 0x85, 0x77, 0xef, 0xf0, 0x9f, 0xad, 0x13, 0x04, 0x50, 0x05, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0xd0, 0x46, - 0xf2, 0x40, 0x22, 0x85, 0x62, 0x44, 0xb7, 0x07, 0x20, 0x01, 0x23, 0xac, 0x07, 0x00, 0xd2, 0x44, 0x42, 0x49, 0xb2, - 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xe3, 0xf0, 0x2a, 0xfb, 0xb5, 0x2a, 0x69, 0xbf, 0x37, 0x07, - 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x87, 0x00, 0x1c, 0xc7, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x26, - 0xc2, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0xcf, 0xa7, 0xa9, 0x44, 0x03, 0x45, 0x04, 0x00, 0x11, 0xe5, 0xb2, 0x40, - 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xef, 0xf0, 0xdf, 0xa1, 0x83, 0x47, 0x04, 0x00, 0x63, 0x94, 0x97, - 0x00, 0xef, 0xf0, 0x7f, 0xa6, 0x05, 0x04, 0xf9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0x25, 0x37, 0x93, 0x07, 0xa0, 0x0a, - 0x63, 0x05, 0xf5, 0x00, 0xef, 0xe0, 0x4f, 0xa4, 0x01, 0xa0, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, - 0xc4, 0x37, 0x44, 0x20, 0x00, 0x13, 0x06, 0xc0, 0x1f, 0x81, 0x45, 0x13, 0x05, 0x04, 0xe0, 0x06, 0xc6, 0x26, 0xc2, - 0xfa, 0xa4, 0xf8, 0x32, 0x4a, 0x9e, 0x77, 0xb7, 0xe1, 0x38, 0xfa, 0x5f, 0xfa, 0x8b, 0x90, 0xe4, 0xd5, 0x46, 0x8b, - 0xf8, 0xa5, 0x00, 0x3d, 0x29, 0x18, 0x6a, 0x41, 0x5d, 0x62, 0xc6, 0xcd, 0xb3, 0xec, 0x20, 0x29, 0xef, 0x20, 0xb0, - 0x7f, 0x13, 0x05, 0x04, 0xe0, 0x93, 0x05, 0xc0, 0x1f, 0xef, 0x20, 0x30, 0x76, 0x93, 0x04, 0x04, 0xe0, 0xb2, 0x40, - 0x22, 0x44, 0x23, 0xae, 0xa4, 0x1e, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x37, 0x45, 0x20, 0x00, 0x22, - 0xc4, 0x93, 0x05, 0xc0, 0x1f, 0x13, 0x04, 0x05, 0xe0, 0x13, 0x05, 0x05, 0xe0, 0x06, 0xc6, 0xef, 0x20, 0x70, 0x73, - 0x03, 0x27, 0xc4, 0x1f, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xa7, 0x00, 0x93, 0x07, 0x50, 0x05, 0xb2, 0x40, 0x22, - 0x44, 0x3e, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, 0xaa, 0x87, 0x63, 0x6e, 0xa7, 0x00, 0x13, 0x77, - 0x35, 0x00, 0x01, 0x45, 0x11, 0xeb, 0x37, 0x45, 0x20, 0x00, 0x13, 0x05, 0x05, 0xe0, 0xf1, 0x9b, 0xaa, 0x97, 0x88, - 0x43, 0x82, 0x80, 0x01, 0x45, 0x82, 0x80, 0x93, 0x07, 0xb0, 0x1f, 0x63, 0xec, 0xa7, 0x00, 0x93, 0x77, 0x35, 0x00, - 0x81, 0xeb, 0xb7, 0x47, 0x20, 0x00, 0x71, 0x99, 0x93, 0x87, 0x07, 0xe0, 0x3e, 0x95, 0x0c, 0xc1, 0x82, 0x80, 0x41, - 0x11, 0x37, 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, 0xc0, 0x1f, 0x13, 0x04, 0x05, 0xe0, 0x13, 0x05, 0x05, 0xe0, - 0x06, 0xc6, 0xef, 0x20, 0xf0, 0x6b, 0xb2, 0x40, 0x23, 0x2e, 0xa4, 0x1e, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, - 0x07, 0xb0, 0x1f, 0x63, 0x61, 0xa7, 0x02, 0x93, 0x77, 0x35, 0x00, 0x13, 0x07, 0x50, 0x05, 0x89, 0xef, 0x41, 0x11, - 0x06, 0xc6, 0x5d, 0x37, 0xfa, 0xdd, 0x63, 0x5d, 0xa7, 0x30, 0xd2, 0xe2, 0xb5, 0xdb, 0x5f, 0x1b, 0xa0, 0xfa, 0x7e, - 0x57, 0xb2, 0x87, 0xe9, 0x27, 0xb4, 0x36, 0x63, 0x7a, 0x0e, 0x18, 0x08, 0xe0, 0x95, 0xf6, 0xf6, 0xf6, 0x19, 0xf8, - 0x29, 0xc9, 0x37, 0xb2, 0x40, 0x13, 0x07, 0xa0, 0x0a, 0x3a, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0x50, 0x05, - 0x3a, 0x85, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x00, 0x90, 0x6c, 0xef, 0x20, 0xe0, 0x5f, 0xb2, 0x40, 0x13, - 0x05, 0xa0, 0x0a, 0x41, 0x01, 0x82, 0x80, 0x73, 0x00, 0x50, 0x10, 0x82, 0x80, 0x3d, 0xce, 0x79, 0x71, 0x22, 0xd4, - 0x26, 0xd2, 0x4a, 0xd0, 0x06, 0xd6, 0x4e, 0xce, 0x52, 0xcc, 0x2a, 0x84, 0x2e, 0x89, 0xb2, 0x84, 0x19, 0xe1, 0xef, - 0xe0, 0x0f, 0x90, 0x93, 0x77, 0x39, 0x00, 0x99, 0xc3, 0xef, 0xe0, 0x6f, 0x8f, 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x87, - 0x34, 0x41, 0x33, 0x05, 0x34, 0x01, 0x63, 0x6c, 0xfa, 0x02, 0x13, 0xd6, 0x24, 0x00, 0xf1, 0x57, 0x33, 0x06, 0xf6, - 0x02, 0x93, 0xf5, 0xc4, 0xff, 0x33, 0x05, 0xb4, 0x00, 0x2e, 0x99, 0x26, 0x96, 0x19, 0xc6, 0x83, 0x27, 0x09, 0x00, - 0x6c, 0x00, 0x3e, 0xc6, 0xef, 0x20, 0xf0, 0x65, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, - 0x4a, 0x45, 0x61, 0x82, 0x80, 0xb3, 0x07, 0x39, 0x01, 0x9c, 0x43, 0x11, 0x46, 0x6c, 0x00, 0x3e, 0xc6, 0x91, 0x09, - 0xef, 0x20, 0xd0, 0x63, 0x7d, 0xb7, 0x82, 0x80, 0x3d, 0xce, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x06, - 0xd6, 0x4e, 0xce, 0x52, 0xcc, 0x2a, 0x84, 0x2e, 0x89, 0xb2, 0x84, 0x99, 0xe1, 0xef, 0xe0, 0x0f, 0x88, 0x93, 0x77, - 0x34, 0x00, 0x99, 0xc3, 0xef, 0xe0, 0x6f, 0x87, 0xfa, 0x4d, 0xf2, 0x04, 0xc7, 0x00, 0x6b, 0x20, 0x73, 0xff, 0xea, - 0xf6, 0xcf, 0x31, 0xa8, 0xed, 0x98, 0xd9, 0x58, 0xf2, 0x3f, 0x65, 0x63, 0x39, 0xca, 0x40, 0x62, 0x11, 0x13, 0x1e, - 0xdf, 0x75, 0x47, 0xd0, 0x2a, 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x87, 0x34, 0x41, 0xb3, 0x05, 0x39, 0x01, 0x63, 0x6c, - 0xfa, 0x02, 0x13, 0xd6, 0x24, 0x00, 0xf1, 0x57, 0x33, 0x06, 0xf6, 0x02, 0x93, 0xf5, 0xc4, 0xff, 0x2e, 0x94, 0xca, - 0x95, 0x26, 0x96, 0x01, 0xca, 0x1c, 0x40, 0x68, 0x00, 0x3e, 0xc6, 0xef, 0x20, 0x30, 0x5e, 0xb2, 0x47, 0x1c, 0xc0, - 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0x11, 0x46, 0x68, - 0x00, 0xef, 0x20, 0x70, 0x5c, 0x32, 0x47, 0xb3, 0x07, 0x34, 0x01, 0x91, 0x09, 0x98, 0xc3, 0x7d, 0xb7, 0x82, 0x80, - 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0xef, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x13, - 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf6, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa0, 0x87, 0xf8, 0xb7, 0x37, 0x20, 0x00, - 0x23, 0x8a, 0x07, 0xa8, 0xef, 0xf0, 0x9f, 0xb3, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xae, 0xa7, 0xf6, 0x19, 0xe1, 0xef, - 0xd0, 0x1f, 0xfe, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x7f, 0xa1, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, - 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xd0, 0x9f, 0xfc, 0x37, 0x35, 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0xa2, 0x85, 0x13, - 0x06, 0xe0, 0x0f, 0x13, 0x05, 0x45, 0xa9, 0x23, 0x8a, 0x07, 0xb8, 0xef, 0x20, 0xb0, 0x54, 0x22, 0x85, 0x22, 0x44, - 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x7f, 0xaf, 0x41, 0x11, 0x22, 0xc4, 0xfa, 0xba, 0x55, 0x8f, 0xa6, 0xa2, 0x00, - 0x3c, 0xce, 0x66, 0x23, 0xf8, 0xf5, 0x15, 0x4a, 0x90, 0x3a, 0x77, 0xde, 0xe3, 0xbe, 0xf6, 0x3b, 0x2a, 0xf8, 0x56, - 0x7d, 0xf9, 0x8a, 0x72, 0x0a, 0xd9, 0x6c, 0xa8, 0x2b, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xd0, - 0x3f, 0xf9, 0xb7, 0x34, 0x20, 0x00, 0x83, 0xc7, 0x44, 0xb9, 0x99, 0xcb, 0x37, 0x35, 0x20, 0x00, 0x13, 0x06, 0xe0, - 0x0f, 0x93, 0x85, 0x44, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0xef, 0x20, 0x10, 0x51, 0xa2, 0x85, 0x13, 0x85, 0x44, 0xb9, - 0x13, 0x06, 0xe0, 0x0f, 0xef, 0x20, 0x30, 0x50, 0x22, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x92, 0x44, 0x41, 0x01, 0x6f, - 0xf0, 0xdf, 0xaa, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x87, 0xf7, 0x82, 0x80, 0x37, 0x35, 0x20, 0x00, 0x83, 0x47, - 0x45, 0xa9, 0x85, 0xc3, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xc7, 0x47, 0xb9, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, - 0x07, 0xa0, 0x0a, 0x23, 0xac, 0xe7, 0xf6, 0x13, 0x05, 0x45, 0xa9, 0x6f, 0xf0, 0xbf, 0xa7, 0x13, 0x05, 0x50, 0x05, - 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x9f, 0x9a, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xf5, 0x00, 0x13, - 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x6d, 0x71, 0x23, 0x26, 0x11, 0x10, 0x23, 0x24, 0x81, 0x10, - 0x23, 0x22, 0x91, 0x10, 0xef, 0xf0, 0x9f, 0x99, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x02, 0x2a, 0x84, 0xef, - 0xf0, 0x1f, 0x9d, 0x63, 0x12, 0x85, 0x06, 0xb7, 0x37, 0x20, 0x00, 0x37, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xf8, - 0x03, 0x25, 0xc7, 0xf7, 0x82, 0x97, 0xef, 0xf0, 0x3f, 0xae, 0xef, 0xf0, 0x1f, 0xac, 0x93, 0x07, 0xfa, 0xa7, 0xd3, - 0x56, 0xdb, 0x3a, 0x0b, 0x96, 0x57, 0xf0, 0x41, 0x1c, 0xe2, 0x6f, 0xfd, 0xb6, 0xc2, 0x82, 0xc0, 0x93, 0x99, 0x1a, - 0x90, 0x8a, 0x09, 0x9f, 0xf0, 0x96, 0xe1, 0x27, 0x01, 0x2a, 0xc4, 0x80, 0x2c, 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x18, - 0xf5, 0x02, 0xef, 0xf0, 0xbf, 0x94, 0x63, 0x14, 0x85, 0x02, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x84, 0xf7, 0x04, - 0x40, 0xb7, 0x35, 0x20, 0x00, 0x63, 0x9c, 0xa4, 0x04, 0x13, 0x85, 0x45, 0xb9, 0xef, 0xf0, 0x1f, 0x9f, 0x63, 0x15, - 0x95, 0x00, 0x93, 0x07, 0x50, 0x05, 0x1c, 0xc0, 0x83, 0x20, 0xc1, 0x10, 0x03, 0x24, 0x81, 0x10, 0x83, 0x24, 0x41, - 0x10, 0x51, 0x61, 0x82, 0x80, 0xef, 0xf0, 0x9f, 0x99, 0x81, 0x44, 0x63, 0x14, 0x85, 0x00, 0x93, 0x04, 0xc0, 0x07, - 0xef, 0xf0, 0x3f, 0x9a, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0xc1, 0xdc, 0x0a, 0x85, 0x23, 0x00, 0x91, - 0x00, 0xa3, 0x00, 0x01, 0x00, 0xef, 0xf0, 0x7f, 0xe8, 0x61, 0xb7, 0x93, 0x04, 0xc0, 0x07, 0xf5, 0xb7, 0x83, 0xc7, - 0x45, 0xb9, 0xcd, 0xdf, 0x03, 0x24, 0x81, 0x10, 0x83, 0x20, 0xc1, 0x10, 0x83, 0x24, 0x41, 0x10, 0x37, 0x35, 0x20, - 0x00, 0x13, 0x06, 0xe0, 0x0f, 0x93, 0x85, 0x45, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0x51, 0x61, 0x6f, 0x20, 0x50, 0x3c, - 0xb7, 0x07, 0x01, 0x04, 0x23, 0xa2, 0x07, 0x00, 0x21, 0x65, 0x6f, 0x20, 0x80, 0x30, 0x41, 0x11, 0x21, 0x65, 0x06, - 0xc6, 0xef, 0x20, 0x20, 0x2f, 0xb2, 0x40, 0xb7, 0x07, 0x01, 0x04, 0x05, 0x47, 0xd8, 0xc3, 0x41, 0x01, 0x82, 0x80, - 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x07, 0x70, 0x02, 0x2a, 0x84, 0xae, 0x84, 0x63, 0xf4, 0xa7, - 0x00, 0xfa, 0x1e, 0xaf, 0x4b, 0x61, 0xd7, 0xa5, 0xaa, 0x9b, 0xb9, 0xac, 0x40, 0x4c, 0x11, 0x95, 0xbe, 0x8d, 0xce, - 0x06, 0xc5, 0x0d, 0x54, 0x0d, 0xeb, 0x31, 0xf0, 0x29, 0x42, 0x81, 0xfe, 0x09, 0x0d, 0x4b, 0x58, 0x2d, 0xef, 0xd0, - 0xbf, 0xde, 0x37, 0x05, 0x01, 0x04, 0x0a, 0x04, 0x13, 0x05, 0x05, 0x10, 0x2a, 0x94, 0x04, 0xc0, 0xb2, 0x40, 0x22, - 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x13, 0x87, 0x07, 0x10, 0x93, 0x87, 0x07, 0x1a, - 0x23, 0x20, 0x07, 0x00, 0x11, 0x07, 0xe3, 0x1d, 0xf7, 0xfe, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0xc8, 0xcb, 0x82, - 0x80, 0x42, 0x05, 0xb7, 0x07, 0x01, 0x04, 0xc8, 0xcb, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x88, 0x4b, 0x13, 0x75, - 0xf5, 0x0f, 0x82, 0x80, 0x89, 0x67, 0x37, 0x07, 0x01, 0x04, 0x8d, 0x07, 0x1c, 0xc7, 0x23, 0x2a, 0x07, 0x00, 0x82, - 0x80, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0x2a, 0x84, 0xad, 0x37, 0xb7, 0x07, 0x01, 0x04, 0x80, 0xcf, 0xc5, 0x37, - 0x65, 0x37, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xf4, 0xb7, 0x06, 0x01, 0x04, 0x9c, 0x46, 0x05, - 0x45, 0x13, 0xf7, 0x17, 0x00, 0x1d, 0xc7, 0x13, 0xf7, 0x07, 0x40, 0x0d, 0x45, 0x1d, 0xe3, 0x98, 0x4a, 0x13, 0x77, - 0xf7, 0x0f, 0x19, 0xcf, 0x13, 0xf7, 0x27, 0x20, 0x09, 0x45, 0x19, 0xeb, 0x13, 0xd7, 0xb7, 0x00, 0x05, 0x8b, 0x11, - 0x45, 0x11, 0xe7, 0x13, 0xd5, 0x87, 0x00, 0x13, 0x45, 0x15, 0x00, 0x05, 0x89, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, - 0x88, 0xcf, 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, 0x06, 0xce, 0x33, 0x07, 0xb6, 0x00, 0x93, 0x07, 0x00, 0x09, 0x2e, - 0x84, 0x63, 0xf8, 0xe7, 0x00, 0xfa, 0x54, 0x9e, 0x6f, 0x39, 0x78, 0xc7, 0x3b, 0x59, 0xb2, 0xc0, 0xb2, 0xb5, 0x84, - 0xfd, 0x3f, 0x5f, 0x4f, 0x3e, 0x32, 0x93, 0xdd, 0xd6, 0x0b, 0xe8, 0xb4, 0xff, 0xd8, 0x1f, 0xca, 0xba, 0xb5, 0xe5, - 0x30, 0x2e, 0x32, 0xc6, 0x2a, 0xc4, 0xef, 0xd0, 0xff, 0xd0, 0x32, 0x46, 0x22, 0x45, 0xb7, 0x15, 0x01, 0x04, 0xa2, - 0x95, 0xef, 0xf0, 0x9f, 0xbe, 0xf2, 0x40, 0x62, 0x44, 0x13, 0x05, 0xa0, 0x0a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, - 0x22, 0xcc, 0x26, 0xca, 0x06, 0xce, 0x33, 0x07, 0xb6, 0x00, 0x93, 0x07, 0x00, 0x08, 0xaa, 0x84, 0x2e, 0x84, 0x63, - 0xf6, 0xe7, 0x00, 0x32, 0xc6, 0xef, 0xd0, 0x7f, 0xcd, 0x32, 0x46, 0x37, 0x25, 0x01, 0x04, 0x13, 0x05, 0x05, 0x80, - 0x22, 0x95, 0x62, 0x44, 0xf2, 0x40, 0xa6, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x6f, 0xf0, 0x5f, 0xc2, 0x39, 0x71, 0x2a, - 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, - 0x06, 0x7a, 0x93, 0x85, 0x05, 0x7b, 0x13, 0x05, 0x45, 0x7b, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x36, - 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xf0, - 0xcf, 0xc8, 0xef, 0xe0, 0x8f, 0xd6, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, - 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, - 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x09, 0x65, 0x6f, 0x20, 0x00, 0x13, 0x09, 0x65, 0x6f, 0x20, 0x60, 0x13, 0x41, - 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xfa, 0x6d, 0x0d, 0x1b, 0x23, 0xf5, 0xbc, 0x94, 0xcb, 0xa7, - 0x29, 0x42, 0x08, 0x5d, 0xe1, 0xc1, 0xd6, 0x0e, 0xae, 0x35, 0x13, 0x3c, 0x44, 0x81, 0xbf, 0xec, 0xba, 0xaa, 0xaa, - 0x19, 0x1a, 0xe2, 0x9d, 0x08, 0x2f, 0xef, 0xd0, 0xbf, 0xc3, 0xdd, 0x37, 0xb7, 0x07, 0x00, 0x07, 0xd8, 0x43, 0x83, - 0x47, 0x64, 0x00, 0xbd, 0x46, 0x63, 0x85, 0xd7, 0x00, 0x61, 0x9b, 0x9d, 0x8b, 0x5d, 0x8f, 0x93, 0x77, 0x77, 0xff, - 0x03, 0x47, 0x74, 0x00, 0x83, 0x46, 0x44, 0x00, 0xb2, 0x40, 0x0e, 0x07, 0x21, 0x8b, 0x5d, 0x8f, 0xfd, 0x77, 0xbd, - 0x07, 0x7d, 0x8f, 0x83, 0x47, 0x84, 0x00, 0x92, 0x07, 0x5d, 0x8f, 0xb7, 0x17, 0x80, 0xff, 0xfd, 0x17, 0x7d, 0x8f, - 0x83, 0x47, 0x54, 0x00, 0xa2, 0x07, 0xd5, 0x8f, 0xb2, 0x07, 0xb7, 0xf6, 0x7f, 0x00, 0xf5, 0x8f, 0xd9, 0x8f, 0x37, - 0x07, 0x80, 0xf8, 0x7d, 0x17, 0xf9, 0x8f, 0x03, 0x47, 0xa4, 0x00, 0xb7, 0x06, 0x80, 0x07, 0x5e, 0x07, 0x75, 0x8f, - 0xd9, 0x8f, 0x37, 0x07, 0x00, 0x88, 0x7d, 0x17, 0xf9, 0x8f, 0x03, 0x47, 0x94, 0x00, 0xb7, 0x06, 0x00, 0x78, 0x22, - 0x44, 0x6e, 0x07, 0x75, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x00, 0x07, 0x5c, 0xc3, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, - 0x20, 0x00, 0x03, 0xa5, 0x87, 0xf8, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x13, 0x05, 0xa0, - 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, - 0x13, 0x05, 0xa0, 0x0a, 0x89, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x89, 0x65, 0x37, 0x35, 0x10, - 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0x85, 0xbb, 0x6f, 0xf0, 0x5f, 0x91, 0xfa, 0xd8, 0x14, 0xfd, 0xf8, 0x0c, - 0xee, 0xbc, 0x7c, 0xa1, 0x4e, 0xe7, 0x3e, 0x25, 0x21, 0xc1, 0xa4, 0x8e, 0x2a, 0x95, 0xb0, 0xa7, 0xb3, 0x44, 0xce, - 0xaf, 0x2b, 0x92, 0x0b, 0xb6, 0xa7, 0x93, 0x7e, 0xe0, 0x2f, 0x41, 0x11, 0xb7, 0x07, 0x08, 0x05, 0x22, 0xc4, 0x03, - 0xa4, 0xc7, 0x20, 0x37, 0x07, 0x00, 0x04, 0x06, 0xc6, 0x26, 0xc2, 0xb3, 0x76, 0xe4, 0x00, 0x91, 0xca, 0x37, 0x55, - 0x10, 0x00, 0x23, 0xa6, 0xe7, 0x20, 0xa5, 0x45, 0x13, 0x05, 0x85, 0x7b, 0xef, 0xf0, 0xef, 0xbb, 0xb7, 0x07, 0x80, - 0x6b, 0xe1, 0x8f, 0x95, 0xcb, 0x37, 0x07, 0x08, 0x05, 0x23, 0x26, 0xf7, 0x20, 0xb7, 0x07, 0x00, 0x68, 0x7d, 0x8c, - 0x93, 0x04, 0x50, 0x05, 0x11, 0xc8, 0x37, 0x55, 0x10, 0x00, 0x9d, 0x45, 0x13, 0x05, 0x85, 0x7b, 0xef, 0xf0, 0x4f, - 0xb9, 0xef, 0xd0, 0xdf, 0xb0, 0xb2, 0x40, 0x22, 0x44, 0x26, 0x85, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, - 0x20, 0x00, 0x93, 0x87, 0xc7, 0xf8, 0x84, 0x43, 0x13, 0x07, 0xa0, 0x0a, 0x63, 0x96, 0xe4, 0x00, 0x13, 0x07, 0x50, - 0x05, 0x98, 0xc3, 0xe1, 0xbf, 0x93, 0x04, 0xa0, 0x0a, 0xd9, 0xbf, 0x81, 0x47, 0xb7, 0x05, 0x08, 0x05, 0x13, 0x07, - 0x00, 0x20, 0xb3, 0x86, 0xb7, 0x00, 0x90, 0x42, 0xb3, 0x06, 0xf5, 0x00, 0x91, 0x07, 0x90, 0xc2, 0xe3, 0x99, 0xe7, - 0xfe, 0x6f, 0xf0, 0xff, 0xf5, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0x2a, 0x84, 0xef, 0xf0, 0x1f, 0xf4, 0xb7, 0x37, - 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa4, 0xe7, 0xf8, 0x8d, 0x47, 0x33, 0x95, 0x87, 0x00, 0xb7, 0xb7, 0xaa, - 0x02, 0x93, 0x87, 0xa7, 0xaa, 0x3d, 0x8d, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xa4, 0xa7, 0x20, 0x89, 0x65, 0xfa, 0x5e, - 0x6c, 0x07, 0xc8, 0xd2, 0x35, 0x1f, 0x8d, 0x20, 0x56, 0x9f, 0xda, 0x3e, 0xb1, 0xdd, 0xf7, 0x9b, 0x1b, 0xec, 0xc5, - 0x37, 0xc2, 0xa4, 0x0b, 0x96, 0xe2, 0x28, 0xf5, 0x1e, 0xf0, 0x78, 0x16, 0xb8, 0x30, 0x37, 0x35, 0x10, 0x00, 0x93, - 0x85, 0x05, 0x71, 0x13, 0x05, 0x85, 0xb9, 0xef, 0xf0, 0xdf, 0x82, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, - 0x3f, 0xf1, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x9f, 0xef, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf8, 0x37, - 0x07, 0x08, 0x05, 0x13, 0x05, 0x00, 0x20, 0xf9, 0x9b, 0x23, 0x22, 0xf7, 0x20, 0xef, 0x10, 0x10, 0x74, 0xb2, 0x40, - 0x39, 0x45, 0x41, 0x01, 0x6f, 0x10, 0x30, 0x75, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf8, 0x1c, 0x43, 0x93, - 0xf7, 0xf7, 0xfd, 0x1c, 0xc3, 0x37, 0x07, 0x08, 0x05, 0x23, 0x22, 0xf7, 0x20, 0x82, 0x80, 0x37, 0x37, 0x20, 0x00, - 0x13, 0x07, 0x47, 0xf8, 0x1c, 0x43, 0x93, 0xe7, 0x07, 0x02, 0x1c, 0xc3, 0x37, 0x07, 0x08, 0x05, 0x23, 0x22, 0xf7, - 0x20, 0x82, 0x80, 0x33, 0x87, 0xc5, 0x00, 0xb7, 0x07, 0x08, 0x00, 0x63, 0x7c, 0xf7, 0x06, 0x01, 0x11, 0x22, 0xcc, - 0x26, 0xca, 0x4e, 0xc6, 0x06, 0xce, 0x4a, 0xc8, 0x93, 0xf4, 0x35, 0x00, 0xaa, 0x89, 0x2e, 0x84, 0x13, 0x05, 0x50, - 0x05, 0x9d, 0xec, 0x32, 0x89, 0xef, 0xf0, 0x5f, 0xe7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x47, 0xf8, 0xb7, 0x06, - 0x08, 0x05, 0xb7, 0x05, 0x00, 0x05, 0x13, 0x67, 0x27, 0x00, 0x23, 0xa2, 0xe6, 0x20, 0x93, 0x87, 0x47, 0xf8, 0x0d, - 0x47, 0x2e, 0x94, 0xb3, 0x06, 0x99, 0x40, 0x63, 0x60, 0xd7, 0x02, 0x98, 0x43, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x05, - 0xa0, 0x0a, 0xfa, 0xa0, 0x2f, 0x24, 0xd9, 0xb1, 0xb6, 0xcf, 0x39, 0xac, 0xb6, 0xdf, 0xcc, 0x67, 0xfc, 0x9c, 0x50, - 0x2c, 0x1f, 0xc4, 0x64, 0xa1, 0xb3, 0xe3, 0x75, 0x93, 0xc6, 0x0b, 0x39, 0x3b, 0x8b, 0xc4, 0xce, 0x90, 0x31, 0x23, - 0xa2, 0xe7, 0x20, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, 0xb3, 0x06, - 0x94, 0x00, 0x90, 0x42, 0xb3, 0x86, 0x99, 0x00, 0x91, 0x04, 0x90, 0xc2, 0xf9, 0xb7, 0x13, 0x05, 0x50, 0x05, 0x82, - 0x80, 0x01, 0x11, 0xaa, 0x85, 0x11, 0x46, 0x68, 0x00, 0x06, 0xce, 0xef, 0xf0, 0x1f, 0xf7, 0x93, 0x07, 0xa0, 0x0a, - 0x63, 0x16, 0xf5, 0x00, 0x32, 0x45, 0xf2, 0x40, 0x05, 0x61, 0x82, 0x80, 0x01, 0x45, 0xe5, 0xbf, 0xb7, 0x07, 0x08, - 0x00, 0x63, 0xef, 0xa7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, - 0x8d, 0xe3, 0xae, 0x84, 0xef, 0xf0, 0xbf, 0xdd, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x22, 0x44, 0xb2, - 0x40, 0x23, 0xaa, 0x97, 0x20, 0x92, 0x44, 0x01, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x9f, 0xe7, 0xb2, 0x40, 0x22, 0x44, - 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xaa, 0x84, 0x2e, - 0x84, 0xef, 0xf0, 0x1f, 0xfb, 0x26, 0x85, 0xef, 0xf0, 0x9f, 0xf8, 0x63, 0x09, 0x85, 0x00, 0x13, 0x05, 0x50, 0x05, - 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xcd, 0xbf, 0x01, 0x11, 0x22, - 0xcc, 0x2e, 0xc6, 0x06, 0xce, 0x2a, 0x84, 0xef, 0xf0, 0x3f, 0xf6, 0xb2, 0x45, 0x63, 0x03, 0xb5, 0x02, 0xfd, 0x57, - 0x63, 0x1a, 0xf5, 0x00, 0x63, 0x8e, 0xfa, 0x4a, 0x1f, 0x43, 0x98, 0xa0, 0x41, 0x34, 0xfd, 0xef, 0x7f, 0xd9, 0x87, - 0xb7, 0x1f, 0xe3, 0x9d, 0x3d, 0x4f, 0x9d, 0x75, 0xd7, 0x86, 0x38, 0x45, 0x27, 0x1c, 0x81, 0x1c, 0x0a, 0xde, 0xbc, - 0xc2, 0x68, 0x32, 0xa5, 0x00, 0x22, 0x85, 0x62, 0x44, 0xf2, 0x40, 0x05, 0x61, 0x6f, 0xf0, 0xdf, 0xfa, 0x13, 0x05, - 0x50, 0x05, 0xf2, 0x40, 0x62, 0x44, 0x05, 0x61, 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xd5, 0xbf, 0xb7, 0x07, 0x08, - 0x00, 0x63, 0xe0, 0xb7, 0x04, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0xf7, 0xf5, 0x1f, 0xaa, 0x84, - 0x2e, 0x84, 0x13, 0x05, 0x50, 0x05, 0x99, 0xef, 0xef, 0xf0, 0x9f, 0xd2, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, - 0x20, 0x39, 0x45, 0xef, 0xf0, 0x3f, 0xdd, 0x26, 0x85, 0xef, 0xf0, 0xdf, 0xda, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, - 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, 0x06, 0xce, 0x22, - 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xfb, 0xb7, 0x00, 0x81, 0x44, 0xf2, 0x40, - 0x62, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x26, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x82, 0x80, 0x93, 0xf4, 0xf5, 0x1f, 0x2e, - 0x84, 0xe5, 0xf4, 0x2a, 0x89, 0xef, 0xf0, 0xdf, 0xcc, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x41, 0x45, - 0xef, 0xf0, 0x7f, 0xd7, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x17, 0xf5, 0xfc, 0x37, 0x34, 0x20, 0x00, 0x13, 0x05, 0x44, - 0xc9, 0xef, 0xf0, 0x3f, 0xd4, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x87, 0x07, 0x20, 0x23, 0xa0, 0x07, 0x00, 0x91, 0x07, - 0xe3, 0x9d, 0xe7, 0xfe, 0x93, 0x09, 0x44, 0xc9, 0x03, 0xd6, 0xfa, 0xa5, 0x13, 0x68, 0xc5, 0x11, 0x04, 0xb3, 0xdd, - 0x87, 0x59, 0xc1, 0x5d, 0x32, 0xa2, 0x6e, 0x90, 0x23, 0x54, 0x5e, 0x34, 0xdc, 0xcb, 0xfa, 0x8a, 0xb8, 0xb3, 0x93, - 0x57, 0x9b, 0xee, 0xd9, 0x84, 0x40, 0x33, 0xc9, 0x1f, 0x93, 0x07, 0xc0, 0x1d, 0x63, 0xfa, 0xc7, 0x00, 0x37, 0x55, - 0x10, 0x00, 0x99, 0x45, 0x13, 0x05, 0x85, 0x7b, 0xef, 0xf0, 0x2f, 0x87, 0x41, 0xbf, 0x93, 0x05, 0x44, 0xc9, 0x4a, - 0x85, 0xef, 0x20, 0xe0, 0x57, 0x83, 0xd4, 0xc9, 0x1f, 0x41, 0xb7, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe7, 0xa7, 0x04, - 0x41, 0x11, 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x13, 0x05, 0x50, 0x05, 0x9d, - 0xe7, 0xef, 0xf0, 0x9f, 0xc4, 0x85, 0x67, 0xb7, 0x04, 0x08, 0x05, 0x93, 0x87, 0x97, 0x82, 0x23, 0xa2, 0xf4, 0x20, - 0x23, 0xac, 0x84, 0x20, 0x39, 0x45, 0xef, 0xf0, 0x9f, 0xce, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf8, 0x13, - 0x05, 0xa0, 0x0a, 0x23, 0xa2, 0xf4, 0x20, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, - 0x50, 0x05, 0x82, 0x80, 0x0d, 0x65, 0x01, 0x11, 0x13, 0x05, 0x05, 0x20, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, - 0xc8, 0x4e, 0xc6, 0xef, 0x10, 0x10, 0x45, 0x39, 0x45, 0xef, 0x10, 0x70, 0x46, 0x13, 0x05, 0x80, 0x07, 0x37, 0x39, - 0x20, 0x00, 0xef, 0xf0, 0xef, 0xbd, 0x93, 0x09, 0x49, 0xf8, 0x83, 0xa7, 0x09, 0x00, 0x37, 0x04, 0x08, 0x05, 0x93, - 0x04, 0x04, 0x20, 0xdc, 0xc0, 0xb7, 0x07, 0x46, 0x00, 0x85, 0x07, 0xdc, 0xcc, 0x85, 0x67, 0x93, 0x87, 0x57, 0x86, - 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, 0xdc, 0xc0, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0xfa, 0x5b, 0xf3, 0xcc, 0x47, - 0x28, 0xc4, 0x2e, 0x9e, 0xf1, 0x58, 0xad, 0xca, 0x83, 0x26, 0x1d, 0x52, 0xdf, 0xdb, 0x9b, 0x49, 0xfe, 0x70, 0xd5, - 0x76, 0x12, 0xd6, 0xaf, 0xa4, 0x8a, 0x4b, 0x4f, 0x8d, 0x18, 0x34, 0x25, 0xba, 0xef, 0xf0, 0x6f, 0xcd, 0xb7, 0x07, - 0x40, 0x08, 0x9c, 0xc8, 0xdc, 0x40, 0x01, 0x45, 0x13, 0x09, 0x49, 0xf8, 0x93, 0xe7, 0x07, 0x18, 0x23, 0xa0, 0xf9, - 0x00, 0xef, 0xf0, 0x7f, 0xf3, 0x93, 0x07, 0x04, 0x10, 0x98, 0x43, 0xb7, 0x67, 0xa5, 0xf0, 0x93, 0x87, 0xf7, 0xa0, - 0x63, 0x05, 0xf7, 0x02, 0x37, 0x55, 0x10, 0x00, 0x95, 0x45, 0x13, 0x05, 0x85, 0x7b, 0xef, 0xe0, 0x3f, 0xf7, 0x41, - 0x67, 0x7d, 0x17, 0x93, 0x07, 0x04, 0x18, 0xb8, 0xd3, 0xf8, 0xd3, 0xb8, 0xd7, 0xf8, 0xd7, 0xb8, 0xdb, 0xf8, 0xdb, - 0xb8, 0xdf, 0xf8, 0xdf, 0x51, 0x45, 0xef, 0xf0, 0x5f, 0xc1, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x91, - 0x8b, 0x91, 0xeb, 0x37, 0x55, 0x10, 0x00, 0x91, 0x45, 0x13, 0x05, 0x85, 0x7b, 0xef, 0xe0, 0xbf, 0xf3, 0xef, 0xd0, - 0x2f, 0xeb, 0xb7, 0x07, 0x08, 0x05, 0x37, 0x07, 0x40, 0x00, 0x23, 0xa6, 0xe7, 0x20, 0x03, 0x27, 0x09, 0x00, 0xf2, - 0x40, 0x62, 0x44, 0x23, 0xa2, 0xe7, 0x20, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, 0x85, 0x67, - 0x37, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0x86, 0x23, 0x22, 0xf7, 0xf8, 0x37, 0x37, 0x20, 0x00, 0x93, 0x07, 0x50, - 0x05, 0x23, 0x24, 0xf7, 0xf8, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, 0xf7, 0xf8, 0x6f, 0xf0, 0xbf, 0xee, 0xb7, 0x07, - 0x08, 0x00, 0x63, 0xe0, 0xa7, 0x06, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xc6, 0x26, 0xc2, 0xfa, - 0x99, 0xd2, 0x61, 0x95, 0x3f, 0xe8, 0x1c, 0x2a, 0x9a, 0x01, 0x8f, 0xeb, 0x20, 0x1d, 0x32, 0x6a, 0xc6, 0x16, 0xc7, - 0x8a, 0xf3, 0x3e, 0x84, 0xc4, 0x22, 0xff, 0x92, 0x5a, 0xff, 0xb5, 0xe8, 0x6e, 0xf0, 0x34, 0x2a, 0x84, 0x13, 0x05, - 0x50, 0x05, 0xa1, 0xe3, 0xae, 0x84, 0xef, 0xf0, 0x5f, 0xad, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x01, - 0x47, 0x93, 0x06, 0x00, 0x20, 0xb3, 0x85, 0xe4, 0x00, 0x8c, 0x41, 0x33, 0x06, 0xf7, 0x00, 0x11, 0x07, 0x0c, 0xc2, - 0xe3, 0x19, 0xd7, 0xfe, 0x7d, 0x57, 0x93, 0x87, 0x07, 0x20, 0xf8, 0xc3, 0xb8, 0xc7, 0xf8, 0xc7, 0xb8, 0xcb, 0x29, - 0x45, 0xef, 0xf0, 0x9f, 0xb5, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, - 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xaa, 0x85, 0x37, 0x05, 0x08, 0x05, 0x41, 0x46, 0x13, 0x05, 0x05, 0x26, 0x6f, - 0xf0, 0x8f, 0xd5, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xef, 0xa7, 0x0a, 0x01, 0x11, 0x26, 0xca, 0x93, 0x77, 0xf5, 0x1f, - 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x56, 0xc2, 0xaa, 0x84, 0x13, 0x05, 0x50, 0x05, 0xd9, - 0xe7, 0x93, 0x07, 0xc0, 0x1d, 0x32, 0x89, 0x63, 0xe3, 0xc7, 0x08, 0xb6, 0x89, 0x37, 0x34, 0x20, 0x00, 0x2e, 0x8a, - 0xef, 0xf0, 0x3f, 0xa4, 0x13, 0x06, 0x00, 0x20, 0x81, 0x45, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x00, 0x38, 0x4a, - 0x86, 0xd2, 0x85, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x80, 0x33, 0x4e, 0x85, 0xef, 0xf0, 0xbf, 0xf9, 0x93, 0x0a, - 0x44, 0xc9, 0xb7, 0x07, 0x08, 0x05, 0x23, 0x9e, 0x2a, 0x1f, 0x13, 0x07, 0x44, 0xc9, 0x93, 0x86, 0x07, 0x20, 0x10, - 0x43, 0x11, 0x07, 0xfa, 0x0a, 0x4b, 0x11, 0x5a, 0x0d, 0x90, 0xd2, 0x18, 0x5a, 0xc5, 0xa2, 0x40, 0xcf, 0x75, 0x28, - 0xdf, 0x8a, 0x4f, 0xe0, 0x3a, 0xe0, 0x4a, 0x3e, 0xa0, 0x27, 0x53, 0xa2, 0x0c, 0xb1, 0x4a, 0x34, 0x0b, 0xc8, 0x35, - 0x90, 0xc3, 0x91, 0x07, 0xe3, 0x9c, 0xd7, 0xfe, 0x13, 0x06, 0x00, 0x20, 0x81, 0x45, 0x13, 0x05, 0x44, 0xc9, 0xef, - 0x20, 0x00, 0x34, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x97, 0x20, 0x31, 0x45, 0xef, 0xf0, 0xff, 0xa9, 0x93, 0x07, - 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x7b, 0x8d, 0x45, 0xef, 0xe0, 0x9f, - 0xdc, 0x13, 0x05, 0x50, 0x05, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, - 0x05, 0x61, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xeb, 0xa7, 0x02, 0x41, - 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0xf5, 0x1f, 0x2a, 0x84, 0x89, 0xef, 0xef, 0xf0, 0xbf, 0x99, 0xb7, 0x07, - 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x22, 0x44, 0xb2, 0x40, 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0xff, 0xa3, 0xb2, - 0x40, 0x22, 0x44, 0x13, 0x05, 0x50, 0x05, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, - 0x22, 0xc4, 0x06, 0xc6, 0x37, 0x04, 0x08, 0x05, 0x23, 0x2c, 0xa4, 0x20, 0xef, 0xf0, 0x3f, 0x96, 0xb7, 0x37, 0x20, - 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa4, 0xe7, 0xf8, 0xb7, 0xb7, 0xaa, 0x02, 0x93, 0x87, 0x67, 0xaa, 0xb2, 0x40, - 0x23, 0x24, 0xf4, 0x20, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xbf, 0x93, 0xb7, - 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0xfa, 0x05, 0xfb, 0xae, 0x90, 0x96, 0x20, 0x2e, 0xf2, 0xc0, 0xb9, 0x69, - 0xb8, 0x49, 0x47, 0x8f, 0x1a, 0xbd, 0x87, 0xfd, 0x54, 0x8e, 0xf1, 0xcd, 0x12, 0x84, 0x44, 0x99, 0xe1, 0xba, 0xb4, - 0x33, 0x80, 0xa0, 0x36, 0x23, 0xa4, 0xe7, 0xf8, 0xb2, 0x40, 0xb7, 0xb7, 0xa6, 0x02, 0x37, 0x07, 0x08, 0x05, 0x93, - 0x87, 0xa7, 0xaa, 0x23, 0x24, 0xf7, 0x20, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x3e, 0xcc, 0xb7, 0x07, 0x08, 0x05, - 0x3a, 0xce, 0x03, 0xa7, 0xc7, 0x20, 0x36, 0xd0, 0xb7, 0x06, 0x40, 0x00, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, - 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, - 0x75, 0x8f, 0x05, 0xcf, 0x23, 0xa6, 0xd7, 0x20, 0x13, 0x07, 0xa0, 0x0a, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0xe7, - 0xf8, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, - 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, - 0x30, 0x03, 0xa7, 0xc7, 0x20, 0xb7, 0x06, 0x00, 0x08, 0x37, 0x55, 0x10, 0x00, 0x75, 0x8f, 0x0d, 0xc3, 0x23, 0xa6, - 0xd7, 0x20, 0x85, 0x45, 0x13, 0x05, 0x85, 0x7b, 0xef, 0xe0, 0xbf, 0xc8, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, - 0x0a, 0x23, 0xa6, 0xe7, 0xf8, 0xef, 0xd0, 0x5f, 0xce, 0x75, 0xb7, 0x89, 0x45, 0x13, 0x05, 0x85, 0x7b, 0xef, 0xe0, - 0xff, 0xc6, 0xb7, 0x07, 0x02, 0x00, 0x73, 0xb0, 0x47, 0x30, 0xe5, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, - 0x05, 0x23, 0xa8, 0xe7, 0xf8, 0x82, 0x80, 0x99, 0x47, 0x63, 0x05, 0xfa, 0x21, 0x42, 0x79, 0x19, 0xd8, 0xe4, 0x27, - 0x7b, 0xc1, 0x9b, 0x06, 0x7f, 0x51, 0xd5, 0xe6, 0xa4, 0x06, 0x28, 0x05, 0x83, 0x03, 0x08, 0x7d, 0x48, 0x9d, 0x59, - 0x6f, 0xa8, 0x38, 0xda, 0xbc, 0xf6, 0x78, 0x37, 0xf5, 0x02, 0x9d, 0x47, 0x63, 0x0b, 0xf5, 0x00, 0x95, 0x47, 0x63, - 0x15, 0xf5, 0x02, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xf7, 0xf7, 0xf7, 0x29, 0xa8, 0xb7, 0x37, 0x20, 0x00, - 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa8, 0xe7, 0xf8, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xe7, 0x07, - 0x08, 0x7c, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf9, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, - 0xf7, 0x00, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xe7, 0x07, 0x08, 0x7c, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, - 0x00, 0x03, 0xa7, 0x07, 0xf9, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, 0xf7, 0x00, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, - 0x93, 0xf7, 0xf7, 0xf7, 0x7c, 0xc3, 0x82, 0x80, 0x39, 0x71, 0x2a, 0xd6, 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, 0x13, - 0x05, 0xc5, 0x7b, 0x85, 0x45, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, - 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0x1f, 0xbb, 0xef, - 0xd0, 0x7f, 0xc1, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, - 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, - 0x00, 0x20, 0x30, 0x39, 0x71, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0xfa, 0x1f, 0xb7, 0xc4, - 0xca, 0x3e, 0x38, 0x03, 0x5e, 0x54, 0x01, 0xdf, 0x72, 0x65, 0xce, 0x62, 0x80, 0x6f, 0x7c, 0x71, 0x39, 0x49, 0x82, - 0x36, 0xd0, 0x49, 0x49, 0x4c, 0xe2, 0x3c, 0x23, 0x6e, 0xcd, 0x50, 0x38, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x3a, - 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xf3, 0x25, 0x20, 0x34, - 0xc1, 0x67, 0x37, 0x55, 0x10, 0x00, 0xdd, 0x8d, 0x13, 0x05, 0xc5, 0x7b, 0xef, 0xe0, 0x1f, 0xb5, 0xef, 0xd0, 0x7f, - 0xbb, 0x01, 0xa0, 0x39, 0x71, 0x2a, 0xd6, 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, 0x13, 0x05, 0xc5, 0x7b, 0x89, 0x45, - 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, - 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0xbf, 0xb1, 0xef, 0xd0, 0x1f, 0xb8, 0xf2, 0x50, - 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, - 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x07, - 0x01, 0x01, 0xb7, 0x07, 0x00, 0x01, 0x13, 0x07, 0x17, 0x10, 0x98, 0xd3, 0x37, 0x07, 0x03, 0x04, 0x09, 0x07, 0xd8, - 0xd3, 0x13, 0x07, 0x50, 0x60, 0x98, 0xd7, 0x37, 0x17, 0x09, 0x00, 0x13, 0x07, 0x77, 0x80, 0xd8, 0xd7, 0x37, 0x17, - 0x0b, 0x0b, 0x13, 0x07, 0xa7, 0xa0, 0x98, 0xdb, 0x37, 0x17, 0x0c, 0x00, 0x13, 0x07, 0xb7, 0xc0, 0xd8, 0xdb, 0x37, - 0x17, 0x0f, 0x00, 0x13, 0x07, 0xd7, 0xe0, 0x98, 0xdf, 0x05, 0x67, 0xd8, 0xdf, 0xb7, 0x17, 0xff, 0x7f, 0x93, 0x87, - 0xfa, 0xf3, 0xbd, 0x3f, 0x3b, 0x8f, 0x42, 0x43, 0xf6, 0x89, 0xf0, 0xa2, 0xe6, 0xf6, 0x3c, 0x5d, 0xd2, 0x5b, 0x73, - 0x53, 0xd4, 0x5e, 0xea, 0xe1, 0x8a, 0x67, 0x59, 0xb5, 0xf7, 0xb9, 0x7c, 0x7b, 0x88, 0x28, 0x39, 0x07, 0x80, 0x73, - 0xa0, 0x47, 0x30, 0xa1, 0x47, 0x73, 0xa0, 0x07, 0x30, 0x82, 0x80, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x40, 0x00, - 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x80, - 0x00, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, - 0x00, 0x04, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x3e, 0xc6, 0xb7, - 0x07, 0x00, 0x20, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x05, 0x65, 0x6f, 0x10, - 0xc0, 0x69, 0x05, 0x65, 0x6f, 0x10, 0x20, 0x6a, 0x01, 0x11, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x06, 0xce, 0x26, - 0xca, 0x52, 0xc4, 0x56, 0xc2, 0x9d, 0x47, 0x2a, 0x84, 0xae, 0x89, 0x32, 0x89, 0x63, 0xd4, 0xc7, 0x00, 0xef, 0xd0, - 0x4f, 0x99, 0xef, 0xf0, 0x5f, 0xfd, 0xb7, 0x07, 0x01, 0x07, 0x18, 0x40, 0xdc, 0x43, 0x93, 0x06, 0xf0, 0x0f, 0x63, - 0x05, 0xd7, 0x00, 0xf1, 0x9b, 0x0d, 0x8b, 0xd9, 0x8f, 0x13, 0xf7, 0xb7, 0xff, 0x83, 0x47, 0x44, 0x00, 0x81, 0x44, - 0x31, 0x4a, 0x8a, 0x07, 0x91, 0x8b, 0xd9, 0x8f, 0x37, 0x07, 0x01, 0x07, 0x5c, 0xc3, 0xb7, 0x1a, 0x01, 0x07, 0x63, - 0xcf, 0x24, 0x03, 0x14, 0x40, 0x05, 0x47, 0xad, 0x47, 0x63, 0x9e, 0xe6, 0x00, 0x83, 0x46, 0x44, 0x00, 0x13, 0x07, - 0xa0, 0x0a, 0xbd, 0x47, 0xfa, 0xf1, 0xd0, 0xfb, 0x5d, 0x05, 0x9d, 0xe2, 0x55, 0x1f, 0xaf, 0xf8, 0x3a, 0xf5, 0x06, - 0x18, 0x37, 0x7f, 0xfa, 0xe9, 0x45, 0xf6, 0x65, 0xb2, 0x45, 0x7b, 0x51, 0x56, 0x64, 0x69, 0xe2, 0x46, 0x3a, 0x00, - 0x3a, 0x63, 0x97, 0xe6, 0x00, 0x14, 0x44, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2a, 0xd7, 0xf8, 0xf2, 0x40, 0x62, 0x44, - 0x37, 0x07, 0x01, 0x07, 0x5c, 0xc7, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, - 0x80, 0xb3, 0x85, 0x44, 0x03, 0x13, 0x95, 0x44, 0x00, 0x31, 0x46, 0x56, 0x95, 0x85, 0x04, 0xce, 0x95, 0xef, 0xf0, - 0x4f, 0x87, 0x7d, 0xb7, 0x1d, 0x71, 0x3e, 0xda, 0xb7, 0x07, 0x01, 0x07, 0xa2, 0xc6, 0x80, 0x47, 0x86, 0xce, 0x96, - 0xcc, 0x9a, 0xca, 0x9e, 0xc8, 0xaa, 0xc4, 0xae, 0xc2, 0xb2, 0xc0, 0x36, 0xde, 0x3a, 0xdc, 0x42, 0xd8, 0x46, 0xd6, - 0x72, 0xd4, 0x76, 0xd2, 0x7a, 0xd0, 0x7e, 0xce, 0x93, 0x77, 0xb4, 0x00, 0x95, 0xc7, 0xb7, 0x07, 0x00, 0x40, 0x73, - 0xb0, 0x47, 0x30, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0xa2, 0x86, 0x13, 0x06, - 0x06, 0x7c, 0x93, 0x85, 0x85, 0x7c, 0x13, 0x05, 0x85, 0x77, 0xef, 0xe0, 0x3f, 0x8c, 0xef, 0xd0, 0xff, 0x99, 0x93, - 0x77, 0x44, 0x00, 0x99, 0xcf, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf9, 0x91, 0xcb, 0x6c, 0x00, 0x28, 0x00, - 0x82, 0x97, 0x22, 0x47, 0xb7, 0x07, 0x01, 0x07, 0x98, 0xcb, 0x32, 0x47, 0xd8, 0xcb, 0xb7, 0x07, 0x01, 0x07, 0x80, - 0xc7, 0x36, 0x44, 0xf6, 0x40, 0xe6, 0x42, 0x56, 0x43, 0xc6, 0x43, 0x26, 0x45, 0x96, 0x45, 0x06, 0x46, 0xf2, 0x56, - 0x62, 0x57, 0xd2, 0x57, 0x42, 0x58, 0xb2, 0x58, 0xfa, 0xad, 0x0d, 0x96, 0x72, 0x90, 0x0e, 0xf4, 0x1c, 0xdb, 0x0f, - 0x60, 0x37, 0x98, 0x29, 0x7b, 0x73, 0x0f, 0x2a, 0xbb, 0xe0, 0xe4, 0x00, 0x4d, 0x42, 0xd1, 0x0f, 0x9a, 0xf5, 0x8a, - 0x25, 0xce, 0x1d, 0xd8, 0x3a, 0x22, 0x5e, 0x92, 0x5e, 0x02, 0x5f, 0xf2, 0x4f, 0x25, 0x61, 0x73, 0x00, 0x20, 0x30, - 0xb7, 0x07, 0x02, 0x04, 0xdc, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, - 0x80, 0x82, 0x80, 0x13, 0x05, 0x00, 0x08, 0x6f, 0x10, 0x40, 0x52, 0x13, 0x05, 0x00, 0x08, 0x6f, 0x10, 0x80, 0x52, - 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x07, 0xd0, 0x79, 0x37, 0x04, 0x02, 0x04, 0x5c, 0xc4, 0x85, - 0x44, 0x95, 0x65, 0x37, 0x35, 0x10, 0x00, 0x04, 0xc4, 0x93, 0x85, 0x05, 0xe2, 0x13, 0x05, 0x65, 0x6e, 0xef, 0xe0, - 0xdf, 0xce, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x13, 0xf5, 0x02, 0x54, 0x44, 0x63, 0x82, 0x96, 0x02, 0x37, 0x56, 0x10, - 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x7c, 0x93, 0x85, 0x45, 0x7d, 0x13, 0x05, - 0x45, 0x75, 0xef, 0xe0, 0x6f, 0xff, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, - 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xdf, 0xf8, 0xb2, 0x40, 0xb7, 0x07, 0x02, 0x04, 0x11, 0x47, 0x98, 0xc7, - 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x22, 0xc4, 0x26, 0xc2, 0x23, - 0xac, 0xe7, 0xf8, 0x06, 0xc6, 0x37, 0x07, 0x02, 0x02, 0x89, 0x46, 0x54, 0xc7, 0x13, 0x84, 0x87, 0xf9, 0x93, 0x04, - 0x50, 0x05, 0xef, 0xe0, 0x5f, 0xc7, 0x1c, 0x40, 0xe3, 0x9d, 0x97, 0xfe, 0xfa, 0x5a, 0xd1, 0x14, 0x0a, 0x0d, 0x7c, - 0x7b, 0x45, 0xab, 0x96, 0xb1, 0xc4, 0x9b, 0x32, 0xb4, 0x6a, 0xca, 0x4e, 0x3b, 0x5b, 0xd9, 0xf3, 0x45, 0x98, 0xc4, - 0xe7, 0x86, 0x28, 0x5b, 0xe0, 0xb0, 0xc6, 0xb0, 0x3b, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, - 0xb7, 0x07, 0x02, 0x02, 0xc8, 0xcb, 0x05, 0x47, 0xd8, 0xc7, 0xd8, 0x53, 0x69, 0x8f, 0x63, 0x1e, 0xa7, 0x00, 0xd4, - 0x57, 0x7d, 0x55, 0xf9, 0x8e, 0x91, 0xea, 0x94, 0x57, 0x75, 0x8f, 0x19, 0xe7, 0x88, 0x47, 0x05, 0x89, 0x33, 0x05, - 0xa0, 0x40, 0x82, 0x80, 0x7d, 0x55, 0x82, 0x80, 0x41, 0x45, 0x6f, 0x10, 0x60, 0x44, 0x41, 0x45, 0x6f, 0x10, 0x40, - 0x43, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, 0x2a, 0xc6, 0xef, 0xf0, 0x3f, 0xff, 0x13, 0x07, 0x50, 0x05, 0xb7, 0x37, - 0x20, 0x00, 0x23, 0xac, 0xe7, 0xf8, 0x37, 0x04, 0x02, 0x02, 0xa1, 0x47, 0x5c, 0xc4, 0x32, 0x45, 0x85, 0x47, 0x1c, - 0xc8, 0x93, 0x07, 0x10, 0x40, 0x5c, 0xc0, 0xef, 0xf0, 0xbf, 0xf9, 0xef, 0xf0, 0xff, 0xf5, 0x23, 0x22, 0x04, 0x00, - 0x62, 0x44, 0xf2, 0x40, 0x05, 0x61, 0x6f, 0xf0, 0x7f, 0xfb, 0x41, 0x11, 0x3a, 0xc6, 0x37, 0x07, 0x02, 0x02, 0x3e, - 0xc4, 0x1c, 0x47, 0x1c, 0xc7, 0x85, 0x8b, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, - 0xe7, 0xf8, 0x32, 0x47, 0xa2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0xc7, - 0xf9, 0x82, 0x80, 0xb7, 0x27, 0x00, 0x06, 0x9c, 0x47, 0x05, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x9d, 0x8b, 0xfd, 0x17, - 0x63, 0x74, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x37, 0x27, 0x00, 0x06, 0x1c, 0x47, 0xfa, 0x40, 0xea, - 0x29, 0x81, 0xae, 0xe3, 0x85, 0x0f, 0x07, 0x8b, 0x3f, 0x7a, 0x35, 0x17, 0x8c, 0x4c, 0xf2, 0x52, 0x8a, 0x9f, 0xbe, - 0x32, 0x6f, 0x10, 0xdf, 0x12, 0xa5, 0x85, 0x8b, 0xda, 0xf9, 0x96, 0x88, 0x3c, 0x85, 0x46, 0x13, 0x05, 0xa0, 0x0a, - 0x9d, 0x8b, 0x63, 0x89, 0xd7, 0x00, 0x1c, 0x47, 0x09, 0x47, 0x9d, 0x8b, 0x63, 0x84, 0xe7, 0x00, 0x13, 0x05, 0x50, - 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xc0, - 0x1f, 0xe9, 0x89, 0x67, 0x63, 0x64, 0xf4, 0x00, 0xef, 0xc0, 0x7f, 0xe8, 0x89, 0x65, 0x37, 0x45, 0x10, 0x00, 0x13, - 0x05, 0x25, 0x88, 0x93, 0x85, 0x05, 0x71, 0xef, 0xe0, 0x3f, 0xc2, 0x37, 0x05, 0x00, 0x06, 0x2a, 0x94, 0x08, 0x40, - 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x65, 0xb7, 0x37, 0x20, 0x00, 0x41, 0x11, 0x13, 0x07, 0x50, - 0x05, 0x13, 0x05, 0x05, 0x80, 0x23, 0xae, 0xe7, 0xf8, 0x06, 0xc6, 0xef, 0x10, 0xc0, 0x32, 0xef, 0xf0, 0xdf, 0xf6, - 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0x85, 0x7d, 0xef, - 0xe0, 0x4f, 0xeb, 0xef, 0xc0, 0xdf, 0xe2, 0xb7, 0x07, 0x46, 0x00, 0xb2, 0x40, 0x37, 0x27, 0x00, 0x06, 0x85, 0x07, - 0x5c, 0xcf, 0x85, 0x47, 0x5c, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, 0x00, - 0x03, 0x93, 0x85, 0xc5, 0x7d, 0x0a, 0x85, 0x22, 0xdc, 0x26, 0xda, 0x4a, 0xd8, 0x06, 0xde, 0x0a, 0x84, 0xef, 0x10, - 0x50, 0x39, 0x7d, 0x59, 0xb7, 0x24, 0x00, 0x06, 0x08, 0x40, 0x19, 0xc9, 0xef, 0xf0, 0xdf, 0xf4, 0x63, 0x13, 0x25, - 0x01, 0xfa, 0xb2, 0x5a, 0x7e, 0x54, 0x18, 0x27, 0xa0, 0x3a, 0x5a, 0xcf, 0x9f, 0x0b, 0x7f, 0xe5, 0xca, 0x69, 0xf8, - 0xd0, 0xd7, 0xa0, 0xfe, 0x16, 0x4b, 0x2a, 0xb9, 0x5b, 0x17, 0x5c, 0xe3, 0xac, 0xe8, 0xf0, 0x60, 0x3d, 0x08, 0x44, - 0x5c, 0x40, 0x31, 0x04, 0xa6, 0x97, 0x88, 0xc3, 0xed, 0xb7, 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, 0x42, 0x59, 0x21, - 0x61, 0x82, 0x80, 0x37, 0x27, 0x00, 0x06, 0x1c, 0x47, 0x85, 0x46, 0x9d, 0x8b, 0x63, 0x89, 0xd7, 0x02, 0x41, 0x11, - 0x06, 0xc6, 0x89, 0x65, 0x37, 0x45, 0x10, 0x00, 0x14, 0xcb, 0x13, 0x05, 0x85, 0x86, 0x93, 0x85, 0x05, 0x71, 0xef, - 0xe0, 0x7f, 0xb5, 0xb7, 0x27, 0x00, 0x06, 0x09, 0x47, 0x98, 0xcb, 0x05, 0x65, 0xb2, 0x40, 0x13, 0x05, 0x05, 0x80, - 0x41, 0x01, 0x6f, 0x10, 0x00, 0x28, 0xb7, 0x27, 0x00, 0x06, 0x09, 0x47, 0x05, 0x65, 0x98, 0xcb, 0x13, 0x05, 0x05, - 0x80, 0xfd, 0xb7, 0x05, 0x65, 0x41, 0x11, 0x13, 0x05, 0x05, 0x80, 0x06, 0xc6, 0xef, 0x10, 0x60, 0x25, 0xb2, 0x40, - 0xb7, 0x27, 0x00, 0x06, 0x21, 0x47, 0x98, 0xcb, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0x26, - 0xc2, 0xaa, 0x84, 0xef, 0xf0, 0xbf, 0xeb, 0x2a, 0x84, 0x6d, 0x2a, 0x13, 0x75, 0xf5, 0x07, 0xef, 0xe0, 0x7f, 0xa1, - 0x26, 0x85, 0xef, 0xf0, 0x9f, 0xea, 0x63, 0x05, 0xa4, 0x00, 0xef, 0xc0, 0xff, 0xd3, 0x01, 0x45, 0xb2, 0x40, 0x22, - 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x06, 0xd6, - 0x52, 0xcc, 0xaa, 0x89, 0x2e, 0x89, 0x93, 0x74, 0xc6, 0xff, 0x01, 0x44, 0x33, 0x8a, 0x89, 0x00, 0x33, 0x05, 0x89, - 0x00, 0x63, 0x1a, 0x94, 0x00, 0xfa, 0xc1, 0xfd, 0xf6, 0x6b, 0x03, 0xc3, 0xcb, 0x0f, 0x53, 0xc3, 0x2a, 0xa9, 0xbe, - 0x0d, 0x45, 0x01, 0xb2, 0x8c, 0x34, 0xde, 0x06, 0xcb, 0xa3, 0x21, 0x2f, 0x68, 0x87, 0x08, 0x49, 0x8f, 0xa3, 0xde, - 0x38, 0x3e, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0xef, - 0xf0, 0x9f, 0xf9, 0x2a, 0xc6, 0x11, 0x46, 0x6c, 0x00, 0x52, 0x85, 0xef, 0x10, 0xb0, 0x28, 0x11, 0x04, 0xc9, 0xbf, - 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x1f, 0xf8, 0x2a, 0x87, 0x85, 0x46, 0x01, 0x45, 0x89, 0x45, 0x01, 0xe7, 0xb2, - 0x40, 0x41, 0x01, 0x82, 0x80, 0x93, 0x77, 0xf7, 0x00, 0x01, 0x46, 0x81, 0xef, 0x63, 0xd3, 0xc5, 0x00, 0xb6, 0x87, - 0x5d, 0x8d, 0x86, 0x06, 0x13, 0x75, 0xf5, 0x0f, 0x93, 0xf6, 0xf6, 0x0f, 0x11, 0x83, 0xf1, 0xbf, 0x13, 0xf8, 0x17, - 0x00, 0x85, 0x83, 0x42, 0x96, 0x93, 0xf7, 0xf7, 0x0f, 0xf1, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, - 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0xae, 0x84, 0x99, 0xc3, 0xef, 0xc0, 0x1f, 0xc9, 0x89, 0x67, 0x63, 0x64, 0xf4, - 0x00, 0xef, 0xc0, 0x7f, 0xc8, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xae, 0xe7, 0xf8, 0xb7, 0x27, - 0x00, 0x06, 0x84, 0xcf, 0xc0, 0xcb, 0x22, 0x44, 0xb2, 0x40, 0x92, 0x44, 0x11, 0x47, 0x98, 0xcb, 0x89, 0x65, 0x37, - 0x45, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0xe5, 0x85, 0x41, 0x01, 0x6f, 0xe0, 0x3f, 0xa0, 0x41, 0x11, - 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xaa, 0x84, 0x2e, 0x84, 0xef, 0xf0, 0x3f, 0xfa, 0x26, 0x85, 0xef, 0xf0, 0x1f, - 0xda, 0x63, 0x09, 0x85, 0x00, 0x13, 0x05, 0x50, 0x05, 0xfa, 0x27, 0xc2, 0x44, 0x8d, 0x9c, 0x5e, 0xf7, 0x3c, 0x3d, - 0x1c, 0x55, 0xeb, 0xf3, 0xa5, 0x6d, 0x8e, 0x51, 0x6e, 0xa3, 0x7d, 0xca, 0xf1, 0x35, 0x94, 0x4e, 0x3a, 0xcb, 0x5f, - 0x22, 0x85, 0x41, 0x0d, 0x10, 0x3f, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0xa0, - 0x0a, 0xcd, 0xbf, 0x39, 0x71, 0x3a, 0xce, 0x37, 0x27, 0x00, 0x06, 0x3e, 0xcc, 0x1c, 0x47, 0x06, 0xde, 0x16, 0xdc, - 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, - 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xa1, 0x8b, 0x85, 0xcf, 0xa1, 0x47, 0x1c, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, - 0xa0, 0x0a, 0x23, 0xae, 0xe7, 0xf8, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, - 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, - 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x85, 0x7d, 0xef, 0xe0, 0xaf, - 0xc3, 0xef, 0xd0, 0x0f, 0xca, 0xe1, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa0, 0xa7, 0xfa, 0x05, 0x47, 0xb7, 0x37, - 0x20, 0x00, 0x23, 0x82, 0xe7, 0xfa, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xc7, 0x47, 0xfa, 0x41, 0x11, 0x06, - 0xc6, 0x99, 0xe3, 0xef, 0xc0, 0xbf, 0xb8, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xfa, 0x88, 0x43, 0x37, 0x67, - 0x19, 0x00, 0x13, 0x07, 0xd7, 0x60, 0x33, 0x05, 0xe5, 0x02, 0x37, 0xf7, 0x6e, 0x3c, 0xb2, 0x40, 0x13, 0x07, 0xf7, - 0x35, 0x3a, 0x95, 0x88, 0xc3, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0xfa, 0xf6, 0x9e, 0x95, 0xca, 0x9e, - 0xd2, 0x8c, 0x3f, 0xd0, 0x2d, 0x3c, 0x9b, 0x30, 0xe2, 0x63, 0x99, 0xa3, 0x9d, 0xd2, 0x1a, 0x53, 0x88, 0x1b, 0x2e, - 0x53, 0xb6, 0x83, 0xcb, 0x09, 0x9f, 0xbc, 0xe5, 0xe8, 0x3f, 0x93, 0x87, 0x47, 0xe9, 0x98, 0x43, 0x94, 0x47, 0xdc, - 0x43, 0x18, 0x4f, 0x13, 0x05, 0xa0, 0x0a, 0x75, 0x8f, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, - 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0xe9, 0x88, 0xc3, 0x37, 0x45, 0x10, 0x00, 0x13, 0x07, 0x00, 0x10, 0x93, - 0x05, 0x80, 0x3e, 0x13, 0x05, 0x45, 0xbe, 0x23, 0xa2, 0x07, 0x00, 0x98, 0xc7, 0x6f, 0xe0, 0x8f, 0xff, 0x37, 0x07, - 0x01, 0x02, 0x5c, 0x43, 0xb7, 0x06, 0x05, 0x00, 0xd5, 0x8f, 0x5c, 0xc3, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, - 0xc6, 0x2a, 0x84, 0xb7, 0x37, 0x00, 0x08, 0x37, 0x05, 0x08, 0x00, 0x63, 0x0c, 0xf4, 0x00, 0xb7, 0x27, 0x00, 0x08, - 0x37, 0x05, 0x04, 0x00, 0x63, 0x06, 0xf4, 0x00, 0xef, 0xc0, 0xbf, 0xae, 0x37, 0x05, 0x08, 0x00, 0xef, 0x00, 0x50, - 0x7c, 0x5c, 0x5c, 0x22, 0x85, 0xb2, 0x40, 0x93, 0xe7, 0x37, 0x00, 0x5c, 0xdc, 0x23, 0x2c, 0x04, 0x00, 0x22, 0x44, - 0x41, 0x01, 0x6f, 0xf0, 0xdf, 0xf8, 0xfd, 0x77, 0x41, 0x11, 0xfd, 0x17, 0x22, 0xc4, 0x06, 0xc6, 0xe9, 0x8f, 0x37, - 0x27, 0x00, 0x08, 0x2a, 0x84, 0x63, 0x84, 0xe7, 0x00, 0xef, 0xc0, 0x1f, 0xab, 0x5c, 0x5c, 0x37, 0x05, 0x04, 0x00, - 0xf5, 0x9b, 0x5c, 0xdc, 0xb7, 0x27, 0x00, 0x08, 0x63, 0x04, 0xf4, 0x00, 0x37, 0x05, 0x08, 0x00, 0x22, 0x44, 0xb2, - 0x40, 0x41, 0x01, 0x6f, 0x00, 0xf0, 0x77, 0x39, 0x71, 0x22, 0xdc, 0x26, 0xda, 0x4a, 0xd8, 0x06, 0xde, 0xfa, 0x48, - 0x9c, 0x5c, 0x0b, 0xb9, 0x41, 0xef, 0x46, 0x07, 0xf1, 0x14, 0x9a, 0xcc, 0x61, 0x9a, 0xfe, 0xdc, 0x4b, 0xf6, 0xff, - 0x82, 0x46, 0x65, 0x34, 0x8f, 0xe9, 0xce, 0xa6, 0xc4, 0x62, 0x73, 0x11, 0xc0, 0x40, 0x4e, 0xd6, 0x52, 0xd4, 0x56, - 0xd2, 0x5a, 0xd0, 0x5e, 0xce, 0x62, 0xcc, 0xaa, 0x84, 0x2e, 0x89, 0x32, 0x84, 0x99, 0xe1, 0xef, 0xc0, 0xff, 0xa6, - 0xfd, 0x77, 0xfd, 0x17, 0xe5, 0x8f, 0x37, 0x27, 0x00, 0x08, 0x63, 0x84, 0xe7, 0x00, 0xef, 0xc0, 0xdf, 0xa5, 0xb7, - 0x39, 0x20, 0x00, 0x93, 0x89, 0x49, 0xe9, 0x85, 0x4a, 0x37, 0x4b, 0x10, 0x00, 0x93, 0x0b, 0xa0, 0x0a, 0x11, 0x4c, - 0x15, 0xe4, 0x9c, 0x4c, 0x37, 0x07, 0x11, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x99, 0xc3, 0x13, 0x05, 0x50, - 0x05, 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, 0x4b, - 0x62, 0x4c, 0x21, 0x61, 0x82, 0x80, 0x93, 0x05, 0x80, 0x3e, 0x13, 0x05, 0x4b, 0xbe, 0x23, 0xa0, 0x99, 0x00, 0x23, - 0xa2, 0x59, 0x01, 0x23, 0xa4, 0x59, 0x01, 0xef, 0xe0, 0xef, 0xed, 0xe3, 0x16, 0x75, 0xfd, 0xdc, 0x50, 0x22, 0x8a, - 0x3e, 0xc6, 0x63, 0x73, 0x8c, 0x00, 0x11, 0x4a, 0x4a, 0x85, 0x52, 0x86, 0x6c, 0x00, 0xef, 0x10, 0x60, 0x78, 0x52, - 0x99, 0x33, 0x04, 0x44, 0x41, 0x71, 0xbf, 0x41, 0x11, 0x37, 0x05, 0x02, 0x00, 0x06, 0xc6, 0xef, 0x00, 0x90, 0x6b, - 0xb2, 0x40, 0xb7, 0x17, 0x00, 0x08, 0x37, 0x07, 0x07, 0x00, 0x98, 0xd3, 0x13, 0x05, 0x40, 0x1f, 0x41, 0x01, 0x6f, - 0xe0, 0x2f, 0xe4, 0xb7, 0x17, 0x00, 0x08, 0x23, 0xa0, 0x07, 0x02, 0x37, 0x05, 0x02, 0x00, 0x6f, 0x00, 0xf0, 0x69, - 0x39, 0x71, 0xfa, 0xb9, 0xbb, 0x04, 0xe9, 0x14, 0x0b, 0x0c, 0x14, 0x47, 0xf3, 0x40, 0x0b, 0x2d, 0xb7, 0x5b, 0x54, - 0x2b, 0x7c, 0x4c, 0x00, 0x23, 0x1d, 0x3f, 0xeb, 0xe3, 0xa8, 0x84, 0xa6, 0x49, 0xb6, 0x21, 0x0d, 0x98, 0x41, 0x3e, - 0xcc, 0xb7, 0x17, 0x00, 0x08, 0x3a, 0xce, 0x98, 0x57, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, - 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0x05, - 0x8b, 0x05, 0xcb, 0x98, 0x57, 0x13, 0x67, 0x17, 0x00, 0x98, 0xd7, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, - 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, - 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x98, 0x57, 0x09, 0x8b, 0x09, 0xc7, 0x98, 0x57, - 0x13, 0x67, 0x27, 0x00, 0xf1, 0xb7, 0x98, 0x57, 0x11, 0x8b, 0x09, 0xc7, 0x98, 0x57, 0x13, 0x67, 0x47, 0x00, 0x7d, - 0xbf, 0xb7, 0x07, 0x00, 0x01, 0x73, 0xb0, 0x47, 0x30, 0xef, 0xd0, 0xcf, 0xa1, 0x4d, 0xbf, 0x37, 0x07, 0x00, 0x02, - 0x5c, 0x4f, 0xb7, 0x36, 0x20, 0x00, 0x13, 0xf6, 0x77, 0x00, 0xe1, 0x9b, 0x23, 0xa4, 0xc6, 0xfa, 0x93, 0xe7, 0x47, - 0x00, 0x5c, 0xcf, 0x1c, 0x4f, 0xf9, 0x9b, 0x1c, 0xcf, 0x82, 0x80, 0x41, 0x11, 0x26, 0xc2, 0xb7, 0x04, 0x00, 0x02, - 0x22, 0xc4, 0xc0, 0x4c, 0x9c, 0x4c, 0x06, 0xc6, 0x13, 0x05, 0x80, 0x07, 0x93, 0xe7, 0x17, 0x00, 0x9c, 0xcc, 0xef, - 0xe0, 0xef, 0xd6, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x87, 0xfa, 0x61, 0x98, 0xb2, 0x40, 0x5d, 0x8c, 0xc0, 0xcc, - 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0xfa, 0x6d, 0x97, 0x0c, 0x41, 0x57, 0x5b, 0x3f, 0x3d, 0x77, 0xa9, 0x84, 0x83, - 0x04, 0x4e, 0x80, 0xcb, 0x33, 0x17, 0x19, 0x4c, 0xc3, 0xab, 0x07, 0x42, 0xb7, 0xa8, 0x6d, 0xbe, 0x06, 0xf2, 0x8e, - 0x24, 0x70, 0x42, 0x82, 0x80, 0x13, 0x17, 0x05, 0x01, 0x93, 0x17, 0x85, 0x01, 0xba, 0x97, 0x13, 0x17, 0x85, 0x00, - 0xba, 0x97, 0x3e, 0x95, 0xb7, 0x07, 0x00, 0x04, 0x88, 0xd3, 0xc8, 0xd3, 0x88, 0xd7, 0xc8, 0xd7, 0x88, 0xdb, 0xc8, - 0xdb, 0x88, 0xdf, 0xc8, 0xdf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x00, 0x08, 0x98, 0xd3, 0x23, 0xa2, - 0x07, 0x02, 0x23, 0xa4, 0x07, 0x02, 0x23, 0xa6, 0x07, 0x02, 0x23, 0xa8, 0x07, 0x02, 0x23, 0xaa, 0x07, 0x02, 0x23, - 0xac, 0x07, 0x02, 0x23, 0xae, 0x07, 0x02, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x07, 0xeb, 0x82, 0x80, - 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0x6f, 0xe0, 0x0f, 0xfd, 0xb7, - 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa8, 0xe7, 0xea, 0xb7, 0x07, 0x00, 0x04, 0xc8, 0xc3, 0x13, 0x07, - 0x90, 0x02, 0x85, 0x65, 0x37, 0x45, 0x10, 0x00, 0x98, 0xc7, 0x93, 0x85, 0x85, 0x38, 0x13, 0x05, 0x25, 0xec, 0x6f, - 0xe0, 0x8f, 0xd1, 0x41, 0x11, 0x22, 0xc4, 0x01, 0x45, 0x37, 0x34, 0x20, 0x00, 0x06, 0xc6, 0x13, 0x04, 0x04, 0xea, - 0xef, 0xf0, 0xbf, 0xf5, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, 0xfb, 0x48, 0x44, 0xb7, - 0x07, 0x02, 0x00, 0x95, 0x07, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0xbf, 0xfa, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, - 0x05, 0x05, 0xef, 0xf0, 0xff, 0xf9, 0x48, 0x44, 0xb7, 0x07, 0xfa, 0xe2, 0x72, 0xd1, 0x1e, 0xe2, 0x74, 0xab, 0xff, - 0x69, 0x9e, 0xfa, 0x16, 0x8f, 0xc4, 0x87, 0x8a, 0xc0, 0x1a, 0x9d, 0xd1, 0xb3, 0xe9, 0x38, 0x9e, 0x78, 0x6d, 0x85, - 0xb8, 0xb3, 0x80, 0x3b, 0xd7, 0x48, 0x43, 0x00, 0x10, 0x99, 0x07, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0xff, 0xf8, - 0x48, 0x44, 0xb7, 0x07, 0x01, 0x10, 0x99, 0x07, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0xff, 0xf7, 0x22, 0x44, 0xb2, - 0x40, 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0xf7, 0x7d, 0x47, 0x63, 0x7e, 0xb7, 0x04, 0xaa, 0x85, 0x37, 0x05, - 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0x6f, 0xe0, 0x6f, 0xf2, 0xb3, 0x06, 0xf5, 0x00, 0x83, - 0xc6, 0x06, 0x00, 0x33, 0x07, 0xf1, 0x00, 0x85, 0x07, 0x23, 0x00, 0xd7, 0x00, 0xe3, 0x97, 0xf5, 0xfe, 0x18, 0x10, - 0x93, 0x87, 0x15, 0x00, 0xba, 0x95, 0x13, 0x07, 0x00, 0xf8, 0x23, 0x80, 0xe5, 0xfe, 0x13, 0x07, 0x00, 0x02, 0x63, - 0x92, 0xe7, 0x02, 0x37, 0x05, 0x00, 0x04, 0x8a, 0x85, 0x13, 0x06, 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0xef, 0xe0, - 0x6f, 0xee, 0xb2, 0x50, 0x45, 0x61, 0x82, 0x80, 0x79, 0x71, 0x06, 0xd6, 0x81, 0x47, 0xd9, 0xb7, 0xb3, 0x06, 0xf1, - 0x00, 0x23, 0x80, 0x06, 0x00, 0x85, 0x07, 0xc9, 0xbf, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x00, 0x08, 0x98, 0xd3, - 0x23, 0xa2, 0x07, 0x02, 0x23, 0xa4, 0x07, 0x02, 0x23, 0xa6, 0x07, 0x02, 0x23, 0xa8, 0x07, 0x02, 0x13, 0x17, 0xb5, - 0x00, 0xb7, 0x06, 0xff, 0x00, 0x23, 0xaa, 0x07, 0x02, 0x75, 0x8f, 0x6e, 0x05, 0x23, 0xac, 0x07, 0x02, 0x3a, 0x95, - 0xc8, 0xdf, 0x82, 0x80, 0x37, 0x65, 0x10, 0x00, 0x01, 0x11, 0x13, 0x05, 0x45, 0x81, 0xfa, 0x91, 0x33, 0xb7, 0xfc, - 0x20, 0xee, 0xb1, 0xaa, 0x15, 0xcf, 0xc4, 0xc6, 0xdd, 0x50, 0x9b, 0xca, 0x7f, 0xc3, 0x59, 0xe7, 0x2e, 0x34, 0x6d, - 0x74, 0x95, 0x95, 0x30, 0x31, 0xd0, 0xf0, 0xe3, 0xf0, 0x20, 0x44, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, - 0x4e, 0xc6, 0x52, 0xc4, 0x37, 0x34, 0x20, 0x00, 0xef, 0xf0, 0xdf, 0xe9, 0x93, 0x07, 0x04, 0xea, 0xc8, 0x47, 0x7e, - 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xff, 0xe9, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x10, 0xf5, 0x2e, 0xaa, 0x84, - 0x13, 0x05, 0x00, 0x02, 0xef, 0xf0, 0x1f, 0xf9, 0x13, 0x04, 0x04, 0xea, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, - 0x17, 0xef, 0xf0, 0xdf, 0xe7, 0xaa, 0x89, 0x63, 0x10, 0x95, 0x2c, 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, - 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x7f, 0xe6, 0xaa, 0x84, 0x63, 0x15, 0x35, 0x2b, 0x48, 0x44, 0x7e, 0x05, 0x13, - 0x65, 0x05, 0x02, 0xef, 0xf0, 0x5f, 0xe5, 0xaa, 0x89, 0x63, 0x1c, 0x95, 0x28, 0x1c, 0x40, 0x48, 0x44, 0x37, 0x0a, - 0x00, 0x04, 0x83, 0xc7, 0x07, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x15, 0x00, 0x93, 0xe7, 0x07, 0x20, 0x23, 0x2c, 0xfa, - 0x00, 0xef, 0xf0, 0x1f, 0xe3, 0xaa, 0x84, 0x63, 0x1a, 0x35, 0x27, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, - 0xef, 0xf0, 0xff, 0xe1, 0x2a, 0x89, 0x63, 0x11, 0x95, 0x26, 0xef, 0xf0, 0x1f, 0xdd, 0x48, 0x44, 0x7e, 0x05, 0x13, - 0x65, 0x05, 0x07, 0xef, 0xf0, 0x9f, 0xe0, 0xaa, 0x84, 0x63, 0x16, 0x25, 0x25, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, - 0xff, 0xef, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xbf, 0xde, 0xfa, - 0xa1, 0x58, 0x5b, 0x85, 0x9b, 0x13, 0x77, 0xa0, 0x34, 0x49, 0x8a, 0x35, 0xce, 0x8d, 0x6c, 0x1e, 0xcb, 0x01, 0x16, - 0x19, 0x0f, 0xb2, 0xe1, 0x0f, 0xf1, 0x55, 0xf2, 0xf9, 0xa4, 0x84, 0x9e, 0x88, 0xf8, 0x44, 0x2a, 0x89, 0x63, 0x17, - 0x95, 0x22, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x9f, 0xdd, 0xaa, 0x84, 0x63, 0x1e, 0x25, - 0x21, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x7f, 0xdc, 0x63, 0x16, 0x95, 0x20, 0x48, 0x44, - 0x93, 0x07, 0x00, 0x10, 0x23, 0x2c, 0xfa, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x15, 0x00, 0xef, 0xf0, 0xff, 0xda, 0x93, - 0x07, 0xa0, 0x0a, 0xaa, 0x84, 0x63, 0x17, 0xf5, 0x1e, 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, - 0x25, 0x01, 0xef, 0xf0, 0x5f, 0xd9, 0xaa, 0x89, 0x63, 0x1c, 0x95, 0x1c, 0xef, 0xf0, 0x7f, 0xd4, 0x48, 0x44, 0x7e, - 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xff, 0xd7, 0xaa, 0x84, 0x63, 0x11, 0x35, 0x1d, 0x13, 0x05, 0x00, 0x04, - 0xef, 0xf0, 0x5f, 0xe7, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x1f, - 0xd6, 0xaa, 0x89, 0x63, 0x12, 0x95, 0x1a, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xff, 0xd4, - 0xaa, 0x84, 0x63, 0x19, 0x35, 0x19, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xdf, 0xd3, 0xaa, - 0x89, 0x63, 0x10, 0x95, 0x18, 0x08, 0x40, 0x05, 0x05, 0xef, 0xf0, 0xdf, 0xd1, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, - 0x05, 0x17, 0xef, 0xf0, 0x3f, 0xd2, 0xaa, 0x84, 0x63, 0x13, 0x35, 0x17, 0x48, 0x44, 0x7e, 0x05, 0x33, 0x65, 0x25, - 0x01, 0xef, 0xf0, 0xfa, 0xed, 0x2d, 0xa7, 0x6f, 0xa4, 0xa0, 0x5f, 0x57, 0x98, 0x80, 0x55, 0x1e, 0x24, 0x63, 0xb1, - 0xa5, 0x10, 0x5d, 0xcf, 0xee, 0x04, 0x8f, 0xd9, 0xb7, 0x95, 0xa9, 0x55, 0x2b, 0x89, 0x4c, 0x8b, 0x32, 0xd0, 0x45, - 0x1f, 0xd1, 0x2a, 0x89, 0x63, 0x1a, 0x95, 0x14, 0xef, 0xf0, 0x3f, 0xcc, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, - 0x07, 0xef, 0xf0, 0xbf, 0xcf, 0xaa, 0x84, 0x63, 0x1f, 0x25, 0x13, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x1f, 0xdf, - 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xcd, 0x63, 0x11, 0x95, - 0x12, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xdf, 0xcc, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, - 0x63, 0x16, 0xf5, 0x10, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x7f, 0xcb, 0xaa, 0x84, 0x63, - 0x1d, 0x25, 0x0f, 0x13, 0x05, 0x10, 0x02, 0xef, 0xf0, 0xdf, 0xda, 0x1c, 0x40, 0x48, 0x44, 0x21, 0x67, 0x83, 0xc7, - 0x07, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xd9, 0x8f, 0x23, 0x20, 0xfa, 0x02, 0xef, 0xf0, 0xff, 0xc8, 0xaa, - 0x89, 0x63, 0x19, 0x95, 0x0c, 0x48, 0x44, 0x89, 0x64, 0x8d, 0x04, 0x7e, 0x05, 0x45, 0x8d, 0xef, 0xf0, 0xbf, 0xc7, - 0x2a, 0x89, 0x63, 0x1f, 0x35, 0x0b, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x9f, 0xc6, 0xaa, - 0x89, 0x63, 0x16, 0x25, 0x0b, 0x08, 0x40, 0x13, 0x05, 0x15, 0x02, 0xef, 0xf0, 0x7f, 0xc4, 0x48, 0x44, 0x7e, 0x05, - 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xc4, 0x2a, 0x89, 0x63, 0x18, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, 0x45, - 0x8d, 0xef, 0xf0, 0xdf, 0xc3, 0xaa, 0x84, 0xfa, 0x4a, 0xaf, 0xa3, 0x8f, 0x01, 0x30, 0xd2, 0x01, 0x38, 0x63, 0x38, - 0xa3, 0x75, 0x5a, 0xf7, 0xf1, 0x6e, 0x45, 0x10, 0xa7, 0x86, 0x73, 0x14, 0xa3, 0x85, 0x35, 0xf5, 0x8e, 0xe7, 0xab, - 0xd8, 0x38, 0xa8, 0x46, 0x63, 0x10, 0x25, 0x09, 0xef, 0xf0, 0xff, 0xbe, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, - 0x07, 0xef, 0xf0, 0x7f, 0xc2, 0x2a, 0x89, 0x63, 0x15, 0x95, 0x06, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0xdf, 0xd1, - 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x9f, 0xc0, 0xaa, 0x84, 0x63, - 0x16, 0x25, 0x05, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x7f, 0xbf, 0x63, 0x1e, 0x95, 0x02, - 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x52, 0xef, 0xf0, 0x7f, 0xbe, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x14, 0xf5, - 0x02, 0x08, 0x40, 0x62, 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0xb7, 0x05, 0x00, 0x04, - 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x06, 0x13, 0x05, 0x15, 0x06, 0x05, 0x61, 0x6f, 0xe0, 0x6f, 0xb0, 0xf2, - 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x4e, 0xc6, - 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x52, 0xc4, 0x93, 0x09, 0x00, 0x04, 0x63, 0xe8, 0xb9, 0x08, 0x37, - 0x3a, 0x20, 0x00, 0xaa, 0x84, 0x2e, 0x84, 0x13, 0x09, 0x0a, 0xea, 0xef, 0xf0, 0x7f, 0xc1, 0x03, 0x25, 0xc9, 0x00, - 0x13, 0x0a, 0x0a, 0xea, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x3f, 0xb7, 0x13, 0x85, 0x04, 0x02, 0x63, - 0x19, 0x34, 0x03, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x05, 0xfa, 0x85, 0x36, 0x11, 0xae, 0x38, 0x42, 0x9f, - 0x47, 0x69, 0xbd, 0x6a, 0x8a, 0x78, 0xc6, 0x55, 0xe9, 0x29, 0x96, 0xb0, 0xa5, 0xc9, 0x3f, 0xd7, 0x66, 0x82, 0x57, - 0xdf, 0xfe, 0x44, 0xe0, 0x79, 0xaa, 0x80, 0x47, 0x05, 0x02, 0x13, 0x06, 0x00, 0x02, 0xef, 0xe0, 0x4f, 0xb2, 0x03, - 0x25, 0xc9, 0x00, 0x62, 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x7e, 0x05, 0x13, 0x65, - 0x05, 0x17, 0x05, 0x61, 0x6f, 0xf0, 0xdf, 0xb3, 0xfd, 0x47, 0x63, 0xf5, 0x87, 0x02, 0x93, 0x05, 0x04, 0xfe, 0xef, - 0xf0, 0x1f, 0xbc, 0x13, 0x04, 0x04, 0x04, 0x93, 0x17, 0xb4, 0x00, 0x37, 0x07, 0xff, 0x00, 0xf9, 0x8f, 0x6e, 0x04, - 0x3e, 0x94, 0xb7, 0x07, 0x00, 0x04, 0x03, 0x25, 0xca, 0x00, 0xc0, 0xdf, 0x7d, 0xbf, 0x01, 0x45, 0xef, 0xf0, 0xff, - 0xa9, 0xf1, 0xbf, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, - 0x01, 0x11, 0x22, 0xcc, 0x37, 0x34, 0x20, 0x00, 0x93, 0x07, 0x04, 0xea, 0x52, 0xc4, 0x2a, 0x8a, 0xc8, 0x47, 0x56, - 0xc2, 0x06, 0xce, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x30, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xae, 0x8a, 0xef, 0xf0, - 0x1f, 0xad, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x11, 0xf5, 0x12, 0xaa, 0x84, 0x13, 0x05, 0x60, 0x03, 0xef, 0xf0, 0x3f, - 0xa5, 0x13, 0x04, 0x04, 0xea, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x45, 0x00, 0xef, 0xf0, 0xff, 0xaa, 0x2a, 0x89, - 0x63, 0x11, 0x95, 0x10, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xa9, 0xaa, 0x84, 0x63, - 0x18, 0x25, 0x0f, 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xfa, 0xda, 0x79, 0x25, - 0x60, 0xe6, 0x40, 0xc1, 0x60, 0x3a, 0x85, 0xd0, 0xb5, 0x2e, 0x51, 0x70, 0x6d, 0x82, 0x7a, 0x5c, 0x25, 0xf8, 0xb2, - 0xe1, 0xe0, 0xca, 0x5d, 0x28, 0x61, 0xc9, 0x5f, 0x7a, 0x81, 0x58, 0x48, 0xef, 0xf0, 0x7f, 0xa8, 0xaa, 0x89, 0x63, - 0x1d, 0x95, 0x0c, 0xd6, 0x85, 0x52, 0x85, 0xef, 0xf0, 0x3f, 0xed, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, - 0xef, 0xf0, 0xdf, 0xa6, 0xaa, 0x84, 0x63, 0x10, 0x35, 0x0d, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x03, 0xef, - 0xf0, 0xbf, 0xa5, 0xaa, 0x89, 0x63, 0x17, 0x95, 0x0a, 0x13, 0x05, 0xc0, 0x05, 0xef, 0xf0, 0x1f, 0x9e, 0x48, 0x44, - 0x7e, 0x05, 0x13, 0x65, 0x45, 0x00, 0xef, 0xf0, 0x1f, 0xa4, 0xaa, 0x84, 0x63, 0x1a, 0x35, 0x09, 0x48, 0x44, 0x7e, - 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xff, 0xa2, 0xaa, 0x89, 0x63, 0x11, 0x95, 0x08, 0x48, 0x44, 0x7e, 0x05, - 0x13, 0x65, 0x05, 0x32, 0xef, 0xf0, 0xdf, 0xa1, 0xaa, 0x84, 0x63, 0x18, 0x35, 0x07, 0x48, 0x44, 0x7e, 0x05, 0x33, - 0x65, 0x25, 0x01, 0xef, 0xf0, 0xbf, 0xa0, 0x63, 0x10, 0x95, 0x06, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x03, - 0xef, 0xf0, 0xbf, 0x9f, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0x63, 0x15, 0xf5, 0x04, 0x13, 0x05, 0x00, 0x06, 0xef, - 0xf0, 0xdf, 0xae, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0x9d, 0xaa, 0x84, 0x63, 0x18, - 0x25, 0x03, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xbf, 0x9c, 0x63, 0x10, 0x95, 0x02, 0x48, - 0x44, 0x62, 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x7e, 0x05, 0x13, 0x65, - 0xfa, 0x8c, 0x67, 0xa4, 0x02, 0x05, 0xd6, 0x25, 0x26, 0x1e, 0x6f, 0x9e, 0xc2, 0x5a, 0x97, 0x1b, 0x94, 0xf3, 0x3e, - 0xdb, 0xf5, 0xc8, 0x08, 0x9f, 0x5f, 0xa2, 0xb4, 0xb3, 0x72, 0x65, 0x2c, 0x48, 0x63, 0x30, 0x49, 0x05, 0x02, 0x05, - 0x61, 0x6f, 0xf0, 0xbf, 0x9a, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, - 0x05, 0x61, 0x82, 0x80, 0x39, 0x71, 0x22, 0xdc, 0x37, 0x34, 0x20, 0x00, 0x06, 0xde, 0x4a, 0xd8, 0x26, 0xda, 0x32, - 0x89, 0x13, 0x04, 0x04, 0xea, 0xef, 0xf0, 0xdf, 0xe8, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x40, 0xef, 0xf0, - 0x5f, 0x97, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x0a, 0xaa, 0x84, 0x37, 0x65, 0x10, 0x00, 0x85, 0x45, 0x13, - 0x05, 0xc5, 0x80, 0xef, 0xf0, 0x9f, 0xe6, 0x85, 0x47, 0x63, 0x07, 0xf9, 0x08, 0x48, 0x44, 0x85, 0x67, 0x93, 0x87, - 0x07, 0x80, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0x7f, 0x94, 0x2a, 0x89, 0x63, 0x1c, 0x95, 0x06, 0xb7, 0x05, 0x00, - 0x04, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x04, 0x68, 0x00, 0xef, 0xe0, 0xaf, 0x87, 0x48, 0x44, 0x89, 0x47, - 0x23, 0x06, 0xf1, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x20, 0xef, 0xf0, 0xdf, 0x91, 0xaa, 0x84, 0x63, 0x17, 0x25, - 0x05, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xbf, 0x90, 0x2a, 0x89, 0x63, 0x1e, 0x95, 0x02, - 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x42, 0xef, 0xf0, 0x9f, 0x8f, 0xaa, 0x84, 0x63, 0x15, 0x25, 0x03, 0x68, - 0x00, 0x93, 0x05, 0x10, 0x02, 0xef, 0xf0, 0x5f, 0xdf, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x10, 0xef, 0xf0, - 0xdf, 0x8d, 0x63, 0x18, 0xfa, 0xaa, 0xed, 0xee, 0x51, 0xc9, 0x70, 0x31, 0x26, 0xa4, 0x37, 0x0b, 0xc8, 0xf7, 0xea, - 0x4e, 0x7c, 0x02, 0x81, 0xa8, 0xa3, 0x9b, 0x49, 0x8c, 0xbc, 0x32, 0x0e, 0xc5, 0x56, 0x9e, 0x18, 0x8e, 0x95, 0x08, - 0x4a, 0x95, 0x00, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xdf, 0x8c, 0xf2, 0x50, 0x62, 0x54, - 0xd2, 0x54, 0x42, 0x59, 0x21, 0x61, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, - 0xea, 0x08, 0x40, 0x09, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x06, 0xc6, 0xef, 0xf0, 0xff, 0xf0, - 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x71, 0xef, 0xf0, 0x7f, 0x89, 0x48, 0x44, 0x22, 0x44, 0xb2, 0x40, 0x7e, - 0x05, 0x13, 0x65, 0x05, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x5f, 0x88, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x07, 0xea, - 0x05, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x6f, 0xf0, 0xbf, 0xed, 0x41, 0x11, 0xb7, 0x65, 0x10, - 0x00, 0x37, 0x05, 0x00, 0x04, 0x22, 0xc4, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x45, 0x81, 0x13, 0x05, 0x05, 0x02, - 0x37, 0x34, 0x20, 0x00, 0x06, 0xc6, 0x13, 0x04, 0x04, 0xea, 0xef, 0xe0, 0x4f, 0x81, 0x48, 0x44, 0x7e, 0x05, 0x13, - 0x65, 0x05, 0x07, 0xef, 0xf0, 0xdf, 0x83, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x1d, 0xf5, 0x00, 0x08, 0x40, 0x22, 0x44, - 0xb2, 0x40, 0x05, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xe8, 0xb2, - 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, 0xea, - 0x48, 0x44, 0x06, 0xc6, 0x7e, 0x05, 0x13, 0x65, 0xfa, 0x1d, 0x57, 0x77, 0xd2, 0x00, 0x60, 0x5b, 0xed, 0x97, 0x49, - 0x7b, 0x00, 0xd1, 0xb3, 0xa6, 0x21, 0x55, 0x28, 0x4b, 0xed, 0x61, 0x3d, 0x8d, 0x64, 0x02, 0x6b, 0x24, 0x11, 0x2c, - 0x09, 0x5f, 0xee, 0xe0, 0x4a, 0x05, 0x04, 0xef, 0xf0, 0xcf, 0xff, 0x08, 0x40, 0x13, 0x06, 0x00, 0x02, 0x81, 0x45, - 0x13, 0x05, 0x15, 0x04, 0xef, 0x00, 0x90, 0x62, 0x08, 0x40, 0x09, 0x46, 0x81, 0x45, 0x13, 0x05, 0x15, 0x04, 0xef, - 0xf0, 0xbf, 0xe4, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x60, 0xef, 0xf0, 0x2f, 0xfd, 0x48, 0x44, 0x7e, 0x05, - 0x13, 0x65, 0x05, 0x71, 0xef, 0xf0, 0x6f, 0xfc, 0x01, 0x45, 0xef, 0xf0, 0x4f, 0xf5, 0x48, 0x44, 0x7e, 0x05, 0x13, - 0x65, 0x05, 0x07, 0xef, 0xf0, 0x4f, 0xfb, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x8f, 0xfa, - 0xb2, 0x40, 0x22, 0x44, 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, 0x98, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x11, 0x65, 0xd5, - 0xa1, 0x37, 0x35, 0x20, 0x00, 0x41, 0x11, 0x51, 0x46, 0x81, 0x45, 0x13, 0x05, 0x05, 0xea, 0x06, 0xc6, 0xef, 0x00, - 0xd0, 0x5b, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x1d, 0x65, 0x23, 0xa6, 0xe7, 0xfa, 0x55, 0x29, 0xb2, - 0x40, 0xb7, 0x07, 0x00, 0x04, 0x05, 0x47, 0x98, 0xcb, 0x41, 0x01, 0x6f, 0xf0, 0xdf, 0xfc, 0x11, 0x65, 0x45, 0xa1, - 0x41, 0x11, 0x26, 0xc2, 0x4a, 0xc0, 0x06, 0xc6, 0x22, 0xc4, 0x2a, 0x89, 0xae, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0xdf, - 0xfa, 0x95, 0x47, 0x13, 0x05, 0x50, 0x05, 0x63, 0xe6, 0x97, 0x02, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, 0xea, - 0xb7, 0x65, 0x10, 0x00, 0x04, 0xc4, 0x93, 0x85, 0x85, 0x83, 0x8a, 0x04, 0xfa, 0x85, 0xe2, 0xb8, 0x46, 0xe3, 0x24, - 0x14, 0x4c, 0xa4, 0x05, 0x16, 0x8a, 0x04, 0x3c, 0x95, 0xc0, 0x53, 0x65, 0x64, 0x1f, 0x9d, 0x09, 0x21, 0xdc, 0xa6, - 0x2e, 0x1d, 0xc3, 0xa0, 0xca, 0x39, 0xf1, 0xb8, 0x4b, 0x85, 0x47, 0xae, 0x94, 0x5c, 0xc0, 0x9c, 0x40, 0x23, 0x20, - 0x24, 0x01, 0x82, 0x97, 0x08, 0x48, 0x23, 0x22, 0x04, 0x00, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, - 0x01, 0x82, 0x80, 0x05, 0xe1, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0xef, 0xb0, 0x3f, 0xf6, 0xb7, 0x05, 0x00, 0x04, - 0x32, 0x45, 0xf2, 0x40, 0x41, 0x46, 0x93, 0x85, 0x05, 0x08, 0x05, 0x61, 0x6f, 0xd0, 0x7f, 0xe3, 0xb7, 0x05, 0x00, - 0x04, 0x41, 0x46, 0x93, 0x85, 0x05, 0x08, 0xcd, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x85, 0x47, 0x2a, 0x84, - 0x63, 0xf4, 0xa7, 0x00, 0xef, 0xb0, 0x1f, 0xf3, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xea, 0xc8, 0x47, 0x46, - 0x04, 0xb2, 0x40, 0x7e, 0x05, 0x49, 0x8c, 0x21, 0x65, 0x15, 0x05, 0x41, 0x8d, 0x22, 0x44, 0x09, 0x47, 0xd8, 0xc3, - 0x41, 0x01, 0x6f, 0xf0, 0x8f, 0xea, 0x39, 0x71, 0x22, 0xdc, 0x56, 0xd2, 0x5a, 0xd0, 0x06, 0xde, 0x26, 0xda, 0x4a, - 0xd8, 0x4e, 0xd6, 0x52, 0xd4, 0x5e, 0xce, 0x62, 0xcc, 0x66, 0xca, 0x6a, 0xc8, 0x2a, 0x84, 0x2e, 0x8b, 0xb2, 0x8a, - 0x99, 0xe1, 0xef, 0xb0, 0x7f, 0xee, 0xb7, 0x0b, 0x00, 0x04, 0xb7, 0x39, 0x20, 0x00, 0x05, 0x6c, 0x81, 0x44, 0x01, - 0x49, 0xc1, 0x4c, 0x93, 0x8b, 0x0b, 0x02, 0x93, 0x89, 0x09, 0xea, 0x09, 0x0c, 0x37, 0x3d, 0x20, 0x00, 0xb3, 0x05, - 0x9b, 0x00, 0x63, 0xe0, 0x54, 0x03, 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, 0xfa, 0x32, 0x99, - 0xeb, 0x80, 0x68, 0x41, 0x51, 0x0e, 0xfc, 0xd9, 0x46, 0x59, 0xb1, 0x28, 0x05, 0xe8, 0x4f, 0xc9, 0x5a, 0xce, 0x7f, - 0xaf, 0xea, 0x6b, 0x81, 0x9a, 0x27, 0x0a, 0x99, 0x00, 0x3b, 0x79, 0x90, 0x4c, 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, - 0xf2, 0x4b, 0x62, 0x4c, 0xd2, 0x4c, 0x42, 0x4d, 0x21, 0x61, 0x82, 0x80, 0x33, 0x8a, 0x9a, 0x40, 0x63, 0xd3, 0x4c, - 0x01, 0x41, 0x4a, 0x4a, 0x85, 0x2e, 0xc6, 0xef, 0xe0, 0xcf, 0x8d, 0xb2, 0x45, 0x13, 0x06, 0x3a, 0x00, 0x71, 0x9a, - 0x5e, 0x85, 0xef, 0xd0, 0xdf, 0xde, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x2f, - 0xe1, 0x03, 0xa5, 0xc9, 0x00, 0x93, 0x17, 0x8a, 0x01, 0x7e, 0x05, 0x5d, 0x8d, 0x13, 0x65, 0x75, 0x00, 0xef, 0xf0, - 0xef, 0xdf, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x33, 0x65, 0x85, 0x01, 0xef, 0xf0, 0x0f, 0xdf, 0x03, 0x27, 0xcd, - 0xfa, 0x93, 0x07, 0x50, 0x05, 0x63, 0x19, 0xf7, 0x00, 0x19, 0xc4, 0x22, 0x85, 0x52, 0x86, 0xca, 0x85, 0xef, 0xe0, - 0x6f, 0x91, 0x41, 0x04, 0x93, 0x07, 0x00, 0x07, 0x63, 0xe3, 0x27, 0x01, 0x41, 0x09, 0xc1, 0x04, 0x9d, 0xb7, 0x39, - 0x71, 0x26, 0xda, 0x52, 0xd4, 0x56, 0xd2, 0x06, 0xde, 0x22, 0xdc, 0x4a, 0xd8, 0x4e, 0xd6, 0x5a, 0xd0, 0x5e, 0xce, - 0x62, 0xcc, 0x66, 0xca, 0x6a, 0xc8, 0x6e, 0xc6, 0xaa, 0x8a, 0xae, 0x84, 0x32, 0x8a, 0x19, 0xe1, 0xef, 0xb0, 0x5f, - 0xe0, 0xb7, 0x39, 0x20, 0x00, 0x37, 0x0b, 0x02, 0x00, 0x85, 0x6b, 0x01, 0x49, 0x81, 0x4d, 0x37, 0x3c, 0x20, 0x00, - 0x41, 0x4d, 0x93, 0x89, 0x09, 0xea, 0x1d, 0x0b, 0x93, 0x8b, 0x0b, 0x82, 0xb3, 0x8c, 0x2a, 0x01, 0x93, 0x07, 0xcc, - 0xfa, 0xfa, 0xc2, 0x2e, 0x87, 0x0b, 0x0b, 0x24, 0x00, 0xc1, 0xac, 0x51, 0x20, 0x80, 0x05, 0xd6, 0x0c, 0xc2, 0xad, - 0x72, 0xb6, 0x28, 0x2f, 0x63, 0x5d, 0x82, 0xe7, 0x66, 0xe4, 0x6e, 0x03, 0x2d, 0x74, 0xf2, 0x68, 0x4d, 0x63, 0x64, - 0x49, 0x03, 0xf2, 0x50, 0x62, 0x54, 0x13, 0x07, 0x50, 0x05, 0x98, 0xc3, 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, 0x22, - 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, 0xd2, 0x4c, 0x42, 0x4d, 0xb2, 0x4d, 0x21, 0x61, 0x82, 0x80, - 0x33, 0x04, 0x2a, 0x41, 0x63, 0x73, 0x8d, 0x00, 0x41, 0x44, 0x6e, 0x85, 0xef, 0xd0, 0x9f, 0xff, 0xb7, 0x37, 0x20, - 0x00, 0x93, 0x87, 0xc7, 0xfa, 0x98, 0x43, 0x93, 0x07, 0x50, 0x05, 0x63, 0x19, 0xf7, 0x00, 0x99, 0xc4, 0x26, 0x85, - 0x22, 0x86, 0xee, 0x85, 0xef, 0xe0, 0x8f, 0x89, 0xc1, 0x04, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x25, - 0x00, 0xef, 0xf0, 0x4f, 0xd1, 0x03, 0xa5, 0xc9, 0x00, 0x93, 0x17, 0x84, 0x01, 0x0d, 0x04, 0x7e, 0x05, 0x5d, 0x8d, - 0x33, 0x65, 0x65, 0x01, 0xef, 0xf0, 0xef, 0xcf, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x33, 0x65, 0x75, 0x01, 0xef, - 0xf0, 0x0f, 0xcf, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x76, 0xc4, 0xff, 0x93, 0x85, 0x05, 0x04, 0x66, 0x85, 0xef, 0xd0, - 0xbf, 0xc2, 0x93, 0x07, 0x00, 0x06, 0x63, 0xe3, 0xb7, 0x01, 0xc1, 0x0d, 0x41, 0x09, 0x81, 0xbf, 0x41, 0x11, 0x22, - 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x7f, 0xd2, 0x21, 0x45, 0xef, 0xf0, 0xcf, 0xcb, 0x93, 0x07, - 0xa0, 0x0a, 0x63, 0x19, 0xf5, 0x00, 0x22, 0x85, 0xef, 0xf0, 0x9f, 0xda, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa2, 0x07, - 0xea, 0xb2, 0x40, 0x22, 0x44, 0xfa, 0x5a, 0x1e, 0x5e, 0x99, 0x27, 0x7b, 0xcc, 0xef, 0x08, 0x03, 0x1f, 0xf5, 0xb9, - 0x29, 0x2d, 0x3c, 0x1f, 0x24, 0x11, 0x0c, 0xa8, 0x3d, 0x1b, 0x93, 0x36, 0xa8, 0x19, 0xb0, 0xa3, 0x83, 0x8c, 0x8c, - 0x40, 0x4e, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa6, 0xa7, 0xfa, 0x82, 0x80, 0xb7, 0x07, 0x00, - 0x04, 0x13, 0x07, 0x60, 0x02, 0x98, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, 0x98, 0xc7, 0x82, 0x80, - 0xb7, 0x07, 0x00, 0x04, 0xc8, 0x4b, 0x82, 0x80, 0x39, 0x71, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x05, 0x47, 0xb7, - 0x07, 0x00, 0x04, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x42, 0xca, - 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xd8, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, - 0xea, 0xd8, 0x43, 0x89, 0x46, 0x7d, 0x17, 0x63, 0xfe, 0xe6, 0x02, 0x37, 0x65, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, - 0x05, 0x81, 0xef, 0xd0, 0x4f, 0xd1, 0xef, 0xc0, 0xaf, 0xd7, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, - 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, - 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x13, 0x07, 0xa0, 0x0a, 0x98, 0xcb, 0xd1, 0xbf, 0xb7, - 0x07, 0x01, 0x02, 0x88, 0xd7, 0xcc, 0xd7, 0x88, 0xdb, 0xcc, 0xdb, 0x88, 0xdf, 0xcc, 0xdf, 0x82, 0x80, 0x01, 0x11, - 0x26, 0xca, 0xb7, 0x04, 0x01, 0x02, 0x22, 0xcc, 0xc0, 0x40, 0xf5, 0x77, 0x93, 0x87, 0xf7, 0xa5, 0x7d, 0x8c, 0x89, - 0x67, 0x93, 0x87, 0x07, 0x1a, 0x06, 0xce, 0x4a, 0xc8, 0xfa, 0xfe, 0x95, 0x0f, 0x28, 0x63, 0x49, 0xd5, 0x45, 0x85, - 0x16, 0x0a, 0x6d, 0x94, 0x72, 0x31, 0x02, 0x77, 0xd3, 0xe3, 0x69, 0x76, 0x9b, 0x8a, 0x1d, 0x56, 0xca, 0xb2, 0xc4, - 0x35, 0xfb, 0xad, 0x0a, 0x18, 0x4f, 0x4e, 0xc6, 0xc1, 0x8f, 0xaa, 0x89, 0xdc, 0xc0, 0x05, 0x45, 0x2e, 0x89, 0xef, - 0xd0, 0x1f, 0x8a, 0x93, 0x67, 0x04, 0x40, 0xdc, 0xc0, 0x05, 0x45, 0xef, 0xd0, 0x5f, 0x89, 0x85, 0x67, 0x93, 0x87, - 0x07, 0x40, 0x5d, 0x8c, 0xc0, 0xc0, 0xb7, 0x47, 0x00, 0x08, 0x23, 0xa4, 0x07, 0x00, 0xb7, 0x57, 0x00, 0x08, 0x23, - 0xa4, 0x07, 0x00, 0xf2, 0x40, 0x62, 0x44, 0x23, 0xa0, 0x34, 0x03, 0x23, 0xa2, 0x24, 0x03, 0xb2, 0x49, 0xd2, 0x44, - 0x42, 0x49, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x02, 0x88, 0x53, 0xcc, 0x53, 0x82, 0x80, 0xb7, 0x07, 0x01, - 0x02, 0x88, 0x47, 0x21, 0x81, 0x13, 0x75, 0xf5, 0x0f, 0x82, 0x80, 0x41, 0x11, 0x01, 0x45, 0x81, 0x45, 0x06, 0xc6, - 0x22, 0xc4, 0x26, 0xc2, 0xef, 0xf0, 0x1f, 0xf6, 0xef, 0xf0, 0x9f, 0xfd, 0xaa, 0x84, 0x2e, 0x84, 0x2a, 0x87, 0xae, - 0x86, 0x37, 0x66, 0x10, 0x00, 0xb7, 0x65, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0x85, 0x85, 0x86, 0x13, 0x05, - 0x85, 0x77, 0x13, 0x06, 0x06, 0x85, 0xef, 0xd0, 0x0f, 0xba, 0xa2, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x26, 0x85, 0x92, - 0x44, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xf3, 0x39, 0x71, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, - 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, - 0xc2, 0x7e, 0xc0, 0xef, 0xf0, 0x7f, 0xf9, 0xef, 0xc0, 0x6f, 0xc4, 0xf2, 0x50, 0xfa, 0x71, 0x27, 0xc3, 0xef, 0x04, - 0xe7, 0x59, 0xc3, 0x58, 0x9d, 0xc8, 0xa9, 0x3d, 0x90, 0x7b, 0xa6, 0x4a, 0x60, 0xf5, 0x50, 0x66, 0x7e, 0xfb, 0xb1, - 0x56, 0xd9, 0x55, 0x9c, 0x90, 0x86, 0x26, 0xbd, 0xf0, 0x4f, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, - 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, - 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x07, 0x00, 0x02, 0x0d, 0x47, 0xf8, 0xcb, 0x13, 0x07, 0x30, - 0x03, 0xb8, 0xcf, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x5c, 0x47, 0xc9, 0x8f, 0x5c, 0xc7, 0x82, 0x80, 0xb7, 0x07, - 0x00, 0x02, 0xd8, 0x47, 0x13, 0x45, 0xf5, 0xff, 0x79, 0x8d, 0xc8, 0xc7, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, - 0x4f, 0xc9, 0x8f, 0x1c, 0xcf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0x98, 0x4f, 0x13, 0x45, 0xf5, 0xff, 0x79, 0x8d, - 0x88, 0xcf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0xc8, 0xcb, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, - 0xe7, 0x47, 0x00, 0x1c, 0xc7, 0xb7, 0x07, 0x00, 0x03, 0x94, 0x4b, 0x37, 0x37, 0x20, 0x00, 0x23, 0x28, 0xd7, 0xfa, - 0x23, 0xa8, 0x07, 0x00, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0xb7, 0x06, 0x00, 0x03, 0xf9, 0x9b, 0x1c, - 0xc7, 0x37, 0x07, 0x08, 0x00, 0x9c, 0x46, 0xf9, 0x8f, 0xf5, 0xff, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, - 0x93, 0xe7, 0x17, 0x00, 0x1c, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xfb, 0xb7, 0x07, 0x00, 0x03, 0x98, - 0xcb, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x47, 0xfb, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xfa, 0x41, - 0xa9, 0xc9, 0xc4, 0xef, 0x34, 0xb8, 0x57, 0x77, 0xf6, 0x7a, 0x01, 0x96, 0x57, 0x12, 0x89, 0xae, 0xdf, 0xcf, 0xa0, - 0x45, 0xe5, 0x03, 0x03, 0xa6, 0x58, 0x8d, 0x23, 0x03, 0x08, 0xaa, 0x5d, 0xc8, 0x50, 0xf5, 0x00, 0xb7, 0x27, 0x03, - 0x04, 0x9c, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x13, 0x05, - 0x00, 0x10, 0x6f, 0xf0, 0x3f, 0xf4, 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2a, 0xf7, 0xfa, 0x41, - 0x11, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2c, 0xf7, 0xfa, 0x06, 0xc6, 0xef, 0xf0, 0x1f, 0xfe, 0xb7, 0x27, 0x03, 0x04, - 0x09, 0x47, 0xd8, 0xc3, 0x37, 0x17, 0x03, 0x04, 0xb7, 0x07, 0x03, 0x04, 0x13, 0x07, 0x07, 0x80, 0x23, 0xa0, 0x07, - 0x00, 0x91, 0x07, 0xe3, 0x9d, 0xe7, 0xfe, 0xb7, 0x27, 0x03, 0x04, 0x0d, 0x47, 0xd8, 0xc7, 0x98, 0x47, 0x85, 0x47, - 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x13, - 0x05, 0x00, 0x10, 0x6f, 0xf0, 0xff, 0xee, 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2a, 0xf7, 0xfa, - 0x37, 0x37, 0x20, 0x00, 0x23, 0x2c, 0xf7, 0xfa, 0xb7, 0x27, 0x03, 0x04, 0x05, 0x47, 0xd8, 0xc3, 0x82, 0x80, 0xc2, - 0x05, 0xc9, 0x8d, 0x93, 0xe5, 0x05, 0x10, 0xb7, 0x07, 0x03, 0x04, 0x23, 0xa0, 0xb7, 0x10, 0x82, 0x80, 0xc2, 0x05, - 0xc9, 0x8d, 0x11, 0x65, 0x13, 0x05, 0x05, 0x50, 0xc9, 0x8d, 0xb7, 0x07, 0x03, 0x04, 0x23, 0xa0, 0xb7, 0x10, 0x82, - 0x80, 0xb7, 0x17, 0x03, 0x04, 0xbe, 0x95, 0x6f, 0xd0, 0x9f, 0x89, 0xb7, 0x07, 0x03, 0x04, 0x3e, 0x95, 0x6f, 0xd0, - 0xff, 0x90, 0xfa, 0xe4, 0xef, 0xa1, 0xf3, 0x44, 0x4e, 0xcc, 0x20, 0x2c, 0xbd, 0xfc, 0xe1, 0xaf, 0x97, 0x3d, 0x6c, - 0x2a, 0x94, 0x69, 0x54, 0xc5, 0x5d, 0x09, 0x72, 0x2a, 0x2e, 0x1f, 0x7f, 0xaf, 0x7c, 0x87, 0x9d, 0xa0, 0x51, 0xb7, - 0x95, 0x04, 0x00, 0x37, 0x55, 0x10, 0x00, 0x41, 0x11, 0x93, 0x85, 0x05, 0x3e, 0x13, 0x05, 0xa5, 0xcb, 0x06, 0xc6, - 0x22, 0xc4, 0xef, 0xd0, 0x6f, 0xe6, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0f, 0xf5, 0x00, 0x37, 0x65, 0x10, 0x00, 0x85, - 0x45, 0x13, 0x05, 0x05, 0x87, 0xef, 0xd0, 0xaf, 0x9f, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, - 0x82, 0x80, 0xb7, 0x17, 0x03, 0x04, 0x83, 0xa7, 0x07, 0x10, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x84, 0xfb, 0x93, - 0xf7, 0xf7, 0x0f, 0x81, 0xe7, 0x1c, 0x40, 0x63, 0x9d, 0xa7, 0x00, 0x37, 0x65, 0x10, 0x00, 0x8d, 0x45, 0x13, 0x05, - 0x05, 0x87, 0xef, 0xd0, 0x4f, 0x9c, 0x93, 0x07, 0xa0, 0x0a, 0x1c, 0xc0, 0xd1, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x03, - 0xa7, 0x47, 0xfb, 0x13, 0x84, 0x47, 0xfb, 0x63, 0x09, 0xa7, 0x00, 0x37, 0x65, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, - 0x05, 0x87, 0xef, 0xd0, 0xef, 0x99, 0x08, 0x40, 0x5d, 0xb7, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x3f, 0xf4, 0xef, - 0xf0, 0xff, 0xf0, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x1f, 0xf6, 0xb7, 0x17, 0x03, 0x04, 0x03, 0xa5, 0x07, 0x10, - 0x41, 0x81, 0x82, 0x80, 0x41, 0x11, 0x3a, 0xc4, 0x37, 0x27, 0x03, 0x04, 0x3e, 0xc2, 0x1c, 0x47, 0x36, 0xc6, 0x93, - 0xf6, 0x27, 0x00, 0x89, 0xca, 0x89, 0x46, 0x14, 0xc7, 0x37, 0x37, 0x20, 0x00, 0x93, 0x06, 0xa0, 0x0a, 0x23, 0x2a, - 0xd7, 0xfa, 0x91, 0x8b, 0x99, 0xcf, 0xfa, 0x5a, 0x7f, 0x1b, 0x15, 0x8c, 0x61, 0x80, 0xcd, 0x88, 0xec, 0xdf, 0x84, - 0x87, 0x06, 0x2e, 0x9d, 0x5b, 0x1f, 0x07, 0x39, 0xe8, 0x72, 0x20, 0x4e, 0xfe, 0xf8, 0x61, 0x27, 0xd1, 0x25, 0x7f, - 0x97, 0x78, 0x52, 0xb7, 0x27, 0x03, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x93, 0x07, 0xa0, 0x0a, 0x37, 0x37, 0x20, 0x00, - 0x23, 0x2c, 0xf7, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2a, 0xf7, 0xfa, 0xb2, 0x46, 0x22, 0x47, 0x92, 0x47, 0x41, - 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x04, 0x00, 0x03, 0x1c, 0x48, 0x06, 0xc6, 0xdd, 0x9b, - 0x1c, 0xc8, 0xef, 0xe0, 0xcf, 0xd1, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x02, 0x5c, 0xcc, 0xb2, 0x40, 0x22, - 0x44, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x80, 0x07, 0xfc, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x2a, 0x84, - 0x21, 0x45, 0x06, 0xc6, 0xef, 0xf0, 0x5f, 0xd8, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x5f, 0xd4, 0x22, 0x04, 0x13, - 0x64, 0x04, 0x03, 0x37, 0x07, 0x00, 0x03, 0x40, 0xc3, 0xb2, 0x40, 0x22, 0x44, 0xc1, 0x67, 0x93, 0x87, 0xa7, 0xfa, - 0x1c, 0xcf, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xaa, 0x84, 0x2e, 0x84, 0x19, - 0xe1, 0xef, 0xb0, 0x5f, 0x83, 0x19, 0xe0, 0xef, 0xb0, 0xff, 0x82, 0x09, 0x45, 0xef, 0xf0, 0x5f, 0xfb, 0x37, 0x07, - 0x20, 0x00, 0xb7, 0x07, 0x00, 0x03, 0x13, 0x07, 0x07, 0x02, 0xd8, 0xcf, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2e, 0x97, - 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x22, 0x87, 0xfc, 0xb2, 0x40, 0x22, 0x44, 0x05, 0x47, 0x98, 0xcb, 0x37, 0x07, - 0x08, 0x00, 0x98, 0xc7, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xfa, 0x45, 0xa5, 0x87, 0xb4, 0x72, 0x67, 0x47, 0xde, - 0xe4, 0x8a, 0xbd, 0x58, 0xcf, 0x34, 0xe7, 0xd3, 0x25, 0x4a, 0x5b, 0xda, 0x12, 0xaa, 0xe6, 0x6f, 0x35, 0xc7, 0xd5, - 0x42, 0xc5, 0xac, 0x08, 0xc2, 0x50, 0x53, 0xb7, 0x07, 0x00, 0x03, 0x9c, 0x47, 0x37, 0x07, 0x04, 0x00, 0x13, 0x05, - 0xa0, 0x0a, 0xf9, 0x8f, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x37, 0x07, 0x00, 0x03, 0x5c, 0x53, 0x13, - 0x05, 0x50, 0x05, 0x93, 0x96, 0x07, 0x01, 0xc1, 0x82, 0xc1, 0x83, 0x63, 0x97, 0xf6, 0x00, 0x1c, 0x47, 0x91, 0x8b, - 0x99, 0xe3, 0x13, 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x3f, 0xf1, 0x37, 0x07, 0x00, - 0x03, 0x5c, 0x47, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc7, 0x5c, 0x47, 0x85, 0x8b, 0xf5, 0xff, 0xb2, 0x40, 0x41, 0x01, - 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xfc, 0x95, 0xc3, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x9f, - 0xee, 0xb7, 0x07, 0x00, 0x03, 0x98, 0x4b, 0xb2, 0x40, 0x13, 0x67, 0x87, 0x00, 0x98, 0xcb, 0x37, 0x07, 0x08, 0x00, - 0x98, 0xc7, 0x41, 0x01, 0x6f, 0xe0, 0xcf, 0xbd, 0x82, 0x80, 0x37, 0x07, 0x00, 0x03, 0x1c, 0x4b, 0xf9, 0x9b, 0x1c, - 0xcb, 0x82, 0x80, 0xb7, 0x06, 0x00, 0x03, 0xdc, 0x42, 0x7d, 0x77, 0x13, 0x07, 0xf7, 0x0f, 0xf9, 0x8f, 0x05, 0x67, - 0x22, 0x05, 0x13, 0x07, 0x07, 0xf0, 0x79, 0x8d, 0x5d, 0x8d, 0xc8, 0xc2, 0x82, 0x80, 0x1d, 0x71, 0x3a, 0xda, 0x37, - 0x07, 0x00, 0x03, 0x3e, 0xd8, 0x1c, 0x47, 0x86, 0xce, 0x96, 0xcc, 0x9a, 0xca, 0x9e, 0xc8, 0xa2, 0xc6, 0xa6, 0xc4, - 0xaa, 0xc2, 0xae, 0xc0, 0x32, 0xde, 0x36, 0xdc, 0x42, 0xd6, 0x46, 0xd4, 0x4a, 0xd2, 0xfa, 0x28, 0x33, 0xa4, 0xfd, - 0xf5, 0x53, 0x0f, 0x3b, 0xa8, 0x00, 0x78, 0x43, 0x8a, 0x49, 0xb3, 0x04, 0xe1, 0x30, 0xf4, 0x77, 0x1d, 0x9a, 0x9b, - 0xe2, 0x56, 0x44, 0x1e, 0x2f, 0xec, 0x7f, 0x07, 0x94, 0x28, 0x54, 0x4e, 0xd0, 0x72, 0xce, 0x76, 0xcc, 0x7a, 0xca, - 0x7e, 0xc8, 0x85, 0x8b, 0xa1, 0xc7, 0x04, 0x57, 0x11, 0x44, 0x37, 0x39, 0x20, 0x00, 0x83, 0x27, 0xc9, 0xfb, 0x13, - 0xf5, 0xf4, 0x0f, 0x7d, 0x14, 0x82, 0x97, 0xa1, 0x80, 0x6d, 0xf8, 0x36, 0x44, 0xf6, 0x40, 0xe6, 0x42, 0x56, 0x43, - 0xc6, 0x43, 0xa6, 0x44, 0x16, 0x45, 0x86, 0x45, 0x72, 0x56, 0xe2, 0x56, 0x52, 0x57, 0xc2, 0x57, 0x32, 0x58, 0xa2, - 0x58, 0x12, 0x59, 0x82, 0x59, 0x72, 0x4e, 0xe2, 0x4e, 0x52, 0x4f, 0xc2, 0x4f, 0x25, 0x61, 0x73, 0x00, 0x20, 0x30, - 0xb7, 0x37, 0x20, 0x00, 0x03, 0xc7, 0x07, 0xfc, 0x13, 0x84, 0x07, 0xfc, 0x05, 0xeb, 0xb7, 0x04, 0x00, 0x03, 0x37, - 0x39, 0x20, 0x00, 0x93, 0x09, 0xa0, 0x0a, 0x9c, 0x44, 0x91, 0x8b, 0xd5, 0xfb, 0x83, 0x27, 0x49, 0xfc, 0x68, 0x00, - 0x82, 0x97, 0x63, 0x0d, 0x35, 0x01, 0x85, 0x47, 0x23, 0x00, 0xf4, 0x00, 0xc1, 0x67, 0x93, 0x87, 0x07, 0x02, 0xdc, - 0xcc, 0x61, 0xbf, 0xef, 0xf0, 0x9f, 0xde, 0x49, 0xbf, 0xb2, 0x47, 0x9c, 0xd8, 0xd1, 0xbf, 0xb7, 0x07, 0xf0, 0xfe, - 0x37, 0x07, 0xf0, 0xff, 0x41, 0x11, 0xaa, 0x97, 0x7d, 0x17, 0x22, 0xc4, 0x06, 0xc6, 0xf9, 0x8f, 0x2a, 0x84, 0x99, - 0xc3, 0xef, 0xb0, 0x6f, 0xe6, 0x5c, 0x40, 0xb2, 0x40, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc0, 0x22, 0x44, 0x41, 0x01, - 0x82, 0x80, 0xb7, 0x07, 0xf0, 0xfe, 0x37, 0x07, 0xf0, 0xff, 0x41, 0x11, 0xaa, 0x97, 0x7d, 0x17, 0x22, 0xc4, 0xfa, - 0x16, 0x7f, 0x2b, 0x0e, 0x40, 0x4e, 0x3b, 0x27, 0xea, 0xba, 0x81, 0x47, 0x0f, 0x12, 0x02, 0x12, 0xfb, 0x7f, 0x19, - 0x60, 0x56, 0xce, 0x46, 0x2f, 0xe7, 0xfc, 0x70, 0x33, 0xf9, 0xab, 0x89, 0xbb, 0x00, 0x55, 0x06, 0xc6, 0xf9, 0x8f, - 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xb0, 0xaf, 0xe3, 0x5c, 0x40, 0xb2, 0x40, 0xf9, 0x9b, 0x5c, 0xc0, 0x22, 0x44, 0x41, - 0x01, 0x82, 0x80, 0xb7, 0x07, 0xf0, 0xfe, 0x37, 0x07, 0xf0, 0xff, 0x01, 0x11, 0xaa, 0x97, 0x7d, 0x17, 0x22, 0xcc, - 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0x06, 0xce, 0xf9, 0x8f, 0x2a, 0x84, 0x2e, 0x89, 0xb2, 0x84, 0xb6, 0x89, 0x99, - 0xc3, 0xef, 0xb0, 0x4f, 0xe0, 0x5c, 0x40, 0x13, 0xf6, 0x24, 0x00, 0xf2, 0x40, 0xf5, 0x9b, 0x5d, 0x8e, 0x50, 0xc0, - 0x23, 0x28, 0x34, 0x01, 0x23, 0x2a, 0x24, 0x01, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, - 0x80, 0xb7, 0x07, 0xf0, 0xfe, 0x37, 0x07, 0xf0, 0xff, 0x41, 0x11, 0xaa, 0x97, 0x7d, 0x17, 0x22, 0xc4, 0x26, 0xc2, - 0x06, 0xc6, 0xf9, 0x8f, 0x2a, 0x84, 0xae, 0x84, 0x99, 0xc3, 0xef, 0xb0, 0x2f, 0xdc, 0x5c, 0x44, 0xb2, 0x40, 0xb3, - 0xe5, 0x97, 0x00, 0x4c, 0xc4, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, - 0x87, 0xfc, 0x82, 0x80, 0x39, 0x71, 0x3a, 0xce, 0x37, 0x07, 0x10, 0x01, 0x3e, 0xcc, 0x1c, 0x47, 0x58, 0x47, 0x06, - 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, - 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xf9, 0x8f, 0x91, 0xcf, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x87, - 0xfc, 0x98, 0x43, 0xfa, 0x80, 0xc5, 0x27, 0x65, 0x52, 0x9a, 0xb6, 0x48, 0x63, 0x69, 0xd9, 0xfa, 0x17, 0x04, 0xd3, - 0xaf, 0x19, 0xff, 0x99, 0x6c, 0x71, 0xe7, 0xed, 0x93, 0xce, 0x5b, 0x34, 0x58, 0x95, 0xcf, 0xba, 0x61, 0xd8, 0x55, - 0x05, 0x07, 0x98, 0xc3, 0xb7, 0x07, 0x10, 0x01, 0x98, 0x47, 0x0d, 0x8b, 0x98, 0xc7, 0x19, 0xa8, 0xb7, 0x07, 0x20, - 0x01, 0x98, 0x47, 0xdc, 0x47, 0x7d, 0x8f, 0xb7, 0x07, 0x20, 0x01, 0x6d, 0xf7, 0xef, 0xb0, 0x9f, 0xe3, 0xf2, 0x50, - 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, - 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x1c, 0x41, - 0x63, 0xf7, 0xb7, 0x00, 0x23, 0x80, 0xc7, 0x00, 0x1c, 0x41, 0x85, 0x07, 0x1c, 0xc1, 0x82, 0x80, 0x1d, 0x71, 0xa2, - 0xcc, 0xa6, 0xca, 0xca, 0xc8, 0x86, 0xce, 0xce, 0xc6, 0xd2, 0xc4, 0xd6, 0xc2, 0xda, 0xc0, 0x5e, 0xde, 0x62, 0xdc, - 0x66, 0xda, 0x6a, 0xd8, 0x6e, 0xd6, 0x2a, 0xc6, 0x2e, 0x84, 0x32, 0x89, 0xb6, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x8f, - 0xce, 0x63, 0x14, 0x09, 0x00, 0xef, 0xb0, 0x0f, 0xce, 0x01, 0x45, 0x05, 0xc4, 0xb2, 0x4a, 0x7d, 0x14, 0x25, 0x4a, - 0x56, 0x94, 0x93, 0x0c, 0xc0, 0x06, 0x13, 0x0b, 0x30, 0x07, 0xa9, 0x4b, 0x1d, 0x4d, 0x03, 0x46, 0x09, 0x00, 0x15, - 0xe6, 0xb2, 0x47, 0x23, 0x80, 0x07, 0x00, 0x32, 0x45, 0x33, 0x05, 0x55, 0x41, 0xf6, 0x40, 0x66, 0x44, 0xd6, 0x44, - 0x46, 0x49, 0xb6, 0x49, 0x26, 0x4a, 0x96, 0x4a, 0x06, 0x4b, 0xf2, 0x5b, 0x62, 0x5c, 0xd2, 0x5c, 0x42, 0x5d, 0xb2, - 0x5d, 0x25, 0x61, 0x82, 0x80, 0x93, 0x07, 0xfa, 0x57, 0xa3, 0xe6, 0x67, 0xbf, 0xcf, 0x59, 0x48, 0x20, 0x86, 0x3b, - 0x75, 0xe9, 0x40, 0xab, 0xf8, 0x87, 0xc1, 0x0a, 0x7b, 0x1d, 0xfa, 0x92, 0x25, 0x34, 0xfb, 0x33, 0x02, 0x24, 0x6c, - 0x82, 0xe8, 0xb0, 0x56, 0x50, 0x02, 0x63, 0x1f, 0xf6, 0x02, 0x93, 0x07, 0x19, 0x00, 0x83, 0xc6, 0x07, 0x00, 0x3e, - 0x89, 0x85, 0x07, 0x13, 0x87, 0x06, 0xfd, 0x13, 0x77, 0xf7, 0x0f, 0xe3, 0x78, 0xea, 0xfe, 0x63, 0x93, 0x96, 0x01, - 0x3e, 0x89, 0x03, 0x46, 0x09, 0x00, 0x63, 0x06, 0x66, 0x0d, 0x63, 0x60, 0xcb, 0x02, 0x93, 0x07, 0x30, 0x06, 0x63, - 0x05, 0xf6, 0x06, 0x93, 0x07, 0x40, 0x06, 0x63, 0x0c, 0xf6, 0x06, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, 0xf2, - 0xa6, 0x89, 0x95, 0xa0, 0x93, 0x07, 0x50, 0x07, 0x63, 0x02, 0xf6, 0x06, 0x93, 0x07, 0x80, 0x07, 0xe3, 0x14, 0xf6, - 0xfe, 0x98, 0x40, 0x93, 0x89, 0x44, 0x00, 0x81, 0x46, 0x37, 0x06, 0x00, 0xf0, 0xb3, 0x75, 0xc7, 0x00, 0xba, 0x84, - 0x36, 0x8c, 0x12, 0x07, 0x85, 0x06, 0x89, 0xe5, 0xe3, 0x99, 0xa6, 0xff, 0x1d, 0x4c, 0xba, 0x84, 0xa1, 0x4d, 0x13, - 0xd7, 0xc4, 0x01, 0x63, 0x74, 0xea, 0x08, 0x13, 0x06, 0x77, 0x05, 0xa2, 0x85, 0x68, 0x00, 0x05, 0x0c, 0xef, 0xf0, - 0x1f, 0xee, 0x92, 0x04, 0xe3, 0x14, 0xbc, 0xff, 0x09, 0xa8, 0x03, 0xc6, 0x04, 0x00, 0xa2, 0x85, 0x68, 0x00, 0x93, - 0x89, 0x44, 0x00, 0xef, 0xf0, 0x9f, 0xec, 0x05, 0x09, 0xce, 0x84, 0x31, 0xbf, 0x5c, 0x08, 0x98, 0x40, 0x93, 0x89, - 0x44, 0x00, 0x3e, 0x8c, 0x81, 0x44, 0xb3, 0x76, 0x77, 0x03, 0x85, 0x04, 0x85, 0x07, 0x93, 0x86, 0x06, 0x03, 0xa3, - 0x8f, 0xd7, 0xfe, 0xba, 0x86, 0x33, 0x57, 0x77, 0x03, 0xe3, 0x65, 0xfa, 0x2c, 0x3a, 0xa7, 0xa5, 0x6c, 0x92, 0x08, - 0x82, 0x4e, 0x2d, 0xa7, 0x53, 0x29, 0xd2, 0xc8, 0xb6, 0x7d, 0xee, 0x93, 0x6b, 0xd9, 0xa9, 0xd2, 0x21, 0x11, 0x35, - 0xeb, 0x5a, 0x62, 0x3f, 0x68, 0xff, 0x88, 0x57, 0xda, 0xfe, 0xfd, 0x5d, 0xfd, 0x14, 0xe3, 0x88, 0xb4, 0xfd, 0xb3, - 0x07, 0x9c, 0x00, 0x03, 0xc6, 0x07, 0x00, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0x5f, 0xe8, 0xed, 0xb7, 0x93, 0x89, - 0x44, 0x00, 0x84, 0x40, 0x03, 0xc6, 0x04, 0x00, 0x45, 0xda, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, 0xe6, 0x85, - 0x04, 0xc5, 0xbf, 0x13, 0x06, 0x07, 0x03, 0xb5, 0xbf, 0x41, 0x11, 0x26, 0xc2, 0xb7, 0x34, 0x20, 0x00, 0x2a, 0x86, - 0xae, 0x86, 0x13, 0x85, 0x44, 0xeb, 0x93, 0x05, 0x00, 0x08, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0xf0, 0xbf, 0xe5, 0x2a, - 0x84, 0x13, 0x85, 0x44, 0xeb, 0xef, 0xd0, 0x6f, 0x8d, 0xb2, 0x40, 0x22, 0x85, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, - 0x82, 0x80, 0x39, 0x71, 0x26, 0xca, 0xb7, 0x34, 0x20, 0x00, 0x2e, 0xd2, 0x32, 0xd4, 0x36, 0xd6, 0x2a, 0x86, 0x54, - 0x10, 0x93, 0x05, 0x00, 0x08, 0x13, 0x85, 0x44, 0xeb, 0x06, 0xce, 0x22, 0xcc, 0x3a, 0xd8, 0x3e, 0xda, 0x42, 0xdc, - 0x46, 0xde, 0x36, 0xc6, 0xef, 0xf0, 0x9f, 0xe1, 0x2a, 0x84, 0x13, 0x85, 0x44, 0xeb, 0xef, 0xd0, 0x4f, 0x89, 0xf2, - 0x40, 0x22, 0x85, 0x62, 0x44, 0xd2, 0x44, 0x21, 0x61, 0x82, 0x80, 0x22, 0x05, 0x61, 0x77, 0x2d, 0x8d, 0xa1, 0x47, - 0x15, 0x07, 0x93, 0x16, 0x05, 0x01, 0x06, 0x05, 0x42, 0x05, 0xc1, 0x86, 0x41, 0x81, 0x63, 0xd5, 0x06, 0x00, 0x39, - 0x8d, 0x42, 0x05, 0x41, 0x81, 0xfd, 0x17, 0xe5, 0xf7, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0xfa, 0x9b, 0x16, 0xee, - 0x22, 0x46, 0x97, 0x65, 0x71, 0xa8, 0xe4, 0xd9, 0x16, 0xd9, 0x0e, 0xee, 0x9f, 0x36, 0x38, 0x18, 0xe1, 0xff, 0x86, - 0xc3, 0xb3, 0x78, 0x05, 0x94, 0x34, 0x32, 0xc0, 0x99, 0x75, 0x60, 0x58, 0x26, 0xc2, 0x06, 0xc6, 0x2a, 0x84, 0xae, - 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x8f, 0xad, 0xa2, 0x94, 0x01, 0x45, 0x63, 0x17, 0x94, 0x00, 0xb2, 0x40, 0x22, 0x44, - 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x04, 0xaa, 0x85, 0x03, 0x45, 0xf4, 0xff, 0xef, 0xf0, 0xff, 0xfa, 0xdd, - 0xb7, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x2a, 0x84, 0xae, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x6f, 0xaa, - 0xb7, 0x86, 0xb8, 0xed, 0x01, 0x47, 0xfd, 0x57, 0x93, 0x86, 0x06, 0x32, 0x63, 0x19, 0x97, 0x00, 0xb2, 0x40, 0x22, - 0x44, 0x92, 0x44, 0x13, 0xc5, 0xf7, 0xff, 0x41, 0x01, 0x82, 0x80, 0x33, 0x06, 0xe4, 0x00, 0x03, 0x46, 0x06, 0x00, - 0xb1, 0x8f, 0x21, 0x46, 0x93, 0xd5, 0x17, 0x00, 0x85, 0x8b, 0x91, 0xc3, 0xb6, 0x87, 0x7d, 0x16, 0xad, 0x8f, 0x6d, - 0xfa, 0x05, 0x07, 0xc1, 0xbf, 0x2a, 0x83, 0x09, 0xca, 0x83, 0x83, 0x05, 0x00, 0x23, 0x00, 0x73, 0x00, 0x7d, 0x16, - 0x05, 0x03, 0x85, 0x05, 0x6d, 0xfa, 0x82, 0x80, 0x15, 0xc2, 0x2a, 0x83, 0x85, 0x46, 0x63, 0x67, 0xb5, 0x00, 0xfd, - 0x56, 0x13, 0x07, 0xf6, 0xff, 0x3a, 0x93, 0xba, 0x95, 0x83, 0x83, 0x05, 0x00, 0x23, 0x00, 0x73, 0x00, 0x7d, 0x16, - 0x36, 0x93, 0xb6, 0x95, 0x6d, 0xfa, 0x82, 0x80, 0x2a, 0x83, 0x11, 0xc6, 0x23, 0x00, 0xb3, 0x00, 0x7d, 0x16, 0x05, - 0x03, 0x65, 0xfe, 0x82, 0x80, 0x00, 0x00, 0x63, 0x6f, 0x64, 0x65, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, - 0xfa, 0x17, 0x74, 0x9d, 0x62, 0x9b, 0x6c, 0x6d, 0x2e, 0x1a, 0xcc, 0xee, 0xec, 0x8b, 0x77, 0xc3, 0xae, 0xc9, 0xf5, - 0xaa, 0x6a, 0xa4, 0x07, 0xad, 0xc7, 0x6e, 0x25, 0x92, 0x33, 0x6f, 0x1d, 0xc8, 0x00, 0x38, 0x59, 0x53, 0x45, 0x43, - 0x43, 0x48, 0x4e, 0x4c, 0x00, 0x4d, 0x43, 0x4e, 0x54, 0x00, 0x00, 0x00, 0x00, 0x65, 0x6e, 0x61, 0x62, 0x6c, 0x65, - 0x64, 0x20, 0x25, 0x64, 0x00, 0x00, 0x4d, 0x41, 0x49, 0x4e, 0x00, 0x00, 0x00, 0x00, 0x54, 0x58, 0x3a, 0x20, 0x25, - 0x64, 0x2f, 0x25, 0x64, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x43, 0x4d, 0x44, 0x33, 0x00, 0x00, 0x00, 0x00, - 0x49, 0x00, 0x00, 0x00, 0x52, 0x58, 0x3a, 0x20, 0x63, 0x6d, 0x64, 0x3d, 0x30, 0x78, 0x25, 0x30, 0x32, 0x78, 0x2c, - 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x6c, 0x65, 0x6e, 0x20, 0x25, 0x64, 0x2f, 0x25, 0x64, 0x00, 0x00, 0x00, 0x72, 0x73, - 0x70, 0x3d, 0x25, 0x78, 0x00, 0x00, 0x73, 0x74, 0x61, 0x72, 0x74, 0x2c, 0x20, 0x76, 0x3a, 0x20, 0x25, 0x78, 0x00, - 0x00, 0x00, 0x00, 0x50, 0x52, 0x4f, 0x56, 0x49, 0x53, 0x49, 0x4f, 0x4e, 0x20, 0x4f, 0x4b, 0x00, 0x00, 0x00, 0x00, - 0x4e, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x43, 0x50, 0x42, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x4c, 0x33, 0x20, - 0x63, 0x6d, 0x64, 0x20, 0x25, 0x64, 0x3a, 0x20, 0x25, 0x78, 0x2c, 0x20, 0x6c, 0x65, 0x6e, 0x3a, 0x20, 0x25, 0x64, - 0x00, 0x00, 0x4c, 0x33, 0x20, 0x61, 0x63, 0x63, 0x65, 0x73, 0x73, 0x20, 0x66, 0x61, 0x69, 0x6c, 0x65, 0x64, 0x2c, - 0x20, 0x63, 0x6d, 0x64, 0x3a, 0x20, 0x25, 0x64, 0x2c, 0x20, 0x6c, 0x65, 0x6e, 0x3a, 0x20, 0x25, 0x64, 0x20, 0x00, - 0x73, 0x65, 0x6e, 0x74, 0xfa, 0x1e, 0x40, 0x64, 0x11, 0xd7, 0xae, 0x2d, 0x74, 0x47, 0x30, 0x45, 0x12, 0x4c, 0x2d, - 0x42, 0xf6, 0xc1, 0xd8, 0xf7, 0x9e, 0xee, 0x47, 0xe2, 0x78, 0xaf, 0x7e, 0x77, 0x4c, 0xb6, 0xf4, 0x88, 0xf3, 0x10, - 0x5a, 0x00, 0x00, 0x00, 0x00, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x20, 0x73, 0x6c, 0x65, 0x65, 0x70, 0x00, 0x77, 0x61, - 0x6b, 0x65, 0x75, 0x70, 0x00, 0x00, 0x9a, 0x19, 0x10, 0x00, 0xd8, 0x19, 0x10, 0x00, 0x04, 0x1a, 0x10, 0x00, 0x34, - 0x1a, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, - 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, - 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0x56, 0x1a, 0x10, 0x00, 0xb0, 0x1a, - 0x10, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 0x00, 0x06, 0x01, 0x00, 0x00, 0x01, 0x00, - 0x00, 0x00, 0x00, 0xa0, 0x1f, 0x00, 0x06, 0x02, 0x00, 0x05, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x06, - 0x03, 0x10, 0x08, 0x00, 0x00, 0x18, 0x00, 0x00, 0x40, 0x1f, 0x00, 0x06, 0x06, 0x10, 0x08, 0x00, 0x04, 0x18, 0x00, - 0x00, 0x60, 0x1f, 0x00, 0x06, 0x04, 0x00, 0x09, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x06, 0x05, 0x05, 0x7f, - 0x07, 0x01, 0x08, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xf0, 0x01, 0x10, 0x10, 0x00, 0x04, 0x02, 0x11, - 0x00, 0x44, 0x02, 0x12, 0x00, 0x84, 0x02, 0x20, 0x90, 0x01, 0x03, 0x21, 0x80, 0x42, 0x03, 0x22, 0xf0, 0x01, 0x03, - 0x30, 0x80, 0x02, 0x04, 0x31, 0x80, 0x42, 0x04, 0xfa, 0xe0, 0xa5, 0xe1, 0x65, 0x2d, 0xf8, 0x4c, 0xe4, 0x45, 0xd8, - 0x83, 0x04, 0xcb, 0x79, 0xbc, 0xd8, 0x9d, 0x20, 0x87, 0xd3, 0x32, 0x1e, 0xdc, 0x39, 0x04, 0xee, 0x7d, 0xc7, 0xca, - 0x24, 0xb1, 0x0c, 0xe8, 0x5a, 0x40, 0x70, 0x04, 0x11, 0x41, 0x70, 0x44, 0x11, 0x42, 0x70, 0x84, 0x11, 0x50, 0xf0, - 0x01, 0x12, 0x60, 0x32, 0x04, 0x13, 0x61, 0x32, 0x44, 0x13, 0x62, 0x32, 0x84, 0x13, 0x63, 0x32, 0xc4, 0x13, 0x70, - 0x32, 0x04, 0x14, 0x71, 0x32, 0x44, 0x14, 0x80, 0x20, 0x04, 0x15, 0x81, 0x20, 0x84, 0x15, 0x82, 0x20, 0x44, 0x15, - 0x90, 0x51, 0x04, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x0f, 0x00, 0x14, 0x04, 0x04, - 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x20, 0x25, 0x6c, 0x75, 0x20, - 0x00, 0x00, 0x25, 0x73, 0x28, 0x25, 0x73, 0x29, 0x3a, 0x20, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x45, - 0x00, 0x00, 0x00, 0x4d, 0x53, 0x47, 0x00, 0x43, 0x52, 0x43, 0x20, 0x72, 0x78, 0x3a, 0x20, 0x25, 0x30, 0x34, 0x78, - 0x2c, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x3a, 0x20, 0x25, 0x30, 0x34, 0x78, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, - 0x00, 0x40, 0x20, 0x10, 0x00, 0x60, 0x20, 0x10, 0x00, 0xb2, 0x20, 0x10, 0x00, 0x14, 0x21, 0x10, 0x00, 0x1e, 0x21, - 0x10, 0x00, 0x4f, 0x53, 0x00, 0x00, 0x63, 0x6f, 0x6e, 0x64, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, 0x43, - 0x50, 0x42, 0x20, 0x49, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x20, 0x21, 0x00, 0x43, 0x50, 0x42, 0x00, - 0x57, 0x00, 0x00, 0x00, 0x46, 0x53, 0x53, 0x00, 0x49, 0x52, 0x51, 0x00, 0xde, 0x1c, 0xcd, 0x5d, 0xca, 0x91, 0x43, - 0xe8, 0x98, 0x94, 0x67, 0x9b, 0xb6, 0x1c, 0xe9, 0xfd, 0xe2, 0x0f, 0x0b, 0x24, 0xb3, 0xd3, 0x05, 0x80, 0x73, 0xb5, - 0x2c, 0x0c, 0x64, 0x8e, 0xc8, 0x8a, 0x9d, 0xc0, 0x5b, 0x53, 0x54, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x4b, 0x44, - 0x42, 0x00, 0x73, 0x74, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x4d, 0x41, 0x44, 0x00, 0x4f, 0x54, 0x50, 0x00, 0x0c, - 0x18, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00, 0x10, 0x18, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, - 0x05, 0x0a, 0x0a, 0x0a, 0x14, 0x18, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x53, 0x43, 0x42, 0x00, 0x4e, 0x6f, - 0x69, 0x73, 0x65, 0x5f, 0x4b, 0x4b, 0x31, 0x5f, 0x32, 0x35, 0x35, 0x31, 0x39, 0x5f, 0x41, 0x45, 0x53, 0x47, 0x43, - 0x4d, 0x5f, 0x53, 0x48, 0x41, 0x32, 0x35, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0x40, 0x10, 0x00, - 0x74, 0x46, 0x10, 0x00, 0x5e, 0x46, 0x10, 0x00, 0x22, 0x46, 0x10, 0x00, 0x08, 0x3f, 0x10, 0x00, 0xcc, 0x46, 0x10, - 0x00, 0x41, 0x4c, 0x41, 0x52, 0x4d, 0x20, 0x43, 0x48, 0x41, 0x4e, 0x4e, 0x45, 0x4c, 0x53, 0x3a, 0x20, 0x25, 0x78, - 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x53, 0x43, 0x4e, 0x54, 0x52, 0x00, 0x00, 0x00, 0x53, 0x50, 0x45, 0x43, 0x54, - 0x00, 0x00, 0x00, 0xc3, 0x14, 0x13, 0x00, 0x72, 0xc3, 0xef, 0xde, 0x86, 0x6b, 0xc7, 0x13, 0x5f, 0xcb, 0x08, 0xbd, - 0xb0, 0x14, 0xfe, 0xc5, 0x27, 0x42, 0x86, 0x8d, 0x6c, 0xcc, 0xa0, 0xec, 0x25, 0x0e, 0x9f, 0x00, 0xe5, 0x55, 0x81, - 0xd2, 0xa5, 0xb0, 0x03, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xf4, 0x57, 0xf8, 0xba, 0x9d, 0x08, 0x11, 0x92, 0x11, 0x8c, - 0xd8, 0x04, 0xe7, 0x4a, 0xdf, 0x14, 0x73, 0x56, 0x8a, 0x35, 0x53, 0x18, 0xbc, 0x23, 0xb8, 0xbb, 0xb6, 0x0d, 0x70, - 0xff, 0x6a, 0x63, 0xd8, 0x02, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x7c, 0x58, - 0x00, 0x00, 0x61, 0xcd, 0x51, 0x19, 0x7d, 0xba, 0xf5, 0x9f, 0x7f, 0x51, 0x7a, 0x24, 0x53, 0x73, 0x22, 0xdb, 0x05, - 0x52, 0x40, 0x98, 0xbd, 0x5c, 0xbe, 0x7a, 0x8a, 0xe3, 0x67, 0x13, 0x46, 0x82, 0xf1, 0x09, 0x46, 0x0b, 0x4d, 0xb3, - 0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; \ No newline at end of file +const uint8_t fw_CPU[] = { + 0x68, 0xb3, 0xff, 0x2a, 0x22, 0x04, 0xa0, 0x0e, 0x0a, 0xae, 0x96, 0x07, 0x9f, 0x7a, 0x52, 0x12, + 0x2c, 0x19, 0x82, 0x79, 0xf5, 0xbf, 0x06, 0xb4, 0x64, 0xac, 0xf9, 0xce, 0x9d, 0x9f, 0x5d, 0x6a, + 0x9c, 0xa4, 0x92, 0xe6, 0x8e, 0x3b, 0xd1, 0x62, 0xfd, 0x49, 0xf0, 0x35, 0xda, 0x24, 0xd2, 0xde, + 0x89, 0x4e, 0xf0, 0x56, 0x8a, 0x10, 0xd2, 0x1e, 0x13, 0x97, 0xaa, 0x22, 0x5f, 0x6a, 0xb7, 0x52, + 0x00, 0xc1, 0xd1, 0x9e, 0x14, 0xd4, 0x87, 0x65, 0x66, 0x02, 0x81, 0x25, 0x9e, 0xa3, 0x93, 0x51, + 0x12, 0x6e, 0xcb, 0x9d, 0xd0, 0xc9, 0x36, 0xe1, 0x30, 0xad, 0x89, 0xe9, 0x6e, 0xed, 0xab, 0x66, + 0x69, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x62, 0xb6, 0xe3, 0x26, 0xc6, 0x32, 0x4d, + 0xe1, 0x92, 0x74, 0xe5, 0x66, 0x7b, 0xf2, 0xdd, 0x73, 0xde, 0xb0, 0xf2, 0x86, 0xc3, 0x6c, 0x58, + 0xc4, 0x9a, 0x0e, 0xd3, 0x9f, 0x6b, 0x50, 0xf5, 0x3b, 0xcb, 0x00, 0x00, 0xc0, 0xb8, 0xfe, 0xb5, + 0xef, 0xbc, 0x1c, 0xe1, 0xe1, 0x97, 0xd4, 0x28, 0xe4, 0x24, 0xc9, 0xe1, 0xb3, 0x4f, 0x66, 0x18, + 0x31, 0x8d, 0x09, 0xcd, 0x94, 0xe5, 0xaa, 0x5b, 0x29, 0x16, 0x2a, 0x59, 0x04, 0x73, 0x93, 0x0e, + 0x7a, 0x01, 0x6b, 0xad, 0xd2, 0xbe, 0x0e, 0xdd, 0x69, 0x01, 0x37, 0x81, 0x42, 0x8a, 0xda, 0x5c, + 0xad, 0xd4, 0x19, 0x94, 0x2f, 0x1e, 0x19, 0xc2, 0x93, 0xfe, 0xbf, 0x0d, 0xfa, 0xa4, 0xd5, 0x47, + 0xc2, 0xb4, 0xa2, 0xe2, 0xb2, 0x56, 0x38, 0xed, 0x8b, 0x01, 0xdf, 0xb8, 0x1d, 0x80, 0xfe, 0xe8, + 0xc9, 0x5d, 0xfb, 0x4c, 0x8b, 0x67, 0x4d, 0x22, 0x17, 0x2c, 0x81, 0xd3, 0xb2, 0x00, 0x04, 0x6f, + 0x30, 0x40, 0x44, 0x6f, 0x30, 0x60, 0x3e, 0x6f, 0x30, 0x20, 0x3e, 0x6f, 0x30, 0xe0, 0x3d, 0x6f, + 0x30, 0xa0, 0x3d, 0x6f, 0x30, 0x60, 0x3d, 0x6f, 0x30, 0x20, 0x3d, 0x6f, 0x50, 0x40, 0x18, 0x6f, + 0x30, 0xa0, 0x3c, 0x6f, 0x30, 0x60, 0x3c, 0x6f, 0x30, 0x20, 0x3c, 0x6f, 0x30, 0xb0, 0x00, 0x6f, + 0x30, 0xa0, 0x3b, 0x6f, 0x30, 0x60, 0x3b, 0x6f, 0x30, 0x20, 0x3b, 0x6f, 0x30, 0xe0, 0x3a, 0x6f, + 0x40, 0x30, 0x7c, 0x6f, 0x30, 0x60, 0x27, 0x6f, 0x30, 0x90, 0x2d, 0x6f, 0x40, 0x90, 0x37, 0x6f, + 0x40, 0x50, 0x37, 0x6f, 0x40, 0x10, 0x37, 0x6f, 0x30, 0xe0, 0x4d, 0x6f, 0x30, 0xe0, 0x4e, 0x6f, + 0x30, 0x70, 0x53, 0x6f, 0x40, 0xd0, 0x5e, 0x6f, 0x30, 0x60, 0x4f, 0x6f, 0x20, 0xf0, 0x21, 0x6f, + 0x40, 0xd0, 0x1f, 0x6f, 0x30, 0xe0, 0x4f, 0x6f, 0x30, 0x40, 0x5c, 0x6f, 0x30, 0x40, 0x40, 0x93, + 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x93, 0x01, 0x00, 0x00, 0x13, 0x02, 0x00, 0x00, 0x93, + 0x02, 0x00, 0x00, 0x13, 0x03, 0x00, 0x00, 0x93, 0x03, 0x00, 0x00, 0x13, 0x04, 0x00, 0x00, 0x93, + 0x04, 0x00, 0x00, 0x13, 0x05, 0x00, 0x00, 0x93, 0x05, 0x00, 0x00, 0x13, 0x06, 0x00, 0x00, 0x93, + 0x06, 0x00, 0x00, 0x13, 0x07, 0x00, 0x00, 0x93, 0x07, 0x00, 0x00, 0x13, 0x08, 0x00, 0x00, 0x93, + 0x08, 0x00, 0x00, 0x13, 0x09, 0x00, 0x00, 0x93, 0x09, 0x00, 0x00, 0x13, 0x0a, 0x00, 0x00, 0x93, + 0x0a, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0xfa, 0x77, 0xbf, 0xf1, 0x81, 0xf8, 0x46, 0x9e, 0x62, + 0x93, 0x30, 0xef, 0x9c, 0x0e, 0x33, 0x36, 0x23, 0x00, 0x0d, 0x3a, 0x61, 0xa5, 0x51, 0x8a, 0xcf, + 0x63, 0xc4, 0x09, 0xeb, 0xb2, 0x8e, 0xeb, 0xc4, 0xd8, 0x04, 0x93, 0x0b, 0x00, 0x00, 0x13, 0x0c, + 0x00, 0x00, 0x93, 0x0c, 0x00, 0x00, 0x13, 0x0d, 0x00, 0x00, 0x93, 0x0d, 0x00, 0x00, 0x13, 0x0e, + 0x00, 0x00, 0x93, 0x0e, 0x00, 0x00, 0x13, 0x0f, 0x00, 0x00, 0x93, 0x0f, 0x00, 0x00, 0x97, 0x00, + 0x00, 0x00, 0x93, 0x80, 0x40, 0xf0, 0x73, 0x90, 0x50, 0x30, 0x93, 0x00, 0x00, 0x00, 0x17, 0x41, + 0x10, 0x00, 0x13, 0x01, 0x41, 0xcf, 0x33, 0x04, 0x01, 0x00, 0x17, 0x0d, 0x10, 0x00, 0x13, 0x0d, + 0x8d, 0xee, 0x97, 0x4d, 0x10, 0x00, 0x93, 0x8d, 0x0d, 0xce, 0x63, 0x57, 0xbd, 0x01, 0x23, 0x20, + 0x0d, 0x00, 0x11, 0x0d, 0xe3, 0x4d, 0xbd, 0xff, 0xef, 0x00, 0x70, 0x71, 0x73, 0x00, 0x50, 0x10, + 0xf5, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, + 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa2, 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa0, + 0x07, 0xf4, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x8e, 0x07, 0xf2, 0x82, 0x80, 0x05, 0x67, 0x93, 0x07, + 0x45, 0x00, 0x01, 0x17, 0x01, 0x45, 0x94, 0x43, 0x99, 0xe6, 0x13, 0x05, 0x05, 0x02, 0x91, 0x07, + 0xe3, 0x1b, 0xe5, 0xfe, 0x82, 0x80, 0x81, 0x47, 0x13, 0x06, 0x00, 0x02, 0x33, 0xd7, 0xf6, 0x00, + 0x05, 0x8b, 0x09, 0xe7, 0x85, 0x07, 0x05, 0x05, 0xe3, 0x9a, 0xc7, 0xfe, 0x82, 0x80, 0x18, 0x41, + 0xfd, 0x57, 0x63, 0x02, 0xf7, 0x06, 0x13, 0x07, 0x45, 0x00, 0x81, 0x47, 0x13, 0x06, 0xf0, 0x07, + 0x14, 0x43, 0xfa, 0x0f, 0x39, 0x44, 0x97, 0x31, 0x75, 0x53, 0x6c, 0x83, 0xaf, 0x8d, 0x72, 0x89, + 0x9b, 0xa0, 0x0b, 0x1d, 0x66, 0x59, 0x1d, 0x43, 0xb7, 0x7f, 0xca, 0x69, 0x84, 0xc2, 0xd9, 0xeb, + 0xd6, 0x9e, 0x73, 0xb0, 0x05, 0x81, 0xea, 0x85, 0x07, 0x11, 0x07, 0xe3, 0x9c, 0xc7, 0xfe, 0x13, + 0x05, 0xa0, 0x0a, 0x82, 0x80, 0x01, 0x47, 0x93, 0x05, 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, 0x05, + 0x8a, 0x19, 0xca, 0x93, 0x05, 0x00, 0x02, 0x33, 0xd6, 0xe6, 0x00, 0x05, 0x8a, 0x15, 0xc6, 0x05, + 0x07, 0xe3, 0x1b, 0xb7, 0xfe, 0x21, 0xa0, 0x05, 0x07, 0xe3, 0x11, 0xb7, 0xfe, 0x89, 0x07, 0x93, + 0x06, 0x00, 0x08, 0x7d, 0x56, 0xe3, 0x85, 0xd7, 0xfc, 0x85, 0x07, 0x13, 0x97, 0x27, 0x00, 0x2a, + 0x97, 0x03, 0x27, 0xc7, 0xff, 0xe3, 0x08, 0xc7, 0xfe, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, + 0x11, 0x22, 0xc4, 0x37, 0x14, 0x20, 0x00, 0x13, 0x04, 0x04, 0x00, 0x83, 0x46, 0x94, 0x07, 0x37, + 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x77, 0x13, + 0x06, 0xc6, 0x52, 0x93, 0x85, 0x85, 0x53, 0x06, 0xc6, 0xef, 0x10, 0xd0, 0x51, 0x03, 0x45, 0x94, + 0x07, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x40, 0xd0, + 0x21, 0xef, 0x20, 0xa0, 0x5d, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x00, 0xb2, 0x40, 0x41, + 0x01, 0x6f, 0x40, 0x90, 0x22, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x93, + 0x05, 0x05, 0x10, 0x2a, 0x84, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x05, 0x54, 0x06, 0xc6, 0xef, + 0x10, 0xd0, 0x54, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x07, 0xf6, 0x14, 0x43, 0xfa, 0x88, 0xa4, + 0x89, 0xae, 0x37, 0x34, 0x85, 0x45, 0x28, 0xde, 0xe6, 0x9a, 0x1c, 0x0c, 0x6f, 0xbe, 0x56, 0x04, + 0x28, 0xa3, 0xc8, 0xe3, 0x70, 0xe5, 0x69, 0x61, 0xa7, 0x3c, 0xef, 0xb7, 0x8e, 0xfb, 0x88, 0x06, + 0x85, 0x47, 0xb3, 0x97, 0x87, 0x00, 0xb2, 0x40, 0x22, 0x44, 0x93, 0xc7, 0xf7, 0xff, 0xf5, 0x8f, + 0x1c, 0xc3, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x2a, 0x84, + 0x93, 0x04, 0xa0, 0x0a, 0xef, 0x20, 0x30, 0x77, 0x63, 0x19, 0x95, 0x00, 0x13, 0x05, 0xa0, 0x0a, + 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x22, 0x85, 0xef, 0x20, 0xb0, 0x79, + 0x22, 0x85, 0xef, 0x20, 0x50, 0x75, 0xe3, 0x03, 0x95, 0xfe, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, + 0x05, 0x54, 0x85, 0x45, 0xef, 0x10, 0xb0, 0x4e, 0x13, 0x05, 0x50, 0x05, 0xd1, 0xbf, 0x01, 0x11, + 0x22, 0xcc, 0x2a, 0x84, 0x37, 0x35, 0x00, 0x08, 0x06, 0xce, 0x2e, 0xc6, 0xef, 0x30, 0x50, 0x14, + 0x32, 0x46, 0xa2, 0x85, 0x37, 0x35, 0x00, 0x08, 0xef, 0x30, 0x70, 0x1b, 0x62, 0x44, 0xf2, 0x40, + 0x37, 0x35, 0x00, 0x08, 0x05, 0x61, 0x6f, 0x30, 0xf0, 0x16, 0x6d, 0x71, 0x23, 0x24, 0x81, 0x10, + 0x2a, 0x84, 0x0a, 0x85, 0x23, 0x26, 0x11, 0x10, 0xef, 0x10, 0xf0, 0x68, 0x0a, 0x85, 0x23, 0x00, + 0x81, 0x00, 0xef, 0x20, 0xa0, 0x47, 0x83, 0x20, 0xc1, 0x10, 0x03, 0x24, 0x81, 0x10, 0x51, 0x61, + 0x82, 0x80, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0x2e, 0xc4, 0xef, 0x20, 0xd0, 0x1b, 0xa2, 0x45, + 0x32, 0x45, 0xef, 0x20, 0xf0, 0x33, 0x2a, 0xc4, 0xef, 0x20, 0x90, 0x1c, 0xf2, 0x40, 0x22, 0x45, + 0x05, 0x61, 0x82, 0x80, 0x13, 0x01, 0x01, 0xde, 0xfa, 0x0f, 0xed, 0xbe, 0x02, 0x0e, 0xe0, 0xf4, + 0x66, 0x4a, 0x48, 0xba, 0xa0, 0x5b, 0xcc, 0x40, 0xb4, 0xd6, 0x52, 0xc1, 0xb1, 0xd8, 0x5b, 0x48, + 0xe1, 0x0f, 0x86, 0x56, 0x2a, 0xdc, 0x98, 0x09, 0x22, 0x60, 0x07, 0x23, 0x2c, 0x81, 0x20, 0x2e, + 0x84, 0xaa, 0x05, 0x23, 0x28, 0x21, 0x21, 0x93, 0x85, 0x05, 0x20, 0x2a, 0x89, 0x08, 0x08, 0x23, + 0x2e, 0x11, 0x20, 0x23, 0x2a, 0x91, 0x20, 0x7d, 0x3f, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x12, 0xf5, + 0x04, 0xaa, 0x84, 0x08, 0x08, 0x09, 0x3d, 0x63, 0x00, 0x95, 0x02, 0x22, 0x85, 0xd1, 0x3d, 0x09, + 0x45, 0x83, 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, 0x41, 0x21, 0x03, 0x29, 0x01, + 0x21, 0x13, 0x01, 0x01, 0x22, 0x82, 0x80, 0x42, 0x44, 0x08, 0x08, 0x22, 0xc6, 0x65, 0x3b, 0x09, + 0x8c, 0x11, 0x46, 0x6c, 0x00, 0x4a, 0x85, 0x22, 0xc6, 0xef, 0x50, 0x00, 0x12, 0x05, 0x45, 0xc9, + 0xbf, 0x01, 0x45, 0xf9, 0xb7, 0x41, 0x11, 0x4a, 0xc0, 0x03, 0xa9, 0x05, 0x00, 0x06, 0xc6, 0x22, + 0xc4, 0x26, 0xc2, 0x2e, 0x84, 0xaa, 0x84, 0xef, 0x20, 0x30, 0x68, 0xca, 0x85, 0x26, 0x85, 0xef, + 0x20, 0x70, 0x1f, 0xa6, 0x85, 0x22, 0x85, 0xef, 0x20, 0xd0, 0x29, 0x93, 0x07, 0xa0, 0x0a, 0x63, + 0x16, 0xf5, 0x02, 0x1c, 0x40, 0x63, 0x93, 0x27, 0x03, 0x93, 0x07, 0x44, 0x00, 0x7d, 0x57, 0x13, + 0x04, 0x04, 0x20, 0x94, 0x43, 0x63, 0x9b, 0xe6, 0x00, 0x91, 0x07, 0xe3, 0x9c, 0x87, 0xfe, 0xb2, + 0x40, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0xc5, + 0xbf, 0x13, 0x01, 0x01, 0xde, 0x23, 0x26, 0x31, 0x21, 0x93, 0x19, 0xa5, 0x00, 0x23, 0x2a, 0x91, + 0x20, 0x93, 0x84, 0xfa, 0x07, 0x1c, 0x50, 0x24, 0x69, 0xae, 0xbc, 0x72, 0xfc, 0x73, 0xd6, 0x37, + 0x39, 0xe2, 0x73, 0x4b, 0xfd, 0x9b, 0xde, 0x63, 0x21, 0xa4, 0x34, 0x5a, 0x01, 0x25, 0xb2, 0x0f, + 0xa7, 0x9e, 0xa7, 0x0b, 0x38, 0x08, 0x09, 0x20, 0x23, 0x2c, 0x81, 0x20, 0xa6, 0x85, 0x2a, 0x84, + 0x0a, 0x85, 0x23, 0x2e, 0x11, 0x20, 0x23, 0x28, 0x21, 0x21, 0xfd, 0x35, 0x93, 0x07, 0xa0, 0x0a, + 0x63, 0x00, 0xf5, 0x02, 0x01, 0x45, 0x83, 0x20, 0xc1, 0x21, 0x03, 0x24, 0x81, 0x21, 0x83, 0x24, + 0x41, 0x21, 0x03, 0x29, 0x01, 0x21, 0x83, 0x29, 0xc1, 0x20, 0x13, 0x01, 0x01, 0x22, 0x82, 0x80, + 0x2a, 0x89, 0x0a, 0x85, 0x1d, 0x33, 0x63, 0x06, 0x25, 0x01, 0x22, 0x85, 0xe5, 0x33, 0x09, 0x45, + 0xd9, 0xbf, 0x02, 0x44, 0x0a, 0x85, 0xcd, 0x31, 0xaa, 0x87, 0xb3, 0x06, 0xa4, 0x40, 0x0d, 0x45, + 0xe3, 0x03, 0xf4, 0xfc, 0x09, 0x45, 0xe3, 0x60, 0xd4, 0xfc, 0x50, 0x00, 0x01, 0x44, 0x13, 0x08, + 0x00, 0x02, 0x13, 0x05, 0xf0, 0x07, 0x0c, 0x42, 0xb1, 0xc5, 0x01, 0x47, 0xb3, 0xd7, 0xe5, 0x00, + 0x85, 0x8b, 0x95, 0xcf, 0x85, 0x47, 0xb3, 0x97, 0xe7, 0x00, 0x93, 0xc7, 0xf7, 0xff, 0xed, 0x8f, + 0x1c, 0xc2, 0xef, 0x20, 0xb0, 0x03, 0x18, 0x04, 0x93, 0x17, 0x24, 0x00, 0xba, 0x97, 0x83, 0xa5, + 0x47, 0xe0, 0x13, 0x05, 0x14, 0x00, 0x0a, 0x05, 0x26, 0x95, 0xef, 0x20, 0x30, 0x14, 0x2a, 0x84, + 0xef, 0x20, 0x70, 0x03, 0x13, 0x05, 0x64, 0xf5, 0x13, 0x35, 0x15, 0x00, 0xad, 0xb7, 0x05, 0x07, + 0xe3, 0x1e, 0x07, 0xfb, 0x05, 0x04, 0x11, 0x06, 0xe3, 0x17, 0xa4, 0xfa, 0xfd, 0x16, 0x8a, 0x85, + 0x13, 0x85, 0x09, 0x40, 0x36, 0xc0, 0xc9, 0x35, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x14, 0xfa, 0xd0, + 0xe7, 0x63, 0x7c, 0x8e, 0xc7, 0xcf, 0x0c, 0xd3, 0x23, 0x96, 0x82, 0xd4, 0xeb, 0x54, 0xfa, 0xbb, + 0xff, 0xb6, 0xc7, 0x5b, 0x2e, 0x96, 0x3c, 0xef, 0xbf, 0x2e, 0x94, 0x4d, 0xde, 0x4d, 0x61, 0x10, + 0x09, 0xf5, 0xf4, 0x8a, 0x85, 0x26, 0x85, 0x55, 0x3d, 0x13, 0x05, 0x65, 0xf5, 0xf9, 0xb7, 0x41, + 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x07, 0x30, 0x0c, 0x2a, 0x84, 0x63, 0x04, 0xf5, 0x00, 0xef, + 0x20, 0x60, 0x4e, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x05, 0x67, 0x23, 0x80, 0x87, + 0x00, 0xba, 0x97, 0xf8, 0x5b, 0x19, 0xe3, 0x05, 0x47, 0xf8, 0xdb, 0xb2, 0x40, 0x22, 0x44, 0x41, + 0x01, 0x82, 0x80, 0x05, 0x66, 0x37, 0x05, 0x20, 0x00, 0x41, 0x11, 0x13, 0x06, 0xc6, 0x07, 0x81, + 0x45, 0x13, 0x05, 0x05, 0x00, 0x06, 0xc6, 0xef, 0x40, 0x50, 0x7b, 0xef, 0x20, 0x00, 0x44, 0xef, + 0x40, 0xc0, 0x4e, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x20, 0x80, 0x3a, 0x41, 0x11, 0x06, 0xc6, 0xef, + 0x20, 0xa0, 0x57, 0xef, 0x30, 0xa0, 0x00, 0xef, 0x40, 0x40, 0x1c, 0xef, 0x40, 0x40, 0x7b, 0xb2, + 0x40, 0x41, 0x01, 0x6f, 0x30, 0x20, 0x17, 0x41, 0x11, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, + 0x05, 0x06, 0xc6, 0x23, 0xa4, 0xe7, 0xf4, 0xef, 0x20, 0xe0, 0x3c, 0x65, 0x37, 0x51, 0x3e, 0xef, + 0x30, 0xe0, 0x1b, 0xe1, 0x37, 0xb2, 0x40, 0x1d, 0x65, 0x13, 0x05, 0x05, 0x6c, 0x41, 0x01, 0x6f, + 0x30, 0x60, 0x23, 0x41, 0x11, 0x26, 0xc2, 0xae, 0x84, 0xb6, 0x85, 0x06, 0xc6, 0x22, 0xc4, 0x4a, + 0xc0, 0x36, 0x84, 0x32, 0x89, 0xef, 0x40, 0x00, 0x79, 0x22, 0x86, 0xca, 0x85, 0x13, 0x05, 0x00, + 0x02, 0xef, 0x40, 0x60, 0x7b, 0xef, 0x40, 0x20, 0x76, 0xfa, 0x0a, 0xff, 0x35, 0xd1, 0x09, 0x01, + 0xdc, 0xdd, 0x42, 0x4c, 0xa2, 0xed, 0x9e, 0x12, 0xb3, 0x29, 0x73, 0x5c, 0xd5, 0xa3, 0x4b, 0xa3, + 0x1c, 0xf9, 0x45, 0x3b, 0x19, 0xb0, 0x84, 0x20, 0x46, 0x68, 0xe8, 0x09, 0xef, 0x40, 0x80, 0x7b, + 0x93, 0x07, 0xa0, 0x0a, 0x13, 0x04, 0x50, 0x05, 0x63, 0x1a, 0xf5, 0x00, 0x2a, 0x84, 0x13, 0x06, + 0x00, 0x02, 0x93, 0x05, 0x00, 0x02, 0x26, 0x85, 0xef, 0x40, 0x80, 0x78, 0xb2, 0x40, 0x22, 0x85, + 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x85, 0x67, 0xc1, 0x07, 0x63, 0xee, + 0xb7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xae, 0x84, 0x37, 0x04, 0x20, 0x00, + 0x19, 0xc5, 0x2e, 0x86, 0xaa, 0x85, 0x13, 0x05, 0x04, 0x00, 0xef, 0x40, 0xf0, 0x6b, 0x13, 0x04, + 0x04, 0x00, 0x93, 0x07, 0x30, 0xfc, 0x23, 0x00, 0xf4, 0x00, 0x85, 0x67, 0x3e, 0x94, 0x64, 0xd8, + 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x82, 0x80, 0x13, 0x01, 0x01, 0xdd, + 0x23, 0x24, 0x81, 0x22, 0x23, 0x22, 0x91, 0x22, 0x23, 0x20, 0x21, 0x23, 0x23, 0x2e, 0x31, 0x21, + 0x23, 0x2c, 0x41, 0x21, 0x23, 0x2a, 0x51, 0x21, 0x23, 0x28, 0x61, 0x21, 0x23, 0x26, 0x71, 0x21, + 0x23, 0x24, 0x81, 0x21, 0x23, 0x26, 0x11, 0x22, 0x13, 0x04, 0x00, 0x20, 0x01, 0x49, 0x93, 0x04, + 0xa0, 0x0a, 0x37, 0x3a, 0x20, 0x00, 0x85, 0x4a, 0x37, 0x5b, 0x10, 0x00, 0xb7, 0x5b, 0x10, 0x00, + 0x37, 0x5c, 0x10, 0x00, 0xc1, 0x49, 0xa2, 0x85, 0x0a, 0x85, 0x51, 0x39, 0x63, 0x16, 0x95, 0x02, + 0x0a, 0x85, 0xfd, 0x34, 0x63, 0x1e, 0x95, 0x04, 0x13, 0x07, 0x0a, 0xf6, 0x14, 0x43, 0xb3, 0x97, + 0x2a, 0x01, 0x13, 0x06, 0xfa, 0x9c, 0x67, 0xfe, 0x49, 0x5b, 0xe4, 0x36, 0xd0, 0x26, 0x62, 0x9e, + 0x4e, 0xdb, 0x34, 0x9f, 0xdc, 0x36, 0x12, 0xe2, 0x22, 0xba, 0x2e, 0xbd, 0xfe, 0xea, 0x30, 0x72, + 0x01, 0xd8, 0x78, 0xd4, 0x38, 0xc0, 0x0a, 0x8b, 0x54, 0xd5, 0x8f, 0x93, 0x85, 0x0b, 0x54, 0xca, + 0x86, 0x13, 0x05, 0x8c, 0x77, 0x1c, 0xc3, 0xef, 0x10, 0x10, 0x08, 0x05, 0x09, 0x13, 0x04, 0x04, + 0x40, 0xe3, 0x14, 0x39, 0xfd, 0x83, 0x20, 0xc1, 0x22, 0x03, 0x24, 0x81, 0x22, 0x83, 0x24, 0x41, + 0x22, 0x03, 0x29, 0x01, 0x22, 0x83, 0x29, 0xc1, 0x21, 0x03, 0x2a, 0x81, 0x21, 0x83, 0x2a, 0x41, + 0x21, 0x03, 0x2b, 0x01, 0x21, 0x83, 0x2b, 0xc1, 0x20, 0x03, 0x2c, 0x81, 0x20, 0x13, 0x01, 0x01, + 0x23, 0x82, 0x80, 0x93, 0x05, 0x04, 0x20, 0x0a, 0x85, 0x25, 0x31, 0xe3, 0x10, 0x95, 0xfc, 0x0a, + 0x85, 0x49, 0x34, 0xe3, 0x1c, 0x95, 0xfa, 0x22, 0x85, 0xef, 0x20, 0xd0, 0x33, 0x8a, 0x85, 0x22, + 0x85, 0xef, 0x20, 0x30, 0x1b, 0xa2, 0x85, 0x0a, 0x85, 0x21, 0x31, 0xe3, 0x10, 0x95, 0xfa, 0x0a, + 0x85, 0x8d, 0x34, 0xe3, 0x0c, 0x95, 0xf6, 0x51, 0xbf, 0xb7, 0x07, 0x00, 0x80, 0x6d, 0x71, 0x37, + 0x55, 0x10, 0x00, 0x23, 0x26, 0x11, 0x10, 0x13, 0x05, 0x45, 0x55, 0x86, 0x85, 0xbe, 0x95, 0xef, + 0x10, 0xf0, 0x06, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x47, 0xf3, 0x93, 0x07, 0xa0, 0x0a, 0x63, + 0x1e, 0xf7, 0x02, 0x37, 0x15, 0x10, 0x00, 0x13, 0x05, 0x85, 0x9f, 0xef, 0x10, 0x70, 0x7b, 0x13, + 0x05, 0xc0, 0x0f, 0xef, 0x10, 0xc0, 0x74, 0x0a, 0x85, 0xef, 0x10, 0xd0, 0x22, 0x93, 0x07, 0xf0, + 0x07, 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, 0x00, 0x23, 0x00, 0xf1, 0x00, 0xef, 0x10, 0xfa, + 0x42, 0x72, 0x52, 0x8e, 0xfd, 0x28, 0x7d, 0x7d, 0x55, 0xf5, 0xbe, 0xa0, 0xee, 0xbc, 0x2c, 0xfa, + 0x20, 0x83, 0x6f, 0x9f, 0xb1, 0xcf, 0x87, 0x58, 0x94, 0x85, 0x8b, 0x32, 0xc6, 0x19, 0xbf, 0xff, + 0x98, 0x0b, 0x20, 0x6e, 0xa3, 0x00, 0xa1, 0x00, 0x0a, 0x85, 0xef, 0x10, 0x10, 0x7d, 0x05, 0x45, + 0xef, 0x40, 0xf0, 0x03, 0xef, 0x40, 0xf0, 0x02, 0xe5, 0x33, 0xef, 0x10, 0xb0, 0x46, 0xf5, 0xbf, + 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0x40, 0x80, 0x68, 0x93, 0x07, 0x00, 0x08, 0x63, 0xf3, + 0xa7, 0x00, 0xad, 0x3f, 0x2a, 0x84, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x40, 0x40, 0x27, 0xb7, 0x17, + 0x20, 0x00, 0xb2, 0x40, 0x23, 0xaa, 0x87, 0x06, 0x22, 0x44, 0x13, 0x05, 0x30, 0x0c, 0x41, 0x01, + 0x82, 0x80, 0x93, 0x07, 0xf0, 0x17, 0x63, 0xf5, 0xa7, 0x00, 0x41, 0x11, 0x06, 0xc6, 0xb9, 0x37, + 0x6f, 0x10, 0x10, 0x58, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x4a, 0xc0, 0x2e, 0x84, 0x06, 0xc6, + 0xaa, 0x84, 0xc5, 0x37, 0x61, 0x8d, 0x13, 0x09, 0x50, 0x05, 0x19, 0xc1, 0x13, 0x09, 0xa0, 0x0a, + 0x26, 0x85, 0xc1, 0x3f, 0x69, 0x8c, 0x13, 0x05, 0xa0, 0x0a, 0x19, 0xe0, 0x13, 0x05, 0x50, 0x05, + 0x63, 0x03, 0x25, 0x01, 0x21, 0x3f, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x02, 0x49, 0x41, 0x01, + 0x82, 0x80, 0x69, 0x71, 0x08, 0x08, 0x23, 0x22, 0x91, 0x12, 0x23, 0x20, 0x21, 0x13, 0x23, 0x2c, + 0x41, 0x11, 0x37, 0x39, 0x20, 0x00, 0x23, 0x26, 0x11, 0x12, 0x23, 0x24, 0x81, 0x12, 0x23, 0x2e, + 0x31, 0x11, 0x23, 0x2a, 0x51, 0x11, 0xef, 0x10, 0x30, 0x15, 0x91, 0x47, 0x13, 0x07, 0x89, 0xf5, + 0x23, 0x08, 0xf1, 0x00, 0x1c, 0x43, 0x37, 0x1a, 0x20, 0x00, 0xfa, 0xd7, 0x18, 0x94, 0x03, 0x24, + 0x8d, 0xf3, 0x32, 0xbe, 0x7c, 0x88, 0xd5, 0x99, 0x57, 0x8a, 0x59, 0x45, 0x08, 0x0a, 0x79, 0xe6, + 0x26, 0xee, 0xd0, 0x90, 0x02, 0x80, 0xde, 0x8d, 0x3b, 0xe0, 0x22, 0x70, 0x0c, 0xb7, 0x34, 0x20, + 0x00, 0x13, 0x09, 0x89, 0xf5, 0x13, 0x0a, 0x0a, 0x00, 0x93, 0x84, 0x44, 0xf5, 0xc5, 0xeb, 0x83, + 0x27, 0x4a, 0x07, 0x23, 0xa0, 0x04, 0x00, 0x1c, 0xc3, 0x3d, 0x47, 0x63, 0x63, 0xf7, 0x00, 0x45, + 0x3d, 0xc1, 0x17, 0x09, 0x46, 0x6c, 0x00, 0x13, 0x05, 0x21, 0x01, 0x3e, 0xc6, 0xef, 0x40, 0xf0, + 0x43, 0x89, 0x47, 0xa3, 0x08, 0xf1, 0x00, 0x13, 0x04, 0xe0, 0x07, 0x93, 0x09, 0x41, 0x01, 0x03, + 0x27, 0x09, 0x00, 0x94, 0x40, 0xb3, 0x07, 0xd7, 0x40, 0x63, 0xf3, 0x87, 0x00, 0x3e, 0x84, 0x37, + 0x56, 0x10, 0x00, 0xb7, 0x5a, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0xa2, 0x87, 0x93, 0x85, 0xca, + 0x56, 0x13, 0x06, 0xc6, 0x55, 0x13, 0x05, 0x45, 0x57, 0xef, 0x10, 0x40, 0x67, 0x8c, 0x40, 0x83, + 0x27, 0x4a, 0x07, 0x33, 0x07, 0xb4, 0x00, 0x63, 0xf8, 0xe7, 0x04, 0x8d, 0x45, 0x13, 0x85, 0xca, + 0x56, 0xef, 0x10, 0x20, 0x6d, 0x13, 0x04, 0x50, 0x05, 0xef, 0xf0, 0x5f, 0x84, 0xef, 0x40, 0xe0, + 0x14, 0xef, 0x20, 0x60, 0x0a, 0xef, 0x20, 0x60, 0x01, 0xbd, 0x31, 0x83, 0x20, 0xc1, 0x12, 0x22, + 0x85, 0x03, 0x24, 0x81, 0x12, 0x83, 0x24, 0x41, 0x12, 0x03, 0x29, 0x01, 0x12, 0x83, 0x29, 0xc1, + 0x11, 0x03, 0x2a, 0x81, 0x11, 0x83, 0x2a, 0x41, 0x11, 0x55, 0x61, 0x82, 0x80, 0x13, 0x04, 0x00, + 0x08, 0x93, 0x09, 0x21, 0x01, 0xad, 0xbf, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, 0x22, + 0x86, 0xbe, 0x95, 0x4e, 0x85, 0xfa, 0x9e, 0xab, 0x8e, 0xc5, 0xb3, 0x79, 0x08, 0x07, 0xd8, 0x27, + 0x87, 0x84, 0xab, 0x38, 0x3a, 0xd4, 0x2a, 0x51, 0x54, 0x3d, 0x70, 0x65, 0x82, 0xa9, 0xa5, 0x42, + 0x26, 0x1d, 0x2b, 0x70, 0x97, 0x72, 0x48, 0x0d, 0xef, 0x40, 0x70, 0x39, 0x83, 0x47, 0x11, 0x01, + 0x98, 0x40, 0x22, 0x97, 0x3e, 0x94, 0x83, 0x27, 0x09, 0x00, 0xa3, 0x08, 0x81, 0x00, 0x98, 0xc0, + 0x13, 0x04, 0x50, 0x05, 0x63, 0x17, 0xf7, 0x00, 0x89, 0x47, 0x23, 0x08, 0xf1, 0x00, 0x13, 0x04, + 0xa0, 0x0a, 0x08, 0x08, 0xef, 0x10, 0x10, 0x63, 0x59, 0xbf, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, + 0x26, 0xca, 0x4a, 0xc8, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xf3, 0xa7, 0x00, 0x5d, 0x3b, 0x0a, 0x05, + 0x05, 0x64, 0xb3, 0x04, 0x85, 0x00, 0x41, 0x04, 0x13, 0x09, 0xc1, 0x00, 0x2a, 0x94, 0x26, 0x85, + 0xef, 0x30, 0xc0, 0x0b, 0x23, 0x00, 0xa9, 0x00, 0x91, 0x04, 0x05, 0x09, 0xe3, 0x99, 0x84, 0xfe, + 0xf2, 0x40, 0x62, 0x44, 0x32, 0x45, 0xd2, 0x44, 0x42, 0x49, 0x05, 0x61, 0x82, 0x80, 0x41, 0x11, + 0x06, 0xc6, 0x8d, 0x47, 0x63, 0xf3, 0xa7, 0x00, 0xad, 0x3b, 0x89, 0x67, 0x93, 0x87, 0x07, 0xbf, + 0x0a, 0x05, 0x3e, 0x95, 0xef, 0x30, 0x80, 0x08, 0xaa, 0x87, 0x13, 0x07, 0xf0, 0x0f, 0x55, 0x45, + 0x63, 0x89, 0xe7, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x59, 0x45, 0x63, 0x94, 0xe7, 0x00, 0x13, 0x05, + 0x30, 0x0c, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x05, 0x71, 0x23, 0x2c, 0x81, 0x1c, 0x23, 0x2e, + 0x11, 0x1c, 0x23, 0x2a, 0x91, 0x1c, 0x23, 0x28, 0x21, 0x1d, 0x23, 0x26, 0x31, 0x1d, 0x23, 0x24, + 0x41, 0x1d, 0x23, 0x22, 0x51, 0x1d, 0x23, 0x20, 0x61, 0x1d, 0x23, 0x2e, 0x71, 0x1b, 0x23, 0x2c, + 0xfa, 0x88, 0x20, 0x3a, 0x4e, 0xbd, 0x8e, 0x18, 0x09, 0x8a, 0x3f, 0xbf, 0xb7, 0x68, 0x17, 0x1d, + 0x0e, 0xb2, 0x78, 0xfd, 0x8e, 0xbd, 0x9d, 0xb1, 0x09, 0x83, 0xa3, 0x53, 0x75, 0x4b, 0xa6, 0x40, + 0xd9, 0x20, 0x0e, 0x81, 0x1b, 0x23, 0x2a, 0x91, 0x1b, 0x23, 0x28, 0xa1, 0x1b, 0x23, 0x26, 0xb1, + 0x1b, 0x83, 0x46, 0x05, 0x00, 0x93, 0x07, 0x20, 0x0a, 0x2a, 0x84, 0x63, 0x82, 0xf6, 0x02, 0x03, + 0x47, 0x15, 0x00, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, + 0x06, 0x86, 0x57, 0x93, 0x85, 0x45, 0x55, 0x13, 0x05, 0x85, 0x77, 0xef, 0x10, 0x80, 0x4f, 0x08, + 0x11, 0xef, 0x10, 0x00, 0x75, 0x83, 0x47, 0x04, 0x00, 0x05, 0x47, 0x23, 0x10, 0xe1, 0x0a, 0xc1, + 0x46, 0x63, 0x8b, 0xd7, 0x46, 0x63, 0xee, 0xf6, 0x02, 0x91, 0x46, 0x63, 0x83, 0xd7, 0x36, 0x63, + 0xe1, 0xf6, 0x02, 0x63, 0x86, 0xe7, 0x06, 0x09, 0x47, 0x63, 0x81, 0xe7, 0x0e, 0x93, 0x07, 0xe0, + 0x07, 0x23, 0x00, 0xf1, 0x0a, 0x08, 0x11, 0xef, 0x10, 0xd0, 0x4d, 0x93, 0x07, 0x50, 0x05, 0xb1, + 0xa9, 0x21, 0x47, 0xe3, 0x95, 0xe7, 0xfe, 0x83, 0x47, 0x14, 0x00, 0xd1, 0xeb, 0xf5, 0x34, 0x15, + 0xa9, 0x93, 0x06, 0x20, 0x0a, 0x63, 0x85, 0xd7, 0x4e, 0x93, 0x06, 0x30, 0x0b, 0x63, 0x81, 0xd7, + 0x48, 0x93, 0x06, 0x00, 0x02, 0xe3, 0x94, 0xd7, 0xfc, 0x83, 0x47, 0x14, 0x00, 0x63, 0x99, 0xe7, + 0x06, 0x03, 0x47, 0x24, 0x00, 0x95, 0x47, 0x63, 0x14, 0xf7, 0x06, 0x85, 0x45, 0x61, 0x45, 0x39, + 0x3b, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x08, 0xf5, 0x44, 0x13, 0x04, 0x80, 0xf8, 0x7d, 0xa0, 0x03, + 0x47, 0x14, 0x00, 0x89, 0x47, 0x63, 0x15, 0xf7, 0x04, 0x83, 0x47, 0xfa, 0xba, 0xc1, 0xe9, 0xda, + 0xc3, 0xf5, 0x60, 0x02, 0xb0, 0xe8, 0x51, 0x83, 0xfa, 0xae, 0x70, 0x5c, 0x43, 0x14, 0x6d, 0xd7, + 0x0d, 0xfd, 0xd2, 0xec, 0x31, 0xf7, 0x6b, 0x98, 0x11, 0xa2, 0x51, 0xba, 0xf8, 0x0e, 0x24, 0x00, + 0x63, 0x8a, 0xe7, 0x04, 0x63, 0x6b, 0xf7, 0x02, 0xa1, 0xe3, 0x83, 0x45, 0x34, 0x00, 0xf5, 0x47, + 0x63, 0xe9, 0xb7, 0x02, 0x9e, 0x05, 0x13, 0x06, 0x00, 0x08, 0x93, 0x85, 0x05, 0x10, 0x13, 0x05, + 0x21, 0x0a, 0xef, 0x20, 0x90, 0x6f, 0x13, 0x04, 0x00, 0x08, 0x08, 0x11, 0xa3, 0x00, 0x81, 0x0a, + 0xef, 0x10, 0x70, 0x44, 0x93, 0x07, 0xa0, 0x0a, 0xd9, 0xa6, 0x13, 0x05, 0x80, 0x1e, 0x63, 0x8d, + 0xd7, 0x00, 0x13, 0x04, 0x10, 0xf8, 0xa1, 0xa8, 0x89, 0x65, 0x13, 0x06, 0x00, 0x08, 0x93, 0x85, + 0x05, 0x90, 0xf1, 0xb7, 0x13, 0x05, 0x00, 0x1f, 0xef, 0x10, 0x50, 0x22, 0x2a, 0xce, 0x11, 0x46, + 0x6c, 0x08, 0x13, 0x05, 0x21, 0x0a, 0xef, 0x40, 0xf0, 0x17, 0x11, 0x44, 0x7d, 0xbf, 0x83, 0x44, + 0x14, 0x00, 0x2d, 0x34, 0x93, 0x07, 0x10, 0x02, 0xe3, 0x95, 0xf4, 0xfc, 0xef, 0x10, 0xd0, 0x77, + 0xef, 0x20, 0xd0, 0x20, 0xef, 0x30, 0x50, 0x40, 0xef, 0x40, 0xc0, 0x15, 0x03, 0x45, 0x24, 0x02, + 0x15, 0x3d, 0x93, 0x07, 0x30, 0x0c, 0x63, 0x0b, 0xf5, 0x02, 0x13, 0x04, 0x70, 0xf8, 0xb3, 0x06, + 0x80, 0x40, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0xf6, + 0xf6, 0x0f, 0x13, 0x06, 0x86, 0x59, 0x93, 0x85, 0x45, 0x55, 0x13, 0x05, 0x85, 0x77, 0x23, 0x00, + 0xd1, 0x0a, 0xef, 0x10, 0x40, 0x39, 0xa3, 0x00, 0x01, 0x0a, 0xf9, 0xb5, 0x83, 0x44, 0x24, 0x02, + 0xef, 0xf0, 0x9f, 0x98, 0x8d, 0x47, 0xfa, 0x70, 0x85, 0x1f, 0x65, 0xc9, 0x16, 0xf8, 0x25, 0xfd, + 0x92, 0xdb, 0x67, 0x98, 0x78, 0x77, 0x06, 0x63, 0x1a, 0x9b, 0xd8, 0x7b, 0x63, 0x50, 0x00, 0xf5, + 0x06, 0x24, 0x91, 0xe6, 0xd7, 0xba, 0xf4, 0xd0, 0x0f, 0xe3, 0xe2, 0x97, 0xfc, 0x13, 0x06, 0x10, + 0x08, 0x81, 0x45, 0x68, 0x08, 0xef, 0x40, 0xf0, 0x13, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0x24, + 0x00, 0x13, 0x05, 0xd1, 0x01, 0x23, 0x0e, 0x91, 0x00, 0xef, 0x40, 0xf0, 0x0e, 0xef, 0x40, 0xa0, + 0x0e, 0x37, 0x25, 0x00, 0x08, 0xef, 0x30, 0xc0, 0x03, 0x81, 0x46, 0x01, 0x46, 0x93, 0x05, 0xd1, + 0x03, 0x45, 0x45, 0xef, 0xf0, 0x9f, 0x9b, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x11, 0xf5, 0xf8, 0x81, + 0x45, 0x68, 0x08, 0xef, 0x30, 0xd0, 0x36, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0xe3, 0x18, 0xf5, + 0xf6, 0x93, 0x06, 0x00, 0x02, 0x13, 0x06, 0xd1, 0x01, 0x93, 0x05, 0xd1, 0x05, 0x49, 0x45, 0xef, + 0xf0, 0xdf, 0x98, 0xaa, 0x84, 0xe3, 0x1c, 0x25, 0xf5, 0x85, 0x45, 0x68, 0x08, 0xef, 0x30, 0x30, + 0x34, 0x2a, 0x89, 0xe3, 0x15, 0x95, 0xf4, 0x83, 0x47, 0xc1, 0x01, 0x85, 0x46, 0x13, 0x06, 0xb1, + 0x01, 0x93, 0x05, 0xd1, 0x05, 0x4d, 0x45, 0xa3, 0x0d, 0xf1, 0x00, 0xef, 0xf0, 0x1f, 0x96, 0xaa, + 0x84, 0xe3, 0x16, 0x25, 0xf3, 0x89, 0x45, 0x68, 0x08, 0xef, 0x30, 0x70, 0x31, 0x2a, 0x89, 0xe3, + 0x1f, 0x95, 0xf0, 0x81, 0x46, 0x01, 0x46, 0x93, 0x05, 0xd1, 0x05, 0x51, 0x45, 0xef, 0xf0, 0xff, + 0x93, 0xaa, 0x84, 0xe3, 0x15, 0x25, 0xf1, 0x8d, 0x45, 0x68, 0x08, 0xef, 0x30, 0x50, 0x2f, 0x2a, + 0x89, 0xe3, 0x1e, 0x95, 0xee, 0x91, 0x45, 0x68, 0x08, 0xef, 0x30, 0x70, 0x2e, 0xaa, 0x84, 0xe3, + 0x17, 0xfa, 0xe9, 0xc0, 0xac, 0x54, 0xf7, 0x6d, 0xf2, 0x67, 0x99, 0x4f, 0x1b, 0xe9, 0xf7, 0x9b, + 0x73, 0xf8, 0xfe, 0xb9, 0xd9, 0x90, 0x0a, 0xcc, 0x61, 0xfd, 0x93, 0x3c, 0xa6, 0x8f, 0x9e, 0xc4, + 0x19, 0x6a, 0xa8, 0x10, 0x25, 0xef, 0x95, 0x45, 0x68, 0x08, 0xef, 0x30, 0x90, 0x2d, 0xe3, 0x11, + 0x95, 0xee, 0xb7, 0x14, 0x20, 0x00, 0x13, 0x85, 0x04, 0x02, 0xef, 0x30, 0xb0, 0x31, 0x37, 0x19, + 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0xd1, 0x03, 0x13, 0x05, 0x09, 0x03, 0xef, 0x40, + 0xd0, 0x00, 0x37, 0x15, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, 0x05, 0xd1, 0x07, 0x13, 0x05, + 0x05, 0x05, 0xef, 0x40, 0x80, 0x7f, 0x83, 0x49, 0x24, 0x02, 0x8d, 0x47, 0x63, 0xf3, 0x37, 0x01, + 0xb9, 0x34, 0xb7, 0x5c, 0x10, 0x00, 0xef, 0x10, 0x30, 0x43, 0x01, 0x4d, 0x93, 0x8c, 0x4c, 0x6c, + 0x0d, 0x4a, 0xfd, 0x5a, 0x13, 0x0b, 0x00, 0x0f, 0xc1, 0x6b, 0x37, 0x0c, 0x00, 0x01, 0x13, 0x17, + 0x2d, 0x00, 0xb3, 0x87, 0xec, 0x00, 0x83, 0xcd, 0x07, 0x00, 0x3a, 0xc6, 0x63, 0x81, 0x0d, 0x08, + 0x80, 0x43, 0x13, 0x55, 0x44, 0x01, 0x41, 0x80, 0x75, 0x3c, 0x3d, 0x88, 0x32, 0x47, 0x63, 0x68, + 0x8a, 0x00, 0x0e, 0x04, 0x33, 0x94, 0x8a, 0x00, 0x13, 0x44, 0xf4, 0xff, 0x61, 0x8d, 0xb3, 0x86, + 0xec, 0x00, 0x83, 0xc6, 0x16, 0x00, 0x33, 0x55, 0x35, 0x01, 0x93, 0x77, 0x15, 0x00, 0x93, 0xf6, + 0x06, 0x0f, 0x63, 0x82, 0x66, 0x05, 0x93, 0x76, 0x05, 0x10, 0x99, 0xc2, 0x93, 0xe7, 0x27, 0x00, + 0xb3, 0x76, 0x75, 0x01, 0x99, 0xc2, 0x93, 0xe7, 0x47, 0x00, 0x33, 0x75, 0x85, 0x01, 0x19, 0xc1, + 0x93, 0xe7, 0x87, 0x00, 0x66, 0x97, 0x18, 0x43, 0xbd, 0x65, 0xc2, 0x07, 0xfa, 0x3e, 0x3b, 0xc6, + 0x93, 0x30, 0x55, 0x8a, 0x47, 0x35, 0x55, 0x80, 0x92, 0x97, 0xee, 0x43, 0x36, 0xcf, 0xed, 0xca, + 0x7a, 0xe6, 0xec, 0x9c, 0x2b, 0x37, 0xe0, 0xb0, 0xbc, 0x6d, 0x24, 0x15, 0x0b, 0x80, 0x11, 0xf9, + 0x8d, 0x21, 0x83, 0x3d, 0x8b, 0x22, 0x07, 0x4d, 0x8f, 0xb3, 0x65, 0xb7, 0x01, 0x6a, 0x85, 0xdd, + 0x8d, 0xef, 0x10, 0x30, 0x3b, 0x05, 0x0d, 0xad, 0xbf, 0xf9, 0xdf, 0x93, 0x07, 0xf0, 0x0f, 0xe1, + 0xbf, 0xef, 0x10, 0xd0, 0x37, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x13, 0x06, 0x00, + 0x02, 0x93, 0x05, 0x09, 0x03, 0x13, 0x05, 0x21, 0x0a, 0x23, 0xa4, 0xe7, 0xf4, 0xef, 0x40, 0x00, + 0x72, 0x41, 0x46, 0x93, 0x85, 0x04, 0x02, 0x13, 0x05, 0x21, 0x0c, 0xef, 0x40, 0x20, 0x71, 0xef, + 0x30, 0xf0, 0x76, 0x13, 0x04, 0x00, 0x03, 0xef, 0xf0, 0x2f, 0xfa, 0xa1, 0xb3, 0xb7, 0x37, 0x20, + 0x00, 0x03, 0xa7, 0x87, 0xf4, 0x93, 0x07, 0xa0, 0x0a, 0x83, 0x44, 0x14, 0x00, 0x63, 0x14, 0xf7, + 0x0e, 0x91, 0xe4, 0x13, 0x04, 0x10, 0xf8, 0xef, 0xf0, 0xef, 0xf9, 0x71, 0xbb, 0xb7, 0x39, 0x20, + 0x00, 0x83, 0xa7, 0x49, 0xf4, 0x93, 0x89, 0x49, 0xf4, 0xad, 0xcb, 0x09, 0x04, 0x37, 0x39, 0x20, + 0x00, 0x13, 0x09, 0x09, 0xf4, 0x83, 0x26, 0x09, 0x00, 0x03, 0xa7, 0x09, 0x00, 0x37, 0x56, 0x10, + 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x77, 0xa6, 0x96, 0x13, + 0x06, 0xc6, 0x58, 0x93, 0x85, 0xc5, 0x56, 0xef, 0x10, 0x80, 0x11, 0x03, 0x25, 0x09, 0x00, 0x83, + 0xa7, 0x09, 0x00, 0x33, 0x87, 0xa4, 0x00, 0xe3, 0xe6, 0xe7, 0xfa, 0x85, 0x67, 0x93, 0x87, 0x07, + 0x02, 0xe3, 0xe1, 0xe7, 0xfa, 0xb7, 0x07, 0xfa, 0xac, 0x84, 0x67, 0xc1, 0xaa, 0x07, 0x0a, 0x33, + 0xa9, 0xd1, 0x33, 0x67, 0xdc, 0x92, 0x5e, 0x7a, 0xa4, 0x96, 0x1b, 0x4c, 0x9f, 0x3f, 0xa4, 0xfd, + 0x91, 0x9e, 0xb6, 0xab, 0x75, 0x8a, 0x97, 0x50, 0x58, 0x12, 0x20, 0x00, 0x93, 0x87, 0x07, 0x00, + 0x26, 0x86, 0x3e, 0x95, 0xa2, 0x85, 0xef, 0x40, 0xa0, 0x67, 0x83, 0x27, 0x09, 0x00, 0xbe, 0x94, + 0x83, 0xa7, 0x09, 0x00, 0x23, 0x20, 0x99, 0x00, 0xbd, 0xe3, 0x75, 0x54, 0x39, 0xbb, 0x89, 0x47, + 0xe3, 0xfb, 0x97, 0xf6, 0x03, 0x49, 0x34, 0x00, 0x83, 0x47, 0x24, 0x00, 0xf9, 0x14, 0x22, 0x09, + 0x3e, 0x99, 0x85, 0x67, 0x93, 0x06, 0xf9, 0xff, 0x13, 0x87, 0xf7, 0x00, 0x11, 0x04, 0xe3, 0x6c, + 0xd7, 0xf4, 0x37, 0x0a, 0x20, 0x00, 0x13, 0x0a, 0x0a, 0x00, 0x3e, 0x9a, 0x41, 0x09, 0x93, 0x07, + 0xf0, 0x07, 0xa3, 0x0c, 0xfa, 0x06, 0x23, 0xa0, 0x29, 0x01, 0xef, 0x10, 0xb0, 0x43, 0xef, 0x20, + 0xa0, 0x6c, 0xef, 0x30, 0x30, 0x0c, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x28, 0x2a, 0x07, 0x23, 0x2a, + 0x0a, 0x06, 0x23, 0xa0, 0x07, 0xf4, 0x2d, 0xbf, 0x13, 0x04, 0x60, 0xf8, 0x39, 0xbf, 0xe3, 0x9e, + 0xf4, 0xf8, 0x01, 0x44, 0x89, 0xb1, 0x83, 0x47, 0x14, 0x00, 0xe3, 0x9a, 0x07, 0xc4, 0xef, 0x10, + 0xd0, 0x10, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x04, 0x05, 0xc4, 0x83, 0x20, 0xc1, 0x1d, 0x03, 0x24, + 0x81, 0x1d, 0x83, 0x24, 0x41, 0x1d, 0x03, 0x29, 0x01, 0x1d, 0x83, 0x29, 0xc1, 0x1c, 0x03, 0x2a, + 0x81, 0x1c, 0x83, 0x2a, 0x41, 0x1c, 0x03, 0x2b, 0x01, 0x1c, 0x83, 0x2b, 0xc1, 0x1b, 0x03, 0x2c, + 0x81, 0x1b, 0x83, 0x2c, 0x41, 0x1b, 0x03, 0x2d, 0x01, 0x1b, 0x83, 0x2d, 0xc1, 0x1a, 0x3e, 0x85, + 0x3d, 0x61, 0xfa, 0x92, 0x00, 0xf8, 0xbc, 0x58, 0x7d, 0x04, 0x0d, 0xf5, 0x2a, 0xd1, 0x5d, 0xa0, + 0xb5, 0x48, 0x9b, 0xa1, 0x1f, 0xda, 0x71, 0x1c, 0x50, 0x11, 0x64, 0xd7, 0x62, 0xab, 0x2c, 0xc2, + 0x2d, 0xa2, 0x3a, 0x30, 0x13, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa8, 0xa7, 0xf4, 0x85, + 0xbe, 0x83, 0x46, 0x14, 0x00, 0xe3, 0x9e, 0xe6, 0xbe, 0x83, 0x47, 0x24, 0x00, 0x63, 0x8b, 0xd7, + 0x02, 0x0d, 0x47, 0xe3, 0x97, 0xe7, 0xbe, 0xa1, 0x45, 0x01, 0x45, 0xef, 0xf0, 0x5f, 0x8a, 0x93, + 0x07, 0xa0, 0x0a, 0x2a, 0x84, 0xe3, 0x13, 0xf5, 0xb8, 0xb7, 0xb5, 0xb5, 0x61, 0x93, 0x85, 0x55, + 0x49, 0x13, 0x05, 0x80, 0x1f, 0xef, 0x10, 0x00, 0x67, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0x87, + 0xf2, 0x95, 0xb7, 0xb7, 0x15, 0x78, 0x4a, 0x93, 0x85, 0x95, 0x21, 0x13, 0x05, 0x80, 0x1f, 0xef, + 0x10, 0x60, 0x65, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xac, 0xe7, 0xf2, 0x99, + 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x47, 0xf3, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1f, 0xf7, + 0xb2, 0x83, 0x47, 0x14, 0x00, 0xe3, 0x96, 0x07, 0xb8, 0x93, 0x05, 0xc0, 0x0f, 0x13, 0x05, 0x21, + 0x0a, 0xef, 0x00, 0xd0, 0x6b, 0x2a, 0x84, 0xe3, 0x51, 0x05, 0xb6, 0xc9, 0xbe, 0x01, 0x11, 0x06, + 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0x8d, 0x47, 0x63, 0xf4, 0xa7, 0x00, 0xef, + 0xf0, 0x8f, 0xf6, 0x89, 0x67, 0x2a, 0x84, 0x93, 0x87, 0x07, 0xbf, 0x0a, 0x05, 0x81, 0x45, 0x3e, + 0x95, 0x13, 0x09, 0x04, 0x0e, 0xef, 0x20, 0x10, 0x2b, 0x16, 0x09, 0x81, 0x44, 0x93, 0x09, 0x00, + 0x02, 0x33, 0x05, 0x99, 0x00, 0x81, 0x45, 0x91, 0x04, 0xef, 0x20, 0xd0, 0x29, 0xfa, 0x27, 0x13, + 0x9a, 0xf4, 0x3f, 0x4b, 0xc3, 0x14, 0xa0, 0x31, 0x5e, 0x8f, 0xfd, 0x4a, 0xe8, 0xe2, 0xdc, 0x95, + 0xb0, 0x2c, 0xca, 0x71, 0x78, 0x01, 0x33, 0xb7, 0x79, 0x01, 0x7a, 0x49, 0x68, 0x47, 0x08, 0x14, + 0xe3, 0x9a, 0x34, 0xff, 0x22, 0x85, 0xef, 0xf0, 0x1f, 0x9b, 0x59, 0x47, 0x93, 0x07, 0xa0, 0x0a, + 0x63, 0x04, 0xe5, 0x00, 0x93, 0x07, 0x50, 0x05, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, + 0xb2, 0x49, 0x3e, 0x85, 0x05, 0x61, 0x82, 0x80, 0x41, 0x11, 0x05, 0x45, 0x06, 0xc6, 0xef, 0x30, + 0xf0, 0x7a, 0xb2, 0x40, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf4, + 0x41, 0x01, 0x82, 0x80, 0x31, 0x71, 0x22, 0xdd, 0x37, 0x34, 0x20, 0x00, 0x93, 0x07, 0x50, 0x05, + 0x06, 0xdf, 0x26, 0xdb, 0x4a, 0xd9, 0x56, 0xd3, 0x5e, 0xcf, 0x4e, 0xd7, 0x52, 0xd5, 0x5a, 0xd1, + 0x62, 0xcd, 0x66, 0xcb, 0x6a, 0xc9, 0x6e, 0xc7, 0x37, 0x39, 0x20, 0x00, 0xb7, 0x34, 0x20, 0x00, + 0xb7, 0x3b, 0x20, 0x00, 0x13, 0x04, 0x44, 0xf3, 0x23, 0x26, 0xf9, 0xf4, 0x23, 0xac, 0xf4, 0xf2, + 0x23, 0xa8, 0xfb, 0xf4, 0x1c, 0xc0, 0xef, 0x10, 0xa0, 0x32, 0xef, 0x10, 0x00, 0x4b, 0x13, 0x07, + 0xc9, 0xf4, 0x3a, 0xc8, 0x13, 0x87, 0x84, 0xf3, 0x3a, 0xca, 0x13, 0x87, 0x0b, 0xf5, 0x93, 0x07, + 0xa0, 0x0a, 0x3a, 0xc6, 0xb7, 0x5a, 0x10, 0x00, 0x85, 0x45, 0x63, 0x0a, 0xf5, 0x00, 0x13, 0x85, + 0x4a, 0x55, 0xef, 0x00, 0xd0, 0x70, 0xef, 0x10, 0xc0, 0x44, 0xef, 0xf0, 0x0f, 0xe8, 0x41, 0x45, + 0xef, 0xf0, 0x2f, 0xf3, 0x08, 0xc0, 0xb7, 0x07, 0x01, 0x02, 0x80, 0x57, 0x98, 0x5b, 0x29, 0x45, + 0x59, 0x8c, 0x98, 0x5f, 0x59, 0x8c, 0x13, 0x77, 0xfa, 0xe7, 0xa0, 0x47, 0x65, 0x38, 0x4e, 0x10, + 0x14, 0xe6, 0x1d, 0x41, 0x20, 0x84, 0x4f, 0xca, 0x4b, 0xac, 0x4e, 0x99, 0xfe, 0xb6, 0xfe, 0xb3, + 0x54, 0x1f, 0xfc, 0x79, 0x6b, 0xa6, 0x58, 0x9d, 0x2f, 0xe0, 0x14, 0xf4, 0x87, 0x98, 0xd7, 0x98, + 0xdb, 0x98, 0xdf, 0xd8, 0x43, 0x13, 0x67, 0x87, 0x00, 0xd8, 0xc3, 0xef, 0x10, 0x40, 0x2d, 0xef, + 0x30, 0x10, 0x27, 0x13, 0x75, 0x05, 0x78, 0x11, 0xc5, 0x13, 0x05, 0x00, 0x78, 0x81, 0x45, 0xef, + 0x30, 0x70, 0x1f, 0xb7, 0x07, 0x01, 0x02, 0x80, 0xd7, 0x80, 0xdb, 0x37, 0x15, 0x10, 0x00, 0x80, + 0xdf, 0x13, 0x05, 0x85, 0x9f, 0xef, 0x10, 0x00, 0x61, 0x13, 0x05, 0x00, 0x1f, 0xef, 0x10, 0x40, + 0x45, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x59, 0x10, 0x00, 0xaa, 0x86, 0x13, 0x06, 0x06, 0x5a, 0x93, + 0x85, 0x4a, 0x55, 0x13, 0x85, 0x89, 0x77, 0xef, 0x00, 0x50, 0x61, 0xef, 0x30, 0xf0, 0x22, 0x93, + 0x07, 0x50, 0x05, 0x63, 0x1e, 0xf5, 0x00, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, + 0x06, 0x06, 0x5b, 0x93, 0x85, 0x4a, 0x55, 0x13, 0x05, 0x45, 0x57, 0xef, 0x00, 0x10, 0x5f, 0xef, + 0x20, 0x20, 0x20, 0x51, 0x45, 0xef, 0x10, 0xc0, 0x40, 0x1d, 0x89, 0xef, 0x20, 0x40, 0x20, 0xef, + 0x10, 0x30, 0x74, 0xef, 0x20, 0xa0, 0x76, 0xef, 0x20, 0x40, 0x7b, 0xef, 0x20, 0x90, 0x2a, 0x37, + 0x35, 0x00, 0x08, 0xef, 0x20, 0x10, 0x2b, 0x6c, 0x10, 0x11, 0x46, 0x37, 0x35, 0x00, 0x08, 0xef, + 0x20, 0x30, 0x32, 0x37, 0x35, 0x00, 0x08, 0xef, 0x20, 0x10, 0x2e, 0x32, 0x55, 0xef, 0x20, 0x50, + 0x1f, 0x09, 0x65, 0x13, 0x05, 0x05, 0x98, 0xef, 0x20, 0x50, 0x03, 0xfd, 0x57, 0x8d, 0x45, 0x63, + 0x12, 0xf5, 0x02, 0xfa, 0x56, 0x47, 0xaa, 0x7a, 0xf3, 0xc1, 0x7b, 0x91, 0xf6, 0x2e, 0x4b, 0x52, + 0x32, 0xad, 0x1e, 0x43, 0xeb, 0x5f, 0x75, 0xc9, 0x64, 0x05, 0xce, 0xa1, 0xd5, 0x85, 0xa4, 0xe3, + 0xfe, 0xe3, 0x3b, 0x41, 0xb8, 0x15, 0x01, 0x44, 0x13, 0x09, 0x00, 0x18, 0x22, 0x85, 0xef, 0xf0, + 0x8f, 0xe2, 0xaa, 0x84, 0x22, 0x85, 0xef, 0xf0, 0x2f, 0xfb, 0x93, 0x47, 0xf5, 0xff, 0x33, 0xf5, + 0x97, 0x00, 0x19, 0xc5, 0x89, 0x45, 0x13, 0x85, 0x4a, 0x55, 0xef, 0x00, 0xb0, 0x5e, 0xcd, 0xb5, + 0x11, 0x04, 0xe3, 0x1d, 0x24, 0xfd, 0x37, 0x55, 0x10, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, + 0x50, 0x05, 0x13, 0x05, 0x45, 0x72, 0x23, 0xa4, 0xe7, 0xf4, 0xef, 0x10, 0x30, 0x10, 0xb7, 0x55, + 0x10, 0x00, 0x13, 0x06, 0x40, 0x05, 0x93, 0x85, 0x05, 0x67, 0x68, 0x10, 0xef, 0x40, 0x00, 0x2d, + 0x60, 0x10, 0x48, 0x40, 0x01, 0xc5, 0xef, 0x20, 0x80, 0x7c, 0x48, 0xc0, 0x31, 0x04, 0x1c, 0x01, + 0xe3, 0x99, 0x87, 0xfe, 0x37, 0x55, 0x10, 0x00, 0x1d, 0x46, 0x6c, 0x10, 0x13, 0x05, 0x05, 0x73, + 0xef, 0x20, 0x00, 0x36, 0xef, 0x20, 0x40, 0x4c, 0xef, 0xf0, 0xef, 0xc1, 0x05, 0x45, 0xef, 0x10, + 0xa0, 0x77, 0xef, 0x30, 0xa0, 0x50, 0xef, 0x30, 0xf0, 0x29, 0x01, 0x45, 0xef, 0x30, 0x70, 0x59, + 0x37, 0x0a, 0x20, 0x00, 0x05, 0x6c, 0x93, 0x07, 0x0a, 0x00, 0xb7, 0x14, 0x20, 0x00, 0x33, 0x8b, + 0x87, 0x01, 0x93, 0x84, 0xc4, 0x07, 0xef, 0x10, 0x80, 0x5d, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, + 0x47, 0xf4, 0x63, 0x81, 0x07, 0x10, 0x37, 0x37, 0x20, 0x00, 0x03, 0x27, 0x07, 0xf4, 0x63, 0x9b, + 0xe7, 0x0e, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xc7, 0xc7, 0xf3, 0x93, 0x87, 0xc7, 0xf3, 0xfa, 0xdc, + 0x0e, 0xdd, 0x7e, 0x5c, 0xb5, 0xff, 0xa9, 0x6d, 0x6c, 0x3a, 0xac, 0x64, 0x18, 0x57, 0x52, 0x2e, + 0xfd, 0xf3, 0x16, 0x80, 0xde, 0xb1, 0x1b, 0xb3, 0xbc, 0xb5, 0xd8, 0x26, 0x58, 0xca, 0x41, 0x90, + 0x16, 0x3e, 0xcc, 0xe3, 0x1e, 0x07, 0x2e, 0x03, 0x26, 0x0b, 0x07, 0x93, 0x07, 0xf0, 0x07, 0x37, + 0x14, 0x20, 0x00, 0xa3, 0x0c, 0xfb, 0x06, 0xc1, 0x4c, 0x13, 0x0d, 0x0a, 0x00, 0x13, 0x04, 0x04, + 0x00, 0x63, 0xfd, 0xcc, 0x0a, 0x13, 0x09, 0x06, 0xff, 0xef, 0x10, 0x40, 0x67, 0x01, 0x45, 0xef, + 0x30, 0x60, 0x54, 0x4a, 0x86, 0x63, 0xf3, 0x2c, 0x01, 0x41, 0x46, 0x93, 0x05, 0x0a, 0x00, 0x68, + 0x10, 0xef, 0x30, 0xa0, 0x56, 0xef, 0x10, 0xa0, 0x6c, 0xb7, 0x57, 0x10, 0x00, 0x23, 0x0c, 0xa4, + 0x06, 0x93, 0x87, 0x47, 0x6c, 0x03, 0xc7, 0x07, 0x00, 0x63, 0x10, 0x07, 0x14, 0x03, 0x29, 0x04, + 0x07, 0xc1, 0x4b, 0x63, 0xf5, 0x2b, 0x07, 0x01, 0x45, 0xef, 0x30, 0xc0, 0x50, 0x41, 0x19, 0x4a, + 0x86, 0x93, 0x05, 0x0a, 0x00, 0x13, 0x05, 0x0a, 0x00, 0xef, 0x30, 0x20, 0x53, 0xb7, 0x1c, 0x20, + 0x00, 0x13, 0x85, 0x0c, 0x02, 0xef, 0x30, 0xe0, 0x6f, 0xef, 0x30, 0xc0, 0x74, 0x37, 0x56, 0x10, + 0x00, 0xb7, 0x5d, 0x10, 0x00, 0xaa, 0x86, 0x13, 0x06, 0x06, 0x5c, 0x93, 0x85, 0x8d, 0x53, 0x13, + 0x85, 0x89, 0x77, 0xef, 0x00, 0xf0, 0x41, 0x93, 0x85, 0x0c, 0x02, 0x41, 0x46, 0x33, 0x05, 0x2d, + 0x01, 0xef, 0x00, 0xf0, 0x30, 0xaa, 0x8c, 0x63, 0x0f, 0x05, 0x0e, 0x89, 0x45, 0x13, 0x85, 0x8d, + 0x53, 0xef, 0x00, 0x70, 0x47, 0x93, 0x07, 0xb0, 0x07, 0xa3, 0x0c, 0xf4, 0x06, 0x37, 0x55, 0x10, + 0x00, 0x91, 0x45, 0x13, 0x05, 0xc5, 0x56, 0xef, 0x00, 0xfa, 0xa7, 0xea, 0xf6, 0xa0, 0x46, 0x14, + 0x4a, 0xb5, 0xb3, 0x67, 0x42, 0x7c, 0xc9, 0x1b, 0x9f, 0x19, 0x35, 0xe3, 0xc8, 0x59, 0x23, 0x3f, + 0x5c, 0x35, 0x7b, 0x50, 0xbc, 0xfa, 0x28, 0xf9, 0x65, 0xf6, 0x68, 0x17, 0x10, 0x46, 0xef, 0xe0, + 0x1f, 0xea, 0xef, 0xe0, 0x5f, 0xfa, 0xef, 0xf0, 0x4f, 0xa2, 0xef, 0x10, 0x00, 0x4b, 0x93, 0x07, + 0xa0, 0x0a, 0x2a, 0x84, 0x63, 0x1d, 0xf5, 0x08, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xc7, 0xc7, 0xf3, + 0xd9, 0xe7, 0xef, 0x00, 0xd0, 0x7a, 0xe3, 0x16, 0x85, 0x18, 0xd2, 0x47, 0x9c, 0x43, 0x63, 0x9a, + 0xa7, 0x00, 0x13, 0x04, 0xa0, 0x0a, 0xef, 0x30, 0xf0, 0x3a, 0xe3, 0x1e, 0x85, 0xfe, 0xef, 0x10, + 0x20, 0x10, 0xb2, 0x47, 0x98, 0x43, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1e, 0xf7, 0x14, 0x37, 0x56, + 0x10, 0x00, 0x13, 0x06, 0x46, 0x61, 0x93, 0x85, 0x4a, 0x55, 0x13, 0x85, 0x89, 0x77, 0xef, 0x00, + 0x70, 0x38, 0xef, 0xf0, 0x8f, 0x9c, 0x37, 0x25, 0x00, 0x08, 0xef, 0x20, 0x70, 0x0a, 0xef, 0xf0, + 0x0f, 0x9a, 0xef, 0x20, 0xa0, 0x59, 0xef, 0x10, 0x10, 0x0f, 0xef, 0x20, 0x50, 0x23, 0xef, 0xe0, + 0xbf, 0xe5, 0x32, 0x47, 0x37, 0x56, 0x10, 0x00, 0x93, 0x07, 0x50, 0x05, 0x13, 0x06, 0x06, 0x62, + 0x93, 0x85, 0x4a, 0x55, 0x13, 0x85, 0x89, 0x77, 0x1c, 0xc3, 0xef, 0x00, 0xb0, 0x34, 0xef, 0x20, + 0x30, 0x23, 0xef, 0x10, 0x50, 0x3b, 0xef, 0x20, 0x20, 0x5b, 0xef, 0x30, 0x90, 0x08, 0xc2, 0x47, + 0x98, 0x43, 0x93, 0x07, 0x50, 0x05, 0xe3, 0x03, 0xf7, 0xe4, 0x71, 0xb9, 0x63, 0x1c, 0xe5, 0x00, + 0x83, 0xc7, 0x17, 0x00, 0xbd, 0x8b, 0xe3, 0x8d, 0x07, 0xea, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, + 0xa0, 0x60, 0x7d, 0xb5, 0xfa, 0xca, 0xd6, 0x98, 0x56, 0xbd, 0xa0, 0x46, 0xd0, 0x15, 0x0a, 0x23, + 0x5c, 0x95, 0xab, 0xfd, 0x6d, 0xed, 0x5c, 0x4b, 0x36, 0x06, 0x35, 0xec, 0x63, 0x82, 0xfc, 0xbc, + 0x7d, 0x99, 0x5c, 0x5d, 0x93, 0x40, 0x18, 0x91, 0x07, 0x4d, 0xb5, 0x03, 0x29, 0x04, 0x07, 0xe3, + 0xef, 0x2b, 0x0d, 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0xc5, 0x56, 0xef, 0x00, 0x10, + 0x37, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x56, 0x95, 0x45, 0xef, 0x00, 0x30, 0x36, 0x13, + 0x05, 0xf0, 0x07, 0x09, 0xb7, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0xc7, 0xf5, 0x14, 0x43, 0xb7, + 0x55, 0x10, 0x00, 0xde, 0x87, 0x13, 0x86, 0x16, 0x00, 0x10, 0xc3, 0x03, 0x47, 0x84, 0x07, 0x37, + 0x56, 0x10, 0x00, 0x13, 0x06, 0x06, 0x5d, 0x93, 0x85, 0xc5, 0x56, 0x13, 0x85, 0x89, 0x77, 0xef, + 0x00, 0x90, 0x2b, 0x03, 0x47, 0x84, 0x07, 0x93, 0x06, 0x20, 0x04, 0x63, 0x07, 0xd7, 0x4c, 0x63, + 0xeb, 0xe6, 0x18, 0x93, 0x06, 0x10, 0x02, 0x63, 0x0f, 0xd7, 0x3c, 0x63, 0xe3, 0xe6, 0x08, 0xc5, + 0x46, 0x63, 0x04, 0xd7, 0x32, 0x63, 0xe9, 0xe6, 0x02, 0x85, 0x46, 0x63, 0x09, 0xd7, 0x24, 0xc1, + 0x46, 0x63, 0x02, 0xd7, 0x26, 0x89, 0x4c, 0xe5, 0xac, 0x13, 0x07, 0x07, 0xfa, 0x13, 0x77, 0xf7, + 0x0f, 0xc5, 0x46, 0xe3, 0xe9, 0xe6, 0xfe, 0xb7, 0x56, 0x10, 0x00, 0x0a, 0x07, 0x93, 0x86, 0x86, + 0x62, 0x36, 0x97, 0x18, 0x43, 0x02, 0x87, 0xc9, 0x46, 0x63, 0x0e, 0xd7, 0x34, 0x93, 0x06, 0x00, + 0x02, 0xe3, 0x1a, 0xd7, 0xfc, 0x21, 0x47, 0x93, 0x0c, 0x00, 0x08, 0x63, 0x92, 0xeb, 0x2c, 0x83, + 0x27, 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x94, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x80, 0x63, 0x9e, 0xfa, + 0x5d, 0x47, 0x07, 0x49, 0x37, 0x24, 0xf7, 0x27, 0x79, 0xec, 0x31, 0xce, 0x0d, 0xfe, 0x44, 0x29, + 0x94, 0xe2, 0x69, 0xaa, 0xd7, 0xdf, 0xf3, 0x7d, 0xc6, 0xb8, 0xa8, 0x8a, 0x64, 0x94, 0xee, 0xb3, + 0x18, 0x19, 0x07, 0x4a, 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xea, 0x87, 0x4a, 0x22, 0x85, 0xef, 0x10, + 0x50, 0x09, 0xfd, 0x57, 0x63, 0x14, 0xf5, 0x4a, 0x83, 0x25, 0x4d, 0x00, 0x22, 0x85, 0xef, 0x10, + 0x90, 0x11, 0x81, 0xae, 0x93, 0x06, 0x10, 0x03, 0x63, 0x08, 0xd7, 0x38, 0x63, 0xec, 0xe6, 0x08, + 0x93, 0x06, 0x20, 0x02, 0x63, 0x09, 0xd7, 0x36, 0x93, 0x06, 0x00, 0x03, 0xe3, 0x1e, 0xd7, 0xf6, + 0x11, 0x47, 0x93, 0x0c, 0x00, 0x08, 0x63, 0x96, 0xeb, 0x26, 0x03, 0x27, 0x0d, 0x00, 0x21, 0x83, + 0x93, 0x16, 0x07, 0x01, 0x0d, 0x8b, 0xc1, 0x82, 0x63, 0x12, 0x07, 0x46, 0x93, 0x07, 0xf0, 0x1f, + 0x63, 0xee, 0xd7, 0x44, 0x83, 0x47, 0x3d, 0x00, 0x7d, 0x47, 0x63, 0x69, 0xf7, 0x44, 0x13, 0xd4, + 0x37, 0x00, 0x36, 0x94, 0x0a, 0x04, 0x62, 0x94, 0x93, 0xfd, 0x77, 0x00, 0x22, 0x85, 0x05, 0x49, + 0xef, 0x20, 0x60, 0x4c, 0x33, 0x19, 0xb9, 0x01, 0xb3, 0x77, 0xa9, 0x00, 0xaa, 0x8c, 0x63, 0x80, + 0x07, 0x22, 0x8a, 0x0d, 0xbd, 0x45, 0xb3, 0x95, 0xb5, 0x01, 0x93, 0xc5, 0xf5, 0xff, 0x22, 0x85, + 0xef, 0x20, 0xa0, 0x4e, 0x22, 0x85, 0x13, 0x49, 0xf9, 0xff, 0xef, 0x20, 0xc0, 0x49, 0x33, 0x79, + 0x99, 0x01, 0x63, 0x0e, 0x25, 0x1f, 0x09, 0x65, 0x81, 0x45, 0x13, 0x05, 0x05, 0x98, 0xef, 0x20, + 0xc0, 0x4c, 0x75, 0xaa, 0x93, 0x06, 0x00, 0x04, 0x63, 0x0d, 0xd7, 0x30, 0x93, 0x06, 0x10, 0x04, + 0xe3, 0x14, 0xd7, 0xee, 0x0d, 0x47, 0x63, 0x90, 0xeb, 0x72, 0xfa, 0xc8, 0xac, 0x7e, 0x5b, 0x3e, + 0x4e, 0x2a, 0x54, 0xb0, 0xb5, 0x35, 0x35, 0x71, 0xe0, 0xfd, 0x7c, 0x51, 0x88, 0x42, 0x00, 0x53, + 0x9a, 0x2c, 0x83, 0x26, 0xb5, 0x77, 0x4b, 0x2b, 0xac, 0x18, 0x22, 0xf0, 0x19, 0x83, 0x27, 0x0d, + 0x00, 0x13, 0x07, 0xf0, 0x1f, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, 0x63, 0x6a, 0xf7, 0x3c, 0xef, + 0x10, 0xf0, 0x48, 0xef, 0x20, 0xe0, 0x75, 0x83, 0x27, 0x0d, 0x00, 0x91, 0x65, 0x93, 0x85, 0x05, + 0x20, 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, 0xa6, 0x07, 0x37, 0x15, 0x20, 0x00, 0xbe, 0x95, 0x13, + 0x05, 0x05, 0x08, 0xef, 0x10, 0xd0, 0x0a, 0x2a, 0x84, 0xef, 0x20, 0xa0, 0x75, 0x93, 0x07, 0xb0, + 0x1d, 0xe3, 0xe7, 0x87, 0xa8, 0x93, 0x05, 0x44, 0x00, 0x39, 0xa4, 0x93, 0x06, 0x10, 0x07, 0x63, + 0xe9, 0xe6, 0x02, 0x93, 0x06, 0xf0, 0x05, 0xe3, 0xe4, 0xe6, 0xe8, 0x93, 0x06, 0x00, 0x05, 0xe3, + 0x1e, 0xd7, 0xe6, 0x09, 0x47, 0x93, 0x0c, 0x00, 0x08, 0x63, 0x96, 0xeb, 0x16, 0x03, 0x44, 0x1d, + 0x00, 0x37, 0x15, 0x20, 0x00, 0x13, 0x05, 0x05, 0x08, 0xa2, 0x85, 0xef, 0xe0, 0x9f, 0xc7, 0xd9, + 0xb7, 0x93, 0x06, 0x20, 0x08, 0x63, 0x09, 0xd7, 0x64, 0x63, 0xed, 0xe6, 0x04, 0x93, 0x06, 0x00, + 0x08, 0x63, 0x00, 0xd7, 0x5e, 0x93, 0x06, 0x10, 0x08, 0xe3, 0x11, 0xd7, 0xe4, 0x0d, 0x47, 0x93, + 0x0c, 0x00, 0x08, 0x63, 0x99, 0xeb, 0x12, 0x03, 0x45, 0x1d, 0x00, 0x3d, 0x47, 0x81, 0x47, 0x63, + 0x6e, 0xa7, 0x00, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf6, 0x89, 0x47, 0x33, 0x57, 0xa7, + 0x00, 0x05, 0x8b, 0x01, 0xc7, 0xef, 0xe0, 0xff, 0xd6, 0xaa, 0x87, 0xfd, 0x17, 0x09, 0x47, 0x63, + 0x68, 0xf7, 0x30, 0x37, 0x65, 0xfa, 0xcc, 0xad, 0x82, 0xbd, 0x2b, 0x90, 0x53, 0x35, 0x2a, 0x42, + 0xc5, 0x83, 0x22, 0x72, 0x80, 0x54, 0x91, 0x8f, 0xa3, 0x7a, 0xd5, 0xdc, 0x0e, 0x5c, 0xa1, 0x05, + 0x76, 0xb4, 0xfd, 0x60, 0x9d, 0x2d, 0xc8, 0x1a, 0x10, 0x00, 0x13, 0x05, 0x85, 0x87, 0xaa, 0x97, + 0x83, 0xcc, 0x07, 0x00, 0xd5, 0xa8, 0x93, 0x06, 0x00, 0x09, 0xe3, 0x1a, 0xd7, 0xde, 0x13, 0x07, + 0x40, 0x02, 0x93, 0x0c, 0x00, 0x08, 0x63, 0x91, 0xeb, 0x0e, 0xef, 0x20, 0x20, 0x01, 0xef, 0x20, + 0x60, 0x67, 0xef, 0x20, 0xa0, 0x01, 0x2a, 0x89, 0xef, 0x20, 0xc0, 0x00, 0xef, 0x20, 0xa0, 0x68, + 0x13, 0x07, 0xa0, 0x0a, 0x63, 0x17, 0xe9, 0x2c, 0x13, 0x05, 0xa0, 0x0a, 0xef, 0x30, 0x80, 0x33, + 0x23, 0x2a, 0x74, 0x07, 0x45, 0xa8, 0x13, 0x07, 0x1c, 0x00, 0x93, 0x0c, 0x00, 0x08, 0x63, 0x65, + 0x77, 0x0b, 0xde, 0x85, 0x13, 0x05, 0x0a, 0x00, 0xef, 0xe0, 0xff, 0xee, 0x61, 0xa8, 0x13, 0x07, + 0x40, 0x02, 0x63, 0x9d, 0xeb, 0x5c, 0x03, 0x25, 0x0d, 0x00, 0x0d, 0x44, 0x21, 0x81, 0x42, 0x05, + 0x41, 0x81, 0x63, 0x68, 0xa4, 0x28, 0xef, 0xf0, 0x8f, 0xa7, 0xd5, 0x47, 0x63, 0x13, 0xf5, 0x28, + 0x03, 0x29, 0x0d, 0x00, 0x13, 0x59, 0x89, 0x00, 0x42, 0x09, 0x13, 0x59, 0x09, 0x01, 0xe3, 0x62, + 0x24, 0x97, 0x13, 0x04, 0x09, 0x0e, 0x16, 0x04, 0x91, 0x4c, 0x71, 0x14, 0x93, 0x0b, 0xa0, 0x0a, + 0x93, 0x0d, 0x40, 0x02, 0xb3, 0x05, 0x9d, 0x01, 0x11, 0x46, 0x68, 0x10, 0xef, 0x30, 0x30, 0x56, + 0xb2, 0x55, 0x33, 0x05, 0x94, 0x01, 0xef, 0x20, 0xc0, 0x36, 0x63, 0x07, 0x75, 0x01, 0x4a, 0x85, + 0xef, 0xf0, 0x9f, 0x83, 0xdd, 0x4c, 0x0d, 0xa8, 0x91, 0x0c, 0xe3, 0x9d, 0xbc, 0xfd, 0x89, 0x67, + 0xfa, 0x51, 0xff, 0x8d, 0x38, 0x3c, 0xb7, 0xe2, 0x1d, 0x58, 0x65, 0x27, 0x3b, 0x01, 0x58, 0x45, + 0xd0, 0x2d, 0x69, 0x94, 0xbc, 0x06, 0xee, 0xe3, 0x61, 0xf5, 0x49, 0xb2, 0xae, 0x2f, 0x0a, 0xce, + 0xf4, 0xa0, 0x1b, 0x93, 0x87, 0x07, 0xbf, 0x13, 0x15, 0x29, 0x00, 0xb7, 0xf5, 0xf0, 0xf0, 0x3e, + 0x95, 0x93, 0x85, 0x05, 0x0f, 0xef, 0x20, 0xe0, 0x2e, 0x4a, 0x85, 0xef, 0xf0, 0x6f, 0xa0, 0x93, + 0x07, 0x30, 0x0c, 0xe3, 0x1a, 0xf5, 0xfc, 0x93, 0x0c, 0x30, 0x0c, 0x13, 0x06, 0x0c, 0x01, 0x81, + 0x45, 0x26, 0x85, 0xef, 0x30, 0xb0, 0x54, 0x93, 0x07, 0x00, 0x08, 0xe3, 0x81, 0xfc, 0xc8, 0x13, + 0xf5, 0xfc, 0x0f, 0x4d, 0xa3, 0x0d, 0x47, 0x63, 0x94, 0xeb, 0x52, 0x03, 0x25, 0x0d, 0x00, 0x0d, + 0x44, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0x6f, 0xa4, 0x1c, 0xef, 0xf0, 0x6f, 0x9c, 0x93, + 0x07, 0x30, 0x0c, 0x63, 0x04, 0xf5, 0x00, 0xaa, 0x8c, 0xc9, 0xb7, 0x83, 0x27, 0x0d, 0x00, 0xa1, + 0x83, 0xc2, 0x07, 0xc1, 0x83, 0xe3, 0x68, 0xf4, 0x8a, 0x93, 0x87, 0x07, 0x0e, 0x13, 0x94, 0x57, + 0x00, 0x13, 0x09, 0x00, 0x02, 0x33, 0x85, 0x8c, 0x00, 0xef, 0x20, 0xa0, 0x1b, 0xb7, 0x17, 0x20, + 0x00, 0x93, 0x87, 0x07, 0x08, 0x2a, 0xd6, 0x11, 0x46, 0x33, 0x85, 0x97, 0x01, 0x6c, 0x10, 0x91, + 0x0c, 0xef, 0x30, 0x10, 0x4a, 0xe3, 0x90, 0x2c, 0xff, 0x93, 0x05, 0x40, 0x02, 0x26, 0x85, 0xf1, + 0xbd, 0x0d, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x9a, 0xeb, 0xf6, 0x03, 0x25, 0x0d, 0x00, 0x21, + 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0xe8, 0xab, 0x16, 0xef, 0xf0, 0x8f, 0x95, 0xd5, 0x47, 0x63, + 0x03, 0xf5, 0x16, 0xd9, 0x47, 0x93, 0x0c, 0x30, 0x0c, 0xe3, 0x09, 0xfa, 0x2a, 0x6d, 0x1c, 0xba, + 0x2a, 0x0e, 0x06, 0x18, 0xc4, 0x5f, 0xd4, 0x9d, 0x5d, 0x46, 0x6f, 0x5d, 0x09, 0xc4, 0xd5, 0xf2, + 0x20, 0x95, 0x98, 0x5b, 0x21, 0x74, 0x76, 0x25, 0xb9, 0xb0, 0x8d, 0x4c, 0x78, 0x1c, 0xf5, 0xf4, + 0x03, 0x25, 0x0d, 0x00, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0xef, 0xf0, 0x4f, 0xf4, 0x93, 0x07, + 0xa0, 0x0a, 0x15, 0xbf, 0x0d, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x9a, 0xeb, 0xf2, 0x83, 0x27, + 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x81, 0x63, 0x96, 0x07, 0x12, + 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe2, 0xa7, 0x12, 0xef, 0x10, 0x60, 0x50, 0xc8, 0xc0, 0xa1, 0x45, + 0x41, 0xbf, 0x05, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x93, 0xeb, 0xf0, 0x01, 0x45, 0xef, 0x10, + 0x70, 0x19, 0xe5, 0xbd, 0x0d, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x9a, 0xeb, 0xee, 0x83, 0x27, + 0x0d, 0x00, 0xa1, 0x83, 0x13, 0x95, 0x07, 0x01, 0x8d, 0x8b, 0x41, 0x81, 0x63, 0x96, 0x07, 0x0e, + 0x93, 0x07, 0xf0, 0x1f, 0x63, 0xe2, 0xa7, 0x0e, 0xef, 0xf0, 0x8f, 0x88, 0xc1, 0xb7, 0x93, 0x07, + 0xb9, 0xfe, 0x13, 0x07, 0xa0, 0x1d, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x62, 0xf7, 0xec, 0x03, 0x25, + 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0x21, 0x81, 0x42, 0x05, 0x41, 0x81, 0x63, 0xee, 0xa7, 0x0a, + 0x11, 0x64, 0x26, 0x05, 0x13, 0x04, 0x04, 0x20, 0x22, 0x95, 0xef, 0x10, 0xb0, 0x0f, 0x93, 0x07, + 0xa0, 0x0a, 0xaa, 0x8d, 0xc1, 0x4c, 0xe3, 0x1c, 0xf5, 0xe8, 0xc1, 0x45, 0x68, 0x10, 0xef, 0xe0, + 0xff, 0x9a, 0xef, 0x20, 0x80, 0x42, 0x83, 0x27, 0x0d, 0x00, 0xb7, 0x05, 0x20, 0x00, 0x74, 0x10, + 0xa1, 0x83, 0xc2, 0x07, 0xc1, 0x83, 0xfa, 0xae, 0x20, 0x89, 0x54, 0xcb, 0x4c, 0xf8, 0xd7, 0x3e, + 0xde, 0xdc, 0x9f, 0xf4, 0x09, 0x40, 0xcf, 0x42, 0x9b, 0x8d, 0x5f, 0x6c, 0x9d, 0x47, 0xa1, 0x11, + 0xd6, 0x67, 0x24, 0x36, 0xda, 0x53, 0xee, 0x50, 0x1d, 0xa6, 0x07, 0x33, 0x85, 0x87, 0x00, 0x13, + 0x06, 0xc9, 0xfe, 0x93, 0x85, 0x45, 0x00, 0xef, 0x10, 0x80, 0x7f, 0x2a, 0x84, 0x93, 0x0c, 0x30, + 0x0c, 0xef, 0x20, 0xe0, 0x41, 0xe3, 0x14, 0xb4, 0xe3, 0xa1, 0xbd, 0x0d, 0x47, 0x93, 0x0c, 0x00, + 0x08, 0xe3, 0x98, 0xeb, 0xe4, 0x03, 0x25, 0x0d, 0x00, 0x93, 0x07, 0xf0, 0x1f, 0x21, 0x81, 0x42, + 0x05, 0x41, 0x81, 0x63, 0xe4, 0xa7, 0x04, 0x91, 0x67, 0x26, 0x05, 0x93, 0x87, 0x07, 0x20, 0x3e, + 0x95, 0x05, 0xbf, 0x11, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x94, 0xeb, 0xe2, 0xc1, 0x45, 0x68, + 0x10, 0xef, 0xe0, 0xff, 0x93, 0x68, 0x10, 0xef, 0x10, 0x80, 0x79, 0xef, 0x30, 0xc0, 0x32, 0xef, + 0x20, 0xe0, 0x3a, 0x91, 0x45, 0x13, 0x05, 0x00, 0x06, 0xef, 0x30, 0x00, 0x47, 0x2a, 0x84, 0xef, + 0x20, 0x00, 0x3c, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x0b, 0xf4, 0xde, 0x93, 0x0c, 0xc0, 0x03, 0xcd, + 0xbb, 0x13, 0x07, 0x00, 0x03, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x94, 0xeb, 0xde, 0xc1, 0x45, 0x68, + 0x10, 0xef, 0xe0, 0xff, 0x8f, 0x68, 0x10, 0xef, 0x10, 0x80, 0x75, 0xef, 0x30, 0xc0, 0x2e, 0xef, + 0x20, 0xe0, 0x36, 0x93, 0x05, 0x00, 0x03, 0x13, 0x05, 0x10, 0x06, 0x7d, 0xbf, 0x0d, 0x47, 0x93, + 0x0c, 0x00, 0x08, 0xe3, 0x9f, 0xeb, 0xda, 0xef, 0x30, 0x00, 0x2d, 0xef, 0x20, 0x20, 0x35, 0x8d, + 0x45, 0x13, 0x05, 0x20, 0x06, 0xef, 0x30, 0x40, 0x41, 0x2a, 0x84, 0xef, 0x20, 0x40, 0x36, 0x93, + 0x07, 0xfa, 0x21, 0x45, 0x84, 0x92, 0x61, 0x6a, 0xbf, 0x01, 0x16, 0xa6, 0xef, 0xb0, 0x10, 0x26, + 0x9d, 0xa1, 0x77, 0x29, 0x5d, 0xd9, 0x0c, 0x08, 0x62, 0x30, 0xc9, 0xd4, 0x20, 0xc6, 0x20, 0x26, + 0xce, 0xa5, 0x28, 0x1e, 0xa0, 0x0a, 0xe3, 0x14, 0xf4, 0xfa, 0xef, 0xe0, 0x9f, 0xd8, 0xc9, 0xbb, + 0x0d, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x97, 0xeb, 0xd8, 0xef, 0x30, 0x00, 0x2a, 0x8d, 0x45, + 0x13, 0x05, 0x30, 0x06, 0xef, 0x30, 0x80, 0x3e, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x11, 0xf5, 0xf8, + 0x85, 0xbb, 0x13, 0x07, 0x00, 0x03, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x95, 0xeb, 0xd6, 0xef, 0x30, + 0xc0, 0x27, 0xef, 0x20, 0xf0, 0x7f, 0xb7, 0x15, 0x20, 0x00, 0x2a, 0xd6, 0x13, 0x06, 0x00, 0x02, + 0x93, 0x85, 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, 0xef, 0x30, 0xa0, 0x31, 0x11, 0x46, 0x6c, 0x10, + 0x13, 0x05, 0x00, 0x0c, 0xef, 0x30, 0xe0, 0x30, 0xef, 0x20, 0x80, 0x2d, 0x93, 0x05, 0x40, 0x02, + 0x13, 0x05, 0x00, 0x07, 0xef, 0x30, 0x80, 0x39, 0x2a, 0x84, 0xef, 0x20, 0x80, 0x2e, 0x93, 0x07, + 0xa0, 0x0a, 0xe3, 0x16, 0xf4, 0xf2, 0xef, 0xe0, 0xdf, 0xd0, 0x99, 0xbb, 0x3d, 0x47, 0x93, 0x0c, + 0x00, 0x08, 0xe3, 0x79, 0x77, 0xd1, 0xef, 0x30, 0x40, 0x22, 0xef, 0x20, 0x70, 0x7a, 0xaa, 0x8c, + 0x01, 0x45, 0xef, 0x20, 0xf0, 0x53, 0x41, 0x46, 0x93, 0x05, 0x0a, 0x00, 0x01, 0x45, 0xef, 0x20, + 0x90, 0x56, 0xef, 0x20, 0xe0, 0x28, 0xb7, 0x15, 0x20, 0x00, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, + 0x05, 0x05, 0x13, 0x05, 0x00, 0x0a, 0x66, 0xd6, 0xef, 0x30, 0xa0, 0x2a, 0x11, 0x46, 0x6c, 0x10, + 0x13, 0x05, 0x00, 0x0c, 0xef, 0x30, 0xe0, 0x29, 0x85, 0x45, 0x13, 0x05, 0xfa, 0x78, 0x2b, 0x26, + 0x00, 0x24, 0x3b, 0x4f, 0xbc, 0x4a, 0x35, 0xa8, 0x5b, 0x42, 0xa5, 0x87, 0x80, 0xcf, 0xb4, 0x5c, + 0x87, 0x92, 0xd6, 0xd3, 0x48, 0x3c, 0xcc, 0x0c, 0xd0, 0x17, 0x84, 0x4d, 0x35, 0x00, 0x1f, 0x10, + 0x04, 0xef, 0x30, 0xe0, 0x32, 0x93, 0x07, 0xa0, 0x0a, 0xaa, 0x8c, 0x63, 0x19, 0xf5, 0x00, 0x81, + 0x45, 0x13, 0x05, 0x20, 0x04, 0xef, 0x30, 0xa0, 0x31, 0x63, 0x05, 0x95, 0x01, 0xef, 0x20, 0x80, + 0x26, 0x45, 0xbd, 0xef, 0x20, 0x20, 0x26, 0x37, 0x07, 0x20, 0x00, 0x93, 0x0d, 0x09, 0xfe, 0xee, + 0x8c, 0x13, 0x0d, 0x07, 0x01, 0xba, 0x8b, 0x13, 0x07, 0x00, 0x09, 0x63, 0x62, 0x97, 0x09, 0xea, + 0x85, 0x66, 0x86, 0x01, 0x45, 0xef, 0x20, 0x50, 0x4f, 0xe6, 0x85, 0x13, 0x05, 0x40, 0x04, 0xef, + 0x30, 0x00, 0x2e, 0x13, 0x07, 0xa0, 0x0a, 0x2a, 0x8d, 0xe3, 0x1c, 0xe5, 0xe6, 0x81, 0x45, 0x13, + 0x05, 0x50, 0x04, 0xef, 0x30, 0xc0, 0x2c, 0xaa, 0x8c, 0xe3, 0x14, 0xa5, 0xe7, 0x01, 0x45, 0xef, + 0x20, 0x50, 0x49, 0x41, 0x46, 0x93, 0x05, 0x0a, 0x00, 0x01, 0x45, 0xef, 0x20, 0xf0, 0x4b, 0x93, + 0x07, 0xf0, 0x03, 0x63, 0xe3, 0xb7, 0x07, 0x93, 0x85, 0x0b, 0x01, 0x01, 0x45, 0x6e, 0x86, 0xef, + 0x20, 0xb0, 0x4a, 0xee, 0x85, 0x13, 0x05, 0x60, 0x04, 0xef, 0x30, 0x60, 0x29, 0xe3, 0x1a, 0x95, + 0xe3, 0x81, 0x45, 0x13, 0x05, 0xa0, 0x04, 0xef, 0x30, 0x80, 0x28, 0x93, 0x07, 0xa0, 0x0a, 0xe3, + 0x11, 0xf5, 0xe2, 0xef, 0x20, 0x10, 0x69, 0x93, 0x07, 0x00, 0x05, 0x7c, 0xd8, 0x19, 0xb1, 0x13, + 0x06, 0x00, 0x09, 0xea, 0x85, 0x01, 0x45, 0xef, 0x20, 0x30, 0x47, 0x93, 0x05, 0x00, 0x09, 0x13, + 0x05, 0x30, 0x04, 0xef, 0x30, 0xc0, 0x25, 0xfa, 0x75, 0xc0, 0xf6, 0xbb, 0x52, 0x0a, 0x2a, 0xdc, + 0x01, 0xf1, 0xee, 0xfb, 0x1b, 0xf3, 0x7a, 0x1d, 0x4d, 0x3b, 0xae, 0xcc, 0x74, 0x12, 0x28, 0xaf, + 0x96, 0x85, 0xf2, 0x67, 0xeb, 0xcf, 0x10, 0x52, 0xd8, 0x1f, 0x93, 0x06, 0xa0, 0x0a, 0xe3, 0x1b, + 0xd5, 0xde, 0x93, 0x8c, 0x0c, 0xf7, 0x13, 0x0d, 0x0d, 0x09, 0x81, 0xbf, 0x93, 0x85, 0x0b, 0x01, + 0x01, 0x45, 0x13, 0x06, 0x00, 0x04, 0xef, 0x20, 0x70, 0x44, 0x93, 0x05, 0x00, 0x04, 0x13, 0x05, + 0x70, 0x04, 0xef, 0x30, 0x00, 0x23, 0xe3, 0x17, 0x95, 0xdd, 0xb7, 0x0c, 0x20, 0x00, 0x13, 0x09, + 0x09, 0xfa, 0x93, 0x8c, 0x0c, 0x05, 0x93, 0x0d, 0x00, 0x08, 0x93, 0x0b, 0xa0, 0x0a, 0x63, 0xe1, + 0x2d, 0x03, 0x4a, 0x86, 0xe6, 0x85, 0x01, 0x45, 0xef, 0x20, 0x50, 0x41, 0xca, 0x85, 0x13, 0x05, + 0x90, 0x04, 0xef, 0x30, 0x00, 0x20, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x1d, 0xf5, 0xd8, 0x9d, 0xb7, + 0xe6, 0x85, 0x01, 0x45, 0x13, 0x06, 0x00, 0x08, 0xef, 0x20, 0x50, 0x3f, 0x93, 0x05, 0x00, 0x08, + 0x13, 0x05, 0x80, 0x04, 0xef, 0x30, 0xe0, 0x1d, 0xe3, 0x1e, 0x75, 0xd7, 0x13, 0x09, 0x09, 0xf8, + 0x93, 0x8c, 0x0c, 0x08, 0x6d, 0xbf, 0x21, 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x9f, 0xeb, 0xb4, + 0x03, 0x44, 0x1d, 0x00, 0xbd, 0x47, 0xe3, 0xef, 0x87, 0xd4, 0x83, 0x2c, 0x4d, 0x00, 0xfd, 0x57, + 0xe3, 0x8a, 0xfc, 0xd4, 0x13, 0x19, 0xa4, 0x00, 0x13, 0x05, 0x09, 0x40, 0xef, 0xe0, 0x4f, 0xe1, + 0x13, 0x07, 0xa0, 0x0a, 0xaa, 0x8b, 0xe3, 0x1f, 0xe5, 0xd2, 0x13, 0x09, 0x09, 0x20, 0x4a, 0x85, + 0xef, 0xe0, 0x0f, 0xe0, 0xaa, 0x8d, 0xe3, 0x17, 0x75, 0xd3, 0xe6, 0x85, 0x4a, 0x85, 0xef, 0x10, + 0x20, 0x17, 0xfa, 0xcc, 0x39, 0x15, 0x60, 0xa6, 0x46, 0x3e, 0xc1, 0xd1, 0x79, 0x47, 0xc8, 0x9b, + 0xd6, 0x75, 0x4b, 0x47, 0x01, 0xf1, 0x2a, 0xc2, 0x5b, 0x50, 0xb8, 0xf6, 0x1f, 0xc9, 0xaf, 0xc8, + 0x40, 0x80, 0xf6, 0xb0, 0x20, 0xe3, 0x11, 0xb5, 0xd3, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x07, + 0xf6, 0x85, 0x47, 0x33, 0x94, 0x87, 0x00, 0x1c, 0x43, 0x5d, 0x8c, 0x00, 0xc3, 0xf5, 0xbc, 0x0d, + 0x47, 0x93, 0x0c, 0x00, 0x08, 0xe3, 0x9c, 0xeb, 0xae, 0x83, 0x45, 0x1d, 0x00, 0xbd, 0x47, 0xe3, + 0xec, 0xb7, 0xce, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xf6, 0xd1, 0x4c, 0xb3, 0xd7, 0xb7, + 0x00, 0x85, 0x8b, 0xe3, 0x8d, 0x07, 0xac, 0x37, 0x15, 0x20, 0x00, 0x13, 0x05, 0x05, 0x08, 0xef, + 0xe0, 0x2f, 0xe6, 0x85, 0x47, 0xe3, 0x0c, 0xf5, 0xba, 0x89, 0x47, 0xe3, 0x01, 0xf5, 0xac, 0xe1, + 0xb1, 0x93, 0x0c, 0x00, 0x08, 0x65, 0xbc, 0xef, 0x10, 0x70, 0x46, 0xef, 0xe0, 0xef, 0xd2, 0x6f, + 0xf0, 0x8f, 0xef, 0xef, 0x00, 0xc0, 0x6f, 0x6f, 0xf0, 0x8f, 0xef, 0xef, 0x00, 0x30, 0x4b, 0x93, + 0x0b, 0x09, 0xff, 0xaa, 0x86, 0x63, 0x0f, 0x05, 0xf2, 0x8d, 0x45, 0x13, 0x85, 0x8d, 0x53, 0x36, + 0xce, 0x69, 0x24, 0xf2, 0x46, 0x37, 0x56, 0x10, 0x00, 0x13, 0x06, 0x86, 0x5c, 0x93, 0x85, 0x8d, + 0x53, 0x13, 0x85, 0x89, 0x77, 0x01, 0x24, 0xf2, 0x46, 0x09, 0x46, 0x05, 0x47, 0x63, 0x83, 0xc6, + 0x00, 0x09, 0x47, 0x83, 0x46, 0x84, 0x07, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0xa3, + 0x0c, 0xe4, 0x06, 0x13, 0x06, 0x86, 0x5e, 0x5e, 0x87, 0x93, 0x85, 0xc5, 0x56, 0x13, 0x85, 0x89, + 0x77, 0xd1, 0x2a, 0xef, 0xe0, 0xcf, 0xc8, 0xef, 0xe0, 0xcf, 0xf9, 0x62, 0x47, 0xfa, 0x57, 0x37, + 0xf4, 0x3b, 0x81, 0x8a, 0x45, 0x6e, 0xf0, 0xcd, 0x0d, 0x91, 0x60, 0xbb, 0x72, 0x97, 0xc3, 0xe6, + 0x19, 0xa8, 0xa5, 0x11, 0x07, 0x3a, 0x66, 0x13, 0x37, 0x87, 0x58, 0x95, 0xb8, 0x83, 0x88, 0x21, + 0x85, 0x47, 0x23, 0x00, 0xf7, 0x00, 0xef, 0x00, 0xc0, 0x5a, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, + 0x63, 0x1f, 0xf5, 0xdc, 0x1d, 0x29, 0x2a, 0x84, 0x63, 0x1b, 0x25, 0xdd, 0xef, 0x30, 0xc0, 0x1a, + 0x63, 0x17, 0x85, 0xdc, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x87, 0xf5, 0xb1, 0xeb, 0x83, 0x27, + 0x4b, 0x07, 0x13, 0x07, 0xfc, 0x00, 0xfd, 0x17, 0x63, 0x64, 0xf7, 0x04, 0x05, 0x45, 0xef, 0x20, + 0xf0, 0x23, 0x03, 0x26, 0x4b, 0x07, 0x37, 0x09, 0x20, 0x00, 0x93, 0x05, 0x09, 0x00, 0x13, 0x05, + 0x09, 0x00, 0xef, 0x20, 0x10, 0x34, 0x37, 0x14, 0x20, 0x00, 0x13, 0x05, 0x04, 0x02, 0xef, 0x20, + 0xd0, 0x42, 0x03, 0x25, 0x4b, 0x07, 0x93, 0x07, 0x09, 0x00, 0x41, 0x46, 0x3e, 0x95, 0x93, 0x05, + 0x04, 0x02, 0xef, 0x30, 0x40, 0x6e, 0x83, 0x27, 0x4b, 0x07, 0xc1, 0x07, 0x23, 0x2a, 0xfb, 0x06, + 0xef, 0x00, 0x70, 0x1e, 0x13, 0x04, 0xa0, 0x0a, 0x63, 0x03, 0x85, 0xd6, 0xef, 0xe0, 0x5f, 0xa2, + 0x63, 0x1f, 0x85, 0xd4, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, + 0x13, 0x06, 0xc6, 0x60, 0x93, 0x85, 0xc5, 0x56, 0x13, 0x05, 0x45, 0x57, 0x31, 0x2a, 0xef, 0xe0, + 0xaf, 0xb0, 0xef, 0x20, 0x50, 0x41, 0xef, 0x00, 0xd0, 0x36, 0xef, 0x00, 0xd0, 0x2d, 0xef, 0xe0, + 0x4f, 0xf3, 0x6f, 0xf0, 0xcf, 0xd2, 0x2a, 0x87, 0x81, 0x47, 0x01, 0x45, 0x63, 0x93, 0xc7, 0x00, + 0x82, 0x80, 0xb3, 0x06, 0xf7, 0x00, 0x33, 0x88, 0xfa, 0x5f, 0xcd, 0x6c, 0xbf, 0xbc, 0x78, 0x9d, + 0xb4, 0xf3, 0xa4, 0xbd, 0x69, 0xec, 0x25, 0x6b, 0x9c, 0xa5, 0x3b, 0xe9, 0xc0, 0x30, 0x80, 0x75, + 0x8b, 0x9c, 0x82, 0x87, 0xc4, 0xa7, 0xbf, 0x17, 0xa1, 0x60, 0x22, 0xf5, 0x00, 0x83, 0xc6, 0x06, + 0x00, 0x03, 0x48, 0x08, 0x00, 0x85, 0x07, 0xb3, 0xc6, 0x06, 0x01, 0x55, 0x8d, 0x13, 0x75, 0xf5, + 0x0f, 0xf9, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x37, 0x37, 0x20, 0x00, 0x03, 0xa8, 0x87, 0xf6, 0x83, + 0x27, 0x47, 0xf6, 0xaa, 0x86, 0x13, 0x07, 0x47, 0xf6, 0x01, 0x45, 0x63, 0x13, 0xf8, 0x00, 0x82, + 0x80, 0x37, 0x26, 0x20, 0x00, 0x13, 0x06, 0xc6, 0x08, 0x93, 0x08, 0xf0, 0x7f, 0x63, 0x01, 0xb5, + 0x02, 0x33, 0x0e, 0xf6, 0x00, 0x03, 0x4e, 0x0e, 0x00, 0x05, 0x05, 0x33, 0x83, 0xa6, 0x00, 0xa3, + 0x0f, 0xc3, 0xff, 0x85, 0x07, 0x63, 0xf3, 0xf8, 0x00, 0x81, 0x47, 0xe3, 0x11, 0xf8, 0xfe, 0x1c, + 0xc3, 0x82, 0x80, 0x93, 0x07, 0xf0, 0x7f, 0x63, 0xe5, 0xa7, 0x02, 0xb7, 0x36, 0x20, 0x00, 0xb7, + 0x37, 0x20, 0x00, 0x93, 0x86, 0x46, 0xf6, 0x83, 0xa7, 0x87, 0xf6, 0x98, 0x42, 0x33, 0x87, 0xe7, + 0x40, 0x13, 0x77, 0xf7, 0x7f, 0x63, 0x76, 0xe5, 0x00, 0x89, 0x8f, 0x93, 0xf7, 0xf7, 0x7f, 0x9c, + 0xc2, 0x82, 0x80, 0xb7, 0x36, 0x20, 0x00, 0x03, 0xa8, 0x86, 0xf6, 0x13, 0x07, 0xf0, 0x7f, 0x13, + 0x86, 0x86, 0xf6, 0x93, 0x07, 0x18, 0x00, 0x63, 0x73, 0xf7, 0x00, 0x81, 0x47, 0xb7, 0x36, 0x20, + 0x00, 0x83, 0xa8, 0x46, 0xf6, 0x37, 0x27, 0x20, 0x00, 0x93, 0x85, 0x46, 0xf6, 0x13, 0x07, 0xc7, + 0x08, 0x63, 0x9f, 0xf8, 0x00, 0x93, 0x88, 0x17, 0x80, 0x93, 0x86, 0x17, 0x00, 0x63, 0x93, 0x08, + 0x00, 0x81, 0x46, 0xfa, 0xec, 0xae, 0x52, 0x4e, 0x3a, 0xe5, 0xee, 0xa8, 0x62, 0x06, 0x5f, 0x13, + 0x3c, 0x1b, 0x5d, 0x82, 0x5a, 0x18, 0xdd, 0xb7, 0x69, 0x5c, 0x0d, 0xc9, 0x72, 0xd7, 0xda, 0x51, + 0x19, 0x3c, 0x77, 0x32, 0x38, 0x23, 0x94, 0xc1, 0xba, 0x96, 0x93, 0x05, 0xa0, 0x02, 0x23, 0x80, + 0xb6, 0x00, 0x42, 0x97, 0x23, 0x00, 0xa7, 0x00, 0x1c, 0xc2, 0x82, 0x80, 0x82, 0x80, 0x39, 0x71, + 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x06, 0xce, 0x36, 0xd6, 0x3a, 0xd8, 0x3e, 0xda, 0x42, 0xdc, + 0x46, 0xde, 0xaa, 0x84, 0x2e, 0x89, 0x32, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x6f, 0xfd, 0x63, 0x14, + 0x09, 0x00, 0xef, 0xe0, 0xef, 0xfc, 0x19, 0xe0, 0xef, 0xe0, 0x8f, 0xfc, 0x7c, 0x10, 0x3e, 0xc6, + 0xef, 0x30, 0x40, 0x21, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0xc5, 0x73, 0xef, 0x30, + 0x40, 0x46, 0x37, 0x55, 0x10, 0x00, 0x4a, 0x86, 0xa6, 0x85, 0x13, 0x05, 0x45, 0x74, 0xef, 0x30, + 0x40, 0x45, 0xb2, 0x45, 0x22, 0x85, 0xef, 0x30, 0xa0, 0x41, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, + 0x05, 0x75, 0xef, 0x30, 0x00, 0x44, 0xb9, 0x29, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, + 0x21, 0x61, 0x82, 0x80, 0xae, 0x86, 0x37, 0x56, 0x10, 0x00, 0xaa, 0x85, 0x37, 0x55, 0x10, 0x00, + 0x13, 0x06, 0x46, 0x5e, 0x13, 0x05, 0x45, 0x75, 0x9d, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, + 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, 0x83, 0xa6, 0x47, 0x10, 0x63, 0x7e, 0xd7, 0x00, 0x0a, 0x07, + 0x3e, 0x97, 0x18, 0x43, 0x18, 0xc1, 0x03, 0xa7, 0x07, 0x10, 0x13, 0x05, 0xa0, 0x0a, 0x05, 0x07, + 0x23, 0xa0, 0xe7, 0x10, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, 0xfa, 0xb9, + 0x54, 0x2d, 0xce, 0x33, 0xa4, 0x18, 0x9b, 0xd2, 0x68, 0xf4, 0xba, 0x6f, 0x38, 0x40, 0x92, 0x18, + 0x9e, 0x71, 0x02, 0xd5, 0xcd, 0xb2, 0xba, 0x58, 0xce, 0x29, 0x89, 0x4c, 0xf8, 0xe9, 0x66, 0x10, + 0x24, 0x26, 0xca, 0xb7, 0x34, 0x20, 0x00, 0x83, 0xa7, 0xc4, 0xf6, 0x06, 0xce, 0x22, 0xcc, 0x4a, + 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x11, 0x47, 0x63, 0x6f, 0xf7, 0x0c, 0x37, 0x57, 0x10, 0x00, 0x8a, + 0x07, 0x13, 0x07, 0xc7, 0x77, 0xba, 0x97, 0x9c, 0x43, 0x2a, 0x84, 0x93, 0x84, 0xc4, 0xf6, 0x82, + 0x87, 0x81, 0x45, 0xef, 0x30, 0x40, 0x3f, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x98, 0xa7, 0xf6, 0xb7, + 0x37, 0x20, 0x00, 0x23, 0x86, 0x87, 0x88, 0xef, 0x20, 0x50, 0x73, 0x9c, 0x40, 0x85, 0x07, 0x81, + 0xa8, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xaa, 0x07, 0xf6, 0x93, 0x07, 0xc0, 0x0f, 0x63, 0xf1, 0xa7, + 0x02, 0x62, 0x44, 0x9d, 0x47, 0xf2, 0x40, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x9c, 0xc0, 0xd2, + 0x44, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x85, 0x75, 0x05, 0x61, 0x2d, 0xbf, 0x37, + 0x39, 0x20, 0x00, 0x13, 0x09, 0x09, 0xf7, 0x83, 0x55, 0x09, 0x00, 0xef, 0x30, 0xc0, 0x39, 0xb7, + 0x37, 0x20, 0x00, 0xa3, 0x86, 0x87, 0x88, 0x23, 0x10, 0xa9, 0x00, 0x8d, 0x47, 0x5d, 0xf4, 0x9c, + 0xc0, 0x91, 0xa8, 0x37, 0x39, 0x20, 0x00, 0x03, 0x27, 0x49, 0xf7, 0x93, 0x07, 0xb0, 0x0f, 0x13, + 0x09, 0x49, 0xf7, 0x63, 0xf4, 0xe7, 0x00, 0xef, 0xe0, 0xcf, 0xe7, 0x83, 0x27, 0x09, 0x00, 0x37, + 0x3a, 0x20, 0x00, 0x13, 0x0a, 0x0a, 0xf7, 0xb7, 0x39, 0x20, 0x00, 0x93, 0x89, 0xc9, 0x88, 0x83, + 0x55, 0x0a, 0x00, 0xce, 0x97, 0x23, 0x81, 0x87, 0x00, 0xfa, 0x48, 0x91, 0x30, 0x2d, 0xf7, 0xb3, + 0x47, 0x07, 0x80, 0x40, 0xde, 0xe7, 0x4a, 0xf1, 0xbc, 0x19, 0x65, 0x02, 0x62, 0x8a, 0xc3, 0x18, + 0xdd, 0xd2, 0x79, 0xc9, 0x21, 0x2b, 0xdf, 0x80, 0x93, 0xe3, 0xe8, 0x24, 0x22, 0x85, 0xef, 0x30, + 0xc0, 0x34, 0x83, 0x27, 0x09, 0x00, 0x03, 0xc7, 0x19, 0x00, 0x23, 0x10, 0xaa, 0x00, 0x85, 0x07, + 0x23, 0x20, 0xf9, 0x00, 0xe3, 0xfd, 0xe7, 0xf4, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, + 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x99, 0xa7, 0xf6, + 0x3d, 0xbf, 0x37, 0x39, 0x20, 0x00, 0x13, 0x09, 0x29, 0xf7, 0x13, 0x14, 0x85, 0x00, 0xb7, 0x39, + 0x20, 0x00, 0x03, 0x55, 0x09, 0x00, 0x93, 0x89, 0x09, 0xf7, 0x83, 0xd7, 0x09, 0x00, 0x49, 0x8c, + 0x23, 0x10, 0x89, 0x00, 0xe3, 0x8d, 0x87, 0xf0, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0x84, 0x75, + 0x99, 0x47, 0x89, 0x45, 0x9c, 0xc0, 0x95, 0x3d, 0x93, 0x05, 0x84, 0x75, 0x62, 0x44, 0x03, 0xd7, + 0x09, 0x00, 0x83, 0x56, 0x09, 0x00, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, + 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x06, 0xc6, 0x75, 0x13, 0x05, 0x85, 0x77, + 0x05, 0x61, 0x6f, 0xf0, 0x3f, 0xdd, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0xb7, 0x25, + 0x10, 0x00, 0x37, 0x25, 0x10, 0x00, 0x23, 0xa0, 0x07, 0x10, 0x23, 0xa2, 0x07, 0x10, 0x93, 0x85, + 0xc5, 0xfd, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x05, 0xe5, 0x00, 0x23, 0xa6, 0x07, 0xf6, 0x6f, 0x20, + 0x70, 0x55, 0x11, 0xed, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0xef, 0xe0, 0xcf, 0xd8, 0x32, 0x45, + 0xf2, 0x40, 0x13, 0x06, 0xfa, 0x21, 0xd9, 0xfb, 0xde, 0x39, 0xa5, 0x32, 0x7f, 0x30, 0xad, 0x62, + 0x53, 0xc9, 0x4e, 0x61, 0x3e, 0xe2, 0xd3, 0x58, 0x70, 0xd0, 0x02, 0xd9, 0xd0, 0x95, 0x74, 0xec, + 0xf5, 0x97, 0x14, 0x4f, 0x92, 0xc0, 0x25, 0xe0, 0x0f, 0x81, 0x45, 0x05, 0x61, 0x6f, 0x30, 0x40, + 0x35, 0x13, 0x06, 0xe0, 0x0f, 0x81, 0x45, 0xdd, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0xc7, + 0xf6, 0x13, 0x05, 0xa0, 0x0a, 0x99, 0xc3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, + 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0xc4, 0xf6, 0x1c, 0x40, 0x06, 0xc6, 0x15, 0x47, 0x63, + 0x98, 0xe7, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x81, + 0xe7, 0x13, 0x05, 0x50, 0x05, 0xcd, 0xbf, 0xef, 0x20, 0x10, 0x54, 0x93, 0x07, 0xa0, 0x0a, 0xe3, + 0x19, 0xf5, 0xfe, 0x01, 0x00, 0x18, 0x40, 0x91, 0x47, 0xe3, 0xcd, 0xe7, 0xfc, 0x99, 0x47, 0x1c, + 0xc0, 0xd9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x20, 0x90, 0x53, 0x93, 0x07, 0xa0, 0x0a, 0x63, + 0x04, 0xf5, 0x00, 0xef, 0x20, 0xf0, 0x54, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0xc7, 0xf6, 0x95, + 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, + 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0xc7, 0xf6, 0x99, 0x47, 0x13, 0x05, 0xa0, + 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, + 0xa7, 0xc7, 0xf6, 0x9d, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, + 0x05, 0x82, 0x80, 0x37, 0x35, 0x20, 0x00, 0x13, 0x05, 0xc5, 0x88, 0x82, 0x80, 0x01, 0x11, 0xfa, + 0xa3, 0x00, 0x28, 0x5f, 0xca, 0x25, 0x1f, 0xec, 0x1a, 0x16, 0x2f, 0xc2, 0x42, 0x21, 0xe2, 0xa0, + 0x8f, 0x58, 0x40, 0xca, 0xfd, 0x04, 0x39, 0x89, 0x4a, 0xfb, 0xad, 0xf9, 0x66, 0x02, 0x4b, 0xb9, + 0x98, 0x26, 0x26, 0xca, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0xaa, 0x84, 0x19, 0xe1, + 0xef, 0xe0, 0xcf, 0xc9, 0x83, 0xc7, 0x14, 0x00, 0x13, 0x07, 0xc0, 0x0f, 0x13, 0x05, 0x50, 0x05, + 0x63, 0x65, 0xf7, 0x06, 0x37, 0x39, 0x20, 0x00, 0x13, 0x04, 0xc9, 0x98, 0x23, 0x20, 0x04, 0x10, + 0x03, 0xc7, 0x04, 0x00, 0xa3, 0x00, 0xf4, 0x00, 0x03, 0xc6, 0x14, 0x00, 0x23, 0x00, 0xe4, 0x00, + 0x93, 0x85, 0x24, 0x00, 0x13, 0x05, 0x24, 0x00, 0xef, 0x30, 0x00, 0x20, 0x83, 0xc9, 0x14, 0x00, + 0x13, 0x05, 0xc9, 0x98, 0x13, 0x09, 0xc9, 0x98, 0x93, 0x84, 0x29, 0x00, 0xa6, 0x85, 0xef, 0x30, + 0x80, 0x16, 0xa2, 0x94, 0x23, 0x80, 0xa4, 0x00, 0x4e, 0x94, 0x21, 0x81, 0x93, 0x87, 0x49, 0x00, + 0xa3, 0x01, 0xa4, 0x00, 0xfd, 0x56, 0x13, 0xf7, 0x37, 0x00, 0x19, 0xef, 0x89, 0x83, 0x23, 0x22, + 0xf9, 0x10, 0xef, 0x20, 0x30, 0x49, 0x13, 0x05, 0xa0, 0x0a, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, + 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, 0x33, 0x07, 0xf9, 0x00, 0x23, 0x00, 0xd7, 0x00, + 0x85, 0x07, 0xd1, 0xbf, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0x98, 0x03, 0xa7, 0x07, 0x10, + 0x83, 0xa7, 0x47, 0x10, 0x63, 0x14, 0xf7, 0x00, 0x6f, 0x20, 0xb0, 0x41, 0x13, 0x05, 0x50, 0x05, + 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa6, 0x07, 0xf6, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, + 0x93, 0x07, 0x00, 0x08, 0x73, 0xa0, 0x47, 0x30, 0x93, 0x06, 0xfa, 0xfe, 0xc7, 0x49, 0x54, 0x80, + 0xb7, 0x8b, 0x81, 0x3f, 0x08, 0xfb, 0x59, 0x05, 0x42, 0x07, 0x1c, 0x3c, 0x34, 0x71, 0xae, 0x7f, + 0x67, 0xc4, 0x98, 0x29, 0x50, 0x3b, 0x48, 0x1e, 0xe3, 0x83, 0x5b, 0x70, 0x27, 0x70, 0x3e, 0x09, + 0x46, 0x93, 0x05, 0x60, 0x04, 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, 0xf0, 0x59, 0x8d, 0x45, 0x37, + 0x05, 0x10, 0x01, 0xef, 0x20, 0xf0, 0x5d, 0x37, 0x05, 0x10, 0x01, 0xef, 0x20, 0x70, 0x53, 0x37, + 0x05, 0x20, 0x01, 0xef, 0x20, 0xb0, 0x55, 0xfd, 0x56, 0x01, 0x46, 0x93, 0x05, 0x60, 0x04, 0x37, + 0x05, 0x20, 0x01, 0xef, 0x20, 0x50, 0x57, 0xb2, 0x40, 0xb7, 0x07, 0x20, 0x01, 0x23, 0xac, 0x07, + 0x00, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x89, 0x2c, 0xb2, 0x40, 0x41, 0x01, 0x45, + 0xb7, 0x41, 0x11, 0x22, 0xc4, 0xb7, 0x07, 0x20, 0x01, 0x06, 0xc6, 0x23, 0xac, 0x07, 0x00, 0x2a, + 0x84, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0xd0, 0x4e, 0x93, 0x07, 0x80, 0x3e, 0x13, 0x05, 0x80, + 0x3e, 0x63, 0xe3, 0x87, 0x00, 0x22, 0x85, 0xb7, 0x07, 0x20, 0x01, 0x98, 0x4f, 0x13, 0x84, 0x87, + 0x01, 0xe3, 0x6d, 0xa7, 0xfe, 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0x50, 0x4f, 0xb2, 0x40, 0x23, + 0x20, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x11, 0xe1, 0x82, 0x80, 0x01, 0x00, 0x7d, + 0x15, 0xe5, 0xbf, 0x6f, 0xf0, 0x9f, 0xb3, 0x29, 0xa4, 0x01, 0x11, 0x26, 0xca, 0xaa, 0x84, 0x37, + 0x05, 0x20, 0x01, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x56, 0xc2, 0x06, 0xce, 0x22, 0xcc, 0x2e, + 0x89, 0x93, 0x09, 0xa0, 0x0a, 0xef, 0x20, 0xd0, 0x48, 0x37, 0x0a, 0x20, 0x01, 0x93, 0x0a, 0x80, + 0x3e, 0x82, 0x94, 0x2a, 0x84, 0xfa, 0xa5, 0x11, 0x96, 0x8a, 0x77, 0x48, 0x86, 0x75, 0x28, 0xdb, + 0x6f, 0x4d, 0xf2, 0x67, 0xcd, 0x0c, 0xfe, 0xd2, 0xa4, 0x19, 0x55, 0x6f, 0xbc, 0x12, 0x6c, 0x23, + 0x5f, 0xa1, 0x35, 0xa6, 0x77, 0x0c, 0x48, 0x28, 0x63, 0x0c, 0x35, 0x03, 0x83, 0x27, 0x8a, 0x01, + 0x63, 0x7a, 0xf9, 0x04, 0x37, 0x54, 0x10, 0x00, 0x13, 0x05, 0x04, 0x79, 0x85, 0x45, 0xef, 0xf0, + 0x9f, 0xb6, 0x37, 0x56, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0x05, 0x04, 0x79, 0xa6, 0x86, + 0x13, 0x06, 0x46, 0x79, 0x13, 0x05, 0x85, 0x77, 0xef, 0xf0, 0x9f, 0xad, 0x13, 0x04, 0x50, 0x05, + 0x37, 0x05, 0x20, 0x01, 0xef, 0x20, 0xd0, 0x46, 0xf2, 0x40, 0x22, 0x85, 0x62, 0x44, 0xb7, 0x07, + 0x20, 0x01, 0x23, 0xac, 0x07, 0x00, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, + 0x05, 0x61, 0x82, 0x80, 0xe3, 0xf0, 0x2a, 0xfb, 0xb5, 0x2a, 0x69, 0xbf, 0x37, 0x07, 0x00, 0x02, + 0x1c, 0x47, 0x93, 0xe7, 0x87, 0x00, 0x1c, 0xc7, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, + 0x26, 0xc2, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0xcf, 0xa7, 0xa9, 0x44, 0x03, 0x45, 0x04, 0x00, + 0x11, 0xe5, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xef, 0xf0, 0xdf, 0xa1, + 0x83, 0x47, 0x04, 0x00, 0x63, 0x94, 0x97, 0x00, 0xef, 0xf0, 0x7f, 0xa6, 0x05, 0x04, 0xf9, 0xbf, + 0x41, 0x11, 0x06, 0xc6, 0x25, 0x37, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x05, 0xf5, 0x00, 0xef, 0xe0, + 0x4f, 0xa4, 0x01, 0xa0, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x44, + 0x20, 0x00, 0x13, 0x06, 0xc0, 0x1f, 0x81, 0x45, 0x13, 0x05, 0x04, 0xe0, 0x06, 0xc6, 0x26, 0xc2, + 0xfa, 0xa4, 0xf8, 0x32, 0x4a, 0x9e, 0x77, 0xb7, 0xe1, 0x38, 0xfa, 0x5f, 0xfa, 0x8b, 0x90, 0xe4, + 0xd5, 0x46, 0x8b, 0xf8, 0xa5, 0x00, 0x3d, 0x29, 0x18, 0x6a, 0x41, 0x5d, 0x62, 0xc6, 0xcd, 0xb3, + 0xec, 0x20, 0x29, 0xef, 0x20, 0xb0, 0x7f, 0x13, 0x05, 0x04, 0xe0, 0x93, 0x05, 0xc0, 0x1f, 0xef, + 0x20, 0x30, 0x76, 0x93, 0x04, 0x04, 0xe0, 0xb2, 0x40, 0x22, 0x44, 0x23, 0xae, 0xa4, 0x1e, 0x92, + 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x37, 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, 0xc0, + 0x1f, 0x13, 0x04, 0x05, 0xe0, 0x13, 0x05, 0x05, 0xe0, 0x06, 0xc6, 0xef, 0x20, 0x70, 0x73, 0x03, + 0x27, 0xc4, 0x1f, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, 0xa7, 0x00, 0x93, 0x07, 0x50, 0x05, 0xb2, + 0x40, 0x22, 0x44, 0x3e, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, 0xaa, 0x87, 0x63, + 0x6e, 0xa7, 0x00, 0x13, 0x77, 0x35, 0x00, 0x01, 0x45, 0x11, 0xeb, 0x37, 0x45, 0x20, 0x00, 0x13, + 0x05, 0x05, 0xe0, 0xf1, 0x9b, 0xaa, 0x97, 0x88, 0x43, 0x82, 0x80, 0x01, 0x45, 0x82, 0x80, 0x93, + 0x07, 0xb0, 0x1f, 0x63, 0xec, 0xa7, 0x00, 0x93, 0x77, 0x35, 0x00, 0x81, 0xeb, 0xb7, 0x47, 0x20, + 0x00, 0x71, 0x99, 0x93, 0x87, 0x07, 0xe0, 0x3e, 0x95, 0x0c, 0xc1, 0x82, 0x80, 0x41, 0x11, 0x37, + 0x45, 0x20, 0x00, 0x22, 0xc4, 0x93, 0x05, 0xc0, 0x1f, 0x13, 0x04, 0x05, 0xe0, 0x13, 0x05, 0x05, + 0xe0, 0x06, 0xc6, 0xef, 0x20, 0xf0, 0x6b, 0xb2, 0x40, 0x23, 0x2e, 0xa4, 0x1e, 0x22, 0x44, 0x41, + 0x01, 0x82, 0x80, 0x13, 0x07, 0xb0, 0x1f, 0x63, 0x61, 0xa7, 0x02, 0x93, 0x77, 0x35, 0x00, 0x13, + 0x07, 0x50, 0x05, 0x89, 0xef, 0x41, 0x11, 0x06, 0xc6, 0x5d, 0x37, 0xfa, 0xdd, 0x63, 0x5d, 0xa7, + 0x30, 0xd2, 0xe2, 0xb5, 0xdb, 0x5f, 0x1b, 0xa0, 0xfa, 0x7e, 0x57, 0xb2, 0x87, 0xe9, 0x27, 0xb4, + 0x36, 0x63, 0x7a, 0x0e, 0x18, 0x08, 0xe0, 0x95, 0xf6, 0xf6, 0xf6, 0x19, 0xf8, 0x29, 0xc9, 0x37, + 0xb2, 0x40, 0x13, 0x07, 0xa0, 0x0a, 0x3a, 0x85, 0x41, 0x01, 0x82, 0x80, 0x13, 0x07, 0x50, 0x05, + 0x3a, 0x85, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0x00, 0x90, 0x6c, 0xef, 0x20, 0xe0, 0x5f, + 0xb2, 0x40, 0x13, 0x05, 0xa0, 0x0a, 0x41, 0x01, 0x82, 0x80, 0x73, 0x00, 0x50, 0x10, 0x82, 0x80, + 0x3d, 0xce, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x06, 0xd6, 0x4e, 0xce, 0x52, 0xcc, + 0x2a, 0x84, 0x2e, 0x89, 0xb2, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0x0f, 0x90, 0x93, 0x77, 0x39, 0x00, + 0x99, 0xc3, 0xef, 0xe0, 0x6f, 0x8f, 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x87, 0x34, 0x41, 0x33, 0x05, + 0x34, 0x01, 0x63, 0x6c, 0xfa, 0x02, 0x13, 0xd6, 0x24, 0x00, 0xf1, 0x57, 0x33, 0x06, 0xf6, 0x02, + 0x93, 0xf5, 0xc4, 0xff, 0x33, 0x05, 0xb4, 0x00, 0x2e, 0x99, 0x26, 0x96, 0x19, 0xc6, 0x83, 0x27, + 0x09, 0x00, 0x6c, 0x00, 0x3e, 0xc6, 0xef, 0x20, 0xf0, 0x65, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, + 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0xb3, 0x07, 0x39, 0x01, 0x9c, 0x43, + 0x11, 0x46, 0x6c, 0x00, 0x3e, 0xc6, 0x91, 0x09, 0xef, 0x20, 0xd0, 0x63, 0x7d, 0xb7, 0x82, 0x80, + 0x3d, 0xce, 0x79, 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x06, 0xd6, 0x4e, 0xce, 0x52, 0xcc, + 0x2a, 0x84, 0x2e, 0x89, 0xb2, 0x84, 0x99, 0xe1, 0xef, 0xe0, 0x0f, 0x88, 0x93, 0x77, 0x34, 0x00, + 0x99, 0xc3, 0xef, 0xe0, 0x6f, 0x87, 0xfa, 0x4d, 0xf2, 0x04, 0xc7, 0x00, 0x6b, 0x20, 0x73, 0xff, + 0xea, 0xf6, 0xcf, 0x31, 0xa8, 0xed, 0x98, 0xd9, 0x58, 0xf2, 0x3f, 0x65, 0x63, 0x39, 0xca, 0x40, + 0x62, 0x11, 0x13, 0x1e, 0xdf, 0x75, 0x47, 0xd0, 0x2a, 0x81, 0x49, 0x0d, 0x4a, 0xb3, 0x87, 0x34, + 0x41, 0xb3, 0x05, 0x39, 0x01, 0x63, 0x6c, 0xfa, 0x02, 0x13, 0xd6, 0x24, 0x00, 0xf1, 0x57, 0x33, + 0x06, 0xf6, 0x02, 0x93, 0xf5, 0xc4, 0xff, 0x2e, 0x94, 0xca, 0x95, 0x26, 0x96, 0x01, 0xca, 0x1c, + 0x40, 0x68, 0x00, 0x3e, 0xc6, 0xef, 0x20, 0x30, 0x5e, 0xb2, 0x47, 0x1c, 0xc0, 0xb2, 0x50, 0x22, + 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0x11, 0x46, 0x68, + 0x00, 0xef, 0x20, 0x70, 0x5c, 0x32, 0x47, 0xb3, 0x07, 0x34, 0x01, 0x91, 0x09, 0x98, 0xc3, 0x7d, + 0xb7, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xe0, 0xef, + 0x80, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf6, 0xb7, 0x37, 0x20, + 0x00, 0x23, 0xa0, 0x87, 0xf8, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x8a, 0x07, 0xa8, 0xef, 0xf0, 0x9f, + 0xb3, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xae, 0xa7, 0xf6, 0x19, 0xe1, 0xef, 0xd0, 0x1f, 0xfe, 0x22, + 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x7f, 0xa1, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, + 0x84, 0x19, 0xe1, 0xef, 0xd0, 0x9f, 0xfc, 0x37, 0x35, 0x20, 0x00, 0xb7, 0x37, 0x20, 0x00, 0xa2, + 0x85, 0x13, 0x06, 0xe0, 0x0f, 0x13, 0x05, 0x45, 0xa9, 0x23, 0x8a, 0x07, 0xb8, 0xef, 0x20, 0xb0, + 0x54, 0x22, 0x85, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x7f, 0xaf, 0x41, 0x11, 0x22, + 0xc4, 0xfa, 0xba, 0x55, 0x8f, 0xa6, 0xa2, 0x00, 0x3c, 0xce, 0x66, 0x23, 0xf8, 0xf5, 0x15, 0x4a, + 0x90, 0x3a, 0x77, 0xde, 0xe3, 0xbe, 0xf6, 0x3b, 0x2a, 0xf8, 0x56, 0x7d, 0xf9, 0x8a, 0x72, 0x0a, + 0xd9, 0x6c, 0xa8, 0x2b, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x19, 0xe1, 0xef, 0xd0, 0x3f, 0xf9, + 0xb7, 0x34, 0x20, 0x00, 0x83, 0xc7, 0x44, 0xb9, 0x99, 0xcb, 0x37, 0x35, 0x20, 0x00, 0x13, 0x06, + 0xe0, 0x0f, 0x93, 0x85, 0x44, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0xef, 0x20, 0x10, 0x51, 0xa2, 0x85, + 0x13, 0x85, 0x44, 0xb9, 0x13, 0x06, 0xe0, 0x0f, 0xef, 0x20, 0x30, 0x50, 0x22, 0x85, 0x22, 0x44, + 0xb2, 0x40, 0x92, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0xdf, 0xaa, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, + 0x87, 0xf7, 0x82, 0x80, 0x37, 0x35, 0x20, 0x00, 0x83, 0x47, 0x45, 0xa9, 0x85, 0xc3, 0xb7, 0x37, + 0x20, 0x00, 0x83, 0xc7, 0x47, 0xb9, 0x99, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, + 0x23, 0xac, 0xe7, 0xf6, 0x13, 0x05, 0x45, 0xa9, 0x6f, 0xf0, 0xbf, 0xa7, 0x13, 0x05, 0x50, 0x05, + 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x9f, 0x9a, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x04, + 0xf5, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x6d, 0x71, 0x23, 0x26, + 0x11, 0x10, 0x23, 0x24, 0x81, 0x10, 0x23, 0x22, 0x91, 0x10, 0xef, 0xf0, 0x9f, 0x99, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x02, 0x2a, 0x84, 0xef, 0xf0, 0x1f, 0x9d, 0x63, 0x12, 0x85, 0x06, + 0xb7, 0x37, 0x20, 0x00, 0x37, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x07, 0xf8, 0x03, 0x25, 0xc7, 0xf7, + 0x82, 0x97, 0xef, 0xf0, 0x3f, 0xae, 0xef, 0xf0, 0x1f, 0xac, 0x93, 0x07, 0xfa, 0xa7, 0xd3, 0x56, + 0xdb, 0x3a, 0x0b, 0x96, 0x57, 0xf0, 0x41, 0x1c, 0xe2, 0x6f, 0xfd, 0xb6, 0xc2, 0x82, 0xc0, 0x93, + 0x99, 0x1a, 0x90, 0x8a, 0x09, 0x9f, 0xf0, 0x96, 0xe1, 0x27, 0x01, 0x2a, 0xc4, 0x80, 0x2c, 0xa0, + 0x0a, 0x2a, 0x84, 0x63, 0x18, 0xf5, 0x02, 0xef, 0xf0, 0xbf, 0x94, 0x63, 0x14, 0x85, 0x02, 0x37, + 0x34, 0x20, 0x00, 0x13, 0x04, 0x84, 0xf7, 0x04, 0x40, 0xb7, 0x35, 0x20, 0x00, 0x63, 0x9c, 0xa4, + 0x04, 0x13, 0x85, 0x45, 0xb9, 0xef, 0xf0, 0x1f, 0x9f, 0x63, 0x15, 0x95, 0x00, 0x93, 0x07, 0x50, + 0x05, 0x1c, 0xc0, 0x83, 0x20, 0xc1, 0x10, 0x03, 0x24, 0x81, 0x10, 0x83, 0x24, 0x41, 0x10, 0x51, + 0x61, 0x82, 0x80, 0xef, 0xf0, 0x9f, 0x99, 0x81, 0x44, 0x63, 0x14, 0x85, 0x00, 0x93, 0x04, 0xc0, + 0x07, 0xef, 0xf0, 0x3f, 0x9a, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, 0xc1, 0xdc, 0x0a, + 0x85, 0x23, 0x00, 0x91, 0x00, 0xa3, 0x00, 0x01, 0x00, 0xef, 0xf0, 0x7f, 0xe8, 0x61, 0xb7, 0x93, + 0x04, 0xc0, 0x07, 0xf5, 0xb7, 0x83, 0xc7, 0x45, 0xb9, 0xcd, 0xdf, 0x03, 0x24, 0x81, 0x10, 0x83, + 0x20, 0xc1, 0x10, 0x83, 0x24, 0x41, 0x10, 0x37, 0x35, 0x20, 0x00, 0x13, 0x06, 0xe0, 0x0f, 0x93, + 0x85, 0x45, 0xb9, 0x13, 0x05, 0x45, 0xa9, 0x51, 0x61, 0x6f, 0x20, 0x50, 0x3c, 0xb7, 0x07, 0x01, + 0x04, 0x23, 0xa2, 0x07, 0x00, 0x21, 0x65, 0x6f, 0x20, 0x80, 0x30, 0x41, 0x11, 0x21, 0x65, 0x06, + 0xc6, 0xef, 0x20, 0x20, 0x2f, 0xb2, 0x40, 0xb7, 0x07, 0x01, 0x04, 0x05, 0x47, 0xd8, 0xc3, 0x41, + 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x07, 0x70, 0x02, 0x2a, + 0x84, 0xae, 0x84, 0x63, 0xf4, 0xa7, 0x00, 0xfa, 0x1e, 0xaf, 0x4b, 0x61, 0xd7, 0xa5, 0xaa, 0x9b, + 0xb9, 0xac, 0x40, 0x4c, 0x11, 0x95, 0xbe, 0x8d, 0xce, 0x06, 0xc5, 0x0d, 0x54, 0x0d, 0xeb, 0x31, + 0xf0, 0x29, 0x42, 0x81, 0xfe, 0x09, 0x0d, 0x4b, 0x58, 0x2d, 0xef, 0xd0, 0xbf, 0xde, 0x37, 0x05, + 0x01, 0x04, 0x0a, 0x04, 0x13, 0x05, 0x05, 0x10, 0x2a, 0x94, 0x04, 0xc0, 0xb2, 0x40, 0x22, 0x44, + 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x13, 0x87, 0x07, 0x10, 0x93, 0x87, + 0x07, 0x1a, 0x23, 0x20, 0x07, 0x00, 0x11, 0x07, 0xe3, 0x1d, 0xf7, 0xfe, 0x82, 0x80, 0xb7, 0x07, + 0x01, 0x04, 0xc8, 0xcb, 0x82, 0x80, 0x42, 0x05, 0xb7, 0x07, 0x01, 0x04, 0xc8, 0xcb, 0x82, 0x80, + 0xb7, 0x07, 0x01, 0x04, 0x88, 0x4b, 0x13, 0x75, 0xf5, 0x0f, 0x82, 0x80, 0x89, 0x67, 0x37, 0x07, + 0x01, 0x04, 0x8d, 0x07, 0x1c, 0xc7, 0x23, 0x2a, 0x07, 0x00, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, + 0x22, 0xc4, 0x2a, 0x84, 0xad, 0x37, 0xb7, 0x07, 0x01, 0x04, 0x80, 0xcf, 0xc5, 0x37, 0x65, 0x37, + 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xf4, 0xb7, 0x06, 0x01, 0x04, 0x9c, 0x46, + 0x05, 0x45, 0x13, 0xf7, 0x17, 0x00, 0x1d, 0xc7, 0x13, 0xf7, 0x07, 0x40, 0x0d, 0x45, 0x1d, 0xe3, + 0x98, 0x4a, 0x13, 0x77, 0xf7, 0x0f, 0x19, 0xcf, 0x13, 0xf7, 0x27, 0x20, 0x09, 0x45, 0x19, 0xeb, + 0x13, 0xd7, 0xb7, 0x00, 0x05, 0x8b, 0x11, 0x45, 0x11, 0xe7, 0x13, 0xd5, 0x87, 0x00, 0x13, 0x45, + 0x15, 0x00, 0x05, 0x89, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x04, 0x88, 0xcf, 0x82, 0x80, 0x01, 0x11, + 0x22, 0xcc, 0x06, 0xce, 0x33, 0x07, 0xb6, 0x00, 0x93, 0x07, 0x00, 0x09, 0x2e, 0x84, 0x63, 0xf8, + 0xe7, 0x00, 0xfa, 0x54, 0x9e, 0x6f, 0x39, 0x78, 0xc7, 0x3b, 0x59, 0xb2, 0xc0, 0xb2, 0xb5, 0x84, + 0xfd, 0x3f, 0x5f, 0x4f, 0x3e, 0x32, 0x93, 0xdd, 0xd6, 0x0b, 0xe8, 0xb4, 0xff, 0xd8, 0x1f, 0xca, + 0xba, 0xb5, 0xe5, 0x30, 0x2e, 0x32, 0xc6, 0x2a, 0xc4, 0xef, 0xd0, 0xff, 0xd0, 0x32, 0x46, 0x22, + 0x45, 0xb7, 0x15, 0x01, 0x04, 0xa2, 0x95, 0xef, 0xf0, 0x9f, 0xbe, 0xf2, 0x40, 0x62, 0x44, 0x13, + 0x05, 0xa0, 0x0a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, 0x26, 0xca, 0x06, 0xce, 0x33, + 0x07, 0xb6, 0x00, 0x93, 0x07, 0x00, 0x08, 0xaa, 0x84, 0x2e, 0x84, 0x63, 0xf6, 0xe7, 0x00, 0x32, + 0xc6, 0xef, 0xd0, 0x7f, 0xcd, 0x32, 0x46, 0x37, 0x25, 0x01, 0x04, 0x13, 0x05, 0x05, 0x80, 0x22, + 0x95, 0x62, 0x44, 0xf2, 0x40, 0xa6, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x6f, 0xf0, 0x5f, 0xc2, 0x39, + 0x71, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x56, 0x10, 0x00, 0x37, + 0x55, 0x10, 0x00, 0x13, 0x06, 0x06, 0x7a, 0x93, 0x85, 0x05, 0x7b, 0x13, 0x05, 0x45, 0x7b, 0x06, + 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, + 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xf0, 0xcf, 0xc8, 0xef, 0xe0, 0x8f, + 0xd6, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, + 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, + 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x09, 0x65, 0x6f, 0x20, 0x00, 0x13, 0x09, 0x65, 0x6f, + 0x20, 0x60, 0x13, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, 0xfa, 0x6d, 0x0d, + 0x1b, 0x23, 0xf5, 0xbc, 0x94, 0xcb, 0xa7, 0x29, 0x42, 0x08, 0x5d, 0xe1, 0xc1, 0xd6, 0x0e, 0xae, + 0x35, 0x13, 0x3c, 0x44, 0x81, 0xbf, 0xec, 0xba, 0xaa, 0xaa, 0x19, 0x1a, 0xe2, 0x9d, 0x08, 0x2f, + 0xef, 0xd0, 0xbf, 0xc3, 0xdd, 0x37, 0xb7, 0x07, 0x00, 0x07, 0xd8, 0x43, 0x83, 0x47, 0x64, 0x00, + 0xbd, 0x46, 0x63, 0x85, 0xd7, 0x00, 0x61, 0x9b, 0x9d, 0x8b, 0x5d, 0x8f, 0x93, 0x77, 0x77, 0xff, + 0x03, 0x47, 0x74, 0x00, 0x83, 0x46, 0x44, 0x00, 0xb2, 0x40, 0x0e, 0x07, 0x21, 0x8b, 0x5d, 0x8f, + 0xfd, 0x77, 0xbd, 0x07, 0x7d, 0x8f, 0x83, 0x47, 0x84, 0x00, 0x92, 0x07, 0x5d, 0x8f, 0xb7, 0x17, + 0x80, 0xff, 0xfd, 0x17, 0x7d, 0x8f, 0x83, 0x47, 0x54, 0x00, 0xa2, 0x07, 0xd5, 0x8f, 0xb2, 0x07, + 0xb7, 0xf6, 0x7f, 0x00, 0xf5, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x80, 0xf8, 0x7d, 0x17, 0xf9, 0x8f, + 0x03, 0x47, 0xa4, 0x00, 0xb7, 0x06, 0x80, 0x07, 0x5e, 0x07, 0x75, 0x8f, 0xd9, 0x8f, 0x37, 0x07, + 0x00, 0x88, 0x7d, 0x17, 0xf9, 0x8f, 0x03, 0x47, 0x94, 0x00, 0xb7, 0x06, 0x00, 0x78, 0x22, 0x44, + 0x6e, 0x07, 0x75, 0x8f, 0xd9, 0x8f, 0x37, 0x07, 0x00, 0x07, 0x5c, 0xc3, 0x41, 0x01, 0x82, 0x80, + 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x87, 0xf8, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, + 0xc7, 0x20, 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, + 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x13, 0x05, 0xa0, 0x0a, 0x89, 0x8b, 0x99, 0xe3, + 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, + 0x13, 0x05, 0x85, 0xbb, 0x6f, 0xf0, 0x5f, 0x91, 0xfa, 0xd8, 0x14, 0xfd, 0xf8, 0x0c, 0xee, 0xbc, + 0x7c, 0xa1, 0x4e, 0xe7, 0x3e, 0x25, 0x21, 0xc1, 0xa4, 0x8e, 0x2a, 0x95, 0xb0, 0xa7, 0xb3, 0x44, + 0xce, 0xaf, 0x2b, 0x92, 0x0b, 0xb6, 0xa7, 0x93, 0x7e, 0xe0, 0x2f, 0x41, 0x11, 0xb7, 0x07, 0x08, + 0x05, 0x22, 0xc4, 0x03, 0xa4, 0xc7, 0x20, 0x37, 0x07, 0x00, 0x04, 0x06, 0xc6, 0x26, 0xc2, 0xb3, + 0x76, 0xe4, 0x00, 0x91, 0xca, 0x37, 0x55, 0x10, 0x00, 0x23, 0xa6, 0xe7, 0x20, 0xa5, 0x45, 0x13, + 0x05, 0x85, 0x7b, 0xef, 0xf0, 0xef, 0xbb, 0xb7, 0x07, 0x80, 0x6b, 0xe1, 0x8f, 0x95, 0xcb, 0x37, + 0x07, 0x08, 0x05, 0x23, 0x26, 0xf7, 0x20, 0xb7, 0x07, 0x00, 0x68, 0x7d, 0x8c, 0x93, 0x04, 0x50, + 0x05, 0x11, 0xc8, 0x37, 0x55, 0x10, 0x00, 0x9d, 0x45, 0x13, 0x05, 0x85, 0x7b, 0xef, 0xf0, 0x4f, + 0xb9, 0xef, 0xd0, 0xdf, 0xb0, 0xb2, 0x40, 0x22, 0x44, 0x26, 0x85, 0x92, 0x44, 0x41, 0x01, 0x82, + 0x80, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0xf8, 0x84, 0x43, 0x13, 0x07, 0xa0, 0x0a, 0x63, + 0x96, 0xe4, 0x00, 0x13, 0x07, 0x50, 0x05, 0x98, 0xc3, 0xe1, 0xbf, 0x93, 0x04, 0xa0, 0x0a, 0xd9, + 0xbf, 0x81, 0x47, 0xb7, 0x05, 0x08, 0x05, 0x13, 0x07, 0x00, 0x20, 0xb3, 0x86, 0xb7, 0x00, 0x90, + 0x42, 0xb3, 0x06, 0xf5, 0x00, 0x91, 0x07, 0x90, 0xc2, 0xe3, 0x99, 0xe7, 0xfe, 0x6f, 0xf0, 0xff, + 0xf5, 0x41, 0x11, 0x06, 0xc6, 0x22, 0xc4, 0x2a, 0x84, 0xef, 0xf0, 0x1f, 0xf4, 0xb7, 0x37, 0x20, + 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa4, 0xe7, 0xf8, 0x8d, 0x47, 0x33, 0x95, 0x87, 0x00, 0xb7, + 0xb7, 0xaa, 0x02, 0x93, 0x87, 0xa7, 0xaa, 0x3d, 0x8d, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xa4, 0xa7, + 0x20, 0x89, 0x65, 0xfa, 0x5e, 0x6c, 0x07, 0xc8, 0xd2, 0x35, 0x1f, 0x8d, 0x20, 0x56, 0x9f, 0xda, + 0x3e, 0xb1, 0xdd, 0xf7, 0x9b, 0x1b, 0xec, 0xc5, 0x37, 0xc2, 0xa4, 0x0b, 0x96, 0xe2, 0x28, 0xf5, + 0x1e, 0xf0, 0x78, 0x16, 0xb8, 0x30, 0x37, 0x35, 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, + 0x85, 0xb9, 0xef, 0xf0, 0xdf, 0x82, 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0xf1, + 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x9f, 0xef, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xf8, + 0x37, 0x07, 0x08, 0x05, 0x13, 0x05, 0x00, 0x20, 0xf9, 0x9b, 0x23, 0x22, 0xf7, 0x20, 0xef, 0x10, + 0x10, 0x74, 0xb2, 0x40, 0x39, 0x45, 0x41, 0x01, 0x6f, 0x10, 0x30, 0x75, 0x37, 0x37, 0x20, 0x00, + 0x13, 0x07, 0x47, 0xf8, 0x1c, 0x43, 0x93, 0xf7, 0xf7, 0xfd, 0x1c, 0xc3, 0x37, 0x07, 0x08, 0x05, + 0x23, 0x22, 0xf7, 0x20, 0x82, 0x80, 0x37, 0x37, 0x20, 0x00, 0x13, 0x07, 0x47, 0xf8, 0x1c, 0x43, + 0x93, 0xe7, 0x07, 0x02, 0x1c, 0xc3, 0x37, 0x07, 0x08, 0x05, 0x23, 0x22, 0xf7, 0x20, 0x82, 0x80, + 0x33, 0x87, 0xc5, 0x00, 0xb7, 0x07, 0x08, 0x00, 0x63, 0x7c, 0xf7, 0x06, 0x01, 0x11, 0x22, 0xcc, + 0x26, 0xca, 0x4e, 0xc6, 0x06, 0xce, 0x4a, 0xc8, 0x93, 0xf4, 0x35, 0x00, 0xaa, 0x89, 0x2e, 0x84, + 0x13, 0x05, 0x50, 0x05, 0x9d, 0xec, 0x32, 0x89, 0xef, 0xf0, 0x5f, 0xe7, 0xb7, 0x37, 0x20, 0x00, + 0x03, 0xa7, 0x47, 0xf8, 0xb7, 0x06, 0x08, 0x05, 0xb7, 0x05, 0x00, 0x05, 0x13, 0x67, 0x27, 0x00, + 0x23, 0xa2, 0xe6, 0x20, 0x93, 0x87, 0x47, 0xf8, 0x0d, 0x47, 0x2e, 0x94, 0xb3, 0x06, 0x99, 0x40, + 0x63, 0x60, 0xd7, 0x02, 0x98, 0x43, 0xb7, 0x07, 0x08, 0x05, 0x13, 0x05, 0xa0, 0x0a, 0xfa, 0xa0, + 0x2f, 0x24, 0xd9, 0xb1, 0xb6, 0xcf, 0x39, 0xac, 0xb6, 0xdf, 0xcc, 0x67, 0xfc, 0x9c, 0x50, 0x2c, + 0x1f, 0xc4, 0x64, 0xa1, 0xb3, 0xe3, 0x75, 0x93, 0xc6, 0x0b, 0x39, 0x3b, 0x8b, 0xc4, 0xce, 0x90, + 0x31, 0x23, 0xa2, 0xe7, 0x20, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, + 0x61, 0x82, 0x80, 0xb3, 0x06, 0x94, 0x00, 0x90, 0x42, 0xb3, 0x86, 0x99, 0x00, 0x91, 0x04, 0x90, + 0xc2, 0xf9, 0xb7, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, 0xaa, 0x85, 0x11, 0x46, 0x68, + 0x00, 0x06, 0xce, 0xef, 0xf0, 0x1f, 0xf7, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x16, 0xf5, 0x00, 0x32, + 0x45, 0xf2, 0x40, 0x05, 0x61, 0x82, 0x80, 0x01, 0x45, 0xe5, 0xbf, 0xb7, 0x07, 0x08, 0x00, 0x63, + 0xef, 0xa7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x26, 0xc2, 0x93, 0x77, 0x35, 0x00, 0x2a, + 0x84, 0x8d, 0xe3, 0xae, 0x84, 0xef, 0xf0, 0xbf, 0xdd, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, + 0x20, 0x22, 0x44, 0xb2, 0x40, 0x23, 0xaa, 0x97, 0x20, 0x92, 0x44, 0x01, 0x45, 0x41, 0x01, 0x6f, + 0xf0, 0x9f, 0xe7, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x82, 0x80, 0x41, + 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xaa, 0x84, 0x2e, 0x84, 0xef, 0xf0, 0x1f, 0xfb, 0x26, + 0x85, 0xef, 0xf0, 0x9f, 0xf8, 0x63, 0x09, 0x85, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, + 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xcd, 0xbf, 0x01, 0x11, 0x22, + 0xcc, 0x2e, 0xc6, 0x06, 0xce, 0x2a, 0x84, 0xef, 0xf0, 0x3f, 0xf6, 0xb2, 0x45, 0x63, 0x03, 0xb5, + 0x02, 0xfd, 0x57, 0x63, 0x1a, 0xf5, 0x00, 0x63, 0x8e, 0xfa, 0x4a, 0x1f, 0x43, 0x98, 0xa0, 0x41, + 0x34, 0xfd, 0xef, 0x7f, 0xd9, 0x87, 0xb7, 0x1f, 0xe3, 0x9d, 0x3d, 0x4f, 0x9d, 0x75, 0xd7, 0x86, + 0x38, 0x45, 0x27, 0x1c, 0x81, 0x1c, 0x0a, 0xde, 0xbc, 0xc2, 0x68, 0x32, 0xa5, 0x00, 0x22, 0x85, + 0x62, 0x44, 0xf2, 0x40, 0x05, 0x61, 0x6f, 0xf0, 0xdf, 0xfa, 0x13, 0x05, 0x50, 0x05, 0xf2, 0x40, + 0x62, 0x44, 0x05, 0x61, 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xd5, 0xbf, 0xb7, 0x07, 0x08, 0x00, + 0x63, 0xe0, 0xb7, 0x04, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0xf7, 0xf5, 0x1f, + 0xaa, 0x84, 0x2e, 0x84, 0x13, 0x05, 0x50, 0x05, 0x99, 0xef, 0xef, 0xf0, 0x9f, 0xd2, 0xb7, 0x07, + 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, 0x39, 0x45, 0xef, 0xf0, 0x3f, 0xdd, 0x26, 0x85, 0xef, 0xf0, + 0xdf, 0xda, 0x13, 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, + 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, + 0x4e, 0xc6, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xfb, 0xb7, 0x00, 0x81, 0x44, 0xf2, 0x40, 0x62, 0x44, + 0x42, 0x49, 0xb2, 0x49, 0x26, 0x85, 0xd2, 0x44, 0x05, 0x61, 0x82, 0x80, 0x93, 0xf4, 0xf5, 0x1f, + 0x2e, 0x84, 0xe5, 0xf4, 0x2a, 0x89, 0xef, 0xf0, 0xdf, 0xcc, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, + 0x87, 0x20, 0x41, 0x45, 0xef, 0xf0, 0x7f, 0xd7, 0x93, 0x07, 0xa0, 0x0a, 0xe3, 0x17, 0xf5, 0xfc, + 0x37, 0x34, 0x20, 0x00, 0x13, 0x05, 0x44, 0xc9, 0xef, 0xf0, 0x3f, 0xd4, 0xb7, 0x07, 0x08, 0x05, + 0x13, 0x87, 0x07, 0x20, 0x23, 0xa0, 0x07, 0x00, 0x91, 0x07, 0xe3, 0x9d, 0xe7, 0xfe, 0x93, 0x09, + 0x44, 0xc9, 0x03, 0xd6, 0xfa, 0xa5, 0x13, 0x68, 0xc5, 0x11, 0x04, 0xb3, 0xdd, 0x87, 0x59, 0xc1, + 0x5d, 0x32, 0xa2, 0x6e, 0x90, 0x23, 0x54, 0x5e, 0x34, 0xdc, 0xcb, 0xfa, 0x8a, 0xb8, 0xb3, 0x93, + 0x57, 0x9b, 0xee, 0xd9, 0x84, 0x40, 0x33, 0xc9, 0x1f, 0x93, 0x07, 0xc0, 0x1d, 0x63, 0xfa, 0xc7, + 0x00, 0x37, 0x55, 0x10, 0x00, 0x99, 0x45, 0x13, 0x05, 0x85, 0x7b, 0xef, 0xf0, 0x2f, 0x87, 0x41, + 0xbf, 0x93, 0x05, 0x44, 0xc9, 0x4a, 0x85, 0xef, 0x20, 0xe0, 0x57, 0x83, 0xd4, 0xc9, 0x1f, 0x41, + 0xb7, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe7, 0xa7, 0x04, 0x41, 0x11, 0x22, 0xc4, 0x93, 0x77, 0xf5, + 0x1f, 0x06, 0xc6, 0x26, 0xc2, 0x2a, 0x84, 0x13, 0x05, 0x50, 0x05, 0x9d, 0xe7, 0xef, 0xf0, 0x9f, + 0xc4, 0x85, 0x67, 0xb7, 0x04, 0x08, 0x05, 0x93, 0x87, 0x97, 0x82, 0x23, 0xa2, 0xf4, 0x20, 0x23, + 0xac, 0x84, 0x20, 0x39, 0x45, 0xef, 0xf0, 0x9f, 0xce, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, + 0xf8, 0x13, 0x05, 0xa0, 0x0a, 0x23, 0xa2, 0xf4, 0x20, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, + 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x0d, 0x65, 0x01, 0x11, 0x13, 0x05, 0x05, + 0x20, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xef, 0x10, 0x10, 0x45, 0x39, + 0x45, 0xef, 0x10, 0x70, 0x46, 0x13, 0x05, 0x80, 0x07, 0x37, 0x39, 0x20, 0x00, 0xef, 0xf0, 0xef, + 0xbd, 0x93, 0x09, 0x49, 0xf8, 0x83, 0xa7, 0x09, 0x00, 0x37, 0x04, 0x08, 0x05, 0x93, 0x04, 0x04, + 0x20, 0xdc, 0xc0, 0xb7, 0x07, 0x46, 0x00, 0x85, 0x07, 0xdc, 0xcc, 0x85, 0x67, 0x93, 0x87, 0x57, + 0x86, 0x89, 0x65, 0x37, 0x35, 0x10, 0x00, 0xdc, 0xc0, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0xfa, + 0x5b, 0xf3, 0xcc, 0x47, 0x28, 0xc4, 0x2e, 0x9e, 0xf1, 0x58, 0xad, 0xca, 0x83, 0x26, 0x1d, 0x52, + 0xdf, 0xdb, 0x9b, 0x49, 0xfe, 0x70, 0xd5, 0x76, 0x12, 0xd6, 0xaf, 0xa4, 0x8a, 0x4b, 0x4f, 0x8d, + 0x18, 0x34, 0x25, 0xba, 0xef, 0xf0, 0x6f, 0xcd, 0xb7, 0x07, 0x40, 0x08, 0x9c, 0xc8, 0xdc, 0x40, + 0x01, 0x45, 0x13, 0x09, 0x49, 0xf8, 0x93, 0xe7, 0x07, 0x18, 0x23, 0xa0, 0xf9, 0x00, 0xef, 0xf0, + 0x7f, 0xf3, 0x93, 0x07, 0x04, 0x10, 0x98, 0x43, 0xb7, 0x67, 0xa5, 0xf0, 0x93, 0x87, 0xf7, 0xa0, + 0x63, 0x05, 0xf7, 0x02, 0x37, 0x55, 0x10, 0x00, 0x95, 0x45, 0x13, 0x05, 0x85, 0x7b, 0xef, 0xe0, + 0x3f, 0xf7, 0x41, 0x67, 0x7d, 0x17, 0x93, 0x07, 0x04, 0x18, 0xb8, 0xd3, 0xf8, 0xd3, 0xb8, 0xd7, + 0xf8, 0xd7, 0xb8, 0xdb, 0xf8, 0xdb, 0xb8, 0xdf, 0xf8, 0xdf, 0x51, 0x45, 0xef, 0xf0, 0x5f, 0xc1, + 0xb7, 0x07, 0x08, 0x05, 0x83, 0xa7, 0xc7, 0x20, 0x91, 0x8b, 0x91, 0xeb, 0x37, 0x55, 0x10, 0x00, + 0x91, 0x45, 0x13, 0x05, 0x85, 0x7b, 0xef, 0xe0, 0xbf, 0xf3, 0xef, 0xd0, 0x2f, 0xeb, 0xb7, 0x07, + 0x08, 0x05, 0x37, 0x07, 0x40, 0x00, 0x23, 0xa6, 0xe7, 0x20, 0x03, 0x27, 0x09, 0x00, 0xf2, 0x40, + 0x62, 0x44, 0x23, 0xa2, 0xe7, 0x20, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, 0x61, 0x82, 0x80, + 0x85, 0x67, 0x37, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0x86, 0x23, 0x22, 0xf7, 0xf8, 0x37, 0x37, + 0x20, 0x00, 0x93, 0x07, 0x50, 0x05, 0x23, 0x24, 0xf7, 0xf8, 0x37, 0x37, 0x20, 0x00, 0x23, 0x26, + 0xf7, 0xf8, 0x6f, 0xf0, 0xbf, 0xee, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xe0, 0xa7, 0x06, 0x41, 0x11, + 0x22, 0xc4, 0x93, 0x77, 0xf5, 0x1f, 0x06, 0xc6, 0x26, 0xc2, 0xfa, 0x99, 0xd2, 0x61, 0x95, 0x3f, + 0xe8, 0x1c, 0x2a, 0x9a, 0x01, 0x8f, 0xeb, 0x20, 0x1d, 0x32, 0x6a, 0xc6, 0x16, 0xc7, 0x8a, 0xf3, + 0x3e, 0x84, 0xc4, 0x22, 0xff, 0x92, 0x5a, 0xff, 0xb5, 0xe8, 0x6e, 0xf0, 0x34, 0x2a, 0x84, 0x13, + 0x05, 0x50, 0x05, 0xa1, 0xe3, 0xae, 0x84, 0xef, 0xf0, 0x5f, 0xad, 0xb7, 0x07, 0x08, 0x05, 0x23, + 0xac, 0x87, 0x20, 0x01, 0x47, 0x93, 0x06, 0x00, 0x20, 0xb3, 0x85, 0xe4, 0x00, 0x8c, 0x41, 0x33, + 0x06, 0xf7, 0x00, 0x11, 0x07, 0x0c, 0xc2, 0xe3, 0x19, 0xd7, 0xfe, 0x7d, 0x57, 0x93, 0x87, 0x07, + 0x20, 0xf8, 0xc3, 0xb8, 0xc7, 0xf8, 0xc7, 0xb8, 0xcb, 0x29, 0x45, 0xef, 0xf0, 0x9f, 0xb5, 0x13, + 0x05, 0xa0, 0x0a, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, + 0x05, 0x82, 0x80, 0xaa, 0x85, 0x37, 0x05, 0x08, 0x05, 0x41, 0x46, 0x13, 0x05, 0x05, 0x26, 0x6f, + 0xf0, 0x8f, 0xd5, 0xb7, 0x07, 0x08, 0x00, 0x63, 0xef, 0xa7, 0x0a, 0x01, 0x11, 0x26, 0xca, 0x93, + 0x77, 0xf5, 0x1f, 0x06, 0xce, 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x56, 0xc2, 0xaa, + 0x84, 0x13, 0x05, 0x50, 0x05, 0xd9, 0xe7, 0x93, 0x07, 0xc0, 0x1d, 0x32, 0x89, 0x63, 0xe3, 0xc7, + 0x08, 0xb6, 0x89, 0x37, 0x34, 0x20, 0x00, 0x2e, 0x8a, 0xef, 0xf0, 0x3f, 0xa4, 0x13, 0x06, 0x00, + 0x20, 0x81, 0x45, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x00, 0x38, 0x4a, 0x86, 0xd2, 0x85, 0x13, + 0x05, 0x44, 0xc9, 0xef, 0x20, 0x80, 0x33, 0x4e, 0x85, 0xef, 0xf0, 0xbf, 0xf9, 0x93, 0x0a, 0x44, + 0xc9, 0xb7, 0x07, 0x08, 0x05, 0x23, 0x9e, 0x2a, 0x1f, 0x13, 0x07, 0x44, 0xc9, 0x93, 0x86, 0x07, + 0x20, 0x10, 0x43, 0x11, 0x07, 0xfa, 0x0a, 0x4b, 0x11, 0x5a, 0x0d, 0x90, 0xd2, 0x18, 0x5a, 0xc5, + 0xa2, 0x40, 0xcf, 0x75, 0x28, 0xdf, 0x8a, 0x4f, 0xe0, 0x3a, 0xe0, 0x4a, 0x3e, 0xa0, 0x27, 0x53, + 0xa2, 0x0c, 0xb1, 0x4a, 0x34, 0x0b, 0xc8, 0x35, 0x90, 0xc3, 0x91, 0x07, 0xe3, 0x9c, 0xd7, 0xfe, + 0x13, 0x06, 0x00, 0x20, 0x81, 0x45, 0x13, 0x05, 0x44, 0xc9, 0xef, 0x20, 0x00, 0x34, 0xb7, 0x07, + 0x08, 0x05, 0x23, 0xac, 0x97, 0x20, 0x31, 0x45, 0xef, 0xf0, 0xff, 0xa9, 0x93, 0x07, 0xa0, 0x0a, + 0x63, 0x0b, 0xf5, 0x00, 0x37, 0x55, 0x10, 0x00, 0x13, 0x05, 0x85, 0x7b, 0x8d, 0x45, 0xef, 0xe0, + 0x9f, 0xdc, 0x13, 0x05, 0x50, 0x05, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, + 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x07, + 0x08, 0x00, 0x63, 0xeb, 0xa7, 0x02, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x93, 0x77, 0xf5, 0x1f, + 0x2a, 0x84, 0x89, 0xef, 0xef, 0xf0, 0xbf, 0x99, 0xb7, 0x07, 0x08, 0x05, 0x23, 0xac, 0x87, 0x20, + 0x22, 0x44, 0xb2, 0x40, 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0xff, 0xa3, 0xb2, 0x40, 0x22, 0x44, + 0x13, 0x05, 0x50, 0x05, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, + 0x22, 0xc4, 0x06, 0xc6, 0x37, 0x04, 0x08, 0x05, 0x23, 0x2c, 0xa4, 0x20, 0xef, 0xf0, 0x3f, 0x96, + 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xa4, 0xe7, 0xf8, 0xb7, 0xb7, 0xaa, 0x02, + 0x93, 0x87, 0x67, 0xaa, 0xb2, 0x40, 0x23, 0x24, 0xf4, 0x20, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, + 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0xbf, 0x93, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, + 0xfa, 0x05, 0xfb, 0xae, 0x90, 0x96, 0x20, 0x2e, 0xf2, 0xc0, 0xb9, 0x69, 0xb8, 0x49, 0x47, 0x8f, + 0x1a, 0xbd, 0x87, 0xfd, 0x54, 0x8e, 0xf1, 0xcd, 0x12, 0x84, 0x44, 0x99, 0xe1, 0xba, 0xb4, 0x33, + 0x80, 0xa0, 0x36, 0x23, 0xa4, 0xe7, 0xf8, 0xb2, 0x40, 0xb7, 0xb7, 0xa6, 0x02, 0x37, 0x07, 0x08, + 0x05, 0x93, 0x87, 0xa7, 0xaa, 0x23, 0x24, 0xf7, 0x20, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x3e, + 0xcc, 0xb7, 0x07, 0x08, 0x05, 0x3a, 0xce, 0x03, 0xa7, 0xc7, 0x20, 0x36, 0xd0, 0xb7, 0x06, 0x40, + 0x00, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x42, + 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0x75, 0x8f, 0x05, 0xcf, 0x23, + 0xa6, 0xd7, 0x20, 0x13, 0x07, 0xa0, 0x0a, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa4, 0xe7, 0xf8, 0xf2, + 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, + 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, + 0x61, 0x73, 0x00, 0x20, 0x30, 0x03, 0xa7, 0xc7, 0x20, 0xb7, 0x06, 0x00, 0x08, 0x37, 0x55, 0x10, + 0x00, 0x75, 0x8f, 0x0d, 0xc3, 0x23, 0xa6, 0xd7, 0x20, 0x85, 0x45, 0x13, 0x05, 0x85, 0x7b, 0xef, + 0xe0, 0xbf, 0xc8, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xa6, 0xe7, 0xf8, 0xef, + 0xd0, 0x5f, 0xce, 0x75, 0xb7, 0x89, 0x45, 0x13, 0x05, 0x85, 0x7b, 0xef, 0xe0, 0xff, 0xc6, 0xb7, + 0x07, 0x02, 0x00, 0x73, 0xb0, 0x47, 0x30, 0xe5, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0x50, + 0x05, 0x23, 0xa8, 0xe7, 0xf8, 0x82, 0x80, 0x99, 0x47, 0x63, 0x05, 0xfa, 0x21, 0x42, 0x79, 0x19, + 0xd8, 0xe4, 0x27, 0x7b, 0xc1, 0x9b, 0x06, 0x7f, 0x51, 0xd5, 0xe6, 0xa4, 0x06, 0x28, 0x05, 0x83, + 0x03, 0x08, 0x7d, 0x48, 0x9d, 0x59, 0x6f, 0xa8, 0x38, 0xda, 0xbc, 0xf6, 0x78, 0x37, 0xf5, 0x02, + 0x9d, 0x47, 0x63, 0x0b, 0xf5, 0x00, 0x95, 0x47, 0x63, 0x15, 0xf5, 0x02, 0x37, 0x07, 0x00, 0x02, + 0x7c, 0x43, 0x93, 0xf7, 0xf7, 0xf7, 0x29, 0xa8, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, + 0x23, 0xa8, 0xe7, 0xf8, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xe7, 0x07, 0x08, + 0x7c, 0xc3, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf9, 0x93, 0x07, 0xa0, 0x0a, + 0x63, 0x18, 0xf7, 0x00, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xe7, 0x07, 0x08, 0x7c, 0xc3, + 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xf9, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x18, + 0xf7, 0x00, 0x37, 0x07, 0x00, 0x02, 0x7c, 0x43, 0x93, 0xf7, 0xf7, 0xf7, 0x7c, 0xc3, 0x82, 0x80, + 0x39, 0x71, 0x2a, 0xd6, 0x37, 0x55, 0x10, 0x00, 0x2e, 0xd4, 0x13, 0x05, 0xc5, 0x7b, 0x85, 0x45, + 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, + 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0x1f, 0xbb, + 0xef, 0xd0, 0x7f, 0xc1, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, + 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, + 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x39, 0x71, 0x06, 0xde, 0x16, 0xdc, + 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0xfa, 0x1f, 0xb7, 0xc4, 0xca, 0x3e, 0x38, 0x03, 0x5e, 0x54, + 0x01, 0xdf, 0x72, 0x65, 0xce, 0x62, 0x80, 0x6f, 0x7c, 0x71, 0x39, 0x49, 0x82, 0x36, 0xd0, 0x49, + 0x49, 0x4c, 0xe2, 0x3c, 0x23, 0x6e, 0xcd, 0x50, 0x38, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x3a, + 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xf3, + 0x25, 0x20, 0x34, 0xc1, 0x67, 0x37, 0x55, 0x10, 0x00, 0xdd, 0x8d, 0x13, 0x05, 0xc5, 0x7b, 0xef, + 0xe0, 0x1f, 0xb5, 0xef, 0xd0, 0x7f, 0xbb, 0x01, 0xa0, 0x39, 0x71, 0x2a, 0xd6, 0x37, 0x55, 0x10, + 0x00, 0x2e, 0xd4, 0x13, 0x05, 0xc5, 0x7b, 0x89, 0x45, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, + 0xd8, 0x32, 0xd2, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, + 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xef, 0xe0, 0xbf, 0xb1, 0xef, 0xd0, 0x1f, 0xb8, 0xf2, 0x50, 0xe2, + 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, + 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, + 0x00, 0x20, 0x30, 0x37, 0x07, 0x01, 0x01, 0xb7, 0x07, 0x00, 0x01, 0x13, 0x07, 0x17, 0x10, 0x98, + 0xd3, 0x37, 0x07, 0x03, 0x04, 0x09, 0x07, 0xd8, 0xd3, 0x13, 0x07, 0x50, 0x60, 0x98, 0xd7, 0x37, + 0x17, 0x09, 0x00, 0x13, 0x07, 0x77, 0x80, 0xd8, 0xd7, 0x37, 0x17, 0x0b, 0x0b, 0x13, 0x07, 0xa7, + 0xa0, 0x98, 0xdb, 0x37, 0x17, 0x0c, 0x00, 0x13, 0x07, 0xb7, 0xc0, 0xd8, 0xdb, 0x37, 0x17, 0x0f, + 0x00, 0x13, 0x07, 0xd7, 0xe0, 0x98, 0xdf, 0x05, 0x67, 0xd8, 0xdf, 0xb7, 0x17, 0xff, 0x7f, 0x93, + 0x87, 0xfa, 0xf3, 0xbd, 0x3f, 0x3b, 0x8f, 0x42, 0x43, 0xf6, 0x89, 0xf0, 0xa2, 0xe6, 0xf6, 0x3c, + 0x5d, 0xd2, 0x5b, 0x73, 0x53, 0xd4, 0x5e, 0xea, 0xe1, 0x8a, 0x67, 0x59, 0xb5, 0xf7, 0xb9, 0x7c, + 0x7b, 0x88, 0x28, 0x39, 0x07, 0x80, 0x73, 0xa0, 0x47, 0x30, 0xa1, 0x47, 0x73, 0xa0, 0x07, 0x30, + 0x82, 0x80, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x40, 0x00, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, + 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, 0x80, 0x00, 0x73, 0xb0, + 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x3e, 0xc6, 0xb7, 0x07, + 0x00, 0x04, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, + 0x3e, 0xc6, 0xb7, 0x07, 0x00, 0x20, 0x73, 0xb0, 0x47, 0x30, 0xb2, 0x47, 0x41, 0x01, 0x73, 0x00, + 0x20, 0x30, 0x05, 0x65, 0x6f, 0x10, 0xc0, 0x69, 0x05, 0x65, 0x6f, 0x10, 0x20, 0x6a, 0x01, 0x11, + 0x22, 0xcc, 0x4a, 0xc8, 0x4e, 0xc6, 0x06, 0xce, 0x26, 0xca, 0x52, 0xc4, 0x56, 0xc2, 0x9d, 0x47, + 0x2a, 0x84, 0xae, 0x89, 0x32, 0x89, 0x63, 0xd4, 0xc7, 0x00, 0xef, 0xd0, 0x4f, 0x99, 0xef, 0xf0, + 0x5f, 0xfd, 0xb7, 0x07, 0x01, 0x07, 0x18, 0x40, 0xdc, 0x43, 0x93, 0x06, 0xf0, 0x0f, 0x63, 0x05, + 0xd7, 0x00, 0xf1, 0x9b, 0x0d, 0x8b, 0xd9, 0x8f, 0x13, 0xf7, 0xb7, 0xff, 0x83, 0x47, 0x44, 0x00, + 0x81, 0x44, 0x31, 0x4a, 0x8a, 0x07, 0x91, 0x8b, 0xd9, 0x8f, 0x37, 0x07, 0x01, 0x07, 0x5c, 0xc3, + 0xb7, 0x1a, 0x01, 0x07, 0x63, 0xcf, 0x24, 0x03, 0x14, 0x40, 0x05, 0x47, 0xad, 0x47, 0x63, 0x9e, + 0xe6, 0x00, 0x83, 0x46, 0x44, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0xbd, 0x47, 0xfa, 0xf1, 0xd0, 0xfb, + 0x5d, 0x05, 0x9d, 0xe2, 0x55, 0x1f, 0xaf, 0xf8, 0x3a, 0xf5, 0x06, 0x18, 0x37, 0x7f, 0xfa, 0xe9, + 0x45, 0xf6, 0x65, 0xb2, 0x45, 0x7b, 0x51, 0x56, 0x64, 0x69, 0xe2, 0x46, 0x3a, 0x00, 0x3a, 0x63, + 0x97, 0xe6, 0x00, 0x14, 0x44, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2a, 0xd7, 0xf8, 0xf2, 0x40, 0x62, + 0x44, 0x37, 0x07, 0x01, 0x07, 0x5c, 0xc7, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, + 0x4a, 0x05, 0x61, 0x82, 0x80, 0xb3, 0x85, 0x44, 0x03, 0x13, 0x95, 0x44, 0x00, 0x31, 0x46, 0x56, + 0x95, 0x85, 0x04, 0xce, 0x95, 0xef, 0xf0, 0x4f, 0x87, 0x7d, 0xb7, 0x1d, 0x71, 0x3e, 0xda, 0xb7, + 0x07, 0x01, 0x07, 0xa2, 0xc6, 0x80, 0x47, 0x86, 0xce, 0x96, 0xcc, 0x9a, 0xca, 0x9e, 0xc8, 0xaa, + 0xc4, 0xae, 0xc2, 0xb2, 0xc0, 0x36, 0xde, 0x3a, 0xdc, 0x42, 0xd8, 0x46, 0xd6, 0x72, 0xd4, 0x76, + 0xd2, 0x7a, 0xd0, 0x7e, 0xce, 0x93, 0x77, 0xb4, 0x00, 0x95, 0xc7, 0xb7, 0x07, 0x00, 0x40, 0x73, + 0xb0, 0x47, 0x30, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0xa2, + 0x86, 0x13, 0x06, 0x06, 0x7c, 0x93, 0x85, 0x85, 0x7c, 0x13, 0x05, 0x85, 0x77, 0xef, 0xe0, 0x3f, + 0x8c, 0xef, 0xd0, 0xff, 0x99, 0x93, 0x77, 0x44, 0x00, 0x99, 0xcf, 0xb7, 0x37, 0x20, 0x00, 0x83, + 0xa7, 0x47, 0xf9, 0x91, 0xcb, 0x6c, 0x00, 0x28, 0x00, 0x82, 0x97, 0x22, 0x47, 0xb7, 0x07, 0x01, + 0x07, 0x98, 0xcb, 0x32, 0x47, 0xd8, 0xcb, 0xb7, 0x07, 0x01, 0x07, 0x80, 0xc7, 0x36, 0x44, 0xf6, + 0x40, 0xe6, 0x42, 0x56, 0x43, 0xc6, 0x43, 0x26, 0x45, 0x96, 0x45, 0x06, 0x46, 0xf2, 0x56, 0x62, + 0x57, 0xd2, 0x57, 0x42, 0x58, 0xb2, 0x58, 0xfa, 0xad, 0x0d, 0x96, 0x72, 0x90, 0x0e, 0xf4, 0x1c, + 0xdb, 0x0f, 0x60, 0x37, 0x98, 0x29, 0x7b, 0x73, 0x0f, 0x2a, 0xbb, 0xe0, 0xe4, 0x00, 0x4d, 0x42, + 0xd1, 0x0f, 0x9a, 0xf5, 0x8a, 0x25, 0xce, 0x1d, 0xd8, 0x3a, 0x22, 0x5e, 0x92, 0x5e, 0x02, 0x5f, + 0xf2, 0x4f, 0x25, 0x61, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x07, 0x02, 0x04, 0xdc, 0x47, 0x13, 0x05, + 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x82, 0x80, 0x13, 0x05, + 0x00, 0x08, 0x6f, 0x10, 0x40, 0x52, 0x13, 0x05, 0x00, 0x08, 0x6f, 0x10, 0x80, 0x52, 0x41, 0x11, + 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x07, 0xd0, 0x79, 0x37, 0x04, 0x02, 0x04, 0x5c, 0xc4, + 0x85, 0x44, 0x95, 0x65, 0x37, 0x35, 0x10, 0x00, 0x04, 0xc4, 0x93, 0x85, 0x05, 0xe2, 0x13, 0x05, + 0x65, 0x6e, 0xef, 0xe0, 0xdf, 0xce, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x13, 0xf5, 0x02, 0x54, 0x44, + 0x63, 0x82, 0x96, 0x02, 0x37, 0x56, 0x10, 0x00, 0xb7, 0x55, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, + 0x13, 0x06, 0xc6, 0x7c, 0x93, 0x85, 0x45, 0x7d, 0x13, 0x05, 0x45, 0x75, 0xef, 0xe0, 0x6f, 0xff, + 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, + 0x06, 0xc6, 0xef, 0xf0, 0xdf, 0xf8, 0xb2, 0x40, 0xb7, 0x07, 0x02, 0x04, 0x11, 0x47, 0x98, 0xc7, + 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x22, 0xc4, + 0x26, 0xc2, 0x23, 0xac, 0xe7, 0xf8, 0x06, 0xc6, 0x37, 0x07, 0x02, 0x02, 0x89, 0x46, 0x54, 0xc7, + 0x13, 0x84, 0x87, 0xf9, 0x93, 0x04, 0x50, 0x05, 0xef, 0xe0, 0x5f, 0xc7, 0x1c, 0x40, 0xe3, 0x9d, + 0x97, 0xfe, 0xfa, 0x5a, 0xd1, 0x14, 0x0a, 0x0d, 0x7c, 0x7b, 0x45, 0xab, 0x96, 0xb1, 0xc4, 0x9b, + 0x32, 0xb4, 0x6a, 0xca, 0x4e, 0x3b, 0x5b, 0xd9, 0xf3, 0x45, 0x98, 0xc4, 0xe7, 0x86, 0x28, 0x5b, + 0xe0, 0xb0, 0xc6, 0xb0, 0x3b, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, + 0x07, 0x02, 0x02, 0xc8, 0xcb, 0x05, 0x47, 0xd8, 0xc7, 0xd8, 0x53, 0x69, 0x8f, 0x63, 0x1e, 0xa7, + 0x00, 0xd4, 0x57, 0x7d, 0x55, 0xf9, 0x8e, 0x91, 0xea, 0x94, 0x57, 0x75, 0x8f, 0x19, 0xe7, 0x88, + 0x47, 0x05, 0x89, 0x33, 0x05, 0xa0, 0x40, 0x82, 0x80, 0x7d, 0x55, 0x82, 0x80, 0x41, 0x45, 0x6f, + 0x10, 0x60, 0x44, 0x41, 0x45, 0x6f, 0x10, 0x40, 0x43, 0x01, 0x11, 0x06, 0xce, 0x22, 0xcc, 0x2a, + 0xc6, 0xef, 0xf0, 0x3f, 0xff, 0x13, 0x07, 0x50, 0x05, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xac, 0xe7, + 0xf8, 0x37, 0x04, 0x02, 0x02, 0xa1, 0x47, 0x5c, 0xc4, 0x32, 0x45, 0x85, 0x47, 0x1c, 0xc8, 0x93, + 0x07, 0x10, 0x40, 0x5c, 0xc0, 0xef, 0xf0, 0xbf, 0xf9, 0xef, 0xf0, 0xff, 0xf5, 0x23, 0x22, 0x04, + 0x00, 0x62, 0x44, 0xf2, 0x40, 0x05, 0x61, 0x6f, 0xf0, 0x7f, 0xfb, 0x41, 0x11, 0x3a, 0xc6, 0x37, + 0x07, 0x02, 0x02, 0x3e, 0xc4, 0x1c, 0x47, 0x1c, 0xc7, 0x85, 0x8b, 0x99, 0xc7, 0xb7, 0x37, 0x20, + 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xac, 0xe7, 0xf8, 0x32, 0x47, 0xa2, 0x47, 0x41, 0x01, 0x73, + 0x00, 0x20, 0x30, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0xc7, 0xf9, 0x82, 0x80, 0xb7, 0x27, 0x00, + 0x06, 0x9c, 0x47, 0x05, 0x47, 0x13, 0x05, 0xa0, 0x0a, 0x9d, 0x8b, 0xfd, 0x17, 0x63, 0x74, 0xf7, + 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x37, 0x27, 0x00, 0x06, 0x1c, 0x47, 0xfa, 0x40, 0xea, + 0x29, 0x81, 0xae, 0xe3, 0x85, 0x0f, 0x07, 0x8b, 0x3f, 0x7a, 0x35, 0x17, 0x8c, 0x4c, 0xf2, 0x52, + 0x8a, 0x9f, 0xbe, 0x32, 0x6f, 0x10, 0xdf, 0x12, 0xa5, 0x85, 0x8b, 0xda, 0xf9, 0x96, 0x88, 0x3c, + 0x85, 0x46, 0x13, 0x05, 0xa0, 0x0a, 0x9d, 0x8b, 0x63, 0x89, 0xd7, 0x00, 0x1c, 0x47, 0x09, 0x47, + 0x9d, 0x8b, 0x63, 0x84, 0xe7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, + 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xc0, 0x1f, 0xe9, 0x89, 0x67, + 0x63, 0x64, 0xf4, 0x00, 0xef, 0xc0, 0x7f, 0xe8, 0x89, 0x65, 0x37, 0x45, 0x10, 0x00, 0x13, 0x05, + 0x25, 0x88, 0x93, 0x85, 0x05, 0x71, 0xef, 0xe0, 0x3f, 0xc2, 0x37, 0x05, 0x00, 0x06, 0x2a, 0x94, + 0x08, 0x40, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x65, 0xb7, 0x37, 0x20, 0x00, + 0x41, 0x11, 0x13, 0x07, 0x50, 0x05, 0x13, 0x05, 0x05, 0x80, 0x23, 0xae, 0xe7, 0xf8, 0x06, 0xc6, + 0xef, 0x10, 0xc0, 0x32, 0xef, 0xf0, 0xdf, 0xf6, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xf5, 0x00, + 0x37, 0x55, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0x85, 0x7d, 0xef, 0xe0, 0x4f, 0xeb, 0xef, 0xc0, + 0xdf, 0xe2, 0xb7, 0x07, 0x46, 0x00, 0xb2, 0x40, 0x37, 0x27, 0x00, 0x06, 0x85, 0x07, 0x5c, 0xcf, + 0x85, 0x47, 0x5c, 0xc7, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0xb7, 0x55, 0x10, 0x00, 0x13, 0x06, + 0x00, 0x03, 0x93, 0x85, 0xc5, 0x7d, 0x0a, 0x85, 0x22, 0xdc, 0x26, 0xda, 0x4a, 0xd8, 0x06, 0xde, + 0x0a, 0x84, 0xef, 0x10, 0x50, 0x39, 0x7d, 0x59, 0xb7, 0x24, 0x00, 0x06, 0x08, 0x40, 0x19, 0xc9, + 0xef, 0xf0, 0xdf, 0xf4, 0x63, 0x13, 0x25, 0x01, 0xfa, 0xb2, 0x5a, 0x7e, 0x54, 0x18, 0x27, 0xa0, + 0x3a, 0x5a, 0xcf, 0x9f, 0x0b, 0x7f, 0xe5, 0xca, 0x69, 0xf8, 0xd0, 0xd7, 0xa0, 0xfe, 0x16, 0x4b, + 0x2a, 0xb9, 0x5b, 0x17, 0x5c, 0xe3, 0xac, 0xe8, 0xf0, 0x60, 0x3d, 0x08, 0x44, 0x5c, 0x40, 0x31, + 0x04, 0xa6, 0x97, 0x88, 0xc3, 0xed, 0xb7, 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, 0x42, 0x59, 0x21, + 0x61, 0x82, 0x80, 0x37, 0x27, 0x00, 0x06, 0x1c, 0x47, 0x85, 0x46, 0x9d, 0x8b, 0x63, 0x89, 0xd7, + 0x02, 0x41, 0x11, 0x06, 0xc6, 0x89, 0x65, 0x37, 0x45, 0x10, 0x00, 0x14, 0xcb, 0x13, 0x05, 0x85, + 0x86, 0x93, 0x85, 0x05, 0x71, 0xef, 0xe0, 0x7f, 0xb5, 0xb7, 0x27, 0x00, 0x06, 0x09, 0x47, 0x98, + 0xcb, 0x05, 0x65, 0xb2, 0x40, 0x13, 0x05, 0x05, 0x80, 0x41, 0x01, 0x6f, 0x10, 0x00, 0x28, 0xb7, + 0x27, 0x00, 0x06, 0x09, 0x47, 0x05, 0x65, 0x98, 0xcb, 0x13, 0x05, 0x05, 0x80, 0xfd, 0xb7, 0x05, + 0x65, 0x41, 0x11, 0x13, 0x05, 0x05, 0x80, 0x06, 0xc6, 0xef, 0x10, 0x60, 0x25, 0xb2, 0x40, 0xb7, + 0x27, 0x00, 0x06, 0x21, 0x47, 0x98, 0xcb, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0x22, + 0xc4, 0x26, 0xc2, 0xaa, 0x84, 0xef, 0xf0, 0xbf, 0xeb, 0x2a, 0x84, 0x6d, 0x2a, 0x13, 0x75, 0xf5, + 0x07, 0xef, 0xe0, 0x7f, 0xa1, 0x26, 0x85, 0xef, 0xf0, 0x9f, 0xea, 0x63, 0x05, 0xa4, 0x00, 0xef, + 0xc0, 0xff, 0xd3, 0x01, 0x45, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x79, + 0x71, 0x22, 0xd4, 0x26, 0xd2, 0x4a, 0xd0, 0x4e, 0xce, 0x06, 0xd6, 0x52, 0xcc, 0xaa, 0x89, 0x2e, + 0x89, 0x93, 0x74, 0xc6, 0xff, 0x01, 0x44, 0x33, 0x8a, 0x89, 0x00, 0x33, 0x05, 0x89, 0x00, 0x63, + 0x1a, 0x94, 0x00, 0xfa, 0xc1, 0xfd, 0xf6, 0x6b, 0x03, 0xc3, 0xcb, 0x0f, 0x53, 0xc3, 0x2a, 0xa9, + 0xbe, 0x0d, 0x45, 0x01, 0xb2, 0x8c, 0x34, 0xde, 0x06, 0xcb, 0xa3, 0x21, 0x2f, 0x68, 0x87, 0x08, + 0x49, 0x8f, 0xa3, 0xde, 0x38, 0x3e, 0xb2, 0x50, 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xf2, 0x49, + 0x62, 0x4a, 0x45, 0x61, 0x82, 0x80, 0xef, 0xf0, 0x9f, 0xf9, 0x2a, 0xc6, 0x11, 0x46, 0x6c, 0x00, + 0x52, 0x85, 0xef, 0x10, 0xb0, 0x28, 0x11, 0x04, 0xc9, 0xbf, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, + 0x1f, 0xf8, 0x2a, 0x87, 0x85, 0x46, 0x01, 0x45, 0x89, 0x45, 0x01, 0xe7, 0xb2, 0x40, 0x41, 0x01, + 0x82, 0x80, 0x93, 0x77, 0xf7, 0x00, 0x01, 0x46, 0x81, 0xef, 0x63, 0xd3, 0xc5, 0x00, 0xb6, 0x87, + 0x5d, 0x8d, 0x86, 0x06, 0x13, 0x75, 0xf5, 0x0f, 0x93, 0xf6, 0xf6, 0x0f, 0x11, 0x83, 0xf1, 0xbf, + 0x13, 0xf8, 0x17, 0x00, 0x85, 0x83, 0x42, 0x96, 0x93, 0xf7, 0xf7, 0x0f, 0xf1, 0xbf, 0x41, 0x11, + 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0x93, 0x77, 0x35, 0x00, 0x2a, 0x84, 0xae, 0x84, 0x99, 0xc3, + 0xef, 0xc0, 0x1f, 0xc9, 0x89, 0x67, 0x63, 0x64, 0xf4, 0x00, 0xef, 0xc0, 0x7f, 0xc8, 0xb7, 0x37, + 0x20, 0x00, 0x13, 0x07, 0x50, 0x05, 0x23, 0xae, 0xe7, 0xf8, 0xb7, 0x27, 0x00, 0x06, 0x84, 0xcf, + 0xc0, 0xcb, 0x22, 0x44, 0xb2, 0x40, 0x92, 0x44, 0x11, 0x47, 0x98, 0xcb, 0x89, 0x65, 0x37, 0x45, + 0x10, 0x00, 0x93, 0x85, 0x05, 0x71, 0x13, 0x05, 0xe5, 0x85, 0x41, 0x01, 0x6f, 0xe0, 0x3f, 0xa0, + 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xaa, 0x84, 0x2e, 0x84, 0xef, 0xf0, 0x3f, 0xfa, + 0x26, 0x85, 0xef, 0xf0, 0x1f, 0xda, 0x63, 0x09, 0x85, 0x00, 0x13, 0x05, 0x50, 0x05, 0xfa, 0x27, + 0xc2, 0x44, 0x8d, 0x9c, 0x5e, 0xf7, 0x3c, 0x3d, 0x1c, 0x55, 0xeb, 0xf3, 0xa5, 0x6d, 0x8e, 0x51, + 0x6e, 0xa3, 0x7d, 0xca, 0xf1, 0x35, 0x94, 0x4e, 0x3a, 0xcb, 0x5f, 0x22, 0x85, 0x41, 0x0d, 0x10, + 0x3f, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, 0xa0, 0x0a, 0xcd, + 0xbf, 0x39, 0x71, 0x3a, 0xce, 0x37, 0x27, 0x00, 0x06, 0x3e, 0xcc, 0x1c, 0x47, 0x06, 0xde, 0x16, + 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, + 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xa1, 0x8b, 0x85, 0xcf, 0xa1, 0x47, 0x1c, + 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x13, 0x07, 0xa0, 0x0a, 0x23, 0xae, 0xe7, 0xf8, 0xf2, 0x50, 0xe2, + 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, + 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, + 0x00, 0x20, 0x30, 0x37, 0x55, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x85, 0x7d, 0xef, 0xe0, 0xaf, + 0xc3, 0xef, 0xd0, 0x0f, 0xca, 0xe1, 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa0, 0xa7, 0xfa, 0x05, + 0x47, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x82, 0xe7, 0xfa, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x83, + 0xc7, 0x47, 0xfa, 0x41, 0x11, 0x06, 0xc6, 0x99, 0xe3, 0xef, 0xc0, 0xbf, 0xb8, 0xb7, 0x37, 0x20, + 0x00, 0x93, 0x87, 0x07, 0xfa, 0x88, 0x43, 0x37, 0x67, 0x19, 0x00, 0x13, 0x07, 0xd7, 0x60, 0x33, + 0x05, 0xe5, 0x02, 0x37, 0xf7, 0x6e, 0x3c, 0xb2, 0x40, 0x13, 0x07, 0xf7, 0x35, 0x3a, 0x95, 0x88, + 0xc3, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0xfa, 0xf6, 0x9e, 0x95, 0xca, 0x9e, 0xd2, + 0x8c, 0x3f, 0xd0, 0x2d, 0x3c, 0x9b, 0x30, 0xe2, 0x63, 0x99, 0xa3, 0x9d, 0xd2, 0x1a, 0x53, 0x88, + 0x1b, 0x2e, 0x53, 0xb6, 0x83, 0xcb, 0x09, 0x9f, 0xbc, 0xe5, 0xe8, 0x3f, 0x93, 0x87, 0x47, 0xe9, + 0x98, 0x43, 0x94, 0x47, 0xdc, 0x43, 0x18, 0x4f, 0x13, 0x05, 0xa0, 0x0a, 0x75, 0x8f, 0x63, 0x04, + 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x47, 0xe9, + 0x88, 0xc3, 0x37, 0x45, 0x10, 0x00, 0x13, 0x07, 0x00, 0x10, 0x93, 0x05, 0x80, 0x3e, 0x13, 0x05, + 0x45, 0xbe, 0x23, 0xa2, 0x07, 0x00, 0x98, 0xc7, 0x6f, 0xe0, 0x8f, 0xff, 0x37, 0x07, 0x01, 0x02, + 0x5c, 0x43, 0xb7, 0x06, 0x05, 0x00, 0xd5, 0x8f, 0x5c, 0xc3, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, + 0x06, 0xc6, 0x2a, 0x84, 0xb7, 0x37, 0x00, 0x08, 0x37, 0x05, 0x08, 0x00, 0x63, 0x0c, 0xf4, 0x00, + 0xb7, 0x27, 0x00, 0x08, 0x37, 0x05, 0x04, 0x00, 0x63, 0x06, 0xf4, 0x00, 0xef, 0xc0, 0xbf, 0xae, + 0x37, 0x05, 0x08, 0x00, 0xef, 0x00, 0x50, 0x7c, 0x5c, 0x5c, 0x22, 0x85, 0xb2, 0x40, 0x93, 0xe7, + 0x37, 0x00, 0x5c, 0xdc, 0x23, 0x2c, 0x04, 0x00, 0x22, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0xdf, 0xf8, + 0xfd, 0x77, 0x41, 0x11, 0xfd, 0x17, 0x22, 0xc4, 0x06, 0xc6, 0xe9, 0x8f, 0x37, 0x27, 0x00, 0x08, + 0x2a, 0x84, 0x63, 0x84, 0xe7, 0x00, 0xef, 0xc0, 0x1f, 0xab, 0x5c, 0x5c, 0x37, 0x05, 0x04, 0x00, + 0xf5, 0x9b, 0x5c, 0xdc, 0xb7, 0x27, 0x00, 0x08, 0x63, 0x04, 0xf4, 0x00, 0x37, 0x05, 0x08, 0x00, + 0x22, 0x44, 0xb2, 0x40, 0x41, 0x01, 0x6f, 0x00, 0xf0, 0x77, 0x39, 0x71, 0x22, 0xdc, 0x26, 0xda, + 0x4a, 0xd8, 0x06, 0xde, 0xfa, 0x48, 0x9c, 0x5c, 0x0b, 0xb9, 0x41, 0xef, 0x46, 0x07, 0xf1, 0x14, + 0x9a, 0xcc, 0x61, 0x9a, 0xfe, 0xdc, 0x4b, 0xf6, 0xff, 0x82, 0x46, 0x65, 0x34, 0x8f, 0xe9, 0xce, + 0xa6, 0xc4, 0x62, 0x73, 0x11, 0xc0, 0x40, 0x4e, 0xd6, 0x52, 0xd4, 0x56, 0xd2, 0x5a, 0xd0, 0x5e, + 0xce, 0x62, 0xcc, 0xaa, 0x84, 0x2e, 0x89, 0x32, 0x84, 0x99, 0xe1, 0xef, 0xc0, 0xff, 0xa6, 0xfd, + 0x77, 0xfd, 0x17, 0xe5, 0x8f, 0x37, 0x27, 0x00, 0x08, 0x63, 0x84, 0xe7, 0x00, 0xef, 0xc0, 0xdf, + 0xa5, 0xb7, 0x39, 0x20, 0x00, 0x93, 0x89, 0x49, 0xe9, 0x85, 0x4a, 0x37, 0x4b, 0x10, 0x00, 0x93, + 0x0b, 0xa0, 0x0a, 0x11, 0x4c, 0x15, 0xe4, 0x9c, 0x4c, 0x37, 0x07, 0x11, 0x00, 0x13, 0x05, 0xa0, + 0x0a, 0xf9, 0x8f, 0x99, 0xc3, 0x13, 0x05, 0x50, 0x05, 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, 0x42, + 0x59, 0xb2, 0x59, 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, 0x21, 0x61, 0x82, + 0x80, 0x93, 0x05, 0x80, 0x3e, 0x13, 0x05, 0x4b, 0xbe, 0x23, 0xa0, 0x99, 0x00, 0x23, 0xa2, 0x59, + 0x01, 0x23, 0xa4, 0x59, 0x01, 0xef, 0xe0, 0xef, 0xed, 0xe3, 0x16, 0x75, 0xfd, 0xdc, 0x50, 0x22, + 0x8a, 0x3e, 0xc6, 0x63, 0x73, 0x8c, 0x00, 0x11, 0x4a, 0x4a, 0x85, 0x52, 0x86, 0x6c, 0x00, 0xef, + 0x10, 0x60, 0x78, 0x52, 0x99, 0x33, 0x04, 0x44, 0x41, 0x71, 0xbf, 0x41, 0x11, 0x37, 0x05, 0x02, + 0x00, 0x06, 0xc6, 0xef, 0x00, 0x90, 0x6b, 0xb2, 0x40, 0xb7, 0x17, 0x00, 0x08, 0x37, 0x07, 0x07, + 0x00, 0x98, 0xd3, 0x13, 0x05, 0x40, 0x1f, 0x41, 0x01, 0x6f, 0xe0, 0x2f, 0xe4, 0xb7, 0x17, 0x00, + 0x08, 0x23, 0xa0, 0x07, 0x02, 0x37, 0x05, 0x02, 0x00, 0x6f, 0x00, 0xf0, 0x69, 0x39, 0x71, 0xfa, + 0xb9, 0xbb, 0x04, 0xe9, 0x14, 0x0b, 0x0c, 0x14, 0x47, 0xf3, 0x40, 0x0b, 0x2d, 0xb7, 0x5b, 0x54, + 0x2b, 0x7c, 0x4c, 0x00, 0x23, 0x1d, 0x3f, 0xeb, 0xe3, 0xa8, 0x84, 0xa6, 0x49, 0xb6, 0x21, 0x0d, + 0x98, 0x41, 0x3e, 0xcc, 0xb7, 0x17, 0x00, 0x08, 0x3a, 0xce, 0x98, 0x57, 0x06, 0xde, 0x16, 0xdc, + 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, 0xc8, + 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0x05, 0x8b, 0x05, 0xcb, 0x98, 0x57, 0x13, 0x67, + 0x17, 0x00, 0x98, 0xd7, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, + 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, + 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x98, 0x57, 0x09, 0x8b, 0x09, 0xc7, + 0x98, 0x57, 0x13, 0x67, 0x27, 0x00, 0xf1, 0xb7, 0x98, 0x57, 0x11, 0x8b, 0x09, 0xc7, 0x98, 0x57, + 0x13, 0x67, 0x47, 0x00, 0x7d, 0xbf, 0xb7, 0x07, 0x00, 0x01, 0x73, 0xb0, 0x47, 0x30, 0xef, 0xd0, + 0xcf, 0xa1, 0x4d, 0xbf, 0x37, 0x07, 0x00, 0x02, 0x5c, 0x4f, 0xb7, 0x36, 0x20, 0x00, 0x13, 0xf6, + 0x77, 0x00, 0xe1, 0x9b, 0x23, 0xa4, 0xc6, 0xfa, 0x93, 0xe7, 0x47, 0x00, 0x5c, 0xcf, 0x1c, 0x4f, + 0xf9, 0x9b, 0x1c, 0xcf, 0x82, 0x80, 0x41, 0x11, 0x26, 0xc2, 0xb7, 0x04, 0x00, 0x02, 0x22, 0xc4, + 0xc0, 0x4c, 0x9c, 0x4c, 0x06, 0xc6, 0x13, 0x05, 0x80, 0x07, 0x93, 0xe7, 0x17, 0x00, 0x9c, 0xcc, + 0xef, 0xe0, 0xef, 0xd6, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x87, 0xfa, 0x61, 0x98, 0xb2, 0x40, + 0x5d, 0x8c, 0xc0, 0xcc, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0xfa, 0x6d, 0x97, 0x0c, 0x41, 0x57, + 0x5b, 0x3f, 0x3d, 0x77, 0xa9, 0x84, 0x83, 0x04, 0x4e, 0x80, 0xcb, 0x33, 0x17, 0x19, 0x4c, 0xc3, + 0xab, 0x07, 0x42, 0xb7, 0xa8, 0x6d, 0xbe, 0x06, 0xf2, 0x8e, 0x24, 0x70, 0x42, 0x82, 0x80, 0x13, + 0x17, 0x05, 0x01, 0x93, 0x17, 0x85, 0x01, 0xba, 0x97, 0x13, 0x17, 0x85, 0x00, 0xba, 0x97, 0x3e, + 0x95, 0xb7, 0x07, 0x00, 0x04, 0x88, 0xd3, 0xc8, 0xd3, 0x88, 0xd7, 0xc8, 0xd7, 0x88, 0xdb, 0xc8, + 0xdb, 0x88, 0xdf, 0xc8, 0xdf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x00, 0x08, 0x98, + 0xd3, 0x23, 0xa2, 0x07, 0x02, 0x23, 0xa4, 0x07, 0x02, 0x23, 0xa6, 0x07, 0x02, 0x23, 0xa8, 0x07, + 0x02, 0x23, 0xaa, 0x07, 0x02, 0x23, 0xac, 0x07, 0x02, 0x23, 0xae, 0x07, 0x02, 0x82, 0x80, 0xb7, + 0x37, 0x20, 0x00, 0x03, 0xa5, 0x07, 0xeb, 0x82, 0x80, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, + 0x06, 0x00, 0x02, 0x13, 0x05, 0x05, 0x02, 0x6f, 0xe0, 0x0f, 0xfd, 0xb7, 0x37, 0x20, 0x00, 0x13, + 0x07, 0x50, 0x05, 0x23, 0xa8, 0xe7, 0xea, 0xb7, 0x07, 0x00, 0x04, 0xc8, 0xc3, 0x13, 0x07, 0x90, + 0x02, 0x85, 0x65, 0x37, 0x45, 0x10, 0x00, 0x98, 0xc7, 0x93, 0x85, 0x85, 0x38, 0x13, 0x05, 0x25, + 0xec, 0x6f, 0xe0, 0x8f, 0xd1, 0x41, 0x11, 0x22, 0xc4, 0x01, 0x45, 0x37, 0x34, 0x20, 0x00, 0x06, + 0xc6, 0x13, 0x04, 0x04, 0xea, 0xef, 0xf0, 0xbf, 0xf5, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, + 0x07, 0xef, 0xf0, 0xbf, 0xfb, 0x48, 0x44, 0xb7, 0x07, 0x02, 0x00, 0x95, 0x07, 0x7e, 0x05, 0x5d, + 0x8d, 0xef, 0xf0, 0xbf, 0xfa, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x05, 0xef, 0xf0, 0xff, + 0xf9, 0x48, 0x44, 0xb7, 0x07, 0xfa, 0xe2, 0x72, 0xd1, 0x1e, 0xe2, 0x74, 0xab, 0xff, 0x69, 0x9e, + 0xfa, 0x16, 0x8f, 0xc4, 0x87, 0x8a, 0xc0, 0x1a, 0x9d, 0xd1, 0xb3, 0xe9, 0x38, 0x9e, 0x78, 0x6d, + 0x85, 0xb8, 0xb3, 0x80, 0x3b, 0xd7, 0x48, 0x43, 0x00, 0x10, 0x99, 0x07, 0x7e, 0x05, 0x5d, 0x8d, + 0xef, 0xf0, 0xff, 0xf8, 0x48, 0x44, 0xb7, 0x07, 0x01, 0x10, 0x99, 0x07, 0x7e, 0x05, 0x5d, 0x8d, + 0xef, 0xf0, 0xff, 0xf7, 0x22, 0x44, 0xb2, 0x40, 0x21, 0x45, 0x41, 0x01, 0x6f, 0xf0, 0x3f, 0xf7, + 0x7d, 0x47, 0x63, 0x7e, 0xb7, 0x04, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, + 0x13, 0x05, 0x05, 0x02, 0x6f, 0xe0, 0x6f, 0xf2, 0xb3, 0x06, 0xf5, 0x00, 0x83, 0xc6, 0x06, 0x00, + 0x33, 0x07, 0xf1, 0x00, 0x85, 0x07, 0x23, 0x00, 0xd7, 0x00, 0xe3, 0x97, 0xf5, 0xfe, 0x18, 0x10, + 0x93, 0x87, 0x15, 0x00, 0xba, 0x95, 0x13, 0x07, 0x00, 0xf8, 0x23, 0x80, 0xe5, 0xfe, 0x13, 0x07, + 0x00, 0x02, 0x63, 0x92, 0xe7, 0x02, 0x37, 0x05, 0x00, 0x04, 0x8a, 0x85, 0x13, 0x06, 0x00, 0x02, + 0x13, 0x05, 0x05, 0x02, 0xef, 0xe0, 0x6f, 0xee, 0xb2, 0x50, 0x45, 0x61, 0x82, 0x80, 0x79, 0x71, + 0x06, 0xd6, 0x81, 0x47, 0xd9, 0xb7, 0xb3, 0x06, 0xf1, 0x00, 0x23, 0x80, 0x06, 0x00, 0x85, 0x07, + 0xc9, 0xbf, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x00, 0x08, 0x98, 0xd3, 0x23, 0xa2, 0x07, 0x02, + 0x23, 0xa4, 0x07, 0x02, 0x23, 0xa6, 0x07, 0x02, 0x23, 0xa8, 0x07, 0x02, 0x13, 0x17, 0xb5, 0x00, + 0xb7, 0x06, 0xff, 0x00, 0x23, 0xaa, 0x07, 0x02, 0x75, 0x8f, 0x6e, 0x05, 0x23, 0xac, 0x07, 0x02, + 0x3a, 0x95, 0xc8, 0xdf, 0x82, 0x80, 0x37, 0x65, 0x10, 0x00, 0x01, 0x11, 0x13, 0x05, 0x45, 0x81, + 0xfa, 0x91, 0x33, 0xb7, 0xfc, 0x20, 0xee, 0xb1, 0xaa, 0x15, 0xcf, 0xc4, 0xc6, 0xdd, 0x50, 0x9b, + 0xca, 0x7f, 0xc3, 0x59, 0xe7, 0x2e, 0x34, 0x6d, 0x74, 0x95, 0x95, 0x30, 0x31, 0xd0, 0xf0, 0xe3, + 0xf0, 0x20, 0x44, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0x52, 0xc4, 0x37, + 0x34, 0x20, 0x00, 0xef, 0xf0, 0xdf, 0xe9, 0x93, 0x07, 0x04, 0xea, 0xc8, 0x47, 0x7e, 0x05, 0x13, + 0x65, 0x05, 0x07, 0xef, 0xf0, 0xff, 0xe9, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x10, 0xf5, 0x2e, 0xaa, + 0x84, 0x13, 0x05, 0x00, 0x02, 0xef, 0xf0, 0x1f, 0xf9, 0x13, 0x04, 0x04, 0xea, 0x48, 0x44, 0x7e, + 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xe7, 0xaa, 0x89, 0x63, 0x10, 0x95, 0x2c, 0x48, + 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0x7f, 0xe6, 0xaa, + 0x84, 0x63, 0x15, 0x35, 0x2b, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0x5f, + 0xe5, 0xaa, 0x89, 0x63, 0x1c, 0x95, 0x28, 0x1c, 0x40, 0x48, 0x44, 0x37, 0x0a, 0x00, 0x04, 0x83, + 0xc7, 0x07, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x15, 0x00, 0x93, 0xe7, 0x07, 0x20, 0x23, 0x2c, 0xfa, + 0x00, 0xef, 0xf0, 0x1f, 0xe3, 0xaa, 0x84, 0x63, 0x1a, 0x35, 0x27, 0x48, 0x44, 0x7e, 0x05, 0x33, + 0x65, 0x25, 0x01, 0xef, 0xf0, 0xff, 0xe1, 0x2a, 0x89, 0x63, 0x11, 0x95, 0x26, 0xef, 0xf0, 0x1f, + 0xdd, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x9f, 0xe0, 0xaa, 0x84, 0x63, + 0x16, 0x25, 0x25, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0xff, 0xef, 0x48, 0x44, 0x23, 0x20, 0x0a, + 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xbf, 0xde, 0xfa, 0xa1, 0x58, 0x5b, 0x85, + 0x9b, 0x13, 0x77, 0xa0, 0x34, 0x49, 0x8a, 0x35, 0xce, 0x8d, 0x6c, 0x1e, 0xcb, 0x01, 0x16, 0x19, + 0x0f, 0xb2, 0xe1, 0x0f, 0xf1, 0x55, 0xf2, 0xf9, 0xa4, 0x84, 0x9e, 0x88, 0xf8, 0x44, 0x2a, 0x89, + 0x63, 0x17, 0x95, 0x22, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x9f, 0xdd, + 0xaa, 0x84, 0x63, 0x1e, 0x25, 0x21, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, + 0x7f, 0xdc, 0x63, 0x16, 0x95, 0x20, 0x48, 0x44, 0x93, 0x07, 0x00, 0x10, 0x23, 0x2c, 0xfa, 0x00, + 0x7e, 0x05, 0x13, 0x65, 0x15, 0x00, 0xef, 0xf0, 0xff, 0xda, 0x93, 0x07, 0xa0, 0x0a, 0xaa, 0x84, + 0x63, 0x17, 0xf5, 0x1e, 0x48, 0x44, 0x09, 0x69, 0x0d, 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, + 0xef, 0xf0, 0x5f, 0xd9, 0xaa, 0x89, 0x63, 0x1c, 0x95, 0x1c, 0xef, 0xf0, 0x7f, 0xd4, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xff, 0xd7, 0xaa, 0x84, 0x63, 0x11, 0x35, 0x1d, + 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x5f, 0xe7, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0x1f, 0xd6, 0xaa, 0x89, 0x63, 0x12, 0x95, 0x1a, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xff, 0xd4, 0xaa, 0x84, 0x63, 0x19, 0x35, 0x19, + 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, 0xf0, 0xdf, 0xd3, 0xaa, 0x89, 0x63, 0x10, + 0x95, 0x18, 0x08, 0x40, 0x05, 0x05, 0xef, 0xf0, 0xdf, 0xd1, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x17, 0xef, 0xf0, 0x3f, 0xd2, 0xaa, 0x84, 0x63, 0x13, 0x35, 0x17, 0x48, 0x44, 0x7e, 0x05, + 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0xfa, 0xed, 0x2d, 0xa7, 0x6f, 0xa4, 0xa0, 0x5f, 0x57, 0x98, + 0x80, 0x55, 0x1e, 0x24, 0x63, 0xb1, 0xa5, 0x10, 0x5d, 0xcf, 0xee, 0x04, 0x8f, 0xd9, 0xb7, 0x95, + 0xa9, 0x55, 0x2b, 0x89, 0x4c, 0x8b, 0x32, 0xd0, 0x45, 0x1f, 0xd1, 0x2a, 0x89, 0x63, 0x1a, 0x95, + 0x14, 0xef, 0xf0, 0x3f, 0xcc, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xbf, + 0xcf, 0xaa, 0x84, 0x63, 0x1f, 0x25, 0x13, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x1f, 0xdf, 0x48, + 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xcd, 0x63, + 0x11, 0x95, 0x12, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xdf, 0xcc, 0x93, + 0x07, 0xa0, 0x0a, 0x2a, 0x89, 0x63, 0x16, 0xf5, 0x10, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, + 0x02, 0xef, 0xf0, 0x7f, 0xcb, 0xaa, 0x84, 0x63, 0x1d, 0x25, 0x0f, 0x13, 0x05, 0x10, 0x02, 0xef, + 0xf0, 0xdf, 0xda, 0x1c, 0x40, 0x48, 0x44, 0x21, 0x67, 0x83, 0xc7, 0x07, 0x00, 0x7e, 0x05, 0x13, + 0x65, 0x05, 0x17, 0xd9, 0x8f, 0x23, 0x20, 0xfa, 0x02, 0xef, 0xf0, 0xff, 0xc8, 0xaa, 0x89, 0x63, + 0x19, 0x95, 0x0c, 0x48, 0x44, 0x89, 0x64, 0x8d, 0x04, 0x7e, 0x05, 0x45, 0x8d, 0xef, 0xf0, 0xbf, + 0xc7, 0x2a, 0x89, 0x63, 0x1f, 0x35, 0x0b, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x02, 0xef, + 0xf0, 0x9f, 0xc6, 0xaa, 0x89, 0x63, 0x16, 0x25, 0x0b, 0x08, 0x40, 0x13, 0x05, 0x15, 0x02, 0xef, + 0xf0, 0x7f, 0xc4, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0xc4, 0x2a, + 0x89, 0x63, 0x18, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, 0x45, 0x8d, 0xef, 0xf0, 0xdf, 0xc3, 0xaa, + 0x84, 0xfa, 0x4a, 0xaf, 0xa3, 0x8f, 0x01, 0x30, 0xd2, 0x01, 0x38, 0x63, 0x38, 0xa3, 0x75, 0x5a, + 0xf7, 0xf1, 0x6e, 0x45, 0x10, 0xa7, 0x86, 0x73, 0x14, 0xa3, 0x85, 0x35, 0xf5, 0x8e, 0xe7, 0xab, + 0xd8, 0x38, 0xa8, 0x46, 0x63, 0x10, 0x25, 0x09, 0xef, 0xf0, 0xff, 0xbe, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x7f, 0xc2, 0x2a, 0x89, 0x63, 0x15, 0x95, 0x06, 0x13, 0x05, + 0x00, 0x04, 0xef, 0xf0, 0xdf, 0xd1, 0x48, 0x44, 0x23, 0x20, 0x0a, 0x02, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x17, 0xef, 0xf0, 0x9f, 0xc0, 0xaa, 0x84, 0x63, 0x16, 0x25, 0x05, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0x7f, 0xbf, 0x63, 0x1e, 0x95, 0x02, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x52, 0xef, 0xf0, 0x7f, 0xbe, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x14, 0xf5, 0x02, + 0x08, 0x40, 0x62, 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0xb7, 0x05, + 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x05, 0x06, 0x13, 0x05, 0x15, 0x06, 0x05, 0x61, + 0x6f, 0xe0, 0x6f, 0xb0, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, + 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x4e, 0xc6, 0x06, 0xce, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, + 0x52, 0xc4, 0x93, 0x09, 0x00, 0x04, 0x63, 0xe8, 0xb9, 0x08, 0x37, 0x3a, 0x20, 0x00, 0xaa, 0x84, + 0x2e, 0x84, 0x13, 0x09, 0x0a, 0xea, 0xef, 0xf0, 0x7f, 0xc1, 0x03, 0x25, 0xc9, 0x00, 0x13, 0x0a, + 0x0a, 0xea, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x3f, 0xb7, 0x13, 0x85, 0x04, 0x02, + 0x63, 0x19, 0x34, 0x03, 0xaa, 0x85, 0x37, 0x05, 0x00, 0x04, 0x13, 0x05, 0xfa, 0x85, 0x36, 0x11, + 0xae, 0x38, 0x42, 0x9f, 0x47, 0x69, 0xbd, 0x6a, 0x8a, 0x78, 0xc6, 0x55, 0xe9, 0x29, 0x96, 0xb0, + 0xa5, 0xc9, 0x3f, 0xd7, 0x66, 0x82, 0x57, 0xdf, 0xfe, 0x44, 0xe0, 0x79, 0xaa, 0x80, 0x47, 0x05, + 0x02, 0x13, 0x06, 0x00, 0x02, 0xef, 0xe0, 0x4f, 0xb2, 0x03, 0x25, 0xc9, 0x00, 0x62, 0x44, 0xf2, + 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x17, 0x05, + 0x61, 0x6f, 0xf0, 0xdf, 0xb3, 0xfd, 0x47, 0x63, 0xf5, 0x87, 0x02, 0x93, 0x05, 0x04, 0xfe, 0xef, + 0xf0, 0x1f, 0xbc, 0x13, 0x04, 0x04, 0x04, 0x93, 0x17, 0xb4, 0x00, 0x37, 0x07, 0xff, 0x00, 0xf9, + 0x8f, 0x6e, 0x04, 0x3e, 0x94, 0xb7, 0x07, 0x00, 0x04, 0x03, 0x25, 0xca, 0x00, 0xc0, 0xdf, 0x7d, + 0xbf, 0x01, 0x45, 0xef, 0xf0, 0xff, 0xa9, 0xf1, 0xbf, 0xf2, 0x40, 0x62, 0x44, 0xd2, 0x44, 0x42, + 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x01, 0x11, 0x22, 0xcc, 0x37, 0x34, 0x20, + 0x00, 0x93, 0x07, 0x04, 0xea, 0x52, 0xc4, 0x2a, 0x8a, 0xc8, 0x47, 0x56, 0xc2, 0x06, 0xce, 0x7e, + 0x05, 0x13, 0x65, 0x05, 0x30, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0xae, 0x8a, 0xef, 0xf0, 0x1f, + 0xad, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x11, 0xf5, 0x12, 0xaa, 0x84, 0x13, 0x05, 0x60, 0x03, 0xef, + 0xf0, 0x3f, 0xa5, 0x13, 0x04, 0x04, 0xea, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x45, 0x00, 0xef, + 0xf0, 0xff, 0xaa, 0x2a, 0x89, 0x63, 0x11, 0x95, 0x10, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, + 0x17, 0xef, 0xf0, 0xdf, 0xa9, 0xaa, 0x84, 0x63, 0x18, 0x25, 0x0f, 0x48, 0x44, 0x09, 0x69, 0x0d, + 0x09, 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xfa, 0xda, 0x79, 0x25, 0x60, 0xe6, 0x40, 0xc1, 0x60, + 0x3a, 0x85, 0xd0, 0xb5, 0x2e, 0x51, 0x70, 0x6d, 0x82, 0x7a, 0x5c, 0x25, 0xf8, 0xb2, 0xe1, 0xe0, + 0xca, 0x5d, 0x28, 0x61, 0xc9, 0x5f, 0x7a, 0x81, 0x58, 0x48, 0xef, 0xf0, 0x7f, 0xa8, 0xaa, 0x89, + 0x63, 0x1d, 0x95, 0x0c, 0xd6, 0x85, 0x52, 0x85, 0xef, 0xf0, 0x3f, 0xed, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xdf, 0xa6, 0xaa, 0x84, 0x63, 0x10, 0x35, 0x0d, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x03, 0xef, 0xf0, 0xbf, 0xa5, 0xaa, 0x89, 0x63, 0x17, 0x95, 0x0a, + 0x13, 0x05, 0xc0, 0x05, 0xef, 0xf0, 0x1f, 0x9e, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x45, 0x00, + 0xef, 0xf0, 0x1f, 0xa4, 0xaa, 0x84, 0x63, 0x1a, 0x35, 0x09, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, + 0x05, 0x17, 0xef, 0xf0, 0xff, 0xa2, 0xaa, 0x89, 0x63, 0x11, 0x95, 0x08, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x32, 0xef, 0xf0, 0xdf, 0xa1, 0xaa, 0x84, 0x63, 0x18, 0x35, 0x07, 0x48, 0x44, + 0x7e, 0x05, 0x33, 0x65, 0x25, 0x01, 0xef, 0xf0, 0xbf, 0xa0, 0x63, 0x10, 0x95, 0x06, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x05, 0x03, 0xef, 0xf0, 0xbf, 0x9f, 0x93, 0x07, 0xa0, 0x0a, 0x2a, 0x89, + 0x63, 0x15, 0xf5, 0x04, 0x13, 0x05, 0x00, 0x06, 0xef, 0xf0, 0xdf, 0xae, 0x48, 0x44, 0x7e, 0x05, + 0x13, 0x65, 0x05, 0x17, 0xef, 0xf0, 0xdf, 0x9d, 0xaa, 0x84, 0x63, 0x18, 0x25, 0x03, 0x48, 0x44, + 0x7e, 0x05, 0x13, 0x65, 0x35, 0x00, 0xef, 0xf0, 0xbf, 0x9c, 0x63, 0x10, 0x95, 0x02, 0x48, 0x44, + 0x62, 0x44, 0xf2, 0x40, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x7e, 0x05, + 0x13, 0x65, 0xfa, 0x8c, 0x67, 0xa4, 0x02, 0x05, 0xd6, 0x25, 0x26, 0x1e, 0x6f, 0x9e, 0xc2, 0x5a, + 0x97, 0x1b, 0x94, 0xf3, 0x3e, 0xdb, 0xf5, 0xc8, 0x08, 0x9f, 0x5f, 0xa2, 0xb4, 0xb3, 0x72, 0x65, + 0x2c, 0x48, 0x63, 0x30, 0x49, 0x05, 0x02, 0x05, 0x61, 0x6f, 0xf0, 0xbf, 0x9a, 0xf2, 0x40, 0x62, + 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x22, 0x4a, 0x92, 0x4a, 0x05, 0x61, 0x82, 0x80, 0x39, + 0x71, 0x22, 0xdc, 0x37, 0x34, 0x20, 0x00, 0x06, 0xde, 0x4a, 0xd8, 0x26, 0xda, 0x32, 0x89, 0x13, + 0x04, 0x04, 0xea, 0xef, 0xf0, 0xdf, 0xe8, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x40, 0xef, + 0xf0, 0x5f, 0x97, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x12, 0xf5, 0x0a, 0xaa, 0x84, 0x37, 0x65, 0x10, + 0x00, 0x85, 0x45, 0x13, 0x05, 0xc5, 0x80, 0xef, 0xf0, 0x9f, 0xe6, 0x85, 0x47, 0x63, 0x07, 0xf9, + 0x08, 0x48, 0x44, 0x85, 0x67, 0x93, 0x87, 0x07, 0x80, 0x7e, 0x05, 0x5d, 0x8d, 0xef, 0xf0, 0x7f, + 0x94, 0x2a, 0x89, 0x63, 0x1c, 0x95, 0x06, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x06, 0x00, 0x02, 0x93, + 0x85, 0x05, 0x04, 0x68, 0x00, 0xef, 0xe0, 0xaf, 0x87, 0x48, 0x44, 0x89, 0x47, 0x23, 0x06, 0xf1, + 0x02, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x20, 0xef, 0xf0, 0xdf, 0x91, 0xaa, 0x84, 0x63, 0x17, 0x25, + 0x05, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xbf, 0x90, 0x2a, 0x89, 0x63, + 0x1e, 0x95, 0x02, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x42, 0xef, 0xf0, 0x9f, 0x8f, 0xaa, + 0x84, 0x63, 0x15, 0x25, 0x03, 0x68, 0x00, 0x93, 0x05, 0x10, 0x02, 0xef, 0xf0, 0x5f, 0xdf, 0x48, + 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x10, 0xef, 0xf0, 0xdf, 0x8d, 0x63, 0x18, 0xfa, 0xaa, 0xed, + 0xee, 0x51, 0xc9, 0x70, 0x31, 0x26, 0xa4, 0x37, 0x0b, 0xc8, 0xf7, 0xea, 0x4e, 0x7c, 0x02, 0x81, + 0xa8, 0xa3, 0x9b, 0x49, 0x8c, 0xbc, 0x32, 0x0e, 0xc5, 0x56, 0x9e, 0x18, 0x8e, 0x95, 0x08, 0x4a, + 0x95, 0x00, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x04, 0xef, 0xf0, 0xdf, 0x8c, 0xf2, 0x50, + 0x62, 0x54, 0xd2, 0x54, 0x42, 0x59, 0x21, 0x61, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, + 0x20, 0x00, 0x13, 0x04, 0x04, 0xea, 0x08, 0x40, 0x09, 0x46, 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, + 0x15, 0x04, 0x06, 0xc6, 0xef, 0xf0, 0xff, 0xf0, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x71, + 0xef, 0xf0, 0x7f, 0x89, 0x48, 0x44, 0x22, 0x44, 0xb2, 0x40, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x40, + 0x41, 0x01, 0x6f, 0xf0, 0x5f, 0x88, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x07, 0xea, 0x05, 0x46, + 0x93, 0x05, 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x6f, 0xf0, 0xbf, 0xed, 0x41, 0x11, 0xb7, 0x65, + 0x10, 0x00, 0x37, 0x05, 0x00, 0x04, 0x22, 0xc4, 0x13, 0x06, 0x00, 0x02, 0x93, 0x85, 0x45, 0x81, + 0x13, 0x05, 0x05, 0x02, 0x37, 0x34, 0x20, 0x00, 0x06, 0xc6, 0x13, 0x04, 0x04, 0xea, 0xef, 0xe0, + 0x4f, 0x81, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0xdf, 0x83, 0x93, 0x07, + 0xa0, 0x0a, 0x63, 0x1d, 0xf5, 0x00, 0x08, 0x40, 0x22, 0x44, 0xb2, 0x40, 0x05, 0x46, 0x93, 0x05, + 0x00, 0x02, 0x13, 0x05, 0x15, 0x04, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xe8, 0xb2, 0x40, 0x22, 0x44, + 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, 0xea, + 0x48, 0x44, 0x06, 0xc6, 0x7e, 0x05, 0x13, 0x65, 0xfa, 0x1d, 0x57, 0x77, 0xd2, 0x00, 0x60, 0x5b, + 0xed, 0x97, 0x49, 0x7b, 0x00, 0xd1, 0xb3, 0xa6, 0x21, 0x55, 0x28, 0x4b, 0xed, 0x61, 0x3d, 0x8d, + 0x64, 0x02, 0x6b, 0x24, 0x11, 0x2c, 0x09, 0x5f, 0xee, 0xe0, 0x4a, 0x05, 0x04, 0xef, 0xf0, 0xcf, + 0xff, 0x08, 0x40, 0x13, 0x06, 0x00, 0x02, 0x81, 0x45, 0x13, 0x05, 0x15, 0x04, 0xef, 0x00, 0x90, + 0x62, 0x08, 0x40, 0x09, 0x46, 0x81, 0x45, 0x13, 0x05, 0x15, 0x04, 0xef, 0xf0, 0xbf, 0xe4, 0x48, + 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x60, 0xef, 0xf0, 0x2f, 0xfd, 0x48, 0x44, 0x7e, 0x05, 0x13, + 0x65, 0x05, 0x71, 0xef, 0xf0, 0x6f, 0xfc, 0x01, 0x45, 0xef, 0xf0, 0x4f, 0xf5, 0x48, 0x44, 0x7e, + 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x4f, 0xfb, 0x48, 0x44, 0x7e, 0x05, 0x13, 0x65, 0x05, + 0x17, 0xef, 0xf0, 0x8f, 0xfa, 0xb2, 0x40, 0x22, 0x44, 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, 0x98, + 0xc7, 0x41, 0x01, 0x82, 0x80, 0x11, 0x65, 0xd5, 0xa1, 0x37, 0x35, 0x20, 0x00, 0x41, 0x11, 0x51, + 0x46, 0x81, 0x45, 0x13, 0x05, 0x05, 0xea, 0x06, 0xc6, 0xef, 0x00, 0xd0, 0x5b, 0xb7, 0x37, 0x20, + 0x00, 0x13, 0x07, 0x50, 0x05, 0x1d, 0x65, 0x23, 0xa6, 0xe7, 0xfa, 0x55, 0x29, 0xb2, 0x40, 0xb7, + 0x07, 0x00, 0x04, 0x05, 0x47, 0x98, 0xcb, 0x41, 0x01, 0x6f, 0xf0, 0xdf, 0xfc, 0x11, 0x65, 0x45, + 0xa1, 0x41, 0x11, 0x26, 0xc2, 0x4a, 0xc0, 0x06, 0xc6, 0x22, 0xc4, 0x2a, 0x89, 0xae, 0x84, 0x19, + 0xe1, 0xef, 0xb0, 0xdf, 0xfa, 0x95, 0x47, 0x13, 0x05, 0x50, 0x05, 0x63, 0xe6, 0x97, 0x02, 0x37, + 0x34, 0x20, 0x00, 0x13, 0x04, 0x04, 0xea, 0xb7, 0x65, 0x10, 0x00, 0x04, 0xc4, 0x93, 0x85, 0x85, + 0x83, 0x8a, 0x04, 0xfa, 0x85, 0xe2, 0xb8, 0x46, 0xe3, 0x24, 0x14, 0x4c, 0xa4, 0x05, 0x16, 0x8a, + 0x04, 0x3c, 0x95, 0xc0, 0x53, 0x65, 0x64, 0x1f, 0x9d, 0x09, 0x21, 0xdc, 0xa6, 0x2e, 0x1d, 0xc3, + 0xa0, 0xca, 0x39, 0xf1, 0xb8, 0x4b, 0x85, 0x47, 0xae, 0x94, 0x5c, 0xc0, 0x9c, 0x40, 0x23, 0x20, + 0x24, 0x01, 0x82, 0x97, 0x08, 0x48, 0x23, 0x22, 0x04, 0x00, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, + 0x02, 0x49, 0x41, 0x01, 0x82, 0x80, 0x05, 0xe1, 0x01, 0x11, 0x06, 0xce, 0x2a, 0xc6, 0xef, 0xb0, + 0x3f, 0xf6, 0xb7, 0x05, 0x00, 0x04, 0x32, 0x45, 0xf2, 0x40, 0x41, 0x46, 0x93, 0x85, 0x05, 0x08, + 0x05, 0x61, 0x6f, 0xd0, 0x7f, 0xe3, 0xb7, 0x05, 0x00, 0x04, 0x41, 0x46, 0x93, 0x85, 0x05, 0x08, + 0xcd, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x85, 0x47, 0x2a, 0x84, 0x63, 0xf4, 0xa7, 0x00, + 0xef, 0xb0, 0x1f, 0xf3, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0x07, 0xea, 0xc8, 0x47, 0x46, 0x04, + 0xb2, 0x40, 0x7e, 0x05, 0x49, 0x8c, 0x21, 0x65, 0x15, 0x05, 0x41, 0x8d, 0x22, 0x44, 0x09, 0x47, + 0xd8, 0xc3, 0x41, 0x01, 0x6f, 0xf0, 0x8f, 0xea, 0x39, 0x71, 0x22, 0xdc, 0x56, 0xd2, 0x5a, 0xd0, + 0x06, 0xde, 0x26, 0xda, 0x4a, 0xd8, 0x4e, 0xd6, 0x52, 0xd4, 0x5e, 0xce, 0x62, 0xcc, 0x66, 0xca, + 0x6a, 0xc8, 0x2a, 0x84, 0x2e, 0x8b, 0xb2, 0x8a, 0x99, 0xe1, 0xef, 0xb0, 0x7f, 0xee, 0xb7, 0x0b, + 0x00, 0x04, 0xb7, 0x39, 0x20, 0x00, 0x05, 0x6c, 0x81, 0x44, 0x01, 0x49, 0xc1, 0x4c, 0x93, 0x8b, + 0x0b, 0x02, 0x93, 0x89, 0x09, 0xea, 0x09, 0x0c, 0x37, 0x3d, 0x20, 0x00, 0xb3, 0x05, 0x9b, 0x00, + 0x63, 0xe0, 0x54, 0x03, 0xf2, 0x50, 0x62, 0x54, 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, 0xfa, 0x32, + 0x99, 0xeb, 0x80, 0x68, 0x41, 0x51, 0x0e, 0xfc, 0xd9, 0x46, 0x59, 0xb1, 0x28, 0x05, 0xe8, 0x4f, + 0xc9, 0x5a, 0xce, 0x7f, 0xaf, 0xea, 0x6b, 0x81, 0x9a, 0x27, 0x0a, 0x99, 0x00, 0x3b, 0x79, 0x90, + 0x4c, 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, 0xd2, 0x4c, 0x42, 0x4d, 0x21, + 0x61, 0x82, 0x80, 0x33, 0x8a, 0x9a, 0x40, 0x63, 0xd3, 0x4c, 0x01, 0x41, 0x4a, 0x4a, 0x85, 0x2e, + 0xc6, 0xef, 0xe0, 0xcf, 0x8d, 0xb2, 0x45, 0x13, 0x06, 0x3a, 0x00, 0x71, 0x9a, 0x5e, 0x85, 0xef, + 0xd0, 0xdf, 0xde, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x05, 0x07, 0xef, 0xf0, 0x2f, + 0xe1, 0x03, 0xa5, 0xc9, 0x00, 0x93, 0x17, 0x8a, 0x01, 0x7e, 0x05, 0x5d, 0x8d, 0x13, 0x65, 0x75, + 0x00, 0xef, 0xf0, 0xef, 0xdf, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x33, 0x65, 0x85, 0x01, 0xef, + 0xf0, 0x0f, 0xdf, 0x03, 0x27, 0xcd, 0xfa, 0x93, 0x07, 0x50, 0x05, 0x63, 0x19, 0xf7, 0x00, 0x19, + 0xc4, 0x22, 0x85, 0x52, 0x86, 0xca, 0x85, 0xef, 0xe0, 0x6f, 0x91, 0x41, 0x04, 0x93, 0x07, 0x00, + 0x07, 0x63, 0xe3, 0x27, 0x01, 0x41, 0x09, 0xc1, 0x04, 0x9d, 0xb7, 0x39, 0x71, 0x26, 0xda, 0x52, + 0xd4, 0x56, 0xd2, 0x06, 0xde, 0x22, 0xdc, 0x4a, 0xd8, 0x4e, 0xd6, 0x5a, 0xd0, 0x5e, 0xce, 0x62, + 0xcc, 0x66, 0xca, 0x6a, 0xc8, 0x6e, 0xc6, 0xaa, 0x8a, 0xae, 0x84, 0x32, 0x8a, 0x19, 0xe1, 0xef, + 0xb0, 0x5f, 0xe0, 0xb7, 0x39, 0x20, 0x00, 0x37, 0x0b, 0x02, 0x00, 0x85, 0x6b, 0x01, 0x49, 0x81, + 0x4d, 0x37, 0x3c, 0x20, 0x00, 0x41, 0x4d, 0x93, 0x89, 0x09, 0xea, 0x1d, 0x0b, 0x93, 0x8b, 0x0b, + 0x82, 0xb3, 0x8c, 0x2a, 0x01, 0x93, 0x07, 0xcc, 0xfa, 0xfa, 0xc2, 0x2e, 0x87, 0x0b, 0x0b, 0x24, + 0x00, 0xc1, 0xac, 0x51, 0x20, 0x80, 0x05, 0xd6, 0x0c, 0xc2, 0xad, 0x72, 0xb6, 0x28, 0x2f, 0x63, + 0x5d, 0x82, 0xe7, 0x66, 0xe4, 0x6e, 0x03, 0x2d, 0x74, 0xf2, 0x68, 0x4d, 0x63, 0x64, 0x49, 0x03, + 0xf2, 0x50, 0x62, 0x54, 0x13, 0x07, 0x50, 0x05, 0x98, 0xc3, 0xd2, 0x54, 0x42, 0x59, 0xb2, 0x59, + 0x22, 0x5a, 0x92, 0x5a, 0x02, 0x5b, 0xf2, 0x4b, 0x62, 0x4c, 0xd2, 0x4c, 0x42, 0x4d, 0xb2, 0x4d, + 0x21, 0x61, 0x82, 0x80, 0x33, 0x04, 0x2a, 0x41, 0x63, 0x73, 0x8d, 0x00, 0x41, 0x44, 0x6e, 0x85, + 0xef, 0xd0, 0x9f, 0xff, 0xb7, 0x37, 0x20, 0x00, 0x93, 0x87, 0xc7, 0xfa, 0x98, 0x43, 0x93, 0x07, + 0x50, 0x05, 0x63, 0x19, 0xf7, 0x00, 0x99, 0xc4, 0x26, 0x85, 0x22, 0x86, 0xee, 0x85, 0xef, 0xe0, + 0x8f, 0x89, 0xc1, 0x04, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x13, 0x65, 0x25, 0x00, 0xef, 0xf0, + 0x4f, 0xd1, 0x03, 0xa5, 0xc9, 0x00, 0x93, 0x17, 0x84, 0x01, 0x0d, 0x04, 0x7e, 0x05, 0x5d, 0x8d, + 0x33, 0x65, 0x65, 0x01, 0xef, 0xf0, 0xef, 0xcf, 0x03, 0xa5, 0xc9, 0x00, 0x7e, 0x05, 0x33, 0x65, + 0x75, 0x01, 0xef, 0xf0, 0x0f, 0xcf, 0xb7, 0x05, 0x00, 0x04, 0x13, 0x76, 0xc4, 0xff, 0x93, 0x85, + 0x05, 0x04, 0x66, 0x85, 0xef, 0xd0, 0xbf, 0xc2, 0x93, 0x07, 0x00, 0x06, 0x63, 0xe3, 0xb7, 0x01, + 0xc1, 0x0d, 0x41, 0x09, 0x81, 0xbf, 0x41, 0x11, 0x22, 0xc4, 0x06, 0xc6, 0x2a, 0x84, 0x19, 0xe1, + 0xef, 0xb0, 0x7f, 0xd2, 0x21, 0x45, 0xef, 0xf0, 0xcf, 0xcb, 0x93, 0x07, 0xa0, 0x0a, 0x63, 0x19, + 0xf5, 0x00, 0x22, 0x85, 0xef, 0xf0, 0x9f, 0xda, 0xb7, 0x37, 0x20, 0x00, 0x23, 0xa2, 0x07, 0xea, + 0xb2, 0x40, 0x22, 0x44, 0xfa, 0x5a, 0x1e, 0x5e, 0x99, 0x27, 0x7b, 0xcc, 0xef, 0x08, 0x03, 0x1f, + 0xf5, 0xb9, 0x29, 0x2d, 0x3c, 0x1f, 0x24, 0x11, 0x0c, 0xa8, 0x3d, 0x1b, 0x93, 0x36, 0xa8, 0x19, + 0xb0, 0xa3, 0x83, 0x8c, 0x8c, 0x40, 0x4e, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x23, + 0xa6, 0xa7, 0xfa, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0x13, 0x07, 0x60, 0x02, 0x98, 0xc7, 0x82, + 0x80, 0xb7, 0x07, 0x00, 0x04, 0x69, 0x47, 0x98, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x04, 0xc8, + 0x4b, 0x82, 0x80, 0x39, 0x71, 0x36, 0xd0, 0x3a, 0xce, 0x3e, 0xcc, 0x05, 0x47, 0xb7, 0x07, 0x00, + 0x04, 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x42, + 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xd8, 0xc7, 0xb7, 0x37, 0x20, + 0x00, 0x93, 0x87, 0x07, 0xea, 0xd8, 0x43, 0x89, 0x46, 0x7d, 0x17, 0x63, 0xfe, 0xe6, 0x02, 0x37, + 0x65, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x05, 0x81, 0xef, 0xd0, 0x4f, 0xd1, 0xef, 0xc0, 0xaf, + 0xd7, 0xf2, 0x50, 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, + 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, + 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, 0x30, 0x13, 0x07, 0xa0, 0x0a, 0x98, 0xcb, 0xd1, 0xbf, 0xb7, + 0x07, 0x01, 0x02, 0x88, 0xd7, 0xcc, 0xd7, 0x88, 0xdb, 0xcc, 0xdb, 0x88, 0xdf, 0xcc, 0xdf, 0x82, + 0x80, 0x01, 0x11, 0x26, 0xca, 0xb7, 0x04, 0x01, 0x02, 0x22, 0xcc, 0xc0, 0x40, 0xf5, 0x77, 0x93, + 0x87, 0xf7, 0xa5, 0x7d, 0x8c, 0x89, 0x67, 0x93, 0x87, 0x07, 0x1a, 0x06, 0xce, 0x4a, 0xc8, 0xfa, + 0xfe, 0x95, 0x0f, 0x28, 0x63, 0x49, 0xd5, 0x45, 0x85, 0x16, 0x0a, 0x6d, 0x94, 0x72, 0x31, 0x02, + 0x77, 0xd3, 0xe3, 0x69, 0x76, 0x9b, 0x8a, 0x1d, 0x56, 0xca, 0xb2, 0xc4, 0x35, 0xfb, 0xad, 0x0a, + 0x18, 0x4f, 0x4e, 0xc6, 0xc1, 0x8f, 0xaa, 0x89, 0xdc, 0xc0, 0x05, 0x45, 0x2e, 0x89, 0xef, 0xd0, + 0x1f, 0x8a, 0x93, 0x67, 0x04, 0x40, 0xdc, 0xc0, 0x05, 0x45, 0xef, 0xd0, 0x5f, 0x89, 0x85, 0x67, + 0x93, 0x87, 0x07, 0x40, 0x5d, 0x8c, 0xc0, 0xc0, 0xb7, 0x47, 0x00, 0x08, 0x23, 0xa4, 0x07, 0x00, + 0xb7, 0x57, 0x00, 0x08, 0x23, 0xa4, 0x07, 0x00, 0xf2, 0x40, 0x62, 0x44, 0x23, 0xa0, 0x34, 0x03, + 0x23, 0xa2, 0x24, 0x03, 0xb2, 0x49, 0xd2, 0x44, 0x42, 0x49, 0x05, 0x61, 0x82, 0x80, 0xb7, 0x07, + 0x01, 0x02, 0x88, 0x53, 0xcc, 0x53, 0x82, 0x80, 0xb7, 0x07, 0x01, 0x02, 0x88, 0x47, 0x21, 0x81, + 0x13, 0x75, 0xf5, 0x0f, 0x82, 0x80, 0x41, 0x11, 0x01, 0x45, 0x81, 0x45, 0x06, 0xc6, 0x22, 0xc4, + 0x26, 0xc2, 0xef, 0xf0, 0x1f, 0xf6, 0xef, 0xf0, 0x9f, 0xfd, 0xaa, 0x84, 0x2e, 0x84, 0x2a, 0x87, + 0xae, 0x86, 0x37, 0x66, 0x10, 0x00, 0xb7, 0x65, 0x10, 0x00, 0x37, 0x55, 0x10, 0x00, 0x93, 0x85, + 0x85, 0x86, 0x13, 0x05, 0x85, 0x77, 0x13, 0x06, 0x06, 0x85, 0xef, 0xd0, 0x0f, 0xba, 0xa2, 0x85, + 0x22, 0x44, 0xb2, 0x40, 0x26, 0x85, 0x92, 0x44, 0x41, 0x01, 0x6f, 0xf0, 0xbf, 0xf3, 0x39, 0x71, + 0x06, 0xde, 0x16, 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, + 0x3a, 0xce, 0x3e, 0xcc, 0x42, 0xca, 0x46, 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, + 0xef, 0xf0, 0x7f, 0xf9, 0xef, 0xc0, 0x6f, 0xc4, 0xf2, 0x50, 0xfa, 0x71, 0x27, 0xc3, 0xef, 0x04, + 0xe7, 0x59, 0xc3, 0x58, 0x9d, 0xc8, 0xa9, 0x3d, 0x90, 0x7b, 0xa6, 0x4a, 0x60, 0xf5, 0x50, 0x66, + 0x7e, 0xfb, 0xb1, 0x56, 0xd9, 0x55, 0x9c, 0x90, 0x86, 0x26, 0xbd, 0xf0, 0x4f, 0xe2, 0x52, 0x52, + 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, 0xe2, 0x47, 0x52, + 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, 0x73, 0x00, 0x20, + 0x30, 0xb7, 0x07, 0x00, 0x02, 0x0d, 0x47, 0xf8, 0xcb, 0x13, 0x07, 0x30, 0x03, 0xb8, 0xcf, 0x82, + 0x80, 0x37, 0x07, 0x00, 0x02, 0x5c, 0x47, 0xc9, 0x8f, 0x5c, 0xc7, 0x82, 0x80, 0xb7, 0x07, 0x00, + 0x02, 0xd8, 0x47, 0x13, 0x45, 0xf5, 0xff, 0x79, 0x8d, 0xc8, 0xc7, 0x82, 0x80, 0x37, 0x07, 0x00, + 0x02, 0x1c, 0x4f, 0xc9, 0x8f, 0x1c, 0xcf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0x98, 0x4f, 0x13, + 0x45, 0xf5, 0xff, 0x79, 0x8d, 0x88, 0xcf, 0x82, 0x80, 0xb7, 0x07, 0x00, 0x02, 0xc8, 0xcb, 0x82, + 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0x93, 0xe7, 0x47, 0x00, 0x1c, 0xc7, 0xb7, 0x07, 0x00, + 0x03, 0x94, 0x4b, 0x37, 0x37, 0x20, 0x00, 0x23, 0x28, 0xd7, 0xfa, 0x23, 0xa8, 0x07, 0x00, 0x82, + 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, 0x47, 0xb7, 0x06, 0x00, 0x03, 0xf9, 0x9b, 0x1c, 0xc7, 0x37, + 0x07, 0x08, 0x00, 0x9c, 0x46, 0xf9, 0x8f, 0xf5, 0xff, 0x82, 0x80, 0x37, 0x07, 0x00, 0x02, 0x1c, + 0x47, 0x93, 0xe7, 0x17, 0x00, 0x1c, 0xc7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x07, 0xfb, 0xb7, + 0x07, 0x00, 0x03, 0x98, 0xcb, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x47, 0xfb, 0x93, + 0x07, 0xa0, 0x0a, 0x63, 0x0b, 0xfa, 0x41, 0xa9, 0xc9, 0xc4, 0xef, 0x34, 0xb8, 0x57, 0x77, 0xf6, + 0x7a, 0x01, 0x96, 0x57, 0x12, 0x89, 0xae, 0xdf, 0xcf, 0xa0, 0x45, 0xe5, 0x03, 0x03, 0xa6, 0x58, + 0x8d, 0x23, 0x03, 0x08, 0xaa, 0x5d, 0xc8, 0x50, 0xf5, 0x00, 0xb7, 0x27, 0x03, 0x04, 0x9c, 0x47, + 0x13, 0x05, 0xa0, 0x0a, 0x85, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, 0x80, 0x13, 0x05, + 0x00, 0x10, 0x6f, 0xf0, 0x3f, 0xf4, 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2a, + 0xf7, 0xfa, 0x41, 0x11, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2c, 0xf7, 0xfa, 0x06, 0xc6, 0xef, 0xf0, + 0x1f, 0xfe, 0xb7, 0x27, 0x03, 0x04, 0x09, 0x47, 0xd8, 0xc3, 0x37, 0x17, 0x03, 0x04, 0xb7, 0x07, + 0x03, 0x04, 0x13, 0x07, 0x07, 0x80, 0x23, 0xa0, 0x07, 0x00, 0x91, 0x07, 0xe3, 0x9d, 0xe7, 0xfe, + 0xb7, 0x27, 0x03, 0x04, 0x0d, 0x47, 0xd8, 0xc7, 0x98, 0x47, 0x85, 0x47, 0x13, 0x05, 0xa0, 0x0a, + 0x63, 0x04, 0xf7, 0x00, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, 0x13, 0x05, + 0x00, 0x10, 0x6f, 0xf0, 0xff, 0xee, 0x93, 0x07, 0x50, 0x05, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2a, + 0xf7, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2c, 0xf7, 0xfa, 0xb7, 0x27, 0x03, 0x04, 0x05, 0x47, + 0xd8, 0xc3, 0x82, 0x80, 0xc2, 0x05, 0xc9, 0x8d, 0x93, 0xe5, 0x05, 0x10, 0xb7, 0x07, 0x03, 0x04, + 0x23, 0xa0, 0xb7, 0x10, 0x82, 0x80, 0xc2, 0x05, 0xc9, 0x8d, 0x11, 0x65, 0x13, 0x05, 0x05, 0x50, + 0xc9, 0x8d, 0xb7, 0x07, 0x03, 0x04, 0x23, 0xa0, 0xb7, 0x10, 0x82, 0x80, 0xb7, 0x17, 0x03, 0x04, + 0xbe, 0x95, 0x6f, 0xd0, 0x9f, 0x89, 0xb7, 0x07, 0x03, 0x04, 0x3e, 0x95, 0x6f, 0xd0, 0xff, 0x90, + 0xfa, 0xe4, 0xef, 0xa1, 0xf3, 0x44, 0x4e, 0xcc, 0x20, 0x2c, 0xbd, 0xfc, 0xe1, 0xaf, 0x97, 0x3d, + 0x6c, 0x2a, 0x94, 0x69, 0x54, 0xc5, 0x5d, 0x09, 0x72, 0x2a, 0x2e, 0x1f, 0x7f, 0xaf, 0x7c, 0x87, + 0x9d, 0xa0, 0x51, 0xb7, 0x95, 0x04, 0x00, 0x37, 0x55, 0x10, 0x00, 0x41, 0x11, 0x93, 0x85, 0x05, + 0x3e, 0x13, 0x05, 0xa5, 0xcb, 0x06, 0xc6, 0x22, 0xc4, 0xef, 0xd0, 0x6f, 0xe6, 0x93, 0x07, 0xa0, + 0x0a, 0x63, 0x0f, 0xf5, 0x00, 0x37, 0x65, 0x10, 0x00, 0x85, 0x45, 0x13, 0x05, 0x05, 0x87, 0xef, + 0xd0, 0xaf, 0x9f, 0x13, 0x05, 0x50, 0x05, 0xb2, 0x40, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, + 0x17, 0x03, 0x04, 0x83, 0xa7, 0x07, 0x10, 0x37, 0x34, 0x20, 0x00, 0x13, 0x04, 0x84, 0xfb, 0x93, + 0xf7, 0xf7, 0x0f, 0x81, 0xe7, 0x1c, 0x40, 0x63, 0x9d, 0xa7, 0x00, 0x37, 0x65, 0x10, 0x00, 0x8d, + 0x45, 0x13, 0x05, 0x05, 0x87, 0xef, 0xd0, 0x4f, 0x9c, 0x93, 0x07, 0xa0, 0x0a, 0x1c, 0xc0, 0xd1, + 0xb7, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa7, 0x47, 0xfb, 0x13, 0x84, 0x47, 0xfb, 0x63, 0x09, 0xa7, + 0x00, 0x37, 0x65, 0x10, 0x00, 0x89, 0x45, 0x13, 0x05, 0x05, 0x87, 0xef, 0xd0, 0xef, 0x99, 0x08, + 0x40, 0x5d, 0xb7, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x3f, 0xf4, 0xef, 0xf0, 0xff, 0xf0, 0xb2, + 0x40, 0x41, 0x01, 0x6f, 0xf0, 0x1f, 0xf6, 0xb7, 0x17, 0x03, 0x04, 0x03, 0xa5, 0x07, 0x10, 0x41, + 0x81, 0x82, 0x80, 0x41, 0x11, 0x3a, 0xc4, 0x37, 0x27, 0x03, 0x04, 0x3e, 0xc2, 0x1c, 0x47, 0x36, + 0xc6, 0x93, 0xf6, 0x27, 0x00, 0x89, 0xca, 0x89, 0x46, 0x14, 0xc7, 0x37, 0x37, 0x20, 0x00, 0x93, + 0x06, 0xa0, 0x0a, 0x23, 0x2a, 0xd7, 0xfa, 0x91, 0x8b, 0x99, 0xcf, 0xfa, 0x5a, 0x7f, 0x1b, 0x15, + 0x8c, 0x61, 0x80, 0xcd, 0x88, 0xec, 0xdf, 0x84, 0x87, 0x06, 0x2e, 0x9d, 0x5b, 0x1f, 0x07, 0x39, + 0xe8, 0x72, 0x20, 0x4e, 0xfe, 0xf8, 0x61, 0x27, 0xd1, 0x25, 0x7f, 0x97, 0x78, 0x52, 0xb7, 0x27, + 0x03, 0x04, 0x11, 0x47, 0x98, 0xc7, 0x93, 0x07, 0xa0, 0x0a, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2c, + 0xf7, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2a, 0xf7, 0xfa, 0xb2, 0x46, 0x22, 0x47, 0x92, 0x47, + 0x41, 0x01, 0x73, 0x00, 0x20, 0x30, 0x41, 0x11, 0x22, 0xc4, 0x37, 0x04, 0x00, 0x03, 0x1c, 0x48, + 0x06, 0xc6, 0xdd, 0x9b, 0x1c, 0xc8, 0xef, 0xe0, 0xcf, 0xd1, 0xb7, 0x07, 0x20, 0x00, 0x93, 0x87, + 0x07, 0x02, 0x5c, 0xcc, 0xb2, 0x40, 0x22, 0x44, 0xb7, 0x37, 0x20, 0x00, 0x23, 0x80, 0x07, 0xfc, + 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x2a, 0x84, 0x21, 0x45, 0x06, 0xc6, 0xef, 0xf0, + 0x5f, 0xd8, 0x13, 0x05, 0x00, 0x04, 0xef, 0xf0, 0x5f, 0xd4, 0x22, 0x04, 0x13, 0x64, 0x04, 0x03, + 0x37, 0x07, 0x00, 0x03, 0x40, 0xc3, 0xb2, 0x40, 0x22, 0x44, 0xc1, 0x67, 0x93, 0x87, 0xa7, 0xfa, + 0x1c, 0xcf, 0x41, 0x01, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xaa, 0x84, + 0x2e, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x5f, 0x83, 0x19, 0xe0, 0xef, 0xb0, 0xff, 0x82, 0x09, 0x45, + 0xef, 0xf0, 0x5f, 0xfb, 0x37, 0x07, 0x20, 0x00, 0xb7, 0x07, 0x00, 0x03, 0x13, 0x07, 0x07, 0x02, + 0xd8, 0xcf, 0x37, 0x37, 0x20, 0x00, 0x23, 0x2e, 0x97, 0xfa, 0x37, 0x37, 0x20, 0x00, 0x23, 0x22, + 0x87, 0xfc, 0xb2, 0x40, 0x22, 0x44, 0x05, 0x47, 0x98, 0xcb, 0x37, 0x07, 0x08, 0x00, 0x98, 0xc7, + 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0xfa, 0x45, 0xa5, 0x87, 0xb4, 0x72, 0x67, 0x47, 0xde, 0xe4, + 0x8a, 0xbd, 0x58, 0xcf, 0x34, 0xe7, 0xd3, 0x25, 0x4a, 0x5b, 0xda, 0x12, 0xaa, 0xe6, 0x6f, 0x35, + 0xc7, 0xd5, 0x42, 0xc5, 0xac, 0x08, 0xc2, 0x50, 0x53, 0xb7, 0x07, 0x00, 0x03, 0x9c, 0x47, 0x37, + 0x07, 0x04, 0x00, 0x13, 0x05, 0xa0, 0x0a, 0xf9, 0x8f, 0x99, 0xe3, 0x13, 0x05, 0x50, 0x05, 0x82, + 0x80, 0x37, 0x07, 0x00, 0x03, 0x5c, 0x53, 0x13, 0x05, 0x50, 0x05, 0x93, 0x96, 0x07, 0x01, 0xc1, + 0x82, 0xc1, 0x83, 0x63, 0x97, 0xf6, 0x00, 0x1c, 0x47, 0x91, 0x8b, 0x99, 0xe3, 0x13, 0x05, 0xa0, + 0x0a, 0x82, 0x80, 0x41, 0x11, 0x06, 0xc6, 0xef, 0xf0, 0x3f, 0xf1, 0x37, 0x07, 0x00, 0x03, 0x5c, + 0x47, 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc7, 0x5c, 0x47, 0x85, 0x8b, 0xf5, 0xff, 0xb2, 0x40, 0x41, + 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x83, 0xa7, 0x47, 0xfc, 0x95, 0xc3, 0x41, 0x11, 0x06, + 0xc6, 0xef, 0xf0, 0x9f, 0xee, 0xb7, 0x07, 0x00, 0x03, 0x98, 0x4b, 0xb2, 0x40, 0x13, 0x67, 0x87, + 0x00, 0x98, 0xcb, 0x37, 0x07, 0x08, 0x00, 0x98, 0xc7, 0x41, 0x01, 0x6f, 0xe0, 0xcf, 0xbd, 0x82, + 0x80, 0x37, 0x07, 0x00, 0x03, 0x1c, 0x4b, 0xf9, 0x9b, 0x1c, 0xcb, 0x82, 0x80, 0xb7, 0x06, 0x00, + 0x03, 0xdc, 0x42, 0x7d, 0x77, 0x13, 0x07, 0xf7, 0x0f, 0xf9, 0x8f, 0x05, 0x67, 0x22, 0x05, 0x13, + 0x07, 0x07, 0xf0, 0x79, 0x8d, 0x5d, 0x8d, 0xc8, 0xc2, 0x82, 0x80, 0x1d, 0x71, 0x3a, 0xda, 0x37, + 0x07, 0x00, 0x03, 0x3e, 0xd8, 0x1c, 0x47, 0x86, 0xce, 0x96, 0xcc, 0x9a, 0xca, 0x9e, 0xc8, 0xa2, + 0xc6, 0xa6, 0xc4, 0xaa, 0xc2, 0xae, 0xc0, 0x32, 0xde, 0x36, 0xdc, 0x42, 0xd6, 0x46, 0xd4, 0x4a, + 0xd2, 0xfa, 0x28, 0x33, 0xa4, 0xfd, 0xf5, 0x53, 0x0f, 0x3b, 0xa8, 0x00, 0x78, 0x43, 0x8a, 0x49, + 0xb3, 0x04, 0xe1, 0x30, 0xf4, 0x77, 0x1d, 0x9a, 0x9b, 0xe2, 0x56, 0x44, 0x1e, 0x2f, 0xec, 0x7f, + 0x07, 0x94, 0x28, 0x54, 0x4e, 0xd0, 0x72, 0xce, 0x76, 0xcc, 0x7a, 0xca, 0x7e, 0xc8, 0x85, 0x8b, + 0xa1, 0xc7, 0x04, 0x57, 0x11, 0x44, 0x37, 0x39, 0x20, 0x00, 0x83, 0x27, 0xc9, 0xfb, 0x13, 0xf5, + 0xf4, 0x0f, 0x7d, 0x14, 0x82, 0x97, 0xa1, 0x80, 0x6d, 0xf8, 0x36, 0x44, 0xf6, 0x40, 0xe6, 0x42, + 0x56, 0x43, 0xc6, 0x43, 0xa6, 0x44, 0x16, 0x45, 0x86, 0x45, 0x72, 0x56, 0xe2, 0x56, 0x52, 0x57, + 0xc2, 0x57, 0x32, 0x58, 0xa2, 0x58, 0x12, 0x59, 0x82, 0x59, 0x72, 0x4e, 0xe2, 0x4e, 0x52, 0x4f, + 0xc2, 0x4f, 0x25, 0x61, 0x73, 0x00, 0x20, 0x30, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xc7, 0x07, 0xfc, + 0x13, 0x84, 0x07, 0xfc, 0x05, 0xeb, 0xb7, 0x04, 0x00, 0x03, 0x37, 0x39, 0x20, 0x00, 0x93, 0x09, + 0xa0, 0x0a, 0x9c, 0x44, 0x91, 0x8b, 0xd5, 0xfb, 0x83, 0x27, 0x49, 0xfc, 0x68, 0x00, 0x82, 0x97, + 0x63, 0x0d, 0x35, 0x01, 0x85, 0x47, 0x23, 0x00, 0xf4, 0x00, 0xc1, 0x67, 0x93, 0x87, 0x07, 0x02, + 0xdc, 0xcc, 0x61, 0xbf, 0xef, 0xf0, 0x9f, 0xde, 0x49, 0xbf, 0xb2, 0x47, 0x9c, 0xd8, 0xd1, 0xbf, + 0xb7, 0x07, 0xf0, 0xfe, 0x37, 0x07, 0xf0, 0xff, 0x41, 0x11, 0xaa, 0x97, 0x7d, 0x17, 0x22, 0xc4, + 0x06, 0xc6, 0xf9, 0x8f, 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xb0, 0x6f, 0xe6, 0x5c, 0x40, 0xb2, 0x40, + 0x93, 0xe7, 0x17, 0x00, 0x5c, 0xc0, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0xf0, 0xfe, + 0x37, 0x07, 0xf0, 0xff, 0x41, 0x11, 0xaa, 0x97, 0x7d, 0x17, 0x22, 0xc4, 0xfa, 0x16, 0x7f, 0x2b, + 0x0e, 0x40, 0x4e, 0x3b, 0x27, 0xea, 0xba, 0x81, 0x47, 0x0f, 0x12, 0x02, 0x12, 0xfb, 0x7f, 0x19, + 0x60, 0x56, 0xce, 0x46, 0x2f, 0xe7, 0xfc, 0x70, 0x33, 0xf9, 0xab, 0x89, 0xbb, 0x00, 0x55, 0x06, + 0xc6, 0xf9, 0x8f, 0x2a, 0x84, 0x99, 0xc3, 0xef, 0xb0, 0xaf, 0xe3, 0x5c, 0x40, 0xb2, 0x40, 0xf9, + 0x9b, 0x5c, 0xc0, 0x22, 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x07, 0xf0, 0xfe, 0x37, 0x07, 0xf0, + 0xff, 0x01, 0x11, 0xaa, 0x97, 0x7d, 0x17, 0x22, 0xcc, 0x26, 0xca, 0x4a, 0xc8, 0x4e, 0xc6, 0x06, + 0xce, 0xf9, 0x8f, 0x2a, 0x84, 0x2e, 0x89, 0xb2, 0x84, 0xb6, 0x89, 0x99, 0xc3, 0xef, 0xb0, 0x4f, + 0xe0, 0x5c, 0x40, 0x13, 0xf6, 0x24, 0x00, 0xf2, 0x40, 0xf5, 0x9b, 0x5d, 0x8e, 0x50, 0xc0, 0x23, + 0x28, 0x34, 0x01, 0x23, 0x2a, 0x24, 0x01, 0x62, 0x44, 0xd2, 0x44, 0x42, 0x49, 0xb2, 0x49, 0x05, + 0x61, 0x82, 0x80, 0xb7, 0x07, 0xf0, 0xfe, 0x37, 0x07, 0xf0, 0xff, 0x41, 0x11, 0xaa, 0x97, 0x7d, + 0x17, 0x22, 0xc4, 0x26, 0xc2, 0x06, 0xc6, 0xf9, 0x8f, 0x2a, 0x84, 0xae, 0x84, 0x99, 0xc3, 0xef, + 0xb0, 0x2f, 0xdc, 0x5c, 0x44, 0xb2, 0x40, 0xb3, 0xe5, 0x97, 0x00, 0x4c, 0xc4, 0x22, 0x44, 0x92, + 0x44, 0x41, 0x01, 0x82, 0x80, 0xb7, 0x37, 0x20, 0x00, 0x03, 0xa5, 0x87, 0xfc, 0x82, 0x80, 0x39, + 0x71, 0x3a, 0xce, 0x37, 0x07, 0x10, 0x01, 0x3e, 0xcc, 0x1c, 0x47, 0x58, 0x47, 0x06, 0xde, 0x16, + 0xdc, 0x1a, 0xda, 0x1e, 0xd8, 0x2a, 0xd6, 0x2e, 0xd4, 0x32, 0xd2, 0x36, 0xd0, 0x42, 0xca, 0x46, + 0xc8, 0x72, 0xc6, 0x76, 0xc4, 0x7a, 0xc2, 0x7e, 0xc0, 0xf9, 0x8f, 0x91, 0xcf, 0xb7, 0x37, 0x20, + 0x00, 0x93, 0x87, 0x87, 0xfc, 0x98, 0x43, 0xfa, 0x80, 0xc5, 0x27, 0x65, 0x52, 0x9a, 0xb6, 0x48, + 0x63, 0x69, 0xd9, 0xfa, 0x17, 0x04, 0xd3, 0xaf, 0x19, 0xff, 0x99, 0x6c, 0x71, 0xe7, 0xed, 0x93, + 0xce, 0x5b, 0x34, 0x58, 0x95, 0xcf, 0xba, 0x61, 0xd8, 0x55, 0x05, 0x07, 0x98, 0xc3, 0xb7, 0x07, + 0x10, 0x01, 0x98, 0x47, 0x0d, 0x8b, 0x98, 0xc7, 0x19, 0xa8, 0xb7, 0x07, 0x20, 0x01, 0x98, 0x47, + 0xdc, 0x47, 0x7d, 0x8f, 0xb7, 0x07, 0x20, 0x01, 0x6d, 0xf7, 0xef, 0xb0, 0x9f, 0xe3, 0xf2, 0x50, + 0xe2, 0x52, 0x52, 0x53, 0xc2, 0x53, 0x32, 0x55, 0xa2, 0x55, 0x12, 0x56, 0x82, 0x56, 0x72, 0x47, + 0xe2, 0x47, 0x52, 0x48, 0xc2, 0x48, 0x32, 0x4e, 0xa2, 0x4e, 0x12, 0x4f, 0x82, 0x4f, 0x21, 0x61, + 0x73, 0x00, 0x20, 0x30, 0x1c, 0x41, 0x63, 0xf7, 0xb7, 0x00, 0x23, 0x80, 0xc7, 0x00, 0x1c, 0x41, + 0x85, 0x07, 0x1c, 0xc1, 0x82, 0x80, 0x1d, 0x71, 0xa2, 0xcc, 0xa6, 0xca, 0xca, 0xc8, 0x86, 0xce, + 0xce, 0xc6, 0xd2, 0xc4, 0xd6, 0xc2, 0xda, 0xc0, 0x5e, 0xde, 0x62, 0xdc, 0x66, 0xda, 0x6a, 0xd8, + 0x6e, 0xd6, 0x2a, 0xc6, 0x2e, 0x84, 0x32, 0x89, 0xb6, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x8f, 0xce, + 0x63, 0x14, 0x09, 0x00, 0xef, 0xb0, 0x0f, 0xce, 0x01, 0x45, 0x05, 0xc4, 0xb2, 0x4a, 0x7d, 0x14, + 0x25, 0x4a, 0x56, 0x94, 0x93, 0x0c, 0xc0, 0x06, 0x13, 0x0b, 0x30, 0x07, 0xa9, 0x4b, 0x1d, 0x4d, + 0x03, 0x46, 0x09, 0x00, 0x15, 0xe6, 0xb2, 0x47, 0x23, 0x80, 0x07, 0x00, 0x32, 0x45, 0x33, 0x05, + 0x55, 0x41, 0xf6, 0x40, 0x66, 0x44, 0xd6, 0x44, 0x46, 0x49, 0xb6, 0x49, 0x26, 0x4a, 0x96, 0x4a, + 0x06, 0x4b, 0xf2, 0x5b, 0x62, 0x5c, 0xd2, 0x5c, 0x42, 0x5d, 0xb2, 0x5d, 0x25, 0x61, 0x82, 0x80, + 0x93, 0x07, 0xfa, 0x57, 0xa3, 0xe6, 0x67, 0xbf, 0xcf, 0x59, 0x48, 0x20, 0x86, 0x3b, 0x75, 0xe9, + 0x40, 0xab, 0xf8, 0x87, 0xc1, 0x0a, 0x7b, 0x1d, 0xfa, 0x92, 0x25, 0x34, 0xfb, 0x33, 0x02, 0x24, + 0x6c, 0x82, 0xe8, 0xb0, 0x56, 0x50, 0x02, 0x63, 0x1f, 0xf6, 0x02, 0x93, 0x07, 0x19, 0x00, 0x83, + 0xc6, 0x07, 0x00, 0x3e, 0x89, 0x85, 0x07, 0x13, 0x87, 0x06, 0xfd, 0x13, 0x77, 0xf7, 0x0f, 0xe3, + 0x78, 0xea, 0xfe, 0x63, 0x93, 0x96, 0x01, 0x3e, 0x89, 0x03, 0x46, 0x09, 0x00, 0x63, 0x06, 0x66, + 0x0d, 0x63, 0x60, 0xcb, 0x02, 0x93, 0x07, 0x30, 0x06, 0x63, 0x05, 0xf6, 0x06, 0x93, 0x07, 0x40, + 0x06, 0x63, 0x0c, 0xf6, 0x06, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, 0xf2, 0xa6, 0x89, 0x95, + 0xa0, 0x93, 0x07, 0x50, 0x07, 0x63, 0x02, 0xf6, 0x06, 0x93, 0x07, 0x80, 0x07, 0xe3, 0x14, 0xf6, + 0xfe, 0x98, 0x40, 0x93, 0x89, 0x44, 0x00, 0x81, 0x46, 0x37, 0x06, 0x00, 0xf0, 0xb3, 0x75, 0xc7, + 0x00, 0xba, 0x84, 0x36, 0x8c, 0x12, 0x07, 0x85, 0x06, 0x89, 0xe5, 0xe3, 0x99, 0xa6, 0xff, 0x1d, + 0x4c, 0xba, 0x84, 0xa1, 0x4d, 0x13, 0xd7, 0xc4, 0x01, 0x63, 0x74, 0xea, 0x08, 0x13, 0x06, 0x77, + 0x05, 0xa2, 0x85, 0x68, 0x00, 0x05, 0x0c, 0xef, 0xf0, 0x1f, 0xee, 0x92, 0x04, 0xe3, 0x14, 0xbc, + 0xff, 0x09, 0xa8, 0x03, 0xc6, 0x04, 0x00, 0xa2, 0x85, 0x68, 0x00, 0x93, 0x89, 0x44, 0x00, 0xef, + 0xf0, 0x9f, 0xec, 0x05, 0x09, 0xce, 0x84, 0x31, 0xbf, 0x5c, 0x08, 0x98, 0x40, 0x93, 0x89, 0x44, + 0x00, 0x3e, 0x8c, 0x81, 0x44, 0xb3, 0x76, 0x77, 0x03, 0x85, 0x04, 0x85, 0x07, 0x93, 0x86, 0x06, + 0x03, 0xa3, 0x8f, 0xd7, 0xfe, 0xba, 0x86, 0x33, 0x57, 0x77, 0x03, 0xe3, 0x65, 0xfa, 0x2c, 0x3a, + 0xa7, 0xa5, 0x6c, 0x92, 0x08, 0x82, 0x4e, 0x2d, 0xa7, 0x53, 0x29, 0xd2, 0xc8, 0xb6, 0x7d, 0xee, + 0x93, 0x6b, 0xd9, 0xa9, 0xd2, 0x21, 0x11, 0x35, 0xeb, 0x5a, 0x62, 0x3f, 0x68, 0xff, 0x88, 0x57, + 0xda, 0xfe, 0xfd, 0x5d, 0xfd, 0x14, 0xe3, 0x88, 0xb4, 0xfd, 0xb3, 0x07, 0x9c, 0x00, 0x03, 0xc6, + 0x07, 0x00, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0x5f, 0xe8, 0xed, 0xb7, 0x93, 0x89, 0x44, 0x00, + 0x84, 0x40, 0x03, 0xc6, 0x04, 0x00, 0x45, 0xda, 0xa2, 0x85, 0x68, 0x00, 0xef, 0xf0, 0xff, 0xe6, + 0x85, 0x04, 0xc5, 0xbf, 0x13, 0x06, 0x07, 0x03, 0xb5, 0xbf, 0x41, 0x11, 0x26, 0xc2, 0xb7, 0x34, + 0x20, 0x00, 0x2a, 0x86, 0xae, 0x86, 0x13, 0x85, 0x44, 0xeb, 0x93, 0x05, 0x00, 0x08, 0x06, 0xc6, + 0x22, 0xc4, 0xef, 0xf0, 0xbf, 0xe5, 0x2a, 0x84, 0x13, 0x85, 0x44, 0xeb, 0xef, 0xd0, 0x6f, 0x8d, + 0xb2, 0x40, 0x22, 0x85, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x39, 0x71, 0x26, 0xca, + 0xb7, 0x34, 0x20, 0x00, 0x2e, 0xd2, 0x32, 0xd4, 0x36, 0xd6, 0x2a, 0x86, 0x54, 0x10, 0x93, 0x05, + 0x00, 0x08, 0x13, 0x85, 0x44, 0xeb, 0x06, 0xce, 0x22, 0xcc, 0x3a, 0xd8, 0x3e, 0xda, 0x42, 0xdc, + 0x46, 0xde, 0x36, 0xc6, 0xef, 0xf0, 0x9f, 0xe1, 0x2a, 0x84, 0x13, 0x85, 0x44, 0xeb, 0xef, 0xd0, + 0x4f, 0x89, 0xf2, 0x40, 0x22, 0x85, 0x62, 0x44, 0xd2, 0x44, 0x21, 0x61, 0x82, 0x80, 0x22, 0x05, + 0x61, 0x77, 0x2d, 0x8d, 0xa1, 0x47, 0x15, 0x07, 0x93, 0x16, 0x05, 0x01, 0x06, 0x05, 0x42, 0x05, + 0xc1, 0x86, 0x41, 0x81, 0x63, 0xd5, 0x06, 0x00, 0x39, 0x8d, 0x42, 0x05, 0x41, 0x81, 0xfd, 0x17, + 0xe5, 0xf7, 0x82, 0x80, 0x41, 0x11, 0x22, 0xc4, 0xfa, 0x9b, 0x16, 0xee, 0x22, 0x46, 0x97, 0x65, + 0x71, 0xa8, 0xe4, 0xd9, 0x16, 0xd9, 0x0e, 0xee, 0x9f, 0x36, 0x38, 0x18, 0xe1, 0xff, 0x86, 0xc3, + 0xb3, 0x78, 0x05, 0x94, 0x34, 0x32, 0xc0, 0x99, 0x75, 0x60, 0x58, 0x26, 0xc2, 0x06, 0xc6, 0x2a, + 0x84, 0xae, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x8f, 0xad, 0xa2, 0x94, 0x01, 0x45, 0x63, 0x17, 0x94, + 0x00, 0xb2, 0x40, 0x22, 0x44, 0x92, 0x44, 0x41, 0x01, 0x82, 0x80, 0x05, 0x04, 0xaa, 0x85, 0x03, + 0x45, 0xf4, 0xff, 0xef, 0xf0, 0xff, 0xfa, 0xdd, 0xb7, 0x41, 0x11, 0x22, 0xc4, 0x26, 0xc2, 0x06, + 0xc6, 0x2a, 0x84, 0xae, 0x84, 0x19, 0xe1, 0xef, 0xb0, 0x6f, 0xaa, 0xb7, 0x86, 0xb8, 0xed, 0x01, + 0x47, 0xfd, 0x57, 0x93, 0x86, 0x06, 0x32, 0x63, 0x19, 0x97, 0x00, 0xb2, 0x40, 0x22, 0x44, 0x92, + 0x44, 0x13, 0xc5, 0xf7, 0xff, 0x41, 0x01, 0x82, 0x80, 0x33, 0x06, 0xe4, 0x00, 0x03, 0x46, 0x06, + 0x00, 0xb1, 0x8f, 0x21, 0x46, 0x93, 0xd5, 0x17, 0x00, 0x85, 0x8b, 0x91, 0xc3, 0xb6, 0x87, 0x7d, + 0x16, 0xad, 0x8f, 0x6d, 0xfa, 0x05, 0x07, 0xc1, 0xbf, 0x2a, 0x83, 0x09, 0xca, 0x83, 0x83, 0x05, + 0x00, 0x23, 0x00, 0x73, 0x00, 0x7d, 0x16, 0x05, 0x03, 0x85, 0x05, 0x6d, 0xfa, 0x82, 0x80, 0x15, + 0xc2, 0x2a, 0x83, 0x85, 0x46, 0x63, 0x67, 0xb5, 0x00, 0xfd, 0x56, 0x13, 0x07, 0xf6, 0xff, 0x3a, + 0x93, 0xba, 0x95, 0x83, 0x83, 0x05, 0x00, 0x23, 0x00, 0x73, 0x00, 0x7d, 0x16, 0x36, 0x93, 0xb6, + 0x95, 0x6d, 0xfa, 0x82, 0x80, 0x2a, 0x83, 0x11, 0xc6, 0x23, 0x00, 0xb3, 0x00, 0x7d, 0x16, 0x05, + 0x03, 0x65, 0xfe, 0x82, 0x80, 0x00, 0x00, 0x63, 0x6f, 0x64, 0x65, 0x3a, 0x20, 0x25, 0x78, 0x00, + 0x00, 0x00, 0x00, 0xfa, 0x17, 0x74, 0x9d, 0x62, 0x9b, 0x6c, 0x6d, 0x2e, 0x1a, 0xcc, 0xee, 0xec, + 0x8b, 0x77, 0xc3, 0xae, 0xc9, 0xf5, 0xaa, 0x6a, 0xa4, 0x07, 0xad, 0xc7, 0x6e, 0x25, 0x92, 0x33, + 0x6f, 0x1d, 0xc8, 0x00, 0x38, 0x59, 0x53, 0x45, 0x43, 0x43, 0x48, 0x4e, 0x4c, 0x00, 0x4d, 0x43, + 0x4e, 0x54, 0x00, 0x00, 0x00, 0x00, 0x65, 0x6e, 0x61, 0x62, 0x6c, 0x65, 0x64, 0x20, 0x25, 0x64, + 0x00, 0x00, 0x4d, 0x41, 0x49, 0x4e, 0x00, 0x00, 0x00, 0x00, 0x54, 0x58, 0x3a, 0x20, 0x25, 0x64, + 0x2f, 0x25, 0x64, 0x2c, 0x20, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x43, 0x4d, 0x44, 0x33, 0x00, 0x00, + 0x00, 0x00, 0x49, 0x00, 0x00, 0x00, 0x52, 0x58, 0x3a, 0x20, 0x63, 0x6d, 0x64, 0x3d, 0x30, 0x78, + 0x25, 0x30, 0x32, 0x78, 0x2c, 0x6c, 0x3d, 0x25, 0x64, 0x00, 0x6c, 0x65, 0x6e, 0x20, 0x25, 0x64, + 0x2f, 0x25, 0x64, 0x00, 0x00, 0x00, 0x72, 0x73, 0x70, 0x3d, 0x25, 0x78, 0x00, 0x00, 0x73, 0x74, + 0x61, 0x72, 0x74, 0x2c, 0x20, 0x76, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x00, 0x50, 0x52, + 0x4f, 0x56, 0x49, 0x53, 0x49, 0x4f, 0x4e, 0x20, 0x4f, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x4e, 0x3a, + 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x43, 0x50, 0x42, 0x3a, 0x20, 0x25, 0x64, 0x00, 0x4c, 0x33, + 0x20, 0x63, 0x6d, 0x64, 0x20, 0x25, 0x64, 0x3a, 0x20, 0x25, 0x78, 0x2c, 0x20, 0x6c, 0x65, 0x6e, + 0x3a, 0x20, 0x25, 0x64, 0x00, 0x00, 0x4c, 0x33, 0x20, 0x61, 0x63, 0x63, 0x65, 0x73, 0x73, 0x20, + 0x66, 0x61, 0x69, 0x6c, 0x65, 0x64, 0x2c, 0x20, 0x63, 0x6d, 0x64, 0x3a, 0x20, 0x25, 0x64, 0x2c, + 0x20, 0x6c, 0x65, 0x6e, 0x3a, 0x20, 0x25, 0x64, 0x20, 0x00, 0x73, 0x65, 0x6e, 0x74, 0xfa, 0x1e, + 0x40, 0x64, 0x11, 0xd7, 0xae, 0x2d, 0x74, 0x47, 0x30, 0x45, 0x12, 0x4c, 0x2d, 0x42, 0xf6, 0xc1, + 0xd8, 0xf7, 0x9e, 0xee, 0x47, 0xe2, 0x78, 0xaf, 0x7e, 0x77, 0x4c, 0xb6, 0xf4, 0x88, 0xf3, 0x10, + 0x5a, 0x00, 0x00, 0x00, 0x00, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x20, 0x73, 0x6c, 0x65, 0x65, 0x70, + 0x00, 0x77, 0x61, 0x6b, 0x65, 0x75, 0x70, 0x00, 0x00, 0x9a, 0x19, 0x10, 0x00, 0xd8, 0x19, 0x10, + 0x00, 0x04, 0x1a, 0x10, 0x00, 0x34, 0x1a, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, + 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, + 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, + 0x00, 0xce, 0x14, 0x10, 0x00, 0xce, 0x14, 0x10, 0x00, 0x56, 0x1a, 0x10, 0x00, 0xb0, 0x1a, 0x10, + 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 0x00, 0x06, 0x01, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x1f, 0x00, 0x06, 0x02, 0x00, 0x05, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x1c, 0x00, 0x06, 0x03, 0x10, 0x08, 0x00, 0x00, 0x18, 0x00, 0x00, 0x40, 0x1f, 0x00, + 0x06, 0x06, 0x10, 0x08, 0x00, 0x04, 0x18, 0x00, 0x00, 0x60, 0x1f, 0x00, 0x06, 0x04, 0x00, 0x09, + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x06, 0x05, 0x05, 0x7f, 0x07, 0x01, 0x08, 0x18, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xf0, 0x01, 0x10, 0x10, 0x00, 0x04, 0x02, 0x11, 0x00, 0x44, + 0x02, 0x12, 0x00, 0x84, 0x02, 0x20, 0x90, 0x01, 0x03, 0x21, 0x80, 0x42, 0x03, 0x22, 0xf0, 0x01, + 0x03, 0x30, 0x80, 0x02, 0x04, 0x31, 0x80, 0x42, 0x04, 0xfa, 0xe0, 0xa5, 0xe1, 0x65, 0x2d, 0xf8, + 0x4c, 0xe4, 0x45, 0xd8, 0x83, 0x04, 0xcb, 0x79, 0xbc, 0xd8, 0x9d, 0x20, 0x87, 0xd3, 0x32, 0x1e, + 0xdc, 0x39, 0x04, 0xee, 0x7d, 0xc7, 0xca, 0x24, 0xb1, 0x0c, 0xe8, 0x5a, 0x40, 0x70, 0x04, 0x11, + 0x41, 0x70, 0x44, 0x11, 0x42, 0x70, 0x84, 0x11, 0x50, 0xf0, 0x01, 0x12, 0x60, 0x32, 0x04, 0x13, + 0x61, 0x32, 0x44, 0x13, 0x62, 0x32, 0x84, 0x13, 0x63, 0x32, 0xc4, 0x13, 0x70, 0x32, 0x04, 0x14, + 0x71, 0x32, 0x44, 0x14, 0x80, 0x20, 0x04, 0x15, 0x81, 0x20, 0x84, 0x15, 0x82, 0x20, 0x44, 0x15, + 0x90, 0x51, 0x04, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x0f, 0x00, + 0x14, 0x04, 0x04, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x23, 0x20, 0x25, 0x6c, 0x75, 0x20, 0x00, 0x00, 0x25, 0x73, 0x28, 0x25, 0x73, 0x29, 0x3a, 0x20, + 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x45, 0x00, 0x00, 0x00, 0x4d, 0x53, 0x47, 0x00, + 0x43, 0x52, 0x43, 0x20, 0x72, 0x78, 0x3a, 0x20, 0x25, 0x30, 0x34, 0x78, 0x2c, 0x20, 0x63, 0x61, + 0x6c, 0x63, 0x3a, 0x20, 0x25, 0x30, 0x34, 0x78, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, + 0x40, 0x20, 0x10, 0x00, 0x60, 0x20, 0x10, 0x00, 0xb2, 0x20, 0x10, 0x00, 0x14, 0x21, 0x10, 0x00, + 0x1e, 0x21, 0x10, 0x00, 0x4f, 0x53, 0x00, 0x00, 0x63, 0x6f, 0x6e, 0x64, 0x3a, 0x20, 0x25, 0x78, + 0x00, 0x00, 0x00, 0x00, 0x43, 0x50, 0x42, 0x20, 0x49, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, + 0x74, 0x20, 0x21, 0x00, 0x43, 0x50, 0x42, 0x00, 0x57, 0x00, 0x00, 0x00, 0x46, 0x53, 0x53, 0x00, + 0x49, 0x52, 0x51, 0x00, 0xde, 0x1c, 0xcd, 0x5d, 0xca, 0x91, 0x43, 0xe8, 0x98, 0x94, 0x67, 0x9b, + 0xb6, 0x1c, 0xe9, 0xfd, 0xe2, 0x0f, 0x0b, 0x24, 0xb3, 0xd3, 0x05, 0x80, 0x73, 0xb5, 0x2c, 0x0c, + 0x64, 0x8e, 0xc8, 0x8a, 0x9d, 0xc0, 0x5b, 0x53, 0x54, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x4b, + 0x44, 0x42, 0x00, 0x73, 0x74, 0x3a, 0x20, 0x25, 0x78, 0x00, 0x00, 0x4d, 0x41, 0x44, 0x00, 0x4f, + 0x54, 0x50, 0x00, 0x0c, 0x18, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00, 0x10, + 0x18, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x05, 0x0a, 0x0a, 0x0a, 0x14, 0x18, 0x00, 0x00, 0x28, + 0x00, 0x00, 0x00, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x53, 0x43, 0x42, 0x00, 0x4e, 0x6f, 0x69, 0x73, 0x65, + 0x5f, 0x4b, 0x4b, 0x31, 0x5f, 0x32, 0x35, 0x35, 0x31, 0x39, 0x5f, 0x41, 0x45, 0x53, 0x47, 0x43, + 0x4d, 0x5f, 0x53, 0x48, 0x41, 0x32, 0x35, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, + 0x40, 0x10, 0x00, 0x74, 0x46, 0x10, 0x00, 0x5e, 0x46, 0x10, 0x00, 0x22, 0x46, 0x10, 0x00, 0x08, + 0x3f, 0x10, 0x00, 0xcc, 0x46, 0x10, 0x00, 0x41, 0x4c, 0x41, 0x52, 0x4d, 0x20, 0x43, 0x48, 0x41, + 0x4e, 0x4e, 0x45, 0x4c, 0x53, 0x3a, 0x20, 0x25, 0x78, 0x20, 0x25, 0x78, 0x00, 0x00, 0x00, 0x53, + 0x43, 0x4e, 0x54, 0x52, 0x00, 0x00, 0x00, 0x53, 0x50, 0x45, 0x43, 0x54, 0x00, 0x00, 0x00, 0xc3, + 0x14, 0x13, 0x00, 0x72, 0xc3, 0xef, 0xde, 0x86, 0x6b, 0xc7, 0x13, 0x5f, 0xcb, 0x08, 0xbd, 0xb0, + 0x14, 0xfe, 0xc5, 0x27, 0x42, 0x86, 0x8d, 0x6c, 0xcc, 0xa0, 0xec, 0x25, 0x0e, 0x9f, 0x00, 0xe5, + 0x55, 0x81, 0xd2, 0xa5, 0xb0, 0x03, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xf4, 0x57, 0xf8, 0xba, 0x9d, 0x08, 0x11, 0x92, 0x11, + 0x8c, 0xd8, 0x04, 0xe7, 0x4a, 0xdf, 0x14, 0x73, 0x56, 0x8a, 0x35, 0x53, 0x18, 0xbc, 0x23, 0xb8, + 0xbb, 0xb6, 0x0d, 0x70, 0xff, 0x6a, 0x63, 0xd8, 0x02, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x7c, 0x58, 0x00, 0x00, + 0x61, 0xcd, 0x51, 0x19, 0x7d, 0xba, 0xf5, 0x9f, 0x7f, 0x51, 0x7a, 0x24, 0x53, 0x73, 0x22, 0xdb, + 0x05, 0x52, 0x40, 0x98, 0xbd, 0x5c, 0xbe, 0x7a, 0x8a, 0xe3, 0x67, 0x13, 0x46, 0x82, 0xf1, 0x09, + 0x46, 0x0b, 0x4d, 0xb3, 0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; \ No newline at end of file diff --git a/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_2_0_0/fw_SPECT.h b/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_2_0_0/fw_SPECT.h index c71ac85b9..3dc3bdcae 100644 --- a/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_2_0_0/fw_SPECT.h +++ b/TROPIC01_fw_update_files/boot_v_2_0_1/fw_v_2_0_0/fw_SPECT.h @@ -5,623 +5,739 @@ /** * @brief SPECT firmware version spect_app-v1.0.0_signed_chunks.bin for bootloader v2.0.1 */ -const uint8_t fw_SPECT[] - = {0x68, 0xd7, 0x2a, 0x0a, 0xb1, 0x9a, 0x44, 0xee, 0xf3, 0x8b, 0xd7, 0xb4, 0xdb, 0xe1, 0x13, 0x4e, 0x87, 0xda, 0x13, - 0xf2, 0x47, 0x06, 0x5a, 0x5a, 0x46, 0x52, 0x82, 0xd9, 0x06, 0x4b, 0x45, 0x0c, 0x87, 0x67, 0x91, 0xc0, 0x89, 0xa0, - 0xbc, 0xa7, 0x2f, 0x53, 0x6c, 0x82, 0xd1, 0x0c, 0xbb, 0x35, 0x19, 0x75, 0x37, 0x00, 0xdd, 0xf1, 0x45, 0xa9, 0xdc, - 0x18, 0xb3, 0x6e, 0x48, 0xa2, 0xc0, 0x98, 0x0a, 0x01, 0xa0, 0x7b, 0x57, 0xe4, 0x44, 0x74, 0x24, 0x7f, 0xf7, 0xde, - 0xec, 0x32, 0xd7, 0x0b, 0xfd, 0xef, 0x57, 0x97, 0xb9, 0x84, 0xe8, 0xe3, 0x41, 0xed, 0x3f, 0xfc, 0x63, 0x54, 0xa4, - 0x52, 0xa2, 0x02, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x62, 0xba, 0x4b, 0x73, 0x36, 0x91, 0x21, 0x1d, 0xeb, - 0x69, 0xfb, 0xb6, 0x6b, 0xa7, 0x0a, 0xf3, 0x26, 0xef, 0x36, 0x08, 0xd9, 0xb1, 0xdd, 0xf8, 0xb0, 0x4a, 0x65, 0xc0, - 0xdb, 0x21, 0xcf, 0x36, 0xe3, 0x00, 0x00, 0x10, 0xa5, 0xaf, 0xbb, 0xc2, 0xd2, 0x77, 0x19, 0xce, 0xe4, 0x30, 0x16, - 0xf9, 0x4a, 0x54, 0x04, 0x9d, 0xc1, 0x73, 0x21, 0x2c, 0x75, 0x19, 0xd9, 0x0a, 0x49, 0x73, 0x2b, 0x0b, 0x10, 0xdb, - 0x5c, 0x54, 0x93, 0xe8, 0x13, 0xf3, 0x01, 0xe5, 0x70, 0x69, 0x6e, 0x58, 0x4e, 0xb2, 0x56, 0xfb, 0x09, 0xaf, 0x9a, - 0x11, 0x0f, 0x6a, 0xa7, 0x27, 0x91, 0x25, 0x53, 0xeb, 0xa4, 0xc7, 0xa4, 0x48, 0x0a, 0xfa, 0x50, 0xd1, 0xc2, 0xa2, - 0xfd, 0x75, 0x8b, 0x0f, 0xf6, 0xfe, 0x2a, 0x27, 0x13, 0x81, 0xae, 0x66, 0xd9, 0x5f, 0x44, 0xb2, 0x2a, 0xc3, 0xee, - 0x40, 0x20, 0xfa, 0x67, 0x87, 0x40, 0xa5, 0x2a, 0x0d, 0x00, 0x04, 0x00, 0x00, 0x7e, 0xa3, 0xe4, 0xa3, 0x00, 0x82, - 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, 0x40, 0xa2, 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0x82, 0x62, 0xf0, 0x10, 0x88, - 0xa2, 0x20, 0x33, 0x4a, 0xc5, 0x00, 0x10, 0x40, 0x28, 0x2c, 0xa3, 0x00, 0x08, 0x60, 0x40, 0x40, 0x28, 0x4c, 0x80, - 0x00, 0x88, 0x10, 0x40, 0x40, 0xa8, 0x84, 0x80, 0x00, 0x08, 0x40, 0x40, 0x40, 0xa8, 0xb8, 0x80, 0x00, 0x08, 0x70, - 0x40, 0x40, 0xa8, 0x20, 0x81, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0x04, 0xa4, 0x00, 0x82, 0xf4, 0x50, 0x8a, 0x24, - 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x60, 0x10, 0x40, 0x28, 0x1c, 0x9f, 0x00, 0x08, 0x61, 0x10, 0x40, - 0xa8, 0x1c, 0x9f, 0x00, 0x08, 0x62, 0x10, 0x40, 0xa8, 0xa4, 0x9f, 0x00, 0x08, 0x63, 0x10, 0x40, 0x28, 0xb0, 0xa0, - 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0xf3, 0x50, 0x8a, 0xa4, 0x00, 0x50, 0x0a, 0xf3, 0x00, - 0x05, 0x4a, 0x49, 0x11, 0x10, 0x40, 0x28, 0x60, 0xa2, 0x00, 0x08, 0x12, 0x10, 0x40, 0x28, 0x9c, 0xa2, 0x00, 0x08, - 0x13, 0x10, 0x40, 0xa8, 0xbc, 0xa2, 0x00, 0x88, 0x14, 0x10, 0x40, 0x28, 0xe0, 0xa2, 0x00, 0x88, 0x40, 0x81, 0x00, - 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x04, 0xa4, 0x00, 0x82, 0xf2, 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, - 0x4a, 0x49, 0x41, 0x10, 0x40, 0x28, 0x94, 0x8f, 0x00, 0x88, 0x42, 0x10, 0x40, 0x28, 0xac, 0x90, 0x00, 0x88, 0xfa, - 0xf0, 0x16, 0x3b, 0xa9, 0x5c, 0xdb, 0xb6, 0xb6, 0x81, 0xdf, 0x01, 0x03, 0x10, 0x82, 0xe9, 0xaa, 0x95, 0x82, 0xee, - 0xe8, 0xbc, 0x80, 0xc4, 0x55, 0x77, 0xb0, 0x3d, 0x6c, 0x8f, 0x56, 0x2b, 0x2d, 0xd8, 0x04, 0x43, 0x10, 0x40, 0xa8, - 0xd4, 0x90, 0x00, 0x88, 0x44, 0x10, 0x40, 0x28, 0x04, 0x91, 0x00, 0x88, 0x45, 0x10, 0x40, 0xa8, 0xfc, 0x91, 0x00, - 0x08, 0x46, 0x10, 0x40, 0xa8, 0xa0, 0x92, 0x00, 0x08, 0x47, 0x10, 0x40, 0x28, 0xf4, 0x92, 0x00, 0x88, 0x48, 0x10, - 0x40, 0x28, 0x30, 0x93, 0x00, 0x88, 0x49, 0x10, 0x40, 0xa8, 0x48, 0x93, 0x00, 0x88, 0x4a, 0x10, 0x40, 0xa8, 0x18, - 0x94, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x04, 0xa4, 0x00, 0x82, 0xf1, 0x50, 0x8a, 0x24, - 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x70, 0x10, 0x40, 0xa8, 0x1c, 0xa1, 0x00, 0x88, 0x40, 0x81, 0x00, - 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x02, 0x00, 0x44, 0x23, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x44, 0x69, 0x00, 0x00, - 0x42, 0xa3, 0xf3, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x40, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xf3, 0x00, - 0x00, 0x00, 0x84, 0x50, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x01, 0x40, 0xc5, - 0x00, 0x00, 0x00, 0xf5, 0x00, 0x00, 0x00, 0xf5, 0xff, 0x00, 0x42, 0xa3, 0x00, 0x10, 0x02, 0xf3, 0xff, 0x10, 0x82, - 0xa4, 0x80, 0x00, 0x80, 0xe2, 0x00, 0x00, 0x00, 0x84, 0xa8, 0xa4, 0x00, 0x18, 0x00, 0x10, 0x02, 0xf3, 0x00, 0x10, - 0x02, 0xf3, 0x80, 0x00, 0x40, 0xe2, 0x00, 0x11, 0x40, 0x49, 0x00, 0x00, 0xc0, 0x93, 0x80, 0x10, 0x84, 0xff, 0x80, - 0x20, 0x86, 0x7f, 0xfa, 0x8a, 0x55, 0xdc, 0xbc, 0xbd, 0x1e, 0x59, 0xf0, 0x49, 0xb7, 0x8e, 0x78, 0xcf, 0xaf, 0xf0, - 0x4b, 0xa0, 0xf9, 0xd1, 0xd8, 0x1b, 0x2e, 0x08, 0x35, 0x16, 0x13, 0x73, 0x74, 0xd2, 0x2c, 0x15, 0xd6, 0xb0, 0x05, - 0x80, 0x31, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x80, 0x41, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, - 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, - 0x88, 0xff, 0x06, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, - 0xe0, 0x7d, 0xa4, 0xdc, 0x81, 0x00, 0x8a, 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x0f, 0x00, 0x7c, 0x23, - 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0xfc, 0x81, 0x00, - 0x0a, 0x80, 0x42, 0x8c, 0xff, 0x00, 0x63, 0x88, 0xff, 0x3f, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, - 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0x1c, 0x82, 0x00, 0x8a, 0x00, 0x43, 0x8a, 0xff, 0x80, - 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x1e, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, - 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0x40, 0x82, 0x00, 0x8a, 0x00, 0x43, 0x88, 0x7f, 0x40, 0x30, 0x4a, - 0xc5, 0x80, 0x00, 0x7c, 0xa3, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x50, 0x0a, 0x63, 0x80, 0x82, - 0x00, 0x8c, 0x00, 0x50, 0x0a, 0x63, 0x94, 0x82, 0x00, 0x0e, 0x80, 0x40, 0x88, 0xff, 0x94, 0x82, 0x00, 0x98, 0x00, - 0x50, 0x0a, 0x63, 0x90, 0x82, 0x00, 0x0c, 0xfa, 0x4e, 0x1b, 0x7f, 0x56, 0x7e, 0xb7, 0x0b, 0xea, 0x52, 0xff, 0x58, - 0x36, 0x27, 0x08, 0xb4, 0xe2, 0x03, 0x3c, 0x42, 0x52, 0x11, 0x35, 0x14, 0x4b, 0x56, 0x93, 0xef, 0x02, 0x77, 0x53, - 0x9b, 0x08, 0x88, 0x06, 0x00, 0x41, 0x88, 0xff, 0x94, 0x82, 0x00, 0x98, 0x80, 0x41, 0x88, 0x7f, 0x02, 0xe0, 0x7d, - 0x24, 0x60, 0x82, 0x00, 0x0a, 0x00, 0x40, 0x42, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x86, 0xef, 0x80, 0x30, - 0x88, 0xef, 0x00, 0x42, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, 0x80, - 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x31, 0x86, 0x6f, 0x80, 0x31, 0x86, 0xef, - 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x8a, 0x6f, 0x80, 0x52, 0x86, 0xef, 0x09, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, - 0xef, 0x01, 0xe0, 0x7d, 0x24, 0xe0, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x86, 0xef, 0x0a, 0x00, 0x7c, 0x23, 0x80, 0x31, - 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x02, 0xe0, 0x7d, 0x24, 0xf4, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x8a, 0xef, 0x80, - 0x52, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, - 0x1e, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, - 0xa4, 0x20, 0x83, 0x00, 0x0a, 0x80, 0x30, 0x86, 0x6f, 0x80, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, - 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x04, 0xe0, 0x7d, 0x24, 0x3c, 0x83, 0x00, 0x8a, 0x00, - 0x31, 0x86, 0x6f, 0x20, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, 0xfa, 0x6c, 0x2d, 0x49, 0x33, 0x2d, 0xfc, 0xeb, - 0xa9, 0x07, 0x59, 0xdd, 0xbe, 0x44, 0xb1, 0x57, 0x7d, 0x92, 0x94, 0xa9, 0xd8, 0x24, 0x99, 0xb7, 0xc5, 0xca, 0xe0, - 0xa1, 0xd6, 0x45, 0x96, 0x15, 0x0e, 0x60, 0x07, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, - 0xef, 0x04, 0xe0, 0x7d, 0x24, 0x5c, 0x83, 0x00, 0x8a, 0x00, 0x31, 0x86, 0x6f, 0x1e, 0x00, 0x7c, 0x23, 0x80, 0x31, - 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, 0x7c, 0x83, 0x00, 0x0a, 0x80, - 0x32, 0x86, 0xef, 0x00, 0x00, 0x00, 0x84, 0xa4, 0x82, 0x00, 0x02, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, - 0x80, 0x30, 0x82, 0xef, 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x84, 0xe7, 0x80, 0x20, 0x88, 0xe7, 0x00, 0x42, 0x86, - 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x41, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, - 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x07, 0x00, 0x7c, 0xa3, 0x80, - 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xdc, 0x83, 0x00, 0x0a, 0x80, 0x21, 0x8a, 0xe7, 0x80, 0x52, 0x86, 0x67, - 0x0f, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xf4, 0x83, 0x00, 0x0a, 0x80, 0x51, 0x84, - 0xe7, 0x00, 0x21, 0x86, 0x67, 0x0f, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x0c, 0x84, - 0x00, 0x0a, 0x80, 0x51, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x22, 0x8a, 0x67, 0x80, - 0x52, 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xfa, 0x5c, 0x11, 0x31, - 0x9b, 0x30, 0xc1, 0x95, 0xb8, 0xee, 0x5e, 0xbe, 0xcb, 0x70, 0x43, 0x85, 0x3f, 0x47, 0x5a, 0x8b, 0xef, 0x1f, 0x06, - 0x82, 0x06, 0xff, 0x84, 0x29, 0x23, 0x31, 0x4e, 0x59, 0x42, 0x38, 0x08, 0x30, 0x84, 0x00, 0x0a, 0x80, 0x51, 0x84, - 0xe7, 0x00, 0x21, 0x86, 0x67, 0x63, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x48, 0x84, - 0x00, 0x0a, 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0x67, 0x01, - 0xe0, 0x7d, 0x24, 0x60, 0x84, 0x00, 0x0a, 0x80, 0x32, 0x84, 0xe7, 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, 0x00, 0x02, - 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x30, 0x86, 0xe7, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, - 0x67, 0x80, 0x31, 0x86, 0x67, 0x00, 0x32, 0x82, 0x67, 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, - 0x80, 0x67, 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, - 0x00, 0x80, 0x67, 0x00, 0x21, 0x84, 0xe7, 0x80, 0x20, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x32, 0x48, 0x45, - 0x00, 0x22, 0x86, 0x67, 0x00, 0x21, 0x88, 0xe7, 0x80, 0x40, 0x88, 0xe8, 0xdc, 0x84, 0x00, 0x8a, 0x00, 0x20, 0x42, - 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x30, 0x42, 0x63, 0x00, 0x00, 0x00, 0x84, 0x00, 0x90, 0x42, 0x63, 0x74, 0x84, - 0x00, 0x82, 0x80, 0x70, 0x8e, 0xe7, 0x80, 0x80, 0x90, 0xe7, 0x01, 0x00, 0x42, 0x23, 0x80, 0x70, 0x8e, 0xe2, 0x00, - 0x80, 0x10, 0xeb, 0x80, 0x83, 0x90, 0xe4, 0x00, 0x80, 0x10, 0xed, 0x00, 0x80, 0x10, 0xf9, 0x00, 0x00, 0x00, 0x84, - 0xfa, 0x20, 0x8d, 0x7b, 0x16, 0x1d, 0xef, 0xe9, 0xbd, 0xa6, 0xbc, 0xef, 0x0d, 0xf0, 0xc2, 0x67, 0x7c, 0x42, 0x46, - 0x71, 0x3a, 0x35, 0x28, 0x72, 0x06, 0xd8, 0x27, 0xf9, 0x6b, 0x89, 0xe0, 0x8b, 0x50, 0x10, 0x09, 0x00, 0xc0, 0x60, - 0x63, 0x00, 0x00, 0x21, 0x63, 0x24, 0x85, 0x00, 0x8c, 0x00, 0x00, 0x6c, 0xa3, 0x2c, 0x85, 0x00, 0x18, 0x01, 0x00, - 0x6c, 0x23, 0x2c, 0x85, 0x00, 0x18, 0x00, 0x00, 0x21, 0x65, 0x00, 0x00, 0x59, 0x63, 0x00, 0x08, 0xa1, 0xe7, 0x01, - 0x00, 0x42, 0x23, 0x80, 0x00, 0xa9, 0xfd, 0x00, 0x03, 0xa1, 0x67, 0x80, 0x00, 0xab, 0x7b, 0x80, 0x5a, 0xa5, 0x67, - 0x80, 0x2a, 0xa5, 0xe7, 0x00, 0x2a, 0xa7, 0xe7, 0x00, 0x29, 0xa5, 0x67, 0x80, 0x2a, 0xa5, 0xe7, 0x00, 0x2a, 0x83, - 0xe7, 0x00, 0x10, 0x60, 0xe3, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0xa4, 0x67, 0x00, 0x29, 0xa5, 0x67, 0x00, 0x28, - 0xa5, 0xe7, 0x80, 0x29, 0xa5, 0xe7, 0x00, 0x29, 0xa1, 0xe7, 0x80, 0x0a, 0xa1, 0xe7, 0x00, 0x32, 0x42, 0x45, 0x80, - 0x20, 0xa3, 0xe7, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x0a, 0xbd, 0xe8, 0x9c, 0x85, 0x00, 0x8a, 0x00, 0x20, 0x41, 0xe3, - 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x7c, 0x23, 0x00, 0xea, 0xa9, 0xfd, 0x00, 0x0a, 0xbd, 0xe8, 0xb4, 0x85, 0x00, - 0x8a, 0x00, 0x10, 0x41, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, 0x88, 0x00, 0x00, - 0x42, 0xa3, 0x00, 0xe0, 0xbd, 0x68, 0xcc, 0x85, 0x00, 0x8a, 0x01, 0x10, 0x82, 0x24, 0x01, 0x60, 0x41, 0xa8, 0xd8, - 0x85, 0x00, 0x8a, 0x02, 0x10, 0x82, 0x24, 0x03, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, 0x88, 0x00, 0x00, 0x46, 0x23, - 0x00, 0x30, 0x86, 0xfd, 0xfa, 0xc4, 0xdc, 0x05, 0x28, 0xd5, 0x0f, 0x74, 0x6e, 0x72, 0x0e, 0xf4, 0x24, 0x89, 0x1f, - 0x96, 0x19, 0xd5, 0x97, 0x9d, 0x0b, 0xbf, 0x56, 0xf2, 0x52, 0xb3, 0xb2, 0x1c, 0x13, 0xdd, 0xc5, 0xbe, 0x70, 0xe8, - 0x09, 0x01, 0x00, 0x7c, 0xa3, 0x00, 0x0f, 0x82, 0xe2, 0x00, 0x1b, 0x40, 0x68, 0x00, 0x86, 0x00, 0x8a, 0x00, 0x00, - 0x56, 0x63, 0x08, 0x86, 0x00, 0x18, 0x00, 0x30, 0x56, 0x63, 0x08, 0x86, 0x00, 0x18, 0x00, 0x00, 0x42, 0xa3, 0x00, - 0x00, 0x00, 0x84, 0xff, 0x0f, 0x42, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x80, 0x83, 0x80, 0xfd, 0x80, 0xc5, 0x82, 0xfd, - 0x80, 0x00, 0x80, 0xe7, 0x80, 0x83, 0x82, 0x7b, 0x80, 0xc5, 0x84, 0xfb, 0x00, 0x11, 0x82, 0xe7, 0x00, 0xa7, 0x84, - 0x67, 0x00, 0x23, 0x84, 0x67, 0x00, 0x21, 0x84, 0x7b, 0x80, 0x96, 0x86, 0xe7, 0x80, 0x31, 0x86, 0xfb, 0x00, 0x10, - 0x88, 0xfd, 0x00, 0x10, 0x80, 0x7b, 0x00, 0x31, 0x82, 0xfd, 0x00, 0x31, 0x84, 0xfb, 0x80, 0x40, 0x96, 0xe7, 0x00, - 0x40, 0x9c, 0x67, 0x00, 0x20, 0x98, 0xe7, 0x80, 0x20, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x80, 0x73, 0x80, 0x67, - 0x00, 0x84, 0x82, 0xe7, 0x80, 0x94, 0x84, 0xe7, 0x00, 0x21, 0x84, 0x7b, 0x80, 0x00, 0x86, 0x7b, 0x00, 0x74, 0x88, - 0x7b, 0x00, 0x42, 0x88, 0xe7, 0x00, 0x32, 0x88, 0xfd, 0x80, 0x00, 0x80, 0x7d, 0x00, 0x20, 0x82, 0xfb, 0x80, 0x40, - 0x8e, 0xe7, 0x80, 0x00, 0x92, 0xe7, 0x80, 0x01, 0x90, 0xe7, 0x80, 0x41, 0x94, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x00, - 0x00, 0x4e, 0xa3, 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, 0xa3, - 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xb0, 0x4e, 0x67, 0xfa, 0xba, 0x81, 0x17, 0x04, 0x2d, 0x85, 0x91, 0xca, 0x3a, 0xa5, - 0x6d, 0x91, 0x74, 0x85, 0xb1, 0xba, 0x7c, 0x4a, 0x11, 0x2f, 0xd2, 0x61, 0x8d, 0xe0, 0xff, 0xf2, 0xbf, 0x09, 0x5c, - 0xeb, 0x51, 0x27, 0xc0, 0x0a, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, 0x86, - 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, - 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0xb8, 0x86, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x56, 0xc9, - 0x20, 0x05, 0x58, 0xc9, 0x40, 0x05, 0x5a, 0x49, 0x00, 0x00, 0x4e, 0xa3, 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, - 0xa3, 0x00, 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xde, 0xf3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xd0, - 0x3b, 0xeb, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, - 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, - 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x14, 0x87, 0x00, 0x0a, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xf0, 0x1e, - 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, - 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, - 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x50, 0x87, 0x00, 0x0a, 0x00, 0x00, 0x7c, 0x23, - 0x80, 0xe3, 0x8f, 0xfd, 0x00, 0xe5, 0x95, 0xfd, 0x18, 0x86, 0x00, 0x02, 0xfa, 0x8b, 0x8a, 0x5f, 0xb5, 0x34, 0x28, - 0x70, 0xc7, 0x30, 0x54, 0x56, 0x3c, 0xdf, 0x16, 0x15, 0x9f, 0x09, 0x43, 0x8b, 0xc2, 0x01, 0x89, 0x62, 0xd3, 0xf6, - 0xf8, 0x70, 0xb1, 0x1c, 0x8d, 0x47, 0xe3, 0x98, 0x0b, 0x80, 0xe3, 0x8f, 0xfd, 0x00, 0xe5, 0x95, 0xfd, 0x00, 0x05, - 0x40, 0x45, 0x20, 0x05, 0x42, 0x45, 0x40, 0x05, 0x44, 0x45, 0x80, 0x06, 0x80, 0xe7, 0x80, 0x16, 0x82, 0xe7, 0x00, - 0xb1, 0x96, 0xe7, 0x00, 0xc1, 0x98, 0xe7, 0x80, 0x05, 0xbc, 0xe8, 0xd4, 0x87, 0x00, 0x0a, 0x00, 0x16, 0xbc, 0xe8, - 0xd4, 0x87, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, - 0x84, 0x40, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, - 0xae, 0x24, 0x80, 0x5b, 0xab, 0x67, 0x00, 0x5b, 0xb1, 0x67, 0x80, 0x6b, 0xad, 0x67, 0x98, 0x96, 0x00, 0x02, 0x80, - 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, - 0x00, 0x02, 0x56, 0x49, 0x20, 0x02, 0x58, 0x49, 0x40, 0x02, 0x5a, 0xc9, 0x60, 0x02, 0x5c, 0x49, 0xf0, 0x86, 0x00, - 0x02, 0x00, 0x00, 0x40, 0xa8, 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0x02, - 0x56, 0x45, 0x20, 0x02, 0x58, 0x45, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, 0x45, 0x00, 0x02, 0x4e, 0x49, 0x20, - 0x02, 0x50, 0xc9, 0x40, 0x02, 0x52, 0x49, 0x60, 0x02, 0x54, 0xc9, 0x00, 0x50, 0x4f, 0xe3, 0x00, 0x60, 0x51, 0xe3, - 0x00, 0x70, 0x53, 0xe3, 0x00, 0x80, 0x55, 0xe3, 0x00, 0x00, 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, 0xfa, 0x1d, 0x5b, - 0x28, 0x41, 0x70, 0xb0, 0x59, 0x24, 0xd7, 0x25, 0xc6, 0x04, 0x9b, 0xcf, 0x6e, 0x4c, 0xb0, 0x92, 0x6e, 0xbc, 0x6d, - 0xf3, 0x51, 0x51, 0x3a, 0x3e, 0x50, 0xdc, 0x56, 0xd4, 0xba, 0x64, 0x70, 0x0c, 0x00, 0x07, 0x9c, 0xfd, 0x18, 0x86, - 0x00, 0x02, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xa0, - 0x31, 0x4c, 0xc5, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, - 0x08, 0x89, 0x00, 0x0a, 0x00, 0x02, 0x56, 0x45, 0x20, 0x02, 0x58, 0x45, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, - 0x45, 0x18, 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0x00, 0xe0, - 0x54, 0x63, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, 0x74, 0x84, 0x00, 0x82, 0x80, - 0xb0, 0xaa, 0xe7, 0x80, 0xc0, 0xac, 0x67, 0x80, 0x5a, 0x83, 0xe7, 0x00, 0x6b, 0x85, 0xe7, 0x80, 0x20, 0x86, 0xfd, - 0x00, 0x11, 0x88, 0xe7, 0x00, 0x43, 0x88, 0x67, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x40, 0x88, 0xfb, 0x00, 0x32, 0x80, - 0xe8, 0x08, 0x89, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, - 0x00, 0x84, 0x80, 0x73, 0x80, 0x67, 0x00, 0x84, 0x82, 0xe7, 0x80, 0x94, 0x84, 0xe7, 0x00, 0x10, 0x86, 0x7d, 0x00, - 0x31, 0x86, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x03, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x01, 0x80, 0x7b, - 0x00, 0x30, 0x86, 0x68, 0x48, 0x89, 0x00, 0x8a, 0x00, 0x74, 0x80, 0x67, 0x00, 0x95, 0x86, 0x67, 0x00, 0x30, 0x86, - 0x68, 0xfa, 0xad, 0x0d, 0x6c, 0x28, 0xb4, 0x04, 0x9e, 0xe5, 0xbc, 0xba, 0xcd, 0xd1, 0x76, 0x08, 0x41, 0x36, 0x85, - 0xe8, 0xbc, 0x36, 0x60, 0x68, 0xe8, 0x58, 0x22, 0xc1, 0xae, 0x3f, 0x1e, 0xf7, 0x7f, 0x0e, 0x48, 0x0d, 0x00, 0x00, - 0x00, 0x84, 0x00, 0x96, 0x80, 0xef, 0x80, 0xa6, 0x82, 0xef, 0x00, 0xb7, 0x84, 0x6f, 0x00, 0x95, 0x86, 0xfb, 0x80, - 0xc6, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x6f, 0x80, 0x00, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x7d, 0x80, 0xa5, 0x88, 0xfb, - 0x00, 0xd7, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xef, 0x00, 0x11, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xfd, 0x80, 0x95, 0x8a, - 0x7b, 0x00, 0xc7, 0x8c, 0x7b, 0x00, 0x53, 0x8a, 0xef, 0x00, 0x01, 0x8c, 0x7b, 0x00, 0x53, 0x8c, 0xfd, 0x00, 0x81, - 0x8e, 0x6f, 0x80, 0x63, 0x8a, 0x7d, 0x80, 0x52, 0x8e, 0x7b, 0x80, 0x53, 0x8a, 0x7b, 0x80, 0x12, 0x8e, 0xfd, 0x80, - 0x12, 0x8a, 0x7b, 0x00, 0x83, 0x8c, 0x6f, 0x00, 0x21, 0x82, 0x7b, 0x00, 0x11, 0x84, 0x7b, 0x00, 0x61, 0x8c, 0x7d, - 0x00, 0x60, 0x8c, 0xfd, 0x00, 0x63, 0x82, 0x7b, 0x00, 0x13, 0x8c, 0x7b, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x80, - 0x7b, 0x00, 0x01, 0x80, 0x7d, 0x00, 0x43, 0x82, 0xef, 0x00, 0x03, 0x84, 0x6f, 0x80, 0x53, 0x8c, 0x6f, 0x00, 0x61, - 0x9a, 0xfb, 0x80, 0x32, 0x8a, 0xef, 0x80, 0x50, 0x98, 0x7d, 0x80, 0x43, 0x8e, 0x6f, 0x00, 0x30, 0x82, 0x6f, 0x80, - 0x70, 0x9c, 0x7b, 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0xef, 0x00, 0xa5, 0x82, 0x6f, 0x80, 0xb5, 0x84, 0x6f, - 0x00, 0x95, 0x86, 0xef, 0x80, 0x31, 0x86, 0xfb, 0x80, 0x95, 0x8e, 0xef, 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x81, 0x8c, - 0xef, 0x80, 0x63, 0x8c, 0x7d, 0xfa, 0x90, 0x3c, 0x2e, 0x4a, 0xe7, 0xc9, 0x5b, 0x18, 0x91, 0xc9, 0xd2, 0x5b, 0xc0, - 0xa2, 0x37, 0xa8, 0x14, 0xe4, 0x5a, 0xb5, 0x5c, 0xb5, 0x14, 0xdd, 0xbc, 0x88, 0x1b, 0x95, 0x48, 0xf7, 0x74, 0x48, - 0x20, 0x0e, 0x00, 0x63, 0x8a, 0xfb, 0x00, 0x53, 0x8c, 0xfb, 0x00, 0x13, 0x8a, 0x7d, 0x00, 0x13, 0x8c, 0x7b, 0x00, - 0x53, 0x8c, 0xef, 0x80, 0x51, 0x8a, 0xef, 0x00, 0x21, 0x86, 0xfb, 0x80, 0x21, 0x84, 0xfb, 0x80, 0x83, 0x8e, 0x6f, - 0x00, 0x71, 0x8e, 0x7d, 0x00, 0x70, 0x8e, 0xfd, 0x80, 0x73, 0x86, 0xfb, 0x80, 0x71, 0x8e, 0xfb, 0x00, 0x00, 0x86, - 0xfb, 0x00, 0x30, 0x80, 0xfb, 0x00, 0x01, 0x80, 0x7d, 0x80, 0x03, 0x80, 0x6f, 0x00, 0x60, 0x8c, 0xfb, 0x80, 0xa5, - 0x80, 0x6f, 0x00, 0x00, 0x80, 0xfb, 0x80, 0x03, 0x8e, 0xef, 0x80, 0x53, 0x8a, 0x7d, 0x80, 0x00, 0x8e, 0xef, 0x80, - 0x73, 0x8e, 0x7b, 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x50, 0x52, 0xe3, 0x00, 0x60, 0x54, 0xe3, 0x00, 0x70, 0x56, 0xe3, - 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, 0x00, 0x56, 0xa3, 0x00, 0x01, 0x7c, - 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, - 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, - 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xa8, 0x8a, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x58, 0x49, - 0x20, 0x05, 0x5a, 0x49, 0x40, 0x05, 0x5c, 0x49, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, 0x00, 0x56, - 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xde, 0xf3, 0xfa, 0x95, 0x6e, 0x4b, 0x91, 0x4e, 0xf9, 0x77, 0xf8, 0xc2, - 0x64, 0x43, 0x28, 0xb8, 0xda, 0x59, 0x77, 0xd2, 0x94, 0x31, 0x97, 0x48, 0x68, 0x92, 0xdb, 0x43, 0x75, 0x79, 0x66, - 0x51, 0xd1, 0x92, 0xaf, 0xf8, 0x0e, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, - 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, - 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xf8, 0x8a, 0x00, 0x0a, 0x00, 0x01, 0x7c, - 0xa3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, - 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, - 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x2c, 0x8b, 0x00, 0x8a, 0x00, 0x00, 0x7c, 0x23, 0x00, 0xe5, 0x95, 0xfd, - 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe5, 0x95, 0xfd, 0x00, 0x05, 0x40, 0x45, 0x20, 0x05, 0x42, 0x45, 0x40, 0x05, 0x44, - 0x45, 0x00, 0x07, 0x80, 0x6f, 0x00, 0x17, 0x82, 0x6f, 0x00, 0xc1, 0x98, 0x6f, 0x00, 0xd1, 0x9a, 0x6f, 0x00, 0x06, - 0xbc, 0x68, 0xa0, 0x8b, 0x00, 0x0a, 0x80, 0x16, 0xbc, 0x68, 0xa0, 0x8b, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, - 0x00, 0x00, 0x84, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x30, 0x7e, 0xc5, 0x00, 0x00, 0xc4, 0x73, - 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xb0, 0x24, 0x00, 0x6c, 0xad, 0xef, 0x00, 0x7c, 0xaf, - 0xef, 0xc8, 0x97, 0x00, 0x82, 0x00, 0x10, 0x53, 0xe3, 0x00, 0x20, 0x55, 0xe3, 0xfa, 0x4f, 0x4c, 0xe4, 0x5b, 0x18, - 0x67, 0x46, 0xca, 0x88, 0x1e, 0x14, 0x95, 0xc1, 0x0a, 0x3f, 0x60, 0x51, 0xe0, 0xf8, 0xae, 0x12, 0xe8, 0x80, 0xbf, - 0x8e, 0x62, 0x11, 0xf1, 0x72, 0xfc, 0xda, 0xe2, 0xd0, 0x0f, 0x00, 0x30, 0x57, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0x94, - 0x8c, 0x00, 0x0a, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x00, 0x30, 0x7e, 0xc5, - 0x80, 0x30, 0x50, 0x45, 0x00, 0x10, 0x59, 0xe3, 0x00, 0x20, 0x5b, 0x63, 0x00, 0x30, 0x5d, 0xe3, 0xd8, 0x8a, 0x00, - 0x02, 0x00, 0x00, 0x40, 0xa8, 0x94, 0x8c, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0x00, - 0x80, 0x68, 0x00, 0x60, 0x53, 0x6f, 0x00, 0x70, 0x55, 0xef, 0x00, 0x80, 0x57, 0x6f, 0x00, 0x10, 0x59, 0xe3, 0x00, - 0x20, 0x5b, 0x63, 0x00, 0x30, 0x5d, 0xe3, 0x80, 0x06, 0x9a, 0xfd, 0x4c, 0x89, 0x00, 0x82, 0x20, 0x30, 0x7e, 0x45, - 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, - 0xa8, 0x94, 0x8c, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0x60, 0x59, 0x63, 0x00, 0x70, - 0x5b, 0x63, 0x00, 0x80, 0x5d, 0x63, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xc0, 0x52, 0xe3, 0x00, 0xd0, 0x54, 0x63, 0x00, - 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0xe0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, - 0x80, 0xc0, 0xac, 0xef, 0x80, 0xd0, 0xae, 0xef, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, - 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x30, 0x40, 0x45, 0x80, 0x30, 0x42, 0x45, 0x00, 0xa5, 0x86, 0xef, 0xfa, 0x1d, - 0x4e, 0x08, 0x6e, 0xd9, 0xe3, 0xeb, 0x07, 0xa8, 0xdc, 0x25, 0xa2, 0x75, 0x8f, 0x94, 0x53, 0x5c, 0x3c, 0x3e, 0x65, - 0x0d, 0x3d, 0x60, 0x43, 0x60, 0x16, 0x0a, 0xb8, 0xe9, 0xd7, 0x15, 0x76, 0xa8, 0x10, 0x80, 0x35, 0x86, 0x6f, 0x80, - 0x94, 0x84, 0x6f, 0x80, 0x24, 0x84, 0xef, 0x80, 0xb5, 0x88, 0x6f, 0x80, 0x45, 0x8a, 0xef, 0x80, 0x04, 0x80, 0xef, - 0x00, 0x02, 0x80, 0x6f, 0x80, 0x12, 0x82, 0xef, 0x80, 0x00, 0x80, 0x7b, 0x00, 0x01, 0x80, 0x7b, 0x80, 0x01, 0x80, - 0x68, 0x00, 0x00, 0x00, 0x84, 0x60, 0x32, 0x40, 0xc5, 0x00, 0x08, 0x80, 0xe7, 0x00, 0x08, 0x83, 0xe7, 0x00, 0x10, - 0x82, 0xfb, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x10, 0x82, 0xfb, 0x00, 0x18, 0x82, 0xe7, 0x98, 0x84, 0x00, 0x02, 0x00, - 0x10, 0x62, 0x63, 0x01, 0x00, 0x44, 0x23, 0x00, 0x20, 0x84, 0x70, 0x00, 0x01, 0x84, 0x62, 0x00, 0x00, 0x00, 0x84, - 0xc0, 0x32, 0x68, 0xc5, 0xe0, 0x32, 0x6a, 0xc5, 0xa0, 0x32, 0x6c, 0x45, 0x00, 0x64, 0x8b, 0x67, 0x80, 0x53, 0x8a, - 0x7b, 0x00, 0x66, 0x8d, 0xe7, 0x80, 0x65, 0x8c, 0x7b, 0x00, 0x53, 0x80, 0x67, 0x80, 0x96, 0x82, 0x67, 0x00, 0x86, - 0x84, 0x67, 0x80, 0x54, 0x86, 0xfb, 0x80, 0x66, 0x88, 0xfb, 0x00, 0x32, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, 0x00, - 0x32, 0x86, 0x7d, 0x00, 0x54, 0x88, 0xfb, 0x00, 0x66, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0x67, 0x00, 0x01, 0x8a, 0x7b, - 0x80, 0x42, 0x88, 0xfd, 0x00, 0x94, 0x8a, 0x7b, 0x00, 0xd6, 0x96, 0xfb, 0x80, 0x55, 0x8a, 0xe7, 0x00, 0x11, 0x96, - 0x7b, 0x80, 0x55, 0x8a, 0x7d, 0x00, 0x42, 0x99, 0xe7, 0x00, 0x51, 0x97, 0xe7, 0x00, 0xb6, 0x98, 0x7b, 0x00, 0x16, - 0x96, 0xfd, 0xfa, 0xa0, 0xce, 0xa3, 0xba, 0x23, 0x5b, 0x6a, 0xa8, 0x3c, 0x45, 0x2d, 0x9c, 0x38, 0xa0, 0xd4, 0xa3, - 0xba, 0xf1, 0x7f, 0x10, 0x32, 0x9b, 0x34, 0x49, 0x00, 0x2d, 0x8a, 0xef, 0x39, 0x9d, 0x16, 0x23, 0x80, 0x11, 0x00, - 0x16, 0x98, 0x7b, 0x00, 0xb6, 0x9a, 0x67, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x82, 0xfb, 0x00, 0x41, 0x85, 0x67, - 0x00, 0x52, 0x89, 0xe7, 0x00, 0x11, 0x82, 0x7b, 0x00, 0x01, 0x84, 0xfd, 0x00, 0x41, 0x85, 0x67, 0x00, 0x41, 0x88, - 0x7b, 0x00, 0x12, 0x80, 0x67, 0x00, 0xd0, 0x9a, 0xfb, 0x00, 0x52, 0x80, 0xe7, 0x80, 0x35, 0x96, 0x67, 0x00, 0xb0, - 0x96, 0xfd, 0x80, 0x30, 0x80, 0xe7, 0x00, 0x56, 0x98, 0x67, 0x00, 0xc0, 0x98, 0xfb, 0x00, 0x66, 0xad, 0x67, 0x00, - 0xbb, 0x96, 0x7d, 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0x67, 0x00, 0x04, 0x80, 0xe7, 0x60, 0x32, 0x42, 0x45, - 0x80, 0x13, 0x82, 0xe7, 0x00, 0x14, 0x82, 0x7b, 0x00, 0x14, 0x82, 0xe7, 0x80, 0x73, 0x84, 0xe7, 0x00, 0x11, 0x82, - 0x7b, 0x80, 0x13, 0x82, 0xe7, 0x80, 0x00, 0x80, 0xe8, 0x00, 0x00, 0x00, 0x84, 0x00, 0x74, 0x80, 0xfb, 0x00, 0x95, - 0x82, 0x7d, 0x00, 0x10, 0x82, 0x67, 0x00, 0x74, 0x80, 0xfd, 0x00, 0x95, 0x84, 0x7b, 0x00, 0x20, 0x84, 0x67, 0x00, - 0x11, 0x86, 0xfb, 0x80, 0x31, 0x86, 0x67, 0x00, 0x11, 0x88, 0x7d, 0x00, 0x42, 0x88, 0xe7, 0x00, 0x36, 0x92, 0x67, - 0x00, 0xb2, 0x94, 0x67, 0x00, 0x00, 0x00, 0x84, 0x00, 0x74, 0x82, 0x7b, 0x80, 0x10, 0x82, 0xe7, 0x00, 0x74, 0x84, - 0x7d, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x11, 0x8e, 0xe7, 0x00, 0x11, 0x82, 0x7d, 0x80, 0x60, 0x86, 0xe7, 0x00, 0x31, - 0x86, 0x7b, 0x80, 0x11, 0x90, 0x67, 0xfa, 0x89, 0xc6, 0xf4, 0xce, 0xb6, 0x79, 0x08, 0x65, 0x13, 0xf0, 0x31, 0xe3, - 0x5a, 0x78, 0x26, 0x64, 0xab, 0xbf, 0xfe, 0x59, 0xa5, 0xad, 0x4d, 0xe0, 0x3f, 0x7f, 0x3d, 0x16, 0xcd, 0xf5, 0x35, - 0xae, 0x58, 0x12, 0x00, 0x00, 0x00, 0x84, 0x80, 0x32, 0x4c, 0x45, 0x00, 0xb0, 0x52, 0x63, 0x00, 0xc0, 0x54, 0xe3, - 0x01, 0x00, 0x4e, 0x23, 0x00, 0x00, 0x50, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xf6, 0xf3, 0x00, 0xb0, 0x37, - 0xeb, 0x00, 0xd0, 0x3b, 0xeb, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, - 0x00, 0x02, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x78, 0x8e, 0x00, 0x0a, 0x00, - 0x01, 0x7c, 0xa3, 0x00, 0xb0, 0x37, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, - 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, 0x00, 0x02, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, - 0x24, 0xa4, 0x8e, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x76, 0x80, 0xe7, 0x00, 0xb4, 0x82, 0xe7, 0x00, 0x86, - 0x84, 0x67, 0x60, 0x32, 0x4c, 0xc5, 0x00, 0x63, 0x86, 0xfb, 0x00, 0x31, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, 0x80, - 0x41, 0x88, 0xfb, 0x80, 0xb3, 0x8a, 0x67, 0x00, 0x51, 0x8a, 0x7b, 0x80, 0x42, 0x88, 0x67, 0x00, 0x31, 0x86, 0xe7, - 0x80, 0x41, 0x88, 0xfd, 0x00, 0x45, 0x88, 0x67, 0x80, 0x00, 0x82, 0xfd, 0x80, 0x10, 0x82, 0xe7, 0x80, 0x14, 0x82, - 0x67, 0x80, 0x40, 0x92, 0xfd, 0x80, 0xd6, 0x86, 0xfb, 0x00, 0x34, 0x86, 0xe7, 0x00, 0x35, 0x86, 0x67, 0x00, 0x30, - 0x8e, 0xe7, 0x00, 0x31, 0x90, 0x67, 0x00, 0x00, 0x00, 0x84, 0xfa, 0x25, 0x4e, 0x29, 0x14, 0x61, 0x53, 0x9e, 0x66, - 0x14, 0x36, 0xd4, 0xbe, 0x79, 0x80, 0x70, 0xde, 0xce, 0x29, 0x73, 0x48, 0xee, 0x63, 0x23, 0xe3, 0x0f, 0x4d, 0x51, - 0x44, 0x16, 0x68, 0x53, 0x65, 0x30, 0x13, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0x00, 0x42, 0xa3, - 0x00, 0xe0, 0x45, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x47, 0xe5, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x49, - 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4b, 0xe5, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4d, 0xe5, 0x00, 0x20, - 0x04, 0xf9, 0x00, 0x30, 0x06, 0xf9, 0x00, 0x40, 0x08, 0xf9, 0x00, 0x50, 0x0a, 0xf9, 0x00, 0x60, 0x0c, 0xf9, 0x00, - 0x00, 0x00, 0x84, 0x00, 0x11, 0x02, 0xfd, 0x80, 0x21, 0x04, 0x7d, 0x00, 0x32, 0x06, 0xfd, 0x80, 0x42, 0x08, 0x7d, - 0x00, 0x53, 0x0a, 0x7d, 0x00, 0x60, 0x0c, 0xf3, 0x00, 0x00, 0x00, 0x84, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, - 0x22, 0x00, 0x40, 0x44, 0xe5, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x20, 0x2c, 0x63, 0x01, 0x60, 0x6b, 0x22, 0x00, 0x00, - 0x42, 0xa3, 0x04, 0x54, 0xe1, 0x35, 0x88, 0x90, 0x00, 0x9c, 0xff, 0x00, 0x40, 0x23, 0x00, 0x00, 0xa3, 0xe2, 0x02, - 0x10, 0x41, 0x28, 0x94, 0x90, 0x00, 0x8a, 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0x21, 0xf5, - 0x00, 0x00, 0xa3, 0xe2, 0x00, 0x20, 0x84, 0x62, 0x00, 0x11, 0x41, 0xe8, 0xa0, 0x90, 0x00, 0x0a, 0x05, 0x54, 0xf3, - 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x00, 0x03, 0x72, 0xc9, 0x05, 0x54, 0xc1, 0x39, 0x88, 0x90, 0x00, 0x9c, 0x00, 0x60, - 0x6b, 0xe3, 0x00, 0x54, 0xf5, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x01, 0x54, 0xef, 0xb5, 0xfa, 0xf7, 0x32, 0x43, 0xc2, - 0x52, 0x28, 0xdb, 0xaa, 0xb7, 0x2a, 0x46, 0x86, 0x68, 0xcb, 0x47, 0x38, 0x54, 0x4b, 0x36, 0x34, 0xa4, 0xad, 0xcb, - 0xd7, 0x90, 0xbb, 0x4e, 0x54, 0xc1, 0xe2, 0xfe, 0x3f, 0x08, 0x14, 0x88, 0x90, 0x00, 0x9c, 0x02, 0x54, 0xfb, 0xb5, - 0x88, 0x90, 0x00, 0x9c, 0x03, 0x54, 0xfd, 0x35, 0x88, 0x90, 0x00, 0x9c, 0x05, 0x54, 0xc1, 0x39, 0x88, 0x90, 0x00, - 0x9c, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, - 0xb5, 0xfd, 0x00, 0xd0, 0xbb, 0xfb, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x71, 0xaf, 0xe8, 0x00, 0xe1, 0xbd, 0xe8, 0x00, - 0x7f, 0xa9, 0x68, 0xe0, 0x03, 0x74, 0x49, 0x00, 0x04, 0x7a, 0xc9, 0xa0, 0x00, 0x60, 0xc5, 0x00, 0x00, 0x21, 0xf9, - 0xc0, 0x00, 0x62, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x05, 0x54, 0xc1, - 0x39, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x12, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, - 0x42, 0x23, 0x00, 0x00, 0x00, 0x84, 0x6c, 0x90, 0x00, 0x82, 0xf2, 0x00, 0x40, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x6c, - 0x90, 0x00, 0x82, 0xf4, 0x00, 0x40, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x6c, 0x90, 0x00, 0x82, 0xf6, 0x00, 0x40, 0x23, - 0x94, 0x81, 0x00, 0x98, 0x00, 0x00, 0xce, 0x73, 0x00, 0x00, 0xd0, 0x73, 0x00, 0x00, 0xd2, 0xf3, 0x00, 0x00, 0xd4, - 0xf3, 0x00, 0x70, 0xc0, 0xe3, 0x0c, 0x40, 0xc1, 0xa5, 0x4c, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, - 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x30, 0x8f, 0x00, 0x02, 0x08, 0x00, 0x56, 0x23, 0x12, 0x00, 0x58, 0x23, 0xfa, - 0xbf, 0x3a, 0x64, 0xef, 0x09, 0xa8, 0x97, 0x10, 0xf8, 0xfa, 0x0e, 0xe3, 0x9e, 0xbe, 0x47, 0x45, 0xa5, 0x8a, 0xd9, - 0xe9, 0x17, 0x32, 0x7f, 0xee, 0xbf, 0x06, 0xbd, 0xd9, 0xa7, 0x76, 0x49, 0x42, 0xe0, 0x14, 0x78, 0x8f, 0x00, 0x02, - 0x01, 0xc0, 0x58, 0x24, 0xe0, 0x90, 0x00, 0x8a, 0x00, 0x10, 0xc0, 0xe9, 0x01, 0xb0, 0x56, 0x24, 0xdc, 0x90, 0x00, - 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, - 0x56, 0x63, 0x30, 0x8f, 0x00, 0x02, 0x80, 0x00, 0x5e, 0xa3, 0x00, 0xf0, 0x1e, 0xf3, 0x00, 0xf0, 0x1e, 0xf3, 0x00, - 0xf0, 0x1e, 0xf3, 0x12, 0xb0, 0x56, 0xa4, 0x80, 0xb7, 0xa0, 0x62, 0x44, 0x91, 0x00, 0x8a, 0x12, 0x00, 0x58, 0x23, - 0x78, 0x8f, 0x00, 0x02, 0x01, 0xc0, 0x58, 0x24, 0x30, 0x91, 0x00, 0x8a, 0x00, 0x10, 0xc0, 0xe9, 0x20, 0x91, 0x00, - 0x18, 0x12, 0xb0, 0x56, 0xa2, 0x88, 0x91, 0x00, 0x08, 0x12, 0x00, 0x58, 0x23, 0x80, 0xc5, 0x58, 0xe4, 0x78, 0x8f, - 0x00, 0x02, 0x01, 0xb0, 0x56, 0x24, 0x54, 0x91, 0x00, 0x0a, 0x01, 0xc0, 0x40, 0x28, 0x9c, 0x91, 0x00, 0x08, 0x04, - 0x00, 0x44, 0x23, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x11, 0x02, 0xfd, 0x00, 0x20, 0x04, 0xf3, 0x01, 0xc0, 0x58, 0x24, - 0x70, 0x91, 0x00, 0x0a, 0x80, 0x10, 0x82, 0x24, 0xac, 0x91, 0x00, 0x98, 0x00, 0x00, 0x42, 0xa3, 0x8a, 0x00, 0x46, - 0xa3, 0x80, 0x11, 0xc2, 0xe2, 0x80, 0x10, 0x82, 0x24, 0xac, 0x91, 0x00, 0x98, 0x84, 0x00, 0x44, 0xa3, 0x00, 0x20, - 0x04, 0xf5, 0x00, 0x11, 0x02, 0xfd, 0xac, 0x91, 0x00, 0x98, 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf6, 0x71, 0x00, - 0x00, 0xc0, 0x2d, 0xfa, 0x25, 0x6b, 0x12, 0x07, 0x27, 0x6b, 0x6c, 0x66, 0xa9, 0xf3, 0x54, 0x8d, 0x3b, 0x9f, 0xbc, - 0xee, 0x42, 0xef, 0x21, 0x48, 0x01, 0xff, 0x8d, 0x50, 0x2b, 0x13, 0x51, 0x52, 0xde, 0x01, 0xc4, 0x33, 0xb8, 0x15, - 0x00, 0x70, 0xce, 0xeb, 0x00, 0x70, 0xd2, 0x6b, 0x00, 0x70, 0xc0, 0xe3, 0x0c, 0xb0, 0xc1, 0xa5, 0x04, 0x00, 0x42, - 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xd0, 0x91, 0x00, 0x0a, 0x80, 0x10, - 0x82, 0x24, 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf8, 0xf1, 0x60, 0x31, 0x7e, 0x45, 0x80, 0xcd, 0xb7, 0xf9, 0x00, - 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x40, 0x31, 0x7e, 0xc5, 0xc0, 0x31, 0x6a, 0x45, - 0xe0, 0x31, 0x6c, 0xc5, 0xdc, 0x87, 0x00, 0x02, 0x01, 0x00, 0x42, 0x23, 0x80, 0x50, 0xab, 0xe2, 0x00, 0x50, 0x2b, - 0xed, 0x80, 0x6a, 0xad, 0xe4, 0x00, 0x60, 0x2d, 0xf9, 0x20, 0x03, 0x6c, 0x49, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, - 0x00, 0x98, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x6b, 0x65, 0x00, 0x50, 0x2b, 0xf9, 0x20, - 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x69, 0xe5, 0x00, 0x40, 0x29, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x67, 0x65, - 0x00, 0x30, 0x27, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x20, 0x25, 0xf9, 0x00, 0x00, 0x00, - 0x84, 0x00, 0x00, 0x4c, 0x23, 0x00, 0x60, 0x8a, 0x70, 0x60, 0xb0, 0x92, 0x22, 0x1f, 0xb0, 0x90, 0x22, 0x20, 0x00, - 0x4e, 0x23, 0x00, 0x74, 0x50, 0xe4, 0x00, 0x80, 0x4e, 0xe3, 0x00, 0x70, 0x0e, 0x63, 0x00, 0x70, 0x0e, 0x63, 0x00, - 0x70, 0x0e, 0x63, 0x01, 0x70, 0x4e, 0x24, 0xfa, 0xbf, 0x09, 0xf5, 0x98, 0xca, 0x99, 0xbb, 0xdc, 0xe4, 0xed, 0x15, - 0x8c, 0xed, 0x4b, 0x76, 0xd0, 0x89, 0x5f, 0xd1, 0x0e, 0xed, 0x4c, 0x60, 0xd3, 0x14, 0xe7, 0x48, 0xc9, 0xb9, 0x40, - 0xab, 0x72, 0x90, 0x16, 0x00, 0x53, 0x0a, 0x7d, 0x01, 0x80, 0x50, 0x24, 0x90, 0x92, 0x00, 0x8a, 0x00, 0x00, 0x00, - 0x84, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, - 0x67, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x20, 0x25, 0xf9, 0x00, - 0x03, 0x68, 0x45, 0x20, 0x03, 0x6a, 0x45, 0x40, 0xb0, 0x7a, 0xa2, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, - 0x00, 0xd0, 0x3b, 0x63, 0x00, 0x00, 0xc0, 0x2d, 0x64, 0x92, 0x00, 0x82, 0x20, 0x90, 0x40, 0x28, 0xb8, 0x93, 0x00, - 0x88, 0x00, 0xd0, 0x65, 0xe3, 0xac, 0x93, 0x00, 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, - 0x67, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x20, 0x25, 0xf9, 0x00, - 0x03, 0x68, 0x45, 0x20, 0x03, 0x6a, 0x45, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x20, 0xe1, 0x6b, 0x80, 0x00, 0x7a, 0xa3, - 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x2c, 0x92, 0x00, 0x82, 0x00, 0x20, 0xe1, - 0x6b, 0x80, 0xd0, 0x7b, 0x22, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x70, 0x81, - 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, 0x80, 0xd5, 0x7b, 0xe2, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, - 0xd0, 0x3b, 0x63, 0x2c, 0x92, 0x00, 0x82, 0x80, 0xb0, 0x40, 0xa8, 0xfa, 0x8b, 0x7c, 0x62, 0x3d, 0x03, 0x28, 0xfc, - 0x9d, 0x3a, 0xee, 0xab, 0xfa, 0xd3, 0x46, 0x0e, 0xbf, 0x90, 0xfb, 0x33, 0x69, 0x29, 0x9b, 0xc2, 0x6f, 0xe2, 0x73, - 0x9f, 0xa0, 0xa1, 0xd0, 0x06, 0x92, 0x68, 0x17, 0xdc, 0x93, 0x00, 0x08, 0x64, 0x92, 0x00, 0x82, 0x60, 0x90, 0x40, - 0xa8, 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, 0xe3, 0x40, 0x90, 0x40, 0x28, 0xac, 0x93, 0x00, 0x88, 0x00, 0x00, - 0x66, 0xa3, 0x20, 0x90, 0x40, 0x28, 0xa0, 0x93, 0x00, 0x88, 0x00, 0x00, 0x68, 0x23, 0x80, 0x52, 0xab, 0x62, 0x80, - 0x53, 0xeb, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x42, 0xa9, 0x62, 0x80, 0x43, 0xe9, 0x62, 0xf8, 0x93, 0x00, 0x98, - 0x80, 0x32, 0xa7, 0x62, 0x80, 0x33, 0xe7, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x22, 0xa5, 0x62, 0x80, 0x23, 0xe5, - 0x62, 0x10, 0xb0, 0x90, 0x22, 0xd0, 0x93, 0x00, 0x8a, 0x80, 0x2e, 0xa5, 0x64, 0xf8, 0x93, 0x00, 0x98, 0x00, 0x20, - 0xe1, 0x6b, 0x00, 0x00, 0x6a, 0xa3, 0xec, 0x93, 0x00, 0x98, 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x6a, 0xa3, 0xff, - 0x00, 0x4e, 0xa3, 0x80, 0x53, 0xeb, 0x62, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x66, 0xa3, 0x00, 0xd0, 0x65, 0xe3, - 0x60, 0x31, 0x7e, 0x45, 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x21, 0xf9, 0x00, 0x10, 0x23, 0xf9, 0x80, 0x08, 0xb3, - 0x79, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x60, 0x31, 0x7e, 0x45, 0xe0, 0x03, - 0x74, 0x45, 0x00, 0x04, 0x44, 0x45, 0x80, 0xac, 0x83, 0xff, 0x80, 0x2c, 0x84, 0xff, 0x80, 0xb0, 0x87, 0x7b, 0x00, - 0x31, 0x86, 0x7b, 0x40, 0x03, 0x46, 0xc9, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, 0xfa, 0x42, 0xc9, 0xcd, - 0xe2, 0x74, 0xb4, 0x3a, 0x9e, 0x8a, 0x29, 0xa5, 0xf3, 0x2d, 0x4e, 0x05, 0x47, 0xf5, 0x36, 0x6c, 0x5b, 0x4e, 0x88, - 0x7b, 0x0c, 0x67, 0x92, 0xf0, 0x20, 0x73, 0xe6, 0xce, 0x6d, 0x40, 0x18, 0x00, 0x03, 0x58, 0x45, 0x00, 0xc0, 0x18, - 0xf9, 0x10, 0x85, 0x00, 0x82, 0x00, 0x10, 0xbc, 0x28, 0x10, 0x95, 0x00, 0x8a, 0x01, 0x00, 0x5a, 0x23, 0x00, 0xb6, - 0x9c, 0x67, 0x00, 0x90, 0x79, 0xe3, 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x4e, 0xc9, 0x80, 0x03, 0x50, 0x49, 0xa0, - 0x03, 0x52, 0x49, 0xc0, 0x03, 0x54, 0x49, 0x40, 0x03, 0x78, 0x45, 0xc0, 0x31, 0x56, 0x45, 0xe0, 0x31, 0x58, 0x45, - 0x01, 0x00, 0x5a, 0x23, 0x00, 0xb6, 0x9c, 0x67, 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x56, 0xc5, 0x80, 0x03, 0x58, - 0xc5, 0xa0, 0x03, 0x5a, 0xc5, 0xc0, 0x03, 0x5c, 0xc5, 0x00, 0x00, 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, 0x00, 0x07, - 0x9c, 0xfd, 0x18, 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0xe4, - 0x84, 0x00, 0x82, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x20, 0x03, 0x48, 0x45, 0xff, 0x0f, 0x7e, 0xa3, - 0x00, 0xf0, 0x41, 0x28, 0x00, 0x82, 0x84, 0xe8, 0x18, 0x95, 0x00, 0x0a, 0x00, 0xf0, 0x41, 0x28, 0x00, 0x82, 0x84, - 0xe8, 0x18, 0x95, 0x00, 0x0a, 0xc3, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x10, 0x00, 0x7c, 0x22, 0x40, 0x03, - 0x4a, 0xc5, 0x00, 0x40, 0x08, 0xf9, 0x00, 0xe0, 0x49, 0x69, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4b, 0xe9, 0x00, - 0x00, 0x40, 0x23, 0x50, 0x00, 0x42, 0xa3, 0x2c, 0x95, 0x00, 0x98, 0x36, 0x00, 0x40, 0x23, 0x1c, 0x95, 0x00, 0x98, - 0xfa, 0x60, 0x57, 0x2b, 0x67, 0x8c, 0xa7, 0xb6, 0xe5, 0x37, 0x0c, 0x47, 0x58, 0x66, 0x71, 0x45, 0x1b, 0xa5, 0x0d, - 0x79, 0xe9, 0x36, 0xb5, 0x93, 0x75, 0x1d, 0x58, 0x94, 0x99, 0xa6, 0xb7, 0x0e, 0xa4, 0x18, 0x19, 0x36, 0x00, 0x40, - 0x23, 0x3c, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, 0x42, 0x23, 0x2c, 0x95, 0x00, 0x98, 0x00, 0x00, - 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x94, 0x81, 0x00, 0x98, 0x00, 0x00, 0x8c, 0x67, 0x00, 0x63, 0x8c, 0xfb, 0x01, - 0x00, 0x7c, 0xa3, 0x00, 0x6f, 0x8e, 0x7b, 0x00, 0x70, 0xbc, 0x28, 0x6c, 0x96, 0x00, 0x88, 0x60, 0x32, 0x50, 0x45, - 0x00, 0x00, 0x7c, 0x23, 0x00, 0xe4, 0x93, 0x7d, 0x00, 0x83, 0x90, 0x67, 0x80, 0x73, 0x94, 0x67, 0x80, 0xa3, 0x96, - 0x67, 0x80, 0x84, 0x90, 0x67, 0x00, 0x85, 0x90, 0xfb, 0x80, 0x84, 0x90, 0x67, 0x80, 0xb5, 0x98, 0x67, 0x00, 0xc6, - 0x94, 0x67, 0x80, 0xc5, 0x98, 0xe7, 0x00, 0xc4, 0x98, 0xe7, 0x00, 0xa6, 0x94, 0x67, 0x00, 0xa0, 0x42, 0x63, 0xac, - 0x83, 0x00, 0x02, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x25, 0x9a, 0x67, 0x00, 0xd6, 0x9a, 0x67, - 0x00, 0x32, 0x7c, 0xc5, 0x00, 0xdf, 0x9c, 0x67, 0x80, 0xd6, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa4, 0x88, - 0x68, 0xc0, 0x95, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, 0xc8, 0x95, 0x00, 0x98, 0x00, 0xe0, 0x42, 0xe3, 0xc8, 0x95, - 0x00, 0x98, 0x00, 0x93, 0x84, 0xe7, 0x00, 0xd0, 0x86, 0xe7, 0x01, 0xe0, 0x89, 0xa4, 0x00, 0x32, 0x86, 0xe7, 0x00, - 0x3f, 0x88, 0xe7, 0x00, 0x83, 0x8c, 0xe7, 0x80, 0x31, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa3, 0xbc, 0xfd, - 0x00, 0xe0, 0xbd, 0xa8, 0xfa, 0xae, 0x24, 0xaf, 0xf5, 0xbb, 0xcd, 0x4c, 0xfe, 0x13, 0xe1, 0xad, 0xa4, 0xd5, 0x2f, - 0x40, 0xf8, 0xb6, 0x20, 0xf3, 0x49, 0xc4, 0xaf, 0xab, 0x92, 0x96, 0xdc, 0x3d, 0x14, 0x6d, 0x05, 0xd7, 0x10, 0xf0, - 0x19, 0xfc, 0x95, 0x00, 0x0a, 0x00, 0x30, 0x40, 0xe3, 0x04, 0x96, 0x00, 0x98, 0x00, 0x40, 0x40, 0x63, 0x04, 0x96, - 0x00, 0x98, 0x80, 0x10, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa4, 0xbc, 0x7d, 0x00, 0xe0, 0xbd, 0xa8, 0x20, - 0x96, 0x00, 0x8a, 0x00, 0x90, 0x46, 0xe3, 0x28, 0x96, 0x00, 0x18, 0x00, 0x20, 0x46, 0x63, 0x28, 0x96, 0x00, 0x18, - 0x38, 0x96, 0x00, 0x8a, 0x00, 0x10, 0x44, 0xe3, 0x01, 0x00, 0x7c, 0xa3, 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, 0x44, - 0x63, 0x00, 0x00, 0x7c, 0x23, 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, 0x40, 0x23, 0x00, 0x01, 0x82, 0xfd, 0x01, 0x00, - 0x50, 0x23, 0x00, 0x24, 0x8c, 0x62, 0x00, 0xe3, 0xbd, 0x68, 0x64, 0x96, 0x00, 0x08, 0x00, 0x10, 0x56, 0xe3, 0x6c, - 0x96, 0x00, 0x18, 0x00, 0x20, 0x56, 0xe3, 0x6c, 0x96, 0x00, 0x18, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xc4, 0x73, - 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, 0x02, 0x00, 0x70, 0xbc, 0x28, 0x70, 0x96, 0x00, - 0x08, 0x80, 0xb3, 0x9a, 0xe7, 0x00, 0x30, 0x56, 0x63, 0x00, 0x70, 0x58, 0x63, 0x00, 0x00, 0x00, 0x84, 0x40, 0x31, - 0x7e, 0xc5, 0x00, 0x05, 0x42, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0xb4, 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, 0x02, 0x00, - 0x70, 0xbc, 0x28, 0x98, 0x96, 0x00, 0x08, 0x00, 0x33, 0x7c, 0x45, 0x00, 0x3f, 0x94, 0x67, 0x80, 0x75, 0x9a, 0xe7, - 0x80, 0x33, 0x98, 0x7d, 0x80, 0x33, 0x9c, 0xfb, 0xfa, 0x52, 0xf1, 0x0e, 0x19, 0x83, 0xc9, 0x13, 0x62, 0xb2, 0x16, - 0x4e, 0x70, 0x3b, 0x56, 0x7e, 0xb0, 0x76, 0x5b, 0x98, 0x08, 0x6d, 0x96, 0x91, 0x11, 0x78, 0x41, 0xb2, 0x84, 0x9c, - 0x40, 0xa7, 0x00, 0xc8, 0x1a, 0x00, 0xd7, 0x80, 0x67, 0x00, 0x00, 0xbc, 0xa8, 0x98, 0x96, 0x00, 0x08, 0x00, 0xa7, - 0x96, 0x67, 0x80, 0xc6, 0x98, 0xe7, 0x00, 0xb6, 0x9c, 0x67, 0x00, 0xb0, 0x96, 0x67, 0x00, 0xc0, 0x98, 0x67, 0x00, - 0x00, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x00, 0x08, 0x8d, 0xef, 0x00, 0x06, 0x8f, 0xef, 0x80, 0x63, 0x8c, 0x6f, - 0x00, 0x60, 0x42, 0x63, 0xa4, 0x82, 0x00, 0x02, 0x00, 0x30, 0x52, 0xe3, 0x80, 0x93, 0x92, 0x6f, 0x00, 0x31, 0x40, - 0xc5, 0x00, 0x90, 0x94, 0xef, 0x80, 0x94, 0x90, 0x6f, 0x00, 0x88, 0x90, 0x6f, 0x00, 0x86, 0x80, 0xe8, 0x00, 0x90, - 0x54, 0xef, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x68, 0xe3, 0x20, 0x31, 0x40, 0x45, 0x60, 0x30, 0x42, 0xc5, 0x80, - 0x30, 0x44, 0x45, 0x00, 0x4a, 0x97, 0x6f, 0x80, 0x05, 0x96, 0xef, 0x80, 0xb5, 0x98, 0xef, 0x80, 0xc5, 0x98, 0x7b, - 0x01, 0x00, 0x48, 0x23, 0x00, 0xc2, 0x9a, 0xfb, 0x80, 0x26, 0x9a, 0x6f, 0x00, 0x00, 0x48, 0xa3, 0x00, 0x46, 0x9c, - 0xfd, 0x00, 0xc0, 0x80, 0xa8, 0x00, 0xe0, 0x40, 0x6f, 0x00, 0x17, 0x9c, 0x6f, 0x80, 0xd6, 0x98, 0xef, 0x00, 0xe7, - 0xa0, 0x6f, 0x00, 0x18, 0x9e, 0xef, 0x80, 0xc7, 0x98, 0xfb, 0x80, 0xc6, 0x98, 0x6f, 0x00, 0x07, 0xa1, 0x6f, 0x00, - 0x28, 0x9e, 0xef, 0x80, 0xc7, 0x98, 0xfb, 0x80, 0xb6, 0xa2, 0xef, 0xf0, 0x96, 0x00, 0x82, 0x00, 0xba, 0xa4, 0x6f, - 0x00, 0x25, 0xa5, 0xef, 0x00, 0xd0, 0x62, 0x6f, 0x00, 0xa0, 0x64, 0xef, 0xfa, 0xb6, 0x3f, 0x62, 0x25, 0xbd, 0x58, - 0x10, 0x06, 0xd2, 0xda, 0xe4, 0x46, 0xd4, 0x6d, 0xaa, 0x1b, 0xe1, 0x72, 0xdd, 0x1a, 0x8c, 0x54, 0xc8, 0xd8, 0x5f, - 0x08, 0x53, 0xb7, 0x2e, 0x2c, 0xff, 0x4c, 0xa0, 0x1b, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x19, 0x82, 0xfd, 0x00, 0x49, - 0x81, 0x68, 0x01, 0x00, 0x44, 0x23, 0x00, 0x01, 0x80, 0xe2, 0x00, 0x10, 0x64, 0x6f, 0x00, 0x10, 0x64, 0x63, 0x00, - 0x27, 0xa5, 0x6f, 0x00, 0xe0, 0x66, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x42, 0xc5, 0x00, 0x00, 0xc4, 0x73, - 0xb4, 0xa3, 0x00, 0x82, 0x28, 0x97, 0x00, 0x02, 0x00, 0x30, 0xbd, 0x28, 0xc8, 0x97, 0x00, 0x88, 0x00, 0x00, 0x00, - 0x84, 0x20, 0x30, 0x7e, 0x45, 0x60, 0x10, 0x40, 0x28, 0x18, 0x98, 0x00, 0x08, 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, - 0x66, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x00, 0x68, 0x23, 0x80, 0x49, 0xb9, 0x79, 0x80, 0xc9, 0x83, 0xe8, 0xb4, - 0x99, 0x00, 0x0a, 0x00, 0xc0, 0x83, 0xa8, 0xb4, 0x99, 0x00, 0x88, 0x2c, 0x98, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, - 0x00, 0x00, 0xe8, 0xf3, 0x80, 0x49, 0xb9, 0x79, 0x00, 0xc0, 0x83, 0xa8, 0xb4, 0x99, 0x00, 0x88, 0x00, 0x00, 0xc0, - 0xf3, 0x00, 0x00, 0xc2, 0x73, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x00, 0xc6, 0xf3, 0x00, 0x00, 0xc0, 0x63, 0x0a, 0xc0, - 0xc1, 0x25, 0x04, 0x00, 0x44, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x04, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x4c, - 0x98, 0x00, 0x0a, 0x80, 0x20, 0x84, 0x24, 0x00, 0x20, 0xc0, 0xe9, 0x00, 0x00, 0xfa, 0x71, 0x20, 0x01, 0x78, 0xc9, - 0x40, 0x01, 0x7a, 0x49, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xcf, 0xf9, 0xff, 0xfa, 0x0b, 0x6a, - 0x55, 0x81, 0xa4, 0x99, 0xf1, 0xe8, 0x5d, 0xdd, 0xa7, 0x49, 0x69, 0xfc, 0x17, 0x5d, 0x2b, 0x2b, 0x6d, 0x2a, 0x60, - 0xd6, 0x76, 0x2d, 0x5d, 0x49, 0xbc, 0x64, 0x9b, 0x55, 0xa5, 0x4d, 0x78, 0x1c, 0x00, 0x30, 0x7e, 0xc5, 0xa0, 0x30, - 0x58, 0x45, 0xc0, 0x30, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, - 0xa3, 0x00, 0x82, 0x01, 0x00, 0x9c, 0xa4, 0x00, 0xc7, 0x98, 0x6f, 0x00, 0xd7, 0x9a, 0x6f, 0x00, 0xc0, 0x52, 0xe3, - 0x00, 0xd0, 0x54, 0x63, 0x00, 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0xc0, 0x99, 0x00, 0x0a, 0x80, 0x30, 0x50, - 0x45, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0xc0, 0x99, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0xc0, 0x99, - 0x00, 0x0a, 0x00, 0xb0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0x90, 0x92, 0x6f, 0x80, 0xa0, 0x94, 0x6f, 0x00, - 0x90, 0x19, 0x6d, 0x00, 0xc0, 0x18, 0xf3, 0xaa, 0xc0, 0x98, 0xa4, 0x00, 0xc0, 0x18, 0xf3, 0x00, 0x01, 0x40, 0xc5, - 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0xa8, 0xe2, 0x60, 0x40, 0x41, 0xa8, 0x08, 0x99, 0x00, 0x08, 0x02, 0xc0, 0x98, - 0x24, 0x0c, 0x99, 0x00, 0x18, 0x01, 0xc0, 0x98, 0x24, 0x00, 0xc0, 0x18, 0xf3, 0x01, 0xc0, 0x98, 0x24, 0x04, 0xa4, - 0xd9, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xd3, 0xb7, 0xb4, 0x99, 0x00, 0x9c, 0x06, 0xa4, 0xd5, 0xb7, 0xb4, - 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, 0x00, 0x9c, - 0x20, 0x01, 0x78, 0xc5, 0x40, 0x01, 0x7a, 0x45, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, - 0xc5, 0xfa, 0xad, 0x17, 0x5b, 0x3b, 0xc1, 0x34, 0xec, 0x26, 0xba, 0xab, 0x7f, 0xc0, 0xd9, 0x69, 0x89, 0x1b, 0x48, - 0x05, 0x68, 0x97, 0xd7, 0x84, 0x50, 0x4a, 0xec, 0x7e, 0x19, 0x99, 0x40, 0x95, 0x9c, 0xb5, 0x50, 0x1d, 0xb4, 0xa3, - 0x00, 0x82, 0x00, 0xc0, 0xb9, 0xfd, 0x00, 0x00, 0xc4, 0x73, 0x00, 0xd1, 0xbb, 0xe8, 0x00, 0x90, 0x75, 0xe3, 0xff, - 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, 0x80, 0xc4, 0x94, 0x68, 0x00, 0xa4, 0xf9, 0x37, - 0xb4, 0x99, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0x37, 0xb4, 0x99, 0x00, - 0x9c, 0x03, 0xa4, 0xc5, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x04, 0xa4, 0xd5, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, - 0xc1, 0xb9, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, 0x00, - 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, - 0x41, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x10, 0x40, 0x28, 0xe0, 0x99, 0x00, 0x08, 0x10, 0x00, 0x48, - 0xa2, 0x00, 0x40, 0x66, 0xe5, 0xe4, 0x99, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, 0x01, 0x00, 0x64, 0xa3, 0x00, 0x20, - 0x25, 0xed, 0x00, 0x00, 0x62, 0x23, 0x00, 0x01, 0x60, 0x23, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x00, 0xc0, 0x2d, 0x00, - 0x00, 0xf9, 0xeb, 0x00, 0xd0, 0x3b, 0xf9, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, - 0x00, 0x00, 0x80, 0x70, 0x80, 0x0e, 0xba, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0xd0, 0xfb, 0x62, 0x00, 0xc0, 0x39, - 0xf9, 0x20, 0x01, 0x7a, 0x49, 0xfa, 0xe0, 0xfe, 0xf7, 0x2c, 0xd8, 0xa3, 0x29, 0x0f, 0xc0, 0xd5, 0xbb, 0xaa, 0x13, - 0xf3, 0xfb, 0x4c, 0x8b, 0xc5, 0x65, 0xac, 0xf3, 0xf1, 0xb3, 0xf5, 0x78, 0xd4, 0x00, 0x7c, 0x62, 0xc4, 0x81, 0x0d, - 0x28, 0x1e, 0x40, 0x01, 0x78, 0xc9, 0x00, 0x00, 0xfc, 0xf3, 0x60, 0x31, 0x7e, 0x45, 0x00, 0xdf, 0xf9, 0x7f, 0x40, - 0x31, 0x7e, 0xc5, 0xc0, 0x31, 0x56, 0x45, 0xe0, 0x31, 0x58, 0x45, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, - 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x9a, 0xa4, 0x80, 0xb6, 0x96, 0xe7, 0x00, 0xb6, 0x9c, 0x67, 0x80, 0xc6, 0x98, - 0xe7, 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0x00, 0xe0, - 0x54, 0x63, 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x70, - 0x9b, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, 0xe4, 0x84, 0x00, 0x82, 0x00, 0x90, 0x15, 0x6d, - 0x00, 0xa0, 0x14, 0xf3, 0xaa, 0xa0, 0x94, 0xa4, 0x00, 0xa0, 0x14, 0xf3, 0x00, 0x01, 0x40, 0xc5, 0xff, 0x00, 0x48, - 0xa3, 0x00, 0x02, 0x92, 0xe2, 0x60, 0x90, 0x40, 0xa8, 0xc0, 0x9a, 0x00, 0x88, 0x02, 0xa0, 0x94, 0x24, 0xc4, 0x9a, - 0x00, 0x98, 0x01, 0xa0, 0x94, 0x24, 0x00, 0xa0, 0x14, 0xf3, 0x02, 0xa0, 0x94, 0x24, 0x04, 0xa4, 0xd5, 0x37, 0x7c, - 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xd1, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0x7c, 0x9b, 0x00, 0x9c, - 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0x9b, 0x00, 0x9c, 0x20, 0x01, 0x78, 0xc5, 0x40, 0x01, 0x7a, 0x45, 0x00, 0x00, 0x40, - 0x23, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x0e, 0xbc, 0xf9, 0xfa, 0x79, 0xa3, 0x1f, 0xda, 0x93, 0x85, 0x23, 0xdd, 0x0f, - 0x1e, 0xfc, 0xab, 0x58, 0x81, 0x62, 0xe6, 0x82, 0x0b, 0x6b, 0x6c, 0x4c, 0x4f, 0x73, 0xaf, 0x26, 0xb4, 0xd2, 0x78, - 0xe5, 0xce, 0xea, 0xff, 0x00, 0x1f, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, - 0x00, 0x80, 0x24, 0x00, 0xe0, 0xb9, 0x7d, 0x00, 0x00, 0xc4, 0x73, 0x00, 0xd1, 0xbb, 0xe8, 0x00, 0x90, 0x75, 0xe3, - 0xff, 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, 0x80, 0xa4, 0x94, 0x68, 0x00, 0xa4, 0xf9, - 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0x37, 0x7c, 0x9b, - 0x00, 0x9c, 0x03, 0xa4, 0xc5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x04, 0xa4, 0xd5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, - 0xa4, 0xc1, 0xb9, 0x7c, 0x9b, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0x9b, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, - 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0x41, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, - 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xc6, 0xf3, 0x00, 0x00, 0xc8, 0x73, 0x00, 0x00, - 0xca, 0xf3, 0x00, 0x00, 0xcc, 0xf3, 0x00, 0x30, 0xc0, 0x63, 0x0b, 0x40, 0xc1, 0x25, 0x4c, 0xa3, 0x00, 0x02, 0x00, - 0x00, 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x43, 0x63, 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, - 0x01, 0xe0, 0x7d, 0x24, 0xb0, 0x9b, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, 0x0e, 0x00, 0x7c, 0xa3, 0x80, 0x00, 0x00, - 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xc8, 0x9b, 0x00, 0x0a, 0xfa, 0xb1, 0xcc, 0x05, 0xb6, 0x55, - 0xbe, 0xd0, 0x38, 0xe7, 0xf1, 0x1e, 0xad, 0xc7, 0x64, 0x47, 0x97, 0xab, 0xd7, 0x48, 0xf5, 0xd2, 0xe7, 0x14, 0xbd, - 0x78, 0x3a, 0x9f, 0x11, 0xaf, 0xce, 0xa5, 0x01, 0xd8, 0x1f, 0x04, 0x00, 0x7c, 0xa3, 0x00, 0x00, 0x42, 0xa3, 0x80, - 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xe0, 0x9b, 0x00, 0x0a, 0x1a, 0x00, 0x7c, 0xa3, - 0x00, 0x0f, 0xc0, 0xe2, 0x80, 0x00, 0x80, 0x24, 0x00, 0x00, 0xc0, 0x69, 0x00, 0x00, 0xf6, 0x71, 0x00, 0x00, 0xc0, - 0x2d, 0x00, 0x30, 0xc6, 0xeb, 0x00, 0x30, 0xca, 0xeb, 0x00, 0x30, 0xc0, 0x63, 0x0b, 0xb0, 0xc1, 0x25, 0x04, 0x00, - 0x42, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x20, 0x9c, 0x00, 0x8a, 0x80, - 0x10, 0x82, 0x24, 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf8, 0xf1, 0x20, 0x01, 0x64, 0x49, 0x20, 0x30, 0x7e, 0x45, - 0x80, 0xcd, 0xb7, 0xf9, 0x00, 0xb0, 0x81, 0xa8, 0xdc, 0x9d, 0x00, 0x88, 0xa0, 0x30, 0x6c, 0xc5, 0xc0, 0x30, 0x6e, - 0x45, 0xa8, 0x8b, 0x00, 0x02, 0x00, 0x00, 0x46, 0xe3, 0x00, 0x00, 0x40, 0xa8, 0xfc, 0x9d, 0x00, 0x8a, 0x20, 0x30, - 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x0b, 0xac, 0x79, 0x00, 0x60, 0x81, 0x28, 0xe4, 0x9d, 0x00, 0x08, 0x00, - 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0x00, 0x72, 0x63, 0x01, 0x90, 0xb3, 0x24, - 0x80, 0x9d, 0x83, 0x7f, 0xa8, 0x81, 0x00, 0x02, 0x20, 0x01, 0x64, 0x45, 0x80, 0x2c, 0x95, 0xff, 0x80, 0x6c, 0x97, - 0xff, 0x80, 0xa5, 0x99, 0x7f, 0x80, 0x55, 0x9b, 0xff, 0x80, 0xc6, 0x96, 0xfb, 0x80, 0xa5, 0x94, 0x7b, 0xfa, 0xa9, - 0x58, 0x21, 0xca, 0x6c, 0x9a, 0xce, 0xe3, 0x69, 0xa5, 0xc6, 0x3e, 0x3c, 0x3e, 0x89, 0x31, 0xdb, 0xe9, 0xd7, 0xce, - 0x96, 0x0b, 0x0a, 0xda, 0x46, 0x88, 0x4e, 0x48, 0xde, 0xcf, 0xed, 0x40, 0xb0, 0x20, 0x00, 0x15, 0x94, 0xff, 0x00, - 0xa0, 0x80, 0xa8, 0xec, 0x9d, 0x00, 0x88, 0x40, 0x01, 0x54, 0x49, 0x00, 0xa0, 0x42, 0x63, 0xa8, 0x81, 0x00, 0x02, - 0x80, 0x20, 0xb9, 0x7f, 0x80, 0x60, 0xb7, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, 0xc0, 0x30, 0x5a, - 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x94, 0x8a, 0x00, 0x82, 0x00, 0x90, 0x5e, 0xe3, 0x00, 0xa0, 0x60, 0x63, 0x00, 0xb0, - 0x62, 0x63, 0x60, 0x01, 0x58, 0xc5, 0x80, 0x01, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0xb0, 0x79, 0x63, 0x94, - 0x8a, 0x00, 0x82, 0x80, 0xf5, 0x84, 0xef, 0x80, 0x98, 0x86, 0xef, 0x80, 0x21, 0x80, 0xe8, 0x38, 0x9d, 0x00, 0x0a, - 0x80, 0x05, 0x85, 0x6f, 0x80, 0xa8, 0x86, 0xef, 0x80, 0x21, 0x80, 0xe8, 0xf4, 0x9d, 0x00, 0x0a, 0xfc, 0x89, 0x00, - 0x02, 0x00, 0x90, 0x58, 0xe3, 0x00, 0xa0, 0x5a, 0x63, 0x00, 0xb0, 0x5c, 0xe3, 0x48, 0x9d, 0x00, 0x98, 0x00, 0xf0, - 0x58, 0xe3, 0x00, 0x00, 0x5b, 0xe3, 0x00, 0x10, 0x5d, 0x63, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe0, 0x42, 0xe3, 0x98, - 0x83, 0x00, 0x82, 0x80, 0xc0, 0x98, 0x6f, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x06, 0x98, 0x79, - 0x00, 0x00, 0x7e, 0xa3, 0x00, 0xf0, 0x41, 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, 0x9d, 0x00, 0x0a, 0x00, 0xf0, 0x41, - 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, 0x9d, 0x00, 0x0a, 0x00, 0x00, 0x46, 0x23, 0xc3, 0x00, 0x44, 0xa3, 0x64, 0x81, - 0x00, 0x02, 0xfa, 0xfb, 0x5d, 0x62, 0x86, 0x76, 0x8c, 0x10, 0xbd, 0x65, 0x28, 0xab, 0x70, 0xe1, 0x2b, 0x2a, 0x23, - 0xeb, 0xc4, 0x76, 0x94, 0xfc, 0xc5, 0x2c, 0x47, 0x07, 0x61, 0x09, 0x88, 0x53, 0x1f, 0xb9, 0xe3, 0x88, 0x21, 0x00, - 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x45, 0x69, 0x00, 0x30, 0x40, 0xa8, 0x01, 0x00, 0x42, 0x23, 0xbc, 0x9d, 0x00, 0x0a, - 0x50, 0x00, 0x42, 0xa3, 0x10, 0x00, 0x7c, 0x22, 0x00, 0x60, 0x2d, 0xf9, 0x00, 0xe0, 0x6d, 0x69, 0x20, 0xe0, 0x7d, - 0x22, 0x40, 0x01, 0x54, 0x45, 0x00, 0xa0, 0x14, 0xf9, 0x00, 0xe0, 0x55, 0xe9, 0x00, 0x30, 0x40, 0xe3, 0x00, 0x00, - 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x76, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x00, - 0x00, 0x7a, 0x23, 0x94, 0x81, 0x00, 0x98, 0x21, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, 0x22, 0x00, 0x46, 0x23, - 0xfc, 0x9d, 0x00, 0x98, 0x23, 0x00, 0x46, 0xa3, 0xfc, 0x9d, 0x00, 0x98, 0x24, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, - 0x98, 0x3c, 0x00, 0x44, 0xa3, 0x01, 0x00, 0x42, 0x23, 0x84, 0x9d, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x40, 0x31, - 0x7e, 0xc5, 0x00, 0x00, 0x40, 0x23, 0x00, 0x08, 0x80, 0xf9, 0x00, 0x08, 0x80, 0xe8, 0xdc, 0x9e, 0x00, 0x0a, 0xd8, - 0x8c, 0x00, 0x02, 0xdc, 0x9e, 0x00, 0x0a, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, - 0x01, 0x00, 0xa4, 0x24, 0x00, 0x09, 0xa1, 0x67, 0x00, 0x19, 0xa3, 0x67, 0x00, 0x00, 0xfc, 0xf3, 0x80, 0x31, 0x7e, - 0xc5, 0x00, 0x3f, 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, 0x70, 0x96, 0x00, 0x02, 0x5c, 0x8e, 0x00, 0x82, 0xd0, 0x8e, - 0x00, 0x02, 0x00, 0x70, 0x6e, 0x63, 0xfa, 0x69, 0xb0, 0x4c, 0xb1, 0x6a, 0xac, 0x23, 0xc3, 0xcd, 0xd8, 0xc1, 0x90, - 0xdf, 0xc5, 0x7a, 0x4a, 0x12, 0x91, 0x1f, 0xad, 0x51, 0x0e, 0x7a, 0xe1, 0x62, 0xd6, 0x6f, 0x0f, 0xee, 0xfb, 0x59, - 0x82, 0x60, 0x22, 0x00, 0x80, 0x70, 0x63, 0x00, 0x90, 0x72, 0x63, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, - 0x00, 0x00, 0x4f, 0xe3, 0x00, 0x20, 0x51, 0x63, 0x00, 0x10, 0x53, 0xe3, 0x0c, 0x8d, 0x00, 0x82, 0x00, 0x00, 0xfc, - 0xf3, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x3f, 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, 0x5c, 0x8e, 0x00, 0x82, 0xd0, 0x8e, - 0x00, 0x02, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x80, 0x04, 0x92, 0xfd, 0x00, - 0x70, 0x57, 0x63, 0x00, 0x80, 0x59, 0xe3, 0x00, 0x90, 0x5b, 0xe3, 0x0c, 0x8d, 0x00, 0x82, 0x00, 0xc0, 0x42, 0x63, - 0x74, 0x84, 0x00, 0x82, 0x80, 0xb0, 0x96, 0xe7, 0x80, 0xd0, 0x9a, 0xe7, 0x01, 0x00, 0x58, 0xa3, 0xd4, 0x8d, 0x00, - 0x82, 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x12, 0x00, 0x40, 0x23, 0x00, 0x00, - 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0xa8, 0xa4, 0x00, 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, - 0x00, 0x48, 0x22, 0x00, 0x40, 0x48, 0xe5, 0xff, 0x00, 0x44, 0xa3, 0x00, 0x41, 0x82, 0xe2, 0x00, 0x40, 0x32, 0xf5, - 0x00, 0x90, 0x09, 0xf5, 0x00, 0x40, 0x08, 0xf5, 0x00, 0x91, 0xb3, 0xe2, 0x00, 0x41, 0x88, 0xe2, 0x00, 0x00, 0x00, - 0x84, 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x33, 0x63, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x01, 0x90, - 0x75, 0x22, 0x04, 0xa4, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0xfa, 0x6d, 0x5e, 0xad, 0xc1, 0xa4, 0xc6, 0xc5, 0xdc, - 0x35, 0x8a, 0x58, 0x8c, 0x2d, 0x2d, 0xbb, 0x86, 0x51, 0xd5, 0xcf, 0xb3, 0x19, 0xf8, 0xa9, 0x6e, 0xf5, 0xff, 0xb4, - 0x34, 0x1a, 0xdb, 0x93, 0x41, 0x38, 0x23, 0x02, 0x40, 0x40, 0xa8, 0x54, 0x9f, 0x00, 0x08, 0x01, 0x40, 0x40, 0xa8, - 0x70, 0x9f, 0x00, 0x08, 0xf4, 0x00, 0x46, 0xa3, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xcc, 0x99, 0x00, - 0x82, 0x00, 0x30, 0x40, 0xa8, 0x68, 0x9f, 0x00, 0x08, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xc3, 0x00, - 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xe4, 0x97, 0x00, 0x02, 0x00, 0x30, 0x40, 0xa8, 0x84, 0x9f, 0x00, 0x88, 0x3c, - 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xc3, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0x64, 0x81, 0x00, 0x02, - 0x00, 0x00, 0x40, 0xa2, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x44, 0x69, 0x00, 0x30, 0x40, 0xe3, 0x00, 0xa1, 0x00, - 0x98, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x68, 0xe3, 0x00, 0x40, 0x6b, 0x22, 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, - 0x35, 0x63, 0x01, 0xa0, 0x75, 0x22, 0xf2, 0x00, 0x46, 0xa3, 0x04, 0xa4, 0xc1, 0xb9, 0x70, 0xa0, 0x00, 0x9e, 0x04, - 0xa4, 0xc5, 0x35, 0x7c, 0xa0, 0x00, 0x1c, 0xf6, 0x00, 0x46, 0x23, 0xff, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x4a, 0x63, - 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0x01, 0x40, 0x40, 0xa8, 0xf4, 0x9f, 0x00, 0x08, 0x02, 0x40, 0x40, - 0xa8, 0x70, 0xa0, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0xaa, 0x40, 0x40, 0x28, 0x70, 0xa0, - 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0x80, 0x4c, 0x40, 0x68, 0xfa, 0x9c, 0x6b, 0xc9, 0x47, - 0x47, 0x8d, 0xbd, 0xb8, 0xb6, 0x5f, 0x30, 0xbb, 0x99, 0x40, 0xff, 0xda, 0x1d, 0x25, 0xe5, 0x9b, 0x46, 0x35, 0xbc, - 0xb8, 0x1f, 0x9a, 0xd4, 0xa1, 0x5a, 0xac, 0x4b, 0x08, 0x10, 0x24, 0x70, 0xa0, 0x00, 0x8a, 0xf4, 0x00, 0x46, 0xa3, - 0x00, 0xe1, 0xbd, 0xe2, 0x02, 0xe0, 0x41, 0x28, 0x44, 0xa0, 0x00, 0x88, 0x01, 0xe0, 0x41, 0x28, 0x70, 0xa0, 0x00, - 0x8a, 0x50, 0x00, 0x42, 0xa3, 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, 0x00, 0x1c, 0x06, 0xa4, 0xe3, 0x35, 0x7c, 0xa0, - 0x00, 0x1c, 0x50, 0xa0, 0x00, 0x18, 0x30, 0x00, 0x42, 0xa3, 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, 0x00, 0x1c, 0x05, - 0xa4, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0xff, 0x0f, 0x4a, 0x23, 0x80, 0x22, 0x84, 0x62, 0x00, 0x20, 0x04, 0xf3, - 0xc3, 0x20, 0x84, 0xa4, 0x00, 0x00, 0x40, 0x23, 0x8c, 0xa0, 0x00, 0x98, 0x12, 0x00, 0x44, 0xa3, 0x05, 0xa4, 0xc1, - 0x39, 0x8c, 0x9f, 0x00, 0x98, 0x3c, 0x00, 0x44, 0xa3, 0xf2, 0x00, 0x46, 0xa3, 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, - 0x00, 0x98, 0x00, 0x50, 0x45, 0xe9, 0x10, 0x40, 0x6d, 0xa2, 0x00, 0x00, 0x21, 0xf9, 0x00, 0x60, 0x61, 0xe9, 0x20, - 0x60, 0x6d, 0x22, 0x00, 0x10, 0x23, 0xf9, 0x00, 0x60, 0x63, 0x69, 0x00, 0x00, 0x40, 0x23, 0x00, 0xa1, 0x00, 0x98, - 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x33, 0x63, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x6a, 0x22, 0x03, 0x94, 0xc1, - 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, - 0x73, 0x22, 0x03, 0x94, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0xfa, - 0xbf, 0xf2, 0x9a, 0x0b, 0x3d, 0x13, 0xb2, 0xef, 0xae, 0x6a, 0xb6, 0x48, 0x2a, 0x81, 0xaa, 0xf9, 0xf5, 0xa7, 0x29, - 0x15, 0xcf, 0x5b, 0x26, 0x37, 0x88, 0x6e, 0x25, 0xad, 0x32, 0x67, 0x8f, 0x97, 0xe8, 0x24, 0x05, 0x94, 0xc1, 0x39, - 0xc3, 0x00, 0x44, 0xa3, 0x00, 0x50, 0x45, 0xe9, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x40, 0x23, 0x00, 0xa1, 0x00, - 0x98, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, - 0x44, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x94, 0x81, 0x00, 0x98, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, 0x22, 0x00, - 0x40, 0x48, 0xe5, 0x00, 0x40, 0x04, 0xf5, 0xff, 0x00, 0x4c, 0x23, 0x00, 0x23, 0x84, 0x62, 0x00, 0x20, 0x32, 0x63, - 0x01, 0x90, 0xb3, 0x24, 0x04, 0x94, 0xcb, 0xb5, 0x0c, 0xa2, 0x00, 0x1c, 0xff, 0x00, 0x4c, 0x23, 0x00, 0x53, 0x8e, - 0xe2, 0x01, 0x70, 0x40, 0xa8, 0x00, 0xa2, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x50, - 0x0a, 0xf5, 0x00, 0x53, 0x8e, 0xe2, 0x00, 0x71, 0x40, 0x68, 0xf4, 0xa1, 0x00, 0x0a, 0x05, 0x94, 0xcb, 0x35, 0x0c, - 0xa2, 0x00, 0x1c, 0x60, 0x01, 0x4a, 0xc9, 0x06, 0x94, 0xcb, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x80, 0x01, 0x4a, 0x49, - 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, 0x73, 0x24, 0x00, 0x94, 0xf5, 0xb5, 0x0c, 0xa2, 0x00, 0x1c, 0x01, 0x94, 0xed, - 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x02, 0x94, 0xeb, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x03, 0x94, 0xef, 0x35, 0x0c, 0xa2, - 0x00, 0x1c, 0x05, 0x94, 0xc1, 0x39, 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x64, 0x65, 0x00, 0x20, 0x25, 0xf9, 0x20, - 0x30, 0x7e, 0x45, 0xfa, 0x19, 0x0c, 0xb0, 0xe2, 0x2a, 0xe7, 0x81, 0x3b, 0x3e, 0xb9, 0xda, 0xac, 0xc0, 0xbd, 0xaa, - 0xe9, 0x1c, 0xee, 0x08, 0xcb, 0x84, 0x63, 0x97, 0x95, 0x36, 0x22, 0xbb, 0x8f, 0x79, 0x59, 0x4e, 0xd4, 0xc0, 0x25, - 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, 0x00, 0x50, 0xab, - 0xfb, 0x00, 0x00, 0xd4, 0xf3, 0x00, 0x65, 0xad, 0x68, 0x00, 0x75, 0xaf, 0x68, 0x80, 0x6b, 0xa9, 0xe8, 0xa0, 0x00, - 0x60, 0xc5, 0x00, 0x00, 0x21, 0xf9, 0xc0, 0x00, 0x62, 0x45, 0x88, 0x9b, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf6, - 0x00, 0x46, 0x23, 0x14, 0xa2, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf4, 0x00, 0x46, 0xa3, 0x14, 0xa2, 0x00, 0x98, - 0x05, 0x94, 0xc1, 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x05, 0x94, 0xc1, - 0x39, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x12, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x00, 0x30, - 0x40, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, 0x00, - 0x00, 0x74, 0xa3, 0x00, 0x00, 0x6e, 0x23, 0x94, 0x81, 0x00, 0x98, 0x20, 0x00, 0x42, 0x23, 0x94, 0x81, 0x00, 0x98, - 0xf2, 0x00, 0x40, 0xa3, 0x50, 0xa2, 0x00, 0x98, 0x00, 0x00, 0xe6, 0x73, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, 0x42, - 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0x30, - 0xe7, 0x62, 0x40, 0x00, 0x66, 0x49, 0x09, 0x00, 0x60, 0xa3, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, - 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0xfa, 0x68, 0xa7, 0xba, 0xf2, 0xde, 0xd4, 0x69, 0x32, 0x27, 0x79, 0xaa, - 0x64, 0xbb, 0x36, 0xb8, 0x95, 0x32, 0xc1, 0x8b, 0xcc, 0x14, 0xf3, 0x2d, 0xaa, 0x46, 0x37, 0xcc, 0x08, 0x84, 0x9a, - 0x06, 0x88, 0x98, 0x26, 0x50, 0xa2, 0x00, 0x98, 0x40, 0x00, 0x66, 0x45, 0x20, 0x00, 0x60, 0x45, 0x60, 0x00, 0x60, - 0xc9, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, - 0x00, 0x98, 0x20, 0x00, 0x42, 0x45, 0x00, 0x12, 0xe0, 0xb5, 0x58, 0xa2, 0x00, 0x9c, 0x40, 0x00, 0x66, 0x45, 0x0c, - 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, - 0x60, 0x00, 0x60, 0xc5, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x10, 0xe6, 0x35, 0x58, 0xa2, 0x00, 0x9c, 0x07, 0x00, 0x40, - 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, - 0x42, 0x23, 0x80, 0x30, 0xe7, 0x62, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, - 0x10, 0x56, 0xc9, 0x00, 0x00, 0x66, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x50, 0xa2, 0x00, 0x98, - 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0xe4, 0xa3, 0x00, 0x82, 0x04, 0xa4, 0x00, 0x82, 0x24, 0xa4, 0x00, - 0x02, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xc0, 0x63, 0x94, 0x81, 0x00, 0x98, 0x1c, 0x00, 0x7c, 0xa3, 0x00, 0x10, - 0x23, 0xf9, 0x00, 0x00, 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, 0xfd, 0x80, 0x08, 0x21, 0x7d, 0x00, - 0x10, 0x23, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x5c, 0xa3, 0x00, 0x0a, 0xfa, 0xb4, 0x60, 0xb1, 0x5a, 0x98, 0xbf, 0x70, - 0x7d, 0x4b, 0x70, 0x88, 0x41, 0xe5, 0x73, 0x50, 0x99, 0x6c, 0xb4, 0x2a, 0x42, 0x5c, 0x55, 0xd0, 0xde, 0xf4, 0x11, - 0xa2, 0x0e, 0xe9, 0x38, 0x54, 0xf8, 0x70, 0x27, 0x00, 0x00, 0xc0, 0x69, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, - 0xfd, 0x00, 0x00, 0x21, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x78, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, 0x00, 0x00, - 0x00, 0x84, 0x54, 0x00, 0x46, 0xa3, 0x00, 0x30, 0x06, 0xf3, 0x53, 0x30, 0x86, 0xa4, 0x00, 0x30, 0x06, 0xf3, 0x01, - 0x30, 0x86, 0x24, 0x00, 0x30, 0x06, 0xf3, 0x80, 0x30, 0x86, 0x24, 0x00, 0x30, 0x06, 0xf5, 0x00, 0x00, 0x00, 0x84, - 0x90, 0xa3, 0x00, 0x82, 0x01, 0x06, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xed, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xc0, - 0xeb, 0x00, 0x10, 0x80, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x08, 0x4c, 0xa3, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x60, - 0x7e, 0x69, 0xd4, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x02, 0x4c, 0xa3, 0x10, 0x00, 0x44, 0x23, 0x00, - 0x20, 0x04, 0xf3, 0x00, 0x61, 0x86, 0xe4, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0xf0, 0xa3, 0x00, 0x0a, - 0x00, 0x00, 0x00, 0x84, 0x80, 0x00, 0x4c, 0xa3, 0x50, 0x00, 0x44, 0xa3, 0x00, 0x20, 0x04, 0xf3, 0x00, 0x61, 0x86, - 0xe4, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0x10, 0xa4, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, - 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x44, 0xa3, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x48, 0xa3, 0x00, - 0x00, 0x4a, 0x23, 0x00, 0x00, 0x4c, 0x23, 0x00, 0x00, 0x4e, 0xa3, 0x00, 0x00, 0x50, 0xa3, 0x82, 0xd5, 0xdc, 0x27, - 0x35, 0x1b, 0x4c, 0xa3, 0x4c, 0x36, 0xeb, 0x41, 0x52, 0x03, 0x83, 0xdf, 0x21, 0x28, 0x70, 0x0c, 0x82, 0x60, 0x7f, - 0x4e, 0x69, 0x4f, 0x91, 0x86, 0x05, 0x9f, 0x4f, 0x41, 0xab, 0x48, 0x28, 0x00, 0x00, 0x52, 0x23, 0x00, 0x00, 0x54, - 0x23, 0x00, 0x00, 0x56, 0xa3, 0x00, 0x00, 0x58, 0x23, 0x00, 0x00, 0x5a, 0xa3, 0x00, 0x00, 0x5c, 0xa3, 0x00, 0x00, - 0x5e, 0x23, 0x00, 0x00, 0x60, 0xa3, 0x00, 0x00, 0x62, 0x23, 0x00, 0x00, 0x64, 0x23, 0x00, 0x00, 0x66, 0xa3, 0x00, - 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, 0x00, 0x00, 0x6e, 0x23, 0x00, 0x00, 0x70, 0x23, - 0x00, 0x00, 0x72, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x76, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, - 0x23, 0x00, 0x00, 0x7c, 0x23, 0x00, 0x00, 0x7e, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x72, 0x15, 0x3d, 0x1a, 0x60, 0x0f, - 0x69, 0x4a, 0x2c, 0xc1, 0x53, 0x08, 0xf6, 0x3c, 0x30, 0x3c, 0xc9, 0x27, 0x90, 0xfc, 0xf3, 0x88, 0x47, 0xba, 0x3a, - 0x14, 0xa3, 0xd7, 0x9f, 0x7b, 0xcb, 0xa5, 0x1f, 0xb0, 0x03, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xd4, 0xf7, 0xa4, 0x0c, - 0xbc, 0xf7, 0x1c, 0x21, 0x26, 0x12, 0xa4, 0x9d, 0x66, 0x93, 0x47, 0xf7, 0x1f, 0xee, 0x20, 0x54, 0x07, 0x06, 0x16, - 0x79, 0x53, 0x6d, 0x70, 0x70, 0xd8, 0xd6, 0x47, 0x37, 0xd8, 0x02, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x01, - 0x00, 0x00, 0x00, 0x01, 0xa8, 0x24, 0x00, 0x00, 0x45, 0x07, 0xdd, 0x4c, 0x3e, 0x76, 0xee, 0xe1, 0x59, 0xcb, 0x26, - 0x98, 0xc7, 0x25, 0x91, 0xb2, 0x59, 0xdd, 0x1c, 0xf0, 0x9e, 0xef, 0xd3, 0x1c, 0x5d, 0xb6, 0x34, 0xbb, 0x20, 0xd4, - 0x52, 0x09, 0xd2, 0x56, 0xbf, 0xa0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff}; \ No newline at end of file +const uint8_t fw_SPECT[] = { + 0x68, 0xd7, 0x2a, 0x0a, 0xb1, 0x9a, 0x44, 0xee, 0xf3, 0x8b, 0xd7, 0xb4, 0xdb, 0xe1, 0x13, 0x4e, + 0x87, 0xda, 0x13, 0xf2, 0x47, 0x06, 0x5a, 0x5a, 0x46, 0x52, 0x82, 0xd9, 0x06, 0x4b, 0x45, 0x0c, + 0x87, 0x67, 0x91, 0xc0, 0x89, 0xa0, 0xbc, 0xa7, 0x2f, 0x53, 0x6c, 0x82, 0xd1, 0x0c, 0xbb, 0x35, + 0x19, 0x75, 0x37, 0x00, 0xdd, 0xf1, 0x45, 0xa9, 0xdc, 0x18, 0xb3, 0x6e, 0x48, 0xa2, 0xc0, 0x98, + 0x0a, 0x01, 0xa0, 0x7b, 0x57, 0xe4, 0x44, 0x74, 0x24, 0x7f, 0xf7, 0xde, 0xec, 0x32, 0xd7, 0x0b, + 0xfd, 0xef, 0x57, 0x97, 0xb9, 0x84, 0xe8, 0xe3, 0x41, 0xed, 0x3f, 0xfc, 0x63, 0x54, 0xa4, 0x52, + 0xa2, 0x02, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x62, 0xba, 0x4b, 0x73, 0x36, 0x91, 0x21, + 0x1d, 0xeb, 0x69, 0xfb, 0xb6, 0x6b, 0xa7, 0x0a, 0xf3, 0x26, 0xef, 0x36, 0x08, 0xd9, 0xb1, 0xdd, + 0xf8, 0xb0, 0x4a, 0x65, 0xc0, 0xdb, 0x21, 0xcf, 0x36, 0xe3, 0x00, 0x00, 0x10, 0xa5, 0xaf, 0xbb, + 0xc2, 0xd2, 0x77, 0x19, 0xce, 0xe4, 0x30, 0x16, 0xf9, 0x4a, 0x54, 0x04, 0x9d, 0xc1, 0x73, 0x21, + 0x2c, 0x75, 0x19, 0xd9, 0x0a, 0x49, 0x73, 0x2b, 0x0b, 0x10, 0xdb, 0x5c, 0x54, 0x93, 0xe8, 0x13, + 0xf3, 0x01, 0xe5, 0x70, 0x69, 0x6e, 0x58, 0x4e, 0xb2, 0x56, 0xfb, 0x09, 0xaf, 0x9a, 0x11, 0x0f, + 0x6a, 0xa7, 0x27, 0x91, 0x25, 0x53, 0xeb, 0xa4, 0xc7, 0xa4, 0x48, 0x0a, 0xfa, 0x50, 0xd1, 0xc2, + 0xa2, 0xfd, 0x75, 0x8b, 0x0f, 0xf6, 0xfe, 0x2a, 0x27, 0x13, 0x81, 0xae, 0x66, 0xd9, 0x5f, 0x44, + 0xb2, 0x2a, 0xc3, 0xee, 0x40, 0x20, 0xfa, 0x67, 0x87, 0x40, 0xa5, 0x2a, 0x0d, 0x00, 0x04, 0x00, + 0x00, 0x7e, 0xa3, 0xe4, 0xa3, 0x00, 0x82, 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, 0x40, 0xa2, 0xff, + 0x00, 0x48, 0xa3, 0x00, 0x02, 0x82, 0x62, 0xf0, 0x10, 0x88, 0xa2, 0x20, 0x33, 0x4a, 0xc5, 0x00, + 0x10, 0x40, 0x28, 0x2c, 0xa3, 0x00, 0x08, 0x60, 0x40, 0x40, 0x28, 0x4c, 0x80, 0x00, 0x88, 0x10, + 0x40, 0x40, 0xa8, 0x84, 0x80, 0x00, 0x08, 0x40, 0x40, 0x40, 0xa8, 0xb8, 0x80, 0x00, 0x08, 0x70, + 0x40, 0x40, 0xa8, 0x20, 0x81, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0x04, 0xa4, 0x00, 0x82, 0xf4, + 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x60, 0x10, 0x40, 0x28, 0x1c, + 0x9f, 0x00, 0x08, 0x61, 0x10, 0x40, 0xa8, 0x1c, 0x9f, 0x00, 0x08, 0x62, 0x10, 0x40, 0xa8, 0xa4, + 0x9f, 0x00, 0x08, 0x63, 0x10, 0x40, 0x28, 0xb0, 0xa0, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0xa8, + 0xa4, 0x00, 0x18, 0xf3, 0x50, 0x8a, 0xa4, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x11, + 0x10, 0x40, 0x28, 0x60, 0xa2, 0x00, 0x08, 0x12, 0x10, 0x40, 0x28, 0x9c, 0xa2, 0x00, 0x08, 0x13, + 0x10, 0x40, 0xa8, 0xbc, 0xa2, 0x00, 0x88, 0x14, 0x10, 0x40, 0x28, 0xe0, 0xa2, 0x00, 0x88, 0x40, + 0x81, 0x00, 0x98, 0xa8, 0xa4, 0x00, 0x18, 0x04, 0xa4, 0x00, 0x82, 0xf2, 0x50, 0x8a, 0x24, 0x00, + 0x50, 0x0a, 0xf3, 0x00, 0x05, 0x4a, 0x49, 0x41, 0x10, 0x40, 0x28, 0x94, 0x8f, 0x00, 0x88, 0x42, + 0x10, 0x40, 0x28, 0xac, 0x90, 0x00, 0x88, 0xfa, 0xf0, 0x16, 0x3b, 0xa9, 0x5c, 0xdb, 0xb6, 0xb6, + 0x81, 0xdf, 0x01, 0x03, 0x10, 0x82, 0xe9, 0xaa, 0x95, 0x82, 0xee, 0xe8, 0xbc, 0x80, 0xc4, 0x55, + 0x77, 0xb0, 0x3d, 0x6c, 0x8f, 0x56, 0x2b, 0x2d, 0xd8, 0x04, 0x43, 0x10, 0x40, 0xa8, 0xd4, 0x90, + 0x00, 0x88, 0x44, 0x10, 0x40, 0x28, 0x04, 0x91, 0x00, 0x88, 0x45, 0x10, 0x40, 0xa8, 0xfc, 0x91, + 0x00, 0x08, 0x46, 0x10, 0x40, 0xa8, 0xa0, 0x92, 0x00, 0x08, 0x47, 0x10, 0x40, 0x28, 0xf4, 0x92, + 0x00, 0x88, 0x48, 0x10, 0x40, 0x28, 0x30, 0x93, 0x00, 0x88, 0x49, 0x10, 0x40, 0xa8, 0x48, 0x93, + 0x00, 0x88, 0x4a, 0x10, 0x40, 0xa8, 0x18, 0x94, 0x00, 0x08, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, + 0x00, 0x18, 0x04, 0xa4, 0x00, 0x82, 0xf1, 0x50, 0x8a, 0x24, 0x00, 0x50, 0x0a, 0xf3, 0x00, 0x05, + 0x4a, 0x49, 0x70, 0x10, 0x40, 0xa8, 0x1c, 0xa1, 0x00, 0x88, 0x40, 0x81, 0x00, 0x98, 0xa8, 0xa4, + 0x00, 0x18, 0x02, 0x00, 0x44, 0x23, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x44, 0x69, 0x00, 0x00, + 0x42, 0xa3, 0xf3, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x40, 0x00, 0x40, 0xa3, 0x00, 0x00, + 0x00, 0xf3, 0x00, 0x00, 0x00, 0x84, 0x50, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x00, + 0x00, 0x84, 0x00, 0x01, 0x40, 0xc5, 0x00, 0x00, 0x00, 0xf5, 0x00, 0x00, 0x00, 0xf5, 0xff, 0x00, + 0x42, 0xa3, 0x00, 0x10, 0x02, 0xf3, 0xff, 0x10, 0x82, 0xa4, 0x80, 0x00, 0x80, 0xe2, 0x00, 0x00, + 0x00, 0x84, 0xa8, 0xa4, 0x00, 0x18, 0x00, 0x10, 0x02, 0xf3, 0x00, 0x10, 0x02, 0xf3, 0x80, 0x00, + 0x40, 0xe2, 0x00, 0x11, 0x40, 0x49, 0x00, 0x00, 0xc0, 0x93, 0x80, 0x10, 0x84, 0xff, 0x80, 0x20, + 0x86, 0x7f, 0xfa, 0x8a, 0x55, 0xdc, 0xbc, 0xbd, 0x1e, 0x59, 0xf0, 0x49, 0xb7, 0x8e, 0x78, 0xcf, + 0xaf, 0xf0, 0x4b, 0xa0, 0xf9, 0xd1, 0xd8, 0x1b, 0x2e, 0x08, 0x35, 0x16, 0x13, 0x73, 0x74, 0xd2, + 0x2c, 0x15, 0xd6, 0xb0, 0x05, 0x80, 0x31, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x80, 0x41, 0x8a, + 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, + 0xff, 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x06, 0x00, 0x7c, + 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, + 0xa4, 0xdc, 0x81, 0x00, 0x8a, 0x80, 0x42, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x0f, 0x00, 0x7c, + 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, + 0xa4, 0xfc, 0x81, 0x00, 0x0a, 0x80, 0x42, 0x8c, 0xff, 0x00, 0x63, 0x88, 0xff, 0x3f, 0x00, 0x7c, + 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x03, 0xe0, 0x7d, + 0xa4, 0x1c, 0x82, 0x00, 0x8a, 0x00, 0x43, 0x8a, 0xff, 0x80, 0x52, 0x88, 0xff, 0x00, 0x42, 0x88, + 0xff, 0x1e, 0x00, 0x7c, 0x23, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, + 0xff, 0x03, 0xe0, 0x7d, 0xa4, 0x40, 0x82, 0x00, 0x8a, 0x00, 0x43, 0x88, 0x7f, 0x40, 0x30, 0x4a, + 0xc5, 0x80, 0x00, 0x7c, 0xa3, 0x00, 0x42, 0x88, 0xff, 0x00, 0x42, 0x88, 0xff, 0x00, 0x50, 0x0a, + 0x63, 0x80, 0x82, 0x00, 0x8c, 0x00, 0x50, 0x0a, 0x63, 0x94, 0x82, 0x00, 0x0e, 0x80, 0x40, 0x88, + 0xff, 0x94, 0x82, 0x00, 0x98, 0x00, 0x50, 0x0a, 0x63, 0x90, 0x82, 0x00, 0x0c, 0xfa, 0x4e, 0x1b, + 0x7f, 0x56, 0x7e, 0xb7, 0x0b, 0xea, 0x52, 0xff, 0x58, 0x36, 0x27, 0x08, 0xb4, 0xe2, 0x03, 0x3c, + 0x42, 0x52, 0x11, 0x35, 0x14, 0x4b, 0x56, 0x93, 0xef, 0x02, 0x77, 0x53, 0x9b, 0x08, 0x88, 0x06, + 0x00, 0x41, 0x88, 0xff, 0x94, 0x82, 0x00, 0x98, 0x80, 0x41, 0x88, 0x7f, 0x02, 0xe0, 0x7d, 0x24, + 0x60, 0x82, 0x00, 0x0a, 0x00, 0x40, 0x42, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x86, 0xef, + 0x80, 0x30, 0x88, 0xef, 0x00, 0x42, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, + 0x00, 0x21, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, + 0x00, 0x31, 0x86, 0x6f, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x8a, 0x6f, + 0x80, 0x52, 0x86, 0xef, 0x09, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x01, 0xe0, 0x7d, 0x24, + 0xe0, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x86, 0xef, 0x0a, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x02, 0xe0, 0x7d, 0x24, 0xf4, 0x82, 0x00, 0x8a, 0x80, 0x32, 0x8a, 0xef, + 0x80, 0x52, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x00, 0x32, 0x84, 0xef, 0x00, 0x21, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x1e, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, 0x20, 0x83, 0x00, 0x0a, 0x80, 0x30, 0x86, 0x6f, + 0x80, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, + 0x80, 0x31, 0x86, 0xef, 0x04, 0xe0, 0x7d, 0x24, 0x3c, 0x83, 0x00, 0x8a, 0x00, 0x31, 0x86, 0x6f, + 0x20, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0xef, 0xfa, 0x6c, 0x2d, 0x49, 0x33, 0x2d, 0xfc, 0xeb, + 0xa9, 0x07, 0x59, 0xdd, 0xbe, 0x44, 0xb1, 0x57, 0x7d, 0x92, 0x94, 0xa9, 0xd8, 0x24, 0x99, 0xb7, + 0xc5, 0xca, 0xe0, 0xa1, 0xd6, 0x45, 0x96, 0x15, 0x0e, 0x60, 0x07, 0x80, 0x31, 0x86, 0xef, 0x80, + 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x04, 0xe0, 0x7d, 0x24, 0x5c, 0x83, 0x00, 0x8a, 0x00, + 0x31, 0x86, 0x6f, 0x1e, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, + 0x31, 0x86, 0xef, 0x03, 0xe0, 0x7d, 0xa4, 0x7c, 0x83, 0x00, 0x0a, 0x80, 0x32, 0x86, 0xef, 0x00, + 0x00, 0x00, 0x84, 0xa4, 0x82, 0x00, 0x02, 0x80, 0x31, 0x86, 0xef, 0x80, 0x31, 0x86, 0xef, 0x80, + 0x30, 0x82, 0xef, 0x00, 0x00, 0x00, 0x84, 0x80, 0x10, 0x84, 0xe7, 0x80, 0x20, 0x88, 0xe7, 0x00, + 0x42, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x41, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x80, + 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x21, 0x84, 0x67, 0x00, + 0x21, 0x86, 0x67, 0x07, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xdc, + 0x83, 0x00, 0x0a, 0x80, 0x21, 0x8a, 0xe7, 0x80, 0x52, 0x86, 0x67, 0x0f, 0x00, 0x7c, 0x23, 0x80, + 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xf4, 0x83, 0x00, 0x0a, 0x80, 0x51, 0x84, 0xe7, 0x00, + 0x21, 0x86, 0x67, 0x0f, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x0c, + 0x84, 0x00, 0x0a, 0x80, 0x51, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, + 0x22, 0x8a, 0x67, 0x80, 0x52, 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, 0x80, 0x31, 0x86, 0x67, 0x01, + 0xe0, 0x7d, 0x24, 0xfa, 0x5c, 0x11, 0x31, 0x9b, 0x30, 0xc1, 0x95, 0xb8, 0xee, 0x5e, 0xbe, 0xcb, + 0x70, 0x43, 0x85, 0x3f, 0x47, 0x5a, 0x8b, 0xef, 0x1f, 0x06, 0x82, 0x06, 0xff, 0x84, 0x29, 0x23, + 0x31, 0x4e, 0x59, 0x42, 0x38, 0x08, 0x30, 0x84, 0x00, 0x0a, 0x80, 0x51, 0x84, 0xe7, 0x00, 0x21, + 0x86, 0x67, 0x63, 0x00, 0x7c, 0x23, 0x80, 0x31, 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x48, 0x84, + 0x00, 0x0a, 0x80, 0x21, 0x84, 0x67, 0x00, 0x21, 0x86, 0x67, 0x31, 0x00, 0x7c, 0xa3, 0x80, 0x31, + 0x86, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x60, 0x84, 0x00, 0x0a, 0x80, 0x32, 0x84, 0xe7, 0x00, 0x00, + 0x00, 0x84, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x30, + 0x86, 0xe7, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x80, 0x31, 0x86, 0x67, 0x00, 0x32, + 0x82, 0x67, 0x00, 0x00, 0x00, 0x84, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0x80, 0x67, 0x00, 0x00, + 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x00, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x00, + 0x80, 0x67, 0x00, 0x21, 0x84, 0xe7, 0x80, 0x20, 0x84, 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x32, + 0x48, 0x45, 0x00, 0x22, 0x86, 0x67, 0x00, 0x21, 0x88, 0xe7, 0x80, 0x40, 0x88, 0xe8, 0xdc, 0x84, + 0x00, 0x8a, 0x00, 0x20, 0x42, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x30, 0x42, 0x63, 0x00, 0x00, + 0x00, 0x84, 0x00, 0x90, 0x42, 0x63, 0x74, 0x84, 0x00, 0x82, 0x80, 0x70, 0x8e, 0xe7, 0x80, 0x80, + 0x90, 0xe7, 0x01, 0x00, 0x42, 0x23, 0x80, 0x70, 0x8e, 0xe2, 0x00, 0x80, 0x10, 0xeb, 0x80, 0x83, + 0x90, 0xe4, 0x00, 0x80, 0x10, 0xed, 0x00, 0x80, 0x10, 0xf9, 0x00, 0x00, 0x00, 0x84, 0xfa, 0x20, + 0x8d, 0x7b, 0x16, 0x1d, 0xef, 0xe9, 0xbd, 0xa6, 0xbc, 0xef, 0x0d, 0xf0, 0xc2, 0x67, 0x7c, 0x42, + 0x46, 0x71, 0x3a, 0x35, 0x28, 0x72, 0x06, 0xd8, 0x27, 0xf9, 0x6b, 0x89, 0xe0, 0x8b, 0x50, 0x10, + 0x09, 0x00, 0xc0, 0x60, 0x63, 0x00, 0x00, 0x21, 0x63, 0x24, 0x85, 0x00, 0x8c, 0x00, 0x00, 0x6c, + 0xa3, 0x2c, 0x85, 0x00, 0x18, 0x01, 0x00, 0x6c, 0x23, 0x2c, 0x85, 0x00, 0x18, 0x00, 0x00, 0x21, + 0x65, 0x00, 0x00, 0x59, 0x63, 0x00, 0x08, 0xa1, 0xe7, 0x01, 0x00, 0x42, 0x23, 0x80, 0x00, 0xa9, + 0xfd, 0x00, 0x03, 0xa1, 0x67, 0x80, 0x00, 0xab, 0x7b, 0x80, 0x5a, 0xa5, 0x67, 0x80, 0x2a, 0xa5, + 0xe7, 0x00, 0x2a, 0xa7, 0xe7, 0x00, 0x29, 0xa5, 0x67, 0x80, 0x2a, 0xa5, 0xe7, 0x00, 0x2a, 0x83, + 0xe7, 0x00, 0x10, 0x60, 0xe3, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0xa4, 0x67, 0x00, 0x29, 0xa5, + 0x67, 0x00, 0x28, 0xa5, 0xe7, 0x80, 0x29, 0xa5, 0xe7, 0x00, 0x29, 0xa1, 0xe7, 0x80, 0x0a, 0xa1, + 0xe7, 0x00, 0x32, 0x42, 0x45, 0x80, 0x20, 0xa3, 0xe7, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x0a, 0xbd, + 0xe8, 0x9c, 0x85, 0x00, 0x8a, 0x00, 0x20, 0x41, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x7c, + 0x23, 0x00, 0xea, 0xa9, 0xfd, 0x00, 0x0a, 0xbd, 0xe8, 0xb4, 0x85, 0x00, 0x8a, 0x00, 0x10, 0x41, + 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, 0x88, 0x00, 0x00, 0x42, + 0xa3, 0x00, 0xe0, 0xbd, 0x68, 0xcc, 0x85, 0x00, 0x8a, 0x01, 0x10, 0x82, 0x24, 0x01, 0x60, 0x41, + 0xa8, 0xd8, 0x85, 0x00, 0x8a, 0x02, 0x10, 0x82, 0x24, 0x03, 0x10, 0x40, 0x28, 0x10, 0x86, 0x00, + 0x88, 0x00, 0x00, 0x46, 0x23, 0x00, 0x30, 0x86, 0xfd, 0xfa, 0xc4, 0xdc, 0x05, 0x28, 0xd5, 0x0f, + 0x74, 0x6e, 0x72, 0x0e, 0xf4, 0x24, 0x89, 0x1f, 0x96, 0x19, 0xd5, 0x97, 0x9d, 0x0b, 0xbf, 0x56, + 0xf2, 0x52, 0xb3, 0xb2, 0x1c, 0x13, 0xdd, 0xc5, 0xbe, 0x70, 0xe8, 0x09, 0x01, 0x00, 0x7c, 0xa3, + 0x00, 0x0f, 0x82, 0xe2, 0x00, 0x1b, 0x40, 0x68, 0x00, 0x86, 0x00, 0x8a, 0x00, 0x00, 0x56, 0x63, + 0x08, 0x86, 0x00, 0x18, 0x00, 0x30, 0x56, 0x63, 0x08, 0x86, 0x00, 0x18, 0x00, 0x00, 0x42, 0xa3, + 0x00, 0x00, 0x00, 0x84, 0xff, 0x0f, 0x42, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x80, 0x83, 0x80, 0xfd, + 0x80, 0xc5, 0x82, 0xfd, 0x80, 0x00, 0x80, 0xe7, 0x80, 0x83, 0x82, 0x7b, 0x80, 0xc5, 0x84, 0xfb, + 0x00, 0x11, 0x82, 0xe7, 0x00, 0xa7, 0x84, 0x67, 0x00, 0x23, 0x84, 0x67, 0x00, 0x21, 0x84, 0x7b, + 0x80, 0x96, 0x86, 0xe7, 0x80, 0x31, 0x86, 0xfb, 0x00, 0x10, 0x88, 0xfd, 0x00, 0x10, 0x80, 0x7b, + 0x00, 0x31, 0x82, 0xfd, 0x00, 0x31, 0x84, 0xfb, 0x80, 0x40, 0x96, 0xe7, 0x00, 0x40, 0x9c, 0x67, + 0x00, 0x20, 0x98, 0xe7, 0x80, 0x20, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x80, 0x73, 0x80, 0x67, + 0x00, 0x84, 0x82, 0xe7, 0x80, 0x94, 0x84, 0xe7, 0x00, 0x21, 0x84, 0x7b, 0x80, 0x00, 0x86, 0x7b, + 0x00, 0x74, 0x88, 0x7b, 0x00, 0x42, 0x88, 0xe7, 0x00, 0x32, 0x88, 0xfd, 0x80, 0x00, 0x80, 0x7d, + 0x00, 0x20, 0x82, 0xfb, 0x80, 0x40, 0x8e, 0xe7, 0x80, 0x00, 0x92, 0xe7, 0x80, 0x01, 0x90, 0xe7, + 0x80, 0x41, 0x94, 0xe7, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x4e, 0xa3, 0x01, 0x00, 0x50, 0x23, + 0x01, 0x00, 0x52, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, + 0x00, 0xb0, 0x4e, 0x67, 0xfa, 0xba, 0x81, 0x17, 0x04, 0x2d, 0x85, 0x91, 0xca, 0x3a, 0xa5, 0x6d, + 0x91, 0x74, 0x85, 0xb1, 0xba, 0x7c, 0x4a, 0x11, 0x2f, 0xd2, 0x61, 0x8d, 0xe0, 0xff, 0xf2, 0xbf, + 0x09, 0x5c, 0xeb, 0x51, 0x27, 0xc0, 0x0a, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, + 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, + 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0xb8, + 0x86, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x56, 0xc9, 0x20, 0x05, 0x58, 0xc9, 0x40, + 0x05, 0x5a, 0x49, 0x00, 0x00, 0x4e, 0xa3, 0x01, 0x00, 0x50, 0x23, 0x01, 0x00, 0x52, 0xa3, 0x00, + 0x00, 0x54, 0x23, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xde, 0xf3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, + 0xd0, 0x3b, 0xeb, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, + 0xe0, 0x54, 0xe7, 0x18, 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, + 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x14, + 0x87, 0x00, 0x0a, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, + 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x18, + 0x86, 0x00, 0x02, 0x68, 0x86, 0x00, 0x82, 0x00, 0xb0, 0x4e, 0x67, 0x00, 0xc0, 0x50, 0xe7, 0x00, + 0xd0, 0x52, 0xe7, 0x00, 0xe0, 0x54, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x50, 0x87, 0x00, 0x0a, 0x00, + 0x00, 0x7c, 0x23, 0x80, 0xe3, 0x8f, 0xfd, 0x00, 0xe5, 0x95, 0xfd, 0x18, 0x86, 0x00, 0x02, 0xfa, + 0x8b, 0x8a, 0x5f, 0xb5, 0x34, 0x28, 0x70, 0xc7, 0x30, 0x54, 0x56, 0x3c, 0xdf, 0x16, 0x15, 0x9f, + 0x09, 0x43, 0x8b, 0xc2, 0x01, 0x89, 0x62, 0xd3, 0xf6, 0xf8, 0x70, 0xb1, 0x1c, 0x8d, 0x47, 0xe3, + 0x98, 0x0b, 0x80, 0xe3, 0x8f, 0xfd, 0x00, 0xe5, 0x95, 0xfd, 0x00, 0x05, 0x40, 0x45, 0x20, 0x05, + 0x42, 0x45, 0x40, 0x05, 0x44, 0x45, 0x80, 0x06, 0x80, 0xe7, 0x80, 0x16, 0x82, 0xe7, 0x00, 0xb1, + 0x96, 0xe7, 0x00, 0xc1, 0x98, 0xe7, 0x80, 0x05, 0xbc, 0xe8, 0xd4, 0x87, 0x00, 0x0a, 0x00, 0x16, + 0xbc, 0xe8, 0xd4, 0x87, 0x00, 0x0a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x01, 0x00, + 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x40, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, + 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xae, 0x24, 0x80, 0x5b, 0xab, 0x67, 0x00, 0x5b, + 0xb1, 0x67, 0x80, 0x6b, 0xad, 0x67, 0x98, 0x96, 0x00, 0x02, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x00, + 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, 0x00, 0x02, + 0x56, 0x49, 0x20, 0x02, 0x58, 0x49, 0x40, 0x02, 0x5a, 0xc9, 0x60, 0x02, 0x5c, 0x49, 0xf0, 0x86, + 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, + 0x00, 0x0a, 0x00, 0x02, 0x56, 0x45, 0x20, 0x02, 0x58, 0x45, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, + 0x5c, 0x45, 0x00, 0x02, 0x4e, 0x49, 0x20, 0x02, 0x50, 0xc9, 0x40, 0x02, 0x52, 0x49, 0x60, 0x02, + 0x54, 0xc9, 0x00, 0x50, 0x4f, 0xe3, 0x00, 0x60, 0x51, 0xe3, 0x00, 0x70, 0x53, 0xe3, 0x00, 0x80, + 0x55, 0xe3, 0x00, 0x00, 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, 0xfa, 0x1d, 0x5b, 0x28, 0x41, 0x70, + 0xb0, 0x59, 0x24, 0xd7, 0x25, 0xc6, 0x04, 0x9b, 0xcf, 0x6e, 0x4c, 0xb0, 0x92, 0x6e, 0xbc, 0x6d, + 0xf3, 0x51, 0x51, 0x3a, 0x3e, 0x50, 0xdc, 0x56, 0xd4, 0xba, 0x64, 0x70, 0x0c, 0x00, 0x07, 0x9c, + 0xfd, 0x18, 0x86, 0x00, 0x02, 0x80, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, + 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xa0, 0x31, 0x4c, 0xc5, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, + 0xa8, 0x08, 0x89, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0x02, 0x56, + 0x45, 0x20, 0x02, 0x58, 0x45, 0x40, 0x02, 0x5a, 0xc5, 0x60, 0x02, 0x5c, 0x45, 0x18, 0x86, 0x00, + 0x02, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0x00, 0xe0, 0x54, + 0x63, 0x10, 0x89, 0x00, 0x82, 0x08, 0x89, 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, 0x74, 0x84, 0x00, + 0x82, 0x80, 0xb0, 0xaa, 0xe7, 0x80, 0xc0, 0xac, 0x67, 0x80, 0x5a, 0x83, 0xe7, 0x00, 0x6b, 0x85, + 0xe7, 0x80, 0x20, 0x86, 0xfd, 0x00, 0x11, 0x88, 0xe7, 0x00, 0x43, 0x88, 0x67, 0x01, 0x00, 0x40, + 0xa3, 0x00, 0x40, 0x88, 0xfb, 0x00, 0x32, 0x80, 0xe8, 0x08, 0x89, 0x00, 0x0a, 0x00, 0x00, 0x40, + 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x80, 0x73, 0x80, + 0x67, 0x00, 0x84, 0x82, 0xe7, 0x80, 0x94, 0x84, 0xe7, 0x00, 0x10, 0x86, 0x7d, 0x00, 0x31, 0x86, + 0xe7, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x03, 0x80, 0x67, 0x80, 0x00, 0x80, 0xe7, 0x00, 0x01, 0x80, + 0x7b, 0x00, 0x30, 0x86, 0x68, 0x48, 0x89, 0x00, 0x8a, 0x00, 0x74, 0x80, 0x67, 0x00, 0x95, 0x86, + 0x67, 0x00, 0x30, 0x86, 0x68, 0xfa, 0xad, 0x0d, 0x6c, 0x28, 0xb4, 0x04, 0x9e, 0xe5, 0xbc, 0xba, + 0xcd, 0xd1, 0x76, 0x08, 0x41, 0x36, 0x85, 0xe8, 0xbc, 0x36, 0x60, 0x68, 0xe8, 0x58, 0x22, 0xc1, + 0xae, 0x3f, 0x1e, 0xf7, 0x7f, 0x0e, 0x48, 0x0d, 0x00, 0x00, 0x00, 0x84, 0x00, 0x96, 0x80, 0xef, + 0x80, 0xa6, 0x82, 0xef, 0x00, 0xb7, 0x84, 0x6f, 0x00, 0x95, 0x86, 0xfb, 0x80, 0xc6, 0x88, 0xfb, + 0x00, 0x32, 0x86, 0x6f, 0x80, 0x00, 0x88, 0xfb, 0x00, 0x32, 0x86, 0x7d, 0x80, 0xa5, 0x88, 0xfb, + 0x00, 0xd7, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xef, 0x00, 0x11, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0xfd, + 0x80, 0x95, 0x8a, 0x7b, 0x00, 0xc7, 0x8c, 0x7b, 0x00, 0x53, 0x8a, 0xef, 0x00, 0x01, 0x8c, 0x7b, + 0x00, 0x53, 0x8c, 0xfd, 0x00, 0x81, 0x8e, 0x6f, 0x80, 0x63, 0x8a, 0x7d, 0x80, 0x52, 0x8e, 0x7b, + 0x80, 0x53, 0x8a, 0x7b, 0x80, 0x12, 0x8e, 0xfd, 0x80, 0x12, 0x8a, 0x7b, 0x00, 0x83, 0x8c, 0x6f, + 0x00, 0x21, 0x82, 0x7b, 0x00, 0x11, 0x84, 0x7b, 0x00, 0x61, 0x8c, 0x7d, 0x00, 0x60, 0x8c, 0xfd, + 0x00, 0x63, 0x82, 0x7b, 0x00, 0x13, 0x8c, 0x7b, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x80, 0x7b, + 0x00, 0x01, 0x80, 0x7d, 0x00, 0x43, 0x82, 0xef, 0x00, 0x03, 0x84, 0x6f, 0x80, 0x53, 0x8c, 0x6f, + 0x00, 0x61, 0x9a, 0xfb, 0x80, 0x32, 0x8a, 0xef, 0x80, 0x50, 0x98, 0x7d, 0x80, 0x43, 0x8e, 0x6f, + 0x00, 0x30, 0x82, 0x6f, 0x80, 0x70, 0x9c, 0x7b, 0x00, 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0xef, + 0x00, 0xa5, 0x82, 0x6f, 0x80, 0xb5, 0x84, 0x6f, 0x00, 0x95, 0x86, 0xef, 0x80, 0x31, 0x86, 0xfb, + 0x80, 0x95, 0x8e, 0xef, 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x81, 0x8c, 0xef, 0x80, 0x63, 0x8c, 0x7d, + 0xfa, 0x90, 0x3c, 0x2e, 0x4a, 0xe7, 0xc9, 0x5b, 0x18, 0x91, 0xc9, 0xd2, 0x5b, 0xc0, 0xa2, 0x37, + 0xa8, 0x14, 0xe4, 0x5a, 0xb5, 0x5c, 0xb5, 0x14, 0xdd, 0xbc, 0x88, 0x1b, 0x95, 0x48, 0xf7, 0x74, + 0x48, 0x20, 0x0e, 0x00, 0x63, 0x8a, 0xfb, 0x00, 0x53, 0x8c, 0xfb, 0x00, 0x13, 0x8a, 0x7d, 0x00, + 0x13, 0x8c, 0x7b, 0x00, 0x53, 0x8c, 0xef, 0x80, 0x51, 0x8a, 0xef, 0x00, 0x21, 0x86, 0xfb, 0x80, + 0x21, 0x84, 0xfb, 0x80, 0x83, 0x8e, 0x6f, 0x00, 0x71, 0x8e, 0x7d, 0x00, 0x70, 0x8e, 0xfd, 0x80, + 0x73, 0x86, 0xfb, 0x80, 0x71, 0x8e, 0xfb, 0x00, 0x00, 0x86, 0xfb, 0x00, 0x30, 0x80, 0xfb, 0x00, + 0x01, 0x80, 0x7d, 0x80, 0x03, 0x80, 0x6f, 0x00, 0x60, 0x8c, 0xfb, 0x80, 0xa5, 0x80, 0x6f, 0x00, + 0x00, 0x80, 0xfb, 0x80, 0x03, 0x8e, 0xef, 0x80, 0x53, 0x8a, 0x7d, 0x80, 0x00, 0x8e, 0xef, 0x80, + 0x73, 0x8e, 0x7b, 0x80, 0x73, 0x8e, 0x7b, 0x00, 0x50, 0x52, 0xe3, 0x00, 0x60, 0x54, 0xe3, 0x00, + 0x70, 0x56, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, + 0x00, 0x56, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xc0, 0x39, 0xeb, 0x00, + 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, + 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, + 0xe0, 0x7d, 0x24, 0xa8, 0x8a, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x58, 0x49, 0x20, + 0x05, 0x5a, 0x49, 0x40, 0x05, 0x5c, 0x49, 0x00, 0x00, 0x52, 0x23, 0x01, 0x00, 0x54, 0xa3, 0x00, + 0x00, 0x56, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xde, 0xf3, 0xfa, 0x95, 0x6e, 0x4b, 0x91, + 0x4e, 0xf9, 0x77, 0xf8, 0xc2, 0x64, 0x43, 0x28, 0xb8, 0xda, 0x59, 0x77, 0xd2, 0x94, 0x31, 0x97, + 0x48, 0x68, 0x92, 0xdb, 0x43, 0x75, 0x79, 0x66, 0x51, 0xd1, 0x92, 0xaf, 0xf8, 0x0e, 0x00, 0xf0, + 0x1e, 0xeb, 0x00, 0xd0, 0x3b, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, + 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, + 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0xf8, 0x8a, 0x00, 0x0a, 0x00, 0x01, + 0x7c, 0xa3, 0x00, 0xf0, 0x1e, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0xc0, 0x52, 0x67, 0x00, 0xd0, + 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x4c, 0x89, 0x00, 0x82, 0xfc, 0x89, 0x00, 0x02, 0x00, 0xc0, + 0x52, 0x67, 0x00, 0xd0, 0x54, 0xe7, 0x00, 0xe0, 0x56, 0x67, 0x01, 0xe0, 0x7d, 0x24, 0x2c, 0x8b, + 0x00, 0x8a, 0x00, 0x00, 0x7c, 0x23, 0x00, 0xe5, 0x95, 0xfd, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe5, + 0x95, 0xfd, 0x00, 0x05, 0x40, 0x45, 0x20, 0x05, 0x42, 0x45, 0x40, 0x05, 0x44, 0x45, 0x00, 0x07, + 0x80, 0x6f, 0x00, 0x17, 0x82, 0x6f, 0x00, 0xc1, 0x98, 0x6f, 0x00, 0xd1, 0x9a, 0x6f, 0x00, 0x06, + 0xbc, 0x68, 0xa0, 0x8b, 0x00, 0x0a, 0x80, 0x16, 0xbc, 0x68, 0xa0, 0x8b, 0x00, 0x0a, 0x00, 0x00, + 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x30, + 0x7e, 0xc5, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, + 0xb0, 0x24, 0x00, 0x6c, 0xad, 0xef, 0x00, 0x7c, 0xaf, 0xef, 0xc8, 0x97, 0x00, 0x82, 0x00, 0x10, + 0x53, 0xe3, 0x00, 0x20, 0x55, 0xe3, 0xfa, 0x4f, 0x4c, 0xe4, 0x5b, 0x18, 0x67, 0x46, 0xca, 0x88, + 0x1e, 0x14, 0x95, 0xc1, 0x0a, 0x3f, 0x60, 0x51, 0xe0, 0xf8, 0xae, 0x12, 0xe8, 0x80, 0xbf, 0x8e, + 0x62, 0x11, 0xf1, 0x72, 0xfc, 0xda, 0xe2, 0xd0, 0x0f, 0x00, 0x30, 0x57, 0xe3, 0x9c, 0x8c, 0x00, + 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, + 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0x80, 0x30, 0x50, 0x45, 0x00, 0x10, 0x59, 0xe3, 0x00, 0x20, 0x5b, + 0x63, 0x00, 0x30, 0x5d, 0xe3, 0xd8, 0x8a, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x94, 0x8c, 0x00, + 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0x00, 0x80, 0x68, 0x00, 0x60, 0x53, + 0x6f, 0x00, 0x70, 0x55, 0xef, 0x00, 0x80, 0x57, 0x6f, 0x00, 0x10, 0x59, 0xe3, 0x00, 0x20, 0x5b, + 0x63, 0x00, 0x30, 0x5d, 0xe3, 0x80, 0x06, 0x9a, 0xfd, 0x4c, 0x89, 0x00, 0x82, 0x20, 0x30, 0x7e, + 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xbf, 0xf9, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0xd8, 0x8a, 0x00, + 0x02, 0x00, 0x00, 0x40, 0xa8, 0x94, 0x8c, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0x94, 0x8c, 0x00, + 0x0a, 0x00, 0x60, 0x59, 0x63, 0x00, 0x70, 0x5b, 0x63, 0x00, 0x80, 0x5d, 0x63, 0x4c, 0x89, 0x00, + 0x82, 0x00, 0xc0, 0x52, 0xe3, 0x00, 0xd0, 0x54, 0x63, 0x00, 0xe0, 0x56, 0xe3, 0x9c, 0x8c, 0x00, + 0x02, 0x94, 0x8c, 0x00, 0x0a, 0x00, 0xe0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0xc0, 0xac, + 0xef, 0x80, 0xd0, 0xae, 0xef, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, 0x00, 0x40, + 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x30, 0x40, 0x45, 0x80, 0x30, 0x42, 0x45, 0x00, 0xa5, 0x86, + 0xef, 0xfa, 0x1d, 0x4e, 0x08, 0x6e, 0xd9, 0xe3, 0xeb, 0x07, 0xa8, 0xdc, 0x25, 0xa2, 0x75, 0x8f, + 0x94, 0x53, 0x5c, 0x3c, 0x3e, 0x65, 0x0d, 0x3d, 0x60, 0x43, 0x60, 0x16, 0x0a, 0xb8, 0xe9, 0xd7, + 0x15, 0x76, 0xa8, 0x10, 0x80, 0x35, 0x86, 0x6f, 0x80, 0x94, 0x84, 0x6f, 0x80, 0x24, 0x84, 0xef, + 0x80, 0xb5, 0x88, 0x6f, 0x80, 0x45, 0x8a, 0xef, 0x80, 0x04, 0x80, 0xef, 0x00, 0x02, 0x80, 0x6f, + 0x80, 0x12, 0x82, 0xef, 0x80, 0x00, 0x80, 0x7b, 0x00, 0x01, 0x80, 0x7b, 0x80, 0x01, 0x80, 0x68, + 0x00, 0x00, 0x00, 0x84, 0x60, 0x32, 0x40, 0xc5, 0x00, 0x08, 0x80, 0xe7, 0x00, 0x08, 0x83, 0xe7, + 0x00, 0x10, 0x82, 0xfb, 0x01, 0x00, 0x40, 0xa3, 0x00, 0x10, 0x82, 0xfb, 0x00, 0x18, 0x82, 0xe7, + 0x98, 0x84, 0x00, 0x02, 0x00, 0x10, 0x62, 0x63, 0x01, 0x00, 0x44, 0x23, 0x00, 0x20, 0x84, 0x70, + 0x00, 0x01, 0x84, 0x62, 0x00, 0x00, 0x00, 0x84, 0xc0, 0x32, 0x68, 0xc5, 0xe0, 0x32, 0x6a, 0xc5, + 0xa0, 0x32, 0x6c, 0x45, 0x00, 0x64, 0x8b, 0x67, 0x80, 0x53, 0x8a, 0x7b, 0x00, 0x66, 0x8d, 0xe7, + 0x80, 0x65, 0x8c, 0x7b, 0x00, 0x53, 0x80, 0x67, 0x80, 0x96, 0x82, 0x67, 0x00, 0x86, 0x84, 0x67, + 0x80, 0x54, 0x86, 0xfb, 0x80, 0x66, 0x88, 0xfb, 0x00, 0x32, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, + 0x00, 0x32, 0x86, 0x7d, 0x00, 0x54, 0x88, 0xfb, 0x00, 0x66, 0x8a, 0xfb, 0x80, 0x42, 0x88, 0x67, + 0x00, 0x01, 0x8a, 0x7b, 0x80, 0x42, 0x88, 0xfd, 0x00, 0x94, 0x8a, 0x7b, 0x00, 0xd6, 0x96, 0xfb, + 0x80, 0x55, 0x8a, 0xe7, 0x00, 0x11, 0x96, 0x7b, 0x80, 0x55, 0x8a, 0x7d, 0x00, 0x42, 0x99, 0xe7, + 0x00, 0x51, 0x97, 0xe7, 0x00, 0xb6, 0x98, 0x7b, 0x00, 0x16, 0x96, 0xfd, 0xfa, 0xa0, 0xce, 0xa3, + 0xba, 0x23, 0x5b, 0x6a, 0xa8, 0x3c, 0x45, 0x2d, 0x9c, 0x38, 0xa0, 0xd4, 0xa3, 0xba, 0xf1, 0x7f, + 0x10, 0x32, 0x9b, 0x34, 0x49, 0x00, 0x2d, 0x8a, 0xef, 0x39, 0x9d, 0x16, 0x23, 0x80, 0x11, 0x00, + 0x16, 0x98, 0x7b, 0x00, 0xb6, 0x9a, 0x67, 0x00, 0x00, 0x82, 0x7b, 0x00, 0x10, 0x82, 0xfb, 0x00, + 0x41, 0x85, 0x67, 0x00, 0x52, 0x89, 0xe7, 0x00, 0x11, 0x82, 0x7b, 0x00, 0x01, 0x84, 0xfd, 0x00, + 0x41, 0x85, 0x67, 0x00, 0x41, 0x88, 0x7b, 0x00, 0x12, 0x80, 0x67, 0x00, 0xd0, 0x9a, 0xfb, 0x00, + 0x52, 0x80, 0xe7, 0x80, 0x35, 0x96, 0x67, 0x00, 0xb0, 0x96, 0xfd, 0x80, 0x30, 0x80, 0xe7, 0x00, + 0x56, 0x98, 0x67, 0x00, 0xc0, 0x98, 0xfb, 0x00, 0x66, 0xad, 0x67, 0x00, 0xbb, 0x96, 0x7d, 0x00, + 0x00, 0x00, 0x84, 0x80, 0x94, 0x80, 0x67, 0x00, 0x04, 0x80, 0xe7, 0x60, 0x32, 0x42, 0x45, 0x80, + 0x13, 0x82, 0xe7, 0x00, 0x14, 0x82, 0x7b, 0x00, 0x14, 0x82, 0xe7, 0x80, 0x73, 0x84, 0xe7, 0x00, + 0x11, 0x82, 0x7b, 0x80, 0x13, 0x82, 0xe7, 0x80, 0x00, 0x80, 0xe8, 0x00, 0x00, 0x00, 0x84, 0x00, + 0x74, 0x80, 0xfb, 0x00, 0x95, 0x82, 0x7d, 0x00, 0x10, 0x82, 0x67, 0x00, 0x74, 0x80, 0xfd, 0x00, + 0x95, 0x84, 0x7b, 0x00, 0x20, 0x84, 0x67, 0x00, 0x11, 0x86, 0xfb, 0x80, 0x31, 0x86, 0x67, 0x00, + 0x11, 0x88, 0x7d, 0x00, 0x42, 0x88, 0xe7, 0x00, 0x36, 0x92, 0x67, 0x00, 0xb2, 0x94, 0x67, 0x00, + 0x00, 0x00, 0x84, 0x00, 0x74, 0x82, 0x7b, 0x80, 0x10, 0x82, 0xe7, 0x00, 0x74, 0x84, 0x7d, 0x00, + 0x21, 0x84, 0xe7, 0x00, 0x11, 0x8e, 0xe7, 0x00, 0x11, 0x82, 0x7d, 0x80, 0x60, 0x86, 0xe7, 0x00, + 0x31, 0x86, 0x7b, 0x80, 0x11, 0x90, 0x67, 0xfa, 0x89, 0xc6, 0xf4, 0xce, 0xb6, 0x79, 0x08, 0x65, + 0x13, 0xf0, 0x31, 0xe3, 0x5a, 0x78, 0x26, 0x64, 0xab, 0xbf, 0xfe, 0x59, 0xa5, 0xad, 0x4d, 0xe0, + 0x3f, 0x7f, 0x3d, 0x16, 0xcd, 0xf5, 0x35, 0xae, 0x58, 0x12, 0x00, 0x00, 0x00, 0x84, 0x80, 0x32, + 0x4c, 0x45, 0x00, 0xb0, 0x52, 0x63, 0x00, 0xc0, 0x54, 0xe3, 0x01, 0x00, 0x4e, 0x23, 0x00, 0x00, + 0x50, 0xa3, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0x00, 0xf6, 0xf3, 0x00, 0xb0, 0x37, 0xeb, 0x00, 0xd0, + 0x3b, 0xeb, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, + 0x00, 0x02, 0x00, 0x90, 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0x78, 0x8e, + 0x00, 0x0a, 0x00, 0x01, 0x7c, 0xa3, 0x00, 0xb0, 0x37, 0xeb, 0x00, 0xc0, 0x39, 0xeb, 0x00, 0x90, + 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x00, 0x8e, 0x00, 0x82, 0x34, 0x8e, 0x00, 0x02, 0x00, 0x90, + 0x4e, 0xe7, 0x00, 0xa0, 0x50, 0xe7, 0x01, 0xe0, 0x7d, 0x24, 0xa4, 0x8e, 0x00, 0x8a, 0x00, 0x00, + 0x00, 0x84, 0x00, 0x76, 0x80, 0xe7, 0x00, 0xb4, 0x82, 0xe7, 0x00, 0x86, 0x84, 0x67, 0x60, 0x32, + 0x4c, 0xc5, 0x00, 0x63, 0x86, 0xfb, 0x00, 0x31, 0x86, 0xe7, 0x80, 0x00, 0x88, 0xfb, 0x80, 0x41, + 0x88, 0xfb, 0x80, 0xb3, 0x8a, 0x67, 0x00, 0x51, 0x8a, 0x7b, 0x80, 0x42, 0x88, 0x67, 0x00, 0x31, + 0x86, 0xe7, 0x80, 0x41, 0x88, 0xfd, 0x00, 0x45, 0x88, 0x67, 0x80, 0x00, 0x82, 0xfd, 0x80, 0x10, + 0x82, 0xe7, 0x80, 0x14, 0x82, 0x67, 0x80, 0x40, 0x92, 0xfd, 0x80, 0xd6, 0x86, 0xfb, 0x00, 0x34, + 0x86, 0xe7, 0x00, 0x35, 0x86, 0x67, 0x00, 0x30, 0x8e, 0xe7, 0x00, 0x31, 0x90, 0x67, 0x00, 0x00, + 0x00, 0x84, 0xfa, 0x25, 0x4e, 0x29, 0x14, 0x61, 0x53, 0x9e, 0x66, 0x14, 0x36, 0xd4, 0xbe, 0x79, + 0x80, 0x70, 0xde, 0xce, 0x29, 0x73, 0x48, 0xee, 0x63, 0x23, 0xe3, 0x0f, 0x4d, 0x51, 0x44, 0x16, + 0x68, 0x53, 0x65, 0x30, 0x13, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0x00, 0x42, + 0xa3, 0x00, 0xe0, 0x45, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x47, 0xe5, 0x20, 0xe0, 0x7d, + 0x22, 0x00, 0xe0, 0x49, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4b, 0xe5, 0x20, 0xe0, 0x7d, + 0x22, 0x00, 0xe0, 0x4d, 0xe5, 0x00, 0x20, 0x04, 0xf9, 0x00, 0x30, 0x06, 0xf9, 0x00, 0x40, 0x08, + 0xf9, 0x00, 0x50, 0x0a, 0xf9, 0x00, 0x60, 0x0c, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x11, 0x02, + 0xfd, 0x80, 0x21, 0x04, 0x7d, 0x00, 0x32, 0x06, 0xfd, 0x80, 0x42, 0x08, 0x7d, 0x00, 0x53, 0x0a, + 0x7d, 0x00, 0x60, 0x0c, 0xf3, 0x00, 0x00, 0x00, 0x84, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, + 0x22, 0x00, 0x40, 0x44, 0xe5, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x20, 0x2c, 0x63, 0x01, 0x60, 0x6b, + 0x22, 0x00, 0x00, 0x42, 0xa3, 0x04, 0x54, 0xe1, 0x35, 0x88, 0x90, 0x00, 0x9c, 0xff, 0x00, 0x40, + 0x23, 0x00, 0x00, 0xa3, 0xe2, 0x02, 0x10, 0x41, 0x28, 0x94, 0x90, 0x00, 0x8a, 0x00, 0x00, 0x21, + 0xf5, 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0x21, 0xf5, 0x00, 0x00, 0xa3, 0xe2, 0x00, 0x20, 0x84, + 0x62, 0x00, 0x11, 0x41, 0xe8, 0xa0, 0x90, 0x00, 0x0a, 0x05, 0x54, 0xf3, 0xb5, 0x88, 0x90, 0x00, + 0x9c, 0x00, 0x03, 0x72, 0xc9, 0x05, 0x54, 0xc1, 0x39, 0x88, 0x90, 0x00, 0x9c, 0x00, 0x60, 0x6b, + 0xe3, 0x00, 0x54, 0xf5, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x01, 0x54, 0xef, 0xb5, 0xfa, 0xf7, 0x32, + 0x43, 0xc2, 0x52, 0x28, 0xdb, 0xaa, 0xb7, 0x2a, 0x46, 0x86, 0x68, 0xcb, 0x47, 0x38, 0x54, 0x4b, + 0x36, 0x34, 0xa4, 0xad, 0xcb, 0xd7, 0x90, 0xbb, 0x4e, 0x54, 0xc1, 0xe2, 0xfe, 0x3f, 0x08, 0x14, + 0x88, 0x90, 0x00, 0x9c, 0x02, 0x54, 0xfb, 0xb5, 0x88, 0x90, 0x00, 0x9c, 0x03, 0x54, 0xfd, 0x35, + 0x88, 0x90, 0x00, 0x9c, 0x05, 0x54, 0xc1, 0x39, 0x88, 0x90, 0x00, 0x9c, 0x60, 0x31, 0x7e, 0x45, + 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, + 0x00, 0xd0, 0xbb, 0xfb, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x71, 0xaf, 0xe8, 0x00, 0xe1, 0xbd, 0xe8, + 0x00, 0x7f, 0xa9, 0x68, 0xe0, 0x03, 0x74, 0x49, 0x00, 0x04, 0x7a, 0xc9, 0xa0, 0x00, 0x60, 0xc5, + 0x00, 0x00, 0x21, 0xf9, 0xc0, 0x00, 0x62, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, + 0x94, 0x81, 0x00, 0x98, 0x05, 0x54, 0xc1, 0x39, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, + 0x12, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x00, 0x84, + 0x6c, 0x90, 0x00, 0x82, 0xf2, 0x00, 0x40, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x6c, 0x90, 0x00, 0x82, + 0xf4, 0x00, 0x40, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x6c, 0x90, 0x00, 0x82, 0xf6, 0x00, 0x40, 0x23, + 0x94, 0x81, 0x00, 0x98, 0x00, 0x00, 0xce, 0x73, 0x00, 0x00, 0xd0, 0x73, 0x00, 0x00, 0xd2, 0xf3, + 0x00, 0x00, 0xd4, 0xf3, 0x00, 0x70, 0xc0, 0xe3, 0x0c, 0x40, 0xc1, 0xa5, 0x4c, 0xa3, 0x00, 0x02, + 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x40, 0x23, 0x94, 0x81, 0x00, 0x98, 0x30, 0x8f, 0x00, 0x02, + 0x08, 0x00, 0x56, 0x23, 0x12, 0x00, 0x58, 0x23, 0xfa, 0xbf, 0x3a, 0x64, 0xef, 0x09, 0xa8, 0x97, + 0x10, 0xf8, 0xfa, 0x0e, 0xe3, 0x9e, 0xbe, 0x47, 0x45, 0xa5, 0x8a, 0xd9, 0xe9, 0x17, 0x32, 0x7f, + 0xee, 0xbf, 0x06, 0xbd, 0xd9, 0xa7, 0x76, 0x49, 0x42, 0xe0, 0x14, 0x78, 0x8f, 0x00, 0x02, 0x01, + 0xc0, 0x58, 0x24, 0xe0, 0x90, 0x00, 0x8a, 0x00, 0x10, 0xc0, 0xe9, 0x01, 0xb0, 0x56, 0x24, 0xdc, + 0x90, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x70, + 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, 0x30, 0x8f, 0x00, 0x02, 0x80, 0x00, 0x5e, 0xa3, 0x00, + 0xf0, 0x1e, 0xf3, 0x00, 0xf0, 0x1e, 0xf3, 0x00, 0xf0, 0x1e, 0xf3, 0x12, 0xb0, 0x56, 0xa4, 0x80, + 0xb7, 0xa0, 0x62, 0x44, 0x91, 0x00, 0x8a, 0x12, 0x00, 0x58, 0x23, 0x78, 0x8f, 0x00, 0x02, 0x01, + 0xc0, 0x58, 0x24, 0x30, 0x91, 0x00, 0x8a, 0x00, 0x10, 0xc0, 0xe9, 0x20, 0x91, 0x00, 0x18, 0x12, + 0xb0, 0x56, 0xa2, 0x88, 0x91, 0x00, 0x08, 0x12, 0x00, 0x58, 0x23, 0x80, 0xc5, 0x58, 0xe4, 0x78, + 0x8f, 0x00, 0x02, 0x01, 0xb0, 0x56, 0x24, 0x54, 0x91, 0x00, 0x0a, 0x01, 0xc0, 0x40, 0x28, 0x9c, + 0x91, 0x00, 0x08, 0x04, 0x00, 0x44, 0x23, 0x00, 0x20, 0x04, 0xf5, 0x00, 0x11, 0x02, 0xfd, 0x00, + 0x20, 0x04, 0xf3, 0x01, 0xc0, 0x58, 0x24, 0x70, 0x91, 0x00, 0x0a, 0x80, 0x10, 0x82, 0x24, 0xac, + 0x91, 0x00, 0x98, 0x00, 0x00, 0x42, 0xa3, 0x8a, 0x00, 0x46, 0xa3, 0x80, 0x11, 0xc2, 0xe2, 0x80, + 0x10, 0x82, 0x24, 0xac, 0x91, 0x00, 0x98, 0x84, 0x00, 0x44, 0xa3, 0x00, 0x20, 0x04, 0xf5, 0x00, + 0x11, 0x02, 0xfd, 0xac, 0x91, 0x00, 0x98, 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf6, 0x71, 0x00, + 0x00, 0xc0, 0x2d, 0xfa, 0x25, 0x6b, 0x12, 0x07, 0x27, 0x6b, 0x6c, 0x66, 0xa9, 0xf3, 0x54, 0x8d, + 0x3b, 0x9f, 0xbc, 0xee, 0x42, 0xef, 0x21, 0x48, 0x01, 0xff, 0x8d, 0x50, 0x2b, 0x13, 0x51, 0x52, + 0xde, 0x01, 0xc4, 0x33, 0xb8, 0x15, 0x00, 0x70, 0xce, 0xeb, 0x00, 0x70, 0xd2, 0x6b, 0x00, 0x70, + 0xc0, 0xe3, 0x0c, 0xb0, 0xc1, 0xa5, 0x04, 0x00, 0x42, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, 0x10, + 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xd0, 0x91, 0x00, 0x0a, 0x80, 0x10, 0x82, 0x24, 0x00, 0x10, + 0xc0, 0xe9, 0x00, 0x00, 0xf8, 0xf1, 0x60, 0x31, 0x7e, 0x45, 0x80, 0xcd, 0xb7, 0xf9, 0x00, 0x00, + 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x40, 0x31, 0x7e, 0xc5, 0xc0, 0x31, + 0x6a, 0x45, 0xe0, 0x31, 0x6c, 0xc5, 0xdc, 0x87, 0x00, 0x02, 0x01, 0x00, 0x42, 0x23, 0x80, 0x50, + 0xab, 0xe2, 0x00, 0x50, 0x2b, 0xed, 0x80, 0x6a, 0xad, 0xe4, 0x00, 0x60, 0x2d, 0xf9, 0x20, 0x03, + 0x6c, 0x49, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, + 0x7c, 0xa2, 0x00, 0xe0, 0x6b, 0x65, 0x00, 0x50, 0x2b, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, + 0x69, 0xe5, 0x00, 0x40, 0x29, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x67, 0x65, 0x00, 0x30, + 0x27, 0xf9, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x20, 0x25, 0xf9, 0x00, 0x00, + 0x00, 0x84, 0x00, 0x00, 0x4c, 0x23, 0x00, 0x60, 0x8a, 0x70, 0x60, 0xb0, 0x92, 0x22, 0x1f, 0xb0, + 0x90, 0x22, 0x20, 0x00, 0x4e, 0x23, 0x00, 0x74, 0x50, 0xe4, 0x00, 0x80, 0x4e, 0xe3, 0x00, 0x70, + 0x0e, 0x63, 0x00, 0x70, 0x0e, 0x63, 0x00, 0x70, 0x0e, 0x63, 0x01, 0x70, 0x4e, 0x24, 0xfa, 0xbf, + 0x09, 0xf5, 0x98, 0xca, 0x99, 0xbb, 0xdc, 0xe4, 0xed, 0x15, 0x8c, 0xed, 0x4b, 0x76, 0xd0, 0x89, + 0x5f, 0xd1, 0x0e, 0xed, 0x4c, 0x60, 0xd3, 0x14, 0xe7, 0x48, 0xc9, 0xb9, 0x40, 0xab, 0x72, 0x90, + 0x16, 0x00, 0x53, 0x0a, 0x7d, 0x01, 0x80, 0x50, 0x24, 0x90, 0x92, 0x00, 0x8a, 0x00, 0x00, 0x00, + 0x84, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, 0x63, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, + 0xa2, 0x00, 0xe0, 0x67, 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, + 0xf9, 0x00, 0x20, 0x25, 0xf9, 0x00, 0x03, 0x68, 0x45, 0x20, 0x03, 0x6a, 0x45, 0x40, 0xb0, 0x7a, + 0xa2, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0x00, 0xc0, + 0x2d, 0x64, 0x92, 0x00, 0x82, 0x20, 0x90, 0x40, 0x28, 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, + 0xe3, 0xac, 0x93, 0x00, 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x67, + 0x65, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x65, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, 0x20, 0x25, + 0xf9, 0x00, 0x03, 0x68, 0x45, 0x20, 0x03, 0x6a, 0x45, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x20, 0xe1, + 0x6b, 0x80, 0x00, 0x7a, 0xa3, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, + 0x98, 0x2c, 0x92, 0x00, 0x82, 0x00, 0x20, 0xe1, 0x6b, 0x80, 0xd0, 0x7b, 0x22, 0x00, 0x00, 0x40, + 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x70, 0x81, 0x00, 0x02, 0x00, 0x00, 0x56, + 0x63, 0x80, 0xd5, 0x7b, 0xe2, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, 0x63, 0x00, 0xd0, 0x3b, + 0x63, 0x2c, 0x92, 0x00, 0x82, 0x80, 0xb0, 0x40, 0xa8, 0xfa, 0x8b, 0x7c, 0x62, 0x3d, 0x03, 0x28, + 0xfc, 0x9d, 0x3a, 0xee, 0xab, 0xfa, 0xd3, 0x46, 0x0e, 0xbf, 0x90, 0xfb, 0x33, 0x69, 0x29, 0x9b, + 0xc2, 0x6f, 0xe2, 0x73, 0x9f, 0xa0, 0xa1, 0xd0, 0x06, 0x92, 0x68, 0x17, 0xdc, 0x93, 0x00, 0x08, + 0x64, 0x92, 0x00, 0x82, 0x60, 0x90, 0x40, 0xa8, 0xb8, 0x93, 0x00, 0x88, 0x00, 0xd0, 0x65, 0xe3, + 0x40, 0x90, 0x40, 0x28, 0xac, 0x93, 0x00, 0x88, 0x00, 0x00, 0x66, 0xa3, 0x20, 0x90, 0x40, 0x28, + 0xa0, 0x93, 0x00, 0x88, 0x00, 0x00, 0x68, 0x23, 0x80, 0x52, 0xab, 0x62, 0x80, 0x53, 0xeb, 0x62, + 0xf8, 0x93, 0x00, 0x98, 0x80, 0x42, 0xa9, 0x62, 0x80, 0x43, 0xe9, 0x62, 0xf8, 0x93, 0x00, 0x98, + 0x80, 0x32, 0xa7, 0x62, 0x80, 0x33, 0xe7, 0x62, 0xf8, 0x93, 0x00, 0x98, 0x80, 0x22, 0xa5, 0x62, + 0x80, 0x23, 0xe5, 0x62, 0x10, 0xb0, 0x90, 0x22, 0xd0, 0x93, 0x00, 0x8a, 0x80, 0x2e, 0xa5, 0x64, + 0xf8, 0x93, 0x00, 0x98, 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x6a, 0xa3, 0xec, 0x93, 0x00, 0x98, + 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x6a, 0xa3, 0xff, 0x00, 0x4e, 0xa3, 0x80, 0x53, 0xeb, 0x62, + 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x66, 0xa3, 0x00, 0xd0, 0x65, 0xe3, 0x60, 0x31, 0x7e, 0x45, + 0x00, 0x20, 0xe1, 0x6b, 0x00, 0x00, 0x21, 0xf9, 0x00, 0x10, 0x23, 0xf9, 0x80, 0x08, 0xb3, 0x79, + 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x94, 0x81, 0x00, 0x98, 0x60, 0x31, 0x7e, 0x45, + 0xe0, 0x03, 0x74, 0x45, 0x00, 0x04, 0x44, 0x45, 0x80, 0xac, 0x83, 0xff, 0x80, 0x2c, 0x84, 0xff, + 0x80, 0xb0, 0x87, 0x7b, 0x00, 0x31, 0x86, 0x7b, 0x40, 0x03, 0x46, 0xc9, 0x40, 0x31, 0x7e, 0xc5, + 0xa0, 0x31, 0x4c, 0xc5, 0xfa, 0x42, 0xc9, 0xcd, 0xe2, 0x74, 0xb4, 0x3a, 0x9e, 0x8a, 0x29, 0xa5, + 0xf3, 0x2d, 0x4e, 0x05, 0x47, 0xf5, 0x36, 0x6c, 0x5b, 0x4e, 0x88, 0x7b, 0x0c, 0x67, 0x92, 0xf0, + 0x20, 0x73, 0xe6, 0xce, 0x6d, 0x40, 0x18, 0x00, 0x03, 0x58, 0x45, 0x00, 0xc0, 0x18, 0xf9, 0x10, + 0x85, 0x00, 0x82, 0x00, 0x10, 0xbc, 0x28, 0x10, 0x95, 0x00, 0x8a, 0x01, 0x00, 0x5a, 0x23, 0x00, + 0xb6, 0x9c, 0x67, 0x00, 0x90, 0x79, 0xe3, 0xa4, 0x86, 0x00, 0x82, 0x60, 0x03, 0x4e, 0xc9, 0x80, + 0x03, 0x50, 0x49, 0xa0, 0x03, 0x52, 0x49, 0xc0, 0x03, 0x54, 0x49, 0x40, 0x03, 0x78, 0x45, 0xc0, + 0x31, 0x56, 0x45, 0xe0, 0x31, 0x58, 0x45, 0x01, 0x00, 0x5a, 0x23, 0x00, 0xb6, 0x9c, 0x67, 0xa4, + 0x86, 0x00, 0x82, 0x60, 0x03, 0x56, 0xc5, 0x80, 0x03, 0x58, 0xc5, 0xa0, 0x03, 0x5a, 0xc5, 0xc0, + 0x03, 0x5c, 0xc5, 0x00, 0x00, 0x40, 0x23, 0x80, 0x05, 0x96, 0xfd, 0x00, 0x07, 0x9c, 0xfd, 0x18, + 0x86, 0x00, 0x02, 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0xe4, + 0x84, 0x00, 0x82, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x20, 0x03, 0x48, 0x45, 0xff, + 0x0f, 0x7e, 0xa3, 0x00, 0xf0, 0x41, 0x28, 0x00, 0x82, 0x84, 0xe8, 0x18, 0x95, 0x00, 0x0a, 0x00, + 0xf0, 0x41, 0x28, 0x00, 0x82, 0x84, 0xe8, 0x18, 0x95, 0x00, 0x0a, 0xc3, 0x00, 0x44, 0xa3, 0x00, + 0xe0, 0x45, 0x69, 0x10, 0x00, 0x7c, 0x22, 0x40, 0x03, 0x4a, 0xc5, 0x00, 0x40, 0x08, 0xf9, 0x00, + 0xe0, 0x49, 0x69, 0x20, 0xe0, 0x7d, 0x22, 0x00, 0xe0, 0x4b, 0xe9, 0x00, 0x00, 0x40, 0x23, 0x50, + 0x00, 0x42, 0xa3, 0x2c, 0x95, 0x00, 0x98, 0x36, 0x00, 0x40, 0x23, 0x1c, 0x95, 0x00, 0x98, 0xfa, + 0x60, 0x57, 0x2b, 0x67, 0x8c, 0xa7, 0xb6, 0xe5, 0x37, 0x0c, 0x47, 0x58, 0x66, 0x71, 0x45, 0x1b, + 0xa5, 0x0d, 0x79, 0xe9, 0x36, 0xb5, 0x93, 0x75, 0x1d, 0x58, 0x94, 0x99, 0xa6, 0xb7, 0x0e, 0xa4, + 0x18, 0x19, 0x36, 0x00, 0x40, 0x23, 0x3c, 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x01, 0x00, + 0x42, 0x23, 0x2c, 0x95, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x94, 0x81, + 0x00, 0x98, 0x00, 0x00, 0x8c, 0x67, 0x00, 0x63, 0x8c, 0xfb, 0x01, 0x00, 0x7c, 0xa3, 0x00, 0x6f, + 0x8e, 0x7b, 0x00, 0x70, 0xbc, 0x28, 0x6c, 0x96, 0x00, 0x88, 0x60, 0x32, 0x50, 0x45, 0x00, 0x00, + 0x7c, 0x23, 0x00, 0xe4, 0x93, 0x7d, 0x00, 0x83, 0x90, 0x67, 0x80, 0x73, 0x94, 0x67, 0x80, 0xa3, + 0x96, 0x67, 0x80, 0x84, 0x90, 0x67, 0x00, 0x85, 0x90, 0xfb, 0x80, 0x84, 0x90, 0x67, 0x80, 0xb5, + 0x98, 0x67, 0x00, 0xc6, 0x94, 0x67, 0x80, 0xc5, 0x98, 0xe7, 0x00, 0xc4, 0x98, 0xe7, 0x00, 0xa6, + 0x94, 0x67, 0x00, 0xa0, 0x42, 0x63, 0xac, 0x83, 0x00, 0x02, 0x00, 0x21, 0x84, 0xe7, 0x00, 0x21, + 0x84, 0xe7, 0x00, 0x25, 0x9a, 0x67, 0x00, 0xd6, 0x9a, 0x67, 0x00, 0x32, 0x7c, 0xc5, 0x00, 0xdf, + 0x9c, 0x67, 0x80, 0xd6, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa4, 0x88, 0x68, 0xc0, 0x95, + 0x00, 0x0a, 0x00, 0xd0, 0x42, 0xe3, 0xc8, 0x95, 0x00, 0x98, 0x00, 0xe0, 0x42, 0xe3, 0xc8, 0x95, + 0x00, 0x98, 0x00, 0x93, 0x84, 0xe7, 0x00, 0xd0, 0x86, 0xe7, 0x01, 0xe0, 0x89, 0xa4, 0x00, 0x32, + 0x86, 0xe7, 0x00, 0x3f, 0x88, 0xe7, 0x00, 0x83, 0x8c, 0xe7, 0x80, 0x31, 0x94, 0x67, 0x80, 0xa5, + 0x94, 0xe7, 0x00, 0xa3, 0xbc, 0xfd, 0x00, 0xe0, 0xbd, 0xa8, 0xfa, 0xae, 0x24, 0xaf, 0xf5, 0xbb, + 0xcd, 0x4c, 0xfe, 0x13, 0xe1, 0xad, 0xa4, 0xd5, 0x2f, 0x40, 0xf8, 0xb6, 0x20, 0xf3, 0x49, 0xc4, + 0xaf, 0xab, 0x92, 0x96, 0xdc, 0x3d, 0x14, 0x6d, 0x05, 0xd7, 0x10, 0xf0, 0x19, 0xfc, 0x95, 0x00, + 0x0a, 0x00, 0x30, 0x40, 0xe3, 0x04, 0x96, 0x00, 0x98, 0x00, 0x40, 0x40, 0x63, 0x04, 0x96, 0x00, + 0x98, 0x80, 0x10, 0x94, 0x67, 0x80, 0xa5, 0x94, 0xe7, 0x00, 0xa4, 0xbc, 0x7d, 0x00, 0xe0, 0xbd, + 0xa8, 0x20, 0x96, 0x00, 0x8a, 0x00, 0x90, 0x46, 0xe3, 0x28, 0x96, 0x00, 0x18, 0x00, 0x20, 0x46, + 0x63, 0x28, 0x96, 0x00, 0x18, 0x38, 0x96, 0x00, 0x8a, 0x00, 0x10, 0x44, 0xe3, 0x01, 0x00, 0x7c, + 0xa3, 0x44, 0x96, 0x00, 0x18, 0x00, 0x00, 0x44, 0x63, 0x00, 0x00, 0x7c, 0x23, 0x44, 0x96, 0x00, + 0x18, 0x00, 0x00, 0x40, 0x23, 0x00, 0x01, 0x82, 0xfd, 0x01, 0x00, 0x50, 0x23, 0x00, 0x24, 0x8c, + 0x62, 0x00, 0xe3, 0xbd, 0x68, 0x64, 0x96, 0x00, 0x08, 0x00, 0x10, 0x56, 0xe3, 0x6c, 0x96, 0x00, + 0x18, 0x00, 0x20, 0x56, 0xe3, 0x6c, 0x96, 0x00, 0x18, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xc4, + 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, 0x02, 0x00, 0x70, 0xbc, + 0x28, 0x70, 0x96, 0x00, 0x08, 0x80, 0xb3, 0x9a, 0xe7, 0x00, 0x30, 0x56, 0x63, 0x00, 0x70, 0x58, + 0x63, 0x00, 0x00, 0x00, 0x84, 0x40, 0x31, 0x7e, 0xc5, 0x00, 0x05, 0x42, 0xc5, 0x00, 0x00, 0xc4, + 0x73, 0xb4, 0xa3, 0x00, 0x82, 0x38, 0x95, 0x00, 0x02, 0x00, 0x70, 0xbc, 0x28, 0x98, 0x96, 0x00, + 0x08, 0x00, 0x33, 0x7c, 0x45, 0x00, 0x3f, 0x94, 0x67, 0x80, 0x75, 0x9a, 0xe7, 0x80, 0x33, 0x98, + 0x7d, 0x80, 0x33, 0x9c, 0xfb, 0xfa, 0x52, 0xf1, 0x0e, 0x19, 0x83, 0xc9, 0x13, 0x62, 0xb2, 0x16, + 0x4e, 0x70, 0x3b, 0x56, 0x7e, 0xb0, 0x76, 0x5b, 0x98, 0x08, 0x6d, 0x96, 0x91, 0x11, 0x78, 0x41, + 0xb2, 0x84, 0x9c, 0x40, 0xa7, 0x00, 0xc8, 0x1a, 0x00, 0xd7, 0x80, 0x67, 0x00, 0x00, 0xbc, 0xa8, + 0x98, 0x96, 0x00, 0x08, 0x00, 0xa7, 0x96, 0x67, 0x80, 0xc6, 0x98, 0xe7, 0x00, 0xb6, 0x9c, 0x67, + 0x00, 0xb0, 0x96, 0x67, 0x00, 0xc0, 0x98, 0x67, 0x00, 0x00, 0x9a, 0xe7, 0x00, 0x00, 0x00, 0x84, + 0x00, 0x08, 0x8d, 0xef, 0x00, 0x06, 0x8f, 0xef, 0x80, 0x63, 0x8c, 0x6f, 0x00, 0x60, 0x42, 0x63, + 0xa4, 0x82, 0x00, 0x02, 0x00, 0x30, 0x52, 0xe3, 0x80, 0x93, 0x92, 0x6f, 0x00, 0x31, 0x40, 0xc5, + 0x00, 0x90, 0x94, 0xef, 0x80, 0x94, 0x90, 0x6f, 0x00, 0x88, 0x90, 0x6f, 0x00, 0x86, 0x80, 0xe8, + 0x00, 0x90, 0x54, 0xef, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x68, 0xe3, 0x20, 0x31, 0x40, 0x45, + 0x60, 0x30, 0x42, 0xc5, 0x80, 0x30, 0x44, 0x45, 0x00, 0x4a, 0x97, 0x6f, 0x80, 0x05, 0x96, 0xef, + 0x80, 0xb5, 0x98, 0xef, 0x80, 0xc5, 0x98, 0x7b, 0x01, 0x00, 0x48, 0x23, 0x00, 0xc2, 0x9a, 0xfb, + 0x80, 0x26, 0x9a, 0x6f, 0x00, 0x00, 0x48, 0xa3, 0x00, 0x46, 0x9c, 0xfd, 0x00, 0xc0, 0x80, 0xa8, + 0x00, 0xe0, 0x40, 0x6f, 0x00, 0x17, 0x9c, 0x6f, 0x80, 0xd6, 0x98, 0xef, 0x00, 0xe7, 0xa0, 0x6f, + 0x00, 0x18, 0x9e, 0xef, 0x80, 0xc7, 0x98, 0xfb, 0x80, 0xc6, 0x98, 0x6f, 0x00, 0x07, 0xa1, 0x6f, + 0x00, 0x28, 0x9e, 0xef, 0x80, 0xc7, 0x98, 0xfb, 0x80, 0xb6, 0xa2, 0xef, 0xf0, 0x96, 0x00, 0x82, + 0x00, 0xba, 0xa4, 0x6f, 0x00, 0x25, 0xa5, 0xef, 0x00, 0xd0, 0x62, 0x6f, 0x00, 0xa0, 0x64, 0xef, + 0xfa, 0xb6, 0x3f, 0x62, 0x25, 0xbd, 0x58, 0x10, 0x06, 0xd2, 0xda, 0xe4, 0x46, 0xd4, 0x6d, 0xaa, + 0x1b, 0xe1, 0x72, 0xdd, 0x1a, 0x8c, 0x54, 0xc8, 0xd8, 0x5f, 0x08, 0x53, 0xb7, 0x2e, 0x2c, 0xff, + 0x4c, 0xa0, 0x1b, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x19, 0x82, 0xfd, 0x00, 0x49, 0x81, 0x68, 0x01, + 0x00, 0x44, 0x23, 0x00, 0x01, 0x80, 0xe2, 0x00, 0x10, 0x64, 0x6f, 0x00, 0x10, 0x64, 0x63, 0x00, + 0x27, 0xa5, 0x6f, 0x00, 0xe0, 0x66, 0xe3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x42, 0xc5, 0x00, + 0x00, 0xc4, 0x73, 0xb4, 0xa3, 0x00, 0x82, 0x28, 0x97, 0x00, 0x02, 0x00, 0x30, 0xbd, 0x28, 0xc8, + 0x97, 0x00, 0x88, 0x00, 0x00, 0x00, 0x84, 0x20, 0x30, 0x7e, 0x45, 0x60, 0x10, 0x40, 0x28, 0x18, + 0x98, 0x00, 0x08, 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x66, 0xe5, 0x00, 0x30, 0x27, 0xf9, 0x00, + 0x00, 0x68, 0x23, 0x80, 0x49, 0xb9, 0x79, 0x80, 0xc9, 0x83, 0xe8, 0xb4, 0x99, 0x00, 0x0a, 0x00, + 0xc0, 0x83, 0xa8, 0xb4, 0x99, 0x00, 0x88, 0x2c, 0x98, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, 0x00, + 0x00, 0xe8, 0xf3, 0x80, 0x49, 0xb9, 0x79, 0x00, 0xc0, 0x83, 0xa8, 0xb4, 0x99, 0x00, 0x88, 0x00, + 0x00, 0xc0, 0xf3, 0x00, 0x00, 0xc2, 0x73, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x00, 0xc6, 0xf3, 0x00, + 0x00, 0xc0, 0x63, 0x0a, 0xc0, 0xc1, 0x25, 0x04, 0x00, 0x44, 0x23, 0x11, 0x00, 0x7c, 0x23, 0x00, + 0x20, 0x04, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x4c, 0x98, 0x00, 0x0a, 0x80, 0x20, 0x84, 0x24, 0x00, + 0x20, 0xc0, 0xe9, 0x00, 0x00, 0xfa, 0x71, 0x20, 0x01, 0x78, 0xc9, 0x40, 0x01, 0x7a, 0x49, 0x20, + 0x30, 0x7e, 0x45, 0x00, 0x00, 0xfc, 0xf3, 0x00, 0xcf, 0xf9, 0xff, 0xfa, 0x0b, 0x6a, 0x55, 0x81, + 0xa4, 0x99, 0xf1, 0xe8, 0x5d, 0xdd, 0xa7, 0x49, 0x69, 0xfc, 0x17, 0x5d, 0x2b, 0x2b, 0x6d, 0x2a, + 0x60, 0xd6, 0x76, 0x2d, 0x5d, 0x49, 0xbc, 0x64, 0x9b, 0x55, 0xa5, 0x4d, 0x78, 0x1c, 0x00, 0x30, + 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, 0xc0, 0x30, 0x5a, 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x00, 0x00, + 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x9c, 0xa4, 0x00, 0xc7, + 0x98, 0x6f, 0x00, 0xd7, 0x9a, 0x6f, 0x00, 0xc0, 0x52, 0xe3, 0x00, 0xd0, 0x54, 0x63, 0x00, 0xe0, + 0x56, 0xe3, 0x9c, 0x8c, 0x00, 0x02, 0xc0, 0x99, 0x00, 0x0a, 0x80, 0x30, 0x50, 0x45, 0xd8, 0x8a, + 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0xc0, 0x99, 0x00, 0x0a, 0x9c, 0x8c, 0x00, 0x02, 0xc0, 0x99, + 0x00, 0x0a, 0x00, 0xb0, 0x42, 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0x90, 0x92, 0x6f, 0x80, 0xa0, + 0x94, 0x6f, 0x00, 0x90, 0x19, 0x6d, 0x00, 0xc0, 0x18, 0xf3, 0xaa, 0xc0, 0x98, 0xa4, 0x00, 0xc0, + 0x18, 0xf3, 0x00, 0x01, 0x40, 0xc5, 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0xa8, 0xe2, 0x60, 0x40, + 0x41, 0xa8, 0x08, 0x99, 0x00, 0x08, 0x02, 0xc0, 0x98, 0x24, 0x0c, 0x99, 0x00, 0x18, 0x01, 0xc0, + 0x98, 0x24, 0x00, 0xc0, 0x18, 0xf3, 0x01, 0xc0, 0x98, 0x24, 0x04, 0xa4, 0xd9, 0x37, 0xb4, 0x99, + 0x00, 0x9c, 0x05, 0xa4, 0xd3, 0xb7, 0xb4, 0x99, 0x00, 0x9c, 0x06, 0xa4, 0xd5, 0xb7, 0xb4, 0x99, + 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, 0x39, 0xb4, 0x99, + 0x00, 0x9c, 0x20, 0x01, 0x78, 0xc5, 0x40, 0x01, 0x7a, 0x45, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, + 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xfa, 0xad, 0x17, 0x5b, 0x3b, 0xc1, 0x34, 0xec, 0x26, 0xba, + 0xab, 0x7f, 0xc0, 0xd9, 0x69, 0x89, 0x1b, 0x48, 0x05, 0x68, 0x97, 0xd7, 0x84, 0x50, 0x4a, 0xec, + 0x7e, 0x19, 0x99, 0x40, 0x95, 0x9c, 0xb5, 0x50, 0x1d, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0xc0, 0xb9, + 0xfd, 0x00, 0x00, 0xc4, 0x73, 0x00, 0xd1, 0xbb, 0xe8, 0x00, 0x90, 0x75, 0xe3, 0xff, 0x00, 0x52, + 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, 0x80, 0xc4, 0x94, 0x68, 0x00, 0xa4, 0xf9, + 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, + 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x03, 0xa4, 0xc5, 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x04, 0xa4, 0xd5, + 0x37, 0xb4, 0x99, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0xb4, 0x99, 0x00, 0x9c, 0x05, 0xa4, 0xc1, + 0x39, 0xb4, 0x99, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, + 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0x41, 0x00, 0x46, + 0x23, 0x00, 0x00, 0x00, 0x84, 0x60, 0x10, 0x40, 0x28, 0xe0, 0x99, 0x00, 0x08, 0x10, 0x00, 0x48, + 0xa2, 0x00, 0x40, 0x66, 0xe5, 0xe4, 0x99, 0x00, 0x18, 0x00, 0x00, 0xe6, 0x73, 0x01, 0x00, 0x64, + 0xa3, 0x00, 0x20, 0x25, 0xed, 0x00, 0x00, 0x62, 0x23, 0x00, 0x01, 0x60, 0x23, 0x00, 0x30, 0x27, + 0xf9, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, 0xf9, 0xeb, 0x00, 0xd0, 0x3b, 0xf9, 0x07, 0x00, 0x40, + 0xa3, 0xff, 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x0e, 0xba, + 0x62, 0xfe, 0x00, 0x42, 0x23, 0x80, 0xd0, 0xfb, 0x62, 0x00, 0xc0, 0x39, 0xf9, 0x20, 0x01, 0x7a, + 0x49, 0xfa, 0xe0, 0xfe, 0xf7, 0x2c, 0xd8, 0xa3, 0x29, 0x0f, 0xc0, 0xd5, 0xbb, 0xaa, 0x13, 0xf3, + 0xfb, 0x4c, 0x8b, 0xc5, 0x65, 0xac, 0xf3, 0xf1, 0xb3, 0xf5, 0x78, 0xd4, 0x00, 0x7c, 0x62, 0xc4, + 0x81, 0x0d, 0x28, 0x1e, 0x40, 0x01, 0x78, 0xc9, 0x00, 0x00, 0xfc, 0xf3, 0x60, 0x31, 0x7e, 0x45, + 0x00, 0xdf, 0xf9, 0x7f, 0x40, 0x31, 0x7e, 0xc5, 0xc0, 0x31, 0x56, 0x45, 0xe0, 0x31, 0x58, 0x45, + 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x9a, 0xa4, + 0x80, 0xb6, 0x96, 0xe7, 0x00, 0xb6, 0x9c, 0x67, 0x80, 0xc6, 0x98, 0xe7, 0xa0, 0x31, 0x4c, 0xc5, + 0x00, 0xb0, 0x4e, 0xe3, 0x00, 0xc0, 0x50, 0x63, 0x00, 0xd0, 0x52, 0x63, 0x00, 0xe0, 0x54, 0x63, + 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, 0xf0, 0x86, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, + 0x70, 0x9b, 0x00, 0x0a, 0x10, 0x89, 0x00, 0x82, 0x70, 0x9b, 0x00, 0x0a, 0xe4, 0x84, 0x00, 0x82, + 0x00, 0x90, 0x15, 0x6d, 0x00, 0xa0, 0x14, 0xf3, 0xaa, 0xa0, 0x94, 0xa4, 0x00, 0xa0, 0x14, 0xf3, + 0x00, 0x01, 0x40, 0xc5, 0xff, 0x00, 0x48, 0xa3, 0x00, 0x02, 0x92, 0xe2, 0x60, 0x90, 0x40, 0xa8, + 0xc0, 0x9a, 0x00, 0x88, 0x02, 0xa0, 0x94, 0x24, 0xc4, 0x9a, 0x00, 0x98, 0x01, 0xa0, 0x94, 0x24, + 0x00, 0xa0, 0x14, 0xf3, 0x02, 0xa0, 0x94, 0x24, 0x04, 0xa4, 0xd5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, + 0x05, 0xa4, 0xd1, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0x7c, 0x9b, 0x00, 0x9c, + 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0x9b, 0x00, 0x9c, 0x20, 0x01, 0x78, 0xc5, 0x40, 0x01, 0x7a, 0x45, + 0x00, 0x00, 0x40, 0x23, 0x60, 0x31, 0x7e, 0x45, 0x00, 0x0e, 0xbc, 0xf9, 0xfa, 0x79, 0xa3, 0x1f, + 0xda, 0x93, 0x85, 0x23, 0xdd, 0x0f, 0x1e, 0xfc, 0xab, 0x58, 0x81, 0x62, 0xe6, 0x82, 0x0b, 0x6b, + 0x6c, 0x4c, 0x4f, 0x73, 0xaf, 0x26, 0xb4, 0xd2, 0x78, 0xe5, 0xce, 0xea, 0xff, 0x00, 0x1f, 0x00, + 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0x80, 0x24, 0x00, + 0xe0, 0xb9, 0x7d, 0x00, 0x00, 0xc4, 0x73, 0x00, 0xd1, 0xbb, 0xe8, 0x00, 0x90, 0x75, 0xe3, 0xff, + 0x00, 0x52, 0x23, 0x00, 0x90, 0x12, 0xf3, 0x00, 0x90, 0x12, 0xf3, 0x80, 0xa4, 0x94, 0x68, 0x00, + 0xa4, 0xf9, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x01, 0xa4, 0xfb, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, + 0xa4, 0xc1, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x03, 0xa4, 0xc5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x04, + 0xa4, 0xd5, 0x37, 0x7c, 0x9b, 0x00, 0x9c, 0x02, 0xa4, 0xc1, 0xb9, 0x7c, 0x9b, 0x00, 0x9c, 0x05, + 0xa4, 0xc1, 0x39, 0x7c, 0x9b, 0x00, 0x9c, 0x00, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x05, + 0xa4, 0xc1, 0x39, 0x41, 0x00, 0x46, 0x23, 0x00, 0x00, 0x00, 0x84, 0x05, 0xa4, 0xc1, 0x39, 0xf2, + 0x00, 0x46, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xc6, 0xf3, 0x00, 0x00, 0xc8, 0x73, 0x00, + 0x00, 0xca, 0xf3, 0x00, 0x00, 0xcc, 0xf3, 0x00, 0x30, 0xc0, 0x63, 0x0b, 0x40, 0xc1, 0x25, 0x4c, + 0xa3, 0x00, 0x02, 0x00, 0x00, 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x43, 0x63, 0x80, + 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xb0, 0x9b, 0x00, 0x0a, 0x00, + 0x00, 0xc0, 0x69, 0x0e, 0x00, 0x7c, 0xa3, 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, + 0xe0, 0x7d, 0x24, 0xc8, 0x9b, 0x00, 0x0a, 0xfa, 0xb1, 0xcc, 0x05, 0xb6, 0x55, 0xbe, 0xd0, 0x38, + 0xe7, 0xf1, 0x1e, 0xad, 0xc7, 0x64, 0x47, 0x97, 0xab, 0xd7, 0x48, 0xf5, 0xd2, 0xe7, 0x14, 0xbd, + 0x78, 0x3a, 0x9f, 0x11, 0xaf, 0xce, 0xa5, 0x01, 0xd8, 0x1f, 0x04, 0x00, 0x7c, 0xa3, 0x00, 0x00, + 0x42, 0xa3, 0x80, 0x00, 0x00, 0xfd, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0xe0, 0x9b, + 0x00, 0x0a, 0x1a, 0x00, 0x7c, 0xa3, 0x00, 0x0f, 0xc0, 0xe2, 0x80, 0x00, 0x80, 0x24, 0x00, 0x00, + 0xc0, 0x69, 0x00, 0x00, 0xf6, 0x71, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x30, 0xc6, 0xeb, 0x00, 0x30, + 0xca, 0xeb, 0x00, 0x30, 0xc0, 0x63, 0x0b, 0xb0, 0xc1, 0x25, 0x04, 0x00, 0x42, 0x23, 0x11, 0x00, + 0x7c, 0x23, 0x00, 0x10, 0x02, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x20, 0x9c, 0x00, 0x8a, 0x80, 0x10, + 0x82, 0x24, 0x00, 0x10, 0xc0, 0xe9, 0x00, 0x00, 0xf8, 0xf1, 0x20, 0x01, 0x64, 0x49, 0x20, 0x30, + 0x7e, 0x45, 0x80, 0xcd, 0xb7, 0xf9, 0x00, 0xb0, 0x81, 0xa8, 0xdc, 0x9d, 0x00, 0x88, 0xa0, 0x30, + 0x6c, 0xc5, 0xc0, 0x30, 0x6e, 0x45, 0xa8, 0x8b, 0x00, 0x02, 0x00, 0x00, 0x46, 0xe3, 0x00, 0x00, + 0x40, 0xa8, 0xfc, 0x9d, 0x00, 0x8a, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, 0x23, 0x00, 0x0b, + 0xac, 0x79, 0x00, 0x60, 0x81, 0x28, 0xe4, 0x9d, 0x00, 0x08, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, + 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x00, 0x00, 0x72, 0x63, 0x01, 0x90, 0xb3, 0x24, 0x80, 0x9d, + 0x83, 0x7f, 0xa8, 0x81, 0x00, 0x02, 0x20, 0x01, 0x64, 0x45, 0x80, 0x2c, 0x95, 0xff, 0x80, 0x6c, + 0x97, 0xff, 0x80, 0xa5, 0x99, 0x7f, 0x80, 0x55, 0x9b, 0xff, 0x80, 0xc6, 0x96, 0xfb, 0x80, 0xa5, + 0x94, 0x7b, 0xfa, 0xa9, 0x58, 0x21, 0xca, 0x6c, 0x9a, 0xce, 0xe3, 0x69, 0xa5, 0xc6, 0x3e, 0x3c, + 0x3e, 0x89, 0x31, 0xdb, 0xe9, 0xd7, 0xce, 0x96, 0x0b, 0x0a, 0xda, 0x46, 0x88, 0x4e, 0x48, 0xde, + 0xcf, 0xed, 0x40, 0xb0, 0x20, 0x00, 0x15, 0x94, 0xff, 0x00, 0xa0, 0x80, 0xa8, 0xec, 0x9d, 0x00, + 0x88, 0x40, 0x01, 0x54, 0x49, 0x00, 0xa0, 0x42, 0x63, 0xa8, 0x81, 0x00, 0x02, 0x80, 0x20, 0xb9, + 0x7f, 0x80, 0x60, 0xb7, 0x7f, 0x00, 0x30, 0x7e, 0xc5, 0xa0, 0x30, 0x58, 0x45, 0xc0, 0x30, 0x5a, + 0xc5, 0x01, 0x00, 0x5c, 0x23, 0x94, 0x8a, 0x00, 0x82, 0x00, 0x90, 0x5e, 0xe3, 0x00, 0xa0, 0x60, + 0x63, 0x00, 0xb0, 0x62, 0x63, 0x60, 0x01, 0x58, 0xc5, 0x80, 0x01, 0x5a, 0xc5, 0x01, 0x00, 0x5c, + 0x23, 0x00, 0xb0, 0x79, 0x63, 0x94, 0x8a, 0x00, 0x82, 0x80, 0xf5, 0x84, 0xef, 0x80, 0x98, 0x86, + 0xef, 0x80, 0x21, 0x80, 0xe8, 0x38, 0x9d, 0x00, 0x0a, 0x80, 0x05, 0x85, 0x6f, 0x80, 0xa8, 0x86, + 0xef, 0x80, 0x21, 0x80, 0xe8, 0xf4, 0x9d, 0x00, 0x0a, 0xfc, 0x89, 0x00, 0x02, 0x00, 0x90, 0x58, + 0xe3, 0x00, 0xa0, 0x5a, 0x63, 0x00, 0xb0, 0x5c, 0xe3, 0x48, 0x9d, 0x00, 0x98, 0x00, 0xf0, 0x58, + 0xe3, 0x00, 0x00, 0x5b, 0xe3, 0x00, 0x10, 0x5d, 0x63, 0x4c, 0x89, 0x00, 0x82, 0x00, 0xe0, 0x42, + 0xe3, 0x98, 0x83, 0x00, 0x82, 0x80, 0xc0, 0x98, 0x6f, 0x20, 0x30, 0x7e, 0x45, 0x00, 0x00, 0x40, + 0x23, 0x00, 0x06, 0x98, 0x79, 0x00, 0x00, 0x7e, 0xa3, 0x00, 0xf0, 0x41, 0x28, 0x00, 0xcb, 0x82, + 0x68, 0xf4, 0x9d, 0x00, 0x0a, 0x00, 0xf0, 0x41, 0x28, 0x00, 0xcb, 0x82, 0x68, 0xf4, 0x9d, 0x00, + 0x0a, 0x00, 0x00, 0x46, 0x23, 0xc3, 0x00, 0x44, 0xa3, 0x64, 0x81, 0x00, 0x02, 0xfa, 0xfb, 0x5d, + 0x62, 0x86, 0x76, 0x8c, 0x10, 0xbd, 0x65, 0x28, 0xab, 0x70, 0xe1, 0x2b, 0x2a, 0x23, 0xeb, 0xc4, + 0x76, 0x94, 0xfc, 0xc5, 0x2c, 0x47, 0x07, 0x61, 0x09, 0x88, 0x53, 0x1f, 0xb9, 0xe3, 0x88, 0x21, + 0x00, 0x00, 0x7c, 0xa2, 0x00, 0xe0, 0x45, 0x69, 0x00, 0x30, 0x40, 0xa8, 0x01, 0x00, 0x42, 0x23, + 0xbc, 0x9d, 0x00, 0x0a, 0x50, 0x00, 0x42, 0xa3, 0x10, 0x00, 0x7c, 0x22, 0x00, 0x60, 0x2d, 0xf9, + 0x00, 0xe0, 0x6d, 0x69, 0x20, 0xe0, 0x7d, 0x22, 0x40, 0x01, 0x54, 0x45, 0x00, 0xa0, 0x14, 0xf9, + 0x00, 0xe0, 0x55, 0xe9, 0x00, 0x30, 0x40, 0xe3, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, + 0x00, 0x00, 0x74, 0xa3, 0x00, 0x00, 0x76, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, + 0x94, 0x81, 0x00, 0x98, 0x21, 0x00, 0x46, 0x23, 0xfc, 0x9d, 0x00, 0x98, 0x22, 0x00, 0x46, 0x23, + 0xfc, 0x9d, 0x00, 0x98, 0x23, 0x00, 0x46, 0xa3, 0xfc, 0x9d, 0x00, 0x98, 0x24, 0x00, 0x46, 0x23, + 0xfc, 0x9d, 0x00, 0x98, 0x3c, 0x00, 0x44, 0xa3, 0x01, 0x00, 0x42, 0x23, 0x84, 0x9d, 0x00, 0x98, + 0xa8, 0xa4, 0x00, 0x18, 0x40, 0x31, 0x7e, 0xc5, 0x00, 0x00, 0x40, 0x23, 0x00, 0x08, 0x80, 0xf9, + 0x00, 0x08, 0x80, 0xe8, 0xdc, 0x9e, 0x00, 0x0a, 0xd8, 0x8c, 0x00, 0x02, 0xdc, 0x9e, 0x00, 0x0a, + 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, 0xa3, 0x00, 0x82, 0x01, 0x00, 0xa4, 0x24, + 0x00, 0x09, 0xa1, 0x67, 0x00, 0x19, 0xa3, 0x67, 0x00, 0x00, 0xfc, 0xf3, 0x80, 0x31, 0x7e, 0xc5, + 0x00, 0x3f, 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, 0x70, 0x96, 0x00, 0x02, 0x5c, 0x8e, 0x00, 0x82, + 0xd0, 0x8e, 0x00, 0x02, 0x00, 0x70, 0x6e, 0x63, 0xfa, 0x69, 0xb0, 0x4c, 0xb1, 0x6a, 0xac, 0x23, + 0xc3, 0xcd, 0xd8, 0xc1, 0x90, 0xdf, 0xc5, 0x7a, 0x4a, 0x12, 0x91, 0x1f, 0xad, 0x51, 0x0e, 0x7a, + 0xe1, 0x62, 0xd6, 0x6f, 0x0f, 0xee, 0xfb, 0x59, 0x82, 0x60, 0x22, 0x00, 0x80, 0x70, 0x63, 0x00, + 0x90, 0x72, 0x63, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x4f, 0xe3, 0x00, + 0x20, 0x51, 0x63, 0x00, 0x10, 0x53, 0xe3, 0x0c, 0x8d, 0x00, 0x82, 0x00, 0x00, 0xfc, 0xf3, 0x80, + 0x31, 0x7e, 0xc5, 0x00, 0x3f, 0xf9, 0xff, 0x40, 0x31, 0x7e, 0xc5, 0x5c, 0x8e, 0x00, 0x82, 0xd0, + 0x8e, 0x00, 0x02, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, 0x00, 0x00, 0x40, 0x23, 0x80, + 0x04, 0x92, 0xfd, 0x00, 0x70, 0x57, 0x63, 0x00, 0x80, 0x59, 0xe3, 0x00, 0x90, 0x5b, 0xe3, 0x0c, + 0x8d, 0x00, 0x82, 0x00, 0xc0, 0x42, 0x63, 0x74, 0x84, 0x00, 0x82, 0x80, 0xb0, 0x96, 0xe7, 0x80, + 0xd0, 0x9a, 0xe7, 0x01, 0x00, 0x58, 0xa3, 0xd4, 0x8d, 0x00, 0x82, 0xe4, 0x9e, 0x00, 0x8a, 0x00, + 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x12, 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0x41, + 0x00, 0x40, 0x23, 0x00, 0x00, 0x00, 0x84, 0xa8, 0xa4, 0x00, 0x18, 0x58, 0x81, 0x00, 0x02, 0x00, + 0x00, 0x48, 0x22, 0x00, 0x40, 0x48, 0xe5, 0xff, 0x00, 0x44, 0xa3, 0x00, 0x41, 0x82, 0xe2, 0x00, + 0x40, 0x32, 0xf5, 0x00, 0x90, 0x09, 0xf5, 0x00, 0x40, 0x08, 0xf5, 0x00, 0x91, 0xb3, 0xe2, 0x00, + 0x41, 0x88, 0xe2, 0x00, 0x00, 0x00, 0x84, 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x33, 0x63, 0x04, + 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0x01, 0x90, 0x75, 0x22, 0x04, 0xa4, 0xc1, 0xb9, 0x7c, + 0xa0, 0x00, 0x1c, 0xfa, 0x6d, 0x5e, 0xad, 0xc1, 0xa4, 0xc6, 0xc5, 0xdc, 0x35, 0x8a, 0x58, 0x8c, + 0x2d, 0x2d, 0xbb, 0x86, 0x51, 0xd5, 0xcf, 0xb3, 0x19, 0xf8, 0xa9, 0x6e, 0xf5, 0xff, 0xb4, 0x34, + 0x1a, 0xdb, 0x93, 0x41, 0x38, 0x23, 0x02, 0x40, 0x40, 0xa8, 0x54, 0x9f, 0x00, 0x08, 0x01, 0x40, + 0x40, 0xa8, 0x70, 0x9f, 0x00, 0x08, 0xf4, 0x00, 0x46, 0xa3, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, + 0x00, 0x98, 0xcc, 0x99, 0x00, 0x82, 0x00, 0x30, 0x40, 0xa8, 0x68, 0x9f, 0x00, 0x08, 0x3c, 0x00, + 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xc3, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0xe4, 0x97, + 0x00, 0x02, 0x00, 0x30, 0x40, 0xa8, 0x84, 0x9f, 0x00, 0x88, 0x3c, 0x00, 0x44, 0xa3, 0x8c, 0x9f, + 0x00, 0x98, 0xc3, 0x00, 0x44, 0xa3, 0x8c, 0x9f, 0x00, 0x98, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, + 0x40, 0xa2, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x44, 0x69, 0x00, 0x30, 0x40, 0xe3, 0x00, 0xa1, + 0x00, 0x98, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x68, 0xe3, 0x00, 0x40, 0x6b, 0x22, 0xf0, 0x9e, + 0x00, 0x02, 0x00, 0x90, 0x35, 0x63, 0x01, 0xa0, 0x75, 0x22, 0xf2, 0x00, 0x46, 0xa3, 0x04, 0xa4, + 0xc1, 0xb9, 0x70, 0xa0, 0x00, 0x9e, 0x04, 0xa4, 0xc5, 0x35, 0x7c, 0xa0, 0x00, 0x1c, 0xf6, 0x00, + 0x46, 0x23, 0xff, 0x00, 0x7c, 0x23, 0x00, 0x20, 0x4a, 0x63, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, + 0x88, 0xe2, 0x01, 0x40, 0x40, 0xa8, 0xf4, 0x9f, 0x00, 0x08, 0x02, 0x40, 0x40, 0xa8, 0x70, 0xa0, + 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0xaa, 0x40, 0x40, 0x28, 0x70, 0xa0, + 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x5f, 0x88, 0xe2, 0x80, 0x4c, 0x40, 0x68, 0xfa, 0x9c, + 0x6b, 0xc9, 0x47, 0x47, 0x8d, 0xbd, 0xb8, 0xb6, 0x5f, 0x30, 0xbb, 0x99, 0x40, 0xff, 0xda, 0x1d, + 0x25, 0xe5, 0x9b, 0x46, 0x35, 0xbc, 0xb8, 0x1f, 0x9a, 0xd4, 0xa1, 0x5a, 0xac, 0x4b, 0x08, 0x10, + 0x24, 0x70, 0xa0, 0x00, 0x8a, 0xf4, 0x00, 0x46, 0xa3, 0x00, 0xe1, 0xbd, 0xe2, 0x02, 0xe0, 0x41, + 0x28, 0x44, 0xa0, 0x00, 0x88, 0x01, 0xe0, 0x41, 0x28, 0x70, 0xa0, 0x00, 0x8a, 0x50, 0x00, 0x42, + 0xa3, 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, 0x00, 0x1c, 0x06, 0xa4, 0xe3, 0x35, 0x7c, 0xa0, 0x00, + 0x1c, 0x50, 0xa0, 0x00, 0x18, 0x30, 0x00, 0x42, 0xa3, 0x05, 0xa4, 0xe1, 0xb5, 0x7c, 0xa0, 0x00, + 0x1c, 0x05, 0xa4, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0xff, 0x0f, 0x4a, 0x23, 0x80, 0x22, 0x84, + 0x62, 0x00, 0x20, 0x04, 0xf3, 0xc3, 0x20, 0x84, 0xa4, 0x00, 0x00, 0x40, 0x23, 0x8c, 0xa0, 0x00, + 0x98, 0x12, 0x00, 0x44, 0xa3, 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, 0x00, 0x98, 0x3c, 0x00, 0x44, + 0xa3, 0xf2, 0x00, 0x46, 0xa3, 0x05, 0xa4, 0xc1, 0x39, 0x8c, 0x9f, 0x00, 0x98, 0x00, 0x50, 0x45, + 0xe9, 0x10, 0x40, 0x6d, 0xa2, 0x00, 0x00, 0x21, 0xf9, 0x00, 0x60, 0x61, 0xe9, 0x20, 0x60, 0x6d, + 0x22, 0x00, 0x10, 0x23, 0xf9, 0x00, 0x60, 0x63, 0x69, 0x00, 0x00, 0x40, 0x23, 0x00, 0xa1, 0x00, + 0x98, 0xf0, 0x9e, 0x00, 0x02, 0x00, 0x90, 0x33, 0x63, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x6a, + 0x22, 0x03, 0x94, 0xc1, 0x39, 0x7c, 0xa0, 0x00, 0x1c, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, + 0x1c, 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, 0x73, 0x22, 0x03, 0x94, 0xc1, 0x39, 0x7c, 0xa0, 0x00, + 0x1c, 0x04, 0x94, 0xc1, 0xb9, 0x7c, 0xa0, 0x00, 0x1c, 0xfa, 0xbf, 0xf2, 0x9a, 0x0b, 0x3d, 0x13, + 0xb2, 0xef, 0xae, 0x6a, 0xb6, 0x48, 0x2a, 0x81, 0xaa, 0xf9, 0xf5, 0xa7, 0x29, 0x15, 0xcf, 0x5b, + 0x26, 0x37, 0x88, 0x6e, 0x25, 0xad, 0x32, 0x67, 0x8f, 0x97, 0xe8, 0x24, 0x05, 0x94, 0xc1, 0x39, + 0xc3, 0x00, 0x44, 0xa3, 0x00, 0x50, 0x45, 0xe9, 0x01, 0x00, 0x42, 0x23, 0x00, 0x00, 0x40, 0x23, + 0x00, 0xa1, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0x00, 0x00, 0x78, 0xa3, + 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x44, 0xa3, 0x00, 0x00, 0x54, 0x23, 0x94, 0x81, 0x00, 0x98, + 0x58, 0x81, 0x00, 0x02, 0x00, 0x00, 0x48, 0x22, 0x00, 0x40, 0x48, 0xe5, 0x00, 0x40, 0x04, 0xf5, + 0xff, 0x00, 0x4c, 0x23, 0x00, 0x23, 0x84, 0x62, 0x00, 0x20, 0x32, 0x63, 0x01, 0x90, 0xb3, 0x24, + 0x04, 0x94, 0xcb, 0xb5, 0x0c, 0xa2, 0x00, 0x1c, 0xff, 0x00, 0x4c, 0x23, 0x00, 0x53, 0x8e, 0xe2, + 0x01, 0x70, 0x40, 0xa8, 0x00, 0xa2, 0x00, 0x8a, 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x50, 0x0a, 0xf5, + 0x00, 0x50, 0x0a, 0xf5, 0x00, 0x53, 0x8e, 0xe2, 0x00, 0x71, 0x40, 0x68, 0xf4, 0xa1, 0x00, 0x0a, + 0x05, 0x94, 0xcb, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x60, 0x01, 0x4a, 0xc9, 0x06, 0x94, 0xcb, 0x35, + 0x0c, 0xa2, 0x00, 0x1c, 0x80, 0x01, 0x4a, 0x49, 0x05, 0x94, 0xc1, 0x39, 0x01, 0x90, 0x73, 0x24, + 0x00, 0x94, 0xf5, 0xb5, 0x0c, 0xa2, 0x00, 0x1c, 0x01, 0x94, 0xed, 0x35, 0x0c, 0xa2, 0x00, 0x1c, + 0x02, 0x94, 0xeb, 0x35, 0x0c, 0xa2, 0x00, 0x1c, 0x03, 0x94, 0xef, 0x35, 0x0c, 0xa2, 0x00, 0x1c, + 0x05, 0x94, 0xc1, 0x39, 0x10, 0x00, 0x48, 0xa2, 0x00, 0x40, 0x64, 0x65, 0x00, 0x20, 0x25, 0xf9, + 0x20, 0x30, 0x7e, 0x45, 0xfa, 0x19, 0x0c, 0xb0, 0xe2, 0x2a, 0xe7, 0x81, 0x3b, 0x3e, 0xb9, 0xda, + 0xac, 0xc0, 0xbd, 0xaa, 0xe9, 0x1c, 0xee, 0x08, 0xcb, 0x84, 0x63, 0x97, 0x95, 0x36, 0x22, 0xbb, + 0x8f, 0x79, 0x59, 0x4e, 0xd4, 0xc0, 0x25, 0x00, 0x00, 0xc4, 0x73, 0x00, 0x05, 0x42, 0xc5, 0xb4, + 0xa3, 0x00, 0x82, 0x00, 0xa0, 0xb5, 0xfd, 0x00, 0x50, 0xab, 0xfb, 0x00, 0x00, 0xd4, 0xf3, 0x00, + 0x65, 0xad, 0x68, 0x00, 0x75, 0xaf, 0x68, 0x80, 0x6b, 0xa9, 0xe8, 0xa0, 0x00, 0x60, 0xc5, 0x00, + 0x00, 0x21, 0xf9, 0xc0, 0x00, 0x62, 0x45, 0x88, 0x9b, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf6, + 0x00, 0x46, 0x23, 0x14, 0xa2, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf4, 0x00, 0x46, 0xa3, 0x14, + 0xa2, 0x00, 0x98, 0x05, 0x94, 0xc1, 0x39, 0xf2, 0x00, 0x46, 0xa3, 0x00, 0x00, 0x7e, 0xa3, 0xd0, + 0xa3, 0x00, 0x02, 0x05, 0x94, 0xc1, 0x39, 0x64, 0x81, 0x00, 0x02, 0x00, 0x00, 0x7c, 0xa2, 0x12, + 0x00, 0x44, 0xa3, 0x00, 0xe0, 0x45, 0x69, 0x00, 0x30, 0x40, 0xe3, 0x01, 0x00, 0x42, 0x23, 0x00, + 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, 0x00, 0x00, 0x74, 0xa3, 0x00, + 0x00, 0x6e, 0x23, 0x94, 0x81, 0x00, 0x98, 0x20, 0x00, 0x42, 0x23, 0x94, 0x81, 0x00, 0x98, 0xf2, + 0x00, 0x40, 0xa3, 0x50, 0xa2, 0x00, 0x98, 0x00, 0x00, 0xe6, 0x73, 0x07, 0x00, 0x40, 0xa3, 0xff, + 0x00, 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, + 0x00, 0x42, 0x23, 0x80, 0x30, 0xe7, 0x62, 0x40, 0x00, 0x66, 0x49, 0x09, 0x00, 0x60, 0xa3, 0x0c, + 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0xfa, + 0x68, 0xa7, 0xba, 0xf2, 0xde, 0xd4, 0x69, 0x32, 0x27, 0x79, 0xaa, 0x64, 0xbb, 0x36, 0xb8, 0x95, + 0x32, 0xc1, 0x8b, 0xcc, 0x14, 0xf3, 0x2d, 0xaa, 0x46, 0x37, 0xcc, 0x08, 0x84, 0x9a, 0x06, 0x88, + 0x98, 0x26, 0x50, 0xa2, 0x00, 0x98, 0x40, 0x00, 0x66, 0x45, 0x20, 0x00, 0x60, 0x45, 0x60, 0x00, + 0x60, 0xc9, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, 0x00, 0x8a, 0x20, 0x10, + 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x20, 0x00, 0x42, 0x45, 0x00, 0x12, 0xe0, 0xb5, 0x58, 0xa2, + 0x00, 0x9c, 0x40, 0x00, 0x66, 0x45, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, + 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x50, 0xa2, 0x00, 0x98, 0x60, 0x00, 0x60, 0xc5, 0x00, 0x00, + 0x42, 0xa3, 0x00, 0x10, 0xe6, 0x35, 0x58, 0xa2, 0x00, 0x9c, 0x07, 0x00, 0x40, 0xa3, 0xff, 0x00, + 0x42, 0xa3, 0x80, 0x00, 0xc0, 0x62, 0x00, 0x00, 0x80, 0x70, 0x80, 0x09, 0xa6, 0x62, 0xfe, 0x00, + 0x42, 0x23, 0x80, 0x30, 0xe7, 0x62, 0x0c, 0x9e, 0x00, 0x02, 0x00, 0x00, 0x40, 0xa8, 0x50, 0xa2, + 0x00, 0x8a, 0x20, 0x10, 0x56, 0xc9, 0x00, 0x00, 0x66, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, + 0x78, 0xa3, 0x50, 0xa2, 0x00, 0x98, 0x00, 0x00, 0x7e, 0xa3, 0xd0, 0xa3, 0x00, 0x02, 0xe4, 0xa3, + 0x00, 0x82, 0x04, 0xa4, 0x00, 0x82, 0x24, 0xa4, 0x00, 0x02, 0x00, 0x00, 0xc0, 0x2d, 0x00, 0x00, + 0xc0, 0x63, 0x94, 0x81, 0x00, 0x98, 0x1c, 0x00, 0x7c, 0xa3, 0x00, 0x10, 0x23, 0xf9, 0x00, 0x00, + 0x40, 0x23, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, 0xfd, 0x80, 0x08, 0x21, 0x7d, 0x00, 0x10, + 0x23, 0xf3, 0x01, 0xe0, 0x7d, 0x24, 0x5c, 0xa3, 0x00, 0x0a, 0xfa, 0xb4, 0x60, 0xb1, 0x5a, 0x98, + 0xbf, 0x70, 0x7d, 0x4b, 0x70, 0x88, 0x41, 0xe5, 0x73, 0x50, 0x99, 0x6c, 0xb4, 0x2a, 0x42, 0x5c, + 0x55, 0xd0, 0xde, 0xf4, 0x11, 0xa2, 0x0e, 0xe9, 0x38, 0x54, 0xf8, 0x70, 0x27, 0x00, 0x00, 0xc0, + 0x69, 0x12, 0x00, 0x7c, 0x23, 0x00, 0x08, 0x00, 0xfd, 0x00, 0x00, 0x21, 0xf3, 0x01, 0xe0, 0x7d, + 0x24, 0x78, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0xc0, 0x69, 0x00, 0x00, 0x00, 0x84, 0x54, 0x00, 0x46, + 0xa3, 0x00, 0x30, 0x06, 0xf3, 0x53, 0x30, 0x86, 0xa4, 0x00, 0x30, 0x06, 0xf3, 0x01, 0x30, 0x86, + 0x24, 0x00, 0x30, 0x06, 0xf3, 0x80, 0x30, 0x86, 0x24, 0x00, 0x30, 0x06, 0xf5, 0x00, 0x00, 0x00, + 0x84, 0x90, 0xa3, 0x00, 0x82, 0x01, 0x06, 0x40, 0xa3, 0x00, 0x00, 0x00, 0xed, 0x00, 0x00, 0xc0, + 0x2d, 0x00, 0x00, 0xc0, 0xeb, 0x00, 0x10, 0x80, 0xf9, 0x00, 0x00, 0x00, 0x84, 0x00, 0x08, 0x4c, + 0xa3, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x60, 0x7e, 0x69, 0xd4, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0x00, + 0x84, 0x00, 0x02, 0x4c, 0xa3, 0x10, 0x00, 0x44, 0x23, 0x00, 0x20, 0x04, 0xf3, 0x00, 0x61, 0x86, + 0xe4, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0xf0, 0xa3, 0x00, 0x0a, 0x00, 0x00, 0x00, + 0x84, 0x80, 0x00, 0x4c, 0xa3, 0x50, 0x00, 0x44, 0xa3, 0x00, 0x20, 0x04, 0xf3, 0x00, 0x61, 0x86, + 0xe4, 0x20, 0x60, 0x4c, 0x24, 0x00, 0x30, 0x7e, 0x69, 0x10, 0xa4, 0x00, 0x0a, 0x00, 0x00, 0x00, + 0x84, 0x00, 0x00, 0x40, 0x23, 0x00, 0x00, 0x42, 0xa3, 0x00, 0x00, 0x44, 0xa3, 0x00, 0x00, 0x46, + 0x23, 0x00, 0x00, 0x48, 0xa3, 0x00, 0x00, 0x4a, 0x23, 0x00, 0x00, 0x4c, 0x23, 0x00, 0x00, 0x4e, + 0xa3, 0x00, 0x00, 0x50, 0xa3, 0x82, 0xd5, 0xdc, 0x27, 0x35, 0x1b, 0x4c, 0xa3, 0x4c, 0x36, 0xeb, + 0x41, 0x52, 0x03, 0x83, 0xdf, 0x21, 0x28, 0x70, 0x0c, 0x82, 0x60, 0x7f, 0x4e, 0x69, 0x4f, 0x91, + 0x86, 0x05, 0x9f, 0x4f, 0x41, 0xab, 0x48, 0x28, 0x00, 0x00, 0x52, 0x23, 0x00, 0x00, 0x54, 0x23, + 0x00, 0x00, 0x56, 0xa3, 0x00, 0x00, 0x58, 0x23, 0x00, 0x00, 0x5a, 0xa3, 0x00, 0x00, 0x5c, 0xa3, + 0x00, 0x00, 0x5e, 0x23, 0x00, 0x00, 0x60, 0xa3, 0x00, 0x00, 0x62, 0x23, 0x00, 0x00, 0x64, 0x23, + 0x00, 0x00, 0x66, 0xa3, 0x00, 0x00, 0x68, 0x23, 0x00, 0x00, 0x6a, 0xa3, 0x00, 0x00, 0x6c, 0xa3, + 0x00, 0x00, 0x6e, 0x23, 0x00, 0x00, 0x70, 0x23, 0x00, 0x00, 0x72, 0xa3, 0x00, 0x00, 0x74, 0xa3, + 0x00, 0x00, 0x76, 0x23, 0x00, 0x00, 0x78, 0xa3, 0x00, 0x00, 0x7a, 0x23, 0x00, 0x00, 0x7c, 0x23, + 0x00, 0x00, 0x7e, 0xa3, 0x00, 0x00, 0x00, 0x84, 0x72, 0x15, 0x3d, 0x1a, 0x60, 0x0f, 0x69, 0x4a, + 0x2c, 0xc1, 0x53, 0x08, 0xf6, 0x3c, 0x30, 0x3c, 0xc9, 0x27, 0x90, 0xfc, 0xf3, 0x88, 0x47, 0xba, + 0x3a, 0x14, 0xa3, 0xd7, 0x9f, 0x7b, 0xcb, 0xa5, 0x1f, 0xb0, 0x03, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xd4, 0xf7, 0xa4, 0x0c, + 0xbc, 0xf7, 0x1c, 0x21, 0x26, 0x12, 0xa4, 0x9d, 0x66, 0x93, 0x47, 0xf7, 0x1f, 0xee, 0x20, 0x54, + 0x07, 0x06, 0x16, 0x79, 0x53, 0x6d, 0x70, 0x70, 0xd8, 0xd6, 0x47, 0x37, 0xd8, 0x02, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x01, 0xa8, 0x24, 0x00, 0x00, 0x45, 0x07, 0xdd, 0x4c, 0x3e, 0x76, 0xee, 0xe1, 0x59, 0xcb, 0x26, + 0x98, 0xc7, 0x25, 0x91, 0xb2, 0x59, 0xdd, 0x1c, 0xf0, 0x9e, 0xef, 0xd3, 0x1c, 0x5d, 0xb6, 0x34, + 0xbb, 0x20, 0xd4, 0x52, 0x09, 0xd2, 0x56, 0xbf, 0xa0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff}; \ No newline at end of file diff --git a/cal/mbedtls_v4/lt_mbedtls_v4_aesgcm.c b/cal/mbedtls_v4/lt_mbedtls_v4_aesgcm.c index 0976fd29b..0f307bb4e 100644 --- a/cal/mbedtls_v4/lt_mbedtls_v4_aesgcm.c +++ b/cal/mbedtls_v4/lt_mbedtls_v4_aesgcm.c @@ -27,7 +27,8 @@ * @param key_len Length of the key * @return LT_OK if success, otherwise returns other error code. */ -static lt_ret_t lt_aesgcm_init(lt_aesgcm_ctx_mbedtls_v4_t *ctx, const uint8_t *key, const uint32_t key_len) +static lt_ret_t lt_aesgcm_init(lt_aesgcm_ctx_mbedtls_v4_t *ctx, const uint8_t *key, + const uint32_t key_len) { psa_status_t status; psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; @@ -90,17 +91,19 @@ lt_ret_t lt_aesgcm_decrypt_init(void *ctx, const uint8_t *key, const uint32_t ke } lt_ret_t lt_aesgcm_encrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, const uint8_t *add, - const uint32_t add_len, const uint8_t *plaintext, const uint32_t plaintext_len, - uint8_t *ciphertext, const uint32_t ciphertext_len) + const uint32_t add_len, const uint8_t *plaintext, + const uint32_t plaintext_len, uint8_t *ciphertext, + const uint32_t ciphertext_len) { lt_ctx_mbedtls_v4_t *_ctx = (lt_ctx_mbedtls_v4_t *)ctx; psa_status_t status; size_t resulting_length; if (ciphertext_len < PSA_AEAD_ENCRYPT_OUTPUT_SIZE(PSA_KEY_TYPE_AES, PSA_ALG_GCM, plaintext_len)) { - LT_LOG_ERROR("AES-GCM output (ciphertext) buffer too small! Current: %" PRIu32 " bytes, required: %" PRIu32 - " bytes", - ciphertext_len, PSA_AEAD_ENCRYPT_OUTPUT_SIZE(PSA_KEY_TYPE_AES, PSA_ALG_GCM, plaintext_len)); + LT_LOG_ERROR("AES-GCM output (ciphertext) buffer too small! Current: %" PRIu32 + " bytes, required: %" PRIu32 " bytes", + ciphertext_len, + PSA_AEAD_ENCRYPT_OUTPUT_SIZE(PSA_KEY_TYPE_AES, PSA_ALG_GCM, plaintext_len)); return LT_PARAM_ERR; } @@ -110,17 +113,21 @@ lt_ret_t lt_aesgcm_encrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, } // PSA AEAD encrypt operation - status = psa_aead_encrypt(_ctx->aesgcm_encrypt_ctx.key_id, PSA_ALG_GCM, iv, iv_len, add, add_len, plaintext, - plaintext_len, ciphertext, ciphertext_len, &resulting_length); + status = psa_aead_encrypt(_ctx->aesgcm_encrypt_ctx.key_id, PSA_ALG_GCM, iv, iv_len, add, add_len, + plaintext, plaintext_len, ciphertext, ciphertext_len, &resulting_length); if (status != PSA_SUCCESS) { LT_LOG_ERROR("AES-GCM encryption failed, status=%" PRId32 " (psa_status_t)", status); return LT_CRYPTO_ERR; } - if (resulting_length != PSA_AEAD_ENCRYPT_OUTPUT_SIZE(PSA_KEY_TYPE_AES, PSA_ALG_GCM, plaintext_len)) { - LT_LOG_ERROR("AES-GCM encryption output length mismatch! Current: %zu bytes, expected: %" PRIu32 " bytes", - resulting_length, PSA_AEAD_ENCRYPT_OUTPUT_SIZE(PSA_KEY_TYPE_AES, PSA_ALG_GCM, plaintext_len)); + if (resulting_length != + PSA_AEAD_ENCRYPT_OUTPUT_SIZE(PSA_KEY_TYPE_AES, PSA_ALG_GCM, plaintext_len)) { + LT_LOG_ERROR( + "AES-GCM encryption output length mismatch! Current: %zu bytes, expected: %" PRIu32 + " bytes", + resulting_length, + PSA_AEAD_ENCRYPT_OUTPUT_SIZE(PSA_KEY_TYPE_AES, PSA_ALG_GCM, plaintext_len)); return LT_CRYPTO_ERR; } @@ -128,16 +135,17 @@ lt_ret_t lt_aesgcm_encrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, } lt_ret_t lt_aesgcm_decrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, const uint8_t *add, - const uint32_t add_len, const uint8_t *ciphertext, const uint32_t ciphertext_len, - uint8_t *plaintext, const uint32_t plaintext_len) + const uint32_t add_len, const uint8_t *ciphertext, + const uint32_t ciphertext_len, uint8_t *plaintext, + const uint32_t plaintext_len) { lt_ctx_mbedtls_v4_t *_ctx = (lt_ctx_mbedtls_v4_t *)ctx; psa_status_t status; size_t resulting_length; - // Some implementations of MbedTLS (e.g. in ESP-IDF) require plaintext != NULL and plaintext_len != 0. - // So if these arguments are passed, we have to use a dummy variable for the plaintext and its size, - // because sometimes we do not care about the plaintext (e.g. when decrypting an authentication tag - // during SecureSession Channel establishment). + // Some implementations of MbedTLS (e.g. in ESP-IDF) require plaintext != NULL and plaintext_len != + // 0. So if these arguments are passed, we have to use a dummy variable for the plaintext and its + // size, because sometimes we do not care about the plaintext (e.g. when decrypting an + // authentication tag during SecureSession Channel establishment). uint8_t dummy_plaintext; uint8_t *_plaintext = plaintext; uint32_t _plaintext_len = plaintext_len; @@ -148,9 +156,10 @@ lt_ret_t lt_aesgcm_decrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, } if (_plaintext_len < PSA_AEAD_DECRYPT_OUTPUT_SIZE(PSA_KEY_TYPE_AES, PSA_ALG_GCM, ciphertext_len)) { - LT_LOG_ERROR("AES-GCM output (plaintext) buffer too small! Current: %" PRIu32 " bytes, required: %" PRIu32 - " bytes", - _plaintext_len, PSA_AEAD_DECRYPT_OUTPUT_SIZE(PSA_KEY_TYPE_AES, PSA_ALG_GCM, ciphertext_len)); + LT_LOG_ERROR("AES-GCM output (plaintext) buffer too small! Current: %" PRIu32 + " bytes, required: %" PRIu32 " bytes", + _plaintext_len, + PSA_AEAD_DECRYPT_OUTPUT_SIZE(PSA_KEY_TYPE_AES, PSA_ALG_GCM, ciphertext_len)); return LT_PARAM_ERR; } @@ -160,17 +169,22 @@ lt_ret_t lt_aesgcm_decrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, } // PSA AEAD decrypt operation - status = psa_aead_decrypt(_ctx->aesgcm_decrypt_ctx.key_id, PSA_ALG_GCM, iv, iv_len, add, add_len, ciphertext, - ciphertext_len, _plaintext, _plaintext_len, &resulting_length); + status = psa_aead_decrypt(_ctx->aesgcm_decrypt_ctx.key_id, PSA_ALG_GCM, iv, iv_len, add, add_len, + ciphertext, ciphertext_len, _plaintext, _plaintext_len, + &resulting_length); if (status != PSA_SUCCESS) { LT_LOG_ERROR("AES-GCM decryption failed, status=%" PRId32 " (psa_status_t)", status); return LT_CRYPTO_ERR; } - if (resulting_length != PSA_AEAD_DECRYPT_OUTPUT_SIZE(PSA_KEY_TYPE_AES, PSA_ALG_GCM, ciphertext_len)) { - LT_LOG_ERROR("AES-GCM decryption output length mismatch! Current: %zu bytes, expected: %" PRIu32 " bytes", - resulting_length, PSA_AEAD_DECRYPT_OUTPUT_SIZE(PSA_KEY_TYPE_AES, PSA_ALG_GCM, ciphertext_len)); + if (resulting_length != + PSA_AEAD_DECRYPT_OUTPUT_SIZE(PSA_KEY_TYPE_AES, PSA_ALG_GCM, ciphertext_len)) { + LT_LOG_ERROR( + "AES-GCM decryption output length mismatch! Current: %zu bytes, expected: %" PRIu32 + " bytes", + resulting_length, + PSA_AEAD_DECRYPT_OUTPUT_SIZE(PSA_KEY_TYPE_AES, PSA_ALG_GCM, ciphertext_len)); return LT_CRYPTO_ERR; } diff --git a/cal/mbedtls_v4/lt_mbedtls_v4_hmac_sha256.c b/cal/mbedtls_v4/lt_mbedtls_v4_hmac_sha256.c index 874518787..03de62c32 100644 --- a/cal/mbedtls_v4/lt_mbedtls_v4_hmac_sha256.c +++ b/cal/mbedtls_v4/lt_mbedtls_v4_hmac_sha256.c @@ -16,8 +16,8 @@ #include "libtropic_logging.h" #include "lt_hmac_sha256.h" -lt_ret_t lt_hmac_sha256(const uint8_t *key, const uint32_t key_len, const uint8_t *input, const uint32_t input_len, - uint8_t *output) +lt_ret_t lt_hmac_sha256(const uint8_t *key, const uint32_t key_len, const uint8_t *input, + const uint32_t input_len, uint8_t *output) { psa_status_t status; psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; @@ -51,7 +51,8 @@ lt_ret_t lt_hmac_sha256(const uint8_t *key, const uint32_t key_len, const uint8_ } if (destroy_key_status != PSA_SUCCESS) { - LT_LOG_ERROR("Couldn't destroy HMAC key, status=%" PRId32 " (psa_status_t)", destroy_key_status); + LT_LOG_ERROR("Couldn't destroy HMAC key, status=%" PRId32 " (psa_status_t)", + destroy_key_status); return LT_CRYPTO_ERR; } diff --git a/cal/mbedtls_v4/lt_mbedtls_v4_sha256.c b/cal/mbedtls_v4/lt_mbedtls_v4_sha256.c index a87f03e07..9dcb79bf4 100644 --- a/cal/mbedtls_v4/lt_mbedtls_v4_sha256.c +++ b/cal/mbedtls_v4/lt_mbedtls_v4_sha256.c @@ -64,7 +64,8 @@ lt_ret_t lt_sha256_finish(void *ctx, uint8_t *output) size_t hash_length; // Finalize the hash and get the digest - status = psa_hash_finish(&_ctx->sha256_ctx, output, PSA_HASH_LENGTH(PSA_ALG_SHA_256), &hash_length); + status = psa_hash_finish(&_ctx->sha256_ctx, output, PSA_HASH_LENGTH(PSA_ALG_SHA_256), + &hash_length); if (status != PSA_SUCCESS) { LT_LOG_ERROR("SHA-256 finish failed, status=%" PRId32 " (psa_status_t)", status); return LT_CRYPTO_ERR; diff --git a/cal/mbedtls_v4/lt_mbedtls_v4_x25519.c b/cal/mbedtls_v4/lt_mbedtls_v4_x25519.c index 2099588cc..9c780cbd3 100644 --- a/cal/mbedtls_v4/lt_mbedtls_v4_x25519.c +++ b/cal/mbedtls_v4/lt_mbedtls_v4_x25519.c @@ -40,8 +40,8 @@ lt_ret_t lt_X25519(const uint8_t *privkey, const uint8_t *pubkey, uint8_t *secre } // Perform X25519 key agreement to compute shared secret - status = psa_raw_key_agreement(PSA_ALG_ECDH, key_id, pubkey, TR01_X25519_KEY_LEN, secret, TR01_X25519_KEY_LEN, - &secret_length); + status = psa_raw_key_agreement(PSA_ALG_ECDH, key_id, pubkey, TR01_X25519_KEY_LEN, secret, + TR01_X25519_KEY_LEN, &secret_length); // Clean up psa_status_t destroy_key_status = psa_destroy_key(key_id); @@ -57,7 +57,8 @@ lt_ret_t lt_X25519(const uint8_t *privkey, const uint8_t *pubkey, uint8_t *secre } if (destroy_key_status != PSA_SUCCESS) { - LT_LOG_ERROR("Couldn't destroy X25519 private key, status=%" PRId32 " (psa_status_t)", destroy_key_status); + LT_LOG_ERROR("Couldn't destroy X25519 private key, status=%" PRId32 " (psa_status_t)", + destroy_key_status); return LT_CRYPTO_ERR; } @@ -103,7 +104,8 @@ lt_ret_t lt_X25519_scalarmult(const uint8_t *sk, uint8_t *pk) } if (destroy_key_status != PSA_SUCCESS) { - LT_LOG_ERROR("Couldn't destroy X25519 private key, status=%" PRId32 " (psa_status_t)", destroy_key_status); + LT_LOG_ERROR("Couldn't destroy X25519 private key, status=%" PRId32 " (psa_status_t)", + destroy_key_status); return LT_CRYPTO_ERR; } diff --git a/cal/openssl/lt_openssl_aesgcm.c b/cal/openssl/lt_openssl_aesgcm.c index 80511491f..627e59b98 100644 --- a/cal/openssl/lt_openssl_aesgcm.c +++ b/cal/openssl/lt_openssl_aesgcm.c @@ -40,24 +40,27 @@ lt_ret_t lt_aesgcm_encrypt_init(void *ctx, const uint8_t *key, const uint32_t ke // Set cipher type. if (!EVP_EncryptInit_ex(_ctx->aesgcm_encrypt_ctx, EVP_aes_256_gcm(), NULL, NULL, NULL)) { err_code = ERR_get_error(); - LT_LOG_ERROR("Failed to initialize AES-GCM encryption context with cipher type, err_code=%lu (%s)", err_code, - ERR_error_string(err_code, NULL)); + LT_LOG_ERROR( + "Failed to initialize AES-GCM encryption context with cipher type, err_code=%lu (%s)", + err_code, ERR_error_string(err_code, NULL)); return LT_CRYPTO_ERR; } // Set IV length. - if (!EVP_CIPHER_CTX_ctrl(_ctx->aesgcm_encrypt_ctx, EVP_CTRL_GCM_SET_IVLEN, TR01_L3_IV_SIZE, NULL)) { + if (!EVP_CIPHER_CTX_ctrl(_ctx->aesgcm_encrypt_ctx, EVP_CTRL_GCM_SET_IVLEN, TR01_L3_IV_SIZE, + NULL)) { err_code = ERR_get_error(); - LT_LOG_ERROR("Failed to initialize AES-GCM encryption context with IV length, err_code=%lu (%s)", err_code, - ERR_error_string(err_code, NULL)); + LT_LOG_ERROR( + "Failed to initialize AES-GCM encryption context with IV length, err_code=%lu (%s)", + err_code, ERR_error_string(err_code, NULL)); return LT_CRYPTO_ERR; } // Set encryption key. if (!EVP_EncryptInit_ex(_ctx->aesgcm_encrypt_ctx, NULL, NULL, key, NULL)) { err_code = ERR_get_error(); - LT_LOG_ERROR("Failed to initialize AES-GCM encryption context with key, err_code=%lu (%s)", err_code, - ERR_error_string(err_code, NULL)); + LT_LOG_ERROR("Failed to initialize AES-GCM encryption context with key, err_code=%lu (%s)", + err_code, ERR_error_string(err_code, NULL)); return LT_CRYPTO_ERR; } @@ -87,24 +90,27 @@ lt_ret_t lt_aesgcm_decrypt_init(void *ctx, const uint8_t *key, const uint32_t ke // Set cipher type. if (!EVP_DecryptInit_ex(_ctx->aesgcm_decrypt_ctx, EVP_aes_256_gcm(), NULL, NULL, NULL)) { err_code = ERR_get_error(); - LT_LOG_ERROR("Failed to initialize AES-GCM decryption context with cipher type, err_code=%lu (%s)", err_code, - ERR_error_string(err_code, NULL)); + LT_LOG_ERROR( + "Failed to initialize AES-GCM decryption context with cipher type, err_code=%lu (%s)", + err_code, ERR_error_string(err_code, NULL)); return LT_CRYPTO_ERR; } // Set IV length. - if (!EVP_CIPHER_CTX_ctrl(_ctx->aesgcm_decrypt_ctx, EVP_CTRL_GCM_SET_IVLEN, TR01_L3_IV_SIZE, NULL)) { + if (!EVP_CIPHER_CTX_ctrl(_ctx->aesgcm_decrypt_ctx, EVP_CTRL_GCM_SET_IVLEN, TR01_L3_IV_SIZE, + NULL)) { err_code = ERR_get_error(); - LT_LOG_ERROR("Failed to initialize AES-GCM decryption context with IV length, err_code=%lu (%s)", err_code, - ERR_error_string(err_code, NULL)); + LT_LOG_ERROR( + "Failed to initialize AES-GCM decryption context with IV length, err_code=%lu (%s)", + err_code, ERR_error_string(err_code, NULL)); return LT_CRYPTO_ERR; } // Set decryption key. if (!EVP_DecryptInit_ex(_ctx->aesgcm_decrypt_ctx, NULL, NULL, key, NULL)) { err_code = ERR_get_error(); - LT_LOG_ERROR("Failed to initialize AES-GCM decryption context with key, err_code=%lu (%s)", err_code, - ERR_error_string(err_code, NULL)); + LT_LOG_ERROR("Failed to initialize AES-GCM decryption context with key, err_code=%lu (%s)", + err_code, ERR_error_string(err_code, NULL)); return LT_CRYPTO_ERR; } @@ -112,11 +118,13 @@ lt_ret_t lt_aesgcm_decrypt_init(void *ctx, const uint8_t *key, const uint32_t ke } lt_ret_t lt_aesgcm_encrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, const uint8_t *add, - const uint32_t add_len, const uint8_t *plaintext, const uint32_t plaintext_len, - uint8_t *ciphertext, const uint32_t ciphertext_len) + const uint32_t add_len, const uint8_t *plaintext, + const uint32_t plaintext_len, uint8_t *ciphertext, + const uint32_t ciphertext_len) { if (iv_len != TR01_L3_IV_SIZE) { - LT_LOG_ERROR("Invalid AES-GCM IV length: got %" PRIu32 " bytes, expected %d bytes", iv_len, TR01_L3_IV_SIZE); + LT_LOG_ERROR("Invalid AES-GCM IV length: got %" PRIu32 " bytes, expected %d bytes", iv_len, + TR01_L3_IV_SIZE); return LT_PARAM_ERR; } @@ -135,12 +143,14 @@ lt_ret_t lt_aesgcm_encrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, // Process AAD (Additional Authenticated Data). if (!EVP_EncryptUpdate(_ctx->aesgcm_encrypt_ctx, NULL, &out_len, add, (int)add_len)) { err_code = ERR_get_error(); - LT_LOG_ERROR("Failed to process AES-GCM AAD, err_code=%lu (%s)", err_code, ERR_error_string(err_code, NULL)); + LT_LOG_ERROR("Failed to process AES-GCM AAD, err_code=%lu (%s)", err_code, + ERR_error_string(err_code, NULL)); return LT_CRYPTO_ERR; } // Encrypt plaintext. - if (!EVP_EncryptUpdate(_ctx->aesgcm_encrypt_ctx, ciphertext, &out_len, plaintext, (int)plaintext_len)) { + if (!EVP_EncryptUpdate(_ctx->aesgcm_encrypt_ctx, ciphertext, &out_len, plaintext, + (int)plaintext_len)) { err_code = ERR_get_error(); LT_LOG_ERROR("Failed to encrypt AES-GCM plaintext, err_code=%lu (%s)", err_code, ERR_error_string(err_code, NULL)); @@ -149,8 +159,9 @@ lt_ret_t lt_aesgcm_encrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, // Check that all plaintext data was processed. if (out_len != (int)(ciphertext_len - TR01_L3_TAG_SIZE)) { - LT_LOG_ERROR("AES-GCM encryption length mismatch! Current: %d bytes, expected: %" PRIu32 " bytes", out_len, - ciphertext_len - TR01_L3_TAG_SIZE); + LT_LOG_ERROR("AES-GCM encryption length mismatch! Current: %d bytes, expected: %" PRIu32 + " bytes", + out_len, ciphertext_len - TR01_L3_TAG_SIZE); return LT_CRYPTO_ERR; } @@ -175,11 +186,13 @@ lt_ret_t lt_aesgcm_encrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, } lt_ret_t lt_aesgcm_decrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, const uint8_t *add, - const uint32_t add_len, const uint8_t *ciphertext, const uint32_t ciphertext_len, - uint8_t *plaintext, const uint32_t plaintext_len) + const uint32_t add_len, const uint8_t *ciphertext, + const uint32_t ciphertext_len, uint8_t *plaintext, + const uint32_t plaintext_len) { if (iv_len != TR01_L3_IV_SIZE) { - LT_LOG_ERROR("Invalid AES-GCM IV length: got %" PRIu32 " bytes, expected %d bytes", iv_len, TR01_L3_IV_SIZE); + LT_LOG_ERROR("Invalid AES-GCM IV length: got %" PRIu32 " bytes, expected %d bytes", iv_len, + TR01_L3_IV_SIZE); return LT_PARAM_ERR; } @@ -198,7 +211,8 @@ lt_ret_t lt_aesgcm_decrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, // Process AAD (Additional Authenticated Data). if (!EVP_DecryptUpdate(_ctx->aesgcm_decrypt_ctx, NULL, &out_len, add, (int)add_len)) { err_code = ERR_get_error(); - LT_LOG_ERROR("Failed to process AES-GCM AAD, err_code=%lu (%s)", err_code, ERR_error_string(err_code, NULL)); + LT_LOG_ERROR("Failed to process AES-GCM AAD, err_code=%lu (%s)", err_code, + ERR_error_string(err_code, NULL)); return LT_CRYPTO_ERR; } @@ -213,8 +227,9 @@ lt_ret_t lt_aesgcm_decrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, // Check that all ciphertext data was processed. if (out_len != (int)(plaintext_len)) { - LT_LOG_ERROR("AES-GCM decryption length mismatch! Current: %d bytes, expected: %" PRIu32 " bytes", out_len, - plaintext_len); + LT_LOG_ERROR("AES-GCM decryption length mismatch! Current: %d bytes, expected: %" PRIu32 + " bytes", + out_len, plaintext_len); return LT_CRYPTO_ERR; } diff --git a/cal/openssl/lt_openssl_hmac_sha256.c b/cal/openssl/lt_openssl_hmac_sha256.c index 1a8d2a28c..e51dd694a 100644 --- a/cal/openssl/lt_openssl_hmac_sha256.c +++ b/cal/openssl/lt_openssl_hmac_sha256.c @@ -14,8 +14,8 @@ #include "libtropic_logging.h" #include "lt_hmac_sha256.h" -lt_ret_t lt_hmac_sha256(const uint8_t *key, const uint32_t key_len, const uint8_t *input, const uint32_t input_len, - uint8_t *output) +lt_ret_t lt_hmac_sha256(const uint8_t *key, const uint32_t key_len, const uint8_t *input, + const uint32_t input_len, uint8_t *output) { EVP_MD_CTX *ctx = NULL; EVP_PKEY *pkey = NULL; @@ -71,8 +71,8 @@ lt_ret_t lt_hmac_sha256(const uint8_t *key, const uint32_t key_len, const uint8_ } if (out_len != LT_HMAC_SHA256_HASH_LEN) { - LT_LOG_ERROR("HMAC-SHA256 output length mismatch! Current: %zu bytes, expected: %d bytes", out_len, - LT_HMAC_SHA256_HASH_LEN); + LT_LOG_ERROR("HMAC-SHA256 output length mismatch! Current: %zu bytes, expected: %d bytes", + out_len, LT_HMAC_SHA256_HASH_LEN); ret = LT_CRYPTO_ERR; goto lt_hmac_sha256_cleanup; } diff --git a/cal/openssl/lt_openssl_sha256.c b/cal/openssl/lt_openssl_sha256.c index c519cba0e..a010b0391 100644 --- a/cal/openssl/lt_openssl_sha256.c +++ b/cal/openssl/lt_openssl_sha256.c @@ -39,8 +39,8 @@ lt_ret_t lt_sha256_start(void *ctx) if (!EVP_DigestInit_ex(_ctx->sha256_ctx, EVP_sha256(), NULL)) { err_code = ERR_get_error(); - LT_LOG_ERROR("Failed to initialize SHA-256 context with hash type, err_code=%lu (%s)", err_code, - ERR_error_string(err_code, NULL)); + LT_LOG_ERROR("Failed to initialize SHA-256 context with hash type, err_code=%lu (%s)", + err_code, ERR_error_string(err_code, NULL)); return LT_CRYPTO_ERR; } @@ -54,7 +54,8 @@ lt_ret_t lt_sha256_update(void *ctx, const uint8_t *input, const size_t input_le if (!EVP_DigestUpdate(_ctx->sha256_ctx, input, input_len)) { err_code = ERR_get_error(); - LT_LOG_ERROR("Failed to update SHA-256 hash, err_code=%lu (%s)", err_code, ERR_error_string(err_code, NULL)); + LT_LOG_ERROR("Failed to update SHA-256 hash, err_code=%lu (%s)", err_code, + ERR_error_string(err_code, NULL)); return LT_CRYPTO_ERR; } @@ -68,7 +69,8 @@ lt_ret_t lt_sha256_finish(void *ctx, uint8_t *output) if (!EVP_DigestFinal_ex(_ctx->sha256_ctx, output, NULL)) { err_code = ERR_get_error(); - LT_LOG_ERROR("Failed to finalize SHA-256 hash, err_code=%lu (%s)", err_code, ERR_error_string(err_code, NULL)); + LT_LOG_ERROR("Failed to finalize SHA-256 hash, err_code=%lu (%s)", err_code, + ERR_error_string(err_code, NULL)); return LT_CRYPTO_ERR; } diff --git a/cal/openssl/lt_openssl_x25519.c b/cal/openssl/lt_openssl_x25519.c index e3005ea1c..72df1cb1b 100644 --- a/cal/openssl/lt_openssl_x25519.c +++ b/cal/openssl/lt_openssl_x25519.c @@ -56,8 +56,8 @@ lt_ret_t lt_X25519(const uint8_t *privkey, const uint8_t *pubkey, uint8_t *secre // Initialize the derivation. if (EVP_PKEY_derive_init(ctx) <= 0) { err_code = ERR_get_error(); - LT_LOG_ERROR("Failed to initialize EVP_PKEY_CTX for X25519 derivation, err_code=%lu (%s)", err_code, - ERR_error_string(err_code, NULL)); + LT_LOG_ERROR("Failed to initialize EVP_PKEY_CTX for X25519 derivation, err_code=%lu (%s)", + err_code, ERR_error_string(err_code, NULL)); lt_ret = LT_CRYPTO_ERR; goto lt_X25519_cleanup; } @@ -65,8 +65,8 @@ lt_ret_t lt_X25519(const uint8_t *privkey, const uint8_t *pubkey, uint8_t *secre // Provide the peer public key. if (EVP_PKEY_derive_set_peer(ctx, pub) <= 0) { err_code = ERR_get_error(); - LT_LOG_ERROR("Failed to set peer public key for X25519 derivation, err_code=%lu (%s)", err_code, - ERR_error_string(err_code, NULL)); + LT_LOG_ERROR("Failed to set peer public key for X25519 derivation, err_code=%lu (%s)", + err_code, ERR_error_string(err_code, NULL)); lt_ret = LT_CRYPTO_ERR; goto lt_X25519_cleanup; } @@ -82,8 +82,8 @@ lt_ret_t lt_X25519(const uint8_t *privkey, const uint8_t *pubkey, uint8_t *secre } if (secret_len != TR01_X25519_KEY_LEN) { - LT_LOG_ERROR("X25519 derived secret length mismatch! Current: %zu bytes, expected: %d bytes", secret_len, - TR01_X25519_KEY_LEN); + LT_LOG_ERROR("X25519 derived secret length mismatch! Current: %zu bytes, expected: %d bytes", + secret_len, TR01_X25519_KEY_LEN); lt_ret = LT_CRYPTO_ERR; goto lt_X25519_cleanup; } @@ -115,15 +115,15 @@ lt_ret_t lt_X25519_scalarmult(const uint8_t *sk, uint8_t *pk) size_t pk_len = TR01_X25519_KEY_LEN; if (!EVP_PKEY_get_raw_public_key(priv, pk, &pk_len)) { err_code = ERR_get_error(); - LT_LOG_ERROR("Failed to extract X25519 public key from private key, err_code=%lu (%s)", err_code, - ERR_error_string(err_code, NULL)); + LT_LOG_ERROR("Failed to extract X25519 public key from private key, err_code=%lu (%s)", + err_code, ERR_error_string(err_code, NULL)); lt_ret = LT_CRYPTO_ERR; goto lt_X25519_scalarmult_cleanup; } if (pk_len != TR01_X25519_KEY_LEN) { - LT_LOG_ERROR("X25519 public key length mismatch! Current: %zu bytes, expected: %d bytes", pk_len, - TR01_X25519_KEY_LEN); + LT_LOG_ERROR("X25519 public key length mismatch! Current: %zu bytes, expected: %d bytes", + pk_len, TR01_X25519_KEY_LEN); lt_ret = LT_CRYPTO_ERR; goto lt_X25519_scalarmult_cleanup; } diff --git a/cal/trezor_crypto/lt_trezor_crypto_aesgcm.c b/cal/trezor_crypto/lt_trezor_crypto_aesgcm.c index db42462b6..75d0600fa 100644 --- a/cal/trezor_crypto/lt_trezor_crypto_aesgcm.c +++ b/cal/trezor_crypto/lt_trezor_crypto_aesgcm.c @@ -5,9 +5,12 @@ * @license For the license see LICENSE.md in the root directory of this source tree. */ +#include + #include "aes/aes.h" #include "aes/aesgcm.h" #include "libtropic_common.h" +#include "libtropic_logging.h" #include "libtropic_trezor_crypto.h" #include "lt_aesgcm.h" @@ -23,6 +26,7 @@ static lt_ret_t lt_aesgcm_init(gcm_ctx *ctx, const uint8_t *key, const uint32_t { int ret = gcm_init_and_key(key, key_len, ctx); if (ret != RETURN_GOOD) { + LT_LOG_ERROR("Failed to initialize AES-GCM context, ret=%d", ret); return LT_CRYPTO_ERR; } return LT_OK; @@ -38,6 +42,7 @@ static lt_ret_t lt_aesgcm_deinit(gcm_ctx *ctx) { int ret = gcm_end(ctx); if (ret != RETURN_GOOD) { + LT_LOG_ERROR("Failed to deinitialize AES-GCM context, ret=%d", ret); return LT_CRYPTO_ERR; } return LT_OK; @@ -58,21 +63,32 @@ lt_ret_t lt_aesgcm_decrypt_init(void *ctx, const uint8_t *key, const uint32_t ke } lt_ret_t lt_aesgcm_encrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, const uint8_t *add, - const uint32_t add_len, const uint8_t *plaintext, const uint32_t plaintext_len, - uint8_t *ciphertext, const uint32_t ciphertext_len) + const uint32_t add_len, const uint8_t *plaintext, + const uint32_t plaintext_len, uint8_t *ciphertext, + const uint32_t ciphertext_len) { lt_ctx_trezor_crypto_t *_ctx = (lt_ctx_trezor_crypto_t *)ctx; + if (ciphertext_len < TR01_L3_TAG_SIZE) { + LT_LOG_ERROR("AES-GCM ciphertext buffer smaller than tag length: %" PRIu32 " < %u", + ciphertext_len, TR01_L3_TAG_SIZE); + return LT_PARAM_ERR; + } + if (plaintext_len != ciphertext_len - TR01_L3_TAG_SIZE) { + LT_LOG_ERROR("Invalid AES-GCM plaintext/ciphertext length: %" PRIu32 " != %" PRIu32 " - %u", + plaintext_len, ciphertext_len, TR01_L3_TAG_SIZE); return LT_PARAM_ERR; } // Copy plaintext into ciphertext, as Trezor's gcm_encrypt_message() works in-place memcpy(ciphertext, plaintext, plaintext_len); - int ret = gcm_encrypt_message(iv, iv_len, add, add_len, ciphertext, plaintext_len, ciphertext + plaintext_len, - TR01_L3_TAG_SIZE, &_ctx->aesgcm_encrypt_ctx); + int ret = gcm_encrypt_message(iv, iv_len, add, add_len, ciphertext, plaintext_len, + ciphertext + plaintext_len, TR01_L3_TAG_SIZE, + &_ctx->aesgcm_encrypt_ctx); if (ret != RETURN_GOOD) { + LT_LOG_ERROR("AES-GCM encryption failed, ret=%d", ret); return LT_CRYPTO_ERR; } @@ -80,21 +96,32 @@ lt_ret_t lt_aesgcm_encrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, } lt_ret_t lt_aesgcm_decrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, const uint8_t *add, - const uint32_t add_len, const uint8_t *ciphertext, const uint32_t ciphertext_len, - uint8_t *plaintext, const uint32_t plaintext_len) + const uint32_t add_len, const uint8_t *ciphertext, + const uint32_t ciphertext_len, uint8_t *plaintext, + const uint32_t plaintext_len) { lt_ctx_trezor_crypto_t *_ctx = (lt_ctx_trezor_crypto_t *)ctx; + if (ciphertext_len < TR01_L3_TAG_SIZE) { + LT_LOG_ERROR("AES-GCM ciphertext buffer smaller than tag length: %" PRIu32 " < %u", + ciphertext_len, TR01_L3_TAG_SIZE); + return LT_PARAM_ERR; + } + if (plaintext_len != ciphertext_len - TR01_L3_TAG_SIZE) { + LT_LOG_ERROR("Invalid AES-GCM plaintext/ciphertext length: %" PRIu32 " != %" PRIu32 " - %u", + plaintext_len, ciphertext_len, TR01_L3_TAG_SIZE); return LT_PARAM_ERR; } // Copy ciphertext into plaintext, as Trezor's gcm_decrypt_message() works in-place memcpy(plaintext, ciphertext, plaintext_len); - int ret = gcm_decrypt_message(iv, iv_len, add, add_len, plaintext, plaintext_len, ciphertext + plaintext_len, - TR01_L3_TAG_SIZE, &_ctx->aesgcm_decrypt_ctx); + int ret = gcm_decrypt_message(iv, iv_len, add, add_len, plaintext, plaintext_len, + ciphertext + plaintext_len, TR01_L3_TAG_SIZE, + &_ctx->aesgcm_decrypt_ctx); if (ret != RETURN_GOOD) { + LT_LOG_ERROR("AES-GCM decryption failed, ret=%d", ret); return LT_CRYPTO_ERR; } diff --git a/cal/trezor_crypto/lt_trezor_crypto_hmac_sha256.c b/cal/trezor_crypto/lt_trezor_crypto_hmac_sha256.c index facca4957..9a9c7949f 100644 --- a/cal/trezor_crypto/lt_trezor_crypto_hmac_sha256.c +++ b/cal/trezor_crypto/lt_trezor_crypto_hmac_sha256.c @@ -11,8 +11,8 @@ #include "libtropic_common.h" #include "lt_hmac_sha256.h" -lt_ret_t lt_hmac_sha256(const uint8_t *key, const uint32_t key_len, const uint8_t *input, const uint32_t input_len, - uint8_t *output) +lt_ret_t lt_hmac_sha256(const uint8_t *key, const uint32_t key_len, const uint8_t *input, + const uint32_t input_len, uint8_t *output) { hmac_sha256(key, key_len, input, input_len, output); return LT_OK; diff --git a/cal/wolfcrypt/lt_wolfcrypt_aesgcm.c b/cal/wolfcrypt/lt_wolfcrypt_aesgcm.c index 7c7ab1fcb..698446490 100644 --- a/cal/wolfcrypt/lt_wolfcrypt_aesgcm.c +++ b/cal/wolfcrypt/lt_wolfcrypt_aesgcm.c @@ -27,8 +27,8 @@ * @param key_len Length of the key * @return LT_OK if success, otherwise returns other error code. */ -static lt_ret_t lt_aesgcm_init(lt_aesgcm_ctx_wolfcrypt_t *ctx, void *heap, const int dev_id, const uint8_t *key, - const uint32_t key_len) +static lt_ret_t lt_aesgcm_init(lt_aesgcm_ctx_wolfcrypt_t *ctx, void *heap, const int dev_id, + const uint8_t *key, const uint32_t key_len) { int ret; @@ -90,13 +90,15 @@ lt_ret_t lt_aesgcm_decrypt_init(void *ctx, const uint8_t *key, const uint32_t ke } lt_ret_t lt_aesgcm_encrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, const uint8_t *add, - const uint32_t add_len, const uint8_t *plaintext, const uint32_t plaintext_len, - uint8_t *ciphertext, const uint32_t ciphertext_len) + const uint32_t add_len, const uint8_t *plaintext, + const uint32_t plaintext_len, uint8_t *ciphertext, + const uint32_t ciphertext_len) { lt_ctx_wolfcrypt_t *_ctx = (lt_ctx_wolfcrypt_t *)ctx; - int ret = wc_AesGcmEncrypt(&_ctx->aesgcm_encrypt_ctx.ctx, ciphertext, plaintext, plaintext_len, iv, iv_len, - ciphertext + (ciphertext_len - TR01_L3_TAG_SIZE), TR01_L3_TAG_SIZE, add, add_len); + int ret = wc_AesGcmEncrypt(&_ctx->aesgcm_encrypt_ctx.ctx, ciphertext, plaintext, plaintext_len, iv, + iv_len, ciphertext + (ciphertext_len - TR01_L3_TAG_SIZE), + TR01_L3_TAG_SIZE, add, add_len); if (ret != 0) { LT_LOG_ERROR("AES-GCM encryption failed, ret=%d (%s)", ret, wc_GetErrorString(ret)); return LT_CRYPTO_ERR; @@ -106,13 +108,15 @@ lt_ret_t lt_aesgcm_encrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, } lt_ret_t lt_aesgcm_decrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, const uint8_t *add, - const uint32_t add_len, const uint8_t *ciphertext, const uint32_t ciphertext_len, - uint8_t *plaintext, const uint32_t plaintext_len) + const uint32_t add_len, const uint8_t *ciphertext, + const uint32_t ciphertext_len, uint8_t *plaintext, + const uint32_t plaintext_len) { lt_ctx_wolfcrypt_t *_ctx = (lt_ctx_wolfcrypt_t *)ctx; - int ret = wc_AesGcmDecrypt(&_ctx->aesgcm_decrypt_ctx.ctx, plaintext, ciphertext, plaintext_len, iv, iv_len, - ciphertext + (ciphertext_len - TR01_L3_TAG_SIZE), TR01_L3_TAG_SIZE, add, add_len); + int ret = wc_AesGcmDecrypt(&_ctx->aesgcm_decrypt_ctx.ctx, plaintext, ciphertext, plaintext_len, iv, + iv_len, ciphertext + (ciphertext_len - TR01_L3_TAG_SIZE), + TR01_L3_TAG_SIZE, add, add_len); if (ret != 0) { LT_LOG_ERROR("AES-GCM decryption failed, ret=%d (%s)", ret, wc_GetErrorString(ret)); return LT_CRYPTO_ERR; diff --git a/cal/wolfcrypt/lt_wolfcrypt_hmac_sha256.c b/cal/wolfcrypt/lt_wolfcrypt_hmac_sha256.c index add5104bd..87e40d344 100644 --- a/cal/wolfcrypt/lt_wolfcrypt_hmac_sha256.c +++ b/cal/wolfcrypt/lt_wolfcrypt_hmac_sha256.c @@ -14,8 +14,8 @@ #include "libtropic_logging.h" #include "lt_hmac_sha256.h" -lt_ret_t lt_hmac_sha256(const uint8_t *key, const uint32_t key_len, const uint8_t *input, const uint32_t input_len, - uint8_t *output) +lt_ret_t lt_hmac_sha256(const uint8_t *key, const uint32_t key_len, const uint8_t *input, + const uint32_t input_len, uint8_t *output) { int ret; Hmac hmac; diff --git a/cal/wolfcrypt/lt_wolfcrypt_x25519.c b/cal/wolfcrypt/lt_wolfcrypt_x25519.c index 0b37a8658..3460a90a1 100644 --- a/cal/wolfcrypt/lt_wolfcrypt_x25519.c +++ b/cal/wolfcrypt/lt_wolfcrypt_x25519.c @@ -29,18 +29,21 @@ lt_ret_t lt_X25519(const uint8_t *privkey, const uint8_t *pubkey, uint8_t *secre ret = wc_curve25519_init(&wc_priv); if (ret != 0) { - LT_LOG_ERROR("Failed to initialize X25519 private key, ret=%d (%s)", ret, wc_GetErrorString(ret)); + LT_LOG_ERROR("Failed to initialize X25519 private key, ret=%d (%s)", ret, + wc_GetErrorString(ret)); return LT_CRYPTO_ERR; } ret = wc_curve25519_init(&wc_pub); if (ret != 0) { - LT_LOG_ERROR("Failed to initialize X25519 public key, ret=%d (%s)", ret, wc_GetErrorString(ret)); + LT_LOG_ERROR("Failed to initialize X25519 public key, ret=%d (%s)", ret, + wc_GetErrorString(ret)); lt_ret = LT_CRYPTO_ERR; goto lt_X25519_cleanup; } - ret = wc_curve25519_import_private_ex(privkey, TR01_X25519_KEY_LEN, &wc_priv, EC25519_LITTLE_ENDIAN); + ret = wc_curve25519_import_private_ex(privkey, TR01_X25519_KEY_LEN, &wc_priv, + EC25519_LITTLE_ENDIAN); if (ret != 0) { LT_LOG_ERROR("Failed to import X25519 private key, ret=%d (%s)", ret, wc_GetErrorString(ret)); lt_ret = LT_CRYPTO_ERR; @@ -50,7 +53,8 @@ lt_ret_t lt_X25519(const uint8_t *privkey, const uint8_t *pubkey, uint8_t *secre #ifdef WOLFSSL_CURVE25519_BLINDING ret = wc_InitRng(&rng); if (ret != 0) { - LT_LOG_ERROR("Failed to init RNG for X25519 blinding, ret=%d (%s)", ret, wc_GetErrorString(ret)); + LT_LOG_ERROR("Failed to init RNG for X25519 blinding, ret=%d (%s)", ret, + wc_GetErrorString(ret)); lt_ret = LT_CRYPTO_ERR; goto lt_X25519_cleanup; } @@ -58,7 +62,8 @@ lt_ret_t lt_X25519(const uint8_t *privkey, const uint8_t *pubkey, uint8_t *secre ret = wc_curve25519_set_rng(&wc_priv, &rng); if (ret != 0) { - LT_LOG_ERROR("Failed to set RNG for X25519 key blinding, ret=%d (%s)", ret, wc_GetErrorString(ret)); + LT_LOG_ERROR("Failed to set RNG for X25519 key blinding, ret=%d (%s)", ret, + wc_GetErrorString(ret)); lt_ret = LT_CRYPTO_ERR; goto lt_X25519_cleanup; } @@ -72,9 +77,11 @@ lt_ret_t lt_X25519(const uint8_t *privkey, const uint8_t *pubkey, uint8_t *secre } word32 secret_out_len = TR01_X25519_KEY_LEN; - ret = wc_curve25519_shared_secret_ex(&wc_priv, &wc_pub, secret, &secret_out_len, EC25519_LITTLE_ENDIAN); + ret = wc_curve25519_shared_secret_ex(&wc_priv, &wc_pub, secret, &secret_out_len, + EC25519_LITTLE_ENDIAN); if (ret != 0) { - LT_LOG_ERROR("Failed to compute X25519 shared secret key, ret=%d (%s)", ret, wc_GetErrorString(ret)); + LT_LOG_ERROR("Failed to compute X25519 shared secret key, ret=%d (%s)", ret, + wc_GetErrorString(ret)); lt_ret = LT_CRYPTO_ERR; goto lt_X25519_cleanup; } @@ -90,7 +97,8 @@ lt_ret_t lt_X25519(const uint8_t *privkey, const uint8_t *pubkey, uint8_t *secre if (rng_initialized) { ret = wc_FreeRng(&rng); if (ret != 0) { - LT_LOG_WARN("Failed to free RNG used for X25519 blinding, ret=%d (%s)", ret, wc_GetErrorString(ret)); + LT_LOG_WARN("Failed to free RNG used for X25519 blinding, ret=%d (%s)", ret, + wc_GetErrorString(ret)); } } #endif @@ -111,7 +119,8 @@ lt_ret_t lt_X25519_scalarmult(const uint8_t *sk, uint8_t *pk) ret = wc_curve25519_init(&wc_secret); if (ret != 0) { - LT_LOG_ERROR("Failed to initialize X25519 private key, ret=%d (%s)", ret, wc_GetErrorString(ret)); + LT_LOG_ERROR("Failed to initialize X25519 private key, ret=%d (%s)", ret, + wc_GetErrorString(ret)); return LT_CRYPTO_ERR; } @@ -125,7 +134,8 @@ lt_ret_t lt_X25519_scalarmult(const uint8_t *sk, uint8_t *pk) #ifdef WOLFSSL_CURVE25519_BLINDING ret = wc_InitRng(&rng); if (ret != 0) { - LT_LOG_ERROR("Failed to init RNG for X25519 blinding, ret=%d (%s)", ret, wc_GetErrorString(ret)); + LT_LOG_ERROR("Failed to init RNG for X25519 blinding, ret=%d (%s)", ret, + wc_GetErrorString(ret)); lt_ret = LT_CRYPTO_ERR; goto lt_X25519_scalarmult_cleanup; } @@ -133,7 +143,8 @@ lt_ret_t lt_X25519_scalarmult(const uint8_t *sk, uint8_t *pk) ret = wc_curve25519_set_rng(&wc_secret, &rng); if (ret != 0) { - LT_LOG_ERROR("Failed to set RNG for X25519 key blinding, ret=%d (%s)", ret, wc_GetErrorString(ret)); + LT_LOG_ERROR("Failed to set RNG for X25519 key blinding, ret=%d (%s)", ret, + wc_GetErrorString(ret)); lt_ret = LT_CRYPTO_ERR; goto lt_X25519_scalarmult_cleanup; } @@ -158,7 +169,8 @@ lt_ret_t lt_X25519_scalarmult(const uint8_t *sk, uint8_t *pk) if (rng_initialized) { ret = wc_FreeRng(&rng); if (ret != 0) { - LT_LOG_WARN("Failed to free RNG used for X25519 blinding, ret=%d (%s)", ret, wc_GetErrorString(ret)); + LT_LOG_WARN("Failed to free RNG used for X25519 blinding, ret=%d (%s)", ret, + wc_GetErrorString(ret)); } } #endif diff --git a/docs/common/examples_descriptions/fw_update.md b/docs/common/examples_descriptions/fw_update.md index 11c8c3c1e..34eca6788 100644 --- a/docs/common/examples_descriptions/fw_update.md +++ b/docs/common/examples_descriptions/fw_update.md @@ -3,6 +3,9 @@ This example explains the firmware update process for both ABAB and ACAB silicon - How to read the current firmware versions. - How to update the firmware using `lt_do_mutable_fw_update()`. + !!! info "Updating FW with `lt_do_mutable_fw_update()` in Your Application" + If you are using `lt_do_mutable_fw_update()` in your application to update TROPIC01's FW, make sure to reinitialize the handle (`lt_handle_t`) after the function returns successfully, i.e. call `lt_deinit()` and `lt_init()`. + !!! info "TROPIC01 Firmware" For more information about the firmware itself, refer to the [TROPIC01 Firmware](/reference/tropic01_fw.md) section. diff --git a/docs/compatibility/host_platforms/index.md b/docs/compatibility/host_platforms/index.md index 65ea5cf8d..9dbfea4ff 100644 --- a/docs/compatibility/host_platforms/index.md +++ b/docs/compatibility/host_platforms/index.md @@ -10,4 +10,8 @@ These are the currently supported host platforms: All HAL files can be found in the `libtropic/hal/` directory. !!! tip - Cannot see your platform in the list above? Refer to [Adding a New Host Platform](../../for_contributors/adding_host_platform.md) section with instructions on how to add a support for it. \ No newline at end of file + Cannot see your platform in the list above? Refer to [Adding a New Host Platform](../../for_contributors/adding_host_platform.md) section with instructions on how to add a support for it. + +!!! warning "Warning: Endianness" + Currently, the Libtropic code is compatible with little-endian machines only due to handling + of integers in packed structures. \ No newline at end of file diff --git a/docs/compatibility/host_platforms/stm32.md b/docs/compatibility/host_platforms/stm32.md index 824e4976f..d5df2ebfa 100644 --- a/docs/compatibility/host_platforms/stm32.md +++ b/docs/compatibility/host_platforms/stm32.md @@ -4,6 +4,8 @@ Currently supported STM32 platforms are: - NUCLEO-F439ZI - NUCLEO-L432KC - Using interrupt pin (`LT_USE_INT_PIN`) is not supported for this platform. +- STM32U5xx series MCUs, tested with: + - NUCLEO-U545RE-Q HALs for these ports are available in the `libtropic/hal/stm32/` directory. diff --git a/docs/for_contributors/adding_host_platform.md b/docs/for_contributors/adding_host_platform.md index 5451818bf..dc5e26447 100644 --- a/docs/for_contributors/adding_host_platform.md +++ b/docs/for_contributors/adding_host_platform.md @@ -1,5 +1,10 @@ # Adding a New Host Platform -Libtropic is written to be *platform-independent*, so no changes to the main code base are needed when adding support for a new host platform. However, to define how communication on the L1 Layer will work, a new Hardware Abstraction Layer (HAL) must be implemented. Currently available HALs are located in `hal/`. +Libtropic is written to be *platform-independent*, so it is possible to add support for a new host platform by creating a new Hardware Abstraction Layer (HAL). The HAL implements low-level functionality, mainly communication on the L1 Layer. Currently available HALs are located in `hal/`. + +!!! warning "Warning: Endianness" + Currently, the Libtropic code is compatible with little-endian machines only due to handling + of integers in packed structures. If your platform uses different endianness, it cannot be + supported for now without patching the code base. ## Guide This guide will walk you through adding support for a new platform. In this guide, we will add a support for a microcontroller called `my_mcu` on a board `my_board`. The directory structure will be different if you create a port e.g., for an operating system. In that case, please get inspired by existing ports (POSIX, Linux). diff --git a/docs/for_contributors/codechecker.md b/docs/for_contributors/codechecker.md new file mode 100644 index 000000000..74827d2b9 --- /dev/null +++ b/docs/for_contributors/codechecker.md @@ -0,0 +1,56 @@ +# Using the CodeChecker +The CodeChecker is a tool for performing static code analysis and generating reports. +We provide scripts and custom configuration for running the CodeChecker. + +We regularly run CodeChecker to check for any potential bugs or security issues. It is also +recommended to run the CodeChecker yourself on any code you plan to contribute, as it can discover +issues that other tools (compiler, ASAN, ...) can miss. + +Note that the CodeChecker is supported on Linux and macOS only. + +## Generating Reports +You need to install the following dependencies: + +- CodeChecker + - Check out the [official repository](https://github.com/Ericsson/codechecker) for guidance. +- Checkers for CodeChecker: + - clang-tidy + - clangsa +- jq (used by our script for merging JSON reports) + +We generate reports from multiple projects (examples and tests) to cover as much CALs and HALs +as possible. The reports are then merged and exported to HTML. + +To generate HTML report, you can use our convenience script. Reports will be +generated to `.codechecker/reports_html` in the Libtropic repository. + +!!! example "Generating HTML report" + === ":fontawesome-brands-linux: Linux" + ```bash { .copy } + # Run from root directory of the Libtropic repository. + scripts/codechecker/run_checks.sh + ``` + + === ":fontawesome-brands-apple: macOS" + TBA + +??? note "Note: Running from a different directory" + The script also supports running from a different directory, but you have to pass + a path to the Libtropic repository as a first argument: + + !!! example "Generating HTML report from any directory" + === ":fontawesome-brands-linux: Linux" + ```bash { .copy } + scripts/codechecker/run_checks.sh + ``` + + === ":fontawesome-brands-apple: macOS" + TBA + +If the script executes without any errors, exports will be ready and you can open +`.codechecker/reports_html/index.html` in your favourite web browser. + +## Remarks +The current CodeChecker configuration is in YAML format, as it is more human-readable than JSON and also supports comments. + +The configuration file enables some strict checkers, which may produce a lot of warnings. It is recommended to run the analysis using the full configuration at least once. After that, you can manually disable any checkers you find unnecessary. \ No newline at end of file diff --git a/docs/for_contributors/index.md b/docs/for_contributors/index.md index e12ba2c2d..e13921990 100644 --- a/docs/for_contributors/index.md +++ b/docs/for_contributors/index.md @@ -2,5 +2,6 @@ - [Contributing Guide](contributing_guide.md) - [Building the Documentation](building_documentation.md) - [Tests](tests/index.md) +- [Using the CodeChecker](codechecker.md) - [Adding a New Host Platform](adding_host_platform.md) - [Adding a New Cryptographic Functionality Provider](adding_cfp.md) \ No newline at end of file diff --git a/docs/for_contributors/tests/functional_mock_tests.md b/docs/for_contributors/tests/functional_mock_tests.md index dc5fcc2c8..442186fc6 100644 --- a/docs/for_contributors/tests/functional_mock_tests.md +++ b/docs/for_contributors/tests/functional_mock_tests.md @@ -97,7 +97,7 @@ Change the lines marked with `TODO`. * @brief TODO: FILL ME * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include "libtropic.h" diff --git a/docs/reference/integrating_libtropic/how_to_use/index.md b/docs/reference/integrating_libtropic/how_to_use/index.md index afd7f1633..b61daf573 100644 --- a/docs/reference/integrating_libtropic/how_to_use/index.md +++ b/docs/reference/integrating_libtropic/how_to_use/index.md @@ -82,7 +82,7 @@ int main(void) { // This should be done only once for a specific handle. // If you need to initialize the specific handle again, call lt_deinit() // first. - lt_ret_t ret = lt_init(h); + lt_ret_t ret = lt_init(&h); if (LT_OK != ret) { return -1; } @@ -90,7 +90,7 @@ int main(void) { // 8. Do your stuff. // 9. Deinitialize the handle. - ret = lt_deinit(h); + ret = lt_deinit(&h); if (LT_OK != ret) { return -1; } diff --git a/docs/reference/logging.md b/docs/reference/logging.md index 62b554056..b95dd7ded 100644 --- a/docs/reference/logging.md +++ b/docs/reference/logging.md @@ -3,7 +3,7 @@ Libtropic contains a logging functionality, which is disabled by default. You may find it useful to enable logging during Libtropic evaluation or integration. There are five logging levels: -- None (default unless compiling *tests* or *examples*), +- None (default unless compiling tests), - Error, - Warning, - Info, diff --git a/docs/tutorials/index.md b/docs/tutorials/index.md index 282527f0c..8577c3e4a 100644 --- a/docs/tutorials/index.md +++ b/docs/tutorials/index.md @@ -13,8 +13,6 @@ If you have already experimented with our TROPIC01 Model and you are ready to tr Pick a set of tutorials based on your host platform: -- :fontawesome-brands-linux: Linux - - [:fontawesome-solid-microchip: Linux SPI](linux/spi/index.md) - - [:fontawesome-brands-usb: TROPIC01 USB Devkit](linux/usb_devkit/index.md) +- [:fontawesome-brands-linux: Linux](linux/index.md) - [:simple-espressif: ESP32](esp32/index.md) - [:simple-stmicroelectronics: STM32](stm32/index.md) \ No newline at end of file diff --git a/docs/tutorials/linux/index.md b/docs/tutorials/linux/index.md new file mode 100644 index 000000000..8ae57e96f --- /dev/null +++ b/docs/tutorials/linux/index.md @@ -0,0 +1,5 @@ +# Linux Tutorials +We offer the following sets of tutorials for Linux: + +- [Linux SPI Tutorials](spi/index.md) +- [TROPIC01 USB Devkit Tutorials](usb_devkit/index.md) \ No newline at end of file diff --git a/docs/tutorials/linux/spi/full_chain_verification.md b/docs/tutorials/linux/spi/full_chain_verification.md new file mode 100644 index 000000000..9d0c51c76 --- /dev/null +++ b/docs/tutorials/linux/spi/full_chain_verification.md @@ -0,0 +1,87 @@ +# 4. Full Chain Verification Example Tutorial + +In this tutorial, you will learn about one of the steps required to verify the authenticity of the TROPIC01 certificate chain — a process that should be done by Tropic Square customers during provisioning of their device which integrates TROPIC01. + +!!! info "Important: read before proceeding" + Detailed information about TROPIC01 device identity and related Tropic Square Public Key Infrastructure (PKI) is provided in the *Device Identity and PKI Application Note* (ODN_TR01_app_003) available on [GitHub](https://github.com/tropicsquare/tropic01/tree/main#application-notes). It is recommended to read this document before proceeding to understand the process described in this tutorial, as here we provide only minimal information to try the process of the certificate chain verification. + +!!! warning "Compatibility" + Only production chips contain the full certificate chain. Sample chips are not supported by this tutorial. If you encounter problems in this tutorial, you probably have an incompatible chip. Find your TROPIC01's part number ([check the FAQ](../../../faq.md#what-is-the-part-number-pn-of-my-tropic01)) and check the [Catalog list](https://github.com/tropicsquare/tropic01#available-parts) to see if your chip is a production one. + +The TROPIC01 comes with its own unique cryptographic identity in the form of a Secure Channel key pair and a certificate. The certificate is issued by Tropic Square PKI which provides a framework for verifying the origin of each TROPIC01 chip ever produced. In this tutorial, we will learn: + +- How to load the certificate chain from a TROPIC01 chip using the `lt_get_info_cert_store()` function from the Libtropic API. +- How to verify all certificates in the chain using OpenSSL CLI with a provided script. + +## Load the Certificates +First, we will load the certificates from your TROPIC01 using a provided C application available in `examples/linux/spi/full_chain_verification`. + +!!! example "Building and running the app" + === ":fontawesome-brands-linux: Linux" + Go to the example's project directory: + ```bash { .copy } + cd examples/linux/spi/full_chain_verification/ + ``` + + Create a `build/` directory and switch to it: + ```bash { .copy } + mkdir build/ + cd build/ + ``` + + And finally, build and run the application: + ```bash { .copy } + cmake .. + make + ./libtropic_dump_certificates + ``` + + The certificates will be stored in the build directory. If the application completed execution without any errors, you should see the following certificates in the build directory: + + - `t01_ca_cert.der` + - `t01_ese_cert.der` + - `t01_xxxx_ca_cert.der` + - `tropicsquare_root_ca_cert.der` + + === ":fontawesome-brands-apple: macOS" + TBA + + === ":fontawesome-brands-windows: Windows" + TBA + +## Verify the Certificates +After loading the certificates from the TROPIC01 chip, we will verify the certificates using a provided script. + +!!! example "Verifying the certificates" + === ":fontawesome-brands-linux: Linux" + Go to the example's project directory: + ```bash { .copy } + cd examples/linux/spi/full_chain_verification/ + ``` + + Run the `verify.sh` script. It accepts a single argument: a path to a directory where certificates that we loaded from the TROPIC01 are located. + ```bash { .copy } + ./verify.sh build/ + ``` + + If all certificates are verified successfully, the script will return 0 and output the following message: `All certificates verified successfully!` + + === ":fontawesome-brands-apple: macOS" + TBA + + === ":fontawesome-brands-windows: Windows" + TBA + +### Understanding the Script +The script demonstrates almost all important steps in the verification process: + +1. Download revocation lists from the URLs specified in the certificates which we obtained from the TROPIC01. +2. Check all certificates we obtained from the TROPIC01 using the chain and revocation lists we downloaded from the Tropic Square PKI website. +3. Check the root certificate (simplified, no out-of-band check provided). + +Authenticity check of the root certificate in step 3 is not fully implemented. The root certificate can be obtained from the chip, we provide it in this repository and it is also available on the Tropic Square PKI website. **Do not blindly trust this certificate** file from GitHub alone. To protect against repository compromise, the trust has to be established by verifying the certificate fingerprint through an independent channel. Tropic Square customers can obtain the verified fingerprint via direct contact with [Customer Support](https://support.tropicsquare.com). + +The script contains comments about each step, so refer to the code of the script for more details about the implementation. It is also recommended to study the *Device Identity and PKI Application Note* (ODN_TR01_app_003) (available [on GitHub](https://github.com/tropicsquare/tropic01/tree/main#application-notes)) to fully understand the principles described in this tutorial. + +!!! note "Alternative implementation of the verification" + The script verifies the TROPIC01 certificates against certificate authority certificates downloaded from the Tropic Square PKI website. As the same certificates are present also in the TROPIC01 itself, those can be used instead. The importance of verifying the root certificate independently remains the key part of the process. diff --git a/docs/tutorials/linux/spi/index.md b/docs/tutorials/linux/spi/index.md index b86265b0b..0ee1c9ead 100644 --- a/docs/tutorials/linux/spi/index.md +++ b/docs/tutorials/linux/spi/index.md @@ -59,6 +59,7 @@ After that, setup your system: 1. [Chip Identification](identify_chip.md) 2. [FW Update](fw_update.md) 3. [Hello, World!](hello_world.md) +4. [Full Chain Verification](full_chain_verification.md) ## FAQ If you encounter any issues, please check the [FAQ](../../../faq.md) before filing an issue or reaching out to our [support](https://support.tropicsquare.com/). \ No newline at end of file diff --git a/docs/tutorials/model/first_steps.md b/docs/tutorials/model/first_steps.md index 395810990..3cfdce0d0 100644 --- a/docs/tutorials/model/first_steps.md +++ b/docs/tutorials/model/first_steps.md @@ -93,4 +93,4 @@ If you see the output, congratulations! 🎉 You used Libtropic to send a *Ping* -[Next tutorial :material-arrow-right:](hw_wallet.md){ .md-button } \ No newline at end of file +[Next tutorial :material-arrow-right:](understanding_libtropic.md){ .md-button } \ No newline at end of file diff --git a/docs/tutorials/model/hw_wallet.md b/docs/tutorials/model/hw_wallet.md index 859d29b15..0dc9f634c 100644 --- a/docs/tutorials/model/hw_wallet.md +++ b/docs/tutorials/model/hw_wallet.md @@ -1,5 +1,5 @@ -# 2. Hardware Wallet Example Tutorial -This example demonstrates how to use configuration objects and different pairing keys to manage access to TROPIC01 features. A hardware wallet device scenario is used as a model for this example. +# 3. Hardware Wallet Example Tutorial +This example demonstrates how to use configuration objects and different pairing keys to manage access to TROPIC01 features. The concept is presented on a hardware wallet scenario. !!! success "Prerequisites" It is assumed that you have already completed the previous TROPIC01 Model tutorials. If not, start [here](../model/index.md). diff --git a/docs/tutorials/model/macandd.md b/docs/tutorials/model/macandd.md index 852c96cb9..271911afc 100644 --- a/docs/tutorials/model/macandd.md +++ b/docs/tutorials/model/macandd.md @@ -1,4 +1,4 @@ -# 3. Mac-And-Destroy Example Tutorial +# 4. Mac-And-Destroy Example Tutorial This example illustrates MAC-And-Destroy, the flagship feature of TROPIC01. !!! success "Prerequisites" diff --git a/docs/tutorials/model/separate_api.md b/docs/tutorials/model/separate_api.md index fa7f5d652..0551ca15b 100644 --- a/docs/tutorials/model/separate_api.md +++ b/docs/tutorials/model/separate_api.md @@ -1,4 +1,4 @@ -# 4. Separate API Example Tutorial +# 5. Separate API Example Tutorial This example showcases the Libtropic's Separate API. It is functionally similar to the *Hello, World!* example, but it uses distinct API calls for incoming and outgoing data. This approach is useful for secure, tunneled communication, such as during chip provisioning in a factory. !!! success "Prerequisites" diff --git a/docs/tutorials/model/understanding_libtropic.md b/docs/tutorials/model/understanding_libtropic.md index 2b0488777..b23d7fd02 100644 --- a/docs/tutorials/model/understanding_libtropic.md +++ b/docs/tutorials/model/understanding_libtropic.md @@ -1 +1,205 @@ -# 2. Understanding Libtropic \ No newline at end of file +# 2. Understanding Libtropic + +This chapter is a short TL;DR that helps you get oriented quickly so you can continue with the next tutorials. +It intentionally links to deeper reference pages instead of duplicating them. + +If you are interested in details about the TROPIC01 chip itself, refer to the [TROPIC01 repository](https://github.com/tropicsquare/tropic01), where we provide datasheets and a documentation of the low-level user API. + +??? question "Which version of the TROPIC01 Datasheet / User API should I use?" + There are several versions of the documents. The right version depends on the TROPIC01 Application Firmware version. + This is not relevant for the model (use the latest), but it matters for the real chip. You will learn + how to read the Application Firmware version in the tutorial for each platform, based on which you can select + the right document version. + +--- + +## Communication Layers +Libtropic communicates with TROPIC01 using a layered protocol described in the reference architecture page. + +- Read: [Libtropic Architecture](../../reference/libtropic_architecture.md) + +The practical takeaway: + +- **L1 (Layer 1) is a raw communication.** Part of this layer is implemented in Libtropic core, part in the Hardware Abstraction Layer (explained below) of the platform. + - You will normally never send raw L1 data manually when using Libtropic. +- **L2 (Layer 2) is an unencrypted layer.** It is used for reading chip information and setup tasks (including setting up L3 and firmware update). + - Unit of communication is a frame. Libtropic sends Requests and receives Responses from TROPIC01. +- **L3 (Layer 3) is encrypted and requires an established Secure Channel Session.** Majority of TROPIC01 functionality is available over L3 only. + - Unit of communication is a packet. Libtropic sends Commands and receives Results from TROPIC01. + +If you’re unsure which API call is L2 vs L3, the function naming and tutorial text usually hint at it (e.g., “L2 Request”, “L3 Command”), and the Doxygen API reference is the ultimate source. + +- Read: [API reference](../../doxygen/build/html/index.html) + +--- + +## Libtropic Architecture in 30 Seconds +At a high level: + +- **Core: Public API functions** are in `include/libtropic.h` and implemented in `src/`. + - Refer to: [API reference](../../doxygen/build/html/index.html) +- **HAL (hardware abstraction layer for the host platform)** lives in `hal/` and provides the low-level transport (SPI on embedded targets, TCP to the model, etc.). + - It allows us to run Libtropic on various hardware: from Linux computers to ESP32 microcontrollers. + - Supported platforms: read [Host Platforms](../../compatibility/host_platforms/index.md) +- **CAL (cryptography abstraction layer)** lives in `cal/` and plugs in “Cryptographic Functionality Providers” (CFP). + - We need cryptographic operations available in Libtropic to securely communicate with the TROPIC01 on Layer 3 (via the Secure Channel Session, which is encrypted). + - CAL allows us to support multiple “Cryptographic Functionality Providers”, which is our umbrella term for crypto libraries (e.g., MbedTLS, OpenSSL) and hardware crypto accelerators. + - Read more: [CFPs](../../compatibility/cfps/index.md) + +CAL and HAL can be chosen at build time: + +- Read: [Integrating Libtropic](../../reference/integrating_libtropic/index.md) + +--- + +## `lt_handle_t`: Your per-chip context +Almost all Libtropic calls operate on an `lt_handle_t`. Think of it as a **context object** for one TROPIC01 instance. + +What it contains (simplified): + +- **L2 state** (including a pointer to your HAL device context at `h.l2.device`). +- **L3 state** (Secure Channel Session status, an L3 buffer, and a pointer to your CAL/CFP context at `h.l3.crypto_ctx`). +- A few metadata used by the library. + +Practical rules: + +- Create **one handle per chip** (you can have multiple handles if you talk to multiple chips). +- The handle stores **pointers** to your HAL device structure and CAL/CFP crypto context structure. These objects must stay alive for the whole lifetime of the handle (Libtropic does not copy them). +- Set the pointers **before** calling `lt_init(&h)`. +- If `lt_init(&h)` fails, do **not** call `lt_deinit(&h)` (cleanup is handled internally). +- As a general C best practice, initialize the handle to zero before filling in pointers (e.g., `lt_handle_t h = {0};`). + +Also remember the basic lifecycle: + +1. Initialize your platform's hardware interfaces (GPIO, SPI, clocks, etc.) and selected CFP. +2. Fill your HAL device struct and CAL crypto context struct. +3. Point the handle to them (`h.l2.device = ...`, `h.l3.crypto_ctx = ...`). +4. Call `lt_init(&h)` and check the return code. +5. Use L2 requests and/or establish a Secure Channel Session for L3. +6. Call `lt_session_abort(&h)` when you are done with L3. +7. Call `lt_deinit(&h)` at the end. + +Minimal initialization pattern (illustrative, not a full program): + +```c +lt_handle_t h = {0}; +lt_dev__t dev; +lt_ctx__t crypto; + +h.l2.device = &dev; +h.l3.crypto_ctx = &crypto; +lt_init(&h); +``` + +!!! tip "Where do I see the real initialization?" + The contents of `lt_dev__t` (HAL device struct) depend on the host platform (SPI pins/speed, TCP host/port for the model, etc.). + The easiest way to learn what to fill in is to look at the corresponding example for your platform and find the code that prepares the handle right before `lt_init(&h)`. + +For a complete example (including which headers to include and what needs to be initialized inside the HAL device struct), see: + +- [How to Use](../../reference/integrating_libtropic/how_to_use/index.md) + +--- + +## Secure Channel Session Basics (and Pairing Keys) +Most interesting TROPIC01 features are accessed via **L3 Layer**, so you will frequently do this flow: + +!!! note "Terminology note" + Secure Channel Session is a protocol used for secure communication on L3 Layer. It is sometimes shortened to Secure Channel or Secure Session. + + More information in the TROPIC01 Datasheet. + +1. Use L2 requests to read info or reboot to the right mode. +2. Start a Secure Session with a selected **pairing key slot**. + - We recommend using our helper `lt_verify_chip_and_start_secure_session`, which will handle all L2 communication required to establish a Secure Session. +3. Execute L3 commands. +4. Abort the session and deinitialize. + +Pairing keys are central to the handshake: + +- Read: [Default Pairing Keys](../../reference/default_pairing_keys.md) + +Key points: + +- New chips come with a factory pairing public key in slot 0 and you use the corresponding private key to establish your *first* Secure Session. +- A common production pattern is: **use slot 0 to bootstrap**, then write your own pairing public key to another slot and **invalidate slot 0**. + - It is also highly recommended to ensure that your TROPIC01 is genuine by verifying whole certificate chain. + - We provide tutorials for certificate verification for Linux: [USB DevKit](../linux/usb_devkit/full_chain_verification.md), [SPI](../linux/spi/full_chain_verification.md). + +!!! danger "Irreversible Actions" + Some operations are one-way. Invalidating pairing slots, erasing certain chip configuration, and similar actions are **not reversible on a real chip**. + On the model, you can recover by restarting the model server (fresh state), but do not rely on that behavior for real hardware. + +If Secure Session establishment fails, the most common causes are wrong pairing keys or the chip being in a mode where L3 is unavailable (**Start-up Mode**): + +- Read: [FAQ](../../faq.md#i-cannot-establish-a-secure-session) + +--- + +## Debugging and Observability +When something doesn’t work, you typically want: (1) clear return codes, (2) logs, (3) a way to inspect the transport. + +### 1) Return Codes +Most API functions return a `lt_ret_t` error code. The FAQ explains common “surprising” root causes (wiring, maintenance mode, etc.): + +- Read: [FAQ](../../faq.md) + +To translate `lt_ret_t` error code to a string, use `lt_ret_verbose(ret)`. + +### 2) Logging +Libtropic logging is off by default (unless you build tests, which default to Info). Turn it on during evaluation: + +- [Logging guide](../../reference/logging.md) +- [Configuration](../../reference/integrating_libtropic/how_to_configure/index.md) (CMake options) + +Useful options: + +- [`LT_LOG_LVL`](../../reference/integrating_libtropic/how_to_configure/index.md#lt_log_lvl) to increase verbosity. +- [`LT_PRINT_SPI_DATA`](../../reference/integrating_libtropic/how_to_configure/index.md#lt_print_spi_data) if you need to see low-level traffic. + +### 3) Debuggers and Sanitizers +If you suspect memory issues or need to step through code: + +- [Debugging guide](../../reference/debugging.md) + +On Linux, tests against the model can be run with AddressSanitizer or Valgrind (and you can attach `gdb`). + +!!! tip "Model + gdb" + If you want to debug an example/your Libtropic binary against the model, run the **model server manually** (as in the first tutorial) and then run your binary under `gdb`. + +--- + +## TROPIC01 Firmware: Keep it up to date +On physical TROPIC01 chip, keeping TROPIC01 firmware current matters for reliability, security fixes, and compatibility with newer SDK features. + +What to remember: + +- Firmware runs on multiple execution engines (CPU FW + SPECT/ECC FW). Libtropic includes the low-level update commands and ships update files. +- A failed or interrupted update can leave the chip in a state where parts of the API are unavailable (often showing up as “Maintenance Mode” symptoms). +- Treat firmware update as a **sensitive operation**: avoid power loss/disconnects during update. + +Where to learn/do it: + +- Read: [TROPIC01 Firmware](../../reference/tropic01_fw.md) +- If Secure Session / commands start failing unexpectedly, also check: [FAQ](../../faq.md#lt_l3_invalid_cmd-or-lt_l2_unknown_req) +- Follow the firmware-update tutorials for your platform (for example on Linux USB devkit): [Tutorials](../../tutorials/index.md) + +--- + +## Safety: Operations that Can Change Chip State Permanently +TROPIC01 exposes powerful commands; some of them intentionally make **permanent** changes. + +Examples you will encounter in these tutorials: + +- Pairing key writes/invalidations (used in the hardware-wallet tutorial). +- I-config (I-memory) writes. +- Firmware update (interruption can brick the device; avoid power loss). + +!!! danger "When in doubt, use the model!" + If you are exploring commands you don’t fully understand yet, prefer using the **TROPIC01 Model** until you’re confident about the effects. + +--- + +## Where to Go Next +- Continue with [Hardware Wallet](hw_wallet.md) to see secure-session + configuration/pairing key management in practice. +- Keep [Libtropic Architecture](../../reference/libtropic_architecture.md) and [Debugging](../../reference/debugging.md) open while working through the rest of the tutorials on the TROPIC01 model. \ No newline at end of file diff --git a/examples/esp32/ESP32-C3-DevKit-RUST-1/fw_update/main/main.c b/examples/esp32/ESP32-C3-DevKit-RUST-1/fw_update/main/main.c index 6113e6df3..32f66ae1d 100644 --- a/examples/esp32/ESP32-C3-DevKit-RUST-1/fw_update/main/main.c +++ b/examples/esp32/ESP32-C3-DevKit-RUST-1/fw_update/main/main.c @@ -1,9 +1,10 @@ /** * @file main.c - * @brief Example showing how to perform an update of the TROPIC01 firmware using Libtropic and ESP32-C3-DevKit-RUST-1. + * @brief Example showing how to perform an update of the TROPIC01 firmware using Libtropic and + * ESP32-C3-DevKit-RUST-1. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -112,8 +113,9 @@ void app_main(void) } ESP_LOGI(TAG, "OK"); - // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** be in the Start-up - // Mode. If there are valid firmwares, TROPIC01 will begin to execute them automatically on boot. + // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** + // be in the Start-up Mode. If there are valid firmwares, TROPIC01 will begin to execute them + // automatically on boot. ESP_LOGI(TAG, "Rebooting TROPIC01..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { diff --git a/examples/esp32/ESP32-C3-DevKit-RUST-1/hello_world/main/main.c b/examples/esp32/ESP32-C3-DevKit-RUST-1/hello_world/main/main.c index 408cee172..bcc6b5ee8 100644 --- a/examples/esp32/ESP32-C3-DevKit-RUST-1/hello_world/main/main.c +++ b/examples/esp32/ESP32-C3-DevKit-RUST-1/hello_world/main/main.c @@ -3,7 +3,7 @@ * @brief Simple "Hello, World!" example of using Libtropic with the ESP32-C3-DevKit-RUST-1. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -99,8 +99,9 @@ void app_main(void) } ESP_LOGI(TAG, "OK"); - // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** be in the Start-up - // Mode. If there are valid firmwares, TROPIC01 will begin to execute them automatically on boot. + // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** + // be in the Start-up Mode. If there are valid firmwares, TROPIC01 will begin to execute them + // automatically on boot. ESP_LOGI(TAG, "Sending reboot request..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { @@ -115,10 +116,11 @@ void app_main(void) ret = lt_verify_chip_and_start_secure_session(<_handle, LT_EX_SH0_PRIV, LT_EX_SH0_PUB, TR01_PAIRING_KEY_SLOT_INDEX_0); if (LT_OK != ret) { - ESP_LOGE(TAG, "Failed to start Secure Session with key %d, ret=%s", (int)TR01_PAIRING_KEY_SLOT_INDEX_0, - lt_ret_verbose(ret)); + ESP_LOGE(TAG, "Failed to start Secure Session with key %d, ret=%s", + (int)TR01_PAIRING_KEY_SLOT_INDEX_0, lt_ret_verbose(ret)); ESP_LOGE(TAG, - "Check if you use correct SH0 keys! Hint: if you use an engineering sample chip, compile with " + "Check if you use correct SH0 keys! Hint: if you use an engineering sample chip, " + "compile with " "-DLT_SH0_KEYS=eng_sample"); lt_deinit(<_handle); mbedtls_psa_crypto_free(); diff --git a/examples/esp32/ESP32-C3-DevKit-RUST-1/identify_chip/main/main.c b/examples/esp32/ESP32-C3-DevKit-RUST-1/identify_chip/main/main.c index a5384ee80..ba599a026 100644 --- a/examples/esp32/ESP32-C3-DevKit-RUST-1/identify_chip/main/main.c +++ b/examples/esp32/ESP32-C3-DevKit-RUST-1/identify_chip/main/main.c @@ -4,7 +4,7 @@ * ESP32-C3-DevKit-RUST-1. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -103,8 +103,9 @@ void app_main(void) } ESP_LOGI(TAG, "OK"); - // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** be in the Start-up - // Mode. If there are valid firmwares, TROPIC01 will begin to execute them automatically on boot. + // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** + // be in the Start-up Mode. If there are valid firmwares, TROPIC01 will begin to execute them + // automatically on boot. ESP_LOGI(TAG, "Sending reboot request..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { @@ -125,8 +126,8 @@ void app_main(void) mbedtls_psa_crypto_free(); return; } - ESP_LOGI(TAG, " RISC-V FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")", fw_ver[3], fw_ver[2], - fw_ver[1], fw_ver[0]); + ESP_LOGI(TAG, " RISC-V FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")", fw_ver[3], + fw_ver[2], fw_ver[1], fw_ver[0]); ret = lt_get_info_spect_fw_ver(<_handle, fw_ver); if (ret != LT_OK) { @@ -135,10 +136,11 @@ void app_main(void) mbedtls_psa_crypto_free(); return; } - ESP_LOGI(TAG, " SPECT FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")", fw_ver[3], fw_ver[2], fw_ver[1], - fw_ver[0]); + ESP_LOGI(TAG, " SPECT FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")", fw_ver[3], + fw_ver[2], fw_ver[1], fw_ver[0]); - // We need to do the maintenance reboot to check bootloader version and FW bank headers in the Startup Mode. + // We need to do the maintenance reboot to check bootloader version and FW bank headers in the + // Startup Mode. ESP_LOGI(TAG, "Sending maintenance reboot request..."); ret = lt_reboot(<_handle, TR01_MAINTENANCE_REBOOT); if (ret != LT_OK) { @@ -151,7 +153,8 @@ void app_main(void) ESP_LOGI(TAG, "Reading data from chip..."); - // When TROPIC01 is in Start-up Mode, we can get RISC-V bootloader version the same way as we got RISC-V FW version. + // When TROPIC01 is in Start-up Mode, we can get RISC-V bootloader version the same way as we got + // RISC-V FW version. ret = lt_get_info_riscv_fw_ver(<_handle, fw_ver); if (ret != LT_OK) { ESP_LOGE(TAG, "Failed to get RISC-V bootloader version, ret=%s", lt_ret_verbose(ret)); diff --git a/examples/esp32/ESP32-DevKitC-V4/fw_update/main/main.c b/examples/esp32/ESP32-DevKitC-V4/fw_update/main/main.c index 333607278..fd718c1f0 100644 --- a/examples/esp32/ESP32-DevKitC-V4/fw_update/main/main.c +++ b/examples/esp32/ESP32-DevKitC-V4/fw_update/main/main.c @@ -1,9 +1,10 @@ /** * @file main.c - * @brief Example showing how to perform an update of the TROPIC01 firmware using Libtropic and ESP32-DevKitC-V4. + * @brief Example showing how to perform an update of the TROPIC01 firmware using Libtropic and + * ESP32-DevKitC-V4. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -112,8 +113,9 @@ void app_main(void) } ESP_LOGI(TAG, "OK"); - // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** be in the Start-up - // Mode. If there are valid firmwares, TROPIC01 will begin to execute them automatically on boot. + // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** + // be in the Start-up Mode. If there are valid firmwares, TROPIC01 will begin to execute them + // automatically on boot. ESP_LOGI(TAG, "Rebooting TROPIC01..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { diff --git a/examples/esp32/ESP32-DevKitC-V4/hello_world/main/main.c b/examples/esp32/ESP32-DevKitC-V4/hello_world/main/main.c index 7df4e6817..241b4b3c3 100644 --- a/examples/esp32/ESP32-DevKitC-V4/hello_world/main/main.c +++ b/examples/esp32/ESP32-DevKitC-V4/hello_world/main/main.c @@ -3,7 +3,7 @@ * @brief Simple "Hello, World!" example of using Libtropic with the ESP32-DevKitC-V4. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -99,8 +99,9 @@ void app_main(void) } ESP_LOGI(TAG, "OK"); - // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** be in the Start-up - // Mode. If there are valid firmwares, TROPIC01 will begin to execute them automatically on boot. + // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** + // be in the Start-up Mode. If there are valid firmwares, TROPIC01 will begin to execute them + // automatically on boot. ESP_LOGI(TAG, "Sending reboot request..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { @@ -115,10 +116,11 @@ void app_main(void) ret = lt_verify_chip_and_start_secure_session(<_handle, LT_EX_SH0_PRIV, LT_EX_SH0_PUB, TR01_PAIRING_KEY_SLOT_INDEX_0); if (LT_OK != ret) { - ESP_LOGE(TAG, "Failed to start Secure Session with key %d, ret=%s", (int)TR01_PAIRING_KEY_SLOT_INDEX_0, - lt_ret_verbose(ret)); + ESP_LOGE(TAG, "Failed to start Secure Session with key %d, ret=%s", + (int)TR01_PAIRING_KEY_SLOT_INDEX_0, lt_ret_verbose(ret)); ESP_LOGE(TAG, - "Check if you use correct SH0 keys! Hint: if you use an engineering sample chip, compile with " + "Check if you use correct SH0 keys! Hint: if you use an engineering sample chip, " + "compile with " "-DLT_SH0_KEYS=eng_sample"); lt_deinit(<_handle); mbedtls_psa_crypto_free(); diff --git a/examples/esp32/ESP32-DevKitC-V4/identify_chip/main/main.c b/examples/esp32/ESP32-DevKitC-V4/identify_chip/main/main.c index 4b83ec398..731aa230c 100644 --- a/examples/esp32/ESP32-DevKitC-V4/identify_chip/main/main.c +++ b/examples/esp32/ESP32-DevKitC-V4/identify_chip/main/main.c @@ -1,9 +1,10 @@ /** * @file main.c - * @brief Example of reading information about the TROPIC01 chip and its firmware using Libtropic and ESP32-DevKitC-V4. + * @brief Example of reading information about the TROPIC01 chip and its firmware using Libtropic and + * ESP32-DevKitC-V4. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -102,8 +103,9 @@ void app_main(void) } ESP_LOGI(TAG, "OK"); - // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** be in the Start-up - // Mode. If there are valid firmwares, TROPIC01 will begin to execute them automatically on boot. + // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** + // be in the Start-up Mode. If there are valid firmwares, TROPIC01 will begin to execute them + // automatically on boot. ESP_LOGI(TAG, "Sending reboot request..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { @@ -124,8 +126,8 @@ void app_main(void) mbedtls_psa_crypto_free(); return; } - ESP_LOGI(TAG, " RISC-V FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")", fw_ver[3], fw_ver[2], - fw_ver[1], fw_ver[0]); + ESP_LOGI(TAG, " RISC-V FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")", fw_ver[3], + fw_ver[2], fw_ver[1], fw_ver[0]); ret = lt_get_info_spect_fw_ver(<_handle, fw_ver); if (ret != LT_OK) { @@ -134,10 +136,11 @@ void app_main(void) mbedtls_psa_crypto_free(); return; } - ESP_LOGI(TAG, " SPECT FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")", fw_ver[3], fw_ver[2], fw_ver[1], - fw_ver[0]); + ESP_LOGI(TAG, " SPECT FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")", fw_ver[3], + fw_ver[2], fw_ver[1], fw_ver[0]); - // We need to do the maintenance reboot to check bootloader version and FW bank headers in the Startup Mode. + // We need to do the maintenance reboot to check bootloader version and FW bank headers in the + // Startup Mode. ESP_LOGI(TAG, "Sending maintenance reboot request..."); ret = lt_reboot(<_handle, TR01_MAINTENANCE_REBOOT); if (ret != LT_OK) { @@ -150,7 +153,8 @@ void app_main(void) ESP_LOGI(TAG, "Reading data from chip..."); - // When TROPIC01 is in Start-up Mode, we can get RISC-V bootloader version the same way as we got RISC-V FW version. + // When TROPIC01 is in Start-up Mode, we can get RISC-V bootloader version the same way as we got + // RISC-V FW version. ret = lt_get_info_riscv_fw_ver(<_handle, fw_ver); if (ret != LT_OK) { ESP_LOGE(TAG, "Failed to get RISC-V bootloader version, ret=%s", lt_ret_verbose(ret)); diff --git a/examples/esp32/ESP32-S3-DevKitC-1/fw_update/main/main.c b/examples/esp32/ESP32-S3-DevKitC-1/fw_update/main/main.c index 5fde4db88..62dcc26af 100644 --- a/examples/esp32/ESP32-S3-DevKitC-1/fw_update/main/main.c +++ b/examples/esp32/ESP32-S3-DevKitC-1/fw_update/main/main.c @@ -1,9 +1,10 @@ /** * @file main.c - * @brief Example showing how to perform an update of the TROPIC01 firmware using Libtropic and ESP32-S3-DevKitC-1. + * @brief Example showing how to perform an update of the TROPIC01 firmware using Libtropic and + * ESP32-S3-DevKitC-1. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -112,8 +113,9 @@ void app_main(void) } ESP_LOGI(TAG, "OK"); - // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** be in the Start-up - // Mode. If there are valid firmwares, TROPIC01 will begin to execute them automatically on boot. + // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** + // be in the Start-up Mode. If there are valid firmwares, TROPIC01 will begin to execute them + // automatically on boot. ESP_LOGI(TAG, "Rebooting TROPIC01..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { diff --git a/examples/esp32/ESP32-S3-DevKitC-1/hello_world/main/main.c b/examples/esp32/ESP32-S3-DevKitC-1/hello_world/main/main.c index abb0d40d1..ea92506ab 100644 --- a/examples/esp32/ESP32-S3-DevKitC-1/hello_world/main/main.c +++ b/examples/esp32/ESP32-S3-DevKitC-1/hello_world/main/main.c @@ -3,7 +3,7 @@ * @brief Simple "Hello, World!" example of using Libtropic with the ESP32-S3-DevKitC-1. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -99,8 +99,9 @@ void app_main(void) } ESP_LOGI(TAG, "OK"); - // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** be in the Start-up - // Mode. If there are valid firmwares, TROPIC01 will begin to execute them automatically on boot. + // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** + // be in the Start-up Mode. If there are valid firmwares, TROPIC01 will begin to execute them + // automatically on boot. ESP_LOGI(TAG, "Sending reboot request..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { @@ -115,10 +116,11 @@ void app_main(void) ret = lt_verify_chip_and_start_secure_session(<_handle, LT_EX_SH0_PRIV, LT_EX_SH0_PUB, TR01_PAIRING_KEY_SLOT_INDEX_0); if (LT_OK != ret) { - ESP_LOGE(TAG, "Failed to start Secure Session with key %d, ret=%s", (int)TR01_PAIRING_KEY_SLOT_INDEX_0, - lt_ret_verbose(ret)); + ESP_LOGE(TAG, "Failed to start Secure Session with key %d, ret=%s", + (int)TR01_PAIRING_KEY_SLOT_INDEX_0, lt_ret_verbose(ret)); ESP_LOGE(TAG, - "Check if you use correct SH0 keys! Hint: if you use an engineering sample chip, compile with " + "Check if you use correct SH0 keys! Hint: if you use an engineering sample chip, " + "compile with " "-DLT_SH0_KEYS=eng_sample"); lt_deinit(<_handle); mbedtls_psa_crypto_free(); diff --git a/examples/esp32/ESP32-S3-DevKitC-1/identify_chip/main/main.c b/examples/esp32/ESP32-S3-DevKitC-1/identify_chip/main/main.c index 3609e796a..8847bab92 100644 --- a/examples/esp32/ESP32-S3-DevKitC-1/identify_chip/main/main.c +++ b/examples/esp32/ESP32-S3-DevKitC-1/identify_chip/main/main.c @@ -4,7 +4,7 @@ * ESP32-S3-DevKitC-1. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -103,8 +103,9 @@ void app_main(void) } ESP_LOGI(TAG, "OK"); - // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** be in the Start-up - // Mode. If there are valid firmwares, TROPIC01 will begin to execute them automatically on boot. + // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** + // be in the Start-up Mode. If there are valid firmwares, TROPIC01 will begin to execute them + // automatically on boot. ESP_LOGI(TAG, "Sending reboot request..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { @@ -125,8 +126,8 @@ void app_main(void) mbedtls_psa_crypto_free(); return; } - ESP_LOGI(TAG, " RISC-V FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")", fw_ver[3], fw_ver[2], - fw_ver[1], fw_ver[0]); + ESP_LOGI(TAG, " RISC-V FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")", fw_ver[3], + fw_ver[2], fw_ver[1], fw_ver[0]); ret = lt_get_info_spect_fw_ver(<_handle, fw_ver); if (ret != LT_OK) { @@ -135,10 +136,11 @@ void app_main(void) mbedtls_psa_crypto_free(); return; } - ESP_LOGI(TAG, " SPECT FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")", fw_ver[3], fw_ver[2], fw_ver[1], - fw_ver[0]); + ESP_LOGI(TAG, " SPECT FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")", fw_ver[3], + fw_ver[2], fw_ver[1], fw_ver[0]); - // We need to do the maintenance reboot to check bootloader version and FW bank headers in the Startup Mode. + // We need to do the maintenance reboot to check bootloader version and FW bank headers in the + // Startup Mode. ESP_LOGI(TAG, "Sending maintenance reboot request..."); ret = lt_reboot(<_handle, TR01_MAINTENANCE_REBOOT); if (ret != LT_OK) { @@ -151,7 +153,8 @@ void app_main(void) ESP_LOGI(TAG, "Reading data from chip..."); - // When TROPIC01 is in Start-up Mode, we can get RISC-V bootloader version the same way as we got RISC-V FW version. + // When TROPIC01 is in Start-up Mode, we can get RISC-V bootloader version the same way as we got + // RISC-V FW version. ret = lt_get_info_riscv_fw_ver(<_handle, fw_ver); if (ret != LT_OK) { ESP_LOGE(TAG, "Failed to get RISC-V bootloader version, ret=%s", lt_ret_verbose(ret)); diff --git a/examples/linux/spi/full_chain_verification/CMakeLists.txt b/examples/linux/spi/full_chain_verification/CMakeLists.txt new file mode 100644 index 000000000..e8c904c04 --- /dev/null +++ b/examples/linux/spi/full_chain_verification/CMakeLists.txt @@ -0,0 +1,81 @@ +cmake_minimum_required(VERSION 3.21.0) +include (FetchContent) + +########################################################################### +# # +# Set up projects and paths # +# # +########################################################################### +project(libtropic_dump_certificates + DESCRIPTION "Libtropic utility to dump certificates from TROPIC01 on Linux using SPI driver." + LANGUAGES C) + +set(PATH_LIBTROPIC ../../../../) + +########################################################################### +# # +# Configuration # +# # +########################################################################### +if (NOT DEFINED LT_SPI_DEV_PATH) + set(LT_SPI_DEV_PATH "/dev/spidev0.0" CACHE STRING "Path to the SPI device where TROPIC01 is connected.") +endif() +message(STATUS "Using SPI device: ${LT_SPI_DEV_PATH}. You can change it by passing -DLT_SPI_DEV_PATH= to cmake.") + +if (NOT DEFINED LT_GPIO_DEV_PATH) + set(LT_GPIO_DEV_PATH "/dev/gpiochip0" CACHE STRING "Path to the GPIO device that provides the TROPIC01's interrupt (INT) and Chip Select (CS) line.") +endif() +message(STATUS "Using GPIO device: ${LT_GPIO_DEV_PATH}. You can change it by passing -DLT_GPIO_DEV_PATH= to cmake.") + +########################################################################### +# # +# Set up dependencies # +# # +########################################################################### + +# ------------------------------------------------------------------------ +# Libtropic +# ------------------------------------------------------------------------ +# Add path to Libtropic source +add_subdirectory(${PATH_LIBTROPIC} "libtropic") + +# ------------------------------------------------------------------------ +# External dependencies +# ------------------------------------------------------------------------ + +# MbedTLS v4.0.0 +set(ENABLE_TESTING OFF CACHE BOOL "Disable mbedtls_v4 test building.") +set(ENABLE_PROGRAMS OFF CACHE BOOL "Disable mbedtls_v4 examples building.") +FetchContent_Declare( + mbedtls_v4 + URL https://github.com/Mbed-TLS/mbedtls/releases/download/mbedtls-4.0.0/mbedtls-4.0.0.tar.bz2 + URL_HASH SHA256=2f3a47f7b3a541ddef450e4867eeecb7ce2ef7776093f3a11d6d43ead6bf2827 +) +FetchContent_MakeAvailable(mbedtls_v4) +target_link_libraries(tropic PUBLIC mbedtls) + +########################################################################### +# # +# Set up sources and compilation # +# # +########################################################################### +# Add MbedTLS v4 CAL +add_subdirectory("${PATH_LIBTROPIC}cal/mbedtls_v4" "mbedtls_v4_cal") +target_sources(tropic PRIVATE ${LT_CAL_SRCS}) +target_include_directories(tropic PUBLIC ${LT_CAL_INC_DIRS}) + +# Add SPI Linux HAL +add_subdirectory("${PATH_LIBTROPIC}hal/linux/spi" "linux_spi_hal") +target_sources(tropic PRIVATE ${LT_HAL_SRCS}) +target_include_directories(tropic PUBLIC ${LT_HAL_INC_DIRS}) + +# Add sources of this example +set(SOURCES + ${CMAKE_CURRENT_SOURCE_DIR}/main.c +) + +# Define executable, pass defines, and link dependencies. +add_executable(${CMAKE_PROJECT_NAME} ${SOURCES}) +target_compile_definitions(${CMAKE_PROJECT_NAME} PRIVATE LT_SPI_DEV_PATH=\"${LT_SPI_DEV_PATH}\") +target_compile_definitions(${CMAKE_PROJECT_NAME} PRIVATE LT_GPIO_DEV_PATH=\"${LT_GPIO_DEV_PATH}\") +target_link_libraries(${CMAKE_PROJECT_NAME} PRIVATE tropic) \ No newline at end of file diff --git a/examples/linux/spi/full_chain_verification/main.c b/examples/linux/spi/full_chain_verification/main.c new file mode 100644 index 000000000..9c4712bdc --- /dev/null +++ b/examples/linux/spi/full_chain_verification/main.c @@ -0,0 +1,170 @@ +/** + * @file main.c + * @brief Utility for dumping certificates from TROPIC01 using Linux SPI driver. Part of the Full chain + * verification example. + * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. + * + * @license For the license see LICENSE.md in the root directory of this source tree. + */ + +#include +#include +#include + +#include "libtropic.h" +#include "libtropic_common.h" +#include "libtropic_mbedtls_v4.h" +#include "libtropic_port_linux_spi.h" +#include "psa/crypto.h" + +lt_ret_t dump_cert_store(lt_handle_t *lt_handle) +{ + uint8_t cert1[TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE] = {0}, + cert2[TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE] = {0}, + cert3[TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE] = {0}, + cert4[TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE] = {0}; + + struct lt_cert_store_t store = { + .certs = {cert1, cert2, cert3, cert4}, + .buf_len = {TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, + TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE}}; + + // Reading X509 Certificate Store + printf("Reading certificates from TROPIC01...\n"); + lt_ret_t ret = lt_get_info_cert_store(lt_handle, &store); + if (ret != LT_OK) { + fprintf(stderr, "Failed to retrieve the certificates, ret=%s\n", lt_ret_verbose(ret)); + return LT_FAIL; + } + + // Dump the certificates to files + const char *names[LT_NUM_CERTIFICATES] = {"t01_ese_cert.der", "t01_xxxx_ca_cert.der", + "t01_ca_cert.der", "tropicsquare_root_ca_cert.der"}; + + printf("Writing certificates to files...\n"); + for (int i = 0; i < LT_NUM_CERTIFICATES; i++) { + if (store.cert_len[i] == 0) { + fprintf(stderr, "Error: Certificate %d is empty!\n", i); + return LT_FAIL; + } + FILE *f = fopen(names[i], "wb"); + if (!f) { + fprintf(stderr, "Error: Couldn't open file %s!\n", names[i]); + return LT_FAIL; + } + if (fwrite(store.certs[i], 1, store.cert_len[i], f) != store.cert_len[i]) { + fprintf(stderr, "Error: Failed to write certificate %d to file!\n", i); + fclose(f); + return LT_FAIL; + } + fclose(f); + } + + return LT_OK; +} + +int main(void) +{ + // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if + // you don't care about stdout/stderr output being shuffled or you use stdout only (or different + // output mechanism altogether). + setvbuf(stdout, NULL, _IONBF, 0); + setvbuf(stderr, NULL, _IONBF, 0); + + printf("====================================================\n"); + printf("==== TROPIC01 Certificate Chain Dumping Utility ====\n"); + printf("====================================================\n"); + + // Cryptographic function provider initialization. + // + // In production, this would typically be done only once, + // usually at the start of the application or before + // the first use of cryptographic functions but no later than + // the first occurrence of any Libtropic function + psa_status_t status = psa_crypto_init(); + if (status != PSA_SUCCESS) { + fprintf(stderr, "PSA Crypto initialization failed, status=%d (psa_status_t)\n", status); + return -1; + } + + // Libtropic handle. + // + // It is declared here (on stack) for + // simplicity. In production, you put it on heap if needed. + lt_handle_t lt_handle = {0}; + + // Device structure. + // + // Modify this according to your environment. Default values + // are compatible with RPi and our RPi shield. + lt_dev_linux_spi_t device = {0}; + + // LT_GPIO_DEV_PATH is defined in CMakeLists.txt. Pass + // -DLT_GPIO_DEV_PATH= to cmake if you want to change it. + int dev_path_len = snprintf(device.gpio_dev, sizeof(device.gpio_dev), "%s", LT_GPIO_DEV_PATH); + if (dev_path_len < 0 || (size_t)dev_path_len >= sizeof(device.gpio_dev)) { + fprintf( + stderr, + "Error: LT_GPIO_DEV_PATH is too long for device.gpio_dev buffer (limit is %zu bytes).\n", + sizeof(device.gpio_dev)); + mbedtls_psa_crypto_free(); + return -1; + } + + // LT_SPI_DEV_PATH is defined in CMakeLists.txt. Pass + // -DLT_SPI_DEV_PATH= to cmake if you want to change it. + dev_path_len = snprintf(device.spi_dev, sizeof(device.spi_dev), "%s", LT_SPI_DEV_PATH); + if (dev_path_len < 0 || (size_t)dev_path_len >= sizeof(device.spi_dev)) { + fprintf(stderr, + "Error: LT_SPI_DEV_PATH is too long for device.spi_dev buffer (limit is %zu bytes).\n", + sizeof(device.spi_dev)); + mbedtls_psa_crypto_free(); + return -1; + } + + device.spi_speed = 5000000; // 5 MHz (change if needed). + device.gpio_cs_num = 25; // GPIO 25 as on RPi shield. +#if LT_USE_INT_PIN + device.gpio_int_num = 5; // GPIO 5 as on RPi shield. +#endif + lt_handle.l2.device = &device; + + // Crypto abstraction layer (CAL) context. + lt_ctx_mbedtls_v4_t crypto_ctx; + lt_handle.l3.crypto_ctx = &crypto_ctx; + + printf("Initializing handle..."); + lt_ret_t ret = lt_init(<_handle); + if (LT_OK != ret) { + fprintf(stderr, "\nFailed to initialize handle, ret=%s\n", lt_ret_verbose(ret)); + mbedtls_psa_crypto_free(); + return -1; + } + printf("OK\n"); + + printf("Dumping certificates...\n"); + if (LT_OK != dump_cert_store(<_handle)) { + fprintf(stderr, "Error: Couldn't dump certificates!\n"); + lt_deinit(<_handle); + mbedtls_psa_crypto_free(); + return -1; + } + printf("Certificates dumped successfully!\n"); + + printf("Deinitializing handle..."); + ret = lt_deinit(<_handle); + if (LT_OK != ret) { + fprintf(stderr, "\nFailed to deinitialize handle, ret=%s\n", lt_ret_verbose(ret)); + mbedtls_psa_crypto_free(); + return -1; + } + printf("OK\n"); + + // Cryptographic function provider deinitialization. + // + // In production, this would be done only once, typically + // during termination of the application. + mbedtls_psa_crypto_free(); + + return 0; +} \ No newline at end of file diff --git a/examples/linux/spi/full_chain_verification/tropicsquare_root_ca_certificate_sn_301.pem b/examples/linux/spi/full_chain_verification/tropicsquare_root_ca_certificate_sn_301.pem new file mode 100644 index 000000000..37b81b00f --- /dev/null +++ b/examples/linux/spi/full_chain_verification/tropicsquare_root_ca_certificate_sn_301.pem @@ -0,0 +1,15 @@ +-----BEGIN CERTIFICATE----- +MIICWDCCAbugAwIBAgICAS0wCgYIKoZIzj0EAwQwTzELMAkGA1UEBhMCQ1oxHTAb +BgNVBAoMFFRyb3BpYyBTcXVhcmUgcy5yLm8uMSEwHwYDVQQDDBhUcm9waWMgU3F1 +YXJlIFJvb3QgQ0EgdjEwIBcNMjUwMzMxMTIwODI1WhgPMjA3NTAzMzExMjA4MjVa +ME8xCzAJBgNVBAYTAkNaMR0wGwYDVQQKDBRUcm9waWMgU3F1YXJlIHMuci5vLjEh +MB8GA1UEAwwYVHJvcGljIFNxdWFyZSBSb290IENBIHYxMIGbMBAGByqGSM49AgEG +BSuBBAAjA4GGAAQBh8zqYoN+IwktinE1eJ/Mb7w9NeefwB9PSY/FwsQJzncvkBNA +CQQD6LpNl+E/HnWUrG0vUf0iOfjUV3afN4RAoYAAcSvxakjqICWDe+/QUCpWL9k5 +QdUsxA7ZVTynmxRbpYXzJJK/15LrltlJ0xZ2zQmfGc6ISGl7jDQwrwFv7ZheHrSj +QjBAMB0GA1UdDgQWBBQ8GK9xGmaZs3kU42OWP+Jc8wSzvzAPBgNVHRMBAf8EBTAD +AQH/MA4GA1UdDwEB/wQEAwIBBjAKBggqhkjOPQQDBAOBigAwgYYCQWhBg3M5M3wY +Kk7olsv9XaWSXwAm56b6Pe5h9JpGtdmFaFjT2GUBvmSw8vM7BdhW3pb1e5R/Secg +6HUJCzDDN3kYAkEv3baNFmUQRR/kxi264MzZUtw04DrmYXgYzNDqKKnf8EWqE6JI +pfBmtRE5yb70cd0ATaxPeNtWz3s+jW+Ph9BI0g== +-----END CERTIFICATE----- diff --git a/examples/linux/spi/full_chain_verification/verify.sh b/examples/linux/spi/full_chain_verification/verify.sh new file mode 100755 index 000000000..6857caa93 --- /dev/null +++ b/examples/linux/spi/full_chain_verification/verify.sh @@ -0,0 +1,80 @@ +#!/usr/bin/env bash + +set -e + +if [[ $# -ne 1 ]]; then + echo "TROPIC01 full certificate chain verification example." + echo "This script verifies certificates downloaded from TROPIC01." + echo + echo "Usage:" + echo "$0 " + echo + echo "Hint: Use provided C application to download the certificates from TROPIC01 chip." + exit 1 +fi + +# Location of certs downloaded from TROPIC01. +T01_CERTS_DIR=${1%/} # Remove last trailing slash (if any present) + +# Check if files exist. +if ! { \ + ls "$T01_CERTS_DIR/t01_ese_cert.der" >/dev/null && \ + ls "$T01_CERTS_DIR/t01_xxxx_ca_cert.der" >/dev/null && \ + ls "$T01_CERTS_DIR/t01_ca_cert.der" >/dev/null; \ +}; then + echo "Missing required cert(s) in '$T01_CERTS_DIR'. Make sure to run the provided C application to download the certificates from the TROPIC01. Check the tutorials." + exit 1 +fi + +# Temp dir we will use for storing downloaded certs. +TMPDIR=$(mktemp -d) +trap 'rm -rf "$TMPDIR"' EXIT + +# Download certificate authorities from Tropic Square PKI web +curl --fail http://pki.tropicsquare.com/l0/tropic01_xxxx_ca_certificate_sn_30001.pem -o "$TMPDIR/tropic01_xxxx_ca_certificate_sn_30001.pem" +curl --fail http://pki.tropicsquare.com/l0/tropic01_ca_certificate_sn_3001.pem -o "$TMPDIR/tropic01_ca_certificate_sn_3001.pem" + +# Parse CRLs from certificates read from device in previous example +L3=$(openssl x509 -in "$T01_CERTS_DIR/t01_ese_cert.der" -inform DER -text | grep URI | cut -d ':' -f 2-) +L2=$(openssl x509 -in "$T01_CERTS_DIR/t01_xxxx_ca_cert.der" -inform DER -text | grep URI | cut -d ':' -f 2-) +L1=$(openssl x509 -in "$T01_CERTS_DIR/t01_ca_cert.der" -inform DER -text | grep URI | cut -d ':' -f 2-) + +# Download CRLs +curl --fail "$L3" -o "$TMPDIR/t01-Tv1.crl" # Downloads t01-Tv1.crl +curl --fail "$L2" -o "$TMPDIR/t01v1.crl" # Downloads t01v1.crl +curl --fail "$L1" -o "$TMPDIR/tsrv1.crl" # Downloads tsrv1.crl + +# Verify (chip) device certificate +echo "Verifying (chip) device certificate..." +cat "$TMPDIR/tropic01_xxxx_ca_certificate_sn_30001.pem" \ + "$TMPDIR/t01-Tv1.crl" \ + "$TMPDIR/tropic01_ca_certificate_sn_3001.pem" \ + "$TMPDIR/t01v1.crl" \ + "./tropicsquare_root_ca_certificate_sn_301.pem" \ + "$TMPDIR/tsrv1.crl" > "$TMPDIR/chain.pem" +openssl verify -verbose -crl_check -CAfile "$TMPDIR/chain.pem" "$T01_CERTS_DIR/t01_ese_cert.der" + +# Verify the "Part Number (group)" certificate +echo "Verifying 'Part Number (group)' certificate..." +cat "$TMPDIR/tropic01_ca_certificate_sn_3001.pem" \ + "$TMPDIR/t01v1.crl" \ + "./tropicsquare_root_ca_certificate_sn_301.pem" \ + "$TMPDIR/tsrv1.crl" > "$TMPDIR/chain.pem" +openssl verify -verbose -crl_check -CAfile "$TMPDIR/chain.pem" "$T01_CERTS_DIR/t01_xxxx_ca_cert.der" + +# Verify the "Product (Part Name)" certificate +echo "Verifying 'Product (Part Name)' certificate..." +cat "./tropicsquare_root_ca_certificate_sn_301.pem" "$TMPDIR/tsrv1.crl" > "$TMPDIR/chain.pem" +openssl verify -verbose -crl_check -CAfile "$TMPDIR/chain.pem" "$T01_CERTS_DIR/t01_ca_cert.der" + +# Verify Tropic Square Root Certificate +echo "Verifying Tropic Square Root certificate..." + +# We provide the root certificate here, in this repository, for convenience. +# HOWEVER. Do not blindly trust this certificate file from GitHub alone. +# To protect against repository compromise, you must verify the certificate +# fingerprint through an independent channel. Contact Tropic Square directly +# to obtain the verified fingerprint. +openssl verify -verbose -CAfile "./tropicsquare_root_ca_certificate_sn_301.pem" "./tropicsquare_root_ca_certificate_sn_301.pem" + +echo "All certificates verified successfully!" \ No newline at end of file diff --git a/examples/linux/spi/fw_update/main.c b/examples/linux/spi/fw_update/main.c index cc23d36d0..8a48cc647 100644 --- a/examples/linux/spi/fw_update/main.c +++ b/examples/linux/spi/fw_update/main.c @@ -1,9 +1,10 @@ /** * @file main.c - * @brief Example showing how to perform an update of the TROPIC01 firmware using Libtropic with Linux SPI. + * @brief Example showing how to perform an update of the TROPIC01 firmware using Libtropic with Linux + * SPI. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -45,8 +46,9 @@ lt_ret_t get_fw_versions(lt_handle_t *lt_handle) int main(void) { - // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if you don't care - // about stdout/stderr output being shuffled or you use stdout only (or different output mechanism altogether). + // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if + // you don't care about stdout/stderr output being shuffled or you use stdout only (or different + // output mechanism altogether). setvbuf(stdout, NULL, _IONBF, 0); setvbuf(stderr, NULL, _IONBF, 0); @@ -82,8 +84,10 @@ int main(void) // -DLT_GPIO_DEV_PATH= to cmake if you want to change it. int dev_path_len = snprintf(device.gpio_dev, sizeof(device.gpio_dev), "%s", LT_GPIO_DEV_PATH); if (dev_path_len < 0 || (size_t)dev_path_len >= sizeof(device.gpio_dev)) { - fprintf(stderr, "Error: LT_GPIO_DEV_PATH is too long for device.gpio_dev buffer (limit is %zu bytes).\n", - sizeof(device.gpio_dev)); + fprintf( + stderr, + "Error: LT_GPIO_DEV_PATH is too long for device.gpio_dev buffer (limit is %zu bytes).\n", + sizeof(device.gpio_dev)); mbedtls_psa_crypto_free(); return -1; } @@ -92,7 +96,8 @@ int main(void) // -DLT_SPI_DEV_PATH= to cmake if you want to change it. dev_path_len = snprintf(device.spi_dev, sizeof(device.spi_dev), "%s", LT_SPI_DEV_PATH); if (dev_path_len < 0 || (size_t)dev_path_len >= sizeof(device.spi_dev)) { - fprintf(stderr, "Error: LT_SPI_DEV_PATH is too long for device.spi_dev buffer (limit is %zu bytes).\n", + fprintf(stderr, + "Error: LT_SPI_DEV_PATH is too long for device.spi_dev buffer (limit is %zu bytes).\n", sizeof(device.spi_dev)); mbedtls_psa_crypto_free(); return -1; @@ -118,8 +123,9 @@ int main(void) } printf("OK\n"); - // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** be in the Start-up - // Mode. If there are valid firmwares, TROPIC01 will begin to execute them automatically on boot. + // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** + // be in the Start-up Mode. If there are valid firmwares, TROPIC01 will begin to execute them + // automatically on boot. printf("Rebooting TROPIC01..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { diff --git a/examples/linux/spi/hello_world/main.c b/examples/linux/spi/hello_world/main.c index 5a9fe7721..0e628c381 100644 --- a/examples/linux/spi/hello_world/main.c +++ b/examples/linux/spi/hello_world/main.c @@ -3,7 +3,7 @@ * @brief Simple "Hello, World!" example of using Libtropic with Linux SPI. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -32,8 +32,9 @@ int main(void) { - // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if you don't care - // about stdout/stderr output being shuffled or you use stdout only (or different output mechanism altogether). + // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if + // you don't care about stdout/stderr output being shuffled or you use stdout only (or different + // output mechanism altogether). setvbuf(stdout, NULL, _IONBF, 0); setvbuf(stderr, NULL, _IONBF, 0); @@ -69,8 +70,10 @@ int main(void) // -DLT_GPIO_DEV_PATH= to cmake if you want to change it. int dev_path_len = snprintf(device.gpio_dev, sizeof(device.gpio_dev), "%s", LT_GPIO_DEV_PATH); if (dev_path_len < 0 || (size_t)dev_path_len >= sizeof(device.gpio_dev)) { - fprintf(stderr, "Error: LT_GPIO_DEV_PATH is too long for device.gpio_dev buffer (limit is %zu bytes).\n", - sizeof(device.gpio_dev)); + fprintf( + stderr, + "Error: LT_GPIO_DEV_PATH is too long for device.gpio_dev buffer (limit is %zu bytes).\n", + sizeof(device.gpio_dev)); mbedtls_psa_crypto_free(); return -1; } @@ -79,7 +82,8 @@ int main(void) // -DLT_SPI_DEV_PATH= to cmake if you want to change it. dev_path_len = snprintf(device.spi_dev, sizeof(device.spi_dev), "%s", LT_SPI_DEV_PATH); if (dev_path_len < 0 || (size_t)dev_path_len >= sizeof(device.spi_dev)) { - fprintf(stderr, "Error: LT_SPI_DEV_PATH is too long for device.spi_dev buffer (limit is %zu bytes).\n", + fprintf(stderr, + "Error: LT_SPI_DEV_PATH is too long for device.spi_dev buffer (limit is %zu bytes).\n", sizeof(device.spi_dev)); mbedtls_psa_crypto_free(); return -1; @@ -105,7 +109,8 @@ int main(void) } printf("OK\n"); - // We need to ensure we are not in the Startup Mode, as L3 commands are available only in the Application Firmware. + // We need to ensure we are not in the Startup Mode, as L3 commands are available only in the + // Application Firmware. printf("Sending reboot request..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { @@ -121,10 +126,11 @@ int main(void) ret = lt_verify_chip_and_start_secure_session(<_handle, LT_EX_SH0_PRIV, LT_EX_SH0_PUB, TR01_PAIRING_KEY_SLOT_INDEX_0); if (LT_OK != ret) { - fprintf(stderr, "\nFailed to start Secure Session with key %d, ret=%s\n", (int)TR01_PAIRING_KEY_SLOT_INDEX_0, - lt_ret_verbose(ret)); + fprintf(stderr, "\nFailed to start Secure Session with key %d, ret=%s\n", + (int)TR01_PAIRING_KEY_SLOT_INDEX_0, lt_ret_verbose(ret)); fprintf(stderr, - "Check if you use correct SH0 keys! Hint: if you use an engineering sample chip, compile with " + "Check if you use correct SH0 keys! Hint: if you use an engineering sample chip, " + "compile with " "-DLT_SH0_KEYS=eng_sample\n"); lt_deinit(<_handle); mbedtls_psa_crypto_free(); diff --git a/examples/linux/spi/identify_chip/main.c b/examples/linux/spi/identify_chip/main.c index e7050781e..b9b8eafda 100644 --- a/examples/linux/spi/identify_chip/main.c +++ b/examples/linux/spi/identify_chip/main.c @@ -1,9 +1,10 @@ /** * @file main.c - * @brief Example of reading information about the TROPIC01 chip and its firmware using Libtropic with Linux SPI. + * @brief Example of reading information about the TROPIC01 chip and its firmware using Libtropic with + * Linux SPI. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -18,8 +19,9 @@ int main(void) { - // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if you don't care - // about stdout/stderr output being shuffled or you use stdout only (or different output mechanism altogether). + // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if + // you don't care about stdout/stderr output being shuffled or you use stdout only (or different + // output mechanism altogether). setvbuf(stdout, NULL, _IONBF, 0); setvbuf(stderr, NULL, _IONBF, 0); @@ -55,8 +57,10 @@ int main(void) // -DLT_GPIO_DEV_PATH= to cmake if you want to change it. int dev_path_len = snprintf(device.gpio_dev, sizeof(device.gpio_dev), "%s", LT_GPIO_DEV_PATH); if (dev_path_len < 0 || (size_t)dev_path_len >= sizeof(device.gpio_dev)) { - fprintf(stderr, "Error: LT_GPIO_DEV_PATH is too long for device.gpio_dev buffer (limit is %zu bytes).\n", - sizeof(device.gpio_dev)); + fprintf( + stderr, + "Error: LT_GPIO_DEV_PATH is too long for device.gpio_dev buffer (limit is %zu bytes).\n", + sizeof(device.gpio_dev)); mbedtls_psa_crypto_free(); return -1; } @@ -65,7 +69,8 @@ int main(void) // -DLT_SPI_DEV_PATH= to cmake if you want to change it. dev_path_len = snprintf(device.spi_dev, sizeof(device.spi_dev), "%s", LT_SPI_DEV_PATH); if (dev_path_len < 0 || (size_t)dev_path_len >= sizeof(device.spi_dev)) { - fprintf(stderr, "Error: LT_SPI_DEV_PATH is too long for device.spi_dev buffer (limit is %zu bytes).\n", + fprintf(stderr, + "Error: LT_SPI_DEV_PATH is too long for device.spi_dev buffer (limit is %zu bytes).\n", sizeof(device.spi_dev)); mbedtls_psa_crypto_free(); return -1; @@ -91,8 +96,9 @@ int main(void) } printf("OK\n"); - // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** be in the Start-up - // Mode. If there are valid firmwares, TROPIC01 will begin to execute them automatically on boot. + // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** + // be in the Start-up Mode. If there are valid firmwares, TROPIC01 will begin to execute them + // automatically on boot. printf("Sending reboot request..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { @@ -113,8 +119,8 @@ int main(void) mbedtls_psa_crypto_free(); return -1; } - printf(" RISC-V FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", fw_ver[3], fw_ver[2], fw_ver[1], - fw_ver[0]); + printf(" RISC-V FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", fw_ver[3], + fw_ver[2], fw_ver[1], fw_ver[0]); ret = lt_get_info_spect_fw_ver(<_handle, fw_ver); if (ret != LT_OK) { @@ -123,10 +129,11 @@ int main(void) mbedtls_psa_crypto_free(); return -1; } - printf(" SPECT FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", fw_ver[3], fw_ver[2], fw_ver[1], - fw_ver[0]); + printf(" SPECT FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", fw_ver[3], + fw_ver[2], fw_ver[1], fw_ver[0]); - // We need to do the maintenance reboot to check bootloader version and FW bank headers in the Startup Mode. + // We need to do the maintenance reboot to check bootloader version and FW bank headers in the + // Startup Mode. printf("Sending maintenance reboot request..."); ret = lt_reboot(<_handle, TR01_MAINTENANCE_REBOOT); if (ret != LT_OK) { @@ -139,7 +146,8 @@ int main(void) printf("Reading data from chip...\n"); - // When TROPIC01 is in Start-up Mode, we can get RISC-V bootloader version the same way as we got RISC-V FW version. + // When TROPIC01 is in Start-up Mode, we can get RISC-V bootloader version the same way as we got + // RISC-V FW version. ret = lt_get_info_riscv_fw_ver(<_handle, fw_ver); if (ret != LT_OK) { fprintf(stderr, "Failed to get RISC-V bootloader version, ret=%s\n", lt_ret_verbose(ret)); @@ -147,8 +155,8 @@ int main(void) mbedtls_psa_crypto_free(); return -1; } - printf(" RISC-V bootloader version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", fw_ver[3] & 0x7f, fw_ver[2], - fw_ver[1], fw_ver[0]); + printf(" RISC-V bootloader version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", + fw_ver[3] & 0x7f, fw_ver[2], fw_ver[1], fw_ver[0]); printf("Firmware bank headers:\n"); ret = lt_print_fw_header(<_handle, TR01_FW_BANK_FW1, printf); diff --git a/examples/linux/usb_devkit/full_chain_verification/CMakeLists.txt b/examples/linux/usb_devkit/full_chain_verification/CMakeLists.txt index 85a9b087f..d00e7abf4 100644 --- a/examples/linux/usb_devkit/full_chain_verification/CMakeLists.txt +++ b/examples/linux/usb_devkit/full_chain_verification/CMakeLists.txt @@ -58,7 +58,7 @@ add_subdirectory("${PATH_LIBTROPIC}cal/mbedtls_v4" "mbedtls_v4_cal") target_sources(tropic PRIVATE ${LT_CAL_SRCS}) target_include_directories(tropic PUBLIC ${LT_CAL_INC_DIRS}) -# Add SPI Linux HAL +# Add USB DevKit POSIX HAL add_subdirectory("${PATH_LIBTROPIC}hal/posix/usb_dongle" "posix_usb_dongle") target_sources(tropic PRIVATE ${LT_HAL_SRCS}) target_include_directories(tropic PUBLIC ${LT_HAL_INC_DIRS}) diff --git a/examples/linux/usb_devkit/full_chain_verification/main.c b/examples/linux/usb_devkit/full_chain_verification/main.c index 70479406c..ff13236cb 100644 --- a/examples/linux/usb_devkit/full_chain_verification/main.c +++ b/examples/linux/usb_devkit/full_chain_verification/main.c @@ -1,10 +1,10 @@ /** * @file main.c - * @brief Utility for dumping certificates from TROPIC01 USB Devkit for Linux. Part of the Full chain verification - * example. + * @brief Utility for dumping certificates from TROPIC01 USB Devkit for Linux. Part of the Full chain + * verification example. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -19,13 +19,15 @@ lt_ret_t dump_cert_store(lt_handle_t *lt_handle) { - uint8_t cert1[TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE] = {0}, cert2[TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE] = {0}, - cert3[TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE] = {0}, cert4[TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE] = {0}; + uint8_t cert1[TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE] = {0}, + cert2[TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE] = {0}, + cert3[TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE] = {0}, + cert4[TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE] = {0}; - struct lt_cert_store_t store - = {.certs = {cert1, cert2, cert3, cert4}, - .buf_len = {TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, - TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE}}; + struct lt_cert_store_t store = { + .certs = {cert1, cert2, cert3, cert4}, + .buf_len = {TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, + TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE}}; // Reading X509 Certificate Store printf("Reading certificates from TROPIC01...\n"); @@ -36,8 +38,8 @@ lt_ret_t dump_cert_store(lt_handle_t *lt_handle) } // Dump the certificates to files - const char *names[LT_NUM_CERTIFICATES] - = {"t01_ese_cert.der", "t01_xxxx_ca_cert.der", "t01_ca_cert.der", "tropicsquare_root_ca_cert.der"}; + const char *names[LT_NUM_CERTIFICATES] = {"t01_ese_cert.der", "t01_xxxx_ca_cert.der", + "t01_ca_cert.der", "tropicsquare_root_ca_cert.der"}; printf("Writing certificates to files...\n"); for (int i = 0; i < LT_NUM_CERTIFICATES; i++) { @@ -63,8 +65,9 @@ lt_ret_t dump_cert_store(lt_handle_t *lt_handle) int main(void) { - // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if you don't care - // about stdout/stderr output being shuffled or you use stdout only (or different output mechanism altogether). + // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if + // you don't care about stdout/stderr output being shuffled or you use stdout only (or different + // output mechanism altogether). setvbuf(stdout, NULL, _IONBF, 0); setvbuf(stderr, NULL, _IONBF, 0); @@ -100,8 +103,10 @@ int main(void) // to cmake if you want to change it. int dev_path_len = snprintf(device.dev_path, sizeof(device.dev_path), "%s", LT_USB_DEVKIT_PATH); if (dev_path_len < 0 || (size_t)dev_path_len >= sizeof(device.dev_path)) { - fprintf(stderr, "Error: LT_USB_DEVKIT_PATH is too long for device.dev_path buffer (limit is %zu bytes).\n", - sizeof(device.dev_path)); + fprintf( + stderr, + "Error: LT_USB_DEVKIT_PATH is too long for device.dev_path buffer (limit is %zu bytes).\n", + sizeof(device.dev_path)); mbedtls_psa_crypto_free(); return -1; } diff --git a/examples/linux/usb_devkit/fw_update/CMakeLists.txt b/examples/linux/usb_devkit/fw_update/CMakeLists.txt index 4e069b1b1..0e1d57041 100644 --- a/examples/linux/usb_devkit/fw_update/CMakeLists.txt +++ b/examples/linux/usb_devkit/fw_update/CMakeLists.txt @@ -62,7 +62,7 @@ add_subdirectory("${PATH_LIBTROPIC}cal/mbedtls_v4" "mbedtls_v4_cal") target_sources(tropic PRIVATE ${LT_CAL_SRCS}) target_include_directories(tropic PUBLIC ${LT_CAL_INC_DIRS}) -# Add SPI Linux HAL +# Add USB DevKit POSIX HAL add_subdirectory("${PATH_LIBTROPIC}hal/posix/usb_dongle" "posix_usb_dongle") target_sources(tropic PRIVATE ${LT_HAL_SRCS}) target_include_directories(tropic PUBLIC ${LT_HAL_INC_DIRS}) diff --git a/examples/linux/usb_devkit/fw_update/main.c b/examples/linux/usb_devkit/fw_update/main.c index c100ba22e..d1066d0d0 100644 --- a/examples/linux/usb_devkit/fw_update/main.c +++ b/examples/linux/usb_devkit/fw_update/main.c @@ -1,9 +1,10 @@ /** * @file main.c - * @brief Example showing how to perform an update of the TROPIC01 firmware using Libtropic with the USB devkit. + * @brief Example showing how to perform an update of the TROPIC01 firmware using Libtropic with the + * USB devkit. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -45,8 +46,9 @@ lt_ret_t get_fw_versions(lt_handle_t *lt_handle) int main(void) { - // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if you don't care - // about stdout/stderr output being shuffled or you use stdout only (or different output mechanism altogether). + // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if + // you don't care about stdout/stderr output being shuffled or you use stdout only (or different + // output mechanism altogether). setvbuf(stdout, NULL, _IONBF, 0); setvbuf(stderr, NULL, _IONBF, 0); @@ -82,8 +84,10 @@ int main(void) // to cmake if you want to change it. int dev_path_len = snprintf(device.dev_path, sizeof(device.dev_path), "%s", LT_USB_DEVKIT_PATH); if (dev_path_len < 0 || (size_t)dev_path_len >= sizeof(device.dev_path)) { - fprintf(stderr, "Error: LT_USB_DEVKIT_PATH is too long for device.dev_path buffer (limit is %zu bytes).\n", - sizeof(device.dev_path)); + fprintf( + stderr, + "Error: LT_USB_DEVKIT_PATH is too long for device.dev_path buffer (limit is %zu bytes).\n", + sizeof(device.dev_path)); mbedtls_psa_crypto_free(); return -1; } @@ -104,8 +108,9 @@ int main(void) } printf("OK\n"); - // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** be in the Start-up - // Mode. If there are valid firmwares, TROPIC01 will begin to execute them automatically on boot. + // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** + // be in the Start-up Mode. If there are valid firmwares, TROPIC01 will begin to execute them + // automatically on boot. printf("Rebooting TROPIC01..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { diff --git a/examples/linux/usb_devkit/hello_world/CMakeLists.txt b/examples/linux/usb_devkit/hello_world/CMakeLists.txt index 454f5e59e..3ab4f2043 100644 --- a/examples/linux/usb_devkit/hello_world/CMakeLists.txt +++ b/examples/linux/usb_devkit/hello_world/CMakeLists.txt @@ -83,7 +83,7 @@ add_subdirectory("${PATH_LIBTROPIC}cal/mbedtls_v4" "mbedtls_v4_cal") target_sources(tropic PRIVATE ${LT_CAL_SRCS}) target_include_directories(tropic PUBLIC ${LT_CAL_INC_DIRS}) -# Add SPI Linux HAL +# Add USB DevKit POSIX HAL add_subdirectory("${PATH_LIBTROPIC}hal/posix/usb_dongle" "posix_usb_dongle") target_sources(tropic PRIVATE ${LT_HAL_SRCS}) target_include_directories(tropic PUBLIC ${LT_HAL_INC_DIRS}) diff --git a/examples/linux/usb_devkit/hello_world/main.c b/examples/linux/usb_devkit/hello_world/main.c index 4a6a05048..02af678b7 100644 --- a/examples/linux/usb_devkit/hello_world/main.c +++ b/examples/linux/usb_devkit/hello_world/main.c @@ -3,7 +3,7 @@ * @brief Simple "Hello, World!" example of using Libtropic with the USB devkit. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -32,8 +32,9 @@ int main(void) { - // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if you don't care - // about stdout/stderr output being shuffled or you use stdout only (or different output mechanism altogether). + // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if + // you don't care about stdout/stderr output being shuffled or you use stdout only (or different + // output mechanism altogether). setvbuf(stdout, NULL, _IONBF, 0); setvbuf(stderr, NULL, _IONBF, 0); @@ -69,8 +70,10 @@ int main(void) // to cmake if you want to change it. int dev_path_len = snprintf(device.dev_path, sizeof(device.dev_path), "%s", LT_USB_DEVKIT_PATH); if (dev_path_len < 0 || (size_t)dev_path_len >= sizeof(device.dev_path)) { - fprintf(stderr, "Error: LT_USB_DEVKIT_PATH is too long for device.dev_path buffer (limit is %zu bytes).\n", - sizeof(device.dev_path)); + fprintf( + stderr, + "Error: LT_USB_DEVKIT_PATH is too long for device.dev_path buffer (limit is %zu bytes).\n", + sizeof(device.dev_path)); mbedtls_psa_crypto_free(); return -1; } @@ -91,7 +94,8 @@ int main(void) } printf("OK\n"); - // We need to ensure we are not in the Startup Mode, as L3 commands are available only in the Application Firmware. + // We need to ensure we are not in the Startup Mode, as L3 commands are available only in the + // Application Firmware. printf("Sending reboot request..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { @@ -107,10 +111,11 @@ int main(void) ret = lt_verify_chip_and_start_secure_session(<_handle, LT_EX_SH0_PRIV, LT_EX_SH0_PUB, TR01_PAIRING_KEY_SLOT_INDEX_0); if (LT_OK != ret) { - fprintf(stderr, "\nFailed to start Secure Session with key %d, ret=%s\n", (int)TR01_PAIRING_KEY_SLOT_INDEX_0, - lt_ret_verbose(ret)); + fprintf(stderr, "\nFailed to start Secure Session with key %d, ret=%s\n", + (int)TR01_PAIRING_KEY_SLOT_INDEX_0, lt_ret_verbose(ret)); fprintf(stderr, - "Check if you use correct SH0 keys! Hint: if you use an engineering sample chip, compile with " + "Check if you use correct SH0 keys! Hint: if you use an engineering sample chip, " + "compile with " "-DLT_SH0_KEYS=eng_sample\n"); lt_deinit(<_handle); mbedtls_psa_crypto_free(); diff --git a/examples/linux/usb_devkit/identify_chip/CMakeLists.txt b/examples/linux/usb_devkit/identify_chip/CMakeLists.txt index 00a88a35a..110daf669 100644 --- a/examples/linux/usb_devkit/identify_chip/CMakeLists.txt +++ b/examples/linux/usb_devkit/identify_chip/CMakeLists.txt @@ -62,7 +62,7 @@ add_subdirectory("${PATH_LIBTROPIC}cal/mbedtls_v4" "mbedtls_v4_cal") target_sources(tropic PRIVATE ${LT_CAL_SRCS}) target_include_directories(tropic PUBLIC ${LT_CAL_INC_DIRS}) -# Add SPI Linux HAL +# Add USB DevKit POSIX HAL add_subdirectory("${PATH_LIBTROPIC}hal/posix/usb_dongle" "posix_usb_dongle") target_sources(tropic PRIVATE ${LT_HAL_SRCS}) target_include_directories(tropic PUBLIC ${LT_HAL_INC_DIRS}) diff --git a/examples/linux/usb_devkit/identify_chip/main.c b/examples/linux/usb_devkit/identify_chip/main.c index 0747f2b78..37de140c6 100644 --- a/examples/linux/usb_devkit/identify_chip/main.c +++ b/examples/linux/usb_devkit/identify_chip/main.c @@ -1,9 +1,10 @@ /** * @file main.c - * @brief Example of reading information about the TROPIC01 chip and its firmware using Libtropic and USB devkit. + * @brief Example of reading information about the TROPIC01 chip and its firmware using Libtropic and + * USB devkit. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -18,8 +19,9 @@ int main(void) { - // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if you don't care - // about stdout/stderr output being shuffled or you use stdout only (or different output mechanism altogether). + // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if + // you don't care about stdout/stderr output being shuffled or you use stdout only (or different + // output mechanism altogether). setvbuf(stdout, NULL, _IONBF, 0); setvbuf(stderr, NULL, _IONBF, 0); @@ -55,8 +57,10 @@ int main(void) // to cmake if you want to change it. int dev_path_len = snprintf(device.dev_path, sizeof(device.dev_path), "%s", LT_USB_DEVKIT_PATH); if (dev_path_len < 0 || (size_t)dev_path_len >= sizeof(device.dev_path)) { - fprintf(stderr, "Error: LT_USB_DEVKIT_PATH is too long for device.dev_path buffer (limit is %zu bytes).\n", - sizeof(device.dev_path)); + fprintf( + stderr, + "Error: LT_USB_DEVKIT_PATH is too long for device.dev_path buffer (limit is %zu bytes).\n", + sizeof(device.dev_path)); mbedtls_psa_crypto_free(); return -1; } @@ -77,8 +81,9 @@ int main(void) } printf("OK\n"); - // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** be in the Start-up - // Mode. If there are valid firmwares, TROPIC01 will begin to execute them automatically on boot. + // First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** + // be in the Start-up Mode. If there are valid firmwares, TROPIC01 will begin to execute them + // automatically on boot. printf("Sending reboot request..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { @@ -99,8 +104,8 @@ int main(void) mbedtls_psa_crypto_free(); return -1; } - printf(" RISC-V FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", fw_ver[3], fw_ver[2], fw_ver[1], - fw_ver[0]); + printf(" RISC-V FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", fw_ver[3], + fw_ver[2], fw_ver[1], fw_ver[0]); ret = lt_get_info_spect_fw_ver(<_handle, fw_ver); if (ret != LT_OK) { @@ -109,10 +114,11 @@ int main(void) mbedtls_psa_crypto_free(); return -1; } - printf(" SPECT FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", fw_ver[3], fw_ver[2], fw_ver[1], - fw_ver[0]); + printf(" SPECT FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", fw_ver[3], + fw_ver[2], fw_ver[1], fw_ver[0]); - // We need to do the maintenance reboot to check bootloader version and FW bank headers in the Startup Mode. + // We need to do the maintenance reboot to check bootloader version and FW bank headers in the + // Startup Mode. printf("Sending maintenance reboot request..."); ret = lt_reboot(<_handle, TR01_MAINTENANCE_REBOOT); if (ret != LT_OK) { @@ -125,7 +131,8 @@ int main(void) printf("Reading data from chip...\n"); - // When TROPIC01 is in Start-up Mode, we can get RISC-V bootloader version the same way as we got RISC-V FW version. + // When TROPIC01 is in Start-up Mode, we can get RISC-V bootloader version the same way as we got + // RISC-V FW version. ret = lt_get_info_riscv_fw_ver(<_handle, fw_ver); if (ret != LT_OK) { fprintf(stderr, "Failed to get RISC-V bootloader version, ret=%s\n", lt_ret_verbose(ret)); @@ -133,8 +140,8 @@ int main(void) mbedtls_psa_crypto_free(); return -1; } - printf(" RISC-V bootloader version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", fw_ver[3] & 0x7f, fw_ver[2], - fw_ver[1], fw_ver[0]); + printf(" RISC-V bootloader version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", + fw_ver[3] & 0x7f, fw_ver[2], fw_ver[1], fw_ver[0]); printf("Firmware bank headers:\n"); ret = lt_print_fw_header(<_handle, TR01_FW_BANK_FW1, printf); diff --git a/examples/model/hello_world/main.c b/examples/model/hello_world/main.c index 1d9cb41bf..d664c9fc9 100644 --- a/examples/model/hello_world/main.c +++ b/examples/model/hello_world/main.c @@ -3,7 +3,7 @@ * @brief Simple "Hello, World!" example of using Libtropic with the model. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -31,8 +31,9 @@ int main(void) { - // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if you don't care - // about stdout/stderr output being shuffled or you use stdout only (or different output mechanism altogether). + // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if + // you don't care about stdout/stderr output being shuffled or you use stdout only (or different + // output mechanism altogether). setvbuf(stdout, NULL, _IONBF, 0); setvbuf(stderr, NULL, _IONBF, 0); @@ -65,7 +66,8 @@ int main(void) lt_handle.l2.device = &device; // Generate seed for the PRNG and seed it. - // Note: model uses rand(), which is not cryptographically secure. Better alternative should be used in production. + // Note: model uses rand(), which is not cryptographically secure. Better alternative should be + // used in production. unsigned int prng_seed; if (0 != getentropy(&prng_seed, sizeof(prng_seed))) { fprintf(stderr, "main: getentropy() failed (%s)!\n", strerror(errno)); @@ -88,7 +90,8 @@ int main(void) } printf("OK\n"); - // We need to ensure we are not in the Startup Mode, as L3 commands are available only in the Application Firmware. + // We need to ensure we are not in the Startup Mode, as L3 commands are available only in the + // Application Firmware. printf("Sending reboot request..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { @@ -103,10 +106,11 @@ int main(void) ret = lt_verify_chip_and_start_secure_session(<_handle, LT_EX_SH0_PRIV, LT_EX_SH0_PUB, TR01_PAIRING_KEY_SLOT_INDEX_0); if (LT_OK != ret) { - fprintf(stderr, "\nFailed to start Secure Session with key %d, ret=%s\n", (int)TR01_PAIRING_KEY_SLOT_INDEX_0, - lt_ret_verbose(ret)); + fprintf(stderr, "\nFailed to start Secure Session with key %d, ret=%s\n", + (int)TR01_PAIRING_KEY_SLOT_INDEX_0, lt_ret_verbose(ret)); fprintf(stderr, - "Check if you use correct SH0 keys! Hint: if you use an engineering sample chip, compile with " + "Check if you use correct SH0 keys! Hint: if you use an engineering sample chip, " + "compile with " "-DLT_SH0_KEYS=eng_sample\n"); lt_deinit(<_handle); mbedtls_psa_crypto_free(); diff --git a/examples/model/hw_wallet/main.c b/examples/model/hw_wallet/main.c index ce8fdbdca..fa1226984 100644 --- a/examples/model/hw_wallet/main.c +++ b/examples/model/hw_wallet/main.c @@ -32,39 +32,39 @@ #define DEFAULT_SH0_PUB sh0pub_prod0 /** @brief Attestation key for ECC slot 0. */ -uint8_t attestation_key[TR01_CURVE_PRIVKEY_LEN] - = {0x22, 0x57, 0xa8, 0x2f, 0x85, 0x8f, 0x13, 0x32, 0xfa, 0x0f, 0xf6, 0x0c, 0x76, 0x29, 0x42, 0x70, - 0xa9, 0x58, 0x9d, 0xfd, 0x47, 0xa5, 0x23, 0x78, 0x18, 0x4d, 0x2d, 0x38, 0xf0, 0xa7, 0xc4, 0x01}; +uint8_t attestation_key[TR01_CURVE_PRIVKEY_LEN] = { + 0x22, 0x57, 0xa8, 0x2f, 0x85, 0x8f, 0x13, 0x32, 0xfa, 0x0f, 0xf6, 0x0c, 0x76, 0x29, 0x42, 0x70, + 0xa9, 0x58, 0x9d, 0xfd, 0x47, 0xa5, 0x23, 0x78, 0x18, 0x4d, 0x2d, 0x38, 0xf0, 0xa7, 0xc4, 0x01}; /** @brief X25519 private key to execute a Secure Channel Handshake on Pairing Key slot 1. */ -const uint8_t sh1priv[] - = {0x58, 0xc4, 0x81, 0x88, 0xf8, 0xb1, 0xcb, 0xd4, 0x19, 0x00, 0x2e, 0x9c, 0x8d, 0xf8, 0xce, 0xea, - 0xf3, 0xa9, 0x11, 0xde, 0xb6, 0x6b, 0xc8, 0x87, 0xae, 0xe7, 0x88, 0x10, 0xfb, 0x48, 0xb6, 0x74}; +const uint8_t sh1priv[] = {0x58, 0xc4, 0x81, 0x88, 0xf8, 0xb1, 0xcb, 0xd4, 0x19, 0x00, 0x2e, + 0x9c, 0x8d, 0xf8, 0xce, 0xea, 0xf3, 0xa9, 0x11, 0xde, 0xb6, 0x6b, + 0xc8, 0x87, 0xae, 0xe7, 0x88, 0x10, 0xfb, 0x48, 0xb6, 0x74}; /** @brief X25519 public key to execute a Secure Channel Handshake on Pairing Key slot 1. */ -const uint8_t sh1pub[] - = {0xe1, 0xdc, 0xf9, 0xc3, 0x46, 0xbc, 0xf2, 0xe7, 0x8b, 0xa8, 0xf0, 0x27, 0xd8, 0x0a, 0x8a, 0x33, - 0xcc, 0xf3, 0xe9, 0xdf, 0x6b, 0xdf, 0x65, 0xa2, 0xc1, 0xae, 0xc4, 0xd9, 0x21, 0xe1, 0x8d, 0x51}; +const uint8_t sh1pub[] = {0xe1, 0xdc, 0xf9, 0xc3, 0x46, 0xbc, 0xf2, 0xe7, 0x8b, 0xa8, 0xf0, + 0x27, 0xd8, 0x0a, 0x8a, 0x33, 0xcc, 0xf3, 0xe9, 0xdf, 0x6b, 0xdf, + 0x65, 0xa2, 0xc1, 0xae, 0xc4, 0xd9, 0x21, 0xe1, 0x8d, 0x51}; /** @brief X25519 private key to execute a Secure Channel Handshake on Pairing Key slot 2. */ -const uint8_t sh2priv[] - = {0x00, 0x40, 0x5e, 0x19, 0x46, 0x75, 0xab, 0xe1, 0x5f, 0x0b, 0x57, 0xf2, 0x5b, 0x12, 0x86, 0x62, - 0xab, 0xb0, 0xe9, 0xc6, 0xa7, 0xc3, 0xca, 0xdf, 0x1c, 0xb1, 0xd2, 0xb7, 0xf8, 0xcf, 0x35, 0x47}; +const uint8_t sh2priv[] = {0x00, 0x40, 0x5e, 0x19, 0x46, 0x75, 0xab, 0xe1, 0x5f, 0x0b, 0x57, + 0xf2, 0x5b, 0x12, 0x86, 0x62, 0xab, 0xb0, 0xe9, 0xc6, 0xa7, 0xc3, + 0xca, 0xdf, 0x1c, 0xb1, 0xd2, 0xb7, 0xf8, 0xcf, 0x35, 0x47}; /** @brief X25519 public key to execute a Secure Channel Handshake on Pairing Key slot 2. */ -const uint8_t sh2pub[] - = {0x66, 0xb9, 0x92, 0x5a, 0x85, 0x66, 0xe8, 0x09, 0x5c, 0x56, 0x80, 0xfb, 0x22, 0xd4, 0xb8, 0x4b, - 0xf8, 0xe3, 0x12, 0xb2, 0x7c, 0x4b, 0xac, 0xce, 0x26, 0x3c, 0x78, 0x39, 0x6d, 0x4c, 0x16, 0x6c}; +const uint8_t sh2pub[] = {0x66, 0xb9, 0x92, 0x5a, 0x85, 0x66, 0xe8, 0x09, 0x5c, 0x56, 0x80, + 0xfb, 0x22, 0xd4, 0xb8, 0x4b, 0xf8, 0xe3, 0x12, 0xb2, 0x7c, 0x4b, + 0xac, 0xce, 0x26, 0x3c, 0x78, 0x39, 0x6d, 0x4c, 0x16, 0x6c}; /** @brief X25519 private key to execute a Secure Channel Handshake on Pairing Key slot 3. */ -const uint8_t sh3priv[] - = {0xb0, 0x90, 0x9f, 0xe1, 0xf3, 0x1f, 0xa1, 0x21, 0x75, 0xef, 0x45, 0xb1, 0x42, 0xde, 0x0e, 0xdd, - 0xa1, 0xf4, 0x51, 0x01, 0x40, 0xc2, 0xe5, 0x2c, 0xf4, 0x68, 0xac, 0x96, 0xa1, 0x0e, 0xcb, 0x46}; +const uint8_t sh3priv[] = {0xb0, 0x90, 0x9f, 0xe1, 0xf3, 0x1f, 0xa1, 0x21, 0x75, 0xef, 0x45, + 0xb1, 0x42, 0xde, 0x0e, 0xdd, 0xa1, 0xf4, 0x51, 0x01, 0x40, 0xc2, + 0xe5, 0x2c, 0xf4, 0x68, 0xac, 0x96, 0xa1, 0x0e, 0xcb, 0x46}; /** @brief X25519 public key to execute a Secure Channel Handshake on Pairing Key slot 3. */ -const uint8_t sh3pub[] - = {0x22, 0x57, 0xa8, 0x2f, 0x85, 0x8f, 0x13, 0x32, 0xfa, 0x0f, 0xf6, 0x0c, 0x76, 0x29, 0x42, 0x70, - 0xa9, 0x58, 0x9d, 0xfd, 0x47, 0xa5, 0x23, 0x78, 0x18, 0x4d, 0x2d, 0x38, 0xf0, 0xa7, 0xc4, 0x01}; +const uint8_t sh3pub[] = {0x22, 0x57, 0xa8, 0x2f, 0x85, 0x8f, 0x13, 0x32, 0xfa, 0x0f, 0xf6, + 0x0c, 0x76, 0x29, 0x42, 0x70, 0xa9, 0x58, 0x9d, 0xfd, 0x47, 0xa5, + 0x23, 0x78, 0x18, 0x4d, 0x2d, 0x38, 0xf0, 0xa7, 0xc4, 0x01}; /** * @brief Creates an HW wallet example config from the virgin R config. @@ -75,21 +75,28 @@ static void create_example_r_config(struct lt_config_t *r_config) { //-------CFG_START_UP------------------------------------ // Enable MBIST and RNGTEST (DIS in their names stands for disable, so writing 0 enables them) - r_config->obj[TR01_CFG_START_UP_IDX] - &= ~(BOOTLOADER_CO_CFG_START_UP_MBIST_DIS_MASK | BOOTLOADER_CO_CFG_START_UP_RNGTEST_DIS_MASK); + r_config->obj[TR01_CFG_START_UP_IDX] &= ~(BOOTLOADER_CO_CFG_START_UP_MBIST_DIS_MASK | + BOOTLOADER_CO_CFG_START_UP_RNGTEST_DIS_MASK); //-------CFG_SENSORS------------------------------------- // Enable all sensors (DIS in their names stands for disable, so writing 0 enables them) r_config->obj[TR01_CFG_SENSORS_IDX] &= ~( - BOOTLOADER_CO_CFG_SENSORS_PTRNG0_TEST_DIS_MASK | BOOTLOADER_CO_CFG_SENSORS_PTRNG1_TEST_DIS_MASK - | BOOTLOADER_CO_CFG_SENSORS_OSCILLATOR_MON_DIS_MASK | BOOTLOADER_CO_CFG_SENSORS_SHIELD_DIS_MASK - | BOOTLOADER_CO_CFG_SENSORS_VOLTAGE_MON_DIS_MASK | BOOTLOADER_CO_CFG_SENSORS_GLITCH_DET_DIS_MASK - | BOOTLOADER_CO_CFG_SENSORS_TEMP_SENS_DIS_MASK | BOOTLOADER_CO_CFG_SENSORS_LASER_DET_DIS_MASK - | BOOTLOADER_CO_CFG_SENSORS_EM_PULSE_DET_DIS_MASK | BOOTLOADER_CO_CFG_SENSORS_CPU_ALERT_DIS_MASK - | BOOTLOADER_CO_CFG_SENSORS_PIN_VERIF_BIT_FLIP_DIS_MASK | BOOTLOADER_CO_CFG_SENSORS_SCB_BIT_FLIP_DIS_MASK - | BOOTLOADER_CO_CFG_SENSORS_CPB_BIT_FLIP_DIS_MASK | BOOTLOADER_CO_CFG_SENSORS_ECC_BIT_FLIP_DIS_MASK - | BOOTLOADER_CO_CFG_SENSORS_R_MEM_BIT_FLIP_DIS_MASK | BOOTLOADER_CO_CFG_SENSORS_EKDB_BIT_FLIP_DIS_MASK - | BOOTLOADER_CO_CFG_SENSORS_I_MEM_BIT_FLIP_DIS_MASK | BOOTLOADER_CO_CFG_SENSORS_PLATFORM_BIT_FLIP_DIS_MASK); + BOOTLOADER_CO_CFG_SENSORS_PTRNG0_TEST_DIS_MASK | + BOOTLOADER_CO_CFG_SENSORS_PTRNG1_TEST_DIS_MASK | + BOOTLOADER_CO_CFG_SENSORS_OSCILLATOR_MON_DIS_MASK | BOOTLOADER_CO_CFG_SENSORS_SHIELD_DIS_MASK | + BOOTLOADER_CO_CFG_SENSORS_VOLTAGE_MON_DIS_MASK | + BOOTLOADER_CO_CFG_SENSORS_GLITCH_DET_DIS_MASK | BOOTLOADER_CO_CFG_SENSORS_TEMP_SENS_DIS_MASK | + BOOTLOADER_CO_CFG_SENSORS_LASER_DET_DIS_MASK | + BOOTLOADER_CO_CFG_SENSORS_EM_PULSE_DET_DIS_MASK | + BOOTLOADER_CO_CFG_SENSORS_CPU_ALERT_DIS_MASK | + BOOTLOADER_CO_CFG_SENSORS_PIN_VERIF_BIT_FLIP_DIS_MASK | + BOOTLOADER_CO_CFG_SENSORS_SCB_BIT_FLIP_DIS_MASK | + BOOTLOADER_CO_CFG_SENSORS_CPB_BIT_FLIP_DIS_MASK | + BOOTLOADER_CO_CFG_SENSORS_ECC_BIT_FLIP_DIS_MASK | + BOOTLOADER_CO_CFG_SENSORS_R_MEM_BIT_FLIP_DIS_MASK | + BOOTLOADER_CO_CFG_SENSORS_EKDB_BIT_FLIP_DIS_MASK | + BOOTLOADER_CO_CFG_SENSORS_I_MEM_BIT_FLIP_DIS_MASK | + BOOTLOADER_CO_CFG_SENSORS_PLATFORM_BIT_FLIP_DIS_MASK); //-------CFG_DEBUG--------------------------------------- // Disable FW logging @@ -105,41 +112,57 @@ static void create_example_r_config(struct lt_config_t *r_config) //------- TR01_CFG_UAP_PAIRING_KEY_WRITE --------------------- // Disable writing pairing keys for all slots r_config->obj[TR01_CFG_UAP_PAIRING_KEY_WRITE_IDX] &= ~LT_TO_PAIRING_KEY_SH0( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_PAIRING_KEY_WRITE_IDX] &= ~LT_TO_PAIRING_KEY_SH1( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_PAIRING_KEY_WRITE_IDX] &= ~LT_TO_PAIRING_KEY_SH2( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_PAIRING_KEY_WRITE_IDX] &= ~LT_TO_PAIRING_KEY_SH3( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); //------- TR01_CFG_UAP_PAIRING_KEY_READ ---------------------- // All sessions can read pairing keys r_config->obj[TR01_CFG_UAP_PAIRING_KEY_READ_IDX] |= LT_TO_PAIRING_KEY_SH0( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_PAIRING_KEY_READ_IDX] |= LT_TO_PAIRING_KEY_SH1( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_PAIRING_KEY_READ_IDX] |= LT_TO_PAIRING_KEY_SH2( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_PAIRING_KEY_READ_IDX] |= LT_TO_PAIRING_KEY_SH3( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); //------- TR01_CFG_UAP_PAIRING_KEY_INVALIDATE ---------------- // 1. Disable all, then enable only specific ones r_config->obj[TR01_CFG_UAP_PAIRING_KEY_INVALIDATE_IDX] &= ~LT_TO_PAIRING_KEY_SH0( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_PAIRING_KEY_INVALIDATE_IDX] &= ~LT_TO_PAIRING_KEY_SH1( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_PAIRING_KEY_INVALIDATE_IDX] &= ~LT_TO_PAIRING_KEY_SH2( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_PAIRING_KEY_INVALIDATE_IDX] &= ~LT_TO_PAIRING_KEY_SH3( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); // 2. Pairing key SH0PUB can be invalidated only from session with SH0PUB - r_config->obj[TR01_CFG_UAP_PAIRING_KEY_INVALIDATE_IDX] |= LT_TO_PAIRING_KEY_SH0(LT_SESSION_SH0_HAS_ACCESS); + r_config->obj[TR01_CFG_UAP_PAIRING_KEY_INVALIDATE_IDX] |= LT_TO_PAIRING_KEY_SH0( + LT_SESSION_SH0_HAS_ACCESS); // 3. Pairing keys SH1PUB, SH2PUB and SH3PUB can be invalidated only from session with SH3PUB - r_config->obj[TR01_CFG_UAP_PAIRING_KEY_INVALIDATE_IDX] |= LT_TO_PAIRING_KEY_SH1(LT_SESSION_SH3_HAS_ACCESS); - r_config->obj[TR01_CFG_UAP_PAIRING_KEY_INVALIDATE_IDX] |= LT_TO_PAIRING_KEY_SH2(LT_SESSION_SH3_HAS_ACCESS); - r_config->obj[TR01_CFG_UAP_PAIRING_KEY_INVALIDATE_IDX] |= LT_TO_PAIRING_KEY_SH3(LT_SESSION_SH3_HAS_ACCESS); + r_config->obj[TR01_CFG_UAP_PAIRING_KEY_INVALIDATE_IDX] |= LT_TO_PAIRING_KEY_SH1( + LT_SESSION_SH3_HAS_ACCESS); + r_config->obj[TR01_CFG_UAP_PAIRING_KEY_INVALIDATE_IDX] |= LT_TO_PAIRING_KEY_SH2( + LT_SESSION_SH3_HAS_ACCESS); + r_config->obj[TR01_CFG_UAP_PAIRING_KEY_INVALIDATE_IDX] |= LT_TO_PAIRING_KEY_SH3( + LT_SESSION_SH3_HAS_ACCESS); //------- TR01_CFG_UAP_R_CONFIG_WRITE_ERASE ------------------ // Keep at reset value, not used currently @@ -155,8 +178,8 @@ static void create_example_r_config(struct lt_config_t *r_config) //------- TR01_CFG_UAP_PING ---------------------------------- // Enable for all pairing keys - r_config->obj[TR01_CFG_UAP_PING_IDX] |= (LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS - | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + r_config->obj[TR01_CFG_UAP_PING_IDX] |= (LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | + LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); //------- TR01_CFG_UAP_R_MEM_DATA_WRITE ---------------------- // Reset value, not used currently @@ -169,156 +192,207 @@ static void create_example_r_config(struct lt_config_t *r_config) //------- TR01_CFG_UAP_RANDOM_VALUE_GET ---------------------- // Enable for all pairing keys - r_config->obj[TR01_CFG_UAP_RANDOM_VALUE_GET_IDX] |= (LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS - | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + r_config->obj[TR01_CFG_UAP_RANDOM_VALUE_GET_IDX] |= (LT_SESSION_SH0_HAS_ACCESS | + LT_SESSION_SH1_HAS_ACCESS | + LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); //------- TR01_CFG_UAP_ECC_KEY_GENERATE ---------------------- // 1. Disable all, then enable only specific ones r_config->obj[TR01_CFG_UAP_ECC_KEY_GENERATE_IDX] &= ~LT_TO_ECC_KEY_SLOT_0_7( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_ECC_KEY_GENERATE_IDX] &= ~LT_TO_ECC_KEY_SLOT_8_15( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_ECC_KEY_GENERATE_IDX] &= ~LT_TO_ECC_KEY_SLOT_16_23( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_ECC_KEY_GENERATE_IDX] &= ~LT_TO_ECC_KEY_SLOT_24_31( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); // 2. Only session with SH3PUB can generate keys in slots 8-31 - r_config->obj[TR01_CFG_UAP_ECC_KEY_GENERATE_IDX] - |= (LT_TO_ECC_KEY_SLOT_8_15(LT_SESSION_SH3_HAS_ACCESS) | LT_TO_ECC_KEY_SLOT_16_23(LT_SESSION_SH3_HAS_ACCESS) - | LT_TO_ECC_KEY_SLOT_24_31(LT_SESSION_SH3_HAS_ACCESS)); + r_config->obj[TR01_CFG_UAP_ECC_KEY_GENERATE_IDX] |= + (LT_TO_ECC_KEY_SLOT_8_15(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_ECC_KEY_SLOT_16_23(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_ECC_KEY_SLOT_24_31(LT_SESSION_SH3_HAS_ACCESS)); //------- TR01_CFG_UAP_ECC_KEY_STORE ------------------------- // 1. Disable all, then enable only specific ones r_config->obj[TR01_CFG_UAP_ECC_KEY_STORE_IDX] &= ~LT_TO_ECC_KEY_SLOT_0_7( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_ECC_KEY_STORE_IDX] &= ~LT_TO_ECC_KEY_SLOT_8_15( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_ECC_KEY_STORE_IDX] &= ~LT_TO_ECC_KEY_SLOT_16_23( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_ECC_KEY_STORE_IDX] &= ~LT_TO_ECC_KEY_SLOT_24_31( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); // 2. Session with SH1PUB can store key into ECC key slot 0-7 r_config->obj[TR01_CFG_UAP_ECC_KEY_STORE_IDX] |= LT_TO_ECC_KEY_SLOT_0_7(LT_SESSION_SH1_HAS_ACCESS); // 3. Session with SH3PUB can store key into ECC key slot 8-31 - r_config->obj[TR01_CFG_UAP_ECC_KEY_STORE_IDX] |= LT_TO_ECC_KEY_SLOT_8_15(LT_SESSION_SH3_HAS_ACCESS) - | LT_TO_ECC_KEY_SLOT_16_23(LT_SESSION_SH3_HAS_ACCESS) - | LT_TO_ECC_KEY_SLOT_24_31(LT_SESSION_SH3_HAS_ACCESS); + r_config->obj[TR01_CFG_UAP_ECC_KEY_STORE_IDX] |= + LT_TO_ECC_KEY_SLOT_8_15(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_ECC_KEY_SLOT_16_23(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_ECC_KEY_SLOT_24_31(LT_SESSION_SH3_HAS_ACCESS); //------- TR01_CFG_UAP_ECC_KEY_READ -------------------------- // Enable for all pairing keys r_config->obj[TR01_CFG_UAP_ECC_KEY_READ_IDX] |= LT_TO_ECC_KEY_SLOT_0_7( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_ECC_KEY_READ_IDX] |= LT_TO_ECC_KEY_SLOT_8_15( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_ECC_KEY_READ_IDX] |= LT_TO_ECC_KEY_SLOT_16_23( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_ECC_KEY_READ_IDX] |= LT_TO_ECC_KEY_SLOT_24_31( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); //------- TR01_CFG_UAP_ECC_KEY_ERASE ------------------------- // 1. Disable all, then enable only specific ones r_config->obj[TR01_CFG_UAP_ECC_KEY_ERASE_IDX] &= ~LT_TO_ECC_KEY_SLOT_0_7( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_ECC_KEY_ERASE_IDX] &= ~LT_TO_ECC_KEY_SLOT_8_15( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_ECC_KEY_ERASE_IDX] &= ~LT_TO_ECC_KEY_SLOT_16_23( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_ECC_KEY_ERASE_IDX] &= ~LT_TO_ECC_KEY_SLOT_24_31( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); // 2. Session with SH1PUB can erase ECC key slots 0-7 r_config->obj[TR01_CFG_UAP_ECC_KEY_ERASE_IDX] |= LT_TO_ECC_KEY_SLOT_0_7(LT_SESSION_SH1_HAS_ACCESS); // 3. Session with SH3PUB can erase ECC key slots 8-31 - r_config->obj[TR01_CFG_UAP_ECC_KEY_ERASE_IDX] |= LT_TO_ECC_KEY_SLOT_8_15(LT_SESSION_SH3_HAS_ACCESS) - | LT_TO_ECC_KEY_SLOT_16_23(LT_SESSION_SH3_HAS_ACCESS) - | LT_TO_ECC_KEY_SLOT_24_31(LT_SESSION_SH3_HAS_ACCESS); + r_config->obj[TR01_CFG_UAP_ECC_KEY_ERASE_IDX] |= + LT_TO_ECC_KEY_SLOT_8_15(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_ECC_KEY_SLOT_16_23(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_ECC_KEY_SLOT_24_31(LT_SESSION_SH3_HAS_ACCESS); //------- TR01_CFG_UAP_ECDSA_SIGN ---------------------------- // 1. Disable all, then enable only specific ones r_config->obj[TR01_CFG_UAP_ECDSA_SIGN_IDX] &= ~LT_TO_ECC_KEY_SLOT_0_7( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_ECDSA_SIGN_IDX] &= ~LT_TO_ECC_KEY_SLOT_8_15( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_ECDSA_SIGN_IDX] &= ~LT_TO_ECC_KEY_SLOT_16_23( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_ECDSA_SIGN_IDX] &= ~LT_TO_ECC_KEY_SLOT_24_31( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); // 2. Session with SH3PUB can sign with all ECC key slots - r_config->obj[TR01_CFG_UAP_ECDSA_SIGN_IDX] - |= (LT_TO_ECC_KEY_SLOT_0_7(LT_SESSION_SH3_HAS_ACCESS) | LT_TO_ECC_KEY_SLOT_8_15(LT_SESSION_SH3_HAS_ACCESS) - | LT_TO_ECC_KEY_SLOT_16_23(LT_SESSION_SH3_HAS_ACCESS) - | LT_TO_ECC_KEY_SLOT_24_31(LT_SESSION_SH3_HAS_ACCESS)); + r_config->obj[TR01_CFG_UAP_ECDSA_SIGN_IDX] |= + (LT_TO_ECC_KEY_SLOT_0_7(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_ECC_KEY_SLOT_8_15(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_ECC_KEY_SLOT_16_23(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_ECC_KEY_SLOT_24_31(LT_SESSION_SH3_HAS_ACCESS)); //------- TR01_CFG_UAP_EDDSA_SIGN ---------------------------- // 1. Disable all, then enable only specific ones r_config->obj[TR01_CFG_UAP_EDDSA_SIGN_IDX] &= ~LT_TO_ECC_KEY_SLOT_0_7( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_EDDSA_SIGN_IDX] &= ~LT_TO_ECC_KEY_SLOT_8_15( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_EDDSA_SIGN_IDX] &= ~LT_TO_ECC_KEY_SLOT_16_23( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_EDDSA_SIGN_IDX] &= ~LT_TO_ECC_KEY_SLOT_24_31( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); // 2. Session with SH3PUB can sign with all ECC key slots - r_config->obj[TR01_CFG_UAP_EDDSA_SIGN_IDX] - |= (LT_TO_ECC_KEY_SLOT_0_7(LT_SESSION_SH3_HAS_ACCESS) | LT_TO_ECC_KEY_SLOT_8_15(LT_SESSION_SH3_HAS_ACCESS) - | LT_TO_ECC_KEY_SLOT_16_23(LT_SESSION_SH3_HAS_ACCESS) - | LT_TO_ECC_KEY_SLOT_24_31(LT_SESSION_SH3_HAS_ACCESS)); + r_config->obj[TR01_CFG_UAP_EDDSA_SIGN_IDX] |= + (LT_TO_ECC_KEY_SLOT_0_7(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_ECC_KEY_SLOT_8_15(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_ECC_KEY_SLOT_16_23(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_ECC_KEY_SLOT_24_31(LT_SESSION_SH3_HAS_ACCESS)); //------- TR01_CFG_UAP_MCOUNTER_INIT ------------------------- // 1. Disable all, then enable only specific ones r_config->obj[TR01_CFG_UAP_MCOUNTER_INIT_IDX] &= ~LT_TO_MCOUNTER_0_3( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_MCOUNTER_INIT_IDX] &= ~LT_TO_MCOUNTER_4_7( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_MCOUNTER_INIT_IDX] &= ~LT_TO_MCOUNTER_8_11( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_MCOUNTER_INIT_IDX] &= ~LT_TO_MCOUNTER_12_15( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); // 2. Session with SH3PUB can init all mcounters - r_config->obj[TR01_CFG_UAP_MCOUNTER_INIT_IDX] - |= (LT_TO_MCOUNTER_0_3(LT_SESSION_SH3_HAS_ACCESS) | LT_TO_MCOUNTER_4_7(LT_SESSION_SH3_HAS_ACCESS) - | LT_TO_MCOUNTER_8_11(LT_SESSION_SH3_HAS_ACCESS) | LT_TO_MCOUNTER_12_15(LT_SESSION_SH3_HAS_ACCESS)); + r_config->obj[TR01_CFG_UAP_MCOUNTER_INIT_IDX] |= (LT_TO_MCOUNTER_0_3(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_MCOUNTER_4_7(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_MCOUNTER_8_11(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_MCOUNTER_12_15(LT_SESSION_SH3_HAS_ACCESS)); //------- TR01_CFG_UAP_MCOUNTER_GET -------------------------- // 1. Disable all, then enable only specific ones r_config->obj[TR01_CFG_UAP_MCOUNTER_GET_IDX] &= ~LT_TO_MCOUNTER_0_3( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_MCOUNTER_GET_IDX] &= ~LT_TO_MCOUNTER_4_7( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_MCOUNTER_GET_IDX] &= ~LT_TO_MCOUNTER_8_11( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_MCOUNTER_GET_IDX] &= ~LT_TO_MCOUNTER_12_15( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); // 2. Session with SH3PUB can get all mcounters - r_config->obj[TR01_CFG_UAP_MCOUNTER_GET_IDX] - |= (LT_TO_MCOUNTER_0_3(LT_SESSION_SH3_HAS_ACCESS) | LT_TO_MCOUNTER_4_7(LT_SESSION_SH3_HAS_ACCESS) - | LT_TO_MCOUNTER_8_11(LT_SESSION_SH3_HAS_ACCESS) | LT_TO_MCOUNTER_12_15(LT_SESSION_SH3_HAS_ACCESS)); + r_config->obj[TR01_CFG_UAP_MCOUNTER_GET_IDX] |= (LT_TO_MCOUNTER_0_3(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_MCOUNTER_4_7(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_MCOUNTER_8_11(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_MCOUNTER_12_15(LT_SESSION_SH3_HAS_ACCESS)); //------- TR01_CFG_UAP_MCOUNTER_UPDATE ----------------------- // 1. Disable all, then enable only specific ones r_config->obj[TR01_CFG_UAP_MCOUNTER_UPDATE_IDX] &= ~LT_TO_MCOUNTER_0_3( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_MCOUNTER_UPDATE_IDX] &= ~LT_TO_MCOUNTER_4_7( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_MCOUNTER_UPDATE_IDX] &= ~LT_TO_MCOUNTER_8_11( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_MCOUNTER_UPDATE_IDX] &= ~LT_TO_MCOUNTER_12_15( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); // 2. Session with SH3PUB can update all mcounters - r_config->obj[TR01_CFG_UAP_MCOUNTER_UPDATE_IDX] - |= (LT_TO_MCOUNTER_0_3(LT_SESSION_SH3_HAS_ACCESS) | LT_TO_MCOUNTER_4_7(LT_SESSION_SH3_HAS_ACCESS) - | LT_TO_MCOUNTER_8_11(LT_SESSION_SH3_HAS_ACCESS) | LT_TO_MCOUNTER_12_15(LT_SESSION_SH3_HAS_ACCESS)); + r_config->obj[TR01_CFG_UAP_MCOUNTER_UPDATE_IDX] |= + (LT_TO_MCOUNTER_0_3(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_MCOUNTER_4_7(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_MCOUNTER_8_11(LT_SESSION_SH3_HAS_ACCESS) | + LT_TO_MCOUNTER_12_15(LT_SESSION_SH3_HAS_ACCESS)); //------- TR01_CFG_UAP_MAC_AND_DESTROY_ADDR ----------------------- // Enable for all pairing key slots r_config->obj[TR01_CFG_UAP_MAC_AND_DESTROY_IDX] |= LT_TO_MACANDD_SLOT_0_31( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_MAC_AND_DESTROY_IDX] |= LT_TO_MACANDD_SLOT_32_63( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_MAC_AND_DESTROY_IDX] |= LT_TO_MACANDD_SLOT_64_95( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); r_config->obj[TR01_CFG_UAP_MAC_AND_DESTROY_IDX] |= LT_TO_MACANDD_SLOT_96_127( - LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | LT_SESSION_SH3_HAS_ACCESS); + LT_SESSION_SH0_HAS_ACCESS | LT_SESSION_SH1_HAS_ACCESS | LT_SESSION_SH2_HAS_ACCESS | + LT_SESSION_SH3_HAS_ACCESS); } /** @@ -344,12 +418,14 @@ static int session_initial(lt_handle_t *h) const uint8_t *pub_keys[] = {DEFAULT_SH0_PUB, sh1pub, sh2pub, sh3pub}; printf("Starting Secure Session with key slot %d...", (int)TR01_PAIRING_KEY_SLOT_INDEX_0); - ret = lt_verify_chip_and_start_secure_session(h, DEFAULT_SH0_PRIV, DEFAULT_SH0_PUB, TR01_PAIRING_KEY_SLOT_INDEX_0); + ret = lt_verify_chip_and_start_secure_session(h, DEFAULT_SH0_PRIV, DEFAULT_SH0_PUB, + TR01_PAIRING_KEY_SLOT_INDEX_0); if (LT_OK != ret) { - fprintf(stderr, "\nFailed to start Secure Session with key %d, ret=%s\n", (int)TR01_PAIRING_KEY_SLOT_INDEX_0, - lt_ret_verbose(ret)); + fprintf(stderr, "\nFailed to start Secure Session with key %d, ret=%s\n", + (int)TR01_PAIRING_KEY_SLOT_INDEX_0, lt_ret_verbose(ret)); fprintf(stderr, - "Check if you use correct SH0 keys! Hint: if you use an engineering sample chip, compile with " + "Check if you use correct SH0 keys! Hint: if you use an engineering sample chip, " + "compile with " "-DLT_SH0_KEYS=eng_sample\n"); return -1; } @@ -435,7 +511,8 @@ static int session_initial(lt_handle_t *h) } /** - * @brief Tries to start a Secure Session with previously invalidated pairing key slot 0 and checks that it fails. + * @brief Tries to start a Secure Session with previously invalidated pairing key slot 0 and checks + * that it fails. * * @param h Handle for communication with TROPIC01 * @return 0 if success, -1 otherwise @@ -444,8 +521,10 @@ static int session0(lt_handle_t *h) { lt_ret_t ret; - printf("Starting Secure Session with key slot %d (should fail)...", (int)TR01_PAIRING_KEY_SLOT_INDEX_0); - ret = lt_verify_chip_and_start_secure_session(h, DEFAULT_SH0_PRIV, DEFAULT_SH0_PUB, TR01_PAIRING_KEY_SLOT_INDEX_0); + printf("Starting Secure Session with key slot %d (should fail)...", + (int)TR01_PAIRING_KEY_SLOT_INDEX_0); + ret = lt_verify_chip_and_start_secure_session(h, DEFAULT_SH0_PRIV, DEFAULT_SH0_PUB, + TR01_PAIRING_KEY_SLOT_INDEX_0); if (ret != LT_L2_HSK_ERR) { fprintf(stderr, "\nReturn value is not LT_L2_HSK_ERR, ret=%s\n", lt_ret_verbose(ret)); return -1; @@ -493,7 +572,8 @@ static int session1(lt_handle_t *h) printf("Storing attestation key into ECC slot %d...", (int)TR01_ECC_SLOT_0); ret = lt_ecc_key_store(h, TR01_ECC_SLOT_0, TR01_CURVE_ED25519, attestation_key); if (LT_OK != ret) { - fprintf(stderr, "\nFailed to store ECC key to slot %d, ret=%s\n", (int)TR01_ECC_SLOT_0, lt_ret_verbose(ret)); + fprintf(stderr, "\nFailed to store ECC key to slot %d, ret=%s\n", (int)TR01_ECC_SLOT_0, + lt_ret_verbose(ret)); lt_session_abort(h); return -1; } @@ -505,7 +585,8 @@ static int session1(lt_handle_t *h) printf("\tWriting pairing key slot %" PRIu8 "...", i); ret = lt_pairing_key_write(h, dummy_key, i); if (LT_L3_UNAUTHORIZED != ret) { - fprintf(stderr, "\n\tReturn value is not LT_L3_UNAUTHORIZED, ret=%s\n", lt_ret_verbose(ret)); + fprintf(stderr, "\n\tReturn value is not LT_L3_UNAUTHORIZED, ret=%s\n", + lt_ret_verbose(ret)); lt_session_abort(h); return -1; } @@ -559,7 +640,8 @@ static int session2(lt_handle_t *h) printf("\t<-- Message received from TROPIC01: '%s'\n", recv_buf); uint8_t dummy_key[TR01_CURVE_PRIVKEY_LEN] = {0}; - printf("Trying to store key into ECC slot %d (should fail due to unauthorized access)...", (int)TR01_ECC_SLOT_0); + printf("Trying to store key into ECC slot %d (should fail due to unauthorized access)...", + (int)TR01_ECC_SLOT_0); ret = lt_ecc_key_store(h, TR01_ECC_SLOT_0, TR01_CURVE_ED25519, dummy_key); if (LT_L3_UNAUTHORIZED != ret) { fprintf(stderr, "\n\tReturn value is not LT_L3_UNAUTHORIZED, ret=%s\n", lt_ret_verbose(ret)); @@ -573,7 +655,8 @@ static int session2(lt_handle_t *h) printf("\tWriting pairing key slot %" PRIu8 "...", i); ret = lt_pairing_key_write(h, dummy_key, i); if (LT_L3_UNAUTHORIZED != ret) { - fprintf(stderr, "\n\tReturn value is not LT_L3_UNAUTHORIZED, ret=%s\n", lt_ret_verbose(ret)); + fprintf(stderr, "\n\tReturn value is not LT_L3_UNAUTHORIZED, ret=%s\n", + lt_ret_verbose(ret)); lt_session_abort(h); return -1; } @@ -759,7 +842,8 @@ static int session3(lt_handle_t *h) printf("OK\n"); uint8_t dummy_key[TR01_CURVE_PRIVKEY_LEN] = {0}; - printf("Trying to store key into ECC slot %d (should fail due to unauthorized access)...", (int)TR01_ECC_SLOT_0); + printf("Trying to store key into ECC slot %d (should fail due to unauthorized access)...", + (int)TR01_ECC_SLOT_0); ret = lt_ecc_key_store(h, TR01_ECC_SLOT_0, TR01_CURVE_ED25519, dummy_key); if (LT_L3_UNAUTHORIZED != ret) { fprintf(stderr, "\nReturn value is not LT_L3_UNAUTHORIZED, ret=%s\n", lt_ret_verbose(ret)); @@ -773,7 +857,8 @@ static int session3(lt_handle_t *h) printf("\tWriting pairing key slot %" PRIu8 "...", i); ret = lt_pairing_key_write(h, dummy_key, i); if (LT_L3_UNAUTHORIZED != ret) { - fprintf(stderr, "\n\tReturn value is not LT_L3_UNAUTHORIZED, ret=%s\n", lt_ret_verbose(ret)); + fprintf(stderr, "\n\tReturn value is not LT_L3_UNAUTHORIZED, ret=%s\n", + lt_ret_verbose(ret)); lt_session_abort(h); return -1; } @@ -793,8 +878,9 @@ static int session3(lt_handle_t *h) int main(void) { - // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if you don't care - // about stdout/stderr output being shuffled or you use stdout only (or different output mechanism altogether). + // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if + // you don't care about stdout/stderr output being shuffled or you use stdout only (or different + // output mechanism altogether). setvbuf(stdout, NULL, _IONBF, 0); setvbuf(stderr, NULL, _IONBF, 0); @@ -827,7 +913,8 @@ int main(void) lt_handle.l2.device = &device; // Generate seed for the PRNG and seed it. - // Note: model uses rand(), which is not cryptographically secure. Better alternative should be used in production. + // Note: model uses rand(), which is not cryptographically secure. Better alternative should be + // used in production. unsigned int prng_seed; if (0 != getentropy(&prng_seed, sizeof(prng_seed))) { fprintf(stderr, "main: getentropy() failed (%s)!\n", strerror(errno)); @@ -850,7 +937,8 @@ int main(void) } printf("OK\n"); - // We need to ensure we are not in the Start-up Mode, as L3 commands are available only in the Application Firmware. + // We need to ensure we are not in the Start-up Mode, as L3 commands are available only in the + // Application Firmware. printf("Sending reboot request..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { diff --git a/examples/model/mac_and_destroy/main.c b/examples/model/mac_and_destroy/main.c index d57cca7a4..a19a63776 100644 --- a/examples/model/mac_and_destroy/main.c +++ b/examples/model/mac_and_destroy/main.c @@ -36,7 +36,8 @@ #define MACANDD_ROUNDS 12 #if (MACANDD_ROUNDS > 12) -#error "For this example, MACANDD_ROUNDS must be less than 12. Generally, the maximum is TR01_MACANDD_ROUNDS_MAX." +#error \ + "For this example, MACANDD_ROUNDS must be less than 12. Generally, the maximum is TR01_MACANDD_ROUNDS_MAX." #endif /** @brief Minimal size of MAC-and-Destroy additional data (only in this example). */ @@ -97,8 +98,8 @@ static void decrypt(const uint8_t *data, const uint8_t *key, uint8_t *destinatio * @param output Output buffer for HMAC result * @return psa_status_t */ -static psa_status_t hmac_sha256(const uint8_t *key, const size_t key_len, const uint8_t *data, const size_t data_len, - uint8_t *output) +static psa_status_t hmac_sha256(const uint8_t *key, const size_t key_len, const uint8_t *data, + const size_t data_len, uint8_t *output) { psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; psa_key_id_t key_id = 0; @@ -121,7 +122,9 @@ static psa_status_t hmac_sha256(const uint8_t *key, const size_t key_len, const PSA_HASH_LENGTH(PSA_ALG_SHA_256), &output_len); cleanup: - if (key_id != 0) psa_destroy_key(key_id); + if (key_id != 0) { + psa_destroy_key(key_id); + } psa_reset_key_attributes(&attributes); return status; } @@ -129,21 +132,22 @@ static psa_status_t hmac_sha256(const uint8_t *key, const size_t key_len, const /** * @brief Example function for setting PIN with Mac And Destroy. * - * @details The New PIN Setup procedure takes the user PIN, add data and high entropy master_secret as an input, - * initializes the scheme slots and returns a 32-byte key final_key as derivative of the master_secret. + * @details The New PIN Setup procedure takes the user PIN, add data and high entropy master_secret as + * an input, initializes the scheme slots and returns a 32-byte key final_key as derivative of the + * master_secret. * - * The MAC-and-Destroy PIN verification scheme uses slots located in the TROPIC01’s flash memory – one slot per - * PIN entry attempt. These slots are first initialized when a new PIN is being set up. - * The slots are then invalidated (destroyed) one by one with each PIN entry attempt. When the correct PIN is - * entered, the slots are initialized again, therefore the PIN entry limit is reset. - * PIN entry attempt fails if: + * The MAC-and-Destroy PIN verification scheme uses slots located in the TROPIC01’s flash memory – one + * slot per PIN entry attempt. These slots are first initialized when a new PIN is being set up. The + * slots are then invalidated (destroyed) one by one with each PIN entry attempt. When the correct PIN + * is entered, the slots are initialized again, therefore the PIN entry limit is reset. PIN entry + * attempt fails if: * * PIN is invalid * * The current slot is not initialized for a given PIN * * The current slot is destroyed by previous invalid PIN entry attempt. * - * There are more ways how to implement Mac And Destroy 'PIN set' functionality, differences could be in way of - * handling nvm data, number of tries, algorithm used for encryption, etc. This function is just one of the possible - * implementations of "PIN set". + * There are more ways how to implement Mac And Destroy 'PIN set' functionality, differences could be + * in way of handling nvm data, number of tries, algorithm used for encryption, etc. This function is + * just one of the possible implementations of "PIN set". * * Take it as an inspiration, copy it into your project and adapt it to your specific hw resources. * @@ -158,12 +162,14 @@ static psa_status_t hmac_sha256(const uint8_t *key, const size_t key_len, const * @param final_key Buffer into which final key will be placed when all went successfully * @return lt_ret_t LT_OK if correct, otherwise LT_FAIL */ -static lt_ret_t new_PIN_setup(lt_handle_t *h, const uint8_t *master_secret, const uint8_t *PIN, const uint8_t PIN_size, - const uint8_t *add, const uint8_t add_size, uint8_t *final_key) +static lt_ret_t new_PIN_setup(lt_handle_t *h, const uint8_t *master_secret, const uint8_t *PIN, + const uint8_t PIN_size, const uint8_t *add, const uint8_t add_size, + uint8_t *final_key) { - if (!h || !master_secret || !PIN || (PIN_size < MACANDD_PIN_SIZE_MIN) || (PIN_size > MACANDD_PIN_SIZE_MAX) - || (add_size > MACANDD_ADD_SIZE_MAX) || !final_key) { - // `add` parameter is not checked for NULL, because it can be NULL (handled in the lines below). + if (!h || !master_secret || !PIN || (PIN_size < MACANDD_PIN_SIZE_MIN) || + (PIN_size > MACANDD_PIN_SIZE_MAX) || (add_size > MACANDD_ADD_SIZE_MAX) || !final_key) { + // `add` parameter is not checked for NULL, because it can be NULL (handled in the lines + // below). return LT_PARAM_ERR; } @@ -174,8 +180,8 @@ static lt_ret_t new_PIN_setup(lt_handle_t *h, const uint8_t *master_secret, cons psa_status_t psa_ret; - // Clear variable for released final_key so there is known data (zeroes) in case this function ended sooner then - // final_key was prepared. + // Clear variable for released final_key so there is known data (zeroes) in case this function + // ended sooner then final_key was prepared. memset(final_key, 0, TR01_MAC_AND_DESTROY_DATA_SIZE); // Variable used during a process of getting a encryption key k_i. @@ -312,12 +318,12 @@ static lt_ret_t new_PIN_setup(lt_handle_t *h, const uint8_t *master_secret, cons /** * @brief Example function for checking PIN with Mac And Destroy. * - * @details The Pin Entry Check procedure takes the PIN and additional add data entered by the user as an input, and - * checks the PIN. If successful, the correct key k is returned. + * @details The Pin Entry Check procedure takes the PIN and additional add data entered by the user as + * an input, and checks the PIN. If successful, the correct key k is returned. * - * There are more ways how to implement Mac And Destroy 'PIN check' functionality, differences could be in way - * of handling nvm data, number of tries, algorithm used for decryption, etc. This function is just one of the possible - * implementations of "PIN check". + * There are more ways how to implement Mac And Destroy 'PIN check' functionality, differences could be + * in way of handling nvm data, number of tries, algorithm used for decryption, etc. This function is + * just one of the possible implementations of "PIN check". * * Take it as an inspiration, copy it into your project and adapt it to your specific hw resources. * @@ -331,12 +337,13 @@ static lt_ret_t new_PIN_setup(lt_handle_t *h, const uint8_t *master_secret, cons * @param final_key Buffer into which final_key will be saved * @return lt_ret_t LT_OK if correct, otherwise LT_FAIL */ -static lt_ret_t PIN_entry_check(lt_handle_t *h, const uint8_t *PIN, const uint8_t PIN_size, const uint8_t *add, - const uint8_t add_size, uint8_t *final_key) +static lt_ret_t PIN_entry_check(lt_handle_t *h, const uint8_t *PIN, const uint8_t PIN_size, + const uint8_t *add, const uint8_t add_size, uint8_t *final_key) { - if (!h || !PIN || (PIN_size < MACANDD_PIN_SIZE_MIN) || (PIN_size > MACANDD_PIN_SIZE_MAX) - || (add_size > MACANDD_ADD_SIZE_MAX) || !final_key) { - // `add` parameter is not checked for NULL, because it can be NULL (handled in the lines below). + if (!h || !PIN || (PIN_size < MACANDD_PIN_SIZE_MIN) || (PIN_size > MACANDD_PIN_SIZE_MAX) || + (add_size > MACANDD_ADD_SIZE_MAX) || !final_key) { + // `add` parameter is not checked for NULL, because it can be NULL (handled in the lines + // below). return LT_PARAM_ERR; } if (h->l3.session_status != LT_SECURE_SESSION_ON) { @@ -350,8 +357,8 @@ static lt_ret_t PIN_entry_check(lt_handle_t *h, const uint8_t *PIN, const uint8_ psa_status_t psa_ret; - // Clear variable for released final_key so there is known data (zeroes) in case this function ended sooner then - // final_key was prepared. + // Clear variable for released final_key so there is known data (zeroes) in case this function + // ended sooner then final_key was prepared. memset(final_key, 0, TR01_MAC_AND_DESTROY_DATA_SIZE); // Variable used during a process of getting a decryption key k_i. @@ -386,7 +393,8 @@ static lt_ret_t PIN_entry_check(lt_handle_t *h, const uint8_t *PIN, const uint8_ // Load M&D data from TROPIC01's R-Memory. printf("\tReading M&D data from R_Mem User slot %d...", MACANDD_R_MEM_DATA_SLOT); uint16_t read_size; - lt_ret_t ret = lt_r_mem_data_read(h, MACANDD_R_MEM_DATA_SLOT, (uint8_t *)&nvm, sizeof(nvm), &read_size); + lt_ret_t ret = lt_r_mem_data_read(h, MACANDD_R_MEM_DATA_SLOT, (uint8_t *)&nvm, sizeof(nvm), + &read_size); if (ret != LT_OK) { fprintf(stderr, "\n\tFailed to read User slot, ret=%s\n", lt_ret_verbose(ret)); goto exit; @@ -407,7 +415,8 @@ static lt_ret_t PIN_entry_check(lt_handle_t *h, const uint8_t *PIN, const uint8_ nvm.i--; // and store M&D data back to TROPIC01's R-Memory. - printf("\tWriting back M&D data into R_Mem User slot %d (erase, then write)...", MACANDD_R_MEM_DATA_SLOT); + printf("\tWriting back M&D data into R_Mem User slot %d (erase, then write)...", + MACANDD_R_MEM_DATA_SLOT); ret = lt_r_mem_data_erase(h, MACANDD_R_MEM_DATA_SLOT); if (ret != LT_OK) { fprintf(stderr, "\n\tFailed to erase User slot, ret=%s\n", lt_ret_verbose(ret)); @@ -485,7 +494,8 @@ static lt_ret_t PIN_entry_check(lt_handle_t *h, const uint8_t *PIN, const uint8_ nvm.i = MACANDD_ROUNDS; // Store NVM data for future use - printf("\tWriting M&D data into R_Mem User slot %d for future use (erase, then write)...", MACANDD_R_MEM_DATA_SLOT); + printf("\tWriting M&D data into R_Mem User slot %d for future use (erase, then write)...", + MACANDD_R_MEM_DATA_SLOT); ret = lt_r_mem_data_erase(h, MACANDD_R_MEM_DATA_SLOT); if (ret != LT_OK) { fprintf(stderr, "\n\tFailed to erase User slot, ret=%s\n", lt_ret_verbose(ret)); @@ -523,8 +533,9 @@ static lt_ret_t PIN_entry_check(lt_handle_t *h, const uint8_t *PIN, const uint8_ int main(void) { - // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if you don't care - // about stdout/stderr output being shuffled or you use stdout only (or different output mechanism altogether). + // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if + // you don't care about stdout/stderr output being shuffled or you use stdout only (or different + // output mechanism altogether). setvbuf(stdout, NULL, _IONBF, 0); setvbuf(stderr, NULL, _IONBF, 0); @@ -557,7 +568,8 @@ int main(void) lt_handle.l2.device = &device; // Generate seed for the PRNG and seed it. - // Note: model uses rand(), which is not cryptographically secure. Better alternative should be used in production. + // Note: model uses rand(), which is not cryptographically secure. Better alternative should be + // used in production. unsigned int prng_seed; if (0 != getentropy(&prng_seed, sizeof(prng_seed))) { fprintf(stderr, "main: getentropy() failed (%s)!\n", strerror(errno)); @@ -580,7 +592,8 @@ int main(void) } printf("OK\n"); - // We need to ensure we are not in the Start-up Mode, as L3 commands are available only in the Application Firmware. + // We need to ensure we are not in the Start-up Mode, as L3 commands are available only in the + // Application Firmware. printf("Sending reboot request..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { @@ -595,10 +608,11 @@ int main(void) ret = lt_verify_chip_and_start_secure_session(<_handle, DEFAULT_SH0_PRIV, DEFAULT_SH0_PUB, TR01_PAIRING_KEY_SLOT_INDEX_0); if (ret != LT_OK) { - fprintf(stderr, "\nFailed to start Secure Session with key %d, ret=%s\n", (int)TR01_PAIRING_KEY_SLOT_INDEX_0, - lt_ret_verbose(ret)); + fprintf(stderr, "\nFailed to start Secure Session with key %d, ret=%s\n", + (int)TR01_PAIRING_KEY_SLOT_INDEX_0, lt_ret_verbose(ret)); fprintf(stderr, - "Check if you use correct SH0 keys! Hint: if you use an engineering sample chip, compile with " + "Check if you use correct SH0 keys! Hint: if you use an engineering sample chip, " + "compile with " "-DLT_SH0_KEYS=eng_sample\n"); lt_deinit(<_handle); mbedtls_psa_crypto_free(); @@ -606,13 +620,14 @@ int main(void) } printf("OK\n"); - // This variable stores final_key which is released to the user after successful PIN check or PIN set. + // This variable stores final_key which is released to the user after successful PIN check or PIN + // set. uint8_t final_key_initialized[TR01_MAC_AND_DESTROY_DATA_SIZE] = {0}; // Additional data passed by user besides PIN - this is optional, but recommended. - uint8_t additional_data[] - = {0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, - 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88}; + uint8_t additional_data[] = {0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x11, 0x22, 0x33, + 0x44, 0x55, 0x66, 0x77, 0x88, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, + 0x77, 0x88, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88}; // User's PIN. uint8_t pin[] = {1, 2, 3, 4}; @@ -644,8 +659,8 @@ int main(void) // Set the PIN and log out the final_key printf("Setting the user PIN...\n"); - ret = new_PIN_setup(<_handle, master_secret, pin, sizeof(pin), additional_data, sizeof(additional_data), - final_key_initialized); + ret = new_PIN_setup(<_handle, master_secret, pin, sizeof(pin), additional_data, + sizeof(additional_data), final_key_initialized); if (ret != LT_OK) { fprintf(stderr, "\nFailed to set the user PIN, ret=%s\n", lt_ret_verbose(ret)); lt_session_abort(<_handle); @@ -655,7 +670,8 @@ int main(void) } printf("PIN was set successfully\n"); - ret = lt_print_bytes(final_key_initialized, sizeof(final_key_initialized), print_buff, PRINT_BUFF_SIZE); + ret = lt_print_bytes(final_key_initialized, sizeof(final_key_initialized), print_buff, + PRINT_BUFF_SIZE); if (ret != LT_OK) { fprintf(stderr, "lt_print_bytes failed, ret=%s\n", lt_ret_verbose(ret)); lt_session_abort(<_handle); @@ -669,8 +685,8 @@ int main(void) printf("\nWill do %d PIN check attempts with wrong PIN:\n", MACANDD_ROUNDS); for (int i = 1; i < MACANDD_ROUNDS; i++) { printf("\tInputting wrong PIN -> slot #%d will be destroyed...\n", i); - ret = PIN_entry_check(<_handle, pin_wrong, sizeof(pin_wrong), additional_data, sizeof(additional_data), - final_key_exported); + ret = PIN_entry_check(<_handle, pin_wrong, sizeof(pin_wrong), additional_data, + sizeof(additional_data), final_key_exported); if (ret != LT_FAIL) { fprintf(stderr, "\nReturn value is not LT_FAIL, ret=%s\n", lt_ret_verbose(ret)); lt_session_abort(<_handle); @@ -679,7 +695,8 @@ int main(void) return -1; } - ret = lt_print_bytes(final_key_exported, sizeof(final_key_exported), print_buff, PRINT_BUFF_SIZE); + ret = lt_print_bytes(final_key_exported, sizeof(final_key_exported), print_buff, + PRINT_BUFF_SIZE); if (ret != LT_OK) { fprintf(stderr, "lt_print_bytes failed, ret=%s\n", lt_ret_verbose(ret)); lt_session_abort(<_handle); @@ -691,7 +708,8 @@ int main(void) } printf("Doing final PIN attempt with correct PIN, slots are reinitialized again...\n"); - ret = PIN_entry_check(<_handle, pin, sizeof(pin), additional_data, sizeof(additional_data), final_key_exported); + ret = PIN_entry_check(<_handle, pin, sizeof(pin), additional_data, sizeof(additional_data), + final_key_exported); if (ret != LT_OK) { fprintf(stderr, "\nAttempt with correct PIN failed, ret=%s\n", lt_ret_verbose(ret)); lt_session_abort(<_handle); diff --git a/examples/model/separate_api/main.c b/examples/model/separate_api/main.c index b022e64ee..a1fb74dd4 100644 --- a/examples/model/separate_api/main.c +++ b/examples/model/separate_api/main.c @@ -3,7 +3,7 @@ * @brief Simple example of using Libtropic's Separate API with the model. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -33,8 +33,9 @@ int main(void) { - // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if you don't care - // about stdout/stderr output being shuffled or you use stdout only (or different output mechanism altogether). + // Cosmetics: Disable buffering to keep output in order. You do not need to do this in your app if + // you don't care about stdout/stderr output being shuffled or you use stdout only (or different + // output mechanism altogether). setvbuf(stdout, NULL, _IONBF, 0); setvbuf(stderr, NULL, _IONBF, 0); @@ -67,7 +68,8 @@ int main(void) lt_handle.l2.device = &device; // Generate seed for the PRNG and seed it. - // Note: model uses rand(), which is not cryptographically secure. Better alternative should be used in production. + // Note: model uses rand(), which is not cryptographically secure. Better alternative should be + // used in production. unsigned int prng_seed; if (0 != getentropy(&prng_seed, sizeof(prng_seed))) { fprintf(stderr, "main: getentropy() failed (%s)!\n", strerror(errno)); @@ -90,7 +92,8 @@ int main(void) } printf("OK\n"); - // We need to ensure we are not in the Startup Mode, as L3 commands are available only in the Application Firmware. + // We need to ensure we are not in the Startup Mode, as L3 commands are available only in the + // Application Firmware. printf("Sending reboot request..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { @@ -104,10 +107,10 @@ int main(void) printf("Getting Certificate Store from TROPIC01..."); uint8_t cert1[TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE], cert2[TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE], cert3[TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE], cert4[TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE]; - struct lt_cert_store_t store - = {.certs = {cert1, cert2, cert3, cert4}, - .buf_len = {TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, - TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE}}; + struct lt_cert_store_t store = { + .certs = {cert1, cert2, cert3, cert4}, + .buf_len = {TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, + TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE}}; ret = lt_get_info_cert_store(<_handle, &store); if (LT_OK != ret) { fprintf(stderr, "\nFailed to get Certificate Store, ret=%s\n", lt_ret_verbose(ret)); @@ -145,7 +148,8 @@ int main(void) } printf("OK\n"); - // handle's buffer (lt_handle.l2_buff) now contains data which must be transferred over a tunnel to TROPIC01. + // handle's buffer (lt_handle.l2_buff) now contains data which must be transferred over a tunnel to + // TROPIC01. // Following L2 functions are called on a remote host. printf("Executing lt_l2_send()..."); @@ -168,14 +172,15 @@ int main(void) } printf("OK\n"); - // Handle's buffer (lt_handle.l2_buff) now contains data which must be transferred over a tunnel back to the server. + // Handle's buffer (lt_handle.l2_buff) now contains data which must be transferred over a tunnel + // back to the server. // Once data are back on server's side, bytes are copied into lt_handle.l2_buff. // Then, the following L2 function is called on the server side. // This function prepares AES-GCM contexts for the session. printf("Executing lt_in__session_start()..."); - ret = lt_in__session_start(<_handle, stpub, TR01_PAIRING_KEY_SLOT_INDEX_0, LT_EX_SH0_PRIV, LT_EX_SH0_PUB, - &host_eph_keys); + ret = lt_in__session_start(<_handle, stpub, TR01_PAIRING_KEY_SLOT_INDEX_0, LT_EX_SH0_PRIV, + LT_EX_SH0_PUB, &host_eph_keys); if (LT_OK != ret) { fprintf(stderr, "\nlt_in__session_start failed, ret=%s\n", lt_ret_verbose(ret)); lt_deinit(<_handle); @@ -184,7 +189,8 @@ int main(void) } printf("OK\n"); - // Now, we can use separate API for the Ping command to send a message to TROPIC01 and receive a response. + // Now, we can use separate API for the Ping command to send a message to TROPIC01 and receive a + // response. uint8_t recv_buf[PING_MSG_SIZE]; printf("Executing lt_out__ping()..."); ret = lt_out__ping(<_handle, (const uint8_t *)PING_MSG, PING_MSG_SIZE); diff --git a/examples/stm32/nucleo_f439zi/fw_update/Src/main.c b/examples/stm32/nucleo_f439zi/fw_update/Src/main.c index 9957e52cc..9b94beeef 100644 --- a/examples/stm32/nucleo_f439zi/fw_update/Src/main.c +++ b/examples/stm32/nucleo_f439zi/fw_update/Src/main.c @@ -1,10 +1,10 @@ /** * @file main.c - * @brief Example showing how to perform an update of the TROPIC01 firmware using Libtropic on STM32 Nucleo F439ZI - * board. + * @brief Example showing how to perform an update of the TROPIC01 firmware using Libtropic on STM32 + * Nucleo F439ZI board. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. * * This example project is based on the UART/UART_Printf example from STM32 example library * which was created by the MCD Application Team. @@ -256,8 +256,9 @@ int main(void) } printf("OK\n"); - /* First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** be in the Start-up - Mode. If there are valid firmwares, TROPIC01 will begin to execute them automatically on boot. */ + /* First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** + be in the Start-up Mode. If there are valid firmwares, TROPIC01 will begin to execute them + automatically on boot. */ printf("Rebooting TROPIC01..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { @@ -436,8 +437,8 @@ static void SystemClock_Config(void) /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType - = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | + RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; diff --git a/examples/stm32/nucleo_f439zi/fw_update/Src/mbedtls_v4/crypto_config.h b/examples/stm32/nucleo_f439zi/fw_update/Src/mbedtls_v4/crypto_config.h index 303d6d9b4..4939948db 100644 --- a/examples/stm32/nucleo_f439zi/fw_update/Src/mbedtls_v4/crypto_config.h +++ b/examples/stm32/nucleo_f439zi/fw_update/Src/mbedtls_v4/crypto_config.h @@ -356,12 +356,13 @@ * * - mbedtls_calloc = MBEDTLS_PLATFORM_STD_CALLOC. * - * Defining MBEDTLS_PLATFORM_CALLOC_MACRO and #MBEDTLS_PLATFORM_STD_CALLOC at the same time is not possible. - * MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO must both be defined or undefined at the same time. - * #MBEDTLS_PLATFORM_STD_CALLOC and #MBEDTLS_PLATFORM_STD_FREE do not have to be defined at the same time, as, if they - * are used, dynamic setup of these functions is possible. See the tree above to see how are they handled in all cases. - * An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. - * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. + * Defining MBEDTLS_PLATFORM_CALLOC_MACRO and #MBEDTLS_PLATFORM_STD_CALLOC at the same time is not + * possible. MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO must both be defined or + * undefined at the same time. #MBEDTLS_PLATFORM_STD_CALLOC and #MBEDTLS_PLATFORM_STD_FREE do not have + * to be defined at the same time, as, if they are used, dynamic setup of these functions is possible. + * See the tree above to see how are they handled in all cases. An uninitialized + * #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. An uninitialized + * #MBEDTLS_PLATFORM_STD_FREE does not do anything. * * Requires: MBEDTLS_PLATFORM_C * @@ -475,20 +476,24 @@ /* To use the following function macros, MBEDTLS_PLATFORM_C must be enabled. */ /* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */ -// #define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be undefined. See -// MBEDTLS_PLATFORM_STD_CALLOC for requirements. */ #define MBEDTLS_PLATFORM_EXIT_MACRO exit /**< Default -// exit macro to use, can be undefined */ #define MBEDTLS_PLATFORM_FREE_MACRO free /**< Default free macro to -// use, can be undefined. See MBEDTLS_PLATFORM_STD_FREE for requirements. */ #define MBEDTLS_PLATFORM_FPRINTF_MACRO -// fprintf /**< Default fprintf macro to use, can be undefined */ #define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t -// //#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t /**< Default milliseconds time macro to use, can be -// undefined. MBEDTLS_HAVE_TIME must be enabled. It must be signed, and at least 64 bits. If it is changed from the -// default, MBEDTLS_PRINTF_MS_TIME must be updated to match.*/ #define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO -// mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ #define -// MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, -// can be undefined */ #define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be -// undefined */ #define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf /**< Default setbuf macro to use, can be undefined */ +// #define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be +// undefined. See MBEDTLS_PLATFORM_STD_CALLOC for requirements. */ #define MBEDTLS_PLATFORM_EXIT_MACRO +// exit /**< Default exit macro to use, can be undefined */ #define MBEDTLS_PLATFORM_FREE_MACRO free +// /**< Default free macro to use, can be undefined. See MBEDTLS_PLATFORM_STD_FREE for requirements. */ +// #define MBEDTLS_PLATFORM_FPRINTF_MACRO fprintf /**< Default fprintf macro to use, can be undefined +// */ #define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t +// //#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t /**< Default milliseconds time macro to use, +// can be undefined. MBEDTLS_HAVE_TIME must be enabled. It must be signed, and at least 64 bits. If it +// is changed from the default, MBEDTLS_PRINTF_MS_TIME must be updated to match.*/ #define +// MBEDTLS_PLATFORM_NV_SEED_READ_MACRO mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read +// function to use, can be undefined */ #define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO +// mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +// #define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be +// undefined */ #define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf /**< Default setbuf macro to use, can +// be undefined */ /* Note: your snprintf must correctly zero-terminate the buffer! */ -// #define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be undefined */ +// #define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be +// undefined */ /** \def MBEDTLS_PLATFORM_STD_CALLOC * @@ -496,44 +501,47 @@ * It must initialize the allocated buffer memory to zeroes. * The size of the buffer is the product of the two parameters. * The calloc function returns either a null pointer or a pointer to the allocated space. - * If the product is 0, the function may either return NULL or a valid pointer to an array of size 0 which is a valid - * input to the deallocation function. An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null - * pointer. See the description of #MBEDTLS_PLATFORM_MEMORY for more details. The corresponding deallocation function is - * #MBEDTLS_PLATFORM_STD_FREE. + * If the product is 0, the function may either return NULL or a valid pointer to an array of size 0 + * which is a valid input to the deallocation function. An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC + * always fails, returning a null pointer. See the description of #MBEDTLS_PLATFORM_MEMORY for more + * details. The corresponding deallocation function is #MBEDTLS_PLATFORM_STD_FREE. */ // #define MBEDTLS_PLATFORM_STD_CALLOC calloc // #define MBEDTLS_PLATFORM_STD_EXIT exit /**< Default exit to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined +// */ #define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be +// undefined */ #define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be +// undefined */ /** \def MBEDTLS_PLATFORM_STD_FREE * * Default free to use, can be undefined. * NULL is a valid parameter, and the function must do nothing. - * A non-null parameter will always be a pointer previously returned by #MBEDTLS_PLATFORM_STD_CALLOC and not yet freed. - * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. - * See the description of #MBEDTLS_PLATFORM_MEMORY for more details (same principles as for MBEDTLS_PLATFORM_STD_CALLOC - * apply). + * A non-null parameter will always be a pointer previously returned by #MBEDTLS_PLATFORM_STD_CALLOC + * and not yet freed. An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. See the + * description of #MBEDTLS_PLATFORM_MEMORY for more details (same principles as for + * MBEDTLS_PLATFORM_STD_CALLOC apply). */ // #define MBEDTLS_PLATFORM_STD_FREE free -// #define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is -// defined. Don't define if no header is needed. */ #define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file -// to read/write with default implementation */ #define MBEDTLS_PLATFORM_STD_NV_SEED_READ -// mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ #define -// MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, -// can be undefined */ #define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if +// MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */ #define +// MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file to read/write with default +// implementation */ #define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read /**< +// Default nv_seed_read function to use, can be undefined */ #define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE +// mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ // #define MBEDTLS_PLATFORM_STD_SETBUF setbuf /**< Default setbuf to use, can be undefined */ /* Note: your snprintf must correctly zero-terminate the buffer! */ // #define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< Default snprintf to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. MBEDTLS_HAVE_TIME must -// be enabled */ #define MBEDTLS_PLATFORM_TIME_MACRO time /**< Default time macro to use, can be undefined. -// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to -// use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf -// /**< Default vsnprintf macro to use, can be undefined */ #define MBEDTLS_PRINTF_MS_TIME PRId64 /**< Default fmt -// for printf. That's avoid compiler warning if mbedtls_ms_time_t is redefined */ +// #define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. +// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_TIME_MACRO time /**< +// Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ #define +// MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to use, can be undefined. +// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf +// /**< Default vsnprintf macro to use, can be undefined */ #define MBEDTLS_PRINTF_MS_TIME PRId64 +// /**< Default fmt for printf. That's avoid compiler warning if mbedtls_ms_time_t is redefined */ /** \} name SECTION: Platform abstraction layer */ @@ -1983,8 +1991,8 @@ // #define MBEDTLS_MPI_WINDOW_SIZE 2 /**< Maximum window size used. */ /* RSA OPTIONS */ -// #define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 /**< Minimum RSA key size that can be generated in bits -// (Minimum possible value is 128 bits) */ +// #define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 /**< Minimum RSA key size that can be +// generated in bits (Minimum possible value is 128 bits) */ /** \} name SECTION: Builtin drivers */ diff --git a/examples/stm32/nucleo_f439zi/fw_update/Src/mbedtls_v4/mbedtls_config.h b/examples/stm32/nucleo_f439zi/fw_update/Src/mbedtls_v4/mbedtls_config.h index 68149cacf..b34657c71 100644 --- a/examples/stm32/nucleo_f439zi/fw_update/Src/mbedtls_v4/mbedtls_config.h +++ b/examples/stm32/nucleo_f439zi/fw_update/Src/mbedtls_v4/mbedtls_config.h @@ -861,7 +861,8 @@ */ // #define MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH -// #define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default 256 or 384 bits) +// #define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default +// 256 or 384 bits) // */ #define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */ #define // MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /**< 1 day */ @@ -910,8 +911,8 @@ // #define MBEDTLS_SSL_CIPHERSUITES // MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 -// #define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, -// or in number of cookies issued */ +// #define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in +// seconds if HAVE_TIME, or in number of cookies issued */ /** \def MBEDTLS_SSL_DTLS_MAX_BUFFERING * @@ -1198,8 +1199,8 @@ */ // #define MBEDTLS_X509_USE_C -// #define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in bytes including the -// null terminator character ('\0'). */ #define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 /**< Maximum number of -// intermediate CAs in a verification chain. */ +// #define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in +// bytes including the null terminator character ('\0'). */ #define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 +// /**< Maximum number of intermediate CAs in a verification chain. */ /** \} name SECTION: X.509 feature selection */ diff --git a/examples/stm32/nucleo_f439zi/fw_update/Src/mbedtls_v4/mbedtls_platform.c b/examples/stm32/nucleo_f439zi/fw_update/Src/mbedtls_v4/mbedtls_platform.c index 3f97b6244..0b93a26a8 100644 --- a/examples/stm32/nucleo_f439zi/fw_update/Src/mbedtls_v4/mbedtls_platform.c +++ b/examples/stm32/nucleo_f439zi/fw_update/Src/mbedtls_v4/mbedtls_platform.c @@ -4,6 +4,7 @@ #include "main.h" #include "mbedtls/platform.h" #include "mbedtls/platform_time.h" +#include "mbedtls/platform_util.h" #include "stm32f4xx_hal.h" mbedtls_ms_time_t mbedtls_ms_time(void) @@ -13,8 +14,8 @@ mbedtls_ms_time_t mbedtls_ms_time(void) return (mbedtls_ms_time_t)HAL_GetTick(); } -int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *estimate_bits, unsigned char *output, - size_t output_size) +int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *estimate_bits, + unsigned char *output, size_t output_size) { /* We don't implement any flags. */ if (flags != 0) { @@ -28,6 +29,7 @@ int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *e while (bytes_left) { hal_status = HAL_RNG_GenerateRandomNumber(&RNGHandle, &random_data); if (hal_status != HAL_OK) { + mbedtls_platform_zeroize(&random_data, sizeof(random_data)); return PSA_ERROR_INSUFFICIENT_ENTROPY; } @@ -39,5 +41,6 @@ int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *e *estimate_bits = 8 * output_size; + mbedtls_platform_zeroize(&random_data, sizeof(random_data)); return 0; } \ No newline at end of file diff --git a/examples/stm32/nucleo_f439zi/hello_world/Src/main.c b/examples/stm32/nucleo_f439zi/hello_world/Src/main.c index 2006a9524..a073583e5 100644 --- a/examples/stm32/nucleo_f439zi/hello_world/Src/main.c +++ b/examples/stm32/nucleo_f439zi/hello_world/Src/main.c @@ -3,7 +3,7 @@ * @brief Simple "Hello, World!" example of using Libtropic on STM32 Nucleo F439ZI board. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. * * This example project is based on the UART/UART_Printf example from STM32 example library * which was created by the MCD Application Team. @@ -227,7 +227,8 @@ int main(void) } printf("OK\n"); - /* We need to ensure we are not in the Startup Mode, as L3 commands are available only in the Application Firmware. + /* We need to ensure we are not in the Startup Mode, as L3 commands are available only in the + * Application Firmware. */ printf("Sending reboot request..."); ret = lt_reboot(<_handle, TR01_REBOOT); @@ -244,10 +245,11 @@ int main(void) ret = lt_verify_chip_and_start_secure_session(<_handle, LT_EX_SH0_PRIV, LT_EX_SH0_PUB, TR01_PAIRING_KEY_SLOT_INDEX_0); if (LT_OK != ret) { - fprintf(stderr, "\nFailed to start Secure Session with key %d, ret=%s\n", (int)TR01_PAIRING_KEY_SLOT_INDEX_0, - lt_ret_verbose(ret)); + fprintf(stderr, "\nFailed to start Secure Session with key %d, ret=%s\n", + (int)TR01_PAIRING_KEY_SLOT_INDEX_0, lt_ret_verbose(ret)); fprintf(stderr, - "Check if you use correct SH0 keys! Hint: if you use an engineering sample chip, compile with " + "Check if you use correct SH0 keys! Hint: if you use an engineering sample chip, " + "compile with " "-DLT_SH0_KEYS=eng_sample\n"); lt_deinit(<_handle); mbedtls_psa_crypto_free(); @@ -368,8 +370,8 @@ static void SystemClock_Config(void) /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType - = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | + RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; diff --git a/examples/stm32/nucleo_f439zi/hello_world/Src/mbedtls_v4/crypto_config.h b/examples/stm32/nucleo_f439zi/hello_world/Src/mbedtls_v4/crypto_config.h index 303d6d9b4..4939948db 100644 --- a/examples/stm32/nucleo_f439zi/hello_world/Src/mbedtls_v4/crypto_config.h +++ b/examples/stm32/nucleo_f439zi/hello_world/Src/mbedtls_v4/crypto_config.h @@ -356,12 +356,13 @@ * * - mbedtls_calloc = MBEDTLS_PLATFORM_STD_CALLOC. * - * Defining MBEDTLS_PLATFORM_CALLOC_MACRO and #MBEDTLS_PLATFORM_STD_CALLOC at the same time is not possible. - * MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO must both be defined or undefined at the same time. - * #MBEDTLS_PLATFORM_STD_CALLOC and #MBEDTLS_PLATFORM_STD_FREE do not have to be defined at the same time, as, if they - * are used, dynamic setup of these functions is possible. See the tree above to see how are they handled in all cases. - * An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. - * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. + * Defining MBEDTLS_PLATFORM_CALLOC_MACRO and #MBEDTLS_PLATFORM_STD_CALLOC at the same time is not + * possible. MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO must both be defined or + * undefined at the same time. #MBEDTLS_PLATFORM_STD_CALLOC and #MBEDTLS_PLATFORM_STD_FREE do not have + * to be defined at the same time, as, if they are used, dynamic setup of these functions is possible. + * See the tree above to see how are they handled in all cases. An uninitialized + * #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. An uninitialized + * #MBEDTLS_PLATFORM_STD_FREE does not do anything. * * Requires: MBEDTLS_PLATFORM_C * @@ -475,20 +476,24 @@ /* To use the following function macros, MBEDTLS_PLATFORM_C must be enabled. */ /* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */ -// #define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be undefined. See -// MBEDTLS_PLATFORM_STD_CALLOC for requirements. */ #define MBEDTLS_PLATFORM_EXIT_MACRO exit /**< Default -// exit macro to use, can be undefined */ #define MBEDTLS_PLATFORM_FREE_MACRO free /**< Default free macro to -// use, can be undefined. See MBEDTLS_PLATFORM_STD_FREE for requirements. */ #define MBEDTLS_PLATFORM_FPRINTF_MACRO -// fprintf /**< Default fprintf macro to use, can be undefined */ #define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t -// //#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t /**< Default milliseconds time macro to use, can be -// undefined. MBEDTLS_HAVE_TIME must be enabled. It must be signed, and at least 64 bits. If it is changed from the -// default, MBEDTLS_PRINTF_MS_TIME must be updated to match.*/ #define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO -// mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ #define -// MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, -// can be undefined */ #define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be -// undefined */ #define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf /**< Default setbuf macro to use, can be undefined */ +// #define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be +// undefined. See MBEDTLS_PLATFORM_STD_CALLOC for requirements. */ #define MBEDTLS_PLATFORM_EXIT_MACRO +// exit /**< Default exit macro to use, can be undefined */ #define MBEDTLS_PLATFORM_FREE_MACRO free +// /**< Default free macro to use, can be undefined. See MBEDTLS_PLATFORM_STD_FREE for requirements. */ +// #define MBEDTLS_PLATFORM_FPRINTF_MACRO fprintf /**< Default fprintf macro to use, can be undefined +// */ #define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t +// //#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t /**< Default milliseconds time macro to use, +// can be undefined. MBEDTLS_HAVE_TIME must be enabled. It must be signed, and at least 64 bits. If it +// is changed from the default, MBEDTLS_PRINTF_MS_TIME must be updated to match.*/ #define +// MBEDTLS_PLATFORM_NV_SEED_READ_MACRO mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read +// function to use, can be undefined */ #define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO +// mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +// #define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be +// undefined */ #define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf /**< Default setbuf macro to use, can +// be undefined */ /* Note: your snprintf must correctly zero-terminate the buffer! */ -// #define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be undefined */ +// #define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be +// undefined */ /** \def MBEDTLS_PLATFORM_STD_CALLOC * @@ -496,44 +501,47 @@ * It must initialize the allocated buffer memory to zeroes. * The size of the buffer is the product of the two parameters. * The calloc function returns either a null pointer or a pointer to the allocated space. - * If the product is 0, the function may either return NULL or a valid pointer to an array of size 0 which is a valid - * input to the deallocation function. An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null - * pointer. See the description of #MBEDTLS_PLATFORM_MEMORY for more details. The corresponding deallocation function is - * #MBEDTLS_PLATFORM_STD_FREE. + * If the product is 0, the function may either return NULL or a valid pointer to an array of size 0 + * which is a valid input to the deallocation function. An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC + * always fails, returning a null pointer. See the description of #MBEDTLS_PLATFORM_MEMORY for more + * details. The corresponding deallocation function is #MBEDTLS_PLATFORM_STD_FREE. */ // #define MBEDTLS_PLATFORM_STD_CALLOC calloc // #define MBEDTLS_PLATFORM_STD_EXIT exit /**< Default exit to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined +// */ #define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be +// undefined */ #define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be +// undefined */ /** \def MBEDTLS_PLATFORM_STD_FREE * * Default free to use, can be undefined. * NULL is a valid parameter, and the function must do nothing. - * A non-null parameter will always be a pointer previously returned by #MBEDTLS_PLATFORM_STD_CALLOC and not yet freed. - * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. - * See the description of #MBEDTLS_PLATFORM_MEMORY for more details (same principles as for MBEDTLS_PLATFORM_STD_CALLOC - * apply). + * A non-null parameter will always be a pointer previously returned by #MBEDTLS_PLATFORM_STD_CALLOC + * and not yet freed. An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. See the + * description of #MBEDTLS_PLATFORM_MEMORY for more details (same principles as for + * MBEDTLS_PLATFORM_STD_CALLOC apply). */ // #define MBEDTLS_PLATFORM_STD_FREE free -// #define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is -// defined. Don't define if no header is needed. */ #define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file -// to read/write with default implementation */ #define MBEDTLS_PLATFORM_STD_NV_SEED_READ -// mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ #define -// MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, -// can be undefined */ #define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if +// MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */ #define +// MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file to read/write with default +// implementation */ #define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read /**< +// Default nv_seed_read function to use, can be undefined */ #define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE +// mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ // #define MBEDTLS_PLATFORM_STD_SETBUF setbuf /**< Default setbuf to use, can be undefined */ /* Note: your snprintf must correctly zero-terminate the buffer! */ // #define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< Default snprintf to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. MBEDTLS_HAVE_TIME must -// be enabled */ #define MBEDTLS_PLATFORM_TIME_MACRO time /**< Default time macro to use, can be undefined. -// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to -// use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf -// /**< Default vsnprintf macro to use, can be undefined */ #define MBEDTLS_PRINTF_MS_TIME PRId64 /**< Default fmt -// for printf. That's avoid compiler warning if mbedtls_ms_time_t is redefined */ +// #define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. +// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_TIME_MACRO time /**< +// Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ #define +// MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to use, can be undefined. +// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf +// /**< Default vsnprintf macro to use, can be undefined */ #define MBEDTLS_PRINTF_MS_TIME PRId64 +// /**< Default fmt for printf. That's avoid compiler warning if mbedtls_ms_time_t is redefined */ /** \} name SECTION: Platform abstraction layer */ @@ -1983,8 +1991,8 @@ // #define MBEDTLS_MPI_WINDOW_SIZE 2 /**< Maximum window size used. */ /* RSA OPTIONS */ -// #define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 /**< Minimum RSA key size that can be generated in bits -// (Minimum possible value is 128 bits) */ +// #define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 /**< Minimum RSA key size that can be +// generated in bits (Minimum possible value is 128 bits) */ /** \} name SECTION: Builtin drivers */ diff --git a/examples/stm32/nucleo_f439zi/hello_world/Src/mbedtls_v4/mbedtls_config.h b/examples/stm32/nucleo_f439zi/hello_world/Src/mbedtls_v4/mbedtls_config.h index 68149cacf..b34657c71 100644 --- a/examples/stm32/nucleo_f439zi/hello_world/Src/mbedtls_v4/mbedtls_config.h +++ b/examples/stm32/nucleo_f439zi/hello_world/Src/mbedtls_v4/mbedtls_config.h @@ -861,7 +861,8 @@ */ // #define MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH -// #define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default 256 or 384 bits) +// #define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default +// 256 or 384 bits) // */ #define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */ #define // MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /**< 1 day */ @@ -910,8 +911,8 @@ // #define MBEDTLS_SSL_CIPHERSUITES // MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 -// #define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, -// or in number of cookies issued */ +// #define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in +// seconds if HAVE_TIME, or in number of cookies issued */ /** \def MBEDTLS_SSL_DTLS_MAX_BUFFERING * @@ -1198,8 +1199,8 @@ */ // #define MBEDTLS_X509_USE_C -// #define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in bytes including the -// null terminator character ('\0'). */ #define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 /**< Maximum number of -// intermediate CAs in a verification chain. */ +// #define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in +// bytes including the null terminator character ('\0'). */ #define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 +// /**< Maximum number of intermediate CAs in a verification chain. */ /** \} name SECTION: X.509 feature selection */ diff --git a/examples/stm32/nucleo_f439zi/hello_world/Src/mbedtls_v4/mbedtls_platform.c b/examples/stm32/nucleo_f439zi/hello_world/Src/mbedtls_v4/mbedtls_platform.c index 3f97b6244..0b93a26a8 100644 --- a/examples/stm32/nucleo_f439zi/hello_world/Src/mbedtls_v4/mbedtls_platform.c +++ b/examples/stm32/nucleo_f439zi/hello_world/Src/mbedtls_v4/mbedtls_platform.c @@ -4,6 +4,7 @@ #include "main.h" #include "mbedtls/platform.h" #include "mbedtls/platform_time.h" +#include "mbedtls/platform_util.h" #include "stm32f4xx_hal.h" mbedtls_ms_time_t mbedtls_ms_time(void) @@ -13,8 +14,8 @@ mbedtls_ms_time_t mbedtls_ms_time(void) return (mbedtls_ms_time_t)HAL_GetTick(); } -int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *estimate_bits, unsigned char *output, - size_t output_size) +int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *estimate_bits, + unsigned char *output, size_t output_size) { /* We don't implement any flags. */ if (flags != 0) { @@ -28,6 +29,7 @@ int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *e while (bytes_left) { hal_status = HAL_RNG_GenerateRandomNumber(&RNGHandle, &random_data); if (hal_status != HAL_OK) { + mbedtls_platform_zeroize(&random_data, sizeof(random_data)); return PSA_ERROR_INSUFFICIENT_ENTROPY; } @@ -39,5 +41,6 @@ int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *e *estimate_bits = 8 * output_size; + mbedtls_platform_zeroize(&random_data, sizeof(random_data)); return 0; } \ No newline at end of file diff --git a/examples/stm32/nucleo_f439zi/identify_chip/Src/main.c b/examples/stm32/nucleo_f439zi/identify_chip/Src/main.c index 85fc2012d..ae1c3de9e 100644 --- a/examples/stm32/nucleo_f439zi/identify_chip/Src/main.c +++ b/examples/stm32/nucleo_f439zi/identify_chip/Src/main.c @@ -1,10 +1,10 @@ /** * @file main.c - * @brief Example of reading information about the TROPIC01 chip and its firmware using Libtropic on STM32 Nucleo F439ZI - * board. + * @brief Example of reading information about the TROPIC01 chip and its firmware using Libtropic on + * STM32 Nucleo F439ZI board. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. * * This example project is based on the UART/UART_Printf example from STM32 example library * which was created by the MCD Application Team. @@ -224,8 +224,9 @@ int main(void) } printf("OK\n"); - /* First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** be in the Start-up - Mode. If there are valid firmwares, TROPIC01 will begin to execute them automatically on boot. */ + /* First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** + be in the Start-up Mode. If there are valid firmwares, TROPIC01 will begin to execute them + automatically on boot. */ printf("Sending reboot request..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { @@ -246,8 +247,8 @@ int main(void) mbedtls_psa_crypto_free(); return -1; } - printf(" RISC-V FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", fw_ver[3], fw_ver[2], fw_ver[1], - fw_ver[0]); + printf(" RISC-V FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", fw_ver[3], + fw_ver[2], fw_ver[1], fw_ver[0]); ret = lt_get_info_spect_fw_ver(<_handle, fw_ver); if (ret != LT_OK) { @@ -256,10 +257,11 @@ int main(void) mbedtls_psa_crypto_free(); return -1; } - printf(" SPECT FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", fw_ver[3], fw_ver[2], fw_ver[1], - fw_ver[0]); + printf(" SPECT FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", fw_ver[3], + fw_ver[2], fw_ver[1], fw_ver[0]); - /* We need to do the maintenance reboot to check bootloader version and FW bank headers in the Startup Mode. */ + /* We need to do the maintenance reboot to check bootloader version and FW bank headers in the + * Startup Mode. */ printf("Sending maintenance reboot request..."); ret = lt_reboot(<_handle, TR01_MAINTENANCE_REBOOT); if (ret != LT_OK) { @@ -272,7 +274,8 @@ int main(void) printf("Reading data from chip...\n"); - /* When TROPIC01 is in Start-up Mode, we can get RISC-V bootloader version the same way as we got RISC-V FW version. + /* When TROPIC01 is in Start-up Mode, we can get RISC-V bootloader version the same way as we got + * RISC-V FW version. */ ret = lt_get_info_riscv_fw_ver(<_handle, fw_ver); if (ret != LT_OK) { @@ -281,8 +284,8 @@ int main(void) mbedtls_psa_crypto_free(); return -1; } - printf(" RISC-V bootloader version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", fw_ver[3] & 0x7f, fw_ver[2], - fw_ver[1], fw_ver[0]); + printf(" RISC-V bootloader version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", + fw_ver[3] & 0x7f, fw_ver[2], fw_ver[1], fw_ver[0]); printf("Firmware bank headers:\n"); ret = lt_print_fw_header(<_handle, TR01_FW_BANK_FW1, printf); @@ -435,8 +438,8 @@ static void SystemClock_Config(void) /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType - = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | + RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; diff --git a/examples/stm32/nucleo_f439zi/identify_chip/Src/mbedtls_v4/crypto_config.h b/examples/stm32/nucleo_f439zi/identify_chip/Src/mbedtls_v4/crypto_config.h index 303d6d9b4..4939948db 100644 --- a/examples/stm32/nucleo_f439zi/identify_chip/Src/mbedtls_v4/crypto_config.h +++ b/examples/stm32/nucleo_f439zi/identify_chip/Src/mbedtls_v4/crypto_config.h @@ -356,12 +356,13 @@ * * - mbedtls_calloc = MBEDTLS_PLATFORM_STD_CALLOC. * - * Defining MBEDTLS_PLATFORM_CALLOC_MACRO and #MBEDTLS_PLATFORM_STD_CALLOC at the same time is not possible. - * MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO must both be defined or undefined at the same time. - * #MBEDTLS_PLATFORM_STD_CALLOC and #MBEDTLS_PLATFORM_STD_FREE do not have to be defined at the same time, as, if they - * are used, dynamic setup of these functions is possible. See the tree above to see how are they handled in all cases. - * An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. - * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. + * Defining MBEDTLS_PLATFORM_CALLOC_MACRO and #MBEDTLS_PLATFORM_STD_CALLOC at the same time is not + * possible. MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO must both be defined or + * undefined at the same time. #MBEDTLS_PLATFORM_STD_CALLOC and #MBEDTLS_PLATFORM_STD_FREE do not have + * to be defined at the same time, as, if they are used, dynamic setup of these functions is possible. + * See the tree above to see how are they handled in all cases. An uninitialized + * #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. An uninitialized + * #MBEDTLS_PLATFORM_STD_FREE does not do anything. * * Requires: MBEDTLS_PLATFORM_C * @@ -475,20 +476,24 @@ /* To use the following function macros, MBEDTLS_PLATFORM_C must be enabled. */ /* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */ -// #define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be undefined. See -// MBEDTLS_PLATFORM_STD_CALLOC for requirements. */ #define MBEDTLS_PLATFORM_EXIT_MACRO exit /**< Default -// exit macro to use, can be undefined */ #define MBEDTLS_PLATFORM_FREE_MACRO free /**< Default free macro to -// use, can be undefined. See MBEDTLS_PLATFORM_STD_FREE for requirements. */ #define MBEDTLS_PLATFORM_FPRINTF_MACRO -// fprintf /**< Default fprintf macro to use, can be undefined */ #define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t -// //#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t /**< Default milliseconds time macro to use, can be -// undefined. MBEDTLS_HAVE_TIME must be enabled. It must be signed, and at least 64 bits. If it is changed from the -// default, MBEDTLS_PRINTF_MS_TIME must be updated to match.*/ #define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO -// mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ #define -// MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, -// can be undefined */ #define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be -// undefined */ #define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf /**< Default setbuf macro to use, can be undefined */ +// #define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be +// undefined. See MBEDTLS_PLATFORM_STD_CALLOC for requirements. */ #define MBEDTLS_PLATFORM_EXIT_MACRO +// exit /**< Default exit macro to use, can be undefined */ #define MBEDTLS_PLATFORM_FREE_MACRO free +// /**< Default free macro to use, can be undefined. See MBEDTLS_PLATFORM_STD_FREE for requirements. */ +// #define MBEDTLS_PLATFORM_FPRINTF_MACRO fprintf /**< Default fprintf macro to use, can be undefined +// */ #define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t +// //#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t /**< Default milliseconds time macro to use, +// can be undefined. MBEDTLS_HAVE_TIME must be enabled. It must be signed, and at least 64 bits. If it +// is changed from the default, MBEDTLS_PRINTF_MS_TIME must be updated to match.*/ #define +// MBEDTLS_PLATFORM_NV_SEED_READ_MACRO mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read +// function to use, can be undefined */ #define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO +// mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +// #define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be +// undefined */ #define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf /**< Default setbuf macro to use, can +// be undefined */ /* Note: your snprintf must correctly zero-terminate the buffer! */ -// #define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be undefined */ +// #define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be +// undefined */ /** \def MBEDTLS_PLATFORM_STD_CALLOC * @@ -496,44 +501,47 @@ * It must initialize the allocated buffer memory to zeroes. * The size of the buffer is the product of the two parameters. * The calloc function returns either a null pointer or a pointer to the allocated space. - * If the product is 0, the function may either return NULL or a valid pointer to an array of size 0 which is a valid - * input to the deallocation function. An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null - * pointer. See the description of #MBEDTLS_PLATFORM_MEMORY for more details. The corresponding deallocation function is - * #MBEDTLS_PLATFORM_STD_FREE. + * If the product is 0, the function may either return NULL or a valid pointer to an array of size 0 + * which is a valid input to the deallocation function. An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC + * always fails, returning a null pointer. See the description of #MBEDTLS_PLATFORM_MEMORY for more + * details. The corresponding deallocation function is #MBEDTLS_PLATFORM_STD_FREE. */ // #define MBEDTLS_PLATFORM_STD_CALLOC calloc // #define MBEDTLS_PLATFORM_STD_EXIT exit /**< Default exit to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined +// */ #define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be +// undefined */ #define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be +// undefined */ /** \def MBEDTLS_PLATFORM_STD_FREE * * Default free to use, can be undefined. * NULL is a valid parameter, and the function must do nothing. - * A non-null parameter will always be a pointer previously returned by #MBEDTLS_PLATFORM_STD_CALLOC and not yet freed. - * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. - * See the description of #MBEDTLS_PLATFORM_MEMORY for more details (same principles as for MBEDTLS_PLATFORM_STD_CALLOC - * apply). + * A non-null parameter will always be a pointer previously returned by #MBEDTLS_PLATFORM_STD_CALLOC + * and not yet freed. An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. See the + * description of #MBEDTLS_PLATFORM_MEMORY for more details (same principles as for + * MBEDTLS_PLATFORM_STD_CALLOC apply). */ // #define MBEDTLS_PLATFORM_STD_FREE free -// #define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is -// defined. Don't define if no header is needed. */ #define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file -// to read/write with default implementation */ #define MBEDTLS_PLATFORM_STD_NV_SEED_READ -// mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ #define -// MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, -// can be undefined */ #define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if +// MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */ #define +// MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file to read/write with default +// implementation */ #define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read /**< +// Default nv_seed_read function to use, can be undefined */ #define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE +// mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ // #define MBEDTLS_PLATFORM_STD_SETBUF setbuf /**< Default setbuf to use, can be undefined */ /* Note: your snprintf must correctly zero-terminate the buffer! */ // #define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< Default snprintf to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. MBEDTLS_HAVE_TIME must -// be enabled */ #define MBEDTLS_PLATFORM_TIME_MACRO time /**< Default time macro to use, can be undefined. -// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to -// use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf -// /**< Default vsnprintf macro to use, can be undefined */ #define MBEDTLS_PRINTF_MS_TIME PRId64 /**< Default fmt -// for printf. That's avoid compiler warning if mbedtls_ms_time_t is redefined */ +// #define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. +// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_TIME_MACRO time /**< +// Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ #define +// MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to use, can be undefined. +// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf +// /**< Default vsnprintf macro to use, can be undefined */ #define MBEDTLS_PRINTF_MS_TIME PRId64 +// /**< Default fmt for printf. That's avoid compiler warning if mbedtls_ms_time_t is redefined */ /** \} name SECTION: Platform abstraction layer */ @@ -1983,8 +1991,8 @@ // #define MBEDTLS_MPI_WINDOW_SIZE 2 /**< Maximum window size used. */ /* RSA OPTIONS */ -// #define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 /**< Minimum RSA key size that can be generated in bits -// (Minimum possible value is 128 bits) */ +// #define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 /**< Minimum RSA key size that can be +// generated in bits (Minimum possible value is 128 bits) */ /** \} name SECTION: Builtin drivers */ diff --git a/examples/stm32/nucleo_f439zi/identify_chip/Src/mbedtls_v4/mbedtls_config.h b/examples/stm32/nucleo_f439zi/identify_chip/Src/mbedtls_v4/mbedtls_config.h index 68149cacf..b34657c71 100644 --- a/examples/stm32/nucleo_f439zi/identify_chip/Src/mbedtls_v4/mbedtls_config.h +++ b/examples/stm32/nucleo_f439zi/identify_chip/Src/mbedtls_v4/mbedtls_config.h @@ -861,7 +861,8 @@ */ // #define MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH -// #define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default 256 or 384 bits) +// #define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default +// 256 or 384 bits) // */ #define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */ #define // MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /**< 1 day */ @@ -910,8 +911,8 @@ // #define MBEDTLS_SSL_CIPHERSUITES // MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 -// #define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, -// or in number of cookies issued */ +// #define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in +// seconds if HAVE_TIME, or in number of cookies issued */ /** \def MBEDTLS_SSL_DTLS_MAX_BUFFERING * @@ -1198,8 +1199,8 @@ */ // #define MBEDTLS_X509_USE_C -// #define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in bytes including the -// null terminator character ('\0'). */ #define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 /**< Maximum number of -// intermediate CAs in a verification chain. */ +// #define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in +// bytes including the null terminator character ('\0'). */ #define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 +// /**< Maximum number of intermediate CAs in a verification chain. */ /** \} name SECTION: X.509 feature selection */ diff --git a/examples/stm32/nucleo_f439zi/identify_chip/Src/mbedtls_v4/mbedtls_platform.c b/examples/stm32/nucleo_f439zi/identify_chip/Src/mbedtls_v4/mbedtls_platform.c index 3f97b6244..0b93a26a8 100644 --- a/examples/stm32/nucleo_f439zi/identify_chip/Src/mbedtls_v4/mbedtls_platform.c +++ b/examples/stm32/nucleo_f439zi/identify_chip/Src/mbedtls_v4/mbedtls_platform.c @@ -4,6 +4,7 @@ #include "main.h" #include "mbedtls/platform.h" #include "mbedtls/platform_time.h" +#include "mbedtls/platform_util.h" #include "stm32f4xx_hal.h" mbedtls_ms_time_t mbedtls_ms_time(void) @@ -13,8 +14,8 @@ mbedtls_ms_time_t mbedtls_ms_time(void) return (mbedtls_ms_time_t)HAL_GetTick(); } -int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *estimate_bits, unsigned char *output, - size_t output_size) +int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *estimate_bits, + unsigned char *output, size_t output_size) { /* We don't implement any flags. */ if (flags != 0) { @@ -28,6 +29,7 @@ int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *e while (bytes_left) { hal_status = HAL_RNG_GenerateRandomNumber(&RNGHandle, &random_data); if (hal_status != HAL_OK) { + mbedtls_platform_zeroize(&random_data, sizeof(random_data)); return PSA_ERROR_INSUFFICIENT_ENTROPY; } @@ -39,5 +41,6 @@ int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *e *estimate_bits = 8 * output_size; + mbedtls_platform_zeroize(&random_data, sizeof(random_data)); return 0; } \ No newline at end of file diff --git a/examples/stm32/nucleo_l432kc/fw_update/Src/main.c b/examples/stm32/nucleo_l432kc/fw_update/Src/main.c index 91f582860..63de4fb5e 100644 --- a/examples/stm32/nucleo_l432kc/fw_update/Src/main.c +++ b/examples/stm32/nucleo_l432kc/fw_update/Src/main.c @@ -1,13 +1,13 @@ /** * @file main.c - * @brief Example showing how to perform an update of the TROPIC01 firmware using Libtropic on STM32 Nucleo L432KC - * board. + * @brief Example showing how to perform an update of the TROPIC01 firmware using Libtropic on STM32 + * Nucleo L432KC board. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. * - * This example project is based on the SPI/SPI_FullDuplex_ComPolling example from STM32 example library - * which was created by the MCD Application Team. + * This example project is based on the SPI/SPI_FullDuplex_ComPolling example from STM32 example + * library which was created by the MCD Application Team. */ /* Includes ------------------------------------------------------------------*/ @@ -284,8 +284,9 @@ int main(void) } printf("OK\n"); - /* First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** be in the Start-up - Mode. If there are valid firmwares, TROPIC01 will begin to execute them automatically on boot. */ + /* First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** + be in the Start-up Mode. If there are valid firmwares, TROPIC01 will begin to execute them + automatically on boot. */ printf("Rebooting TROPIC01..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { @@ -465,8 +466,8 @@ void SystemClock_Config(void) /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType - = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | + RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; diff --git a/examples/stm32/nucleo_l432kc/fw_update/Src/mbedtls_v4/crypto_config.h b/examples/stm32/nucleo_l432kc/fw_update/Src/mbedtls_v4/crypto_config.h index 303d6d9b4..4939948db 100644 --- a/examples/stm32/nucleo_l432kc/fw_update/Src/mbedtls_v4/crypto_config.h +++ b/examples/stm32/nucleo_l432kc/fw_update/Src/mbedtls_v4/crypto_config.h @@ -356,12 +356,13 @@ * * - mbedtls_calloc = MBEDTLS_PLATFORM_STD_CALLOC. * - * Defining MBEDTLS_PLATFORM_CALLOC_MACRO and #MBEDTLS_PLATFORM_STD_CALLOC at the same time is not possible. - * MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO must both be defined or undefined at the same time. - * #MBEDTLS_PLATFORM_STD_CALLOC and #MBEDTLS_PLATFORM_STD_FREE do not have to be defined at the same time, as, if they - * are used, dynamic setup of these functions is possible. See the tree above to see how are they handled in all cases. - * An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. - * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. + * Defining MBEDTLS_PLATFORM_CALLOC_MACRO and #MBEDTLS_PLATFORM_STD_CALLOC at the same time is not + * possible. MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO must both be defined or + * undefined at the same time. #MBEDTLS_PLATFORM_STD_CALLOC and #MBEDTLS_PLATFORM_STD_FREE do not have + * to be defined at the same time, as, if they are used, dynamic setup of these functions is possible. + * See the tree above to see how are they handled in all cases. An uninitialized + * #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. An uninitialized + * #MBEDTLS_PLATFORM_STD_FREE does not do anything. * * Requires: MBEDTLS_PLATFORM_C * @@ -475,20 +476,24 @@ /* To use the following function macros, MBEDTLS_PLATFORM_C must be enabled. */ /* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */ -// #define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be undefined. See -// MBEDTLS_PLATFORM_STD_CALLOC for requirements. */ #define MBEDTLS_PLATFORM_EXIT_MACRO exit /**< Default -// exit macro to use, can be undefined */ #define MBEDTLS_PLATFORM_FREE_MACRO free /**< Default free macro to -// use, can be undefined. See MBEDTLS_PLATFORM_STD_FREE for requirements. */ #define MBEDTLS_PLATFORM_FPRINTF_MACRO -// fprintf /**< Default fprintf macro to use, can be undefined */ #define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t -// //#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t /**< Default milliseconds time macro to use, can be -// undefined. MBEDTLS_HAVE_TIME must be enabled. It must be signed, and at least 64 bits. If it is changed from the -// default, MBEDTLS_PRINTF_MS_TIME must be updated to match.*/ #define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO -// mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ #define -// MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, -// can be undefined */ #define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be -// undefined */ #define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf /**< Default setbuf macro to use, can be undefined */ +// #define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be +// undefined. See MBEDTLS_PLATFORM_STD_CALLOC for requirements. */ #define MBEDTLS_PLATFORM_EXIT_MACRO +// exit /**< Default exit macro to use, can be undefined */ #define MBEDTLS_PLATFORM_FREE_MACRO free +// /**< Default free macro to use, can be undefined. See MBEDTLS_PLATFORM_STD_FREE for requirements. */ +// #define MBEDTLS_PLATFORM_FPRINTF_MACRO fprintf /**< Default fprintf macro to use, can be undefined +// */ #define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t +// //#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t /**< Default milliseconds time macro to use, +// can be undefined. MBEDTLS_HAVE_TIME must be enabled. It must be signed, and at least 64 bits. If it +// is changed from the default, MBEDTLS_PRINTF_MS_TIME must be updated to match.*/ #define +// MBEDTLS_PLATFORM_NV_SEED_READ_MACRO mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read +// function to use, can be undefined */ #define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO +// mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +// #define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be +// undefined */ #define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf /**< Default setbuf macro to use, can +// be undefined */ /* Note: your snprintf must correctly zero-terminate the buffer! */ -// #define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be undefined */ +// #define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be +// undefined */ /** \def MBEDTLS_PLATFORM_STD_CALLOC * @@ -496,44 +501,47 @@ * It must initialize the allocated buffer memory to zeroes. * The size of the buffer is the product of the two parameters. * The calloc function returns either a null pointer or a pointer to the allocated space. - * If the product is 0, the function may either return NULL or a valid pointer to an array of size 0 which is a valid - * input to the deallocation function. An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null - * pointer. See the description of #MBEDTLS_PLATFORM_MEMORY for more details. The corresponding deallocation function is - * #MBEDTLS_PLATFORM_STD_FREE. + * If the product is 0, the function may either return NULL or a valid pointer to an array of size 0 + * which is a valid input to the deallocation function. An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC + * always fails, returning a null pointer. See the description of #MBEDTLS_PLATFORM_MEMORY for more + * details. The corresponding deallocation function is #MBEDTLS_PLATFORM_STD_FREE. */ // #define MBEDTLS_PLATFORM_STD_CALLOC calloc // #define MBEDTLS_PLATFORM_STD_EXIT exit /**< Default exit to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined +// */ #define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be +// undefined */ #define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be +// undefined */ /** \def MBEDTLS_PLATFORM_STD_FREE * * Default free to use, can be undefined. * NULL is a valid parameter, and the function must do nothing. - * A non-null parameter will always be a pointer previously returned by #MBEDTLS_PLATFORM_STD_CALLOC and not yet freed. - * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. - * See the description of #MBEDTLS_PLATFORM_MEMORY for more details (same principles as for MBEDTLS_PLATFORM_STD_CALLOC - * apply). + * A non-null parameter will always be a pointer previously returned by #MBEDTLS_PLATFORM_STD_CALLOC + * and not yet freed. An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. See the + * description of #MBEDTLS_PLATFORM_MEMORY for more details (same principles as for + * MBEDTLS_PLATFORM_STD_CALLOC apply). */ // #define MBEDTLS_PLATFORM_STD_FREE free -// #define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is -// defined. Don't define if no header is needed. */ #define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file -// to read/write with default implementation */ #define MBEDTLS_PLATFORM_STD_NV_SEED_READ -// mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ #define -// MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, -// can be undefined */ #define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if +// MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */ #define +// MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file to read/write with default +// implementation */ #define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read /**< +// Default nv_seed_read function to use, can be undefined */ #define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE +// mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ // #define MBEDTLS_PLATFORM_STD_SETBUF setbuf /**< Default setbuf to use, can be undefined */ /* Note: your snprintf must correctly zero-terminate the buffer! */ // #define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< Default snprintf to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. MBEDTLS_HAVE_TIME must -// be enabled */ #define MBEDTLS_PLATFORM_TIME_MACRO time /**< Default time macro to use, can be undefined. -// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to -// use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf -// /**< Default vsnprintf macro to use, can be undefined */ #define MBEDTLS_PRINTF_MS_TIME PRId64 /**< Default fmt -// for printf. That's avoid compiler warning if mbedtls_ms_time_t is redefined */ +// #define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. +// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_TIME_MACRO time /**< +// Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ #define +// MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to use, can be undefined. +// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf +// /**< Default vsnprintf macro to use, can be undefined */ #define MBEDTLS_PRINTF_MS_TIME PRId64 +// /**< Default fmt for printf. That's avoid compiler warning if mbedtls_ms_time_t is redefined */ /** \} name SECTION: Platform abstraction layer */ @@ -1983,8 +1991,8 @@ // #define MBEDTLS_MPI_WINDOW_SIZE 2 /**< Maximum window size used. */ /* RSA OPTIONS */ -// #define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 /**< Minimum RSA key size that can be generated in bits -// (Minimum possible value is 128 bits) */ +// #define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 /**< Minimum RSA key size that can be +// generated in bits (Minimum possible value is 128 bits) */ /** \} name SECTION: Builtin drivers */ diff --git a/examples/stm32/nucleo_l432kc/fw_update/Src/mbedtls_v4/mbedtls_config.h b/examples/stm32/nucleo_l432kc/fw_update/Src/mbedtls_v4/mbedtls_config.h index 68149cacf..b34657c71 100644 --- a/examples/stm32/nucleo_l432kc/fw_update/Src/mbedtls_v4/mbedtls_config.h +++ b/examples/stm32/nucleo_l432kc/fw_update/Src/mbedtls_v4/mbedtls_config.h @@ -861,7 +861,8 @@ */ // #define MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH -// #define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default 256 or 384 bits) +// #define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default +// 256 or 384 bits) // */ #define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */ #define // MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /**< 1 day */ @@ -910,8 +911,8 @@ // #define MBEDTLS_SSL_CIPHERSUITES // MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 -// #define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, -// or in number of cookies issued */ +// #define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in +// seconds if HAVE_TIME, or in number of cookies issued */ /** \def MBEDTLS_SSL_DTLS_MAX_BUFFERING * @@ -1198,8 +1199,8 @@ */ // #define MBEDTLS_X509_USE_C -// #define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in bytes including the -// null terminator character ('\0'). */ #define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 /**< Maximum number of -// intermediate CAs in a verification chain. */ +// #define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in +// bytes including the null terminator character ('\0'). */ #define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 +// /**< Maximum number of intermediate CAs in a verification chain. */ /** \} name SECTION: X.509 feature selection */ diff --git a/examples/stm32/nucleo_l432kc/fw_update/Src/mbedtls_v4/mbedtls_platform.c b/examples/stm32/nucleo_l432kc/fw_update/Src/mbedtls_v4/mbedtls_platform.c index 7383d28d3..13d29a2d0 100644 --- a/examples/stm32/nucleo_l432kc/fw_update/Src/mbedtls_v4/mbedtls_platform.c +++ b/examples/stm32/nucleo_l432kc/fw_update/Src/mbedtls_v4/mbedtls_platform.c @@ -4,6 +4,7 @@ #include "main.h" #include "mbedtls/platform.h" #include "mbedtls/platform_time.h" +#include "mbedtls/platform_util.h" #include "stm32l4xx_hal.h" mbedtls_ms_time_t mbedtls_ms_time(void) @@ -13,8 +14,8 @@ mbedtls_ms_time_t mbedtls_ms_time(void) return (mbedtls_ms_time_t)HAL_GetTick(); } -int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *estimate_bits, unsigned char *output, - size_t output_size) +int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *estimate_bits, + unsigned char *output, size_t output_size) { // We don't implement any flags. if (flags != 0) { @@ -28,6 +29,7 @@ int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *e while (bytes_left) { hal_status = HAL_RNG_GenerateRandomNumber(&RNGHandle, &random_data); if (hal_status != HAL_OK) { + mbedtls_platform_zeroize(&random_data, sizeof(random_data)); return PSA_ERROR_INSUFFICIENT_ENTROPY; } @@ -39,5 +41,6 @@ int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *e *estimate_bits = 8 * output_size; + mbedtls_platform_zeroize(&random_data, sizeof(random_data)); return 0; } \ No newline at end of file diff --git a/examples/stm32/nucleo_l432kc/fw_update/Src/system_stm32l4xx.c b/examples/stm32/nucleo_l432kc/fw_update/Src/system_stm32l4xx.c index 8633cb04f..e3b652429 100644 --- a/examples/stm32/nucleo_l432kc/fw_update/Src/system_stm32l4xx.c +++ b/examples/stm32/nucleo_l432kc/fw_update/Src/system_stm32l4xx.c @@ -153,8 +153,8 @@ uint32_t SystemCoreClock = 4000000; const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; -const uint32_t MSIRangeTable[12] - = {100000, 200000, 400000, 800000, 1000000, 2000000, 4000000, 8000000, 16000000, 24000000, 32000000, 48000000}; +const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, + 4000000, 8000000, 16000000, 24000000, 32000000, 48000000}; /** * @} */ diff --git a/examples/stm32/nucleo_l432kc/hello_world/Src/main.c b/examples/stm32/nucleo_l432kc/hello_world/Src/main.c index 9f40d39c7..e5159d6b3 100644 --- a/examples/stm32/nucleo_l432kc/hello_world/Src/main.c +++ b/examples/stm32/nucleo_l432kc/hello_world/Src/main.c @@ -3,10 +3,10 @@ * @brief Simple "Hello, World!" example of using Libtropic on STM32 Nucleo L432KC board. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. * - * This example project is based on the SPI/SPI_FullDuplex_ComPolling example from STM32 example library - * which was created by the MCD Application Team. + * This example project is based on the SPI/SPI_FullDuplex_ComPolling example from STM32 example + * library which was created by the MCD Application Team. */ /* Includes ------------------------------------------------------------------*/ @@ -255,7 +255,8 @@ int main(void) } printf("OK\n"); - /* We need to ensure we are not in the Startup Mode, as L3 commands are available only in the Application Firmware. + /* We need to ensure we are not in the Startup Mode, as L3 commands are available only in the + * Application Firmware. */ printf("Sending reboot request..."); ret = lt_reboot(<_handle, TR01_REBOOT); @@ -272,10 +273,11 @@ int main(void) ret = lt_verify_chip_and_start_secure_session(<_handle, LT_EX_SH0_PRIV, LT_EX_SH0_PUB, TR01_PAIRING_KEY_SLOT_INDEX_0); if (LT_OK != ret) { - fprintf(stderr, "\nFailed to start Secure Session with key %d, ret=%s\n", (int)TR01_PAIRING_KEY_SLOT_INDEX_0, - lt_ret_verbose(ret)); + fprintf(stderr, "\nFailed to start Secure Session with key %d, ret=%s\n", + (int)TR01_PAIRING_KEY_SLOT_INDEX_0, lt_ret_verbose(ret)); fprintf(stderr, - "Check if you use correct SH0 keys! Hint: if you use an engineering sample chip, compile with " + "Check if you use correct SH0 keys! Hint: if you use an engineering sample chip, " + "compile with " "-DLT_SH0_KEYS=eng_sample\n"); lt_deinit(<_handle); mbedtls_psa_crypto_free(); @@ -397,8 +399,8 @@ void SystemClock_Config(void) /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType - = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | + RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; diff --git a/examples/stm32/nucleo_l432kc/hello_world/Src/mbedtls_v4/crypto_config.h b/examples/stm32/nucleo_l432kc/hello_world/Src/mbedtls_v4/crypto_config.h index 303d6d9b4..4939948db 100644 --- a/examples/stm32/nucleo_l432kc/hello_world/Src/mbedtls_v4/crypto_config.h +++ b/examples/stm32/nucleo_l432kc/hello_world/Src/mbedtls_v4/crypto_config.h @@ -356,12 +356,13 @@ * * - mbedtls_calloc = MBEDTLS_PLATFORM_STD_CALLOC. * - * Defining MBEDTLS_PLATFORM_CALLOC_MACRO and #MBEDTLS_PLATFORM_STD_CALLOC at the same time is not possible. - * MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO must both be defined or undefined at the same time. - * #MBEDTLS_PLATFORM_STD_CALLOC and #MBEDTLS_PLATFORM_STD_FREE do not have to be defined at the same time, as, if they - * are used, dynamic setup of these functions is possible. See the tree above to see how are they handled in all cases. - * An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. - * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. + * Defining MBEDTLS_PLATFORM_CALLOC_MACRO and #MBEDTLS_PLATFORM_STD_CALLOC at the same time is not + * possible. MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO must both be defined or + * undefined at the same time. #MBEDTLS_PLATFORM_STD_CALLOC and #MBEDTLS_PLATFORM_STD_FREE do not have + * to be defined at the same time, as, if they are used, dynamic setup of these functions is possible. + * See the tree above to see how are they handled in all cases. An uninitialized + * #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. An uninitialized + * #MBEDTLS_PLATFORM_STD_FREE does not do anything. * * Requires: MBEDTLS_PLATFORM_C * @@ -475,20 +476,24 @@ /* To use the following function macros, MBEDTLS_PLATFORM_C must be enabled. */ /* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */ -// #define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be undefined. See -// MBEDTLS_PLATFORM_STD_CALLOC for requirements. */ #define MBEDTLS_PLATFORM_EXIT_MACRO exit /**< Default -// exit macro to use, can be undefined */ #define MBEDTLS_PLATFORM_FREE_MACRO free /**< Default free macro to -// use, can be undefined. See MBEDTLS_PLATFORM_STD_FREE for requirements. */ #define MBEDTLS_PLATFORM_FPRINTF_MACRO -// fprintf /**< Default fprintf macro to use, can be undefined */ #define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t -// //#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t /**< Default milliseconds time macro to use, can be -// undefined. MBEDTLS_HAVE_TIME must be enabled. It must be signed, and at least 64 bits. If it is changed from the -// default, MBEDTLS_PRINTF_MS_TIME must be updated to match.*/ #define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO -// mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ #define -// MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, -// can be undefined */ #define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be -// undefined */ #define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf /**< Default setbuf macro to use, can be undefined */ +// #define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be +// undefined. See MBEDTLS_PLATFORM_STD_CALLOC for requirements. */ #define MBEDTLS_PLATFORM_EXIT_MACRO +// exit /**< Default exit macro to use, can be undefined */ #define MBEDTLS_PLATFORM_FREE_MACRO free +// /**< Default free macro to use, can be undefined. See MBEDTLS_PLATFORM_STD_FREE for requirements. */ +// #define MBEDTLS_PLATFORM_FPRINTF_MACRO fprintf /**< Default fprintf macro to use, can be undefined +// */ #define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t +// //#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t /**< Default milliseconds time macro to use, +// can be undefined. MBEDTLS_HAVE_TIME must be enabled. It must be signed, and at least 64 bits. If it +// is changed from the default, MBEDTLS_PRINTF_MS_TIME must be updated to match.*/ #define +// MBEDTLS_PLATFORM_NV_SEED_READ_MACRO mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read +// function to use, can be undefined */ #define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO +// mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +// #define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be +// undefined */ #define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf /**< Default setbuf macro to use, can +// be undefined */ /* Note: your snprintf must correctly zero-terminate the buffer! */ -// #define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be undefined */ +// #define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be +// undefined */ /** \def MBEDTLS_PLATFORM_STD_CALLOC * @@ -496,44 +501,47 @@ * It must initialize the allocated buffer memory to zeroes. * The size of the buffer is the product of the two parameters. * The calloc function returns either a null pointer or a pointer to the allocated space. - * If the product is 0, the function may either return NULL or a valid pointer to an array of size 0 which is a valid - * input to the deallocation function. An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null - * pointer. See the description of #MBEDTLS_PLATFORM_MEMORY for more details. The corresponding deallocation function is - * #MBEDTLS_PLATFORM_STD_FREE. + * If the product is 0, the function may either return NULL or a valid pointer to an array of size 0 + * which is a valid input to the deallocation function. An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC + * always fails, returning a null pointer. See the description of #MBEDTLS_PLATFORM_MEMORY for more + * details. The corresponding deallocation function is #MBEDTLS_PLATFORM_STD_FREE. */ // #define MBEDTLS_PLATFORM_STD_CALLOC calloc // #define MBEDTLS_PLATFORM_STD_EXIT exit /**< Default exit to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined +// */ #define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be +// undefined */ #define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be +// undefined */ /** \def MBEDTLS_PLATFORM_STD_FREE * * Default free to use, can be undefined. * NULL is a valid parameter, and the function must do nothing. - * A non-null parameter will always be a pointer previously returned by #MBEDTLS_PLATFORM_STD_CALLOC and not yet freed. - * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. - * See the description of #MBEDTLS_PLATFORM_MEMORY for more details (same principles as for MBEDTLS_PLATFORM_STD_CALLOC - * apply). + * A non-null parameter will always be a pointer previously returned by #MBEDTLS_PLATFORM_STD_CALLOC + * and not yet freed. An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. See the + * description of #MBEDTLS_PLATFORM_MEMORY for more details (same principles as for + * MBEDTLS_PLATFORM_STD_CALLOC apply). */ // #define MBEDTLS_PLATFORM_STD_FREE free -// #define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is -// defined. Don't define if no header is needed. */ #define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file -// to read/write with default implementation */ #define MBEDTLS_PLATFORM_STD_NV_SEED_READ -// mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ #define -// MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, -// can be undefined */ #define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if +// MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */ #define +// MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file to read/write with default +// implementation */ #define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read /**< +// Default nv_seed_read function to use, can be undefined */ #define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE +// mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ // #define MBEDTLS_PLATFORM_STD_SETBUF setbuf /**< Default setbuf to use, can be undefined */ /* Note: your snprintf must correctly zero-terminate the buffer! */ // #define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< Default snprintf to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. MBEDTLS_HAVE_TIME must -// be enabled */ #define MBEDTLS_PLATFORM_TIME_MACRO time /**< Default time macro to use, can be undefined. -// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to -// use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf -// /**< Default vsnprintf macro to use, can be undefined */ #define MBEDTLS_PRINTF_MS_TIME PRId64 /**< Default fmt -// for printf. That's avoid compiler warning if mbedtls_ms_time_t is redefined */ +// #define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. +// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_TIME_MACRO time /**< +// Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ #define +// MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to use, can be undefined. +// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf +// /**< Default vsnprintf macro to use, can be undefined */ #define MBEDTLS_PRINTF_MS_TIME PRId64 +// /**< Default fmt for printf. That's avoid compiler warning if mbedtls_ms_time_t is redefined */ /** \} name SECTION: Platform abstraction layer */ @@ -1983,8 +1991,8 @@ // #define MBEDTLS_MPI_WINDOW_SIZE 2 /**< Maximum window size used. */ /* RSA OPTIONS */ -// #define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 /**< Minimum RSA key size that can be generated in bits -// (Minimum possible value is 128 bits) */ +// #define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 /**< Minimum RSA key size that can be +// generated in bits (Minimum possible value is 128 bits) */ /** \} name SECTION: Builtin drivers */ diff --git a/examples/stm32/nucleo_l432kc/hello_world/Src/mbedtls_v4/mbedtls_config.h b/examples/stm32/nucleo_l432kc/hello_world/Src/mbedtls_v4/mbedtls_config.h index 68149cacf..b34657c71 100644 --- a/examples/stm32/nucleo_l432kc/hello_world/Src/mbedtls_v4/mbedtls_config.h +++ b/examples/stm32/nucleo_l432kc/hello_world/Src/mbedtls_v4/mbedtls_config.h @@ -861,7 +861,8 @@ */ // #define MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH -// #define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default 256 or 384 bits) +// #define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default +// 256 or 384 bits) // */ #define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */ #define // MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /**< 1 day */ @@ -910,8 +911,8 @@ // #define MBEDTLS_SSL_CIPHERSUITES // MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 -// #define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, -// or in number of cookies issued */ +// #define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in +// seconds if HAVE_TIME, or in number of cookies issued */ /** \def MBEDTLS_SSL_DTLS_MAX_BUFFERING * @@ -1198,8 +1199,8 @@ */ // #define MBEDTLS_X509_USE_C -// #define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in bytes including the -// null terminator character ('\0'). */ #define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 /**< Maximum number of -// intermediate CAs in a verification chain. */ +// #define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in +// bytes including the null terminator character ('\0'). */ #define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 +// /**< Maximum number of intermediate CAs in a verification chain. */ /** \} name SECTION: X.509 feature selection */ diff --git a/examples/stm32/nucleo_l432kc/hello_world/Src/mbedtls_v4/mbedtls_platform.c b/examples/stm32/nucleo_l432kc/hello_world/Src/mbedtls_v4/mbedtls_platform.c index 7383d28d3..13d29a2d0 100644 --- a/examples/stm32/nucleo_l432kc/hello_world/Src/mbedtls_v4/mbedtls_platform.c +++ b/examples/stm32/nucleo_l432kc/hello_world/Src/mbedtls_v4/mbedtls_platform.c @@ -4,6 +4,7 @@ #include "main.h" #include "mbedtls/platform.h" #include "mbedtls/platform_time.h" +#include "mbedtls/platform_util.h" #include "stm32l4xx_hal.h" mbedtls_ms_time_t mbedtls_ms_time(void) @@ -13,8 +14,8 @@ mbedtls_ms_time_t mbedtls_ms_time(void) return (mbedtls_ms_time_t)HAL_GetTick(); } -int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *estimate_bits, unsigned char *output, - size_t output_size) +int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *estimate_bits, + unsigned char *output, size_t output_size) { // We don't implement any flags. if (flags != 0) { @@ -28,6 +29,7 @@ int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *e while (bytes_left) { hal_status = HAL_RNG_GenerateRandomNumber(&RNGHandle, &random_data); if (hal_status != HAL_OK) { + mbedtls_platform_zeroize(&random_data, sizeof(random_data)); return PSA_ERROR_INSUFFICIENT_ENTROPY; } @@ -39,5 +41,6 @@ int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *e *estimate_bits = 8 * output_size; + mbedtls_platform_zeroize(&random_data, sizeof(random_data)); return 0; } \ No newline at end of file diff --git a/examples/stm32/nucleo_l432kc/hello_world/Src/system_stm32l4xx.c b/examples/stm32/nucleo_l432kc/hello_world/Src/system_stm32l4xx.c index 8633cb04f..e3b652429 100644 --- a/examples/stm32/nucleo_l432kc/hello_world/Src/system_stm32l4xx.c +++ b/examples/stm32/nucleo_l432kc/hello_world/Src/system_stm32l4xx.c @@ -153,8 +153,8 @@ uint32_t SystemCoreClock = 4000000; const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; -const uint32_t MSIRangeTable[12] - = {100000, 200000, 400000, 800000, 1000000, 2000000, 4000000, 8000000, 16000000, 24000000, 32000000, 48000000}; +const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, + 4000000, 8000000, 16000000, 24000000, 32000000, 48000000}; /** * @} */ diff --git a/examples/stm32/nucleo_l432kc/identify_chip/Src/main.c b/examples/stm32/nucleo_l432kc/identify_chip/Src/main.c index 9aa3d3501..20c5527d7 100644 --- a/examples/stm32/nucleo_l432kc/identify_chip/Src/main.c +++ b/examples/stm32/nucleo_l432kc/identify_chip/Src/main.c @@ -1,13 +1,13 @@ /** * @file main.c - * @brief Example of reading information about the TROPIC01 chip and its firmware using Libtropic on STM32 Nucleo L432KC - * board. + * @brief Example of reading information about the TROPIC01 chip and its firmware using Libtropic on + * STM32 Nucleo L432KC board. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. * - * This example project is based on the SPI/SPI_FullDuplex_ComPolling example from STM32 example library - * which was created by the MCD Application Team. + * This example project is based on the SPI/SPI_FullDuplex_ComPolling example from STM32 example + * library which was created by the MCD Application Team. */ /* Includes ------------------------------------------------------------------*/ @@ -252,8 +252,9 @@ int main(void) } printf("OK\n"); - /* First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** be in the Start-up - Mode. If there are valid firmwares, TROPIC01 will begin to execute them automatically on boot. */ + /* First, we check versions of both updateable firmwares. To do that, we need TROPIC01 to **not** + be in the Start-up Mode. If there are valid firmwares, TROPIC01 will begin to execute them + automatically on boot. */ printf("Sending reboot request..."); ret = lt_reboot(<_handle, TR01_REBOOT); if (ret != LT_OK) { @@ -274,8 +275,8 @@ int main(void) mbedtls_psa_crypto_free(); return -1; } - printf(" RISC-V FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", fw_ver[3], fw_ver[2], fw_ver[1], - fw_ver[0]); + printf(" RISC-V FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", fw_ver[3], + fw_ver[2], fw_ver[1], fw_ver[0]); ret = lt_get_info_spect_fw_ver(<_handle, fw_ver); if (ret != LT_OK) { @@ -284,10 +285,11 @@ int main(void) mbedtls_psa_crypto_free(); return -1; } - printf(" SPECT FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", fw_ver[3], fw_ver[2], fw_ver[1], - fw_ver[0]); + printf(" SPECT FW version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", fw_ver[3], + fw_ver[2], fw_ver[1], fw_ver[0]); - /* We need to do the maintenance reboot to check bootloader version and FW bank headers in the Startup Mode. */ + /* We need to do the maintenance reboot to check bootloader version and FW bank headers in the + * Startup Mode. */ printf("Sending maintenance reboot request..."); ret = lt_reboot(<_handle, TR01_MAINTENANCE_REBOOT); if (ret != LT_OK) { @@ -300,7 +302,8 @@ int main(void) printf("Reading data from chip...\n"); - /* When TROPIC01 is in Start-up Mode, we can get RISC-V bootloader version the same way as we got RISC-V FW version. + /* When TROPIC01 is in Start-up Mode, we can get RISC-V bootloader version the same way as we got + * RISC-V FW version. */ ret = lt_get_info_riscv_fw_ver(<_handle, fw_ver); if (ret != LT_OK) { @@ -309,8 +312,8 @@ int main(void) mbedtls_psa_crypto_free(); return -1; } - printf(" RISC-V bootloader version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", fw_ver[3] & 0x7f, fw_ver[2], - fw_ver[1], fw_ver[0]); + printf(" RISC-V bootloader version: %" PRIX8 ".%" PRIX8 ".%" PRIX8 " (.%" PRIX8 ")\n", + fw_ver[3] & 0x7f, fw_ver[2], fw_ver[1], fw_ver[0]); printf("Firmware bank headers:\n"); ret = lt_print_fw_header(<_handle, TR01_FW_BANK_FW1, printf); @@ -464,8 +467,8 @@ void SystemClock_Config(void) /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType - = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | + RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; diff --git a/examples/stm32/nucleo_l432kc/identify_chip/Src/mbedtls_v4/crypto_config.h b/examples/stm32/nucleo_l432kc/identify_chip/Src/mbedtls_v4/crypto_config.h index 303d6d9b4..4939948db 100644 --- a/examples/stm32/nucleo_l432kc/identify_chip/Src/mbedtls_v4/crypto_config.h +++ b/examples/stm32/nucleo_l432kc/identify_chip/Src/mbedtls_v4/crypto_config.h @@ -356,12 +356,13 @@ * * - mbedtls_calloc = MBEDTLS_PLATFORM_STD_CALLOC. * - * Defining MBEDTLS_PLATFORM_CALLOC_MACRO and #MBEDTLS_PLATFORM_STD_CALLOC at the same time is not possible. - * MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO must both be defined or undefined at the same time. - * #MBEDTLS_PLATFORM_STD_CALLOC and #MBEDTLS_PLATFORM_STD_FREE do not have to be defined at the same time, as, if they - * are used, dynamic setup of these functions is possible. See the tree above to see how are they handled in all cases. - * An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. - * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. + * Defining MBEDTLS_PLATFORM_CALLOC_MACRO and #MBEDTLS_PLATFORM_STD_CALLOC at the same time is not + * possible. MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO must both be defined or + * undefined at the same time. #MBEDTLS_PLATFORM_STD_CALLOC and #MBEDTLS_PLATFORM_STD_FREE do not have + * to be defined at the same time, as, if they are used, dynamic setup of these functions is possible. + * See the tree above to see how are they handled in all cases. An uninitialized + * #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. An uninitialized + * #MBEDTLS_PLATFORM_STD_FREE does not do anything. * * Requires: MBEDTLS_PLATFORM_C * @@ -475,20 +476,24 @@ /* To use the following function macros, MBEDTLS_PLATFORM_C must be enabled. */ /* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */ -// #define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be undefined. See -// MBEDTLS_PLATFORM_STD_CALLOC for requirements. */ #define MBEDTLS_PLATFORM_EXIT_MACRO exit /**< Default -// exit macro to use, can be undefined */ #define MBEDTLS_PLATFORM_FREE_MACRO free /**< Default free macro to -// use, can be undefined. See MBEDTLS_PLATFORM_STD_FREE for requirements. */ #define MBEDTLS_PLATFORM_FPRINTF_MACRO -// fprintf /**< Default fprintf macro to use, can be undefined */ #define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t -// //#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t /**< Default milliseconds time macro to use, can be -// undefined. MBEDTLS_HAVE_TIME must be enabled. It must be signed, and at least 64 bits. If it is changed from the -// default, MBEDTLS_PRINTF_MS_TIME must be updated to match.*/ #define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO -// mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ #define -// MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, -// can be undefined */ #define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be -// undefined */ #define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf /**< Default setbuf macro to use, can be undefined */ +// #define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be +// undefined. See MBEDTLS_PLATFORM_STD_CALLOC for requirements. */ #define MBEDTLS_PLATFORM_EXIT_MACRO +// exit /**< Default exit macro to use, can be undefined */ #define MBEDTLS_PLATFORM_FREE_MACRO free +// /**< Default free macro to use, can be undefined. See MBEDTLS_PLATFORM_STD_FREE for requirements. */ +// #define MBEDTLS_PLATFORM_FPRINTF_MACRO fprintf /**< Default fprintf macro to use, can be undefined +// */ #define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t +// //#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t /**< Default milliseconds time macro to use, +// can be undefined. MBEDTLS_HAVE_TIME must be enabled. It must be signed, and at least 64 bits. If it +// is changed from the default, MBEDTLS_PRINTF_MS_TIME must be updated to match.*/ #define +// MBEDTLS_PLATFORM_NV_SEED_READ_MACRO mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read +// function to use, can be undefined */ #define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO +// mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +// #define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be +// undefined */ #define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf /**< Default setbuf macro to use, can +// be undefined */ /* Note: your snprintf must correctly zero-terminate the buffer! */ -// #define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be undefined */ +// #define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be +// undefined */ /** \def MBEDTLS_PLATFORM_STD_CALLOC * @@ -496,44 +501,47 @@ * It must initialize the allocated buffer memory to zeroes. * The size of the buffer is the product of the two parameters. * The calloc function returns either a null pointer or a pointer to the allocated space. - * If the product is 0, the function may either return NULL or a valid pointer to an array of size 0 which is a valid - * input to the deallocation function. An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null - * pointer. See the description of #MBEDTLS_PLATFORM_MEMORY for more details. The corresponding deallocation function is - * #MBEDTLS_PLATFORM_STD_FREE. + * If the product is 0, the function may either return NULL or a valid pointer to an array of size 0 + * which is a valid input to the deallocation function. An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC + * always fails, returning a null pointer. See the description of #MBEDTLS_PLATFORM_MEMORY for more + * details. The corresponding deallocation function is #MBEDTLS_PLATFORM_STD_FREE. */ // #define MBEDTLS_PLATFORM_STD_CALLOC calloc // #define MBEDTLS_PLATFORM_STD_EXIT exit /**< Default exit to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined +// */ #define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be +// undefined */ #define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be +// undefined */ /** \def MBEDTLS_PLATFORM_STD_FREE * * Default free to use, can be undefined. * NULL is a valid parameter, and the function must do nothing. - * A non-null parameter will always be a pointer previously returned by #MBEDTLS_PLATFORM_STD_CALLOC and not yet freed. - * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. - * See the description of #MBEDTLS_PLATFORM_MEMORY for more details (same principles as for MBEDTLS_PLATFORM_STD_CALLOC - * apply). + * A non-null parameter will always be a pointer previously returned by #MBEDTLS_PLATFORM_STD_CALLOC + * and not yet freed. An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. See the + * description of #MBEDTLS_PLATFORM_MEMORY for more details (same principles as for + * MBEDTLS_PLATFORM_STD_CALLOC apply). */ // #define MBEDTLS_PLATFORM_STD_FREE free -// #define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is -// defined. Don't define if no header is needed. */ #define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file -// to read/write with default implementation */ #define MBEDTLS_PLATFORM_STD_NV_SEED_READ -// mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ #define -// MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, -// can be undefined */ #define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if +// MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */ #define +// MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file to read/write with default +// implementation */ #define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read /**< +// Default nv_seed_read function to use, can be undefined */ #define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE +// mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ // #define MBEDTLS_PLATFORM_STD_SETBUF setbuf /**< Default setbuf to use, can be undefined */ /* Note: your snprintf must correctly zero-terminate the buffer! */ // #define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< Default snprintf to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. MBEDTLS_HAVE_TIME must -// be enabled */ #define MBEDTLS_PLATFORM_TIME_MACRO time /**< Default time macro to use, can be undefined. -// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to -// use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf -// /**< Default vsnprintf macro to use, can be undefined */ #define MBEDTLS_PRINTF_MS_TIME PRId64 /**< Default fmt -// for printf. That's avoid compiler warning if mbedtls_ms_time_t is redefined */ +// #define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. +// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_TIME_MACRO time /**< +// Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ #define +// MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to use, can be undefined. +// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf +// /**< Default vsnprintf macro to use, can be undefined */ #define MBEDTLS_PRINTF_MS_TIME PRId64 +// /**< Default fmt for printf. That's avoid compiler warning if mbedtls_ms_time_t is redefined */ /** \} name SECTION: Platform abstraction layer */ @@ -1983,8 +1991,8 @@ // #define MBEDTLS_MPI_WINDOW_SIZE 2 /**< Maximum window size used. */ /* RSA OPTIONS */ -// #define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 /**< Minimum RSA key size that can be generated in bits -// (Minimum possible value is 128 bits) */ +// #define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 /**< Minimum RSA key size that can be +// generated in bits (Minimum possible value is 128 bits) */ /** \} name SECTION: Builtin drivers */ diff --git a/examples/stm32/nucleo_l432kc/identify_chip/Src/mbedtls_v4/mbedtls_config.h b/examples/stm32/nucleo_l432kc/identify_chip/Src/mbedtls_v4/mbedtls_config.h index 68149cacf..b34657c71 100644 --- a/examples/stm32/nucleo_l432kc/identify_chip/Src/mbedtls_v4/mbedtls_config.h +++ b/examples/stm32/nucleo_l432kc/identify_chip/Src/mbedtls_v4/mbedtls_config.h @@ -861,7 +861,8 @@ */ // #define MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH -// #define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default 256 or 384 bits) +// #define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default +// 256 or 384 bits) // */ #define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */ #define // MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /**< 1 day */ @@ -910,8 +911,8 @@ // #define MBEDTLS_SSL_CIPHERSUITES // MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 -// #define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, -// or in number of cookies issued */ +// #define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in +// seconds if HAVE_TIME, or in number of cookies issued */ /** \def MBEDTLS_SSL_DTLS_MAX_BUFFERING * @@ -1198,8 +1199,8 @@ */ // #define MBEDTLS_X509_USE_C -// #define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in bytes including the -// null terminator character ('\0'). */ #define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 /**< Maximum number of -// intermediate CAs in a verification chain. */ +// #define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in +// bytes including the null terminator character ('\0'). */ #define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 +// /**< Maximum number of intermediate CAs in a verification chain. */ /** \} name SECTION: X.509 feature selection */ diff --git a/examples/stm32/nucleo_l432kc/identify_chip/Src/mbedtls_v4/mbedtls_platform.c b/examples/stm32/nucleo_l432kc/identify_chip/Src/mbedtls_v4/mbedtls_platform.c index 7383d28d3..13d29a2d0 100644 --- a/examples/stm32/nucleo_l432kc/identify_chip/Src/mbedtls_v4/mbedtls_platform.c +++ b/examples/stm32/nucleo_l432kc/identify_chip/Src/mbedtls_v4/mbedtls_platform.c @@ -4,6 +4,7 @@ #include "main.h" #include "mbedtls/platform.h" #include "mbedtls/platform_time.h" +#include "mbedtls/platform_util.h" #include "stm32l4xx_hal.h" mbedtls_ms_time_t mbedtls_ms_time(void) @@ -13,8 +14,8 @@ mbedtls_ms_time_t mbedtls_ms_time(void) return (mbedtls_ms_time_t)HAL_GetTick(); } -int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *estimate_bits, unsigned char *output, - size_t output_size) +int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *estimate_bits, + unsigned char *output, size_t output_size) { // We don't implement any flags. if (flags != 0) { @@ -28,6 +29,7 @@ int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *e while (bytes_left) { hal_status = HAL_RNG_GenerateRandomNumber(&RNGHandle, &random_data); if (hal_status != HAL_OK) { + mbedtls_platform_zeroize(&random_data, sizeof(random_data)); return PSA_ERROR_INSUFFICIENT_ENTROPY; } @@ -39,5 +41,6 @@ int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *e *estimate_bits = 8 * output_size; + mbedtls_platform_zeroize(&random_data, sizeof(random_data)); return 0; } \ No newline at end of file diff --git a/examples/stm32/nucleo_l432kc/identify_chip/Src/system_stm32l4xx.c b/examples/stm32/nucleo_l432kc/identify_chip/Src/system_stm32l4xx.c index 8633cb04f..e3b652429 100644 --- a/examples/stm32/nucleo_l432kc/identify_chip/Src/system_stm32l4xx.c +++ b/examples/stm32/nucleo_l432kc/identify_chip/Src/system_stm32l4xx.c @@ -153,8 +153,8 @@ uint32_t SystemCoreClock = 4000000; const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; -const uint32_t MSIRangeTable[12] - = {100000, 200000, 400000, 800000, 1000000, 2000000, 4000000, 8000000, 16000000, 24000000, 32000000, 48000000}; +const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, + 4000000, 8000000, 16000000, 24000000, 32000000, 48000000}; /** * @} */ diff --git a/hal/arduino/libtropic_port_arduino.h b/hal/arduino/libtropic_port_arduino.h index 5c02e57a2..cae92518f 100644 --- a/hal/arduino/libtropic_port_arduino.h +++ b/hal/arduino/libtropic_port_arduino.h @@ -12,8 +12,6 @@ #include #include -#include "libtropic_port.h" - /** * @brief Device structure for Arduino port. * diff --git a/hal/esp-idf/libtropic_port_esp_idf.c b/hal/esp-idf/libtropic_port_esp_idf.c index d8d2e0807..5afe12f80 100644 --- a/hal/esp-idf/libtropic_port_esp_idf.c +++ b/hal/esp-idf/libtropic_port_esp_idf.c @@ -89,12 +89,13 @@ lt_ret_t lt_port_init(lt_l2_state_t *s2) } // Create configuration for the SPI device. - spi_device_interface_config_t spi_dev_cfg = {.mode = 0, // TROPIC01 supports only CPOL=0 and CPHA=0. - .clock_speed_hz = dev->spi_clk_hz, - .spics_io_num = -1, // We handle CS ourselves. - .queue_size = 1, - .pre_cb = NULL, - .post_cb = NULL}; + spi_device_interface_config_t spi_dev_cfg = { + .mode = 0, // TROPIC01 supports only CPOL=0 and CPHA=0. + .clock_speed_hz = dev->spi_clk_hz, + .spics_io_num = -1, // We handle CS ourselves. + .queue_size = 1, + .pre_cb = NULL, + .post_cb = NULL}; // Add the SPI device to the bus. esp_ret = spi_bus_add_device(dev->spi_host_id, &spi_dev_cfg, &dev->spi_handle); diff --git a/hal/linux/spi/libtropic_port_linux_spi.c b/hal/linux/spi/libtropic_port_linux_spi.c index 854df5633..4fa75bd24 100644 --- a/hal/linux/spi/libtropic_port_linux_spi.c +++ b/hal/linux/spi/libtropic_port_linux_spi.c @@ -213,7 +213,8 @@ lt_ret_t lt_port_spi_csn_high(lt_l2_state_t *s2) return LT_OK; } -lt_ret_t lt_port_spi_transfer(lt_l2_state_t *s2, uint8_t offset, uint16_t tx_data_length, uint32_t timeout_ms) +lt_ret_t lt_port_spi_transfer(lt_l2_state_t *s2, uint8_t offset, uint16_t tx_data_length, + uint32_t timeout_ms) { LT_UNUSED(timeout_ms); lt_dev_linux_spi_t *device = (lt_dev_linux_spi_t *)(s2->device); @@ -259,8 +260,9 @@ lt_ret_t lt_port_random_bytes(lt_l2_state_t *s2, void *buff, size_t count) } if ((size_t)ret != count) { - LT_LOG_ERROR("lt_port_random_bytes: getrandom() generated %zd bytes instead of requested %zu bytes!", ret, - count); + LT_LOG_ERROR( + "lt_port_random_bytes: getrandom() generated %zd bytes instead of requested %zu bytes!", + ret, count); return LT_FAIL; } diff --git a/hal/linux/spi_native_cs/libtropic_port_linux_spi_native_cs.c b/hal/linux/spi_native_cs/libtropic_port_linux_spi_native_cs.c index 93832f7ca..3288da001 100644 --- a/hal/linux/spi_native_cs/libtropic_port_linux_spi_native_cs.c +++ b/hal/linux/spi_native_cs/libtropic_port_linux_spi_native_cs.c @@ -1,10 +1,11 @@ /** * @file libtropic_port_linux_spi_native_cs.c * @copyright Copyright (c) 2020-2025 Tropic Square s.r.o. - * @brief Port for communication using Generic SPI UAPI with native CS handling and GPIO for interrupt handling. + * @brief Port for communication using Generic SPI UAPI with native CS handling and GPIO for interrupt + * handling. * - * @note As this HAL controls CS using SPI driver natively, whole buffer is transferred each time, which - * introduces a small overhead. + * @note As this HAL controls CS using SPI driver natively, whole buffer is transferred each time, + * which introduces a small overhead. * * @warning This HAL is experimental. It can be modified or removed in the next release without notice. * @@ -183,7 +184,8 @@ lt_ret_t lt_port_spi_csn_high(lt_l2_state_t *s2) return LT_OK; } -lt_ret_t lt_port_spi_transfer(lt_l2_state_t *s2, uint8_t offset, uint16_t tx_data_length, uint32_t timeout_ms) +lt_ret_t lt_port_spi_transfer(lt_l2_state_t *s2, uint8_t offset, uint16_t tx_data_length, + uint32_t timeout_ms) { LT_UNUSED(offset); LT_UNUSED(tx_data_length); @@ -191,7 +193,8 @@ lt_ret_t lt_port_spi_transfer(lt_l2_state_t *s2, uint8_t offset, uint16_t tx_dat lt_dev_linux_spi_native_cs_t *device = (lt_dev_linux_spi_native_cs_t *)(s2->device); if (!device->frame_in_progress) { - LT_LOG_ERROR("lt_port_spi_transfer: No transfer in progress (spi_transfer called before csn_low)!"); + LT_LOG_ERROR( + "lt_port_spi_transfer: No transfer in progress (spi_transfer called before csn_low)!"); return LT_L1_SPI_ERROR; } @@ -240,8 +243,9 @@ lt_ret_t lt_port_random_bytes(lt_l2_state_t *s2, void *buff, size_t count) } if ((size_t)ret != count) { - LT_LOG_ERROR("lt_port_random_bytes: getrandom() generated %zd bytes instead of requested %zu bytes!", ret, - count); + LT_LOG_ERROR( + "lt_port_random_bytes: getrandom() generated %zd bytes instead of requested %zu bytes!", + ret, count); return LT_FAIL; } diff --git a/hal/linux/spi_native_cs/libtropic_port_linux_spi_native_cs.h b/hal/linux/spi_native_cs/libtropic_port_linux_spi_native_cs.h index 99612a85f..8895223e1 100644 --- a/hal/linux/spi_native_cs/libtropic_port_linux_spi_native_cs.h +++ b/hal/linux/spi_native_cs/libtropic_port_linux_spi_native_cs.h @@ -4,7 +4,8 @@ /** * @file libtropic_port_linux_spi_native_cs.h * @copyright Copyright (c) 2020-2025 Tropic Square s.r.o. - * @brief Port for communication using Generic SPI UAPI with native CS handling and GPIO UAPI for interrupt handling. + * @brief Port for communication using Generic SPI UAPI with native CS handling and GPIO UAPI for + * interrupt handling. * * @warning This HAL is experimental. It can be modified or removed in the next release without notice. * @@ -63,10 +64,10 @@ typedef struct lt_dev_linux_spi_native_cs_t { /** @private @brief True if lt_port_spi_transfer was already called during current frame. If true, * lt_port_spi_transfer does not do any communication and immediately returns. * - * Normally, Libtropic transfers frame by parts. E.g., it first transfers 1 byte to receive CHIP_STATUS. - * This is possible thanks to separate CS handling. In this HAL, separate CS is not available and as such - * we have to transfer whole buffer (even though actual frame may be smaller) at once. Hence only single SPI - * transfer is done. + * Normally, Libtropic transfers frame by parts. E.g., it first transfers 1 byte to receive + * CHIP_STATUS. This is possible thanks to separate CS handling. In this HAL, separate CS is not + * available and as such we have to transfer whole buffer (even though actual frame may be smaller) + * at once. Hence only single SPI transfer is done. */ int frame_completed; diff --git a/hal/mock/libtropic_port_mock.c b/hal/mock/libtropic_port_mock.c index fa34a9211..38b1f70bc 100644 --- a/hal/mock/libtropic_port_mock.c +++ b/hal/mock/libtropic_port_mock.c @@ -3,7 +3,7 @@ * @brief Mock HAL implementation (only for testing purposes). * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include "libtropic_port_mock.h" @@ -153,9 +153,10 @@ lt_ret_t lt_port_spi_transfer(lt_l2_state_t *s2, uint8_t offset, uint16_t tx_len } // If reading more bytes than available in the mocked response, log. Normally, this is OK: - // this happens when writing, as on the MOSI there is whole L2 Request and on MISO there is just CHIP_STATUS byte. - // During reading, this should not happen, as the lt_l1_read always reads up to the length of the response frame. It - // can happen only if the queued frame is invalid (shorter than minimum, not containing length byte or CRC etc). + // this happens when writing, as on the MOSI there is whole L2 Request and on MISO there is just + // CHIP_STATUS byte. During reading, this should not happen, as the lt_l1_read always reads up to + // the length of the response frame. It can happen only if the queued frame is invalid (shorter + // than minimum, not containing length byte or CRC etc). if (tx_len > r->len - dev->frame_bytes_transferred) { LT_LOG_DEBUG("Mock HAL: SPI Transfer length exceeds mocked response length."); } @@ -163,10 +164,11 @@ lt_ret_t lt_port_spi_transfer(lt_l2_state_t *s2, uint8_t offset, uint16_t tx_len memcpy(s2->buff + offset, r->data + dev->frame_bytes_transferred, tx_len); dev->frame_bytes_transferred += tx_len; - LT_LOG_DEBUG("Mock HAL queue position: head=%zu, tail=%zu, count=%zu", dev->mock_queue_head, dev->mock_queue_tail, - dev->mock_queue_count); + LT_LOG_DEBUG("Mock HAL queue position: head=%zu, tail=%zu, count=%zu", dev->mock_queue_head, + dev->mock_queue_tail, dev->mock_queue_count); for (size_t i = 0; i < tx_len; i++) { - LT_LOG_DEBUG("Mock HAL: SPI Transfer: buff[%zu] = 0x%02" PRIX8, offset + i, s2->buff[offset + i]); + LT_LOG_DEBUG("Mock HAL: SPI Transfer: buff[%zu] = 0x%02" PRIX8, offset + i, + s2->buff[offset + i]); } return LT_OK; diff --git a/hal/mock/libtropic_port_mock.h b/hal/mock/libtropic_port_mock.h index 613da72d2..c8d744de9 100644 --- a/hal/mock/libtropic_port_mock.h +++ b/hal/mock/libtropic_port_mock.h @@ -6,10 +6,12 @@ * @brief Mock HAL implementation (only for testing purposes). * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ -#include "libtropic_port.h" +#include + +#include "libtropic_common.h" #ifdef __cplusplus extern "C" { @@ -18,8 +20,9 @@ extern "C" { /** * @brief Mocked MISO data structure. * - * @details This can be either L2 Response frame or a single CHIP_STATUS byte (in a case of writing REQ_ID=0xAA). - * Basically, anything that can be returned by the chip during a period between CSN low and CSN high on the MISO line. + * @details This can be either L2 Response frame or a single CHIP_STATUS byte (in a case of writing + * REQ_ID=0xAA). Basically, anything that can be returned by the chip during a period between CSN low + * and CSN high on the MISO line. */ typedef struct mock_miso_data_t { size_t len; @@ -53,15 +56,16 @@ typedef struct lt_dev_mock_t { /** * @brief Reset internal mock state (clear queued responses and flags). * - * @warning This has to be called by the test developer before starting a new test case. It is not called automatically - * by HAL, as mocked reponses may be needed before/after initializing Libtropic. + * @warning This has to be called by the test developer before starting a new test case. It is not + * called automatically by HAL, as mocked reponses may be needed before/after initializing Libtropic. */ lt_ret_t lt_mock_hal_reset(lt_l2_state_t *s2); /** * @brief Enqueue a raw response that the mock will return on the next SPI transfer. * - * @details The mock copies `len` bytes from `data` into its internal queue. `len` must be <= TR01_L1_LEN_MAX. + * @details The mock copies `len` bytes from `data` into its internal queue. `len` must be <= + * TR01_L1_LEN_MAX. * * @param data Pointer to response bytes. * @param len Length of response bytes. diff --git a/hal/posix/tcp/libtropic_port_posix_tcp.c b/hal/posix/tcp/libtropic_port_posix_tcp.c index 662aa9e56..8afaac0a8 100644 --- a/hal/posix/tcp/libtropic_port_posix_tcp.c +++ b/hal/posix/tcp/libtropic_port_posix_tcp.c @@ -79,11 +79,14 @@ static lt_ret_t send_all(const int socket_fd, const uint8_t *buffer, const size_ * @brief Send and receive data to/from the TCP port. * * @param dev TCP HAL Device structure - * @param tx_payload_length_ptr Pointer to the length of the payload to send (excluding tag and length fields) - * @param rx_payload_length_ptr Pointer to the length of the payload to receive (excluding tag and length fields) + * @param tx_payload_length_ptr Pointer to the length of the payload to send (excluding tag and length + * fields) + * @param rx_payload_length_ptr Pointer to the length of the payload to receive (excluding tag and + * length fields) * @return LT_OK on success, LT_FAIL otherwise */ -static lt_ret_t communicate(lt_dev_posix_tcp_t *dev, int *tx_payload_length_ptr, int *rx_payload_length_ptr) +static lt_ret_t communicate(lt_dev_posix_tcp_t *dev, int *tx_payload_length_ptr, + int *rx_payload_length_ptr) { int nb_bytes_received; int nb_bytes_received_total = 0; @@ -119,7 +122,8 @@ static lt_ret_t communicate(lt_dev_posix_tcp_t *dev, int *tx_payload_length_ptr, LT_LOG_DEBUG("Length field: %" PRIu16 ".", dev->rx_buffer.len); nb_bytes_to_receive += dev->rx_buffer.len; nb_bytes_received_total += nb_bytes_received; - LT_LOG_DEBUG("Received %d bytes out of %d expected.", nb_bytes_received_total, nb_bytes_to_receive); + LT_LOG_DEBUG("Received %d bytes out of %d expected.", nb_bytes_received_total, + nb_bytes_to_receive); if (nb_bytes_received_total < nb_bytes_to_receive) { rx_ptr += nb_bytes_received; @@ -143,7 +147,8 @@ static lt_ret_t communicate(lt_dev_posix_tcp_t *dev, int *tx_payload_length_ptr, } if (nb_bytes_received_total != nb_bytes_to_receive) { - LT_LOG_ERROR("Received %d bytes in total instead of %d.", nb_bytes_received_total, nb_bytes_to_receive); + LT_LOG_ERROR("Received %d bytes in total instead of %d.", nb_bytes_received_total, + nb_bytes_to_receive); return LT_FAIL; } @@ -159,7 +164,8 @@ static lt_ret_t communicate(lt_dev_posix_tcp_t *dev, int *tx_payload_length_ptr, } // RX tag and TX tag should be identical else if (dev->rx_buffer.tag != dev->tx_buffer.tag) { - LT_LOG_ERROR("Expected tag %" PRIu8 ", received %" PRIu8 ".", dev->rx_buffer.tag, dev->tx_buffer.tag); + LT_LOG_ERROR("Expected tag %" PRIu8 ", received %" PRIu8 ".", dev->rx_buffer.tag, + dev->tx_buffer.tag); return LT_FAIL; } @@ -238,7 +244,8 @@ lt_ret_t lt_port_spi_csn_high(lt_l2_state_t *s2) return communicate(dev, NULL, NULL); } -lt_ret_t lt_port_spi_transfer(lt_l2_state_t *s2, uint8_t offset, uint16_t tx_data_length, uint32_t timeout_ms) +lt_ret_t lt_port_spi_transfer(lt_l2_state_t *s2, uint8_t offset, uint16_t tx_data_length, + uint32_t timeout_ms) { LT_UNUSED(timeout_ms); lt_dev_posix_tcp_t *dev = (lt_dev_posix_tcp_t *)(s2->device); diff --git a/hal/posix/usb_dongle/libtropic_port_posix_usb_dongle.c b/hal/posix/usb_dongle/libtropic_port_posix_usb_dongle.c index 58f623174..b900e715e 100644 --- a/hal/posix/usb_dongle/libtropic_port_posix_usb_dongle.c +++ b/hal/posix/usb_dongle/libtropic_port_posix_usb_dongle.c @@ -35,10 +35,10 @@ #error "Interrupt PIN not supported in the USB dongle port!" #endif -// getentropy() has a limit of random bytes it can generate in one call. The POSIX.1-2024 standard requires -// GETENTROPY_MAX to be defined in limits.h, but because this standard is quite new, we will define the macro here in -// case the current limits.h does not define it yet. The value 256 is safe to use because it was always the minimum -// value. +// getentropy() has a limit of random bytes it can generate in one call. The POSIX.1-2024 standard +// requires GETENTROPY_MAX to be defined in limits.h, but because this standard is quite new, we will +// define the macro here in case the current limits.h does not define it yet. The value 256 is safe to +// use because it was always the minimum value. #ifndef GETENTROPY_MAX #define GETENTROPY_MAX 256 #endif @@ -239,7 +239,8 @@ lt_ret_t lt_port_spi_csn_high(lt_l2_state_t *s2) return LT_OK; } -lt_ret_t lt_port_spi_transfer(lt_l2_state_t *s2, uint8_t offset, uint16_t tx_data_length, uint32_t timeout_ms) +lt_ret_t lt_port_spi_transfer(lt_l2_state_t *s2, uint8_t offset, uint16_t tx_data_length, + uint32_t timeout_ms) { LT_UNUSED(timeout_ms); diff --git a/hal/stm32/nucleo_f439zi/libtropic_port_stm32_nucleo_f439zi.c b/hal/stm32/nucleo_f439zi/libtropic_port_stm32_nucleo_f439zi.c index d6f1eafb9..47cb5bb04 100644 --- a/hal/stm32/nucleo_f439zi/libtropic_port_stm32_nucleo_f439zi.c +++ b/hal/stm32/nucleo_f439zi/libtropic_port_stm32_nucleo_f439zi.c @@ -20,6 +20,7 @@ #include "libtropic_logging.h" #include "libtropic_macros.h" #include "libtropic_port.h" +#include "libtropic_secure_memzero.h" #include "stm32f4xx_hal.h" #define LT_STM32_F439ZI_GPIO_OUTPUT_CHECK_ATTEMPTS 10 @@ -36,6 +37,7 @@ lt_ret_t lt_port_random_bytes(lt_l2_state_t *s2, void *buff, size_t count) ret = HAL_RNG_GenerateRandomNumber(device->rng_handle, &random_data); if (ret != HAL_OK) { LT_LOG_ERROR("HAL_RNG_GenerateRandomNumber failed, ret=%d", ret); + lt_secure_memzero(&random_data, sizeof(random_data)); return LT_FAIL; } @@ -45,6 +47,7 @@ lt_ret_t lt_port_random_bytes(lt_l2_state_t *s2, void *buff, size_t count) buff_ptr += cpy_cnt; } + lt_secure_memzero(&random_data, sizeof(random_data)); return LT_OK; } @@ -54,7 +57,8 @@ lt_ret_t lt_port_spi_csn_low(lt_l2_state_t *s2) HAL_GPIO_WritePin(device->spi_cs_gpio_bank, device->spi_cs_gpio_pin, GPIO_PIN_RESET); - for (uint8_t read_attempts = 0; read_attempts < LT_STM32_F439ZI_GPIO_OUTPUT_CHECK_ATTEMPTS; read_attempts++) { + for (uint8_t read_attempts = 0; read_attempts < LT_STM32_F439ZI_GPIO_OUTPUT_CHECK_ATTEMPTS; + read_attempts++) { if (!HAL_GPIO_ReadPin(device->spi_cs_gpio_bank, device->spi_cs_gpio_pin)) { return LT_OK; } @@ -70,7 +74,8 @@ lt_ret_t lt_port_spi_csn_high(lt_l2_state_t *s2) HAL_GPIO_WritePin(device->spi_cs_gpio_bank, device->spi_cs_gpio_pin, GPIO_PIN_SET); - for (uint8_t read_attempts = 0; read_attempts < LT_STM32_F439ZI_GPIO_OUTPUT_CHECK_ATTEMPTS; read_attempts++) { + for (uint8_t read_attempts = 0; read_attempts < LT_STM32_F439ZI_GPIO_OUTPUT_CHECK_ATTEMPTS; + read_attempts++) { if (HAL_GPIO_ReadPin(device->spi_cs_gpio_bank, device->spi_cs_gpio_pin)) { return LT_OK; } @@ -146,7 +151,8 @@ lt_ret_t lt_port_deinit(lt_l2_state_t *s2) return LT_OK; } -lt_ret_t lt_port_spi_transfer(lt_l2_state_t *s2, uint8_t offset, uint16_t tx_data_length, uint32_t timeout_ms) +lt_ret_t lt_port_spi_transfer(lt_l2_state_t *s2, uint8_t offset, uint16_t tx_data_length, + uint32_t timeout_ms) { lt_dev_stm32_nucleo_f439zi_t *device = (lt_dev_stm32_nucleo_f439zi_t *)(s2->device); @@ -154,8 +160,8 @@ lt_ret_t lt_port_spi_transfer(lt_l2_state_t *s2, uint8_t offset, uint16_t tx_dat LT_LOG_ERROR("Invalid data length!"); return LT_L1_DATA_LEN_ERROR; } - int ret = HAL_SPI_TransmitReceive(&device->spi_handle, s2->buff + offset, s2->buff + offset, tx_data_length, - timeout_ms); + int ret = HAL_SPI_TransmitReceive(&device->spi_handle, s2->buff + offset, s2->buff + offset, + tx_data_length, timeout_ms); if (ret != HAL_OK) { LT_LOG_ERROR("HAL_SPI_TransmitReceive failed, ret=%d", ret); return LT_L1_SPI_ERROR; diff --git a/hal/stm32/nucleo_f439zi/libtropic_port_stm32_nucleo_f439zi.h b/hal/stm32/nucleo_f439zi/libtropic_port_stm32_nucleo_f439zi.h index cb2063a07..0b599e8d0 100644 --- a/hal/stm32/nucleo_f439zi/libtropic_port_stm32_nucleo_f439zi.h +++ b/hal/stm32/nucleo_f439zi/libtropic_port_stm32_nucleo_f439zi.h @@ -9,7 +9,6 @@ * @license For the license see LICENSE.md in the root directory of this source tree. */ -#include "libtropic_port.h" #include "stm32f4xx_hal.h" /** @@ -23,11 +22,12 @@ typedef struct lt_dev_stm32_nucleo_f439zi_t { SPI_TypeDef *spi_instance; /** - * @brief @public Baudrate prescaler value, used to set SPI speed. Use STM32 macro (e.g. SPI_BAUDRATEPRESCALER_32). + * @brief @public Baudrate prescaler value, used to set SPI speed. Use STM32 macro (e.g. + * SPI_BAUDRATEPRESCALER_32). * * @note If set to zero, it will default to SPI_BAUDRATEPRESCALER_32. */ - uint16_t baudrate_prescaler; + uint32_t baudrate_prescaler; /** @brief @public GPIO pin used for chip select. Use STM32 macro (GPIO_PIN_XX). */ uint16_t spi_cs_gpio_pin; diff --git a/hal/stm32/nucleo_l432kc/libtropic_port_stm32_nucleo_l432kc.c b/hal/stm32/nucleo_l432kc/libtropic_port_stm32_nucleo_l432kc.c index 3dacae6b0..057f74b59 100644 --- a/hal/stm32/nucleo_l432kc/libtropic_port_stm32_nucleo_l432kc.c +++ b/hal/stm32/nucleo_l432kc/libtropic_port_stm32_nucleo_l432kc.c @@ -17,6 +17,7 @@ #include "libtropic_logging.h" #include "libtropic_macros.h" #include "libtropic_port.h" +#include "libtropic_secure_memzero.h" #include "stm32l4xx_hal.h" #define LT_STM32_L432KC_GPIO_OUTPUT_CHECK_ATTEMPTS 10 @@ -33,6 +34,7 @@ lt_ret_t lt_port_random_bytes(lt_l2_state_t *s2, void *buff, size_t count) ret = HAL_RNG_GenerateRandomNumber(device->rng_handle, &random_data); if (ret != HAL_OK) { LT_LOG_ERROR("HAL_RNG_GenerateRandomNumber failed, ret=%d", ret); + lt_secure_memzero(&random_data, sizeof(random_data)); return LT_FAIL; } @@ -42,6 +44,7 @@ lt_ret_t lt_port_random_bytes(lt_l2_state_t *s2, void *buff, size_t count) buff_ptr += cpy_cnt; } + lt_secure_memzero(&random_data, sizeof(random_data)); return LT_OK; } @@ -50,7 +53,8 @@ lt_ret_t lt_port_spi_csn_low(lt_l2_state_t *s2) lt_dev_stm32_nucleo_l432kc_t *device = (lt_dev_stm32_nucleo_l432kc_t *)(s2->device); HAL_GPIO_WritePin(device->spi_cs_gpio_bank, device->spi_cs_gpio_pin, GPIO_PIN_RESET); - for (uint8_t read_attempts = 0; read_attempts < LT_STM32_L432KC_GPIO_OUTPUT_CHECK_ATTEMPTS; read_attempts++) { + for (uint8_t read_attempts = 0; read_attempts < LT_STM32_L432KC_GPIO_OUTPUT_CHECK_ATTEMPTS; + read_attempts++) { if (!HAL_GPIO_ReadPin(device->spi_cs_gpio_bank, device->spi_cs_gpio_pin)) { return LT_OK; } @@ -65,7 +69,8 @@ lt_ret_t lt_port_spi_csn_high(lt_l2_state_t *s2) lt_dev_stm32_nucleo_l432kc_t *device = (lt_dev_stm32_nucleo_l432kc_t *)(s2->device); HAL_GPIO_WritePin(device->spi_cs_gpio_bank, device->spi_cs_gpio_pin, GPIO_PIN_SET); - for (uint8_t read_attempts = 0; read_attempts < LT_STM32_L432KC_GPIO_OUTPUT_CHECK_ATTEMPTS; read_attempts++) { + for (uint8_t read_attempts = 0; read_attempts < LT_STM32_L432KC_GPIO_OUTPUT_CHECK_ATTEMPTS; + read_attempts++) { if (HAL_GPIO_ReadPin(device->spi_cs_gpio_bank, device->spi_cs_gpio_pin)) { return LT_OK; } @@ -132,7 +137,8 @@ lt_ret_t lt_port_deinit(lt_l2_state_t *s2) return LT_OK; } -lt_ret_t lt_port_spi_transfer(lt_l2_state_t *s2, uint8_t offset, uint16_t tx_data_length, uint32_t timeout_ms) +lt_ret_t lt_port_spi_transfer(lt_l2_state_t *s2, uint8_t offset, uint16_t tx_data_length, + uint32_t timeout_ms) { lt_dev_stm32_nucleo_l432kc_t *device = (lt_dev_stm32_nucleo_l432kc_t *)(s2->device); @@ -140,8 +146,8 @@ lt_ret_t lt_port_spi_transfer(lt_l2_state_t *s2, uint8_t offset, uint16_t tx_dat LT_LOG_ERROR("Invalid data length!"); return LT_L1_DATA_LEN_ERROR; } - int ret = HAL_SPI_TransmitReceive(&device->spi_handle, s2->buff + offset, s2->buff + offset, tx_data_length, - timeout_ms); + int ret = HAL_SPI_TransmitReceive(&device->spi_handle, s2->buff + offset, s2->buff + offset, + tx_data_length, timeout_ms); if (ret != HAL_OK) { LT_LOG_ERROR("HAL_SPI_TransmitReceive failed, ret=%d", ret); return LT_L1_SPI_ERROR; diff --git a/hal/stm32/nucleo_l432kc/libtropic_port_stm32_nucleo_l432kc.h b/hal/stm32/nucleo_l432kc/libtropic_port_stm32_nucleo_l432kc.h index f6c128b29..37d1ac691 100644 --- a/hal/stm32/nucleo_l432kc/libtropic_port_stm32_nucleo_l432kc.h +++ b/hal/stm32/nucleo_l432kc/libtropic_port_stm32_nucleo_l432kc.h @@ -9,7 +9,6 @@ * @license For the license see LICENSE.md in the root directory of this source tree. */ -#include "libtropic_port.h" #include "stm32l4xx_hal.h" /** @@ -23,11 +22,12 @@ typedef struct lt_dev_stm32_nucleo_l432kc_t { SPI_TypeDef *spi_instance; /** - * @brief @public Baudrate prescaler value, used to set SPI speed. Use STM32 macro (e.g. SPI_BAUDRATEPRESCALER_32). + * @brief @public Baudrate prescaler value, used to set SPI speed. Use STM32 macro (e.g. + * SPI_BAUDRATEPRESCALER_32). * * @note If set to zero, it will default to SPI_BAUDRATEPRESCALER_32. */ - uint16_t baudrate_prescaler; + uint32_t baudrate_prescaler; /** @brief @public GPIO pin used for chip select. Use STM32 macro (GPIO_PIN_XX). */ uint16_t spi_cs_gpio_pin; diff --git a/hal/stm32/stm32u5xx/CMakeLists.txt b/hal/stm32/stm32u5xx/CMakeLists.txt new file mode 100644 index 000000000..30d7ee007 --- /dev/null +++ b/hal/stm32/stm32u5xx/CMakeLists.txt @@ -0,0 +1,13 @@ +cmake_minimum_required(VERSION 3.21.0) + +set(LT_HAL_SRCS + ${CMAKE_CURRENT_SOURCE_DIR}/libtropic_port_stm32u5xx.c +) + +set(LT_HAL_INC_DIRS + ${CMAKE_CURRENT_SOURCE_DIR} +) + +# export generic names for parent to consume +set(LT_HAL_SRCS ${LT_HAL_SRCS} PARENT_SCOPE) +set(LT_HAL_INC_DIRS ${LT_HAL_INC_DIRS} PARENT_SCOPE) \ No newline at end of file diff --git a/hal/stm32/stm32u5xx/libtropic_port_stm32u5xx.c b/hal/stm32/stm32u5xx/libtropic_port_stm32u5xx.c new file mode 100644 index 000000000..1f2e6a5a1 --- /dev/null +++ b/hal/stm32/stm32u5xx/libtropic_port_stm32u5xx.c @@ -0,0 +1,225 @@ +/** + * @file libtropic_port_stm32u5xx.c + * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. + * @brief Port for STM32U5xx series using native SPI HAL (and GPIO HAL for chip select). + * + * @license For the license see LICENSE.md in the root directory of this source tree. + */ + +#include "libtropic_port_stm32u5xx.h" + +#include +#include +#include +#include + +#include "libtropic_common.h" +#include "libtropic_logging.h" +#include "libtropic_macros.h" +#include "libtropic_port.h" +#include "libtropic_secure_memzero.h" +#include "stm32u5xx_hal.h" + +#define LT_STM32U5XX_GPIO_OUTPUT_CHECK_ATTEMPTS 10 + +lt_ret_t lt_port_random_bytes(lt_l2_state_t *s2, void *buff, size_t count) +{ + lt_dev_stm32u5xx_t *device = (lt_dev_stm32u5xx_t *)(s2->device); + size_t bytes_left = count; + uint8_t *buff_ptr = buff; + int ret; + uint32_t random_data; + + while (bytes_left) { + ret = HAL_RNG_GenerateRandomNumber(device->rng_handle, &random_data); + if (ret != HAL_OK) { + LT_LOG_ERROR("HAL_RNG_GenerateRandomNumber failed, ret=%d", ret); + lt_secure_memzero(&random_data, sizeof(random_data)); + return LT_FAIL; + } + + size_t cpy_cnt = bytes_left < sizeof(random_data) ? bytes_left : sizeof(random_data); + memcpy(buff_ptr, &random_data, cpy_cnt); + bytes_left -= cpy_cnt; + buff_ptr += cpy_cnt; + } + + lt_secure_memzero(&random_data, sizeof(random_data)); + return LT_OK; +} + +lt_ret_t lt_port_spi_csn_low(lt_l2_state_t *s2) +{ + lt_dev_stm32u5xx_t *device = (lt_dev_stm32u5xx_t *)(s2->device); + + HAL_GPIO_WritePin(device->spi_cs_gpio_bank, device->spi_cs_gpio_pin, GPIO_PIN_RESET); + + for (uint8_t read_attempts = 0; read_attempts < LT_STM32U5XX_GPIO_OUTPUT_CHECK_ATTEMPTS; + read_attempts++) { + if (!HAL_GPIO_ReadPin(device->spi_cs_gpio_bank, device->spi_cs_gpio_pin)) { + return LT_OK; + } + } + + LT_LOG_ERROR("Failed to set CSN low!"); + return LT_L1_SPI_ERROR; +} + +lt_ret_t lt_port_spi_csn_high(lt_l2_state_t *s2) +{ + lt_dev_stm32u5xx_t *device = (lt_dev_stm32u5xx_t *)(s2->device); + + HAL_GPIO_WritePin(device->spi_cs_gpio_bank, device->spi_cs_gpio_pin, GPIO_PIN_SET); + + for (uint8_t read_attempts = 0; read_attempts < LT_STM32U5XX_GPIO_OUTPUT_CHECK_ATTEMPTS; + read_attempts++) { + if (HAL_GPIO_ReadPin(device->spi_cs_gpio_bank, device->spi_cs_gpio_pin)) { + return LT_OK; + } + } + + LT_LOG_ERROR("Failed to set CSN high!"); + return LT_L1_SPI_ERROR; +} + +lt_ret_t lt_port_init(lt_l2_state_t *s2) +{ + lt_dev_stm32u5xx_t *device = (lt_dev_stm32u5xx_t *)(s2->device); + HAL_StatusTypeDef ret; + + // Configure SPI. + device->spi_handle.Instance = device->spi_instance; + device->spi_handle.Init.Mode = SPI_MODE_MASTER; + device->spi_handle.Init.Direction = SPI_DIRECTION_2LINES; + device->spi_handle.Init.DataSize = SPI_DATASIZE_8BIT; + device->spi_handle.Init.CLKPolarity = SPI_POLARITY_LOW; + device->spi_handle.Init.CLKPhase = SPI_PHASE_1EDGE; + device->spi_handle.Init.NSS = SPI_NSS_SOFT; + device->spi_handle.Init.BaudRatePrescaler = device->baudrate_prescaler; + device->spi_handle.Init.FirstBit = SPI_FIRSTBIT_MSB; + device->spi_handle.Init.TIMode = SPI_TIMODE_DISABLE; + device->spi_handle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + device->spi_handle.Init.CRCPolynomial = 0x7; + device->spi_handle.Init.NSSPMode = SPI_NSS_PULSE_DISABLE; + device->spi_handle.Init.NSSPolarity = SPI_NSS_POLARITY_LOW; + device->spi_handle.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA; + device->spi_handle.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE; + device->spi_handle.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE; + device->spi_handle.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE; + device->spi_handle.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE; + device->spi_handle.Init.IOSwap = SPI_IO_SWAP_DISABLE; + device->spi_handle.Init.ReadyMasterManagement = SPI_RDY_MASTER_MANAGEMENT_INTERNALLY; + device->spi_handle.Init.ReadyPolarity = SPI_RDY_POLARITY_HIGH; + + ret = HAL_SPI_Init(&device->spi_handle); + if (ret != HAL_OK) { + LT_LOG_ERROR("Failed to init SPI, ret=%d", ret); + return LT_L1_SPI_ERROR; + } + + SPI_AutonomousModeConfTypeDef HAL_SPI_AutonomousMode_Cfg_Struct = { + .TriggerState = SPI_AUTO_MODE_DISABLE, + .TriggerSelection = SPI_GRP1_GPDMA_CH0_TCF_TRG, + .TriggerPolarity = SPI_TRIG_POLARITY_RISING}; + + ret = HAL_SPIEx_SetConfigAutonomousMode(&device->spi_handle, &HAL_SPI_AutonomousMode_Cfg_Struct); + if (ret != HAL_OK) { + LT_LOG_ERROR("Failed to configure SPI autonomous mode, ret=%d", ret); + HAL_SPI_DeInit(&device->spi_handle); + return LT_L1_SPI_ERROR; + } + + // Configure GPIO for chip select and set default value. + GPIO_InitTypeDef GPIO_InitStruct = {0}; + HAL_GPIO_WritePin(device->spi_cs_gpio_bank, device->spi_cs_gpio_pin, GPIO_PIN_SET); + GPIO_InitStruct.Pin = device->spi_cs_gpio_pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; + HAL_GPIO_Init(device->spi_cs_gpio_bank, &GPIO_InitStruct); + +#if LT_USE_INT_PIN + // Configure GPIO for INT pin. + GPIO_InitStruct.Pin = device->int_gpio_pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(device->int_gpio_bank, &GPIO_InitStruct); +#endif + + return LT_OK; +} + +lt_ret_t lt_port_deinit(lt_l2_state_t *s2) +{ + lt_dev_stm32u5xx_t *device = (lt_dev_stm32u5xx_t *)(s2->device); + int ret; + + ret = HAL_SPI_DeInit(&device->spi_handle); + if (ret != HAL_OK) { + LT_LOG_ERROR("Failed to deinit SPI, ret=%d", ret); + return LT_L1_SPI_ERROR; + } + + return LT_OK; +} + +lt_ret_t lt_port_spi_transfer(lt_l2_state_t *s2, uint8_t offset, uint16_t tx_data_length, + uint32_t timeout_ms) +{ + lt_dev_stm32u5xx_t *device = (lt_dev_stm32u5xx_t *)(s2->device); + + if (offset + tx_data_length > TR01_L1_LEN_MAX) { + LT_LOG_ERROR("Invalid data length!"); + return LT_L1_DATA_LEN_ERROR; + } + int ret = HAL_SPI_TransmitReceive(&device->spi_handle, s2->buff + offset, s2->buff + offset, + tx_data_length, timeout_ms); + if (ret != HAL_OK) { + LT_LOG_ERROR("HAL_SPI_TransmitReceive failed, ret=%d", ret); + return LT_L1_SPI_ERROR; + } + + return LT_OK; +} + +lt_ret_t lt_port_delay(lt_l2_state_t *s2, uint32_t ms) +{ + LT_UNUSED(s2); + + HAL_Delay(ms); + + return LT_OK; +} + +#if LT_USE_INT_PIN +lt_ret_t lt_port_delay_on_int(lt_l2_state_t *s2, uint32_t ms) +{ + lt_dev_stm32u5xx_t *device = (lt_dev_stm32u5xx_t *)(s2->device); + uint32_t time_initial = HAL_GetTick(); + uint32_t time_actual; + + while ((HAL_GPIO_ReadPin(device->int_gpio_bank, device->int_gpio_pin) == 0)) { + time_actual = HAL_GetTick(); + if ((time_actual - time_initial) > ms) { + return LT_L1_INT_TIMEOUT; + } + // HAL_Delay(ms); + } + + return LT_OK; +} +#endif + +int lt_port_log(const char *format, ...) +{ + va_list args; + int ret; + + va_start(args, format); + ret = vprintf(format, args); + fflush(stdout); + va_end(args); + + return ret; +} diff --git a/hal/stm32/stm32u5xx/libtropic_port_stm32u5xx.h b/hal/stm32/stm32u5xx/libtropic_port_stm32u5xx.h new file mode 100644 index 000000000..61ea1bffa --- /dev/null +++ b/hal/stm32/stm32u5xx/libtropic_port_stm32u5xx.h @@ -0,0 +1,47 @@ +#ifndef LIBTROPIC_PORT_STM32U5XX_H +#define LIBTROPIC_PORT_STM32U5XX_H + +/** + * @file libtropic_port_stm32u5xx.h + * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. + * @brief Port for STM32U5xx series using native SPI HAL (and GPIO HAL for chip select). + * + * @license For the license see LICENSE.md in the root directory of this source tree. + */ + +#include "stm32u5xx_hal.h" + +/** + * @brief Device structure for STM32U5xx series port. + * + * @note Public members are meant to be configured by the developer before passing the handle to + * libtropic. + */ +typedef struct lt_dev_stm32u5xx_t { + /** @brief @public Instance of STM SPI interface. Use STM32 macro (SPIX, e.g. SPI1). */ + SPI_TypeDef *spi_instance; + + /** @brief @public Baudrate prescaler value, used to set SPI speed. Use STM32 macro (e.g. + * SPI_BAUDRATEPRESCALER_2). */ + uint32_t baudrate_prescaler; + + /** @brief @public GPIO pin used for chip select. Use STM32 macro (GPIO_PIN_XX). */ + uint16_t spi_cs_gpio_pin; + /** @brief @public GPIO bank of the pin used for chip select. Use STM32 macro (GPIOX). */ + GPIO_TypeDef *spi_cs_gpio_bank; + +#if LT_USE_INT_PIN + /** @brief @public GPIO pin used for interrupts. Use STM32 macro (GPIO_PIN_XX). */ + uint16_t int_gpio_pin; + /** @brief @public GPIO bank of the pin used for interrupts. Use STM32 macro (GPIOX). */ + GPIO_TypeDef *int_gpio_bank; +#endif + + /** @brief @public Random number generator handle. */ + RNG_HandleTypeDef *rng_handle; + + /** @brief @private SPI handle. */ + SPI_HandleTypeDef spi_handle; +} lt_dev_stm32u5xx_t; + +#endif // LIBTROPIC_PORT_STM32U5XX_H \ No newline at end of file diff --git a/include/libtropic.h b/include/libtropic.h index e55e72aa6..4689c5a6a 100644 --- a/include/libtropic.h +++ b/include/libtropic.h @@ -4,7 +4,8 @@ /** * @defgroup libtropic_API 1. Libtropic API * @brief Expected to be used by an application - * @details Dear users, please use this API. It contains all functions you need to interface with TROPIC01 device. + * @details Dear users, please use this API. It contains all functions you need to interface with + * TROPIC01 device. * @{ */ @@ -27,13 +28,15 @@ extern "C" { /** * @brief Initialize handle and transport layer. - * @note If the function fails, `lt_deinit` must not be called. In this case, the function handles the cleanup itself. + * @note If the function fails, `lt_deinit()` must not be called. In this case, the function handles + * the cleanup itself. * * @param h Handle for communication with TROPIC01 * - * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval LT_OK Function executed successfully and TROPIC01 is running Application FW, if + * it is valid. + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value * */ lt_ret_t lt_init(lt_handle_t *h); @@ -49,8 +52,8 @@ lt_ret_t lt_init(lt_handle_t *h); * @param h Handle for communication with TROPIC01 * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_deinit(lt_handle_t *h); @@ -62,8 +65,8 @@ lt_ret_t lt_deinit(lt_handle_t *h); * @param[out] mode Current mode of TROPIC01 * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose - * encoding of returned value. The `mode` parameter should **not** be considered valid. + * @retval other Function did not execute successully, you might use lt_ret_verbose() to + * get verbose encoding of returned value. The `mode` parameter should **not** be considered valid. */ lt_ret_t lt_get_tr01_mode(lt_handle_t *h, lt_tr01_mode_t *mode); @@ -74,8 +77,8 @@ lt_ret_t lt_get_tr01_mode(lt_handle_t *h, lt_tr01_mode_t *mode); * @param store Certificate store handle to be filled * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_get_info_cert_store(lt_handle_t *h, struct lt_cert_store_t *store); @@ -83,12 +86,12 @@ lt_ret_t lt_get_info_cert_store(lt_handle_t *h, struct lt_cert_store_t *store); * @brief Extracts ST_Pub from TROPIC01's Certificate Store * * @param store Certificate store handle - * @param stpub When the function executes successfully, TROPIC01's STPUB of length `TR01_STPUB_LEN` will be - * written into this buffer + * @param stpub When the function executes successfully, TROPIC01's STPUB of length + * `TR01_STPUB_LEN` will be written into this buffer * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_get_st_pub(const struct lt_cert_store_t *store, uint8_t *stpub); @@ -103,8 +106,8 @@ lt_ret_t lt_get_st_pub(const struct lt_cert_store_t *store, uint8_t *stpub); * @param chip_id Structure which holds all fields of CHIP ID * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_get_info_chip_id(lt_handle_t *h, struct lt_chip_id_t *chip_id); @@ -115,8 +118,8 @@ lt_ret_t lt_get_info_chip_id(lt_handle_t *h, struct lt_chip_id_t *chip_id); * @param ver Buffer for FW version bytes with size `TR01_L2_GET_INFO_RISCV_FW_SIZE` * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_get_info_riscv_fw_ver(lt_handle_t *h, uint8_t *ver); @@ -127,15 +130,16 @@ lt_ret_t lt_get_info_riscv_fw_ver(lt_handle_t *h, uint8_t *ver); * @param ver Buffer for SPECT version bytes with size `TR01_L2_GET_INFO_SPECT_FW_SIZE` * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_get_info_spect_fw_ver(lt_handle_t *h, uint8_t *ver); /** * @brief Read TROPIC01's firmware bank info * - * @note Reported git hashes will not match for certain old firmware versions, see documentation for details. + * @note Reported git hashes will not match for certain old firmware versions, see documentation for + * details. * * @param h Handle for communication with TROPIC01 * @param bank_id ID of firmware bank (one from enum lt_bank_id_t) @@ -144,8 +148,8 @@ lt_ret_t lt_get_info_spect_fw_ver(lt_handle_t *h, uint8_t *ver); * @param header_read_size Number of bytes read into the header buffer * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_get_info_fw_bank(lt_handle_t *h, const lt_bank_id_t bank_id, uint8_t *header, const uint16_t header_max_size, uint16_t *header_read_size); @@ -153,10 +157,10 @@ lt_ret_t lt_get_info_fw_bank(lt_handle_t *h, const lt_bank_id_t bank_id, uint8_t /** * @brief Establishes encrypted secure session between TROPIC01 and host MCU * - * @note To successfully estabilish Secure Session, you need to know Tropic01's X25519 public key. - * (STPUB). The STPUB can be obtained using lt_get_st_pub, or you can use - * lt_verify_chip_and_start_secure_session helper function, which will obtain the STPUB - * automatically and set up the Secure Session for you. + * @note To successfully estabilish Secure Session, you need to know Tropic01's X25519 + * public key. (STPUB). The STPUB can be obtained using lt_get_st_pub, or you can use + * lt_verify_chip_and_start_secure_session helper function, which will obtain the + * STPUB automatically and set up the Secure Session for you. * * @param h Handle for communication with TROPIC01 * @param stpub STPUB from device's certificate @@ -165,8 +169,8 @@ lt_ret_t lt_get_info_fw_bank(lt_handle_t *h, const lt_bank_id_t bank_id, uint8_t * @param shipub Secure host public key * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_session_start(lt_handle_t *h, const uint8_t *stpub, const lt_pkey_index_t pkey_index, const uint8_t *shipriv, const uint8_t *shipub); @@ -182,8 +186,8 @@ lt_ret_t lt_session_start(lt_handle_t *h, const uint8_t *stpub, const lt_pkey_in * @param h Handle for communication with TROPIC01 * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_session_abort(lt_handle_t *h); @@ -194,8 +198,8 @@ lt_ret_t lt_session_abort(lt_handle_t *h); * @param sleep_kind Kind of sleep * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_sleep(lt_handle_t *h, const uint8_t sleep_kind); @@ -206,8 +210,8 @@ lt_ret_t lt_sleep(lt_handle_t *h, const uint8_t sleep_kind); * @param startup_id Startup ID (determines into which mode will TROPIC01 reboot) * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_reboot(lt_handle_t *h, const lt_startup_id_t startup_id); @@ -221,8 +225,8 @@ lt_ret_t lt_reboot(lt_handle_t *h, const lt_startup_id_t startup_id); * @param bank_id enum lt_bank_id_t * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_mutable_fw_erase(lt_handle_t *h, const lt_bank_id_t bank_id); @@ -234,7 +238,8 @@ lt_ret_t lt_mutable_fw_erase(lt_handle_t *h, const lt_bank_id_t bank_id); * @param fw_data_size Number of firmware's bytes in passed array * @param bank_id enum lt_bank_id_t * lt_ret_t LT_OK - SUCCESS - * other parameters - ERROR, for verbose output pass return value to function lt_ret_verbose() + * other parameters - ERROR, for verbose output pass return value to function + * lt_ret_verbose() */ lt_ret_t lt_mutable_fw_update(lt_handle_t *h, const uint8_t *fw_data, const uint16_t fw_data_size, lt_bank_id_t bank_id); @@ -261,13 +266,15 @@ lt_ret_t lt_mutable_fw_update(lt_handle_t *h, const uint8_t *update_request); * @param update_data_size Size of update data * @return LT_OK if success, otherwise returns other error code. */ -lt_ret_t lt_mutable_fw_update_data(lt_handle_t *h, const uint8_t *update_data, const uint16_t update_data_size); +lt_ret_t lt_mutable_fw_update_data(lt_handle_t *h, const uint8_t *update_data, + const uint16_t update_data_size); #endif /** * @brief Gets Log message of TROPIC01's RISC-V FW (if enabled/available). - * @note RISC-V FW logging can be disabled in the I/R-Config and for the production chips, it **will** be disabled. This - * function is used mainly for internal debugging and not expected to be used by the user. + * @note RISC-V FW logging can be disabled in the I/R-Config and for the production chips, it **will** + * be disabled. This function is used mainly for internal debugging and not expected to be used by the + * user. * * @param h Handle for communication with TROPIC01 * @param log_msg Buffer for the log message (atleast 255B) @@ -275,14 +282,15 @@ lt_ret_t lt_mutable_fw_update_data(lt_handle_t *h, const uint8_t *update_data, c * @param log_msg_read_size Number of bytes read into the log message buffer * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ -lt_ret_t lt_get_log_req(lt_handle_t *h, uint8_t *log_msg, const uint16_t log_msg_max_size, uint16_t *log_msg_read_size); +lt_ret_t lt_get_log_req(lt_handle_t *h, uint8_t *log_msg, const uint16_t log_msg_max_size, + uint16_t *log_msg_read_size); /** - * @brief A dummy command to check the Secure Channel Session communication by exchanging a message with TROPIC01, whish - * is echoed through the Secure Channel. + * @brief A dummy command to check the Secure Channel Session communication by exchanging a message + * with TROPIC01, whish is echoed through the Secure Channel. * * @param h Handle for communication with TROPIC01 * @param msg_out Ping message going out @@ -290,26 +298,26 @@ lt_ret_t lt_get_log_req(lt_handle_t *h, uint8_t *log_msg, const uint16_t log_msg * @param msg_len Length of both messages (msg_out and msg_in) * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_ping(lt_handle_t *h, const uint8_t *msg_out, uint8_t *msg_in, const uint16_t msg_len); /** * @brief Writes pairing public key into TROPIC01's pairing key slot 0-3 - * @warning The pairing keys reside in I-Memory, which has narrower operating temperature range (-20 °C to 85 °C) than - * the rest of TROPIC01. New CPU firmware versions (v2.0.0 and newer) return error when the operation is unsuccessful, - * but with older firmwares the operation fails silently. If you use CPU firmware older than v2.0.0, make sure to - * manually check whether the pairing key was correctly written if operating outside this range. Refer to datasheet for - * absolute maximum ratings. + * @warning The pairing keys reside in I-Memory, which has narrower operating temperature range (-20 °C + * to 85 °C) than the rest of TROPIC01. New CPU firmware versions (v2.0.0 and newer) return error when + * the operation is unsuccessful, but with older firmwares the operation fails silently. If you use CPU + * firmware older than v2.0.0, make sure to manually check whether the pairing key was correctly + * written if operating outside this range. Refer to datasheet for absolute maximum ratings. * * @param h Handle for communication with TROPIC01 * @param pairing_pub 32B of pubkey * @param slot Pairing key lot SH0PUB - SH3PUB * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_pairing_key_write(lt_handle_t *h, const uint8_t *pairing_pub, const uint8_t slot); @@ -321,31 +329,31 @@ lt_ret_t lt_pairing_key_write(lt_handle_t *h, const uint8_t *pairing_pub, const * @param slot Pairing key lot SH0PUB - SH3PUB * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_pairing_key_read(lt_handle_t *h, uint8_t *pairing_pub, const uint8_t slot); /** * @brief Invalidates pairing key in slot 0-3 - * @warning The pairing keys reside in I-Memory, which has narrower operating temperature range (-20 °C to 85 °C) than - * the rest of TROPIC01. New CPU firmware versions (v2.0.0 and newer) return error when the operation is unsuccessful, - * but with older firmwares the operation fails silently. If you use CPU firmware older than v2.0.0, make sure to - * manually check whether the pairing key was correctly invalidated if operating outside this range. Refer to datasheet - * for absolute maximum ratings. + * @warning The pairing keys reside in I-Memory, which has narrower operating temperature range (-20 °C + * to 85 °C) than the rest of TROPIC01. New CPU firmware versions (v2.0.0 and newer) return error when + * the operation is unsuccessful, but with older firmwares the operation fails silently. If you use CPU + * firmware older than v2.0.0, make sure to manually check whether the pairing key was correctly + * invalidated if operating outside this range. Refer to datasheet for absolute maximum ratings. * * @param h Handle for communication with TROPIC01 * @param slot Pairing key lot SH0PUB - SH3PUB * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_pairing_key_invalidate(lt_handle_t *h, const uint8_t slot); /** - * @brief Writes configuration object specified by `addr`. Make sure to read the Configuration Objects Application Note - * (ODN_TR01_app_006) to see how to handle the R-config before proceeding. + * @brief Writes configuration object specified by `addr`. Make sure to read the Configuration Objects + * Application Note (ODN_TR01_app_006) to see how to handle the R-config before proceeding. * * @warning Writing R-config before erasing it first can brick the TROPIC01 chip. Refer to Erratum * OI_TR01_ERR_2026010800: R-Config write triggers permanent Alarm Mode. @@ -355,55 +363,56 @@ lt_ret_t lt_pairing_key_invalidate(lt_handle_t *h, const uint8_t slot); * @param obj Content to be written * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_r_config_write(lt_handle_t *h, const enum lt_config_obj_addr_t addr, const uint32_t obj); /** - * @brief Reads configuration object specified by `addr`. Make sure to read the Configuration Objects Application Note - * (ODN_TR01_app_006) to see how to handle the R-config before proceeding. + * @brief Reads configuration object specified by `addr`. Make sure to read the Configuration Objects + * Application Note (ODN_TR01_app_006) to see how to handle the R-config before proceeding. * * @param h Handle for communication with TROPIC01 * @param addr Address of a config object * @param obj Variable to read content into * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value * */ lt_ret_t lt_r_config_read(lt_handle_t *h, const enum lt_config_obj_addr_t addr, uint32_t *obj); /** - * @brief Erases all configuration objects. Make sure to read the Configuration Objects Application Note - * (ODN_TR01_app_006) to see how to handle the R-config before proceeding. + * @brief Erases all configuration objects. Make sure to read the Configuration Objects Application + * Note (ODN_TR01_app_006) to see how to handle the R-config before proceeding. * * @param h Handle for communication with TROPIC01 * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_r_config_erase(lt_handle_t *h); /** * @brief Writes configuration object specified by `addr` to I-Config - * @warning The I-Config resides in I-Memory, which has narrower operating temperature range (-20 °C to 85 °C) than - * the rest of TROPIC01. New CPU firmware versions (v2.0.0 and newer) return error when the operation is unsuccessful, - * but with older firmwares the operation fails silently. If you use CPU firmware older than v2.0.0, make sure to - * manually check whether the I-Config was correctly written if operating outside this range. Refer to datasheet for - * absolute maximum ratings. + * @warning The I-Config resides in I-Memory, which has narrower operating temperature range (-20 °C to + * 85 °C) than the rest of TROPIC01. New CPU firmware versions (v2.0.0 and newer) return error when the + * operation is unsuccessful, but with older firmwares the operation fails silently. If you use CPU + * firmware older than v2.0.0, make sure to manually check whether the I-Config was correctly written + * if operating outside this range. Refer to datasheet for absolute maximum ratings. * * @param h Handle for communication with TROPIC01 * @param addr Address of a config object * @param bit_index Index of bit to write from 1 to 0 * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ -lt_ret_t lt_i_config_write(lt_handle_t *h, const enum lt_config_obj_addr_t addr, const uint8_t bit_index); +lt_ret_t lt_i_config_write(lt_handle_t *h, const enum lt_config_obj_addr_t addr, + const uint8_t bit_index); /** * @brief Reads configuration object specified by `addr` from I-Config @@ -413,8 +422,8 @@ lt_ret_t lt_i_config_write(lt_handle_t *h, const enum lt_config_obj_addr_t addr, * @param obj Variable to read content into * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_i_config_read(lt_handle_t *h, const enum lt_config_obj_addr_t addr, uint32_t *obj); @@ -424,14 +433,15 @@ lt_ret_t lt_i_config_read(lt_handle_t *h, const enum lt_config_obj_addr_t addr, * @param h Handle for communication with TROPIC01 * @param udata_slot Memory's slot to be written * @param data Buffer of data to be written into R MEMORY slot - * @param data_size Size of data to be written (valid range given by macros `TR01_R_MEM_DATA_SIZE_MIN` and - * `TR01_R_MEM_DATA_SIZE_MAX`) + * @param data_size Size of data to be written (valid range given by macros + * `TR01_R_MEM_DATA_SIZE_MIN` and `TR01_R_MEM_DATA_SIZE_MAX`) * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ -lt_ret_t lt_r_mem_data_write(lt_handle_t *h, const uint16_t udata_slot, const uint8_t *data, const uint16_t data_size); +lt_ret_t lt_r_mem_data_write(lt_handle_t *h, const uint16_t udata_slot, const uint8_t *data, + const uint16_t data_size); /** * @brief Reads bytes from a given slot of the User Partition in the R memory @@ -443,11 +453,11 @@ lt_ret_t lt_r_mem_data_write(lt_handle_t *h, const uint16_t udata_slot, const ui * @param data_read_size Number of bytes read into data buffer * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ -lt_ret_t lt_r_mem_data_read(lt_handle_t *h, const uint16_t udata_slot, uint8_t *data, const uint16_t data_max_size, - uint16_t *data_read_size); +lt_ret_t lt_r_mem_data_read(lt_handle_t *h, const uint16_t udata_slot, uint8_t *data, + const uint16_t data_max_size, uint16_t *data_read_size); /** * @brief Erases the given slot of the User Partition in the R memory @@ -456,8 +466,8 @@ lt_ret_t lt_r_mem_data_read(lt_handle_t *h, const uint16_t udata_slot, uint8_t * * @param udata_slot Memory's slot to be erased * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_r_mem_data_erase(lt_handle_t *h, const uint16_t udata_slot); @@ -469,8 +479,8 @@ lt_ret_t lt_r_mem_data_erase(lt_handle_t *h, const uint16_t udata_slot); * @param rnd_bytes_cnt Number of random bytes to get (255 bytes is the maximum) * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose - * encoding of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() + * to get verbose encoding of returned value */ lt_ret_t lt_random_value_get(lt_handle_t *h, uint8_t *rnd_bytes, const uint16_t rnd_bytes_cnt); @@ -479,25 +489,28 @@ lt_ret_t lt_random_value_get(lt_handle_t *h, uint8_t *rnd_bytes, const uint16_t * * @param h Handle for communication with TROPIC01 * @param slot Slot number lt_ecc_slot_t - * @param curve Type of ECC curve. Use L3_ECC_KEY_GENERATE_CURVE_ED25519 or L3_ECC_KEY_GENERATE_CURVE_P256 + * @param curve Type of ECC curve. Use L3_ECC_KEY_GENERATE_CURVE_ED25519 or + * L3_ECC_KEY_GENERATE_CURVE_P256 * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ -lt_ret_t lt_ecc_key_generate(lt_handle_t *h, const lt_ecc_slot_t slot, const lt_ecc_curve_type_t curve); +lt_ret_t lt_ecc_key_generate(lt_handle_t *h, const lt_ecc_slot_t slot, + const lt_ecc_curve_type_t curve); /** * @brief Stores ECC key to the specified ECC key slot * * @param h Handle for communication with TROPIC01 * @param slot Slot number lt_ecc_slot_t - * @param curve Type of ECC curve. Use L3_ECC_KEY_GENERATE_CURVE_ED25519 or L3_ECC_KEY_GENERATE_CURVE_P256 + * @param curve Type of ECC curve. Use L3_ECC_KEY_GENERATE_CURVE_ED25519 or + * L3_ECC_KEY_GENERATE_CURVE_P256 * @param key Key to store (only the first 32 bytes are stored) * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_ecc_key_store(lt_handle_t *h, const lt_ecc_slot_t slot, const lt_ecc_curve_type_t curve, const uint8_t *key); @@ -507,19 +520,21 @@ lt_ret_t lt_ecc_key_store(lt_handle_t *h, const lt_ecc_slot_t slot, const lt_ecc * * @param h Handle for communication with TROPIC01 * @param ecc_slot Slot number TR01_ECC_SLOT_0 - TR01_ECC_SLOT_31 - * @param key Buffer for retrieving a key; length depends on the type of key in the slot (32B for Ed25519, - * 64B for P256), according to *curve* + * @param key Buffer for retrieving a key; length depends on the type of key in the slot + * (32B for Ed25519, 64B for P256), according to *curve* * @param key_max_size Size of the key buffer - * @param curve When the function executes successfully, the type of elliptic curve public key will be written - * @param origin When the function executes successfully, the origin of the public key (generated/stored) will - * be written + * @param curve When the function executes successfully, the type of elliptic curve public key + * will be written + * @param origin When the function executes successfully, the origin of the public key + * (generated/stored) will be written * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose - * encoding of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to + * get verbose encoding of returned value */ -lt_ret_t lt_ecc_key_read(lt_handle_t *h, const lt_ecc_slot_t ecc_slot, uint8_t *key, const uint8_t key_max_size, - lt_ecc_curve_type_t *curve, lt_ecc_key_origin_t *origin); +lt_ret_t lt_ecc_key_read(lt_handle_t *h, const lt_ecc_slot_t ecc_slot, uint8_t *key, + const uint8_t key_max_size, lt_ecc_curve_type_t *curve, + lt_ecc_key_origin_t *origin); /** * @brief Erases ECC key from the specified ECC key slot @@ -528,8 +543,8 @@ lt_ret_t lt_ecc_key_read(lt_handle_t *h, const lt_ecc_slot_t ecc_slot, uint8_t * * @param ecc_slot Slot number TR01_ECC_SLOT_0 - TR01_ECC_SLOT_31 * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_ecc_key_erase(lt_handle_t *h, const lt_ecc_slot_t ecc_slot); @@ -540,14 +555,15 @@ lt_ret_t lt_ecc_key_erase(lt_handle_t *h, const lt_ecc_slot_t ecc_slot); * @param ecc_slot Slot containing a private key, TR01_ECC_SLOT_0 - TR01_ECC_SLOT_31 * @param msg Buffer containing a message * @param msg_len Length of the message - * @param rs Buffer for storing a signature in a form of R and S bytes (should always have length 64B) + * @param rs Buffer for storing a signature in a form of R and S bytes (should always have + * length 64B) * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ -lt_ret_t lt_ecc_ecdsa_sign(lt_handle_t *h, const lt_ecc_slot_t ecc_slot, const uint8_t *msg, const uint32_t msg_len, - uint8_t *rs); +lt_ret_t lt_ecc_ecdsa_sign(lt_handle_t *h, const lt_ecc_slot_t ecc_slot, const uint8_t *msg, + const uint32_t msg_len, uint8_t *rs); /** * @brief Performs EdDSA sign of a message with a private ECC key stored in TROPIC01 @@ -556,27 +572,30 @@ lt_ret_t lt_ecc_ecdsa_sign(lt_handle_t *h, const lt_ecc_slot_t ecc_slot, const u * @param ecc_slot Slot containing a private key, TR01_ECC_SLOT_0 - TR01_ECC_SLOT_31 * @param msg Buffer containing a message to sign, max length is 4096B * @param msg_len Length of the message - * @param rs Buffer for storing a signature in a form of R and S bytes (should always have length 64B) + * @param rs Buffer for storing a signature in a form of R and S bytes (should always have + * length 64B) * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ -lt_ret_t lt_ecc_eddsa_sign(lt_handle_t *h, const lt_ecc_slot_t ecc_slot, const uint8_t *msg, const uint16_t msg_len, - uint8_t *rs); +lt_ret_t lt_ecc_eddsa_sign(lt_handle_t *h, const lt_ecc_slot_t ecc_slot, const uint8_t *msg, + const uint16_t msg_len, uint8_t *rs); /** * @brief Initializes monotonic counter of a given index * * @param h Handle for communication with TROPIC01 * @param mcounter_index Index of monotonic counter - * @param mcounter_value Value to set as an initial value (allowed range is 0-`TR01_MCOUNTER_VALUE_MAX`) + * @param mcounter_value Value to set as an initial value (allowed range is + * 0-`TR01_MCOUNTER_VALUE_MAX`) * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose - * encoding of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to + * get verbose encoding of returned value */ -lt_ret_t lt_mcounter_init(lt_handle_t *h, const enum lt_mcounter_index_t mcounter_index, const uint32_t mcounter_value); +lt_ret_t lt_mcounter_init(lt_handle_t *h, const enum lt_mcounter_index_t mcounter_index, + const uint32_t mcounter_value); /** * @brief Updates monotonic counter of a given index @@ -585,8 +604,8 @@ lt_ret_t lt_mcounter_init(lt_handle_t *h, const enum lt_mcounter_index_t mcounte * @param mcounter_index Index of monotonic counter * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose - * encoding of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to + * get verbose encoding of returned value */ lt_ret_t lt_mcounter_update(lt_handle_t *h, const enum lt_mcounter_index_t mcounter_index); @@ -598,16 +617,17 @@ lt_ret_t lt_mcounter_update(lt_handle_t *h, const enum lt_mcounter_index_t mcoun * @param mcounter_value Value of monotonic counter (from range 0-`TR01_MCOUNTER_VALUE_MAX`) * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose - * encoding of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to + * get verbose encoding of returned value */ -lt_ret_t lt_mcounter_get(lt_handle_t *h, const enum lt_mcounter_index_t mcounter_index, uint32_t *mcounter_value); +lt_ret_t lt_mcounter_get(lt_handle_t *h, const enum lt_mcounter_index_t mcounter_index, + uint32_t *mcounter_value); /** * @brief Executes the MAC-and-Destroy sequence. - * @details This command is just a part of MAC And Destroy sequence, which takes place between the host and TROPIC01. - * Example code can be found in examples/lt_ex_macandd.c, for more info about Mac And Destroy functionality, - * read the Application note. + * @details This command is just a part of MAC And Destroy sequence, which takes place between the host + * and TROPIC01. Example code can be found in examples/lt_ex_macandd.c, for more info about Mac And + * Destroy functionality, read the Application note. * * @param h Handle for communication with TROPIC01 * @param slot Mac-and-Destroy slot index, valid values are 0-127 @@ -615,19 +635,19 @@ lt_ret_t lt_mcounter_get(lt_handle_t *h, const enum lt_mcounter_index_t mcounter * @param data_in Data returned from TROPIC01 to host * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ -lt_ret_t lt_mac_and_destroy(lt_handle_t *h, const lt_mac_and_destroy_slot_t slot, const uint8_t *data_out, - uint8_t *data_in); +lt_ret_t lt_mac_and_destroy(lt_handle_t *h, const lt_mac_and_destroy_slot_t slot, + const uint8_t *data_out, uint8_t *data_in); /** @} */ // end of libtropic_API group #ifdef LT_HELPERS /** * @defgroup libtropic_API_helpers 1.1. Libtropic API: Helpers - * @brief These functions are usually wrappers around one or more TROPIC01 commands, beside `lt_ret_verbose()` and - * `lt_print_bytes()`. + * @brief These functions are usually wrappers around one or more TROPIC01 commands, beside + * `lt_ret_verbose()` and `lt_print_bytes()`. * @{ */ @@ -643,14 +663,14 @@ extern struct lt_config_obj_desc_t cfg_desc_table[LT_CONFIG_OBJ_CNT]; * @param ret lt_ret_t returned type value * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ const char *lt_ret_verbose(lt_ret_t ret); /** - * @brief Writes the whole R-Config with the passed `config`. Make sure to read the Configuration Objects Application - * Note (ODN_TR01_app_006) to see how to handle the R-config before proceeding. + * @brief Writes the whole R-Config with the passed `config`. Make sure to read the Configuration + * Objects Application Note (ODN_TR01_app_006) to see how to handle the R-config before proceeding. * * @warning Writing R-config before erasing it first can brick the TROPIC01 chip. Refer to Erratum * OI_TR01_ERR_2026010800: R-Config write triggers permanent Alarm Mode. @@ -659,21 +679,21 @@ const char *lt_ret_verbose(lt_ret_t ret); * @param config Array into which objects are read * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_write_whole_R_config(lt_handle_t *h, const struct lt_config_t *config); /** - * @brief Reads all of the R-Config objects into `config`. Make sure to read the Configuration Objects Application Note - * (ODN_TR01_app_006) to see how to handle the R-config before proceeding. + * @brief Reads all of the R-Config objects into `config`. Make sure to read the Configuration Objects + * Application Note (ODN_TR01_app_006) to see how to handle the R-config before proceeding. * * @param h Handle for communication with TROPIC01 * @param config Struct into which objects are readed * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_read_whole_R_config(lt_handle_t *h, struct lt_config_t *config); @@ -684,37 +704,38 @@ lt_ret_t lt_read_whole_R_config(lt_handle_t *h, struct lt_config_t *config); * @param config Struct into which objects are readed * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_read_whole_I_config(lt_handle_t *h, struct lt_config_t *config); /** * @brief Writes the whole I-Config with the passed `config`. * @details Only the zero bits in `config` are written. - * @warning The I-Config resides in I-Memory, which has narrower operating temperature range (-20 °C to 85 °C) than - * the rest of TROPIC01. New CPU firmware versions (v2.0.0 and newer) return error when the operation is unsuccessful, - * but with older firmwares the operation fails silently. If you use CPU firmware older than v2.0.0, make sure to - * manually check whether the I-Config was correctly written if operating outside this range. Refer to datasheet for - * absolute maximum ratings. + * @warning The I-Config resides in I-Memory, which has narrower operating temperature range (-20 °C to + * 85 °C) than the rest of TROPIC01. New CPU firmware versions (v2.0.0 and newer) return error when the + * operation is unsuccessful, but with older firmwares the operation fails silently. If you use CPU + * firmware older than v2.0.0, make sure to manually check whether the I-Config was correctly written + * if operating outside this range. Refer to datasheet for absolute maximum ratings. * * @param h Handle for communication with TROPIC01 * @param config Array into which objects are read * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ lt_ret_t lt_write_whole_I_config(lt_handle_t *h, const struct lt_config_t *config); /** * @brief Establishes a secure channel between host MCU and TROPIC01 * - * @warning This function currently DOES NOT validate/verify the whole certificate chain, it just parses out STPUB from - * the device's certificate, because STPUB is used for handshake. + * @warning This function currently DOES NOT validate/verify the whole certificate chain, it just + * parses out STPUB from the device's certificate, because STPUB is used for handshake. * * To verify the whole certificate chain we recommend to download all certificates from chip by using - * lt_get_info_cert_store() and use any apropriate third party tool to verify validity of certificate chain. + * lt_get_info_cert_store() and use any apropriate third party tool to verify validity of certificate + * chain. * * @param h Handle for communication with TROPIC01 * @param shipriv Host's private pairing key for the slot `pkey_index` @@ -722,10 +743,11 @@ lt_ret_t lt_write_whole_I_config(lt_handle_t *h, const struct lt_config_t *confi * @param pkey_index Pairing key index * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ -lt_ret_t lt_verify_chip_and_start_secure_session(lt_handle_t *h, const uint8_t *shipriv, const uint8_t *shipub, +lt_ret_t lt_verify_chip_and_start_secure_session(lt_handle_t *h, const uint8_t *shipriv, + const uint8_t *shipub, const lt_pkey_index_t pkey_index); /** @@ -737,10 +759,11 @@ lt_ret_t lt_verify_chip_and_start_secure_session(lt_handle_t *h, const uint8_t * * @param out_buf_size Size of `out_buf` * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ -lt_ret_t lt_print_bytes(const uint8_t *bytes, const size_t bytes_cnt, char *out_buf, const size_t out_buf_size); +lt_ret_t lt_print_bytes(const uint8_t *bytes, const size_t bytes_cnt, char *out_buf, + const size_t out_buf_size); /** * @brief Interprets fields of CHIP_ID and prints them using the passed printf-like function. @@ -749,36 +772,41 @@ lt_ret_t lt_print_bytes(const uint8_t *bytes, const size_t bytes_cnt, char *out_ * @param print_func printf-like function to use for printing * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding - * of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get + * verbose encoding of returned value */ -lt_ret_t lt_print_chip_id(const struct lt_chip_id_t *chip_id, int (*print_func)(const char *format, ...)); +lt_ret_t lt_print_chip_id(const struct lt_chip_id_t *chip_id, + int (*print_func)(const char *format, ...)); /** * @brief Prints interpreted firmware header of the given bank using the passed printf-like function. * - * @note Reported git hashes will not match for certain old firmware versions, see documentation for details. + * @note Reported git hashes will not match for certain old firmware versions, see documentation for + * details. * * @param h Handle for communication with TROPIC01 * @param bank_id Bank ID whose header should be printed * @param print_func printf-like function to use for printing * @retval LT_OK if success, otherwise returns other error code. */ -lt_ret_t lt_print_fw_header(lt_handle_t *h, const lt_bank_id_t bank_id, int (*print_func)(const char *format, ...)); +lt_ret_t lt_print_fw_header(lt_handle_t *h, const lt_bank_id_t bank_id, + int (*print_func)(const char *format, ...)); /** * @brief Performs mutable firmware update on ABAB and ACAB silicon revisions. + * @important After this function returns successfully, the handle (`lt_handle_t`) has to be + * initialized again (i.e. calling `lt_deinit()` and `lt_init()`). * * @param h Handle for communication with TROPIC01 * @param update_data Pointer to the data to be written * @param update_data_size Size of the data to be written * @param bank_id Bank ID where the update should be applied, valid values are - * For ABAB: TR01_FW_BANK_FW1, TR01_FW_BANK_FW2, TR01_FW_BANK_SPECT1, TR01_FW_BANK_SPECT2 - * For ACAB: Parameter is ignored, chip is handling firmware banks on its own + * For ABAB: TR01_FW_BANK_FW1, TR01_FW_BANK_FW2, TR01_FW_BANK_SPECT1, + * TR01_FW_BANK_SPECT2 For ACAB: Parameter is ignored, chip is handling firmware banks on its own * @return LT_OK if success, otherwise returns other error code. */ -lt_ret_t lt_do_mutable_fw_update(lt_handle_t *h, const uint8_t *update_data, const uint16_t update_data_size, - const lt_bank_id_t bank_id); +lt_ret_t lt_do_mutable_fw_update(lt_handle_t *h, const uint8_t *update_data, + const uint16_t update_data_size, const lt_bank_id_t bank_id); /** @} */ // end of libtropic_API_helpers group #endif diff --git a/include/libtropic_common.h b/include/libtropic_common.h index a57801a50..eb455d5d6 100644 --- a/include/libtropic_common.h +++ b/include/libtropic_common.h @@ -55,11 +55,12 @@ extern "C" { #define TR01_L2_CHUNK_MAX_DATA_SIZE 252u /** * @brief Maximal size of one l2 frame - * @note This macro corresponds to both L2 Request and Response frame, so for the first addend, we could also use - * TR01_L2_REQ_ID_SIZE. + * @note This macro corresponds to both L2 Request and Response frame, so for the first addend, we + * could also use TR01_L2_REQ_ID_SIZE. */ -#define TR01_L2_MAX_FRAME_SIZE \ - (TR01_L2_STATUS_SIZE + TR01_L2_REQ_RSP_LEN_SIZE + TR01_L2_CHUNK_MAX_DATA_SIZE + TR01_L2_REQ_RSP_CRC_SIZE) +#define TR01_L2_MAX_FRAME_SIZE \ + (TR01_L2_STATUS_SIZE + TR01_L2_REQ_RSP_LEN_SIZE + TR01_L2_CHUNK_MAX_DATA_SIZE + \ + TR01_L2_REQ_RSP_CRC_SIZE) /** @brief Size of IV. */ #define TR01_L3_IV_SIZE 12u @@ -85,7 +86,8 @@ extern "C" { #define TR01_L3_RES_CIPHERTEXT_MAX_SIZE 4097u /** @brief Max size of ciphertext for both L3 Commands and L3 Responses. */ -#define TR01_L3_CIPHERTEXT_MAX_SIZE LT_COMPTIME_MAX(TR01_L3_CMD_CIPHERTEXT_MAX_SIZE, TR01_L3_RES_CIPHERTEXT_MAX_SIZE) +#define TR01_L3_CIPHERTEXT_MAX_SIZE \ + LT_COMPTIME_MAX(TR01_L3_CMD_CIPHERTEXT_MAX_SIZE, TR01_L3_RES_CIPHERTEXT_MAX_SIZE) /** * @brief Max possible size of one unit of transport on L3 (for both Commands and Responses). @@ -93,39 +95,39 @@ extern "C" { #define TR01_L3_PACKET_MAX_SIZE (TR01_L3_SIZE_SIZE + TR01_L3_CIPHERTEXT_MAX_SIZE + TR01_L3_TAG_SIZE) /** - * @brief Host MCU's X25519 private key to execute a Secure Channel Handshake on Pairing Key slot 0 of the engineering - * (pre-production) TROPIC01 samples. + * @brief Host MCU's X25519 private key to execute a Secure Channel Handshake on Pairing Key slot 0 of + * the engineering (pre-production) TROPIC01 samples. * - * @note This key should be used for the first Secure Channel Handshake and we recommend invalidating the slot 0 after - * you write your own pairing key to another slot. Refer to the section 5.4 (Security Lifecycle Management) in the - * datasheet for more information. + * @note This key should be used for the first Secure Channel Handshake and we recommend invalidating + * the slot 0 after you write your own pairing key to another slot. Refer to the section 5.4 (Security + * Lifecycle Management) in the datasheet for more information. */ extern const uint8_t sh0priv_eng_sample[]; /** - * @brief Host MCU's X25519 public key (stored in TROPIC01) to execute a Secure Channel Handshake on Pairing Key slot 0 - * of the engineering (pre-production) TROPIC01 samples. + * @brief Host MCU's X25519 public key (stored in TROPIC01) to execute a Secure Channel Handshake on + * Pairing Key slot 0 of the engineering (pre-production) TROPIC01 samples. * - * @note This key should be used for the first Secure Channel Handshake and we recommend invalidating the slot 0 after - * you write your own pairing key to another slot. Refer to the section 5.4 (Security Lifecycle Management) in the - * datasheet for more information. + * @note This key should be used for the first Secure Channel Handshake and we recommend invalidating + * the slot 0 after you write your own pairing key to another slot. Refer to the section 5.4 (Security + * Lifecycle Management) in the datasheet for more information. */ extern const uint8_t sh0pub_eng_sample[]; /** - * @brief Host MCU's X25519 private key to execute a Secure Channel Handshake on Pairing Key slot 0 of the production - * TROPIC01 chips. + * @brief Host MCU's X25519 private key to execute a Secure Channel Handshake on Pairing Key slot 0 of + * the production TROPIC01 chips. * - * @note This key should be used for the first Secure Channel Handshake and we recommend invalidating the slot 0 after - * you write your own pairing key to another slot. Refer to the section 5.4 (Security Lifecycle Management) in the - * datasheet for more information. + * @note This key should be used for the first Secure Channel Handshake and we recommend invalidating + * the slot 0 after you write your own pairing key to another slot. Refer to the section 5.4 (Security + * Lifecycle Management) in the datasheet for more information. */ extern const uint8_t sh0priv_prod0[]; /** - * @brief Host MCU's X25519 public key (stored in TROPIC01) to execute a Secure Channel Handshake on Pairing Key slot 0 - * of the production TROPIC01 chips. + * @brief Host MCU's X25519 public key (stored in TROPIC01) to execute a Secure Channel Handshake on + * Pairing Key slot 0 of the production TROPIC01 chips. * - * @note This key should be used for the first Secure Channel Handshake and we recommend invalidating the slot 0 after - * you write your own pairing key to another slot. Refer to the section 5.4 (Security Lifecycle Management) in the - * datasheet for more information. + * @note This key should be used for the first Secure Channel Handshake and we recommend invalidating + * the slot 0 after you write your own pairing key to another slot. Refer to the section 5.4 (Security + * Lifecycle Management) in the datasheet for more information. */ extern const uint8_t sh0pub_prod0[]; @@ -154,23 +156,25 @@ LT_STATIC_ASSERT( // clang-format on //--------------------------------------------------------------------------------------------------------------------// -/** @brief Values for the Startup_Req command, which TROPIC01 uses to determine the mode to reboot into. */ +/** @brief Values for the Startup_Req command, which TROPIC01 uses to determine the mode to reboot + * into. */ typedef enum lt_startup_id_t { - TR01_REBOOT = 0x01, /**< Restart, then initialize as if a power-cycle was applied. */ - TR01_MAINTENANCE_REBOOT - = 0x03 /**< Restart, then initialize. Stay in Start-up mode and do not load the mutable FW from R-Memory. */ + TR01_REBOOT = 0x01, /**< Restart, then initialize as if a power-cycle was applied. */ + TR01_MAINTENANCE_REBOOT = 0x03 /**< Restart, then initialize. Stay in Start-up mode and do not load + the mutable FW from R-Memory. */ } lt_startup_id_t; /** - * @brief Interprets TROPIC01's **Chip Modes** and **CHIP_STATUS** values (described in the TROPIC01 datasheet) and - * defines new modes (not described in the TROPIC01 datasheet) based on them. These modes are practical when working - * with the chip. + * @brief Interprets TROPIC01's **Chip Modes** and **CHIP_STATUS** values (described in the TROPIC01 + * datasheet) and defines new modes (not described in the TROPIC01 datasheet) based on them. These + * modes are practical when working with the chip. * */ typedef enum lt_tr01_mode_t { /** - * @brief TROPIC01 is in Maintenance Mode (defined by Libtropic), if it is not running Application FW and is ready - * to accept L2 Requests defined by the Bootloader API (refer to the TROPIC01 User API). + * @brief TROPIC01 is in Maintenance Mode (defined by Libtropic), if it is not running Application + * FW and is ready to accept L2 Requests defined by the Bootloader API (refer to the TROPIC01 User + * API). * * Values of **Chip Mode** and **CHIP_STATUS** from the datasheet: * @@ -181,8 +185,9 @@ typedef enum lt_tr01_mode_t { */ LT_TR01_MAINTENANCE, /** - * @brief TROPIC01 is in Application Mode (defined by Libtropic), if it is running Application FW and is ready to - * accept L2 Requests or L3 Commands defined by the Application API (refer to the TROPIC01 User API). + * @brief TROPIC01 is in Application Mode (defined by Libtropic), if it is running Application FW + * and is ready to accept L2 Requests or L3 Commands defined by the Application API (refer to the + * TROPIC01 User API). * * Values of **Chip Mode** and **CHIP_STATUS** from the datasheet: * @@ -193,8 +198,8 @@ typedef enum lt_tr01_mode_t { */ LT_TR01_APPLICATION, /** - * @brief TROPIC01 is in Alarm Mode (defined by Libtropic) if the values of **Chip Mode** and **CHIP_STATUS** from - * the datasheet are: + * @brief TROPIC01 is in Alarm Mode (defined by Libtropic) if the values of **Chip Mode** and + * **CHIP_STATUS** from the datasheet are: * * - **Chip Mode**: Alarm * @@ -254,8 +259,8 @@ typedef struct lt_tr01_attrs_t { /** * @details This structure holds data related to one physical chip. - * Contains AESGCM contexts for encrypting and decrypting L3 commands, nonce and device void pointer, which can be used - * for passing arbitrary data. + * Contains AESGCM contexts for encrypting and decrypting L3 commands, nonce and device void pointer, + * which can be used for passing arbitrary data. */ typedef struct lt_handle_t { lt_l2_state_t l2; @@ -279,16 +284,17 @@ typedef enum lt_ret_t { /** @brief Error detected during cryptographic operation */ LT_CRYPTO_ERR = 4, /** - * @brief TROPIC01's Application FW is too new for the current version of Libtropic. Please update Libtropic to a - * newer release version. + * @brief TROPIC01's Application FW is too new for the current version of Libtropic. Please update + * Libtropic to a newer release version. */ LT_APP_FW_TOO_NEW = 5, - /** @brief TROPIC01 executed the Startup_Req L2 Request (invoked by calling `lt_reboot()`) successfully, but the - mode TROPIC01 is in after the reboot is not the expected one based on the `startup_id` argument: + /** @brief TROPIC01 executed the Startup_Req L2 Request (invoked by calling `lt_reboot()`) + successfully, but the mode TROPIC01 is in after the reboot is not the expected one based on the + `startup_id` argument: - - `startup_id`==`TR01_REBOOT` and TROPIC01's mode after successful reboot is **not** `LT_TR01_APPLICATION` (this - can e.g. happen when the chip, for some reason, cannot execute the Application FW - it will stay in Start-up Mode - no matter the `startup_id`), or + - `startup_id`==`TR01_REBOOT` and TROPIC01's mode after successful reboot is **not** + `LT_TR01_APPLICATION` (this can e.g. happen when the chip, for some reason, cannot execute the + Application FW - it will stay in Start-up Mode no matter the `startup_id`), or - `startup_id`==`TR01_MAINTENANCE_REBOOT` and TROPIC01's mode after successful reboot is **not** `LT_TR01_MAINTENANCE`. @@ -313,14 +319,17 @@ typedef enum lt_ret_t { LT_L3_SLOT_NOT_EMPTY = 13, /** @brief L3 result [API R_Mem_Data_Write]: The target FLASH slot has expired. */ LT_L3_SLOT_EXPIRED = 14, - /** @brief L3 result [API EDDSA_Sign, ECDSA_Sign, ECC_Key_Read]: The key in selected slot is invalid or corrupted. + /** @brief L3 result [API EDDSA_Sign, ECDSA_Sign, ECC_Key_Read]: The key in selected slot is + * invalid or corrupted. */ LT_L3_INVALID_KEY = 15, /** @brief L3 result [API MCounter_Update]: Update operation failed (i.e. mcounter done at 0). */ LT_L3_UPDATE_ERR = 16, - /** @brief L3 result [API MCounter_Update, MCounter_Get]: The Monotonic Counter is disabled or locked. */ + /** @brief L3 result [API MCounter_Update, MCounter_Get]: The Monotonic Counter is disabled or + locked. */ LT_L3_COUNTER_INVALID = 17, - /** @brief L3 result [API Pairing_Key_Read]: The requested slot is empty and contains no valid data. */ + /** @brief L3 result [API Pairing_Key_Read]: The requested slot is empty and contains no valid + data. */ LT_L3_SLOT_EMPTY = 18, /** @brief L3 result [API Pairing_Key_Read]: The slot content is invalidated. */ LT_L3_SLOT_INVALID = 19, @@ -332,8 +341,8 @@ typedef enum lt_ret_t { LT_L3_UNAUTHORIZED = 22, /** @brief Unknown L3 Command packet. */ LT_L3_INVALID_CMD = 23, - /** @brief L3 result [API Pairing_Key_Write, Pairing_Key_Invalidate, R_Config_Write, I_Config_Write, - R_Mem_Data_Write]: A hardware error occurred during a write operation. */ + /** @brief L3 result [API Pairing_Key_Write, Pairing_Key_Invalidate, R_Config_Write, + I_Config_Write, R_Mem_Data_Write]: A hardware error occurred during a write operation. */ LT_L3_HARDWARE_FAIL = 24, // Libtropic's return values for the L3 Layer. @@ -473,7 +482,8 @@ LT_STATIC_ASSERT( #define TR01_FAB_ID_EPS_BRNO 0x001 /** - * @brief Data in this struct comes from BP (batch package) yml file. CHIP_INFO is read into this struct. + * @brief Data in this struct comes from BP (batch package) yml file. CHIP_INFO is read into this + * struct. */ typedef struct lt_chip_id_t { /** @@ -490,7 +500,8 @@ typedef struct lt_chip_id_t { /** * @brief Manufacturing level test info (128 bits), structure retrieved from test line and BP. - * @details The exact copy of first two words of MAN_FUNC_TEST structure. In case of missing, it is filled with 0x00 + * @details The exact copy of first two words of MAN_FUNC_TEST structure. In case of missing, it is + * filled with 0x00 */ uint8_t func_test_info[8]; @@ -630,8 +641,9 @@ typedef enum lt_bank_id_t { } lt_bank_id_t; /** - * @brief When in MAINTENANCE mode, it is possible to read firmware header from a firmware bank. Returned data differs - * based on bootloader version. This header layout is returned by bootloader version v1.0.1 + * @brief When in MAINTENANCE mode, it is possible to read firmware header from a firmware bank. + * Returned data differs based on bootloader version. This header layout is returned by bootloader + * version v1.0.1 */ typedef struct lt_header_boot_v1_t { uint8_t type[4]; @@ -658,8 +670,9 @@ LT_STATIC_ASSERT( // clang-format on /** - * @brief When in MAINTENANCE mode, it is possible to read firmware header from a firmware bank. Returned data differs - * based on bootloader version. This header layout is returned by bootloader version v2.0.1 + * @brief When in MAINTENANCE mode, it is possible to read firmware header from a firmware bank. + * Returned data differs based on bootloader version. This header layout is returned by bootloader + * version v2.0.1 */ typedef struct lt_header_boot_v2_t { /** @brief Currently only two types supported: @@ -678,8 +691,8 @@ typedef struct lt_header_boot_v2_t { uint32_t git_hash; /** @brief Hash for data integrity (SHA256, 32B). */ uint8_t hash[32]; - /** @brief Other FW version compatibility. In case RISCV FW there may be SPECT version to match. Zero means any - * version.*/ + /** @brief Other FW version compatibility. In case RISCV FW there may be SPECT version to match. + * Zero means any version.*/ uint32_t pair_version; } __attribute__((packed)) lt_header_boot_v2_t; @@ -720,8 +733,8 @@ typedef struct lt_host_eph_keys_t { /** @brief Length of key used in X25519 function. * - * ECDH uses X25519 function with Curve25519 -> 32 bytes. See "Variables" section in GLOSSARY in TROPIC01 datasheet. - * This is the same for stpub, ehpriv, ehpub. + * ECDH uses X25519 function with Curve25519 -> 32 bytes. See "Variables" section in GLOSSARY in + * TROPIC01 datasheet. This is the same for stpub, ehpriv, ehpub. */ #define TR01_X25519_KEY_LEN 32 @@ -735,12 +748,15 @@ typedef struct lt_host_eph_keys_t { #define TR01_STPUB_LEN TR01_X25519_KEY_LEN /** @brief Length of TROPIC01 X25519 private key for a Secure Channel Handshake. */ #define TR01_STPRIV_LEN TR01_X25519_KEY_LEN -/** @brief Length of X25519 public key of the Host MCU to execute a Secure Channel Handshake on Pairing Key slot i. +/** @brief Length of X25519 public key of the Host MCU to execute a Secure Channel Handshake on Pairing + * Key slot i. * - * @note In other words, SHiPUB is also a length of the key that is stored in pairing key slots in TROPIC01. + * @note In other words, SHiPUB is also a length of the key that is stored in pairing key slots in + * TROPIC01. */ #define TR01_SHIPUB_LEN TR01_X25519_KEY_LEN -/** @brief Length of X25519 private key of the Host MCU to execute a Secure Channel Handshake on Pairing Key slot i. */ +/** @brief Length of X25519 private key of the Host MCU to execute a Secure Channel Handshake on + * Pairing Key slot i. */ #define TR01_SHIPRIV_LEN TR01_X25519_KEY_LEN /** @brief Length of TROPIC01 ephemeral private key. */ diff --git a/include/libtropic_l2.h b/include/libtropic_l2.h index a4829e6d6..98e2326ad 100644 --- a/include/libtropic_l2.h +++ b/include/libtropic_l2.h @@ -24,8 +24,8 @@ extern "C" { /** * @brief Sends L2 request. - * @note Before calling this function, place request's data into handle's internal L2 buffer. Structures defined in - * lt_l2_api_structs.h might help with encoding the data. + * @note Before calling this function, place request's data into handle's internal L2 buffer. + * Structures defined in lt_l2_api_structs.h might help with encoding the data. * * @param s2 Structure holding l2 state * diff --git a/include/libtropic_l3.h b/include/libtropic_l3.h index 7620ed6ee..160552e94 100644 --- a/include/libtropic_l3.h +++ b/include/libtropic_l3.h @@ -3,13 +3,14 @@ /** * @defgroup libtropic_l3 4. Layer 3 - * @brief Expected to be used by an application when using separate calls for L3 data out and L3 data in - * @details This module provides functions for separate L3 communication with TROPIC01. Function prepended with - * 'lt_out__' are used to prepare data for sending to TROPIC01, while functions prepended with 'lt_in__' are used to - * decode data received from TROPIC01. + * @brief Expected to be used by an application when using separate calls for L3 data out and L3 data + * in + * @details This module provides functions for separate L3 communication with TROPIC01. Function + * prepended with 'lt_out__' are used to prepare data for sending to TROPIC01, while functions + * prepended with 'lt_in__' are used to decode data received from TROPIC01. * - * Sending and receiving data is done through L2 layer, which is not covered by this module and user is expected to call - * lt_l2_send() at the point when data is ready to be sent to TROPIC01. + * Sending and receiving data is done through L2 layer, which is not covered by this module and user is + * expected to call lt_l2_send() at the point when data is ready to be sent to TROPIC01. * * For more information have a look into `libtropic.c`, how separate calls are used in a single call. * @{ @@ -40,29 +41,32 @@ extern "C" { * * @param h Handle for communication with TROPIC01 * @param pkey_index Index of pairing public key - * @param host_eph_keys Host MCU ephemeral keys, used to finish secure session establishment in lt_in__session_start(). + * @param host_eph_keys Host MCU ephemeral keys, used to finish secure session establishment in + * lt_in__session_start(). * @return LT_OK if success, otherwise returns other error code. */ -lt_ret_t lt_out__session_start(lt_handle_t *h, const lt_pkey_index_t pkey_index, lt_host_eph_keys_t *host_eph_keys); +lt_ret_t lt_out__session_start(lt_handle_t *h, const lt_pkey_index_t pkey_index, + lt_host_eph_keys_t *host_eph_keys); /** * @brief Decodes TROPIC01's response during secure session's establishment. * * Designed to be used together with `lt_out__session_start()`, `lt_l2_send()` and `lt_l2_receive()`. - * @note Secure session will be established after successful execution. For more information read info at the top of - * this file. + * @note Secure session will be established after successful execution. For more information read info + * at the top of this file. * * @param h Handle for communication with TROPIC01 * @param stpub STPUB from device's certificate * @param pkey_index Index of pairing public key * @param shipriv Secure host private key * @param shipub Secure host public key - * @param host_eph_keys Host MCU ephemeral keys, must be filled by lt_out__session_start() and used to finish secure - * session establishment. + * @param host_eph_keys Host MCU ephemeral keys, must be filled by lt_out__session_start() and used to + * finish secure session establishment. * @return LT_OK if success, otherwise returns other error code. */ lt_ret_t lt_in__session_start(lt_handle_t *h, const uint8_t *stpub, const lt_pkey_index_t pkey_index, - const uint8_t *shipriv, const uint8_t *shipub, lt_host_eph_keys_t *host_eph_keys); + const uint8_t *shipriv, const uint8_t *shipub, + lt_host_eph_keys_t *host_eph_keys); /** * @brief Encodes Ping command payload. @@ -162,7 +166,8 @@ lt_ret_t lt_in__pairing_key_invalidate(lt_handle_t *h); * @param obj Content to be written * @return LT_OK if success, otherwise returns other error code. */ -lt_ret_t lt_out__r_config_write(lt_handle_t *h, const enum lt_config_obj_addr_t addr, const uint32_t obj); +lt_ret_t lt_out__r_config_write(lt_handle_t *h, const enum lt_config_obj_addr_t addr, + const uint32_t obj); /** * @brief Decodes R_Config_Write result payload. @@ -226,7 +231,8 @@ lt_ret_t lt_in__r_config_erase(lt_handle_t *h); * @param bit_index Bit index to write in the configuration object * @return LT_OK if success, otherwise returns other error code. */ -lt_ret_t lt_out__i_config_write(lt_handle_t *h, const enum lt_config_obj_addr_t addr, const uint8_t bit_index); +lt_ret_t lt_out__i_config_write(lt_handle_t *h, const enum lt_config_obj_addr_t addr, + const uint8_t bit_index); /** * @brief Decodes I_Config_Write result payload. @@ -268,8 +274,8 @@ lt_ret_t lt_in__i_config_read(lt_handle_t *h, uint32_t *obj); * @param h Handle for communication with TROPIC01 * @param udata_slot Memory's slot to be written * @param data Buffer of data to be written into R MEMORY slot - * @param data_size Size of data to be written (valid range given by macros `TR01_R_MEM_DATA_SIZE_MIN` and - * `TR01_R_MEM_DATA_SIZE_MAX`) + * @param data_size Size of data to be written (valid range given by macros + * `TR01_R_MEM_DATA_SIZE_MIN` and `TR01_R_MEM_DATA_SIZE_MAX`) * @return LT_OK if success, otherwise returns other error code. */ lt_ret_t lt_out__r_mem_data_write(lt_handle_t *h, const uint16_t udata_slot, const uint8_t *data, @@ -307,7 +313,8 @@ lt_ret_t lt_out__r_mem_data_read(lt_handle_t *h, const uint16_t udata_slot); * @param data_read_size Number of bytes read into data buffer * @return LT_OK if success, otherwise returns other error code. */ -lt_ret_t lt_in__r_mem_data_read(lt_handle_t *h, uint8_t *data, const uint16_t data_max_size, uint16_t *data_read_size); +lt_ret_t lt_in__r_mem_data_read(lt_handle_t *h, uint8_t *data, const uint16_t data_max_size, + uint16_t *data_read_size); /** * @brief Encodes R_Mem_Data_Erase command payload. @@ -363,7 +370,8 @@ lt_ret_t lt_in__random_value_get(lt_handle_t *h, uint8_t *rnd_bytes, const uint1 * @param curve ECC curve type to use for key generation * @return LT_OK if success, otherwise returns other error code. */ -lt_ret_t lt_out__ecc_key_generate(lt_handle_t *h, const lt_ecc_slot_t slot, const lt_ecc_curve_type_t curve); +lt_ret_t lt_out__ecc_key_generate(lt_handle_t *h, const lt_ecc_slot_t slot, + const lt_ecc_curve_type_t curve); /** * @brief Decodes ECC_Key_Generate result payload. @@ -386,8 +394,8 @@ lt_ret_t lt_in__ecc_key_generate(lt_handle_t *h); * @param key Ecc key to store, 32B length * @return LT_OK if success, otherwise returns other error code. */ -lt_ret_t lt_out__ecc_key_store(lt_handle_t *h, const lt_ecc_slot_t slot, const lt_ecc_curve_type_t curve, - const uint8_t *key); +lt_ret_t lt_out__ecc_key_store(lt_handle_t *h, const lt_ecc_slot_t slot, + const lt_ecc_curve_type_t curve, const uint8_t *key); /** * @brief Decodes ECC_Key_Store result payload. @@ -416,16 +424,17 @@ lt_ret_t lt_out__ecc_key_read(lt_handle_t *h, const lt_ecc_slot_t slot); * the top of this file. * * @param h Handle for communication with TROPIC01 - * @param key Buffer for retrieving a key; length depends on the type of key in the slot (32B for Ed25519, - * 64B for P256), according to *curve* + * @param key Buffer for retrieving a key; length depends on the type of key in the slot + * (32B for Ed25519, 64B for P256), according to *curve* * @param key_max_size Size of the key buffer - * @param curve When the function executes successfully, the type of elliptic curve public key will be written - * @param origin When the function executes successfully, the origin of the public key (generated/stored) will - * be written + * @param curve When the function executes successfully, the type of elliptic curve public key + * will be written + * @param origin When the function executes successfully, the origin of the public key + * (generated/stored) will be written * @return LT_OK if success, otherwise returns other error code. */ -lt_ret_t lt_in__ecc_key_read(lt_handle_t *h, uint8_t *key, const uint8_t key_max_size, lt_ecc_curve_type_t *curve, - lt_ecc_key_origin_t *origin); +lt_ret_t lt_in__ecc_key_read(lt_handle_t *h, uint8_t *key, const uint8_t key_max_size, + lt_ecc_curve_type_t *curve, lt_ecc_key_origin_t *origin); /** * @brief Encodes ECC_Key_Erase command payload. @@ -459,7 +468,8 @@ lt_ret_t lt_in__ecc_key_erase(lt_handle_t *h); * @param msg_len Length of the message * @return LT_OK if success, otherwise returns other error code. */ -lt_ret_t lt_out__ecc_ecdsa_sign(lt_handle_t *h, const lt_ecc_slot_t slot, const uint8_t *msg, const uint32_t msg_len); +lt_ret_t lt_out__ecc_ecdsa_sign(lt_handle_t *h, const lt_ecc_slot_t slot, const uint8_t *msg, + const uint32_t msg_len); /** * @brief Decodes ECDSA_Sign result payload. @@ -467,7 +477,8 @@ lt_ret_t lt_out__ecc_ecdsa_sign(lt_handle_t *h, const lt_ecc_slot_t slot, const * the top of this file. * * @param h Handle for communication with TROPIC01 - * @param rs Buffer with a signature in a form of R and S bytes (should always have length 64B) + * @param rs Buffer with a signature in a form of R and S bytes (should always have length + * 64B) * @return LT_OK if success, otherwise returns other error code. */ lt_ret_t lt_in__ecc_ecdsa_sign(lt_handle_t *h, uint8_t *rs); @@ -492,7 +503,8 @@ lt_ret_t lt_out__ecc_eddsa_sign(lt_handle_t *h, const lt_ecc_slot_t ecc_slot, co * the top of this file. * * @param h Handle for communication with TROPIC01 - * @param rs Buffer with a signature in a form of R and S bytes (should always have length 64B) + * @param rs Buffer with a signature in a form of R and S bytes (should always have length + * 64B) * @return LT_OK if success, otherwise returns other error code. */ lt_ret_t lt_in__ecc_eddsa_sign(lt_handle_t *h, uint8_t *rs); @@ -507,8 +519,8 @@ lt_ret_t lt_in__ecc_eddsa_sign(lt_handle_t *h, uint8_t *rs); * @param mcounter_value Value to set as an initial value * * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose - * encoding of returned value + * @retval other Function did not execute successully, you might use lt_ret_verbose() to + * get verbose encoding of returned value */ lt_ret_t lt_out__mcounter_init(lt_handle_t *h, const enum lt_mcounter_index_t mcounter_index, const uint32_t mcounter_value); @@ -576,7 +588,8 @@ lt_ret_t lt_in__mcounter_get(lt_handle_t *h, uint32_t *mcounter_value); * @param data_out Data to be sent out, must be 32 bytes long * @return LT_OK if success, otherwise returns other error code. */ -lt_ret_t lt_out__mac_and_destroy(lt_handle_t *h, lt_mac_and_destroy_slot_t slot, const uint8_t *data_out); +lt_ret_t lt_out__mac_and_destroy(lt_handle_t *h, lt_mac_and_destroy_slot_t slot, + const uint8_t *data_out); /** * @brief Decodes MAC_And_Destroy result payload. diff --git a/include/libtropic_logging.h b/include/libtropic_logging.h index d96d2131b..0ce6799a6 100644 --- a/include/libtropic_logging.h +++ b/include/libtropic_logging.h @@ -54,9 +54,10 @@ extern "C" { #endif // This has no effect, test runner just simply copies these lines to the log. -#define LT_LOG_LINE(f_, ...) \ - LT_LOG_INFO("\t-----------------------------------------------------------------------------------" f_, \ - ##__VA_ARGS__) +#define LT_LOG_LINE(f_, ...) \ + LT_LOG_INFO( \ + "\t-----------------------------------------------------------------------------------" f_, \ + ##__VA_ARGS__) // Assertions. Will log as a system message and call native assert function. // Note that parameters are stored to _val_ and _exp_ for a case when there diff --git a/include/libtropic_port.h b/include/libtropic_port.h index d4ca10a06..52b074701 100644 --- a/include/libtropic_port.h +++ b/include/libtropic_port.h @@ -4,8 +4,9 @@ /** * @defgroup group_port_functions 7. HAL Interface * @brief Functions defined for each supported platform. - * @details Function used by host platform during hardware-specific operations. Check 'hal/' folder to see what is - * supported. All of these functions have to be impemented by the port for libtropic to work. + * @details Function used by host platform during hardware-specific operations. Check 'hal/' folder to + * see what is supported. All of these functions have to be impemented by the port for libtropic to + * work. * * @{ */ @@ -85,8 +86,8 @@ lt_ret_t lt_port_spi_csn_high(lt_l2_state_t *s2); lt_ret_t lt_port_spi_transfer(lt_l2_state_t *s2, uint8_t offset, uint16_t tx_len, uint32_t timeout_ms); /** - * @brief Platform defined function for delay, specifies what host platform should do when libtropic's functions need - * some delay. + * @brief Platform defined function for delay, specifies what host platform should do when libtropic's + * functions need some delay. * * @param s2 Structure holding l2 state * @param ms Time to wait in miliseconds @@ -98,8 +99,8 @@ lt_ret_t lt_port_delay(lt_l2_state_t *s2, uint32_t ms); #if LT_USE_INT_PIN /** - * @brief Platform defined function used to specify reading of an interrupt pin, used as a signal that chip has a - * response. + * @brief Platform defined function used to specify reading of an interrupt pin, used as a signal that + * chip has a response. * * @param s2 Structure holding l2 state * @param ms Max time to wait in miliseconds @@ -111,8 +112,8 @@ lt_ret_t lt_port_delay_on_int(lt_l2_state_t *s2, uint32_t ms); #endif /** * @brief Fill buffer with random bytes, platform defined function. - * @note This function should use some cryptographically secure mechanism to generate the random bytes. Its speed should - * not be a concern, as this function is not called often. + * @note This function should use some cryptographically secure mechanism to generate the random bytes. + * Its speed should not be a concern, as this function is not called often. * * @param s2 Structure holding l2 state * @param buff Buffer to be filled @@ -124,9 +125,11 @@ lt_ret_t lt_port_delay_on_int(lt_l2_state_t *s2, uint32_t ms); lt_ret_t lt_port_random_bytes(lt_l2_state_t *s2, void *buff, size_t count); /** - * @brief Port-specific printf-like function used by Libtropic for logging debug information and test outputs. + * @brief Port-specific printf-like function used by Libtropic for logging debug information and test + * outputs. * @note The implementation shall not modify output in any way (e.g., by appending arbitrary newlines) - * apart from behavior expected from a standard printf-like function (e.g., replacing format specifiers). + * apart from behavior expected from a standard printf-like function (e.g., replacing format + * specifiers). * @warning Some implementations use size limited buffer for temporarily storing the log message. * * @param format Pointer to a null-terminated byte string specifying how to interpret the data diff --git a/src/lt_secure_memzero.h b/include/libtropic_secure_memzero.h similarity index 63% rename from src/lt_secure_memzero.h rename to include/libtropic_secure_memzero.h index 855ea0a10..9b2431c7a 100644 --- a/src/lt_secure_memzero.h +++ b/include/libtropic_secure_memzero.h @@ -1,8 +1,8 @@ -#ifndef LT_SECURE_MEMZERO_H -#define LT_SECURE_MEMZERO_H +#ifndef LIBTROPIC_SECURE_MEMZERO_H +#define LIBTROPIC_SECURE_MEMZERO_H /** - * @file lt_secure_memzero.h + * @file libtropic_secure_memzero.h * @brief Declarations for secure memory zeroing. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * @@ -13,12 +13,21 @@ #include "libtropic_common.h" +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Securely overwrites the memory with zeros. + * @note This function is primarily used for internal purposes. * * @param ptr Pointer to the memory * @param count Number of bytes to overwrite with zeros */ void lt_secure_memzero(void *const ptr, size_t count); -#endif // LT_SECURE_MEMZERO_H \ No newline at end of file +#ifdef __cplusplus +} +#endif + +#endif // LIBTROPIC_SECURE_MEMZERO_H \ No newline at end of file diff --git a/mkdocs.yml b/mkdocs.yml index 001bcc41c..029b65c77 100644 --- a/mkdocs.yml +++ b/mkdocs.yml @@ -57,16 +57,18 @@ nav: - Model: - tutorials/model/index.md - 1. Your First Steps: tutorials/model/first_steps.md - # - 2. Understanding Libtropic: tutorials/model/understanding_libtropic.md - - 2. HW Wallet: tutorials/model/hw_wallet.md - - 3. Mac-And-Destroy: tutorials/model/macandd.md - - 4. Separate API: tutorials/model/separate_api.md + - 2. Understanding Libtropic: tutorials/model/understanding_libtropic.md + - 3. HW Wallet: tutorials/model/hw_wallet.md + - 4. Mac-And-Destroy: tutorials/model/macandd.md + - 5. Separate API: tutorials/model/separate_api.md - Linux: + - tutorials/linux/index.md - Linux SPI: - tutorials/linux/spi/index.md - 1. Chip Identification: tutorials/linux/spi/identify_chip.md - 2. FW Update: tutorials/linux/spi/fw_update.md - 3. Hello, World!: tutorials/linux/spi/hello_world.md + - 4. Full Chain Verification: tutorials/linux/spi/full_chain_verification.md - USB Devkit: - tutorials/linux/usb_devkit/index.md - 1. Chip Identification: tutorials/linux/usb_devkit/identify_chip.md @@ -125,6 +127,7 @@ nav: - Functional Tests: for_contributors/tests/functional_tests.md - Functional Mock Tests: for_contributors/tests/functional_mock_tests.md - Code Coverage: for_contributors/tests/code_coverage.md + - Using the CodeChecker: for_contributors/codechecker.md - Adding a New Host Platform: for_contributors/adding_host_platform.md - Adding a New Cryptographic Functionality Provider: for_contributors/adding_cfp.md - FAQ: faq.md diff --git a/scripts/codechecker/README.md b/scripts/codechecker/README.md deleted file mode 100644 index e66753a62..000000000 --- a/scripts/codechecker/README.md +++ /dev/null @@ -1,36 +0,0 @@ -# CodeChecker - -The CodeChecker tool is used to perform static code analysis and generate reports. - -You need to install CodeChecker and dependencies. Check out the [official repository](https://github.com/Ericsson/codechecker) for guidance. - -## Generating reports - -There are 2 options to get reports: - -1. Generate HTML report using CLI. - - Run following commands: - - ```sh - CodeChecker check -b "./scripts/codechecker/codechecker_build.sh" --config ./scripts/codechecker/codechecker_config.yml --output ./.codechecker/reports - CodeChecker parse -e html ./.codechecker/reports -o ./.codechecker/reports_html - ``` - - - Open `./.codechecker/reports_html/index.html` in your favorite web browser. - -2. Use VS Code CodeChecker add-on. - - Install the add-on from [marketplace](https://marketplace.visualstudio.com/items?itemName=codechecker.vscode-codechecker). - - Add these lines to your VS Code's workspace settings (`.vscode/settings.json`): - - ```json - "codechecker.executor.executablePath": , - "codechecker.analyze.arguments": "--config ./scripts/codechecker/codechecker_config.yml", - "codechecker.log.buildCommand": "./scripts/codechecker/codechecker_build.sh", - "codechecker.backend.compilationDatabasePath": "${workspaceFolder}/.codechecker/compile_commands.json" - ``` - - - Note: `` can be replaced with "CodeChecker" if the CodeChecker is available in your `$PATH`. Otherwise, you need to specify full path to the CodeChecker executable. - -## Remarks -The current CodeChecker configuration is in YAML format, as it is more human-readable than JSON and also supports comments. -The configuration file enables some strict checkers, which may produce a lot of warnings. It is recommended to run the analysis using the full configuration at least once. After that, you can manually disable any checkers you find unnecessary. \ No newline at end of file diff --git a/scripts/codechecker/codechecker.skip b/scripts/codechecker/codechecker.skip index 17ac8cb07..dbae3d3d4 100644 --- a/scripts/codechecker/codechecker.skip +++ b/scripts/codechecker/codechecker.skip @@ -3,7 +3,10 @@ +*/libtropic/cal/* +*/libtropic/hal/* +*/libtropic/include/* -+*/libtropic/examples/* + +# Disable checking of source codes of examples, +# as we intentionally omit some checks and patterns for simplicity. +# +*/libtropic/examples/*/main.c # Skip everything else (vendor libs, CMake internal libs...) -* \ No newline at end of file diff --git a/scripts/codechecker/codechecker_build.sh b/scripts/codechecker/codechecker_build.sh deleted file mode 100755 index 7c08bb044..000000000 --- a/scripts/codechecker/codechecker_build.sh +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/bash -cd tests/functional/model/ -./download_deps.sh -rm -rf build/ -mkdir -p build/ -cd build/ -cmake -DLT_CAL=mbedtls_v4 .. -make -j \ No newline at end of file diff --git a/scripts/codechecker/codechecker_config.yml b/scripts/codechecker/codechecker_config.yml index 3ceadaef4..4fcf0f6d7 100644 --- a/scripts/codechecker/codechecker_config.yml +++ b/scripts/codechecker/codechecker_config.yml @@ -1,10 +1,4 @@ analyzer: - ################################################ - # Configure skipfile to select which sources - # to check. - ################################################ - - --skip=scripts/codechecker/codechecker.skip - ################################################ # Enable / disable checks ################################################ @@ -48,11 +42,6 @@ analyzer: ################################################ - --ctu-all - ################################################ - # Export setup - ################################################ - - --output=.codechecker/reports - ################################################ # Checker selection ################################################ diff --git a/scripts/codechecker/run_checks.sh b/scripts/codechecker/run_checks.sh new file mode 100755 index 000000000..fc24e9e58 --- /dev/null +++ b/scripts/codechecker/run_checks.sh @@ -0,0 +1,78 @@ +#!/usr/bin/env bash + +# This script builds Libtropic in multiple configurations for CodeChecker evaluation. +# +# Majority of platforms are built using examples, as they are quicker to build, +# the model is built using tests, as they allow to change CAL, which has +# to be done for one target. + +set -eo pipefail + +LT_ROOT_DIR="." + +if [ -z "$1" ]; then + echo "Assuming Libtropic root directory is a current working directory." + echo "To change the Libtropic root directory, pass it as the first argument:" + echo " $0 " +else + LT_ROOT_DIR="${1%/}" # Remove last trailing slash (if any present) + echo "Libtropic root directory set to: $LT_ROOT_DIR" +fi + +echo "Checking dependencies..." +if ! command -v CodeChecker >/dev/null 2>&1; then + echo "Missing CodeChecker! Install and try again." + exit 1 +fi +if ! command -v jq >/dev/null 2>&1; then + echo "Missing jq! Install and try again." + exit 1 +fi +if ! command -v cmake >/dev/null 2>&1; then + echo "Missing cmake! Install and try again." + exit 1 +fi +if ! command -v make >/dev/null 2>&1; then + echo "Missing make! Install and try again." + exit 1 +fi + +# Recreating directories +rm -fr "$LT_ROOT_DIR/.codechecker/" +mkdir -p "$LT_ROOT_DIR/.codechecker/compile_commands" +mkdir -p "$LT_ROOT_DIR/.codechecker/reports" +mkdir -p "$LT_ROOT_DIR/.codechecker/reports_html" + +# Linux USB DevKit + MbedTLSv4 +CodeChecker log -b "cd \"$LT_ROOT_DIR/examples/linux/usb_devkit/hello_world\" && rm -rf build && mkdir build && cd build && cmake .. && make -j" \ + -o "$LT_ROOT_DIR/.codechecker/compile_commands/usb_devkit_compile_commands.json" + +# Linux SPI + MbedTLSv4 +CodeChecker log -b "cd \"$LT_ROOT_DIR/examples/linux/spi/hello_world\" && rm -rf build && mkdir build && cd build && cmake .. && make -j" \ + -o "$LT_ROOT_DIR/.codechecker/compile_commands/linux_spi_compile_commands.json" + +# Model + all CALs +CALS=("trezor_crypto" "mbedtls_v4" "openssl" "wolfcrypt") +for CURRENT_CAL in "${CALS[@]}"; do + CodeChecker log -b "cd \"$LT_ROOT_DIR/tests/functional/model\" && rm -rf build && mkdir build && cd build && cmake -DLT_CAL=$CURRENT_CAL .. && make -j" \ + -o "$LT_ROOT_DIR/.codechecker/compile_commands/model_${CURRENT_CAL}_compile_commands.json" +done + +# Merge compile_commands.json files +# Change temporarily to the directory, so we support +# also special symbols in the path specified by $LT_ROOT_DIR. +(cd "$LT_ROOT_DIR/.codechecker/compile_commands" && \ + jq -s 'add' ./*_compile_commands.json \ + > "../merged_compile_commands.json") + +set +e +# Run analysis on merged compilation database +CodeChecker analyze "$LT_ROOT_DIR/.codechecker/merged_compile_commands.json" \ + --config "$LT_ROOT_DIR/scripts/codechecker/codechecker_config.yml" \ + --skip "$LT_ROOT_DIR/scripts/codechecker/codechecker.skip" \ + -o "$LT_ROOT_DIR/.codechecker/reports" +set -e + +CodeChecker parse "$LT_ROOT_DIR/.codechecker/reports" \ + -e html \ + -o "$LT_ROOT_DIR/.codechecker/reports_html" \ No newline at end of file diff --git a/src/libtropic.c b/src/libtropic.c index 9c8a09e10..3743928fa 100644 --- a/src/libtropic.c +++ b/src/libtropic.c @@ -21,6 +21,7 @@ #include "libtropic_logging.h" #include "libtropic_macros.h" #include "libtropic_port.h" +#include "libtropic_secure_memzero.h" #include "lt_asn1_der.h" #include "lt_crypto_common.h" #include "lt_hkdf.h" @@ -29,7 +30,6 @@ #include "lt_l3_api_structs.h" #include "lt_l3_process.h" #include "lt_port_wrap.h" -#include "lt_secure_memzero.h" #include "lt_sha256.h" #include "lt_tr01_attrs.h" #include "lt_x25519.h" @@ -68,7 +68,32 @@ lt_ret_t lt_init(lt_handle_t *h) goto crypto_ctx_cleanup; } - // Initialize the TROPIC01 attributes based on its Application FW. + // Now, we need to initialize TROPIC01 attributes based on its Application FW: + // 1. Get current TROPIC01's mode. + lt_tr01_mode_t tr01_mode; + ret = lt_get_tr01_mode(h, &tr01_mode); + if (ret != LT_OK) { + goto crypto_ctx_cleanup; + } + + // 2. Reboot if TROPIC01 is not executing Application FW. + if (tr01_mode != LT_TR01_APPLICATION) { + ret = lt_reboot(h, TR01_REBOOT); + + if (ret == LT_REBOOT_UNSUCCESSFUL) { + // We allow this, because TROPIC01 might contain invalid Application FW, but should not be + // restricted from using Libtropic in Start-up Mode. + LT_LOG_WARN( + "TROPIC01's App FW attributes were not initialized. TROPIC01 will be usable in " + "Start-up Mode only until a successful FW update."); + return LT_OK; + } + if (ret != LT_OK) { + goto crypto_ctx_cleanup; + } + } + + // 3. Initialize TROPIC01 attributes based on its Application FW version. ret = lt_init_tr01_attrs(h); if (ret != LT_OK) { goto crypto_ctx_cleanup; @@ -218,8 +243,10 @@ lt_ret_t lt_get_info_cert_store(lt_handle_t *h, struct lt_cert_store_t *store) } // Read out and copy certificate chunk. Assumes that: - // - A single certificate is always larger than 128 bytes -> There is at most one "trailing chunk"! - // No need to handle this case explicitly since it is very likely to be like that, but worth mentioning. + // - A single certificate is always larger than 128 bytes -> There is at most one "trailing + // chunk"! + // No need to handle this case explicitly since it is very likely to be like that, but worth + // mentioning. // Copy certificate chunk int available = tail - head; @@ -263,7 +290,8 @@ lt_ret_t lt_get_st_pub(const struct lt_cert_store_t *store, uint8_t *stpub) uint8_t *head = store->certs[LT_CERT_KIND_DEVICE]; uint16_t len = store->cert_len[LT_CERT_KIND_DEVICE]; - return asn1der_find_object(head, len, LT_OBJ_ID_CURVEX25519, stpub, TR01_STPUB_LEN, LT_ASN1DER_CROP_PREFIX); + return asn1der_find_object(head, len, LT_OBJ_ID_CURVEX25519, stpub, TR01_STPUB_LEN, + LT_ASN1DER_CROP_PREFIX); } lt_ret_t lt_get_info_chip_id(lt_handle_t *h, struct lt_chip_id_t *chip_id) @@ -295,7 +323,8 @@ lt_ret_t lt_get_info_chip_id(lt_handle_t *h, struct lt_chip_id_t *chip_id) return LT_L2_RSP_LEN_ERROR; } - memcpy(chip_id, ((struct lt_l2_get_info_rsp_t *)h->l2.buff)->object, TR01_L2_GET_INFO_CHIP_ID_SIZE); + memcpy(chip_id, ((struct lt_l2_get_info_rsp_t *)h->l2.buff)->object, + TR01_L2_GET_INFO_CHIP_ID_SIZE); return LT_OK; } @@ -371,9 +400,9 @@ lt_ret_t lt_get_info_spect_fw_ver(lt_handle_t *h, uint8_t *ver) lt_ret_t lt_get_info_fw_bank(lt_handle_t *h, const lt_bank_id_t bank_id, uint8_t *header, const uint16_t header_max_size, uint16_t *header_read_size) { - if (!h || !header || !header_read_size - || ((bank_id != TR01_FW_BANK_FW1) && (bank_id != TR01_FW_BANK_FW2) && (bank_id != TR01_FW_BANK_SPECT1) - && (bank_id != TR01_FW_BANK_SPECT2))) { + if (!h || !header || !header_read_size || + ((bank_id != TR01_FW_BANK_FW1) && (bank_id != TR01_FW_BANK_FW2) && + (bank_id != TR01_FW_BANK_SPECT1) && (bank_id != TR01_FW_BANK_SPECT2))) { return LT_PARAM_ERR; } @@ -396,9 +425,9 @@ lt_ret_t lt_get_info_fw_bank(lt_handle_t *h, const lt_bank_id_t bank_id, uint8_t return ret; } - if ((TR01_L2_GET_INFO_FW_HEADER_SIZE_BOOT_V1 != p_l2_resp->rsp_len) - && (TR01_L2_GET_INFO_FW_HEADER_SIZE_BOOT_V2 != p_l2_resp->rsp_len) - && (TR01_L2_GET_INFO_FW_HEADER_SIZE_BOOT_V2_EMPTY_BANK != p_l2_resp->rsp_len)) { + if ((TR01_L2_GET_INFO_FW_HEADER_SIZE_BOOT_V1 != p_l2_resp->rsp_len) && + (TR01_L2_GET_INFO_FW_HEADER_SIZE_BOOT_V2 != p_l2_resp->rsp_len) && + (TR01_L2_GET_INFO_FW_HEADER_SIZE_BOOT_V2_EMPTY_BANK != p_l2_resp->rsp_len)) { return LT_L2_RSP_LEN_ERROR; } @@ -437,6 +466,14 @@ lt_ret_t lt_session_start(lt_handle_t *h, const uint8_t *stpub, const lt_pkey_in goto cleanup; } + // Setup a pointer to a response in the L2 buffer. + struct lt_l2_handshake_rsp_t *p_l2_resp = (struct lt_l2_handshake_rsp_t *)h->l2.buff; + + if (TR01_L2_HANDSHAKE_RSP_LEN != (p_l2_resp->rsp_len)) { + ret = LT_L2_RSP_LEN_ERROR; + goto cleanup; + } + ret = lt_in__session_start(h, stpub, pkey_index, shipriv, shipub, &host_eph_keys); cleanup: @@ -453,9 +490,11 @@ lt_ret_t lt_session_abort(lt_handle_t *h) lt_l3_invalidate_host_session_data(&h->l3); // Setup a request pointer to l2 buffer, which is placed in handle - struct lt_l2_encrypted_session_abt_req_t *p_l2_req = (struct lt_l2_encrypted_session_abt_req_t *)h->l2.buff; + struct lt_l2_encrypted_session_abt_req_t *p_l2_req = (struct lt_l2_encrypted_session_abt_req_t *) + h->l2.buff; // Setup a request pointer to l2 buffer with response data - struct lt_l2_encrypted_session_abt_rsp_t *p_l2_resp = (struct lt_l2_encrypted_session_abt_rsp_t *)h->l2.buff; + struct lt_l2_encrypted_session_abt_rsp_t *p_l2_resp = (struct lt_l2_encrypted_session_abt_rsp_t *) + h->l2.buff; p_l2_req->req_id = TR01_L2_ENCRYPTED_SESSION_ABT_ID; p_l2_req->req_len = TR01_L2_ENCRYPTED_SESSION_ABT_LEN; @@ -555,8 +594,8 @@ lt_ret_t lt_reboot(lt_handle_t *h, const lt_startup_id_t startup_id) } // Validate the current TROPIC01 mode based on the given `startup_id`. - if ((startup_id == TR01_REBOOT && tr01_mode != LT_TR01_APPLICATION) - || (startup_id == TR01_MAINTENANCE_REBOOT && tr01_mode != LT_TR01_MAINTENANCE)) { + if ((startup_id == TR01_REBOOT && tr01_mode != LT_TR01_APPLICATION) || + (startup_id == TR01_MAINTENANCE_REBOOT && tr01_mode != LT_TR01_MAINTENANCE)) { return LT_REBOOT_UNSUCCESSFUL; } @@ -566,9 +605,8 @@ lt_ret_t lt_reboot(lt_handle_t *h, const lt_startup_id_t startup_id) #ifdef ABAB lt_ret_t lt_mutable_fw_erase(lt_handle_t *h, const lt_bank_id_t bank_id) { - if (!h - || ((bank_id != TR01_FW_BANK_FW1) && (bank_id != TR01_FW_BANK_FW2) && (bank_id != TR01_FW_BANK_SPECT1) - && (bank_id != TR01_FW_BANK_SPECT2))) { + if (!h || ((bank_id != TR01_FW_BANK_FW1) && (bank_id != TR01_FW_BANK_FW2) && + (bank_id != TR01_FW_BANK_SPECT1) && (bank_id != TR01_FW_BANK_SPECT2))) { return LT_PARAM_ERR; } @@ -597,18 +635,21 @@ lt_ret_t lt_mutable_fw_erase(lt_handle_t *h, const lt_bank_id_t bank_id) return LT_OK; } -lt_ret_t lt_mutable_fw_update(lt_handle_t *h, const uint8_t *fw_data, const uint16_t fw_data_size, lt_bank_id_t bank_id) +lt_ret_t lt_mutable_fw_update(lt_handle_t *h, const uint8_t *fw_data, const uint16_t fw_data_size, + lt_bank_id_t bank_id) { - if (!h || !fw_data || fw_data_size > TR01_MUTABLE_FW_UPDATE_SIZE_MAX - || ((bank_id != TR01_FW_BANK_FW1) && (bank_id != TR01_FW_BANK_FW2) && (bank_id != TR01_FW_BANK_SPECT1) - && (bank_id != TR01_FW_BANK_SPECT2))) { + if (!h || !fw_data || fw_data_size > TR01_MUTABLE_FW_UPDATE_SIZE_MAX || + ((bank_id != TR01_FW_BANK_FW1) && (bank_id != TR01_FW_BANK_FW2) && + (bank_id != TR01_FW_BANK_SPECT1) && (bank_id != TR01_FW_BANK_SPECT2))) { return LT_PARAM_ERR; } // Setup a request pointer to l2 buffer, which is placed in handle - struct lt_l2_mutable_fw_update_req_t *p_l2_req = (struct lt_l2_mutable_fw_update_req_t *)h->l2.buff; + struct lt_l2_mutable_fw_update_req_t *p_l2_req = (struct lt_l2_mutable_fw_update_req_t *) + h->l2.buff; // Setup a request pointer to l2 buffer with response data - struct lt_l2_mutable_fw_update_rsp_t *p_l2_resp = (struct lt_l2_mutable_fw_update_rsp_t *)h->l2.buff; + struct lt_l2_mutable_fw_update_rsp_t *p_l2_resp = (struct lt_l2_mutable_fw_update_rsp_t *) + h->l2.buff; uint16_t loops = fw_data_size / 128; uint16_t rest = fw_data_size % 128; @@ -666,19 +707,22 @@ lt_ret_t lt_mutable_fw_update(lt_handle_t *h, const uint8_t *update_request) // This structure reflects incomming data and is used for passing those data into l2 frame struct data_format_t { - uint8_t req_len; /**< Length byte */ - uint8_t signature[64]; /**< Signature of SHA256 hash of all following data in this packet */ - uint8_t hash[32]; /**< SHA256 HASH of first FW chunk of data sent using Mutable_FW_Update_Data */ - uint16_t type; /**< FW type which is going to be updated */ + uint8_t req_len; /**< Length byte */ + uint8_t signature[64]; /**< Signature of SHA256 hash of all following data in this packet */ + uint8_t + hash[32]; /**< SHA256 HASH of first FW chunk of data sent using Mutable_FW_Update_Data */ + uint16_t type; /**< FW type which is going to be updated */ uint8_t padding; /**< Padding, zero value */ uint8_t header_version; /**< Version of used header */ uint32_t version; /**< Version of FW */ } __attribute__((__packed__)); // Setup a request pointer to l2 buffer, which is placed in handle - struct lt_l2_mutable_fw_update_req_t *p_l2_req = (struct lt_l2_mutable_fw_update_req_t *)h->l2.buff; + struct lt_l2_mutable_fw_update_req_t *p_l2_req = (struct lt_l2_mutable_fw_update_req_t *) + h->l2.buff; // Setup a request pointer to l2 buffer with response data - struct lt_l2_mutable_fw_update_rsp_t *p_l2_resp = (struct lt_l2_mutable_fw_update_rsp_t *)h->l2.buff; + struct lt_l2_mutable_fw_update_rsp_t *p_l2_resp = (struct lt_l2_mutable_fw_update_rsp_t *) + h->l2.buff; // Setup a pointer to incomming data struct data_format_t *data_p = (struct data_format_t *)(update_request); @@ -710,26 +754,30 @@ lt_ret_t lt_mutable_fw_update(lt_handle_t *h, const uint8_t *update_request) return LT_OK; } -lt_ret_t lt_mutable_fw_update_data(lt_handle_t *h, const uint8_t *update_data, const uint16_t update_data_size) +lt_ret_t lt_mutable_fw_update_data(lt_handle_t *h, const uint8_t *update_data, + const uint16_t update_data_size) { - if (!h || !update_data || update_data_size <= (TR01_L2_MUTABLE_FW_UPDATE_REQ_LEN + 1U) - || update_data_size > TR01_MUTABLE_FW_UPDATE_SIZE_MAX) { + if (!h || !update_data || update_data_size <= (TR01_L2_MUTABLE_FW_UPDATE_REQ_LEN + 1U) || + update_data_size > TR01_MUTABLE_FW_UPDATE_SIZE_MAX) { return LT_PARAM_ERR; } // Setup a request pointer to l2 buffer, which is placed in handle - struct lt_l2_mutable_fw_update_data_req_t *p2_l2_req = (struct lt_l2_mutable_fw_update_data_req_t *)h->l2.buff; + struct lt_l2_mutable_fw_update_data_req_t *p2_l2_req = + (struct lt_l2_mutable_fw_update_data_req_t *)h->l2.buff; // Setup a request pointer to l2 buffer with response data - struct lt_l2_mutable_fw_update_rsp_t *p_l2_resp = (struct lt_l2_mutable_fw_update_rsp_t *)h->l2.buff; + struct lt_l2_mutable_fw_update_rsp_t *p_l2_resp = (struct lt_l2_mutable_fw_update_rsp_t *) + h->l2.buff; // Normalized sizes for arithmetic. size_t upd_size = (size_t)update_data_size; size_t copy_len; - // Compute how many bytes are available in the `lt_l2_mutable_fw_update_data_req_t` struct starting at `req_len`. - // This is a compile-time-safe calculation and prevents overflow into unknown memory. + // Compute how many bytes are available in the `lt_l2_mutable_fw_update_data_req_t` struct starting + // at `req_len`. This is a compile-time-safe calculation and prevents overflow into unknown memory. const size_t dest_offset = offsetof(struct lt_l2_mutable_fw_update_data_req_t, req_len); - const size_t dest_capacity = sizeof(*p2_l2_req) > dest_offset ? sizeof(*p2_l2_req) - dest_offset : 0U; + const size_t dest_capacity = sizeof(*p2_l2_req) > dest_offset ? sizeof(*p2_l2_req) - dest_offset + : 0U; // Data consist of "request" and "data" parts, // 'data' byte chunks are taken starting from 'chunk_index' @@ -764,7 +812,8 @@ lt_ret_t lt_mutable_fw_update_data(lt_handle_t *h, const uint8_t *update_data, c #error "Undefined silicon revision. Please define either ABAB or ACAB." #endif -lt_ret_t lt_get_log_req(lt_handle_t *h, uint8_t *log_msg, const uint16_t log_msg_max_size, uint16_t *log_msg_read_size) +lt_ret_t lt_get_log_req(lt_handle_t *h, uint8_t *log_msg, const uint16_t log_msg_max_size, + uint16_t *log_msg_read_size) { if (!h || !log_msg || !log_msg_read_size) { return LT_PARAM_ERR; @@ -818,7 +867,8 @@ lt_ret_t lt_ping(lt_handle_t *h, const uint8_t *msg_out, uint8_t *msg_in, const return ret; } - ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, lt_min(h->l3.buff_len, TR01_L3_PING_RES_PACKET_SIZE_MAX)); + ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, + lt_min(h->l3.buff_len, TR01_L3_PING_RES_PACKET_SIZE_MAX)); if (ret != LT_OK) { return ret; } @@ -901,8 +951,8 @@ lt_ret_t lt_pairing_key_invalidate(lt_handle_t *h, const uint8_t slot) return ret; } - ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, - lt_min(h->l3.buff_len, TR01_L3_PAIRING_KEY_INVALIDATE_RES_PACKET_SIZE)); + ret = lt_l2_recv_encrypted_res( + &h->l2, h->l3.buff, lt_min(h->l3.buff_len, TR01_L3_PAIRING_KEY_INVALIDATE_RES_PACKET_SIZE)); if (ret != LT_OK) { return ret; } @@ -929,7 +979,8 @@ lt_ret_t lt_r_config_write(lt_handle_t *h, const enum lt_config_obj_addr_t addr, return ret; } - ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, lt_min(h->l3.buff_len, TR01_L3_R_CONFIG_WRITE_RES_PACKET_SIZE)); + ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, + lt_min(h->l3.buff_len, TR01_L3_R_CONFIG_WRITE_RES_PACKET_SIZE)); if (ret != LT_OK) { return ret; } @@ -956,7 +1007,8 @@ lt_ret_t lt_r_config_read(lt_handle_t *h, const enum lt_config_obj_addr_t addr, return ret; } - ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, lt_min(h->l3.buff_len, TR01_L3_R_CONFIG_READ_RES_PACKET_SIZE)); + ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, + lt_min(h->l3.buff_len, TR01_L3_R_CONFIG_READ_RES_PACKET_SIZE)); if (ret != LT_OK) { return ret; } @@ -983,7 +1035,8 @@ lt_ret_t lt_r_config_erase(lt_handle_t *h) return ret; } - ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, lt_min(h->l3.buff_len, TR01_L3_R_CONFIG_ERASE_RES_PACKET_SIZE)); + ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, + lt_min(h->l3.buff_len, TR01_L3_R_CONFIG_ERASE_RES_PACKET_SIZE)); if (ret != LT_OK) { return ret; } @@ -991,7 +1044,8 @@ lt_ret_t lt_r_config_erase(lt_handle_t *h) return lt_in__r_config_erase(h); } -lt_ret_t lt_i_config_write(lt_handle_t *h, const enum lt_config_obj_addr_t addr, const uint8_t bit_index) +lt_ret_t lt_i_config_write(lt_handle_t *h, const enum lt_config_obj_addr_t addr, + const uint8_t bit_index) { if (!h || (bit_index > 31)) { return LT_PARAM_ERR; @@ -1010,7 +1064,8 @@ lt_ret_t lt_i_config_write(lt_handle_t *h, const enum lt_config_obj_addr_t addr, return ret; } - ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, lt_min(h->l3.buff_len, TR01_L3_I_CONFIG_WRITE_RES_PACKET_SIZE)); + ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, + lt_min(h->l3.buff_len, TR01_L3_I_CONFIG_WRITE_RES_PACKET_SIZE)); if (ret != LT_OK) { return ret; } @@ -1037,7 +1092,8 @@ lt_ret_t lt_i_config_read(lt_handle_t *h, const enum lt_config_obj_addr_t addr, return ret; } - ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, lt_min(h->l3.buff_len, TR01_L3_I_CONFIG_READ_RES_PACKET_SIZE)); + ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, + lt_min(h->l3.buff_len, TR01_L3_I_CONFIG_READ_RES_PACKET_SIZE)); if (ret != LT_OK) { return ret; } @@ -1045,10 +1101,12 @@ lt_ret_t lt_i_config_read(lt_handle_t *h, const enum lt_config_obj_addr_t addr, return lt_in__i_config_read(h, obj); } -lt_ret_t lt_r_mem_data_write(lt_handle_t *h, const uint16_t udata_slot, const uint8_t *data, const uint16_t data_size) +lt_ret_t lt_r_mem_data_write(lt_handle_t *h, const uint16_t udata_slot, const uint8_t *data, + const uint16_t data_size) { - if (!h || !data || data_size < TR01_R_MEM_DATA_SIZE_MIN || data_size > h->tr01_attrs.r_mem_udata_slot_size_max - || (udata_slot > TR01_R_MEM_DATA_SLOT_MAX)) { + if (!h || !data || data_size < TR01_R_MEM_DATA_SIZE_MIN || + data_size > h->tr01_attrs.r_mem_udata_slot_size_max || + (udata_slot > TR01_R_MEM_DATA_SLOT_MAX)) { return LT_PARAM_ERR; } if (h->l3.session_status != LT_SECURE_SESSION_ON) { @@ -1074,8 +1132,8 @@ lt_ret_t lt_r_mem_data_write(lt_handle_t *h, const uint16_t udata_slot, const ui return lt_in__r_mem_data_write(h); } -lt_ret_t lt_r_mem_data_read(lt_handle_t *h, const uint16_t udata_slot, uint8_t *data, const uint16_t data_max_size, - uint16_t *data_read_size) +lt_ret_t lt_r_mem_data_read(lt_handle_t *h, const uint16_t udata_slot, uint8_t *data, + const uint16_t data_max_size, uint16_t *data_read_size) { if (!h || !data || !data_read_size || (udata_slot > TR01_R_MEM_DATA_SLOT_MAX)) { return LT_PARAM_ERR; @@ -1096,9 +1154,10 @@ lt_ret_t lt_r_mem_data_read(lt_handle_t *h, const uint16_t udata_slot, uint8_t * ret = lt_l2_recv_encrypted_res( &h->l2, h->l3.buff, - lt_min(h->l3.buff_len, TR01_L3_SIZE_SIZE + TR01_L3_RESULT_SIZE - + (TR01_L3_R_MEM_DATA_READ_PADDING_SIZE + h->tr01_attrs.r_mem_udata_slot_size_max) - + TR01_L3_TAG_SIZE)); + lt_min(h->l3.buff_len, + TR01_L3_SIZE_SIZE + TR01_L3_RESULT_SIZE + + (TR01_L3_R_MEM_DATA_READ_PADDING_SIZE + h->tr01_attrs.r_mem_udata_slot_size_max) + + TR01_L3_TAG_SIZE)); if (ret != LT_OK) { return ret; } @@ -1153,8 +1212,8 @@ lt_ret_t lt_random_value_get(lt_handle_t *h, uint8_t *rnd_bytes, const uint16_t return ret; } - ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, - lt_min(h->l3.buff_len, TR01_L3_RANDOM_VALUE_GET_RES_PACKET_SIZE_MAX)); + ret = lt_l2_recv_encrypted_res( + &h->l2, h->l3.buff, lt_min(h->l3.buff_len, TR01_L3_RANDOM_VALUE_GET_RES_PACKET_SIZE_MAX)); if (ret != LT_OK) { return ret; } @@ -1164,7 +1223,8 @@ lt_ret_t lt_random_value_get(lt_handle_t *h, uint8_t *rnd_bytes, const uint16_t lt_ret_t lt_ecc_key_generate(lt_handle_t *h, const lt_ecc_slot_t slot, const lt_ecc_curve_type_t curve) { - if (!h || (slot > TR01_ECC_SLOT_31) || ((curve != TR01_CURVE_P256) && (curve != TR01_CURVE_ED25519))) { + if (!h || (slot > TR01_ECC_SLOT_31) || + ((curve != TR01_CURVE_P256) && (curve != TR01_CURVE_ED25519))) { return LT_PARAM_ERR; } if (h->l3.session_status != LT_SECURE_SESSION_ON) { @@ -1190,9 +1250,11 @@ lt_ret_t lt_ecc_key_generate(lt_handle_t *h, const lt_ecc_slot_t slot, const lt_ return lt_in__ecc_key_generate(h); } -lt_ret_t lt_ecc_key_store(lt_handle_t *h, const lt_ecc_slot_t slot, const lt_ecc_curve_type_t curve, const uint8_t *key) +lt_ret_t lt_ecc_key_store(lt_handle_t *h, const lt_ecc_slot_t slot, const lt_ecc_curve_type_t curve, + const uint8_t *key) { - if (!h || (slot > TR01_ECC_SLOT_31) || ((curve != TR01_CURVE_P256) && (curve != TR01_CURVE_ED25519)) || !key) { + if (!h || (slot > TR01_ECC_SLOT_31) || + ((curve != TR01_CURVE_P256) && (curve != TR01_CURVE_ED25519)) || !key) { return LT_PARAM_ERR; } if (h->l3.session_status != LT_SECURE_SESSION_ON) { @@ -1208,7 +1270,8 @@ lt_ret_t lt_ecc_key_store(lt_handle_t *h, const lt_ecc_slot_t slot, const lt_ecc return ret; } - ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, lt_min(h->l3.buff_len, TR01_L3_ECC_KEY_STORE_RES_PACKET_SIZE)); + ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, + lt_min(h->l3.buff_len, TR01_L3_ECC_KEY_STORE_RES_PACKET_SIZE)); if (ret != LT_OK) { return ret; } @@ -1216,8 +1279,9 @@ lt_ret_t lt_ecc_key_store(lt_handle_t *h, const lt_ecc_slot_t slot, const lt_ecc return lt_in__ecc_key_store(h); } -lt_ret_t lt_ecc_key_read(lt_handle_t *h, const lt_ecc_slot_t ecc_slot, uint8_t *key, const uint8_t key_max_size, - lt_ecc_curve_type_t *curve, lt_ecc_key_origin_t *origin) +lt_ret_t lt_ecc_key_read(lt_handle_t *h, const lt_ecc_slot_t ecc_slot, uint8_t *key, + const uint8_t key_max_size, lt_ecc_curve_type_t *curve, + lt_ecc_key_origin_t *origin) { if (!h || (ecc_slot > TR01_ECC_SLOT_31) || !key || !curve || !origin) { return LT_PARAM_ERR; @@ -1264,7 +1328,8 @@ lt_ret_t lt_ecc_key_erase(lt_handle_t *h, const lt_ecc_slot_t ecc_slot) return ret; } - ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, lt_min(h->l3.buff_len, TR01_L3_ECC_KEY_ERASE_RES_PACKET_SIZE)); + ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, + lt_min(h->l3.buff_len, TR01_L3_ECC_KEY_ERASE_RES_PACKET_SIZE)); if (ret != LT_OK) { return ret; } @@ -1272,8 +1337,8 @@ lt_ret_t lt_ecc_key_erase(lt_handle_t *h, const lt_ecc_slot_t ecc_slot) return lt_in__ecc_key_erase(h); } -lt_ret_t lt_ecc_ecdsa_sign(lt_handle_t *h, const lt_ecc_slot_t ecc_slot, const uint8_t *msg, const uint32_t msg_len, - uint8_t *rs) +lt_ret_t lt_ecc_ecdsa_sign(lt_handle_t *h, const lt_ecc_slot_t ecc_slot, const uint8_t *msg, + const uint32_t msg_len, uint8_t *rs) { if (!h || !msg || !rs || (ecc_slot > TR01_ECC_SLOT_31)) { return LT_PARAM_ERR; @@ -1292,7 +1357,8 @@ lt_ret_t lt_ecc_ecdsa_sign(lt_handle_t *h, const lt_ecc_slot_t ecc_slot, const u return ret; } - ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, lt_min(h->l3.buff_len, TR01_L3_ECDSA_SIGN_RES_PACKET_SIZE)); + ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, + lt_min(h->l3.buff_len, TR01_L3_ECDSA_SIGN_RES_PACKET_SIZE)); if (ret != LT_OK) { return ret; } @@ -1300,10 +1366,11 @@ lt_ret_t lt_ecc_ecdsa_sign(lt_handle_t *h, const lt_ecc_slot_t ecc_slot, const u return lt_in__ecc_ecdsa_sign(h, rs); } -lt_ret_t lt_ecc_eddsa_sign(lt_handle_t *h, const lt_ecc_slot_t ecc_slot, const uint8_t *msg, const uint16_t msg_len, - uint8_t *rs) +lt_ret_t lt_ecc_eddsa_sign(lt_handle_t *h, const lt_ecc_slot_t ecc_slot, const uint8_t *msg, + const uint16_t msg_len, uint8_t *rs) { - if (!h || !msg || !rs || (msg_len > TR01_L3_EDDSA_SIGN_CMD_MSG_LEN_MAX) || (ecc_slot > TR01_ECC_SLOT_31)) { + if (!h || !msg || !rs || (msg_len > TR01_L3_EDDSA_SIGN_CMD_MSG_LEN_MAX) || + (ecc_slot > TR01_ECC_SLOT_31)) { return LT_PARAM_ERR; } if (h->l3.session_status != LT_SECURE_SESSION_ON) { @@ -1320,7 +1387,8 @@ lt_ret_t lt_ecc_eddsa_sign(lt_handle_t *h, const lt_ecc_slot_t ecc_slot, const u return ret; } - ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, lt_min(h->l3.buff_len, TR01_L3_EDDSA_SIGN_RES_PACKET_SIZE)); + ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, + lt_min(h->l3.buff_len, TR01_L3_EDDSA_SIGN_RES_PACKET_SIZE)); if (ret != LT_OK) { return ret; } @@ -1328,7 +1396,8 @@ lt_ret_t lt_ecc_eddsa_sign(lt_handle_t *h, const lt_ecc_slot_t ecc_slot, const u return lt_in__ecc_eddsa_sign(h, rs); } -lt_ret_t lt_mcounter_init(lt_handle_t *h, const enum lt_mcounter_index_t mcounter_index, const uint32_t mcounter_value) +lt_ret_t lt_mcounter_init(lt_handle_t *h, const enum lt_mcounter_index_t mcounter_index, + const uint32_t mcounter_value) { if (!h || (mcounter_index > TR01_MCOUNTER_INDEX_15) || mcounter_value > TR01_MCOUNTER_VALUE_MAX) { return LT_PARAM_ERR; @@ -1347,7 +1416,8 @@ lt_ret_t lt_mcounter_init(lt_handle_t *h, const enum lt_mcounter_index_t mcounte return ret; } - ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, lt_min(h->l3.buff_len, TR01_L3_MCOUNTER_INIT_RES_PACKET_SIZE)); + ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, + lt_min(h->l3.buff_len, TR01_L3_MCOUNTER_INIT_RES_PACKET_SIZE)); if (ret != LT_OK) { return ret; } @@ -1374,7 +1444,8 @@ lt_ret_t lt_mcounter_update(lt_handle_t *h, const enum lt_mcounter_index_t mcoun return ret; } - ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, lt_min(h->l3.buff_len, TR01_L3_MCOUNTER_UPDATE_RES_PACKET_SIZE)); + ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, + lt_min(h->l3.buff_len, TR01_L3_MCOUNTER_UPDATE_RES_PACKET_SIZE)); if (ret != LT_OK) { return ret; } @@ -1382,7 +1453,8 @@ lt_ret_t lt_mcounter_update(lt_handle_t *h, const enum lt_mcounter_index_t mcoun return lt_in__mcounter_update(h); } -lt_ret_t lt_mcounter_get(lt_handle_t *h, const enum lt_mcounter_index_t mcounter_index, uint32_t *mcounter_value) +lt_ret_t lt_mcounter_get(lt_handle_t *h, const enum lt_mcounter_index_t mcounter_index, + uint32_t *mcounter_value) { if (!h || (mcounter_index > TR01_MCOUNTER_INDEX_15) || !mcounter_value) { return LT_PARAM_ERR; @@ -1401,7 +1473,8 @@ lt_ret_t lt_mcounter_get(lt_handle_t *h, const enum lt_mcounter_index_t mcounter return ret; } - ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, lt_min(h->l3.buff_len, TR01_L3_MCOUNTER_GET_RES_PACKET_SIZE)); + ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, + lt_min(h->l3.buff_len, TR01_L3_MCOUNTER_GET_RES_PACKET_SIZE)); if (ret != LT_OK) { return ret; } @@ -1409,8 +1482,8 @@ lt_ret_t lt_mcounter_get(lt_handle_t *h, const enum lt_mcounter_index_t mcounter return lt_in__mcounter_get(h, mcounter_value); } -lt_ret_t lt_mac_and_destroy(lt_handle_t *h, const lt_mac_and_destroy_slot_t slot, const uint8_t *data_out, - uint8_t *data_in) +lt_ret_t lt_mac_and_destroy(lt_handle_t *h, const lt_mac_and_destroy_slot_t slot, + const uint8_t *data_out, uint8_t *data_in) { if (!h || !data_out || !data_in || slot > TR01_MAC_AND_DESTROY_SLOT_127) { return LT_PARAM_ERR; @@ -1429,7 +1502,8 @@ lt_ret_t lt_mac_and_destroy(lt_handle_t *h, const lt_mac_and_destroy_slot_t slot return ret; } - ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, lt_min(h->l3.buff_len, TR01_L3_MAC_AND_DESTROY_RES_PACKET_SIZE)); + ret = lt_l2_recv_encrypted_res(&h->l2, h->l3.buff, + lt_min(h->l3.buff_len, TR01_L3_MAC_AND_DESTROY_RES_PACKET_SIZE)); if (ret != LT_OK) { return ret; } @@ -1487,7 +1561,9 @@ static const char *lt_ret_strs[] = {"LT_OK", const char *lt_ret_verbose(lt_ret_t ret) { - if (ret < LT_RET_T_LAST_VALUE) return lt_ret_strs[ret]; + if (ret < LT_RET_T_LAST_VALUE) { + return lt_ret_strs[ret]; + } return "FATAL ERROR, unknown return value"; } @@ -1495,34 +1571,34 @@ const char *lt_ret_verbose(lt_ret_t ret) //--------------------------------------------------------------------------------------------------------// #ifdef LT_HELPERS -struct lt_config_obj_desc_t cfg_desc_table[LT_CONFIG_OBJ_CNT] - = {{"TR01_CFG_START_UP ", TR01_CFG_START_UP_ADDR}, - {"TR01_CFG_SENSORS ", TR01_CFG_SENSORS_ADDR}, - {"TR01_CFG_DEBUG ", TR01_CFG_DEBUG_ADDR}, - {"TR01_CFG_GPO_ADDR ", TR01_CFG_GPO_ADDR}, - {"TR01_CFG_SLEEP_MODE ", TR01_CFG_SLEEP_MODE_ADDR}, - {"TR01_CFG_UAP_PAIRING_KEY_WRITE ", TR01_CFG_UAP_PAIRING_KEY_WRITE_ADDR}, - {"TR01_CFG_UAP_PAIRING_KEY_READ ", TR01_CFG_UAP_PAIRING_KEY_READ_ADDR}, - {"TR01_CFG_UAP_PAIRING_KEY_INVALIDATE ", TR01_CFG_UAP_PAIRING_KEY_INVALIDATE_ADDR}, - {"TR01_CFG_UAP_R_CONFIG_WRITE_ERASE ", TR01_CFG_UAP_R_CONFIG_WRITE_ERASE_ADDR}, - {"TR01_CFG_UAP_R_CONFIG_READ ", TR01_CFG_UAP_R_CONFIG_READ_ADDR}, - {"TR01_CFG_UAP_I_CONFIG_WRITE ", TR01_CFG_UAP_I_CONFIG_WRITE_ADDR}, - {"TR01_CFG_UAP_I_CONFIG_READ ", TR01_CFG_UAP_I_CONFIG_READ_ADDR}, - {"TR01_CFG_UAP_PING ", TR01_CFG_UAP_PING_ADDR}, - {"TR01_CFG_UAP_R_MEM_DATA_WRITE ", TR01_CFG_UAP_R_MEM_DATA_WRITE_ADDR}, - {"TR01_CFG_UAP_R_MEM_DATA_READ ", TR01_CFG_UAP_R_MEM_DATA_READ_ADDR}, - {"TR01_CFG_UAP_R_MEM_DATA_ERASE ", TR01_CFG_UAP_R_MEM_DATA_ERASE_ADDR}, - {"TR01_CFG_UAP_RANDOM_VALUE_GET ", TR01_CFG_UAP_RANDOM_VALUE_GET_ADDR}, - {"TR01_CFG_UAP_ECC_KEY_GENERATE ", TR01_CFG_UAP_ECC_KEY_GENERATE_ADDR}, - {"TR01_CFG_UAP_ECC_KEY_STORE ", TR01_CFG_UAP_ECC_KEY_STORE_ADDR}, - {"TR01_CFG_UAP_ECC_KEY_READ ", TR01_CFG_UAP_ECC_KEY_READ_ADDR}, - {"TR01_CFG_UAP_ECC_KEY_ERASE ", TR01_CFG_UAP_ECC_KEY_ERASE_ADDR}, - {"TR01_CFG_UAP_ECDSA_SIGN ", TR01_CFG_UAP_ECDSA_SIGN_ADDR}, - {"TR01_CFG_UAP_EDDSA_SIGN ", TR01_CFG_UAP_EDDSA_SIGN_ADDR}, - {"TR01_CFG_UAP_MCOUNTER_INIT ", TR01_CFG_UAP_MCOUNTER_INIT_ADDR}, - {"TR01_CFG_UAP_MCOUNTER_GET ", TR01_CFG_UAP_MCOUNTER_GET_ADDR}, - {"TR01_CFG_UAP_MCOUNTER_UPDATE ", TR01_CFG_UAP_MCOUNTER_UPDATE_ADDR}, - {"TR01_CFG_UAP_MAC_AND_DESTROY ", TR01_CFG_UAP_MAC_AND_DESTROY_ADDR}}; +struct lt_config_obj_desc_t cfg_desc_table[LT_CONFIG_OBJ_CNT] = { + {"TR01_CFG_START_UP ", TR01_CFG_START_UP_ADDR}, + {"TR01_CFG_SENSORS ", TR01_CFG_SENSORS_ADDR}, + {"TR01_CFG_DEBUG ", TR01_CFG_DEBUG_ADDR}, + {"TR01_CFG_GPO_ADDR ", TR01_CFG_GPO_ADDR}, + {"TR01_CFG_SLEEP_MODE ", TR01_CFG_SLEEP_MODE_ADDR}, + {"TR01_CFG_UAP_PAIRING_KEY_WRITE ", TR01_CFG_UAP_PAIRING_KEY_WRITE_ADDR}, + {"TR01_CFG_UAP_PAIRING_KEY_READ ", TR01_CFG_UAP_PAIRING_KEY_READ_ADDR}, + {"TR01_CFG_UAP_PAIRING_KEY_INVALIDATE ", TR01_CFG_UAP_PAIRING_KEY_INVALIDATE_ADDR}, + {"TR01_CFG_UAP_R_CONFIG_WRITE_ERASE ", TR01_CFG_UAP_R_CONFIG_WRITE_ERASE_ADDR}, + {"TR01_CFG_UAP_R_CONFIG_READ ", TR01_CFG_UAP_R_CONFIG_READ_ADDR}, + {"TR01_CFG_UAP_I_CONFIG_WRITE ", TR01_CFG_UAP_I_CONFIG_WRITE_ADDR}, + {"TR01_CFG_UAP_I_CONFIG_READ ", TR01_CFG_UAP_I_CONFIG_READ_ADDR}, + {"TR01_CFG_UAP_PING ", TR01_CFG_UAP_PING_ADDR}, + {"TR01_CFG_UAP_R_MEM_DATA_WRITE ", TR01_CFG_UAP_R_MEM_DATA_WRITE_ADDR}, + {"TR01_CFG_UAP_R_MEM_DATA_READ ", TR01_CFG_UAP_R_MEM_DATA_READ_ADDR}, + {"TR01_CFG_UAP_R_MEM_DATA_ERASE ", TR01_CFG_UAP_R_MEM_DATA_ERASE_ADDR}, + {"TR01_CFG_UAP_RANDOM_VALUE_GET ", TR01_CFG_UAP_RANDOM_VALUE_GET_ADDR}, + {"TR01_CFG_UAP_ECC_KEY_GENERATE ", TR01_CFG_UAP_ECC_KEY_GENERATE_ADDR}, + {"TR01_CFG_UAP_ECC_KEY_STORE ", TR01_CFG_UAP_ECC_KEY_STORE_ADDR}, + {"TR01_CFG_UAP_ECC_KEY_READ ", TR01_CFG_UAP_ECC_KEY_READ_ADDR}, + {"TR01_CFG_UAP_ECC_KEY_ERASE ", TR01_CFG_UAP_ECC_KEY_ERASE_ADDR}, + {"TR01_CFG_UAP_ECDSA_SIGN ", TR01_CFG_UAP_ECDSA_SIGN_ADDR}, + {"TR01_CFG_UAP_EDDSA_SIGN ", TR01_CFG_UAP_EDDSA_SIGN_ADDR}, + {"TR01_CFG_UAP_MCOUNTER_INIT ", TR01_CFG_UAP_MCOUNTER_INIT_ADDR}, + {"TR01_CFG_UAP_MCOUNTER_GET ", TR01_CFG_UAP_MCOUNTER_GET_ADDR}, + {"TR01_CFG_UAP_MCOUNTER_UPDATE ", TR01_CFG_UAP_MCOUNTER_UPDATE_ADDR}, + {"TR01_CFG_UAP_MAC_AND_DESTROY ", TR01_CFG_UAP_MAC_AND_DESTROY_ADDR}}; lt_ret_t lt_read_whole_R_config(lt_handle_t *h, struct lt_config_t *config) { @@ -1604,7 +1680,8 @@ lt_ret_t lt_write_whole_I_config(lt_handle_t *h, const struct lt_config_t *confi return LT_OK; } -lt_ret_t lt_verify_chip_and_start_secure_session(lt_handle_t *h, const uint8_t *shipriv, const uint8_t *shipub, +lt_ret_t lt_verify_chip_and_start_secure_session(lt_handle_t *h, const uint8_t *shipriv, + const uint8_t *shipub, const lt_pkey_index_t pkey_index) { if (!h || !shipriv || !shipub || (pkey_index > TR01_PAIRING_KEY_SLOT_INDEX_3)) { @@ -1640,11 +1717,11 @@ lt_ret_t lt_verify_chip_and_start_secure_session(lt_handle_t *h, const uint8_t * uint8_t cert_tr01[TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE] = {0}; uint8_t cert_root[TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE] = {0}; - struct lt_cert_store_t cert_store - = {.cert_len = {0, 0, 0, 0}, - .buf_len = {TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, - TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE}, - .certs = {cert_ese, cert_xxxx, cert_tr01, cert_root}}; + struct lt_cert_store_t cert_store = { + .cert_len = {0, 0, 0, 0}, + .buf_len = {TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, + TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE, TR01_L2_GET_INFO_REQ_CERT_SIZE_SINGLE}, + .certs = {cert_ese, cert_xxxx, cert_tr01, cert_root}}; ret = lt_get_info_cert_store(h, &cert_store); if (ret != LT_OK) { @@ -1666,7 +1743,8 @@ lt_ret_t lt_verify_chip_and_start_secure_session(lt_handle_t *h, const uint8_t * return LT_OK; } -lt_ret_t lt_print_bytes(const uint8_t *bytes, const size_t bytes_cnt, char *out_buf, const size_t out_buf_size) +lt_ret_t lt_print_bytes(const uint8_t *bytes, const size_t bytes_cnt, char *out_buf, + const size_t out_buf_size) { if (!bytes || !out_buf || out_buf_size < (bytes_cnt * 2 + 1)) { // Write empty string if buffer too small @@ -1690,7 +1768,8 @@ lt_ret_t lt_print_bytes(const uint8_t *bytes, const size_t bytes_cnt, char *out_ return LT_OK; } -lt_ret_t lt_print_chip_id(const struct lt_chip_id_t *chip_id, int (*print_func)(const char *format, ...)) +lt_ret_t lt_print_chip_id(const struct lt_chip_id_t *chip_id, + int (*print_func)(const char *format, ...)) { if (!chip_id || !print_func) { return LT_PARAM_ERR; @@ -1698,43 +1777,41 @@ lt_ret_t lt_print_chip_id(const struct lt_chip_id_t *chip_id, int (*print_func)( char print_bytes_buff[LT_CHIP_ID_FIELD_MAX_SIZE]; - if (LT_OK - != lt_print_bytes(chip_id->chip_id_ver, sizeof(chip_id->chip_id_ver), print_bytes_buff, - sizeof(print_bytes_buff)) - || 0 > print_func("CHIP_ID ver = 0x%s (v%" PRIu8 ".%" PRIu8 ".%" PRIu8 ".%" PRIu8 ")\n", - print_bytes_buff, chip_id->chip_id_ver[0], chip_id->chip_id_ver[1], chip_id->chip_id_ver[2], - chip_id->chip_id_ver[3])) { + if (LT_OK != lt_print_bytes(chip_id->chip_id_ver, sizeof(chip_id->chip_id_ver), print_bytes_buff, + sizeof(print_bytes_buff)) || + 0 > print_func("CHIP_ID ver = 0x%s (v%" PRIu8 ".%" PRIu8 ".%" PRIu8 ".%" PRIu8 + ")\n", + print_bytes_buff, chip_id->chip_id_ver[0], chip_id->chip_id_ver[1], + chip_id->chip_id_ver[2], chip_id->chip_id_ver[3])) { return LT_FAIL; } - if (LT_OK - != lt_print_bytes(chip_id->fl_chip_info, sizeof(chip_id->fl_chip_info), print_bytes_buff, - sizeof(print_bytes_buff)) - || 0 > print_func("FL_PROD_DATA = 0x%s (%s)\n", print_bytes_buff, - chip_id->fl_chip_info[0] == 0x01 ? "PASSED" : "N/A")) { + if (LT_OK != lt_print_bytes(chip_id->fl_chip_info, sizeof(chip_id->fl_chip_info), print_bytes_buff, + sizeof(print_bytes_buff)) || + 0 > print_func("FL_PROD_DATA = 0x%s (%s)\n", print_bytes_buff, + chip_id->fl_chip_info[0] == 0x01 ? "PASSED" : "N/A")) { return LT_FAIL; } - if (LT_OK - != lt_print_bytes(chip_id->func_test_info, sizeof(chip_id->func_test_info), print_bytes_buff, - sizeof(print_bytes_buff)) - || 0 > print_func("MAN_FUNC_TEST = 0x%s (%s)\n", print_bytes_buff, - chip_id->func_test_info[0] == 0x01 ? "PASSED" : "N/A")) { + if (LT_OK != lt_print_bytes(chip_id->func_test_info, sizeof(chip_id->func_test_info), + print_bytes_buff, sizeof(print_bytes_buff)) || + 0 > print_func("MAN_FUNC_TEST = 0x%s (%s)\n", print_bytes_buff, + chip_id->func_test_info[0] == 0x01 ? "PASSED" : "N/A")) { return LT_FAIL; } - if (LT_OK - != lt_print_bytes(chip_id->silicon_rev, sizeof(chip_id->silicon_rev), print_bytes_buff, - sizeof(print_bytes_buff)) - || 0 > print_func("Silicon rev = 0x%s (%c%c%c%c)\n", print_bytes_buff, chip_id->silicon_rev[0], - chip_id->silicon_rev[1], chip_id->silicon_rev[2], chip_id->silicon_rev[3])) { + if (LT_OK != lt_print_bytes(chip_id->silicon_rev, sizeof(chip_id->silicon_rev), print_bytes_buff, + sizeof(print_bytes_buff)) || + 0 > print_func("Silicon rev = 0x%s (%c%c%c%c)\n", print_bytes_buff, + chip_id->silicon_rev[0], chip_id->silicon_rev[1], chip_id->silicon_rev[2], + chip_id->silicon_rev[3])) { return LT_FAIL; } - uint16_t packg_type_id = ((uint16_t)chip_id->packg_type_id[0] << 8) | ((uint16_t)chip_id->packg_type_id[1]); - if (LT_OK - != lt_print_bytes(chip_id->packg_type_id, sizeof(chip_id->packg_type_id), print_bytes_buff, - sizeof(print_bytes_buff))) { + uint16_t packg_type_id = ((uint16_t)chip_id->packg_type_id[0] << 8) | + ((uint16_t)chip_id->packg_type_id[1]); + if (LT_OK != lt_print_bytes(chip_id->packg_type_id, sizeof(chip_id->packg_type_id), + print_bytes_buff, sizeof(print_bytes_buff))) { return LT_FAIL; } const char *packg_type_id_str; @@ -1755,21 +1832,25 @@ lt_ret_t lt_print_chip_id(const struct lt_chip_id_t *chip_id, int (*print_func)( return LT_FAIL; } - if (0 > print_func("Prov info ver = 0x%02" PRIX8 " (v%" PRIu8 ")\n", chip_id->prov_ver_fab_id_pn[0], - chip_id->prov_ver_fab_id_pn[0])) { + if (0 > print_func("Prov info ver = 0x%02" PRIX8 " (v%" PRIu8 ")\n", + chip_id->prov_ver_fab_id_pn[0], chip_id->prov_ver_fab_id_pn[0])) { return LT_FAIL; } - uint16_t parsed_fab_id = ((chip_id->prov_ver_fab_id_pn[1] << 4) | (chip_id->prov_ver_fab_id_pn[2] >> 4)) & 0xfff; + uint16_t parsed_fab_id = ((chip_id->prov_ver_fab_id_pn[1] << 4) | + (chip_id->prov_ver_fab_id_pn[2] >> 4)) & + 0xfff; switch (parsed_fab_id) { case TR01_FAB_ID_TROPIC_SQUARE_LAB: - if (0 > print_func("Fab ID = 0x%03" PRIX16 " (%s)\n", parsed_fab_id, "Tropic Square Lab")) { + if (0 > print_func("Fab ID = 0x%03" PRIX16 " (%s)\n", parsed_fab_id, + "Tropic Square Lab")) { return LT_FAIL; } break; case TR01_FAB_ID_EPS_BRNO: - if (0 > print_func("Fab ID = 0x%03" PRIX16 " (%s)\n", parsed_fab_id, "EPS Global - Brno")) { + if (0 > print_func("Fab ID = 0x%03" PRIX16 " (%s)\n", parsed_fab_id, + "EPS Global - Brno")) { return LT_FAIL; } break; @@ -1781,33 +1862,34 @@ lt_ret_t lt_print_chip_id(const struct lt_chip_id_t *chip_id, int (*print_func)( break; } - uint16_t parsed_short_pn = ((chip_id->prov_ver_fab_id_pn[2] << 8) | (chip_id->prov_ver_fab_id_pn[3])) & 0xfff; + uint16_t parsed_short_pn = ((chip_id->prov_ver_fab_id_pn[2] << 8) | + (chip_id->prov_ver_fab_id_pn[3])) & + 0xfff; if (0 > print_func("P/N ID (short P/N) = 0x%03" PRIX16 "\n", parsed_short_pn)) { return LT_FAIL; } - if (LT_OK - != lt_print_bytes(chip_id->provisioning_date, sizeof(chip_id->provisioning_date), print_bytes_buff, - sizeof(print_bytes_buff)) - || 0 > print_func("Prov date = 0x%s\n", print_bytes_buff)) { + if (LT_OK != lt_print_bytes(chip_id->provisioning_date, sizeof(chip_id->provisioning_date), + print_bytes_buff, sizeof(print_bytes_buff)) || + 0 > print_func("Prov date = 0x%s\n", print_bytes_buff)) { return LT_FAIL; } - if (LT_OK != lt_print_bytes(chip_id->hsm_ver, sizeof(chip_id->hsm_ver), print_bytes_buff, sizeof(print_bytes_buff)) - || 0 > print_func("HSM HW/FW/SW ver = 0x%s\n", print_bytes_buff)) { + if (LT_OK != lt_print_bytes(chip_id->hsm_ver, sizeof(chip_id->hsm_ver), print_bytes_buff, + sizeof(print_bytes_buff)) || + 0 > print_func("HSM HW/FW/SW ver = 0x%s\n", print_bytes_buff)) { return LT_FAIL; } - if (LT_OK - != lt_print_bytes(chip_id->prog_ver, sizeof(chip_id->prog_ver), print_bytes_buff, sizeof(print_bytes_buff)) - || 0 > print_func("Programmer ver = 0x%s\n", print_bytes_buff)) { + if (LT_OK != lt_print_bytes(chip_id->prog_ver, sizeof(chip_id->prog_ver), print_bytes_buff, + sizeof(print_bytes_buff)) || + 0 > print_func("Programmer ver = 0x%s\n", print_bytes_buff)) { return LT_FAIL; } - if (LT_OK - != lt_print_bytes((uint8_t *)&chip_id->ser_num, sizeof(chip_id->ser_num), print_bytes_buff, - sizeof(print_bytes_buff)) - || 0 > print_func("S/N = 0x%s\n", print_bytes_buff)) { + if (LT_OK != lt_print_bytes((uint8_t *)&chip_id->ser_num, sizeof(chip_id->ser_num), + print_bytes_buff, sizeof(print_bytes_buff)) || + 0 > print_func("S/N = 0x%s\n", print_bytes_buff)) { return LT_FAIL; } @@ -1815,59 +1897,54 @@ lt_ret_t lt_print_chip_id(const struct lt_chip_id_t *chip_id, int (*print_func)( uint8_t pn_data[16]; // 15B for data, last byte for '\0' memcpy(pn_data, &chip_id->part_num_data[1], pn_len); pn_data[pn_len] = '\0'; - if (LT_OK - != lt_print_bytes(chip_id->part_num_data, sizeof(chip_id->part_num_data), print_bytes_buff, - sizeof(print_bytes_buff)) - || 0 > print_func("P/N (long) = 0x%s (%s)\n", print_bytes_buff, pn_data)) { + if (LT_OK != lt_print_bytes(chip_id->part_num_data, sizeof(chip_id->part_num_data), + print_bytes_buff, sizeof(print_bytes_buff)) || + 0 > print_func("P/N (long) = 0x%s (%s)\n", print_bytes_buff, pn_data)) { return LT_FAIL; } - if (LT_OK - != lt_print_bytes(chip_id->prov_templ_ver, sizeof(chip_id->prov_templ_ver), print_bytes_buff, - sizeof(print_bytes_buff)) - || 0 > print_func("Prov template ver = 0x%s (v%" PRIu8 ".%" PRIu8 ")\n", print_bytes_buff, - chip_id->prov_templ_ver[0], chip_id->prov_templ_ver[1])) { + if (LT_OK != lt_print_bytes(chip_id->prov_templ_ver, sizeof(chip_id->prov_templ_ver), + print_bytes_buff, sizeof(print_bytes_buff)) || + 0 > print_func("Prov template ver = 0x%s (v%" PRIu8 ".%" PRIu8 ")\n", print_bytes_buff, + chip_id->prov_templ_ver[0], chip_id->prov_templ_ver[1])) { return LT_FAIL; } - if (LT_OK - != lt_print_bytes(chip_id->prov_templ_tag, sizeof(chip_id->prov_templ_tag), print_bytes_buff, - sizeof(print_bytes_buff)) - || 0 > print_func("Prov template tag = 0x%s\n", print_bytes_buff)) { + if (LT_OK != lt_print_bytes(chip_id->prov_templ_tag, sizeof(chip_id->prov_templ_tag), + print_bytes_buff, sizeof(print_bytes_buff)) || + 0 > print_func("Prov template tag = 0x%s\n", print_bytes_buff)) { return LT_FAIL; } - if (LT_OK - != lt_print_bytes(chip_id->prov_spec_ver, sizeof(chip_id->prov_spec_ver), print_bytes_buff, - sizeof(print_bytes_buff)) - || 0 > print_func("Prov specification ver = 0x%s (v%" PRIu8 ".%" PRIu8 ")\n", print_bytes_buff, - chip_id->prov_spec_ver[0], chip_id->prov_spec_ver[1])) { + if (LT_OK != lt_print_bytes(chip_id->prov_spec_ver, sizeof(chip_id->prov_spec_ver), + print_bytes_buff, sizeof(print_bytes_buff)) || + 0 > print_func("Prov specification ver = 0x%s (v%" PRIu8 ".%" PRIu8 ")\n", print_bytes_buff, + chip_id->prov_spec_ver[0], chip_id->prov_spec_ver[1])) { return LT_FAIL; } - if (LT_OK - != lt_print_bytes(chip_id->prov_spec_tag, sizeof(chip_id->prov_spec_tag), print_bytes_buff, - sizeof(print_bytes_buff)) - || 0 > print_func("Prov specification tag = 0x%s\n", print_bytes_buff)) { + if (LT_OK != lt_print_bytes(chip_id->prov_spec_tag, sizeof(chip_id->prov_spec_tag), + print_bytes_buff, sizeof(print_bytes_buff)) || + 0 > print_func("Prov specification tag = 0x%s\n", print_bytes_buff)) { return LT_FAIL; } - if (LT_OK - != lt_print_bytes(chip_id->batch_id, sizeof(chip_id->batch_id), print_bytes_buff, sizeof(print_bytes_buff)) - || 0 > print_func("Batch ID = 0x%s\n", print_bytes_buff)) { + if (LT_OK != lt_print_bytes(chip_id->batch_id, sizeof(chip_id->batch_id), print_bytes_buff, + sizeof(print_bytes_buff)) || + 0 > print_func("Batch ID = 0x%s\n", print_bytes_buff)) { return LT_FAIL; } return LT_OK; } -lt_ret_t lt_do_mutable_fw_update(lt_handle_t *h, const uint8_t *update_data, const uint16_t update_data_size, - const lt_bank_id_t bank_id) +lt_ret_t lt_do_mutable_fw_update(lt_handle_t *h, const uint8_t *update_data, + const uint16_t update_data_size, const lt_bank_id_t bank_id) { #ifdef ABAB - if (!h || !update_data || update_data_size > TR01_MUTABLE_FW_UPDATE_SIZE_MAX - || ((bank_id != TR01_FW_BANK_FW1) && (bank_id != TR01_FW_BANK_FW2) && (bank_id != TR01_FW_BANK_SPECT1) - && (bank_id != TR01_FW_BANK_SPECT2))) { + if (!h || !update_data || update_data_size > TR01_MUTABLE_FW_UPDATE_SIZE_MAX || + ((bank_id != TR01_FW_BANK_FW1) && (bank_id != TR01_FW_BANK_FW2) && + (bank_id != TR01_FW_BANK_SPECT1) && (bank_id != TR01_FW_BANK_SPECT2))) { return LT_PARAM_ERR; } lt_ret_t ret = lt_mutable_fw_erase(h, bank_id); @@ -1905,7 +1982,8 @@ lt_ret_t lt_do_mutable_fw_update(lt_handle_t *h, const uint8_t *update_data, con return LT_OK; } -lt_ret_t lt_print_fw_header(lt_handle_t *h, const lt_bank_id_t bank_id, int (*print_func)(const char *format, ...)) +lt_ret_t lt_print_fw_header(lt_handle_t *h, const lt_bank_id_t bank_id, + int (*print_func)(const char *format, ...)) { if (!h || !print_func) { return LT_PARAM_ERR; @@ -1939,22 +2017,24 @@ lt_ret_t lt_print_fw_header(lt_handle_t *h, const lt_bank_id_t bank_id, int (*pr } if (read_header_size == TR01_L2_GET_INFO_FW_HEADER_SIZE_BOOT_V1) { - print_func(" Bootloader v1.0.1 detected, reading %dB header\n", TR01_L2_GET_INFO_FW_HEADER_SIZE_BOOT_V1); + print_func(" Bootloader v1.0.1 detected, reading %dB header\n", + TR01_L2_GET_INFO_FW_HEADER_SIZE_BOOT_V1); struct lt_header_boot_v1_t *p_h = (struct lt_header_boot_v1_t *)header; - print_func(" Type: %02" PRIX8 "%02" PRIX8 "%02" PRIX8 "%02" PRIX8 "\n", p_h->type[3], p_h->type[2], - p_h->type[1], p_h->type[0]); - print_func(" Version: %02" PRIX8 "%02" PRIX8 "%02" PRIX8 "%02" PRIX8 "\n", p_h->version[3], - p_h->version[2], p_h->version[1], p_h->version[0]); - print_func(" Size: %02" PRIX8 "%02" PRIX8 "%02" PRIX8 "%02" PRIX8 "\n", p_h->size[3], p_h->size[2], - p_h->size[1], p_h->size[0]); - print_func(" Git hash: %02" PRIX8 "%02" PRIX8 "%02" PRIX8 "%02" PRIX8 "\n", p_h->git_hash[3], - p_h->git_hash[2], p_h->git_hash[1], p_h->git_hash[0]); - print_func(" FW hash: %02" PRIX8 "%02" PRIX8 "%02" PRIX8 "%02" PRIX8 "\n", p_h->hash[3], p_h->hash[2], - p_h->hash[1], p_h->hash[0]); + print_func(" Type: %02" PRIX8 "%02" PRIX8 "%02" PRIX8 "%02" PRIX8 "\n", p_h->type[3], + p_h->type[2], p_h->type[1], p_h->type[0]); + print_func(" Version: %02" PRIX8 "%02" PRIX8 "%02" PRIX8 "%02" PRIX8 "\n", + p_h->version[3], p_h->version[2], p_h->version[1], p_h->version[0]); + print_func(" Size: %02" PRIX8 "%02" PRIX8 "%02" PRIX8 "%02" PRIX8 "\n", p_h->size[3], + p_h->size[2], p_h->size[1], p_h->size[0]); + print_func(" Git hash: %02" PRIX8 "%02" PRIX8 "%02" PRIX8 "%02" PRIX8 "\n", + p_h->git_hash[3], p_h->git_hash[2], p_h->git_hash[1], p_h->git_hash[0]); + print_func(" FW hash: %02" PRIX8 "%02" PRIX8 "%02" PRIX8 "%02" PRIX8 "\n", p_h->hash[3], + p_h->hash[2], p_h->hash[1], p_h->hash[0]); } else if (read_header_size == TR01_L2_GET_INFO_FW_HEADER_SIZE_BOOT_V2) { - print_func(" Bootloader v2.0.1 detected, reading %dB header\n", TR01_L2_GET_INFO_FW_HEADER_SIZE_BOOT_V2); + print_func(" Bootloader v2.0.1 detected, reading %dB header\n", + TR01_L2_GET_INFO_FW_HEADER_SIZE_BOOT_V2); struct lt_header_boot_v2_t *p_h = (struct lt_header_boot_v2_t *)header; print_func(" Type: %04" PRIX16 "\n", p_h->type); diff --git a/src/libtropic_default_sh0_keys.c b/src/libtropic_default_sh0_keys.c index 3546b657e..69020144e 100644 --- a/src/libtropic_default_sh0_keys.c +++ b/src/libtropic_default_sh0_keys.c @@ -8,18 +8,18 @@ #include "libtropic_common.h" -const uint8_t sh0priv_eng_sample[] - = {0xd0, 0x99, 0x92, 0xb1, 0xf1, 0x7a, 0xbc, 0x4d, 0xb9, 0x37, 0x17, 0x68, 0xa2, 0x7d, 0xa0, 0x5b, - 0x18, 0xfa, 0xb8, 0x56, 0x13, 0xa7, 0x84, 0x2c, 0xa6, 0x4c, 0x79, 0x10, 0xf2, 0x2e, 0x71, 0x6b}; +const uint8_t sh0priv_eng_sample[] = {0xd0, 0x99, 0x92, 0xb1, 0xf1, 0x7a, 0xbc, 0x4d, 0xb9, 0x37, 0x17, + 0x68, 0xa2, 0x7d, 0xa0, 0x5b, 0x18, 0xfa, 0xb8, 0x56, 0x13, 0xa7, + 0x84, 0x2c, 0xa6, 0x4c, 0x79, 0x10, 0xf2, 0x2e, 0x71, 0x6b}; -const uint8_t sh0pub_eng_sample[] - = {0xe7, 0xf7, 0x35, 0xba, 0x19, 0xa3, 0x3f, 0xd6, 0x73, 0x23, 0xab, 0x37, 0x26, 0x2d, 0xe5, 0x36, - 0x08, 0xca, 0x57, 0x85, 0x76, 0x53, 0x43, 0x52, 0xe1, 0x8f, 0x64, 0xe6, 0x13, 0xd3, 0x8d, 0x54}; +const uint8_t sh0pub_eng_sample[] = {0xe7, 0xf7, 0x35, 0xba, 0x19, 0xa3, 0x3f, 0xd6, 0x73, 0x23, 0xab, + 0x37, 0x26, 0x2d, 0xe5, 0x36, 0x08, 0xca, 0x57, 0x85, 0x76, 0x53, + 0x43, 0x52, 0xe1, 0x8f, 0x64, 0xe6, 0x13, 0xd3, 0x8d, 0x54}; -const uint8_t sh0priv_prod0[] - = {0x28, 0x3f, 0x5a, 0x0f, 0xfc, 0x41, 0xcf, 0x50, 0x98, 0xa8, 0xe1, 0x7d, 0xb6, 0x37, 0x2c, 0x3c, - 0xaa, 0xd1, 0xee, 0xee, 0xdf, 0x0f, 0x75, 0xbc, 0x3f, 0xbf, 0xcd, 0x9c, 0xab, 0x3d, 0xe9, 0x72}; +const uint8_t sh0priv_prod0[] = {0x28, 0x3f, 0x5a, 0x0f, 0xfc, 0x41, 0xcf, 0x50, 0x98, 0xa8, 0xe1, + 0x7d, 0xb6, 0x37, 0x2c, 0x3c, 0xaa, 0xd1, 0xee, 0xee, 0xdf, 0x0f, + 0x75, 0xbc, 0x3f, 0xbf, 0xcd, 0x9c, 0xab, 0x3d, 0xe9, 0x72}; -const uint8_t sh0pub_prod0[] - = {0xf9, 0x75, 0xeb, 0x3c, 0x2f, 0xd7, 0x90, 0xc9, 0x6f, 0x29, 0x4f, 0x15, 0x57, 0xa5, 0x03, 0x17, - 0x80, 0xc9, 0xaa, 0xfa, 0x14, 0x0d, 0xa2, 0x8f, 0x55, 0xe7, 0x51, 0x57, 0x37, 0xb2, 0x50, 0x2c}; \ No newline at end of file +const uint8_t sh0pub_prod0[] = {0xf9, 0x75, 0xeb, 0x3c, 0x2f, 0xd7, 0x90, 0xc9, 0x6f, 0x29, 0x4f, + 0x15, 0x57, 0xa5, 0x03, 0x17, 0x80, 0xc9, 0xaa, 0xfa, 0x14, 0x0d, + 0xa2, 0x8f, 0x55, 0xe7, 0x51, 0x57, 0x37, 0xb2, 0x50, 0x2c}; \ No newline at end of file diff --git a/src/libtropic_l2.c b/src/libtropic_l2.c index 70af59114..060cd3dcb 100644 --- a/src/libtropic_l2.c +++ b/src/libtropic_l2.c @@ -73,8 +73,9 @@ lt_ret_t lt_l2_receive(lt_l2_state_t *s2) // if the chip started to reboot. See Erratum CI_TR01_ERR_2025091800. // // If the reboot was successful, we only check the frame up to the first CRC byte. - if (s2->startup_req_sent && s2->buff[TR01_L2_STATUS_OFFSET] == TR01_L2_STATUS_REQUEST_OK - && s2->buff[TR01_L2_RSP_LEN_OFFSET] == 0x00 && s2->buff[TR01_L2_RSP_DATA_RSP_CRC_OFFSET] == 0x03) { + if (s2->startup_req_sent && s2->buff[TR01_L2_STATUS_OFFSET] == TR01_L2_STATUS_REQUEST_OK && + s2->buff[TR01_L2_RSP_LEN_OFFSET] == 0x00 && + s2->buff[TR01_L2_RSP_DATA_RSP_CRC_OFFSET] == 0x03) { return LT_OK; } @@ -104,7 +105,7 @@ lt_ret_t lt_l2_send_encrypted_cmd(lt_l2_state_t *s2, uint8_t *buff, uint16_t buf int ret = LT_FAIL; - // There is l3 payload in passed buffer. + // There is L3 payload in provided buffer (buff). // First check how much data are to be send and if it actually fits into that buffer, // there must be a space for 2B of size value, ?B of command (ID + data) and 16B of TAG. struct lt_l3_gen_frame_t *p_frame = (struct lt_l3_gen_frame_t *)buff; @@ -112,33 +113,36 @@ lt_ret_t lt_l2_send_encrypted_cmd(lt_l2_state_t *s2, uint8_t *buff, uint16_t buf // Prevent sending more data than is the max size of L3 packet. if (packet_size > TR01_L3_PACKET_MAX_SIZE) { - LT_LOG_ERROR("Packet size %" PRIu16 "exceeds maximum L3 packet size %u", packet_size, TR01_L3_PACKET_MAX_SIZE); + LT_LOG_ERROR("Packet size %" PRIu16 "exceeds maximum L3 packet size %u", packet_size, + TR01_L3_PACKET_MAX_SIZE); return LT_L3_DATA_LEN_ERROR; } - // Prevent sending more data than is the size of passed buffer. + // Prevent sending more data than is the size of the provided buffer. if (packet_size > buff_len) { LT_LOG_ERROR("Packet size %" PRIu16 "exceeds L3 buffer size %" PRIu16, packet_size, buff_len); return LT_PARAM_ERR; } - // Setup a request pointer to l2 buffer, which is placed in handle + // Setup a request pointer to L2 buffer, which is placed in handle struct lt_l2_encrypted_cmd_req_t *req = (struct lt_l2_encrypted_cmd_req_t *)s2->buff; // Calculate number of chunks to send. // First, get the number of full chunks. uint16_t full_chunk_num = (packet_size / TR01_L2_CHUNK_MAX_DATA_SIZE); - // Second, if packet_size is not divisible by the maximum chunk size, one additional smaller chunk will be created, - // which we add to the total count. - uint16_t chunk_num = (packet_size % TR01_L2_CHUNK_MAX_DATA_SIZE) == 0 ? full_chunk_num : full_chunk_num + 1; + // Second, if packet_size is not divisible by the maximum chunk size, one additional smaller chunk + // will be created, which we add to the total count. + uint16_t chunk_num = (packet_size % TR01_L2_CHUNK_MAX_DATA_SIZE) == 0 ? full_chunk_num + : full_chunk_num + 1; // Calculate the length of the last chunk uint16_t last_chunk_len = packet_size - ((chunk_num - 1) * TR01_L2_CHUNK_MAX_DATA_SIZE); uint16_t buff_offset = 0; - // Split encrypted buffer into chunks and proceed them into l2 transfers: + // Split encrypted buffer into chunks and proceed them into L2 transfers: for (int i = 0; i < chunk_num; i++) { req->req_id = TR01_L2_ENCRYPTED_CMD_REQ_ID; - // If the currently processed chunk is the last one, get its length (may be shorter than L2_CHUNK_MAX_DATA_SIZE) + // If the currently processed chunk is the last one, get its length (may be shorter than + // L2_CHUNK_MAX_DATA_SIZE) if (i == (chunk_num - 1)) { req->req_len = last_chunk_len; } @@ -149,13 +153,13 @@ lt_ret_t lt_l2_send_encrypted_cmd(lt_l2_state_t *s2, uint8_t *buff, uint16_t buf buff_offset += req->req_len; // Move offset for next chunk add_crc(req); - // Send l2 request cointaining a chunk from l3 buff + // Send L2 request containing a chunk from L3 buff ret = lt_l1_write(s2, 2 + req->req_len + 2, LT_L1_TIMEOUT_MS_DEFAULT); if (ret != LT_OK) { return ret; } - // Read a response on this l2 request + // Read a response on this L2 request ret = lt_l1_read(s2, TR01_L1_LEN_MAX, LT_L1_TIMEOUT_MS_DEFAULT); if (ret != LT_OK) { return ret; @@ -174,28 +178,28 @@ lt_ret_t lt_l2_send_encrypted_cmd(lt_l2_state_t *s2, uint8_t *buff, uint16_t buf lt_ret_t lt_l2_recv_encrypted_res(lt_l2_state_t *s2, uint8_t *buff, uint16_t max_len) { if (!s2 - // Max len must be definitively smaller than size of l3 buffer + // Max len must be definitively smaller than size of L3 buffer || max_len > TR01_L3_PACKET_MAX_SIZE || !buff) { return LT_PARAM_ERR; } int ret = LT_FAIL; - // Setup a response pointer to l2 buffer, which is placed in handle + // Setup a response pointer to L2 buffer, which is placed in handle struct lt_l2_encrypted_cmd_rsp_t *resp = (struct lt_l2_encrypted_cmd_rsp_t *)s2->buff; - // Position into l3 buffer where processed l2 chunk will be copied into + // Position into L3 buffer where processed L2 chunk will be copied into uint16_t offset = 0; // Tropic can respond with various lengths of chunks, this loop should be limited uint16_t loops = 0; do { - /* Get one l2 frame of a device's response */ + // Get one L2 frame of a device's response ret = lt_l1_read(s2, TR01_L1_LEN_MAX, LT_L1_TIMEOUT_MS_DEFAULT); if (ret != LT_OK) { return ret; } - // Prevent receiving more data then is compiled size of l3 buffer + // Prevent receiving more data than is the size of the provided L3 buffer. if (offset + resp->rsp_len > max_len) { return LT_L2_RSP_LEN_ERROR; } @@ -204,17 +208,17 @@ lt_ret_t lt_l2_recv_encrypted_res(lt_l2_state_t *s2, uint8_t *buff, uint16_t max ret = lt_l2_frame_check(s2->buff); switch (ret) { case LT_L2_RES_CONT: - // Copy content of l2 into certain offset of l3 buffer + // Copy content of L2 into current offset of the L3 buffer memcpy(buff + offset, (struct l2_encrypted_rsp_t *)resp->l3_chunk, resp->rsp_len); offset += resp->rsp_len; loops++; break; case LT_OK: - // This was last l2 frame of l3 packet, copy it and return + // This was last L2 frame of L3 packet, copy it and return memcpy(buff + offset, (struct l2_encrypted_rsp_t *)resp->l3_chunk, resp->rsp_len); return LT_OK; default: - // Any other L2 packet's status is not expected + // Any other frame status is not expected return ret; } } while (loops < LT_L2_RECV_ENC_RES_MAX_LOOPS); diff --git a/src/libtropic_l3.c b/src/libtropic_l3.c index baee02ae5..33ca4d830 100644 --- a/src/libtropic_l3.c +++ b/src/libtropic_l3.c @@ -17,6 +17,7 @@ #include "libtropic_common.h" #include "libtropic_l2.h" #include "libtropic_port.h" +#include "libtropic_secure_memzero.h" #include "lt_aesgcm.h" #include "lt_hkdf.h" #include "lt_l1.h" @@ -24,11 +25,11 @@ #include "lt_l3_api_structs.h" #include "lt_l3_process.h" #include "lt_port_wrap.h" -#include "lt_secure_memzero.h" #include "lt_sha256.h" #include "lt_x25519.h" -lt_ret_t lt_out__session_start(lt_handle_t *h, const lt_pkey_index_t pkey_index, lt_host_eph_keys_t *host_eph_keys) +lt_ret_t lt_out__session_start(lt_handle_t *h, const lt_pkey_index_t pkey_index, + lt_host_eph_keys_t *host_eph_keys) { if (!h || (pkey_index > TR01_PAIRING_KEY_SLOT_INDEX_3) || !host_eph_keys) { return LT_PARAM_ERR; @@ -36,7 +37,8 @@ lt_ret_t lt_out__session_start(lt_handle_t *h, const lt_pkey_index_t pkey_index, // Remove any previous session data and init IVs. // In case we reuse handle and use separate l3 buffer, we need to ensure that IV's are zeroed, - // because on session start we expect IV's to be 0. It does not hurt to zero them anyway on session start. + // because on session start we expect IV's to be 0. It does not hurt to zero them anyway on session + // start. lt_l3_invalidate_host_session_data(&h->l3); // Create ephemeral host keys @@ -63,23 +65,27 @@ lt_ret_t lt_out__session_start(lt_handle_t *h, const lt_pkey_index_t pkey_index, } lt_ret_t lt_in__session_start(lt_handle_t *h, const uint8_t *stpub, const lt_pkey_index_t pkey_index, - const uint8_t *shipriv, const uint8_t *shipub, lt_host_eph_keys_t *host_eph_keys) + const uint8_t *shipriv, const uint8_t *shipub, + lt_host_eph_keys_t *host_eph_keys) { - if (!h || !stpub || (pkey_index > TR01_PAIRING_KEY_SLOT_INDEX_3) || !shipriv || !shipub || !host_eph_keys) { + if (!h || !stpub || (pkey_index > TR01_PAIRING_KEY_SLOT_INDEX_3) || !shipriv || !shipub || + !host_eph_keys) { return LT_PARAM_ERR; } // Remove any previous session data and init IVs. // In case we reuse handle and use separate l3 buffer, we need to ensure that IV's are zeroed, - // because on session start we expect IV's to be 0. It does not hurt to zero them anyway on session start. + // because on session start we expect IV's to be 0. It does not hurt to zero them anyway on session + // start. lt_l3_invalidate_host_session_data(&h->l3); // Setup a response pointer to l2 buffer, which is placed in handle struct lt_l2_handshake_rsp_t *p_rsp = (struct lt_l2_handshake_rsp_t *)h->l2.buff; // Noise_KK1_25519_AESGCM_SHA256\x00\x00\x00 - uint8_t protocol_name[32] = {'N', 'o', 'i', 's', 'e', '_', 'K', 'K', '1', '_', '2', '5', '5', '1', '9', '_', - 'A', 'E', 'S', 'G', 'C', 'M', '_', 'S', 'H', 'A', '2', '5', '6', 0x00, 0x00, 0x00}; + uint8_t protocol_name[32] = {'N', 'o', 'i', 's', 'e', '_', 'K', 'K', '1', '_', '2', + '5', '5', '1', '9', '_', 'A', 'E', 'S', 'G', 'C', 'M', + '_', 'S', 'H', 'A', '2', '5', '6', 0x00, 0x00, 0x00}; uint8_t hash[LT_SHA256_DIGEST_LENGTH] = {0}; lt_ret_t ret; lt_ret_t ret_unused; @@ -198,8 +204,10 @@ lt_ret_t lt_in__session_start(lt_handle_t *h, const uint8_t *stpub, const lt_pke uint8_t output_1[33] = {0}; // Temp storage for ck, kcmd. uint8_t output_2[32] = {0}; // Temp storage for kauth. uint8_t shared_secret[TR01_X25519_KEY_LEN] = {0}; - uint8_t kcmd[TR01_AES256_KEY_LEN] = {0}; // AES256 key used for L3 command packet encryption/decryption. - uint8_t kres[TR01_AES256_KEY_LEN] = {0}; // AES256 key used for L3 result packet encryption/decryption. + uint8_t kcmd[TR01_AES256_KEY_LEN] = { + 0}; // AES256 key used for L3 command packet encryption/decryption. + uint8_t kres[TR01_AES256_KEY_LEN] = { + 0}; // AES256 key used for L3 result packet encryption/decryption. uint8_t kauth[TR01_AES256_KEY_LEN] = {0}; // AES256 key used for handshake authentication. // ck = protocol_name @@ -208,7 +216,8 @@ lt_ret_t lt_in__session_start(lt_handle_t *h, const uint8_t *stpub, const lt_pke if (ret != LT_OK) { goto key_derivation_cleanup; } - ret = lt_hkdf(protocol_name, sizeof(protocol_name), shared_secret, sizeof(shared_secret), 1, output_1, output_2); + ret = lt_hkdf(protocol_name, sizeof(protocol_name), shared_secret, sizeof(shared_secret), 1, + output_1, output_2); if (ret != LT_OK) { goto key_derivation_cleanup; } @@ -217,7 +226,8 @@ lt_ret_t lt_in__session_start(lt_handle_t *h, const uint8_t *stpub, const lt_pke if (ret != LT_OK) { goto key_derivation_cleanup; } - ret = lt_hkdf(output_1, sizeof(output_1), shared_secret, sizeof(shared_secret), 1, output_1, output_2); + ret = lt_hkdf(output_1, sizeof(output_1), shared_secret, sizeof(shared_secret), 1, output_1, + output_2); if (ret != LT_OK) { goto key_derivation_cleanup; } @@ -226,7 +236,8 @@ lt_ret_t lt_in__session_start(lt_handle_t *h, const uint8_t *stpub, const lt_pke if (ret != LT_OK) { goto key_derivation_cleanup; } - ret = lt_hkdf(output_1, sizeof(output_1), shared_secret, sizeof(shared_secret), 2, output_1, kauth); + ret = lt_hkdf(output_1, sizeof(output_1), shared_secret, sizeof(shared_secret), 2, output_1, + kauth); if (ret != LT_OK) { goto key_derivation_cleanup; } @@ -241,8 +252,8 @@ lt_ret_t lt_in__session_start(lt_handle_t *h, const uint8_t *stpub, const lt_pke goto aesgcm_error; } - ret = lt_aesgcm_decrypt(h->l3.crypto_ctx, h->l3.decryption_IV, sizeof(h->l3.decryption_IV), hash, sizeof(hash), - p_rsp->t_tauth, sizeof(p_rsp->t_tauth), (uint8_t *)"", 0); + ret = lt_aesgcm_decrypt(h->l3.crypto_ctx, h->l3.decryption_IV, sizeof(h->l3.decryption_IV), hash, + sizeof(hash), p_rsp->t_tauth, sizeof(p_rsp->t_tauth), (uint8_t *)"", 0); if (ret != LT_OK) { goto aesgcm_error; } @@ -343,7 +354,8 @@ lt_ret_t lt_out__pairing_key_write(lt_handle_t *h, const uint8_t *pairing_pub, c } // Pointer to access l3 buffer when it contains command data - struct lt_l3_pairing_key_write_cmd_t *p_l3_cmd = (struct lt_l3_pairing_key_write_cmd_t *)h->l3.buff; + struct lt_l3_pairing_key_write_cmd_t *p_l3_cmd = (struct lt_l3_pairing_key_write_cmd_t *) + h->l3.buff; // Fill l3 buffer p_l3_cmd->cmd_size = TR01_L3_PAIRING_KEY_WRITE_CMD_SIZE; @@ -369,7 +381,8 @@ lt_ret_t lt_in__pairing_key_write(lt_handle_t *h) } // Pointer to access l3 buffer with result's data. - struct lt_l3_pairing_key_write_res_t *p_l3_res = (struct lt_l3_pairing_key_write_res_t *)h->l3.buff; + struct lt_l3_pairing_key_write_res_t *p_l3_res = (struct lt_l3_pairing_key_write_res_t *) + h->l3.buff; // The result status is OK, we can check for precise size. if (p_l3_res->res_size != TR01_L3_PAIRING_KEY_WRITE_RES_SIZE) { @@ -438,7 +451,8 @@ lt_ret_t lt_out__pairing_key_invalidate(lt_handle_t *h, const uint8_t slot) } // Pointer to access l3 buffer when it contains command data - struct lt_l3_pairing_key_invalidate_cmd_t *p_l3_cmd = (struct lt_l3_pairing_key_invalidate_cmd_t *)h->l3.buff; + struct lt_l3_pairing_key_invalidate_cmd_t *p_l3_cmd = (struct lt_l3_pairing_key_invalidate_cmd_t *) + h->l3.buff; // Fill l3 buffer p_l3_cmd->cmd_size = TR01_L3_PAIRING_KEY_INVALIDATE_CMD_SIZE; @@ -464,7 +478,8 @@ lt_ret_t lt_in__pairing_key_invalidate(lt_handle_t *h) } // Pointer to access L3 buffer with result's data. - struct lt_l3_pairing_key_invalidate_res_t *p_l3_res = (struct lt_l3_pairing_key_invalidate_res_t *)h->l3.buff; + struct lt_l3_pairing_key_invalidate_res_t *p_l3_res = (struct lt_l3_pairing_key_invalidate_res_t *) + h->l3.buff; // The result status is OK, we can check for precise size. if (p_l3_res->res_size != TR01_L3_PAIRING_KEY_INVALIDATE_RES_SIZE) { @@ -512,7 +527,8 @@ static bool conf_addr_valid(enum lt_config_obj_addr_t addr) return valid; } -lt_ret_t lt_out__r_config_write(lt_handle_t *h, const enum lt_config_obj_addr_t addr, const uint32_t obj) +lt_ret_t lt_out__r_config_write(lt_handle_t *h, const enum lt_config_obj_addr_t addr, + const uint32_t obj) { if (!h || !conf_addr_valid(addr)) { return LT_PARAM_ERR; @@ -652,7 +668,8 @@ lt_ret_t lt_in__r_config_erase(lt_handle_t *h) return LT_OK; } -lt_ret_t lt_out__i_config_write(lt_handle_t *h, const enum lt_config_obj_addr_t addr, const uint8_t bit_index) +lt_ret_t lt_out__i_config_write(lt_handle_t *h, const enum lt_config_obj_addr_t addr, + const uint8_t bit_index) { if (!h || !conf_addr_valid(addr) || (bit_index > 31)) { return LT_PARAM_ERR; @@ -750,8 +767,9 @@ lt_ret_t lt_in__i_config_read(lt_handle_t *h, uint32_t *obj) lt_ret_t lt_out__r_mem_data_write(lt_handle_t *h, const uint16_t udata_slot, const uint8_t *data, const uint16_t data_size) { - if (!h || !data || data_size < TR01_R_MEM_DATA_SIZE_MIN || data_size > h->tr01_attrs.r_mem_udata_slot_size_max - || (udata_slot > TR01_R_MEM_DATA_SLOT_MAX)) { + if (!h || !data || data_size < TR01_R_MEM_DATA_SIZE_MIN || + data_size > h->tr01_attrs.r_mem_udata_slot_size_max || + (udata_slot > TR01_R_MEM_DATA_SLOT_MAX)) { return LT_PARAM_ERR; } if (h->l3.session_status != LT_SECURE_SESSION_ON) { @@ -816,7 +834,8 @@ lt_ret_t lt_out__r_mem_data_read(lt_handle_t *h, const uint16_t udata_slot) return lt_l3_encrypt_request(&h->l3); } -lt_ret_t lt_in__r_mem_data_read(lt_handle_t *h, uint8_t *data, const uint16_t data_max_size, uint16_t *data_read_size) +lt_ret_t lt_in__r_mem_data_read(lt_handle_t *h, uint8_t *data, const uint16_t data_max_size, + uint16_t *data_read_size) { if (!h || !data || !data_read_size) { return LT_PARAM_ERR; @@ -833,8 +852,8 @@ lt_ret_t lt_in__r_mem_data_read(lt_handle_t *h, uint8_t *data, const uint16_t da // Pointer to access L3 buffer with result's data. struct lt_l3_r_mem_data_read_res_t *p_l3_res = (struct lt_l3_r_mem_data_read_res_t *)h->l3.buff; - if (p_l3_res->res_size - > TR01_L3_RESULT_SIZE + h->tr01_attrs.r_mem_udata_slot_size_max + TR01_L3_R_MEM_DATA_READ_PADDING_SIZE) { + if (p_l3_res->res_size > TR01_L3_RESULT_SIZE + h->tr01_attrs.r_mem_udata_slot_size_max + + TR01_L3_R_MEM_DATA_READ_PADDING_SIZE) { lt_l3_invalidate_host_session_data(&h->l3); return LT_L3_RES_SIZE_ERROR; } @@ -950,15 +969,18 @@ lt_ret_t lt_in__random_value_get(lt_handle_t *h, uint8_t *rnd_bytes, const uint1 } // Here we copy only random bytes, excluding padding and result status, hence using len from the - // parameter. Note: p_l3_res->res_size could be used as well if we subtract TR01_L3_RANDOM_VALUE_GET_RES_SIZE_MIN. + // parameter. Note: p_l3_res->res_size could be used as well if we subtract + // TR01_L3_RANDOM_VALUE_GET_RES_SIZE_MIN. memcpy(rnd_bytes, p_l3_res->random_data, rnd_bytes_cnt); return LT_OK; } -lt_ret_t lt_out__ecc_key_generate(lt_handle_t *h, const lt_ecc_slot_t slot, const lt_ecc_curve_type_t curve) +lt_ret_t lt_out__ecc_key_generate(lt_handle_t *h, const lt_ecc_slot_t slot, + const lt_ecc_curve_type_t curve) { - if (!h || (slot > TR01_ECC_SLOT_31) || ((curve != TR01_CURVE_P256) && (curve != TR01_CURVE_ED25519))) { + if (!h || (slot > TR01_ECC_SLOT_31) || + ((curve != TR01_CURVE_P256) && (curve != TR01_CURVE_ED25519))) { return LT_PARAM_ERR; } if (h->l3.session_status != LT_SECURE_SESSION_ON) { @@ -1003,10 +1025,11 @@ lt_ret_t lt_in__ecc_key_generate(lt_handle_t *h) return LT_OK; } -lt_ret_t lt_out__ecc_key_store(lt_handle_t *h, const lt_ecc_slot_t slot, const lt_ecc_curve_type_t curve, - const uint8_t *key) +lt_ret_t lt_out__ecc_key_store(lt_handle_t *h, const lt_ecc_slot_t slot, + const lt_ecc_curve_type_t curve, const uint8_t *key) { - if (!h || (slot > TR01_ECC_SLOT_31) || ((curve != TR01_CURVE_P256) && (curve != TR01_CURVE_ED25519)) || !key) { + if (!h || (slot > TR01_ECC_SLOT_31) || + ((curve != TR01_CURVE_P256) && (curve != TR01_CURVE_ED25519)) || !key) { return LT_PARAM_ERR; } if (h->l3.session_status != LT_SECURE_SESSION_ON) { @@ -1072,8 +1095,8 @@ lt_ret_t lt_out__ecc_key_read(lt_handle_t *h, const lt_ecc_slot_t slot) return lt_l3_encrypt_request(&h->l3); } -lt_ret_t lt_in__ecc_key_read(lt_handle_t *h, uint8_t *key, const uint8_t key_max_size, lt_ecc_curve_type_t *curve, - lt_ecc_key_origin_t *origin) +lt_ret_t lt_in__ecc_key_read(lt_handle_t *h, uint8_t *key, const uint8_t key_max_size, + lt_ecc_curve_type_t *curve, lt_ecc_key_origin_t *origin) { if (!h || !key || !curve || !origin) { return LT_PARAM_ERR; @@ -1090,8 +1113,9 @@ lt_ret_t lt_in__ecc_key_read(lt_handle_t *h, uint8_t *key, const uint8_t key_max // Pointer to access L3 buffer with result's data. struct lt_l3_ecc_key_read_res_t *p_l3_res = (struct lt_l3_ecc_key_read_res_t *)h->l3.buff; - size_t pubkey_size_in_result = p_l3_res->res_size - sizeof(p_l3_res->result) - sizeof(p_l3_res->curve) - - sizeof(p_l3_res->origin) - sizeof(p_l3_res->padding); + size_t pubkey_size_in_result = p_l3_res->res_size - sizeof(p_l3_res->result) - + sizeof(p_l3_res->curve) - sizeof(p_l3_res->origin) - + sizeof(p_l3_res->padding); if (p_l3_res->curve == (uint8_t)TR01_CURVE_ED25519) { // Check whether RES_SIZE was set correctly. @@ -1178,7 +1202,8 @@ lt_ret_t lt_in__ecc_key_erase(lt_handle_t *h) return LT_OK; } -lt_ret_t lt_out__ecc_ecdsa_sign(lt_handle_t *h, const lt_ecc_slot_t slot, const uint8_t *msg, const uint32_t msg_len) +lt_ret_t lt_out__ecc_ecdsa_sign(lt_handle_t *h, const lt_ecc_slot_t slot, const uint8_t *msg, + const uint32_t msg_len) { if (!h || (slot > TR01_ECC_SLOT_31) || !msg) { return LT_PARAM_ERR; @@ -1261,7 +1286,8 @@ lt_ret_t lt_in__ecc_ecdsa_sign(lt_handle_t *h, uint8_t *rs) lt_ret_t lt_out__ecc_eddsa_sign(lt_handle_t *h, const lt_ecc_slot_t ecc_slot, const uint8_t *msg, const uint16_t msg_len) { - if (!h || !msg || (msg_len > TR01_L3_EDDSA_SIGN_CMD_MSG_LEN_MAX) || (ecc_slot > TR01_ECC_SLOT_31)) { + if (!h || !msg || (msg_len > TR01_L3_EDDSA_SIGN_CMD_MSG_LEN_MAX) || + (ecc_slot > TR01_ECC_SLOT_31)) { return LT_PARAM_ERR; } if (h->l3.session_status != LT_SECURE_SESSION_ON) { @@ -1451,7 +1477,8 @@ lt_ret_t lt_in__mcounter_get(lt_handle_t *h, uint32_t *mcounter_value) return LT_OK; } -lt_ret_t lt_out__mac_and_destroy(lt_handle_t *h, lt_mac_and_destroy_slot_t slot, const uint8_t *data_out) +lt_ret_t lt_out__mac_and_destroy(lt_handle_t *h, lt_mac_and_destroy_slot_t slot, + const uint8_t *data_out) { if (!h || !data_out || slot > TR01_MAC_AND_DESTROY_SLOT_127) { return LT_PARAM_ERR; diff --git a/src/lt_secure_memzero.c b/src/libtropic_secure_memzero.c similarity index 94% rename from src/lt_secure_memzero.c rename to src/libtropic_secure_memzero.c index 31cb93430..b7bbf2823 100644 --- a/src/lt_secure_memzero.c +++ b/src/libtropic_secure_memzero.c @@ -1,12 +1,12 @@ /** - * @file lt_secure_memzero.c + * @file libtropic_secure_memzero.c * @brief Implementation of secure memory zeroing. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * * @license For the license see LICENSE.md in the root directory of this source tree. */ -#include "lt_secure_memzero.h" +#include "libtropic_secure_memzero.h" #include #include diff --git a/src/lt_aesgcm.h b/src/lt_aesgcm.h index 153ec0632..c64c139cd 100644 --- a/src/lt_aesgcm.h +++ b/src/lt_aesgcm.h @@ -52,8 +52,9 @@ lt_ret_t lt_aesgcm_decrypt_init(void *ctx, const uint8_t *key, const uint32_t ke * @return LT_OK if success, otherwise returns other error code. */ lt_ret_t lt_aesgcm_encrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, const uint8_t *add, - const uint32_t add_len, const uint8_t *plaintext, const uint32_t plaintext_len, - uint8_t *ciphertext, const uint32_t ciphertext_len) __attribute__((warn_unused_result)); + const uint32_t add_len, const uint8_t *plaintext, + const uint32_t plaintext_len, uint8_t *ciphertext, + const uint32_t ciphertext_len) __attribute__((warn_unused_result)); /** * @brief Decrypts data and expects initialized context with valid keys. @@ -70,13 +71,14 @@ lt_ret_t lt_aesgcm_encrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, * @return LT_OK if success, otherwise returns other error code. */ lt_ret_t lt_aesgcm_decrypt(void *ctx, const uint8_t *iv, const uint32_t iv_len, const uint8_t *add, - const uint32_t add_len, const uint8_t *ciphertext, const uint32_t ciphertext_len, - uint8_t *plaintext, const uint32_t plaintext_len) __attribute__((warn_unused_result)); + const uint32_t add_len, const uint8_t *ciphertext, + const uint32_t ciphertext_len, uint8_t *plaintext, + const uint32_t plaintext_len) __attribute__((warn_unused_result)); /** * @brief Deinitializes AES-GCM encryption context. - * @warning Implementation can assume that `lt_crypto_ctx_init` was called before, but must not assume that - * `lt_aesgcm_encrypt_init` was called before. + * @warning Implementation can assume that `lt_crypto_ctx_init` was called before, but must not assume + * that `lt_aesgcm_encrypt_init` was called before. * * @param ctx Crypto context structure * @return LT_OK if success, otherwise returns other error code. @@ -85,8 +87,8 @@ lt_ret_t lt_aesgcm_encrypt_deinit(void *ctx) __attribute__((warn_unused_result)) /** * @brief Deinitializes AES-GCM decryption context. - * @warning Implementation can assume that `lt_crypto_ctx_init` was called before, but must not assume that - * `lt_aesgcm_decrypt_init` was called before. + * @warning Implementation can assume that `lt_crypto_ctx_init` was called before, but must not assume + * that `lt_aesgcm_decrypt_init` was called before. * * @param ctx Crypto context structure * @return LT_OK if success, otherwise returns other error code. diff --git a/src/lt_asn1_der.c b/src/lt_asn1_der.c index a1374ce38..fdea66fbf 100644 --- a/src/lt_asn1_der.c +++ b/src/lt_asn1_der.c @@ -57,8 +57,9 @@ struct parse_ctx_t { static lt_ret_t consume_bytes(struct parse_ctx_t *ctx, uint8_t *buf, uint16_t n, bool copy) { if (ctx->past + n > ctx->len) { - LT_ASN1_DER_PARSE_ERR(ctx, "Incomplete byte stream. Past: %" PRIu16 ", n: %" PRIu16 ", len: %" PRIu16, - ctx->past, n, ctx->len); + LT_ASN1_DER_PARSE_ERR( + ctx, "Incomplete byte stream. Past: %" PRIu16 ", n: %" PRIu16 ", len: %" PRIu16, ctx->past, + n, ctx->len); return LT_CERT_STORE_INVALID; } @@ -145,7 +146,9 @@ static lt_ret_t parse_object(struct parse_ctx_t *ctx) LT_ASN1_DER_GET_NEXT_BYTE(ctx, &b); rv = parse_length(ctx, &len); - if (rv != LT_OK) return rv; + if (rv != LT_OK) { + return rv; + } uint16_t start = ctx->past; @@ -160,7 +163,9 @@ static lt_ret_t parse_object(struct parse_ctx_t *ctx) case LT_ASN1DER_SEQUENCE: while (ctx->past < start + len - 1) { rv = parse_object(ctx); - if (rv != LT_OK) return rv; + if (rv != LT_OK) { + return rv; + } } if (start + len != ctx->past) { @@ -190,11 +195,13 @@ static lt_ret_t parse_object(struct parse_ctx_t *ctx) LT_ASN1_DER_GET_BYTES(ctx, buf, len); // We skip this step if the len is shorter than 3, so this is OK. - uint32_t obj_id = (((uint32_t)buf[0]) << 16) | (((uint32_t)buf[1]) << 8) | (((uint32_t)buf[2])); + uint32_t obj_id = (((uint32_t)buf[0]) << 16) | (((uint32_t)buf[1]) << 8) | + (((uint32_t)buf[2])); if (ctx->obj_id == obj_id) { #ifdef ASNDER_LOG_EN - LT_LOG_DEBUG("Found searched object: 0x%" PRIx32 ". Next object will be sampled!", ctx->obj_id); + LT_LOG_DEBUG("Found searched object: 0x%" PRIx32 ". Next object will be sampled!", + ctx->obj_id); #endif ctx->sample_next = true; } @@ -222,10 +229,11 @@ static lt_ret_t parse_object(struct parse_ctx_t *ctx) ctx->cropped = true; #ifdef ASNDER_LOG_EN - LT_LOG_DEBUG("Sample buffer (%d) is smaller than size of the object to be sampled (%" PRIu8 - "). " - "Cropping %" PRIu16 " bytes from %s of the searched object", - ctx->sbuf_len, sample_len, n_crop_bytes, crop_prefix ? "prefix" : "suffix"); + LT_LOG_DEBUG( + "Sample buffer (%d) is smaller than size of the object to be sampled (%" PRIu8 + "). " + "Cropping %" PRIu16 " bytes from %s of the searched object", + ctx->sbuf_len, sample_len, n_crop_bytes, crop_prefix ? "prefix" : "suffix"); #endif if (crop_prefix) { @@ -263,8 +271,8 @@ static lt_ret_t parse_object(struct parse_ctx_t *ctx) * Public API *******************************************************************************/ -lt_ret_t asn1der_find_object(const uint8_t *stream, uint16_t len, int32_t obj_id, uint8_t *buf, int buf_len, - enum lt_asn1der_crop_kind_t crop_kind) +lt_ret_t asn1der_find_object(const uint8_t *stream, uint16_t len, int32_t obj_id, uint8_t *buf, + int buf_len, enum lt_asn1der_crop_kind_t crop_kind) { struct parse_ctx_t ctx = {.head = (uint8_t *)stream, .len = len, @@ -279,10 +287,14 @@ lt_ret_t asn1der_find_object(const uint8_t *stream, uint16_t len, int32_t obj_id while (ctx.past < ctx.len - 1) { lt_ret_t rv = parse_object(&ctx); - if (rv != LT_OK) return rv; + if (rv != LT_OK) { + return rv; + } }; - if (!ctx.found) return LT_CERT_ITEM_NOT_FOUND; + if (!ctx.found) { + return LT_CERT_ITEM_NOT_FOUND; + } return LT_OK; } diff --git a/src/lt_asn1_der.h b/src/lt_asn1_der.h index 250976ba0..9c5a5fb78 100644 --- a/src/lt_asn1_der.h +++ b/src/lt_asn1_der.h @@ -28,7 +28,10 @@ typedef enum lt_asn1der_obj_kind_t { LT_ASN1DER_SEQUENCE = 0x30, } lt_asn1der_obj_kind_t; -typedef enum lt_asn1der_crop_kind_t { LT_ASN1DER_CROP_SUFFIX, LT_ASN1DER_CROP_PREFIX } lt_asn1der_crop_kind_t; +typedef enum lt_asn1der_crop_kind_t { + LT_ASN1DER_CROP_SUFFIX, + LT_ASN1DER_CROP_PREFIX +} lt_asn1der_crop_kind_t; #define LT_OBJ_ID_CURVEX25519 0x2B656E @@ -44,16 +47,17 @@ typedef enum lt_asn1der_crop_kind_t { LT_ASN1DER_CROP_SUFFIX, LT_ASN1DER_CROP_PR * @param buf_len Size of the buffer pointed to by "buf" * @param crop_kind If size of the found object is bigger than "buf" buffer, the only * part of the object is copied to "buf". - * LT_ASN1DER_CROP_SUFFIX - Crop Suffix , copy to "buf" from 0 to "buf_len" - 1 - * LT_ASN1DER_CROP_PREFIX - Crop Prefix, copy to "buf" from N - buf_len to N - 1 - * where N is length of the object being sampled. + * LT_ASN1DER_CROP_SUFFIX - Crop Suffix , copy to "buf" from 0 to "buf_len" - + * 1 LT_ASN1DER_CROP_PREFIX - Crop Prefix, copy to "buf" from N - buf_len to N - 1 where N is length of + * the object being sampled. * @return lt_ret_t LT_OK if sucessfull (and the object was found) * LT_CERT_STORE_INVALID if the stream does not contain valid ASN1 syntax - * LT_CERT_UNSUPPORTED if the ASN1 stream contains features unsupported by this parser - * LT_CERT_ITEM_NOT_FOUND if OBJECT_IDENTIFIER with "obj_id" value was not found! + * LT_CERT_UNSUPPORTED if the ASN1 stream contains features unsupported by this + * parser LT_CERT_ITEM_NOT_FOUND if OBJECT_IDENTIFIER with "obj_id" value was not found! */ -lt_ret_t asn1der_find_object(const uint8_t *stream, uint16_t len, int32_t obj_id, uint8_t *buf, int buf_len, - enum lt_asn1der_crop_kind_t crop_kind) __attribute__((warn_unused_result)); +lt_ret_t asn1der_find_object(const uint8_t *stream, uint16_t len, int32_t obj_id, uint8_t *buf, + int buf_len, enum lt_asn1der_crop_kind_t crop_kind) + __attribute__((warn_unused_result)); #ifdef __cplusplus } diff --git a/src/lt_crc16.c b/src/lt_crc16.c index 6b69e8c81..e8cd07128 100644 --- a/src/lt_crc16.c +++ b/src/lt_crc16.c @@ -29,8 +29,8 @@ static uint16_t crc16_byte(uint8_t data, uint16_t crc) crc ^= current_byte << 8; i = 8; // Iterate over every bit in a byte. do { - if (crc - & 0x8000) { // Highest bit set -> carry -> add generator polynomial of finite field used in CRC calulation. + if (crc & 0x8000) { // Highest bit set -> carry -> add generator polynomial of finite field + // used in CRC calulation. crc <<= 1; crc ^= LT_CRC16_POLYNOMIAL; } diff --git a/src/lt_crc16.h b/src/lt_crc16.h index 5cce01aff..10c1f7c45 100644 --- a/src/lt_crc16.h +++ b/src/lt_crc16.h @@ -27,7 +27,8 @@ uint16_t crc16(const uint8_t *buf, int16_t size) __attribute__((warn_unused_resu /** * @brief Takes pointer to filled l2 buffer and adds checksum * - * @note Current implementation rely on that passed data come from l2 functions which always prepare data correctly + * @note Current implementation rely on that passed data come from l2 functions which always prepare + * data correctly * * @param req */ diff --git a/src/lt_crypto_common.h b/src/lt_crypto_common.h index e08857da8..6741b5ce6 100644 --- a/src/lt_crypto_common.h +++ b/src/lt_crypto_common.h @@ -13,7 +13,8 @@ /** * @brief Initializes the crypto context. - * @warning This function must not allocate anything, just initialize the context structure to defined values. + * @warning This function must not allocate anything, just initialize the context structure to defined + * values. * * @param ctx Context structure * @return LT_OK if success, otherwise returns other error code. diff --git a/src/lt_hkdf.c b/src/lt_hkdf.c index 987082170..99a9b9e5d 100644 --- a/src/lt_hkdf.c +++ b/src/lt_hkdf.c @@ -12,11 +12,11 @@ #include #include "libtropic_common.h" +#include "libtropic_secure_memzero.h" #include "lt_hmac_sha256.h" -#include "lt_secure_memzero.h" -lt_ret_t lt_hkdf(const uint8_t *ck, const uint32_t ck_len, const uint8_t *input, const uint32_t input_len, - const uint8_t nouts, uint8_t *output_1, uint8_t *output_2) +lt_ret_t lt_hkdf(const uint8_t *ck, const uint32_t ck_len, const uint8_t *input, + const uint32_t input_len, const uint8_t nouts, uint8_t *output_1, uint8_t *output_2) { LT_UNUSED(nouts); diff --git a/src/lt_hkdf.h b/src/lt_hkdf.h index 8ff48f4c2..acba80d32 100644 --- a/src/lt_hkdf.h +++ b/src/lt_hkdf.h @@ -29,8 +29,9 @@ extern "C" { * @param output_1 Output data 1 * @param output_2 Output data 2 */ -lt_ret_t lt_hkdf(const uint8_t *ck, const uint32_t ck_len, const uint8_t *input, const uint32_t input_len, - const uint8_t nouts, uint8_t *output_1, uint8_t *output_2) __attribute__((warn_unused_result)); +lt_ret_t lt_hkdf(const uint8_t *ck, const uint32_t ck_len, const uint8_t *input, + const uint32_t input_len, const uint8_t nouts, uint8_t *output_1, uint8_t *output_2) + __attribute__((warn_unused_result)); #ifdef __cplusplus } diff --git a/src/lt_hmac_sha256.h b/src/lt_hmac_sha256.h index 6b6f0c64b..ff9c053ea 100644 --- a/src/lt_hmac_sha256.h +++ b/src/lt_hmac_sha256.h @@ -33,8 +33,8 @@ extern "C" { * @param output Output buffer * @return LT_OK if success, otherwise returns other error code. */ -lt_ret_t lt_hmac_sha256(const uint8_t *key, const uint32_t key_len, const uint8_t *input, const uint32_t input_len, - uint8_t *output) __attribute__((warn_unused_result)); +lt_ret_t lt_hmac_sha256(const uint8_t *key, const uint32_t key_len, const uint8_t *input, + const uint32_t input_len, uint8_t *output) __attribute__((warn_unused_result)); #ifdef __cplusplus } diff --git a/src/lt_l1.c b/src/lt_l1.c index 2bf2cb017..13399d34d 100644 --- a/src/lt_l1.c +++ b/src/lt_l1.c @@ -19,22 +19,24 @@ #include "lt_port_wrap.h" #ifdef LT_PRINT_SPI_DATA -#include "stdio.h" -#define LT_L1_SPI_DIR_MISO 0 -#define LT_L1_SPI_DIR_MOSI 1 -static void print_hex_chunks(const uint8_t *data, uint8_t len, uint8_t dir) +#include "libtropic_port.h" +enum lt_spi_dir_t { LT_L1_SPI_DIR_MISO, LT_L1_SPI_DIR_MOSI }; +static void print_spi_data_hex(const uint8_t *data, const size_t len, const enum lt_spi_dir_t dir) { if ((!data) || (len == 0)) { + LT_LOG_ERROR("Can't print SPI data, invalid argument(s)!"); return; } - printf("%s", dir ? " >> TX: " : " << RX: "); + + lt_port_log("SPI %s", dir == LT_L1_SPI_DIR_MOSI ? ">> TX " : "<< RX "); for (size_t i = 0; i < len; i++) { - printf("%02" PRIX8 " ", data[i]); + lt_port_log("%02" PRIX8 " ", data[i]); if ((i + 1) % 32 == 0) { - printf("\n "); + lt_port_log("\n "); } } - printf("\n"); + + lt_port_log("\n"); } #endif @@ -88,13 +90,15 @@ lt_ret_t lt_l1_read(lt_l2_state_t *s2, const uint32_t max_len, const uint32_t ti return LT_L1_CHIP_ALARM_MODE; } - // Proceed further in case CHIP_STATUS contains READY bit, signalizing that chip is ready to receive request + // Proceed further in case CHIP_STATUS contains READY bit, signalizing that chip is ready to + // receive request if (s2->buff[0] & TR01_L1_CHIP_MODE_READY_bit) { // receive STATUS byte and length byte ret = lt_l1_spi_transfer(s2, 1, 2, timeout_ms); if (ret != LT_OK) { // offset 1 lt_ret_t ret_unused = lt_l1_spi_csn_high(s2); - LT_UNUSED(ret_unused); // We don't care about it, we return ret from SPI transfer anyway. + LT_UNUSED( + ret_unused); // We don't care about it, we return ret from SPI transfer anyway. return ret; } @@ -115,14 +119,16 @@ lt_ret_t lt_l1_read(lt_l2_state_t *s2, const uint32_t max_len, const uint32_t ti uint16_t length = s2->buff[2] + 2; if (length > (TR01_L1_LEN_MAX - 2)) { lt_ret_t ret_unused = lt_l1_spi_csn_high(s2); - LT_UNUSED(ret_unused); // We don't care about it, we return LT_L1_DATA_LEN_ERROR anyway. + LT_UNUSED( + ret_unused); // We don't care about it, we return LT_L1_DATA_LEN_ERROR anyway. return LT_L1_DATA_LEN_ERROR; } // Receive the rest of incomming bytes, including crc ret = lt_l1_spi_transfer(s2, 3, length, timeout_ms); if (ret != LT_OK) { // offset 3 lt_ret_t ret_unused = lt_l1_spi_csn_high(s2); - LT_UNUSED(ret_unused); // We don't care about it, we return ret from SPI transfer anyway. + LT_UNUSED( + ret_unused); // We don't care about it, we return ret from SPI transfer anyway. return ret; } ret = lt_l1_spi_csn_high(s2); @@ -130,7 +136,7 @@ lt_ret_t lt_l1_read(lt_l2_state_t *s2, const uint32_t max_len, const uint32_t ti return ret; } #ifdef LT_PRINT_SPI_DATA - print_hex_chunks(s2->buff, s2->buff[2] + 5, LT_L1_SPI_DIR_MISO); + print_spi_data_hex(s2->buff, s2->buff[2] + 5, LT_L1_SPI_DIR_MISO); #endif return LT_OK; @@ -152,7 +158,8 @@ lt_ret_t lt_l1_read(lt_l2_state_t *s2, const uint32_t max_len, const uint32_t ti } else { #if LT_USE_INT_PIN - // Wait for rising edge on the INT pin, which signalizes that L2 Response frame is ready to be received + // Wait for rising edge on the INT pin, which signalizes that L2 Response frame is + // ready to be received ret = lt_l1_delay_on_int(s2, LT_L1_TIMEOUT_MS_MAX); if (ret != LT_OK) { return ret; @@ -192,7 +199,7 @@ lt_ret_t lt_l1_write(lt_l2_state_t *s2, const uint16_t len, const uint32_t timeo return ret; } #ifdef LT_PRINT_SPI_DATA - print_hex_chunks(s2->buff, len, LT_L1_SPI_DIR_MOSI); + print_spi_data_hex(s2->buff, len, LT_L1_SPI_DIR_MOSI); #endif ret = lt_l1_spi_transfer(s2, 0, len, timeout_ms); if (ret != LT_OK) { @@ -244,7 +251,8 @@ lt_ret_t lt_l1_retrieve_alarm_log(lt_l2_state_t *s2, const uint32_t timeout_ms) LT_LOG_DEBUG("LOG SIZE: %" PRIu8, log_size); LT_LOG_DEBUG("------------ DECODED CPU Log BEGIN ------------"); - for (size_t i = 0; i < log_size; i++) { // log_size is guaranteed to be <= TR01_L2_CHUNK_MAX_DATA_SIZE + for (size_t i = 0; i < log_size; + i++) { // log_size is guaranteed to be <= TR01_L2_CHUNK_MAX_DATA_SIZE lt_port_log("%c", s2->buff[i + TR01_L2_RSP_DATA_RSP_CRC_OFFSET]); } lt_port_log("\n"); diff --git a/src/lt_l1.h b/src/lt_l1.h index 6ebe9bdc3..f3d6009cf 100644 --- a/src/lt_l1.h +++ b/src/lt_l1.h @@ -78,7 +78,8 @@ lt_ret_t lt_l1_write(lt_l2_state_t *s2, const uint16_t len, const uint32_t timeo * * @return LT_OK if success, otherwise returns other error code. */ -lt_ret_t lt_l1_retrieve_alarm_log(lt_l2_state_t *s2, const uint32_t timeout_ms) __attribute__((warn_unused_result)); +lt_ret_t lt_l1_retrieve_alarm_log(lt_l2_state_t *s2, const uint32_t timeout_ms) + __attribute__((warn_unused_result)); /** @} */ // end of group_l1_functions diff --git a/src/lt_l2_api_structs.h b/src/lt_l2_api_structs.h index a2b60c722..bf89bbff6 100644 --- a/src/lt_l2_api_structs.h +++ b/src/lt_l2_api_structs.h @@ -23,8 +23,10 @@ extern "C" { #define TR01_L2_GET_INFO_REQ_ID 0x01 /** @brief Request length */ #define TR01_L2_GET_INFO_REQ_LEN 2u -//------- Certificate -------------------------------------------------------------------------------------// -/** @brief The X.509 chip certificate read from I-Memory and signed by Tropic Square (max length of 512B). */ +//------- Certificate +//-------------------------------------------------------------------------------------// +/** @brief The X.509 chip certificate read from I-Memory and signed by Tropic Square (max length of + * 512B). */ #define TR01_L2_GET_INFO_REQ_OBJECT_ID_X509_CERTIFICATE 0x00 /** @brief Request for data bytes 0-127 of the object. */ #define TR01_L2_GET_INFO_REQ_BLOCK_INDEX_DATA_CHUNK_0_127 0x00 @@ -40,8 +42,10 @@ extern "C" { #define TR01_L2_GET_INFO_REQ_OBJECT_ID_RISCV_FW_VERSION 0x02 /** @brief The SPECT FW version (4 Bytes) */ #define TR01_L2_GET_INFO_REQ_OBJECT_ID_SPECT_FW_VERSION 0x04 -//------- FW Bank -----------------------------------------------------------------------------------------// -/** @brief The FW header read from the selected bank id (shown as an index). Supported only in Start-up mode. */ +//------- FW Bank +//-----------------------------------------------------------------------------------------// +/** @brief The FW header read from the selected bank id (shown as an index). Supported only in Start-up + * mode. */ #define TR01_L2_GET_INFO_REQ_OBJECT_ID_FW_BANK 0xb0 /** @brief Response length */ @@ -49,11 +53,12 @@ extern "C" { /** * @brief - * Request to obtain information about TROPIC01. The type of information obtained is distinguished by OBJECT_ID. + * Request to obtain information about TROPIC01. The type of information obtained is distinguished by + * OBJECT_ID. * - * NOTE: If Start-up mode is active, TROPIC01 executes the immutable FW. Any version identification then has the highest - * bit set to 1. SPECT_FW_VERSION then returns a dummy value of 0x80000000 because the SPECT FW is part of the immutable - * FW. + * NOTE: If Start-up mode is active, TROPIC01 executes the immutable FW. Any version identification + * then has the highest bit set to 1. SPECT_FW_VERSION then returns a dummy value of 0x80000000 because + * the SPECT FW is part of the immutable FW. */ struct lt_l2_get_info_req_t { uint8_t req_id; /**< Request ID byte */ @@ -88,11 +93,12 @@ LT_STATIC_ASSERT( /** * @brief - * Request to obtain information about TROPIC01. The type of information obtained is distinguished by OBJECT_ID. + * Request to obtain information about TROPIC01. The type of information obtained is distinguished by + * OBJECT_ID. * - * NOTE: If Start-up mode is active, TROPIC01 executes the immutable FW. Any version identification then has the highest - * bit set to 1. SPECT_FW_VERSION then returns a dummy value of 0x80000000 because the SPECT FW is part of the immutable - * FW. + * NOTE: If Start-up mode is active, TROPIC01 executes the immutable FW. Any version identification + * then has the highest bit set to 1. SPECT_FW_VERSION then returns a dummy value of 0x80000000 because + * the SPECT FW is part of the immutable FW. */ struct lt_l2_get_info_rsp_t { uint8_t chip_status; /**< CHIP_STATUS byte */ @@ -130,22 +136,22 @@ LT_STATIC_ASSERT( /** * @brief - * Request to execute a Secure Channel Handshake and establish a new Secure Channel Session (TROPIC01 moves to Secure - * Channel Mode). + * Request to execute a Secure Channel Handshake and establish a new Secure Channel Session (TROPIC01 + * moves to Secure Channel Mode). */ struct lt_l2_handshake_req_t { uint8_t req_id; /**< Request ID byte */ uint8_t req_len; /**< Length byte */ /** * @brief - * The Host MCU's Ephemeral X25519 public key. A little endian encoding of the x-coordinate from the public - * Curve25519 point. + * The Host MCU's Ephemeral X25519 public key. A little endian encoding of the x-coordinate from + * the public Curve25519 point. */ uint8_t e_hpub[32]; /**< Ephemeral Key of Host MCU. */ /** * @brief - * The index of the Pairing Key slot to establish a Secure Channel Session with (TROPIC01 fetches $S_{HiPub}$ from - * the Pairing Key slot specified in this field). + * The index of the Pairing Key slot to establish a Secure Channel Session with (TROPIC01 fetches + * $S_{HiPub}$ from the Pairing Key slot specified in this field). */ uint8_t pkey_index; /**< Pairing Key slot */ uint8_t crc[2]; /**< Checksum */ @@ -168,8 +174,8 @@ LT_STATIC_ASSERT( /** * @brief - * Request to execute a Secure Channel Handshake and establish a new Secure Channel Session (TROPIC01 moves to Secure - * Channel Mode). + * Request to execute a Secure Channel Handshake and establish a new Secure Channel Session (TROPIC01 + * moves to Secure Channel Mode). */ struct lt_l2_handshake_rsp_t { uint8_t chip_status; /**< CHIP_STATUS byte */ @@ -223,7 +229,7 @@ struct lt_l2_encrypted_cmd_req_t { uint8_t req_id; /**< Request ID byte */ uint8_t req_len; /**< Length byte */ /** Contains a chunk of encrypted command */ - uint8_t l3_chunk[255]; + uint8_t l3_chunk[TR01_L2_CHUNK_MAX_DATA_SIZE]; uint8_t crc[2]; /**< Checksum */ } __attribute__((packed)); @@ -254,7 +260,7 @@ struct lt_l2_encrypted_cmd_rsp_t { * The size of the RES_CIPHERTEXT L3 Field in bytes. */ /** Contains a chunk of encrypted command */ - uint8_t l3_chunk[255]; + uint8_t l3_chunk[TR01_L2_CHUNK_MAX_DATA_SIZE]; uint8_t crc[2]; /**< Checksum */ } __attribute__((packed)); @@ -283,7 +289,8 @@ LT_STATIC_ASSERT( /** * @brief - * Request to abort current Secure Channel Session and execution of L3 command (TROPIC01 moves to Idle Mode). + * Request to abort current Secure Channel Session and execution of L3 command (TROPIC01 moves to Idle + * Mode). */ struct lt_l2_encrypted_session_abt_req_t { uint8_t req_id; /**< Request ID byte */ @@ -306,7 +313,8 @@ LT_STATIC_ASSERT( /** * @brief - * Request to abort current Secure Channel Session and execution of L3 command (TROPIC01 moves to Idle Mode). + * Request to abort current Secure Channel Session and execution of L3 command (TROPIC01 moves to Idle + * Mode). */ struct lt_l2_encrypted_session_abt_rsp_t { uint8_t chip_status; /**< CHIP_STATUS byte */ @@ -610,12 +618,12 @@ LT_STATIC_ASSERT( * NOTE: Chip automatically selects memory space for FW storage and erases it. */ struct lt_l2_mutable_fw_update_req_t { - uint8_t req_id; /**< Request ID byte */ - uint8_t req_len; /**< Length byte */ - uint8_t signature[64]; /**< Signature of SHA256 hash of all following data in this packet */ - uint8_t hash[32]; /**< SHA256 HASH of first FW chunk of data sent using Mutable_FW_Update_Data */ - uint16_t type; /**< FW type which is going to be updated */ - uint8_t padding; /**< Padding, zero value */ + uint8_t req_id; /**< Request ID byte */ + uint8_t req_len; /**< Length byte */ + uint8_t signature[64]; /**< Signature of SHA256 hash of all following data in this packet */ + uint8_t hash[32]; /**< SHA256 HASH of first FW chunk of data sent using Mutable_FW_Update_Data */ + uint16_t type; /**< FW type which is going to be updated */ + uint8_t padding; /**< Padding, zero value */ uint8_t header_version; /**< Version of used header */ uint32_t version; /**< Version of FW */ uint8_t crc[2]; /**< Checksum */ @@ -672,10 +680,11 @@ LT_STATIC_ASSERT( * Supported only in Start-up mode after Mutable_FW_Update_Req successfully processed. */ struct lt_l2_mutable_fw_update_data_req_t { - uint8_t req_id; /**< Request ID byte */ - uint8_t req_len; /**< Length byte */ - uint8_t hash[32]; /**< SHA256 HASH of the next FW chunk of data sent using Mutable_FW_Update_Data */ - uint16_t offset; /**< The offset of the specific bank to write the FW chunk data to */ + uint8_t req_id; /**< Request ID byte */ + uint8_t req_len; /**< Length byte */ + uint8_t + hash[32]; /**< SHA256 HASH of the next FW chunk of data sent using Mutable_FW_Update_Data */ + uint16_t offset; /**< The offset of the specific bank to write the FW chunk data to */ uint8_t data[220]; /**< The binary data to write. Data size should be a multiple of 4 */ uint8_t crc[2]; /**< Checksum */ } __attribute__((__packed__)); diff --git a/src/lt_l3_api_structs.h b/src/lt_l3_api_structs.h index 2cce270e3..c82f4398f 100644 --- a/src/lt_l3_api_structs.h +++ b/src/lt_l3_api_structs.h @@ -35,7 +35,8 @@ extern "C" { /** @brief Result max length (fields: RESULT + RES_DATA) */ #define TR01_L3_PING_RES_SIZE_MAX 4097u /** @brief Max packet length (incl. RES_SIZE and TAG) */ -#define TR01_L3_PING_RES_PACKET_SIZE_MAX TR01_L3_SIZE_SIZE + TR01_L3_PING_RES_SIZE_MAX + TR01_L3_TAG_SIZE +#define TR01_L3_PING_RES_PACKET_SIZE_MAX \ + TR01_L3_SIZE_SIZE + TR01_L3_PING_RES_SIZE_MAX + TR01_L3_TAG_SIZE /** * @brief @@ -300,7 +301,8 @@ LT_STATIC_ASSERT( /** @brief Result length (fields: RESULT + zero RES_DATA) */ #define TR01_L3_R_CONFIG_WRITE_RES_SIZE 1u /** @brief Packet length (incl. RES_SIZE and TAG) */ -#define TR01_L3_R_CONFIG_WRITE_RES_PACKET_SIZE TR01_L3_SIZE_SIZE + TR01_L3_R_CONFIG_WRITE_RES_SIZE + TR01_L3_TAG_SIZE +#define TR01_L3_R_CONFIG_WRITE_RES_PACKET_SIZE \ + TR01_L3_SIZE_SIZE + TR01_L3_R_CONFIG_WRITE_RES_SIZE + TR01_L3_TAG_SIZE /** * @brief @@ -370,7 +372,8 @@ LT_STATIC_ASSERT( /** @brief Result length (fields: RESULT + RES_DATA) */ #define TR01_L3_R_CONFIG_READ_RES_SIZE 8u /** @brief Packet length (incl. RES_SIZE and TAG) */ -#define TR01_L3_R_CONFIG_READ_RES_PACKET_SIZE TR01_L3_SIZE_SIZE + TR01_L3_R_CONFIG_READ_RES_SIZE + TR01_L3_TAG_SIZE +#define TR01_L3_R_CONFIG_READ_RES_PACKET_SIZE \ + TR01_L3_SIZE_SIZE + TR01_L3_R_CONFIG_READ_RES_SIZE + TR01_L3_TAG_SIZE /** * @brief @@ -440,7 +443,8 @@ LT_STATIC_ASSERT( /** @brief Result length (fields: RESULT + zero RES_DATA) */ #define TR01_L3_R_CONFIG_ERASE_RES_SIZE 1u /** @brief Packet length (incl. RES_SIZE and TAG) */ -#define TR01_L3_R_CONFIG_ERASE_RES_PACKET_SIZE TR01_L3_SIZE_SIZE + TR01_L3_R_CONFIG_ERASE_RES_SIZE + TR01_L3_TAG_SIZE +#define TR01_L3_R_CONFIG_ERASE_RES_PACKET_SIZE \ + TR01_L3_SIZE_SIZE + TR01_L3_R_CONFIG_ERASE_RES_SIZE + TR01_L3_TAG_SIZE /** * @brief @@ -492,7 +496,8 @@ LT_STATIC_ASSERT( /** @brief Result length (fields: RESULT + zero RES_DATA) */ #define TR01_L3_I_CONFIG_WRITE_RES_SIZE 1u /** @brief Packet length (incl. RES_SIZE and TAG) */ -#define TR01_L3_I_CONFIG_WRITE_RES_PACKET_SIZE TR01_L3_SIZE_SIZE + TR01_L3_I_CONFIG_WRITE_RES_SIZE + TR01_L3_TAG_SIZE +#define TR01_L3_I_CONFIG_WRITE_RES_PACKET_SIZE \ + TR01_L3_SIZE_SIZE + TR01_L3_I_CONFIG_WRITE_RES_SIZE + TR01_L3_TAG_SIZE /** * @brief @@ -556,7 +561,8 @@ LT_STATIC_ASSERT( /** @brief Result length (fields: RESULT + RES_DATA) */ #define TR01_L3_I_CONFIG_READ_RES_SIZE 8u /** @brief Packet length (incl. RES_SIZE and TAG) */ -#define TR01_L3_I_CONFIG_READ_RES_PACKET_SIZE TR01_L3_SIZE_SIZE + TR01_L3_I_CONFIG_READ_RES_SIZE + TR01_L3_TAG_SIZE +#define TR01_L3_I_CONFIG_READ_RES_PACKET_SIZE \ + TR01_L3_SIZE_SIZE + TR01_L3_I_CONFIG_READ_RES_SIZE + TR01_L3_TAG_SIZE /** * @brief @@ -1141,7 +1147,8 @@ LT_STATIC_ASSERT( /** @brief Result length (fields: RESULT + zero RES_DATA) */ #define TR01_L3_ECC_KEY_ERASE_RES_SIZE 1u /** @brief Packet length (incl. RES_SIZE and TAG) */ -#define TR01_L3_ECC_KEY_ERASE_RES_PACKET_SIZE TR01_L3_SIZE_SIZE + TR01_L3_ECC_KEY_ERASE_RES_SIZE + TR01_L3_TAG_SIZE +#define TR01_L3_ECC_KEY_ERASE_RES_PACKET_SIZE \ + TR01_L3_SIZE_SIZE + TR01_L3_ECC_KEY_ERASE_RES_SIZE + TR01_L3_TAG_SIZE /** * @brief @@ -1199,7 +1206,8 @@ LT_STATIC_ASSERT( /** @brief Result length (fields: RESULT + RES_DATA) */ #define TR01_L3_ECDSA_SIGN_RES_SIZE 80u /** @brief Packet length (incl. RES_SIZE and TAG) */ -#define TR01_L3_ECDSA_SIGN_RES_PACKET_SIZE TR01_L3_SIZE_SIZE + TR01_L3_ECDSA_SIGN_RES_SIZE + TR01_L3_TAG_SIZE +#define TR01_L3_ECDSA_SIGN_RES_PACKET_SIZE \ + TR01_L3_SIZE_SIZE + TR01_L3_ECDSA_SIGN_RES_SIZE + TR01_L3_TAG_SIZE /** * @brief @@ -1291,7 +1299,8 @@ LT_STATIC_ASSERT( /** @brief Result length (fields: RESULT + RES_DATA) */ #define TR01_L3_EDDSA_SIGN_RES_SIZE 80u /** @brief Packet length (incl. RES_SIZE and TAG) */ -#define TR01_L3_EDDSA_SIGN_RES_PACKET_SIZE TR01_L3_SIZE_SIZE + TR01_L3_EDDSA_SIGN_RES_SIZE + TR01_L3_TAG_SIZE +#define TR01_L3_EDDSA_SIGN_RES_PACKET_SIZE \ + TR01_L3_SIZE_SIZE + TR01_L3_EDDSA_SIGN_RES_SIZE + TR01_L3_TAG_SIZE /** * @brief @@ -1379,7 +1388,8 @@ LT_STATIC_ASSERT( /** @brief Result length (fields: RESULT + zero RES_DATA) */ #define TR01_L3_MCOUNTER_INIT_RES_SIZE 1u /** @brief Packet length (incl. RES_SIZE and TAG) */ -#define TR01_L3_MCOUNTER_INIT_RES_PACKET_SIZE TR01_L3_SIZE_SIZE + TR01_L3_MCOUNTER_INIT_RES_SIZE + TR01_L3_TAG_SIZE +#define TR01_L3_MCOUNTER_INIT_RES_PACKET_SIZE \ + TR01_L3_SIZE_SIZE + TR01_L3_MCOUNTER_INIT_RES_SIZE + TR01_L3_TAG_SIZE /** * @brief @@ -1449,7 +1459,8 @@ LT_STATIC_ASSERT( /** @brief Result length (fields: RESULT + zero RES_DATA) */ #define TR01_L3_MCOUNTER_UPDATE_RES_SIZE 1u /** @brief Packet length (incl. RES_SIZE and TAG) */ -#define TR01_L3_MCOUNTER_UPDATE_RES_PACKET_SIZE TR01_L3_SIZE_SIZE + TR01_L3_MCOUNTER_UPDATE_RES_SIZE + TR01_L3_TAG_SIZE +#define TR01_L3_MCOUNTER_UPDATE_RES_PACKET_SIZE \ + TR01_L3_SIZE_SIZE + TR01_L3_MCOUNTER_UPDATE_RES_SIZE + TR01_L3_TAG_SIZE /** * @brief @@ -1507,7 +1518,8 @@ LT_STATIC_ASSERT( /** @brief Result length (fields: RESULT + RES_DATA) */ #define TR01_L3_MCOUNTER_GET_RES_SIZE 8u /** @brief Packet length (incl. RES_SIZE and TAG) */ -#define TR01_L3_MCOUNTER_GET_RES_PACKET_SIZE TR01_L3_SIZE_SIZE + TR01_L3_MCOUNTER_GET_RES_SIZE + TR01_L3_TAG_SIZE +#define TR01_L3_MCOUNTER_GET_RES_PACKET_SIZE \ + TR01_L3_SIZE_SIZE + TR01_L3_MCOUNTER_GET_RES_SIZE + TR01_L3_TAG_SIZE /** * @brief @@ -1577,7 +1589,8 @@ LT_STATIC_ASSERT( /** @brief Result length (fields: RESULT + RES_DATA) */ #define TR01_L3_MAC_AND_DESTROY_RES_SIZE 36u /** @brief Packet length (incl. RES_SIZE and TAG) */ -#define TR01_L3_MAC_AND_DESTROY_RES_PACKET_SIZE TR01_L3_SIZE_SIZE + TR01_L3_MAC_AND_DESTROY_RES_SIZE + TR01_L3_TAG_SIZE +#define TR01_L3_MAC_AND_DESTROY_RES_PACKET_SIZE \ + TR01_L3_SIZE_SIZE + TR01_L3_MAC_AND_DESTROY_RES_SIZE + TR01_L3_TAG_SIZE /** * @brief @@ -1588,8 +1601,8 @@ struct lt_l3_mac_and_destroy_cmd_t { uint8_t cmd_id; /**< Command Identifier */ /** * @brief - * The slot (from the MAC-and-Destroy data partition in R-Memory) to execute the MAC_And_Destroy sequence. Valid - * values are 0 - 127. + * The slot (from the MAC-and-Destroy data partition in R-Memory) to execute the MAC_And_Destroy + * sequence. Valid values are 0 - 127. */ uint16_t slot; /**< Mac-and-Destroy slot */ /** diff --git a/src/lt_l3_process.c b/src/lt_l3_process.c index 8125a08b9..44dee49f1 100644 --- a/src/lt_l3_process.c +++ b/src/lt_l3_process.c @@ -16,10 +16,10 @@ #include "libtropic_common.h" #include "libtropic_l2.h" #include "libtropic_logging.h" +#include "libtropic_secure_memzero.h" #include "lt_aesgcm.h" #include "lt_crypto_common.h" #include "lt_l1.h" -#include "lt_secure_memzero.h" static lt_ret_t lt_l3_nonce_increase(uint8_t *nonce) { @@ -75,8 +75,9 @@ lt_ret_t lt_l3_encrypt_request(lt_l3_state_t *s3) // p_frame->data is both input plaintext and output ciphertext buffer, // it is large enough to hold both plaintext and ciphertext + tag. - int ret = lt_aesgcm_encrypt(s3->crypto_ctx, s3->encryption_IV, TR01_L3_IV_SIZE, (uint8_t *)"", 0, p_frame->data, - p_frame->cmd_size, p_frame->data, p_frame->cmd_size + TR01_L3_TAG_SIZE); + int ret = lt_aesgcm_encrypt(s3->crypto_ctx, s3->encryption_IV, TR01_L3_IV_SIZE, (uint8_t *)"", 0, + p_frame->data, p_frame->cmd_size, p_frame->data, + p_frame->cmd_size + TR01_L3_TAG_SIZE); if (ret != LT_OK) { lt_l3_invalidate_host_session_data(s3); return ret; @@ -106,9 +107,9 @@ lt_ret_t lt_l3_decrypt_response(lt_l3_state_t *s3) return LT_L3_BUFFER_TOO_SMALL; } - lt_ret_t ret - = lt_aesgcm_decrypt(s3->crypto_ctx, s3->decryption_IV, TR01_L3_IV_SIZE, (uint8_t *)"", 0, p_frame->data, - p_frame->cmd_size + TR01_L3_TAG_SIZE, p_frame->data, p_frame->cmd_size); + lt_ret_t ret = lt_aesgcm_decrypt(s3->crypto_ctx, s3->decryption_IV, TR01_L3_IV_SIZE, (uint8_t *)"", + 0, p_frame->data, p_frame->cmd_size + TR01_L3_TAG_SIZE, + p_frame->data, p_frame->cmd_size); if (ret != LT_OK) { lt_l3_invalidate_host_session_data(s3); return ret; diff --git a/src/lt_port_wrap.h b/src/lt_port_wrap.h index 38fd259a1..ce292dd5b 100644 --- a/src/lt_port_wrap.h +++ b/src/lt_port_wrap.h @@ -92,8 +92,8 @@ lt_ret_t lt_l1_delay_on_int(lt_l2_state_t *s2, uint32_t ms) __attribute__((warn_ #endif /** - * @brief Generate `count` random bytes using host's random number generator. This is a wrapper for platform defined - * function. + * @brief Generate `count` random bytes using host's random number generator. This is a wrapper for + * platform defined function. * * @param h Handle for communication with TROPIC01 * @param buff Buffer to be filled diff --git a/src/lt_sha256.h b/src/lt_sha256.h index a76119845..41e712d87 100644 --- a/src/lt_sha256.h +++ b/src/lt_sha256.h @@ -45,7 +45,8 @@ lt_ret_t lt_sha256_start(void *ctx) __attribute__((warn_unused_result)); * @param input_len Length of input data * @return LT_OK if success, otherwise returns other error code. */ -lt_ret_t lt_sha256_update(void *ctx, const uint8_t *input, const size_t input_len) __attribute__((warn_unused_result)); +lt_ret_t lt_sha256_update(void *ctx, const uint8_t *input, const size_t input_len) + __attribute__((warn_unused_result)); /** * @brief Finishes SHA-256 operation. @@ -58,8 +59,8 @@ lt_ret_t lt_sha256_finish(void *ctx, uint8_t *output) __attribute__((warn_unused /** * @brief Deinitializes SHA-256 context. Call once after finishing SHA-256 operations. - * @warning This function has to be called even if any other SHA-256 function failed. If `lt_sha256_init` - * failed, calling this function is not necessary. + * @warning This function has to be called even if any other SHA-256 function failed. If + * `lt_sha256_init` failed, calling this function is not necessary. * * @param ctx Hash context * @return LT_OK if success, otherwise returns other error code. diff --git a/src/lt_tr01_attrs.c b/src/lt_tr01_attrs.c index 22665554d..233988129 100644 --- a/src/lt_tr01_attrs.c +++ b/src/lt_tr01_attrs.c @@ -25,42 +25,29 @@ lt_ret_t lt_init_tr01_attrs(lt_handle_t *h) #endif lt_ret_t ret; - lt_tr01_mode_t tr01_mode; uint8_t riscv_fw_ver[TR01_L2_GET_INFO_RISCV_FW_SIZE]; // 1. Set some default dummy values for the attributes h->tr01_attrs.r_mem_udata_slot_size_max = 0; - // 2. Get current TROPIC01's mode - ret = lt_get_tr01_mode(h, &tr01_mode); - if (ret != LT_OK) { - return ret; - } - - // 3. Reboot if TROPIC01 is not executing Application FW. - if (tr01_mode != LT_TR01_APPLICATION) { - ret = lt_reboot(h, TR01_REBOOT); - if (ret != LT_OK) { - return ret; - } - } - - // 4. Read Application FW version + // 2. Read Application FW version ret = lt_get_info_riscv_fw_ver(h, riscv_fw_ver); if (ret != LT_OK) { return ret; } - // 5. Check if the Application FW version is supported by the current version of libtropic + // 3. Check if the Application FW version is supported by the current version of libtropic // TODO: handle FW versions older than 1.0.0 - if (riscv_fw_ver[3] > LT_LATEST_RISCV_FW_VER_MAJOR - || (riscv_fw_ver[3] == LT_LATEST_RISCV_FW_VER_MAJOR && riscv_fw_ver[2] > LT_LATEST_RISCV_FW_VER_MINOR) - || (riscv_fw_ver[3] == LT_LATEST_RISCV_FW_VER_MAJOR && riscv_fw_ver[2] == LT_LATEST_RISCV_FW_VER_MINOR - && riscv_fw_ver[1] > LT_LATEST_RISCV_FW_VER_PATCH)) { + if (riscv_fw_ver[3] > LT_LATEST_RISCV_FW_VER_MAJOR || + (riscv_fw_ver[3] == LT_LATEST_RISCV_FW_VER_MAJOR && + riscv_fw_ver[2] > LT_LATEST_RISCV_FW_VER_MINOR) || + (riscv_fw_ver[3] == LT_LATEST_RISCV_FW_VER_MAJOR && + riscv_fw_ver[2] == LT_LATEST_RISCV_FW_VER_MINOR && + riscv_fw_ver[1] > LT_LATEST_RISCV_FW_VER_PATCH)) { return LT_APP_FW_TOO_NEW; } - // 6. Initialize the TROPIC01 attributes structure + // 4. Initialize the TROPIC01 attributes structure // this is the most crucial part - has to be efficient and logically correct if (riscv_fw_ver[3] < 2) { h->tr01_attrs.r_mem_udata_slot_size_max = 444; diff --git a/src/lt_tr01_attrs.h b/src/lt_tr01_attrs.h index c708da663..d55c4ddda 100644 --- a/src/lt_tr01_attrs.h +++ b/src/lt_tr01_attrs.h @@ -15,10 +15,13 @@ /** * @brief Initializes the lt_tr01_attrs_t structure based on the read Application FW version. + * @warning This function expects that TROPIC01 is executing Application FW, otherwise Get_Info_Req for + * the Application FW version will fail. * * @param h Handle for communication with TROPIC01 * @retval LT_OK Function executed successfully - * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose encoding + * @retval other Function did not execute successully, you might use lt_ret_verbose() to get verbose + * encoding */ lt_ret_t lt_init_tr01_attrs(lt_handle_t *h) __attribute__((warn_unused_result)); diff --git a/src/lt_x25519.h b/src/lt_x25519.h index 907884147..f2c1e0ede 100644 --- a/src/lt_x25519.h +++ b/src/lt_x25519.h @@ -23,7 +23,8 @@ extern "C" { * @param secret Shared secret (32B) * @return LT_OK if success, otherwise returns other error code. */ -lt_ret_t lt_X25519(const uint8_t *privkey, const uint8_t *pubkey, uint8_t *secret) __attribute__((warn_unused_result)); +lt_ret_t lt_X25519(const uint8_t *privkey, const uint8_t *pubkey, uint8_t *secret) + __attribute__((warn_unused_result)); /** * @brief Performs X25519 scalar multiplication with a base point. diff --git a/tests/common/lt_test_common.h b/tests/common/lt_test_common.h index 87db1b159..ce90dda0c 100644 --- a/tests/common/lt_test_common.h +++ b/tests/common/lt_test_common.h @@ -62,7 +62,8 @@ void lt_assert_fail_handler(void); assert(_exp_ == _val_); \ } -// Used to instruct the test runner that the test finshed and may disconnect (useful in embedded ports). +// Used to instruct the test runner that the test finshed and may disconnect (useful in embedded +// ports). #define LT_FINISH_TEST() \ { \ LT_LOG_INFO("TEST FINISHED!"); \ @@ -79,12 +80,12 @@ void hexdump_8byte(const uint8_t *data, uint16_t size); /** * @brief Printf-like wrapper for LT_LOG_INFO used with lt_print_chip_id(). * - * @param format A printf-style format string describing how to format the subsequent arguments. Must be a - * null-terminated string. + * @param format A printf-style format string describing how to format the subsequent arguments. Must + * be a null-terminated string. * @param ... Additional arguments corresponding to the format specifiers in `format`. * - * @return The number of characters printed (excluding the terminating null byte), or a negative value if an - * output error occurs. + * @return The number of characters printed (excluding the terminating null byte), or a negative + * value if an output error occurs. */ int chip_id_printf_wrapper(const char *format, ...); diff --git a/tests/functional/esp32/ESP32-C3-DevKit-RUST-1/main.c b/tests/functional/esp32/ESP32-C3-DevKit-RUST-1/main.c index 91e4b400e..885628b35 100644 --- a/tests/functional/esp32/ESP32-C3-DevKit-RUST-1/main.c +++ b/tests/functional/esp32/ESP32-C3-DevKit-RUST-1/main.c @@ -26,8 +26,9 @@ void app_main(void) { // Declarations - psa_status_t psa_init_status = PSA_ERROR_GENERIC_ERROR; // The value needs to be different than PSA_SUCCESS to - // indicate that psa_crypto_init was not called. + psa_status_t psa_init_status = + PSA_ERROR_GENERIC_ERROR; // The value needs to be different than PSA_SUCCESS to + // indicate that psa_crypto_init was not called. esp_err_t esp_ret = ESP_OK; lt_handle_t *__lt_handle__ = NULL; // __lt_handle__ identifier is used by the test registry. #if LT_SEPARATE_L3_BUFF diff --git a/tests/functional/esp32/ESP32-DevKitC-V4/main.c b/tests/functional/esp32/ESP32-DevKitC-V4/main.c index a731ae1ee..34f6dc248 100644 --- a/tests/functional/esp32/ESP32-DevKitC-V4/main.c +++ b/tests/functional/esp32/ESP32-DevKitC-V4/main.c @@ -26,8 +26,9 @@ void app_main(void) { // Declarations - psa_status_t psa_init_status = PSA_ERROR_GENERIC_ERROR; // The value needs to be different than PSA_SUCCESS to - // indicate that psa_crypto_init was not called. + psa_status_t psa_init_status = + PSA_ERROR_GENERIC_ERROR; // The value needs to be different than PSA_SUCCESS to + // indicate that psa_crypto_init was not called. esp_err_t esp_ret = ESP_OK; lt_handle_t *__lt_handle__ = NULL; // __lt_handle__ identifier is used by the test registry. #if LT_SEPARATE_L3_BUFF diff --git a/tests/functional/esp32/ESP32-S3-DevKitC-1/main.c b/tests/functional/esp32/ESP32-S3-DevKitC-1/main.c index 0b98d2ab4..5ee42ce16 100644 --- a/tests/functional/esp32/ESP32-S3-DevKitC-1/main.c +++ b/tests/functional/esp32/ESP32-S3-DevKitC-1/main.c @@ -26,8 +26,9 @@ void app_main(void) { // Declarations - psa_status_t psa_init_status = PSA_ERROR_GENERIC_ERROR; // The value needs to be different than PSA_SUCCESS to - // indicate that psa_crypto_init was not called. + psa_status_t psa_init_status = + PSA_ERROR_GENERIC_ERROR; // The value needs to be different than PSA_SUCCESS to + // indicate that psa_crypto_init was not called. esp_err_t esp_ret = ESP_OK; lt_handle_t *__lt_handle__ = NULL; // __lt_handle__ identifier is used by the test registry. #if LT_SEPARATE_L3_BUFF diff --git a/tests/functional/esp32/common.cmake b/tests/functional/esp32/common.cmake index 4b105ecb4..1fd6a439b 100644 --- a/tests/functional/esp32/common.cmake +++ b/tests/functional/esp32/common.cmake @@ -84,7 +84,7 @@ set(SOURCES # Enable strict compile flags for main.c and Libtropic HAL sources if(LT_STRICT_COMPILATION) - set_source_files_properties(${CMAKE_CURRENT_SOURCE_DIR}/main.c ${LT_HAL_SRCS} PROPERTIES COMPILE_OPTIONS "${LT_STRICT_COMPILATION_FLAGS}") + set_source_files_properties(${SOURCES} ${LT_HAL_SRCS} PROPERTIES COMPILE_OPTIONS "${LT_STRICT_COMPILATION_FLAGS}") endif() ########################################################################### diff --git a/tests/functional/linux/spi/CMakeLists.txt b/tests/functional/linux/spi/CMakeLists.txt index fecb18e7d..ec1cba9d7 100644 --- a/tests/functional/linux/spi/CMakeLists.txt +++ b/tests/functional/linux/spi/CMakeLists.txt @@ -78,7 +78,7 @@ set(SOURCES # Enable strict compile flags for main.c and Libtropic HAL sources if(LT_STRICT_COMPILATION) - set_source_files_properties(${CMAKE_CURRENT_SOURCE_DIR}/main.c ${LT_HAL_SRCS} PROPERTIES COMPILE_OPTIONS "${LT_STRICT_COMPILATION_FLAGS}") + set_source_files_properties(${SOURCES} ${LT_HAL_SRCS} PROPERTIES COMPILE_OPTIONS "${LT_STRICT_COMPILATION_FLAGS}") endif() ########################################################################### diff --git a/tests/functional/linux/spi/main.c b/tests/functional/linux/spi/main.c index b3fbb83a2..94fe41211 100644 --- a/tests/functional/linux/spi/main.c +++ b/tests/functional/linux/spi/main.c @@ -2,7 +2,7 @@ * @file main.c * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -81,8 +81,9 @@ int main(void) // LT_GPIO_DEV_PATH is defined in CMakeLists.txt. int dev_path_len = snprintf(device.gpio_dev, sizeof(device.gpio_dev), "%s", LT_GPIO_DEV_PATH); if (dev_path_len < 0 || (size_t)dev_path_len >= sizeof(device.gpio_dev)) { - LT_LOG_ERROR("Error: LT_GPIO_DEV_PATH is too long for device.gpio_dev buffer (limit is %zu bytes).", - sizeof(device.gpio_dev)); + LT_LOG_ERROR( + "Error: LT_GPIO_DEV_PATH is too long for device.gpio_dev buffer (limit is %zu bytes).", + sizeof(device.gpio_dev)); LT_UNUSED(cleanup()); // Not caring about return val - we fail anyway. return -1; } @@ -90,8 +91,9 @@ int main(void) // LT_SPI_DEV_PATH is defined in CMakeLists.txt. dev_path_len = snprintf(device.spi_dev, sizeof(device.spi_dev), "%s", LT_SPI_DEV_PATH); if (dev_path_len < 0 || (size_t)dev_path_len >= sizeof(device.spi_dev)) { - LT_LOG_ERROR("Error: LT_SPI_DEV_PATH is too long for device.spi_dev buffer (limit is %zu bytes).", - sizeof(device.spi_dev)); + LT_LOG_ERROR( + "Error: LT_SPI_DEV_PATH is too long for device.spi_dev buffer (limit is %zu bytes).", + sizeof(device.spi_dev)); LT_UNUSED(cleanup()); // Not caring about return val - we fail anyway. return -1; } diff --git a/tests/functional/linux/spi_native_cs/main.c b/tests/functional/linux/spi_native_cs/main.c index 977f811cf..abe65a5ea 100644 --- a/tests/functional/linux/spi_native_cs/main.c +++ b/tests/functional/linux/spi_native_cs/main.c @@ -2,7 +2,7 @@ * @file main.c * @author Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -81,8 +81,9 @@ int main(void) // LT_SPI_DEV_PATH is defined in CMakeLists.txt. int dev_path_len = snprintf(device.spi_dev, sizeof(device.spi_dev), "%s", LT_SPI_DEV_PATH); if (dev_path_len < 0 || (size_t)dev_path_len >= sizeof(device.spi_dev)) { - LT_LOG_ERROR("Error: LT_SPI_DEV_PATH is too long for device.spi_dev buffer (limit is %zu bytes).", - sizeof(device.spi_dev)); + LT_LOG_ERROR( + "Error: LT_SPI_DEV_PATH is too long for device.spi_dev buffer (limit is %zu bytes).", + sizeof(device.spi_dev)); LT_UNUSED(cleanup()); // Not caring about return val - we fail anyway. return -1; } @@ -92,8 +93,9 @@ int main(void) #if LT_USE_INT_PIN dev_path_len = snprintf(device.gpio_dev, sizeof(device.gpio_dev), "%s", LT_GPIO_DEV_PATH); if (dev_path_len < 0 || (size_t)dev_path_len >= sizeof(device.gpio_dev)) { - LT_LOG_ERROR("Error: LT_GPIO_DEV_PATH is too long for device.gpio_dev buffer (limit is %zu bytes).", - sizeof(device.gpio_dev)); + LT_LOG_ERROR( + "Error: LT_GPIO_DEV_PATH is too long for device.gpio_dev buffer (limit is %zu bytes).", + sizeof(device.gpio_dev)); LT_UNUSED(cleanup()); // Not caring about return val - we fail anyway. return -1; } diff --git a/tests/functional/linux/usb_devkit/CMakeLists.txt b/tests/functional/linux/usb_devkit/CMakeLists.txt index 804c21528..171903265 100644 --- a/tests/functional/linux/usb_devkit/CMakeLists.txt +++ b/tests/functional/linux/usb_devkit/CMakeLists.txt @@ -72,7 +72,7 @@ set(SOURCES # Enable strict compile flags for main.c and Libtropic HAL sources if(LT_STRICT_COMPILATION) - set_source_files_properties(${CMAKE_CURRENT_SOURCE_DIR}/src/main.c ${LT_HAL_SRCS} PROPERTIES COMPILE_OPTIONS "${LT_STRICT_COMPILATION_FLAGS}") + set_source_files_properties(${SOURCES} ${LT_HAL_SRCS} PROPERTIES COMPILE_OPTIONS "${LT_STRICT_COMPILATION_FLAGS}") endif() ########################################################################### diff --git a/tests/functional/linux/usb_devkit/main.c b/tests/functional/linux/usb_devkit/main.c index f4a514677..df9361140 100644 --- a/tests/functional/linux/usb_devkit/main.c +++ b/tests/functional/linux/usb_devkit/main.c @@ -2,7 +2,7 @@ * @file main.c * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -81,8 +81,9 @@ int main(void) // LT_USB_DEVKIT_PATH is defined in CMakeLists.txt. int dev_path_len = snprintf(device.dev_path, sizeof(device.dev_path), "%s", LT_USB_DEVKIT_PATH); if (dev_path_len < 0 || (size_t)dev_path_len >= sizeof(device.dev_path)) { - LT_LOG_ERROR("Error: LT_USB_DEVKIT_PATH is too long for device.dev_path buffer (limit is %zu bytes).", - sizeof(device.dev_path)); + LT_LOG_ERROR( + "Error: LT_USB_DEVKIT_PATH is too long for device.dev_path buffer (limit is %zu bytes).", + sizeof(device.dev_path)); LT_UNUSED(cleanup()); // Not caring about return val - we fail anyway. return -1; } diff --git a/tests/functional/model/CMakeLists.txt b/tests/functional/model/CMakeLists.txt index 6b81e7ba0..d833db0ed 100644 --- a/tests/functional/model/CMakeLists.txt +++ b/tests/functional/model/CMakeLists.txt @@ -81,7 +81,7 @@ set(SOURCES # Enable strict compile flags for main.c and Libtropic HAL sources. if(LT_STRICT_COMPILATION) - set_source_files_properties(${CMAKE_CURRENT_SOURCE_DIR}/main.c ${LT_HAL_SRCS} PROPERTIES COMPILE_OPTIONS "${LT_STRICT_COMPILATION_FLAGS}") + set_source_files_properties(${SOURCES} ${LT_HAL_SRCS} PROPERTIES COMPILE_OPTIONS "${LT_STRICT_COMPILATION_FLAGS}") endif() ########################################################################### diff --git a/tests/functional/model/main.c b/tests/functional/model/main.c index 16e75ea2b..ce0915176 100644 --- a/tests/functional/model/main.c +++ b/tests/functional/model/main.c @@ -3,7 +3,7 @@ * @brief Common entrypoint for running functional tests against TROPIC01 model. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include diff --git a/tests/functional/src/CMakeLists.txt b/tests/functional/src/CMakeLists.txt index be9244bed..3c5ea5eca 100644 --- a/tests/functional/src/CMakeLists.txt +++ b/tests/functional/src/CMakeLists.txt @@ -313,6 +313,7 @@ set(LIBTROPIC_TEST_LIST lt_test_rev_random_value_get lt_test_rev_mac_and_destroy lt_test_rev_get_log_req + lt_test_rev_init_after_deinit ) # Export test list to parent project (usually platform-specific implementation) @@ -365,6 +366,7 @@ set(TEST_SRCS ${PATH_LIBTROPIC}/tests/functional/src/lt_test_rev_random_value_get.c ${PATH_LIBTROPIC}/tests/functional/src/lt_test_rev_mac_and_destroy.c ${PATH_LIBTROPIC}/tests/functional/src/lt_test_rev_get_log_req.c + ${PATH_LIBTROPIC}/tests/functional/src/lt_test_rev_init_after_deinit.c ) set(TEST_DIRS diff --git a/tests/functional/src/libtropic_functional_tests.h b/tests/functional/src/libtropic_functional_tests.h index 9573bafed..ae57d5c39 100644 --- a/tests/functional/src/libtropic_functional_tests.h +++ b/tests/functional/src/libtropic_functional_tests.h @@ -320,8 +320,8 @@ void lt_test_rev_ecc_key_generate(lt_handle_t *h); * 5. Try storing again, also using Ed25519 curve and check for errors. * 6. Read the stored public key and check curve and origin. * 7. Erase the key slot. - * 8. Repeat steps 2-6 for the Ed25519 curve with pre-generated keys (without storing invalid private key - that cannot - * be checked in the case of Ed25519). + * 8. Repeat steps 2-6 for the Ed25519 curve with pre-generated keys (without storing invalid private + * key - that cannot be checked in the case of Ed25519). * * @param h Handle for communication with TROPIC01 */ @@ -348,11 +348,11 @@ void lt_test_rev_random_value_get(lt_handle_t *h); * 1. Start Secure Session with pairing key slot 0. * 2. Setup random PIN with randomly generated number of attempts. * 3. Do a random number of wrong attempts (less than the maximum number of attempts). - * 4. Do an attempt with the correct PIN with the first understroyed slot and compare the cryptographic key with the - * one from the setup phase. + * 4. Do an attempt with the correct PIN with the first understroyed slot and compare the + * cryptographic key with the one from the setup phase. * 5. Restore all destroyed slots. - * 6. Do an attempt with the correct PIN with all the used slots and compare the cryptographic keys with the one from - * the setup phase. + * 6. Do an attempt with the correct PIN with all the used slots and compare the cryptographic keys + * with the one from the setup phase. * * @param h Handle for communication with TROPIC01 */ @@ -373,6 +373,22 @@ void lt_test_rev_mac_and_destroy(lt_handle_t *h); */ void lt_test_rev_get_log_req(lt_handle_t *h); +/** + * @brief Tests calling lt_init after lt_deinit. + * + * Test steps: + * 1. Initialize the handle. + * 2. Start Secure Session with pairing key slot 0. + * 3. Generate random data and send a Ping command. + * 4. Compare sent and received message. + * 5. Abort Secure Session. + * 6. Deinitialize the handle. + * 7. Repeat steps 1-6 to test reinitialization after deinitialization. + * + * @param h Handle for communication with TROPIC01 + */ +void lt_test_rev_init_after_deinit(lt_handle_t *h); + /** @} */ // end of libtropic_funct_tests group #ifdef __cplusplus diff --git a/tests/functional/src/lt_test_ire_pairing_key_slots.c b/tests/functional/src/lt_test_ire_pairing_key_slots.c index 94158f1bd..b0c4791a7 100644 --- a/tests/functional/src/lt_test_ire_pairing_key_slots.c +++ b/tests/functional/src/lt_test_ire_pairing_key_slots.c @@ -18,34 +18,34 @@ #define PRINT_BUFF_SIZE 65 /** @brief X25519 private key to execute a Secure Channel Handshake on Pairing Key slot 1. */ -const uint8_t sh1priv[] - = {0x58, 0xc4, 0x81, 0x88, 0xf8, 0xb1, 0xcb, 0xd4, 0x19, 0x00, 0x2e, 0x9c, 0x8d, 0xf8, 0xce, 0xea, - 0xf3, 0xa9, 0x11, 0xde, 0xb6, 0x6b, 0xc8, 0x87, 0xae, 0xe7, 0x88, 0x10, 0xfb, 0x48, 0xb6, 0x74}; +const uint8_t sh1priv[] = {0x58, 0xc4, 0x81, 0x88, 0xf8, 0xb1, 0xcb, 0xd4, 0x19, 0x00, 0x2e, + 0x9c, 0x8d, 0xf8, 0xce, 0xea, 0xf3, 0xa9, 0x11, 0xde, 0xb6, 0x6b, + 0xc8, 0x87, 0xae, 0xe7, 0x88, 0x10, 0xfb, 0x48, 0xb6, 0x74}; /** @brief X25519 public key to execute a Secure Channel Handshake on Pairing Key slot 1. */ -const uint8_t sh1pub[] - = {0xe1, 0xdc, 0xf9, 0xc3, 0x46, 0xbc, 0xf2, 0xe7, 0x8b, 0xa8, 0xf0, 0x27, 0xd8, 0x0a, 0x8a, 0x33, - 0xcc, 0xf3, 0xe9, 0xdf, 0x6b, 0xdf, 0x65, 0xa2, 0xc1, 0xae, 0xc4, 0xd9, 0x21, 0xe1, 0x8d, 0x51}; +const uint8_t sh1pub[] = {0xe1, 0xdc, 0xf9, 0xc3, 0x46, 0xbc, 0xf2, 0xe7, 0x8b, 0xa8, 0xf0, + 0x27, 0xd8, 0x0a, 0x8a, 0x33, 0xcc, 0xf3, 0xe9, 0xdf, 0x6b, 0xdf, + 0x65, 0xa2, 0xc1, 0xae, 0xc4, 0xd9, 0x21, 0xe1, 0x8d, 0x51}; /** @brief X25519 private key to execute a Secure Channel Handshake on Pairing Key slot 2. */ -const uint8_t sh2priv[] - = {0x00, 0x40, 0x5e, 0x19, 0x46, 0x75, 0xab, 0xe1, 0x5f, 0x0b, 0x57, 0xf2, 0x5b, 0x12, 0x86, 0x62, - 0xab, 0xb0, 0xe9, 0xc6, 0xa7, 0xc3, 0xca, 0xdf, 0x1c, 0xb1, 0xd2, 0xb7, 0xf8, 0xcf, 0x35, 0x47}; +const uint8_t sh2priv[] = {0x00, 0x40, 0x5e, 0x19, 0x46, 0x75, 0xab, 0xe1, 0x5f, 0x0b, 0x57, + 0xf2, 0x5b, 0x12, 0x86, 0x62, 0xab, 0xb0, 0xe9, 0xc6, 0xa7, 0xc3, + 0xca, 0xdf, 0x1c, 0xb1, 0xd2, 0xb7, 0xf8, 0xcf, 0x35, 0x47}; /** @brief X25519 public key to execute a Secure Channel Handshake on Pairing Key slot 2. */ -const uint8_t sh2pub[] - = {0x66, 0xb9, 0x92, 0x5a, 0x85, 0x66, 0xe8, 0x09, 0x5c, 0x56, 0x80, 0xfb, 0x22, 0xd4, 0xb8, 0x4b, - 0xf8, 0xe3, 0x12, 0xb2, 0x7c, 0x4b, 0xac, 0xce, 0x26, 0x3c, 0x78, 0x39, 0x6d, 0x4c, 0x16, 0x6c}; +const uint8_t sh2pub[] = {0x66, 0xb9, 0x92, 0x5a, 0x85, 0x66, 0xe8, 0x09, 0x5c, 0x56, 0x80, + 0xfb, 0x22, 0xd4, 0xb8, 0x4b, 0xf8, 0xe3, 0x12, 0xb2, 0x7c, 0x4b, + 0xac, 0xce, 0x26, 0x3c, 0x78, 0x39, 0x6d, 0x4c, 0x16, 0x6c}; /** @brief X25519 private key to execute a Secure Channel Handshake on Pairing Key slot 3. */ -const uint8_t sh3priv[] - = {0xb0, 0x90, 0x9f, 0xe1, 0xf3, 0x1f, 0xa1, 0x21, 0x75, 0xef, 0x45, 0xb1, 0x42, 0xde, 0x0e, 0xdd, - 0xa1, 0xf4, 0x51, 0x01, 0x40, 0xc2, 0xe5, 0x2c, 0xf4, 0x68, 0xac, 0x96, 0xa1, 0x0e, 0xcb, 0x46}; +const uint8_t sh3priv[] = {0xb0, 0x90, 0x9f, 0xe1, 0xf3, 0x1f, 0xa1, 0x21, 0x75, 0xef, 0x45, + 0xb1, 0x42, 0xde, 0x0e, 0xdd, 0xa1, 0xf4, 0x51, 0x01, 0x40, 0xc2, + 0xe5, 0x2c, 0xf4, 0x68, 0xac, 0x96, 0xa1, 0x0e, 0xcb, 0x46}; /** @brief X25519 public key to execute a Secure Channel Handshake on Pairing Key slot 3. */ -const uint8_t sh3pub[] - = {0x22, 0x57, 0xa8, 0x2f, 0x85, 0x8f, 0x13, 0x32, 0xfa, 0x0f, 0xf6, 0x0c, 0x76, 0x29, 0x42, 0x70, - 0xa9, 0x58, 0x9d, 0xfd, 0x47, 0xa5, 0x23, 0x78, 0x18, 0x4d, 0x2d, 0x38, 0xf0, 0xa7, 0xc4, 0x01}; +const uint8_t sh3pub[] = {0x22, 0x57, 0xa8, 0x2f, 0x85, 0x8f, 0x13, 0x32, 0xfa, 0x0f, 0xf6, + 0x0c, 0x76, 0x29, 0x42, 0x70, 0xa9, 0x58, 0x9d, 0xfd, 0x47, 0xa5, + 0x23, 0x78, 0x18, 0x4d, 0x2d, 0x38, 0xf0, 0xa7, 0xc4, 0x01}; void lt_test_ire_pairing_key_slots(lt_handle_t *h) { @@ -83,7 +83,8 @@ void lt_test_ire_pairing_key_slots(lt_handle_t *h) // Write pairing keys into slot 1,2,3 for (uint8_t i = TR01_PAIRING_KEY_SLOT_INDEX_1; i <= TR01_PAIRING_KEY_SLOT_INDEX_3; i++) { LT_LOG_INFO("Writing to pairing key slot %" PRIu8 "...", i); - LT_TEST_ASSERT(LT_OK, lt_print_bytes(pub_keys[i], TR01_SHIPUB_LEN, print_buff, PRINT_BUFF_SIZE)); + LT_TEST_ASSERT(LT_OK, + lt_print_bytes(pub_keys[i], TR01_SHIPUB_LEN, print_buff, PRINT_BUFF_SIZE)); LT_LOG_INFO("%s", print_buff); LT_TEST_ASSERT(LT_OK, lt_pairing_key_write(h, pub_keys[i], i)); LT_LOG_INFO(); @@ -110,7 +111,8 @@ void lt_test_ire_pairing_key_slots(lt_handle_t *h) // Test secure session with slots 1,2,3 for (uint8_t i = TR01_PAIRING_KEY_SLOT_INDEX_1; i <= TR01_PAIRING_KEY_SLOT_INDEX_3; i++) { LT_LOG_INFO("Starting Secure Session with key %" PRIu8 "...", i); - LT_TEST_ASSERT(LT_OK, lt_verify_chip_and_start_secure_session(h, priv_keys[i], pub_keys[i], i)); + LT_TEST_ASSERT(LT_OK, + lt_verify_chip_and_start_secure_session(h, priv_keys[i], pub_keys[i], i)); LT_LOG_INFO("Aborting Secure Session with slot %" PRIu8 "...", i); LT_TEST_ASSERT(LT_OK, lt_session_abort(h)); diff --git a/tests/functional/src/lt_test_rev_ecc_key_generate.c b/tests/functional/src/lt_test_rev_ecc_key_generate.c index 04904518d..f15da3b49 100644 --- a/tests/functional/src/lt_test_rev_ecc_key_generate.c +++ b/tests/functional/src/lt_test_rev_ecc_key_generate.c @@ -21,9 +21,10 @@ lt_handle_t *g_h; static lt_ret_t lt_test_rev_ecc_key_generate_cleanup(void) { lt_ret_t ret; - uint8_t read_pub_key[TR01_CURVE_P256_PUBKEY_LEN]; // The read key can have 32B or 64B, depending on the used curve, - // but we don't know what is stored in the slot, so to be safe, - // let's assume the size of pubkey on the P256 curve. + uint8_t read_pub_key[TR01_CURVE_P256_PUBKEY_LEN]; // The read key can have 32B or 64B, depending + // on the used curve, but we don't know what is + // stored in the slot, so to be safe, let's + // assume the size of pubkey on the P256 curve. lt_ecc_curve_type_t curve; lt_ecc_key_origin_t origin; @@ -79,10 +80,11 @@ void lt_test_rev_ecc_key_generate(lt_handle_t *h) // Making the handle accessible to the cleanup function. g_h = h; - uint8_t read_pub_key[TR01_CURVE_P256_PUBKEY_LEN]; // The read key can have 32B or 64B, depending on the used curve, - // and we work with both curves here, so let's use one buffer for - // both for simplification and assume the size of pubkey on the - // P256 curve to be safe. + uint8_t read_pub_key[TR01_CURVE_P256_PUBKEY_LEN]; // The read key can have 32B or 64B, depending + // on the used curve, and we work with both + // curves here, so let's use one buffer for both + // for simplification and assume the size of + // pubkey on the P256 curve to be safe. lt_ecc_curve_type_t curve; lt_ecc_key_origin_t origin; @@ -102,7 +104,8 @@ void lt_test_rev_ecc_key_generate(lt_handle_t *h) LT_LOG_INFO("Testing ECC key slot #%" PRIu8 "...", i); LT_LOG_INFO("Checking if slot is empty..."); - LT_TEST_ASSERT(LT_L3_INVALID_KEY, lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); + LT_TEST_ASSERT(LT_L3_INVALID_KEY, + lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); LT_LOG_INFO("Generating private key using P256 curve..."); LT_TEST_ASSERT(LT_OK, lt_ecc_key_generate(h, i, TR01_CURVE_P256)); @@ -114,7 +117,8 @@ void lt_test_rev_ecc_key_generate(lt_handle_t *h) LT_TEST_ASSERT(LT_L3_FAIL, lt_ecc_key_generate(h, i, TR01_CURVE_ED25519)); LT_LOG_INFO("Reading the generated public key..."); - LT_TEST_ASSERT(LT_OK, lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); + LT_TEST_ASSERT(LT_OK, + lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); LT_LOG_INFO("Checking curve type of the read key..."); LT_TEST_ASSERT(1, (curve == TR01_CURVE_P256)); @@ -133,7 +137,8 @@ void lt_test_rev_ecc_key_generate(lt_handle_t *h) LT_LOG_INFO("Testing ECC key slot #%" PRIu8 "...", i); LT_LOG_INFO("Checking if slot is empty..."); - LT_TEST_ASSERT(LT_L3_INVALID_KEY, lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); + LT_TEST_ASSERT(LT_L3_INVALID_KEY, + lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); LT_LOG_INFO("Generating private key using Ed25519 curve..."); LT_TEST_ASSERT(LT_OK, lt_ecc_key_generate(h, i, TR01_CURVE_ED25519)); @@ -145,7 +150,8 @@ void lt_test_rev_ecc_key_generate(lt_handle_t *h) LT_TEST_ASSERT(LT_L3_FAIL, lt_ecc_key_generate(h, i, TR01_CURVE_P256)); LT_LOG_INFO("Reading the generated public key..."); - LT_TEST_ASSERT(LT_OK, lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); + LT_TEST_ASSERT(LT_OK, + lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); LT_LOG_INFO("Checking curve type of the read key..."); LT_TEST_ASSERT(1, (curve == TR01_CURVE_ED25519)); @@ -157,7 +163,8 @@ void lt_test_rev_ecc_key_generate(lt_handle_t *h) LT_TEST_ASSERT(LT_OK, lt_ecc_key_erase(h, i)); LT_LOG_INFO("Trying to read the erased slot (should fail)..."); - LT_TEST_ASSERT(LT_L3_INVALID_KEY, lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); + LT_TEST_ASSERT(LT_L3_INVALID_KEY, + lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); } LT_LOG_LINE(); diff --git a/tests/functional/src/lt_test_rev_ecc_key_store.c b/tests/functional/src/lt_test_rev_ecc_key_store.c index c5fe257fd..5432b3a81 100644 --- a/tests/functional/src/lt_test_rev_ecc_key_store.c +++ b/tests/functional/src/lt_test_rev_ecc_key_store.c @@ -16,25 +16,25 @@ #include "string.h" // Pre-generated keys for testing using OpenSSL -uint8_t p256_priv_test_key[] - = {0x7d, 0x35, 0xc5, 0x0a, 0xfe, 0x9b, 0x15, 0xeb, 0x41, 0x16, 0xcb, 0x9b, 0xaa, 0xc2, 0xcb, 0xdd, - 0xbb, 0xdc, 0xb9, 0xb8, 0x77, 0xc7, 0x0f, 0x9e, 0x21, 0x8c, 0x2c, 0xff, 0xaa, 0x8b, 0x6f, 0x72}; -uint8_t p256_pub_test_key[] - = {0x62, 0x4e, 0xeb, 0x9d, 0x01, 0x82, 0x24, 0xdd, 0x1f, 0x2a, 0xbb, 0xdc, 0x0f, 0x8f, 0xca, 0xa3, - 0xc8, 0x9c, 0x2f, 0x9a, 0x46, 0x11, 0x73, 0x8b, 0x5f, 0xcb, 0xc5, 0x5b, 0xdb, 0x51, 0x93, 0xd7, - 0x2f, 0x2e, 0x48, 0x56, 0x1b, 0x97, 0x51, 0x16, 0xc4, 0x26, 0x6e, 0x50, 0x64, 0x30, 0xbc, 0x40, - 0xbf, 0x11, 0xb5, 0xc7, 0x51, 0x8c, 0xac, 0x64, 0xb2, 0x4c, 0xc3, 0x8b, 0x80, 0x4d, 0xa5, 0x1b}; -uint8_t ed25519_priv_test_key[] - = {0x73, 0x5b, 0x09, 0xb9, 0x5f, 0x4e, 0x17, 0x83, 0x4f, 0xa0, 0x7e, 0x93, 0x14, 0xa8, 0x7b, 0xa8, - 0x86, 0x36, 0x00, 0x30, 0x7f, 0x90, 0xf2, 0x3d, 0x52, 0x4c, 0xac, 0x15, 0x5f, 0x94, 0x44, 0xe0}; -uint8_t ed25519_pub_test_key[] - = {0xde, 0x86, 0x1d, 0xac, 0xc2, 0x36, 0x4a, 0xe0, 0x5f, 0xb4, 0xef, 0x3c, 0xfc, 0xc1, 0xb2, 0x41, - 0xab, 0x51, 0xdb, 0xc6, 0x38, 0xfc, 0x84, 0xb2, 0x5f, 0x04, 0xe6, 0x58, 0x5a, 0xd5, 0x3c, 0xcd}; +uint8_t p256_priv_test_key[] = {0x7d, 0x35, 0xc5, 0x0a, 0xfe, 0x9b, 0x15, 0xeb, 0x41, 0x16, 0xcb, + 0x9b, 0xaa, 0xc2, 0xcb, 0xdd, 0xbb, 0xdc, 0xb9, 0xb8, 0x77, 0xc7, + 0x0f, 0x9e, 0x21, 0x8c, 0x2c, 0xff, 0xaa, 0x8b, 0x6f, 0x72}; +uint8_t p256_pub_test_key[] = { + 0x62, 0x4e, 0xeb, 0x9d, 0x01, 0x82, 0x24, 0xdd, 0x1f, 0x2a, 0xbb, 0xdc, 0x0f, 0x8f, 0xca, 0xa3, + 0xc8, 0x9c, 0x2f, 0x9a, 0x46, 0x11, 0x73, 0x8b, 0x5f, 0xcb, 0xc5, 0x5b, 0xdb, 0x51, 0x93, 0xd7, + 0x2f, 0x2e, 0x48, 0x56, 0x1b, 0x97, 0x51, 0x16, 0xc4, 0x26, 0x6e, 0x50, 0x64, 0x30, 0xbc, 0x40, + 0xbf, 0x11, 0xb5, 0xc7, 0x51, 0x8c, 0xac, 0x64, 0xb2, 0x4c, 0xc3, 0x8b, 0x80, 0x4d, 0xa5, 0x1b}; +uint8_t ed25519_priv_test_key[] = {0x73, 0x5b, 0x09, 0xb9, 0x5f, 0x4e, 0x17, 0x83, 0x4f, 0xa0, 0x7e, + 0x93, 0x14, 0xa8, 0x7b, 0xa8, 0x86, 0x36, 0x00, 0x30, 0x7f, 0x90, + 0xf2, 0x3d, 0x52, 0x4c, 0xac, 0x15, 0x5f, 0x94, 0x44, 0xe0}; +uint8_t ed25519_pub_test_key[] = {0xde, 0x86, 0x1d, 0xac, 0xc2, 0x36, 0x4a, 0xe0, 0x5f, 0xb4, 0xef, + 0x3c, 0xfc, 0xc1, 0xb2, 0x41, 0xab, 0x51, 0xdb, 0xc6, 0x38, 0xfc, + 0x84, 0xb2, 0x5f, 0x04, 0xe6, 0x58, 0x5a, 0xd5, 0x3c, 0xcd}; // Invalid key can be checked only for P256 -uint8_t p256_invalid_priv_test_key[] - = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; +uint8_t p256_invalid_priv_test_key[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; // Shared with cleanup function lt_handle_t *g_h; @@ -42,9 +42,10 @@ lt_handle_t *g_h; static lt_ret_t lt_test_rev_ecc_key_store_cleanup(void) { lt_ret_t ret; - uint8_t read_pub_key[TR01_CURVE_P256_PUBKEY_LEN]; // The read key can have 32B or 64B, depending on the used curve, - // but we don't know what is stored in the slot, so to be safe, - // let's assume the size of pubkey on the P256 curve. + uint8_t read_pub_key[TR01_CURVE_P256_PUBKEY_LEN]; // The read key can have 32B or 64B, depending + // on the used curve, but we don't know what is + // stored in the slot, so to be safe, let's + // assume the size of pubkey on the P256 curve. lt_ecc_curve_type_t curve; lt_ecc_key_origin_t origin; @@ -100,10 +101,11 @@ void lt_test_rev_ecc_key_store(lt_handle_t *h) // Making the handle accessible to the cleanup function. g_h = h; - uint8_t read_pub_key[TR01_CURVE_P256_PUBKEY_LEN]; // The read key can have 32B or 64B, depending on the used curve, - // and we work with both curves here, so let's use one buffer for - // both for simplification and assume the size of pubkey on the - // P256 curve to be safe. + uint8_t read_pub_key[TR01_CURVE_P256_PUBKEY_LEN]; // The read key can have 32B or 64B, depending + // on the used curve, and we work with both + // curves here, so let's use one buffer for both + // for simplification and assume the size of + // pubkey on the P256 curve to be safe. lt_ecc_curve_type_t curve; lt_ecc_key_origin_t origin; @@ -123,10 +125,12 @@ void lt_test_rev_ecc_key_store(lt_handle_t *h) LT_LOG_INFO("Testing ECC key slot #%" PRIu8 "...", i); LT_LOG_INFO("Checking if slot is empty..."); - LT_TEST_ASSERT(LT_L3_INVALID_KEY, lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); + LT_TEST_ASSERT(LT_L3_INVALID_KEY, + lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); LT_LOG_INFO("Storing invalid private key (should fail)..."); - LT_TEST_ASSERT(LT_L3_FAIL, lt_ecc_key_store(h, i, TR01_CURVE_P256, p256_invalid_priv_test_key)); + LT_TEST_ASSERT(LT_L3_FAIL, + lt_ecc_key_store(h, i, TR01_CURVE_P256, p256_invalid_priv_test_key)); LT_LOG_INFO("Storing private key pre-generated using P256 curve..."); LT_TEST_ASSERT(LT_OK, lt_ecc_key_store(h, i, TR01_CURVE_P256, p256_priv_test_key)); @@ -138,7 +142,8 @@ void lt_test_rev_ecc_key_store(lt_handle_t *h) LT_TEST_ASSERT(LT_L3_FAIL, lt_ecc_key_store(h, i, TR01_CURVE_ED25519, ed25519_priv_test_key)); LT_LOG_INFO("Reading the stored public key..."); - LT_TEST_ASSERT(LT_OK, lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); + LT_TEST_ASSERT(LT_OK, + lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); LT_LOG_INFO("Checking curve type of the read key..."); LT_TEST_ASSERT(1, (curve == TR01_CURVE_P256)); @@ -160,7 +165,8 @@ void lt_test_rev_ecc_key_store(lt_handle_t *h) LT_LOG_INFO("Testing ECC key slot #%" PRIu8 "...", i); LT_LOG_INFO("Checking if slot is empty..."); - LT_TEST_ASSERT(LT_L3_INVALID_KEY, lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); + LT_TEST_ASSERT(LT_L3_INVALID_KEY, + lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); LT_LOG_INFO("Storing private key pre-generated using Ed25519 curve..."); LT_TEST_ASSERT(LT_OK, lt_ecc_key_store(h, i, TR01_CURVE_ED25519, ed25519_priv_test_key)); @@ -172,7 +178,8 @@ void lt_test_rev_ecc_key_store(lt_handle_t *h) LT_TEST_ASSERT(LT_L3_FAIL, lt_ecc_key_store(h, i, TR01_CURVE_P256, p256_priv_test_key)); LT_LOG_INFO("Reading the stored public key..."); - LT_TEST_ASSERT(LT_OK, lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); + LT_TEST_ASSERT(LT_OK, + lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); LT_LOG_INFO("Checking curve type of the read key..."); LT_TEST_ASSERT(1, (curve == TR01_CURVE_ED25519)); @@ -187,7 +194,8 @@ void lt_test_rev_ecc_key_store(lt_handle_t *h) LT_TEST_ASSERT(LT_OK, lt_ecc_key_erase(h, i)); LT_LOG_INFO("Trying to read the erased slot (should fail)..."); - LT_TEST_ASSERT(LT_L3_INVALID_KEY, lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); + LT_TEST_ASSERT(LT_L3_INVALID_KEY, + lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); } LT_LOG_LINE(); diff --git a/tests/functional/src/lt_test_rev_ecdsa_sign.c b/tests/functional/src/lt_test_rev_ecdsa_sign.c index 02a606da6..8c9cd4a6b 100644 --- a/tests/functional/src/lt_test_rev_ecdsa_sign.c +++ b/tests/functional/src/lt_test_rev_ecdsa_sign.c @@ -22,9 +22,9 @@ #define MSG_TO_SIGN_LEN_MAX 4096 // Pre-generated key for testing using OpenSSL -uint8_t priv_test_key[] - = {0x5e, 0xc6, 0xf1, 0xef, 0x96, 0x1f, 0x69, 0xb5, 0xd4, 0x34, 0xe1, 0x50, 0x6e, 0xa1, 0xcc, 0x51, - 0x11, 0x91, 0x94, 0x65, 0x87, 0xcb, 0x36, 0x82, 0x24, 0x07, 0x70, 0x32, 0x10, 0x1d, 0x62, 0xd1}; +uint8_t priv_test_key[] = {0x5e, 0xc6, 0xf1, 0xef, 0x96, 0x1f, 0x69, 0xb5, 0xd4, 0x34, 0xe1, + 0x50, 0x6e, 0xa1, 0xcc, 0x51, 0x11, 0x91, 0x94, 0x65, 0x87, 0xcb, + 0x36, 0x82, 0x24, 0x07, 0x70, 0x32, 0x10, 0x1d, 0x62, 0xd1}; // Shared with cleanup function lt_handle_t *g_h; @@ -32,10 +32,11 @@ lt_handle_t *g_h; static lt_ret_t lt_test_rev_ecdsa_sign_cleanup(void) { lt_ret_t ret; - uint8_t read_pub_key[TR01_CURVE_P256_PUBKEY_LEN]; // The read key can have 32B or 64B, depending on the used curve, - // and we work with both curves here, so let's use one buffer for - // both for simplification and assume the size of pubkey on the - // P256 curve to be safe. + uint8_t read_pub_key[TR01_CURVE_P256_PUBKEY_LEN]; // The read key can have 32B or 64B, depending + // on the used curve, and we work with both + // curves here, so let's use one buffer for both + // for simplification and assume the size of + // pubkey on the P256 curve to be safe. lt_ecc_curve_type_t curve; lt_ecc_key_origin_t origin; @@ -117,7 +118,8 @@ void lt_test_rev_ecdsa_sign(lt_handle_t *h) LT_TEST_ASSERT(LT_OK, lt_random_bytes(h, &msg_to_sign_len, sizeof(msg_to_sign_len))); msg_to_sign_len %= MSG_TO_SIGN_LEN_MAX + 1; // 0-MSG_TO_SIGN_LEN_MAX - LT_LOG_INFO("Generating random message with length %" PRIu32 " for signing...", msg_to_sign_len); + LT_LOG_INFO("Generating random message with length %" PRIu32 " for signing...", + msg_to_sign_len); LT_TEST_ASSERT(LT_OK, lt_random_bytes(h, msg_to_sign, msg_to_sign_len)); LT_LOG_INFO("Signing message with empty slot (should fail)..."); @@ -127,7 +129,8 @@ void lt_test_rev_ecdsa_sign(lt_handle_t *h) LT_TEST_ASSERT(LT_OK, lt_ecc_key_store(h, i, TR01_CURVE_P256, priv_test_key)); LT_LOG_INFO("Reading the stored public key..."); - LT_TEST_ASSERT(LT_OK, lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); + LT_TEST_ASSERT(LT_OK, + lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); LT_LOG_INFO("Signing message..."); LT_TEST_ASSERT(LT_OK, lt_ecc_ecdsa_sign(h, i, msg_to_sign, msg_to_sign_len, rs)); @@ -159,7 +162,8 @@ void lt_test_rev_ecdsa_sign(lt_handle_t *h) LT_TEST_ASSERT(LT_OK, lt_random_bytes(h, &msg_to_sign_len, sizeof(msg_to_sign_len))); msg_to_sign_len %= MSG_TO_SIGN_LEN_MAX + 1; // 0-MSG_TO_SIGN_LEN_MAX - LT_LOG_INFO("Generating random message with length %" PRIu32 " for signing...", msg_to_sign_len); + LT_LOG_INFO("Generating random message with length %" PRIu32 " for signing...", + msg_to_sign_len); LT_TEST_ASSERT(LT_OK, lt_random_bytes(h, msg_to_sign, msg_to_sign_len)); LT_LOG_INFO("Signing message with empty slot (should fail)..."); @@ -169,7 +173,8 @@ void lt_test_rev_ecdsa_sign(lt_handle_t *h) LT_TEST_ASSERT(LT_OK, lt_ecc_key_generate(h, i, TR01_CURVE_P256)); LT_LOG_INFO("Reading the generated public key..."); - LT_TEST_ASSERT(LT_OK, lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); + LT_TEST_ASSERT(LT_OK, + lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); LT_LOG_INFO("Signing message..."); LT_TEST_ASSERT(LT_OK, lt_ecc_ecdsa_sign(h, i, msg_to_sign, msg_to_sign_len, rs)); diff --git a/tests/functional/src/lt_test_rev_eddsa_sign.c b/tests/functional/src/lt_test_rev_eddsa_sign.c index 1b776164f..bf3ea79eb 100644 --- a/tests/functional/src/lt_test_rev_eddsa_sign.c +++ b/tests/functional/src/lt_test_rev_eddsa_sign.c @@ -19,9 +19,9 @@ #include "string.h" // Pre-generated key for testing using OpenSSL -uint8_t priv_test_key[] - = {0x42, 0xb2, 0xee, 0x0e, 0x9b, 0xb5, 0x72, 0x50, 0x6e, 0xda, 0x06, 0x3e, 0xcb, 0x98, 0x43, 0x51, - 0x6f, 0xeb, 0xe6, 0x5f, 0x94, 0x3e, 0xf1, 0xb6, 0x0c, 0x74, 0x6d, 0x4c, 0x46, 0x83, 0xde, 0x15}; +uint8_t priv_test_key[] = {0x42, 0xb2, 0xee, 0x0e, 0x9b, 0xb5, 0x72, 0x50, 0x6e, 0xda, 0x06, + 0x3e, 0xcb, 0x98, 0x43, 0x51, 0x6f, 0xeb, 0xe6, 0x5f, 0x94, 0x3e, + 0xf1, 0xb6, 0x0c, 0x74, 0x6d, 0x4c, 0x46, 0x83, 0xde, 0x15}; // Shared with cleanup function lt_handle_t *g_h; @@ -29,10 +29,11 @@ lt_handle_t *g_h; static lt_ret_t lt_test_rev_eddsa_sign_cleanup(void) { lt_ret_t ret; - uint8_t read_pub_key[TR01_CURVE_P256_PUBKEY_LEN]; // The read key can have 32B or 64B, depending on the used curve, - // and we work with both curves here, so let's use one buffer for - // both for simplification and assume the size of pubkey on the - // P256 curve to be safe. + uint8_t read_pub_key[TR01_CURVE_P256_PUBKEY_LEN]; // The read key can have 32B or 64B, depending + // on the used curve, and we work with both + // curves here, so let's use one buffer for both + // for simplification and assume the size of + // pubkey on the P256 curve to be safe. lt_ecc_curve_type_t curve; lt_ecc_key_origin_t origin; @@ -88,8 +89,8 @@ void lt_test_rev_eddsa_sign(lt_handle_t *h) // Making the handle accessible to the cleanup function. g_h = h; - uint8_t read_pub_key[TR01_CURVE_ED25519_PUBKEY_LEN], msg_to_sign[TR01_L3_EDDSA_SIGN_CMD_MSG_LEN_MAX], - rs[TR01_ECDSA_EDDSA_SIGNATURE_LENGTH]; + uint8_t read_pub_key[TR01_CURVE_ED25519_PUBKEY_LEN], + msg_to_sign[TR01_L3_EDDSA_SIGN_CMD_MSG_LEN_MAX], rs[TR01_ECDSA_EDDSA_SIGNATURE_LENGTH]; lt_ecc_curve_type_t curve; lt_ecc_key_origin_t origin; uint32_t msg_to_sign_len; @@ -109,11 +110,13 @@ void lt_test_rev_eddsa_sign(lt_handle_t *h) LT_LOG_INFO(); LT_LOG_INFO("Testing signing with ECC key slot #%" PRIu8 "...", i); - LT_LOG_INFO("Generating random message length <= %d...", (int)TR01_L3_EDDSA_SIGN_CMD_MSG_LEN_MAX); + LT_LOG_INFO("Generating random message length <= %d...", + (int)TR01_L3_EDDSA_SIGN_CMD_MSG_LEN_MAX); LT_TEST_ASSERT(LT_OK, lt_random_bytes(h, &msg_to_sign_len, sizeof(msg_to_sign_len))); msg_to_sign_len %= TR01_L3_EDDSA_SIGN_CMD_MSG_LEN_MAX + 1; // 0-4096 - LT_LOG_INFO("Generating random message with length %" PRIu32 " for signing...", msg_to_sign_len); + LT_LOG_INFO("Generating random message with length %" PRIu32 " for signing...", + msg_to_sign_len); LT_TEST_ASSERT(LT_OK, lt_random_bytes(h, msg_to_sign, msg_to_sign_len)); LT_LOG_INFO("Signing message with empty slot (should fail)..."); @@ -123,7 +126,8 @@ void lt_test_rev_eddsa_sign(lt_handle_t *h) LT_TEST_ASSERT(LT_OK, lt_ecc_key_store(h, i, TR01_CURVE_ED25519, priv_test_key)); LT_LOG_INFO("Reading the stored public key..."); - LT_TEST_ASSERT(LT_OK, lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); + LT_TEST_ASSERT(LT_OK, + lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); LT_LOG_INFO("Signing message..."); LT_TEST_ASSERT(LT_OK, lt_ecc_eddsa_sign(h, i, msg_to_sign, msg_to_sign_len, rs)); @@ -144,11 +148,13 @@ void lt_test_rev_eddsa_sign(lt_handle_t *h) LT_LOG_INFO(); LT_LOG_INFO("Testing signing with ECC key slot #%" PRIu8 "...", i); - LT_LOG_INFO("Generating random message length <= %d...", (int)TR01_L3_EDDSA_SIGN_CMD_MSG_LEN_MAX); + LT_LOG_INFO("Generating random message length <= %d...", + (int)TR01_L3_EDDSA_SIGN_CMD_MSG_LEN_MAX); LT_TEST_ASSERT(LT_OK, lt_random_bytes(h, &msg_to_sign_len, sizeof(msg_to_sign_len))); msg_to_sign_len %= TR01_L3_EDDSA_SIGN_CMD_MSG_LEN_MAX + 1; // 0-4096 - LT_LOG_INFO("Generating random message with length %" PRIu32 " for signing...", msg_to_sign_len); + LT_LOG_INFO("Generating random message with length %" PRIu32 " for signing...", + msg_to_sign_len); LT_TEST_ASSERT(LT_OK, lt_random_bytes(h, msg_to_sign, msg_to_sign_len)); LT_LOG_INFO("Signing message with empty slot (should fail)..."); @@ -158,7 +164,8 @@ void lt_test_rev_eddsa_sign(lt_handle_t *h) LT_TEST_ASSERT(LT_OK, lt_ecc_key_generate(h, i, TR01_CURVE_ED25519)); LT_LOG_INFO("Reading the generated public key..."); - LT_TEST_ASSERT(LT_OK, lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); + LT_TEST_ASSERT(LT_OK, + lt_ecc_key_read(h, i, read_pub_key, sizeof(read_pub_key), &curve, &origin)); LT_LOG_INFO("Signing message..."); LT_TEST_ASSERT(LT_OK, lt_ecc_eddsa_sign(h, i, msg_to_sign, msg_to_sign_len, rs)); diff --git a/tests/functional/src/lt_test_rev_get_info_req_app.c b/tests/functional/src/lt_test_rev_get_info_req_app.c index 8c9ce76e9..687d02d77 100644 --- a/tests/functional/src/lt_test_rev_get_info_req_app.c +++ b/tests/functional/src/lt_test_rev_get_info_req_app.c @@ -27,8 +27,9 @@ void lt_test_rev_get_info_req_app(lt_handle_t *h) uint8_t cert1[CERTS_BUF_LEN] = {0}, cert2[CERTS_BUF_LEN] = {0}, cert3[CERTS_BUF_LEN] = {0}, cert4[CERTS_BUF_LEN] = {0}, riscv_ver[TR01_L2_GET_INFO_RISCV_FW_SIZE], spect_ver[TR01_L2_GET_INFO_SPECT_FW_SIZE]; - struct lt_cert_store_t store = {.certs = {cert1, cert2, cert3, cert4}, - .buf_len = {CERTS_BUF_LEN, CERTS_BUF_LEN, CERTS_BUF_LEN, CERTS_BUF_LEN}}; + struct lt_cert_store_t store = { + .certs = {cert1, cert2, cert3, cert4}, + .buf_len = {CERTS_BUF_LEN, CERTS_BUF_LEN, CERTS_BUF_LEN, CERTS_BUF_LEN}}; struct lt_chip_id_t chip_id = {0}; LT_LOG_INFO("Initializing handle"); @@ -46,12 +47,14 @@ void lt_test_rev_get_info_req_app(lt_handle_t *h) LT_TEST_ASSERT(1, (store.cert_len[i] != 0)); LT_LOG_INFO("Size in bytes: %" PRIu16, store.cert_len[i]); - for (int j = 0; j < store.cert_len[i]; j += 16) - LT_LOG_INFO("%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 - "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8, - cert[j], cert[j + 1], cert[j + 2], cert[j + 3], cert[j + 4], cert[j + 5], cert[j + 6], - cert[j + 7], cert[j + 8], cert[j + 9], cert[j + 10], cert[j + 11], cert[j + 12], cert[j + 13], - cert[j + 14], cert[j + 15]); + for (int j = 0; j < store.cert_len[i]; j += 16) { + LT_LOG_INFO("%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 + "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 + "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8, + cert[j], cert[j + 1], cert[j + 2], cert[j + 3], cert[j + 4], cert[j + 5], + cert[j + 6], cert[j + 7], cert[j + 8], cert[j + 9], cert[j + 10], cert[j + 11], + cert[j + 12], cert[j + 13], cert[j + 14], cert[j + 15]); + } LT_LOG_INFO(); } LT_LOG_LINE(); @@ -63,14 +66,14 @@ void lt_test_rev_get_info_req_app(lt_handle_t *h) LT_LOG_INFO("Reading RISC-V FW version..."); LT_TEST_ASSERT(LT_OK, lt_get_info_riscv_fw_ver(h, riscv_ver)); - LT_LOG_INFO("RISC-V FW version: v%" PRIu8 ".%" PRIu8 ".%" PRIu8 ".%" PRIu8 "", riscv_ver[3], riscv_ver[2], - riscv_ver[1], riscv_ver[0]); + LT_LOG_INFO("RISC-V FW version: v%" PRIu8 ".%" PRIu8 ".%" PRIu8 ".%" PRIu8 "", riscv_ver[3], + riscv_ver[2], riscv_ver[1], riscv_ver[0]); LT_LOG_LINE(); LT_LOG_INFO("Reading SPECT FW version..."); LT_TEST_ASSERT(LT_OK, lt_get_info_spect_fw_ver(h, spect_ver)); - LT_LOG_INFO("SPECT FW version: v%" PRIu8 ".%" PRIu8 ".%" PRIu8 ".%" PRIu8 "", spect_ver[3], spect_ver[2], - spect_ver[1], spect_ver[0]); + LT_LOG_INFO("SPECT FW version: v%" PRIu8 ".%" PRIu8 ".%" PRIu8 ".%" PRIu8 "", spect_ver[3], + spect_ver[2], spect_ver[1], spect_ver[0]); LT_LOG_INFO("Checking if SPECT FW version is not dummy..."); LT_TEST_ASSERT(1, (memcmp(spect_ver, "\x00\x00\x00\x80", sizeof(spect_ver)) != 0)); LT_LOG_LINE(); diff --git a/tests/functional/src/lt_test_rev_get_info_req_bootloader.c b/tests/functional/src/lt_test_rev_get_info_req_bootloader.c index 95f29f71e..ee2372fb4 100644 --- a/tests/functional/src/lt_test_rev_get_info_req_bootloader.c +++ b/tests/functional/src/lt_test_rev_get_info_req_bootloader.c @@ -28,16 +28,16 @@ static void print_fw_header_bootloader_v1_0_1(uint8_t *header, uint16_t header_s struct lt_header_boot_v1_t *p_h = (struct lt_header_boot_v1_t *)header; - LT_LOG_INFO("Type: 0x%02" PRIX8 "%02" PRIX8 "%02" PRIX8 "%02" PRIX8, p_h->type[3], p_h->type[2], p_h->type[1], - p_h->type[0]); - LT_LOG_INFO("Version: 0x%02" PRIX8 "%02" PRIX8 "%02" PRIX8 "%02" PRIX8, p_h->version[3], p_h->version[2], - p_h->version[1], p_h->version[0]); - LT_LOG_INFO("Size: 0x%02" PRIX8 "%02" PRIX8 "%02" PRIX8 "%02" PRIX8, p_h->size[3], p_h->size[2], p_h->size[1], - p_h->size[0]); - LT_LOG_INFO("Git hash: 0x%02" PRIX8 "%02" PRIX8 "%02" PRIX8 "%02" PRIX8, p_h->git_hash[3], p_h->git_hash[2], - p_h->git_hash[1], p_h->git_hash[0]); - LT_LOG_INFO("FW hash: 0x%02" PRIX8 "%02" PRIX8 "%02" PRIX8 "%02" PRIX8, p_h->hash[3], p_h->hash[2], p_h->hash[1], - p_h->hash[0]); + LT_LOG_INFO("Type: 0x%02" PRIX8 "%02" PRIX8 "%02" PRIX8 "%02" PRIX8, p_h->type[3], + p_h->type[2], p_h->type[1], p_h->type[0]); + LT_LOG_INFO("Version: 0x%02" PRIX8 "%02" PRIX8 "%02" PRIX8 "%02" PRIX8, p_h->version[3], + p_h->version[2], p_h->version[1], p_h->version[0]); + LT_LOG_INFO("Size: 0x%02" PRIX8 "%02" PRIX8 "%02" PRIX8 "%02" PRIX8, p_h->size[3], + p_h->size[2], p_h->size[1], p_h->size[0]); + LT_LOG_INFO("Git hash: 0x%02" PRIX8 "%02" PRIX8 "%02" PRIX8 "%02" PRIX8, p_h->git_hash[3], + p_h->git_hash[2], p_h->git_hash[1], p_h->git_hash[0]); + LT_LOG_INFO("FW hash: 0x%02" PRIX8 "%02" PRIX8 "%02" PRIX8 "%02" PRIX8, p_h->hash[3], + p_h->hash[2], p_h->hash[1], p_h->hash[0]); } static void print_fw_header_bootloader_v2_0_1(uint8_t *header, uint16_t header_size) @@ -53,8 +53,8 @@ static void print_fw_header_bootloader_v2_0_1(uint8_t *header, uint16_t header_s char hash_str[BOOTLOADER_V2_0_1_HASH_PRINT_BUFF_SIZE]; LT_LOG_INFO("Calling lt_print_bytes()..."); - LT_TEST_ASSERT(LT_OK, - lt_print_bytes(p_h->hash, sizeof(p_h->hash), hash_str, BOOTLOADER_V2_0_1_HASH_PRINT_BUFF_SIZE)); + LT_TEST_ASSERT(LT_OK, lt_print_bytes(p_h->hash, sizeof(p_h->hash), hash_str, + BOOTLOADER_V2_0_1_HASH_PRINT_BUFF_SIZE)); LT_LOG_INFO("Type: 0x%04" PRIX16, p_h->type); LT_LOG_INFO("Padding: 0x%02" PRIX8, p_h->padding); @@ -72,24 +72,26 @@ static void read_fw_banks_bootloader_v1_0_1(void) uint16_t read_header_size; LT_LOG_INFO("Reading FW bank %d...", (int)TR01_FW_BANK_FW1); - LT_TEST_ASSERT(LT_OK, lt_get_info_fw_bank(g_h, TR01_FW_BANK_FW1, fw_header, sizeof(fw_header), &read_header_size)); + LT_TEST_ASSERT(LT_OK, lt_get_info_fw_bank(g_h, TR01_FW_BANK_FW1, fw_header, sizeof(fw_header), + &read_header_size)); print_fw_header_bootloader_v1_0_1(fw_header, read_header_size); LT_LOG_INFO(); LT_LOG_INFO("Reading FW bank %d...", (int)TR01_FW_BANK_FW2); - LT_TEST_ASSERT(LT_OK, lt_get_info_fw_bank(g_h, TR01_FW_BANK_FW2, fw_header, sizeof(fw_header), &read_header_size)); + LT_TEST_ASSERT(LT_OK, lt_get_info_fw_bank(g_h, TR01_FW_BANK_FW2, fw_header, sizeof(fw_header), + &read_header_size)); print_fw_header_bootloader_v1_0_1(fw_header, read_header_size); LT_LOG_INFO(); LT_LOG_INFO("Reading SPECT bank %d...", (int)TR01_FW_BANK_SPECT1); - LT_TEST_ASSERT(LT_OK, - lt_get_info_fw_bank(g_h, TR01_FW_BANK_SPECT1, fw_header, sizeof(fw_header), &read_header_size)); + LT_TEST_ASSERT(LT_OK, lt_get_info_fw_bank(g_h, TR01_FW_BANK_SPECT1, fw_header, sizeof(fw_header), + &read_header_size)); print_fw_header_bootloader_v1_0_1(fw_header, read_header_size); LT_LOG_INFO(); LT_LOG_INFO("Reading SPECT bank %d...", (int)TR01_FW_BANK_SPECT2); - LT_TEST_ASSERT(LT_OK, - lt_get_info_fw_bank(g_h, TR01_FW_BANK_SPECT2, fw_header, sizeof(fw_header), &read_header_size)); + LT_TEST_ASSERT(LT_OK, lt_get_info_fw_bank(g_h, TR01_FW_BANK_SPECT2, fw_header, sizeof(fw_header), + &read_header_size)); print_fw_header_bootloader_v1_0_1(fw_header, read_header_size); LT_LOG_INFO(); } @@ -100,24 +102,26 @@ static void read_fw_banks_bootloader_v2_0_1(void) uint16_t read_header_size; LT_LOG_INFO("Reading FW bank %d...", (int)TR01_FW_BANK_FW1); - LT_TEST_ASSERT(LT_OK, lt_get_info_fw_bank(g_h, TR01_FW_BANK_FW1, fw_header, sizeof(fw_header), &read_header_size)); + LT_TEST_ASSERT(LT_OK, lt_get_info_fw_bank(g_h, TR01_FW_BANK_FW1, fw_header, sizeof(fw_header), + &read_header_size)); print_fw_header_bootloader_v2_0_1(fw_header, read_header_size); LT_LOG_INFO(); LT_LOG_INFO("Reading FW bank %d...", (int)TR01_FW_BANK_FW2); - LT_TEST_ASSERT(LT_OK, lt_get_info_fw_bank(g_h, TR01_FW_BANK_FW2, fw_header, sizeof(fw_header), &read_header_size)); + LT_TEST_ASSERT(LT_OK, lt_get_info_fw_bank(g_h, TR01_FW_BANK_FW2, fw_header, sizeof(fw_header), + &read_header_size)); print_fw_header_bootloader_v2_0_1(fw_header, read_header_size); LT_LOG_INFO(); LT_LOG_INFO("Reading SPECT bank %d...", (int)TR01_FW_BANK_SPECT1); - LT_TEST_ASSERT(LT_OK, - lt_get_info_fw_bank(g_h, TR01_FW_BANK_SPECT1, fw_header, sizeof(fw_header), &read_header_size)); + LT_TEST_ASSERT(LT_OK, lt_get_info_fw_bank(g_h, TR01_FW_BANK_SPECT1, fw_header, sizeof(fw_header), + &read_header_size)); print_fw_header_bootloader_v2_0_1(fw_header, read_header_size); LT_LOG_INFO(); LT_LOG_INFO("Reading SPECT bank %d...", (int)TR01_FW_BANK_SPECT2); - LT_TEST_ASSERT(LT_OK, - lt_get_info_fw_bank(g_h, TR01_FW_BANK_SPECT2, fw_header, sizeof(fw_header), &read_header_size)); + LT_TEST_ASSERT(LT_OK, lt_get_info_fw_bank(g_h, TR01_FW_BANK_SPECT2, fw_header, sizeof(fw_header), + &read_header_size)); print_fw_header_bootloader_v2_0_1(fw_header, read_header_size); LT_LOG_INFO(); } @@ -153,8 +157,9 @@ void lt_test_rev_get_info_req_bootloader(lt_handle_t *h) #ifdef ACAB uint8_t cert1[CERTS_BUF_LEN] = {0}, cert2[CERTS_BUF_LEN] = {0}, cert3[CERTS_BUF_LEN] = {0}, cert4[CERTS_BUF_LEN] = {0}; - struct lt_cert_store_t store = {.certs = {cert1, cert2, cert3, cert4}, - .buf_len = {CERTS_BUF_LEN, CERTS_BUF_LEN, CERTS_BUF_LEN, CERTS_BUF_LEN}}; + struct lt_cert_store_t store = { + .certs = {cert1, cert2, cert3, cert4}, + .buf_len = {CERTS_BUF_LEN, CERTS_BUF_LEN, CERTS_BUF_LEN, CERTS_BUF_LEN}}; #endif uint8_t riscv_ver[TR01_L2_GET_INFO_RISCV_FW_SIZE], spect_ver[TR01_L2_GET_INFO_SPECT_FW_SIZE]; struct lt_chip_id_t chip_id = {0}; @@ -180,12 +185,14 @@ void lt_test_rev_get_info_req_bootloader(lt_handle_t *h) LT_TEST_ASSERT(1, (store.cert_len[i] != 0)); LT_LOG_INFO("Size in bytes: %" PRIu16, store.cert_len[i]); - for (int j = 0; j < store.cert_len[i]; j += 16) - LT_LOG_INFO("%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 - "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8, - cert[j], cert[j + 1], cert[j + 2], cert[j + 3], cert[j + 4], cert[j + 5], cert[j + 6], - cert[j + 7], cert[j + 8], cert[j + 9], cert[j + 10], cert[j + 11], cert[j + 12], cert[j + 13], - cert[j + 14], cert[j + 15]); + for (int j = 0; j < store.cert_len[i]; j += 16) { + LT_LOG_INFO("%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 + "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 + "%02" PRIx8 "%02" PRIx8 "%02" PRIx8 "%02" PRIx8, + cert[j], cert[j + 1], cert[j + 2], cert[j + 3], cert[j + 4], cert[j + 5], + cert[j + 6], cert[j + 7], cert[j + 8], cert[j + 9], cert[j + 10], cert[j + 11], + cert[j + 12], cert[j + 13], cert[j + 14], cert[j + 15]); + } LT_LOG_INFO(); } LT_LOG_LINE(); @@ -201,24 +208,26 @@ void lt_test_rev_get_info_req_bootloader(lt_handle_t *h) LT_LOG_INFO("Reading RISC-V bootloader version..."); LT_TEST_ASSERT(LT_OK, lt_get_info_riscv_fw_ver(h, riscv_ver)); - LT_LOG_INFO("RISC-V Bootloader version: v%" PRIu8 ".%" PRIu8 ".%" PRIu8 "(.%" PRIu8 ")", riscv_ver[3] & 0x7f, - riscv_ver[2], riscv_ver[1], riscv_ver[0]); + LT_LOG_INFO("RISC-V Bootloader version: v%" PRIu8 ".%" PRIu8 ".%" PRIu8 "(.%" PRIu8 ")", + riscv_ver[3] & 0x7f, riscv_ver[2], riscv_ver[1], riscv_ver[0]); LT_LOG_LINE(); LT_LOG_INFO("Reading SPECT bootloader version (should be dummy)..."); LT_TEST_ASSERT(LT_OK, lt_get_info_spect_fw_ver(h, spect_ver)); - LT_LOG_INFO("SPECT Bootloader version: v%" PRIu8 ".%" PRIu8 ".%" PRIu8 ".%" PRIu8 "", spect_ver[3], spect_ver[2], - spect_ver[1], spect_ver[0]); + LT_LOG_INFO("SPECT Bootloader version: v%" PRIu8 ".%" PRIu8 ".%" PRIu8 ".%" PRIu8 "", spect_ver[3], + spect_ver[2], spect_ver[1], spect_ver[0]); LT_LOG_INFO("Checking SPECT bootloader version dummy value..."); LT_TEST_ASSERT(0, memcmp(spect_ver, "\x00\x00\x00\x80", sizeof(spect_ver))); LT_LOG_LINE(); // Bootloader version 1.0.1 (ABAB) - if (((riscv_ver[3] & 0x7f) == 1) && (riscv_ver[2] == 0) && (riscv_ver[1] == 1) && (riscv_ver[0] == 0)) { + if (((riscv_ver[3] & 0x7f) == 1) && (riscv_ver[2] == 0) && (riscv_ver[1] == 1) && + (riscv_ver[0] == 0)) { read_fw_banks_bootloader_v1_0_1(); } // Bootloader version 2.0.1 (ACAB) - else if (((riscv_ver[3] & 0x7f) == 2) && (riscv_ver[2] == 0) && (riscv_ver[1] == 1) && (riscv_ver[0] == 0)) { + else if (((riscv_ver[3] & 0x7f) == 2) && (riscv_ver[2] == 0) && (riscv_ver[1] == 1) && + (riscv_ver[0] == 0)) { read_fw_banks_bootloader_v2_0_1(); } else { diff --git a/tests/functional/src/lt_test_rev_get_log_req.c b/tests/functional/src/lt_test_rev_get_log_req.c index abd931bd0..a5ab6bfd6 100644 --- a/tests/functional/src/lt_test_rev_get_log_req.c +++ b/tests/functional/src/lt_test_rev_get_log_req.c @@ -23,12 +23,12 @@ static void lt_test_rev_get_log_req_body(uint32_t i_config_cfg_debug, uint32_t r { uint8_t log_msg[TR01_GET_LOG_MAX_MSG_LEN + 1]; // +1 for '\0' added later uint16_t log_msg_read_size; - int fw_log_en = (i_config_cfg_debug & BOOTLOADER_CO_CFG_DEBUG_FW_LOG_EN_MASK) - && (r_config_cfg_debug & BOOTLOADER_CO_CFG_DEBUG_FW_LOG_EN_MASK); + int fw_log_en = (i_config_cfg_debug & BOOTLOADER_CO_CFG_DEBUG_FW_LOG_EN_MASK) && + (r_config_cfg_debug & BOOTLOADER_CO_CFG_DEBUG_FW_LOG_EN_MASK); LT_LOG_INFO("Getting RISC-V FW log..."); - LT_TEST_ASSERT_COND(lt_get_log_req(g_h, log_msg, TR01_GET_LOG_MAX_MSG_LEN, &log_msg_read_size), fw_log_en, LT_OK, - LT_L2_RESP_DISABLED); + LT_TEST_ASSERT_COND(lt_get_log_req(g_h, log_msg, TR01_GET_LOG_MAX_MSG_LEN, &log_msg_read_size), + fw_log_en, LT_OK, LT_L2_RESP_DISABLED); if (fw_log_en) { if (log_msg_read_size) { @@ -42,8 +42,10 @@ static void lt_test_rev_get_log_req_body(uint32_t i_config_cfg_debug, uint32_t r } else { LT_LOG_INFO("RISC-V FW logging is disabled:"); - LT_LOG_INFO("I config FW_LOG_EN=%d", (int)i_config_cfg_debug & BOOTLOADER_CO_CFG_DEBUG_FW_LOG_EN_MASK); - LT_LOG_INFO("R config FW_LOG_EN=%d", (int)r_config_cfg_debug & BOOTLOADER_CO_CFG_DEBUG_FW_LOG_EN_MASK); + LT_LOG_INFO("I config FW_LOG_EN=%d", + (int)i_config_cfg_debug & BOOTLOADER_CO_CFG_DEBUG_FW_LOG_EN_MASK); + LT_LOG_INFO("R config FW_LOG_EN=%d", + (int)r_config_cfg_debug & BOOTLOADER_CO_CFG_DEBUG_FW_LOG_EN_MASK); } } @@ -85,8 +87,8 @@ void lt_test_rev_get_log_req(lt_handle_t *h) LT_TEST_ASSERT(LT_OK, lt_reboot(h, TR01_REBOOT)); LT_LOG_INFO("Starting Secure Session with key %d", (int)TR01_PAIRING_KEY_SLOT_INDEX_0); - LT_TEST_ASSERT(LT_OK, lt_verify_chip_and_start_secure_session(g_h, LT_TEST_SH0_PRIV, LT_TEST_SH0_PUB, - TR01_PAIRING_KEY_SLOT_INDEX_0)); + LT_TEST_ASSERT(LT_OK, lt_verify_chip_and_start_secure_session( + g_h, LT_TEST_SH0_PRIV, LT_TEST_SH0_PUB, TR01_PAIRING_KEY_SLOT_INDEX_0)); LT_LOG_INFO("Reading CFG_DEBUG from I config..."); LT_TEST_ASSERT(LT_OK, lt_i_config_read(g_h, TR01_CFG_DEBUG_ADDR, &i_config_cfg_debug)); diff --git a/tests/functional/src/lt_test_rev_handshake_req.c b/tests/functional/src/lt_test_rev_handshake_req.c index 7502f4156..edcdb5f64 100644 --- a/tests/functional/src/lt_test_rev_handshake_req.c +++ b/tests/functional/src/lt_test_rev_handshake_req.c @@ -31,8 +31,9 @@ void lt_test_rev_handshake_req(lt_handle_t *h) LT_LOG_INFO("Part 2/3: Start Secure Session multiple times without aborting."); for (int i = 0; i < 3; i++) { LT_LOG_INFO("Starting Secure Session (attempt %d)...", i); - LT_TEST_ASSERT(LT_OK, lt_verify_chip_and_start_secure_session(h, LT_TEST_SH0_PRIV, LT_TEST_SH0_PUB, - TR01_PAIRING_KEY_SLOT_INDEX_0)); + LT_TEST_ASSERT(LT_OK, + lt_verify_chip_and_start_secure_session(h, LT_TEST_SH0_PRIV, LT_TEST_SH0_PUB, + TR01_PAIRING_KEY_SLOT_INDEX_0)); } LT_LOG_INFO("Part 3/3: Abort Secure Session multiple times."); diff --git a/tests/functional/src/lt_test_rev_init_after_deinit.c b/tests/functional/src/lt_test_rev_init_after_deinit.c new file mode 100644 index 000000000..be10c5afc --- /dev/null +++ b/tests/functional/src/lt_test_rev_init_after_deinit.c @@ -0,0 +1,60 @@ +/** + * @file lt_test_rev_init_after_deinit.c + * @brief Test calling lt_init after lt_deinit. + * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. + * + * @license For the license see LICENSE.md in the root directory of this source tree. + */ + +#include +#include + +#include "libtropic.h" +#include "libtropic_common.h" +#include "libtropic_functional_tests.h" +#include "libtropic_logging.h" +#include "lt_port_wrap.h" +#include "lt_test_common.h" + +void lt_test_rev_init_after_deinit(lt_handle_t *h) +{ + LT_LOG_INFO("----------------------------------------------"); + LT_LOG_INFO("lt_test_rev_init_after_deinit()"); + LT_LOG_INFO("----------------------------------------------"); + + uint8_t ping_msg_out[TR01_PING_LEN_MAX], ping_msg_in[TR01_PING_LEN_MAX]; + uint16_t ping_msg_len; + + for (int i = 0; i < 2; i++) { + LT_LOG_INFO("Iteration #%d", i + 1); + + LT_LOG_INFO("Initializing handle"); + LT_TEST_ASSERT(LT_OK, lt_init(h)); + + LT_LOG_INFO("Starting Secure Session with key %d", (int)TR01_PAIRING_KEY_SLOT_INDEX_0); + LT_TEST_ASSERT(LT_OK, + lt_verify_chip_and_start_secure_session(h, LT_TEST_SH0_PRIV, LT_TEST_SH0_PUB, + TR01_PAIRING_KEY_SLOT_INDEX_0)); + + LT_LOG_INFO("Generating random data length <= %d...", (int)TR01_PING_LEN_MAX); + LT_TEST_ASSERT(LT_OK, lt_random_bytes(h, &ping_msg_len, sizeof(ping_msg_len))); + ping_msg_len %= TR01_PING_LEN_MAX + 1; // 0-4096 + + LT_LOG_INFO("Generating %" PRIu16 " random bytes...", ping_msg_len); + LT_TEST_ASSERT(LT_OK, lt_random_bytes(h, ping_msg_out, ping_msg_len)); + + LT_LOG_INFO("Sending Ping command..."); + LT_TEST_ASSERT(LT_OK, lt_ping(h, ping_msg_out, ping_msg_in, ping_msg_len)); + + LT_LOG_INFO("Comparing sent and received message..."); + LT_TEST_ASSERT(0, memcmp(ping_msg_out, ping_msg_in, ping_msg_len)); + + LT_LOG_INFO("Aborting Secure Session..."); + LT_TEST_ASSERT(LT_OK, lt_session_abort(h)); + + LT_LOG_INFO("Deinitializing handle"); + LT_TEST_ASSERT(LT_OK, lt_deinit(h)); + + LT_LOG_LINE(); + } +} diff --git a/tests/functional/src/lt_test_rev_mac_and_destroy.c b/tests/functional/src/lt_test_rev_mac_and_destroy.c index 03be0ef7b..998cf12fa 100644 --- a/tests/functional/src/lt_test_rev_mac_and_destroy.c +++ b/tests/functional/src/lt_test_rev_mac_and_destroy.c @@ -25,8 +25,8 @@ static int pin_check(lt_handle_t *h, uint8_t *pin, uint16_t pin_len, lt_mac_and_ uint8_t ciphertexts[TR01_MACANDD_ROUNDS_MAX][TR01_MAC_AND_DESTROY_DATA_SIZE], uint8_t t[LT_HMAC_SHA256_HASH_LEN], uint8_t s[TR01_MAC_AND_DESTROY_DATA_SIZE]) { - uint8_t v[LT_HMAC_SHA256_HASH_LEN], w[TR01_MAC_AND_DESTROY_DATA_SIZE], k_i[LT_HMAC_SHA256_HASH_LEN], - t_[LT_HMAC_SHA256_HASH_LEN]; + uint8_t v[LT_HMAC_SHA256_HASH_LEN], w[TR01_MAC_AND_DESTROY_DATA_SIZE], + k_i[LT_HMAC_SHA256_HASH_LEN], t_[LT_HMAC_SHA256_HASH_LEN]; LT_LOG_INFO("Computing v = KDF(0, PIN_DATA)..."); LT_TEST_ASSERT(LT_OK, lt_hmac_sha256(kdf_key_zeros, sizeof(kdf_key_zeros), pin, pin_len, v)); @@ -38,14 +38,19 @@ static int pin_check(lt_handle_t *h, uint8_t *pin, uint16_t pin_len, lt_mac_and_ LT_TEST_ASSERT(LT_OK, lt_hmac_sha256(w, sizeof(w), pin, pin_len, k_i)); LT_LOG_INFO("Decrypting (XOR) c_i using k_i..."); - for (uint8_t j = 0; j < TR01_MAC_AND_DESTROY_DATA_SIZE; j++) s[j] = ciphertexts[slot][j] ^ k_i[j]; + for (uint8_t j = 0; j < TR01_MAC_AND_DESTROY_DATA_SIZE; j++) { + s[j] = ciphertexts[slot][j] ^ k_i[j]; + } LT_LOG_INFO("Computing t' = KDF(s, \"0\")..."); LT_TEST_ASSERT(LT_OK, lt_hmac_sha256(s, TR01_MAC_AND_DESTROY_DATA_SIZE, (uint8_t *)"0", 1, t_)); LT_LOG_INFO("Checking if t' != t..."); - for (uint8_t i = 0; i < sizeof(t_); i++) - if (t_[i] != t[i]) return 1; + for (uint8_t i = 0; i < sizeof(t_); i++) { + if (t_[i] != t[i]) { + return 1; + } + } return 0; } @@ -58,9 +63,9 @@ void lt_test_rev_mac_and_destroy(lt_handle_t *h) uint8_t n, wrong_attempts, s[TR01_MAC_AND_DESTROY_DATA_SIZE], t[LT_HMAC_SHA256_HASH_LEN], u[LT_HMAC_SHA256_HASH_LEN], v[LT_HMAC_SHA256_HASH_LEN], w[TR01_MAC_AND_DESTROY_DATA_SIZE], - k_from_setup[LT_HMAC_SHA256_HASH_LEN], k_from_check[LT_HMAC_SHA256_HASH_LEN], k_i[LT_HMAC_SHA256_HASH_LEN], - ignored[TR01_MAC_AND_DESTROY_DATA_SIZE], pin[PIN_LEN_MAX], pin_wrong[PIN_LEN_MAX], - ciphertexts[TR01_MACANDD_ROUNDS_MAX][TR01_MAC_AND_DESTROY_DATA_SIZE]; + k_from_setup[LT_HMAC_SHA256_HASH_LEN], k_from_check[LT_HMAC_SHA256_HASH_LEN], + k_i[LT_HMAC_SHA256_HASH_LEN], ignored[TR01_MAC_AND_DESTROY_DATA_SIZE], pin[PIN_LEN_MAX], + pin_wrong[PIN_LEN_MAX], ciphertexts[TR01_MACANDD_ROUNDS_MAX][TR01_MAC_AND_DESTROY_DATA_SIZE]; uint16_t pin_len; LT_LOG_INFO("Initializing handle"); @@ -74,7 +79,8 @@ void lt_test_rev_mac_and_destroy(lt_handle_t *h) LT_LOG_INFO("Setup PIN"); LT_LOG_INFO(); - LT_LOG_INFO("Generating random number of max attempts n from {1...%d}...", (int)TR01_MAC_AND_DESTROY_SLOT_127); + LT_LOG_INFO("Generating random number of max attempts n from {1...%d}...", + (int)TR01_MAC_AND_DESTROY_SLOT_127); LT_TEST_ASSERT(LT_OK, lt_random_bytes(h, &n, sizeof(n))); n = (n % TR01_MAC_AND_DESTROY_SLOT_127) + 1; diff --git a/tests/functional/src/lt_test_rev_mcounter.c b/tests/functional/src/lt_test_rev_mcounter.c index 230ee3459..d1f6aad3c 100644 --- a/tests/functional/src/lt_test_rev_mcounter.c +++ b/tests/functional/src/lt_test_rev_mcounter.c @@ -89,16 +89,17 @@ void lt_test_rev_mcounter(lt_handle_t *h) LT_LOG_INFO("Generating random init value..."); LT_TEST_ASSERT(LT_OK, lt_random_bytes(h, &init_val, sizeof(init_val))); LT_LOG_INFO("Initializing monotonic counter %d with %" PRIu32 "...", i, init_val); - LT_TEST_ASSERT_COND(lt_mcounter_init(h, i, init_val), (init_val <= TR01_MCOUNTER_VALUE_MAX), LT_OK, - LT_PARAM_ERR); + LT_TEST_ASSERT_COND(lt_mcounter_init(h, i, init_val), (init_val <= TR01_MCOUNTER_VALUE_MAX), + LT_OK, LT_PARAM_ERR); LT_LOG_INFO("Initializing monotonic counter %d again (should be ok)...", i); - LT_TEST_ASSERT_COND(lt_mcounter_init(h, i, init_val), (init_val <= TR01_MCOUNTER_VALUE_MAX), LT_OK, - LT_PARAM_ERR); + LT_TEST_ASSERT_COND(lt_mcounter_init(h, i, init_val), (init_val <= TR01_MCOUNTER_VALUE_MAX), + LT_OK, LT_PARAM_ERR); LT_LOG_INFO("Trying a few decrements..."); current_decrements = 0; - for (int expected_val = init_val; expected_val > 0 && current_decrements < max_decrements; expected_val--) { + for (int expected_val = init_val; expected_val > 0 && current_decrements < max_decrements; + expected_val--) { LT_LOG_INFO("Reading mcounter %d value...", i); LT_TEST_ASSERT(LT_OK, lt_mcounter_get(h, i, &mcounter_val)); LT_LOG_INFO("Verifying mcounter value, should be: %d", expected_val); diff --git a/tests/functional/src/lt_test_rev_param_check.c b/tests/functional/src/lt_test_rev_param_check.c index a0256221c..07a5537ca 100644 --- a/tests/functional/src/lt_test_rev_param_check.c +++ b/tests/functional/src/lt_test_rev_param_check.c @@ -70,29 +70,32 @@ void lt_test_rev_param_check(lt_handle_t *h) uint8_t dummy_header[1]; uint16_t dummy_size = 0; + LT_TEST_ASSERT(LT_PARAM_ERR, lt_get_info_fw_bank(NULL, TR01_FW_BANK_FW1, dummy_header, + sizeof(dummy_header), &dummy_size)); LT_TEST_ASSERT(LT_PARAM_ERR, - lt_get_info_fw_bank(NULL, TR01_FW_BANK_FW1, dummy_header, sizeof(dummy_header), &dummy_size)); - LT_TEST_ASSERT(LT_PARAM_ERR, lt_get_info_fw_bank(h, 0xFF, dummy_header, sizeof(dummy_header), &dummy_size)); - LT_TEST_ASSERT(LT_PARAM_ERR, lt_get_info_fw_bank(h, TR01_FW_BANK_FW1, NULL, sizeof(dummy_header), &dummy_size)); - LT_TEST_ASSERT(LT_PARAM_ERR, - lt_get_info_fw_bank(h, TR01_FW_BANK_FW1, dummy_header, sizeof(dummy_header), NULL)); + lt_get_info_fw_bank(h, 0xFF, dummy_header, sizeof(dummy_header), &dummy_size)); + LT_TEST_ASSERT(LT_PARAM_ERR, lt_get_info_fw_bank(h, TR01_FW_BANK_FW1, NULL, + sizeof(dummy_header), &dummy_size)); + LT_TEST_ASSERT(LT_PARAM_ERR, lt_get_info_fw_bank(h, TR01_FW_BANK_FW1, dummy_header, + sizeof(dummy_header), NULL)); } - LT_TEST_ASSERT(LT_PARAM_ERR, lt_session_start(NULL, (const uint8_t *)1, TR01_PAIRING_KEY_SLOT_INDEX_0, - (const uint8_t *)1, (const uint8_t *)1)); - - LT_TEST_ASSERT(LT_PARAM_ERR, - lt_session_start(h, NULL, TR01_PAIRING_KEY_SLOT_INDEX_0, (const uint8_t *)1, (const uint8_t *)1)); - LT_TEST_ASSERT(LT_PARAM_ERR, - lt_session_start(h, (const uint8_t *)1, (lt_pkey_index_t)(TR01_PAIRING_KEY_SLOT_INDEX_3 + 1), + lt_session_start(NULL, (const uint8_t *)1, TR01_PAIRING_KEY_SLOT_INDEX_0, (const uint8_t *)1, (const uint8_t *)1)); - LT_TEST_ASSERT(LT_PARAM_ERR, - lt_session_start(h, (const uint8_t *)1, TR01_PAIRING_KEY_SLOT_INDEX_0, NULL, (const uint8_t *)1)); + LT_TEST_ASSERT(LT_PARAM_ERR, lt_session_start(h, NULL, TR01_PAIRING_KEY_SLOT_INDEX_0, + (const uint8_t *)1, (const uint8_t *)1)); - LT_TEST_ASSERT(LT_PARAM_ERR, - lt_session_start(h, (const uint8_t *)1, TR01_PAIRING_KEY_SLOT_INDEX_0, (const uint8_t *)1, NULL)); + LT_TEST_ASSERT(LT_PARAM_ERR, lt_session_start(h, (const uint8_t *)1, + (lt_pkey_index_t)(TR01_PAIRING_KEY_SLOT_INDEX_3 + 1), + (const uint8_t *)1, (const uint8_t *)1)); + + LT_TEST_ASSERT(LT_PARAM_ERR, lt_session_start(h, (const uint8_t *)1, TR01_PAIRING_KEY_SLOT_INDEX_0, + NULL, (const uint8_t *)1)); + + LT_TEST_ASSERT(LT_PARAM_ERR, lt_session_start(h, (const uint8_t *)1, TR01_PAIRING_KEY_SLOT_INDEX_0, + (const uint8_t *)1, NULL)); LT_TEST_ASSERT(LT_PARAM_ERR, lt_session_abort(NULL)); @@ -157,15 +160,15 @@ void lt_test_rev_param_check(lt_handle_t *h) { uint8_t data[TR01_R_MEM_DATA_SIZE_MIN]; LT_TEST_ASSERT(LT_PARAM_ERR, lt_r_mem_data_write(NULL, 0, data, sizeof(data))); - LT_TEST_ASSERT(LT_PARAM_ERR, - lt_r_mem_data_write(h, (uint16_t)(TR01_R_MEM_DATA_SLOT_MAX + 1), data, sizeof(data))); + LT_TEST_ASSERT(LT_PARAM_ERR, lt_r_mem_data_write(h, (uint16_t)(TR01_R_MEM_DATA_SLOT_MAX + 1), + data, sizeof(data))); LT_TEST_ASSERT(LT_PARAM_ERR, lt_r_mem_data_write(h, 0, NULL, sizeof(data))); LT_TEST_ASSERT(LT_PARAM_ERR, lt_r_mem_data_write(h, 0, data, 0)); uint16_t data_read_size; LT_TEST_ASSERT(LT_PARAM_ERR, lt_r_mem_data_read(NULL, 0, data, sizeof(data), &data_read_size)); - LT_TEST_ASSERT(LT_PARAM_ERR, lt_r_mem_data_read(h, (uint16_t)(TR01_R_MEM_DATA_SLOT_MAX + 1), data, sizeof(data), - &data_read_size)); + LT_TEST_ASSERT(LT_PARAM_ERR, lt_r_mem_data_read(h, (uint16_t)(TR01_R_MEM_DATA_SLOT_MAX + 1), + data, sizeof(data), &data_read_size)); LT_TEST_ASSERT(LT_PARAM_ERR, lt_r_mem_data_read(h, 0, NULL, sizeof(data), &data_read_size)); LT_TEST_ASSERT(LT_PARAM_ERR, lt_r_mem_data_read(h, 0, data, sizeof(data), NULL)); @@ -177,19 +180,22 @@ void lt_test_rev_param_check(lt_handle_t *h) uint8_t buf[1]; LT_TEST_ASSERT(LT_PARAM_ERR, lt_random_value_get(NULL, buf, sizeof(buf))); LT_TEST_ASSERT(LT_PARAM_ERR, lt_random_value_get(h, NULL, sizeof(buf))); - LT_TEST_ASSERT(LT_PARAM_ERR, lt_random_value_get(h, buf, (uint16_t)(TR01_RANDOM_VALUE_GET_LEN_MAX + 1))); + LT_TEST_ASSERT(LT_PARAM_ERR, + lt_random_value_get(h, buf, (uint16_t)(TR01_RANDOM_VALUE_GET_LEN_MAX + 1))); } LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_key_generate(NULL, TR01_ECC_SLOT_0, TR01_CURVE_ED25519)); - LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_key_generate(h, (lt_ecc_slot_t)(TR01_ECC_SLOT_31 + 1), TR01_CURVE_ED25519)); + LT_TEST_ASSERT(LT_PARAM_ERR, + lt_ecc_key_generate(h, (lt_ecc_slot_t)(TR01_ECC_SLOT_31 + 1), TR01_CURVE_ED25519)); LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_key_generate(h, TR01_ECC_SLOT_0, 0xFF)); { uint8_t key[32]; LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_key_store(NULL, TR01_ECC_SLOT_0, TR01_CURVE_ED25519, key)); + LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_key_store(h, (lt_ecc_slot_t)(TR01_ECC_SLOT_31 + 1), + TR01_CURVE_ED25519, key)); LT_TEST_ASSERT(LT_PARAM_ERR, - lt_ecc_key_store(h, (lt_ecc_slot_t)(TR01_ECC_SLOT_31 + 1), TR01_CURVE_ED25519, key)); - LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_key_store(h, TR01_ECC_SLOT_0, (lt_ecc_curve_type_t)0xFF, key)); + lt_ecc_key_store(h, TR01_ECC_SLOT_0, (lt_ecc_curve_type_t)0xFF, key)); LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_key_store(h, TR01_ECC_SLOT_0, TR01_CURVE_ED25519, NULL)); } @@ -197,12 +203,16 @@ void lt_test_rev_param_check(lt_handle_t *h) uint8_t key[64]; lt_ecc_curve_type_t curve; lt_ecc_key_origin_t origin; - LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_key_read(NULL, TR01_ECC_SLOT_0, key, sizeof(key), &curve, &origin)); LT_TEST_ASSERT(LT_PARAM_ERR, - lt_ecc_key_read(h, (lt_ecc_slot_t)(TR01_ECC_SLOT_31 + 1), key, sizeof(key), &curve, &origin)); - LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_key_read(h, TR01_ECC_SLOT_0, NULL, sizeof(key), &curve, &origin)); - LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_key_read(h, TR01_ECC_SLOT_0, key, sizeof(key), NULL, &origin)); - LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_key_read(h, TR01_ECC_SLOT_0, key, sizeof(key), &curve, NULL)); + lt_ecc_key_read(NULL, TR01_ECC_SLOT_0, key, sizeof(key), &curve, &origin)); + LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_key_read(h, (lt_ecc_slot_t)(TR01_ECC_SLOT_31 + 1), key, + sizeof(key), &curve, &origin)); + LT_TEST_ASSERT(LT_PARAM_ERR, + lt_ecc_key_read(h, TR01_ECC_SLOT_0, NULL, sizeof(key), &curve, &origin)); + LT_TEST_ASSERT(LT_PARAM_ERR, + lt_ecc_key_read(h, TR01_ECC_SLOT_0, key, sizeof(key), NULL, &origin)); + LT_TEST_ASSERT(LT_PARAM_ERR, + lt_ecc_key_read(h, TR01_ECC_SLOT_0, key, sizeof(key), &curve, NULL)); } LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_key_erase(NULL, TR01_ECC_SLOT_0)); @@ -211,8 +221,8 @@ void lt_test_rev_param_check(lt_handle_t *h) { uint8_t msg[1], sig[64]; LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_ecdsa_sign(NULL, TR01_ECC_SLOT_0, msg, sizeof(msg), sig)); - LT_TEST_ASSERT(LT_PARAM_ERR, - lt_ecc_ecdsa_sign(h, (lt_ecc_slot_t)(TR01_ECC_SLOT_31 + 1), msg, sizeof(msg), sig)); + LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_ecdsa_sign(h, (lt_ecc_slot_t)(TR01_ECC_SLOT_31 + 1), msg, + sizeof(msg), sig)); LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_ecdsa_sign(h, TR01_ECC_SLOT_0, NULL, sizeof(msg), sig)); LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_ecdsa_sign(h, TR01_ECC_SLOT_0, msg, sizeof(msg), NULL)); } @@ -220,38 +230,47 @@ void lt_test_rev_param_check(lt_handle_t *h) { uint8_t msg[1], sig[64]; LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_eddsa_sign(NULL, TR01_ECC_SLOT_0, msg, sizeof(msg), sig)); - LT_TEST_ASSERT(LT_PARAM_ERR, - lt_ecc_eddsa_sign(h, (lt_ecc_slot_t)(TR01_ECC_SLOT_31 + 1), msg, sizeof(msg), sig)); + LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_eddsa_sign(h, (lt_ecc_slot_t)(TR01_ECC_SLOT_31 + 1), msg, + sizeof(msg), sig)); LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_eddsa_sign(h, TR01_ECC_SLOT_0, NULL, sizeof(msg), sig)); - LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_eddsa_sign(h, TR01_ECC_SLOT_0, msg, - (uint16_t)(TR01_L3_EDDSA_SIGN_CMD_MSG_LEN_MAX + 1), sig)); + LT_TEST_ASSERT(LT_PARAM_ERR, + lt_ecc_eddsa_sign(h, TR01_ECC_SLOT_0, msg, + (uint16_t)(TR01_L3_EDDSA_SIGN_CMD_MSG_LEN_MAX + 1), sig)); LT_TEST_ASSERT(LT_PARAM_ERR, lt_ecc_eddsa_sign(h, TR01_ECC_SLOT_0, msg, sizeof(msg), NULL)); } LT_TEST_ASSERT(LT_PARAM_ERR, lt_mcounter_init(NULL, TR01_MCOUNTER_INDEX_0, 0)); - LT_TEST_ASSERT(LT_PARAM_ERR, lt_mcounter_init(h, (enum lt_mcounter_index_t)(TR01_MCOUNTER_INDEX_15 + 1), 0)); - LT_TEST_ASSERT(LT_PARAM_ERR, lt_mcounter_init(h, TR01_MCOUNTER_INDEX_0, TR01_MCOUNTER_VALUE_MAX + 1)); + LT_TEST_ASSERT(LT_PARAM_ERR, + lt_mcounter_init(h, (enum lt_mcounter_index_t)(TR01_MCOUNTER_INDEX_15 + 1), 0)); + LT_TEST_ASSERT(LT_PARAM_ERR, + lt_mcounter_init(h, TR01_MCOUNTER_INDEX_0, TR01_MCOUNTER_VALUE_MAX + 1)); LT_TEST_ASSERT(LT_PARAM_ERR, lt_mcounter_update(NULL, TR01_MCOUNTER_INDEX_0)); - LT_TEST_ASSERT(LT_PARAM_ERR, lt_mcounter_update(h, (enum lt_mcounter_index_t)(TR01_MCOUNTER_INDEX_15 + 1))); + LT_TEST_ASSERT(LT_PARAM_ERR, + lt_mcounter_update(h, (enum lt_mcounter_index_t)(TR01_MCOUNTER_INDEX_15 + 1))); { uint32_t mv; LT_TEST_ASSERT(LT_PARAM_ERR, lt_mcounter_get(NULL, TR01_MCOUNTER_INDEX_0, &mv)); - LT_TEST_ASSERT(LT_PARAM_ERR, lt_mcounter_get(h, (enum lt_mcounter_index_t)(TR01_MCOUNTER_INDEX_15 + 1), &mv)); + LT_TEST_ASSERT( + LT_PARAM_ERR, + lt_mcounter_get(h, (enum lt_mcounter_index_t)(TR01_MCOUNTER_INDEX_15 + 1), &mv)); LT_TEST_ASSERT(LT_PARAM_ERR, lt_mcounter_get(h, TR01_MCOUNTER_INDEX_0, NULL)); } { uint8_t out[1], in[1]; LT_TEST_ASSERT(LT_PARAM_ERR, lt_mac_and_destroy(NULL, TR01_MAC_AND_DESTROY_SLOT_0, out, in)); - LT_TEST_ASSERT(LT_PARAM_ERR, - lt_mac_and_destroy(h, (lt_mac_and_destroy_slot_t)(TR01_MAC_AND_DESTROY_SLOT_127 + 1), out, in)); + LT_TEST_ASSERT( + LT_PARAM_ERR, + lt_mac_and_destroy(h, (lt_mac_and_destroy_slot_t)(TR01_MAC_AND_DESTROY_SLOT_127 + 1), out, + in)); LT_TEST_ASSERT(LT_PARAM_ERR, lt_mac_and_destroy(h, TR01_MAC_AND_DESTROY_SLOT_0, NULL, in)); LT_TEST_ASSERT(LT_PARAM_ERR, lt_mac_and_destroy(h, TR01_MAC_AND_DESTROY_SLOT_0, out, NULL)); } - LT_TEST_ASSERT(0, strcmp(lt_ret_verbose(LT_RET_T_LAST_VALUE), "FATAL ERROR, unknown return value")); + LT_TEST_ASSERT(0, + strcmp(lt_ret_verbose(LT_RET_T_LAST_VALUE), "FATAL ERROR, unknown return value")); // -------------------------------------------------------- // Silicon revision specific functions @@ -262,11 +281,15 @@ void lt_test_rev_param_check(lt_handle_t *h) { uint8_t dummy_data[1]; - LT_TEST_ASSERT(LT_PARAM_ERR, lt_mutable_fw_update(NULL, dummy_data, sizeof(dummy_data), TR01_FW_BANK_FW1)); - LT_TEST_ASSERT(LT_PARAM_ERR, lt_mutable_fw_update(h, NULL, sizeof(dummy_data), TR01_FW_BANK_FW1)); LT_TEST_ASSERT(LT_PARAM_ERR, - lt_mutable_fw_update(h, dummy_data, TR01_MUTABLE_FW_UPDATE_SIZE_MAX + 1, TR01_FW_BANK_FW1)); - LT_TEST_ASSERT(LT_PARAM_ERR, lt_mutable_fw_update(h, dummy_data, sizeof(dummy_data), 0xFFFFFFFF)); + lt_mutable_fw_update(NULL, dummy_data, sizeof(dummy_data), TR01_FW_BANK_FW1)); + LT_TEST_ASSERT(LT_PARAM_ERR, + lt_mutable_fw_update(h, NULL, sizeof(dummy_data), TR01_FW_BANK_FW1)); + LT_TEST_ASSERT(LT_PARAM_ERR, + lt_mutable_fw_update(h, dummy_data, TR01_MUTABLE_FW_UPDATE_SIZE_MAX + 1, + TR01_FW_BANK_FW1)); + LT_TEST_ASSERT(LT_PARAM_ERR, + lt_mutable_fw_update(h, dummy_data, sizeof(dummy_data), 0xFFFFFFFF)); } #elif ACAB { @@ -274,9 +297,12 @@ void lt_test_rev_param_check(lt_handle_t *h) LT_TEST_ASSERT(LT_PARAM_ERR, lt_mutable_fw_update(NULL, dummy_data)); LT_TEST_ASSERT(LT_PARAM_ERR, lt_mutable_fw_update(h, NULL)); - LT_TEST_ASSERT(LT_PARAM_ERR, lt_mutable_fw_update_data(NULL, dummy_data, TR01_L2_MUTABLE_FW_UPDATE_REQ_LEN)); - LT_TEST_ASSERT(LT_PARAM_ERR, lt_mutable_fw_update_data(h, NULL, TR01_L2_MUTABLE_FW_UPDATE_REQ_LEN)); - LT_TEST_ASSERT(LT_PARAM_ERR, lt_mutable_fw_update_data(h, dummy_data, TR01_MUTABLE_FW_UPDATE_SIZE_MAX + 1)); + LT_TEST_ASSERT(LT_PARAM_ERR, + lt_mutable_fw_update_data(NULL, dummy_data, TR01_L2_MUTABLE_FW_UPDATE_REQ_LEN)); + LT_TEST_ASSERT(LT_PARAM_ERR, + lt_mutable_fw_update_data(h, NULL, TR01_L2_MUTABLE_FW_UPDATE_REQ_LEN)); + LT_TEST_ASSERT(LT_PARAM_ERR, + lt_mutable_fw_update_data(h, dummy_data, TR01_MUTABLE_FW_UPDATE_SIZE_MAX + 1)); } #else #warning "Unknown silicon revision, no revision specific parameter checks implemented!" @@ -304,14 +330,15 @@ void lt_test_rev_param_check(lt_handle_t *h) { uint8_t shipriv[TR01_SHIPRIV_LEN] = {0}; uint8_t shipub[TR01_SHIPUB_LEN] = {0}; - LT_TEST_ASSERT(LT_PARAM_ERR, - lt_verify_chip_and_start_secure_session(NULL, shipriv, shipub, TR01_PAIRING_KEY_SLOT_INDEX_0)); - LT_TEST_ASSERT(LT_PARAM_ERR, - lt_verify_chip_and_start_secure_session(h, NULL, shipub, TR01_PAIRING_KEY_SLOT_INDEX_0)); - LT_TEST_ASSERT(LT_PARAM_ERR, - lt_verify_chip_and_start_secure_session(h, shipriv, NULL, TR01_PAIRING_KEY_SLOT_INDEX_0)); LT_TEST_ASSERT(LT_PARAM_ERR, lt_verify_chip_and_start_secure_session( - h, shipriv, shipub, (lt_pkey_index_t)(TR01_PAIRING_KEY_SLOT_INDEX_3 + 1))); + NULL, shipriv, shipub, TR01_PAIRING_KEY_SLOT_INDEX_0)); + LT_TEST_ASSERT(LT_PARAM_ERR, lt_verify_chip_and_start_secure_session( + h, NULL, shipub, TR01_PAIRING_KEY_SLOT_INDEX_0)); + LT_TEST_ASSERT(LT_PARAM_ERR, lt_verify_chip_and_start_secure_session( + h, shipriv, NULL, TR01_PAIRING_KEY_SLOT_INDEX_0)); + LT_TEST_ASSERT(LT_PARAM_ERR, + lt_verify_chip_and_start_secure_session( + h, shipriv, shipub, (lt_pkey_index_t)(TR01_PAIRING_KEY_SLOT_INDEX_3 + 1))); } { @@ -331,10 +358,12 @@ void lt_test_rev_param_check(lt_handle_t *h) { uint8_t data[1] = {0}; - LT_TEST_ASSERT(LT_PARAM_ERR, lt_do_mutable_fw_update(NULL, data, sizeof(data), TR01_FW_BANK_FW1)); + LT_TEST_ASSERT(LT_PARAM_ERR, + lt_do_mutable_fw_update(NULL, data, sizeof(data), TR01_FW_BANK_FW1)); LT_TEST_ASSERT(LT_PARAM_ERR, lt_do_mutable_fw_update(h, NULL, sizeof(data), TR01_FW_BANK_FW1)); - LT_TEST_ASSERT(LT_PARAM_ERR, lt_do_mutable_fw_update(h, data, (uint16_t)(TR01_MUTABLE_FW_UPDATE_SIZE_MAX + 1), - TR01_FW_BANK_FW1)); + LT_TEST_ASSERT(LT_PARAM_ERR, lt_do_mutable_fw_update( + h, data, (uint16_t)(TR01_MUTABLE_FW_UPDATE_SIZE_MAX + 1), + TR01_FW_BANK_FW1)); } { diff --git a/tests/functional/src/lt_test_rev_r_mem.c b/tests/functional/src/lt_test_rev_r_mem.c index 7aae2af6a..2070e59c8 100644 --- a/tests/functional/src/lt_test_rev_r_mem.c +++ b/tests/functional/src/lt_test_rev_r_mem.c @@ -86,7 +86,8 @@ void lt_test_rev_r_mem(lt_handle_t *h) // Making the handle accessible to the cleanup function. g_h = h; - uint8_t r_mem_data[R_MEM_DATA_SIZE_MAX], write_data[R_MEM_DATA_SIZE_MAX], zeros[R_MEM_DATA_SIZE_MAX] = {0}; + uint8_t r_mem_data[R_MEM_DATA_SIZE_MAX], write_data[R_MEM_DATA_SIZE_MAX], + zeros[R_MEM_DATA_SIZE_MAX] = {0}; uint16_t read_data_size, write_data_len; LT_LOG_INFO("Initializing handle"); @@ -122,10 +123,12 @@ void lt_test_rev_r_mem(lt_handle_t *h) LT_TEST_ASSERT(LT_OK, lt_random_bytes(h, write_data, h->tr01_attrs.r_mem_udata_slot_size_max)); LT_LOG_INFO("Writing to slot #%" PRIu16 "...", i); - LT_TEST_ASSERT(LT_OK, lt_r_mem_data_write(h, i, write_data, h->tr01_attrs.r_mem_udata_slot_size_max)); + LT_TEST_ASSERT(LT_OK, + lt_r_mem_data_write(h, i, write_data, h->tr01_attrs.r_mem_udata_slot_size_max)); LT_LOG_INFO("Reading slot #%" PRIu16 "...", i); - LT_TEST_ASSERT(LT_OK, lt_r_mem_data_read(h, i, r_mem_data, sizeof(r_mem_data), &read_data_size)); + LT_TEST_ASSERT(LT_OK, + lt_r_mem_data_read(h, i, r_mem_data, sizeof(r_mem_data), &read_data_size)); LT_LOG_INFO("Checking number of read bytes..."); LT_TEST_ASSERT(1, (read_data_size == h->tr01_attrs.r_mem_udata_slot_size_max)); @@ -134,11 +137,13 @@ void lt_test_rev_r_mem(lt_handle_t *h) LT_TEST_ASSERT(0, memcmp(r_mem_data, write_data, h->tr01_attrs.r_mem_udata_slot_size_max)); LT_LOG_INFO("Writing zeros to slot #%" PRIu16 " (should fail)...", i); - LT_TEST_ASSERT(LT_L3_SLOT_NOT_EMPTY, lt_r_mem_data_write(h, i, zeros, h->tr01_attrs.r_mem_udata_slot_size_max)); + LT_TEST_ASSERT(LT_L3_SLOT_NOT_EMPTY, + lt_r_mem_data_write(h, i, zeros, h->tr01_attrs.r_mem_udata_slot_size_max)); LT_LOG_INFO("Reading slot #%" PRIu16 "...", i); read_data_size = 0; // Set different value just in case - LT_TEST_ASSERT(LT_OK, lt_r_mem_data_read(h, i, r_mem_data, sizeof(r_mem_data), &read_data_size)); + LT_TEST_ASSERT(LT_OK, + lt_r_mem_data_read(h, i, r_mem_data, sizeof(r_mem_data), &read_data_size)); LT_LOG_INFO("Checking number of read bytes..."); LT_TEST_ASSERT(1, (read_data_size == h->tr01_attrs.r_mem_udata_slot_size_max)); @@ -166,11 +171,12 @@ void lt_test_rev_r_mem(lt_handle_t *h) LT_LOG_INFO("Testing writing all slots partially..."); for (uint16_t i = 0; i <= TR01_R_MEM_DATA_SLOT_MAX; i++) { LT_LOG_INFO(); - LT_LOG_INFO("Generating random data length < %" PRIu16 "...", h->tr01_attrs.r_mem_udata_slot_size_max); + LT_LOG_INFO("Generating random data length < %" PRIu16 "...", + h->tr01_attrs.r_mem_udata_slot_size_max); LT_TEST_ASSERT(LT_OK, lt_random_bytes(h, &write_data_len, sizeof(write_data_len))); - write_data_len - %= h->tr01_attrs.r_mem_udata_slot_size_max - 1; // 0..(h->tr01_attrs.r_mem_udata_slot_size_max-2) - write_data_len += 1; // 1..(h->tr01_attrs.r_mem_udata_slot_size_max-1) + write_data_len %= h->tr01_attrs.r_mem_udata_slot_size_max - + 1; // 0..(h->tr01_attrs.r_mem_udata_slot_size_max-2) + write_data_len += 1; // 1..(h->tr01_attrs.r_mem_udata_slot_size_max-1) LT_LOG_INFO("Generating %" PRIu16 " random bytes for slot #%" PRIu16 "...", write_data_len, i); LT_TEST_ASSERT(LT_OK, lt_random_bytes(h, write_data, write_data_len)); @@ -179,7 +185,8 @@ void lt_test_rev_r_mem(lt_handle_t *h) LT_TEST_ASSERT(LT_OK, lt_r_mem_data_write(h, i, write_data, write_data_len)); LT_LOG_INFO("Reading slot #%" PRIu16 "...", i); - LT_TEST_ASSERT(LT_OK, lt_r_mem_data_read(h, i, r_mem_data, sizeof(r_mem_data), &read_data_size)); + LT_TEST_ASSERT(LT_OK, + lt_r_mem_data_read(h, i, r_mem_data, sizeof(r_mem_data), &read_data_size)); LT_LOG_INFO("Checking number of read bytes..."); LT_TEST_ASSERT(1, (read_data_size == write_data_len)); diff --git a/tests/functional/src/lt_test_rev_startup_req.c b/tests/functional/src/lt_test_rev_startup_req.c index 99f292b1a..100cd94c5 100644 --- a/tests/functional/src/lt_test_rev_startup_req.c +++ b/tests/functional/src/lt_test_rev_startup_req.c @@ -115,12 +115,14 @@ void lt_test_rev_startup_req(lt_handle_t *h) LT_TEST_ASSERT(MAINTENANCE_MODE, check_current_state()); LT_LOG_INFO("Checking that the handshake does not work..."); #ifdef ABAB - LT_TEST_ASSERT(LT_L2_GEN_ERR, lt_verify_chip_and_start_secure_session(h, LT_TEST_SH0_PRIV, LT_TEST_SH0_PUB, - TR01_PAIRING_KEY_SLOT_INDEX_0)); + LT_TEST_ASSERT(LT_L2_GEN_ERR, + lt_verify_chip_and_start_secure_session(h, LT_TEST_SH0_PRIV, LT_TEST_SH0_PUB, + TR01_PAIRING_KEY_SLOT_INDEX_0)); #elif ACAB - LT_TEST_ASSERT(LT_L2_UNKNOWN_REQ, lt_verify_chip_and_start_secure_session(h, LT_TEST_SH0_PRIV, LT_TEST_SH0_PUB, - TR01_PAIRING_KEY_SLOT_INDEX_0)); + LT_TEST_ASSERT(LT_L2_UNKNOWN_REQ, + lt_verify_chip_and_start_secure_session(h, LT_TEST_SH0_PRIV, LT_TEST_SH0_PUB, + TR01_PAIRING_KEY_SLOT_INDEX_0)); #else #error "Undefined silicon revision. Please define either ABAB or ACAB." #endif diff --git a/tests/functional/src/lt_test_rev_write_r_config.c b/tests/functional/src/lt_test_rev_write_r_config.c index c023a8d0f..2accb4d16 100644 --- a/tests/functional/src/lt_test_rev_write_r_config.c +++ b/tests/functional/src/lt_test_rev_write_r_config.c @@ -127,7 +127,8 @@ void lt_test_rev_write_r_config(lt_handle_t *h) LT_LOG_INFO("Writing the whole R config again (should fail)"); for (int i = 0; i < LT_CONFIG_OBJ_CNT; i++) { - LT_TEST_ASSERT(LT_L3_FAIL, lt_r_config_write(h, cfg_desc_table[i].addr, r_config_backup.obj[i])); + LT_TEST_ASSERT(LT_L3_FAIL, + lt_r_config_write(h, cfg_desc_table[i].addr, r_config_backup.obj[i])); } LT_LOG_INFO("Reading the whole R config"); diff --git a/tests/functional/stm32/download_deps.sh b/tests/functional/stm32/download_deps.sh index 45ec04649..5ece92176 100755 --- a/tests/functional/stm32/download_deps.sh +++ b/tests/functional/stm32/download_deps.sh @@ -53,4 +53,19 @@ fi tar -xjf "$SCRIPT_DIR/_deps/mbedtls.tar.bz2" -C "$SCRIPT_DIR/_deps" rm "$SCRIPT_DIR/_deps/mbedtls.tar.bz2" -mv "$SCRIPT_DIR/_deps/mbedtls-4.0.0" "$SCRIPT_DIR/_deps/mbedtls_v4" \ No newline at end of file +mv "$SCRIPT_DIR/_deps/mbedtls-4.0.0" "$SCRIPT_DIR/_deps/mbedtls_v4" + +echo "Downloading WolfSSL..." +curl -L -o "$SCRIPT_DIR/_deps/wolfssl.zip" "https://github.com/wolfSSL/wolfssl/archive/refs/tags/v5.8.4-stable.zip" + +echo "Verifying wolfssl.zip checksum..." +EXPECTED_WOLFSSL="9f52b92b2937acdbb03f2a731160d70f23f74a375f651de057214783c266fbeb" +ACTUAL_WOLFSSL=$(sha256sum "$SCRIPT_DIR/_deps/wolfssl.zip" | awk '{print $1}') +if [ "$EXPECTED_WOLFSSL" != "$ACTUAL_WOLFSSL" ]; then + echo "Checksum mismatch for wolfssl.zip: expected $EXPECTED_WOLFSSL, got $ACTUAL_WOLFSSL" >&2 + exit 1 +fi + +unzip "$SCRIPT_DIR/_deps/wolfssl.zip" -d "$SCRIPT_DIR/_deps" +mv "$SCRIPT_DIR/_deps/wolfssl-5.8.4-stable" "$SCRIPT_DIR/_deps/wolfssl" +rm "$SCRIPT_DIR/_deps/wolfssl.zip" \ No newline at end of file diff --git a/tests/functional/stm32/nucleo_f439zi/CMakeLists.txt b/tests/functional/stm32/nucleo_f439zi/CMakeLists.txt index ebfb7bc1a..de8b7dcc9 100644 --- a/tests/functional/stm32/nucleo_f439zi/CMakeLists.txt +++ b/tests/functional/stm32/nucleo_f439zi/CMakeLists.txt @@ -90,6 +90,15 @@ endif() # Add path to libtropic's repository root folder add_subdirectory(${PATH_FN_TESTS} "libtropic_functional_tests") +# Additional configuration for WolfCrypt. +if(LT_CAL STREQUAL "wolfcrypt") + target_compile_definitions(wolfssl PUBLIC WOLFSSL_USER_SETTINGS) + # Use BUILD_INTERFACE to strictly limit this path to the build phase + target_include_directories(wolfssl PUBLIC + $ + ) +endif() + ########################################################################### # # # Sources # @@ -131,6 +140,11 @@ if (LT_CAL STREQUAL "mbedtls_v4") # MbedTLS platform-specific implementations ${CMAKE_CURRENT_SOURCE_DIR}/Src/mbedtls_v4/mbedtls_platform.c ) +elseif (LT_CAL STREQUAL "wolfcrypt") + set(SOURCES ${SOURCES} + # WolfCrypt platform-specific implementations + ${CMAKE_CURRENT_SOURCE_DIR}/Src/wolfcrypt/wolfcrypt_platform.c + ) endif() # Include path for directories containing header files diff --git a/tests/functional/stm32/nucleo_f439zi/Src/main.c b/tests/functional/stm32/nucleo_f439zi/Src/main.c index 80e0da0f5..0a0b06428 100644 --- a/tests/functional/stm32/nucleo_f439zi/Src/main.c +++ b/tests/functional/stm32/nucleo_f439zi/Src/main.c @@ -3,7 +3,7 @@ * @brief Wrapper project for running Libtropic functional test suite on Nucleo F439ZI. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. * * This example project is based on the UART/UART_Printf example from STM32 example library * which was created by the MCD Application Team. @@ -24,9 +24,16 @@ #if LT_USE_TREZOR_CRYPTO #include "libtropic_trezor_crypto.h" +#define CRYPTO_CTX_TYPE lt_ctx_trezor_crypto_t #elif LT_USE_MBEDTLS_V4 #include "libtropic_mbedtls_v4.h" #include "psa/crypto.h" +#define CRYPTO_CTX_TYPE lt_ctx_mbedtls_v4_t +#elif LT_USE_WOLFCRYPT +#include "libtropic_wolfcrypt.h" +#include "wolfssl/wolfcrypt/error-crypt.h" +#include "wolfssl/wolfcrypt/wc_port.h" +#define CRYPTO_CTX_TYPE lt_ctx_wolfcrypt_t #endif /** @addtogroup STM32F4xx_HAL_Examples @@ -162,6 +169,12 @@ int main(void) LT_LOG_ERROR("PSA Crypto initialization failed, status=%d (psa_status_t)", status); return -1; } +#elif LT_USE_WOLFCRYPT + int ret = wolfCrypt_Init(); + if (ret != 0) { + LT_LOG_ERROR("WolfCrypt initialization failed, ret=%d (%s)", ret, wc_GetErrorString(ret)); + return ret; + } #endif /* Libtropic handle initialization */ @@ -187,12 +200,7 @@ int main(void) lt_handle.l2.device = &device; /* Crypto abstraction layer (CAL) context (selectable). */ -#if LT_USE_TREZOR_CRYPTO - lt_ctx_trezor_crypto_t -#elif LT_USE_MBEDTLS_V4 - lt_ctx_mbedtls_v4_t -#endif - crypto_ctx; + CRYPTO_CTX_TYPE crypto_ctx; lt_handle.l3.crypto_ctx = &crypto_ctx; /* Test code (correct test function is selected automatically per binary) @@ -203,6 +211,12 @@ int main(void) /* Cryptographic function provider deinitialization. */ #if LT_USE_MBEDTLS_V4 mbedtls_psa_crypto_free(); +#elif LT_USE_WOLFCRYPT + ret = wolfCrypt_Cleanup(); + if (ret != 0) { + LT_LOG_ERROR("WolfCrypt cleanup failed, ret=%d (%s)", ret, wc_GetErrorString(ret)); + return ret; + } #endif /* Inform the test runner that the test finished */ @@ -283,8 +297,8 @@ static void SystemClock_Config(void) /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType - = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | + RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; diff --git a/tests/functional/stm32/nucleo_f439zi/Src/mbedtls_v4/crypto_config.h b/tests/functional/stm32/nucleo_f439zi/Src/mbedtls_v4/crypto_config.h index 303d6d9b4..4939948db 100644 --- a/tests/functional/stm32/nucleo_f439zi/Src/mbedtls_v4/crypto_config.h +++ b/tests/functional/stm32/nucleo_f439zi/Src/mbedtls_v4/crypto_config.h @@ -356,12 +356,13 @@ * * - mbedtls_calloc = MBEDTLS_PLATFORM_STD_CALLOC. * - * Defining MBEDTLS_PLATFORM_CALLOC_MACRO and #MBEDTLS_PLATFORM_STD_CALLOC at the same time is not possible. - * MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO must both be defined or undefined at the same time. - * #MBEDTLS_PLATFORM_STD_CALLOC and #MBEDTLS_PLATFORM_STD_FREE do not have to be defined at the same time, as, if they - * are used, dynamic setup of these functions is possible. See the tree above to see how are they handled in all cases. - * An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. - * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. + * Defining MBEDTLS_PLATFORM_CALLOC_MACRO and #MBEDTLS_PLATFORM_STD_CALLOC at the same time is not + * possible. MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO must both be defined or + * undefined at the same time. #MBEDTLS_PLATFORM_STD_CALLOC and #MBEDTLS_PLATFORM_STD_FREE do not have + * to be defined at the same time, as, if they are used, dynamic setup of these functions is possible. + * See the tree above to see how are they handled in all cases. An uninitialized + * #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. An uninitialized + * #MBEDTLS_PLATFORM_STD_FREE does not do anything. * * Requires: MBEDTLS_PLATFORM_C * @@ -475,20 +476,24 @@ /* To use the following function macros, MBEDTLS_PLATFORM_C must be enabled. */ /* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */ -// #define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be undefined. See -// MBEDTLS_PLATFORM_STD_CALLOC for requirements. */ #define MBEDTLS_PLATFORM_EXIT_MACRO exit /**< Default -// exit macro to use, can be undefined */ #define MBEDTLS_PLATFORM_FREE_MACRO free /**< Default free macro to -// use, can be undefined. See MBEDTLS_PLATFORM_STD_FREE for requirements. */ #define MBEDTLS_PLATFORM_FPRINTF_MACRO -// fprintf /**< Default fprintf macro to use, can be undefined */ #define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t -// //#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t /**< Default milliseconds time macro to use, can be -// undefined. MBEDTLS_HAVE_TIME must be enabled. It must be signed, and at least 64 bits. If it is changed from the -// default, MBEDTLS_PRINTF_MS_TIME must be updated to match.*/ #define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO -// mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ #define -// MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, -// can be undefined */ #define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be -// undefined */ #define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf /**< Default setbuf macro to use, can be undefined */ +// #define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be +// undefined. See MBEDTLS_PLATFORM_STD_CALLOC for requirements. */ #define MBEDTLS_PLATFORM_EXIT_MACRO +// exit /**< Default exit macro to use, can be undefined */ #define MBEDTLS_PLATFORM_FREE_MACRO free +// /**< Default free macro to use, can be undefined. See MBEDTLS_PLATFORM_STD_FREE for requirements. */ +// #define MBEDTLS_PLATFORM_FPRINTF_MACRO fprintf /**< Default fprintf macro to use, can be undefined +// */ #define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t +// //#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t /**< Default milliseconds time macro to use, +// can be undefined. MBEDTLS_HAVE_TIME must be enabled. It must be signed, and at least 64 bits. If it +// is changed from the default, MBEDTLS_PRINTF_MS_TIME must be updated to match.*/ #define +// MBEDTLS_PLATFORM_NV_SEED_READ_MACRO mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read +// function to use, can be undefined */ #define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO +// mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +// #define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be +// undefined */ #define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf /**< Default setbuf macro to use, can +// be undefined */ /* Note: your snprintf must correctly zero-terminate the buffer! */ -// #define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be undefined */ +// #define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be +// undefined */ /** \def MBEDTLS_PLATFORM_STD_CALLOC * @@ -496,44 +501,47 @@ * It must initialize the allocated buffer memory to zeroes. * The size of the buffer is the product of the two parameters. * The calloc function returns either a null pointer or a pointer to the allocated space. - * If the product is 0, the function may either return NULL or a valid pointer to an array of size 0 which is a valid - * input to the deallocation function. An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null - * pointer. See the description of #MBEDTLS_PLATFORM_MEMORY for more details. The corresponding deallocation function is - * #MBEDTLS_PLATFORM_STD_FREE. + * If the product is 0, the function may either return NULL or a valid pointer to an array of size 0 + * which is a valid input to the deallocation function. An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC + * always fails, returning a null pointer. See the description of #MBEDTLS_PLATFORM_MEMORY for more + * details. The corresponding deallocation function is #MBEDTLS_PLATFORM_STD_FREE. */ // #define MBEDTLS_PLATFORM_STD_CALLOC calloc // #define MBEDTLS_PLATFORM_STD_EXIT exit /**< Default exit to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined +// */ #define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be +// undefined */ #define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be +// undefined */ /** \def MBEDTLS_PLATFORM_STD_FREE * * Default free to use, can be undefined. * NULL is a valid parameter, and the function must do nothing. - * A non-null parameter will always be a pointer previously returned by #MBEDTLS_PLATFORM_STD_CALLOC and not yet freed. - * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. - * See the description of #MBEDTLS_PLATFORM_MEMORY for more details (same principles as for MBEDTLS_PLATFORM_STD_CALLOC - * apply). + * A non-null parameter will always be a pointer previously returned by #MBEDTLS_PLATFORM_STD_CALLOC + * and not yet freed. An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. See the + * description of #MBEDTLS_PLATFORM_MEMORY for more details (same principles as for + * MBEDTLS_PLATFORM_STD_CALLOC apply). */ // #define MBEDTLS_PLATFORM_STD_FREE free -// #define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is -// defined. Don't define if no header is needed. */ #define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file -// to read/write with default implementation */ #define MBEDTLS_PLATFORM_STD_NV_SEED_READ -// mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ #define -// MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, -// can be undefined */ #define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if +// MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */ #define +// MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file to read/write with default +// implementation */ #define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read /**< +// Default nv_seed_read function to use, can be undefined */ #define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE +// mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ // #define MBEDTLS_PLATFORM_STD_SETBUF setbuf /**< Default setbuf to use, can be undefined */ /* Note: your snprintf must correctly zero-terminate the buffer! */ // #define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< Default snprintf to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. MBEDTLS_HAVE_TIME must -// be enabled */ #define MBEDTLS_PLATFORM_TIME_MACRO time /**< Default time macro to use, can be undefined. -// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to -// use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf -// /**< Default vsnprintf macro to use, can be undefined */ #define MBEDTLS_PRINTF_MS_TIME PRId64 /**< Default fmt -// for printf. That's avoid compiler warning if mbedtls_ms_time_t is redefined */ +// #define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. +// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_TIME_MACRO time /**< +// Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ #define +// MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to use, can be undefined. +// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf +// /**< Default vsnprintf macro to use, can be undefined */ #define MBEDTLS_PRINTF_MS_TIME PRId64 +// /**< Default fmt for printf. That's avoid compiler warning if mbedtls_ms_time_t is redefined */ /** \} name SECTION: Platform abstraction layer */ @@ -1983,8 +1991,8 @@ // #define MBEDTLS_MPI_WINDOW_SIZE 2 /**< Maximum window size used. */ /* RSA OPTIONS */ -// #define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 /**< Minimum RSA key size that can be generated in bits -// (Minimum possible value is 128 bits) */ +// #define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 /**< Minimum RSA key size that can be +// generated in bits (Minimum possible value is 128 bits) */ /** \} name SECTION: Builtin drivers */ diff --git a/tests/functional/stm32/nucleo_f439zi/Src/mbedtls_v4/mbedtls_config.h b/tests/functional/stm32/nucleo_f439zi/Src/mbedtls_v4/mbedtls_config.h index 68149cacf..b34657c71 100644 --- a/tests/functional/stm32/nucleo_f439zi/Src/mbedtls_v4/mbedtls_config.h +++ b/tests/functional/stm32/nucleo_f439zi/Src/mbedtls_v4/mbedtls_config.h @@ -861,7 +861,8 @@ */ // #define MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH -// #define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default 256 or 384 bits) +// #define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default +// 256 or 384 bits) // */ #define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */ #define // MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /**< 1 day */ @@ -910,8 +911,8 @@ // #define MBEDTLS_SSL_CIPHERSUITES // MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 -// #define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, -// or in number of cookies issued */ +// #define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in +// seconds if HAVE_TIME, or in number of cookies issued */ /** \def MBEDTLS_SSL_DTLS_MAX_BUFFERING * @@ -1198,8 +1199,8 @@ */ // #define MBEDTLS_X509_USE_C -// #define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in bytes including the -// null terminator character ('\0'). */ #define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 /**< Maximum number of -// intermediate CAs in a verification chain. */ +// #define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in +// bytes including the null terminator character ('\0'). */ #define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 +// /**< Maximum number of intermediate CAs in a verification chain. */ /** \} name SECTION: X.509 feature selection */ diff --git a/tests/functional/stm32/nucleo_f439zi/Src/mbedtls_v4/mbedtls_platform.c b/tests/functional/stm32/nucleo_f439zi/Src/mbedtls_v4/mbedtls_platform.c index 3f97b6244..0b93a26a8 100644 --- a/tests/functional/stm32/nucleo_f439zi/Src/mbedtls_v4/mbedtls_platform.c +++ b/tests/functional/stm32/nucleo_f439zi/Src/mbedtls_v4/mbedtls_platform.c @@ -4,6 +4,7 @@ #include "main.h" #include "mbedtls/platform.h" #include "mbedtls/platform_time.h" +#include "mbedtls/platform_util.h" #include "stm32f4xx_hal.h" mbedtls_ms_time_t mbedtls_ms_time(void) @@ -13,8 +14,8 @@ mbedtls_ms_time_t mbedtls_ms_time(void) return (mbedtls_ms_time_t)HAL_GetTick(); } -int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *estimate_bits, unsigned char *output, - size_t output_size) +int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *estimate_bits, + unsigned char *output, size_t output_size) { /* We don't implement any flags. */ if (flags != 0) { @@ -28,6 +29,7 @@ int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *e while (bytes_left) { hal_status = HAL_RNG_GenerateRandomNumber(&RNGHandle, &random_data); if (hal_status != HAL_OK) { + mbedtls_platform_zeroize(&random_data, sizeof(random_data)); return PSA_ERROR_INSUFFICIENT_ENTROPY; } @@ -39,5 +41,6 @@ int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *e *estimate_bits = 8 * output_size; + mbedtls_platform_zeroize(&random_data, sizeof(random_data)); return 0; } \ No newline at end of file diff --git a/tests/functional/stm32/nucleo_f439zi/Src/wolfcrypt/user_settings.h b/tests/functional/stm32/nucleo_f439zi/Src/wolfcrypt/user_settings.h new file mode 100644 index 000000000..dc20ca90f --- /dev/null +++ b/tests/functional/stm32/nucleo_f439zi/Src/wolfcrypt/user_settings.h @@ -0,0 +1,26 @@ +#ifndef USER_SETTINGS_H +#define USER_SETTINGS_H + +#define WOLFCRYPT_ONLY // Build only wolfCrypt library. +#define NO_OLD_RNGNAME // Resolves collision between STM32 HAL 'RNG' and WolfSSL 'RNG'. +// #define USE_FAST_MATH + +// We will provide custom implementation for seed generation. +extern int wolfcrypt_custom_seed_gen(unsigned char *output, unsigned int sz); +#define CUSTOM_RAND_GENERATE_SEED wolfcrypt_custom_seed_gen + +#define WOLFSSL_SMALL_STACK // Offload stack usage to heap where possible. +#define WOLFSSL_MALLOC_CHECK // Optional: Safety check for malloc failures. + +#define NO_FILESYSTEM // Prevents filesystem errors on bare metal. +#undef WOLFSSL_SYS_CA_CERTS // Force disable system CA certs (fixes dirent.h / filesystem errors). +#define NO_WRITEV // IO vector write support usually missing. +#define NO_WRITE_TEMP_FILES +#define NO_DEV_RANDOM // We use STM32's RNG, not /dev/random. +#define NO_MAIN_DRIVER + +#define WOLFSSL_USER_IO // Disable the default BSD socket callbacks. + +#define SINGLE_THREADED // No threads. + +#endif /* USER_SETTINGS_H */ \ No newline at end of file diff --git a/tests/functional/stm32/nucleo_f439zi/Src/wolfcrypt/wolfcrypt_platform.c b/tests/functional/stm32/nucleo_f439zi/Src/wolfcrypt/wolfcrypt_platform.c new file mode 100644 index 000000000..30ebc3ede --- /dev/null +++ b/tests/functional/stm32/nucleo_f439zi/Src/wolfcrypt/wolfcrypt_platform.c @@ -0,0 +1,30 @@ +#include +#include +#include +#include + +#include "main.h" +#include "stm32f4xx_hal.h" + +int wolfcrypt_custom_seed_gen(unsigned char *output, unsigned int sz) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + uint32_t random_data; + size_t bytes_left = sz; + + while (bytes_left) { + hal_status = HAL_RNG_GenerateRandomNumber(&RNGHandle, &random_data); + if (hal_status != HAL_OK) { + wc_ForceZero(&random_data, sizeof(random_data)); + return RNG_FAILURE_E; + } + + size_t cpy_cnt = bytes_left < sizeof(random_data) ? bytes_left : sizeof(random_data); + memcpy(output, &random_data, cpy_cnt); + bytes_left -= cpy_cnt; + output += cpy_cnt; + } + + wc_ForceZero(&random_data, sizeof(random_data)); + return 0; +} \ No newline at end of file diff --git a/tests/functional/stm32/nucleo_f439zi/run_test.sh b/tests/functional/stm32/nucleo_f439zi/run_test.sh index 79a32bf85..121e28bfe 100755 --- a/tests/functional/stm32/nucleo_f439zi/run_test.sh +++ b/tests/functional/stm32/nucleo_f439zi/run_test.sh @@ -88,11 +88,19 @@ trap 'cleanup' EXIT # ---- Flash the device ---- if [ -z "$STLINK_SERIAL_NUMBER" ]; then echo "OpenOCD will autodiscover STLink programming interface." - openocd -f board/stm32f429discovery.cfg -c "program $BINARY_PATH verify reset exit" + openocd -f board/stm32f429discovery.cfg \ + -c "gdb_port disabled" \ + -c "telnet_port disabled" \ + -c "tcl_port disabled" \ + -c "program $BINARY_PATH verify reset exit" else - OPENOCD_SERIAL_NUMBER_ARG= echo "OpenOCD will use STLink serial number $STLINK_SERIAL_NUMBER for programming." - openocd -f board/stm32f429discovery.cfg -c "adapter serial $STLINK_SERIAL_NUMBER" -c "program $BINARY_PATH verify reset exit" + openocd -f board/stm32f429discovery.cfg \ + -c "gdb_port disabled" \ + -c "telnet_port disabled" \ + -c "tcl_port disabled" \ + -c "adapter serial $STLINK_SERIAL_NUMBER" \ + -c "program $BINARY_PATH verify reset exit" fi # ---- Wait for serial reader to finish ---- diff --git a/tests/functional/stm32/nucleo_l432kc/CMakeLists.txt b/tests/functional/stm32/nucleo_l432kc/CMakeLists.txt index 1fb4b77f6..a0ac6f8f4 100644 --- a/tests/functional/stm32/nucleo_l432kc/CMakeLists.txt +++ b/tests/functional/stm32/nucleo_l432kc/CMakeLists.txt @@ -94,6 +94,15 @@ endif() # Add path to libtropic's repository root folder add_subdirectory(${PATH_FN_TESTS} "libtropic_functional_tests") +# Additional configuration for WolfCrypt. +if(LT_CAL STREQUAL "wolfcrypt") + target_compile_definitions(wolfssl PUBLIC WOLFSSL_USER_SETTINGS) + # Use BUILD_INTERFACE to strictly limit this path to the build phase + target_include_directories(wolfssl PUBLIC + $ + ) +endif() + ########################################################################### # # # Sources # @@ -136,6 +145,11 @@ if (LT_CAL STREQUAL "mbedtls_v4") # MbedTLS platform-specific implementations ${CMAKE_CURRENT_SOURCE_DIR}/Src/mbedtls_v4/mbedtls_platform.c ) +elseif (LT_CAL STREQUAL "wolfcrypt") + set(SOURCES ${SOURCES} + # WolfCrypt platform-specific implementations + ${CMAKE_CURRENT_SOURCE_DIR}/Src/wolfcrypt/wolfcrypt_platform.c + ) endif() # Include path for directories containing header files diff --git a/tests/functional/stm32/nucleo_l432kc/Src/main.c b/tests/functional/stm32/nucleo_l432kc/Src/main.c index 1be9b049c..2f56b5c15 100644 --- a/tests/functional/stm32/nucleo_l432kc/Src/main.c +++ b/tests/functional/stm32/nucleo_l432kc/Src/main.c @@ -3,10 +3,10 @@ * @brief Wrapper project for running Libtropic functional test suite on Nucleo L432KC. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. * - * This example project is based on the SPI/SPI_FullDuplex_ComPolling example from STM32 example library - * which was created by the MCD Application Team. + * This example project is based on the SPI/SPI_FullDuplex_ComPolling example from STM32 example + * library which was created by the MCD Application Team. */ /* Includes ------------------------------------------------------------------*/ @@ -23,9 +23,16 @@ #if LT_USE_TREZOR_CRYPTO #include "libtropic_trezor_crypto.h" +#define CRYPTO_CTX_TYPE lt_ctx_trezor_crypto_t #elif LT_USE_MBEDTLS_V4 #include "libtropic_mbedtls_v4.h" #include "psa/crypto.h" +#define CRYPTO_CTX_TYPE lt_ctx_mbedtls_v4_t +#elif LT_USE_WOLFCRYPT +#include "libtropic_wolfcrypt.h" +#include "wolfssl/wolfcrypt/error-crypt.h" +#include "wolfssl/wolfcrypt/wc_port.h" +#define CRYPTO_CTX_TYPE lt_ctx_wolfcrypt_t #endif /** @addtogroup STM32L4xx_HAL_Examples @@ -198,6 +205,12 @@ int main(void) LT_LOG_ERROR("PSA Crypto initialization failed, status=%d (psa_status_t)", status); return -1; } +#elif LT_USE_WOLFCRYPT + int ret = wolfCrypt_Init(); + if (ret != 0) { + LT_LOG_ERROR("WolfCrypt initialization failed, ret=%d (%s)", ret, wc_GetErrorString(ret)); + return ret; + } #endif /* Libtropic handle initialization */ @@ -215,12 +228,7 @@ int main(void) lt_handle.l2.device = &device; /* Crypto abstraction layer (CAL) context (selectable). */ -#if LT_USE_TREZOR_CRYPTO - lt_ctx_trezor_crypto_t -#elif LT_USE_MBEDTLS_V4 - lt_ctx_mbedtls_v4_t -#endif - crypto_ctx; + CRYPTO_CTX_TYPE crypto_ctx; lt_handle.l3.crypto_ctx = &crypto_ctx; /* Test code (correct test function is selected automatically per binary) @@ -231,6 +239,12 @@ int main(void) /* Cryptographic function provider deinitialization. */ #if LT_USE_MBEDTLS_V4 mbedtls_psa_crypto_free(); +#elif LT_USE_WOLFCRYPT + ret = wolfCrypt_Cleanup(); + if (ret != 0) { + LT_LOG_ERROR("WolfCrypt cleanup failed, ret=%d (%s)", ret, wc_GetErrorString(ret)); + return ret; + } #endif /* Inform the test runner that the test finished */ @@ -312,8 +326,8 @@ void SystemClock_Config(void) /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType - = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | + RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; diff --git a/tests/functional/stm32/nucleo_l432kc/Src/mbedtls_v4/crypto_config.h b/tests/functional/stm32/nucleo_l432kc/Src/mbedtls_v4/crypto_config.h index 303d6d9b4..4939948db 100644 --- a/tests/functional/stm32/nucleo_l432kc/Src/mbedtls_v4/crypto_config.h +++ b/tests/functional/stm32/nucleo_l432kc/Src/mbedtls_v4/crypto_config.h @@ -356,12 +356,13 @@ * * - mbedtls_calloc = MBEDTLS_PLATFORM_STD_CALLOC. * - * Defining MBEDTLS_PLATFORM_CALLOC_MACRO and #MBEDTLS_PLATFORM_STD_CALLOC at the same time is not possible. - * MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO must both be defined or undefined at the same time. - * #MBEDTLS_PLATFORM_STD_CALLOC and #MBEDTLS_PLATFORM_STD_FREE do not have to be defined at the same time, as, if they - * are used, dynamic setup of these functions is possible. See the tree above to see how are they handled in all cases. - * An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. - * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. + * Defining MBEDTLS_PLATFORM_CALLOC_MACRO and #MBEDTLS_PLATFORM_STD_CALLOC at the same time is not + * possible. MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO must both be defined or + * undefined at the same time. #MBEDTLS_PLATFORM_STD_CALLOC and #MBEDTLS_PLATFORM_STD_FREE do not have + * to be defined at the same time, as, if they are used, dynamic setup of these functions is possible. + * See the tree above to see how are they handled in all cases. An uninitialized + * #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. An uninitialized + * #MBEDTLS_PLATFORM_STD_FREE does not do anything. * * Requires: MBEDTLS_PLATFORM_C * @@ -475,20 +476,24 @@ /* To use the following function macros, MBEDTLS_PLATFORM_C must be enabled. */ /* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */ -// #define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be undefined. See -// MBEDTLS_PLATFORM_STD_CALLOC for requirements. */ #define MBEDTLS_PLATFORM_EXIT_MACRO exit /**< Default -// exit macro to use, can be undefined */ #define MBEDTLS_PLATFORM_FREE_MACRO free /**< Default free macro to -// use, can be undefined. See MBEDTLS_PLATFORM_STD_FREE for requirements. */ #define MBEDTLS_PLATFORM_FPRINTF_MACRO -// fprintf /**< Default fprintf macro to use, can be undefined */ #define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t -// //#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t /**< Default milliseconds time macro to use, can be -// undefined. MBEDTLS_HAVE_TIME must be enabled. It must be signed, and at least 64 bits. If it is changed from the -// default, MBEDTLS_PRINTF_MS_TIME must be updated to match.*/ #define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO -// mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ #define -// MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, -// can be undefined */ #define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be -// undefined */ #define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf /**< Default setbuf macro to use, can be undefined */ +// #define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be +// undefined. See MBEDTLS_PLATFORM_STD_CALLOC for requirements. */ #define MBEDTLS_PLATFORM_EXIT_MACRO +// exit /**< Default exit macro to use, can be undefined */ #define MBEDTLS_PLATFORM_FREE_MACRO free +// /**< Default free macro to use, can be undefined. See MBEDTLS_PLATFORM_STD_FREE for requirements. */ +// #define MBEDTLS_PLATFORM_FPRINTF_MACRO fprintf /**< Default fprintf macro to use, can be undefined +// */ #define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t +// //#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t /**< Default milliseconds time macro to use, +// can be undefined. MBEDTLS_HAVE_TIME must be enabled. It must be signed, and at least 64 bits. If it +// is changed from the default, MBEDTLS_PRINTF_MS_TIME must be updated to match.*/ #define +// MBEDTLS_PLATFORM_NV_SEED_READ_MACRO mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read +// function to use, can be undefined */ #define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO +// mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +// #define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be +// undefined */ #define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf /**< Default setbuf macro to use, can +// be undefined */ /* Note: your snprintf must correctly zero-terminate the buffer! */ -// #define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be undefined */ +// #define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be +// undefined */ /** \def MBEDTLS_PLATFORM_STD_CALLOC * @@ -496,44 +501,47 @@ * It must initialize the allocated buffer memory to zeroes. * The size of the buffer is the product of the two parameters. * The calloc function returns either a null pointer or a pointer to the allocated space. - * If the product is 0, the function may either return NULL or a valid pointer to an array of size 0 which is a valid - * input to the deallocation function. An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null - * pointer. See the description of #MBEDTLS_PLATFORM_MEMORY for more details. The corresponding deallocation function is - * #MBEDTLS_PLATFORM_STD_FREE. + * If the product is 0, the function may either return NULL or a valid pointer to an array of size 0 + * which is a valid input to the deallocation function. An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC + * always fails, returning a null pointer. See the description of #MBEDTLS_PLATFORM_MEMORY for more + * details. The corresponding deallocation function is #MBEDTLS_PLATFORM_STD_FREE. */ // #define MBEDTLS_PLATFORM_STD_CALLOC calloc // #define MBEDTLS_PLATFORM_STD_EXIT exit /**< Default exit to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined +// */ #define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be +// undefined */ #define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be +// undefined */ /** \def MBEDTLS_PLATFORM_STD_FREE * * Default free to use, can be undefined. * NULL is a valid parameter, and the function must do nothing. - * A non-null parameter will always be a pointer previously returned by #MBEDTLS_PLATFORM_STD_CALLOC and not yet freed. - * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. - * See the description of #MBEDTLS_PLATFORM_MEMORY for more details (same principles as for MBEDTLS_PLATFORM_STD_CALLOC - * apply). + * A non-null parameter will always be a pointer previously returned by #MBEDTLS_PLATFORM_STD_CALLOC + * and not yet freed. An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. See the + * description of #MBEDTLS_PLATFORM_MEMORY for more details (same principles as for + * MBEDTLS_PLATFORM_STD_CALLOC apply). */ // #define MBEDTLS_PLATFORM_STD_FREE free -// #define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is -// defined. Don't define if no header is needed. */ #define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file -// to read/write with default implementation */ #define MBEDTLS_PLATFORM_STD_NV_SEED_READ -// mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ #define -// MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, -// can be undefined */ #define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if +// MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */ #define +// MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file to read/write with default +// implementation */ #define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read /**< +// Default nv_seed_read function to use, can be undefined */ #define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE +// mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ // #define MBEDTLS_PLATFORM_STD_SETBUF setbuf /**< Default setbuf to use, can be undefined */ /* Note: your snprintf must correctly zero-terminate the buffer! */ // #define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< Default snprintf to use, can be undefined */ -// #define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. MBEDTLS_HAVE_TIME must -// be enabled */ #define MBEDTLS_PLATFORM_TIME_MACRO time /**< Default time macro to use, can be undefined. -// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to -// use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf -// /**< Default vsnprintf macro to use, can be undefined */ #define MBEDTLS_PRINTF_MS_TIME PRId64 /**< Default fmt -// for printf. That's avoid compiler warning if mbedtls_ms_time_t is redefined */ +// #define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. +// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_TIME_MACRO time /**< +// Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ #define +// MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to use, can be undefined. +// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf +// /**< Default vsnprintf macro to use, can be undefined */ #define MBEDTLS_PRINTF_MS_TIME PRId64 +// /**< Default fmt for printf. That's avoid compiler warning if mbedtls_ms_time_t is redefined */ /** \} name SECTION: Platform abstraction layer */ @@ -1983,8 +1991,8 @@ // #define MBEDTLS_MPI_WINDOW_SIZE 2 /**< Maximum window size used. */ /* RSA OPTIONS */ -// #define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 /**< Minimum RSA key size that can be generated in bits -// (Minimum possible value is 128 bits) */ +// #define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 /**< Minimum RSA key size that can be +// generated in bits (Minimum possible value is 128 bits) */ /** \} name SECTION: Builtin drivers */ diff --git a/tests/functional/stm32/nucleo_l432kc/Src/mbedtls_v4/mbedtls_config.h b/tests/functional/stm32/nucleo_l432kc/Src/mbedtls_v4/mbedtls_config.h index 68149cacf..b34657c71 100644 --- a/tests/functional/stm32/nucleo_l432kc/Src/mbedtls_v4/mbedtls_config.h +++ b/tests/functional/stm32/nucleo_l432kc/Src/mbedtls_v4/mbedtls_config.h @@ -861,7 +861,8 @@ */ // #define MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH -// #define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default 256 or 384 bits) +// #define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default +// 256 or 384 bits) // */ #define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */ #define // MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /**< 1 day */ @@ -910,8 +911,8 @@ // #define MBEDTLS_SSL_CIPHERSUITES // MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 -// #define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, -// or in number of cookies issued */ +// #define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in +// seconds if HAVE_TIME, or in number of cookies issued */ /** \def MBEDTLS_SSL_DTLS_MAX_BUFFERING * @@ -1198,8 +1199,8 @@ */ // #define MBEDTLS_X509_USE_C -// #define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in bytes including the -// null terminator character ('\0'). */ #define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 /**< Maximum number of -// intermediate CAs in a verification chain. */ +// #define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in +// bytes including the null terminator character ('\0'). */ #define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 +// /**< Maximum number of intermediate CAs in a verification chain. */ /** \} name SECTION: X.509 feature selection */ diff --git a/tests/functional/stm32/nucleo_l432kc/Src/mbedtls_v4/mbedtls_platform.c b/tests/functional/stm32/nucleo_l432kc/Src/mbedtls_v4/mbedtls_platform.c index 7383d28d3..13d29a2d0 100644 --- a/tests/functional/stm32/nucleo_l432kc/Src/mbedtls_v4/mbedtls_platform.c +++ b/tests/functional/stm32/nucleo_l432kc/Src/mbedtls_v4/mbedtls_platform.c @@ -4,6 +4,7 @@ #include "main.h" #include "mbedtls/platform.h" #include "mbedtls/platform_time.h" +#include "mbedtls/platform_util.h" #include "stm32l4xx_hal.h" mbedtls_ms_time_t mbedtls_ms_time(void) @@ -13,8 +14,8 @@ mbedtls_ms_time_t mbedtls_ms_time(void) return (mbedtls_ms_time_t)HAL_GetTick(); } -int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *estimate_bits, unsigned char *output, - size_t output_size) +int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *estimate_bits, + unsigned char *output, size_t output_size) { // We don't implement any flags. if (flags != 0) { @@ -28,6 +29,7 @@ int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *e while (bytes_left) { hal_status = HAL_RNG_GenerateRandomNumber(&RNGHandle, &random_data); if (hal_status != HAL_OK) { + mbedtls_platform_zeroize(&random_data, sizeof(random_data)); return PSA_ERROR_INSUFFICIENT_ENTROPY; } @@ -39,5 +41,6 @@ int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *e *estimate_bits = 8 * output_size; + mbedtls_platform_zeroize(&random_data, sizeof(random_data)); return 0; } \ No newline at end of file diff --git a/tests/functional/stm32/nucleo_l432kc/Src/system_stm32l4xx.c b/tests/functional/stm32/nucleo_l432kc/Src/system_stm32l4xx.c index 8633cb04f..e3b652429 100644 --- a/tests/functional/stm32/nucleo_l432kc/Src/system_stm32l4xx.c +++ b/tests/functional/stm32/nucleo_l432kc/Src/system_stm32l4xx.c @@ -153,8 +153,8 @@ uint32_t SystemCoreClock = 4000000; const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; -const uint32_t MSIRangeTable[12] - = {100000, 200000, 400000, 800000, 1000000, 2000000, 4000000, 8000000, 16000000, 24000000, 32000000, 48000000}; +const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, + 4000000, 8000000, 16000000, 24000000, 32000000, 48000000}; /** * @} */ diff --git a/tests/functional/stm32/nucleo_l432kc/Src/wolfcrypt/user_settings.h b/tests/functional/stm32/nucleo_l432kc/Src/wolfcrypt/user_settings.h new file mode 100644 index 000000000..dc20ca90f --- /dev/null +++ b/tests/functional/stm32/nucleo_l432kc/Src/wolfcrypt/user_settings.h @@ -0,0 +1,26 @@ +#ifndef USER_SETTINGS_H +#define USER_SETTINGS_H + +#define WOLFCRYPT_ONLY // Build only wolfCrypt library. +#define NO_OLD_RNGNAME // Resolves collision between STM32 HAL 'RNG' and WolfSSL 'RNG'. +// #define USE_FAST_MATH + +// We will provide custom implementation for seed generation. +extern int wolfcrypt_custom_seed_gen(unsigned char *output, unsigned int sz); +#define CUSTOM_RAND_GENERATE_SEED wolfcrypt_custom_seed_gen + +#define WOLFSSL_SMALL_STACK // Offload stack usage to heap where possible. +#define WOLFSSL_MALLOC_CHECK // Optional: Safety check for malloc failures. + +#define NO_FILESYSTEM // Prevents filesystem errors on bare metal. +#undef WOLFSSL_SYS_CA_CERTS // Force disable system CA certs (fixes dirent.h / filesystem errors). +#define NO_WRITEV // IO vector write support usually missing. +#define NO_WRITE_TEMP_FILES +#define NO_DEV_RANDOM // We use STM32's RNG, not /dev/random. +#define NO_MAIN_DRIVER + +#define WOLFSSL_USER_IO // Disable the default BSD socket callbacks. + +#define SINGLE_THREADED // No threads. + +#endif /* USER_SETTINGS_H */ \ No newline at end of file diff --git a/tests/functional/stm32/nucleo_l432kc/Src/wolfcrypt/wolfcrypt_platform.c b/tests/functional/stm32/nucleo_l432kc/Src/wolfcrypt/wolfcrypt_platform.c new file mode 100644 index 000000000..52baa938b --- /dev/null +++ b/tests/functional/stm32/nucleo_l432kc/Src/wolfcrypt/wolfcrypt_platform.c @@ -0,0 +1,30 @@ +#include +#include +#include +#include + +#include "main.h" +#include "stm32l4xx_hal.h" + +int wolfcrypt_custom_seed_gen(unsigned char *output, unsigned int sz) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + uint32_t random_data; + size_t bytes_left = sz; + + while (bytes_left) { + hal_status = HAL_RNG_GenerateRandomNumber(&RNGHandle, &random_data); + if (hal_status != HAL_OK) { + wc_ForceZero(&random_data, sizeof(random_data)); + return RNG_FAILURE_E; + } + + size_t cpy_cnt = bytes_left < sizeof(random_data) ? bytes_left : sizeof(random_data); + memcpy(output, &random_data, cpy_cnt); + bytes_left -= cpy_cnt; + output += cpy_cnt; + } + + wc_ForceZero(&random_data, sizeof(random_data)); + return 0; +} \ No newline at end of file diff --git a/tests/functional/stm32/nucleo_l432kc/run_test.sh b/tests/functional/stm32/nucleo_l432kc/run_test.sh index 940987565..71c3fe0ee 100755 --- a/tests/functional/stm32/nucleo_l432kc/run_test.sh +++ b/tests/functional/stm32/nucleo_l432kc/run_test.sh @@ -88,11 +88,19 @@ trap 'cleanup' EXIT # ---- Flash the device ---- if [ -z "$STLINK_SERIAL_NUMBER" ]; then echo "OpenOCD will autodiscover STLink programming interface." - openocd -f board/st_nucleo_l4.cfg -c "program $BINARY_PATH verify reset exit" + openocd -f board/st_nucleo_l4.cfg \ + -c "gdb_port disabled" \ + -c "telnet_port disabled" \ + -c "tcl_port disabled" \ + -c "program $BINARY_PATH verify reset exit" else - OPENOCD_SERIAL_NUMBER_ARG= echo "OpenOCD will use STLink serial number $STLINK_SERIAL_NUMBER for programming." - openocd -f board/st_nucleo_l4.cfg -c "adapter serial $STLINK_SERIAL_NUMBER" -c "program $BINARY_PATH verify reset exit" + openocd -f board/st_nucleo_l4.cfg \ + -c "gdb_port disabled" \ + -c "telnet_port disabled" \ + -c "tcl_port disabled" \ + -c "adapter serial $STLINK_SERIAL_NUMBER" \ + -c "program $BINARY_PATH verify reset exit" fi # ---- Wait for serial reader to finish ---- diff --git a/tests/functional/stm32/nucleo_u545re_q/CMakeLists.txt b/tests/functional/stm32/nucleo_u545re_q/CMakeLists.txt new file mode 100644 index 000000000..11ac9023e --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/CMakeLists.txt @@ -0,0 +1,228 @@ +cmake_minimum_required(VERSION 3.21.0) +if (${CMAKE_VERSION} VERSION_GREATER "3.27") + cmake_policy(SET CMP0152 OLD) # Path resolution policy +endif() + +include (FetchContent) + +########################################################################### +# # +# Set up project and paths # +# # +########################################################################### + +# Specify stm32 device +set(STM32_DEVICE "STM32U545xx") +# Openocd config file for used nucleo board +set(OPENOCD_CFG ${CMAKE_CURRENT_SOURCE_DIR}/nucleo-u5xx.cfg) +# Path to linker script file +set(LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/STM32U545RETXQ_FLASH.ld) +# Path to toolchain file +set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_SOURCE_DIR}/toolchain.cmake) +# Paths to STM32 drivers. +# We provide a stripped-down snapshot of STM32CubeU5 repo in this example. +set(PATH_TO_STM32CUBEU5 ${CMAKE_CURRENT_SOURCE_DIR}/Vendor/STM32CubeU5/Drivers) + +# Path to Libtropic repository root +file(REAL_PATH ../../../../ PATH_LIBTROPIC) +# Path to functional tests sources directory +file(REAL_PATH ../../src/ PATH_FN_TESTS) +# Path to external dependencies +file(REAL_PATH ${CMAKE_CURRENT_SOURCE_DIR}/../_deps/ PATH_DEPS) + +if (NOT EXISTS ${PATH_DEPS}) + message(FATAL_ERROR "Dependencies not installed. Please run download_deps.sh!") +endif() + +project( + libtropic_functional_tests_stm32_nucleo_u545re_q + DESCRIPTION "Functional tests on STM32 Nucleo U545RE-Q board" + LANGUAGES C ASM) + +########################################################################### +# # +# Configuration # +# # +########################################################################### + +if (LT_CAL STREQUAL "openssl") + message(FATAL_ERROR "OpenSSL is not supported on STM32!") +endif() + +# Serial number of the STLink device which will be used for flashing. +# You need to define this only if you have multiple STM32s connected using built-in STLink, +# or if you encounter problems with OpenOCD's autodetection. +if (NOT DEFINED STLINK_SERIAL_NUMBER) + set(STLINK_SERIAL_NUMBER "") +endif() + +# Optional prefix to tests registered to CTest. Useful when running same test against +# different chips to differentiate them by their name in JUnit output. +if (NOT DEFINED CTEST_PREFIX) + set(CTEST_PREFIX "") +endif() + +########################################################################### +# # +# Add Libtropic functional tests and set them up # +# # +########################################################################### + +# MbedTLSv4 requires special configuration +if (LT_CAL STREQUAL "mbedtls_v4") + # We configure MbedTLS using config file with following configuration: + # - config.py preset "crypto_baremetal" + # - following options enabled: + # MBEDTLS_PLATFORM_MS_TIME_ALT + # MBEDTLS_HAVE_TIME + # MBEDTLS_PSA_DRIVER_GET_ENTROPY + # - following options disabled: + # MBEDTLS_PSA_BUILTIN_GET_ENTROPY + # MBEDTLS_TEST_HOOKS + # MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS + # We need to set both CMake variables and compile definitions for MbedTLS to pick up our config file. + set(MBEDTLS_CONFIG_FILE "${CMAKE_CURRENT_SOURCE_DIR}/Src/mbedtls_v4/mbedtls_config.h") + set(TF_PSA_CRYPTO_CONFIG_FILE "${CMAKE_CURRENT_SOURCE_DIR}/Src/mbedtls_v4/crypto_config.h") + add_compile_definitions(MBEDTLS_CONFIG_FILE="${MBEDTLS_CONFIG_FILE}") + add_compile_definitions(TF_PSA_CRYPTO_CONFIG_FILE="${TF_PSA_CRYPTO_CONFIG_FILE}") +endif() + +# Add path to libtropic's repository root folder +add_subdirectory(${PATH_FN_TESTS} "libtropic_functional_tests") + +# Additional configuration for WolfCrypt. +if(LT_CAL STREQUAL "wolfcrypt") + target_compile_definitions(wolfssl PUBLIC WOLFSSL_USER_SETTINGS) + # Use BUILD_INTERFACE to strictly limit this path to the build phase + target_include_directories(wolfssl PUBLIC + $ + ) +endif() + +########################################################################### +# # +# Sources # +# # +########################################################################### + +# Add Libtropic STM32 HAL +add_subdirectory("${PATH_LIBTROPIC}/hal/stm32/stm32u5xx" "stm32u5xx_hal") + +# Specify other source files +set(SOURCES + # STM32 vendor HAL, BSP + ${PATH_TO_STM32CUBEU5}/BSP/STM32U5xx_Nucleo/stm32u5xx_nucleo.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_exti.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash_ex.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpio.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c_ex.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_icache.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc_ex.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart.c + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart_ex.c + + # Project sources + ${CMAKE_CURRENT_SOURCE_DIR}/Src/main.c + ${CMAKE_CURRENT_SOURCE_DIR}/Src/stm32u5xx_it.c + ${CMAKE_CURRENT_SOURCE_DIR}/Src/stm32u5xx_hal_msp.c + ${CMAKE_CURRENT_SOURCE_DIR}/Src/system_stm32u5xx.c + ${CMAKE_CURRENT_SOURCE_DIR}/Src/startup_stm32u545retxq.s + ${CMAKE_CURRENT_SOURCE_DIR}/Src/syscalls.c + ${CMAKE_CURRENT_SOURCE_DIR}/Src/sysmem.c + + # STM32 HAL + ${LT_HAL_SRCS} +) + +# Append special sources. +if (LT_CAL STREQUAL "mbedtls_v4") + set(SOURCES ${SOURCES} + # MbedTLS platform-specific implementations + ${CMAKE_CURRENT_SOURCE_DIR}/Src/mbedtls_v4/mbedtls_platform.c + ) +elseif (LT_CAL STREQUAL "wolfcrypt") + set(SOURCES ${SOURCES} + # WolfCrypt platform-specific implementations + ${CMAKE_CURRENT_SOURCE_DIR}/Src/wolfcrypt/wolfcrypt_platform.c + ) +endif() + +# Include path for directories containing header files +set(INCLUDE_DIRS + # STM32 vendor HAL, BSP + ${PATH_TO_STM32CUBEU5}/CMSIS/Include/ + ${PATH_TO_STM32CUBEU5}/CMSIS/Device/ST/STM32U5xx/Include/ + ${PATH_TO_STM32CUBEU5}/BSP/STM32U5xx_Nucleo/ + ${PATH_TO_STM32CUBEU5}/STM32U5xx_HAL_Driver/Inc/ + + # Project includes + ${CMAKE_CURRENT_SOURCE_DIR}/Inc/ + + # STM32 HAL + ${LT_HAL_INC_DIRS} +) + +# Enable strict compile flags but exclude missing prototypes for main.c. +if(LT_STRICT_COMPILATION) + set_source_files_properties(${LT_HAL_SRCS} PROPERTIES COMPILE_OPTIONS "${LT_STRICT_COMPILATION_FLAGS}") + + # Do not enforce prototypes on main.c. + set(LT_STRICT_COMPILATION_FLAGS_NO_MISSING_PROTOTYPES ${LT_STRICT_COMPILATION_FLAGS}) + list(REMOVE_ITEM LT_STRICT_COMPILATION_FLAGS_NO_MISSING_PROTOTYPES "-Wmissing-prototypes") + set_source_files_properties(${CMAKE_CURRENT_SOURCE_DIR}/Src/main.c PROPERTIES COMPILE_OPTIONS "${LT_STRICT_COMPILATION_FLAGS_NO_MISSING_PROTOTYPES}") +endif() + + +########################################################################### +# # +# Configure test building # +# # +########################################################################### +# Enable CTest. +enable_testing() + +# Loop through tests defined in libtropic and prepare environment. +foreach(TEST_NAME IN LISTS LIBTROPIC_TEST_LIST) + + # Create a correct macro from test name. + string(TOUPPER ${TEST_NAME} TEST_MACRO) + string(REPLACE " " "_" TEST_MACRO ${TEST_MACRO}) + + set(EXE_NAME ${TEST_NAME}.elf) + + # Define executable (separate for each test) and link dependencies. + add_executable(${EXE_NAME} ${SOURCES}) + target_link_libraries(${EXE_NAME} PRIVATE libtropic_functional_tests) + target_compile_definitions(${EXE_NAME} PRIVATE -D${STM32_DEVICE}) # Configure target MCU (used by STM32 HAL) + target_include_directories(${EXE_NAME} PRIVATE ${INCLUDE_DIRS}) + # Choose correct test for the binary. + target_compile_definitions(${EXE_NAME} PRIVATE ${TEST_MACRO}) + + if(CTEST_PREFIX STREQUAL "") + set(TEST_NAME_WITH_PREFIX ${TEST_NAME}) + else() + set(TEST_NAME_WITH_PREFIX ${CTEST_PREFIX}_${TEST_NAME}) + endif() + + # Add CTest entry. + add_test(NAME ${TEST_NAME_WITH_PREFIX} + COMMAND ${CMAKE_CURRENT_SOURCE_DIR}/run_test.sh ${CMAKE_CURRENT_BINARY_DIR}/${EXE_NAME} ${STLINK_SERIAL_NUMBER} + ) + +endforeach() diff --git a/tests/functional/stm32/nucleo_u545re_q/Inc/main.h b/tests/functional/stm32/nucleo_u545re_q/Inc/main.h new file mode 100644 index 000000000..f32414be7 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Inc/main.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" +#include "stm32u5xx_nucleo.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported variables ------------------------------------------------------- */ +extern RNG_HandleTypeDef hrng; + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Inc/stm32u5xx_hal_conf.h b/tests/functional/stm32/nucleo_u545re_q/Inc/stm32u5xx_hal_conf.h new file mode 100644 index 000000000..f4e4fce3b --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Inc/stm32u5xx_hal_conf.h @@ -0,0 +1,517 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021-2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_CONF_H +#define STM32U5xx_HAL_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + +/*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_COMP_MODULE_ENABLED */ +/*#define HAL_CORDIC_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +/*#define HAL_DCACHE_MODULE_ENABLED */ +/*#define HAL_DCMI_MODULE_ENABLED */ +/*#define HAL_DMA2D_MODULE_ENABLED */ +/*#define HAL_DSI_MODULE_ENABLED */ +/*#define HAL_FDCAN_MODULE_ENABLED */ +/*#define HAL_FMAC_MODULE_ENABLED */ +/*#define HAL_GFXMMU_MODULE_ENABLED */ +/*#define HAL_GFXTIM_MODULE_ENABLED */ +/*#define HAL_GPU2D_MODULE_ENABLED */ +/*#define HAL_GTZC_MODULE_ENABLED */ +/*#define HAL_HASH_MODULE_ENABLED */ +/*#define HAL_HCD_MODULE_ENABLED */ +/*#define HAL_I2C_MODULE_ENABLED */ +#define HAL_ICACHE_MODULE_ENABLED +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_JPEG_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_LTDC_MODULE_ENABLED */ +/*#define HAL_MDF_MODULE_ENABLED */ +/*#define HAL_MMC_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_OPAMP_MODULE_ENABLED */ +/*#define HAL_OSPI_MODULE_ENABLED */ +/*#define HAL_OTFDEC_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_PKA_MODULE_ENABLED */ +/*#define HAL_PSSI_MODULE_ENABLED */ +/*#define HAL_RAMCFG_MODULE_ENABLED */ +#define HAL_RNG_MODULE_ENABLED +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SAI_MODULE_ENABLED */ +/*#define HAL_SD_MODULE_ENABLED */ +/*#define HAL_SDIO_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +/*#define HAL_SRAM_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +/*#define HAL_TSC_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +/*#define HAL_XSPI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined(HSE_VALUE) +#define HSE_VALUE 16000000UL /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined(HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined(MSI_VALUE) +#define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined(HSI_VALUE) +#define HSI_VALUE 16000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined(HSI48_VALUE) +#define HSI48_VALUE \ + 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. \ + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined(LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz. The real value may \ +vary depending on the variations in voltage and temperature.*/ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined(LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined(LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for SAI1 peripheral + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * frequency. + */ +#if !defined(EXTERNAL_SAI1_CLOCK_VALUE) +#define EXTERNAL_SAI1_CLOCK_VALUE 48000UL /*!< Value of the SAI1 External clock source in Hz*/ +#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U /*!< Enable prefetch */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/unregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32u5xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */ +#define USE_HAL_GFXTIM_REGISTER_CALLBACKS 0U /* GFXTIM register callback disabled */ +#define USE_HAL_GPU2D_REGISTER_CALLBACKS 0U /* GPU2D register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MDF_REGISTER_CALLBACKS 0U /* MDF register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */ +#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SDIO_REGISTER_CALLBACKS 0U /* SDIO register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ +#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OSPI register callback disabled */ +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ +#define USE_SPI_CRC 0U + +/* ################## SDMMC peripheral configuration ######################### */ + +#define USE_SD_TRANSCEIVER 0U + +/* ################## SDIO peripheral configuration ########################## */ +#define USE_SDIO_TRANSCEIVER 0U +#define SDIO_MAX_IO_NUMBER 7U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32u5xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32u5xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_ICACHE_MODULE_ENABLED +#include "stm32u5xx_hal_icache.h" +#endif /* HAL_ICACHE_MODULE_ENABLED */ + +#ifdef HAL_DCACHE_MODULE_ENABLED +#include "stm32u5xx_hal_dcache.h" +#endif /* HAL_DCACHE_MODULE_ENABLED */ + +#ifdef HAL_GTZC_MODULE_ENABLED +#include "stm32u5xx_hal_gtzc.h" +#endif /* HAL_GTZC_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32u5xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED +#include "stm32u5xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED +#include "stm32u5xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32u5xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED +#include "stm32u5xx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32u5xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED +#include "stm32u5xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32u5xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32u5xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED +#include "stm32u5xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED +#include "stm32u5xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED +#include "stm32u5xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED +#include "stm32u5xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED +#include "stm32u5xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED +#include "stm32u5xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32u5xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32u5xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32u5xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED +#include "stm32u5xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32u5xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED +#include "stm32u5xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED +#include "stm32u5xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32u5xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_OSPI_MODULE_ENABLED +#include "stm32u5xx_hal_ospi.h" +#endif /* HAL_OSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32u5xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32u5xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED +#include "stm32u5xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED +#include "stm32u5xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SDIO_MODULE_ENABLED +#include "stm32u5xx_hal_sdio.h" +#endif /* HAL_SDIO_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32u5xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32u5xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32u5xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_TSC_MODULE_ENABLED +#include "stm32u5xx_hal_tsc.h" +#endif /* HAL_TSC_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32u5xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32u5xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32u5xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32u5xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32u5xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32u5xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32u5xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_CORDIC_MODULE_ENABLED +#include "stm32u5xx_hal_cordic.h" +#endif /* HAL_CORDIC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED +#include "stm32u5xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32u5xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED +#include "stm32u5xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_FMAC_MODULE_ENABLED +#include "stm32u5xx_hal_fmac.h" +#endif /* HAL_FMAC_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED +#include "stm32u5xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_GFXTIM_MODULE_ENABLED +#include "stm32u5xx_hal_gfxtim.h" +#endif /* HAL_GFXTIM_MODULE_ENABLED */ + +#ifdef HAL_GPU2D_MODULE_ENABLED +#include "stm32u5xx_hal_gpu2d.h" +#endif /* HAL_GPU2D_MODULE_ENABLED */ + +#ifdef HAL_OTFDEC_MODULE_ENABLED +#include "stm32u5xx_hal_otfdec.h" +#endif /* HAL_OTFDEC_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED +#include "stm32u5xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_RAMCFG_MODULE_ENABLED +#include "stm32u5xx_hal_ramcfg.h" +#endif /* HAL_RAMCFG_MODULE_ENABLED */ + +#ifdef HAL_MDF_MODULE_ENABLED +#include "stm32u5xx_hal_mdf.h" +#endif /* HAL_MDF_MODULE_ENABLED */ + +#ifdef HAL_XSPI_MODULE_ENABLED +#include "stm32u5xx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_CONF_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Inc/stm32u5xx_it.h b/tests/functional/stm32/nucleo_u545re_q/Inc/stm32u5xx_it.h new file mode 100644 index 000000000..3f69304b6 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Inc/stm32u5xx_it.h @@ -0,0 +1,66 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32u5xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32U5xx_IT_H +#define __STM32U5xx_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32U5xx_IT_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Inc/stm32u5xx_nucleo_conf.h b/tests/functional/stm32/nucleo_u545re_q/Inc/stm32u5xx_nucleo_conf.h new file mode 100644 index 000000000..5e6a47266 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Inc/stm32u5xx_nucleo_conf.h @@ -0,0 +1,79 @@ + +/** + ****************************************************************************** + * @file stm32u5xx_nucleo_conf.h + * @author MCD Application Team + * @brief STM32U5xx_Nucleo board configuration file. + * This file should be copied to the application folder and renamed + * to stm32u5xx_nucleo_conf.h + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5XX_NUCLEO_CONF_H +#define STM32U5XX_NUCLEO_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32U5XX_NUCLEO + * @{ + */ + +/** @defgroup STM32U5XX_NUCLEO_CONFIG Config + * @{ + */ + +/** @defgroup STM32C0XX_NUCLEO_CONFIG_Exported_Constants Exported Constants + * @{ + */ +/* Nucleo pin and part number defines */ +#define USE_STM32U5XX_NUCLEO +#define USE_NUCLEO_64 + +/* COM define */ +#define USE_COM_LOG 0U +#define USE_BSP_COM_FEATURE 0U + +/* IRQ priorities */ +#define BSP_BUTTON_USER_IT_PRIORITY 15U + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5XX_NUCLEO_CONF_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/SLA0048_STM32CubeMX.pdf b/tests/functional/stm32/nucleo_u545re_q/SLA0048_STM32CubeMX.pdf new file mode 100644 index 000000000..6e700a699 Binary files /dev/null and b/tests/functional/stm32/nucleo_u545re_q/SLA0048_STM32CubeMX.pdf differ diff --git a/tests/functional/stm32/nucleo_u545re_q/STM32U545RETXQ_FLASH.ld b/tests/functional/stm32/nucleo_u545re_q/STM32U545RETXQ_FLASH.ld new file mode 100644 index 000000000..f5163cc13 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/STM32U545RETXQ_FLASH.ld @@ -0,0 +1,166 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32U545xE Device from STM32U5 series +** 512Kbytes FLASH +** 272Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +** Copyright (c) 2025 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K + SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + KEEP(*(.isr_vector)) /* Startup code */ + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/tests/functional/stm32/nucleo_u545re_q/Src/main.c b/tests/functional/stm32/nucleo_u545re_q/Src/main.c new file mode 100644 index 000000000..ad6676ec7 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Src/main.c @@ -0,0 +1,365 @@ +/** + * @file main.c + * @brief Wrapper project for running Libtropic functional test suite on Nucleo U545RE-Q. + * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. + * + * @license For the license see LICENSE.md in the root directory of this source tree. + */ + +// This file was generated using Stm32CubeMX and modified by Tropic Square to run Libtropic +// functional tests. + +/** + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +#include +#include + +#include "libtropic.h" +#include "libtropic_functional_tests.h" +#include "libtropic_logging.h" +#include "libtropic_port_stm32u5xx.h" +#include "lt_test_common.h" + +#if LT_USE_TREZOR_CRYPTO +#include "libtropic_trezor_crypto.h" +#define CRYPTO_CTX_TYPE lt_ctx_trezor_crypto_t +#elif LT_USE_MBEDTLS_V4 +#include "libtropic_mbedtls_v4.h" +#include "psa/crypto.h" +#define CRYPTO_CTX_TYPE lt_ctx_mbedtls_v4_t +#elif LT_USE_WOLFCRYPT +#include "libtropic_wolfcrypt.h" +#include "wolfssl/wolfcrypt/error-crypt.h" +#include "wolfssl/wolfcrypt/wc_port.h" +#define CRYPTO_CTX_TYPE lt_ctx_wolfcrypt_t +#endif + +/* Private variables ---------------------------------------------------------*/ +/* RNG handle declaration */ +RNG_HandleTypeDef hrng; + +/* UART handle declaration */ +UART_HandleTypeDef huart1; + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void SystemPower_Config(void); +static void MX_GPIO_Init(void); +static void MX_ICACHE_Init(void); +static void MX_RNG_Init(void); +static void MX_USART1_UART_Init(void); + +#if defined(__ICCARM__) +/* New definition from EWARM V9, compatible with EWARM8 */ +int iar_fputc(int ch); +#define PUTCHAR_PROTOTYPE int iar_fputc(int ch) +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +/* ARM Compiler 5/6*/ +#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#elif defined(__GNUC__) +#define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#endif /* __ICCARM__ */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* Configure the System Power */ + SystemPower_Config(); + + /* Configure the system clock */ + SystemClock_Config(); + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_ICACHE_Init(); + MX_RNG_Init(); + MX_USART1_UART_Init(); + + /* libtropic related code BEGIN */ + /* libtropic related code BEGIN */ + /* libtropic related code BEGIN */ + /* libtropic related code BEGIN */ + /* libtropic related code BEGIN */ + + /* Cryptographic function provider initialization. */ +#if LT_USE_MBEDTLS_V4 + psa_status_t status = psa_crypto_init(); + if (status != PSA_SUCCESS) { + LT_LOG_ERROR("PSA Crypto initialization failed, status=%d (psa_status_t)", status); + return -1; + } +#elif LT_USE_WOLFCRYPT + int ret = wolfCrypt_Init(); + if (ret != 0) { + LT_LOG_ERROR("WolfCrypt initialization failed, ret=%d (%s)", ret, wc_GetErrorString(ret)); + return ret; + } +#endif + + /* Libtropic handle initialization */ + lt_handle_t lt_handle = {0}; + + /* Device mappings */ + lt_dev_stm32u5xx_t device = {0}; + + device.spi_instance = SPI1; + device.baudrate_prescaler = SPI_BAUDRATEPRESCALER_2; + device.spi_cs_gpio_bank = GPIOC; + device.spi_cs_gpio_pin = GPIO_PIN_9; + device.rng_handle = &hrng; + +#ifdef LT_USE_INT_PIN + device.int_gpio_bank = GPIOC; + device.int_gpio_pin = GPIO_PIN_8; +#endif + + lt_handle.l2.device = &device; + + /* Crypto abstraction layer (CAL) context (selectable). */ + CRYPTO_CTX_TYPE crypto_ctx; + lt_handle.l3.crypto_ctx = &crypto_ctx; + + /* Test code (correct test function is selected automatically per binary) + __lt_handle__ identifier is used by the test registry. */ + lt_handle_t *__lt_handle__ = <_handle; +#include "lt_test_registry.c.inc" + + /* Cryptographic function provider deinitialization. */ +#if LT_USE_MBEDTLS_V4 + mbedtls_psa_crypto_free(); +#elif LT_USE_WOLFCRYPT + ret = wolfCrypt_Cleanup(); + if (ret != 0) { + LT_LOG_ERROR("WolfCrypt cleanup failed, ret=%d (%s)", ret, wc_GetErrorString(ret)); + return ret; + } +#endif + + /* Inform the test runner that the test finished */ + LT_FINISH_TEST(); + + /* libtropic related code END */ + /* libtropic related code END */ + /* libtropic related code END */ + /* libtropic related code END */ + /* libtropic related code END */ + + /* Not strictly necessary, but we deinitialize RNG here to demonstrate proper usage. */ + if (HAL_RNG_DeInit(&hrng) != HAL_OK) { + Error_Handler(); + } + + while (1) { + } +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 10; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 1; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_0; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | + RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + Error_Handler(); + } +} + +/** + * @brief Power Configuration + * @retval None + */ +static void SystemPower_Config(void) +{ + /* + * Switch to SMPS regulator instead of LDO + */ + if (HAL_PWREx_ConfigSupply(PWR_SMPS_SUPPLY) != HAL_OK) { + Error_Handler(); + } +} + +/** + * @brief ICACHE Initialization Function + * @param None + * @retval None + */ +static void MX_ICACHE_Init(void) +{ + /** Enable instruction cache in 1-way (direct mapped cache) + */ + if (HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY) != HAL_OK) { + Error_Handler(); + } + if (HAL_ICACHE_Enable() != HAL_OK) { + Error_Handler(); + } +} + +/** + * @brief RNG Initialization Function + * @param None + * @retval None + */ +static void MX_RNG_Init(void) +{ + hrng.Instance = RNG; + hrng.Init.ClockErrorDetection = RNG_CED_ENABLE; + if (HAL_RNG_Init(&hrng) != HAL_OK) { + Error_Handler(); + } +} + +/** + * @brief USART1 Initialization Function + * @param None + * @retval None + */ +static void MX_USART1_UART_Init(void) +{ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart1) != HAL_OK) { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) { + Error_Handler(); + } + if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) { + Error_Handler(); + } +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); +} + +/** + * @brief Retargets the C library printf function to the USART. + * @param None + * @retval None + */ +PUTCHAR_PROTOTYPE +{ + /* Translates LF to CFLF, as this is what most serial monitors expect + by default + */ + if (ch == '\n') { + HAL_UART_Transmit(&huart1, (uint8_t *)"\r\n", 2, 0xFFFF); + } + else { + HAL_UART_Transmit(&huart1, (uint8_t *)&ch, 1, 0xFFFF); + } + + return ch; +} + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + __disable_irq(); + while (1) { + } +} +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) { + } +} +#endif /* USE_FULL_ASSERT */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Src/mbedtls_v4/crypto_config.h b/tests/functional/stm32/nucleo_u545re_q/Src/mbedtls_v4/crypto_config.h new file mode 100644 index 000000000..4939948db --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Src/mbedtls_v4/crypto_config.h @@ -0,0 +1,2002 @@ +/** + * \file psa/crypto_config.h + * \brief PSA crypto configuration options (set of defines) + * + */ +/** + * This file determines which cryptographic mechanisms are enabled + * through the PSA Cryptography API (\c psa_xxx() functions). + * + * To enable a cryptographic mechanism, uncomment the definition of + * the corresponding \c PSA_WANT_xxx preprocessor symbol. + * To disable a cryptographic mechanism, comment out the definition of + * the corresponding \c PSA_WANT_xxx preprocessor symbol. + * The names of cryptographic mechanisms correspond to values + * defined in psa/crypto_values.h, with the prefix \c PSA_WANT_ instead + * of \c PSA_. + * + * Note that many cryptographic mechanisms involve two symbols: one for + * the key type (\c PSA_WANT_KEY_TYPE_xxx) and one for the algorithm + * (\c PSA_WANT_ALG_xxx). Mechanisms with additional parameters may involve + * additional symbols. + */ + +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + */ + +#ifndef PSA_CRYPTO_CONFIG_H +#define PSA_CRYPTO_CONFIG_H + +/** + * This is an optional version symbol that enables compatibility handling of + * config files. + * + * It is equal to the #TF_PSA_CRYPTO_VERSION_NUMBER of the TF-PSA-Crypto + * version introduced the config format we want to be compatible with. + */ +#define TF_PSA_CRYPTO_CONFIG_VERSION 0x01000000 + +/** + * \name SECTION: SECTION Cryptographic mechanism selection (PSA API) + * + * This section sets PSA API settings. + * \{ + */ + +#define PSA_WANT_ALG_CBC_NO_PADDING 1 +#define PSA_WANT_ALG_CBC_PKCS7 1 +#define PSA_WANT_ALG_CCM 1 +#define PSA_WANT_ALG_CCM_STAR_NO_TAG 1 +#define PSA_WANT_ALG_CMAC 1 +#define PSA_WANT_ALG_CFB 1 +#define PSA_WANT_ALG_CHACHA20_POLY1305 1 +#define PSA_WANT_ALG_CTR 1 +#define PSA_WANT_ALG_DETERMINISTIC_ECDSA 1 +#define PSA_WANT_ALG_ECB_NO_PADDING 1 +#define PSA_WANT_ALG_ECDH 1 +#define PSA_WANT_ALG_FFDH 1 +#define PSA_WANT_ALG_ECDSA 1 +#define PSA_WANT_ALG_JPAKE 1 +#define PSA_WANT_ALG_GCM 1 +#define PSA_WANT_ALG_HKDF 1 +#define PSA_WANT_ALG_HKDF_EXTRACT 1 +#define PSA_WANT_ALG_HKDF_EXPAND 1 +#define PSA_WANT_ALG_HMAC 1 +#define PSA_WANT_ALG_MD5 1 +#define PSA_WANT_ALG_OFB 1 +#define PSA_WANT_ALG_PBKDF2_HMAC 1 +#define PSA_WANT_ALG_PBKDF2_AES_CMAC_PRF_128 1 +#define PSA_WANT_ALG_RIPEMD160 1 +#define PSA_WANT_ALG_RSA_OAEP 1 +#define PSA_WANT_ALG_RSA_PKCS1V15_CRYPT 1 +#define PSA_WANT_ALG_RSA_PKCS1V15_SIGN 1 +#define PSA_WANT_ALG_RSA_PSS 1 +#define PSA_WANT_ALG_SHA_1 1 +#define PSA_WANT_ALG_SHA_224 1 +#define PSA_WANT_ALG_SHA_256 1 +#define PSA_WANT_ALG_SHA_384 1 +#define PSA_WANT_ALG_SHA_512 1 +#define PSA_WANT_ALG_SHA3_224 1 +#define PSA_WANT_ALG_SHA3_256 1 +#define PSA_WANT_ALG_SHA3_384 1 +#define PSA_WANT_ALG_SHA3_512 1 +#define PSA_WANT_ALG_STREAM_CIPHER 1 +#define PSA_WANT_ALG_TLS12_PRF 1 +#define PSA_WANT_ALG_TLS12_PSK_TO_MS 1 +#define PSA_WANT_ALG_TLS12_ECJPAKE_TO_PMS 1 + +#define PSA_WANT_ECC_BRAINPOOL_P_R1_256 1 +#define PSA_WANT_ECC_BRAINPOOL_P_R1_384 1 +#define PSA_WANT_ECC_BRAINPOOL_P_R1_512 1 +#define PSA_WANT_ECC_MONTGOMERY_255 1 +#define PSA_WANT_ECC_MONTGOMERY_448 1 +#define PSA_WANT_ECC_SECP_K1_256 1 +/* For secp256r1, consider enabling #MBEDTLS_PSA_P256M_DRIVER_ENABLED + * (see the description in psa/crypto_config.h for details). */ +#define PSA_WANT_ECC_SECP_R1_256 1 +#define PSA_WANT_ECC_SECP_R1_384 1 +#define PSA_WANT_ECC_SECP_R1_521 1 +/* These 2 curves are not part of the public API. They are kept temporarily for + * internal testing only and will removed in a future minor version. */ +#define PSA_WANT_ECC_SECP_K1_192 1 +#define PSA_WANT_ECC_SECP_R1_192 1 + +#define PSA_WANT_DH_RFC7919_2048 1 +#define PSA_WANT_DH_RFC7919_3072 1 +#define PSA_WANT_DH_RFC7919_4096 1 +#define PSA_WANT_DH_RFC7919_6144 1 +#define PSA_WANT_DH_RFC7919_8192 1 + +#define PSA_WANT_KEY_TYPE_DERIVE 1 +#define PSA_WANT_KEY_TYPE_PASSWORD 1 +#define PSA_WANT_KEY_TYPE_PASSWORD_HASH 1 +#define PSA_WANT_KEY_TYPE_HMAC 1 +#define PSA_WANT_KEY_TYPE_AES 1 +#define PSA_WANT_KEY_TYPE_ARIA 1 +#define PSA_WANT_KEY_TYPE_CAMELLIA 1 +#define PSA_WANT_KEY_TYPE_CHACHA20 1 +#define PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY 1 +#define PSA_WANT_KEY_TYPE_DH_PUBLIC_KEY 1 +#define PSA_WANT_KEY_TYPE_RAW_DATA 1 +#define PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY 1 + +/* + * The following symbols extend and deprecate the legacy + * PSA_WANT_KEY_TYPE_xxx_KEY_PAIR ones. They include the usage of that key in + * the name's suffix. "_USE" is the most generic and it can be used to describe + * a generic suport, whereas other ones add more features on top of that and + * they are more specific. + */ +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE 1 + +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC 1 +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT 1 +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT 1 +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE 1 +// #define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_DERIVE 1 /* Not supported */ + +#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC 1 +#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_IMPORT 1 +#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_EXPORT 1 +#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE 1 +// #define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_DERIVE 1 /* Not supported */ +/** \} name SECTION Cryptographic mechanism selection (PSA API) */ + +/** + * \name SECTION: Platform abstraction layer + * + * This section sets platform specific settings. + * \{ + */ + +/** + * \def MBEDTLS_MEMORY_BUFFER_ALLOC_C + * + * Enable the buffer allocator implementation that makes use of a (stack) + * based buffer to 'allocate' dynamic memory. (replaces calloc() and free() + * calls) + * + * Module: drivers/builtin/src/memory_buffer_alloc.c + * + * Requires: MBEDTLS_PLATFORM_C + * MBEDTLS_PLATFORM_MEMORY (to use it within Mbed TLS) + * + * Enable this module to enable the buffer memory allocator. + */ +// #define MBEDTLS_MEMORY_BUFFER_ALLOC_C + +/** + * \def MBEDTLS_FS_IO + * + * Enable functions that use the filesystem. + */ +// #define MBEDTLS_FS_IO + +/** + * \def MBEDTLS_HAVE_TIME + * + * System has time.h and time(). + * The time does not need to be correct, only time differences are used, + * by contrast with MBEDTLS_HAVE_TIME_DATE + * + * Defining MBEDTLS_HAVE_TIME allows you to specify MBEDTLS_PLATFORM_TIME_ALT, + * MBEDTLS_PLATFORM_TIME_MACRO, MBEDTLS_PLATFORM_TIME_TYPE_MACRO and + * MBEDTLS_PLATFORM_STD_TIME. + * + * Comment if your system does not support time functions. + */ +#define MBEDTLS_HAVE_TIME + +/** + * \def MBEDTLS_HAVE_TIME_DATE + * + * System has time.h, time(), and an implementation for + * mbedtls_platform_gmtime_r() (see below). + * The time needs to be correct (not necessarily very accurate, but at least + * the date should be correct). This is used to verify the validity period of + * X.509 certificates. + * + * Comment if your system does not have a correct clock. + * + * \note mbedtls_platform_gmtime_r() is an abstraction in platform_util.h that + * behaves similarly to the gmtime_r() function from the C standard. Refer to + * the documentation for mbedtls_platform_gmtime_r() for more information. + * + * \note It is possible to configure an implementation for + * mbedtls_platform_gmtime_r() at compile-time by using the macro + * MBEDTLS_PLATFORM_GMTIME_R_ALT. + */ +// #define MBEDTLS_HAVE_TIME_DATE + +/** + * \def MBEDTLS_MEMORY_DEBUG + * + * Enable debugging of buffer allocator memory issues. Automatically prints + * (to stderr) all (fatal) messages on memory allocation issues. Enables + * function for 'debug output' of allocated memory. + * + * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C + * + * Uncomment this macro to let the buffer allocator print out error messages. + */ +// #define MBEDTLS_MEMORY_DEBUG + +/** + * \def MBEDTLS_MEMORY_BACKTRACE + * + * Include backtrace information with each allocated block. + * + * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C + * GLIBC-compatible backtrace() and backtrace_symbols() support + * + * Uncomment this macro to include backtrace information + */ +// #define MBEDTLS_MEMORY_BACKTRACE + +/** + * \def MBEDTLS_PLATFORM_C + * + * Enable the platform abstraction layer that allows you to re-assign + * functions like calloc(), free(), snprintf(), printf(), fprintf(), exit(). + * + * Enabling MBEDTLS_PLATFORM_C enables to use of MBEDTLS_PLATFORM_XXX_ALT + * or MBEDTLS_PLATFORM_XXX_MACRO directives, allowing the functions mentioned + * above to be specified at runtime or compile time respectively. + * + * \note This abstraction layer must be enabled on Windows (including MSYS2) + * as other modules rely on it for a fixed snprintf implementation. + * + * Module: drivers/builtin/src/platform.c + * Caller: Most other .c files + * + * This module enables abstraction of common (libc) functions. + */ +#define MBEDTLS_PLATFORM_C + +/** + * \def MBEDTLS_PLATFORM_EXIT_ALT + * + * MBEDTLS_PLATFORM_XXX_ALT: Uncomment a macro to let Mbed TLS support the + * function in the platform abstraction layer. + * + * Example: In case you uncomment MBEDTLS_PLATFORM_PRINTF_ALT, Mbed TLS will + * provide a function "mbedtls_platform_set_printf()" that allows you to set an + * alternative printf function pointer. + * + * All these define require MBEDTLS_PLATFORM_C to be defined! + * + * \note MBEDTLS_PLATFORM_SNPRINTF_ALT is required on Windows; + * it will be enabled automatically by check_config.h + * + * \warning MBEDTLS_PLATFORM_XXX_ALT cannot be defined at the same time as + * MBEDTLS_PLATFORM_XXX_MACRO! + * + * Requires: MBEDTLS_PLATFORM_TIME_ALT requires MBEDTLS_HAVE_TIME + * + * Uncomment a macro to enable alternate implementation of specific base + * platform function + */ +#define MBEDTLS_PLATFORM_SETBUF_ALT +#define MBEDTLS_PLATFORM_EXIT_ALT +// #define MBEDTLS_PLATFORM_TIME_ALT +// #define MBEDTLS_PLATFORM_FPRINTF_ALT +#define MBEDTLS_PLATFORM_PRINTF_ALT +#define MBEDTLS_PLATFORM_SNPRINTF_ALT +#define MBEDTLS_PLATFORM_VSNPRINTF_ALT +// #define MBEDTLS_PLATFORM_NV_SEED_ALT +// #define MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT +#define MBEDTLS_PLATFORM_MS_TIME_ALT + +/** + * Uncomment the macro to let Mbed TLS use your alternate implementation of + * mbedtls_platform_gmtime_r(). This replaces the default implementation in + * platform_util.c. + * + * gmtime() is not a thread-safe function as defined in the C standard. The + * library will try to use safer implementations of this function, such as + * gmtime_r() when available. However, if Mbed TLS cannot identify the target + * system, the implementation of mbedtls_platform_gmtime_r() will default to + * using the standard gmtime(). In this case, calls from the library to + * gmtime() will be guarded by the global mutex mbedtls_threading_gmtime_mutex + * if MBEDTLS_THREADING_C is enabled. We recommend that calls from outside the + * library are also guarded with this mutex to avoid race conditions. However, + * if the macro MBEDTLS_PLATFORM_GMTIME_R_ALT is defined, Mbed TLS will + * unconditionally use the implementation for mbedtls_platform_gmtime_r() + * supplied at compile time. + */ +// #define MBEDTLS_PLATFORM_GMTIME_R_ALT + +/** + * \def MBEDTLS_PLATFORM_MEMORY + * + * Enable the memory allocation layer. + * + * By default Mbed TLS uses the system-provided calloc() and free(). + * This allows different allocators (self-implemented or provided) to be + * provided to the platform abstraction layer. + * + * Enabling #MBEDTLS_PLATFORM_MEMORY without the + * MBEDTLS_PLATFORM_{FREE,CALLOC}_MACROs will provide + * "mbedtls_platform_set_calloc_free()" allowing you to set an alternative calloc() and + * free() function pointer at runtime. + * + * Enabling #MBEDTLS_PLATFORM_MEMORY and specifying + * MBEDTLS_PLATFORM_{CALLOC,FREE}_MACROs will allow you to specify the + * alternate function at compile time. + * + * An overview of how the value of mbedtls_calloc is determined: + * + * - if !MBEDTLS_PLATFORM_MEMORY + * - mbedtls_calloc = calloc + * - if MBEDTLS_PLATFORM_MEMORY + * - if (MBEDTLS_PLATFORM_CALLOC_MACRO && MBEDTLS_PLATFORM_FREE_MACRO): + * - mbedtls_calloc = MBEDTLS_PLATFORM_CALLOC_MACRO + * - if !(MBEDTLS_PLATFORM_CALLOC_MACRO && MBEDTLS_PLATFORM_FREE_MACRO): + * - Dynamic setup via mbedtls_platform_set_calloc_free is now possible with a default value + * MBEDTLS_PLATFORM_STD_CALLOC. + * - How is MBEDTLS_PLATFORM_STD_CALLOC handled? + * - if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS: + * - MBEDTLS_PLATFORM_STD_CALLOC is not set to anything; + * - MBEDTLS_PLATFORM_STD_MEM_HDR can be included if present; + * - if !MBEDTLS_PLATFORM_NO_STD_FUNCTIONS: + * - if MBEDTLS_PLATFORM_STD_CALLOC is present: + * - User-defined MBEDTLS_PLATFORM_STD_CALLOC is respected; + * - if !MBEDTLS_PLATFORM_STD_CALLOC: + * - MBEDTLS_PLATFORM_STD_CALLOC = calloc + * + * - At this point the presence of MBEDTLS_PLATFORM_STD_CALLOC is checked. + * - if !MBEDTLS_PLATFORM_STD_CALLOC + * - MBEDTLS_PLATFORM_STD_CALLOC = uninitialized_calloc + * + * - mbedtls_calloc = MBEDTLS_PLATFORM_STD_CALLOC. + * + * Defining MBEDTLS_PLATFORM_CALLOC_MACRO and #MBEDTLS_PLATFORM_STD_CALLOC at the same time is not + * possible. MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO must both be defined or + * undefined at the same time. #MBEDTLS_PLATFORM_STD_CALLOC and #MBEDTLS_PLATFORM_STD_FREE do not have + * to be defined at the same time, as, if they are used, dynamic setup of these functions is possible. + * See the tree above to see how are they handled in all cases. An uninitialized + * #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. An uninitialized + * #MBEDTLS_PLATFORM_STD_FREE does not do anything. + * + * Requires: MBEDTLS_PLATFORM_C + * + * Enable this layer to allow use of alternative memory allocators. + */ +#define MBEDTLS_PLATFORM_MEMORY + +/** + * \def MBEDTLS_PLATFORM_NO_STD_FUNCTIONS + * + * Do not assign standard functions in the platform layer (e.g. calloc() to + * MBEDTLS_PLATFORM_STD_CALLOC and printf() to MBEDTLS_PLATFORM_STD_PRINTF) + * + * This makes sure there are no linking errors on platforms that do not support + * these functions. You will HAVE to provide alternatives, either at runtime + * via the platform_set_xxx() functions or at compile time by setting + * the MBEDTLS_PLATFORM_STD_XXX defines, or enabling a + * MBEDTLS_PLATFORM_XXX_MACRO. + * + * Requires: MBEDTLS_PLATFORM_C + * + * Uncomment to prevent default assignment of standard functions in the + * platform layer. + */ +// #define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS + +/** + * Uncomment the macro to let Mbed TLS use your alternate implementation of + * mbedtls_platform_zeroize(), to wipe sensitive data in memory. This replaces + * the default implementation in platform_util.c. + * + * By default, the library uses a system function such as memset_s() + * (optional feature of C11), explicit_bzero() (BSD and compatible), or + * SecureZeroMemory (Windows). If no such function is detected, the library + * falls back to a plain C implementation. Compilers are technically + * permitted to optimize this implementation out, meaning that the memory is + * not actually wiped. The library tries to prevent that, but the C language + * makes it impossible to guarantee that the memory will always be wiped. + * + * If your platform provides a guaranteed method to wipe memory which + * `platform_util.c` does not detect, define this macro to the name of + * a function that takes two arguments, a `void *` pointer and a length, + * and wipes that many bytes starting at the specified address. For example, + * if your platform has explicit_bzero() but `platform_util.c` does not + * detect its presence, define `MBEDTLS_PLATFORM_ZEROIZE_ALT` to be + * `explicit_bzero` to use that function as mbedtls_platform_zeroize(). + */ +// #define MBEDTLS_PLATFORM_ZEROIZE_ALT + +/** + * \def MBEDTLS_THREADING_ALT + * + * Provide your own alternate implementation of threading primitives: + * mutexes and condition variables. If you enable this option: + * + * - Provide a header file `"threading_alt.h"`, defining the following + * elements: + * - The type `mbedtls_platform_mutex_t` of mutex objects. + * - The type `mbedtls_platform_condition_variable_t` of + * condition variable objects. + * + * - Call the function mbedtls_threading_set_alt() in your application + * before calling any other library function (in particular before + * calling psa_crypto_init()). + * + * See mbedtls/threading.h for more details, especially the documentation + * of mbedtls_threading_set_alt(). + * + * Requires: MBEDTLS_THREADING_C + * + * Uncomment this to allow your own alternate threading implementation. + */ +// #define MBEDTLS_THREADING_ALT + +/** + * \def MBEDTLS_THREADING_PTHREAD + * + * Enable the pthread wrapper layer for the threading layer. + * + * Requires: MBEDTLS_THREADING_C + * + * Uncomment this to enable pthread mutexes. + */ +// #define MBEDTLS_THREADING_PTHREAD + +/** + * \def MBEDTLS_THREADING_C + * + * Enable the threading abstraction layer. + * + * \note You must enable this option if TF-PSA-Crypto runs in a + * multithreaded environment. Otherwise the PSA cryptography subsystem is + * not thread-safe. As an exception, this option can be disabled if all + * PSA crypto functions are ever called from a single thread. Note that + * this includes indirect calls, for example through PK. + * + * Module: drivers/builtin/src/threading.c + * + * This allows different threading implementations (built-in or + * provided externally). + * + * You will have to enable either #MBEDTLS_THREADING_ALT or + * #MBEDTLS_THREADING_PTHREAD. + * + * Enable this layer to allow use of mutexes within Mbed TLS + */ +// #define MBEDTLS_THREADING_C + +/* Memory buffer allocator options */ +// #define MBEDTLS_MEMORY_ALIGN_MULTIPLE 4 /**< Align on multiples of this value */ + +/* To use the following function macros, MBEDTLS_PLATFORM_C must be enabled. */ +/* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */ +// #define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be +// undefined. See MBEDTLS_PLATFORM_STD_CALLOC for requirements. */ #define MBEDTLS_PLATFORM_EXIT_MACRO +// exit /**< Default exit macro to use, can be undefined */ #define MBEDTLS_PLATFORM_FREE_MACRO free +// /**< Default free macro to use, can be undefined. See MBEDTLS_PLATFORM_STD_FREE for requirements. */ +// #define MBEDTLS_PLATFORM_FPRINTF_MACRO fprintf /**< Default fprintf macro to use, can be undefined +// */ #define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t +// //#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t /**< Default milliseconds time macro to use, +// can be undefined. MBEDTLS_HAVE_TIME must be enabled. It must be signed, and at least 64 bits. If it +// is changed from the default, MBEDTLS_PRINTF_MS_TIME must be updated to match.*/ #define +// MBEDTLS_PLATFORM_NV_SEED_READ_MACRO mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read +// function to use, can be undefined */ #define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO +// mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +// #define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be +// undefined */ #define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf /**< Default setbuf macro to use, can +// be undefined */ +/* Note: your snprintf must correctly zero-terminate the buffer! */ +// #define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be +// undefined */ + +/** \def MBEDTLS_PLATFORM_STD_CALLOC + * + * Default allocator to use, can be undefined. + * It must initialize the allocated buffer memory to zeroes. + * The size of the buffer is the product of the two parameters. + * The calloc function returns either a null pointer or a pointer to the allocated space. + * If the product is 0, the function may either return NULL or a valid pointer to an array of size 0 + * which is a valid input to the deallocation function. An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC + * always fails, returning a null pointer. See the description of #MBEDTLS_PLATFORM_MEMORY for more + * details. The corresponding deallocation function is #MBEDTLS_PLATFORM_STD_FREE. + */ +// #define MBEDTLS_PLATFORM_STD_CALLOC calloc + +// #define MBEDTLS_PLATFORM_STD_EXIT exit /**< Default exit to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined +// */ #define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be +// undefined */ #define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be +// undefined */ + +/** \def MBEDTLS_PLATFORM_STD_FREE + * + * Default free to use, can be undefined. + * NULL is a valid parameter, and the function must do nothing. + * A non-null parameter will always be a pointer previously returned by #MBEDTLS_PLATFORM_STD_CALLOC + * and not yet freed. An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. See the + * description of #MBEDTLS_PLATFORM_MEMORY for more details (same principles as for + * MBEDTLS_PLATFORM_STD_CALLOC apply). + */ +// #define MBEDTLS_PLATFORM_STD_FREE free + +// #define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if +// MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */ #define +// MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file to read/write with default +// implementation */ #define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read /**< +// Default nv_seed_read function to use, can be undefined */ #define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE +// mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_SETBUF setbuf /**< Default setbuf to use, can be undefined */ +/* Note: your snprintf must correctly zero-terminate the buffer! */ +// #define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< Default snprintf to use, can be undefined */ +// #define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. +// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_TIME_MACRO time /**< +// Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ #define +// MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to use, can be undefined. +// MBEDTLS_HAVE_TIME must be enabled */ #define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf +// /**< Default vsnprintf macro to use, can be undefined */ #define MBEDTLS_PRINTF_MS_TIME PRId64 +// /**< Default fmt for printf. That's avoid compiler warning if mbedtls_ms_time_t is redefined */ + +/** \} name SECTION: Platform abstraction layer */ + +/** + * \name SECTION: General and test configuration options + * + * This section sets test specific settings. + * \{ + */ + +/** + * \def MBEDTLS_CHECK_RETURN_WARNING + * + * If this macro is defined, emit a compile-time warning if application code + * calls a function without checking its return value, but the return value + * should generally be checked in portable applications. + * + * This is only supported on platforms where #MBEDTLS_CHECK_RETURN is + * implemented. Otherwise this option has no effect. + * + * Uncomment to get warnings on using fallible functions without checking + * their return value. + * + * \note This feature is a work in progress. + * Warnings will be added to more functions in the future. + * + * \note A few functions are considered critical, and ignoring the return + * value of these functions will trigger a warning even if this + * macro is not defined. To completely disable return value check + * warnings, define #MBEDTLS_CHECK_RETURN with an empty expansion. + */ +#define MBEDTLS_CHECK_RETURN_WARNING + +/** + * \def MBEDTLS_DEPRECATED_WARNING + * + * Mark deprecated functions and features so that they generate a warning if + * used. Functionality deprecated in one version will usually be removed in the + * next version. You can enable this to help you prepare the transition to a + * new major version by making sure your code is not using this functionality. + * + * This only works with GCC and Clang. With other compilers, you may want to + * use MBEDTLS_DEPRECATED_REMOVED + * + * Uncomment to get warnings on using deprecated functions and features. + */ +// #define MBEDTLS_DEPRECATED_WARNING + +/** + * \def MBEDTLS_DEPRECATED_REMOVED + * + * Remove deprecated functions and features so that they generate an error if + * used. Functionality deprecated in one version will usually be removed in the + * next version. You can enable this to help you prepare the transition to a + * new major version by making sure your code is not using this functionality. + * + * Uncomment to get errors on using deprecated functions and features. + */ +// #define MBEDTLS_DEPRECATED_REMOVED + +/** \def MBEDTLS_CHECK_RETURN + * + * This macro is used at the beginning of the declaration of a function + * to indicate that its return value should be checked. It should + * instruct the compiler to emit a warning or an error if the function + * is called without checking its return value. + * + * There is a default implementation for popular compilers in platform_util.h. + * You can override the default implementation by defining your own here. + * + * If the implementation here is empty, this will effectively disable the + * checking of functions' return values. + */ +// #define MBEDTLS_CHECK_RETURN __attribute__((__warn_unused_result__)) + +/** \def MBEDTLS_IGNORE_RETURN + * + * This macro requires one argument, which should be a C function call. + * If that function call would cause a #MBEDTLS_CHECK_RETURN warning, this + * warning is suppressed. + */ +// #define MBEDTLS_IGNORE_RETURN( result ) ((void) !(result)) + +/** + * \def TF_PSA_CRYPTO_CONFIG_FILE + * + * If defined, this is a header which will be included instead of + * `"psa/crypto_config.h"`. + * This header file specifies which cryptographic mechanisms are available + * through the PSA API. + * + * This macro is expanded after an \#include directive. This is a popular but + * non-standard feature of the C language, so this feature is only available + * with compilers that perform macro expansion on an \#include line. + * + * The value of this symbol is typically a path in double quotes, either + * absolute or relative to a directory on the include search path. + */ +// #define TF_PSA_CRYPTO_CONFIG_FILE "psa/crypto_config.h" + +/** + * \def TF_PSA_CRYPTO_USER_CONFIG_FILE + * + * If defined, this is a header which will be included after + * `"psa/crypto_config.h"` or #TF_PSA_CRYPTO_CONFIG_FILE. + * This allows you to modify the default configuration, including the ability + * to undefine options that are enabled by default. + * + * This macro is expanded after an \#include directive. This is a popular but + * non-standard feature of the C language, so this feature is only available + * with compilers that perform macro expansion on an \#include line. + * + * The value of this symbol is typically a path in double quotes, either + * absolute or relative to a directory on the include search path. + */ +// #define TF_PSA_CRYPTO_USER_CONFIG_FILE "/dev/null" + +/** + * \def MBEDTLS_SELF_TEST + * + * Enable the checkup functions (*_self_test). + */ +#define MBEDTLS_SELF_TEST + +/** + * \def MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN + * + * Enable testing of the constant-flow nature of some sensitive functions with + * clang's MemorySanitizer. This causes some existing tests to also test + * this non-functional property of the code under test. + * + * This setting requires compiling with clang -fsanitize=memory. The test + * suites can then be run normally. + * + * \warning This macro is only used for extended testing; it is not considered + * part of the library's API, so it may change or disappear at any time. + * + * Uncomment to enable testing of the constant-flow nature of selected code. + */ +// #define MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN + +/** + * \def MBEDTLS_TEST_CONSTANT_FLOW_VALGRIND + * + * Enable testing of the constant-flow nature of some sensitive functions with + * valgrind's memcheck tool. This causes some existing tests to also test + * this non-functional property of the code under test. + * + * This setting requires valgrind headers for building, and is only useful for + * testing if the tests suites are run with valgrind's memcheck. This can be + * done for an individual test suite with 'valgrind ./test_suite_xxx', or when + * using CMake, this can be done for all test suites with 'make memcheck'. + * + * \warning This macro is only used for extended testing; it is not considered + * part of the library's API, so it may change or disappear at any time. + * + * Uncomment to enable testing of the constant-flow nature of selected code. + */ +// #define MBEDTLS_TEST_CONSTANT_FLOW_VALGRIND + +/** + * \def MBEDTLS_TEST_HOOKS + * + * Enable features for invasive testing such as introspection functions and + * hooks for fault injection. This enables additional unit tests. + * + * Merely enabling this feature should not change the behavior of the product. + * It only adds new code, and new branching points where the default behavior + * is the same as when this feature is disabled. + * However, this feature increases the attack surface: there is an added + * risk of vulnerabilities, and more gadgets that can make exploits easier. + * Therefore this feature must never be enabled in production. + * + * See `docs/architecture/testing/mbed-crypto-invasive-testing.md` for more + * information. + * + * Uncomment to enable invasive tests. + */ +// #define MBEDTLS_TEST_HOOKS + +/** + * \def TF_PSA_CRYPTO_VERSION + * + * Enable run-time version information. + * + * This option enables functions for getting the version of TF-PSA-Crypto + * at runtime defined in include/tf-psa-crypto/version.h. + */ +#define TF_PSA_CRYPTO_VERSION + +/** \} name SECTION: General and test configuration options */ + +/** + * \name SECTION: Cryptographic mechanism selection (extended API) + * + * This section sets cryptographic mechanism settings. + * \{ + */ + +/** + * \def MBEDTLS_LMS_C + * + * Enable the LMS stateful-hash asymmetric signature algorithm. + * + * Module: drivers/builtin/src/lms.c + * Caller: + * + * Requires: MBEDTLS_PSA_CRYPTO_C + * + * Uncomment to enable the LMS verification algorithm and public key operations. + */ +#define MBEDTLS_LMS_C + +/** + * \def MBEDTLS_LMS_PRIVATE + * + * Enable LMS private-key operations and signing code. Functions enabled by this + * option are experimental, and should not be used in production. + * + * Requires: MBEDTLS_LMS_C + * + * Uncomment to enable the LMS signature algorithm and private key operations. + */ +#define MBEDTLS_LMS_PRIVATE + +/** + * \def MBEDTLS_MD_C + * + * Enable the generic layer for message digest (hashing). + * + * Requires: MBEDTLS_PSA_CRYPTO_C with at least one hash. + * Module: drivers/builtin/src/md.c + * Caller: drivers/builtin/src/constant_time.c + * drivers/builtin/src/ecdsa.c + * drivers/builtin/src/ecjpake.c + * drivers/builtin/src/hmac_drbg.c + * drivers/builtin/src/pk.c + * drivers/builtin/src/pkcs5.c + * drivers/builtin/src/psa_crypto_ecp.c + * drivers/builtin/src/psa_crypto_rsa.c + * drivers/builtin/src/rsa.c + * + * Uncomment to enable generic message digest wrappers. + */ +#define MBEDTLS_MD_C + +/** + * \def MBEDTLS_NIST_KW_C + * + * Enable the 128-bit key wrapping modes from NIST SP 800-38F: + * KW (also known as RFC 3394) and KWP (RFC 5649). + * Currently these modes are only supported with AES. + * + * Module: drivers/builtin/src/nist_kw.c + * + * Auto enables: PSA_WANT_ALG_ECB_NO_PADDING + */ +#define MBEDTLS_NIST_KW_C + +/** + * \def MBEDTLS_PK_C + * + * Enable the generic public (asymmetric) key layer. + * + * Module: drivers/builtin/src/pk.c + * Caller: drivers/builtin/src/psa_crypto_rsa.c + * + * Requires: #MBEDTLS_PSA_CRYPTO_CLIENT and at least one between + * #PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY and + * #PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY. + * + * Uncomment to enable generic public key wrappers. + */ +#define MBEDTLS_PK_C + +/** + * \def MBEDTLS_PKCS5_C + * + * Enable PKCS#5 functions. + * + * Module: drivers/builtin/src/pkcs5.c + * + * Auto-enables: MBEDTLS_MD_C + * + * This module adds support for the PKCS#5 functions. + */ +#define MBEDTLS_PKCS5_C + +/** + * \def MBEDTLS_PK_PARSE_C + * + * Enable the generic public (asymmetric) key parser. + * + * Module: drivers/builtin/src/pkparse.c + * + * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_PK_C + * + * Uncomment to enable generic public key parse functions. + */ +#define MBEDTLS_PK_PARSE_C + +/** + * \def MBEDTLS_PK_PARSE_EC_EXTENDED + * + * Enhance support for reading EC keys using variants of SEC1 not allowed by + * RFC 5915 and RFC 5480. + * + * Currently this means parsing the SpecifiedECDomain choice of EC + * parameters (only known groups are supported, not arbitrary domains, to + * avoid validation issues). + * + * Disable if you only need to support RFC 5915 + 5480 key formats. + */ +#define MBEDTLS_PK_PARSE_EC_EXTENDED + +/** + * \def MBEDTLS_PK_PARSE_EC_COMPRESSED + * + * Enable the support for parsing public keys of type Short Weierstrass + * (PSA_ECC_FAMILY_SECP_XXX and PSA_ECC_FAMILY_BRAINPOOL_XXX) which are using the + * compressed point format. + */ +#define MBEDTLS_PK_PARSE_EC_COMPRESSED + +/** + * \def MBEDTLS_PK_WRITE_C + * + * Enable the generic public (asymmetric) key writer. + * + * Module: drivers/builtin/src/pkwrite.c + * + * Requires: MBEDTLS_ASN1_WRITE_C, MBEDTLS_PK_C + * + * Uncomment to enable generic public key write functions. + */ +#define MBEDTLS_PK_WRITE_C + +/** \} name SECTION: Cryptographic mechanism selection (extended API) */ + +/** + * \name SECTION: Data format support + * + * This section sets data-format specific settings. + * \{ + */ + +/** + * \def MBEDTLS_ASN1_PARSE_C + * + * Enable the generic ASN1 parser. + * + * Module: drivers/builtin/src/asn1.c + * Caller: drivers/builtin/src/pkcs5.c + * drivers/builtin/src/pkparse.c + */ +#define MBEDTLS_ASN1_PARSE_C + +/** + * \def MBEDTLS_ASN1_WRITE_C + * + * Enable the generic ASN1 writer. + * + * Module: drivers/builtin/src/asn1write.c + * Caller: drivers/builtin/src/ecdsa.c + * drivers/builtin/src/pkwrite.c + */ +#define MBEDTLS_ASN1_WRITE_C + +/** + * \def MBEDTLS_BASE64_C + * + * Enable the Base64 module. + * + * Module: drivers/builtin/src/base64.c + * Caller: drivers/builtin/src/pem.c + * + * This module is required for PEM support (required by X.509). + */ +#define MBEDTLS_BASE64_C + +/** + * \def MBEDTLS_PEM_PARSE_C + * + * Enable PEM decoding / parsing. + * + * Module: drivers/builtin/src/pem.c + * Caller: drivers/builtin/src/pkparse.c + * + * Requires: MBEDTLS_BASE64_C + * optionally PSA_WANT_ALG_MD5 + * + * This modules adds support for decoding / parsing PEM files. + */ +#define MBEDTLS_PEM_PARSE_C + +/** + * \def MBEDTLS_PEM_WRITE_C + * + * Enable PEM encoding / writing. + * + * Module: drivers/builtin/src/pem.c + * Caller: drivers/builtin/src/pkwrite.c + * + * Requires: MBEDTLS_BASE64_C + * + * This modules adds support for encoding / writing PEM files. + */ +#define MBEDTLS_PEM_WRITE_C + +/** \} name SECTION: Data format support */ + +/** + * \name SECTION: PSA core + * + * This section sets PSA specific settings. + * \{ + */ + +/** + * \def MBEDTLS_CTR_DRBG_C + * + * Enable the CTR_DRBG AES-based random generator. + * The CTR_DRBG generator uses AES-256 by default. + * To use AES-128 instead, set #MBEDTLS_PSA_CRYPTO_RNG_STRENGTH to 128. + * + * AES support can either be achieved through built-in AES or PSA. Built-in is + * the default option when present otherwise PSA is used. + * + * Module: drivers/builtin/src/ctr_drbg.c + * + * Requires: MBEDTLS_PSA_CRYPTO_C, PSA_WANT_KEY_TYPE_AES and + * PSA_WANT_ALG_ECB_NO_PADDING + * + * This module provides the CTR_DRBG AES random number generator. + */ +#define MBEDTLS_CTR_DRBG_C + +/** + * \def MBEDTLS_ENTROPY_NO_SOURCES_OK + * + * Normally, TF-PSA-Crypto requires at least one "true" entropy source, such + * #MBEDTLS_PSA_BUILTIN_GET_ENTROPY or #MBEDTLS_PSA_DRIVER_GET_ENTROPY. + * + * It is possible to build the library with a seed injected during device + * provisioning, thanks to #MBEDTLS_ENTROPY_NV_SEED. + * This is only an initial entropy input: without a true entropy source, + * the device will not obtain additional entropy during its lifetime. + * Thus, if the seed value is leaked, it is impossible to recover from + * this compromise. + * + * Enable this option if this loss of security is acceptable to you. + */ +#define MBEDTLS_ENTROPY_NO_SOURCES_OK + +/** + * \def MBEDTLS_ENTROPY_NV_SEED + * + * Enable the non-volatile (NV) seed file-based entropy source. + * (Also enables the NV seed read/write functions in the platform layer) + * + * This is crucial (if not required) on systems that do not have a + * cryptographic entropy source (in hardware or kernel) available. + * + * Requires: MBEDTLS_PSA_CRYPTO_C, + * !MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG + * MBEDTLS_PLATFORM_C + * + * \note The read/write functions that are used by the entropy source are + * determined in the platform layer, and can be modified at runtime and/or + * compile-time depending on the flags (MBEDTLS_PLATFORM_NV_SEED_*) used. + * + * \note If you use the default implementation functions that read a seedfile + * with regular fopen(), please make sure you make a seedfile with the + * proper name (defined in MBEDTLS_PLATFORM_STD_NV_SEED_FILE) and at + * least MBEDTLS_ENTROPY_BLOCK_SIZE bytes in size that can be read from + * and written to or you will get an entropy source error! The default + * implementation will only use the first MBEDTLS_ENTROPY_BLOCK_SIZE + * bytes from the file. + * + * \note The entropy collector will write to the seed file before entropy is + * given to an external source, to update it. + */ +// #define MBEDTLS_ENTROPY_NV_SEED + +/** + * \def MBEDTLS_HMAC_DRBG_C + * + * Enable the HMAC_DRBG random generator. + * + * Module: drivers/builtin/src/hmac_drbg.c + * Caller: + * + * Requires: MBEDTLS_MD_C + * + * Uncomment to enable the HMAC_DRBG random number generator. + */ +#define MBEDTLS_HMAC_DRBG_C + +/** + * \def MBEDTLS_PSA_CRYPTO_C + * + * Enable the Platform Security Architecture cryptography API. + * + * Module: core/psa_crypto.c + * + * Requires: one of the following: + * - MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG + * - MBEDTLS_CTR_DRBG_C + * - MBEDTLS_HMAC_DRBG_C + * + * If MBEDTLS_CTR_DRBG_C or MBEDTLS_HMAC_DRBG_C is used as the PSA + * random generator, then either PSA_WANT_ALG_SHA_256 or + * PSA_WANT_ALG_SHA_512 must be enabled for the entropy module. + * + * \note The PSA crypto subsystem prioritizes DRBG mechanisms as follows: + * - #MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG, if enabled + * - CTR_DRBG (AES), seeded by the entropy module, if + * #MBEDTLS_CTR_DRBG_C is enabled + * - HMAC_DRBG, seeded by the entropy module, if + * #MBEDTLS_HMAC_DRBG_C is enabled + * + * A future version may reevaluate the prioritization of DRBG mechanisms. + */ +#define MBEDTLS_PSA_CRYPTO_C + +/** + * \def MBEDTLS_PSA_ASSUME_EXCLUSIVE_BUFFERS + * + * Assume all buffers passed to PSA functions are owned exclusively by the + * PSA function and are not stored in shared memory. + * + * This option may be enabled if all buffers passed to any PSA function reside + * in memory that is accessible only to the PSA function during its execution. + * + * This option MUST be disabled whenever buffer arguments are in memory shared + * with an untrusted party, for example where arguments to PSA calls are passed + * across a trust boundary. + * + * \note Enabling this option reduces memory usage and code size. + * + * \note Enabling this option causes overlap of input and output buffers + * not to be supported by PSA functions. + */ +// #define MBEDTLS_PSA_ASSUME_EXCLUSIVE_BUFFERS + +/** + * \def MBEDTLS_PSA_BUILTIN_GET_ENTROPY + * + * Enable entropy sources for which the library has a built-in driver. + * + * Requires: MBEDTLS_PSA_CRYPTO_C, !MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG + * + * These are: + * - getrandom() on Linux (if syscall() is available at compile time); + * - getrandom() on FreeBSD and DragonFlyBSD (if available at compile time); + * - `sysctl(KERN_ARND)` on FreeBSD and NetBSD; + * - `/dev/urandom` on Unix-like platforms (unless one of the above is used); + * - BCryptGenRandom() on Windows. + * + * You should enable this option if your platform has one of these. If not: + * + * - You can enable #MBEDTLS_PSA_DRIVER_GET_ENTROPY instead, and provide + * an entropy source callback for your platform. + * - If your platform has a fast cryptographic-quality random generator, + * enable #MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG and provide a random generator + * callback instead. + * - If your platform has no source of entropy at all, you can enable + * #MBEDTLS_ENTROPY_NV_SEED and provide a seed in nonvolatile memory + * during the provisioning of the device. + * - The random generator requires a random generator callback, + * an entropy source or a seed in nonvolatile memory. + * Builds with no random generator are not officially supported yet, except + * client-only builds (#MBEDTLS_PSA_CRYPTO_CLIENT enabled and + * #MBEDTLS_PSA_CRYPTO_C disabled). + */ +// #define MBEDTLS_PSA_BUILTIN_GET_ENTROPY + +/** \def MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS + * + * Enable support for platform built-in keys. If you enable this feature, + * you must implement the function mbedtls_psa_platform_get_builtin_key(). + * See the documentation of that function for more information. + * + * Built-in keys are typically derived from a hardware unique key or + * stored in a secure element. + * + * Requires: MBEDTLS_PSA_CRYPTO_C. + * + * \warning This interface is experimental and may change or be removed + * without notice. + */ +// #define MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS + +/** \def MBEDTLS_PSA_CRYPTO_CLIENT + * + * Enable support for PSA crypto client. + * + * \note This option allows to include the code necessary for a PSA + * crypto client when the PSA crypto implementation is not included in + * the library (MBEDTLS_PSA_CRYPTO_C disabled). The code included is the + * code to set and get PSA key attributes. + * The development of PSA drivers partially relying on the library to + * fulfill the hardware gaps is another possible usage of this option. + * + * \warning This interface is experimental and may change or be removed + * without notice. + */ +#define MBEDTLS_PSA_CRYPTO_CLIENT + +/** \def MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG + * + * Make the PSA Crypto module use an external random generator provided + * by a driver, instead of Mbed TLS's entropy and DRBG modules. + * + * \note This random generator must deliver random numbers with cryptographic + * quality and high performance. It must supply unpredictable numbers + * with a uniform distribution. The implementation of this function + * is responsible for ensuring that the random generator is seeded + * with sufficient entropy. If you have a hardware TRNG which is slow + * or delivers non-uniform output, declare it as an entropy source + * with mbedtls_entropy_add_source() instead of enabling this option. + * + * If you enable this option, you must configure the type + * ::mbedtls_psa_external_random_context_t in psa/crypto_platform.h + * and define a function called mbedtls_psa_external_get_random() + * with the following prototype: + * ``` + * psa_status_t mbedtls_psa_external_get_random( + * mbedtls_psa_external_random_context_t *context, + * uint8_t *output, size_t output_size, size_t *output_length); + * ); + * ``` + * The \c context value is initialized to 0 before the first call. + * The function must fill the \c output buffer with \c output_size bytes + * of random data and set \c *output_length to \c output_size. + * + * Requires: MBEDTLS_PSA_CRYPTO_C + * + * \warning If you enable this option, code that uses the PSA cryptography + * interface will not use any of the entropy sources set up for + * the entropy module, nor the NV seed that MBEDTLS_ENTROPY_NV_SEED + * enables. + * + * \note This option is experimental and may be removed without notice. + */ +// #define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG + +/* MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER + * + * Enable key identifiers that encode a key owner identifier. + * + * The owner of a key is identified by a value of type ::mbedtls_key_owner_id_t + * which is currently hard-coded to be int32_t. + * + * Note that this option is meant for internal use only and may be removed + * without notice. + */ +// #define MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER + +/** + * \def MBEDTLS_PSA_CRYPTO_SPM + * + * When MBEDTLS_PSA_CRYPTO_SPM is defined, the code is built for SPM (Secure + * Partition Manager) integration which separates the code into two parts: a + * NSPE (Non-Secure Process Environment) and an SPE (Secure Process + * Environment). + * + * If you enable this option, your build environment must include a header + * file `"crypto_spe.h"` (either in the `psa` subdirectory of the Mbed TLS + * header files, or in another directory on the compiler's include search + * path). Alternatively, your platform may customize the header + * `psa/crypto_platform.h`, in which case it can skip or replace the + * inclusion of `"crypto_spe.h"`. + * + * Module: core/psa_crypto.c + * Requires: MBEDTLS_PSA_CRYPTO_C + * + */ +// #define MBEDTLS_PSA_CRYPTO_SPM + +/** + * \def MBEDTLS_PSA_CRYPTO_STORAGE_C + * + * Enable the Platform Security Architecture persistent key storage. + * + * Module: core/psa_crypto_storage.c + * + * Requires: MBEDTLS_PSA_CRYPTO_C, + * either MBEDTLS_PSA_ITS_FILE_C or a native implementation of + * the PSA ITS interface + */ +// #define MBEDTLS_PSA_CRYPTO_STORAGE_C + +/** + * \def MBEDTLS_PSA_DRIVER_GET_ENTROPY + * + * Requires: MBEDTLS_PSA_CRYPTO_C, !MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG + * + * Enable the custom entropy callback mbedtls_platform_get_entropy() + * (declared in mbedtls/platform.h). You need to provide this callback + * if you need an entropy source and the built-in entropy callback + * provided by #MBEDTLS_PSA_BUILTIN_GET_ENTROPY does not work on your platform. + * + * Enabling both #MBEDTLS_PSA_BUILTIN_GET_ENTROPY and + * #MBEDTLS_PSA_DRIVER_GET_ENTROPY is currently not supported. + * + * You do not need any entropy source in the following circumstances: + * + * - If your platform has a fast cryptographic-quality random generator, and + * you enable #MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG and provide a random generator + * callback instead. + * - If your platform has no source of entropy at all, and you enable + * #MBEDTLS_ENTROPY_NV_SEED and provide a seed in nonvolatile memory + * during the provisioning of the device. + * - If you build the library with no random generator. + * Builds with no random generator are not officially supported yet, except + * client-only builds (#MBEDTLS_PSA_CRYPTO_CLIENT enabled and + * #MBEDTLS_PSA_CRYPTO_C disabled). + */ +#define MBEDTLS_PSA_DRIVER_GET_ENTROPY + +/** + * \def MBEDTLS_PSA_ITS_FILE_C + * + * Enable the emulation of the Platform Security Architecture + * Internal Trusted Storage (PSA ITS) over files. + * + * Module: core/psa_its_file.c + * + * Requires: MBEDTLS_FS_IO + */ +// #define MBEDTLS_PSA_ITS_FILE_C + +/** + * \def MBEDTLS_PSA_KEY_STORE_DYNAMIC + * + * Dynamically resize the PSA key store to accommodate any number of + * volatile keys (until the heap memory is exhausted). + * + * If this option is disabled, the key store has a fixed size + * #MBEDTLS_PSA_KEY_SLOT_COUNT for volatile keys and loaded persistent keys + * together. + * + * This option has no effect when #MBEDTLS_PSA_CRYPTO_C is disabled. + * + * Module: core/psa_crypto.c + * Requires: MBEDTLS_PSA_CRYPTO_C + */ +#define MBEDTLS_PSA_KEY_STORE_DYNAMIC + +/** + * \def MBEDTLS_PSA_STATIC_KEY_SLOTS + * + * Statically preallocate memory to store keys' material in PSA instead + * of allocating it dynamically when required. This allows builds without a + * heap, if none of the enabled cryptographic implementations or other features + * require it. + * This feature affects both volatile and persistent keys which means that + * it's not possible to persistently store a key which is larger than + * #MBEDTLS_PSA_STATIC_KEY_SLOT_BUFFER_SIZE. + * + * \note This feature comes with a (potentially) higher RAM usage since: + * - All the key slots are allocated no matter if they are used or not. + * - Each key buffer's length is #MBEDTLS_PSA_STATIC_KEY_SLOT_BUFFER_SIZE bytes. + * + * Requires: MBEDTLS_PSA_CRYPTO_C + * + */ +// #define MBEDTLS_PSA_STATIC_KEY_SLOTS + +/* Entropy options */ + +/** + * \def MBEDTLS_PSA_CRYPTO_PLATFORM_FILE + * + * If defined, this is a header which will be included instead of + * `"psa/crypto_platform.h"`. This file should declare the same identifiers + * as the one in Mbed TLS, but with definitions adapted to the platform on + * which the library code will run. + * + * \note The required content of this header can vary from one version of + * Mbed TLS to the next. Integrators who provide an alternative file + * should review the changes in the original file whenever they + * upgrade Mbed TLS. + * + * This macro is expanded after an \#include directive. This is a popular but + * non-standard feature of the C language, so this feature is only available + * with compilers that perform macro expansion on an \#include line. + * + * The value of this symbol is typically a path in double quotes, either + * absolute or relative to a directory on the include search path. + */ +// #define MBEDTLS_PSA_CRYPTO_PLATFORM_FILE "psa/crypto_platform_alt.h" + +/** + * \def MBEDTLS_PSA_CRYPTO_STRUCT_FILE + * + * If defined, this is a header which will be included instead of + * `"psa/crypto_struct.h"`. This file should declare the same identifiers + * as the one in Mbed TLS, but with definitions adapted to the environment + * in which the library code will run. The typical use for this feature + * is to provide alternative type definitions on the client side in + * client-server integrations of PSA crypto, where operation structures + * contain handles instead of cryptographic data. + * + * \note The required content of this header can vary from one version of + * Mbed TLS to the next. Integrators who provide an alternative file + * should review the changes in the original file whenever they + * upgrade Mbed TLS. + * + * This macro is expanded after an \#include directive. This is a popular but + * non-standard feature of the C language, so this feature is only available + * with compilers that perform macro expansion on an \#include line. + * + * The value of this symbol is typically a path in double quotes, either + * absolute or relative to a directory on the include search path. + */ +// #define MBEDTLS_PSA_CRYPTO_STRUCT_FILE "psa/crypto_struct_alt.h" + +/** \def MBEDTLS_PSA_KEY_SLOT_COUNT + * + * When #MBEDTLS_PSA_KEY_STORE_DYNAMIC is disabled, + * the maximum amount of PSA keys simultaneously in memory. This counts all + * volatile keys, plus loaded persistent keys. + * + * When #MBEDTLS_PSA_KEY_STORE_DYNAMIC is enabled, + * the maximum number of loaded persistent keys. + * + * Currently, persistent keys do not need to be loaded all the time while + * a multipart operation is in progress, only while the operation is being + * set up. This may change in future versions of the library. + * + * Currently, the library traverses of the whole table on each access to a + * persistent key. Therefore large values may cause poor performance. + * + * This option has no effect when #MBEDTLS_PSA_CRYPTO_C is disabled. + */ +// #define MBEDTLS_PSA_KEY_SLOT_COUNT 32 + +/** + * \def MBEDTLS_PSA_STATIC_KEY_SLOT_BUFFER_SIZE + * + * Define the size (in bytes) of each static key buffer when + * #MBEDTLS_PSA_STATIC_KEY_SLOTS is set. If not + * explicitly defined then it's automatically guessed from available PSA keys + * enabled in the build through PSA_WANT_xxx symbols. + * If required by the application this parameter can be set to higher values + * in order to store larger objects (ex: raw keys), but please note that this + * will increase RAM usage. + */ +// #define MBEDTLS_PSA_STATIC_KEY_SLOT_BUFFER_SIZE 256 + +/** + * \def MBEDTLS_PSA_CRYPTO_RNG_STRENGTH + * + * Minimum security strength (in bits) of the PSA RNG. + * + * \note Valid values: 128 or default of 256. + */ +// #define MBEDTLS_PSA_CRYPTO_RNG_STRENGTH 256 + +/** + * \def MBEDTLS_PSA_CRYPTO_RNG_HASH + * + * \brief Hash algorithm to use for the entropy module and for HMAC_DRBG if configured. + * + * The hash size (in bits) must be at least #MBEDTLS_PSA_CRYPTO_RNG_STRENGTH. + * + * In addition, if the entropy module is enabled (#MBEDTLS_PSA_CRYPTO_C is enabled + * and #MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG is disabled): + * - The hash size must be at least 32 bytes (i.e., 256 bits). + * - Only two values are currently allowed: PSA_ALG_SHA_256 and PSA_ALG_SHA_512. + * A future version may lift this limitation. + * + * If #MBEDTLS_PSA_CRYPTO_RNG_HASH is not explicitly set in the configuration, + * a default hash that satisfies the above constraints is selected automatically. + * If no suitable default can be selected, this will result in a build error. + */ +// #define MBEDTLS_PSA_CRYPTO_RNG_HASH PSA_ALG_SHA_256 + +/** + * \def MBEDTLS_PSA_RNG_RESEED_INTERVAL + * + * In CTR_DRBG and HMAC_DRBG, the interval before the DRBG is reseeded from entropy. + * The interval is the number of requests to the random generator, for any purpose. + * + * \note Requests have a maximum size (which depends on the library configuration + * and is currently unspecified), so the maximum number of bytes before a reseed + * is the interval multiplied by the maximum request size. + */ +// #define MBEDTLS_PSA_RNG_RESEED_INTERVAL 1000 + +/** \} name SECTION: PSA core */ + +/** + * \name SECTION: Builtin drivers + * + * This section sets driver specific settings. + * \{ + */ + +/** + * \def MBEDTLS_AESNI_C + * + * Enable AES-NI support on x86-64 or x86-32. + * + * \note AESNI is only supported with certain compilers and target options: + * - Visual Studio: supported + * - GCC, x86-64, target not explicitly supporting AESNI: + * requires MBEDTLS_HAVE_ASM. + * - GCC, x86-32, target not explicitly supporting AESNI: + * not supported. + * - GCC, x86-64 or x86-32, target supporting AESNI: supported. + * For this assembly-less implementation, you must currently compile + * `drivers/builtin/src/aesni.c` and `drivers/builtin/src/aes.c` with machine + * options to enable SSE2 and AESNI instructions: `gcc -msse2 -maes -mpclmul` + * or `clang -maes -mpclmul`. + * - Non-x86 targets: this option is silently ignored. + * - Other compilers: this option is silently ignored. + * + * \note + * Above, "GCC" includes compatible compilers such as Clang. + * The limitations on target support are likely to be relaxed in the future. + * + * Module: drivers/builtin/src/aesni.c + * Caller: drivers/builtin/src/aes.c + * + * Requires: MBEDTLS_HAVE_ASM (on some platforms, see note) + * + * This modules adds support for the AES-NI instructions on x86. + */ +#define MBEDTLS_AESNI_C + +/** + * \def MBEDTLS_AESCE_C + * + * Enable AES cryptographic extension support on Armv8. + * + * Module: drivers/builtin/src/aesce.c + * Caller: drivers/builtin/src/aes.c + * + * Requires: The AES built-in implementation + * + * \warning Runtime detection only works on Linux. For non-Linux operating + * system, Armv8-A Cryptographic Extensions must be supported by + * the CPU when this option is enabled. + * + * \note Minimum compiler versions for this feature when targeting aarch64 + * are Clang 4.0; armclang 6.6; GCC 6.0; or MSVC 2019 version 16.11.2. + * Minimum compiler versions for this feature when targeting 32-bit + * Arm or Thumb are Clang 11.0; armclang 6.20; or GCC 6.0. + * + * \note \c CFLAGS must be set to a minimum of \c -march=armv8-a+crypto for + * armclang <= 6.9 + * + * This module adds support for the AES Armv8-A Cryptographic Extensions on Armv8 systems. + */ +#define MBEDTLS_AESCE_C + +/** + * \def MBEDTLS_AES_ROM_TABLES + * + * Use precomputed AES tables stored in ROM. + * + * Uncomment this macro to use precomputed AES tables stored in ROM. + * Comment this macro to generate AES tables in RAM at runtime. + * + * Tradeoff: Using precomputed ROM tables reduces RAM usage by ~8kb + * (or ~2kb if \c MBEDTLS_AES_FEWER_TABLES is used) and reduces the + * initialization time before the first AES operation can be performed. + * It comes at the cost of additional ~8kb ROM use (resp. ~2kb if \c + * MBEDTLS_AES_FEWER_TABLES below is used), and potentially degraded + * performance if ROM access is slower than RAM access. + * + * This option is independent of \c MBEDTLS_AES_FEWER_TABLES. + */ +#define MBEDTLS_AES_ROM_TABLES + +/** + * \def MBEDTLS_AES_FEWER_TABLES + * + * Use less ROM/RAM for AES tables. + * + * Uncommenting this macro omits 75% of the AES tables from + * ROM / RAM (depending on the value of \c MBEDTLS_AES_ROM_TABLES) + * by computing their values on the fly during operations + * (the tables are entry-wise rotations of one another). + * + * Tradeoff: Uncommenting this reduces the RAM / ROM footprint + * by ~6kb but at the cost of more arithmetic operations during + * runtime. Specifically, one has to compare 4 accesses within + * different tables to 4 accesses with additional arithmetic + * operations within the same table. The performance gain/loss + * depends on the system and memory details. + * + * This option is independent of \c MBEDTLS_AES_ROM_TABLES. + */ +#define MBEDTLS_AES_FEWER_TABLES + +/** + * \def MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH + * + * Use only 128-bit keys in AES operations to save ROM. + * + * Uncomment this macro to remove support for AES operations that use 192- + * or 256-bit keys. + * + * Uncommenting this macro reduces the size of AES code by ~300 bytes + * on v8-M/Thumb2. + * + * Module: drivers/builtin/src/aes.c + * + * Requires: The AES built-in implementation + */ +// #define MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH + +/* + * Disable plain C implementation for AES. + * + * When the plain C implementation is enabled, and an implementation using a + * special CPU feature (such as MBEDTLS_AESCE_C) is also enabled, runtime + * detection will be used to select between them. + * + * If only one implementation is present, runtime detection will not be used. + * This configuration will crash at runtime if running on a CPU without the + * necessary features. It will not build unless at least one of MBEDTLS_AESCE_C + * and/or MBEDTLS_AESNI_C is enabled & present in the build. + */ +// #define MBEDTLS_AES_USE_HARDWARE_ONLY + +/** + * \def MBEDTLS_BLOCK_CIPHER_NO_DECRYPT + * + * Remove decryption operation for AES, ARIA and Camellia block cipher. + * + * \note This feature is incompatible with PSA_WANT_ALG_ECB_NO_PADDING, + * PSA_WANT_ALG_CBC_NO_PADDING, PSA_WANT_ALG_CBC_PKCS7 and + * MBEDTLS_NIST_KW_C. + * + * Module: drivers/builtin/src/aes.c + * drivers/builtin/src/aesce.c + * drivers/builtin/src/aesni.c + * drivers/builtin/src/aria.c + * drivers/builtin/src/camellia.c + * drivers/builtin/src/cipher.c + */ +// #define MBEDTLS_BLOCK_CIPHER_NO_DECRYPT + +/** + * \def MBEDTLS_CAMELLIA_SMALL_MEMORY + * + * Use less ROM for the Camellia implementation (saves about 768 bytes). + * + * Uncomment this macro to use less memory for Camellia. + */ +#define MBEDTLS_CAMELLIA_SMALL_MEMORY + +/** + * Enable the verified implementations of ECDH primitives from Project Everest + * (currently only Curve25519). This feature changes the layout of ECDH + * contexts and therefore is a compatibility break for applications that access + * fields of a mbedtls_ecdh_context structure directly. See also + * MBEDTLS_ECDH_LEGACY_CONTEXT in drivers/builtin/include/mbedtls/private/ecdh.h. + * + * The Everest code is provided under the Apache 2.0 license only; therefore enabling this + * option is not compatible with taking the library under the GPL v2.0-or-later license. + */ +// #define MBEDTLS_ECDH_VARIANT_EVEREST_ENABLED + +/** + * \def MBEDTLS_ECP_NIST_OPTIM + * + * Enable specific 'modulo p' routines for each NIST prime. + * Depending on the prime and architecture, makes operations 4 to 8 times + * faster on the corresponding curve. + * + * Comment this macro to disable NIST curves optimisation. + */ +#define MBEDTLS_ECP_NIST_OPTIM + +/** + * \def MBEDTLS_ECP_RESTARTABLE + * + * Enable "non-blocking" ECC operations that can return early and be resumed. + * + * This allows various functions to pause by returning + * #PSA_OPERATION_INCOMPLETE and then be called later again in + * order to further progress and eventually complete their operation. This is + * controlled through mbedtls_ecp_set_max_ops() which limits the maximum + * number of ECC operations a function may perform before pausing; see + * mbedtls_ecp_set_max_ops() for more information. + * + * This is useful in non-threaded environments if you want to avoid blocking + * for too long on ECC (and, hence, X.509 or SSL/TLS) operations. + * + * This option: + * - Adds xxx_restartable() variants of existing operations in the + * following modules, with corresponding restart context types: + * - ECP (for Short Weierstrass curves only): scalar multiplication (mul), + * linear combination (muladd); + * - ECDSA: signature generation & verification; + * - PK: signature generation & verification; + * - X509: certificate chain verification. + * - Adds mbedtls_ecdh_enable_restart() in the ECDH module. + * - Changes the behaviour of TLS 1.2 clients (not servers) when using the + * ECDHE-ECDSA key exchange (not other key exchanges) to make all ECC + * computations restartable: + * - verification of the server's key exchange signature; + * - verification of the server's certificate chain; + * - generation of the client's signature if client authentication is used, + * with an ECC key/certificate. + * + * \note When this option is enabled, restartable operations in PK, X.509 + * and TLS (see above) are not using PSA. On the other hand, ECDH + * computations in TLS are using PSA, and are not restartable. These + * are temporary limitations that should be lifted in the future. (See + * https://github.com/Mbed-TLS/mbedtls/issues/9784 and + * https://github.com/Mbed-TLS/mbedtls/issues/9817) + * + * Requires: Builtin support of Elliptic Curves. + * + * Uncomment this macro to enable restartable ECC computations. + */ +#define MBEDTLS_ECP_RESTARTABLE + +/** + * Uncomment to enable using new bignum code in the ECC modules. + * + * \warning This is currently experimental, incomplete and therefore should not + * be used in production. + */ +// #define MBEDTLS_ECP_WITH_MPI_UINT + +/** + * \def MBEDTLS_GCM_LARGE_TABLE + * + * Enable large pre-computed tables for Galois/Counter Mode (GCM). + * Can significantly increase throughput on systems without GCM hardware + * acceleration (e.g., AESNI, AESCE). + * + * The mbedtls_gcm_context size will increase by 3840 bytes. + * The code size will increase by roughly 344 bytes. + * + * Module: drivers/builtin/src/gcm.c + * + * Requires: The GCM built-in implementation + */ +#define MBEDTLS_GCM_LARGE_TABLE + +/** + * \def MBEDTLS_HAVE_ASM + * + * The compiler has support for asm(). + * + * Requires support for asm() in compiler. + * + * Used in: + * drivers/builtin/src/aesni.h + * drivers/builtin/src/aria.c + * drivers/builtin/src/bn_mul.h + * drivers/builtin/src/constant_time.c + * + * Required by: + * MBEDTLS_AESCE_C + * MBEDTLS_AESNI_C (on some platforms) + * + * Comment to disable the use of assembly code. + */ +#define MBEDTLS_HAVE_ASM + +/** + * \def MBEDTLS_HAVE_SSE2 + * + * CPU supports SSE2 instruction set. + * + * Uncomment if the CPU supports SSE2 (IA-32 specific). + */ +// #define MBEDTLS_HAVE_SSE2 + +/** + * \def MBEDTLS_NO_UDBL_DIVISION + * + * The platform lacks support for double-width integer division (64-bit + * division on a 32-bit platform, 128-bit division on a 64-bit platform). + * + * Used in: + * include/mbedtls/bignum.h + * drivers/builtin/src/bignum.c + * + * The bignum code uses double-width division to speed up some operations. + * Double-width division is often implemented in software that needs to + * be linked with the program. The presence of a double-width integer + * type is usually detected automatically through preprocessor macros, + * but the automatic detection cannot know whether the code needs to + * and can be linked with an implementation of division for that type. + * By default division is assumed to be usable if the type is present. + * Uncomment this option to prevent the use of double-width division. + * + * Note that division for the native integer type is always required. + * Furthermore, a 64-bit type is always required even on a 32-bit + * platform, but it need not support multiplication or division. In some + * cases it is also desirable to disable some double-width operations. For + * example, if double-width division is implemented in software, disabling + * it can reduce code size in some embedded targets. + */ +// #define MBEDTLS_NO_UDBL_DIVISION + +/** + * \def MBEDTLS_NO_64BIT_MULTIPLICATION + * + * The platform lacks support for 32x32 -> 64-bit multiplication. + * + * Used in: + * drivers/builtin/src/poly1305.c + * + * Some parts of the library may use multiplication of two unsigned 32-bit + * operands with a 64-bit result in order to speed up computations. On some + * platforms, this is not available in hardware and has to be implemented in + * software, usually in a library provided by the toolchain. + * + * Sometimes it is not desirable to have to link to that library. This option + * removes the dependency of that library on platforms that lack a hardware + * 64-bit multiplier by embedding a software implementation in Mbed TLS. + * + * Note that depending on the compiler, this may decrease performance compared + * to using the library function provided by the toolchain. + */ +// #define MBEDTLS_NO_64BIT_MULTIPLICATION + +/** + * Uncomment to enable p256-m. This is an alternative implementation of + * key generation, ECDH and (randomized) ECDSA on the curve SECP256R1. + * Compared to the default implementation: + * + * - p256-m has a much smaller code size and RAM footprint. + * - p256-m is only available via the PSA API. This includes the pk module. + * - p256-m does not support deterministic ECDSA, EC-JPAKE, custom protocols + * over the core arithmetic, or deterministic derivation of keys. + * + * We recommend enabling this option if your application uses the PSA API + * and the only elliptic curve support it needs is ECDH and ECDSA over + * SECP256R1. + * + * If you enable this option, you do not need to enable any ECC-related + * MBEDTLS_xxx option. You do need to separately request support for the + * cryptographic mechanisms through the PSA API: + * - #MBEDTLS_PSA_CRYPTO_C for PSA-based configuration; + * - #PSA_WANT_ECC_SECP_R1_256; + * - #PSA_WANT_ALG_ECDH and/or #PSA_WANT_ALG_ECDSA as needed; + * - #PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY, #PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC, + * #PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT, + * #PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT and/or + * #PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE as needed. + * + * \note To benefit from the smaller code size of p256-m, make sure that you + * do not enable any ECC-related option not supported by p256-m: this + * would cause the built-in ECC implementation to be built as well, in + * order to provide the required option. + * Make sure #PSA_WANT_ALG_DETERMINISTIC_ECDSA, #PSA_WANT_ALG_JPAKE and + * #PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE, and curves other than + * SECP256R1 are disabled as they are not supported by this driver. + * Also, avoid defining #MBEDTLS_PK_PARSE_EC_COMPRESSED or + * #MBEDTLS_PK_PARSE_EC_EXTENDED as those currently require a subset of + * the built-in ECC implementation, see docs/driver-only-builds.md. + */ +// #define MBEDTLS_PSA_P256M_DRIVER_ENABLED + +/** + * \def MBEDTLS_RSA_NO_CRT + * + * Do not use the Chinese Remainder Theorem + * for the RSA private operation. + * + * Uncomment this macro to disable the use of CRT in RSA. + * + */ +// #define MBEDTLS_RSA_NO_CRT + +/** + * \def MBEDTLS_SHA256_SMALLER + * + * Enable an implementation of SHA-256 that has lower ROM footprint but also + * lower performance. + * + * The default implementation is meant to be a reasonable compromise between + * performance and size. This version optimizes more aggressively for size at + * the expense of performance. Eg on Cortex-M4 it reduces the size of + * mbedtls_sha256_process() from ~2KB to ~0.5KB for a performance hit of about + * 30%. + * + * Uncomment to enable the smaller implementation of SHA256. + */ +#define MBEDTLS_SHA256_SMALLER + +/** + * \def MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT + * + * Enable acceleration of the SHA-256 and SHA-224 cryptographic hash algorithms + * with the ARMv8 cryptographic extensions if they are available at runtime. + * If not, the library will fall back to the C implementation. + * + * \note MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT requires the built-in + * SHA-256 implementation to be present in the build. This implementation is + * included only if PSA_WANT_ALG_SHA_256 is enabled and this results in + * MBEDTLS_PSA_BUILTIN_ALG_SHA_256 being defined internally (i.e., no + * fully-featured, fallback-free accelerator driver is present). + * + * \note If MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT is defined when building + * for a non-Armv8-A build it will be silently ignored. + * + * \note Minimum compiler versions for this feature are Clang 4.0, + * armclang 6.6 or GCC 6.0. + * + * \note \c CFLAGS must be set to a minimum of \c -march=armv8-a+crypto for + * armclang <= 6.9 + * + * \warning MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT cannot be defined at the + * same time as MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_ONLY. + * + * Requires: The SHA-256 built-in implementation + * + * Module: drivers/builtin/src/sha256.c + * + * Uncomment to have the library check for the Armv8-A SHA-256 crypto extensions + * and use them if available. + */ +// #define MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT + +/** + * \def MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_ONLY + * + * Enable acceleration of the SHA-256 and SHA-224 cryptographic hash algorithms + * with the ARMv8 cryptographic extensions, which must be available at runtime + * or else an illegal instruction fault will occur. + * + * \note MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_ONLY requires the built-in SHA-256 + * implementation to be present in the build. This implementation is included + * only if PSA_WANT_ALG_SHA_256 is enabled and this results in + * MBEDTLS_PSA_BUILTIN_ALG_SHA_256 being defined internally (i.e., no + * fully-featured, fallback-free accelerator driver is present). + * + * \note This allows builds with a smaller code size than with + * MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT + * + * \note Minimum compiler versions for this feature are Clang 4.0, + * armclang 6.6 or GCC 6.0. + * + * \note \c CFLAGS must be set to a minimum of \c -march=armv8-a+crypto for + * armclang <= 6.9 + * + * \warning MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_ONLY cannot be defined at the same + * time as MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT. + * + * Requires: The SHA-256 built-in implementation + * + * Module: drivers/builtin/src/sha256.c + * + * Uncomment to have the library use the Armv8-A SHA-256 crypto extensions + * unconditionally. + */ +// #define MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_ONLY + +/** + * \def MBEDTLS_SHA512_SMALLER + * + * Enable an implementation of SHA-512 that has lower ROM footprint but also + * lower performance. + * + * Uncomment to enable the smaller implementation of SHA512. + */ +#define MBEDTLS_SHA512_SMALLER + +/** + * \def MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT + * + * Enable acceleration of the SHA-512 and SHA-384 cryptographic hash algorithms + * with the ARMv8 cryptographic extensions if they are available at runtime. + * If not, the library will fall back to the C implementation. + * + * \note MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT requires the built-in + * SHA-512 implementation to be present in the build. This implementation is + * included only if PSA_WANT_ALG_SHA_512 is enabled and this results in + * MBEDTLS_PSA_BUILTIN_ALG_SHA_512 being defined internally (i.e., no + * fully-featured, fallback-free accelerator driver is present). + * + * \note If MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT is defined when building + * for a non-Aarch64 build it will be silently ignored. + * + * \note Minimum compiler versions for this feature are Clang 7.0, + * armclang 6.9 or GCC 8.0. + * + * \note \c CFLAGS must be set to a minimum of \c -march=armv8.2-a+sha3 for + * armclang 6.9 + * + * \warning MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT cannot be defined at the + * same time as MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY. + * + * Requires: The SHA-512 built-in implementation + * + * Module: drivers/builtin/src/sha512.c + * + * Uncomment to have the library check for the A64 SHA-512 crypto extensions + * and use them if available. + */ +// #define MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT + +/** + * \def MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY + * + * Enable acceleration of the SHA-512 and SHA-384 cryptographic hash algorithms + * with the ARMv8 cryptographic extensions, which must be available at runtime + * or else an illegal instruction fault will occur. + * + * \note MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT requires the built-in + * SHA-512 implementation to be present in the build. This implementation is + * included only if PSA_WANT_ALG_SHA_512 is enabled and this results in + * MBEDTLS_PSA_BUILTIN_ALG_SHA_512 being defined internally (i.e., no + * fully-featured, fallback-free accelerator driver is present). + * + * \note This allows builds with a smaller code size than with + * MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT + * + * \note Minimum compiler versions for this feature are Clang 7.0, + * armclang 6.9 or GCC 8.0. + * + * \note \c CFLAGS must be set to a minimum of \c -march=armv8.2-a+sha3 for + * armclang 6.9 + * + * \warning MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY cannot be defined at the same + * time as MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT. + * + * Requires: The SHA-512 built-in implementation + * + * Module: drivers/builtin/src/sha512.c + * + * Uncomment to have the library use the A64 SHA-512 crypto extensions + * unconditionally. + */ +// #define MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY + +/* ECP options */ +// #define MBEDTLS_ECP_FIXED_POINT_OPTIM 1 /**< Enable fixed-point speed-up */ +// #define MBEDTLS_ECP_WINDOW_SIZE 4 /**< Maximum window size used */ + +/* MPI / BIGNUM options */ +// #define MBEDTLS_MPI_MAX_SIZE 1024 /**< Maximum number of bytes for usable MPIs. */ +// #define MBEDTLS_MPI_WINDOW_SIZE 2 /**< Maximum window size used. */ + +/* RSA OPTIONS */ +// #define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 /**< Minimum RSA key size that can be +// generated in bits (Minimum possible value is 128 bits) */ + +/** \} name SECTION: Builtin drivers */ + +/* Do not enable except for testing. Will be removed in a future minor version. + */ +#define TF_PSA_CRYPTO_ALLOW_REMOVED_MECHANISMS +#endif /* PSA_CRYPTO_CONFIG_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Src/mbedtls_v4/mbedtls_config.h b/tests/functional/stm32/nucleo_u545re_q/Src/mbedtls_v4/mbedtls_config.h new file mode 100644 index 000000000..b34657c71 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Src/mbedtls_v4/mbedtls_config.h @@ -0,0 +1,1206 @@ +/** + * \file mbedtls_config.h + * + * \brief Configuration options (set of defines) + * + * This set of compile-time options may be used to enable + * or disable features selectively, and reduce the global + * memory footprint. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + */ + +/** + * This is an optional version symbol that enables compatibility handling of + * config files. + * + * It is equal to the #MBEDTLS_VERSION_NUMBER of the Mbed TLS version that + * introduced the config format we want to be compatible with. + */ +#define MBEDTLS_CONFIG_VERSION 0x04000000 + +/** + * \name SECTION: Platform abstraction layer + * + * This section sets platform specific settings. + * \{ + */ + +/** + * \def MBEDTLS_NET_C + * + * Enable the TCP and UDP over IPv6/IPv4 networking routines. + * + * \note This module only works on POSIX/Unix (including Linux, BSD and OS X) + * and Windows. For other platforms, you'll want to disable it, and write your + * own networking callbacks to be passed to \c mbedtls_ssl_set_bio(). + * + * \note See also our Knowledge Base article about porting to a new + * environment: + * https://mbed-tls.readthedocs.io/en/latest/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS + * + * Module: library/net_sockets.c + * + * This module provides networking routines. + */ +// #define MBEDTLS_NET_C + +/** + * \def MBEDTLS_TIMING_ALT + * + * Uncomment to provide your own alternate implementation for + * mbedtls_timing_get_timer(), mbedtls_set_alarm(), mbedtls_set/get_delay() + * + * Only works if you have MBEDTLS_TIMING_C enabled. + * + * You will need to provide a header "timing_alt.h" and an implementation at + * compile time. + */ +// #define MBEDTLS_TIMING_ALT + +/** + * \def MBEDTLS_TIMING_C + * + * Enable the semi-portable timing interface. + * + * \note The provided implementation only works on POSIX/Unix (including Linux, + * BSD and OS X) and Windows. On other platforms, you can either disable that + * module and provide your own implementations of the callbacks needed by + * \c mbedtls_ssl_set_timer_cb() for DTLS, or leave it enabled and provide + * your own implementation of the whole module by setting + * \c MBEDTLS_TIMING_ALT in the current file. + * + * \note The timing module will include time.h on suitable platforms + * regardless of the setting of MBEDTLS_HAVE_TIME, unless + * MBEDTLS_TIMING_ALT is used. See timing.c for more information. + * + * \note See also our Knowledge Base article about porting to a new + * environment: + * https://mbed-tls.readthedocs.io/en/latest/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS + * + * Module: library/timing.c + */ +// #define MBEDTLS_TIMING_C + +/** \} name SECTION: Platform abstraction layer */ + +/** + * \name SECTION: General configuration options + * + * This section contains Mbed TLS build settings that are not associated + * with a particular module. + * \{ + */ + +/** + * \def MBEDTLS_ERROR_C + * + * Enable error code to error string conversion. + * + * Module: library/error.c + * Caller: + * + * This module enables mbedtls_strerror(). + */ +// #define MBEDTLS_ERROR_C + +/** + * \def MBEDTLS_ERROR_STRERROR_DUMMY + * + * Enable a dummy error function to make use of mbedtls_strerror() in + * third party libraries easier when MBEDTLS_ERROR_C is disabled + * (no effect when MBEDTLS_ERROR_C is enabled). + * + * You can safely disable this if MBEDTLS_ERROR_C is enabled, or if you're + * not using mbedtls_strerror() or error_strerror() in your application. + * + * Disable if you run into name conflicts and want to really remove the + * mbedtls_strerror() + */ +// #define MBEDTLS_ERROR_STRERROR_DUMMY + +/** + * \def MBEDTLS_VERSION_C + * + * Enable run-time version information. + * + * Module: library/version.c + * + * This module provides run-time version information. + */ +// #define MBEDTLS_VERSION_C + +/** + * \def MBEDTLS_VERSION_FEATURES + * + * Allow run-time checking of compile-time enabled features. Thus allowing users + * to check at run-time if the library is for instance compiled with threading + * support via mbedtls_version_check_feature(). + * + * Requires: MBEDTLS_VERSION_C + * + * Comment this to disable run-time checking and save ROM space + */ +// #define MBEDTLS_VERSION_FEATURES + +/** + * \def MBEDTLS_CONFIG_FILE + * + * If defined, this is a header which will be included instead of + * `"mbedtls/mbedtls_config.h"`. + * This header file specifies the compile-time configuration of Mbed TLS. + * Unlike other configuration options, this one must be defined on the + * compiler command line: a definition in `mbedtls_config.h` would have + * no effect. + * + * This macro is expanded after an \#include directive. This is a popular but + * non-standard feature of the C language, so this feature is only available + * with compilers that perform macro expansion on an \#include line. + * + * The value of this symbol is typically a path in double quotes, either + * absolute or relative to a directory on the include search path. + */ +// #define MBEDTLS_CONFIG_FILE "mbedtls/mbedtls_config.h" + +/** + * \def MBEDTLS_USER_CONFIG_FILE + * + * If defined, this is a header which will be included after + * `"mbedtls/mbedtls_config.h"` or #MBEDTLS_CONFIG_FILE. + * This allows you to modify the default configuration, including the ability + * to undefine options that are enabled by default. + * + * This macro is expanded after an \#include directive. This is a popular but + * non-standard feature of the C language, so this feature is only available + * with compilers that perform macro expansion on an \#include line. + * + * The value of this symbol is typically a path in double quotes, either + * absolute or relative to a directory on the include search path. + */ +// #define MBEDTLS_USER_CONFIG_FILE "/dev/null" + +/** \} name SECTION: General configuration options */ + +/** + * \name SECTION: TLS feature selection + * + * This section sets support for features that are or are not needed + * within the modules that are enabled. + * \{ + */ + +/** + * \def MBEDTLS_SSL_NULL_CIPHERSUITES + * + * Enable ciphersuites without encryption. + * + * Warning: Only do so when you know what you are doing. This allows for + * channels without any encryption. All data are transmitted in clear. + * + * Uncomment this macro to enable the NULL ciphersuites + */ +// #define MBEDTLS_SSL_NULL_CIPHERSUITES + +/** + * \def MBEDTLS_DEBUG_C + * + * Enable the debug functions. + * + * Module: library/debug.c + * Caller: library/ssl_msg.c + * library/ssl_tls.c + * library/ssl_tls12_*.c + * library/ssl_tls13_*.c + * + * This module provides debugging functions. + */ +// #define MBEDTLS_DEBUG_C + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED + * + * Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS. + * + * Requires: PSA_WANT_ALG_ECDH + * PSA_WANT_ALG_ECDSA + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 + */ +// #define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED + * + * Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS. + * + * Requires: PSA_WANT_ALG_ECDH + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 + */ +// #define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED + * + * Enable the ECDHE-RSA based ciphersuite modes in SSL / TLS. + * + * Requires: PSA_WANT_ALG_ECDH + * PSA_WANT_ALG_RSA_PKCS1V15_SIGN + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 + */ +// #define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED + * + * Enable the ECJPAKE based ciphersuite modes in SSL / TLS. + * + * \warning This is currently experimental. EC J-PAKE support is based on the + * Thread v1.0.0 specification; incompatible changes to the specification + * might still happen. For this reason, this is disabled by default. + * + * Requires: PSA_WANT_ALG_JPAKE + * PSA_WANT_ALG_SHA_256 + * PSA_WANT_ECC_SECP_R1_256 + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8 + */ +// #define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_PSK_ENABLED + * + * Enable the PSK based ciphersuite modes in SSL / TLS. + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256 + */ +// #define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED + +/** + * \def MBEDTLS_SSL_ALL_ALERT_MESSAGES + * + * Enable sending of alert messages in case of encountered errors as per RFC. + * If you choose not to send the alert messages, Mbed TLS can still communicate + * with other servers, only debugging of failures is harder. + * + * The advantage of not sending alert messages, is that no information is given + * about reasons for failures thus preventing adversaries of gaining intel. + * + * Enable sending of all alert messages + */ +// #define MBEDTLS_SSL_ALL_ALERT_MESSAGES + +/** + * \def MBEDTLS_SSL_ALPN + * + * Enable support for RFC 7301 Application Layer Protocol Negotiation. + * + * Comment this macro to disable support for ALPN. + */ +// #define MBEDTLS_SSL_ALPN + +/** + * \def MBEDTLS_SSL_ASYNC_PRIVATE + * + * Enable asynchronous external private key operations in SSL. This allows + * you to configure an SSL connection to call an external cryptographic + * module to perform private key operations instead of performing the + * operation inside the library. + * + * Requires: MBEDTLS_X509_CRT_PARSE_C + */ +// #define MBEDTLS_SSL_ASYNC_PRIVATE + +/** + * \def MBEDTLS_SSL_CACHE_C + * + * Enable simple SSL cache implementation. + * + * Module: library/ssl_cache.c + * Caller: + * + * Requires: MBEDTLS_SSL_CACHE_C + */ +// #define MBEDTLS_SSL_CACHE_C + +/** + * \def MBEDTLS_SSL_CLI_C + * + * Enable the SSL/TLS client code. + * + * Module: library/ssl*_client.c + * Caller: + * + * Requires: MBEDTLS_SSL_TLS_C + * + * \warning You must call psa_crypto_init() before doing any TLS operations. + * + * This module is required for SSL/TLS client support. + */ +// #define MBEDTLS_SSL_CLI_C + +/** + * \def MBEDTLS_SSL_CONTEXT_SERIALIZATION + * + * Enable serialization of the TLS context structures, through use of the + * functions mbedtls_ssl_context_save() and mbedtls_ssl_context_load(). + * + * This pair of functions allows one side of a connection to serialize the + * context associated with the connection, then free or re-use that context + * while the serialized state is persisted elsewhere, and finally deserialize + * that state to a live context for resuming read/write operations on the + * connection. From a protocol perspective, the state of the connection is + * unaffected, in particular this is entirely transparent to the peer. + * + * Note: this is distinct from TLS session resumption, which is part of the + * protocol and fully visible by the peer. TLS session resumption enables + * establishing new connections associated to a saved session with shorter, + * lighter handshakes, while context serialization is a local optimization in + * handling a single, potentially long-lived connection. + * + * Enabling these APIs makes some SSL structures larger, as 64 extra bytes are + * saved after the handshake to allow for more efficient serialization, so if + * you don't need this feature you'll save RAM by disabling it. + * + * Requires: PSA_WANT_ALG_GCM or PSA_WANT_ALG_CCM or PSA_WANT_ALG_CHACHA20_POLY1305 + * + * Comment to disable the context serialization APIs. + */ +// #define MBEDTLS_SSL_CONTEXT_SERIALIZATION + +/** + * \def MBEDTLS_SSL_COOKIE_C + * + * Enable basic implementation of DTLS cookies for hello verification. + * + * Module: library/ssl_cookie.c + * Caller: + */ +// #define MBEDTLS_SSL_COOKIE_C + +/** + * \def MBEDTLS_SSL_DEBUG_ALL + * + * Enable the debug messages in SSL module for all issues. + * Debug messages have been disabled in some places to prevent timing + * attacks due to (unbalanced) debugging function calls. + * + * If you need all error reporting you should enable this during debugging, + * but remove this for production servers that should log as well. + * + * Uncomment this macro to report all debug messages on errors introducing + * a timing side-channel. + * + */ +// #define MBEDTLS_SSL_DEBUG_ALL + +/** + * \def MBEDTLS_SSL_DTLS_ANTI_REPLAY + * + * Enable support for the anti-replay mechanism in DTLS. + * + * Requires: MBEDTLS_SSL_TLS_C + * MBEDTLS_SSL_PROTO_DTLS + * + * \warning Disabling this is often a security risk! + * See mbedtls_ssl_conf_dtls_anti_replay() for details. + * + * Comment this to disable anti-replay in DTLS. + */ +// #define MBEDTLS_SSL_DTLS_ANTI_REPLAY + +/** + * \def MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE + * + * Enable server-side support for clients that reconnect from the same port. + * + * Some clients unexpectedly close the connection and try to reconnect using the + * same source port. This needs special support from the server to handle the + * new connection securely, as described in section 4.2.8 of RFC 6347. This + * flag enables that support. + * + * Requires: MBEDTLS_SSL_DTLS_HELLO_VERIFY + * + * Comment this to disable support for clients reusing the source port. + */ +// #define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE + +/** + * \def MBEDTLS_SSL_DTLS_CONNECTION_ID + * + * Enable support for the DTLS Connection ID (CID) extension, + * which allows to identify DTLS connections across changes + * in the underlying transport. The CID functionality is described + * in RFC 9146. + * + * Setting this option enables the SSL APIs `mbedtls_ssl_set_cid()`, + * mbedtls_ssl_get_own_cid()`, `mbedtls_ssl_get_peer_cid()` and + * `mbedtls_ssl_conf_cid()`. See the corresponding documentation for + * more information. + * + * The maximum lengths of outgoing and incoming CIDs can be configured + * through the options + * - MBEDTLS_SSL_CID_OUT_LEN_MAX + * - MBEDTLS_SSL_CID_IN_LEN_MAX. + * + * Requires: MBEDTLS_SSL_PROTO_DTLS + * + * Uncomment to enable the Connection ID extension. + */ +// #define MBEDTLS_SSL_DTLS_CONNECTION_ID + +/** + * \def MBEDTLS_SSL_DTLS_HELLO_VERIFY + * + * Enable support for HelloVerifyRequest on DTLS servers. + * + * This feature is highly recommended to prevent DTLS servers being used as + * amplifiers in DoS attacks against other hosts. It should always be enabled + * unless you know for sure amplification cannot be a problem in the + * environment in which your server operates. + * + * \warning Disabling this can be a security risk! (see above) + * + * Requires: MBEDTLS_SSL_PROTO_DTLS + * + * Comment this to disable support for HelloVerifyRequest. + */ +// #define MBEDTLS_SSL_DTLS_HELLO_VERIFY + +/** + * \def MBEDTLS_SSL_DTLS_SRTP + * + * Enable support for negotiation of DTLS-SRTP (RFC 5764) + * through the use_srtp extension. + * + * \note This feature provides the minimum functionality required + * to negotiate the use of DTLS-SRTP and to allow the derivation of + * the associated SRTP packet protection key material. + * In particular, the SRTP packet protection itself, as well as the + * demultiplexing of RTP and DTLS packets at the datagram layer + * (see Section 5 of RFC 5764), are not handled by this feature. + * Instead, after successful completion of a handshake negotiating + * the use of DTLS-SRTP, the extended key exporter API + * mbedtls_ssl_conf_export_keys_cb() should be used to implement + * the key exporter described in Section 4.2 of RFC 5764 and RFC 5705 + * (this is implemented in the SSL example programs). + * The resulting key should then be passed to an SRTP stack. + * + * Setting this option enables the runtime API + * mbedtls_ssl_conf_dtls_srtp_protection_profiles() + * through which the supported DTLS-SRTP protection + * profiles can be configured. You must call this API at + * runtime if you wish to negotiate the use of DTLS-SRTP. + * + * Requires: MBEDTLS_SSL_PROTO_DTLS + * + * Uncomment this to enable support for use_srtp extension. + */ +// #define MBEDTLS_SSL_DTLS_SRTP + +/** + * \def MBEDTLS_SSL_EARLY_DATA + * + * Enable support for RFC 8446 TLS 1.3 early data. + * + * Requires: MBEDTLS_SSL_SESSION_TICKETS and either + * MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED or + * MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED + * + * Comment this to disable support for early data. If MBEDTLS_SSL_PROTO_TLS1_3 + * is not enabled, this option does not have any effect on the build. + * + * \note The maximum amount of early data can be set with + * MBEDTLS_SSL_MAX_EARLY_DATA_SIZE. + * + */ +// #define MBEDTLS_SSL_EARLY_DATA + +/** \def MBEDTLS_SSL_ENCRYPT_THEN_MAC + * + * Enable support for Encrypt-then-MAC, RFC 7366. + * + * This allows peers that both support it to use a more robust protection for + * ciphersuites using CBC, providing deep resistance against timing attacks + * on the padding or underlying cipher. + * + * This only affects CBC ciphersuites, and is useless if none is defined. + * + * Requires: MBEDTLS_SSL_PROTO_TLS1_2 + * + * Comment this macro to disable support for Encrypt-then-MAC + */ +// #define MBEDTLS_SSL_ENCRYPT_THEN_MAC + +/** \def MBEDTLS_SSL_EXTENDED_MASTER_SECRET + * + * Enable support for RFC 7627: Session Hash and Extended Master Secret + * Extension. + * + * This was introduced as "the proper fix" to the Triple Handshake family of + * attacks, but it is recommended to always use it (even if you disable + * renegotiation), since it actually fixes a more fundamental issue in the + * original SSL/TLS design, and has implications beyond Triple Handshake. + * + * Requires: MBEDTLS_SSL_PROTO_TLS1_2 + * + * Comment this macro to disable support for Extended Master Secret. + */ +// #define MBEDTLS_SSL_EXTENDED_MASTER_SECRET + +/** + * \def MBEDTLS_SSL_KEEP_PEER_CERTIFICATE + * + * This option controls the availability of the API mbedtls_ssl_get_peer_cert() + * giving access to the peer's certificate after completion of the handshake. + * + * Unless you need mbedtls_ssl_peer_cert() in your application, it is + * recommended to disable this option for reduced RAM usage. + * + * \note If this option is disabled, mbedtls_ssl_get_peer_cert() is still + * defined, but always returns \c NULL. + * + * \note This option has no influence on the protection against the + * triple handshake attack. Even if it is disabled, Mbed TLS will + * still ensure that certificates do not change during renegotiation, + * for example by keeping a hash of the peer's certificate. + * + * \note This option is required if MBEDTLS_SSL_PROTO_TLS1_3 is set. + * + * Comment this macro to disable storing the peer's certificate + * after the handshake. + */ +// #define MBEDTLS_SSL_KEEP_PEER_CERTIFICATE + +/** + * \def MBEDTLS_SSL_MAX_FRAGMENT_LENGTH + * + * Enable support for RFC 6066 max_fragment_length extension in SSL. + * + * Comment this macro to disable support for the max_fragment_length extension + */ +// #define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH + +/** + * \def MBEDTLS_SSL_PROTO_DTLS + * + * Enable support for DTLS (all available versions). + * + * Enable this and MBEDTLS_SSL_PROTO_TLS1_2 to enable DTLS 1.2. + * + * Requires: MBEDTLS_SSL_PROTO_TLS1_2 + * + * Comment this macro to disable support for DTLS + */ +// #define MBEDTLS_SSL_PROTO_DTLS + +/** + * \def MBEDTLS_SSL_PROTO_TLS1_2 + * + * Enable support for TLS 1.2 (and DTLS 1.2 if DTLS is enabled). + * + * Requires: PSA_WANT_ALG_SHA_256 or PSA_WANT_ALG_SHA_384 + * + * Comment this macro to disable support for TLS 1.2 / DTLS 1.2 + */ +// #define MBEDTLS_SSL_PROTO_TLS1_2 + +/** + * \def MBEDTLS_SSL_PROTO_TLS1_3 + * + * Enable support for TLS 1.3. + * + * \note See docs/architecture/tls13-support.md for a description of the TLS + * 1.3 support that this option enables. + * + * Requires: MBEDTLS_SSL_KEEP_PEER_CERTIFICATE + * Requires: MBEDTLS_PSA_CRYPTO_C + * + * Uncomment this macro to enable the support for TLS 1.3. + */ +// #define MBEDTLS_SSL_PROTO_TLS1_3 + +/** + * \def MBEDTLS_SSL_RECORD_SIZE_LIMIT + * + * Enable support for RFC 8449 record_size_limit extension in SSL (TLS 1.3 only). + * + * Requires: MBEDTLS_SSL_PROTO_TLS1_3 + * + * Uncomment this macro to enable support for the record_size_limit extension + */ +// #define MBEDTLS_SSL_RECORD_SIZE_LIMIT + +/** + * \def MBEDTLS_SSL_KEYING_MATERIAL_EXPORT + * + * When this option is enabled, the client and server can extract additional + * shared symmetric keys after an SSL handshake using the function + * mbedtls_ssl_export_keying_material(). + * + * The process for deriving the keys is specified in RFC 5705 for TLS 1.2 and + * in RFC 8446, Section 7.5, for TLS 1.3. + * + * Comment this macro to disable mbedtls_ssl_export_keying_material(). + */ +// #define MBEDTLS_SSL_KEYING_MATERIAL_EXPORT + +/** + * \def MBEDTLS_SSL_RENEGOTIATION + * + * Enable support for TLS renegotiation. + * + * The two main uses of renegotiation are (1) refresh keys on long-lived + * connections and (2) client authentication after the initial handshake. + * If you don't need renegotiation, it's probably better to disable it, since + * it has been associated with security issues in the past and is easy to + * misuse/misunderstand. + * + * Requires: MBEDTLS_SSL_PROTO_TLS1_2 + * + * Comment this to disable support for renegotiation. + * + * \note Even if this option is disabled, both client and server are aware + * of the Renegotiation Indication Extension (RFC 5746) used to + * prevent the SSL renegotiation attack (see RFC 5746 Sect. 1). + * (See \c mbedtls_ssl_conf_legacy_renegotiation for the + * configuration of this extension). + * + */ +// #define MBEDTLS_SSL_RENEGOTIATION + +/** + * \def MBEDTLS_SSL_SERVER_NAME_INDICATION + * + * Enable support for RFC 6066 server name indication (SNI) in SSL. + * + * Requires: MBEDTLS_X509_CRT_PARSE_C + * + * Comment this macro to disable support for server name indication in SSL + */ +// #define MBEDTLS_SSL_SERVER_NAME_INDICATION + +/** + * \def MBEDTLS_SSL_SESSION_TICKETS + * + * Enable support for RFC 5077 session tickets in SSL. + * Client-side, provides full support for session tickets (maintenance of a + * session store remains the responsibility of the application, though). + * Server-side, you also need to provide callbacks for writing and parsing + * tickets, including authenticated encryption and key management. Example + * callbacks are provided by MBEDTLS_SSL_TICKET_C. + * + * Comment this macro to disable support for SSL session tickets + */ +// #define MBEDTLS_SSL_SESSION_TICKETS + +/** + * \def MBEDTLS_SSL_SRV_C + * + * Enable the SSL/TLS server code. + * + * Module: library/ssl*_server.c + * Caller: + * + * Requires: MBEDTLS_SSL_TLS_C + * + * \warning You must call psa_crypto_init() before doing any TLS operations. + * + * This module is required for SSL/TLS server support. + */ +// #define MBEDTLS_SSL_SRV_C + +/** + * \def MBEDTLS_SSL_TICKET_C + * + * Enable an implementation of TLS server-side callbacks for session tickets. + * + * Module: library/ssl_ticket.c + * Caller: + * + * Requires: PSA_WANT_ALG_GCM or PSA_WANT_ALG_CCM or PSA_WANT_ALG_CHACHA20_POLY1305 + */ +// #define MBEDTLS_SSL_TICKET_C + +/** + * \def MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE + * + * Enable TLS 1.3 middlebox compatibility mode. + * + * As specified in Section D.4 of RFC 8446, TLS 1.3 offers a compatibility + * mode to make a TLS 1.3 connection more likely to pass through middle boxes + * expecting TLS 1.2 traffic. + * + * Turning on the compatibility mode comes at the cost of a few added bytes + * on the wire, but it doesn't affect compatibility with TLS 1.3 implementations + * that don't use it. Therefore, unless transmission bandwidth is critical and + * you know that middlebox compatibility issues won't occur, it is therefore + * recommended to set this option. + * + * Comment to disable compatibility mode for TLS 1.3. If + * MBEDTLS_SSL_PROTO_TLS1_3 is not enabled, this option does not have any + * effect on the build. + * + */ +// #define MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE + +/** + * \def MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED + * + * Enable TLS 1.3 ephemeral key exchange mode. + * + * Requires: PSA_WANT_ALG_ECDH or PSA_WANT_ALG_FFDH + * MBEDTLS_X509_CRT_PARSE_C + * and at least one of: + * PSA_WANT_ALG_ECDSA + * PSA_WANT_ALG_RSA_PSS + * + * Comment to disable support for the ephemeral key exchange mode in TLS 1.3. + * If MBEDTLS_SSL_PROTO_TLS1_3 is not enabled, this option does not have any + * effect on the build. + * + */ +// #define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED + +/** + * \def MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED + * + * Enable TLS 1.3 PSK key exchange mode. + * + * Comment to disable support for the PSK key exchange mode in TLS 1.3. If + * MBEDTLS_SSL_PROTO_TLS1_3 is not enabled, this option does not have any + * effect on the build. + * + */ +// #define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED + +/** + * \def MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED + * + * Enable TLS 1.3 PSK ephemeral key exchange mode. + * + * Requires: PSA_WANT_ALG_ECDH or PSA_WANT_ALG_FFDH + * + * Comment to disable support for the PSK ephemeral key exchange mode in + * TLS 1.3. If MBEDTLS_SSL_PROTO_TLS1_3 is not enabled, this option does not + * have any effect on the build. + * + */ +// #define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED + +/** + * \def MBEDTLS_SSL_TLS_C + * + * Enable the generic SSL/TLS code. + * + * Module: library/ssl_tls.c + * Caller: library/ssl*_client.c + * library/ssl*_server.c + * + * Requires: PSA_WANT_ALG_SHA_256 or PSA_WANT_ALG_SHA_384 + * and at least one of the MBEDTLS_SSL_PROTO_XXX defines + * + * This module is required for SSL/TLS. + */ +// #define MBEDTLS_SSL_TLS_C + +/** + * \def MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH + * + * When this option is enabled, the SSL buffer will be resized automatically + * based on the negotiated maximum fragment length in each direction. + * + * Requires: MBEDTLS_SSL_MAX_FRAGMENT_LENGTH + */ +// #define MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH + +// #define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default +// 256 or 384 bits) +// */ #define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */ #define +// MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /**< 1 day */ + +/** \def MBEDTLS_SSL_CID_IN_LEN_MAX + * + * The maximum length of CIDs used for incoming DTLS messages. + * + */ +// #define MBEDTLS_SSL_CID_IN_LEN_MAX 32 + +/** \def MBEDTLS_SSL_CID_OUT_LEN_MAX + * + * The maximum length of CIDs used for outgoing DTLS messages. + * + */ +// #define MBEDTLS_SSL_CID_OUT_LEN_MAX 32 + +/** \def MBEDTLS_SSL_CID_TLS1_3_PADDING_GRANULARITY + * + * This option controls the use of record plaintext padding + * in TLS 1.3 and when using the Connection ID extension in DTLS 1.2. + * + * The padding will always be chosen so that the length of the + * padded plaintext is a multiple of the value of this option. + * + * Note: A value of \c 1 means that no padding will be used + * for outgoing records. + * + * Note: On systems lacking division instructions, + * a power of two should be preferred. + */ +// #define MBEDTLS_SSL_CID_TLS1_3_PADDING_GRANULARITY 16 + +/** + * Complete list of ciphersuites to use, in order of preference. + * + * \warning No dependency checking is done on that field! This option can only + * be used to restrict the set of available ciphersuites. It is your + * responsibility to make sure the needed modules are active. + * + * Use this to save a few hundred bytes of ROM (default ordering of all + * available ciphersuites) and a few to a few hundred bytes of RAM. + * + * The value below is only an example, not the default. + */ +// #define MBEDTLS_SSL_CIPHERSUITES +// MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 + +// #define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in +// seconds if HAVE_TIME, or in number of cookies issued */ + +/** \def MBEDTLS_SSL_DTLS_MAX_BUFFERING + * + * Maximum number of heap-allocated bytes for the purpose of + * DTLS handshake message reassembly and future message buffering. + * + * This should be at least 9/8 * MBEDTLS_SSL_IN_CONTENT_LEN + * to account for a reassembled handshake message of maximum size, + * together with its reassembly bitmap. + * + * A value of 2 * MBEDTLS_SSL_IN_CONTENT_LEN (32768 by default) + * should be sufficient for all practical situations as it allows + * to reassembly a large handshake message (such as a certificate) + * while buffering multiple smaller handshake messages. + * + */ +// #define MBEDTLS_SSL_DTLS_MAX_BUFFERING 32768 + +/** \def MBEDTLS_SSL_IN_CONTENT_LEN + * + * Maximum length (in bytes) of incoming plaintext fragments. + * + * This determines the size of the incoming TLS I/O buffer in such a way + * that it is capable of holding the specified amount of plaintext data, + * regardless of the protection mechanism used. + * + * \note When using a value less than the default of 16KB on the client, it is + * recommended to use the Maximum Fragment Length (MFL) extension to + * inform the server about this limitation. On the server, there + * is no supported, standardized way of informing the client about + * restriction on the maximum size of incoming messages, and unless + * the limitation has been communicated by other means, it is recommended + * to only change the outgoing buffer size #MBEDTLS_SSL_OUT_CONTENT_LEN + * while keeping the default value of 16KB for the incoming buffer. + * + * Uncomment to set the maximum plaintext size of the incoming I/O buffer. + */ +// #define MBEDTLS_SSL_IN_CONTENT_LEN 16384 + +/** + * \def MBEDTLS_SSL_MAX_EARLY_DATA_SIZE + * + * The default maximum amount of 0-RTT data. See the documentation of + * \c mbedtls_ssl_conf_max_early_data_size() for more information. + * + * It must be positive and smaller than UINT32_MAX. + * + * If MBEDTLS_SSL_EARLY_DATA is not defined, this default value does not + * have any impact on the build. + */ +// #define MBEDTLS_SSL_MAX_EARLY_DATA_SIZE 1024 + +/** \def MBEDTLS_SSL_OUT_CONTENT_LEN + * + * Maximum length (in bytes) of outgoing plaintext fragments. + * + * This determines the size of the outgoing TLS I/O buffer in such a way + * that it is capable of holding the specified amount of plaintext data, + * regardless of the protection mechanism used. + * + * It is possible to save RAM by setting a smaller outward buffer, while keeping + * the default inward 16384 byte buffer to conform to the TLS specification. + * + * The minimum required outward buffer size is determined by the handshake + * protocol's usage. Handshaking will fail if the outward buffer is too small. + * The specific size requirement depends on the configured ciphers and any + * certificate data which is sent during the handshake. + * + * Uncomment to set the maximum plaintext size of the outgoing I/O buffer. + */ +// #define MBEDTLS_SSL_OUT_CONTENT_LEN 16384 + +/** + * \def MBEDTLS_SSL_TLS1_3_DEFAULT_NEW_SESSION_TICKETS + * + * Default number of NewSessionTicket messages to be sent by a TLS 1.3 server + * after handshake completion. This is not used in TLS 1.2 and relevant only if + * the MBEDTLS_SSL_SESSION_TICKETS option is enabled. + * + */ +// #define MBEDTLS_SSL_TLS1_3_DEFAULT_NEW_SESSION_TICKETS 1 + +/** + * \def MBEDTLS_SSL_TLS1_3_TICKET_AGE_TOLERANCE + * + * Maximum allowed ticket age difference in milliseconds tolerated between + * server and client. Default value is 6000. This is not used in TLS 1.2. + * + * - The client ticket age is the time difference between the time when the + * client proposes to the server to use the ticket and the time the client + * received the ticket from the server. + * - The server ticket age is the time difference between the time when the + * server receives a proposition from the client to use the ticket and the + * time when the ticket was created by the server. + * + * The ages might be different due to the client and server clocks not running + * at the same pace. The typical accuracy of an RTC crystal is ±100 to ±20 parts + * per million (360 to 72 milliseconds per hour). Default tolerance window is + * 6s, thus in the worst case clients and servers must sync up their system time + * every 6000/360/2~=8 hours. + * + * See section 8.3 of the TLS 1.3 specification(RFC 8446) for more information. + */ +// #define MBEDTLS_SSL_TLS1_3_TICKET_AGE_TOLERANCE 6000 + +/** + * \def MBEDTLS_SSL_TLS1_3_TICKET_NONCE_LENGTH + * + * Size in bytes of a ticket nonce. This is not used in TLS 1.2. + * + * This must be less than 256. + */ +// #define MBEDTLS_SSL_TLS1_3_TICKET_NONCE_LENGTH 32 + +/** \} name SECTION: TLS feature selection */ + +/** + * \name SECTION: X.509 feature selection + * + * This section sets Certificate related options. + * \{ + */ + +/** + * \def MBEDTLS_PKCS7_C + * + * Enable PKCS #7 core for using PKCS #7-formatted signatures. + * RFC Link - https://tools.ietf.org/html/rfc2315 + * + * Module: library/pkcs7.c + * + * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_PK_PARSE_C, + * MBEDTLS_X509_CRT_PARSE_C MBEDTLS_X509_CRL_PARSE_C, + * MBEDTLS_MD_C + * + * This module is required for the PKCS #7 parsing modules. + */ +// #define MBEDTLS_PKCS7_C + +/** + * \def MBEDTLS_X509_CREATE_C + * + * Enable X.509 core for creating certificates. + * + * Module: library/x509_create.c + * + * Requires: MBEDTLS_ASN1_WRITE_C, MBEDTLS_PK_PARSE_C + * + * \warning You must call psa_crypto_init() before doing any X.509 operation. + * + * This module is the basis for creating X.509 certificates and CSRs. + */ +// #define MBEDTLS_X509_CREATE_C + +/** + * \def MBEDTLS_X509_CRL_PARSE_C + * + * Enable X.509 CRL parsing. + * + * Module: library/x509_crl.c + * Caller: library/x509_crt.c + * + * Requires: MBEDTLS_X509_USE_C + * + * This module is required for X.509 CRL parsing. + */ +// #define MBEDTLS_X509_CRL_PARSE_C + +/** + * \def MBEDTLS_X509_CRT_PARSE_C + * + * Enable X.509 certificate parsing. + * + * Module: library/x509_crt.c + * Caller: library/ssl_tls.c + * library/ssl*_client.c + * library/ssl*_server.c + * + * Requires: MBEDTLS_X509_USE_C + * + * This module is required for X.509 certificate parsing. + */ +// #define MBEDTLS_X509_CRT_PARSE_C + +/** + * \def MBEDTLS_X509_CRT_WRITE_C + * + * Enable creating X.509 certificates. + * + * Module: library/x509_crt_write.c + * + * Requires: MBEDTLS_X509_CREATE_C + * + * This module is required for X.509 certificate creation. + */ +// #define MBEDTLS_X509_CRT_WRITE_C + +/** + * \def MBEDTLS_X509_CSR_PARSE_C + * + * Enable X.509 Certificate Signing Request (CSR) parsing. + * + * Module: library/x509_csr.c + * Caller: library/x509_crt_write.c + * + * Requires: MBEDTLS_X509_USE_C + * + * This module is used for reading X.509 certificate request. + */ +// #define MBEDTLS_X509_CSR_PARSE_C + +/** + * \def MBEDTLS_X509_CSR_WRITE_C + * + * Enable creating X.509 Certificate Signing Requests (CSR). + * + * Module: library/x509_csr_write.c + * + * Requires: MBEDTLS_X509_CREATE_C + * + * This module is required for X.509 certificate request writing. + */ +// #define MBEDTLS_X509_CSR_WRITE_C + +/** + * \def MBEDTLS_X509_REMOVE_INFO + * + * Disable mbedtls_x509_*_info() and related APIs. + * + * Uncomment to omit mbedtls_x509_*_info(), as well as mbedtls_debug_print_crt() + * and other functions/constants only used by these functions, thus reducing + * the code footprint by several KB. + */ +// #define MBEDTLS_X509_REMOVE_INFO + +/** + * \def MBEDTLS_X509_RSASSA_PSS_SUPPORT + * + * Enable parsing and verification of X.509 certificates, CRLs and CSRS + * signed with RSASSA-PSS (aka PKCS#1 v2.1). + * + * Requires: PSA_WANT_ALG_RSA_PSS + * + * Comment this macro to disallow using RSASSA-PSS in certificates. + */ +// #define MBEDTLS_X509_RSASSA_PSS_SUPPORT + +/** + * \def MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK + * + * If set, this enables the X.509 API `mbedtls_x509_crt_verify_with_ca_cb()` + * and the SSL API `mbedtls_ssl_conf_ca_cb()` which allow users to configure + * the set of trusted certificates through a callback instead of a linked + * list. + * + * This is useful for example in environments where a large number of trusted + * certificates is present and storing them in a linked list isn't efficient + * enough, or when the set of trusted certificates changes frequently. + * + * See the documentation of `mbedtls_x509_crt_verify_with_ca_cb()` and + * `mbedtls_ssl_conf_ca_cb()` for more information. + * + * Requires: MBEDTLS_X509_CRT_PARSE_C + * + * Uncomment to enable trusted certificate callbacks. + */ +// #define MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK + +/** + * \def MBEDTLS_X509_USE_C + * + * Enable X.509 core for using certificates. + * + * Module: library/x509.c + * Caller: library/x509_crl.c + * library/x509_crt.c + * library/x509_csr.c + * + * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_PK_PARSE_C + * + * \warning You must call psa_crypto_init() before doing any X.509 operation. + * + * This module is required for the X.509 parsing modules. + */ +// #define MBEDTLS_X509_USE_C + +// #define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in +// bytes including the null terminator character ('\0'). */ #define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 +// /**< Maximum number of intermediate CAs in a verification chain. */ + +/** \} name SECTION: X.509 feature selection */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Src/mbedtls_v4/mbedtls_platform.c b/tests/functional/stm32/nucleo_u545re_q/Src/mbedtls_v4/mbedtls_platform.c new file mode 100644 index 000000000..0b6c99900 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Src/mbedtls_v4/mbedtls_platform.c @@ -0,0 +1,46 @@ +#include +#include + +#include "main.h" +#include "mbedtls/platform.h" +#include "mbedtls/platform_time.h" +#include "mbedtls/platform_util.h" +#include "stm32u5xx_hal.h" + +mbedtls_ms_time_t mbedtls_ms_time(void) +{ + /* Use STM32 HAL millisecond tick. HAL_GetTick() returns uint32_t ms since startup. + See Page 48 of UM1725 Rev 8. */ + return (mbedtls_ms_time_t)HAL_GetTick(); +} + +int mbedtls_platform_get_entropy(psa_driver_get_entropy_flags_t flags, size_t *estimate_bits, + unsigned char *output, size_t output_size) +{ + /* We don't implement any flags. */ + if (flags != 0) { + return PSA_ERROR_NOT_SUPPORTED; + } + + HAL_StatusTypeDef hal_status = HAL_OK; + uint32_t random_data; + size_t bytes_left = output_size; + + while (bytes_left) { + hal_status = HAL_RNG_GenerateRandomNumber(&hrng, &random_data); + if (hal_status != HAL_OK) { + mbedtls_platform_zeroize(&random_data, sizeof(random_data)); + return PSA_ERROR_INSUFFICIENT_ENTROPY; + } + + size_t cpy_cnt = bytes_left < sizeof(random_data) ? bytes_left : sizeof(random_data); + memcpy(output, &random_data, cpy_cnt); + bytes_left -= cpy_cnt; + output += cpy_cnt; + } + + *estimate_bits = 8 * output_size; + + mbedtls_platform_zeroize(&random_data, sizeof(random_data)); + return 0; +} \ No newline at end of file diff --git a/tests/functional/stm32/nucleo_u545re_q/Src/startup_stm32u545retxq.s b/tests/functional/stm32/nucleo_u545re_q/Src/startup_stm32u545retxq.s new file mode 100644 index 000000000..2e42c0e39 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Src/startup_stm32u545retxq.s @@ -0,0 +1,654 @@ +/** + ****************************************************************************** + * @file startup_stm32u545retx.s + * @author Auto-generated by STM32CubeIDE + * @brief STM32U545RETx device vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +.syntax unified +.cpu cortex-m33 +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + .size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32U545RETx vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word SecureFault_Handler + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word RTC_IRQHandler + .word RTC_S_IRQHandler + .word TAMP_IRQHandler + .word RAMCFG_IRQHandler + .word FLASH_IRQHandler + .word FLASH_S_IRQHandler + .word GTZC_IRQHandler + .word RCC_IRQHandler + .word RCC_S_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word EXTI5_IRQHandler + .word EXTI6_IRQHandler + .word EXTI7_IRQHandler + .word EXTI8_IRQHandler + .word EXTI9_IRQHandler + .word EXTI10_IRQHandler + .word EXTI11_IRQHandler + .word EXTI12_IRQHandler + .word EXTI13_IRQHandler + .word EXTI14_IRQHandler + .word EXTI15_IRQHandler + .word IWDG_IRQHandler + .word SAES_IRQHandler + .word GPDMA1_Channel0_IRQHandler + .word GPDMA1_Channel1_IRQHandler + .word GPDMA1_Channel2_IRQHandler + .word GPDMA1_Channel3_IRQHandler + .word GPDMA1_Channel4_IRQHandler + .word GPDMA1_Channel5_IRQHandler + .word GPDMA1_Channel6_IRQHandler + .word GPDMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word DAC1_IRQHandler + .word FDCAN1_IT0_IRQHandler + .word FDCAN1_IT1_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word TIM5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word 0 + .word USART3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word LPUART1_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word TIM15_IRQHandler + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word COMP_IRQHandler + .word USB_IRQHandler + .word CRS_IRQHandler + .word 0 + .word OCTOSPI1_IRQHandler + .word PWR_S3WU_IRQHandler + .word SDMMC1_IRQHandler + .word 0 + .word GPDMA1_Channel8_IRQHandler + .word GPDMA1_Channel9_IRQHandler + .word GPDMA1_Channel10_IRQHandler + .word GPDMA1_Channel11_IRQHandler + .word GPDMA1_Channel12_IRQHandler + .word GPDMA1_Channel13_IRQHandler + .word GPDMA1_Channel14_IRQHandler + .word GPDMA1_Channel15_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SAI1_IRQHandler + .word 0 + .word TSC_IRQHandler + .word AES_IRQHandler + .word RNG_IRQHandler + .word FPU_IRQHandler + .word HASH_IRQHandler + .word PKA_IRQHandler + .word LPTIM3_IRQHandler + .word SPI3_IRQHandler + .word I2C4_ER_IRQHandler + .word I2C4_EV_IRQHandler + .word MDF1_FLT0_IRQHandler + .word MDF1_FLT1_IRQHandler + .word 0 + .word 0 + .word 0 + .word ICACHE_IRQHandler + .word OTFDEC1_IRQHandler + .word 0 + .word LPTIM4_IRQHandler + .word DCACHE1_IRQHandler + .word ADF1_IRQHandler + .word ADC4_IRQHandler + .word LPDMA1_Channel0_IRQHandler + .word LPDMA1_Channel1_IRQHandler + .word LPDMA1_Channel2_IRQHandler + .word LPDMA1_Channel3_IRQHandler + .word 0 + .word DCMI_PSSI_IRQHandler + .word 0 + .word 0 + .word 0 + .word CORDIC_IRQHandler + .word FMAC_IRQHandler + .word LSECSSD_IRQHandler + + .size g_pfnVectors, .-g_pfnVectors + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SecureFault_Handler + .thumb_set SecureFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak RTC_S_IRQHandler + .thumb_set RTC_S_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak RAMCFG_IRQHandler + .thumb_set RAMCFG_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak FLASH_S_IRQHandler + .thumb_set FLASH_S_IRQHandler,Default_Handler + + .weak GTZC_IRQHandler + .thumb_set GTZC_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak RCC_S_IRQHandler + .thumb_set RCC_S_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak SAES_IRQHandler + .thumb_set SAES_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak DAC1_IRQHandler + .thumb_set DAC1_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak OCTOSPI1_IRQHandler + .thumb_set OCTOSPI1_IRQHandler,Default_Handler + + .weak PWR_S3WU_IRQHandler + .thumb_set PWR_S3WU_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel8_IRQHandler + .thumb_set GPDMA1_Channel8_IRQHandler,Default_Handler + + .weak GPDMA1_Channel9_IRQHandler + .thumb_set GPDMA1_Channel9_IRQHandler,Default_Handler + + .weak GPDMA1_Channel10_IRQHandler + .thumb_set GPDMA1_Channel10_IRQHandler,Default_Handler + + .weak GPDMA1_Channel11_IRQHandler + .thumb_set GPDMA1_Channel11_IRQHandler,Default_Handler + + .weak GPDMA1_Channel12_IRQHandler + .thumb_set GPDMA1_Channel12_IRQHandler,Default_Handler + + .weak GPDMA1_Channel13_IRQHandler + .thumb_set GPDMA1_Channel13_IRQHandler,Default_Handler + + .weak GPDMA1_Channel14_IRQHandler + .thumb_set GPDMA1_Channel14_IRQHandler,Default_Handler + + .weak GPDMA1_Channel15_IRQHandler + .thumb_set GPDMA1_Channel15_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak MDF1_FLT0_IRQHandler + .thumb_set MDF1_FLT0_IRQHandler,Default_Handler + + .weak MDF1_FLT1_IRQHandler + .thumb_set MDF1_FLT1_IRQHandler,Default_Handler + + .weak ICACHE_IRQHandler + .thumb_set ICACHE_IRQHandler,Default_Handler + + .weak OTFDEC1_IRQHandler + .thumb_set OTFDEC1_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak DCACHE1_IRQHandler + .thumb_set DCACHE1_IRQHandler,Default_Handler + + .weak ADF1_IRQHandler + .thumb_set ADF1_IRQHandler,Default_Handler + + .weak ADC4_IRQHandler + .thumb_set ADC4_IRQHandler,Default_Handler + + .weak LPDMA1_Channel0_IRQHandler + .thumb_set LPDMA1_Channel0_IRQHandler,Default_Handler + + .weak LPDMA1_Channel1_IRQHandler + .thumb_set LPDMA1_Channel1_IRQHandler,Default_Handler + + .weak LPDMA1_Channel2_IRQHandler + .thumb_set LPDMA1_Channel2_IRQHandler,Default_Handler + + .weak LPDMA1_Channel3_IRQHandler + .thumb_set LPDMA1_Channel3_IRQHandler,Default_Handler + + .weak DCMI_PSSI_IRQHandler + .thumb_set DCMI_PSSI_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak FMAC_IRQHandler + .thumb_set FMAC_IRQHandler,Default_Handler + + .weak LSECSSD_IRQHandler + .thumb_set LSECSSD_IRQHandler,Default_Handler + diff --git a/tests/functional/stm32/nucleo_u545re_q/Src/stm32u5xx_hal_msp.c b/tests/functional/stm32/nucleo_u545re_q/Src/stm32u5xx_hal_msp.c new file mode 100644 index 000000000..b8396d899 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Src/stm32u5xx_hal_msp.c @@ -0,0 +1,274 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32u5xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** + * @brief RNG MSP Initialization + * This function configures the hardware resources used in this example + * @param hrng: RNG handle pointer + * @retval None + */ +void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng) +{ + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if (hrng->Instance == RNG) { + /* USER CODE BEGIN RNG_MspInit 0 */ + + /* USER CODE END RNG_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RNG; + PeriphClkInit.RngClockSelection = RCC_RNGCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_RNG_CLK_ENABLE(); + /* USER CODE BEGIN RNG_MspInit 1 */ + + /* USER CODE END RNG_MspInit 1 */ + } +} + +/** + * @brief RNG MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hrng: RNG handle pointer + * @retval None + */ +void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) +{ + if (hrng->Instance == RNG) { + /* USER CODE BEGIN RNG_MspDeInit 0 */ + + /* USER CODE END RNG_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RNG_CLK_DISABLE(); + /* USER CODE BEGIN RNG_MspDeInit 1 */ + + /* USER CODE END RNG_MspDeInit 1 */ + } +} + +/** + * @brief SPI MSP Initialization + * This function configures the hardware resources used in this example + * @param hspi: SPI handle pointer + * @retval None + */ +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if (hspi->Instance == SPI1) { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SPI1; + PeriphClkInit.Spi1ClockSelection = RCC_SPI1CLKSOURCE_HSI; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + } +} + +/** + * @brief SPI MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hspi: SPI handle pointer + * @retval None + */ +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + if (hspi->Instance == SPI1) { + /* USER CODE BEGIN SPI1_MspDeInit 0 */ + + /* USER CODE END SPI1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI1_CLK_DISABLE(); + + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7); + + /* USER CODE BEGIN SPI1_MspDeInit 1 */ + + /* USER CODE END SPI1_MspDeInit 1 */ + } +} + +/** + * @brief UART MSP Initialization + * This function configures the hardware resources used in this example + * @param huart: UART handle pointer + * @retval None + */ +void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if (huart->Instance == USART1) { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1; + PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_9 | GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } +} + +/** + * @brief UART MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param huart: UART handle pointer + * @retval None + */ +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + if (huart->Instance == USART1) { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9 | GPIO_PIN_10); + + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Src/stm32u5xx_it.c b/tests/functional/stm32/nucleo_u545re_q/Src/stm32u5xx_it.c new file mode 100644 index 000000000..ca0114e27 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Src/stm32u5xx_it.c @@ -0,0 +1,199 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32u5xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_it.h" + +#include "main.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32U5xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32u5xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Src/syscalls.c b/tests/functional/stm32/nucleo_u545re_q/Src/syscalls.c new file mode 100644 index 000000000..9b6c2b0b1 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Src/syscalls.c @@ -0,0 +1,166 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeIDE + * @brief STM32CubeIDE Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + +char *__env[1] = {0}; +char **environ = __env; + +/* Functions */ +void initialise_monitor_handles() {} + +int _getpid(void) { return 1; } + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit(int status) +{ + _kill(status, -1); + while (1) { + } /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} diff --git a/tests/functional/stm32/nucleo_u545re_q/Src/sysmem.c b/tests/functional/stm32/nucleo_u545re_q/Src/sysmem.c new file mode 100644 index 000000000..be892dfd3 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Src/sysmem.c @@ -0,0 +1,77 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeIDE + * @brief STM32CubeIDE System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the newlib libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} diff --git a/tests/functional/stm32/nucleo_u545re_q/Src/system_stm32u5xx.c b/tests/functional/stm32/nucleo_u545re_q/Src/system_stm32u5xx.c new file mode 100644 index 000000000..82cc1b2d9 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Src/system_stm32u5xx.c @@ -0,0 +1,363 @@ +/** + ****************************************************************************** + * @file system_stm32u5xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32u5xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the MSI (4 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32u5xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | MSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB3 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL1_SRC | No clock + *----------------------------------------------------------------------------- + * PLL1_M | 1 + *----------------------------------------------------------------------------- + * PLL1_N | 8 + *----------------------------------------------------------------------------- + * PLL1_P | 7 + *----------------------------------------------------------------------------- + * PLL1_Q | 2 + *----------------------------------------------------------------------------- + * PLL1_R | 2 + *----------------------------------------------------------------------------- + * PLL2_SRC | NA + *----------------------------------------------------------------------------- + * PLL2_M | NA + *----------------------------------------------------------------------------- + * PLL2_N | NA + *----------------------------------------------------------------------------- + * PLL2_P | NA + *----------------------------------------------------------------------------- + * PLL2_Q | NA + *----------------------------------------------------------------------------- + * PLL2_R | NA + *----------------------------------------------------------------------------- + * PLL3_SRC | NA + *----------------------------------------------------------------------------- + * PLL3_M | NA + *----------------------------------------------------------------------------- + * PLL3_N | NA + *----------------------------------------------------------------------------- + * PLL3_P | NA + *----------------------------------------------------------------------------- + * Require 48MHz for USB FS, | Disabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32U5xx_system + * @{ + */ + +/** @addtogroup STM32U5xx_System_Private_Includes + * @{ + */ + +#include + +#include "stm32u5xx.h" + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Defines + * @{ + */ + +#if !defined(HSE_VALUE) +#define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined(MSI_VALUE) +#define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +#if !defined(HSI_VALUE) +#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET \ + 0x00000000UL /*!< Vector Table base offset field. \ + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ + /******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Variables + * @{ + */ +/* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. +*/ +uint32_t SystemCoreClock = 4000000U; + +const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; +const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; +const uint32_t MSIRangeTable[16] = {48000000U, 24000000U, 16000000U, 12000000U, 4000000U, 2000000U, + 1330000U, 1000000U, 3072000U, 1536000U, 1024000U, 768000U, + 400000U, 200000U, 133000U, 100000U}; +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ +/* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U) | (3UL << 22U)); /* set CP10 and CP11 Full Access */ +#endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC->CR = RCC_CR_MSISON; + + /* Reset CFGR register */ + RCC->CFGR1 = 0U; + RCC->CFGR2 = 0U; + RCC->CFGR3 = 0U; + + /* Reset HSEON, CSSON , HSION, PLLxON bits */ + RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON); + + /* Reset PLLCFGR register */ + RCC->PLL1CFGR = 0U; + + /* Reset HSEBYP bit */ + RCC->CR &= ~(RCC_CR_HSEBYP); + + /* Disable all interrupts */ + RCC->CIER = 0U; + +/* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) MSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t pllr, pllsource, pllm, tmp, pllfracen, msirange; + float_t fracn1, pllvco; + + /* Get MSI Range frequency--------------------------------------------------*/ + if (READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U) { + /* MSISRANGE from RCC_CSR applies */ + msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos; + } + else { + /* MSIRANGE from RCC_CR applies */ + msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos; + } + + /*MSI frequency range in HZ*/ + msirange = MSIRangeTable[msirange]; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR1 & RCC_CFGR1_SWS) { + case 0x00: /* MSI used as system clock source */ + SystemCoreClock = msirange; + break; + + case 0x04: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + + case 0x08: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x0C: /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); + pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; + pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> + RCC_PLL1FRACR_PLL1FRACN_Pos)); + + switch (pllsource) { + case 0x00: /* No clock sent to PLL*/ + pllvco = (float_t)0U; + break; + + case 0x02: /* HSI used as PLL clock source */ + pllvco = ((float_t)HSI_VALUE / (float_t)pllm); + break; + + case 0x03: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm); + break; + + default: /* MSI used as PLL clock source */ + pllvco = ((float_t)msirange / (float_t)pllm); + break; + } + + pllvco = pllvco * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + + (fracn1 / (float_t)0x2000) + (float_t)1U); + pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U); + SystemCoreClock = (uint32_t)((uint32_t)pllvco / pllr); + break; + + default: + SystemCoreClock = msirange; + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Src/wolfcrypt/user_settings.h b/tests/functional/stm32/nucleo_u545re_q/Src/wolfcrypt/user_settings.h new file mode 100644 index 000000000..dc20ca90f --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Src/wolfcrypt/user_settings.h @@ -0,0 +1,26 @@ +#ifndef USER_SETTINGS_H +#define USER_SETTINGS_H + +#define WOLFCRYPT_ONLY // Build only wolfCrypt library. +#define NO_OLD_RNGNAME // Resolves collision between STM32 HAL 'RNG' and WolfSSL 'RNG'. +// #define USE_FAST_MATH + +// We will provide custom implementation for seed generation. +extern int wolfcrypt_custom_seed_gen(unsigned char *output, unsigned int sz); +#define CUSTOM_RAND_GENERATE_SEED wolfcrypt_custom_seed_gen + +#define WOLFSSL_SMALL_STACK // Offload stack usage to heap where possible. +#define WOLFSSL_MALLOC_CHECK // Optional: Safety check for malloc failures. + +#define NO_FILESYSTEM // Prevents filesystem errors on bare metal. +#undef WOLFSSL_SYS_CA_CERTS // Force disable system CA certs (fixes dirent.h / filesystem errors). +#define NO_WRITEV // IO vector write support usually missing. +#define NO_WRITE_TEMP_FILES +#define NO_DEV_RANDOM // We use STM32's RNG, not /dev/random. +#define NO_MAIN_DRIVER + +#define WOLFSSL_USER_IO // Disable the default BSD socket callbacks. + +#define SINGLE_THREADED // No threads. + +#endif /* USER_SETTINGS_H */ \ No newline at end of file diff --git a/tests/functional/stm32/nucleo_u545re_q/Src/wolfcrypt/wolfcrypt_platform.c b/tests/functional/stm32/nucleo_u545re_q/Src/wolfcrypt/wolfcrypt_platform.c new file mode 100644 index 000000000..f7bd20918 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Src/wolfcrypt/wolfcrypt_platform.c @@ -0,0 +1,30 @@ +#include +#include +#include +#include + +#include "main.h" +#include "stm32u5xx_hal.h" + +int wolfcrypt_custom_seed_gen(unsigned char *output, unsigned int sz) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + uint32_t random_data; + size_t bytes_left = sz; + + while (bytes_left) { + hal_status = HAL_RNG_GenerateRandomNumber(&hrng, &random_data); + if (hal_status != HAL_OK) { + wc_ForceZero(&random_data, sizeof(random_data)); + return RNG_FAILURE_E; + } + + size_t cpy_cnt = bytes_left < sizeof(random_data) ? bytes_left : sizeof(random_data); + memcpy(output, &random_data, cpy_cnt); + bytes_left -= cpy_cnt; + output += cpy_cnt; + } + + wc_ForceZero(&random_data, sizeof(random_data)); + return 0; +} \ No newline at end of file diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/BSP/STM32U5xx_Nucleo/LICENSE.md b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/BSP/STM32U5xx_Nucleo/LICENSE.md new file mode 100644 index 000000000..9226612ae --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/BSP/STM32U5xx_Nucleo/LICENSE.md @@ -0,0 +1,27 @@ +Copyright 2021 STMicroelectronics. +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its contributors +may be used to endorse or promote products derived from this software without +specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/BSP/STM32U5xx_Nucleo/stm32u5xx_nucleo.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/BSP/STM32U5xx_Nucleo/stm32u5xx_nucleo.c new file mode 100644 index 000000000..8db7c2c5f --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/BSP/STM32U5xx_Nucleo/stm32u5xx_nucleo.c @@ -0,0 +1,795 @@ +/** + ****************************************************************************** + * @file stm32u5xx_nucleo.c + * @author MCD Application Team + * @brief This file provides set of firmware functions to manage: + * - LEDs and push-button available on STM32U5xx-Nucleo Kit + * from STMicroelectronics + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_nucleo.h" +#if defined(__ICCARM__) +#include +#endif /* __ICCARM__ */ + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32U5XX_NUCLEO + * @{ + */ + +/** @addtogroup STM32U5XX_NUCLEO_LOW_LEVEL LOW LEVEL + * @brief This file provides set of firmware functions to manage Leds and push-button + * available on STM32U5xx-Nucleo Kit from STMicroelectronics. + * @{ + */ + +/** @defgroup STM32U5XX_NUCLEO_LOW_LEVEL_Private_Defines LOW LEVEL Private Defines + * @{ + */ + +/** + * @} + */ + +/** @defgroup STM32U5XX_NUCLEO_LOW_LEVEL_Private_TypesDefinitions LOW LEVEL Private Types Definitions + * @{ + */ +typedef void (* BSP_EXTI_LineCallback)(void); +/** + * @} + */ + +/** @defgroup STM32U5XX_NUCLEO_LOW_LEVEL_Exported_Variables LOW LEVEL Exported Variables + * @{ + */ +EXTI_HandleTypeDef hpb_exti[BUTTONn]; +#if (USE_BSP_COM_FEATURE > 0) +UART_HandleTypeDef hcom_uart[COMn]; +USART_TypeDef *COM_USART[COMn] = {COM1_UART}; +#endif /* USE_BSP_COM_FEATURE */ +/** + * @} + */ +/** @defgroup STM32U5XX_NUCLEO_LOW_LEVEL_Private_Variables LOW LEVEL Private Variables + * @{ + */ +static GPIO_TypeDef *LED_PORT[LEDn] = +{ +#if defined (USE_NUCLEO_144) + LED1_GPIO_PORT, +#endif /* defined (USE_NUCLEO_144) */ + LED2_GPIO_PORT, +#if defined (USE_NUCLEO_144) + LED3_GPIO_PORT +#endif /* defined (USE_NUCLEO_144) */ +}; + +static const uint16_t LED_PIN[LEDn] = +{ +#if defined (USE_NUCLEO_144) + LED1_PIN, +#endif /* defined (USE_NUCLEO_144) */ + LED2_PIN, +#if defined (USE_NUCLEO_144) + LED3_PIN +#endif /* defined (USE_NUCLEO_144) */ +}; + +static GPIO_TypeDef *BUTTON_PORT[BUTTONn] = {BUTTON_USER_GPIO_PORT}; +static const uint16_t BUTTON_PIN[BUTTONn] = {BUTTON_USER_PIN}; +static const IRQn_Type BUTTON_IRQn[BUTTONn] = {BUTTON_USER_EXTI_IRQn}; + +#if (USE_BSP_COM_FEATURE > 0) +#if (USE_COM_LOG > 0) +static COM_TypeDef COM_ActiveLogPort = COM1; +#endif /* USE_COM_LOG */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +static uint32_t IsComMspCbValid[COMn] = {0}; +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS == 1) */ +#endif /* USE_BSP_COM_FEATURE) */ + +/** + * @} + */ + +/** @defgroup STM32U5XX_NUCLEO_LOW_LEVEL_Private_FunctionPrototypes LOW LEVEL Private Functions Prototypes + * @{ + */ +static void BUTTON_USER_EXTI_Callback(void); +#if (USE_BSP_COM_FEATURE > 0) +static void COM1_MspInit(UART_HandleTypeDef *huart); +static void COM1_MspDeInit(UART_HandleTypeDef *huart); +#endif /* USE_BSP_COM_FEATURE */ + +#if defined(__ICCARM__) +/* New definition from EWARM V9, compatible with EWARM8 */ +int iar_fputc(int ch); +#define PUTCHAR_PROTOTYPE int iar_fputc(int ch) +#elif defined ( __CC_ARM ) || defined(__ARMCC_VERSION) +/* ARM Compiler 5/6*/ +#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#elif defined(__GNUC__) +#define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#endif /* __ICCARM__ */ + +/** + * @} + */ + +/** @defgroup STM32U5XX_NUCLEO_LOW_LEVEL_Exported_Functions LOW LEVEL Exported Functions + * @{ + */ + +/** + * @brief This method returns the STM32U5XX NUCLEO BSP Driver revision + * @retval version: 0xXYZR (8bits for each decimal, R for RC) + */ +int32_t BSP_GetVersion(void) +{ + return (int32_t)STM32U5XX_NUCLEO_BSP_VERSION; +} + +/** + * @brief This method returns the board name + * @retval pointer to the board name string + */ +const uint8_t *BSP_GetBoardName(void) +{ + return (uint8_t *)STM32U5XX_NUCLEO_BSP_BOARD_NAME; +} + +/** + * @brief This method returns the board ID + * @retval pointer to the board name string + */ +const uint8_t *BSP_GetBoardID(void) +{ + return (uint8_t *)STM32U5XX_NUCLEO_BSP_BOARD_ID; +} + +/** + * @brief Configures LED GPIO. + * @param Led Specifies the Led to be configured. + * This parameter can be one of following parameters: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @retval BSP status + */ +int32_t BSP_LED_Init(Led_TypeDef Led) +{ + int32_t ret = BSP_ERROR_NONE; + GPIO_InitTypeDef gpio_init_structure; +#if defined (USE_NUCLEO_144) + uint32_t pwrenabled = 0U; +#endif /* USE_NUCLEO_144 */ + + if ((Led != LED2) +#if defined (USE_NUCLEO_144) + && (Led != LED1) && (Led != LED3) +#endif /* defined (USE_NUCLEO_144) */ + ) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + /* Enable the GPIO LED Clock */ + if (Led == LED2) + { + LED2_GPIO_CLK_ENABLE(); + } +#if defined (USE_NUCLEO_144) + else if (Led == LED1) + { + LED1_GPIO_CLK_ENABLE(); + } + else /* Led == Led3 */ + { + /* Enable VddIO2 for Led3 */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrenabled = 1U; + } + + HAL_PWREx_EnableVddIO2(); + + if (pwrenabled == 1U) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + + LED3_GPIO_CLK_ENABLE(); + } +#endif /* defined (USE_NUCLEO_144) */ + /* Configure the GPIO_LED pin */ + gpio_init_structure.Pin = LED_PIN[Led]; + gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + gpio_init_structure.Pull = GPIO_NOPULL; + gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + + HAL_GPIO_Init(LED_PORT[Led], &gpio_init_structure); + } + + return ret; +} + +/** + * @brief DeInit LEDs. + * @param Led LED to be de-init. + * This parameter can be one of the following values: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @note Led DeInit does not disable the GPIO clock nor disable the Mfx + * @retval BSP status + */ +int32_t BSP_LED_DeInit(Led_TypeDef Led) +{ + int32_t ret = BSP_ERROR_NONE; + GPIO_InitTypeDef gpio_init_structure; + + if ((Led != LED2) +#if defined (USE_NUCLEO_144) + && (Led != LED1) && (Led != LED3) +#endif /* defined (USE_NUCLEO_144) */ + ) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + /* Turn off LED */ + HAL_GPIO_WritePin(LED_PORT[Led], LED_PIN[Led], GPIO_PIN_RESET); + /* DeInit the GPIO_LED pin */ + gpio_init_structure.Pin = LED_PIN[Led]; + HAL_GPIO_DeInit(LED_PORT[Led], gpio_init_structure.Pin); + } + + return ret; +} + +/** + * @brief Turns selected LED On. + * @param Led Specifies the Led to be set on. + * This parameter can be one of following parameters: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @retval BSP status + */ +int32_t BSP_LED_On(Led_TypeDef Led) +{ + int32_t ret = BSP_ERROR_NONE; + + if ((Led != LED2) +#if defined (USE_NUCLEO_144) + && (Led != LED1) && (Led != LED3) +#endif /* defined (USE_NUCLEO_144) */ + ) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + HAL_GPIO_WritePin(LED_PORT[Led], LED_PIN[Led], GPIO_PIN_SET); + } + + return ret; +} + +/** + * @brief Turns selected LED Off. + * @param Led: Specifies the Led to be set off. + * This parameter can be one of following parameters: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @retval BSP status + */ +int32_t BSP_LED_Off(Led_TypeDef Led) +{ + int32_t ret = BSP_ERROR_NONE; + + if ((Led != LED2) +#if defined (USE_NUCLEO_144) + && (Led != LED1) && (Led != LED3) +#endif /* defined (USE_NUCLEO_144) */ + ) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + HAL_GPIO_WritePin(LED_PORT[Led], LED_PIN[Led], GPIO_PIN_RESET); + } + + return ret; +} + +/** + * @brief Toggles the selected LED. + * @param Led Specifies the Led to be toggled. + * This parameter can be one of following parameters: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @retval BSP status + */ +int32_t BSP_LED_Toggle(Led_TypeDef Led) +{ + int32_t ret = BSP_ERROR_NONE; + + if ((Led != LED2) +#if defined (USE_NUCLEO_144) + && (Led != LED1) && (Led != LED3) +#endif /* defined (USE_NUCLEO_144) */ + ) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + HAL_GPIO_TogglePin(LED_PORT[Led], LED_PIN[Led]); + } + + return ret; +} + +/** + * @brief Get the state of the selected LED. + * @param Led LED to get its state + * This parameter can be one of following parameters: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @retval LED status + */ +int32_t BSP_LED_GetState(Led_TypeDef Led) +{ + int32_t ret; + + if ((Led != LED2) +#if defined (USE_NUCLEO_144) + && (Led != LED1) && (Led != LED3) +#endif /* defined (USE_NUCLEO_144) */ + ) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + ret = (int32_t)HAL_GPIO_ReadPin(LED_PORT [Led], LED_PIN [Led]); + } + + return ret; +} + +/** + * @brief Configures button GPIO and EXTI Line. + * @param Button Button to be configured + * This parameter can be one of the following values: + * @arg BUTTON_USER: Wakeup Push Button + * @param ButtonMode Button mode + * This parameter can be one of the following values: + * @arg BUTTON_MODE_GPIO: Button will be used as simple IO + * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line + * with interrupt generation capability + */ +int32_t BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode) +{ + GPIO_InitTypeDef gpio_init_structure; + static BSP_EXTI_LineCallback ButtonCallback[BUTTONn] = {BUTTON_USER_EXTI_Callback}; + static uint32_t BSP_BUTTON_PRIO [BUTTONn] = {BSP_BUTTON_USER_IT_PRIORITY}; + static const uint32_t BUTTON_EXTI_LINE[BUTTONn] = {BUTTON_USER_EXTI_LINE}; + + /* Enable the BUTTON clock */ + BUTTON_USER_GPIO_CLK_ENABLE(); + + gpio_init_structure.Pin = BUTTON_PIN [Button]; + gpio_init_structure.Pull = GPIO_PULLDOWN; + gpio_init_structure.Speed = GPIO_SPEED_FREQ_HIGH; + + if (ButtonMode == BUTTON_MODE_GPIO) + { + /* Configure Button pin as input */ + gpio_init_structure.Mode = GPIO_MODE_INPUT; + HAL_GPIO_Init(BUTTON_PORT [Button], &gpio_init_structure); + } + else /* (ButtonMode == BUTTON_MODE_EXTI) */ + { + /* Configure Button pin as input with External interrupt */ + gpio_init_structure.Mode = GPIO_MODE_IT_RISING; + + HAL_GPIO_Init(BUTTON_PORT[Button], &gpio_init_structure); + + (void)HAL_EXTI_GetHandle(&hpb_exti[Button], BUTTON_EXTI_LINE[Button]); + (void)HAL_EXTI_RegisterCallback(&hpb_exti[Button], HAL_EXTI_COMMON_CB_ID, ButtonCallback[Button]); + + /* Enable and set Button EXTI Interrupt to the lowest priority */ + HAL_NVIC_SetPriority((BUTTON_IRQn[Button]), BSP_BUTTON_PRIO[Button], 0x00); + HAL_NVIC_EnableIRQ((BUTTON_IRQn[Button])); + } + + return BSP_ERROR_NONE; +} + +/** + * @brief Push Button DeInit. + * @param Button Button to be configured + * This parameter can be one of the following values: + * @arg BUTTON_USER: Wakeup Push Button + * @note PB DeInit does not disable the GPIO clock + */ +int32_t BSP_PB_DeInit(Button_TypeDef Button) +{ + GPIO_InitTypeDef gpio_init_structure; + + gpio_init_structure.Pin = BUTTON_PIN[Button]; + HAL_NVIC_DisableIRQ((IRQn_Type)(BUTTON_IRQn[Button])); + HAL_GPIO_DeInit(BUTTON_PORT[Button], gpio_init_structure.Pin); + + return BSP_ERROR_NONE; +} + +/** + * @brief Returns the selected button state. + * @param Button Button to be checked + * This parameter can be one of the following values: + * @arg BUTTON_USER: Wakeup Push Button + * @retval The Button GPIO pin value (GPIO_PIN_RESET = button pressed) + */ +int32_t BSP_PB_GetState(Button_TypeDef Button) +{ + return (int32_t)HAL_GPIO_ReadPin(BUTTON_PORT[Button], BUTTON_PIN[Button]); +} + +/** + * @brief BSP Button IRQ handler + * @param Button Can only be BUTTON_USER + * @retval None + */ +void BSP_PB_IRQHandler(Button_TypeDef Button) +{ + HAL_EXTI_IRQHandler(&hpb_exti[Button]); +} + +/** + * @brief BSP Push Button callback + * @param Button Specifies the pin connected EXTI line + * @retval None + */ +__weak void BSP_PB_Callback(Button_TypeDef Button) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Button); + + /* This function should be implemented by the user application. + It is called into this driver when an event on Button is triggered. */ +} + +#if (USE_BSP_COM_FEATURE > 0) +/** + * @brief Configures COM port. + * @param COM COM port to be configured. + * This parameter can be COM1 + * @param COM_Init Pointer to a UART_HandleTypeDef structure that contains the + * configuration information for the specified USART peripheral. + * @retval BSP error code + */ +int32_t BSP_COM_Init(COM_TypeDef COM, COM_InitTypeDef *COM_Init) +{ + int32_t ret = BSP_ERROR_NONE; + + if (COM >= COMn) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 0) + /* Init the UART Msp */ + COM1_MspInit(&hcom_uart[COM]); +#else + if (IsComMspCbValid[COM] == 0U) + { + if (BSP_COM_RegisterDefaultMspCallbacks(COM) != BSP_ERROR_NONE) + { + return BSP_ERROR_MSP_FAILURE; + } + } +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS == 0) */ + + if (MX_USART1_Init(&hcom_uart[COM], COM_Init) != HAL_OK) + { + ret = BSP_ERROR_PERIPH_FAILURE; + } + } + + return ret; +} + +/** + * @brief DeInit COM port. + * @param COM COM port to be configured. + * This parameter can be COM1 + * @retval BSP status + */ +int32_t BSP_COM_DeInit(COM_TypeDef COM) +{ + int32_t ret = BSP_ERROR_NONE; + + if (COM >= COMn) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + /* USART configuration */ + hcom_uart[COM].Instance = COM_USART[COM]; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 0) + COM1_MspDeInit(&hcom_uart[COM]); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS == 0) */ + + if (HAL_UART_DeInit(&hcom_uart[COM]) != HAL_OK) + { + ret = BSP_ERROR_PERIPH_FAILURE; + } + } + + return ret; +} + +/** + * @brief Configures COM port. + * @param huart USART handle + * @param COM_Init Pointer to a UART_HandleTypeDef structure that contains the + * configuration information for the specified USART peripheral. + * @retval HAL error code + */ +__weak HAL_StatusTypeDef MX_USART1_Init(UART_HandleTypeDef *huart, MX_UART_InitTypeDef *COM_Init) +{ + /* USART configuration */ + huart->Instance = COM_USART[COM1]; + huart->Init.BaudRate = COM_Init->BaudRate; + huart->Init.Mode = UART_MODE_TX_RX; + huart->Init.Parity = (uint32_t)COM_Init->Parity; + huart->Init.WordLength = (uint32_t)COM_Init->WordLength; + huart->Init.StopBits = (uint32_t)COM_Init->StopBits; + huart->Init.HwFlowCtl = (uint32_t)COM_Init->HwFlowCtl; + huart->Init.OverSampling = UART_OVERSAMPLING_8; + huart->Init.ClockPrescaler = UART_PRESCALER_DIV1; + return HAL_UART_Init(huart); +} + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register Default COM Msp Callbacks + * @param COM COM port to be configured. + * This parameter can be COM1 + * @retval BSP status + */ +int32_t BSP_COM_RegisterDefaultMspCallbacks(COM_TypeDef COM) +{ + int32_t ret = BSP_ERROR_NONE; + + if (COM >= COMn) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + __HAL_UART_RESET_HANDLE_STATE(&hcom_uart[COM]); + + /* Register default MspInit/MspDeInit Callback */ + if (HAL_UART_RegisterCallback(&hcom_uart[COM], HAL_UART_MSPINIT_CB_ID, COM1_MspInit) != HAL_OK) + { + ret = BSP_ERROR_PERIPH_FAILURE; + } + else if (HAL_UART_RegisterCallback(&hcom_uart[COM], HAL_UART_MSPDEINIT_CB_ID, COM1_MspDeInit) != HAL_OK) + { + ret = BSP_ERROR_PERIPH_FAILURE; + } + else + { + IsComMspCbValid[COM] = 1U; + } + } + + /* BSP status */ + return ret; +} + +/** + * @brief Register COM Msp Callback registering + * @param COM COM port to be configured. + * This parameter can be COM1 + * @param Callbacks pointer to COM1 MspInit/MspDeInit callback functions + * @retval BSP status + */ +int32_t BSP_COM_RegisterMspCallbacks(COM_TypeDef COM, BSP_COM_Cb_t *Callback) +{ + int32_t ret = BSP_ERROR_NONE; + + if (COM >= COMn) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + __HAL_UART_RESET_HANDLE_STATE(&hcom_uart[COM]); + + /* Register MspInit/MspDeInit Callbacks */ + if (HAL_UART_RegisterCallback(&hcom_uart[COM], HAL_UART_MSPINIT_CB_ID, Callback->pMspInitCb) != HAL_OK) + { + ret = BSP_ERROR_PERIPH_FAILURE; + } + else if (HAL_UART_RegisterCallback(&hcom_uart[COM], HAL_UART_MSPDEINIT_CB_ID, Callback->pMspDeInitCb) != HAL_OK) + { + ret = BSP_ERROR_PERIPH_FAILURE; + } + else + { + IsComMspCbValid[COM] = 1U; + } + } + /* BSP status */ + return ret; +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +#if (USE_COM_LOG > 0) +/** + * @brief Select the active COM port. + * @param COM COM port to be activated. + * This parameter can be COM1 + * @retval BSP status + */ +int32_t BSP_COM_SelectLogPort(COM_TypeDef COM) +{ + if (COM_ActiveLogPort != COM) + { + COM_ActiveLogPort = COM; + } + return BSP_ERROR_NONE; +} + +/** + * @brief Retargets the C library __write function to the IAR function iar_fputc. + * @param file: file descriptor. + * @param ptr: pointer to the buffer where the data is stored. + * @param len: length of the data to write in bytes. + * @retval length of the written data in bytes. + */ +#if defined(__ICCARM__) +size_t __write(int file, unsigned char const *ptr, size_t len) +{ + size_t idx; + unsigned char const *pdata = ptr; + + for (idx = 0; idx < len; idx++) + { + iar_fputc((int)*pdata); + pdata++; + } + return len; +} +#endif /* __ICCARM__ */ + +/** + * @brief Redirect console output to COM + */ +PUTCHAR_PROTOTYPE +{ + HAL_UART_Transmit(&hcom_uart [COM_ActiveLogPort], (uint8_t *) &ch, 1, COM_POLL_TIMEOUT); + return ch; +} +#endif /* USE_COM_LOG */ +#endif /* USE_BSP_COM_FEATURE */ + +/** + * @} + */ + +/** @defgroup STM32U5XX_NUCLEO_LOW_LEVEL_Private_Functions LOW LEVEL Private functions + * @{ + */ +/** + * @brief Key EXTI line detection callbacks. + * @retval BSP status + */ +static void BUTTON_USER_EXTI_Callback(void) +{ + BSP_PB_Callback(BUTTON_USER); +} + +#if (USE_BSP_COM_FEATURE > 0) +/** + * @brief Initializes UART MSP. + * @param huart UART handle + * @retval BSP status + */ +static void COM1_MspInit(UART_HandleTypeDef *huart) +{ + GPIO_InitTypeDef gpio_init_structure; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* Enable GPIO clock */ + COM1_TX_GPIO_CLK_ENABLE(); + COM1_RX_GPIO_CLK_ENABLE(); + + /* Enable USART clock */ + COM1_CLK_ENABLE(); + + /* Configure USART Tx as alternate function */ + gpio_init_structure.Pin = COM1_TX_PIN; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Speed = GPIO_SPEED_FREQ_HIGH; + gpio_init_structure.Pull = GPIO_PULLUP; + gpio_init_structure.Alternate = COM1_TX_AF; + HAL_GPIO_Init(COM1_TX_GPIO_PORT, &gpio_init_structure); + + /* Configure USART Rx as alternate function */ + gpio_init_structure.Pin = COM1_RX_PIN; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Alternate = COM1_RX_AF; + HAL_GPIO_Init(COM1_RX_GPIO_PORT, &gpio_init_structure); +} + +/** + * @brief Initialize USART3 Msp part + * @param huart UART handle + * @retval BSP status + */ +static void COM1_MspDeInit(UART_HandleTypeDef *huart) +{ + GPIO_InitTypeDef gpio_init_structure; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* COM GPIO pin configuration */ + gpio_init_structure.Pin = COM1_TX_PIN; + HAL_GPIO_DeInit(COM1_TX_GPIO_PORT, gpio_init_structure.Pin); + + gpio_init_structure.Pin = COM1_RX_PIN; + HAL_GPIO_DeInit(COM1_RX_GPIO_PORT, gpio_init_structure.Pin); + + /* Disable USART clock */ + COM1_CLK_DISABLE(); +} +#endif /* USE_BSP_COM_FEATURE */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/BSP/STM32U5xx_Nucleo/stm32u5xx_nucleo.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/BSP/STM32U5xx_Nucleo/stm32u5xx_nucleo.h new file mode 100644 index 000000000..5e5d34ffb --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/BSP/STM32U5xx_Nucleo/stm32u5xx_nucleo.h @@ -0,0 +1,323 @@ +/** + ****************************************************************************** + * @file stm32u5xx_nucleo.h + * @author MCD Application Team + * @brief This file contains definitions for: + * - LEDs and push-button available on STM32U5xx-Nucleo Kit + * from STMicroelectronics + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5XX_NUCLEO_H +#define STM32U5XX_NUCLEO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_nucleo_conf.h" +#include "stm32u5xx_nucleo_errno.h" + +#if (USE_BSP_COM_FEATURE == 1) +#include "stdio.h" +#endif /* USE_BSP_COM_FEATURE */ + +/** @addtogroup BSP + * @{ + */ + +/** @defgroup STM32U5XX_NUCLEO STM32U5XX_NUCLEO + * @{ + */ + +/** @defgroup STM32U5XX_NUCLEO_LOW_LEVEL LOW LEVEL + * @{ + */ + +/** + * @brief Define for STM32U5XX_NUCLEO board + */ +#if !defined (USE_STM32U5XX_NUCLEO) +#define USE_STM32U5XX_NUCLEO +#endif /* !defined (USE_STM32U5XX_NUCLEO) */ + +#if !defined (USE_NUCLEO_144) && !defined (USE_NUCLEO_64) +#error "Board Pin number not defined!! Add USE_NUCLEO_144 or USE_NUCLEO_64 define within stm32u5xx_nucleo_conf.h file" +#endif /* !defined (USE_NUCLEO_144) && !defined (USE_NUCLEO_64) */ + +/** @defgroup STM32U5XX_NUCLEO_LOW_LEVEL_Exported_Types LOW LEVEL Exported Types + * @{ + */ + +typedef enum +{ +#if defined (USE_NUCLEO_144) + LED1 = 0, + LED_GREEN = LED1, + LED2 = 1, + LED_BLUE = LED2, + LED3 = 2, + LED_RED = LED3, +#else + LED2 = 0, + LED_GREEN = LED2, +#endif /* defined (USE_NUCLEO_144) */ + LEDn +} Led_TypeDef; + +typedef enum +{ + BUTTON_USER = 0U, + BUTTONn +} Button_TypeDef; + +typedef enum +{ + BUTTON_MODE_GPIO = 0, + BUTTON_MODE_EXTI = 1 +} ButtonMode_TypeDef; + +#if (USE_BSP_COM_FEATURE > 0) +typedef enum +{ + COM1 = 0U, + COMn +} COM_TypeDef; + +typedef enum +{ + COM_STOPBITS_1 = UART_STOPBITS_1, + COM_STOPBITS_2 = UART_STOPBITS_2, +} COM_StopBitsTypeDef; + +typedef enum +{ + COM_PARITY_NONE = UART_PARITY_NONE, + COM_PARITY_EVEN = UART_PARITY_EVEN, + COM_PARITY_ODD = UART_PARITY_ODD, +} COM_ParityTypeDef; + +typedef enum +{ + COM_HWCONTROL_NONE = UART_HWCONTROL_NONE, + COM_HWCONTROL_RTS = UART_HWCONTROL_RTS, + COM_HWCONTROL_CTS = UART_HWCONTROL_CTS, + COM_HWCONTROL_RTS_CTS = UART_HWCONTROL_RTS_CTS, +} COM_HwFlowCtlTypeDef; + +typedef enum +{ + COM_WORDLENGTH_7B = UART_WORDLENGTH_7B, + COM_WORDLENGTH_8B = UART_WORDLENGTH_8B, + COM_WORDLENGTH_9B = UART_WORDLENGTH_9B, +} COM_WordLengthTypeDef; + +typedef struct +{ + uint32_t BaudRate; + COM_WordLengthTypeDef WordLength; + COM_StopBitsTypeDef StopBits; + COM_ParityTypeDef Parity; + COM_HwFlowCtlTypeDef HwFlowCtl; +} COM_InitTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +typedef struct +{ + void (* pMspInitCb)(UART_HandleTypeDef *); + void (* pMspDeInitCb)(UART_HandleTypeDef *); +} BSP_COM_Cb_t; +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS == 1) */ + +#define MX_UART_InitTypeDef COM_InitTypeDef + +#endif /* USE_BSP_COM_FEATURE */ + +/** + * @} + */ + +/** @defgroup STM32U5XX_NUCLEO_LOW_LEVEL_Exported_Constants LOW LEVEL Exported Constants + * @{ + */ + +/** + * @brief STM32U5XX NUCLEO BSP Driver version number V1.2.3 + */ +#define STM32U5XX_NUCLEO_BSP_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define STM32U5XX_NUCLEO_BSP_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ +#define STM32U5XX_NUCLEO_BSP_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ +#define STM32U5XX_NUCLEO_BSP_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define STM32U5XX_NUCLEO_BSP_VERSION ((STM32U5XX_NUCLEO_BSP_VERSION_MAIN << 24)\ + |(STM32U5XX_NUCLEO_BSP_VERSION_SUB1 << 16)\ + |(STM32U5XX_NUCLEO_BSP_VERSION_SUB2 << 8 )\ + |(STM32U5XX_NUCLEO_BSP_VERSION_RC)) + +#if defined (USE_NUCLEO_144) +#define STM32U5XX_NUCLEO_BSP_BOARD_NAME "NUCLEO-U575ZI-Q"; +#define STM32U5XX_NUCLEO_BSP_BOARD_ID "MB1549C"; +#else +#define STM32U5XX_NUCLEO_BSP_BOARD_NAME "NUCLEO-U545RE-Q"; +#define STM32U5XX_NUCLEO_BSP_BOARD_ID "MB1841A"; +#endif /* defined (USE_NUCLEO_144) */ + +/** @defgroup STM32U5XX_NUCLEO_LOW_LEVEL_LED LOW LEVEL LED + * @{ + */ +#if defined (USE_NUCLEO_144) +#define LED1_PIN GPIO_PIN_7 +#define LED1_GPIO_PORT GPIOC +#define LED1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define LED1_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE() + +#define LED2_PIN GPIO_PIN_7 +#define LED2_GPIO_PORT GPIOB +#define LED2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define LED2_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE() + +#define LED3_PIN GPIO_PIN_2 +#define LED3_GPIO_PORT GPIOG +#define LED3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE() +#define LED3_GPIO_CLK_DISABLE() __HAL_RCC_GPIOG_CLK_DISABLE() +#else +#define LED2_PIN GPIO_PIN_5 +#define LED2_GPIO_PORT GPIOA +#define LED2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define LED2_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() +#endif /* defined (USE_NUCLEO_144) */ +/** + * @} + */ + +/** @defgroup STM32U5XX_NUCLEO_LOW_LEVEL_BUTTON LOW LEVEL BUTTON + * @{ + */ +/* Button state */ +#define BUTTON_RELEASED 0U +#define BUTTON_PRESSED 1U + +/** + * @brief Key push-button + */ +#define BUTTON_USER_PIN GPIO_PIN_13 +#define BUTTON_USER_GPIO_PORT GPIOC +#define BUTTON_USER_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define BUTTON_USER_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE() +#define BUTTON_USER_EXTI_IRQn EXTI13_IRQn +#define BUTTON_USER_EXTI_LINE EXTI_LINE_13 + +/** + * @} + */ + +/** @defgroup STM32U5XX_NUCLEO_LOW_LEVEL_COM LOW LEVEL COM + * @{ + */ +/** + * @brief Definition for COM port1, connected to UART1 + */ +#if (USE_BSP_COM_FEATURE > 0) +#define COM1_UART USART1 +#define COM1_CLK_ENABLE() __HAL_RCC_USART1_CLK_ENABLE() +#define COM1_CLK_DISABLE() __HAL_RCC_USART1_CLK_DISABLE() + +#define COM1_TX_PIN GPIO_PIN_9 +#define COM1_TX_GPIO_PORT GPIOA +#define COM1_TX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define COM1_TX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() +#define COM1_TX_AF GPIO_AF7_USART1 + +#define COM1_RX_PIN GPIO_PIN_10 +#define COM1_RX_GPIO_PORT GPIOA +#define COM1_RX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define COM1_RX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() +#define COM1_RX_AF GPIO_AF7_USART1 +#define COM_POLL_TIMEOUT 1000 +#endif /* USE_BSP_COM_FEATURE */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup STM32U5XX_NUCLEO_LOW_LEVEL_Exported_Variables LOW LEVEL Exported Variables + * @{ + */ +extern EXTI_HandleTypeDef hpb_exti[]; +#if (USE_BSP_COM_FEATURE > 0) +extern UART_HandleTypeDef hcom_uart[]; +extern USART_TypeDef *COM_USART[]; +#endif /* USE_BSP_COM_FEATURE */ + +/** + * @} + */ + +/** @defgroup STM32U5XX_NUCLEO_LOW_LEVEL_Exported_FunctionsPrototypes LOW LEVEL Exported Functions Prototypes + * @{ + */ +int32_t BSP_GetVersion(void); +const uint8_t *BSP_GetBoardName(void); +const uint8_t *BSP_GetBoardID(void); +int32_t BSP_LED_Init(Led_TypeDef Led); +int32_t BSP_LED_DeInit(Led_TypeDef Led); +int32_t BSP_LED_On(Led_TypeDef Led); +int32_t BSP_LED_Off(Led_TypeDef Led); +int32_t BSP_LED_Toggle(Led_TypeDef Led); +int32_t BSP_LED_GetState(Led_TypeDef Led); +int32_t BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode); +int32_t BSP_PB_DeInit(Button_TypeDef Button); +int32_t BSP_PB_GetState(Button_TypeDef Button); +void BSP_PB_IRQHandler(Button_TypeDef Button); +void BSP_PB_Callback(Button_TypeDef Button); + +#if (USE_BSP_COM_FEATURE > 0) +int32_t BSP_COM_Init(COM_TypeDef COM, COM_InitTypeDef *COM_Init); +int32_t BSP_COM_DeInit(COM_TypeDef COM); +#if (USE_COM_LOG > 0) +int32_t BSP_COM_SelectLogPort(COM_TypeDef COM); +#endif /* USE_COM_LOG */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +int32_t BSP_COM_RegisterDefaultMspCallbacks(COM_TypeDef COM); +int32_t BSP_COM_RegisterMspCallbacks(COM_TypeDef COM, BSP_COM_Cb_t *Callback); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +HAL_StatusTypeDef MX_USART1_Init(UART_HandleTypeDef *huart, MX_UART_InitTypeDef *COM_Init); +#endif /* USE_BSP_COM_FEATURE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5XX_NUCLEO_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/BSP/STM32U5xx_Nucleo/stm32u5xx_nucleo_errno.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/BSP/STM32U5xx_Nucleo/stm32u5xx_nucleo_errno.h new file mode 100644 index 000000000..756bea0ad --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/BSP/STM32U5xx_Nucleo/stm32u5xx_nucleo_errno.h @@ -0,0 +1,45 @@ +/** + ****************************************************************************** + * @file stm32u5xx_nucleo_errno.h + * @author MCD Application Team + * @brief Error Code. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5XX_NUCLEO_ERRNO_H +#define STM32U5XX_NUCLEO_ERRNO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Common Error codes */ +#define BSP_ERROR_NONE 0 +#define BSP_ERROR_NO_INIT -1 +#define BSP_ERROR_WRONG_PARAM -2 +#define BSP_ERROR_BUSY -3 +#define BSP_ERROR_PERIPH_FAILURE -4 +#define BSP_ERROR_COMPONENT_FAILURE -5 +#define BSP_ERROR_UNKNOWN_FAILURE -6 +#define BSP_ERROR_UNKNOWN_COMPONENT -7 +#define BSP_ERROR_BUS_FAILURE -8 +#define BSP_ERROR_CLOCK_FAILURE -9 +#define BSP_ERROR_MSP_FAILURE -10 +#define BSP_ERROR_FEATURE_NOT_SUPPORTED -11 + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5XX_NUCLEO_ERRNO_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u545xx.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u545xx.h new file mode 100644 index 000000000..55553ed78 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u545xx.h @@ -0,0 +1,21985 @@ +/** + ****************************************************************************** + * @file stm32u545xx.h + * @author MCD Application Team + * @brief CMSIS STM32U545xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32U545xx_H +#define STM32U545xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32U545xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32U545xx Specific Interrupt Numbers ================================= */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + IWDG_IRQn = 27, /*!< IWDG global interrupt */ + SAES_IRQn = 28, /*!< Secure AES global interrupt */ + GPDMA1_Channel0_IRQn = 29, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 30, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 31, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 32, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 33, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 34, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 35, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 36, /*!< GPDMA1 Channel 7 global interrupt */ + ADC1_IRQn = 37, /*!< ADC1 global interrupt */ + DAC1_IRQn = 38, /*!< DAC1 global interrupt */ + FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ + TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 45, /*!< TIM2 global interrupt */ + TIM3_IRQn = 46, /*!< TIM3 global interrupt */ + TIM4_IRQn = 47, /*!< TIM4 global interrupt */ + TIM5_IRQn = 48, /*!< TIM5 global interrupt */ + TIM6_IRQn = 49, /*!< TIM6 global interrupt */ + TIM7_IRQn = 50, /*!< TIM7 global interrupt */ + TIM8_BRK_IRQn = 51, /*!< TIM8 Break interrupt */ + TIM8_UP_IRQn = 52, /*!< TIM8 Update interrupt */ + TIM8_TRG_COM_IRQn = 53, /*!< TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQn = 54, /*!< TIM8 Capture Compare interrupt */ + I2C1_EV_IRQn = 55, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 56, /*!< I2C1 Error interrupt */ + I2C2_EV_IRQn = 57, /*!< I2C2 Event interrupt */ + I2C2_ER_IRQn = 58, /*!< I2C2 Error interrupt */ + SPI1_IRQn = 59, /*!< SPI1 global interrupt */ + SPI2_IRQn = 60, /*!< SPI2 global interrupt */ + USART1_IRQn = 61, /*!< USART1 global interrupt */ + USART3_IRQn = 63, /*!< USART3 global interrupt */ + UART4_IRQn = 64, /*!< UART4 global interrupt */ + UART5_IRQn = 65, /*!< UART5 global interrupt */ + LPUART1_IRQn = 66, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 67, /*!< LPTIM1 global interrupt */ + LPTIM2_IRQn = 68, /*!< LPTIM2 global interrupt */ + TIM15_IRQn = 69, /*!< TIM15 global interrupt */ + TIM16_IRQn = 70, /*!< TIM16 global interrupt */ + TIM17_IRQn = 71, /*!< TIM17 global interrupt */ + COMP_IRQn = 72, /*!< COMP1 and COMP2 through EXTI Lines interrupts */ + USB_IRQn = 73, /*!< USB global interrupt */ + CRS_IRQn = 74, /*!< CRS global interrupt */ + OCTOSPI1_IRQn = 76, /*!< OctoSPI1 global interrupt */ + PWR_S3WU_IRQn = 77, /*!< PWR wake up from Stop3 interrupt */ + SDMMC1_IRQn = 78, /*!< SDMMC1 global interrupt */ + GPDMA1_Channel8_IRQn = 80, /*!< GPDMA1 Channel 8 global interrupt */ + GPDMA1_Channel9_IRQn = 81, /*!< GPDMA1 Channel 9 global interrupt */ + GPDMA1_Channel10_IRQn = 82, /*!< GPDMA1 Channel 10 global interrupt */ + GPDMA1_Channel11_IRQn = 83, /*!< GPDMA1 Channel 11 global interrupt */ + GPDMA1_Channel12_IRQn = 84, /*!< GPDMA1 Channel 12 global interrupt */ + GPDMA1_Channel13_IRQn = 85, /*!< GPDMA1 Channel 13 global interrupt */ + GPDMA1_Channel14_IRQn = 86, /*!< GPDMA1 Channel 14 global interrupt */ + GPDMA1_Channel15_IRQn = 87, /*!< GPDMA1 Channel 15 global interrupt */ + I2C3_EV_IRQn = 88, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 89, /*!< I2C3 error interrupt */ + SAI1_IRQn = 90, /*!< Serial Audio Interface 1 global interrupt */ + TSC_IRQn = 92, /*!< Touch Sense Controller global interrupt */ + AES_IRQn = 93, /*!< AES global interrupt */ + RNG_IRQn = 94, /*!< RNG global interrupt */ + FPU_IRQn = 95, /*!< FPU global interrupt */ + HASH_IRQn = 96, /*!< HASH global interrupt */ + PKA_IRQn = 97, /*!< PKA global interrupt */ + LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */ + SPI3_IRQn = 99, /*!< SPI3 global interrupt */ + I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */ + I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */ + MDF1_FLT0_IRQn = 102, /*!< MDF1 Filter 0 global interrupt */ + MDF1_FLT1_IRQn = 103, /*!< MDF1 Filter 1 global interrupt */ + ICACHE_IRQn = 107, /*!< Instruction cache global interrupt */ + OTFDEC1_IRQn = 108, /*!< OTFDEC1 global interrupt */ + LPTIM4_IRQn = 110, /*!< LPTIM4 global interrupt */ + DCACHE1_IRQn = 111, /*!< Data cache global interrupt */ + ADF1_IRQn = 112, /*!< ADF interrupt */ + ADC4_IRQn = 113, /*!< ADC4 (12bits) global interrupt */ + LPDMA1_Channel0_IRQn = 114, /*!< LPDMA1 SmartRun Channel 0 global interrupt */ + LPDMA1_Channel1_IRQn = 115, /*!< LPDMA1 SmartRun Channel 1 global interrupt */ + LPDMA1_Channel2_IRQn = 116, /*!< LPDMA1 SmartRun Channel 2 global interrupt */ + LPDMA1_Channel3_IRQn = 117, /*!< LPDMA1 SmartRun Channel 3 global interrupt */ + DCMI_PSSI_IRQn = 119, /*!< DCMI/PSSI global interrupt */ + CORDIC_IRQn = 123, /*!< CORDIC global interrupt */ + FMAC_IRQn = 124, /*!< FMAC global interrupt */ + LSECSSD_IRQn = 125, /*!< LSECSSD and MSI_PLL_UNLOCK global interrupts */ +} IRQn_Type; + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u5xx.h" /*!< STM32U5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; +} I2C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + uint32_t RESERVED4[7]; /*!< Reserved4, Address offset: 0x84-0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + uint32_t RESERVED5[7]; /*!< Reserved5, Address offset: 0xA4-0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + uint32_t RESERVED7[7]; /*!< Reserved7, Address offset: 0xD4-0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ + __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ + __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ + __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ + __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x180 */ + uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x200 */ + __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +}MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + + +/** + * @brief OTFDEC register + */ +typedef struct +{ + __IO uint32_t REG_CONFIGR; /*!< OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_START_ADDR; /*!< OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_END_ADDR; /*!< OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER0; /*!< OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER1; /*!< OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR0; /*!< OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR1; /*!< OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR2; /*!< OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR3; /*!< OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */ +} OTFDEC_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< OTFDEC Control register, Address offset: 0x000 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x004-0x00C */ + __IO uint32_t PRIVCFGR; /*!< OTFDEC Privileged access control Configuration register, Address offset: 0x010 */ + uint32_t RESERVED2[187]; /*!< Reserved, Address offset: 0x014-0x2FC */ + __IO uint32_t ISR; /*!< OTFDEC Interrupt Status register, Address offset: 0x300 */ + __IO uint32_t ICR; /*!< OTFDEC Interrupt Clear register, Address offset: 0x304 */ + __IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */ +} OTFDEC_TypeDef; + + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + uint32_t RESERVED1[1]; /*!< Reserved1, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + uint32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x78-0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ + __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ + __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ + __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ + __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ + __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ + __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ + __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ + __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ + uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ +} SYSCFG_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + __IO uint32_t RESERVED0[8]; /*!< Reserved, */ + __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IO uint32_t TXBD; /*!= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0x30000UL) /*!< SRAM1=192k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ + +/* External memories base addresses - Not aliased */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ + + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (512 KB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (192 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x20030000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08308UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x06000UL) +#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x06400UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) +#define OTFDEC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL) +#define OTFDEC1_REGION2_BASE_NS (OTFDEC1_BASE_NS + 0x50UL) +#define OTFDEC1_REGION3_BASE_NS (OTFDEC1_BASE_NS + 0x80UL) +#define OTFDEC1_REGION4_BASE_NS (OTFDEC1_BASE_NS + 0xB0UL) +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1308UL) +#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) +#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) +#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) +#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) +#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) +#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) +#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) +#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) +#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (192 KB) secure base address */ +#define SRAM2_BASE_S (0x30030000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) + +/*!< APB3 Secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08308UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x06000UL) +#define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x06400UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) +#define OTFDEC1_BASE_S (AHB2PERIPH_BASE_S + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL) +#define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL) +#define OTFDEC1_REGION3_BASE_S (OTFDEC1_BASE_S + 0x80UL) +#define OTFDEC1_REGION4_BASE_S (OTFDEC1_BASE_S + 0xB0UL) +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1308UL) +#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) +#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) +#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) +#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) +#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) +#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) +#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) +#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0044000UL) +#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ +#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ + + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0UL) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0UL) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1UL) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) +#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define OTFDEC1_NS ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS) +#define OTFDEC1_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS) +#define OTFDEC1_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS) +#define OTFDEC1_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS) +#define OTFDEC1_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) +#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) +#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) +#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) +#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) +#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) + +/*!< APB2 Secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) + +/*!< APB3 secure peripherals */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define USB_DRD_FS_S ((USB_DRD_TypeDef *) USB_DRD_BASE_S) +#define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define OTFDEC1_S ((OTFDEC_TypeDef *) OTFDEC1_BASE_S) +#define OTFDEC1_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S) +#define OTFDEC1_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S) +#define OTFDEC1_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S) +#define OTFDEC1_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) +#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) +#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) +#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) +#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) +#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM4_BASE SRAM4_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define LPDMA1 LPDMA1_S +#define LPDMA1_BASE LPDMA1_BASE_S + +#define LPDMA1_Channel0 LPDMA1_Channel0_S +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S + +#define LPDMA1_Channel1 LPDMA1_Channel1_S +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S + +#define LPDMA1_Channel2 LPDMA1_Channel2_S +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S + +#define LPDMA1_Channel3 LPDMA1_Channel3_S +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + + +#define LPGPIO1 LPGPIO1_S +#define LPGPIO1_BASE LPGPIO1_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_S +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZSC2 GTZC_TZSC2_S +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_TZIC2 GTZC_TZIC2_S +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + + +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define DAC DAC_S +#define DAC_BASE DAC_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define OPAMP OPAMP_S +#define OPAMP_BASE OPAMP_BASE_S + +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S + +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP1_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + + +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S + +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define AES AES_S +#define AES_BASE AES_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + +#define OTFDEC1 OTFDEC1_S +#define OTFDEC1_BASE OTFDEC1_BASE_S + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_S +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_S + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_S +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_S + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_S +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_S + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_S +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_S + + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + + + +#define USB_DRD_FS USB_DRD_FS_S +#define USB_DRD_BASE USB_DRD_BASE_S +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_S +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define LPDMA1 LPDMA1_NS +#define LPDMA1_BASE LPDMA1_BASE_NS + +#define LPDMA1_Channel0 LPDMA1_Channel0_NS +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS + +#define LPDMA1_Channel1 LPDMA1_Channel1_NS +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS + +#define LPDMA1_Channel2 LPDMA1_Channel2_NS +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS + +#define LPDMA1_Channel3 LPDMA1_Channel3_NS +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define LPGPIO1 LPGPIO1_NS +#define LPGPIO1_BASE LPGPIO1_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZSC2 GTZC_TZSC2_NS +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_TZIC2 GTZC_TZIC2_NS +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + + +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define OPAMP OPAMP_NS +#define OPAMP_BASE OPAMP_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP1_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS + +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define AES AES_NS +#define AES_BASE AES_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + +#define OTFDEC1 OTFDEC1_NS +#define OTFDEC1_BASE OTFDEC1_BASE_NS + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_NS +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_NS + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_NS +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_NS + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_NS +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_NS + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_NS +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_NS + + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + + +#define USB_DRD_FS USB_DRD_FS_NS +#define USB_DRD_BASE USB_DRD_BASE_NS +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#endif + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10UL) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_EOCAL_Pos (11UL) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ +#define ADC_ISR_LDORDY_Pos (12UL) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10UL) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IER_EOCALIE_Pos (11UL) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ +#define ADC_IER_LDORDYIE_Pos (12UL) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADCALLIN_Pos (16UL) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ + +#define ADC_CR_CALINDEX_Pos (24UL) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ +#define ADC_CR_CALINDEX0_Pos (24UL) +#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ +#define ADC_CR_CALINDEX1_Pos (25UL) +#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ +#define ADC_CR_CALINDEX2_Pos (26UL) +#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ +#define ADC_CR_CALINDEX3_Pos (27UL) +#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ +#define ADC_CR_ADVREGEN_Pos (28UL) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC4_CFGR1_DMAEN_Pos (0UL) +#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC4_CFGR1_DMACFG_Pos (1UL) +#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC4_CFGR1_SCANDIR_Pos (4UL) +#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC4_CFGR1_ALIGN_Pos (5UL) +#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ + +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC4_CFGR1_WAIT_Pos (14UL) +#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +/* Specific ADC4 */ +#define ADC4_CFGR1_EXTSEL_Pos (6UL) +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ + +#define ADC4_CFGR1_CHSELRMOD_Pos (21UL) +#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (27UL) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* Specific ADC4 */ +#define ADC4_CFGR2_OVSR_Pos (2UL) +#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC4_CFGR2_LFTRIG_Pos (29UL) +#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC4_SMPR_SMP1_Pos (0UL) +#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC4_SMPR_SMP2_Pos (4UL) +#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC4_SMPR_SMPSEL_Pos (8UL) +#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ +#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ +#define ADC4_SMPR_SMPSEL0_Pos (8UL) +#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ +#define ADC4_SMPR_SMPSEL1_Pos (9UL) +#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ +#define ADC4_SMPR_SMPSEL2_Pos (10UL) +#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ +#define ADC4_SMPR_SMPSEL3_Pos (11UL) +#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ +#define ADC4_SMPR_SMPSEL4_Pos (12UL) +#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ +#define ADC4_SMPR_SMPSEL5_Pos (13UL) +#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ +#define ADC4_SMPR_SMPSEL6_Pos (14UL) +#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ +#define ADC4_SMPR_SMPSEL7_Pos (15UL) +#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ +#define ADC4_SMPR_SMPSEL8_Pos (16UL) +#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ +#define ADC4_SMPR_SMPSEL9_Pos (17UL) +#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ +#define ADC4_SMPR_SMPSEL10_Pos (18UL) +#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ +#define ADC4_SMPR_SMPSEL11_Pos (19UL) +#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ +#define ADC4_SMPR_SMPSEL12_Pos (20UL) +#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ +#define ADC4_SMPR_SMPSEL13_Pos (21UL) +#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ +#define ADC4_SMPR_SMPSEL14_Pos (22UL) +#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ +#define ADC4_SMPR_SMPSEL15_Pos (23UL) +#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ +#define ADC4_SMPR_SMPSEL16_Pos (24UL) +#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ +#define ADC4_SMPR_SMPSEL17_Pos (25UL) +#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ +#define ADC4_SMPR_SMPSEL18_Pos (26UL) +#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ +#define ADC4_SMPR_SMPSEL19_Pos (27UL) +#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ +#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ +#define ADC4_SMPR_SMPSEL20_Pos (26UL) +#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ +#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL21_Pos (26UL) +#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ +#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL22_Pos (30UL) +#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ +#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ +#define ADC4_SMPR_SMPSEL23_Pos (31UL) +#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ +#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0UL) +#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0UL) +#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +#define ADC_HTR_AWDFILT_Pos (29UL) +#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_PW register ********************/ +#define ADC4_PWRR_AUTOFF_Pos (0UL) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1UL) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2UL) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3UL) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0UL) +#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ + +#define ADC_OFR1_OFFSETPOS_Pos (24UL) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_USAT_Pos (25UL) +#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_SSAT_Pos (26UL) +#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (27UL) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0UL) +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ + +#define ADC_OFR2_OFFSETPOS_Pos (24UL) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR2_USAT_Pos (25UL) +#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR2_SSAT_Pos (26UL) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (27UL) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0UL) +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ + +#define ADC_OFR3_OFFSETPOS_Pos (24UL) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR3_USAT_Pos (25UL) +#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR3_SSAT_Pos (26UL) +#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (27UL) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0UL) +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ + +#define ADC_OFR4_OFFSETPOS_Pos (24UL) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR4_USAT_Pos (25UL) +#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR4_SSAT_Pos (26UL) +#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (27UL) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_GCOMP register ********************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0UL) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16UL) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0UL) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16UL) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0UL) +#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_CHSEL0_Pos (0UL) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1UL) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2UL) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3UL) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4UL) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5UL) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6UL) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7UL) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8UL) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9UL) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10UL) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11UL) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12UL) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13UL) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14UL) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15UL) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16UL) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17UL) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18UL) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19UL) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20UL) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21UL) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22UL) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL23_Pos (23UL) +#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0UL) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ1_Pos (0UL) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +#define ADC_CHSELR_SQ2_Pos (4UL) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ3_Pos (8UL) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ4_Pos (12UL) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ5_Pos (16UL) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ6_Pos (20UL) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ7_Pos (24UL) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ8_Pos (28UL) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0UL) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16UL) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0UL) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_I_APB_ADDR_Pos (0UL) +#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ +#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ + +#define ADC_CALFACT_I_APB_DATA_Pos (08UL) +#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ + +#define ADC_CALFACT_VALIDITY_Pos (16UL) +#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_LATCH_COEF_Pos (24UL) +#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CAPTURE_COEF_Pos (25UL) +#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ + +#define ADC4_CALFACT_CALFACT_Pos (0UL) +#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_CALFACT_Pos (0UL) +#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ +#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ +#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OR register ********************/ +#define ADC_OR_CHN0SEL_Pos (0UL) +#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ +#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ + +/************************* ADC Common registers *****************************/ + +#define ADC_CCR_PRESC_Pos (18UL) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VSENSEEN_Pos (23UL) +#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_LFMEN_Pos (25UL) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ +#define ADC_CCR_VDDCOREN_Pos (26UL) +#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ +#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ + + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0UL) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4UL) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8UL) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16UL) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17UL) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18UL) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19UL) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20UL) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21UL) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22UL) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31UL) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0UL) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0UL) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0UL) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1UL) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2UL) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3UL) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5UL) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6UL) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7UL) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8UL) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0UL) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16UL) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24UL) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28UL) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31UL) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0UL) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1UL) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2UL) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3UL) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8UL) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9UL) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10UL) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15UL) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16UL) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0UL) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1UL) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2UL) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3UL) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2UL) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3UL) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5UL) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7UL) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8UL) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12UL) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13UL) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16UL) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20UL) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30UL) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31UL) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0UL) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1UL) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2UL) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5UL) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6UL) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0UL) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3UL) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9UL) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12UL) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15UL) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0UL) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0UL) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14UL) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16UL) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30UL) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) + +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0UL) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_PRFTEN_Pos (8UL) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11UL) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12UL) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13UL) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14UL) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0UL) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1UL) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3UL) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4UL) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5UL) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6UL) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7UL) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13UL) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16UL) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17UL) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18UL) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19UL) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20UL) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21UL) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0UL) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1UL) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3UL) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4UL) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5UL) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6UL) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7UL) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16UL) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17UL) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR register *****************/ +#define FLASH_NSCR_PG_Pos (0UL) +#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR_PER_Pos (1UL) +#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR_MER1_Pos (2UL) +#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ +#define FLASH_NSCR_PNB_Pos (3UL) +#define FLASH_NSCR_PNB_Msk (0x1FUL << FLASH_NSCR_PNB_Pos) /*!< 0x000001F8 */ +#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR_BKER_Pos (11UL) +#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR_BWR_Pos (14UL) +#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR_MER2_Pos (15UL) +#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ +#define FLASH_NSCR_STRT_Pos (16UL) +#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR_OPTSTRT_Pos (17UL) +#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR_EOPIE_Pos (24UL) +#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR_ERRIE_Pos (25UL) +#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR_OBL_LAUNCH_Pos (27UL) +#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR_OPTLOCK_Pos (30UL) +#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR_LOCK_Pos (31UL) +#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR register ****************/ +#define FLASH_SECCR_PG_Pos (0UL) +#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR_PER_Pos (1UL) +#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR_MER1_Pos (2UL) +#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR_PNB_Pos (3UL) +#define FLASH_SECCR_PNB_Msk (0x1FUL << FLASH_SECCR_PNB_Pos) /*!< 0x000001F8 */ +#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR_BKER_Pos (11UL) +#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR_BWR_Pos (14UL) +#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR_MER2_Pos (15UL) +#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ +#define FLASH_SECCR_STRT_Pos (16UL) +#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR_EOPIE_Pos (24UL) +#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR_ERRIE_Pos (25UL) +#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR_INV_Pos (29UL) +#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR_LOCK_Pos (31UL) +#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0UL) +#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0003FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21UL) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (22UL) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24UL) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30UL) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31UL) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0UL) +#define FLASH_OPSR_ADDR_OP_Msk (0x3FFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x0003FFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ +#define FLASH_OPSR_BK_OP_Pos (21UL) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (22UL) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29UL) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0UL) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8UL) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12UL) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13UL) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_nRST_SHDW_Pos (14UL) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ +#define FLASH_OPTR_SRAM_RST_Pos (15UL) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16UL) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17UL) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18UL) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19UL) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20UL) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ +#define FLASH_OPTR_DUALBANK_Pos (21UL) +#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ +#define FLASH_OPTR_BKPRAM_ECC_Pos (22UL) +#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTR_SRAM2_ECC_Pos (24UL) +#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25UL) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26UL) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27UL) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN_Pos (28UL) +#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29UL) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30UL) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#define FLASH_OPTR_TZEN_Pos (31UL) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7UL) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7UL) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0UL) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7UL) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0UL) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0x1FUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16UL) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0x1FUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16UL) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0x1FUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31UL) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0UL) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16UL) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31UL) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0UL) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16UL) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31UL) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0UL) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0x1FUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16UL) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0x1FUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16UL) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0x1FUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31UL) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0UL) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0x1FUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16UL) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0x1FUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31UL) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0UL) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0x1FUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16UL) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0x1FUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31UL) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0UL) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1UL) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0UL) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1UL) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0UL) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8UL) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24UL) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0UL) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8UL) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0UL) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8UL) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24UL) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0UL) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8UL) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16UL) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24UL) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31UL) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0UL) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1UL) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2UL) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3UL) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4UL) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8UL) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9UL) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15UL) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16UL) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0UL) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1UL) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8UL) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9UL) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10UL) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0UL) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0UL) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + + +/******************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0UL) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2UL) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4UL) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6UL) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8UL) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10UL) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12UL) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14UL) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16UL) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18UL) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20UL) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22UL) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24UL) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26UL) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28UL) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30UL) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0UL) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1UL) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2UL) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3UL) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4UL) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5UL) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6UL) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7UL) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8UL) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9UL) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10UL) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11UL) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12UL) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13UL) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14UL) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15UL) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0UL) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2UL) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4UL) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6UL) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8UL) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10UL) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12UL) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14UL) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16UL) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18UL) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20UL) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22UL) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24UL) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26UL) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28UL) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30UL) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0UL) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2UL) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4UL) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6UL) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8UL) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10UL) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12UL) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14UL) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16UL) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18UL) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20UL) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22UL) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24UL) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26UL) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28UL) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30UL) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0UL) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1UL) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2UL) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3UL) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4UL) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5UL) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6UL) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7UL) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8UL) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9UL) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10UL) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11UL) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12UL) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13UL) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14UL) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15UL) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0UL) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1UL) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2UL) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3UL) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4UL) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5UL) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6UL) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7UL) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8UL) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9UL) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10UL) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11UL) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12UL) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13UL) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14UL) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15UL) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0UL) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1UL) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2UL) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3UL) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4UL) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5UL) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6UL) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7UL) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8UL) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9UL) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10UL) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11UL) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12UL) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13UL) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14UL) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15UL) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16UL) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17UL) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18UL) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19UL) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20UL) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21UL) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22UL) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23UL) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24UL) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25UL) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26UL) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27UL) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28UL) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29UL) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30UL) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31UL) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0UL) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1UL) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2UL) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3UL) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4UL) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5UL) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6UL) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7UL) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8UL) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9UL) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10UL) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11UL) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12UL) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13UL) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14UL) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15UL) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16UL) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0UL) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4UL) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8UL) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12UL) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16UL) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20UL) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24UL) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28UL) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0UL) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4UL) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8UL) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12UL) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16UL) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20UL) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24UL) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28UL) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0UL) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1UL) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2UL) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3UL) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4UL) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5UL) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6UL) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7UL) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8UL) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9UL) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10UL) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11UL) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12UL) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13UL) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14UL) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15UL) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + +/****************** Bits definition for GPIO_HSLVR register ******************/ +#define GPIO_HSLVR_HSLV0_Pos (0UL) +#define GPIO_HSLVR_HSLV0_Msk (0x1UL << GPIO_HSLVR_HSLV0_Pos) /*!< 0x00000001 */ +#define GPIO_HSLVR_HSLV0 GPIO_HSLVR_HSLV0_Msk +#define GPIO_HSLVR_HSLV1_Pos (1UL) +#define GPIO_HSLVR_HSLV1_Msk (0x1UL << GPIO_HSLVR_HSLV1_Pos) /*!< 0x00000002 */ +#define GPIO_HSLVR_HSLV1 GPIO_HSLVR_HSLV1_Msk +#define GPIO_HSLVR_HSLV2_Pos (2UL) +#define GPIO_HSLVR_HSLV2_Msk (0x1UL << GPIO_HSLVR_HSLV2_Pos) /*!< 0x00000004 */ +#define GPIO_HSLVR_HSLV2 GPIO_HSLVR_HSLV2_Msk +#define GPIO_HSLVR_HSLV3_Pos (3UL) +#define GPIO_HSLVR_HSLV3_Msk (0x1UL << GPIO_HSLVR_HSLV3_Pos) /*!< 0x00000008 */ +#define GPIO_HSLVR_HSLV3 GPIO_HSLVR_HSLV3_Msk +#define GPIO_HSLVR_HSLV4_Pos (4UL) +#define GPIO_HSLVR_HSLV4_Msk (0x1UL << GPIO_HSLVR_HSLV4_Pos) /*!< 0x00000010 */ +#define GPIO_HSLVR_HSLV4 GPIO_HSLVR_HSLV4_Msk +#define GPIO_HSLVR_HSLV5_Pos (5UL) +#define GPIO_HSLVR_HSLV5_Msk (0x1UL << GPIO_HSLVR_HSLV5_Pos) /*!< 0x00000020 */ +#define GPIO_HSLVR_HSLV5 GPIO_HSLVR_HSLV5_Msk +#define GPIO_HSLVR_HSLV6_Pos (6UL) +#define GPIO_HSLVR_HSLV6_Msk (0x1UL << GPIO_HSLVR_HSLV6_Pos) /*!< 0x00000040 */ +#define GPIO_HSLVR_HSLV6 GPIO_HSLVR_HSLV6_Msk +#define GPIO_HSLVR_HSLV7_Pos (7UL) +#define GPIO_HSLVR_HSLV7_Msk (0x1UL << GPIO_HSLVR_HSLV7_Pos) /*!< 0x00000080 */ +#define GPIO_HSLVR_HSLV7 GPIO_HSLVR_HSLV7_Msk +#define GPIO_HSLVR_HSLV8_Pos (8UL) +#define GPIO_HSLVR_HSLV8_Msk (0x1UL << GPIO_HSLVR_HSLV8_Pos) /*!< 0x00000100 */ +#define GPIO_HSLVR_HSLV8 GPIO_HSLVR_HSLV8_Msk +#define GPIO_HSLVR_HSLV9_Pos (9UL) +#define GPIO_HSLVR_HSLV9_Msk (0x1UL << GPIO_HSLVR_HSLV9_Pos) /*!< 0x00000200 */ +#define GPIO_HSLVR_HSLV9 GPIO_HSLVR_HSLV9_Msk +#define GPIO_HSLVR_HSLV10_Pos (10UL) +#define GPIO_HSLVR_HSLV10_Msk (0x1UL << GPIO_HSLVR_HSLV10_Pos) /*!< 0x00000400 */ +#define GPIO_HSLVR_HSLV10 GPIO_HSLVR_HSLV10_Msk +#define GPIO_HSLVR_HSLV11_Pos (11UL) +#define GPIO_HSLVR_HSLV11_Msk (x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */ +#define GPIO_HSLVR_HSLV11 GPIO_HSLVR_HSLV11_Msk +#define GPIO_HSLVR_HSLV12_Pos (12UL) +#define GPIO_HSLVR_HSLV12_Msk (0x1UL << GPIO_HSLVR_HSLV12_Pos) /*!< 0x00001000 */ +#define GPIO_HSLVR_HSLV12 GPIO_HSLVR_HSLV12_Msk +#define GPIO_HSLVR_HSLV13_Pos (13UL) +#define GPIO_HSLVR_HSLV13_Msk (0x1UL << GPIO_HSLVR_HSLV13_Pos) /*!< 0x00002000 */ +#define GPIO_HSLVR_HSLV13 GPIO_HSLVR_HSLV13_Msk +#define GPIO_HSLVR_HSLV14_Pos (14UL) +#define GPIO_HSLVR_HSLV14_Msk (0x1UL << GPIO_HSLVR_HSLV14_Pos) /*!< 0x00004000 */ +#define GPIO_HSLVR_HSLV14 GPIO_HSLVR_HSLV14_Msk +#define GPIO_HSLVR_HSLV15_Pos (15UL) +#define GPIO_HSLVR_HSLV15_Msk (0x1UL << GPIO_HSLVR_HSLV15_Pos) /*!< 0x00008000 */ +#define GPIO_HSLVR_HSLV15 GPIO_HSLVR_HSLV15_Msk + +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0UL) +#define GPIO_SECCFGR_SEC0_Msk (0x1UL << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1UL) +#define GPIO_SECCFGR_SEC1_Msk (0x1UL << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2UL) +#define GPIO_SECCFGR_SEC2_Msk (0x1UL << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3UL) +#define GPIO_SECCFGR_SEC3_Msk (0x1UL << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4UL) +#define GPIO_SECCFGR_SEC4_Msk (0x1UL << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5UL) +#define GPIO_SECCFGR_SEC5_Msk (0x1UL << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6UL) +#define GPIO_SECCFGR_SEC6_Msk (0x1UL << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7UL) +#define GPIO_SECCFGR_SEC7_Msk (0x1UL << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk +#define GPIO_SECCFGR_SEC8_Pos (8UL) +#define GPIO_SECCFGR_SEC8_Msk (0x1UL << GPIO_SECCFGR_SEC8_Pos) /*!< 0x00000100 */ +#define GPIO_SECCFGR_SEC8 GPIO_SECCFGR_SEC8_Msk +#define GPIO_SECCFGR_SEC9_Pos (9UL) +#define GPIO_SECCFGR_SEC9_Msk (0x1UL << GPIO_SECCFGR_SEC9_Pos) /*!< 0x00000200 */ +#define GPIO_SECCFGR_SEC9 GPIO_SECCFGR_SEC9_Msk +#define GPIO_SECCFGR_SEC10_Pos (10UL) +#define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */ +#define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk +#define GPIO_SECCFGR_SEC11_Pos (11UL) +#define GPIO_SECCFGR_SEC11_Msk (x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */ +#define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk +#define GPIO_SECCFGR_SEC12_Pos (12UL) +#define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */ +#define GPIO_SECCFGR_SEC12 GPIO_SECCFGR_SEC12_Msk +#define GPIO_SECCFGR_SEC13_Pos (13UL) +#define GPIO_SECCFGR_SEC13_Msk (0x1UL << GPIO_SECCFGR_SEC13_Pos) /*!< 0x00002000 */ +#define GPIO_SECCFGR_SEC13 GPIO_SECCFGR_SEC13_Msk +#define GPIO_SECCFGR_SEC14_Pos (14UL) +#define GPIO_SECCFGR_SEC14_Msk (0x1UL << GPIO_SECCFGR_SEC14_Pos) /*!< 0x00004000 */ +#define GPIO_SECCFGR_SEC14 GPIO_SECCFGR_SEC14_Msk +#define GPIO_SECCFGR_SEC15_Pos (15UL) +#define GPIO_SECCFGR_SEC15_Msk (0x1UL << GPIO_SECCFGR_SEC15_Pos) /*!< 0x00008000 */ +#define GPIO_SECCFGR_SEC15 GPIO_SECCFGR_SEC15_Msk + +/******************************************************************************/ +/* */ +/* Low Power General Purpose IOs (LPGPIO) */ +/* */ +/******************************************************************************/ +/****************** Bits definition for LPGPIO_MODER register *****************/ +#define LPGPIO_MODER_MOD0_Pos (0UL) +#define LPGPIO_MODER_MOD0_Msk (0x1UL << LPGPIO_MODER_MOD0_Pos) /*!< 0x00000001 */ +#define LPGPIO_MODER_MOD0 LPGPIO_MODER_MOD0_Msk +#define LPGPIO_MODER_MOD1_Pos (1UL) +#define LPGPIO_MODER_MOD1_Msk (0x1UL << LPGPIO_MODER_MOD1_Pos) /*!< 0x00000002 */ +#define LPGPIO_MODER_MOD1 LPGPIO_MODER_MOD1_Msk +#define LPGPIO_MODER_MOD2_Pos (2UL) +#define LPGPIO_MODER_MOD2_Msk (0x1UL << LPGPIO_MODER_MOD2_Pos) /*!< 0x00000004 */ +#define LPGPIO_MODER_MOD2 LPGPIO_MODER_MOD2_Msk +#define LPGPIO_MODER_MOD3_Pos (3UL) +#define LPGPIO_MODER_MOD3_Msk (0x1UL << LPGPIO_MODER_MOD3_Pos) /*!< 0x00000008 */ +#define LPGPIO_MODER_MOD3 LPGPIO_MODER_MOD3_Msk +#define LPGPIO_MODER_MOD4_Pos (4UL) +#define LPGPIO_MODER_MOD4_Msk (0x1UL << LPGPIO_MODER_MOD4_Pos) /*!< 0x00000010 */ +#define LPGPIO_MODER_MOD4 LPGPIO_MODER_MOD4_Msk +#define LPGPIO_MODER_MOD5_Pos (5UL) +#define LPGPIO_MODER_MOD5_Msk (0x1UL << LPGPIO_MODER_MOD5_Pos) /*!< 0x00000020 */ +#define LPGPIO_MODER_MOD5 LPGPIO_MODER_MOD5_Msk +#define LPGPIO_MODER_MOD6_Pos (6UL) +#define LPGPIO_MODER_MOD6_Msk (0x1UL << LPGPIO_MODER_MOD6_Pos) /*!< 0x00000040 */ +#define LPGPIO_MODER_MOD6 LPGPIO_MODER_MOD6_Msk +#define LPGPIO_MODER_MOD7_Pos (7UL) +#define LPGPIO_MODER_MOD7_Msk (0x1UL << LPGPIO_MODER_MOD7_Pos) /*!< 0x00000080 */ +#define LPGPIO_MODER_MOD7 LPGPIO_MODER_MOD7_Msk +#define LPGPIO_MODER_MOD8_Pos (8UL) +#define LPGPIO_MODER_MOD8_Msk (0x1UL << LPGPIO_MODER_MOD8_Pos) /*!< 0x00000100 */ +#define LPGPIO_MODER_MOD8 LPGPIO_MODER_MOD8_Msk +#define LPGPIO_MODER_MOD9_Pos (9UL) +#define LPGPIO_MODER_MOD9_Msk (0x1UL << LPGPIO_MODER_MOD9_Pos) /*!< 0x00000200 */ +#define LPGPIO_MODER_MOD9 LPGPIO_MODER_MOD9_Msk +#define LPGPIO_MODER_MOD10_Pos (10UL) +#define LPGPIO_MODER_MOD10_Msk (0x1UL << LPGPIO_MODER_MOD10_Pos) /*!< 0x00000400 */ +#define LPGPIO_MODER_MOD10 LPGPIO_MODER_MOD10_Msk +#define LPGPIO_MODER_MOD11_Pos (11UL) +#define LPGPIO_MODER_MOD11_Msk (0x1UL << LPGPIO_MODER_MOD11_Pos) /*!< 0x00000800 */ +#define LPGPIO_MODER_MOD11 LPGPIO_MODER_MOD11_Msk +#define LPGPIO_MODER_MOD12_Pos (12UL) +#define LPGPIO_MODER_MOD12_Msk (0x1UL << LPGPIO_MODER_MOD12_Pos) /*!< 0x00001000 */ +#define LPGPIO_MODER_MOD12 LPGPIO_MODER_MOD12_Msk +#define LPGPIO_MODER_MOD13_Pos (13UL) +#define LPGPIO_MODER_MOD13_Msk (0x1UL << LPGPIO_MODER_MOD13_Pos) /*!< 0x00002000 */ +#define LPGPIO_MODER_MOD13 LPGPIO_MODER_MOD13_Msk +#define LPGPIO_MODER_MOD14_Pos (14UL) +#define LPGPIO_MODER_MOD14_Msk (0x1UL << LPGPIO_MODER_MOD14_Pos) /*!< 0x00004000 */ +#define LPGPIO_MODER_MOD14 LPGPIO_MODER_MOD14_Msk +#define LPGPIO_MODER_MOD15_Pos (15UL) +#define LPGPIO_MODER_MOD15_Msk (0x1UL << LPGPIO_MODER_MOD15_Pos) /*!< 0x00008000 */ +#define LPGPIO_MODER_MOD15 LPGPIO_MODER_MOD15_Msk + +/****************** Bits definition for LPGPIO_IDR register *******************/ +#define LPGPIO_IDR_ID0_Pos (0UL) +#define LPGPIO_IDR_ID0_Msk (0x1UL << LPGPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define LPGPIO_IDR_ID0 LPGPIO_IDR_ID0_Msk +#define LPGPIO_IDR_ID1_Pos (1UL) +#define LPGPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define LPGPIO_IDR_ID1 LPGPIO_IDR_ID1_Msk +#define LPGPIO_IDR_ID2_Pos (2UL) +#define LPGPIO_IDR_ID2_Msk (0x1UL << LPGPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define LPGPIO_IDR_ID2 LPGPIO_IDR_ID2_Msk +#define LPGPIO_IDR_ID3_Pos (3UL) +#define LPGPIO_IDR_ID3_Msk (0x1UL << LPGPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define LPGPIO_IDR_ID3 LPGPIO_IDR_ID3_Msk +#define LPGPIO_IDR_ID4_Pos (4UL) +#define LPGPIO_IDR_ID4_Msk (0x1UL << LPGPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define LPGPIO_IDR_ID4 LPGPIO_IDR_ID4_Msk +#define LPGPIO_IDR_ID5_Pos (5UL) +#define LPGPIO_IDR_ID5_Msk (0x1UL << LPGPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define LPGPIO_IDR_ID5 LPGPIO_IDR_ID5_Msk +#define LPGPIO_IDR_ID6_Pos (6UL) +#define LPGPIO_IDR_ID6_Msk (0x1UL << LPGPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define LPGPIO_IDR_ID6 LPGPIO_IDR_ID6_Msk +#define LPGPIO_IDR_ID7_Pos (7UL) +#define LPGPIO_IDR_ID7_Msk (0x1UL << LPGPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define LPGPIO_IDR_ID7 LPGPIO_IDR_ID7_Msk +#define LPGPIO_IDR_ID8_Pos (8UL) +#define LPGPIO_IDR_ID8_Msk (0x1UL << LPGPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define LPGPIO_IDR_ID8 LPGPIO_IDR_ID8_Msk +#define LPGPIO_IDR_ID9_Pos (9UL) +#define LPGPIO_IDR_ID9_Msk (0x1UL << LPGPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define LPGPIO_IDR_ID9 LPGPIO_IDR_ID9_Msk +#define LPGPIO_IDR_ID10_Pos (10UL) +#define LPGPIO_IDR_ID10_Msk (0x1UL << LPGPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define LPGPIO_IDR_ID10 LPGPIO_IDR_ID10_Msk +#define LPGPIO_IDR_ID11_Pos (11UL) +#define LPGPIO_IDR_ID11_Msk (0x1UL << LPGPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define LPGPIO_IDR_ID11 LPGPIO_IDR_ID11_Msk +#define LPGPIO_IDR_ID12_Pos (12UL) +#define LPGPIO_IDR_ID12_Msk (0x1UL << LPGPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define LPGPIO_IDR_ID12 LPGPIO_IDR_ID12_Msk +#define LPGPIO_IDR_ID13_Pos (13UL) +#define LPGPIO_IDR_ID13_Msk (0x1UL << LPGPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define LPGPIO_IDR_ID13 LPGPIO_IDR_ID13_Msk +#define LPGPIO_IDR_ID14_Pos (14UL) +#define LPGPIO_IDR_ID14_Msk (0x1UL << LPGPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define LPGPIO_IDR_ID14 LPGPIO_IDR_ID14_Msk +#define LPGPIO_IDR_ID15_Pos (15UL) +#define LPGPIO_IDR_ID15_Msk (0x1UL << LPGPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define LPGPIO_IDR_ID15 LPGPIO_IDR_ID15_Msk + +/****************** Bits definition for LPGPIO_ODR register *******************/ +#define LPGPIO_ODR_OD0_Pos (0UL) +#define LPGPIO_ODR_OD0_Msk (0x1UL << LPGPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define LPGPIO_ODR_OD0 LPGPIO_ODR_OD0_Msk +#define LPGPIO_ODR_OD1_Pos (1UL) +#define LPGPIO_ODR_OD1_Msk (0x1UL << LPGPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define LPGPIO_ODR_OD1 LPGPIO_ODR_OD1_Msk +#define LPGPIO_ODR_OD2_Pos (2UL) +#define LPGPIO_ODR_OD2_Msk (0x1UL << LPGPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define LPGPIO_ODR_OD2 LPGPIO_ODR_OD2_Msk +#define LPGPIO_ODR_OD3_Pos (3UL) +#define LPGPIO_ODR_OD3_Msk (0x1UL << LPGPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define LPGPIO_ODR_OD3 LPGPIO_ODR_OD3_Msk +#define LPGPIO_ODR_OD4_Pos (4UL) +#define LPGPIO_ODR_OD4_Msk (0x1UL << LPGPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define LPGPIO_ODR_OD4 LPGPIO_ODR_OD4_Msk +#define LPGPIO_ODR_OD5_Pos (5UL) +#define LPGPIO_ODR_OD5_Msk (0x1UL << LPGPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define LPGPIO_ODR_OD5 LPGPIO_ODR_OD5_Msk +#define LPGPIO_ODR_OD6_Pos (6UL) +#define LPGPIO_ODR_OD6_Msk (0x1UL << LPGPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define LPGPIO_ODR_OD6 LPGPIO_ODR_OD6_Msk +#define LPGPIO_ODR_OD7_Pos (7UL) +#define LPGPIO_ODR_OD7_Msk (0x1UL << LPGPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define LPGPIO_ODR_OD7 LPGPIO_ODR_OD7_Msk +#define LPGPIO_ODR_OD8_Pos (8UL) +#define LPGPIO_ODR_OD8_Msk (0x1UL << LPGPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define LPGPIO_ODR_OD8 LPGPIO_ODR_OD8_Msk +#define LPGPIO_ODR_OD9_Pos (9UL) +#define LPGPIO_ODR_OD9_Msk (0x1UL << LPGPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define LPGPIO_ODR_OD9 LPGPIO_ODR_OD9_Msk +#define LPGPIO_ODR_OD10_Pos (10UL) +#define LPGPIO_ODR_OD10_Msk (0x1UL << LPGPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define LPGPIO_ODR_OD10 LPGPIO_ODR_OD10_Msk +#define LPGPIO_ODR_OD11_Pos (11UL) +#define LPGPIO_ODR_OD11_Msk (0x1UL << LPGPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define LPGPIO_ODR_OD11 LPGPIO_ODR_OD11_Msk +#define LPGPIO_ODR_OD12_Pos (12UL) +#define LPGPIO_ODR_OD12_Msk (0x1UL << LPGPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define LPGPIO_ODR_OD12 LPGPIO_ODR_OD12_Msk +#define LPGPIO_ODR_OD13_Pos (13UL) +#define LPGPIO_ODR_OD13_Msk (0x1UL << LPGPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define LPGPIO_ODR_OD13 LPGPIO_ODR_OD13_Msk +#define LPGPIO_ODR_OD14_Pos (14UL) +#define LPGPIO_ODR_OD14_Msk (0x1UL << LPGPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define LPGPIO_ODR_OD14 LPGPIO_ODR_OD14_Msk +#define LPGPIO_ODR_OD15_Pos (15UL) +#define LPGPIO_ODR_OD15_Msk (0x1UL << LPGPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define LPGPIO_ODR_OD15 LPGPIO_ODR_OD15_Msk + +/****************** Bits definition for LPGPIO_BSRR register ******************/ +#define LPGPIO_BSRR_BS0_Pos (0UL) +#define LPGPIO_BSRR_BS0_Msk (0x1UL << LPGPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define LPGPIO_BSRR_BS0 LPGPIO_BSRR_BS0_Msk +#define LPGPIO_BSRR_BS1_Pos (1UL) +#define LPGPIO_BSRR_BS1_Msk (0x1UL << LPGPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define LPGPIO_BSRR_BS1 LPGPIO_BSRR_BS1_Msk +#define LPGPIO_BSRR_BS2_Pos (2UL) +#define LPGPIO_BSRR_BS2_Msk (0x1UL << LPGPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define LPGPIO_BSRR_BS2 LPGPIO_BSRR_BS2_Msk +#define LPGPIO_BSRR_BS3_Pos (3UL) +#define LPGPIO_BSRR_BS3_Msk (0x1UL << LPGPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define LPGPIO_BSRR_BS3 LPGPIO_BSRR_BS3_Msk +#define LPGPIO_BSRR_BS4_Pos (4UL) +#define LPGPIO_BSRR_BS4_Msk (0x1UL << LPGPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define LPGPIO_BSRR_BS4 LPGPIO_BSRR_BS4_Msk +#define LPGPIO_BSRR_BS5_Pos (5UL) +#define LPGPIO_BSRR_BS5_Msk (0x1UL << LPGPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define LPGPIO_BSRR_BS5 LPGPIO_BSRR_BS5_Msk +#define LPGPIO_BSRR_BS6_Pos (6UL) +#define LPGPIO_BSRR_BS6_Msk (0x1UL << LPGPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define LPGPIO_BSRR_BS6 LPGPIO_BSRR_BS6_Msk +#define LPGPIO_BSRR_BS7_Pos (7UL) +#define LPGPIO_BSRR_BS7_Msk (0x1UL << LPGPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define LPGPIO_BSRR_BS7 LPGPIO_BSRR_BS7_Msk +#define LPGPIO_BSRR_BS8_Pos (8UL) +#define LPGPIO_BSRR_BS8_Msk (0x1UL << LPGPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define LPGPIO_BSRR_BS8 LPGPIO_BSRR_BS8_Msk +#define LPGPIO_BSRR_BS9_Pos (9UL) +#define LPGPIO_BSRR_BS9_Msk (0x1UL << LPGPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define LPGPIO_BSRR_BS9 LPGPIO_BSRR_BS9_Msk +#define LPGPIO_BSRR_BS10_Pos (10UL) +#define LPGPIO_BSRR_BS10_Msk (0x1UL << LPGPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define LPGPIO_BSRR_BS10 LPGPIO_BSRR_BS10_Msk +#define LPGPIO_BSRR_BS11_Pos (11UL) +#define LPGPIO_BSRR_BS11_Msk (0x1UL << LPGPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define LPGPIO_BSRR_BS11 LPGPIO_BSRR_BS11_Msk +#define LPGPIO_BSRR_BS12_Pos (12UL) +#define LPGPIO_BSRR_BS12_Msk (0x1UL << LPGPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define LPGPIO_BSRR_BS12 LPGPIO_BSRR_BS12_Msk +#define LPGPIO_BSRR_BS13_Pos (13UL) +#define LPGPIO_BSRR_BS13_Msk (0x1UL << LPGPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define LPGPIO_BSRR_BS13 LPGPIO_BSRR_BS13_Msk +#define LPGPIO_BSRR_BS14_Pos (14UL) +#define LPGPIO_BSRR_BS14_Msk (0x1UL << LPGPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define LPGPIO_BSRR_BS14 LPGPIO_BSRR_BS14_Msk +#define LPGPIO_BSRR_BS15_Pos (15UL) +#define LPGPIO_BSRR_BS15_Msk (0x1UL << LPGPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define LPGPIO_BSRR_BS15 LPGPIO_BSRR_BS15_Msk +#define LPGPIO_BSRR_BR0_Pos (16UL) +#define LPGPIO_BSRR_BR0_Msk (0x1UL << LPGPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define LPGPIO_BSRR_BR0 LPGPIO_BSRR_BR0_Msk +#define LPGPIO_BSRR_BR1_Pos (17UL) +#define LPGPIO_BSRR_BR1_Msk (0x1UL << LPGPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define LPGPIO_BSRR_BR1 LPGPIO_BSRR_BR1_Msk +#define LPGPIO_BSRR_BR2_Pos (18UL) +#define LPGPIO_BSRR_BR2_Msk (0x1UL << LPGPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define LPGPIO_BSRR_BR2 LPGPIO_BSRR_BR2_Msk +#define LPGPIO_BSRR_BR3_Pos (19UL) +#define LPGPIO_BSRR_BR3_Msk (0x1UL << LPGPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define LPGPIO_BSRR_BR3 LPGPIO_BSRR_BR3_Msk +#define LPGPIO_BSRR_BR4_Pos (20UL) +#define LPGPIO_BSRR_BR4_Msk (0x1UL << LPGPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define LPGPIO_BSRR_BR4 LPGPIO_BSRR_BR4_Msk +#define LPGPIO_BSRR_BR5_Pos (21UL) +#define LPGPIO_BSRR_BR5_Msk (0x1UL << LPGPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define LPGPIO_BSRR_BR5 LPGPIO_BSRR_BR5_Msk +#define LPGPIO_BSRR_BR6_Pos (22UL) +#define LPGPIO_BSRR_BR6_Msk (0x1UL << LPGPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define LPGPIO_BSRR_BR6 LPGPIO_BSRR_BR6_Msk +#define LPGPIO_BSRR_BR7_Pos (23UL) +#define LPGPIO_BSRR_BR7_Msk (0x1UL << LPGPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define LPGPIO_BSRR_BR7 LPGPIO_BSRR_BR7_Msk +#define LPGPIO_BSRR_BR8_Pos (24UL) +#define LPGPIO_BSRR_BR8_Msk (0x1UL << LPGPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define LPGPIO_BSRR_BR8 LPGPIO_BSRR_BR8_Msk +#define LPGPIO_BSRR_BR9_Pos (25UL) +#define LPGPIO_BSRR_BR9_Msk (0x1UL << LPGPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define LPGPIO_BSRR_BR9 LPGPIO_BSRR_BR9_Msk +#define LPGPIO_BSRR_BR10_Pos (26UL) +#define LPGPIO_BSRR_BR10_Msk (0x1UL << LPGPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define LPGPIO_BSRR_BR10 LPGPIO_BSRR_BR10_Msk +#define LPGPIO_BSRR_BR11_Pos (27UL) +#define LPGPIO_BSRR_BR11_Msk (0x1UL << LPGPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define LPGPIO_BSRR_BR11 LPGPIO_BSRR_BR11_Msk +#define LPGPIO_BSRR_BR12_Pos (28UL) +#define LPGPIO_BSRR_BR12_Msk (0x1UL << LPGPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define LPGPIO_BSRR_BR12 LPGPIO_BSRR_BR12_Msk +#define LPGPIO_BSRR_BR13_Pos (29UL) +#define LPGPIO_BSRR_BR13_Msk (0x1UL << LPGPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define LPGPIO_BSRR_BR13 LPGPIO_BSRR_BR13_Msk +#define LPGPIO_BSRR_BR14_Pos (30UL) +#define LPGPIO_BSRR_BR14_Msk (0x1UL << LPGPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define LPGPIO_BSRR_BR14 LPGPIO_BSRR_BR14_Msk +#define LPGPIO_BSRR_BR15_Pos (31UL) +#define LPGPIO_BSRR_BR15_Msk (0x1UL << LPGPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define LPGPIO_BSRR_BR15 LPGPIO_BSRR_BR15_Msk + +/****************** Bits definition for LPGPIO_BRR register ******************/ +#define LPGPIO_BRR_BR0_Pos (0UL) +#define LPGPIO_BRR_BR0_Msk (0x1UL << LPGPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define LPGPIO_BRR_BR0 LPGPIO_BRR_BR0_Msk +#define LPGPIO_BRR_BR1_Pos (1UL) +#define LPGPIO_BRR_BR1_Msk (0x1UL << LPGPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define LPGPIO_BRR_BR1 LPGPIO_BRR_BR1_Msk +#define LPGPIO_BRR_BR2_Pos (2UL) +#define LPGPIO_BRR_BR2_Msk (0x1UL << LPGPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define LPGPIO_BRR_BR2 LPGPIO_BRR_BR2_Msk +#define LPGPIO_BRR_BR3_Pos (3UL) +#define LPGPIO_BRR_BR3_Msk (0x1UL << LPGPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define LPGPIO_BRR_BR3 LPGPIO_BRR_BR3_Msk +#define LPGPIO_BRR_BR4_Pos (4UL) +#define LPGPIO_BRR_BR4_Msk (0x1UL << LPGPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define LPGPIO_BRR_BR4 LPGPIO_BRR_BR4_Msk +#define LPGPIO_BRR_BR5_Pos (5UL) +#define LPGPIO_BRR_BR5_Msk (0x1UL << LPGPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define LPGPIO_BRR_BR5 LPGPIO_BRR_BR5_Msk +#define LPGPIO_BRR_BR6_Pos (6UL) +#define LPGPIO_BRR_BR6_Msk (0x1UL << LPGPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define LPGPIO_BRR_BR6 LPGPIO_BRR_BR6_Msk +#define LPGPIO_BRR_BR7_Pos (7UL) +#define LPGPIO_BRR_BR7_Msk (0x1UL << LPGPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define LPGPIO_BRR_BR7 LPGPIO_BRR_BR7_Msk +#define LPGPIO_BRR_BR8_Pos (8UL) +#define LPGPIO_BRR_BR8_Msk (0x1UL << LPGPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define LPGPIO_BRR_BR8 LPGPIO_BRR_BR8_Msk +#define LPGPIO_BRR_BR9_Pos (9UL) +#define LPGPIO_BRR_BR9_Msk (0x1UL << LPGPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define LPGPIO_BRR_BR9 LPGPIO_BRR_BR9_Msk +#define LPGPIO_BRR_BR10_Pos (10UL) +#define LPGPIO_BRR_BR10_Msk (0x1UL << LPGPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define LPGPIO_BRR_BR10 LPGPIO_BRR_BR10_Msk +#define LPGPIO_BRR_BR11_Pos (11UL) +#define LPGPIO_BRR_BR11_Msk (0x1UL << LPGPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define LPGPIO_BRR_BR11 LPGPIO_BRR_BR11_Msk +#define LPGPIO_BRR_BR12_Pos (12UL) +#define LPGPIO_BRR_BR12_Msk (0x1UL << LPGPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define LPGPIO_BRR_BR12 LPGPIO_BRR_BR12_Msk +#define LPGPIO_BRR_BR13_Pos (13UL) +#define LPGPIO_BRR_BR13_Msk (0x1UL << LPGPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define LPGPIO_BRR_BR13 LPGPIO_BRR_BR13_Msk +#define LPGPIO_BRR_BR14_Pos (14UL) +#define LPGPIO_BRR_BR14_Msk (0x1UL << LPGPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define LPGPIO_BRR_BR14 LPGPIO_BRR_BR14_Msk +#define LPGPIO_BRR_BR15_Pos (15UL) +#define LPGPIO_BRR_BR15_Msk (0x1UL << LPGPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define LPGPIO_BRR_BR15 LPGPIO_BRR_BR15_Msk + +/******************************************************************************/ +/* */ +/* ICACHE */ +/* */ +/******************************************************************************/ +/****************** Bit definition for ICACHE_CR register *******************/ +#define ICACHE_CR_EN_Pos (0UL) +#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< Enable */ +#define ICACHE_CR_CACHEINV_Pos (1UL) +#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< Cache invalidation */ +#define ICACHE_CR_WAYSEL_Pos (2UL) +#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ +#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< Ways selection */ +#define ICACHE_CR_HITMEN_Pos (16UL) +#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ +#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< Hit monitor enable */ +#define ICACHE_CR_MISSMEN_Pos (17UL) +#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ +#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< Miss monitor enable */ +#define ICACHE_CR_HITMRST_Pos (18UL) +#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ +#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< Hit monitor reset */ +#define ICACHE_CR_MISSMRST_Pos (19UL) +#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ +#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< Miss monitor reset */ + +/****************** Bit definition for ICACHE_SR register *******************/ +#define ICACHE_SR_BUSYF_Pos (0UL) +#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< Busy flag */ +#define ICACHE_SR_BSYENDF_Pos (1UL) +#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< Busy end flag */ +#define ICACHE_SR_ERRF_Pos (2UL) +#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< Cache error flag */ + +/****************** Bit definition for ICACHE_IER register ******************/ +#define ICACHE_IER_BSYENDIE_Pos (1UL) +#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ +#define ICACHE_IER_ERRIE_Pos (2UL) +#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< Cache error interrupt enable */ + +/****************** Bit definition for ICACHE_FCR register ******************/ +#define ICACHE_FCR_CBSYENDF_Pos (1UL) +#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ +#define ICACHE_FCR_CERRF_Pos (2UL) +#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< Cache error flag clear */ + +/****************** Bit definition for ICACHE_HMONR register ****************/ +#define ICACHE_HMONR_HITMON_Pos (0UL) +#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ +#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< Cache hit monitor register */ + +/****************** Bit definition for ICACHE_MMONR register ****************/ +#define ICACHE_MMONR_MISSMON_Pos (0UL) +#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ +#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< Cache miss monitor register */ + +/****************** Bit definition for ICACHE_CRRx register *****************/ +#define ICACHE_CRRx_BASEADDR_Pos (0UL) +#define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */ +#define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< Base address of region X to remap */ +#define ICACHE_CRRx_RSIZE_Pos (9UL) +#define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */ +#define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< Region X size */ +#define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */ +#define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */ +#define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */ +#define ICACHE_CRRx_REN_Pos (15UL) +#define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */ +#define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< Region X enable */ +#define ICACHE_CRRx_REMAPADDR_Pos (16UL) +#define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */ +#define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< Remap address of Region X to be remapped */ +#define ICACHE_CRRx_MSTSEL_Pos (28UL) +#define ICACHE_CRRx_MSTSEL_Msk (0x1UL << ICACHE_CRRx_MSTSEL_Pos) /*!< 0x10000000 */ +#define ICACHE_CRRx_MSTSEL ICACHE_CRRx_MSTSEL_Msk /*!< Region X AHB cache master selection */ +#define ICACHE_CRRx_HBURST_Pos (31UL) +#define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */ +#define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< Region X output burst type */ + +/******************************************************************************/ +/* */ +/* DCACHE */ +/* */ +/******************************************************************************/ +/****************** Bit definition for DCACHE_CR register *******************/ +#define DCACHE_CR_EN_Pos (0UL) +#define DCACHE_CR_EN_Msk (0x1UL << DCACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define DCACHE_CR_EN DCACHE_CR_EN_Msk /*!< Enable */ +#define DCACHE_CR_CACHEINV_Pos (1UL) +#define DCACHE_CR_CACHEINV_Msk (0x1UL << DCACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define DCACHE_CR_CACHEINV DCACHE_CR_CACHEINV_Msk /*!< Cache invalidation */ +#define DCACHE_CR_CACHECMD_Pos (8UL) +#define DCACHE_CR_CACHECMD_Msk (0x7UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000700 */ +#define DCACHE_CR_CACHECMD DCACHE_CR_CACHECMD_Msk /*!< Cache command */ +#define DCACHE_CR_CACHECMD_0 (0x1UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000100 */ +#define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200 */ +#define DCACHE_CR_CACHECMD_2 (0x4UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000400 */ +#define DCACHE_CR_STARTCMD_Pos (11UL) +#define DCACHE_CR_STARTCMD_Msk (0x1UL << DCACHE_CR_STARTCMD_Pos) /*!< 0x00000800 */ +#define DCACHE_CR_STARTCMD DCACHE_CR_STARTCMD_Msk /*!< Start command */ +#define DCACHE_CR_RHITMEN_Pos (16UL) +#define DCACHE_CR_RHITMEN_Msk (0x1UL << DCACHE_CR_RHITMEN_Pos) /*!< 0x00010000 */ +#define DCACHE_CR_RHITMEN DCACHE_CR_RHITMEN_Msk /*!< Read Hit monitor enable */ +#define DCACHE_CR_RMISSMEN_Pos (17UL) +#define DCACHE_CR_RMISSMEN_Msk (0x1UL << DCACHE_CR_RMISSMEN_Pos) /*!< 0x00020000 */ +#define DCACHE_CR_RMISSMEN DCACHE_CR_RMISSMEN_Msk /*!< Read Miss monitor enable */ +#define DCACHE_CR_RHITMRST_Pos (18UL) +#define DCACHE_CR_RHITMRST_Msk (0x1UL << DCACHE_CR_RHITMRST_Pos) /*!< 0x00040000 */ +#define DCACHE_CR_RHITMRST DCACHE_CR_RHITMRST_Msk /*!< Read Hit monitor reset */ +#define DCACHE_CR_RMISSMRST_Pos (19UL) +#define DCACHE_CR_RMISSMRST_Msk (0x1UL << DCACHE_CR_RMISSMRST_Pos) /*!< 0x00080000 */ +#define DCACHE_CR_RMISSMRST DCACHE_CR_RMISSMRST_Msk /*!< Read Miss monitor reset */ +#define DCACHE_CR_WHITMEN_Pos (20UL) +#define DCACHE_CR_WHITMEN_Msk (0x1UL << DCACHE_CR_WHITMEN_Pos) /*!< 0x00100000 */ +#define DCACHE_CR_WHITMEN DCACHE_CR_WHITMEN_Msk /*!< Write Hit monitor enable */ +#define DCACHE_CR_WMISSMEN_Pos (21UL) +#define DCACHE_CR_WMISSMEN_Msk (0x1UL << DCACHE_CR_WMISSMEN_Pos) /*!< 0x00200000 */ +#define DCACHE_CR_WMISSMEN DCACHE_CR_WMISSMEN_Msk /*!< Write Miss monitor enable */ +#define DCACHE_CR_WHITMRST_Pos (22UL) +#define DCACHE_CR_WHITMRST_Msk (0x1UL << DCACHE_CR_WHITMRST_Pos) /*!< 0x00400000 */ +#define DCACHE_CR_WHITMRST DCACHE_CR_WHITMRST_Msk /*!< Write Hit monitor reset */ +#define DCACHE_CR_WMISSMRST_Pos (23UL) +#define DCACHE_CR_WMISSMRST_Msk (0x1UL << DCACHE_CR_WMISSMRST_Pos) /*!< 0x00800000 */ +#define DCACHE_CR_WMISSMRST DCACHE_CR_WMISSMRST_Msk /*!< Write Miss monitor reset */ +#define DCACHE_CR_HBURST_Pos (31UL) +#define DCACHE_CR_HBURST_Msk (0x1UL << DCACHE_CR_HBURST_Pos) /*!< 0x80000000 */ +#define DCACHE_CR_HBURST DCACHE_CR_HBURST_Msk /*!< Read burst type */ + +/****************** Bit definition for DCACHE_SR register *******************/ +#define DCACHE_SR_BUSYF_Pos (0UL) +#define DCACHE_SR_BUSYF_Msk (0x1UL << DCACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define DCACHE_SR_BUSYF DCACHE_SR_BUSYF_Msk /*!< Busy flag */ +#define DCACHE_SR_BSYENDF_Pos (1UL) +#define DCACHE_SR_BSYENDF_Msk (0x1UL << DCACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define DCACHE_SR_BSYENDF DCACHE_SR_BSYENDF_Msk /*!< Busy end flag */ +#define DCACHE_SR_ERRF_Pos (2UL) +#define DCACHE_SR_ERRF_Msk (0x1UL << DCACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define DCACHE_SR_ERRF DCACHE_SR_ERRF_Msk /*!< Cache error flag */ +#define DCACHE_SR_BUSYCMDF_Pos (3UL) +#define DCACHE_SR_BUSYCMDF_Msk (0x1UL << DCACHE_SR_BUSYCMDF_Pos) /*!< 0x00000008 */ +#define DCACHE_SR_BUSYCMDF DCACHE_SR_BUSYCMDF_Msk /*!< Busy command flag */ +#define DCACHE_SR_CMDENDF_Pos (4UL) +#define DCACHE_SR_CMDENDF_Msk (0x1UL << DCACHE_SR_CMDENDF_Pos) /*!< 0x00000010 */ +#define DCACHE_SR_CMDENDF DCACHE_SR_CMDENDF_Msk /*!< Command end flag */ + +/****************** Bit definition for DCACHE_IER register ******************/ +#define DCACHE_IER_BSYENDIE_Pos (1UL) +#define DCACHE_IER_BSYENDIE_Msk (0x1UL << DCACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define DCACHE_IER_BSYENDIE DCACHE_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ +#define DCACHE_IER_ERRIE_Pos (2UL) +#define DCACHE_IER_ERRIE_Msk (0x1UL << DCACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define DCACHE_IER_ERRIE DCACHE_IER_ERRIE_Msk /*!< Cache error interrupt enable */ +#define DCACHE_IER_CMDENDIE_Pos (4UL) +#define DCACHE_IER_CMDENDIE_Msk (0x1UL << DCACHE_IER_CMDENDIE_Pos) /*!< 0x00000010 */ +#define DCACHE_IER_CMDENDIE DCACHE_IER_CMDENDIE_Msk /*!< Command end interrupt enable */ + +/****************** Bit definition for DCACHE_FCR register ******************/ +#define DCACHE_FCR_CBSYENDF_Pos (1UL) +#define DCACHE_FCR_CBSYENDF_Msk (0x1UL << DCACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define DCACHE_FCR_CBSYENDF DCACHE_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ +#define DCACHE_FCR_CERRF_Pos (2UL) +#define DCACHE_FCR_CERRF_Msk (0x1UL << DCACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define DCACHE_FCR_CERRF DCACHE_FCR_CERRF_Msk /*!< Cache error flag clear */ +#define DCACHE_FCR_CCMDENDF_Pos (4UL) +#define DCACHE_FCR_CCMDENDF_Msk (0x1UL << DCACHE_FCR_CCMDENDF_Pos) /*!< 0x00000010 */ +#define DCACHE_FCR_CCMDENDF DCACHE_FCR_CCMDENDF_Msk /*!< Command end flag clear */ + +/****************** Bit definition for DCACHE_RHMONR register ****************/ +#define DCACHE_RHMONR_RHITMON_Pos (0UL) +#define DCACHE_RHMONR_RHITMON_Msk (0xFFFFFFFFUL << DCACHE_RHMONR_RHITMON_Pos) /*!< 0xFFFFFFFF */ +#define DCACHE_RHMONR_RHITMON DCACHE_RHMONR_RHITMON_Msk /*!< Cache Read hit monitor register */ + +/****************** Bit definition for DCACHE_RMMONR register ****************/ +#define DCACHE_RMMONR_RMISSMON_Pos (0UL) +#define DCACHE_RMMONR_RMISSMON_Msk (0xFFFFUL << DCACHE_RMMONR_RMISSMON_Pos) /*!< 0x0000FFFF */ +#define DCACHE_RMMONR_RMISSMON DCACHE_RMMONR_RMISSMON_Msk /*!< Cache Read miss monitor register */ + +/****************** Bit definition for DCACHE_WHMONR register ****************/ +#define DCACHE_WHMONR_WHITMON_Pos (0UL) +#define DCACHE_WHMONR_WHITMON_Msk (0xFFFFFFFFUL << DCACHE_WHMONR_WHITMON_Pos) /*!< 0xFFFFFFFF */ +#define DCACHE_WHMONR_WHITMON DCACHE_WHMONR_WHITMON_Msk /*!< Cache Read hit monitor register */ + +/****************** Bit definition for DCACHE_WMMONR register ****************/ +#define DCACHE_WMMONR_WMISSMON_Pos (0UL) +#define DCACHE_WMMONR_WMISSMON_Msk (0xFFFFUL << DCACHE_WMMONR_WMISSMON_Pos) /*!< 0x0000FFFF */ +#define DCACHE_WMMONR_WMISSMON DCACHE_WMMONR_WMISSMON_Msk /*!< Cache Read miss monitor register */ + +/****************** Bit definition for DCACHE_CMDRSADDRR register ****************/ +#define DCACHE_CMDRSADDRR_CMDSTARTADDR_Pos (0UL) +#define DCACHE_CMDRSADDRR_CMDSTARTADDR_Msk (0xFFFFFFF0UL << DCACHE_CMDRSADDRR_CMDSTARTADDR_Pos) /*!< 0xFFFFFFF0 */ +#define DCACHE_CMDRSADDRR_CMDSTARTADDR DCACHE_CMDRSADDRR_CMDSTARTADDR_Msk /*!< Command start address */ + +/****************** Bit definition for DCACHE_CMDREADDRR register ****************/ +#define DCACHE_CMDREADDRR_CMDENDADDR_Pos (0UL) +#define DCACHE_CMDREADDRR_CMDENDADDR_Msk (0xFFFFFFF0UL << DCACHE_CMDREADDRR_CMDENDADDR_Pos) /*!< 0xFFFFFFF0 */ +#define DCACHE_CMDREADDRR_CMDENDADDR DCACHE_CMDREADDRR_CMDENDADDR_Msk /*!< Command end address */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ + +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0UL) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ +#define COMP_CSR_INMSEL_Pos (4UL) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x000000F0 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ +#define COMP_CSR_INPSEL_Pos (8UL) +#define COMP_CSR_INPSEL_Msk (0x7UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000700 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000200 */ +#define COMP_CSR_INPSEL_2 (0x4UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000400 */ +#define COMP_CSR_WINMODE_Pos (11UL) +#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000800 */ +#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ +#define COMP_CSR_WINOUT_Pos (14UL) +#define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ +#define COMP_CSR_POLARITY_Pos (15UL) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ +#define COMP_CSR_HYST_Pos (16UL) +#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator input hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_PWRMODE_Pos (18UL) +#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x000C0000 */ +#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ +#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00040000 */ +#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKSEL_Pos (20UL) +#define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01F00000 */ +#define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKSEL_0 (0x01UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKSEL_1 (0x02UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00200000 */ +#define COMP_CSR_BLANKSEL_2 (0x04UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BLANKSEL_3 (0x08UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00800000 */ +#define COMP_CSR_BLANKSEL_4 (0x10UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ +#define COMP_CSR_VALUE_Pos (30UL) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ +#define COMP_CSR_LOCK_Pos (31UL) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* Operational Amplifier (OPAMP) */ +/* */ +/******************************************************************************/ +/********************* Bit definition for OPAMPx_CSR register ***************/ +#define OPAMP_CSR_OPAEN_Pos (0UL) +#define OPAMP_CSR_OPAEN_Msk (0x1UL << OPAMP_CSR_OPAEN_Pos) /*!< 0x00000001 */ +#define OPAMP_CSR_OPAEN OPAMP_CSR_OPAEN_Msk /*!< OPAMP enable */ +#define OPAMP_CSR_OPALPM_Pos (1UL) +#define OPAMP_CSR_OPALPM_Msk (0x1UL << OPAMP_CSR_OPALPM_Pos) /*!< 0x00000002 */ +#define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk /*!< Operational amplifier Low Power Mode */ +#define OPAMP_CSR_OPAMODE_Pos (2UL) +#define OPAMP_CSR_OPAMODE_Msk (0x3UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x0000000C */ +#define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk /*!< Operational amplifier PGA mode */ +#define OPAMP_CSR_OPAMODE_0 (0x1UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000004 */ +#define OPAMP_CSR_OPAMODE_1 (0x2UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000008 */ +#define OPAMP_CSR_PGA_GAIN_Pos (4UL) +#define OPAMP_CSR_PGA_GAIN_Msk (0x3UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00000030 */ +#define OPAMP_CSR_PGA_GAIN OPAMP_CSR_PGA_GAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */ +#define OPAMP_CSR_PGA_GAIN_0 (0x1UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00000010 */ +#define OPAMP_CSR_PGA_GAIN_1 (0x2UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00000020 */ +#define OPAMP_CSR_VM_SEL_Pos (8UL) +#define OPAMP_CSR_VM_SEL_Msk (0x3UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000300 */ +#define OPAMP_CSR_VM_SEL OPAMP_CSR_VM_SEL_Msk /*!< Inverting input selection */ +#define OPAMP_CSR_VM_SEL_0 (0x1UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000100 */ +#define OPAMP_CSR_VM_SEL_1 (0x2UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000200 */ +#define OPAMP_CSR_VP_SEL_Pos (10UL) +#define OPAMP_CSR_VP_SEL_Msk (0x1UL << OPAMP_CSR_VP_SEL_Pos) /*!< 0x00000400 */ +#define OPAMP_CSR_VP_SEL OPAMP_CSR_VP_SEL_Msk /*!< Non inverted input selection */ +#define OPAMP_CSR_CALON_Pos (12UL) +#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00001000 */ +#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */ +#define OPAMP_CSR_CALSEL_Pos (13UL) +#define OPAMP_CSR_CALSEL_Msk (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */ +#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */ +#define OPAMP_CSR_USERTRIM_Pos (14UL) +#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00004000 */ +#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */ +#define OPAMP_CSR_CALOUT_Pos (15UL) +#define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) /*!< 0x00008000 */ +#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier calibration output */ +#define OPAMP_CSR_HSM_Pos (30UL) +#define OPAMP_CSR_HSM_Msk (0x1UL << OPAMP_CSR_HSM_Pos) /*!< 0x40000000 */ +#define OPAMP_CSR_HSM OPAMP_CSR_HSM_Msk /*!< Operational amplifier high speed mode */ +#define OPAMP_CSR_OPARANGE_Pos (31UL) +#define OPAMP_CSR_OPARANGE_Msk (0x1UL << OPAMP_CSR_OPARANGE_Pos) /*!< 0x80000000 */ +#define OPAMP_CSR_OPARANGE OPAMP_CSR_OPARANGE_Msk /*!< Operational amplifier range setting */ + +/******************* Bit definition for OPAMPx_OTR register ******************/ +#define OPAMP_OTR_TRIMOFFSETN_Pos (0UL) +#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */ +#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */ +#define OPAMP_OTR_TRIMOFFSETP_Pos (8UL) +#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */ +#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */ + +/******************* Bit definition for OPAMPx_LPOTR register ****************/ +#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0UL) +#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */ +#define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */ +#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8UL) +#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */ +#define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */ + +/******************************************************************************/ +/* */ +/* MDF/ADF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for MDF/ADF_GCR register ********************/ +#define MDF_GCR_TRGO_Pos (0UL) +#define MDF_GCR_TRGO_Msk (0x1UL << MDF_GCR_TRGO_Pos) /*!< 0x00000001 */ +#define MDF_GCR_TRGO MDF_GCR_TRGO_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0UL) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1UL) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2UL) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3UL) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4UL) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5UL) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6UL) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7UL) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16UL) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17UL) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18UL) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20UL) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21UL) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22UL) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23UL) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24UL) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26UL) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27UL) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28UL) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16UL) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17UL) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18UL) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22UL) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23UL) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24UL) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25UL) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26UL) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27UL) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28UL) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29UL) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30UL) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31UL) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24UL) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31UL) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0UL) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0UL) +#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14UL) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15UL) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0UL) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1UL) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2UL) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3UL) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4UL) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5UL) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6UL) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7UL) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16UL) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17UL) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18UL) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20UL) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21UL) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22UL) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23UL) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24UL) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26UL) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27UL) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28UL) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0UL) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1UL) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2UL) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3UL) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4UL) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5UL) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6UL) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7UL) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16UL) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17UL) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18UL) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP5F_Pos (20UL) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21UL) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22UL) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23UL) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24UL) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26UL) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27UL) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28UL) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0UL) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1UL) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2UL) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3UL) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4UL) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5UL) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6UL) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7UL) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16UL) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17UL) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18UL) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20UL) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21UL) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22UL) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23UL) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24UL) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26UL) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27UL) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28UL) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0UL) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1UL) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2UL) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3UL) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4UL) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5UL) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6UL) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7UL) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0UL) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1UL) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2UL) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3UL) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4UL) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5UL) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6UL) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7UL) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16UL) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17UL) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18UL) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20UL) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21UL) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22UL) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23UL) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24UL) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26UL) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27UL) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28UL) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk + +/******************** Bits definition for TAMP_COUNTR register ***************/ +#define TAMP_COUNTR_Pos (16UL) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_ERCFGR register ***************/ +#define TAMP_ERCFGR0_Pos (0UL) +#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0UL) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0UL) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0UL) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0UL) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0UL) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0UL) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0UL) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0UL) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0UL) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0UL) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0UL) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0UL) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0UL) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0UL) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0UL) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0UL) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0UL) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0UL) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0UL) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0UL) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0UL) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0UL) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0UL) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0UL) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0UL) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0UL) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0UL) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0UL) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0UL) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0UL) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0UL) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0UL) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Touch Sensing Controller (TSC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TSC_CR register *********************/ +#define TSC_CR_TSCE_Pos (0UL) +#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ +#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/** @addtogroup STM32U5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS)|| \ + ((INSTANCE) == ADC1_S) || \ + ((INSTANCE) == ADC4_NS)|| \ + ((INSTANCE) == ADC4_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ + ((INSTANCE) == ADC12_COMMON_S) || \ + ((INSTANCE) == ADC4_COMMON_NS) || \ + ((INSTANCE) == ADC4_COMMON_S)) + +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S)) + +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************** FDCAN Instances *****************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S)) + +/******************************** COMP Instances ******************************/ +#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S)) + +/******************************* CORDIC Instances *****************************/ +#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S )) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S) || \ + ((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +#define IS_LPDMA_INSTANCE(INSTANCE) (((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +/****************************** OTFDEC Instances ********************************/ +#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM4_NS) || ((INSTANCE) == RAMCFG_SRAM4_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG IT Instances ******************************/ +#define IS_RAMCFG_IT_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + +/******************************** FMAC Instances ******************************/ +#define IS_FMAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FMAC_NS) || ((INSTANCE) == FMAC_S)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S) || \ + ((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/******************************* LPGPIO Instances *****************************/ +#define IS_LPGPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S)) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On U5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On U5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************************** OPAMP Instances *******************************/ +#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1_NS) || ((INSTANCE) == OPAMP1_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S)) +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +/******************* SMBUS Instances : Group belongingness *********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) ||\ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) ||\ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) ||\ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) ||\ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) ||\ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) ||\ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)||\ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) ||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \ + ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \ + ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \ + ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \ + ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \ + ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \ + ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/******************************* USB DRD FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/******************************* USB DRD FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/******************************* MDF/ADF Instances ****************************/ +#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_NS) || ((INSTANCE) == MDF1_Filter0_S) || \ + ((INSTANCE) == MDF1_Filter1_NS) || ((INSTANCE) == MDF1_Filter1_S) || \ + ((INSTANCE) == MDF1_Filter2_NS) || ((INSTANCE) == MDF1_Filter2_S) || \ + ((INSTANCE) == MDF1_Filter3_NS) || ((INSTANCE) == MDF1_Filter3_S) || \ + ((INSTANCE) == MDF1_Filter4_NS) || ((INSTANCE) == MDF1_Filter4_S) || \ + ((INSTANCE) == MDF1_Filter5_NS) || ((INSTANCE) == MDF1_Filter5_S) || \ + ((INSTANCE) == ADF1_Filter0_NS) || ((INSTANCE) == ADF1_Filter0_S)) + + +/** @} */ /* End of group STM32U5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32U545xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U545xx_H */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h new file mode 100644 index 000000000..70d1922d5 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h @@ -0,0 +1,268 @@ +/** + ****************************************************************************** + * @file stm32u5xx.h + * @author MCD Application Team + * @brief CMSIS STM32U5xx Device Peripheral Access Layer Header File. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The STM32U5xx device used in the target application + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers + * rather than drivers API), this option is controlled by + * "#define USE_HAL_DRIVER" + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32u5xx + * @{ + */ + +#ifndef STM32U5xx_H +#define STM32U5xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32U5) +#define STM32U5 +#endif /* STM32U5 */ + +/* Uncomment the line below according to the target STM32U5 device used in your + application + */ + +#if !defined (STM32U575xx) && !defined (STM32U585xx) \ + && !defined (STM32U595xx) && !defined (STM32U599xx) \ + && !defined (STM32U5A5xx) && !defined (STM32U5A9xx) \ + && !defined (STM32U5F7xx) && !defined (STM32U5G7xx) \ + && !defined (STM32U5F9xx) && !defined (STM32U5G9xx) \ + && !defined (STM32U535xx) && !defined (STM32U545xx) \ + /* #define STM32U575xx */ /*!< STM32U575CIU6 STM32U575CIT6 STM32U575RIT6 STM32U575VIT6 STM32U575ZIT6 STM32U575QII6 STM32U575AII6 STM32U575CIU6Q STM32U575CIT6Q STM32U575OIY6Q STM32U575VIT6Q STM32U575QII6Q STM32U575ZIT6Q STM32U575RIT6Q STM32U575CGU6 STM32U575CGT6 STM32U575RGT6 STM32U575VGT6 STM32U575ZGT6 STM32U575QGI6 STM32U575AGI6 STM32U575CGU6Q STM32U575CGT6Q STM32U575OGY6Q STM32U575VGT6Q STM32U575QGI6Q STM32U575ZGT6Q STM32U575RGT6Q STM32U575AGI6Q Devices */ + /* #define STM32U585xx */ /*!< STM32U585CIU6 STM32U585CIT6 STM32U585RIT6 STM32U585VIT6 STM32U585AII6 STM32U585QII6 STM32U585ZIT6 STM32U585OIY6Q STM32U585VIT6Q STM32U585QEI6Q STM32U585RIT6Q STM32U585AII6Q STM32U585CIU6Q STM32U585CIT6Q STM32U585ZET6Q Devices */ + /* #define STM32U595xx */ /*!< STM32U595AJH6 STM32U595ZJT6 STM32U595QJI6 STM32U595VJT6 STM32U595RJT6 STM32U595AJH6Q STM32U595ZJY6QTR STM32U595ZJT6Q STM32U595QJI6Q STM32U595VJT6Q STM32U595RJT6Q STM32U595AIH6 STM32U595ZIT6 STM32U595QII6 STM32U595VIT6 STM32U595RIT6 STM32U595AIH6Q STM32U595ZIY6QTR STM32U595ZIT6Q STM32U595QII6Q STM32U595VIT6Q STM32U595RIT6Q Devices */ + /* #define STM32U599xx */ /*!< STM32U599VJT6 STM32U599NJH6Q STM32U599BJY6QTR STM32U599ZJY6QTR STM32U599ZJT6Q STM32U599VJT6Q STM32U599NIH6Q STM32U599ZIY6QTR STM32U599ZIT6Q STM32U599VIT6Q Devices */ + /* #define STM32U5A5xx */ /*!< STM32U5A5AJH6 STM32U5A5ZJT6 STM32U5A5QJI6 STM32U5A5VJT6 STM32U5A5RJT6 STM32U5A5AJH6Q STM32U5A5ZJY6QTR STM32U5A5ZJT6Q STM32U5A5QJI6Q STM32U5A5VJT6Q STM32U5A5RJT6Q STM32U5A5QII3Q Devices */ + /* #define STM32U5A9xx */ /*!< STM32U5A9NJH6Q STM32U5A9BJY6QTR STM32U5A9ZJY6QTR STM32U5A9ZJT6Q STM32U5A9VJT6Q Devices */ + /* #define STM32U5F7xx */ /*!< STM32U5F7VJT6Q STM32U5F7VJT6 STM32U5F7VIT6Q STM32U5F7VIT6 Devices */ + /* #define STM32U5G7xx */ /*!< STM32U5G7VJT6Q STM32U5G7VJT6 Devices */ + /* #define STM32U5F9xx */ /*!< STM32U5F9NJH6Q STM32U5F9BJY6QTR STM32U5F9ZJJ6QTR STM32U5F9ZJT6Q STM32U5F9VJT6Q STM32U5F9ZIJ6QTR STM32U5F9ZIT6Q STM32U5F9VIT6Q Devices */ + /* #define STM32U5G9xx */ /*!< STM32U5G9NJH6Q STM32U5G9BJY6QTR STM32U5G9ZJJ6QTR STM32U5G9ZJT6Q STM32U5G9VJT6Q Devices */ + /* #define STM32U535xx */ /*!< STM32U535CET6 STM32U535CEU6 STM32U535RET6 STM32U535REI6 STM32U535VET6 STM32U535VEI6 STM32U535CET6Q STM32U535CEU6Q STM32U535RET6Q STM32U535REI6Q STM32U535VET6Q STM32U535VEI6Q STM32U535NEY6Q STM32U535JEY6Q Devices */ + /* #define STM32U545xx */ /*!< STM32U545CET6 STM32U545CEU6 STM32U545RET6 STM32U545REI6 STM32U545VET6 STM32U545VEI6 STM32U545CET6Q STM32U545CEU6Q STM32U545RET6Q STM32U545REI6Q STM32U545VET6Q STM32U545VEI6Q STM32U545NEY6Q STM32U545JEY6Q Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number 1.4.2 + */ +#define __STM32U5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32U5_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ +#define __STM32U5_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ +#define __STM32U5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32U5_CMSIS_VERSION ((__STM32U5_CMSIS_VERSION_MAIN << 24U)\ + |(__STM32U5_CMSIS_VERSION_SUB1 << 16U)\ + |(__STM32U5_CMSIS_VERSION_SUB2 << 8U )\ + |(__STM32U5_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32U575xx) + #include "stm32u575xx.h" +#elif defined(STM32U585xx) + #include "stm32u585xx.h" +#elif defined(STM32U595xx) + #include "stm32u595xx.h" +#elif defined(STM32U599xx) + #include "stm32u599xx.h" +#elif defined(STM32U5A5xx) + #include "stm32u5a5xx.h" +#elif defined(STM32U5A9xx) + #include "stm32u5a9xx.h" +#elif defined(STM32U5F9xx) + #include "stm32u5f9xx.h" +#elif defined(STM32U5G9xx) + #include "stm32u5g9xx.h" +#elif defined(STM32U5F7xx) + #include "stm32u5f7xx.h" +#elif defined(STM32U5G7xx) + #include "stm32u5g7xx.h" +#elif defined(STM32U535xx) + #include "stm32u535xx.h" +#elif defined(STM32U545xx) + #include "stm32u545xx.h" +#else + #error "Please select first the target STM32U5xx device used in your application (in stm32u5xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/* Use of CMSIS compiler intrinsics for register exclusive access */ +/* Atomic 32-bit register access macro to set one or several bits */ +#define ATOMIC_SET_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEAR_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint32_t val; \ + do { \ + val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to set one or several bits */ +#define ATOMIC_SETH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEARH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint16_t val; \ + do { \ + val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32u5xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32U5xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/system_stm32u5xx.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/system_stm32u5xx.h new file mode 100644 index 000000000..811a27024 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Device/ST/STM32U5xx/Include/system_stm32u5xx.h @@ -0,0 +1,109 @@ +/** + ****************************************************************************** + * @file system_stm32u5xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M33 Device System Source File for STM32U5xx devices. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32u5xx_system + * @{ + */ + +#ifndef SYSTEM_STM32U5XX_H +#define SYSTEM_STM32U5XX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup STM32U5xx_System_Includes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Exported_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint32_t MSIRangeTable[16]; /*!< MSI ranges table values */ + +/** + * @} + */ + + +/** @addtogroup STM32U5xx_System_Exported_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + * @brief Update SystemCoreClock variable. + * + * Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + + +/** + * @brief Update SystemCoreClock variable from secure application and return its value + * when security is implemented in the system (Non-secure callable function). + * + * Returns the SystemCoreClock value with current core Clock retrieved from cpu registers. + */ +extern uint32_t SECURE_SystemCoreClockUpdate(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_STM32U5XX_H */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Device/ST/STM32U5xx/LICENSE.md b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Device/ST/STM32U5xx/LICENSE.md new file mode 100644 index 000000000..d1a7d01b0 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Device/ST/STM32U5xx/LICENSE.md @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. For the purposes of this definition, + "control" means (i) the power, direct or indirect, to cause the + direction or management of such entity, whether by contract or + otherwise, or (ii) ownership of fifty percent (50%) or more of the + outstanding shares, or (iii) beneficial ownership of such entity. + + "You" (or "Your") shall mean an individual or Legal Entity + exercising permissions granted by this License. + + "Source" form shall mean the preferred form for making modifications, + including but not limited to software source code, documentation + source, and configuration files. + + "Object" form shall mean any form resulting from mechanical + transformation or translation of a Source form, including but + not limited to compiled object code, generated documentation, + and conversions to other media types. + + "Work" shall mean the work of authorship, whether in Source or + Object form, made available under the License, as indicated by a + copyright notice that is included in or attached to the work + (an example is provided in the Appendix below). + + "Derivative Works" shall mean any work, whether in Source or Object + form, that is based on (or derived from) the Work and for which the + editorial revisions, annotations, elaborations, or other modifications + represent, as a whole, an original work of authorship. For the purposes + of this License, Derivative Works shall not include works that remain + separable from, or merely link (or bind by name) to the interfaces of, + the Work and Derivative Works thereof. + + "Contribution" shall mean any work of authorship, including + the original version of the Work and any modifications or additions + to that Work or Derivative Works thereof, that is intentionally + submitted to Licensor for inclusion in the Work by the copyright owner + or by an individual or Legal Entity authorized to submit on behalf of + the copyright owner. For the purposes of this definition, "submitted" + means any form of electronic, verbal, or written communication sent + to the Licensor or its representatives, including but not limited to + communication on electronic mailing lists, source code control systems, + and issue tracking systems that are managed by, or on behalf of, the + Licensor for the purpose of discussing and improving the Work, but + excluding communication that is conspicuously marked or otherwise + designated in writing by the copyright owner as "Not a Contribution." + + "Contributor" shall mean Licensor and any individual or Legal Entity + on behalf of whom a Contribution has been received by Licensor and + subsequently incorporated within the Work. + + 2. Grant of Copyright License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + copyright license to reproduce, prepare Derivative Works of, + publicly display, publicly perform, sublicense, and distribute the + Work and such Derivative Works in Source or Object form. + + 3. Grant of Patent License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + (except as stated in this section) patent license to make, have made, + use, offer to sell, sell, import, and otherwise transfer the Work, + where such license applies only to those patent claims licensable + by such Contributor that are necessarily infringed by their + Contribution(s) alone or by combination of their Contribution(s) + with the Work to which such Contribution(s) was submitted. If You + institute patent litigation against any entity (including a + cross-claim or counterclaim in a lawsuit) alleging that the Work + or a Contribution incorporated within the Work constitutes direct + or contributory patent infringement, then any patent licenses + granted to You under this License for that Work shall terminate + as of the date such litigation is filed. + + 4. Redistribution. You may reproduce and distribute copies of the + Work or Derivative Works thereof in any medium, with or without + modifications, and in Source or Object form, provided that You + meet the following conditions: + + (a) You must give any other recipients of the Work or + Derivative Works a copy of this License; and + + (b) You must cause any modified files to carry prominent notices + stating that You changed the files; and + + (c) You must retain, in the Source form of any Derivative Works + that You distribute, all copyright, patent, trademark, and + attribution notices from the Source form of the Work, + excluding those notices that do not pertain to any part of + the Derivative Works; and + + (d) If the Work includes a "NOTICE" text file as part of its + distribution, then any Derivative Works that You distribute must + include a readable copy of the attribution notices contained + within such NOTICE file, excluding those notices that do not + pertain to any part of the Derivative Works, in at least one + of the following places: within a NOTICE text file distributed + as part of the Derivative Works; within the Source form or + documentation, if provided along with the Derivative Works; or, + within a display generated by the Derivative Works, if and + wherever such third-party notices normally appear. The contents + of the NOTICE file are for informational purposes only and + do not modify the License. You may add Your own attribution + notices within Derivative Works that You distribute, alongside + or as an addendum to the NOTICE text from the Work, provided + that such additional attribution notices cannot be construed + as modifying the License. + + You may add Your own copyright statement to Your modifications and + may provide additional or different license terms and conditions + for use, reproduction, or distribution of Your modifications, or + for any such Derivative Works as a whole, provided Your use, + reproduction, and distribution of the Work otherwise complies with + the conditions stated in this License. + + 5. Submission of Contributions. Unless You explicitly state otherwise, + any Contribution intentionally submitted for inclusion in the Work + by You to the Licensor shall be under the terms and conditions of + this License, without any additional terms or conditions. + Notwithstanding the above, nothing herein shall supersede or modify + the terms of any separate license agreement you may have executed + with Licensor regarding such Contributions. + + 6. Trademarks. This License does not grant permission to use the trade + names, trademarks, service marks, or product names of the Licensor, + except as required for reasonable and customary use in describing the + origin of the Work and reproducing the content of the NOTICE file. + + 7. Disclaimer of Warranty. Unless required by applicable law or + agreed to in writing, Licensor provides the Work (and each + Contributor provides its Contributions) on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied, including, without limitation, any warranties or conditions + of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A + PARTICULAR PURPOSE. You are solely responsible for determining the + appropriateness of using or redistributing the Work and assume any + risks associated with Your exercise of permissions under this License. + + 8. Limitation of Liability. In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "[]" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright 2021 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. \ No newline at end of file diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Device/ST/STM32U5xx/LICENSE.txt b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Device/ST/STM32U5xx/LICENSE.txt new file mode 100644 index 000000000..2ab18ddaf --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Device/ST/STM32U5xx/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the Apache-2.0 license shall apply. +You may obtain a copy of the Apache-2.0 at: +https://opensource.org/licenses/Apache-2.0 \ No newline at end of file diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cachel1_armv7.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cachel1_armv7.h new file mode 100644 index 000000000..efb29d88b --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cachel1_armv7.h @@ -0,0 +1,441 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.3 + * @date 17. March 2023 + ******************************************************************************/ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + struct { + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + } locals + #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__)) + __ALIGNED(__SCB_DCACHE_LINE_SIZE) + #endif + ; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + #if !defined(__OPTIMIZE__) + /* + * For the endless loop issue with no optimization builds. + * More details, see https://github.com/ARM-software/CMSIS_5/issues/620 + * + * The issue only happens when local variables are in stack. If + * local variables are saved in general purpose register, then the function + * is OK. + * + * When local variables are in stack, after disabling the cache, flush the + * local variables cache line for data consistency. + */ + /* Clean and invalidate the local variable cache. */ + #if defined(__ICCARM__) + /* As we can't align the stack to the cache line size, invalidate each of the variables */ + SCB->DCCIMVAC = (uint32_t)&locals.sets; + SCB->DCCIMVAC = (uint32_t)&locals.ways; + SCB->DCCIMVAC = (uint32_t)&locals.ccsidr; + #else + SCB->DCCIMVAC = (uint32_t)&locals; + #endif + __DSB(); + __ISB(); + #endif + + locals.ccsidr = SCB->CCSIDR; + /* clean & invalidate D-Cache */ + locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr)); + do { + locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr)); + do { + SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (locals.ways-- != 0U); + } while(locals.sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_armcc.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 000000000..a955d4713 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_armclang.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 000000000..691141774 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_armclang_ltm.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 000000000..1e255d590 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_compiler.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 000000000..adbf296f1 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_gcc.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 000000000..67bda4ef3 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_iccarm.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 000000000..65b824b00 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_version.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_version.h new file mode 100644 index 000000000..8b4765f18 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_armv81mml.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_armv81mml.h new file mode 100644 index 000000000..94128a1a7 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_armv81mml.h @@ -0,0 +1,4228 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.4.2 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_armv8mbl.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 000000000..932d3d188 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_armv8mml.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_armv8mml.h new file mode 100644 index 000000000..c119fbf24 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,3209 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm0.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm0.h new file mode 100644 index 000000000..6441ff341 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm0plus.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm0plus.h new file mode 100644 index 000000000..4e7179a61 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm1.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm1.h new file mode 100644 index 000000000..76b456974 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm23.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm23.h new file mode 100644 index 000000000..55fff9950 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm23.h @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm3.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm3.h new file mode 100644 index 000000000..74fb87e5c --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm33.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm33.h new file mode 100644 index 000000000..18a2e6fb0 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm33.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm35p.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm35p.h new file mode 100644 index 000000000..3843d9542 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm35p.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm4.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm4.h new file mode 100644 index 000000000..e21cd1492 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm55.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm55.h new file mode 100644 index 000000000..faa30ce36 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm55.h @@ -0,0 +1,4817 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.2.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2018-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ +#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ + +#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ +#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ + +#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ +#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sanple Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + +} STL_Type; + +/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ + +/* 'SCnSCB' is deprecated and replaced by 'ICB' */ +typedef ICB_Type SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk) + +#define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos) +#define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk) + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk) + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos) +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk) + +#define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos) +#define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk) + +#define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos) +#define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk) + +#define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos) +#define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk) + +#define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos) +#define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk) + +#define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos) +#define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk) + +#define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos) +#define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk) + +#define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos) +#define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk) + +#define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos) +#define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk) + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos) +#define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk) + +#define SCnSCB (ICB) +#define SCnSCB_NS (ICB_NS) + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm7.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm7.h new file mode 100644 index 000000000..010506e9f --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm7.h @@ -0,0 +1,2366 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.6 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm85.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm85.h new file mode 100644 index 000000000..604631118 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_cm85.h @@ -0,0 +1,4672 @@ +/**************************************************************************//** + * @file core_cm85.h + * @brief CMSIS Cortex-M85 Core Peripheral Access Layer Header File + * @version V1.0.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM85_H_GENERIC +#define __CORE_CM85_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M85 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM85 definitions */ + +#define __CORTEX_M (85U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM85_H_DEPENDANT +#define __CORE_CM85_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM85_REV + #define __CM85_REV 0x0001U + #warning "__CM85_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M85 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ +#define MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M85 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ +#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ +#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ +#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ +#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "pac_armv81.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_sc000.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_sc000.h new file mode 100644 index 000000000..dbc755fff --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_sc000.h @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_sc300.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_sc300.h new file mode 100644 index 000000000..d66621031 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_sc300.h @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.10 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_starmc1.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_starmc1.h new file mode 100644 index 000000000..d86c8d385 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/core_starmc1.h @@ -0,0 +1,3592 @@ +/**************************************************************************//** + * @file core_starmc1.h + * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File + * @version V1.0.2 + * @date 07. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. + * Copyright (c) 2018-2022 Arm China. + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_STAR_H_GENERIC +#define __CORE_STAR_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup STAR-MC1 + @{ + */ + +#include "cmsis_version.h" + +/* Macro Define for STAR-MC1 */ +#define __STAR_MC (1U) /*!< STAR-MC Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_STAR_H_DEPENDANT +#define __CORE_STAR_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __STAR_REV + #define __STAR_REV 0x0000U + #warning "__STAR_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group STAR-MC1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for STAR-MC1 processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +typedef struct +{ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ +}EMSS_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ +#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ + +#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ +#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ + + + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache line Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ +#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ + +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean line by Set-way Register Definitions */ +#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ +#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ + +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ +#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ + +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* ArmChina: Implementation Defined */ +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ +#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ + +#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ +#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ + +#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ +#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ + +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/** + \brief Software Reset + \details Initiates a system reset request to reset the CPU. + */ +__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ + SCB_AIRCR_SYSRESETREQ_Msk ); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/mpu_armv7.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/mpu_armv7.h new file mode 100644 index 000000000..d9eedf81a --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/mpu_armv8.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/mpu_armv8.h new file mode 100644 index 000000000..3de16efc8 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/pac_armv81.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/pac_armv81.h new file mode 100644 index 000000000..854b60a20 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/pac_armv81.h @@ -0,0 +1,206 @@ +/****************************************************************************** + * @file pac_armv81.h + * @brief CMSIS PAC key functions for Armv8.1-M PAC extension + * @version V1.0.0 + * @date 23. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/pmu_armv8.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/pmu_armv8.h new file mode 100644 index 000000000..f8f3d8935 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.1 + * @date 15. April 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/tz_context.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/tz_context.h new file mode 100644 index 000000000..0d09749f3 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/LICENSE.txt b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/LICENSE.txt new file mode 100644 index 000000000..8dada3eda --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. For the purposes of this definition, + "control" means (i) the power, direct or indirect, to cause the + direction or management of such entity, whether by contract or + otherwise, or (ii) ownership of fifty percent (50%) or more of the + outstanding shares, or (iii) beneficial ownership of such entity. + + "You" (or "Your") shall mean an individual or Legal Entity + exercising permissions granted by this License. + + "Source" form shall mean the preferred form for making modifications, + including but not limited to software source code, documentation + source, and configuration files. + + "Object" form shall mean any form resulting from mechanical + transformation or translation of a Source form, including but + not limited to compiled object code, generated documentation, + and conversions to other media types. + + "Work" shall mean the work of authorship, whether in Source or + Object form, made available under the License, as indicated by a + copyright notice that is included in or attached to the work + (an example is provided in the Appendix below). + + "Derivative Works" shall mean any work, whether in Source or Object + form, that is based on (or derived from) the Work and for which the + editorial revisions, annotations, elaborations, or other modifications + represent, as a whole, an original work of authorship. For the purposes + of this License, Derivative Works shall not include works that remain + separable from, or merely link (or bind by name) to the interfaces of, + the Work and Derivative Works thereof. + + "Contribution" shall mean any work of authorship, including + the original version of the Work and any modifications or additions + to that Work or Derivative Works thereof, that is intentionally + submitted to Licensor for inclusion in the Work by the copyright owner + or by an individual or Legal Entity authorized to submit on behalf of + the copyright owner. For the purposes of this definition, "submitted" + means any form of electronic, verbal, or written communication sent + to the Licensor or its representatives, including but not limited to + communication on electronic mailing lists, source code control systems, + and issue tracking systems that are managed by, or on behalf of, the + Licensor for the purpose of discussing and improving the Work, but + excluding communication that is conspicuously marked or otherwise + designated in writing by the copyright owner as "Not a Contribution." + + "Contributor" shall mean Licensor and any individual or Legal Entity + on behalf of whom a Contribution has been received by Licensor and + subsequently incorporated within the Work. + + 2. Grant of Copyright License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + copyright license to reproduce, prepare Derivative Works of, + publicly display, publicly perform, sublicense, and distribute the + Work and such Derivative Works in Source or Object form. + + 3. Grant of Patent License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + (except as stated in this section) patent license to make, have made, + use, offer to sell, sell, import, and otherwise transfer the Work, + where such license applies only to those patent claims licensable + by such Contributor that are necessarily infringed by their + Contribution(s) alone or by combination of their Contribution(s) + with the Work to which such Contribution(s) was submitted. If You + institute patent litigation against any entity (including a + cross-claim or counterclaim in a lawsuit) alleging that the Work + or a Contribution incorporated within the Work constitutes direct + or contributory patent infringement, then any patent licenses + granted to You under this License for that Work shall terminate + as of the date such litigation is filed. + + 4. Redistribution. You may reproduce and distribute copies of the + Work or Derivative Works thereof in any medium, with or without + modifications, and in Source or Object form, provided that You + meet the following conditions: + + (a) You must give any other recipients of the Work or + Derivative Works a copy of this License; and + + (b) You must cause any modified files to carry prominent notices + stating that You changed the files; and + + (c) You must retain, in the Source form of any Derivative Works + that You distribute, all copyright, patent, trademark, and + attribution notices from the Source form of the Work, + excluding those notices that do not pertain to any part of + the Derivative Works; and + + (d) If the Work includes a "NOTICE" text file as part of its + distribution, then any Derivative Works that You distribute must + include a readable copy of the attribution notices contained + within such NOTICE file, excluding those notices that do not + pertain to any part of the Derivative Works, in at least one + of the following places: within a NOTICE text file distributed + as part of the Derivative Works; within the Source form or + documentation, if provided along with the Derivative Works; or, + within a display generated by the Derivative Works, if and + wherever such third-party notices normally appear. The contents + of the NOTICE file are for informational purposes only and + do not modify the License. You may add Your own attribution + notices within Derivative Works that You distribute, alongside + or as an addendum to the NOTICE text from the Work, provided + that such additional attribution notices cannot be construed + as modifying the License. + + You may add Your own copyright statement to Your modifications and + may provide additional or different license terms and conditions + for use, reproduction, or distribution of Your modifications, or + for any such Derivative Works as a whole, provided Your use, + reproduction, and distribution of the Work otherwise complies with + the conditions stated in this License. + + 5. Submission of Contributions. Unless You explicitly state otherwise, + any Contribution intentionally submitted for inclusion in the Work + by You to the Licensor shall be under the terms and conditions of + this License, without any additional terms or conditions. + Notwithstanding the above, nothing herein shall supersede or modify + the terms of any separate license agreement you may have executed + with Licensor regarding such Contributions. + + 6. Trademarks. This License does not grant permission to use the trade + names, trademarks, service marks, or product names of the Licensor, + except as required for reasonable and customary use in describing the + origin of the Work and reproducing the content of the NOTICE file. + + 7. Disclaimer of Warranty. Unless required by applicable law or + agreed to in writing, Licensor provides the Work (and each + Contributor provides its Contributions) on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied, including, without limitation, any warranties or conditions + of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A + PARTICULAR PURPOSE. You are solely responsible for determining the + appropriateness of using or redistributing the Work and assume any + risks associated with Your exercise of permissions under this License. + + 8. Limitation of Liability. In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "{}" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright {yyyy} {name of copyright owner} + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h new file mode 100644 index 000000000..2d6d7715b --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -0,0 +1,4425 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +#if defined(STM32H7) || defined(STM32MP1) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#endif /* STM32H7 || STM32MP1 */ +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE +#endif /* STM32H5 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM + input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif + +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#if defined(STM32H5) || defined(STM32C0) +#else +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for + inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for + inter STM32 series compatibility */ +#endif +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ + defined(STM32F4) || defined(STM32G4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + +#endif /* STM32L4 */ + +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) +#define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) || defined(STM32C0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ +#if defined(STM32H7RS) +#define FLASH_OPTKEY1 FLASH_OPT_KEY1 +#define FLASH_OPTKEY2 FLASH_OPT_KEY2 +#endif /* STM32H7RS */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE +#endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ +#if defined(STM32H5) +#define FLASH_ECC_AREA_EDATA FLASH_ECC_AREA_EDATA_BANK1 +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ + +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ + + +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ + STM32H757xx */ +#endif /* STM32H7 */ + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ + defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ + +#if defined(STM32L1) +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 + +#if defined(STM32U5) || defined(STM32H5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 || STM32H5 */ +#if defined(STM32U5) +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB +#endif /* STM32U5 */ +#if defined(STM32H5) +#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB +#endif /* STM32H5 */ +#if defined(STM32H5) || defined(STM32U5) +#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX +#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED +#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED +#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC +#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC +#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV +#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV +#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF +#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON +#endif /* STM32H5 || STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) +#endif /* STM32F3 */ + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ + defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP + +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM +#endif /* STM32H5 || STM32H7RS || STM32N6 */ + +#if defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 +#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK +#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE +#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH +#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM +#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL +#endif /* STM32WBA */ + +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +#if defined(STM32F7) || defined(STM32WB) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 || STM32WB */ + +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ + +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB) +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */ + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP + +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP + +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +#if defined(STM32U5) || defined(STM32MP2) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to + the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from + MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus + or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status + of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and + transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input + frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control + de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control + activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status + (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and + status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose + * @{ + */ + +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ + +/** + * @} + */ + +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ + HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ + HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ + HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ + HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ + defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ + defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || + STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ + defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ +/** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP +#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP +#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP +#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP +#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP +#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP +#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP +#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP +#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP + + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP +#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP + + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN +#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey +#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock +#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock +#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ + defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ + defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ + HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ + } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ + HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ + } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ + HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \ + defined(STM32U0) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE + +#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE +#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI +#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI +#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE +#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 +#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 +#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 +#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 +#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE +#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM + +#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE +#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE +#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE +#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE +#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE +#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE +#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE +#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE +#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE +#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE + +#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE +#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE +#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE +#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE +#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG +#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG +#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG +#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE +#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE +#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE +#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE +#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG + +#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE +#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE +#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE +#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE +#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG + +#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE +#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE +#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE +#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE +#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG + +#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 +#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 +#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 +#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 + +#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE +#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM + +#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE +#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI +#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI +#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE + +#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 +#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 +#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 +#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 + +#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE +#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM + +#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE +#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI +#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI +#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE + + +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32WBA) || defined (STM32H5) || \ + defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV +#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV +#endif + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) || defined(STM32L5) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32F7) +#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE +#endif /* STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h new file mode 100644 index 000000000..a779890d0 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h @@ -0,0 +1,850 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32U5xx_HAL_H +#define __STM32U5xx_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_conf.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HAL_Exported_Types HAL Exported Types + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported variables --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup REV_ID device revision ID + * @{ + */ +#define REV_ID_A 0x1000U /*!< STM32U5 rev.A */ +#define REV_ID_B 0x2000U /*!< STM32U5 rev.B */ +/** + * @} + */ + + +/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants + * @{ + */ + +/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts + * @{ + */ +#define SYSCFG_IT_FPU_IOC SYSCFG_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ +#define SYSCFG_IT_FPU_DZC SYSCFG_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ +#define SYSCFG_IT_FPU_UFC SYSCFG_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ +#define SYSCFG_IT_FPU_OFC SYSCFG_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ +#define SYSCFG_IT_FPU_IDC SYSCFG_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ +#define SYSCFG_IT_FPU_IXC SYSCFG_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ + +/** + * @} + */ + +/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale + * @{ + */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREF_OUT3) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1) /*!< Voltage reference scale 3 (VREF_OUT4) */ + +/** + * @} + */ + +/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance + * @{ + */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to + Voltage reference buffer output */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ + +/** + * @} + */ + +/** @defgroup SYSCFG_flags_definition Flags + * @{ + */ + +#define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ +#define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ + +/** + * @} + */ + +/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO + * @{ + */ + +/** @brief Fast-mode Plus driving capability on a specific GPIO + */ +#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ +#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ +#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ +#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ +/** + * @} + */ + +#if defined(SYSCFG_CFGR1_ENDCAP) +/** @defgroup SYSCFG_DECOUPLING_CAPACITANCE SYSCFG DECOUPLING CAPACITANCE + * @{ + */ +#define SYSCFG_HSPI_CAPACITANCE_OFF 0x00000000U /*!< Decoupling with no capacitance value on HSPI supply */ +#define SYSCFG_HSPI_CAPACITANCE_1_DIV_3 SYSCFG_CFGR1_ENDCAP_0 /*!< Decoupling with 1/3 of capacitance value on HSPI supply */ +#define SYSCFG_HSPI_CAPACITANCE_2_DIV_3 SYSCFG_CFGR1_ENDCAP_1 /*!< Decoupling with 2/3 of capacitance value on HSPI supply */ +#define SYSCFG_HSPI_CAPACITANCE_FULL SYSCFG_CFGR1_ENDCAP /*!< Decoupling with full capacitance value on HSPI supply */ +/** + * @} + */ +#endif /* SYSCFG_CFGR1_ENDCAP */ + +/** @defgroup SYSCFG_Lock_items SYSCFG Lock items + * @brief SYSCFG items to set lock on + * @{ + */ +#define SYSCFG_MPU_NSEC SYSCFG_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or non-secure only) */ +#define SYSCFG_VTOR_NSEC SYSCFG_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or non-secure only) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU (SYSCFG_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */ +#define SYSCFG_MPU_SEC (SYSCFG_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only) */ +#define SYSCFG_VTOR_AIRCR_SEC (SYSCFG_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure code only) */ +#define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC|SYSCFG_SAU|SYSCFG_MPU_SEC|SYSCFG_VTOR_AIRCR_SEC) /*!< All */ +#else +#define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** @defgroup SYSCFG_Attributes_items SYSCFG Attributes items + * @brief SYSCFG items to configure secure or non-secure attributes on + * @{ + */ +#define SYSCFG_CLK SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock control */ +#define SYSCFG_CLASSB SYSCFG_SECCFGR_CLASSBSEC /*!< Class B */ +#define SYSCFG_FPU SYSCFG_SECCFGR_FPUSEC /*!< FPU */ +#define SYSCFG_ALL (SYSCFG_CLK | SYSCFG_CLASSB | SYSCFG_FPU) /*!< All */ +/** + * @} + */ + +/** @defgroup SYSCFG_attributes SYSCFG attributes + * @brief SYSCFG secure or non-secure attributes + * @{ + */ +#define SYSCFG_SEC 0x00000001U /*!< Secure attribute */ +#define SYSCFG_NSEC 0x00000000U /*!< Non-secure attribute */ +/** + * @} + */ + +#endif /* __ARM_FEATURE_CMSE */ + +#ifdef SYSCFG_OTGHSPHYCR_EN +/** @defgroup SYSCFG_OTG_PHY_RefenceClockSelection OTG PHY Reference Clock Selection + * @{ + */ + +/** @brief OTG HS PHY reference clock frequency selection + */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_1 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1) /*!< 16Mhz */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_2 SYSCFG_OTGHSPHYCR_CLKSEL_3 /*!< 19.2Mhz */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_3 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 20Mhz */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_4 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 24Mhz */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_5 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_2 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 26Mhz */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_6 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 32Mhz */ +/** + * @} + */ + +/** @defgroup SYSCFG_OTG_PHY_PowerDown OTG PHY Power Down + * @{ + */ + +/** @brief OTG HS PHY Power Down config + */ + +#define SYSCFG_OTG_HS_PHY_POWER_ON 0x00000000U /*!< PHY state machine, bias and OTG PHY PLL are powered down */ +#define SYSCFG_OTG_HS_PHY_POWER_DOWN SYSCFG_OTGHSPHYCR_PDCTRL /*!< PHY state machine, bias and OTG PHY PLL remain powered */ + +/** + * @} + */ + +/** @defgroup SYSCFG_OTG_PHY_Enable OTG PHY Enable + * @{ + */ + +#define SYSCFG_OTG_HS_PHY_UNDERRESET 0x00000000U /*!< PHY under reset */ +#define SYSCFG_OTG_HS_PHY_ENABLE SYSCFG_OTGHSPHYCR_EN /*!< PHY enabled */ + +/** + * @} + */ + +/** @defgroup SYSCFG_OTG_PHYTUNER_PreemphasisCurrent OTG PHYTUNER Preemphasis Current + * @{ + */ + +/** @brief High-speed (HS) transmitter preemphasis current control + */ +#define SYSCFG_OTG_HS_PHY_PREEMP_DISABLED 0x00000000U /*!< HS transmitter preemphasis circuit disabled */ +#define SYSCFG_OTG_HS_PHY_PREEMP_1X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */ +#define SYSCFG_OTG_HS_PHY_PREEMP_2X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */ +#define SYSCFG_OTG_HS_PHY_PREEMP_3X (SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1) /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */ + +/** + * @} + */ + +/** @defgroup SYSCFG_OTG_PHYTUNER_SquelchThreshold OTG PHYTUNER Squelch Threshold + * @{ + */ + +/** @brief Squelch threshold adjustment + */ +#define SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT 0x00000000U /*!< +15% (recommended value) */ +#define SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT (SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0 | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1) /*!< 0% (default value) */ + +/** + * @} + */ + +/** @defgroup SYSCFG_OTG_PHYTUNER_DisconnectThreshold OTG PHYTUNER Disconnect Threshold + * @{ + */ + +/** @brief Disconnect threshold adjustment + */ +#define SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1 /*!< +5.9% (recommended value) */ +#define SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0 /*!< 0% (default value) */ + +/** + * @} + */ + +#endif /* SYSCFG_OTGHSPHYCR_EN */ +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros + * @{ + */ + +/** @brief Freeze/Unfreeze Peripherals in Debug mode + */ +#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) +#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) +#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) +#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) +#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) +#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) +#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) +#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) +#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) +#define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) +#define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */ + +#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP) +#define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) +#endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */ + +#if defined(DBGMCU_APB1FZR2_DBG_I2C5_STOP) +#define __HAL_DBGMCU_FREEZE_I2C5() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C5_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C5() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C5_STOP) +#endif /* DBGMCU_APB1FZR2_DBG_I2C5_STOP */ + +#if defined(DBGMCU_APB1FZR2_DBG_I2C6_STOP) +#define __HAL_DBGMCU_FREEZE_I2C6() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C6_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C6() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C6_STOP) +#endif /* DBGMCU_APB1FZR2_DBG_I2C6_STOP */ + +#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) +#endif /* DBGMCU_APB1FZR2_DBG_LPTIM2_STOP */ + +#if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP) +#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) +#endif /* DBGMCU_APB2FZR_DBG_TIM1_STOP */ + +#if defined(DBGMCU_APB2FZR_DBG_TIM8_STOP) +#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) +#endif /* DBGMCU_APB2FZR_DBG_TIM8_STOP */ + +#if defined(DBGMCU_APB2FZR_DBG_TIM15_STOP) +#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) +#endif /* DBGMCU_APB2FZR_DBG_TIM15_STOP */ + +#if defined(DBGMCU_APB2FZR_DBG_TIM16_STOP) +#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) +#endif /* DBGMCU_APB2FZR_DBG_TIM16_STOP */ + +#if defined(DBGMCU_APB2FZR_DBG_TIM17_STOP) +#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) +#endif /* DBGMCU_APB2FZR_DBG_TIM17_STOP */ + +#if defined(DBGMCU_APB3FZR_DBG_I2C3_STOP) +#define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP) +#endif /* DBGMCU_APB3FZR_DBG_I2C3_STOP */ + +#if defined(DBGMCU_APB3FZR_DBG_LPTIM1_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP) +#endif /* DBGMCU_APB3FZR_DBG_LPTIM1_STOP */ + +#if defined(DBGMCU_APB3FZR_DBG_LPTIM3_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP) +#endif /* DBGMCU_APB3FZR_DBG_LPTIM3_STOP */ + +#if defined(DBGMCU_APB3FZR_DBG_LPTIM4_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP) +#endif /* DBGMCU_APB3FZR_DBG_LPTIM4_STOP */ + +#if defined(DBGMCU_APB3FZR_DBG_RTC_STOP) +#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP) +#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP) +#endif /* DBGMCU_APB3FZR_DBG_RTC_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA0_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA0_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA0_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA0_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA3_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA3_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA3_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA3_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA4_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA4_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA4_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA4_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA5_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA5_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA5_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA5_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA6_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA6_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA6_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA6_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA7_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA7_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA7_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA7_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA8_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA8_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA8_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA8_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA9_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA9_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA9_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA9_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA10_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA10_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA10_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA10_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA11_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA11_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA11_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA11_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA12_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA12() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA12_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA12() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA12_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA12_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA13_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA13() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA13_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA13() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA13_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA13_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA14_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA14() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA14_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA14() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA14_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA14_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA15_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA15() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA15_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA15() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA15_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA15_STOP */ + +#if defined(DBGMCU_AHB3FZR_DBG_LPDMA0_STOP) +#define __HAL_DBGMCU_FREEZE_LPDMA0() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA0_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPDMA0() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA0_STOP) +#endif /* DBGMCU_AHB3FZR_DBG_LPDMA0_STOP */ + +#if defined(DBGMCU_AHB3FZR_DBG_LPDMA1_STOP) +#define __HAL_DBGMCU_FREEZE_LPDMA1() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA1_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPDMA1() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA1_STOP) +#endif /* DBGMCU_AHB3FZR_DBG_LPDMA1_STOP */ + +#if defined(DBGMCU_AHB3FZR_DBG_LPDMA2_STOP) +#define __HAL_DBGMCU_FREEZE_LPDMA2() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA2_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPDMA2() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA2_STOP) +#endif /* DBGMCU_AHB3FZR_DBG_LPDMA2_STOP */ + +#if defined(DBGMCU_AHB3FZR_DBG_LPDMA3_STOP) +#define __HAL_DBGMCU_FREEZE_LPDMA3() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA3_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPDMA3() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA3_STOP) +#endif /* DBGMCU_AHB3FZR_DBG_LPDMA3_STOP */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros + * @{ + */ + +/** @brief Floating Point Unit interrupt enable/disable macros + * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts + */ +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ + SET_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ + }while(0) + +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ + CLEAR_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ + }while(0) + +/** @brief SYSCFG Break ECC lock. + * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) + +/** @brief SYSCFG Break Cortex-M33 Lockup lock. + * Enable and lock the connection of Cortex-M33 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) + +/** @brief SYSCFG Break PVD lock. + * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in + * the PWR_CR2 register. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) + +/** @brief SYSCFG Break SRAM2 parity lock. + * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. + * @note The selected configuration is locked and can be unlocked by system reset. + */ +#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) + +/** @brief Check SYSCFG flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag + * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\ + & (__FLAG__))!= 0) ? 1 : 0) + +/** @brief Set the SPF bit to clear the SRAM Parity Error Flag. + */ +#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) + +/** @brief Fast-mode Plus driving capability enable/disable macros + * @param __FASTMODEPLUS__: This parameter can be a value of : + * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 + * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 + * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 + * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 + */ +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) \ + do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ + }while(0) + +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) \ + do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ + }while(0) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros + * @{ + */ + +#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ + (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ + (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ + (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ + (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ + (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) + +#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ + ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ + ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ + ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) + +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ + ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \ + ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \ + ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3)) + +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ + ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) + +#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) + +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) + +#if defined(SYSCFG_CFGR1_ENDCAP) +#define IS_SYSCFG_DECOUPLING_CAPACITANCE(__CAPA__) (((__CAPA__) == SYSCFG_HSPI_CAPACITANCE_OFF) || \ + ((__CAPA__) == SYSCFG_HSPI_CAPACITANCE_1_DIV_3) || \ + ((__CAPA__) == SYSCFG_HSPI_CAPACITANCE_2_DIV_3) || \ + ((__CAPA__) == SYSCFG_HSPI_CAPACITANCE_FULL)) +#endif /* SYSCFG_CFGR1_ENDCAP */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_SYSCFG_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SYSCFG_SEC) ||\ + ((__ATTRIBUTES__) == SYSCFG_NSEC)) + +#define IS_SYSCFG_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SYSCFG_CLK) == SYSCFG_CLK) || \ + (((__ITEM__) & SYSCFG_CLASSB) == SYSCFG_CLASSB) || \ + (((__ITEM__) & SYSCFG_FPU) == SYSCFG_FPU) || \ + (((__ITEM__) & ~(SYSCFG_ALL)) == 0U)) + +#define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ + (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ + (((__ITEM__) & SYSCFG_SAU) == SYSCFG_SAU) || \ + (((__ITEM__) & SYSCFG_MPU_SEC) == SYSCFG_MPU_SEC) || \ + (((__ITEM__) & SYSCFG_VTOR_AIRCR_SEC) == SYSCFG_VTOR_AIRCR_SEC) || \ + (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) + +#else + +#define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ + (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ + (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) +#endif /* __ARM_FEATURE_CMSE */ + +#if defined SYSCFG_OTGHSPHYCR_EN +#define IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_1) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_2) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_3) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_4) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_5) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_6)) + +#define IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_DOWN) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_ON)) + +#define IS_SYSCFG_OTGPHY_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_UNDERRESET) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_ENABLE)) + +#define IS_SYSCFG_OTGPHY_DISCONNECT(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT)) + +#define IS_SYSCFG_OTGPHY_SQUELCH(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT)) + +#define IS_SYSCFG_OTGPHY_PREEMPHASIS(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_DISABLED) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_1X) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_2X) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_3X)) +#endif /* SYSCFG_OTGHSPHYCR_EN */ + +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @addtogroup HAL_Exported_Functions_Group1 HAL Initialization and de-initialization Functions + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group3 HAL Debug functions + * @{ + */ + +/* DBGMCU Peripheral Control functions *****************************************/ +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions + * @{ + */ + +/* SYSCFG Control functions ****************************************************/ +void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); +void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); +void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); +HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); +void HAL_SYSCFG_DisableVREFBUF(void); +#ifdef SYSCFG_OTGHSPHYCR_EN +void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClkSelection); +void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig); +void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig); +void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold); +void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold); +void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent); +#endif /* SYSCFG_OTGHSPHYCR_EN */ +void HAL_SYSCFG_EnableIOAnalogBooster(void); +void HAL_SYSCFG_DisableIOAnalogBooster(void); +void HAL_SYSCFG_EnableIOAnalogVoltageSelection(void); +void HAL_SYSCFG_DisableIOAnalogVoltageSelection(void); +#if defined(SYSCFG_CFGR1_ENDCAP) +void HAL_SYSCFG_SetHSPIDecouplingCapacitance(uint32_t Capacitance); +uint32_t HAL_SYSCFG_GetHSPIDecouplingCapacitance(void); +#endif /* SYSCFG_CFGR1_ENDCAP */ +void HAL_SYSCFG_EnableSRAMCached(void); +void HAL_SYSCFG_DisableSRAMCached(void); +void HAL_SYSCFG_EnableVddCompensationCell(void); +void HAL_SYSCFG_EnableVddIO2CompensationCell(void); +#if defined(SYSCFG_CCCSR_EN3) +void HAL_SYSCFG_EnableVddHSPICompensationCell(void); +#endif /* SYSCFG_CCCSR_EN3 */ +void HAL_SYSCFG_DisableVddCompensationCell(void); +void HAL_SYSCFG_DisableVddIO2CompensationCell(void); +#if defined(SYSCFG_CCCSR_EN3) +void HAL_SYSCFG_DisableVddHSPICompensationCell(void); +#endif /* SYSCFG_CCCSR_EN3 */ +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group5 HAL SYSCFG lock management functions + * @{ + */ + +/* SYSCFG Lock functions ********************************************/ +void HAL_SYSCFG_Lock(uint32_t Item); +HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem); + +/** + * @} + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** @addtogroup HAL_Exported_Functions_Group6 HAL SYSCFG attributes management functions + * @{ + */ + +/* SYSCFG Attributes functions ********************************************/ +void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes); +HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); + +/** + * @} + */ + +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32U5xx_HAL_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h new file mode 100644 index 000000000..3c5bd145d --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h @@ -0,0 +1,391 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32U5xx_HAL_CORTEX_H +#define __STM32U5xx_HAL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types CORTEX Exported Types + * @{ + */ + +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the index of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */ + uint8_t AttributesIndex; /*!< Specifies the memory attributes index. + This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter + can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ +} MPU_Region_InitTypeDef; +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes + * Initialization Structure Definition + * @{ + */ +typedef struct +{ + uint8_t Number; /*!< Specifies the number of the memory attributes to configure. + This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ + + uint8_t Attributes; /*!< Specifies the memory attributes value. Attributes This parameter + can be a combination of @ref CORTEX_MPU_Attributes */ + +} MPU_Attributes_InitTypeDef; +/** + * @} + */ + + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ +#define NVIC_PRIORITYGROUP_0 0x7U /*!< 0 bit for pre-emption priority, + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x6U /*!< 1 bit for pre-emption priority, + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x5U /*!< 2 bits for pre-emption priority, + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x4U /*!< 3 bits for pre-emption priority, + 1 bit for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x3U /*!< 4 bits for pre-emption priority, + 0 bit for subpriority */ +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x0U /*!< AHB clock divided by 8 selected as SysTick clock source */ +#define SYSTICK_CLKSOURCE_LSI 0x1U /*!< LSI clock selected as SysTick clock source */ +#define SYSTICK_CLKSOURCE_LSE 0x2U /*!< LSE clock selected as SysTick clock source */ +#define SYSTICK_CLKSOURCE_HCLK 0x4U /*!< AHB clock selected as SysTick clock source */ +/** + * @} + */ + +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE 1U /*!< Enable region */ +#define MPU_REGION_DISABLE 0U /*!< Disable region */ +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< Execute attribute */ +#define MPU_INSTRUCTION_ACCESS_DISABLE 1U /*!< Execute never attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_NOT_SHAREABLE 0U /*!< Not shareable attribute */ +#define MPU_ACCESS_OUTER_SHAREABLE 2U /*!< Outer shareable attribute */ +#define MPU_ACCESS_INNER_SHAREABLE 3U /*!< Inner shareable attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_PRIV_RW 0U /*!< Read/write privileged-only attribute */ +#define MPU_REGION_ALL_RW 1U /*!< Read/write privileged/unprivileged attribute */ +#define MPU_REGION_PRIV_RO 2U /*!< Read-only privileged-only attribute */ +#define MPU_REGION_ALL_RO 3U /*!< Read-only privileged/unprivileged attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 0U +#define MPU_REGION_NUMBER1 1U +#define MPU_REGION_NUMBER2 2U +#define MPU_REGION_NUMBER3 3U +#define MPU_REGION_NUMBER4 4U +#define MPU_REGION_NUMBER5 5U +#define MPU_REGION_NUMBER6 6U +#define MPU_REGION_NUMBER7 7U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number + * @{ + */ +#define MPU_ATTRIBUTES_NUMBER0 0U +#define MPU_ATTRIBUTES_NUMBER1 1U +#define MPU_ATTRIBUTES_NUMBER2 2U +#define MPU_ATTRIBUTES_NUMBER3 3U +#define MPU_ATTRIBUTES_NUMBER4 4U +#define MPU_ATTRIBUTES_NUMBER5 5U +#define MPU_ATTRIBUTES_NUMBER6 6U +#define MPU_ATTRIBUTES_NUMBER7 7U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes + * @{ + */ +/* Device memory attributes */ +#define MPU_DEVICE_NGNRNE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ +#define MPU_DEVICE_NGNRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ +#define MPU_DEVICE_NGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ +#define MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ + +/* Normal memory attributes */ +/* To set with INNER_OUTER() macro for both inner/outer cache attributes */ + +/* Non-cacheable memory attribute */ +#define MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable */ + +/* Cacheable memory attributes: combination of cache write policy, transient and allocation */ +/* - cache write policy */ +#define MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through */ +#define MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back */ +/* - transient mode attribute */ +#define MPU_TRANSIENT 0x0U /*!< Normal memory, transient */ +#define MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient */ +/* - allocation attribute */ +#define MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate */ +#define MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate */ +#define MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate */ +#define MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros + * @{ + */ +#define OUTER(__ATTR__) ((__ATTR__) << 4U) +#define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and Configuration functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * @{ + */ +/* Peripheral Control functions ***********************************************/ +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, + uint32_t *const pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +uint32_t HAL_SYSTICK_GetCLKSourceConfig(void); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); + +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit); +void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* MPU_NS Control functions ***********************************************/ +void HAL_MPU_Enable_NS(uint32_t MPU_Control); +void HAL_MPU_Disable_NS(void); +void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber); +void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber); +void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit); +void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ + ((GROUP) == NVIC_PRIORITYGROUP_1) || \ + ((GROUP) == NVIC_PRIORITYGROUP_2) || \ + ((GROUP) == NVIC_PRIORITYGROUP_3) || \ + ((GROUP) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_LSI) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_LSE) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK)|| \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_MPU_INSTANCE(INSTANCE) (((INSTANCE) == MPU) || ((INSTANCE) == MPU_NS)) +#endif /* __ARM_FEATURE_CMSE */ + +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_ALL_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_ALL_RO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#define IS_MPU_ATTRIBUTES_NUMBER(NUMBER) (((NUMBER) == MPU_ATTRIBUTES_NUMBER0) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER1) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER2) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER3) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER4) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER5) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER6) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER7)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32U5xx_HAL_CORTEX_H */ + + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_def.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_def.h new file mode 100644 index 000000000..5fac6913c --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_def.h @@ -0,0 +1,229 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32U5xx_HAL_DEF +#define __STM32U5xx_HAL_DEF + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#include +#endif /* __ARM_FEATURE_CMSE */ + +#include "stm32u5xx.h" +#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ +#include +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00, + HAL_ERROR = 0x01, + HAL_BUSY = 0x02, + HAL_TIMEOUT = 0x03 +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00, + HAL_LOCKED = 0x01 +} HAL_LockTypeDef; + +/* Exported macros -----------------------------------------------------------*/ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0) + +#if !defined(UNUSED) +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ +#endif /* UNUSED */ + +/** @brief Reset the Handle's State field. + * @param __HANDLE__: specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) + +#if (USE_RTOS == 1) +/* Reserved for future use */ +#error " USE_RTOS should be 0 in the current HAL release " +#else +#define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0) + +#define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0) +#endif /* USE_RTOS */ + +#if defined ( __GNUC__ ) +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __GNUC__ */ + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((packed)) +#endif /* __packed */ +#endif /* __ARMCC_VERSION */ + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used + instead */ +#if defined (__GNUC__) /* GNU Compiler */ +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4))) +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#ifndef __ALIGN_END +#define __ALIGN_END __ALIGNED(4) +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ +#else +#ifndef __ALIGN_END +#define __ALIGN_END +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#if defined (__CC_ARM) /* ARM Compiler */ +#define __ALIGN_BEGIN __align(4) +#elif defined (__ICCARM__) /* IAR Compiler */ +#define __ALIGN_BEGIN +#endif /* __CC_ARM */ +#endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */ +#if defined (__GNUC__) /* GNU Compiler */ +#define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32))) +#elif defined (__ICCARM__) /* IAR Compiler */ +#define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define ALIGN_32BYTES(buf) __ALIGNED(32) buf +#elif defined (__CC_ARM) /* ARM Compiler */ +#define ALIGN_32BYTES(buf) __align(32) buf +#endif /* __GNUC__ */ + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + +/* ARM Compiler + ------------ + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC HAL_StatusTypeDef + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc HAL_StatusTypeDef + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc"))) + +#endif /* __RAM_FUNC */ + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM & GNUCompiler + ---------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif /* __NOINLINE */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32U5xx_HAL_DEF */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h new file mode 100644 index 000000000..a15d4fe8c --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h @@ -0,0 +1,932 @@ +/** + ********************************************************************************************************************** + * @file stm32u5xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32U5xx_HAL_DMA_H +#define STM32U5xx_HAL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + + +/* Exported types ----------------------------------------------------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Types DMA Exported Types + * @brief DMA Exported Types + * @{ + */ + +/** + * @brief DMA Transfer Configuration Structure definition. + */ +typedef struct +{ + uint32_t Request; /*!< Specifies the DMA channel request. + This parameter can be a value of @ref DMA_Request_Selection */ + + uint32_t BlkHWRequest; /*!< Specifies the Block hardware request mode for DMA channel. + Block Hardware request feature can be used only with dedicated peripherals. + This parameter can be a value of @ref DMA_Block_Request */ + + uint32_t Direction; /*!< Specifies the transfer direction for DMA channel. + This parameter can be a value of @ref DMA_Transfer_Direction */ + + uint32_t SrcInc; /*!< Specifies the source increment mode for the DMA channel. + This parameter can be a value of @ref DMA_Source_Increment_Mode */ + + uint32_t DestInc; /*!< Specifies the destination increment mode for the DMA channel. + This parameter can be a value of @ref DMA_Destination_Increment_Mode */ + + uint32_t SrcDataWidth; /*!< Specifies the source data width for the DMA channel. + This parameter can be a value of @ref DMA_Source_Data_Width */ + + uint32_t DestDataWidth; /*!< Specifies the destination data width for the DMA channel. + This parameter can be a value of @ref DMA_Destination_Data_Width */ + + uint32_t Priority; /*!< Specifies the priority level for the DMA channel. + This parameter can be a value of @ref DMA_Priority_Level */ + + uint32_t SrcBurstLength; /*!< Specifies the source burst length (number of beats within a burst) for the DMA + channel. + This parameter can be a value between 1 and 64 */ + + uint32_t DestBurstLength; /*!< Specifies the destination burst length (number of beats within a burst) for the + DMA channel. + This parameter can be a value between 1 and 64 */ + + uint32_t TransferAllocatedPort; /*!< Specifies the transfer allocated ports. + This parameter can be a combination of @ref DMA_Transfer_Allocated_Port */ + + uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. + This parameter can be a value of @ref DMA_Transfer_Event_Mode */ + + uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel. + This parameter can be a value of @ref DMA_Transfer_Mode */ + +} DMA_InitTypeDef; + +/** + * @brief DMA Linked-List Configuration Structure Definition. + */ +typedef struct +{ + uint32_t Priority; /*!< Specifies the priority level for the DMA channel. + This parameter can be a value of @ref DMA_Priority_Level */ + + uint32_t LinkStepMode; /*!< Specifies the link step mode for the DMA channel. + This parameter can be a value of @ref DMAEx_Link_Step_Mode */ + + uint32_t LinkAllocatedPort; /*!< Specifies the linked-list allocated port for the DMA channel. + This parameter can be a value of @ref DMAEx_Link_Allocated_Port */ + + uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. + This parameter can be a value of @ref DMA_Transfer_Event_Mode */ + + uint32_t LinkedListMode; /*!< Specifies linked-list transfer mode for the DMA channel. + This parameter can be a value of @ref DMAEx_LinkedList_Mode */ + +} DMA_InitLinkedListTypeDef; + +/** + * @brief HAL DMA State Enumeration Definition. + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */ + HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */ + HAL_DMA_STATE_SUSPEND = 0x05U, /*!< DMA Suspend state */ + +} HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Level Complete Enumeration Definition. + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full channel transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half channel transfer */ + +} HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Callbacks IDs Enumeration Definition. + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Complete transfer callback ID */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half complete transfer callback ID */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error transfer callback ID */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort transfer callback ID */ + HAL_DMA_XFER_SUSPEND_CB_ID = 0x04U, /*!< Suspend transfer callback ID */ + HAL_DMA_XFER_ALL_CB_ID = 0x05U /*!< All callback ID */ + +} HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Channel_TypeDef *Instance; /*!< Register the DMA channel base address */ + + DMA_InitTypeDef Init; /*!< DMA channel init parameters */ + + DMA_InitLinkedListTypeDef InitLinkedList; /*!< DMA channel linked-list init parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + uint32_t Mode; /*!< DMA transfer mode */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + __IO uint32_t ErrorCode; /*!< DMA error code */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA half transfer complete callback */ + + void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Abort callback */ + + void (* XferSuspendCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Suspend callback */ + + struct __DMA_QListTypeDef *LinkedListQueue; /*!< DMA linked-list queue */ + +} DMA_HandleTypeDef; +/** + * @} + */ + + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @brief DMA Exported constants + * @{ + */ + +/** @defgroup DMA_Error_Codes DMA Error Codes + * @brief DMA Error Codes + * @{ + */ +#define HAL_DMA_ERROR_NONE (0x0000U) /*!< No error */ +#define HAL_DMA_ERROR_DTE (0x0001U) /*!< Data transfer error */ +#define HAL_DMA_ERROR_ULE (0x0002U) /*!< Update linked-list item error */ +#define HAL_DMA_ERROR_USE (0x0004U) /*!< User setting error */ +#define HAL_DMA_ERROR_TO (0x0008U) /*!< Trigger overrun error */ +#define HAL_DMA_ERROR_TIMEOUT (0x0010U) /*!< Timeout error */ +#define HAL_DMA_ERROR_NO_XFER (0x0020U) /*!< No transfer ongoing error */ +#define HAL_DMA_ERROR_BUSY (0x0040U) /*!< Busy error */ +#define HAL_DMA_ERROR_INVALID_CALLBACK (0x0080U) /*!< Invalid callback error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED (0x0100U) /*!< Not supported mode */ +/** + * @} + */ + +/** @defgroup DMA_Interrupt_Enable_Definition DMA Interrupt Enable Definition + * @brief DMA Interrupt Enable Definition + * @{ + */ +#define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer complete interrupt */ +#define DMA_IT_HT DMA_CCR_HTIE /*!< Half transfer complete interrupt */ +#define DMA_IT_DTE DMA_CCR_DTEIE /*!< Data transfer error interrupt */ +#define DMA_IT_ULE DMA_CCR_ULEIE /*!< Update linked-list item error interrupt */ +#define DMA_IT_USE DMA_CCR_USEIE /*!< User eetting error interrupt */ +#define DMA_IT_SUSP DMA_CCR_SUSPIE /*!< Completed suspension interrupt */ +#define DMA_IT_TO DMA_CCR_TOIE /*!< Trigger overrun interrupt */ +/** + * @} + */ + +/** @defgroup DMA_Flag_Definition DMA Flag Definition + * @brief DMA Flag Definition + * @{ + */ +#define DMA_FLAG_IDLE DMA_CSR_IDLEF /*!< Idle flag */ +#define DMA_FLAG_TC DMA_CSR_TCF /*!< Transfer complete flag */ +#define DMA_FLAG_HT DMA_CSR_HTF /*!< Half transfer complete flag */ +#define DMA_FLAG_DTE DMA_CSR_DTEF /*!< Data transfer error flag */ +#define DMA_FLAG_ULE DMA_CSR_ULEF /*!< Update linked-list item error flag */ +#define DMA_FLAG_USE DMA_CSR_USEF /*!< User setting error flag */ +#define DMA_FLAG_SUSP DMA_CSR_SUSPF /*!< Completed suspension flag */ +#define DMA_FLAG_TO DMA_CSR_TOF /*!< Trigger overrun flag */ +/** + * @} + */ + +/** @defgroup DMA_Request_Selection DMA Request Selection + * @brief DMA Request Selection + * @{ + */ +/* GPDMA1 requests */ +#define GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW request is ADC1 */ +#define GPDMA1_REQUEST_ADC4 1U /*!< GPDMA1 HW request is ADC4 */ +#define GPDMA1_REQUEST_DAC1_CH1 2U /*!< GPDMA1 HW request is DAC1_CH1 */ +#define GPDMA1_REQUEST_DAC1_CH2 3U /*!< GPDMA1 HW request is DAC1_CH2 */ +#define GPDMA1_REQUEST_TIM6_UP 4U /*!< GPDMA1 HW request is TIM6_UP */ +#define GPDMA1_REQUEST_TIM7_UP 5U /*!< GPDMA1 HW request is TIM7_UP */ +#define GPDMA1_REQUEST_SPI1_RX 6U /*!< GPDMA1 HW request is SPI1_RX */ +#define GPDMA1_REQUEST_SPI1_TX 7U /*!< GPDMA1 HW request is SPI1_TX */ +#define GPDMA1_REQUEST_SPI2_RX 8U /*!< GPDMA1 HW request is SPI2_RX */ +#define GPDMA1_REQUEST_SPI2_TX 9U /*!< GPDMA1 HW request is SPI2_TX */ +#define GPDMA1_REQUEST_SPI3_RX 10U /*!< GPDMA1 HW request is SPI3_RX */ +#define GPDMA1_REQUEST_SPI3_TX 11U /*!< GPDMA1 HW request is SPI3_TX */ +#define GPDMA1_REQUEST_I2C1_RX 12U /*!< GPDMA1 HW request is I2C1_RX */ +#define GPDMA1_REQUEST_I2C1_TX 13U /*!< GPDMA1 HW request is I2C1_TX */ +#define GPDMA1_REQUEST_I2C1_EVC 14U /*!< GPDMA1 HW request is I2C1_EVC */ +#define GPDMA1_REQUEST_I2C2_RX 15U /*!< GPDMA1 HW request is I2C2_RX */ +#define GPDMA1_REQUEST_I2C2_TX 16U /*!< GPDMA1 HW request is I2C2_TX */ +#define GPDMA1_REQUEST_I2C2_EVC 17U /*!< GPDMA1 HW request is I2C2_EVC */ +#define GPDMA1_REQUEST_I2C3_RX 18U /*!< GPDMA1 HW request is I2C3_RX */ +#define GPDMA1_REQUEST_I2C3_TX 19U /*!< GPDMA1 HW request is I2C3_TX */ +#define GPDMA1_REQUEST_I2C3_EVC 20U /*!< GPDMA1 HW request is I2C3_EVC */ +#define GPDMA1_REQUEST_I2C4_RX 21U /*!< GPDMA1 HW request is I2C4_RX */ +#define GPDMA1_REQUEST_I2C4_TX 22U /*!< GPDMA1 HW request is I2C4_TX */ +#define GPDMA1_REQUEST_I2C4_EVC 23U /*!< GPDMA1 HW request is I2C4_EVC */ +#define GPDMA1_REQUEST_USART1_RX 24U /*!< GPDMA1 HW request is USART1_RX */ +#define GPDMA1_REQUEST_USART1_TX 25U /*!< GPDMA1 HW request is USART1_TX */ +#if defined(USART2) +#define GPDMA1_REQUEST_USART2_RX 26U /*!< GPDMA1 HW request is USART2_RX */ +#define GPDMA1_REQUEST_USART2_TX 27U /*!< GPDMA1 HW request is USART2_TX */ +#endif /* USART2 */ +#define GPDMA1_REQUEST_USART3_RX 28U /*!< GPDMA1 HW request is USART3_RX */ +#define GPDMA1_REQUEST_USART3_TX 29U /*!< GPDMA1 HW request is USART3_TX */ +#define GPDMA1_REQUEST_UART4_RX 30U /*!< GPDMA1 HW request is UART4_RX */ +#define GPDMA1_REQUEST_UART4_TX 31U /*!< GPDMA1 HW request is UART4_TX */ +#define GPDMA1_REQUEST_UART5_RX 32U /*!< GPDMA1 HW request is UART5_RX */ +#define GPDMA1_REQUEST_UART5_TX 33U /*!< GPDMA1 HW request is UART5_TX */ +#define GPDMA1_REQUEST_LPUART1_RX 34U /*!< GPDMA1 HW request is LPUART1_RX */ +#define GPDMA1_REQUEST_LPUART1_TX 35U /*!< GPDMA1 HW request is LPUART1_TX */ +#define GPDMA1_REQUEST_SAI1_A 36U /*!< GPDMA1 HW request is SAI1_A */ +#define GPDMA1_REQUEST_SAI1_B 37U /*!< GPDMA1 HW request is SAI1_B */ +#if defined(SAI2) +#define GPDMA1_REQUEST_SAI2_A 38U /*!< GPDMA1 HW request is SAI2_A */ +#define GPDMA1_REQUEST_SAI2_B 39U /*!< GPDMA1 HW request is SAI2_B */ +#endif /* SAI2 */ +#define GPDMA1_REQUEST_OCTOSPI1 40U /*!< GPDMA1 HW request is OCTOSPI1 */ +#if defined(OCTOSPI2) +#define GPDMA1_REQUEST_OCTOSPI2 41U /*!< GPDMA1 HW request is OCTOSPI2 */ +#endif /* OCTOSPI2 */ +#define GPDMA1_REQUEST_TIM1_CH1 42U /*!< GPDMA1 HW request is TIM1_CH1 */ +#define GPDMA1_REQUEST_TIM1_CH2 43U /*!< GPDMA1 HW request is TIM1_CH2 */ +#define GPDMA1_REQUEST_TIM1_CH3 44U /*!< GPDMA1 HW request is TIM1_CH3 */ +#define GPDMA1_REQUEST_TIM1_CH4 45U /*!< GPDMA1 HW request is TIM1_CH4 */ +#define GPDMA1_REQUEST_TIM1_UP 46U /*!< GPDMA1 HW request is TIM1_UP */ +#define GPDMA1_REQUEST_TIM1_TRIG 47U /*!< GPDMA1 HW request is TIM1_TRIG */ +#define GPDMA1_REQUEST_TIM1_COM 48U /*!< GPDMA1 HW request is TIM1_COM */ +#define GPDMA1_REQUEST_TIM8_CH1 49U /*!< GPDMA1 HW request is TIM8_CH1 */ +#define GPDMA1_REQUEST_TIM8_CH2 50U /*!< GPDMA1 HW request is TIM8_CH2 */ +#define GPDMA1_REQUEST_TIM8_CH3 51U /*!< GPDMA1 HW request is TIM8_CH3 */ +#define GPDMA1_REQUEST_TIM8_CH4 52U /*!< GPDMA1 HW request is TIM8_CH4 */ +#define GPDMA1_REQUEST_TIM8_UP 53U /*!< GPDMA1 HW request is TIM8_UP */ +#define GPDMA1_REQUEST_TIM8_TRIG 54U /*!< GPDMA1 HW request is TIM8_TRIG */ +#define GPDMA1_REQUEST_TIM8_COM 55U /*!< GPDMA1 HW request is TIM8_COM */ +#define GPDMA1_REQUEST_TIM2_CH1 56U /*!< GPDMA1 HW request is TIM2_CH1 */ +#define GPDMA1_REQUEST_TIM2_CH2 57U /*!< GPDMA1 HW request is TIM2_CH2 */ +#define GPDMA1_REQUEST_TIM2_CH3 58U /*!< GPDMA1 HW request is TIM2_CH3 */ +#define GPDMA1_REQUEST_TIM2_CH4 59U /*!< GPDMA1 HW request is TIM2_CH4 */ +#define GPDMA1_REQUEST_TIM2_UP 60U /*!< GPDMA1 HW request is TIM2_UP */ +#define GPDMA1_REQUEST_TIM3_CH1 61U /*!< GPDMA1 HW request is TIM3_CH1 */ +#define GPDMA1_REQUEST_TIM3_CH2 62U /*!< GPDMA1 HW request is TIM3_CH2 */ +#define GPDMA1_REQUEST_TIM3_CH3 63U /*!< GPDMA1 HW request is TIM3_CH3 */ +#define GPDMA1_REQUEST_TIM3_CH4 64U /*!< GPDMA1 HW request is TIM3_CH4 */ +#define GPDMA1_REQUEST_TIM3_UP 65U /*!< GPDMA1 HW request is TIM3_UP */ +#define GPDMA1_REQUEST_TIM3_TRIG 66U /*!< GPDMA1 HW request is TIM3_TRIG */ +#define GPDMA1_REQUEST_TIM4_CH1 67U /*!< GPDMA1 HW request is TIM4_CH1 */ +#define GPDMA1_REQUEST_TIM4_CH2 68U /*!< GPDMA1 HW request is TIM4_CH2 */ +#define GPDMA1_REQUEST_TIM4_CH3 69U /*!< GPDMA1 HW request is TIM4_CH3 */ +#define GPDMA1_REQUEST_TIM4_CH4 70U /*!< GPDMA1 HW request is TIM4_CH4 */ +#define GPDMA1_REQUEST_TIM4_UP 71U /*!< GPDMA1 HW request is TIM4_UP */ +#define GPDMA1_REQUEST_TIM5_CH1 72U /*!< GPDMA1 HW request is TIM5_CH1 */ +#define GPDMA1_REQUEST_TIM5_CH2 73U /*!< GPDMA1 HW request is TIM5_CH2 */ +#define GPDMA1_REQUEST_TIM5_CH3 74U /*!< GPDMA1 HW request is TIM5_CH3 */ +#define GPDMA1_REQUEST_TIM5_CH4 75U /*!< GPDMA1 HW request is TIM5_CH4 */ +#define GPDMA1_REQUEST_TIM5_UP 76U /*!< GPDMA1 HW request is TIM5_UP */ +#define GPDMA1_REQUEST_TIM5_TRIG 77U /*!< GPDMA1 HW request is TIM5_TRIG */ +#define GPDMA1_REQUEST_TIM15_CH1 78U /*!< GPDMA1 HW request is TIM15_CH1 */ +#define GPDMA1_REQUEST_TIM15_UP 79U /*!< GPDMA1 HW request is TIM15_UP */ +#define GPDMA1_REQUEST_TIM15_TRIG 80U /*!< GPDMA1 HW request is TIM15_TRIG */ +#define GPDMA1_REQUEST_TIM15_COM 81U /*!< GPDMA1 HW request is TIM15_COM */ +#define GPDMA1_REQUEST_TIM16_CH1 82U /*!< GPDMA1 HW request is TIM16_CH1 */ +#define GPDMA1_REQUEST_TIM16_UP 83U /*!< GPDMA1 HW request is TIM16_UP */ +#define GPDMA1_REQUEST_TIM17_CH1 84U /*!< GPDMA1 HW request is TIM17_CH1 */ +#define GPDMA1_REQUEST_TIM17_UP 85U /*!< GPDMA1 HW request is TIM17_UP */ +#define GPDMA1_REQUEST_DCMI_PSSI 86U /*!< GPDMA1 HW request is DCMI_PSSI */ +#define GPDMA1_REQUEST_AES_IN 87U /*!< GPDMA1 HW request is AES_IN */ +#define GPDMA1_REQUEST_AES_OUT 88U /*!< GPDMA1 HW request is AES_OUT */ +#define GPDMA1_REQUEST_HASH_IN 89U /*!< GPDMA1 HW request is HASH_IN */ +#if defined(UCPD1) +#define GPDMA1_REQUEST_UCPD1_TX 90U /*!< GPDMA1 HW request is UCPD1_TX */ +#define GPDMA1_REQUEST_UCPD1_RX 91U /*!< GPDMA1 HW request is UCPD1_RX */ +#endif /* UCPD1 */ +#define GPDMA1_REQUEST_MDF1_FLT0 92U /*!< GPDMA1 HW request is MDF1_FLT0 */ +#define GPDMA1_REQUEST_MDF1_FLT1 93U /*!< GPDMA1 HW request is MDF1_FLT1 */ +#define GPDMA1_REQUEST_MDF1_FLT2 94U /*!< GPDMA1 HW request is MDF1_FLT2 */ +#define GPDMA1_REQUEST_MDF1_FLT3 95U /*!< GPDMA1 HW request is MDF1_FLT3 */ +#define GPDMA1_REQUEST_MDF1_FLT4 96U /*!< GPDMA1 HW request is MDF1_FLT4 */ +#define GPDMA1_REQUEST_MDF1_FLT5 97U /*!< GPDMA1 HW request is MDF1_FLT5 */ +#define GPDMA1_REQUEST_ADF1_FLT0 98U /*!< GPDMA1 HW request is ADF1_FLT0 */ +#define GPDMA1_REQUEST_FMAC_READ 99U /*!< GPDMA1 HW request is FMAC_READ */ +#define GPDMA1_REQUEST_FMAC_WRITE 100U /*!< GPDMA1 HW request is FMAC_WRITE */ +#define GPDMA1_REQUEST_CORDIC_READ 101U /*!< GPDMA1 HW request is CORDIC_READ */ +#define GPDMA1_REQUEST_CORDIC_WRITE 102U /*!< GPDMA1 HW request is CORDIC_WRITE */ +#define GPDMA1_REQUEST_SAES_IN 103U /*!< GPDMA1 HW request is SAES_IN */ +#define GPDMA1_REQUEST_SAES_OUT 104U /*!< GPDMA1 HW request is SAES_OUT */ +#define GPDMA1_REQUEST_LPTIM1_IC1 105U /*!< GPDMA1 HW request is LPTIM1_IC1 */ +#define GPDMA1_REQUEST_LPTIM1_IC2 106U /*!< GPDMA1 HW request is LPTIM1_IC2 */ +#define GPDMA1_REQUEST_LPTIM1_UE 107U /*!< GPDMA1 HW request is LPTIM1_UE */ +#define GPDMA1_REQUEST_LPTIM2_IC1 108U /*!< GPDMA1 HW request is LPTIM2_IC1 */ +#define GPDMA1_REQUEST_LPTIM2_IC2 109U /*!< GPDMA1 HW request is LPTIM2_IC2 */ +#define GPDMA1_REQUEST_LPTIM2_UE 110U /*!< GPDMA1 HW request is LPTIM2_UE */ +#define GPDMA1_REQUEST_LPTIM3_IC1 111U /*!< GPDMA1 HW request is LPTIM3_IC1 */ +#define GPDMA1_REQUEST_LPTIM3_IC2 112U /*!< GPDMA1 HW request is LPTIM3_IC2 */ +#define GPDMA1_REQUEST_LPTIM3_UE 113U /*!< GPDMA1 HW request is LPTIM3_UE */ +#if defined (HSPI1_BASE) +#define GPDMA1_REQUEST_HSPI1 114U /*!< GPDMA1 HW request is HSPI1 */ +#endif /* HSPI1_BASE */ +#if defined (I2C5) +#define GPDMA1_REQUEST_I2C5_RX 115U /*!< GPDMA1 HW request is I2C5_RX */ +#define GPDMA1_REQUEST_I2C5_TX 116U /*!< GPDMA1 HW request is I2C5_TX */ +#define GPDMA1_REQUEST_I2C5_EVC 117U /*!< GPDMA1 HW request is I2C5_EVC */ +#endif /* I2C5 */ +#if defined (I2C6) +#define GPDMA1_REQUEST_I2C6_RX 118U /*!< GPDMA1 HW request is I2C6_RX */ +#define GPDMA1_REQUEST_I2C6_TX 119U /*!< GPDMA1 HW request is I2C6_TX */ +#define GPDMA1_REQUEST_I2C6_EVC 120U /*!< GPDMA1 HW request is I2C6_EVC */ +#endif /* I2C6 */ +#if defined (USART6) +#define GPDMA1_REQUEST_USART6_RX 121U /*!< GPDMA1 HW request is USART6_RX */ +#define GPDMA1_REQUEST_USART6_TX 122U /*!< GPDMA1 HW request is USART6_TX */ +#endif /* USART6 */ +#if defined (ADC2) +#define GPDMA1_REQUEST_ADC2 123U /*!< GPDMA1 HW request is ADC2 */ +#endif /* ADC2 */ +#if defined (JPEG) +#define GPDMA1_REQUEST_JPEG_RX 124U /*!< GPDMA1 HW request is JPEG_TX */ +#define GPDMA1_REQUEST_JPEG_TX 125U /*!< GPDMA1 HW request is JPEG_RX */ +#endif /* JPEG */ + +/* LPDMA1 requests */ +#define LPDMA1_REQUEST_LPUART1_RX 0U /*!< LPDMA1 HW request is LPUART1_RX */ +#define LPDMA1_REQUEST_LPUART1_TX 1U /*!< LPDMA1 HW request is LPUART1_TX */ +#define LPDMA1_REQUEST_SPI3_RX 2U /*!< LPDMA1 HW request is SPI3_RX */ +#define LPDMA1_REQUEST_SPI3_TX 3U /*!< LPDMA1 HW request is SPI3_TX */ +#define LPDMA1_REQUEST_I2C3_RX 4U /*!< LPDMA1 HW request is I2C3_RX */ +#define LPDMA1_REQUEST_I2C3_TX 5U /*!< LPDMA1 HW request is I2C3_TX */ +#define LPDMA1_REQUEST_I2C3_EVC 6U /*!< LPDMA1 HW request is I2C3_EVC */ +#define LPDMA1_REQUEST_ADC4 7U /*!< LPDMA1 HW request is ADC4 */ +#define LPDMA1_REQUEST_DAC1_CH1 8U /*!< LPDMA1 HW request is DAC1_CH1 */ +#define LPDMA1_REQUEST_DAC1_CH2 9U /*!< LPDMA1 HW request is DAC1_CH2 */ +#define LPDMA1_REQUEST_ADF1_FLT0 10U /*!< LPDMA1 HW request is ADF1_FLT0 */ +#define LPDMA1_REQUEST_LPTIM1_IC1 11U /*!< LPDMA1 HW request is LPTIM1_IC1 */ +#define LPDMA1_REQUEST_LPTIM1_IC2 12U /*!< LPDMA1 HW request is LPTIM1_IC2 */ +#define LPDMA1_REQUEST_LPTIM1_UE 13U /*!< LPDMA1 HW request is LPTIM1_UE */ +#define LPDMA1_REQUEST_LPTIM3_IC1 14U /*!< LPDMA1 HW request is LPTIM3_IC1 */ +#define LPDMA1_REQUEST_LPTIM3_IC2 15U /*!< LPDMA1 HW request is LPTIM3_IC2 */ +#define LPDMA1_REQUEST_LPTIM3_UE 16U /*!< LPDMA1 HW request is LPTIM3_UE */ + +/* Software request */ +#define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */ +/** + * @} + */ + +/** @defgroup DMA_Block_Request DMA Block Request + * @brief DMA Block Request + * @{ + */ +#define DMA_BREQ_SINGLE_BURST 0x00000000U /*!< Hardware request protocol at a single / burst level */ +#define DMA_BREQ_BLOCK DMA_CTR2_BREQ /*!< Hardware request protocol at a block level */ +/** + * @} + */ + +/** @defgroup DMA_Transfer_Direction DMA Transfer Direction + * @brief DMA transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_Source_Increment_Mode DMA Source Increment Mode + * @brief DMA Source Increment Mode + * @{ + */ +#define DMA_SINC_FIXED 0x00000000U /*!< Source fixed single / burst */ +#define DMA_SINC_INCREMENTED DMA_CTR1_SINC /*!< Source incremented single / burst */ +/** + * @} + */ + +/** @defgroup DMA_Destination_Increment_Mode DMA Destination Increment Mode + * @brief DMA Destination Increment Mode + * @{ + */ +#define DMA_DINC_FIXED 0x00000000U /*!< Destination fixed single / burst */ +#define DMA_DINC_INCREMENTED DMA_CTR1_DINC /*!< Destination incremented single / burst */ +/** + * @} + */ + +/** @defgroup DMA_Source_Data_Width DMA Source Data Width + * @brief DMA Source Data Width + * @{ + */ +#define DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source data width : Byte */ +#define DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source data width : HalfWord */ +#define DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source data width : Word */ +/** + * @} + */ + +/** @defgroup DMA_Destination_Data_Width DMA destination Data Width + * @brief DMA destination Data Width + * @{ + */ +#define DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination data width : Byte */ +#define DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination data width : HalfWord */ +#define DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination data width : Word */ + +/** + * @} + */ + +/** @defgroup DMA_Priority_Level DMA Priority Level + * @brief DMA Priority Level + * @{ + */ +#define DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low weight */ +#define DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid weight */ +#define DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High weight */ +#define DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : HIGH Priority */ +/** + * @} + */ + +/** @defgroup DMA_Transfer_Allocated_Port DMA Transfer Allocated Port + * @brief DMA Transfer Allocated Port + * @{ + */ +#define DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source allocated Port 0 */ +#define DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source allocated Port 1 */ +#define DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination allocated Port 0 */ +#define DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination allocated Port 1 */ +/** + * @} + */ + +/** @defgroup DMA_Transfer_Event_Mode DMA Transfer Event Mode + * @brief DMA Transfer Event Mode + * @{ + */ +#define DMA_TCEM_BLOCK_TRANSFER 0x00000000U /*!< The TC event is generated at the end of each block and the + HT event is generated at the half of each block */ +#define DMA_TCEM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC event is generated at the end of the repeated block + and the HT event is generated at the half of the repeated + block */ +#define DMA_TCEM_EACH_LL_ITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC event is generated at the end of each linked-list + item and the HT event is generated at the half of each + linked-list item */ +#define DMA_TCEM_LAST_LL_ITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC event is generated at the end of the last + linked-list item and the HT event is generated at the half + of the last linked-list item */ +/** + * @} + */ + +/** @defgroup DMA_Transfer_Mode DMA Transfer Mode + * @brief DMA Transfer Mode + * @{ + */ +#define DMA_NORMAL (0x00U) /*!< Normal DMA transfer */ +/** + * @} + */ + +/** @defgroup DMA_Channel_Attributes DMA Channel Attributes + * @brief DMA Channel Security and Privilege Attributes + * @note Secure and non-secure attributes are only available from the secure world when TZEN = 1 + * @{ + */ +#define DMA_CHANNEL_PRIV (DMA_CHANNEL_ATTR_PRIV_MASK | 0x01U) /*!< Channel is privileged */ +#define DMA_CHANNEL_NPRIV (DMA_CHANNEL_ATTR_PRIV_MASK) /*!< Channel is unprivileged */ + +#define DMA_CHANNEL_SEC (DMA_CHANNEL_ATTR_SEC_MASK | 0x02U) /*!< Channel is secure */ +#define DMA_CHANNEL_NSEC (DMA_CHANNEL_ATTR_SEC_MASK) /*!< Channel is non-secure */ +#define DMA_CHANNEL_SRC_SEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK | 0x04U) /*!< Channel source is secure */ +#define DMA_CHANNEL_SRC_NSEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK) /*!< Channel source is non-secure */ +#define DMA_CHANNEL_DEST_SEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK | 0x08U) /*!< Channel destination is secure */ +#define DMA_CHANNEL_DEST_NSEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK) /*!< Channel destination is non-secure */ + +#define DMA_CHANNEL_ATTRIBUTE_UNLOCKED (0x00U) /*!< Channel attribute is unlocked */ +#define DMA_CHANNEL_ATTRIBUTE_LOCKED (0x01U) /*!< Channel attribute is locked */ +/** + * @} + */ + + +/** + * @} + */ + + +/* Exported macro ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros + * @brief DMA Exported Macros + * @{ + */ + +/** @brief Reset DMA handle state. + * @param __HANDLE__ : DMA handle. + * @retval None. + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) \ + ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__ : DMA handle. + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__ : DMA handle. + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_RESET)) + +/** + * @brief Get the DMA channel pending flags. + * @param __HANDLE__ : DMA handle. + * @param __FLAG__ : Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TC : Transfer Complete flag. + * @arg DMA_FLAG_HT : Half Transfer Complete flag. + * @arg DMA_FLAG_DTE : Data Transfer Error flag. + * @arg DMA_FLAG_ULE : Update linked-list Error flag. + * @arg DMA_FLAG_USE : User Setting Error flag. + * @arg DMA_FLAG_TO : Trigger Overrun flag. + * @arg DMA_FLAG_SUSP : Completed Suspension flag. + * @arg DMA_FLAG_IDLEF : Idle flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \ + ((__HANDLE__)->Instance->CSR & (__FLAG__)) + +/** + * @brief Clear the DMA Channel pending flags. + * @param __HANDLE__ : DMA handle. + * @param __FLAG__ : Specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TC : Transfer Complete flag. + * @arg DMA_FLAG_HT : Half Transfer Complete flag. + * @arg DMA_FLAG_DTE : Data Transfer Error flag. + * @arg DMA_FLAG_ULE : Update Linked-List Error flag. + * @arg DMA_FLAG_USE : User Setting Error flag. + * @arg DMA_FLAG_TO : Trigger Overrun flag. + * @arg DMA_FLAG_SUSP : Completed Suspension flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + ((__HANDLE__)->Instance->CFCR = (__FLAG__)) + +/** + * @brief Enable the specified DMA Channel interrupts. + * @param __HANDLE__ : DMA handle. + * @param __INTERRUPT__ : Specifies the DMA interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC : Transfer Complete interrupt. + * @arg DMA_IT_HT : Half Transfer Complete interrupt. + * @arg DMA_IT_DTE : Data Transfer Error interrupt. + * @arg DMA_IT_ULE : Update Linked-List Error interrupt. + * @arg DMA_IT_USE : User Setting Error interrupt. + * @arg DMA_IT_TO : Trigger Overrun interrupt. + * @arg DMA_IT_SUSP : Completed Suspension interrupt. + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified DMA Channel interrupts. + * @param __HANDLE__ : DMA handle. + * @param __INTERRUPT__ : specifies the DMA interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC : Transfer Complete interrupt. + * @arg DMA_IT_HT : Half Transfer Complete interrupt. + * @arg DMA_IT_DTE : Data Transfer Error interrupt. + * @arg DMA_IT_ULE : Update Linked-List Error interrupt. + * @arg DMA_IT_USE : User Setting Error interrupt. + * @arg DMA_IT_TO : Trigger Overrun interrupt. + * @arg DMA_IT_SUSP : Completed Suspension interrupt. + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified DMA Channel interrupt is enabled or not. + * @param __HANDLE__ : DMA handle. + * @param __INTERRUPT__ : specifies the DMA interrupt source to check. + * @arg DMA_IT_TC : Transfer Complete interrupt. + * @arg DMA_IT_HT : Half Transfer Complete interrupt. + * @arg DMA_IT_DTE : Data Transfer Error interrupt. + * @arg DMA_IT_ULE : Update Linked-List Error interrupt. + * @arg DMA_IT_USE : User Setting Error interrupt. + * @arg DMA_IT_TO : Trigger Overrun interrupt. + * @arg DMA_IT_SUSP : Completed Suspension interrupt. + * @retval The state of DMA_IT (SET or RESET). + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) + +/** + * @brief Writes the block number of bytes to be transferred from the source on the DMA Channel. + * @param __HANDLE__ : DMA handle. + * @param __COUNTER__ : Number of data bytes to be transferred from the source (from 0 to 65535). + */ +#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) \ + MODIFY_REG((__HANDLE__)->Instance->CBR1, DMA_CBR1_BNDT, (__COUNTER__)) + +/** + * @brief Returns the number of remaining data bytes in the current DMA Channel transfer. + * @param __HANDLE__ : DMA handle. + * @retval The number of remaining data units in the current DMA Stream transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) \ + (((__HANDLE__)->Instance->CBR1) & DMA_CBR1_BNDT) +/** + * @} + */ + + +/* Include DMA HAL Extension module */ +#include "stm32u5xx_hal_dma_ex.h" + + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @brief DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @brief Initialization and De-Initialization Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 I/O Operation Functions + * @brief I/O Operation Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma, + HAL_DMA_LevelCompleteTypeDef CompleteLevel, + uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, + HAL_DMA_CallbackIDTypeDef CallbackID, + void (*const pCallback)(DMA_HandleTypeDef *const _hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, + HAL_DMA_CallbackIDTypeDef CallbackID); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 State and Error Functions + * @brief State and Error Functions + * @{ + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group4 DMA Attributes Functions + * @brief DMA Attributes Functions + * @{ + */ + +HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, + uint32_t ChannelAttributes); +HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma, + uint32_t *const pChannelAttributes); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, + uint32_t *const pLockState); + + +/** + * @} + */ + +/** + * @} + */ + + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Constants DMA Private Constants + * @brief DMA Private Constants + * @{ + */ +#define HAL_TIMEOUT_DMA_ABORT (0x00000005U) /* DMA channel abort timeout 5 milli-second */ +#define HAL_DMA_CHANNEL_START (0x00000050U) /* DMA channel offset */ +#define HAL_DMA_CHANNEL_SIZE (0x00000080U) /* DMA channel size */ +#define HAL_DMA_OFFSET_MASK (0x00000FFFU) /* DMA channel offset mask */ +#define DMA_CHANNEL_ATTR_PRIV_MASK (0x00000010U) /* DMA channel privilege mask */ +#define DMA_CHANNEL_ATTR_SEC_MASK (0x00000020U) /* DMA channel secure mask */ +#define DMA_CHANNEL_ATTR_SEC_SRC_MASK (0x00000040U) /* DMA channel source secure mask */ +#define DMA_CHANNEL_ATTR_SEC_DEST_MASK (0x00000080U) /* DMA channel destination secure mask */ +#define DMA_CHANNEL_ATTR_VALUE_MASK (0x0000000FU) /* DMA channel attributes value mask */ +#define DMA_CHANNEL_ATTR_ITEM_MASK (0x000000F0U) /* DMA channel attributes item mask */ +#define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */ +#define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */ +/** + * @} + */ + + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @brief DMA Private Macros + * @{ + */ +#define GET_DMA_INSTANCE(__HANDLE__) \ + ((DMA_TypeDef *)((uint32_t)((__HANDLE__)->Instance) & (~HAL_DMA_OFFSET_MASK))) + +#define GET_DMA_CHANNEL(__HANDLE__) \ + ((((uint32_t)((__HANDLE__)->Instance) & HAL_DMA_OFFSET_MASK) - HAL_DMA_CHANNEL_START) / HAL_DMA_CHANNEL_SIZE) + +#define IS_DMA_MODE(MODE) \ + ((MODE) == DMA_NORMAL) + +#define IS_DMA_DIRECTION(DIRECTION) \ + (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_LEVEL_COMPLETE(LEVEL) \ + (((LEVEL) == HAL_DMA_FULL_TRANSFER) || \ + ((LEVEL) == HAL_DMA_HALF_TRANSFER)) + +#define IS_DMA_SOURCE_INC(INC) \ + (((INC) == DMA_SINC_FIXED) || \ + ((INC) == DMA_SINC_INCREMENTED)) + +#define IS_DMA_DESTINATION_INC(INC) \ + (((INC) == DMA_DINC_FIXED) || \ + ((INC) == DMA_DINC_INCREMENTED)) + +#define IS_DMA_SOURCE_DATA_WIDTH(WIDTH) \ + (((WIDTH) == DMA_SRC_DATAWIDTH_BYTE) || \ + ((WIDTH) == DMA_SRC_DATAWIDTH_HALFWORD) || \ + ((WIDTH) == DMA_SRC_DATAWIDTH_WORD)) + +#define IS_DMA_DESTINATION_DATA_WIDTH(WIDTH) \ + (((WIDTH) == DMA_DEST_DATAWIDTH_BYTE) || \ + ((WIDTH) == DMA_DEST_DATAWIDTH_HALFWORD) || \ + ((WIDTH) == DMA_DEST_DATAWIDTH_WORD)) + +#define IS_DMA_BURST_LENGTH(LENGTH) \ + (((LENGTH) >= DMA_CHANNEL_BURST_MIN) && \ + ((LENGTH) <= DMA_CHANNEL_BURST_MAX)) + +#define IS_DMA_PRIORITY(PRIORITY) \ + (((PRIORITY) == DMA_LOW_PRIORITY_LOW_WEIGHT) || \ + ((PRIORITY) == DMA_LOW_PRIORITY_MID_WEIGHT) || \ + ((PRIORITY) == DMA_LOW_PRIORITY_HIGH_WEIGHT) || \ + ((PRIORITY) == DMA_HIGH_PRIORITY)) + +#define IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \ + (((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U) + +#if defined (GPDMA1_REQUEST_JPEG_TX) +#define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_JPEG_TX)) +#elif defined (GPDMA1_REQUEST_ADC2) +#define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_ADC2)) +#else +#define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_LPTIM3_UE)) +#endif /* GPDMA1_REQUEST_JPEG_TX */ + +#define IS_DMA_BLOCK_HW_REQUEST(MODE) \ + (((MODE) == DMA_BREQ_SINGLE_BURST) || \ + ((MODE) == DMA_BREQ_BLOCK)) + +#define IS_DMA_TCEM_EVENT_MODE(MODE) \ + (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ + ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) + +#define IS_DMA_BLOCK_SIZE(SIZE) \ + (((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ + (((ATTRIBUTE) != 0U) && (((ATTRIBUTE) & (~(DMA_CHANNEL_ATTR_VALUE_MASK | DMA_CHANNEL_ATTR_ITEM_MASK))) == 0U) && \ + (((((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U) | ((ATTRIBUTE) & DMA_CHANNEL_ATTR_VALUE_MASK)) == \ + (((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U))) +#else +#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ + (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ + ((ATTRIBUTE) == DMA_CHANNEL_NPRIV)) +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_DMA_GLOBAL_ACTIVE_FLAG_S(INSTANCE, GLOBAL_FLAG) \ + (((INSTANCE)->SMISR & (GLOBAL_FLAG))) +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#define IS_DMA_GLOBAL_ACTIVE_FLAG_NS(INSTANCE, GLOBAL_FLAG) \ + (((INSTANCE)->MISR & (GLOBAL_FLAG))) + +/** + * @} + */ + + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @brief DMA Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_DMA_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma_ex.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma_ex.h new file mode 100644 index 000000000..ac6a09c4e --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma_ex.h @@ -0,0 +1,735 @@ +/** + ********************************************************************************************************************** + * @file stm32u5xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32U5xx_HAL_DMA_EX_H +#define STM32U5xx_HAL_DMA_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @brief DMAEx Exported types + * @{ + */ + +/** + * @brief DMAEx Data Handling Configuration Structure Definition. + */ +typedef struct +{ + uint32_t DataExchange; /*!< Specifies the DMA channel data exchange mode. + This parameter can be a value of @ref DMAEx_Data_Exchange */ + + uint32_t DataAlignment; /*!< Specifies the DMA channel data padding and alignment mode + This parameter can be a value of @ref DMAEx_Data_Alignment */ + +} DMA_DataHandlingConfTypeDef; + +/** + * @brief DMAEx Trigger Configuration Structure Definition. + */ +typedef struct +{ + uint32_t TriggerMode; /*!< Specifies the DMA channel trigger mode. + This parameter can be a value of @ref DMAEx_Trigger_Mode */ + + uint32_t TriggerPolarity; /*!< Specifies the DMA channel trigger event polarity. + This parameter can be a value of @ref DMAEx_Trigger_Polarity */ + + uint32_t TriggerSelection; /*!< Specifies the DMA channel trigger event selection. + This parameter can be a value of @ref DMAEx_Trigger_Selection */ + +} DMA_TriggerConfTypeDef; + +/** + * @brief DMAEx Repeated Block Configuration Structure Definition. + */ +typedef struct +{ + uint32_t RepeatCount; /*!< Specifies the DMA channel repeat count (the number of repetitions of block). + This parameter can be a value between 1 and 2048 */ + + int32_t SrcAddrOffset; /*!< Specifies the DMA channel single/burst source address offset : + This parameter can be a value between -8191 and 8191. + * If source address offset > 0 => Increment the source address by offset from where + the last single/burst transfer ends. + * If source address offset < 0 => Decrement the source address by offset from where + the last single/burst transfer ends. + * If source address offset == 0 => The next single/burst source address starts from + where the last transfer ends */ + + int32_t DestAddrOffset; /*!< Specifies the DMA channel single/burst destination address offset signed value : + This parameter can be a value between -8191 and 8191. + * If destination address offset > 0 => Increment the destination address by offset + from where the last single/burst transfer ends. + * If destination address offset < 0 => Decrement the destination address by offset + from where the last single/burst transfer ends. + * If destination address offset == 0 => The next single/burst destination address + starts from where the last transfer ends. */ + + int32_t BlkSrcAddrOffset; /*!< Specifies the DMA channel block source address offset signed value : + This parameter can be a value between -65535 and 65535. + * If block source address offset > 0 => Increment the block source address by offset + from where the last block ends. + * If block source address offset < 0 => Decrement the next block source address by + offset from where the last block ends. + * If block source address offset == 0 => the next block source address starts from + where the last block ends */ + + int32_t BlkDestAddrOffset; /*!< Specifies the DMA channel block destination address offset signed value : + This parameter can be a value between -65535 and 65535. + * If block destination address offset > 0 => Increment the block destination address + by offset from where the last block ends. + * If block destination address offset < 0 => Decrement the next block destination + address by offset from where the last block ends. + * If block destination address offset == 0 => the next block destination address + starts from where the last block ends */ + +} DMA_RepeatBlockConfTypeDef; + +/** + * @brief DMAEx Queue State Enumeration Definition. + */ +typedef enum +{ + HAL_DMA_QUEUE_STATE_RESET = 0x00U, /*!< DMA queue empty */ + HAL_DMA_QUEUE_STATE_READY = 0x01U, /*!< DMA queue ready for use */ + HAL_DMA_QUEUE_STATE_BUSY = 0x02U /*!< DMA queue execution on going */ + +} HAL_DMA_QStateTypeDef; + +/** + * @brief DMAEx Linked-List Node Configuration Structure Definition. + */ +typedef struct +{ + uint32_t NodeType; /*!< Specifies the DMA channel node type. + This parameter can be a value of @ref DMAEx_Node_Type */ + + DMA_InitTypeDef Init; /*!< Specifies the DMA channel basic configuration */ + + DMA_DataHandlingConfTypeDef DataHandlingConfig; /*!< Specifies the DMA channel data handling channel configuration */ + + DMA_TriggerConfTypeDef TriggerConfig; /*!< Specifies the DMA channel trigger configuration */ + + DMA_RepeatBlockConfTypeDef RepeatBlockConfig; /*!< Specifies the DMA channel repeated block configuration */ + + uint32_t SrcAddress; /*!< Specifies the source memory address */ + uint32_t DstAddress; /*!< Specifies the destination memory address */ + uint32_t DataSize; /*!< Specifies the source data size in bytes */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t SrcSecure; /*!< Specifies the source security attribute */ + uint32_t DestSecure; /*!< Specifies the destination security attribute */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +} DMA_NodeConfTypeDef; + +/** + * @brief DMAEx Linked-List Node Structure Definition. + */ +typedef struct +{ + uint32_t LinkRegisters[8U]; /*!< Physical Node register description */ + uint32_t NodeInfo; /*!< Node information */ + +} DMA_NodeTypeDef; + +/** + * @brief DMAEx Linked-List Queue Structure Definition. + */ +typedef struct __DMA_QListTypeDef +{ + DMA_NodeTypeDef *Head; /*!< Specifies the queue head node */ + + DMA_NodeTypeDef *FirstCircularNode; /*!< Specifies the queue first circular node */ + + uint32_t NodeNumber; /*!< Specifies the queue node number */ + + __IO HAL_DMA_QStateTypeDef State; /*!< Specifies the queue state */ + + __IO uint32_t ErrorCode; /*!< Specifies the queue error code */ + + __IO uint32_t Type; /*!< Specifies whether the queue is static or dynamic */ + +} DMA_QListTypeDef; +/** + * @} + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants + * @brief DMAEx Exported Constants + * @{ + */ + +/** @defgroup Queue_Error_Codes Queue Error Codes + * @brief Queue Error Codes + * @{ + */ +#define HAL_DMA_QUEUE_ERROR_NONE (0x00U) /*!< No error */ +#define HAL_DMA_QUEUE_ERROR_BUSY (0x01U) /*!< Error busy */ +#define HAL_DMA_QUEUE_ERROR_EMPTY (0x02U) /*!< Error unallowed operation for empty queue */ +#define HAL_DMA_QUEUE_ERROR_UNSUPPORTED (0x03U) /*!< Error unsupported feature */ +#define HAL_DMA_QUEUE_ERROR_INVALIDTYPE (0x04U) /*!< Error incompatible node type or circular initialization + and queue circular types are incompatible */ +#define HAL_DMA_QUEUE_ERROR_OUTOFRANGE (0x05U) /*!< Error out of range node memory */ +#define HAL_DMA_QUEUE_ERROR_NOTFOUND (0x06U) /*!< Error node not found in queue */ +/** + * @} + */ + +/** @defgroup DMAEx_LinkedList_Mode DMAEx LinkedList Mode + * @brief DMAEx LinkedList Mode + * @{ + */ +#define DMA_LINKEDLIST_NORMAL DMA_LINKEDLIST /*!< Linear linked-list DMA channel transfer */ +#define DMA_LINKEDLIST_CIRCULAR (DMA_LINKEDLIST | (0x01U)) /*!< Circular linked-list DMA channel transfer */ +/** + * @} + */ + +/** @defgroup DMAEx_Data_Alignment DMAEx Data Alignment + * @brief DMAEx Data Alignment + * @{ + */ +#define DMA_DATA_RIGHTALIGN_ZEROPADDED 0x00000000U /*!< If source data width < destination data width + => Right aligned padded with 0 up to destination data + width */ +#define DMA_DATA_RIGHTALIGN_LEFTTRUNC 0x00000000U /*!< If source data width > destination data width + => Right aligned left Truncated down to destination + data width */ +#define DMA_DATA_RIGHTALIGN_SIGNEXT DMA_CTR1_PAM_0 /*!< If source data width < destination data width + => Right Aligned padded with sign extended up to + destination data width */ +#define DMA_DATA_LEFTALIGN_RIGHTTRUNC DMA_CTR1_PAM_0 /*!< If source data width > destination data width + => Left Aligned Right Truncated down to the + destination data width */ +#define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width + => Packed at the destination data width + (Not available on LPDMA) */ +#define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width + => Unpacked at the destination data width + (Not available on LPDMA) */ +/** + * @} + */ + +/** @defgroup DMAEx_Data_Exchange DMAEx Data Exchange + * @brief DMAEx Data Exchange + * @{ + */ +#define DMA_EXCHANGE_NONE 0x00000000U /*!< No data exchange */ +#define DMA_EXCHANGE_DEST_BYTE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width is > Byte */ +#define DMA_EXCHANGE_DEST_HALFWORD DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width is > Half-Word */ +#define DMA_EXCHANGE_SRC_BYTE DMA_CTR1_SBX /*!< Source Byte endianness exchange when source data width is word */ +/** + * @} + */ + +/** @defgroup DMAEx_Trigger_Polarity DMAEx Trigger Polarity + * @brief DMAEx Trigger Polarity + * @{ + */ +#define DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. Masked trigger event */ +#define DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising edge of the selected trigger event input */ +#define DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling edge of the selected trigger event input */ +/** + * @} + */ + +/** @defgroup DMAEx_Trigger_Mode DMAEx Trigger Mode + * @brief DMAEx Trigger Mode + * @{ + */ +#define DMA_TRIGM_BLOCK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) one hit trigger */ +#define DMA_TRIGM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) one hit trigger */ +#define DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) one hit trigger */ +#define DMA_TRIGM_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM /*!< A single/burst transfer is conditioned by (at least) one hit trigger */ +/** + * @} + */ + +/** @defgroup DMAEx_Trigger_Selection DMAEx Trigger Selection + * @brief DMAEx Trigger Selection + * @{ + */ +/* GPDMA1 triggers */ +#define GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */ +#define GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */ +#define GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger signal is EXTI_LINE2 */ +#define GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger signal is EXTI_LINE3 */ +#define GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger signal is EXTI_LINE4 */ +#define GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger signal is EXTI_LINE5 */ +#define GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger signal is EXTI_LINE6 */ +#define GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger signal is EXTI_LINE7 */ +#define GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger signal is TAMP_TRG1 */ +#define GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger signal is TAMP_TRG2 */ +#define GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger signal is TAMP_TRG3 */ +#define GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */ +#define GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */ +#define GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */ +#define GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ +#define GPDMA1_TRIGGER_LPTIM4_OUT 15U /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */ +#define GPDMA1_TRIGGER_COMP1_OUT 16U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ +#if defined(COMP2) +#define GPDMA1_TRIGGER_COMP2_OUT 17U /*!< GPDMA1 HW Trigger signal is COMP2_OUT */ +#endif /* COMP2 */ +#define GPDMA1_TRIGGER_RTC_ALRA_TRG 18U /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */ +#define GPDMA1_TRIGGER_RTC_ALRB_TRG 19U /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */ +#define GPDMA1_TRIGGER_RTC_WUT_TRG 20U /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */ +#define GPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH2_TCF 24U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH3_TCF 25U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH4_TCF 26U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH5_TCF 27U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH6_TCF 28U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH7_TCF 29U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH8_TCF 30U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH9_TCF 31U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH10_TCF 32U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH11_TCF 33U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH12_TCF 34U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH13_TCF 35U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH14_TCF 36U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH15_TCF 37U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */ +#define GPDMA1_TRIGGER_LPDMA1_CH0_TCF 38U /*!< GPDMA1 HW Trigger signal is LPDMA1_CH0_TCF */ +#define GPDMA1_TRIGGER_LPDMA1_CH1_TCF 39U /*!< GPDMA1 HW Trigger signal is LPDMA1_CH1_TCF */ +#define GPDMA1_TRIGGER_LPDMA1_CH2_TCF 40U /*!< GPDMA1 HW Trigger signal is LPDMA1_CH2_TCF */ +#define GPDMA1_TRIGGER_LPDMA1_CH3_TCF 41U /*!< GPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */ +#define GPDMA1_TRIGGER_TIM2_TRGO 42U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */ +#define GPDMA1_TRIGGER_TIM15_TRGO 43U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */ +#if defined (TIM3_TRGO_TRIGGER_SUPPORT) +#define GPDMA1_TRIGGER_TIM3_TRGO 44U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ +#endif /* TIM3_TRGO_TRIGGER_SUPPORT */ +#if defined (TIM4_TRGO_TRIGGER_SUPPORT) +#define GPDMA1_TRIGGER_TIM4_TRGO 45U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ +#endif /* TIM4_TRGO_TRIGGER_SUPPORT */ +#if defined (TIM5_TRGO_TRIGGER_SUPPORT) +#define GPDMA1_TRIGGER_TIM5_TRGO 46U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */ +#endif /* TIM5_TRGO_TRIGGER_SUPPORT */ +#if defined (LTDC) +#define GPDMA1_TRIGGER_LTDC_LI 47U /*!< GPDMA1 HW Trigger signal is LTDC_LI */ +#endif /* LTDC */ +#if defined (DSI) +#define GPDMA1_TRIGGER_DSI_TE 48U /*!< GPDMA1 HW Trigger signal is DSI_TE */ +#define GPDMA1_TRIGGER_DSI_ER 49U /*!< GPDMA1 HW Trigger signal is DSI_ER */ +#endif /* DSI */ +#if defined (DMA2D_TRIGGER_SUPPORT) +#define GPDMA1_TRIGGER_DMA2D_TC 50U /*!< GPDMA1 HW Trigger signal is DMA2D_TC */ +#define GPDMA1_TRIGGER_DMA2D_CTC 51U /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */ +#define GPDMA1_TRIGGER_DMA2D_TW 52U /*!< GPDMA1 HW Trigger signal is DMA2D_TW */ +#endif /* DMA2D_TRIGGER_SUPPORT */ +#if defined (GPU2D) +#define GPDMA1_TRIGGER_GPU2D_FLAG0 53U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG0 */ +#define GPDMA1_TRIGGER_GPU2D_FLAG1 54U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG1 */ +#define GPDMA1_TRIGGER_GPU2D_FLAG2 55U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG2 */ +#define GPDMA1_TRIGGER_GPU2D_FLAG3 56U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG3 */ +#endif /* GPU2D */ +#define GPDMA1_TRIGGER_ADC4_AWD1 57U /*!< GPDMA1 HW Trigger signal is ADC4_AWD1 */ +#define GPDMA1_TRIGGER_ADC1_AWD1 58U /*!< GPDMA1 HW Trigger signal is ADC1_AWD1 */ +#if defined (GFXTIM) +#define GPDMA1_TRIGGER_GFXTIM_EVT3 59U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT3 */ +#define GPDMA1_TRIGGER_GFXTIM_EVT2 60U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT2 */ +#define GPDMA1_TRIGGER_GFXTIM_EVT1 61U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT1 */ +#define GPDMA1_TRIGGER_GFXTIM_EVT0 62U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT0 */ +#endif /* GFXTIM */ +#if defined (JPEG) +#define GPDMA1_TRIGGER_JPEG_EOC 63U /*!< GPDMA1 HW Trigger signal is JPEG_EOC */ +#define GPDMA1_TRIGGER_JPEG_IFNF 64U /*!< GPDMA1 HW Trigger signal is JPEG_IFNF */ +#define GPDMA1_TRIGGER_JPEG_IFT 65U /*!< GPDMA1 HW Trigger signal is JPEG_IFT */ +#define GPDMA1_TRIGGER_JPEG_OFNE 66U /*!< GPDMA1 HW Trigger signal is JPEG_OFNE */ +#define GPDMA1_TRIGGER_JPEG_OFT 67U /*!< GPDMA1 HW Trigger signal is JPEG_OFT */ +#endif /* JPEG */ + +/* LPDMA1 triggers */ +#define LPDMA1_TRIGGER_EXTI_LINE0 0U /*!< LPDMA1 HW Trigger signal is EXTI_LINE0 */ +#define LPDMA1_TRIGGER_EXTI_LINE1 1U /*!< LPDMA1 HW Trigger signal is EXTI_LINE1 */ +#define LPDMA1_TRIGGER_EXTI_LINE2 2U /*!< LPDMA1 HW Trigger signal is EXTI_LINE2 */ +#define LPDMA1_TRIGGER_EXTI_LINE3 3U /*!< LPDMA1 HW Trigger signal is EXTI_LINE3 */ +#define LPDMA1_TRIGGER_EXTI_LINE4 4U /*!< LPDMA1 HW Trigger signal is EXTI_LINE4 */ +#define LPDMA1_TRIGGER_TAMP_TRG1 5U /*!< LPDMA1 HW Trigger signal is TAMP_TRG1 */ +#define LPDMA1_TRIGGER_TAMP_TRG2 6U /*!< LPDMA1 HW Trigger signal is TAMP_TRG2 */ +#define LPDMA1_TRIGGER_TAMP_TRG3 7U /*!< LPDMA1 HW Trigger signal is TAMP_TRG3 */ +#define LPDMA1_TRIGGER_LPTIM1_CH1 8U /*!< LPDMA1 HW Trigger signal is LPTIM1_CH1 */ +#define LPDMA1_TRIGGER_LPTIM1_CH2 9U /*!< LPDMA1 HW Trigger signal is LPTIM1_CH2 */ +#define LPDMA1_TRIGGER_LPTIM3_CH1 10U /*!< LPDMA1 HW Trigger signal is LPTIM3_CH1 */ +#define LPDMA1_TRIGGER_LPTIM4_OUT 11U /*!< LPDMA1 HW Trigger signal is LPTIM4_OUT */ +#define LPDMA1_TRIGGER_COMP1_OUT 12U /*!< LPDMA1 HW Trigger signal is COMP1_OUT */ +#if defined(COMP2) +#define LPDMA1_TRIGGER_COMP2_OUT 13U /*!< LPDMA1 HW Trigger signal is COMP2_OUT */ +#endif /* COMP2 */ +#define LPDMA1_TRIGGER_RTC_ALRA_TRG 14U /*!< LPDMA1 HW Trigger signal is RTC_ALRA_TRG */ +#define LPDMA1_TRIGGER_RTC_ALRB_TRG 15U /*!< LPDMA1 HW Trigger signal is RTC_ALRB_TRG */ +#define LPDMA1_TRIGGER_RTC_WUT_TRG 16U /*!< LPDMA1 HW Trigger signal is RTC_WUT_TRG */ +#define LPDMA1_TRIGGER_ADC4_AWD1 17U /*!< LPDMA1 HW Trigger signal is ADC4_AWD1 */ +#define LPDMA1_TRIGGER_LPDMA1_CH0_TCF 18U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH0_TCF */ +#define LPDMA1_TRIGGER_LPDMA1_CH1_TCF 19U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH1_TCF */ +#define LPDMA1_TRIGGER_LPDMA1_CH2_TCF 20U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH2_TCF */ +#define LPDMA1_TRIGGER_LPDMA1_CH3_TCF 21U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH4_TCF 24U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH5_TCF 25U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH6_TCF 26U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH7_TCF 27U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH12_TCF 28U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH13_TCF 29U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ +#define LPDMA1_TRIGGER_TIM2_TRGO 30U /*!< LPDMA1 HW Trigger signal is TIM2_TRGO */ +#define LPDMA1_TRIGGER_TIM15_TRGO 31U /*!< LPDMA1 HW Trigger signal is TIM15_TRGO */ +/** + * @} + */ + +/** @defgroup DMAEx_Node_Type DMAEx Node Type + * @brief DMAEx Node Type + * @{ + */ +#define DMA_LPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_LPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the LPDMA linear addressing node type */ +#define DMA_GPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the GPDMA linear addressing node type */ +#define DMA_GPDMA_2D_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_2D_ADDR) /*!< Defines the GPDMA 2 dimension addressing node type */ +/** + * @} + */ + +/** @defgroup DMAEx_Link_Allocated_Port DMAEx Linked-List Allocated Port + * @brief DMAEx Linked-List Allocated Port + * @{ + */ +#define DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Link allocated port 0 */ +#define DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Link allocated port 1 */ +/** + * @} + */ + +/** @defgroup DMAEx_Link_Step_Mode DMAEx Link Step Mode + * @brief DMAEx Link Step Mode + * @{ + */ +#define DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel is executed for the full linked-list */ +#define DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel is executed once for the current LLI */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + * @brief DMAEx Exported functions + * @{ + */ + +/** @defgroup DMAEx_Exported_Functions_Group1 Linked-List Initialization and De-Initialization Functions + * @brief Linked-List Initialization and De-Initialization Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List IO Operation Functions + * @brief Linked-List IO Operation Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group3 Linked-List Management Functions + * @brief Linked-List Management Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, + DMA_NodeTypeDef *const pNode); +HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, + DMA_NodeTypeDef const *const pNode); + +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pPrevNode, + DMA_NodeTypeDef *const pNewNode); +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode); +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode); + +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNode); +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList); +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList); + +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pOldNode, + DMA_NodeTypeDef *const pNewNode); +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode); +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode); + +HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList); + +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, + DMA_NodeTypeDef const *const pPrevNode, + DMA_QListTypeDef *const pDestQList); +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, + DMA_QListTypeDef *const pDestQList); +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, + DMA_QListTypeDef *const pDestQList); + +HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pFirstCircularNode); +HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList); +HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList); + +HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList); +HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList); + +HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma, + DMA_QListTypeDef *const pQList); +HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group4 Data Handling, Repeated Block and Trigger Configuration Functions + * @brief Data Handling, Repeated Block and Trigger Configuration Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma, + DMA_DataHandlingConfTypeDef const *const pConfigDataHandling); +HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma, + DMA_TriggerConfTypeDef const *const pConfigTrigger); +HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma, + DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group5 Suspend and Resume Operation Functions + * @brief Suspend and Resume Operation Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group6 FIFO Status Function + * @brief FIFO Status Function + * @{ + */ +uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Types DMAEx Private Types + * @brief DMAEx Private Types + * @{ + */ + +/** + * @brief DMA Node in Queue Information Structure Definition. + */ +typedef struct +{ + uint32_t cllr_offset; /* CLLR register offset */ + + uint32_t previousnode_addr; /* Previous node address */ + + uint32_t currentnode_pos; /* Current node position */ + + uint32_t currentnode_addr; /* Current node address */ + + uint32_t nextnode_addr; /* Next node address */ + +} DMA_NodeInQInfoTypeDef; +/** + * @} + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Constants DMAEx Private Constants + * @brief DMAEx Private Constants + * @{ + */ +#define DMA_LINKEDLIST (0x0080UL) /* DMA channel linked-list mode */ + +#define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001UL) /* DMA channel linear addressing mode */ +#define DMA_CHANNEL_TYPE_2D_ADDR (0x0002UL) /* DMA channel 2D addressing mode */ +#define DMA_CHANNEL_TYPE_LPDMA (0x0010UL) /* LPDMA channel node */ +#define DMA_CHANNEL_TYPE_GPDMA (0x0020UL) /* GPDMA channel node */ + +#define NODE_TYPE_MASK (0x00FFUL) /* DMA channel node type */ +#define NODE_CLLR_IDX (0x0700UL) /* DMA channel node CLLR index mask */ +#define NODE_CLLR_IDX_POS (0x0008UL) /* DMA channel node CLLR index position */ + +#define NODE_MAXIMUM_SIZE (0x0008UL) /* Amount of registers of the node */ + +#define NODE_STATIC_FORMAT (0x0000UL) /* DMA channel node static format */ +#define NODE_DYNAMIC_FORMAT (0x0001UL) /* DMA channel node dynamic format */ + +#define UPDATE_CLLR_POSITION (0x0000UL) /* DMA channel update CLLR position */ +#define UPDATE_CLLR_VALUE (0x0001UL) /* DMA channel update CLLR value */ + +#define LASTNODE_ISNOT_CIRCULAR (0x0000UL) /* Last node is not first circular node */ +#define LASTNODE_IS_CIRCULAR (0x0001UL) /* Last node is first circular node */ + +#define QUEUE_TYPE_STATIC (0x0000UL) /* DMA channel static queue */ +#define QUEUE_TYPE_DYNAMIC (0x0001UL) /* DMA channel dynamic queue */ + +#define NODE_CTR1_DEFAULT_OFFSET (0x0000UL) /* CTR1 default offset */ +#define NODE_CTR2_DEFAULT_OFFSET (0x0001UL) /* CTR2 default offset */ +#define NODE_CBR1_DEFAULT_OFFSET (0x0002UL) /* CBR1 default offset */ +#define NODE_CSAR_DEFAULT_OFFSET (0x0003UL) /* CSAR default offset */ +#define NODE_CDAR_DEFAULT_OFFSET (0x0004UL) /* CDAR default offset */ +#define NODE_CTR3_DEFAULT_OFFSET (0x0005UL) /* CTR3 2D addressing default offset */ +#define NODE_CBR2_DEFAULT_OFFSET (0x0006UL) /* CBR2 2D addressing default offset */ +#define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007UL) /* CLLR 2D addressing default offset */ +#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005UL) /* CLLR linear addressing default offset */ + +#define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */ +#define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */ +#define DMA_BLOCK_ADDR_OFFSET_MIN (-65536L) /* DMA block minimum address offset */ +#define DMA_BLOCK_ADDR_OFFSET_MAX (65536L) /* DMA block maximum address offset */ +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Macros DMAEx Private Macros + * @brief DMAEx Private Macros + * @{ + */ +#define IS_DMA_DATA_ALIGNMENT(ALIGNMENT) \ + (((ALIGNMENT) == DMA_DATA_RIGHTALIGN_ZEROPADDED) || \ + ((ALIGNMENT) == DMA_DATA_RIGHTALIGN_SIGNEXT) || \ + ((ALIGNMENT) == DMA_DATA_PACK)) + +#define IS_DMA_DATA_EXCHANGE(EXCHANGE) \ + (((EXCHANGE) & (~(DMA_EXCHANGE_SRC_BYTE | DMA_EXCHANGE_DEST_BYTE | DMA_EXCHANGE_DEST_HALFWORD))) == 0U) + +#define IS_DMA_REPEAT_COUNT(COUNT) \ + (((COUNT) > 0U) && ((COUNT) <= (DMA_CBR1_BRC >> DMA_CBR1_BRC_Pos))) + +#define IS_DMA_BURST_ADDR_OFFSET(BURST_ADDR_OFFSET) \ + (((BURST_ADDR_OFFSET) > DMA_BURST_ADDR_OFFSET_MIN) && \ + ((BURST_ADDR_OFFSET) < DMA_BURST_ADDR_OFFSET_MAX)) + +#define IS_DMA_BLOCK_ADDR_OFFSET(BLOCK_ADDR_OFFSET) \ + (((BLOCK_ADDR_OFFSET) > DMA_BLOCK_ADDR_OFFSET_MIN) && \ + ((BLOCK_ADDR_OFFSET) < DMA_BLOCK_ADDR_OFFSET_MAX)) + +#define IS_DMA_LINK_ALLOCATED_PORT(LINK_ALLOCATED_PORT) \ + (((LINK_ALLOCATED_PORT) & (~(DMA_CCR_LAP))) == 0U) + +#define IS_DMA_LINK_STEP_MODE(MODE) \ + (((MODE) == DMA_LSM_FULL_EXECUTION) || \ + ((MODE) == DMA_LSM_1LINK_EXECUTION)) + +#define IS_DMA_TRIGGER_MODE(MODE) \ + (((MODE) == DMA_TRIGM_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TRIGM_REPEATED_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TRIGM_LLI_LINK_TRANSFER) || \ + ((MODE) == DMA_TRIGM_SINGLE_BURST_TRANSFER)) + +#define IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(MODE) \ + (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ + ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) + +#define IS_DMA_LINKEDLIST_MODE(MODE) \ + (((MODE) == DMA_LINKEDLIST_NORMAL) || \ + ((MODE) == DMA_LINKEDLIST_CIRCULAR)) + +#define IS_DMA_TRIGGER_POLARITY(POLARITY) \ + (((POLARITY) == DMA_TRIG_POLARITY_MASKED) || \ + ((POLARITY) == DMA_TRIG_POLARITY_RISING) || \ + ((POLARITY) == DMA_TRIG_POLARITY_FALLING)) + +#if defined (GPDMA1_TRIGGER_JPEG_OFT) +#define IS_DMA_TRIGGER_SELECTION(TRIGGER) ((TRIGGER) <= GPDMA1_TRIGGER_JPEG_OFT) +#else +#define IS_DMA_TRIGGER_SELECTION(TRIGGER) ((TRIGGER) <= GPDMA1_TRIGGER_ADC1_AWD1) +#endif /* GPDMA1_TRIGGER_JPEG_OFT */ + +#define IS_DMA_NODE_TYPE(TYPE) \ + (((TYPE) == DMA_LPDMA_LINEAR_NODE) || \ + ((TYPE) == DMA_GPDMA_LINEAR_NODE) || \ + ((TYPE) == DMA_GPDMA_2D_NODE)) +/** + * @} + */ + + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Functions DMAEx Private Functions + * @brief DMAEx Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32U5xx_HAL_DMA_EX_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_exti.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_exti.h new file mode 100644 index 000000000..5f0f16511 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_exti.h @@ -0,0 +1,393 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_EXTI_H +#define STM32U5xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U, + HAL_EXTI_RISING_CB_ID = 0x01U, + HAL_EXTI_FALLING_CB_ID = 0x02U, +} EXTI_CallbackIDTypeDef; + + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* RisingCallback)(void); /*!< Exti rising callback */ + void (* FallingCallback)(void); /*!< Exti falling callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00U) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01U) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02U) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03U) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04U) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05U) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06U) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07U) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08U) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09U) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0AU) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0BU) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0CU) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0DU) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0EU) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0FU) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10U) +#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11U) +#if defined(EXTI_IMR1_IM18) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | 0x12U) +#endif /* EXTI_IMR1_IM18 */ +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | 0x13U) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14U) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | 0x15U) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | 0x16U) +#define EXTI_LINE_23 (EXTI_CONFIG | EXTI_REG1 | 0x17U) +#if defined(EXTI_IMR1_IM24) +#define EXTI_LINE_24 (EXTI_CONFIG | EXTI_REG1 | 0x18U) +#endif /* EXTI_IMR1_IM24 */ +#if defined(EXTI_IMR1_IM25) +#define EXTI_LINE_25 (EXTI_CONFIG | EXTI_REG1 | 0x19U) +#endif /* EXTI_IMR1_IM25 */ +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000U +#define EXTI_MODE_INTERRUPT 0x00000001U +#define EXTI_MODE_EVENT 0x00000002U +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_NONE 0x00000000U +#define EXTI_TRIGGER_RISING 0x00000001U +#define EXTI_TRIGGER_FALLING 0x00000002U +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000U +#define EXTI_GPIOB 0x00000001U +#define EXTI_GPIOC 0x00000002U +#define EXTI_GPIOD 0x00000003U +#define EXTI_GPIOE 0x00000004U +#if defined(GPIOF) +#define EXTI_GPIOF 0x00000005U +#endif /* GPIOF */ +#define EXTI_GPIOG 0x00000006U +#define EXTI_GPIOH 0x00000007U +#if defined(GPIOI) +#define EXTI_GPIOI 0x00000008U +#endif /* GPIOI */ +#if defined(GPIOJ) +#define EXTI_GPIOJ 0x00000009U +#endif /* GPIOJ */ + +/** + * @} + */ + +/** @defgroup EXTI_Line_attributes EXTI line attributes + * @brief EXTI line secure or non-secure and privileged or non-privileged attributes + * @note secure and non-secure attributes are only available from secure state when the system + * implement the security (TZEN=1) + * @{ + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/*!< Secure line attribute */ +#define EXTI_LINE_SEC (EXTI_LINE_ATTR_SEC_MASK | 0x00000001U) +/*!< Non-secure line attribute */ +#define EXTI_LINE_NSEC (EXTI_LINE_ATTR_SEC_MASK | 0x00000000U) +#endif /* __ARM_FEATURE_CMSE */ +/*!< Privileged line attribute */ +#define EXTI_LINE_PRIV (EXTI_LINE_ATTR_PRIV_MASK | 0x00000002U) +/*!< Non-privileged line attribute */ +#define EXTI_LINE_NPRIV (EXTI_LINE_ATTR_PRIV_MASK | 0x00000000U) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24UL +#define EXTI_DIRECT (0x01UL << EXTI_PROPERTY_SHIFT) +#define EXTI_CONFIG (0x02UL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08UL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI Register and bit usage + */ +#define EXTI_REG_SHIFT 16UL +#define EXTI_REG1 (0x00UL << EXTI_REG_SHIFT) +#define EXTI_REG2 (0x01UL << EXTI_REG_SHIFT) +#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2) +#define EXTI_PIN_MASK 0x0000001FU + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#if defined(EXTI_IMR1_IM24) && defined(EXTI_IMR1_IM25) +#define EXTI_LINE_NB 26U +#else +#define EXTI_LINE_NB 24U +#endif /* defined(EXTI_IMR1_IM24) && defined(EXTI_IMR1_IM25) */ + +/** + * @brief EXTI Mask for secure & privilege attributes + */ +#define EXTI_LINE_ATTR_SEC_MASK 0x100U +#define EXTI_LINE_ATTR_PRIV_MASK 0x200U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | \ + EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) \ + &&((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ + (((EXTI_LINE_NB / 32U) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32U)))) + +#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \ + (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U)) + +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U) + +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \ + ((__EXTI_LINE__) == EXTI_TRIGGER_FALLING)) + +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U) + +#if defined(GPIOJ) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI) || \ + ((__PORT__) == EXTI_GPIOJ)) +#elif defined(GPIOF) && defined (GPIOI) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH)) +#endif /* GPIOJ */ + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +#define IS_EXTI_LINE_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & EXTI_LINE_SEC) == EXTI_LINE_SEC) || \ + (((__ATTRIBUTES__) & EXTI_LINE_NSEC) == EXTI_LINE_NSEC) || \ + (((__ATTRIBUTES__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \ + (((__ATTRIBUTES__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \ + (((__ATTRIBUTES__) & ~(EXTI_LINE_SEC|EXTI_LINE_NSEC|EXTI_LINE_PRIV| \ + EXTI_LINE_NPRIV)) == 0U)) + +#else + +#define IS_EXTI_LINE_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \ + (((__ATTRIBUTES__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \ + (((__ATTRIBUTES__) & ~(EXTI_LINE_PRIV|EXTI_LINE_NPRIV)) == 0U)) + +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, + void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group3 EXTI line attributes management functions + * @{ + */ + +/* EXTI line attributes management functions **********************************/ +void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes); +HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +void HAL_EXTI_LockAttributes(void); +uint32_t HAL_EXTI_GetLockAttributes(void); +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_EXTI_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash.h new file mode 100644 index 000000000..1a003f2d7 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash.h @@ -0,0 +1,1122 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_FLASH_H +#define STM32U5xx_HAL_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< Mass erase or page erase. + This parameter can be a value of @ref FLASH_Type_Erase */ + uint32_t Banks; /*!< Select bank to erase. + This parameter must be a value of @ref FLASH_Banks + (FLASH_BANK_BOTH should be used only for mass erase) */ + uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled + This parameter must be a value between 0 and (max number of pages in the bank - 1) + (eg : 127 for 2MB dual bank) */ + uint32_t NbPages; /*!< Number of pages to be erased. This parameter must be a value between 1 and + (max number of pages in the bank - value of initial page)*/ +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured. + This parameter can be a combination of the values of @ref FLASH_OB_Type */ + uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). + Only one WRP area could be programmed at the same time. + This parameter can be value of @ref FLASH_OB_WRP_Area */ + uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). + This parameter must be a value between 0 and (max number of pages in the bank - 1) */ + uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). + This parameter must be a value between WRPStartOffset + and (max number of pages in the bank - 1) */ + FunctionalState WRPLock; /*!< Write protection lock (used for OPTIONBYTE_WRP). + This parameter can be set to ENABLE or DISABLE */ + uint32_t RDPLevel; /*!< Set the read protection level (used for OPTIONBYTE_RDP). + This parameter can be a value of @ref FLASH_OB_Read_Protection */ + uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). + This parameter can be a combination of @ref FLASH_OB_USER_Type */ + uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). + This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, + @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, + @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST, + @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP, + @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW, + @ref FLASH_OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK, + @ref FLASH_OB_USER_BKPRAM_RST, @ref FLASH_OB_USER_SRAM3_ECC, + @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM2_RST, + @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0, + @ref FLASH_OB_USER_PA15_PUPEN, @ref FLASH_OB_USER_IO_VDD_HSLV, + @ref FLASH_OB_USER_IO_VDDIO2_HSLV, @ref FLASH_OB_USER_TZEN */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t WMSecConfig; /*!< Configuration of the Watermark-based Secure Area (used for OPTIONBYTE_WMSEC). + This parameter must be a value of @ref FLASH_OB_WMSEC */ + uint32_t WMSecStartPage; /*!< Start page of secure area (used for OPTIONBYTE_WMSEC). + This parameter must be a value between 0 and (max number of pages in the bank - 1) */ + uint32_t WMSecEndPage; /*!< End page of secure area (used for OPTIONBYTE_WMSEC). This parameter must be a value + between WMSecStartPage and (max number of pages in the bank - 1) */ + uint32_t WMHDPEndPage; /*!< End page of the secure hide protection (used for OPTIONBYTE_WMSEC). + This parameter must be a value between WMSecStartPage and WMSecEndPage */ + uint32_t BootLock; /*!< Configuration of the boot lock (used for OPTIONBYTE_BOOT_LOCK). + This parameter must be a value of @ref FLASH_OB_BOOT_LOCK */ +#endif /* __ARM_FEATURE_CMSE */ + uint32_t BootAddrConfig; /*!< Configuration of the Boot address (used for OPTIONBYTE_BOOTADDR). + This parameter must be a value of @ref FLASH_OB_BOOTADDR */ + uint32_t BootAddr; /*!< Boot address (used for OPTIONBYTE_BOOTADDR). + This parameter must be a value between 0x0 and 0xFFFFFF00 */ + uint32_t RDPKeyType; /*!< Configuration of the RDP OEM keys (used for OPTIONBYTE_RDPKEY). + This parameter can be a value of @ref FLASH_OB_RDP_Key_Type */ + uint32_t RDPKey1; /*!< Value of the RDP OEM key 1 (used for OPTIONBYTE_RDPKEY) */ + uint32_t RDPKey2; /*!< Value of the RDP OEM key 2 (used for OPTIONBYTE_RDPKEY) */ +} FLASH_OBProgramInitTypeDef; + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + HAL_LockTypeDef Lock; /* FLASH locking object */ + uint32_t ErrorCode; /* FLASH error code */ + uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing + or not in IT context */ + uint32_t Address; /* Internal variable to save address selected for program + in IT context */ + uint32_t Bank; /* Internal variable to save current bank selected during erase + in IT context */ + uint32_t Page; /* Internal variable to define the current page which is being erased + in IT context */ + uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ +} FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASH_Flags FLASH Flags Definition + * @{ + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_FLAG_EOP FLASH_SECSR_EOP /*!< FLASH End of operation flag */ +#define FLASH_FLAG_OPERR FLASH_SECSR_OPERR /*!< FLASH Operation error flag */ +#define FLASH_FLAG_PROGERR FLASH_SECSR_PROGERR /*!< FLASH Programming error flag */ +#define FLASH_FLAG_WRPERR FLASH_SECSR_WRPERR /*!< FLASH Write protection error flag */ +#define FLASH_FLAG_PGAERR FLASH_SECSR_PGAERR /*!< FLASH Programming alignment error flag */ +#define FLASH_FLAG_SIZERR FLASH_SECSR_SIZERR /*!< FLASH Size error flag */ +#define FLASH_FLAG_PGSERR FLASH_SECSR_PGSERR /*!< FLASH Programming sequence error flag */ +#define FLASH_FLAG_OPTWERR FLASH_NSSR_OPTWERR /*!< FLASH Option modification error flag */ +#define FLASH_FLAG_BSY FLASH_SECSR_BSY /*!< FLASH Busy flag */ +#define FLASH_FLAG_WDW FLASH_SECSR_WDW /*!< FLASH Wait Data to Write flag */ +#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ +#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ + +#define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR) +#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD) +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_OPTWERR | FLASH_FLAG_ECCR_ERRORS) +#else +#define FLASH_FLAG_EOP FLASH_NSSR_EOP /*!< FLASH End of operation flag */ +#define FLASH_FLAG_OPERR FLASH_NSSR_OPERR /*!< FLASH Operation error flag */ +#define FLASH_FLAG_PROGERR FLASH_NSSR_PROGERR /*!< FLASH Programming error flag */ +#define FLASH_FLAG_WRPERR FLASH_NSSR_WRPERR /*!< FLASH Write protection error flag */ +#define FLASH_FLAG_PGAERR FLASH_NSSR_PGAERR /*!< FLASH Programming alignment error flag */ +#define FLASH_FLAG_SIZERR FLASH_NSSR_SIZERR /*!< FLASH Size error flag */ +#define FLASH_FLAG_PGSERR FLASH_NSSR_PGSERR /*!< FLASH Programming sequence error flag */ +#define FLASH_FLAG_OPTWERR FLASH_NSSR_OPTWERR /*!< FLASH Option modification error flag */ +#define FLASH_FLAG_BSY FLASH_NSSR_BSY /*!< FLASH Busy flag */ +#define FLASH_FLAG_WDW FLASH_NSSR_WDW /*!< FLASH Wait Data to Write flag */ +#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ +#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ + +#define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ + FLASH_FLAG_OPTWERR) +#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD) +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS) +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition + * @brief FLASH Interrupt definition + * @{ + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_IT_EOP FLASH_SECCR_EOPIE /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_OPERR FLASH_SECCR_ERRIE /*!< Error Interrupt source */ +#define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */ +#else +#define FLASH_IT_EOP FLASH_NSCR_EOPIE /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_OPERR FLASH_NSCR_ERRIE /*!< Error Interrupt source */ +#define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** @defgroup FLASH_Error FLASH Error + * @{ + */ +#define HAL_FLASH_ERROR_NONE 0x00000000U +#define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR +#define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR +#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR +#define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR +#define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR +#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR +#define HAL_FLASH_ERROR_OPTW FLASH_FLAG_OPTWERR +#define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC +#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD +/** + * @} + */ + +/** @defgroup FLASH_Type_Erase FLASH Erase Type + * @{ + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_TYPEERASE_PAGES FLASH_SECCR_PER /*!< Secure pages erase + activation */ +#define FLASH_TYPEERASE_PAGES_NS (FLASH_NSCR_PER | FLASH_NON_SECURE_MASK) /*!< Non-secure pages erase + activation */ +#define FLASH_TYPEERASE_MASSERASE (FLASH_SECCR_MER1 | FLASH_SECCR_MER2) /*!< Secure flash mass erase + activation */ +#define FLASH_TYPEERASE_MASSERASE_NS (FLASH_NSCR_MER1 | FLASH_NSCR_MER2 | FLASH_NON_SECURE_MASK) /*!< Non-secure flash + mass erase activation */ +#else +#define FLASH_TYPEERASE_PAGES FLASH_NSCR_PER /*!< Pages erase activation */ +#define FLASH_TYPEERASE_MASSERASE (FLASH_NSCR_MER1 | FLASH_NSCR_MER2) /*!< Flash mass erase activation */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** @defgroup FLASH_Banks FLASH Banks + * @{ + */ +#define FLASH_BANK_1 0x00000001U /*!< Bank 1 */ +#define FLASH_BANK_2 0x00000002U /*!< Bank 2 */ +#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ +/** + * @} + */ + +/** @defgroup FLASH_Type_Program FLASH Program Type + * @{ + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_TYPEPROGRAM_QUADWORD FLASH_SECCR_PG /*!< Program a quad-word (128-bit) + at a specified secure address */ +#define FLASH_TYPEPROGRAM_QUADWORD_NS (FLASH_NSCR_PG | FLASH_NON_SECURE_MASK) /*!< Program a quad-word (128-bit) + at a specified non-secure address */ +#define FLASH_TYPEPROGRAM_BURST (FLASH_SECCR_PG | FLASH_SECCR_BWR) /*!< Program a burst (8xquad-word) + at a specified secure address */ +#define FLASH_TYPEPROGRAM_BURST_NS (FLASH_NSCR_PG | FLASH_NSCR_BWR | FLASH_NON_SECURE_MASK) /*!< Program a burst +(8xquad-word) at a specified non-secure address */ +#else +#define FLASH_TYPEPROGRAM_QUADWORD FLASH_NSCR_PG /*!ACR, FLASH_ACR_LATENCY, (__LATENCY__)) + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * This return value can be one of the following values : + * @arg FLASH_LATENCY_0: FLASH Zero wait state + * @arg FLASH_LATENCY_1: FLASH One wait state + * @arg FLASH_LATENCY_2: FLASH Two wait states + * @arg FLASH_LATENCY_3: FLASH Three wait states + * @arg FLASH_LATENCY_4: FLASH Four wait states + * @arg FLASH_LATENCY_5: FLASH Five wait states + * @arg FLASH_LATENCY_6: FLASH Six wait states + * @arg FLASH_LATENCY_7: FLASH Seven wait states + * @arg FLASH_LATENCY_8: FLASH Eight wait states + * @arg FLASH_LATENCY_9: FLASH Nine wait states + * @arg FLASH_LATENCY_10: FLASH Ten wait states + * @arg FLASH_LATENCY_11: FLASH Eleven wait states + * @arg FLASH_LATENCY_12: FLASH Twelve wait states + * @arg FLASH_LATENCY_13: FLASH Thirteen wait states + * @arg FLASH_LATENCY_14: FLASH Fourteen wait states + * @arg FLASH_LATENCY_15: FLASH Fifteen wait states + */ +#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) + +/** + * @brief Enable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) + +/** + * @brief Enable the FLASH power down during Low-Power sleep mode + * @retval none + */ +#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) + +/** + * @brief Disable the FLASH power down during Low-Power sleep mode + * @retval none + */ +#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) + +/** + * @} + */ + +/** @defgroup FLASH_Interrupt FLASH Interrupts Macros + * @brief macros to handle FLASH interrupts + * @{ + */ + +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt + * @arg FLASH_IT_OPERR: Error Interrupt + * @arg FLASH_IT_ECCC: ECC Correction Interrupt + * @retval none + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* Enable secure FLASH interrupts from the secure world */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ + { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ + { SET_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ + } while(0) +/* Enable non-secure FLASH interrupts from the secure world */ +#define __HAL_FLASH_ENABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ + { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ + { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ + } while(0) +#else +/* Enable non-secure FLASH interrupts from the non-secure world */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ + { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ + { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ + } while(0) +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt + * @arg FLASH_IT_OPERR: Error Interrupt + * @arg FLASH_IT_ECCC: ECC Correction Interrupt + * @retval none + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* Disable secure FLASH interrupts from the secure world */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ + { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ + { CLEAR_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC)));}\ + } while(0) +/* Disable non-secure FLASH interrupts from the secure world */ +#define __HAL_FLASH_DISABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ + { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ + { CLEAR_BIT(FLASH->NSCR, ((__INTERRUPT__) & \ + (~FLASH_IT_ECCC))); }\ + } while(0) +#else +/* Disable non-secure FLASH interrupts from the non-secure world */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ + { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ + { CLEAR_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ + } while(0) +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Check whether the specified FLASH flag is set or not. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR: FLASH Operation error flag + * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag + * @arg FLASH_FLAG_SIZERR: FLASH Size error flag + * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag + * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag + * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag + * @arg FLASH_FLAG_WDW: FLASH Wait Data to Write flag + * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected + * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* Get secure FLASH flags from the secure world */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \ + (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ + ((((__FLAG__) & (FLASH_FLAG_OPTWERR)) != 0U) ? \ + (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__)) : \ + (READ_BIT(FLASH->SECSR, (__FLAG__)) == (__FLAG__)))) +/* Get non-secure FLASH flags from the secure world */ +#define __HAL_FLASH_GET_FLAG_NS(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \ + (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ + (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__))) +#else +/* Get non-secure FLASH flags from the non-secure world */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \ + (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ + (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__))) +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Clear the FLASH's pending flags. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR: FLASH Operation error flag + * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag + * @arg FLASH_FLAG_SIZERR: FLASH Size error flag + * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag + * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag (Only in non-secure) + * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected + * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected + * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags + * @retval None + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* Clear secure FLASH flags from the secure world */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) \ + { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ + if(((__FLAG__) & FLASH_FLAG_OPTWERR) != 0U) \ + { SET_BIT(FLASH->NSSR, ((__FLAG__) & (FLASH_FLAG_OPTWERR))); }\ + if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | \ + FLASH_FLAG_OPTWERR)) != 0U) \ + { WRITE_REG(FLASH->SECSR, ((__FLAG__) & \ + ~(FLASH_FLAG_ECCR_ERRORS | FLASH_FLAG_OPTWERR))); }\ + } while(0) +/* Clear non-secure FLASH flags from the secure world */ +#define __HAL_FLASH_CLEAR_FLAG_NS(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) \ + { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ + if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) \ + { WRITE_REG(FLASH->NSSR, ((__FLAG__) & \ + ~(FLASH_FLAG_ECCR_ERRORS))); }\ + } while(0) +#else +/* Clear non-secure FLASH flags from the non-secure world */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) \ + { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ + if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) \ + { WRITE_REG(FLASH->NSSR, ((__FLAG__) & \ + ~(FLASH_FLAG_ECCR_ERRORS))); }\ + } while(0) +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/* Include FLASH HAL Extended module */ +#include "stm32u5xx_hal_flash_ex.h" + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/* Program operation functions ***********************************************/ +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress); +/* FLASH IRQ handler method */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +/* Option bytes control */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +uint32_t HAL_FLASH_GetError(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ + +#define FLASH_TIMEOUT_VALUE 1000U /* 1 s */ + +#define FLASH_NON_SECURE_MASK 0x80000000U + +#define FLASH_NB_WORDS_IN_BURST 32 + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ + ((VALUE) == FLASH_TYPEERASE_PAGES_NS) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE_NS)) +#else +#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE)) +#endif /* __ARM_FEATURE_CMSE */ + +#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2) || \ + ((BANK) == FLASH_BANK_BOTH)) + +#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_NS) || \ + ((VALUE) == FLASH_TYPEPROGRAM_BURST) || \ + ((VALUE) == FLASH_TYPEPROGRAM_BURST_NS)) +#else +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_BURST)) +#endif /* __ARM_FEATURE_CMSE */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) || \ + (((ADDRESS) >= FLASH_BASE_NS) && ((ADDRESS) < (FLASH_BASE_NS+FLASH_SIZE)))) +#else +#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) +#endif /* __ARM_FEATURE_CMSE */ + +#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_OTP_BASE)\ + && ((ADDRESS) < (FLASH_OTP_BASE + FLASH_OTP_SIZE))) + +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS))) + +#define IS_FLASH_PAGE(PAGE) ((PAGE) < FLASH_PAGE_NB) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ + OPTIONBYTE_WMSEC | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_BOOTADDR | \ + OPTIONBYTE_RDPKEY))) +#else +#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ + OPTIONBYTE_BOOTADDR | OPTIONBYTE_RDPKEY))) +#endif /* __ARM_FEATURE_CMSE */ + +#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ + ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) + +#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ + ((LEVEL) == OB_RDP_LEVEL_0_5) ||\ + ((LEVEL) == OB_RDP_LEVEL_1) ||\ + ((LEVEL) == OB_RDP_LEVEL_2)) + +#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= 0x1FFFFFU) && ((TYPE) != 0U)) + +#define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ + ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \ + ((LEVEL) == OB_BOR_LEVEL_4)) + +#define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) + +#define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) + +#define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST)) + +#define IS_OB_USER_SRAM_RST(VALUE) (((VALUE) == OB_SRAM_RST_ERASE) || ((VALUE) == OB_SRAM_RST_NOT_ERASE)) + +#define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) + +#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) + +#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) + +#define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) + +#define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE)) + +#define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL)) + +#define IS_OB_USER_BKPRAM_ECC(VALUE) (((VALUE) == OB_BKPRAM_ECC_ENABLE) || ((VALUE) == OB_BKPRAM_ECC_DISABLE)) + +#define IS_OB_USER_SRAM3_ECC(VALUE) (((VALUE) == OB_SRAM3_ECC_ENABLE) || ((VALUE) == OB_SRAM3_ECC_DISABLE)) + +#define IS_OB_USER_SRAM2_ECC(VALUE) (((VALUE) == OB_SRAM2_ECC_ENABLE) || ((VALUE) == OB_SRAM2_ECC_DISABLE)) + +#define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) + +#define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) + +#define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_NBOOT0_RESET) || ((VALUE) == OB_NBOOT0_SET)) + +#define IS_OB_USER_PA15_PUPEN(VALUE) (((VALUE) == OB_PA15_PUP_DISABLE) || ((VALUE) == OB_PA15_PUP_ENABLE)) + +#define IS_OB_USER_IO_VDD_HSLV(VALUE) (((VALUE) == OB_IO_VDD_HSLV_DISABLE) || ((VALUE) == OB_IO_VDD_HSLV_ENABLE)) + +#define IS_OB_USER_IO_VDDIO2_HSLV(VALUE) (((VALUE) == OB_IO_VDDIO2_HSLV_DISABLE)\ + || ((VALUE) == OB_IO_VDDIO2_HSLV_ENABLE)) + +#define IS_OB_USER_TZEN(VALUE) (((VALUE) == OB_TZEN_DISABLE) || ((VALUE) == OB_TZEN_ENABLE)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_DISABLE) || ((VALUE) == OB_BOOT_LOCK_ENABLE)) + +#define IS_OB_WMSEC_CONFIG(CFG) ((((CFG) & 0x7F3U) != 0U) && \ + (((CFG) & 0x3U) != 0U) && (((CFG) & 0xFFFFF80CU) == 0U)) + +#define IS_OB_WMSEC_AREA_EXCLUSIVE(WMSEC) (((((WMSEC) & OB_WMSEC_AREA1) != 0U) && \ + (((WMSEC) & OB_WMSEC_AREA2) == 0U)) || \ + ((((WMSEC) & OB_WMSEC_AREA2) != 0U) && \ + (((WMSEC) & OB_WMSEC_AREA1) == 0U))) +#endif /* __ARM_FEATURE_CMSE */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_OB_BOOTADDR_CONFIG(CFG) (((CFG) == OB_BOOTADDR_NS0) || ((CFG) == OB_BOOTADDR_NS1) || \ + ((CFG) == OB_BOOTADDR_SEC0)) +#else +#define IS_OB_BOOTADDR_CONFIG(CFG) (((CFG) == OB_BOOTADDR_NS0) || ((CFG) == OB_BOOTADDR_NS1)) +#endif /* __ARM_FEATURE_CMSE */ + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ + ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ + ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ + ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ + ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ + ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ + ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ + ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) + +#define IS_OB_RDP_KEY_TYPE(TYPE) (((TYPE) == OB_RDP_KEY_OEM1) || \ + ((TYPE) == OB_RDP_KEY_OEM2)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_FLASH_SECURE_OPERATION() ((pFlash.ProcedureOnGoing & FLASH_NON_SECURE_MASK) == 0U) +#else +#define IS_FLASH_SECURE_OPERATION() (0U) +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_FLASH_H */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash_ex.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash_ex.h new file mode 100644 index 000000000..6add95aca --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash_ex.h @@ -0,0 +1,240 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of FLASH HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_FLASH_EX_H +#define STM32U5xx_HAL_FLASH_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Types FLASHEx Exported Types + * @{ + */ + +/** + * @brief FLASHEx Block-based attributes structure definition + */ + +typedef struct +{ + uint32_t Bank; /*!< Selection of the associated bank of Block-based Area. + This parameter must be a value of @ref FLASH_Banks */ + uint32_t BBAttributesType; /*!< Block-Based Attributes type. This parameter must + be a value of @ref FLASH_BB_Attributes */ + uint32_t BBAttributes_array[FLASH_BLOCKBASED_NB_REG]; /*!< Each bit specifies the block-based attribute configuration + of a page: 0 means page non-protected, 1 means page + protected. Protection (secure or privilege) depends + on BBAttributesType value */ +} FLASH_BBAttributesTypeDef; + + +/** + * @brief FLASHEx Operation structure definition + */ +typedef struct +{ + uint32_t OperationType; /*!< Flash operation Type. + This parameter must be a value of @ref FLASH_Operation_Type */ + uint32_t FlashArea; /*!< Flash operation memory area. + This parameter must be a value of @ref FLASH_Operation_Area */ + uint32_t Address; /*!< Flash operation Address offset. + This parameter is given by bank, and must be a value between 0x0 and 0xFFFF0 */ +} FLASH_OperationTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Constants + * @{ + */ +/** @defgroup PRIV_MODE_CFG FLASH privilege mode configuration + * @{ + */ +#define FLASH_NSPRIV_GRANTED 0x00000000U /*!< access to non-secure Flash registers is granted + to privileged or unprivileged access */ +#define FLASH_NSPRIV_DENIED FLASH_PRIVCFGR_NSPRIV /*!< access to non-secure Flash registers is denied + to non-privilege access */ +#define FLASH_SPRIV_GRANTED 0x00000000U /*!< access to secure Flash registers is granted to privileged + or unprivileged access */ +#define FLASH_SPRIV_DENIED FLASH_PRIVCFGR_SPRIV /*!< access to secure Flash registers is denied + to non-privilege access */ +/** + * @} + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** @defgroup SEC_INVERSION_CFG FLASH security inversion configuration + * @{ + */ +#define FLASH_INV_DISABLE 0x00000000U /*!< Security state of Flash is not inverted */ +#define FLASH_INV_ENABLE FLASH_SECCR_INV /*!< Security state of Flash is inverted */ +/** + * @} + */ +#endif /* __ARM_FEATURE_CMSE */ + +/** @defgroup FLASH_LPM_CFG FLASH LPM configuration + * @{ + */ +#define FLASH_LPM_DISABLE 0x00000000U /*!< Flash is in normal read mode */ +#define FLASH_LPM_ENABLE FLASH_ACR_LPM /*!< Flash is in low-power read mode */ +/** + * @} + */ + +/** @defgroup FLASH_BB_Attributes FLASH Block-Base Attributes + * @{ + */ +#define FLASH_BB_SEC 0x01U /*!< Flash Block-Based Security Attributes */ +#define FLASH_BB_PRIV 0x02U /*!< Flash Block-Based Privilege Attributes */ +/** + * @} + */ + +/** @defgroup FLASH_Operation_Type FLASH Operation Type + * @{ + */ +#define FLASH_OPERATION_TYPE_NONE 00000000U /*!< No Flash operation */ +#define FLASH_OPERATION_TYPE_QUADWORD FLASH_OPSR_CODE_OP_0 /*!< Single write operation */ +#define FLASH_OPERATION_TYPE_BURST FLASH_OPSR_CODE_OP_1 /*!< Burst write operation */ +#define FLASH_OPERATION_TYPE_PAGEERASE (FLASH_OPSR_CODE_OP_1 | FLASH_OPSR_CODE_OP_0) /*!< Page erase operation */ +#define FLASH_OPERATION_TYPE_BANKERASE FLASH_OPSR_CODE_OP_2 /*!< Bank erase operation */ +#define FLASH_OPERATION_TYPE_MASSERASE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_0) /*!< Mass erase operation */ +#define FLASH_OPERATION_TYPE_OPTIONCHANGE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1) /*!< Option change operation */ +/** + * @} + */ + +/** @defgroup FLASH_Operation_Area FLASH Operation Area + * @{ + */ +#define FLASH_OPERATION_AREA_BANK_1 00000000U /*!< Operation in Bank 1 */ +#define FLASH_OPERATION_AREA_BANK_2 FLASH_OPSR_BK_OP /*!< Operation in Bank 2 */ +#define FLASH_OPERATION_AREA_SYSF FLASH_OPSR_SYSF_OP /*!< Operation in System Flash memory */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ + +/* Extended Program operation functions *************************************/ +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); +HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes); +void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +void HAL_FLASHEx_EnableSecHideProtection(uint32_t Banks); +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group2 + * @{ + */ +void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode); +uint32_t HAL_FLASHEx_GetPrivMode(void); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState); +uint32_t HAL_FLASHEx_GetSecInversion(void); +#endif /* __ARM_FEATURE_CMSE */ +HAL_StatusTypeDef HAL_FLASHEx_EnablePowerDown(uint32_t Banks); +HAL_StatusTypeDef HAL_FLASHEx_ConfigLowPowerRead(uint32_t ConfigLPM); +uint32_t HAL_FLASHEx_GetLowPowerRead(void); +void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation); +/** + * @} + */ + +/** + * @} + */ + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +void FLASH_PageErase(uint32_t Page, uint32_t Banks); +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Macros FLASH Private Macros + * @{ + */ +#define IS_FLASH_BB_EXCLUSIVE(CFG) (((CFG) == FLASH_BB_SEC) || \ + ((CFG) == FLASH_BB_PRIV)) + +#define IS_FLASH_CFGPRIVMODE(CFG) (((CFG) & 0xFFFFFFFCU) == 0U) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_FLASH_CFGSECINV(CFG) (((CFG) == FLASH_INV_DISABLE) || \ + ((CFG) == FLASH_INV_ENABLE)) +#endif /* __ARM_FEATURE_CMSE */ + +#define IS_FLASH_CFGLPM(CFG) (((CFG) == FLASH_LPM_DISABLE) || \ + ((CFG) == FLASH_LPM_ENABLE)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_FLASH_EX_H */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio.h new file mode 100644 index 000000000..61cdc0e63 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio.h @@ -0,0 +1,410 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_GPIO_H +#define STM32U5xx_HAL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be a value of @ref GPIO_pins */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ +} GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0U, + GPIO_PIN_SET +} GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ +/** @defgroup GPIO_pins GPIO pins + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) +#define GPIO_PIN_1 ((uint16_t)0x0002) +#define GPIO_PIN_2 ((uint16_t)0x0004) +#define GPIO_PIN_3 ((uint16_t)0x0008) +#define GPIO_PIN_4 ((uint16_t)0x0010) +#define GPIO_PIN_5 ((uint16_t)0x0020) +#define GPIO_PIN_6 ((uint16_t)0x0040) +#define GPIO_PIN_7 ((uint16_t)0x0080) +#define GPIO_PIN_8 ((uint16_t)0x0100) +#define GPIO_PIN_9 ((uint16_t)0x0200) +#define GPIO_PIN_10 ((uint16_t)0x0400) +#define GPIO_PIN_11 ((uint16_t)0x0800) +#define GPIO_PIN_12 ((uint16_t)0x1000) +#define GPIO_PIN_13 ((uint16_t)0x2000) +#define GPIO_PIN_14 ((uint16_t)0x4000) +#define GPIO_PIN_15 ((uint16_t)0x8000) +#define GPIO_PIN_ALL ((uint16_t)0xFFFF) + +#define GPIO_PIN_MASK (0x0000FFFFU) +/** + * @} + */ + +/** @defgroup GPIO_mode GPIO mode + * @brief GPIO Configuration Mode + * Elements values convention: 0xX0yz00YZ + * - X : GPIO mode or EXTI Mode + * - y : External IT or Event trigger detection + * - z : IO configuration on External IT or Event + * - Y : Output type (Push Pull or Open Drain) + * - Z : IO Direction mode (Input, Output, (Alternate or Analog) not applicable in case of LPGPIO) + * @{ + */ +/*!< Input Floating Mode */ +#define GPIO_MODE_INPUT (0x00000000U) +/*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_PP (0x00000001U) +/*!< Output Open Drain Mode */ +#define GPIO_MODE_OUTPUT_OD (0x00000011U) +/*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_PP (0x00000002U) +/*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_AF_OD (0x00000012U) +/*!< Analog Mode */ +#define GPIO_MODE_ANALOG (0x00000003U) +/*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_RISING (0x10110000U) +/*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_FALLING (0x10210000U) +/*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) +/*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_RISING (0x10120000U) +/*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (0x10220000U) +/*!< External Event Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) +/** + * @} + */ + +/** @defgroup GPIO_speed GPIO speed + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< High speed */ +#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< Very-high speed */ +/** + * @} + */ + +/** @defgroup GPIO_pull GPIO pull + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */ +#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */ +/** + * @} + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** @defgroup GPIO_attributes GPIO attributes + * @brief GPIO pin secure or non-secure attributes + * @{ + */ +#define GPIO_PIN_SEC (0x00000001U) /*!< Secure pin attribute */ +#define GPIO_PIN_NSEC (0x00000000U) /*!< Non-secure pin attribute */ +/** + * @} + */ + +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Check whether the specified EXTI line is rising edge asserted or not. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line rising pending bits. + * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is falling edge asserted or not. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line falling pending bits. + * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (__HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) || \ + __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending bits. + * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) \ + do { \ + __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__); \ + __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__); \ + } while(0) + + +/** + * @brief Generate a Software interrupt on selected EXTI line(s). + * @param __EXTI_LINE__: specifies the EXTI line to set. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) + +/** + * @brief Clear the EXTI line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) + +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) + +#define IS_GPIO_SINGLE_PIN(__PIN__) (((__PIN__) == GPIO_PIN_0) ||\ + ((__PIN__) == GPIO_PIN_1) ||\ + ((__PIN__) == GPIO_PIN_2) ||\ + ((__PIN__) == GPIO_PIN_3) ||\ + ((__PIN__) == GPIO_PIN_4) ||\ + ((__PIN__) == GPIO_PIN_5) ||\ + ((__PIN__) == GPIO_PIN_6) ||\ + ((__PIN__) == GPIO_PIN_7) ||\ + ((__PIN__) == GPIO_PIN_8) ||\ + ((__PIN__) == GPIO_PIN_9) ||\ + ((__PIN__) == GPIO_PIN_10) ||\ + ((__PIN__) == GPIO_PIN_11) ||\ + ((__PIN__) == GPIO_PIN_12) ||\ + ((__PIN__) == GPIO_PIN_13) ||\ + ((__PIN__) == GPIO_PIN_14) ||\ + ((__PIN__) == GPIO_PIN_15)) + +#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \ + (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u) + +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_MODE_AF_PP) ||\ + ((__MODE__) == GPIO_MODE_AF_OD) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING) ||\ + ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ + ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_ANALOG)) + +#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH)) + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ + ((__PULL__) == GPIO_PULLUP) || \ + ((__PULL__) == GPIO_PULLDOWN)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +#define IS_GPIO_PIN_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == GPIO_PIN_SEC) ||\ + ((__ATTRIBUTES__) == GPIO_PIN_NSEC)) + +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/* Include GPIO HAL Extended module */ +#include "stm32u5xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @brief GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet); +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** @defgroup GPIO_Exported_Functions_Group3 IO attributes management functions + * @{ + */ + +/* IO attributes management functions *****************************************/ +void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes); +HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, + uint32_t *pPinAttributes); + +/** + * @} + */ + +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_GPIO_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio_ex.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio_ex.h new file mode 100644 index 000000000..c3710473c --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio_ex.h @@ -0,0 +1,342 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_GPIO_EX_H +#define STM32U5xx_HAL_GPIO_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @brief GPIO Extended HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup LPGPIO_MapTypeDef GPIO/Ex Exported Types + * @{ + */ +typedef struct +{ + GPIO_TypeDef *GPIO_PORT; + uint32_t Pin_Pos; +} LPGPIO_MapTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection + * @{ + */ + +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50HZ ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_CSLEEP ((uint8_t)0x00) /* CSLEEP Alternate Function mapping */ +#define GPIO_AF0_CSTOP ((uint8_t)0x00) /* CSTOP Alternate Function mapping */ +#define GPIO_AF0_CRS ((uint8_t)0x00) /* CRS Alternate Function mapping */ +#define GPIO_AF0_SRDSTOP ((uint8_t)0x00) /* SRDSTOP Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */ +#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_LPTIM2 ((uint8_t)0x02) /* LPTIM2 Alternate Function mapping */ +#define GPIO_AF2_LPTIM3 ((uint8_t)0x02) /* LPTIM3 Alternate Function mapping */ +#if defined(I2C5) +#define GPIO_AF2_I2C5 ((uint8_t)0x02) /* I2C5 Alternate Function mapping */ +#endif /* I2C5 */ +#if defined(I2C6) +#define GPIO_AF2_I2C6 ((uint8_t)0x02) /* I2C6 Alternate Function mapping */ +#endif /* I2C6 */ +#if defined(GFXTIM) +#define GPIO_AF2_GFXTIM ((uint8_t)0x02) /* GFXTIM Alternate Function mapping */ +#endif /* GFXTIM */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */ +#define GPIO_AF3_OCTOSPI1 ((uint8_t)0x03) /* OCTOSPI1 Alternate Function mapping */ +#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */ +#define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */ +#define GPIO_AF3_TIM1 ((uint8_t)0x03) /* TIM1 Alternate Function mapping */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM8_COMP1 ((uint8_t)0x03) /* TIM8/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF3_TIM8_COMP2 ((uint8_t)0x03) /* TIM8/COMP2 Break in Alternate Function mapping */ +#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */ +#if defined(USART2) +#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */ +#endif /* USART2 */ +#define GPIO_AF3_ADF1 ((uint8_t)0x03) /* ADF1 Alternate Function mapping */ +#if defined(USB_OTG_HS) +#define GPIO_AF3_USB_HS ((uint8_t)0x03) /* USB_HS Alternate Function mapping */ +#endif /* USB_OTG_HS */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ +#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */ +#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */ +#define GPIO_AF4_LPTIM3 ((uint8_t)0x04) /* LPTIM3 Alternate Function mapping */ +#if defined (I2C5) +#define GPIO_AF4_I2C5 ((uint8_t)0x04) /* I2C5 Alternate Function mapping */ +#endif /* I2C5 */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */ +#define GPIO_AF5_OCTOSPI1 ((uint8_t)0x05) /* OCTOSPI1 Alternate Function mapping */ +#if defined(OCTOSPI2) +#define GPIO_AF5_OCTOSPI2 ((uint8_t)0x05) /* OCTOSPI2 Alternate Function mapping */ +#endif /* OCTOSPI2 */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */ +#define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */ +#define GPIO_AF5_MDF1 ((uint8_t)0x05) /* MDF1 Alternate Function mapping */ +#define GPIO_AF5_PSSI ((uint8_t)0x05) /* PSSI Alternate Function mapping */ +#if defined(GFXTIM) +#define GPIO_AF5_GFXTIM ((uint8_t)0x05) /* GFXTIM Alternate Function mapping */ +#endif /* GFXTIM */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_OCTOSPI1 ((uint8_t)0x06) /* OCTOSPI1 Alternate Function mapping */ +#if defined(OCTOSPI2) +#define GPIO_AF6_OCTOSPI2 ((uint8_t)0x06) /* OCTOSPI2 Alternate Function mapping */ +#endif /* OCTOPSI2 */ +#define GPIO_AF6_MDF1 ((uint8_t)0x06) /* MDF1 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ +#define GPIO_AF6_I2C3 ((uint8_t)0x06) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#if defined(USART2) +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#endif /* USART2 */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#if defined(USART6) +#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */ +#endif /* USART6 */ +#if defined(LTDC) +#define GPIO_AF7_LTDC ((uint8_t)0x07) /* LTDC Alternate Function mapping */ +#endif /* LTDC */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */ +#if defined(SDMMC2) +#define GPIO_AF8_SDMMC2 ((uint8_t)0x08) /* SDMMC2 Alternate Function mapping */ +#endif /* SDMMC2 */ +#if defined(LTDC) +#define GPIO_AF8_LTDC ((uint8_t)0x08) /* LTDC Alternate Function mapping */ +#endif /* LTDC */ +#if defined(HSPI1) +#define GPIO_AF8_HSPI1 ((uint8_t)0x08) /* HSPI1 Alternate Function mapping */ +#endif /* HSPI1 */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */ +#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_DCMI ((uint8_t)0x0A) /* DCMI Alternate Function mapping */ +#define GPIO_AF10_PSSI ((uint8_t)0x0A) /* PSSI Alternate Function mapping */ +#define GPIO_AF10_USB ((uint8_t)0x0A) /* USB Alternate Function mapping */ +#define GPIO_AF10_OCTOSPI1 ((uint8_t)0x0A) /* OCTOSPI1 Alternate Function mapping */ +#if defined(OCTOSPI2) +#define GPIO_AF10_OCTOSPI2 ((uint8_t)0x0A) /* OCTOSPI2 Alternate Function mapping */ +#endif /* OCTOSPI2 */ +#define GPIO_AF10_CRS ((uint8_t)0x0A) /* CRS Alternate Function mapping */ +#if defined(USB_OTG_HS) +#define GPIO_AF10_USB_HS ((uint8_t)0x0A) /* USB_HS Alternate Function mapping */ +#endif /* USB_OTG_HS */ +#if defined(DSI) +#define GPIO_AF10_DSI ((uint8_t)0x0A) /* DSI Alternate Function mapping */ +#endif /* DSI */ +#if defined(GFXTIM) +#define GPIO_AF10_GFXTIM ((uint8_t)0x0A) /* GFXTIM Alternate Function mapping */ +#endif /* GFXTIM */ + +/** + * @brief AF 11 selection + */ +#if defined(UCPD1) +#define GPIO_AF11_UCPD1 ((uint8_t)0x0B) /* UCPD1 Alternate Function mapping */ +#endif /* UCPD1 */ +#if defined(SDMMC2) +#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */ +#endif /* SDMMC2 */ +#define GPIO_AF11_LPGPIO1 ((uint8_t)0x0B) /* LPGPIO1 Alternate Function mapping */ +#if defined(FMC_BASE) +#define GPIO_AF11_FMC ((uint8_t)0x0B) /* FMC Alternate Function mapping */ +#endif /* FMC_BASE */ +#if defined(DSI) +#define GPIO_AF11_DSI ((uint8_t)0x0B) /* DSI Alternate Function mapping */ +#endif /* DSI */ +#if defined(GFXTIM) +#define GPIO_AF11_GFXTIM ((uint8_t)0x0B) /* GFXTIM Alternate Function mapping */ +#endif /* GFXTIM */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ +#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ +#if defined(FMC_BASE) +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#endif /* FMC_BASE */ +#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */ +#define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */ +#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ +#if defined(SDMMC2) +#define GPIO_AF12_SDMMC2 ((uint8_t)0x0C) /* SDMMC2 Alternate Function mapping */ +#endif /* SDMMC2 */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ +#if defined(SAI2) +#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */ +#endif /* SAI2 */ +#define GPIO_AF13_LPTIM4 ((uint8_t)0x0D) /* LPTIM4 Alternate Function mapping */ +#define GPIO_AF13_LPTIM2 ((uint8_t)0x0D) /* LPTIM2 Alternate Function mapping */ +#if defined(GFXTIM) +#define GPIO_AF13_GFXTIM ((uint8_t)0x0D) /* GFXTIM Alternate Function mapping */ +#endif /* GFXTIM */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */ +#define GPIO_AF14_LPTIM3 ((uint8_t)0x0E) /* LPTIM3 Alternate Function mapping */ +#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ +#define GPIO_AF14_TIM15_COMP1 ((uint8_t)0x0E) /* TIM15/COMP1 Alternate Function mapping */ +#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */ +#define GPIO_AF14_TIM16_COMP1 ((uint8_t)0x0E) /* TIM16/COMP1 Alternate Function mapping */ +#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */ +#define GPIO_AF14_TIM17_COMP1 ((uint8_t)0x0E) /* TIM17/COMP1 Alternate Function mapping */ +#if defined(FMC_BASE) +#define GPIO_AF14_FMC ((uint8_t)0x0E) /* FMC Alternate Function mapping */ +#endif /* FMC_BASE */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros + * @{ + */ + +/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index + * @{ + */ + +/* GPIO_Peripheral_Memory_Mapping Peripheral Memory Mapping */ +#define GPIO_GET_INDEX(__GPIOx__) (((uint32_t )(__GPIOx__) & (~GPIOA_BASE)) >> 10) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_GPIO_EX_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gtzc.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gtzc.h new file mode 100644 index 000000000..10749e0a1 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gtzc.h @@ -0,0 +1,675 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_gtzc.h + * @author MCD Application Team + * @brief Header file of GTZC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_GTZC_H +#define STM32U5xx_HAL_GTZC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup GTZC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup GTZC_Exported_Types GTZC Exported Types + * @{ + */ + +/*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */ +#if defined (SRAM5_BASE) +#define GTZC_MPCBB_NB_VCTR_REG_MAX (52U) /* Up to 52 super-blocks */ +#define GTZC_MPCBB_NB_LCK_VCTR_REG_MAX (2U) /* More than one 32-bit needed */ +#else +#define GTZC_MPCBB_NB_VCTR_REG_MAX (32U) /* Up to 32 super-blocks */ +#define GTZC_MPCBB_NB_LCK_VCTR_REG_MAX (1U) /* One 32-bit needed */ +#endif /* SRAM5_BASE */ + +typedef struct +{ + uint32_t MPCBB_SecConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for + a super-block. Each bit corresponds to a block + inside the super-block. 0 means non-secure, + 1 means secure */ + uint32_t MPCBB_PrivConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for + a super-block. Each bit corresponds to a block + inside the super-block. 0 means non-privilege, + 1 means privilege */ + uint32_t MPCBB_LockConfig_array[GTZC_MPCBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of + a super-block (32 blocks). 0 means unlocked, + 1 means locked */ +} MPCBB_Attribute_ConfigTypeDef; + +typedef struct +{ + uint32_t SecureRWIllegalMode; /*!< Secure read/write illegal access + field. It can be a value of @ref GTZC_MPCBB_SecureRWIllegalMode */ + uint32_t InvertSecureState; /*!< Default security state field (can be inverted or not). + It can be a value of @ref GTZC_MPCBB_InvertSecureState */ + MPCBB_Attribute_ConfigTypeDef AttributeConfig; /*!< MPCBB attribute configuration sub-structure */ +} MPCBB_ConfigTypeDef; + +typedef struct +{ + uint32_t AreaId; /*!< Area identifier field. It can be a value of @ref + GTZC_MPCWM_AreaId */ + uint32_t Offset; /*!< Offset of the watermark area, starting from the selected + memory base address. It must aligned on 128KB for FMC + and OCTOSPI memories, and on 32-byte for BKPSRAM */ + uint32_t Length; /*!< Length of the watermark area, starting from the selected + Offset. It must aligned on 128KB for FMC and OCTOSPI + memories, and on 32-byte for BKPSRAM */ + uint32_t Attribute; /*!< Attributes of the watermark area. It can be a value + of @ref GTZC_MPCWM_Attribute */ + uint32_t Lock; /*!< Lock of the watermark area. It can be a value + of @ref GTZC_MPCWM_Lock */ + uint32_t AreaStatus; /*!< Status of the watermark area. It can be set to + ENABLE or DISABLE */ +} MPCWM_ConfigTypeDef; + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ + +/** @defgroup GTZC_Private_Constants GTZC Private Constants + * @{ + */ + +/** @defgroup GTZC_Private_PeriphId_composition GTZC Peripheral identifier composition + * @{ + */ + +/* composition definition for Peripheral identifier parameter (PeriphId) used in + * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() + * functions and also in all HAL_GTZC_TZIC relative functions. + * Bitmap Definition + * bits[31:28] Field "register". Define the register index a peripheral belongs to. + * Each bit is dedicated to a single register. + * bit[5] Field "all peripherals". If this bit is set then the PeriphId targets + * all peripherals within all registers. + * bits[4:0] Field "bit position". Define the bit position within the + * register dedicated to the peripheral, value from 0 to 31. + */ +#define GTZC_PERIPH_REG_SHIFT (28U) +#define GTZC_PERIPH_REG (0xF0000000U) +#define GTZC1_PERIPH_REG1 (0x00000000U) +#define GTZC1_PERIPH_REG2 (0x10000000U) +#define GTZC1_PERIPH_REG3 (0x20000000U) +#define GTZC1_PERIPH_REG4 (0x30000000U) +#define GTZC2_PERIPH_REG1 (0x40000000U) +#define GTZC2_PERIPH_REG2 (0x50000000U) +#define GTZC_PERIPH_BIT_POSITION (0x0000001FU) + +/** + * @} + */ + +/** @defgroup GTZC_Private_Attributes_Msk GTZC Attributes Masks + * @{ + */ +#define GTZC_ATTR_SEC_MASK 0x100U +#define GTZC_ATTR_PRIV_MASK 0x200U + +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GTZC_Exported_Constants GTZC Exported Constants + * @{ + */ + +/** @defgroup GTZC_MPCBB_SecureRWIllegalMode GTZC MPCBB SRWILADIS values + * @{ + */ + +#define GTZC_MPCBB_SRWILADIS_ENABLE (0U) +#define GTZC_MPCBB_SRWILADIS_DISABLE (GTZC_MPCBB_CR_SRWILADIS_Msk) + +/** + * @} + */ + +/** @defgroup GTZC_MPCBB_InvertSecureState GTZC MPCBB INVSECSTATE values + * @{ + */ + +#define GTZC_MPCBB_INVSECSTATE_NOT_INVERTED (0U) +#define GTZC_MPCBB_INVSECSTATE_INVERTED (GTZC_MPCBB_CR_INVSECSTATE_Msk) + +/** + * @} + */ + +/** @defgroup GTZC_MPCWM_AreaId GTZC MPCWM area identifier values + * @{ + */ + +#define GTZC_TZSC_MPCWM_ID1 (0U) +#define GTZC_TZSC_MPCWM_ID2 (1U) + +/** + * @} + */ + +/** @defgroup GTZC_TZSC_TZIC_PeriphId GTZC TZSC and TZIC Peripheral identifier values + * @{ + */ +/* GTZC1 */ +#define GTZC_PERIPH_TIM2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM2_Pos) +#define GTZC_PERIPH_TIM3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM3_Pos) +#define GTZC_PERIPH_TIM4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM4_Pos) +#define GTZC_PERIPH_TIM5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM5_Pos) +#define GTZC_PERIPH_TIM6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM6_Pos) +#define GTZC_PERIPH_TIM7 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM7_Pos) +#define GTZC_PERIPH_WWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos) +#define GTZC_PERIPH_IWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos) +#define GTZC_PERIPH_SPI2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_SPI2_Pos) +#if defined (USART2) +#define GTZC_PERIPH_USART2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos) +#endif /* USART2 */ +#define GTZC_PERIPH_USART3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART3_Pos) +#define GTZC_PERIPH_UART4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART4_Pos) +#define GTZC_PERIPH_UART5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART5_Pos) +#define GTZC_PERIPH_I2C1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C1_Pos) +#define GTZC_PERIPH_I2C2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C2_Pos) +#define GTZC_PERIPH_CRS (GTZC1_PERIPH_REG1 | GTZC_CFGR1_CRS_Pos) +#define GTZC_PERIPH_I2C4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C4_Pos) +#define GTZC_PERIPH_LPTIM2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos) +#define GTZC_PERIPH_FDCAN1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_FDCAN1_Pos) +#if defined (UCPD1) +#define GTZC_PERIPH_UCPD1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UCPD1_Pos) +#endif /* UCPD1 */ +#if defined (USART6) +#define GTZC_PERIPH_USART6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART6_Pos) +#endif /* USART6 */ +#if defined (I2C5) +#define GTZC_PERIPH_I2C5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C5_Pos) +#endif /* I2C5 */ +#if defined (I2C6) +#define GTZC_PERIPH_I2C6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C6_Pos) +#endif /* I2C6 */ +#define GTZC_PERIPH_TIM1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM1_Pos) +#define GTZC_PERIPH_SPI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos) +#define GTZC_PERIPH_TIM8 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM8_Pos) +#define GTZC_PERIPH_USART1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_USART1_Pos) +#define GTZC_PERIPH_TIM15 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM15_Pos) +#define GTZC_PERIPH_TIM16 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos) +#define GTZC_PERIPH_TIM17 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos) +#define GTZC_PERIPH_SAI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos) +#if defined (SAI2) +#define GTZC_PERIPH_SAI2 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI2_Pos) +#endif /* SAI2 */ +#if defined (LTDC) || defined (USB_DRD_FS) +#define GTZC_PERIPH_LTDCUSB (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LTDCUSB_Pos) +#endif /* LTDC || USB_DRD_FS */ +#if defined (DSI) +#define GTZC_PERIPH_DSI (GTZC1_PERIPH_REG2 | GTZC_CFGR2_DSI_Pos) +#endif /* DSI */ +#if defined (GFXTIM) +#define GTZC_PERIPH_GFXTIM (GTZC1_PERIPH_REG2 | GTZC_CFGR2_GFXTIM_Pos) +#endif /* GFXTIM */ +#define GTZC_PERIPH_MDF1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_MDF1_Pos) +#define GTZC_PERIPH_CORDIC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CORDIC_Pos) +#define GTZC_PERIPH_FMAC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FMAC_Pos) +#define GTZC_PERIPH_CRC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos) +#define GTZC_PERIPH_TSC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_TSC_Pos) +#if defined (DMA2D) +#define GTZC_PERIPH_DMA2D (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DMA2D_Pos) +#endif /* DMA2D */ +#define GTZC_PERIPH_ICACHE_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ICACHE_REG_Pos) +#define GTZC_PERIPH_DCACHE1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCACHE1_REG_Pos) +#define GTZC_PERIPH_ADC12 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ADC12_Pos) +#define GTZC_PERIPH_DCMI_PSSI (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCMI_Pos) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define GTZC_PERIPH_OTG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OTG_Pos) +#endif /* (USB_OTG_FS) || (USB_OTG_HS) */ +#if defined (AES) +#define GTZC_PERIPH_AES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_AES_Pos) +#endif /* AES */ +#define GTZC_PERIPH_HASH (GTZC1_PERIPH_REG3 | GTZC_CFGR3_HASH_Pos) +#define GTZC_PERIPH_RNG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RNG_Pos) +#if defined (PKA) +#define GTZC_PERIPH_PKA (GTZC1_PERIPH_REG3 | GTZC_CFGR3_PKA_Pos) +#endif /* PKA */ +#if defined (SAES) +#define GTZC_PERIPH_SAES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SAES_Pos) +#endif /* SAES */ +#if defined (OCTOSPIM) +#define GTZC_PERIPH_OCTOSPIM (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPIM_Pos) +#endif /* OCTOSPIM */ +#define GTZC_PERIPH_SDMMC1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC1_Pos) +#if defined (SDMMC2) +#define GTZC_PERIPH_SDMMC2 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC2_Pos) +#endif /* SDMMC2 */ +#if defined (FMC_BASE) +#define GTZC_PERIPH_FSMC_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FSMC_REG_Pos) +#endif /* FMC_BASE */ +#define GTZC_PERIPH_OCTOSPI1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI1_REG_Pos) +#if defined (OCTOSPI2) +#define GTZC_PERIPH_OCTOSPI2_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI2_REG_Pos) +#endif /* OCTOSPI2 */ +#define GTZC_PERIPH_RAMCFG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RAMCFG_Pos) +#if defined (GPU2D) +#define GTZC_PERIPH_GPU2D (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GPU2D_Pos) +#endif /* GPU2D */ +#if defined (GFXMMU) +#define GTZC_PERIPH_GFXMMU (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GFXMMU_Pos) +#define GTZC_PERIPH_GFXMMU_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GFXMMU_REG_Pos) +#endif /* GFXMMU */ +#if defined (HSPI1) +#define GTZC_PERIPH_HSPI1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_HSPI1_REG_Pos) +#endif /* HSPI1 */ +#if defined (DCACHE2) +#define GTZC_PERIPH_DCACHE2_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCACHE2_REG_Pos) +#endif /* DCACHE2 */ +#if defined (JPEG) +#define GTZC_PERIPH_JPEG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_JPEG_Pos) +#endif /* JPEG */ +#define GTZC_PERIPH_GPDMA1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_GPDMA1_Pos) +#define GTZC_PERIPH_FLASH_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos) +#define GTZC_PERIPH_FLASH (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_Pos) +#if defined (OTFDEC2) +#define GTZC_PERIPH_OTFDEC2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC2_Pos) +#endif /* OTFDEC2 */ +#if defined (OTFDEC1) +#define GTZC_PERIPH_OTFDEC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC1_Pos) +#endif /* OTFDEC1 */ +#define GTZC_PERIPH_TZSC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZSC1_Pos) +#define GTZC_PERIPH_TZIC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZIC1_Pos) +#define GTZC_PERIPH_OCTOSPI1_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI1_MEM_Pos) +#if defined (FMC_BASE) +#define GTZC_PERIPH_FSMC_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FSMC_MEM_Pos) +#endif /* FMC_BASE */ +#define GTZC_PERIPH_BKPSRAM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_BKPSRAM_Pos) +#if defined (OCTOSPI2) +#define GTZC_PERIPH_OCTOSPI2_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI2_MEM_Pos) +#endif /* OCTOSPI2 */ +#if defined (HSPI1) +#define GTZC_PERIPH_HSPI1_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_HSPI1_MEM_Pos) +#endif /* HSPI1 */ +#if defined (SRAM6_BASE) +#define GTZC_PERIPH_SRAM6 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM6_Pos) +#define GTZC_PERIPH_MPCBB6_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB6_REG_Pos) +#endif /* SRAM6_BASE */ +#define GTZC_PERIPH_SRAM1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM1_Pos) +#define GTZC_PERIPH_MPCBB1_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos) +#define GTZC_PERIPH_SRAM2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos) +#define GTZC_PERIPH_MPCBB2_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos) +#if defined (SRAM3_BASE) +#define GTZC_PERIPH_SRAM3 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM3_Pos) +#endif /* SRAM3_BASE */ +#define GTZC_PERIPH_MPCBB3_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB3_REG_Pos) +#if defined (SRAM5_BASE) +#define GTZC_PERIPH_SRAM5 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM5_Pos) +#define GTZC_PERIPH_MPCBB5_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB5_REG_Pos) +#endif /* SRAM5_BASE */ + +/* GTZC2 */ +#define GTZC_PERIPH_SPI3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_SPI3_Pos) +#define GTZC_PERIPH_LPUART1 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPUART1_Pos) +#define GTZC_PERIPH_I2C3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_I2C3_Pos) +#define GTZC_PERIPH_LPTIM1 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPTIM1_Pos) +#define GTZC_PERIPH_LPTIM3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPTIM3_Pos) +#define GTZC_PERIPH_LPTIM4 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPTIM4_Pos) +#define GTZC_PERIPH_OPAMP (GTZC2_PERIPH_REG1 | GTZC_CFGR1_OPAMP_Pos) +#define GTZC_PERIPH_COMP (GTZC2_PERIPH_REG1 | GTZC_CFGR1_COMP_Pos) +#define GTZC_PERIPH_ADC4 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_ADC4_Pos) +#define GTZC_PERIPH_VREFBUF (GTZC2_PERIPH_REG1 | GTZC_CFGR1_VREFBUF_Pos) +#define GTZC_PERIPH_DAC1 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_DAC1_Pos) +#define GTZC_PERIPH_ADF1 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_ADF1_Pos) +#define GTZC_PERIPH_SYSCFG (GTZC2_PERIPH_REG2 | GTZC_CFGR2_SYSCFG_Pos) +#define GTZC_PERIPH_RTC (GTZC2_PERIPH_REG2 | GTZC_CFGR2_RTC_Pos) +#define GTZC_PERIPH_TAMP (GTZC2_PERIPH_REG2 | GTZC_CFGR2_TAMP_Pos) +#define GTZC_PERIPH_PWR (GTZC2_PERIPH_REG2 | GTZC_CFGR2_PWR_Pos) +#define GTZC_PERIPH_RCC (GTZC2_PERIPH_REG2 | GTZC_CFGR2_RCC_Pos) +#define GTZC_PERIPH_LPDMA1 (GTZC2_PERIPH_REG2 | GTZC_CFGR2_LPDMA1_Pos) +#define GTZC_PERIPH_EXTI (GTZC2_PERIPH_REG2 | GTZC_CFGR2_EXTI_Pos) +#define GTZC_PERIPH_TZSC2 (GTZC2_PERIPH_REG2 | GTZC_CFGR2_TZSC2_Pos) +#define GTZC_PERIPH_TZIC2 (GTZC2_PERIPH_REG2 | GTZC_CFGR2_TZIC2_Pos) +#define GTZC_PERIPH_SRAM4 (GTZC2_PERIPH_REG2 | GTZC_CFGR2_SRAM4_Pos) +#define GTZC_PERIPH_MPCBB4_REG (GTZC2_PERIPH_REG2 | GTZC_CFGR2_MPCBB4_REG_Pos) + +#define GTZC_PERIPH_ALL (0x00000020U) + +/* Note that two maximum values are also defined here: + * - max number of securable AHB/APB peripherals or masters + * (used in TZSC sub-block) + * - max number of securable and TrustZone-aware AHB/APB peripherals or masters + * (used in TZIC sub-block) + */ +#define GTZC_TZSC_PERIPH_NUMBER (HAL_GTZC_TZSC_GET_ARRAY_INDEX(GTZC_PERIPH_ADF1 + 1U)) +#define GTZC_TZIC_PERIPH_NUMBER (HAL_GTZC_TZIC_GET_ARRAY_INDEX(GTZC_PERIPH_MPCBB4_REG + 1U)) + +/** + * @} + */ + +/** @defgroup GTZC_TZSC_PeriphAttributes GTZC TZSC peripheral attribute values + * @{ + */ + +/* user-oriented definitions for attribute parameter (PeriphAttributes) used in + * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() + * functions + */ +#define GTZC_TZSC_PERIPH_SEC (GTZC_ATTR_SEC_MASK | 0x00000001U) /*!< Secure attribute */ +#define GTZC_TZSC_PERIPH_NSEC (GTZC_ATTR_SEC_MASK | 0x00000000U) /*!< Non-secure attribute */ +#define GTZC_TZSC_PERIPH_PRIV (GTZC_ATTR_PRIV_MASK | 0x00000002U) /*!< Privilege attribute */ +#define GTZC_TZSC_PERIPH_NPRIV (GTZC_ATTR_PRIV_MASK | 0x00000000U) /*!< Non-privilege attribute */ + +/** + * @} + */ + +/** @defgroup GTZC_TZSC_Lock GTZC TZSC lock values + * @{ + */ + +/* user-oriented definitions for HAL_GTZC_TZSC_GetLock() returned value */ +#define GTZC_TZSC_LOCK_OFF (0U) +#define GTZC_TZSC_LOCK_ON GTZC_TZSC_CR_LCK_Msk + +/** + * @} + */ + +/** @defgroup GTZC_MPCWM_Group GTZC MPCWM values + * @{ + */ + +/* user-oriented definitions for TZSC_MPCWM */ +#define GTZC_TZSC_MPCWM_GRANULARITY_1 0x00020000U /* OCTOSPI & FMC granularity: 128 kbytes */ +#define GTZC_TZSC_MPCWM_GRANULARITY_2 0x00000020U /* BKPSRAM granularity: 32 bytes */ + +/** + * @} + */ + +/** @defgroup GTZC_MPCWM_Lock GTZC MPCWM Lock values + * @{ + */ + +/* user-oriented definitions for TZSC_MPCWM */ +#define GTZC_TZSC_MPCWM_LOCK_OFF (0U) +#define GTZC_TZSC_MPCWM_LOCK_ON GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk + +/** + * @} + */ + +/** @defgroup GTZC_MPCWM_Attribute GTZC MPCWM Attribute values + * @{ + */ + +/* user-oriented definitions for TZSC_MPCWM */ +#define GTZC_TZSC_MPCWM_REGION_NSEC (0U) +#define GTZC_TZSC_MPCWM_REGION_SEC (1U) +#define GTZC_TZSC_MPCWM_REGION_NPRIV (0U) +#define GTZC_TZSC_MPCWM_REGION_PRIV (2U) + +/** + * @} + */ + +/** @defgroup GTZC_MPCBB_Group GTZC MPCBB values + * @{ + */ + +/* user-oriented definitions for MPCBB */ +#define GTZC_MPCBB_BLOCK_SIZE 0x200U /* 512 Bytes */ +#define GTZC_MPCBB_SUPERBLOCK_SIZE (GTZC_MPCBB_BLOCK_SIZE * 32U) /* 16 KBytes */ +#define GTZC_MPCBB_SUPERBLOCK_UNLOCKED (0U) +#define GTZC_MPCBB_SUPERBLOCK_LOCKED (1U) + +#define GTZC_MPCBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U) +#define GTZC_MPCBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U) +#define GTZC_MPCBB_BLOCK_NPRIV (GTZC_ATTR_PRIV_MASK | 0U) +#define GTZC_MPCBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U) + +/* user-oriented definitions for HAL_GTZC_MPCBB_GetLock() returned value */ +#define GTZC_MPCBB_LOCK_OFF (0U) +#define GTZC_MPCBB_LOCK_ON (1U) + +/** + * @} + */ + +/** @defgroup GTZC_TZIC_Flag GTZC TZIC flag values + * @{ + */ + +/* user-oriented definitions for HAL_GTZC_TZIC_GetFlag() flag parameter */ +#define GTZC_TZIC_NO_ILA_EVENT (0U) +#define GTZC_TZIC_ILA_EVENT_PENDING (1U) + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup GTZC_Private_Macros GTZC Private Macros + * @{ + */ + +/* retrieve information to access register for a specific PeriphId */ +#define GTZC_GET_REG_INDEX(periph_id)\ + (((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) +#define GTZC_GET_REG_INDEX_IN_INSTANCE(periph_id)\ + ((((periph_id) & GTZC_PERIPH_REG) <= GTZC1_PERIPH_REG4) ? \ + (((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) : \ + ((((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) - 4U)) +#define GTZC_GET_PERIPH_POS(periph_id) ((periph_id) & GTZC_PERIPH_BIT_POSITION) + +#define IS_GTZC_BASE_ADDRESS(mem, address)\ + ( ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) || \ + ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) ) + +#define GTZC_MEM_SIZE(mem)\ + ( mem ## _SIZE ) + +#define GTZC_BASE_ADDRESS_S(mem)\ + ( mem ## _BASE_S ) + +#define GTZC_BASE_ADDRESS_NS(mem)\ + ( mem ## _BASE_NS ) + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup GTZC_Exported_Macros GTZC Exported Macros + * @{ + */ + +/* user-oriented macro to get array index of a specific PeriphId + * in case of GTZC_PERIPH_ALL usage in the two following functions: + * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() + */ +#define HAL_GTZC_TZSC_GET_ARRAY_INDEX(periph_id) \ + (uint32_t)((HAL_GTZC_TZSC_GET_INSTANCE(periph_id) == GTZC_TZSC1)? \ + ((GTZC_GET_REG_INDEX(periph_id) * 32U) + GTZC_GET_PERIPH_POS(periph_id)) : \ + (((GTZC_GET_REG_INDEX(periph_id) - 1U) * 32U) + GTZC_GET_PERIPH_POS(periph_id) )) + +#define HAL_GTZC_TZIC_GET_ARRAY_INDEX(periph_id) \ + ( (GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id)) ) + +/* user-oriented macro to get TZSC instance of a specific PeriphId */ +#define HAL_GTZC_TZSC_GET_INSTANCE(periph_id) \ + ((GTZC_GET_REG_INDEX(periph_id) <= (GTZC1_PERIPH_REG4 >> GTZC_PERIPH_REG_SHIFT))? \ + GTZC_TZSC1 : GTZC_TZSC2) + +/* user-oriented macro to get TZIC instance of a specific PeriphId */ +#define HAL_GTZC_TZIC_GET_INSTANCE(periph_id) \ + ((GTZC_GET_REG_INDEX(periph_id) <= (GTZC1_PERIPH_REG4>> GTZC_PERIPH_REG_SHIFT))? \ + GTZC_TZIC1 : GTZC_TZIC2) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup GTZC_Exported_Functions + * @{ + */ + +/** @addtogroup GTZC_Exported_Functions_Group1 + * @brief TZSC Initialization and Configuration functions + * @{ + */ + +HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, + uint32_t PeriphAttributes); +HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, + uint32_t *PeriphAttributes); + +/** + * @} + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** @addtogroup GTZC_Exported_Functions_Group2 + * @brief MPCWM Initialization and Configuration functions + * @{ + */ + +HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, + const MPCWM_ConfigTypeDef *pMPCWM_Desc); +HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, + MPCWM_ConfigTypeDef *pMPCWM_Desc); +/** + * @} + */ + +/** @addtogroup GTZC_Exported_Functions_Group3 + * @brief TZSC and TZSC-MPCWM Lock functions + * @{ + */ + +void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance); +uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance); + +/** + * @} + */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/** @addtogroup GTZC_Exported_Functions_Group4 + * @brief MPCBB Initialization and Configuration functions + * @{ + */ + +HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, + const MPCBB_ConfigTypeDef *pMPCBB_desc); +HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, + MPCBB_ConfigTypeDef *pMPCBB_desc); +HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, + uint32_t NbBlocks, + const uint32_t *pMemAttributes); +HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, + uint32_t NbBlocks, + uint32_t *pMemAttributes); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, + uint32_t NbSuperBlocks, + const uint32_t *pLockAttributes); +HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, + uint32_t NbSuperBlocks, + uint32_t *pLockAttributes); +HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress); +HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, + uint32_t *pLockState); +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @} + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** @addtogroup GTZC_Exported_Functions_Group5 + * @brief TZIC functions + * @{ + */ + +HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId); +HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId); +HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag); +HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId); + +/** + * @} + */ + +/** @addtogroup GTZC_Exported_Functions_Group6 + * @brief IRQ related Functions + * @{ + */ + +void HAL_GTZC_IRQHandler(void); +void HAL_GTZC_TZIC_Callback(uint32_t PeriphId); + +/** + * @} + */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_GTZC_H */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c.h new file mode 100644 index 000000000..d37fb0e2a --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c.h @@ -0,0 +1,846 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_I2C_H +#define STM32U5xx_HAL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + * @brief I2C Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter calculated by referring to I2C initialization section + in Reference manual */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing + mode is selected. + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ + +} I2C_InitTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap :\n + * b7-b6 Error information\n + * 00 : No Error\n + * 01 : Abort (Abort user request on going)\n + * 10 : Timeout\n + * 11 : Error\n + * b5 Peripheral initialization status\n + * 0 : Reset (peripheral not initialized)\n + * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n + * b4 (not used)\n + * x : Should be set to 0\n + * b3\n + * 0 : Ready or Busy (No Listen mode ongoing)\n + * 1 : Listen (peripheral in Address Listen Mode)\n + * b2 Intrinsic process state\n + * 0 : Ready\n + * 1 : Busy (peripheral busy with some configuration or internal operations)\n + * b1 Rx state\n + * 0 : Ready (no Rx operation ongoing)\n + * 1 : Busy (Rx operation ongoing)\n + * b0 Tx state\n + * 0 : Ready (no Tx operation ongoing)\n + * 1 : Busy (Tx operation ongoing) + * @{ + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + +} HAL_I2C_StateTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +} HAL_I2C_ModeTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ +#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ +/** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ +typedef struct __I2C_HandleTypeDef +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can + be a value of @ref I2C_XFEROPTIONS */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state */ + + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); + /*!< I2C transfer IRQ handler function pointer */ + +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + +#endif /*HAL_DMA_MODULE_ENABLED*/ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ + + __IO uint32_t Devaddress; /*!< I2C Target device address */ + + __IO uint32_t Memaddress; /*!< I2C Target memory address */ + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp DeInit callback */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} I2C_HandleTypeDef; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief HAL I2C Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ + HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ + HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ + HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ + HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ + HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ + HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ + HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ + HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ + + HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ + HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ + +} HAL_I2C_CallbackIDTypeDef; + +/** + * @brief HAL I2C Callback pointer definition + */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); +/*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an I2C Address Match callback function */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options + * @{ + */ +#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define I2C_OTHER_FRAME (0x000000AAU) +#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U) +/** + * @} + */ + +/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE (0x00000000U) +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN +/** + * @} + */ + +/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks + * @{ + */ +#define I2C_OA2_NOMASK ((uint8_t)0x00U) +#define I2C_OA2_MASK01 ((uint8_t)0x01U) +#define I2C_OA2_MASK02 ((uint8_t)0x02U) +#define I2C_OA2_MASK03 ((uint8_t)0x03U) +#define I2C_OA2_MASK04 ((uint8_t)0x04U) +#define I2C_OA2_MASK05 ((uint8_t)0x05U) +#define I2C_OA2_MASK06 ((uint8_t)0x06U) +#define I2C_OA2_MASK07 ((uint8_t)0x07U) +/** + * @} + */ + +/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE (0x00000000U) +#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN +/** + * @} + */ + +/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE (0x00000000U) +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT (0x00000001U) +#define I2C_MEMADD_SIZE_16BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View + * @{ + */ +#define I2C_DIRECTION_TRANSMIT (0x00000000U) +#define I2C_DIRECTION_RECEIVE (0x00000001U) +/** + * @} + */ + +/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode + * @{ + */ +#define I2C_RELOAD_MODE I2C_CR2_RELOAD +#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND +#define I2C_SOFTEND_MODE (0x00000000U) +/** + * @} + */ + +/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode + * @{ + */ +#define I2C_NO_STARTSTOP (0x00000000U) +#define I2C_GENERATE_NO_START_READ (uint32_t)(0x80000000U | I2C_CR2_RD_WRN) +#define I2C_GENERATE_NO_START_WRITE (uint32_t)(0x80000000U) +#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define I2C_IT_ERRI I2C_CR1_ERRIE +#define I2C_IT_TCI I2C_CR1_TCIE +#define I2C_IT_STOPI I2C_CR1_STOPIE +#define I2C_IT_NACKI I2C_CR1_NACKIE +#define I2C_IT_ADDRI I2C_CR1_ADDRIE +#define I2C_IT_RXI I2C_CR1_RXIE +#define I2C_IT_TXI I2C_CR1_TXIE +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_AF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY +#define I2C_FLAG_DIR I2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** @brief Enable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified I2C interrupt source is enabled or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_TXIS Transmit interrupt status + * @arg @ref I2C_FLAG_RXNE Receive data register not empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_TC Transfer complete (master mode) + * @arg @ref I2C_FLAG_TCR Transfer complete reload + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * @arg @ref I2C_FLAG_BUSY Bus busy + * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define I2C_FLAG_MASK (0x0001FFFFU) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) + +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) +/** + * @} + */ + +/* Include I2C HAL Extended module */ +#include "stm32u5xx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions******************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions ****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + +#if defined(HAL_DMA_MODULE_ENABLED) +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +#endif /*HAL_DMA_MODULE_ENABLED*/ +/** + * @} + */ + +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @{ + */ +/* Peripheral State, Mode and Error functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ + +#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) + +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) + +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) + +#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) + +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_GENERATE_NO_START_READ) || \ + ((REQUEST) == I2C_GENERATE_NO_START_WRITE)|| \ + ((REQUEST) == I2C_NO_STARTSTOP)) + +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ + ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) + +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN))) + +#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \ + >> 16U)) +#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \ + >> 16U)) +#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) +#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ + (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) + +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ + (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_ADD10) | (I2C_CR2_START) | \ + (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN))) + +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ + ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions are defined in stm32u5xx_hal_i2c.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32U5xx_HAL_I2C_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c_ex.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c_ex.h new file mode 100644 index 000000000..19067fcdb --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c_ex.h @@ -0,0 +1,312 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_I2C_EX_H +#define STM32U5xx_HAL_I2C_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Autonomous_Mode_Configuration_Structure_definition Autonomous Mode Configuration Structure definition + * @brief I2C Autonomous Mode Configuration structure definition + * @{ + */ +typedef struct +{ + uint32_t TriggerState; /*!< Specifies the trigger state. This parameter can be a value + of @ref I2CEx_AutonomousMode_FunctionalState */ + + uint32_t TriggerSelection; /*!< Specifies the autonomous mode trigger signal selection. This parameter + can be a value of @ref I2CEx_AutonomousMode_TriggerSelection */ + + uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity sensitivity. This parameter + can be a value of @ref I2CEx_AutonomousMode_TriggerPolarity */ + +} I2C_AutonomousModeConfTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +/** + * @} + */ + +/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus + * @{ + */ +#define I2C_FASTMODEPLUS_ENABLE 0x00000000U /*!< Enable Fast Mode Plus */ +#define I2C_FASTMODEPLUS_DISABLE 0x00000001U /*!< Disable Fast Mode Plus */ +/** + * @} + */ + +/** @defgroup I2CEx_AutonomousMode_FunctionalState I2C Extended Autonomous Mode State + * @{ + */ +#define I2C_AUTO_MODE_DISABLE (0x00000000U) /*!< Autonomous mode disable */ +#define I2C_AUTO_MODE_ENABLE I2C_AUTOCR_TRIGEN /*!< Autonomous mode enable */ +/** + * @} + */ + +/** @defgroup I2CEx_AutonomousMode_TriggerSelection I2C Extended Autonomous Mode Trigger Selection + * @{ + */ +#define I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2, I2C4, I2C5, I2C6 (depends on Product) */ +#define I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ + +#define I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x00000000UL)) +/*!< HW Trigger signal is GPDMA_CH0_TRG */ +#define I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH1_TRG */ +#define I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH2_TRG */ +#define I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH3_TRG */ +#define I2C_GRP1_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI5_TRG */ +#define I2C_GRP1_EXTI9_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI9_TRG */ +#define I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x6UL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM1_CH1_TRG */ +#define I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x7UL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM2_CH1_TRG */ +#define I2C_GRP1_COMP1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x8UL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP1_TRG */ +#define I2C_GRP1_COMP2_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x9UL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP2_TRG */ +#define I2C_GRP1_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xAUL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_ALRA_TRG */ +#define I2C_GRP1_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xBUL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_WUT_TRG */ + +#define I2C_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x00000000UL)) +/*!< HW Trigger signal is LPDMA_CH0_TRG */ +#define I2C_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPDMA_CH1_TRG */ +#define I2C_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPDMA_CH2_TRG */ +#define I2C_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPDMA_CH3_TRG */ +#define I2C_GRP2_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI5_TRG */ +#define I2C_GRP2_EXTI8_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI8_TRG */ +#define I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x6UL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM1_CH1_TRG */ +#define I2C_GRP2_LPTIM3_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x7UL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM3_CH1_TRG */ +#define I2C_GRP2_COMP1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x8UL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP1_TRG */ +#define I2C_GRP2_COMP2_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x9UL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP2_TRG */ +#define I2C_GRP2_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xAUL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_ALRA_TRG */ +#define I2C_GRP2_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xBUL << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_WUT_TRG */ +/** + * @} + */ + +/** @defgroup I2CEx_AutonomousMode_TriggerPolarity Extended Autonomous Mode Trigger Polarity + * @{ + */ +#define I2C_TRIG_POLARITY_RISING (0x00000000U) /*!< I2C HW Trigger signal on rising edge */ +#define I2C_TRIG_POLARITY_FALLING I2C_AUTOCR_TRIGPOL /*!< I2C HW Trigger signal on falling edge */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @{ + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @{ + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group4 Autonomous Mode Functions + * @{ + */ +HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, + const I2C_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_I2CEx_GetConfigAutonomousMode(const I2C_HandleTypeDef *hi2c, + I2C_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#define IS_I2C_FASTMODEPLUS(__CONFIG__) (((__CONFIG__) == (I2C_FASTMODEPLUS_ENABLE)) || \ + ((__CONFIG__) == (I2C_FASTMODEPLUS_DISABLE))) + +#define IS_I2C_AUTO_MODE(__MODE__) (((__MODE__) == I2C_AUTO_MODE_DISABLE) || \ + ((__MODE__) == I2C_AUTO_MODE_ENABLE)) + +#define IS_I2C_TRIG_SOURCE(__INSTANCE__, __SOURCE__) (((__INSTANCE__) == I2C3) ? \ + IS_I2C_GRP2_TRIG_SOURCE(__SOURCE__) : \ + IS_I2C_GRP1_TRIG_SOURCE(__SOURCE__)) + +#define IS_I2C_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == I2C_GRP1_GPDMA_CH0_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_GPDMA_CH1_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_GPDMA_CH2_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_GPDMA_CH3_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_EXTI5_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_EXTI9_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_LPTIM1_CH1_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_LPTIM2_CH1_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_COMP1_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_COMP2_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_RTC_ALRA_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_RTC_WUT_TRG )) + +#define IS_I2C_GRP2_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == I2C_GRP2_LPDMA_CH0_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_LPDMA_CH1_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_LPDMA_CH2_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_LPDMA_CH3_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_EXTI5_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_EXTI8_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_LPTIM1_CH1_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_LPTIM3_CH1_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_COMP1_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_COMP2_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_RTC_ALRA_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_RTC_WUT_TRG )) + +#define IS_I2C_TRIG_INPUT_INSTANCE(__INSTANCE__) (IS_I2C_GRP1_INSTANCE(__INSTANCE__) || \ + IS_I2C_GRP2_INSTANCE(__INSTANCE__)) + +#define IS_I2C_AUTO_MODE_TRG_POL(__POLARITY__) (((__POLARITY__) == I2C_TRIG_POLARITY_RISING) || \ + ((__POLARITY__) == I2C_TRIG_POLARITY_FALLING)) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32u5xx_hal_i2c_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_I2C_EX_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_icache.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_icache.h new file mode 100644 index 000000000..2f200ccec --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_icache.h @@ -0,0 +1,294 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_icache.h + * @author MCD Application Team + * @brief Header file of ICACHE HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion ------------------------------------*/ +#ifndef STM32U5xx_HAL_ICACHE_H +#define STM32U5xx_HAL_ICACHE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -----------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +#if defined(ICACHE) +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup ICACHE + * @{ + */ + +/* Exported types -----------------------------------------------------------*/ +/** @defgroup ICACHE_Exported_Types ICACHE Exported Types + * @{ + */ + +/** + * @brief HAL ICACHE region configuration structure definition + */ +typedef struct +{ + uint32_t BaseAddress; /*!< Configures the Base address of Region i to be remapped */ + + uint32_t RemapAddress; /*!< Configures the Remap address of Region i to be remapped */ + + uint32_t Size; /*!< Configures the Region size. + This parameter can be a value of @ref ICACHE_Region_Size */ + + uint32_t TrafficRoute; /*!< Selects the traffic route. + This parameter can be a value of @ref ICACHE_Traffic_Route */ + + uint32_t OutputBurstType; /*!< Selects the output burst type. + This parameter can be a value of @ref ICACHE_Output_Burst_Type */ +} ICACHE_RegionConfigTypeDef; +/** + * @} + */ + +/* Exported constants -------------------------------------------------------*/ +/** @defgroup ICACHE_Exported_Constants ICACHE Exported Constants + * @{ + */ + +/** @defgroup ICACHE_WaysSelection Ways selection + * @{ + */ +#define ICACHE_1WAY 0UL /*!< 1-way cache (direct mapped cache) */ +#define ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */ +/** + * @} + */ + +/** @defgroup ICACHE_Monitor_Type Monitor type + * @{ + */ +#define ICACHE_MONITOR_HIT_MISS (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< Hit & Miss monitoring */ +#define ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitoring */ +#define ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitoring */ +/** + * @} + */ + +/** @defgroup ICACHE_Region Remapped Region number + * @{ + */ +#define ICACHE_REGION_0 0UL /*!< Region 0 */ +#define ICACHE_REGION_1 1UL /*!< Region 1 */ +#define ICACHE_REGION_2 2UL /*!< Region 2 */ +#define ICACHE_REGION_3 3UL /*!< Region 3 */ +/** + * @} + */ + +/** @defgroup ICACHE_Region_Size Remapped Region size + * @{ + */ +#define ICACHE_REGIONSIZE_2MB 1UL /*!< Region size 2MB */ +#define ICACHE_REGIONSIZE_4MB 2UL /*!< Region size 4MB */ +#define ICACHE_REGIONSIZE_8MB 3UL /*!< Region size 8MB */ +#define ICACHE_REGIONSIZE_16MB 4UL /*!< Region size 16MB */ +#define ICACHE_REGIONSIZE_32MB 5UL /*!< Region size 32MB */ +#define ICACHE_REGIONSIZE_64MB 6UL /*!< Region size 64MB */ +#define ICACHE_REGIONSIZE_128MB 7UL /*!< Region size 128MB */ +/** + * @} + */ + +/** @defgroup ICACHE_Traffic_Route Remapped Traffic route + * @{ + */ +#define ICACHE_MASTER1_PORT 0UL /*!< Master1 port */ +#define ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */ +/** + * @} + */ + +/** @defgroup ICACHE_Output_Burst_Type Remapped Output burst type + * @{ + */ +#define ICACHE_OUTPUT_BURST_WRAP 0UL /*!< WRAP */ +#define ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */ +/** + * @} + */ + +/** @defgroup ICACHE_Interrupts Interrupts + * @{ + */ +#define ICACHE_IT_BUSYEND ICACHE_IER_BSYENDIE /*!< Busy end interrupt */ +#define ICACHE_IT_ERROR ICACHE_IER_ERRIE /*!< Cache error interrupt */ +/** + * @} + */ + +/** @defgroup ICACHE_Flags Flags + * @{ + */ +#define ICACHE_FLAG_BUSY ICACHE_SR_BUSYF /*!< Busy flag */ +#define ICACHE_FLAG_BUSYEND ICACHE_SR_BSYENDF /*!< Busy end flag */ +#define ICACHE_FLAG_ERROR ICACHE_SR_ERRF /*!< Cache error flag */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ----------------------------------------------------------*/ +/** @defgroup ICACHE_Exported_Macros ICACHE Exported Macros + * @{ + */ + +/** @defgroup ICACHE_Flags_Interrupts_Management Flags and Interrupts Management + * @brief macros to manage the specified ICACHE flags and interrupts. + * @{ + */ + +/** @brief Enable ICACHE interrupts. + * @param __INTERRUPT__ specifies the ICACHE interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt + * @arg @ref ICACHE_IT_ERROR Cache error interrupt + */ +#define __HAL_ICACHE_ENABLE_IT(__INTERRUPT__) SET_BIT(ICACHE->IER, (__INTERRUPT__)) + +/** @brief Disable ICACHE interrupts. + * @param __INTERRUPT__ specifies the ICACHE interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt + * @arg @ref ICACHE_IT_ERROR Cache error interrupt + */ +#define __HAL_ICACHE_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(ICACHE->IER, (__INTERRUPT__)) + +/** @brief Check whether the specified ICACHE interrupt source is enabled or not. + * @param __INTERRUPT__ specifies the ICACHE interrupt source to check. + * This parameter can be any combination of the following values: + * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt + * @arg @ref ICACHE_IT_ERROR Cache error interrupt + * @retval The state of __INTERRUPT__ (0 or 1). + */ +#define __HAL_ICACHE_GET_IT_SOURCE(__INTERRUPT__) \ + ((READ_BIT(ICACHE->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U) + +/** @brief Check whether the selected ICACHE flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref ICACHE_FLAG_BUSY Busy flag + * @arg @ref ICACHE_FLAG_BUSYEND Busy end flag + * @arg @ref ICACHE_FLAG_ERROR Cache error flag + * @retval The state of __FLAG__ (0 or 1). + */ +#define __HAL_ICACHE_GET_FLAG(__FLAG__) ((READ_BIT(ICACHE->SR, (__FLAG__)) != 0U) ? 1U : 0U) + +/** @brief Clear the selected ICACHE flags. + * @param __FLAG__ specifies the ICACHE flags to clear. + * This parameter can be any combination of the following values: + * @arg @ref ICACHE_FLAG_BUSYEND Busy end flag + * @arg @ref ICACHE_FLAG_ERROR Cache error flag + */ +#define __HAL_ICACHE_CLEAR_FLAG(__FLAG__) WRITE_REG(ICACHE->FCR, (__FLAG__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions -------------------------------------------------------*/ +/** @addtogroup ICACHE_Exported_Functions + * @{ + */ + +/** @addtogroup ICACHE_Exported_Functions_Group1 + * @brief Initialization and control functions + * @{ + */ +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_ICACHE_Enable(void); +HAL_StatusTypeDef HAL_ICACHE_Disable(void); +uint32_t HAL_ICACHE_IsEnabled(void); +HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode); +HAL_StatusTypeDef HAL_ICACHE_DeInit(void); + +/******* Invalidate in blocking mode (Polling) */ +HAL_StatusTypeDef HAL_ICACHE_Invalidate(void); +/******* Invalidate in non-blocking mode (Interrupt) */ +HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void); +/******* Wait for Invalidate complete in blocking mode (Polling) */ +HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void); + +/******* Performance instruction cache monitoring functions */ +HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType); +HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType); +HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType); +uint32_t HAL_ICACHE_Monitor_GetHitValue(void); +uint32_t HAL_ICACHE_Monitor_GetMissValue(void); + +/** + * @} + */ + +/** @addtogroup ICACHE_Exported_Functions_Group2 + * @brief IRQ and callback functions + * @{ + */ +/******* IRQHandler and Callbacks used in non-blocking mode (Interrupt) */ +void HAL_ICACHE_IRQHandler(void); +void HAL_ICACHE_InvalidateCompleteCallback(void); +void HAL_ICACHE_ErrorCallback(void); + +/** + * @} + */ + +/** @addtogroup ICACHE_Exported_Functions_Group3 + * @brief Memory remapped regions functions + * @{ + */ +/******* Memory remapped regions functions */ +HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig); +HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* ICACHE */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_ICACHE_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr.h new file mode 100644 index 000000000..c44722dc9 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr.h @@ -0,0 +1,813 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_PWR_H +#define STM32U5xx_HAL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< Specifies the PVD detection level. + This parameter can be a value of + @ref PWR_PVD_Detection_Level. */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode. */ +} PWR_PVDTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_PVD_Detection_Level Programmable Voltage Detection Level + * @{ + */ +#define PWR_PVDLEVEL_0 0x00000000UL /*!< PVD threshold around 2.0 V */ +#define PWR_PVDLEVEL_1 (PWR_SVMCR_PVDLS_0) /*!< PVD threshold around 2.2 V */ +#define PWR_PVDLEVEL_2 (PWR_SVMCR_PVDLS_1) /*!< PVD threshold around 2.4 V */ +#define PWR_PVDLEVEL_3 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_1) /*!< PVD threshold around 2.5 V */ +#define PWR_PVDLEVEL_4 (PWR_SVMCR_PVDLS_2) /*!< PVD threshold around 2.6 V */ +#define PWR_PVDLEVEL_5 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_2) /*!< PVD threshold around 2.8 V */ +#define PWR_PVDLEVEL_6 (PWR_SVMCR_PVDLS_1 | PWR_SVMCR_PVDLS_2) /*!< PVD threshold around 2.9 V */ +#define PWR_PVDLEVEL_7 (PWR_SVMCR_PVDLS) /*!< External input analog voltage + (compared internally to VREFINT) */ +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL (0x00U) /*!< Basic Mode is used */ +#define PWR_PVD_MODE_IT_RISING (0x05U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING (0x06U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING (0x07U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING (0x09U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING (0x0AU) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x0BU) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWR_Regulator_In_LowPower_Mode PWR Regulator State in Sleep/Stop Mode + * @{ + */ +#define PWR_MAINREGULATOR_ON (0x00U) /*!< Main Regulator ON in Run Mode */ +#define PWR_LOWPOWERREGULATOR_ON (0x00U) /*!< Main Regulator ON in Low Power Mode */ +/** + * @} + */ + +/** @defgroup PWR_Sleep_Mode_Entry PWR Sleep Mode Entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Sleep mode */ +#define PWR_SLEEPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Sleep mode */ +#define PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR (0x03U) +/** + * @} + */ + +/** @defgroup PWR_Stop_Mode_Entry PWR Stop Mode Entry + * @{ + */ +#define PWR_STOPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Stop mode */ +#define PWR_STOPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Stop mode */ +#define PWR_STOPENTRY_WFE_NO_EVT_CLEAR (0x03U) +/** + * @} + */ + +/** @defgroup PWR_Flags PWR Flags + * @{ + */ +#define PWR_FLAG_VOSRDY (0x01U) /*!< Voltage scaling ready flag */ +#define PWR_FLAG_BOOSTRDY (0x02U) /*!< EPOD booster ready flag */ +#define PWR_FLAG_STOPF (0x03U) /*!< Stop flag */ +#define PWR_FLAG_SBF (0x04U) /*!< Standby flag */ +#define PWR_FLAG_VDDA2RDY (0x05U) /*!< VDDA ready flag (versus 1.8 V threshold) */ +#define PWR_FLAG_VDDA1RDY (0x06U) /*!< VDDA ready flag (versus 1.6 V threshold) */ +#define PWR_FLAG_VDDIO2RDY (0x07U) /*!< VDDIO2 ready flag */ +#define PWR_FLAG_VDDUSBRDY (0x08U) /*!< VDDUSB ready flag */ +#define PWR_FLAG_ACTVOSRDY (0x09U) /*!< Currently applied VOS ready flag */ +#define PWR_FLAG_PVDO (0x0AU) /*!< VDD voltage detector output flag */ +#define PWR_FLAG_REGS (0x0BU) /*!< Regulator selection flag */ +#define PWR_FLAG_TEMPH (0x0CU) /*!< Temperature level flag (versus high threshold) */ +#define PWR_FLAG_TEMPL (0x0DU) /*!< Temperature level flag (versus low threshold) */ +#define PWR_FLAG_VBATH (0x0EU) /*!< Backup domain voltage level flag (versus high threshold) */ +#if defined (PWR_VOSR_USBBOOSTRDY) +#define PWR_FLAG_USBBOOSTRDY (0x0FU) /*!< USB EPOD booster ready flag */ +#endif /* defined (PWR_VOSR_USBBOOSTRDY) */ +/** + * @} + */ + +/** @defgroup PWR_WakeUp_Lines_Flags PWR Wakeup Lines Flags + * @{ + */ +#define PWR_WAKEUP_FLAG1 (0x10U) /*!< Wakeup flag 1 */ +#define PWR_WAKEUP_FLAG2 (0x20U) /*!< Wakeup flag 2 */ +#define PWR_WAKEUP_FLAG3 (0x30U) /*!< Wakeup flag 3 */ +#define PWR_WAKEUP_FLAG4 (0x40U) /*!< Wakeup flag 4 */ +#define PWR_WAKEUP_FLAG5 (0x50U) /*!< Wakeup flag 5 */ +#define PWR_WAKEUP_FLAG6 (0x60U) /*!< Wakeup flag 6 */ +#define PWR_WAKEUP_FLAG7 (0x70U) /*!< Wakeup flag 7 */ +#define PWR_WAKEUP_FLAG8 (0x80U) /*!< Wakeup flag 8 */ +#define PWR_WAKEUP_ALL_FLAG (0x90U) /*!< Wakeup flag all */ +/** + * @} + */ + +/** @defgroup PWR_WakeUp_Pin_High_Polarity PWR Wake Up Pins High Polarity + * @{ + */ +#define PWR_WAKEUP_PIN1_HIGH_0 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_SOURCE_SELECTION_0) /*!< PA0 : Wakeup pin 1 (high polarity) */ +#define PWR_WAKEUP_PIN1_HIGH_1 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_SOURCE_SELECTION_1) /*!< PB2 : Wakeup pin 1 (high polarity) */ +#define PWR_WAKEUP_PIN1_HIGH_2 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_SOURCE_SELECTION_2) /*!< PE4 : Wakeup pin 1 (high polarity) */ + +#define PWR_WAKEUP_PIN2_HIGH_0 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_SOURCE_SELECTION_0) /*!< PA4 : Wakeup pin 2 (high polarity) */ +#define PWR_WAKEUP_PIN2_HIGH_1 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_SOURCE_SELECTION_1) /*!< PC13 : Wakeup pin 2 (high polarity) */ +#define PWR_WAKEUP_PIN2_HIGH_2 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_SOURCE_SELECTION_2) /*!< PE5 : Wakeup pin 2 (high polarity) */ + +#define PWR_WAKEUP_PIN3_HIGH_0 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_SOURCE_SELECTION_0) /*!< PE6 : Wakeup pin 3 (high polarity) */ +#define PWR_WAKEUP_PIN3_HIGH_1 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_SOURCE_SELECTION_1) /*!< PA1 : Wakeup pin 3 (high polarity) */ +#define PWR_WAKEUP_PIN3_HIGH_2 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_SOURCE_SELECTION_2) /*!< PB6 : Wakeup pin 3 (high polarity) */ + +#define PWR_WAKEUP_PIN4_HIGH_0 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_SOURCE_SELECTION_0) /*!< PA2 : Wakeup pin 4 (high polarity) */ +#define PWR_WAKEUP_PIN4_HIGH_1 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_SOURCE_SELECTION_1) /*!< PB1 : Wakeup pin 4 (high polarity) */ +#define PWR_WAKEUP_PIN4_HIGH_2 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_SOURCE_SELECTION_2) /*!< PB7 : Wakeup pin 4 (high polarity) */ + +#define PWR_WAKEUP_PIN5_HIGH_0 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_SOURCE_SELECTION_0) /*!< PC5 : Wakeup pin 5 (high polarity) */ +#define PWR_WAKEUP_PIN5_HIGH_1 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_SOURCE_SELECTION_1) /*!< PA3 : Wakeup pin 5 (high polarity) */ +#define PWR_WAKEUP_PIN5_HIGH_2 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_SOURCE_SELECTION_2) /*!< PB8 : Wakeup pin 5 (high polarity) */ + +#define PWR_WAKEUP_PIN6_HIGH_0 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_SOURCE_SELECTION_0) /*!< PB5 : Wakeup pin 6 (high polarity) */ +#define PWR_WAKEUP_PIN6_HIGH_1 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_SOURCE_SELECTION_1) /*!< PA5 : Wakeup pin 6 (high polarity) */ +#define PWR_WAKEUP_PIN6_HIGH_2 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_SOURCE_SELECTION_2) /*!< PE7 : Wakeup pin 6 (high polarity) */ +#define PWR_WAKEUP_PIN6_HIGH_3 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 6 (high polarity) */ + +#define PWR_WAKEUP_PIN7_HIGH_0 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_SOURCE_SELECTION_0) /*!< PB15 : Wakeup pin 7 (high polarity) */ +#define PWR_WAKEUP_PIN7_HIGH_1 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_SOURCE_SELECTION_1) /*!< PA6 : Wakeup pin 7 (high polarity) */ +#define PWR_WAKEUP_PIN7_HIGH_2 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_SOURCE_SELECTION_2) /*!< PE8 : Wakeup pin 7 (high polarity) */ +#define PWR_WAKEUP_PIN7_HIGH_3 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 7 (high polarity) */ + +#define PWR_WAKEUP_PIN8_HIGH_0 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_SOURCE_SELECTION_0) /*!< PF2 : Wakeup pin 8 (high polarity) */ +#define PWR_WAKEUP_PIN8_HIGH_1 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_SOURCE_SELECTION_1) /*!< PA7 : Wakeup pin 8 (high polarity) */ +#define PWR_WAKEUP_PIN8_HIGH_2 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_SOURCE_SELECTION_2) /*!< PB10 : Wakeup pin 8 (high polarity) */ +#define PWR_WAKEUP_PIN8_HIGH_3 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 8 (high polarity) */ +/** + * @} + */ + +/** @defgroup PWR_WakeUp_Pin_Low_Polarity PWR Wake Up Pins Low Polarity + * @{ + */ +#define PWR_WAKEUP_PIN1_LOW_0 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_POLARITY_LOW | PWR_WAKEUP1_SOURCE_SELECTION_0) /*!< PA0 : Wakeup pin 1 (low polarity) */ +#define PWR_WAKEUP_PIN1_LOW_1 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_POLARITY_LOW | PWR_WAKEUP1_SOURCE_SELECTION_1) /*!< PB2 : Wakeup pin 1 (low polarity) */ +#define PWR_WAKEUP_PIN1_LOW_2 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_POLARITY_LOW | PWR_WAKEUP1_SOURCE_SELECTION_2) /*!< PE4 : Wakeup pin 1 (low polarity) */ + +#define PWR_WAKEUP_PIN2_LOW_0 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_POLARITY_LOW | PWR_WAKEUP2_SOURCE_SELECTION_0) /*!< PA4 : Wakeup pin 2 (low polarity) */ +#define PWR_WAKEUP_PIN2_LOW_1 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_POLARITY_LOW | PWR_WAKEUP2_SOURCE_SELECTION_1) /*!< PC13 : Wakeup pin 2 (low polarity) */ +#define PWR_WAKEUP_PIN2_LOW_2 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_POLARITY_LOW | PWR_WAKEUP2_SOURCE_SELECTION_2) /*!< PE5 : Wakeup pin 2 (low polarity) */ + +#define PWR_WAKEUP_PIN3_LOW_0 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_POLARITY_LOW | PWR_WAKEUP3_SOURCE_SELECTION_0) /*!< PE6 : Wakeup pin 3 (low polarity) */ +#define PWR_WAKEUP_PIN3_LOW_1 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_POLARITY_LOW | PWR_WAKEUP3_SOURCE_SELECTION_1) /*!< PA1 : Wakeup pin 3 (low polarity) */ +#define PWR_WAKEUP_PIN3_LOW_2 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_POLARITY_LOW | PWR_WAKEUP3_SOURCE_SELECTION_2) /*!< PB6 : Wakeup pin 3 (low polarity) */ + +#define PWR_WAKEUP_PIN4_LOW_0 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_POLARITY_LOW | PWR_WAKEUP4_SOURCE_SELECTION_0) /*!< PA2 : Wakeup pin 4 (low polarity) */ +#define PWR_WAKEUP_PIN4_LOW_1 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_POLARITY_LOW | PWR_WAKEUP4_SOURCE_SELECTION_1) /*!< PB1 : Wakeup pin 4 (low polarity) */ +#define PWR_WAKEUP_PIN4_LOW_2 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_POLARITY_LOW | PWR_WAKEUP4_SOURCE_SELECTION_2) /*!< PB7 : Wakeup pin 4 (low polarity) */ + +#define PWR_WAKEUP_PIN5_LOW_0 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_POLARITY_LOW | PWR_WAKEUP5_SOURCE_SELECTION_0) /*!< PC5 : Wakeup pin 5 (low polarity) */ +#define PWR_WAKEUP_PIN5_LOW_1 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_POLARITY_LOW | PWR_WAKEUP5_SOURCE_SELECTION_1) /*!< PA3 : Wakeup pin 5 (low polarity) */ +#define PWR_WAKEUP_PIN5_LOW_2 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_POLARITY_LOW | PWR_WAKEUP5_SOURCE_SELECTION_2) /*!< PB8 : Wakeup pin 5 (low polarity) */ + +#define PWR_WAKEUP_PIN6_LOW_0 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_POLARITY_LOW | PWR_WAKEUP6_SOURCE_SELECTION_0) /*!< PB5 : Wakeup pin 6 (low polarity) */ +#define PWR_WAKEUP_PIN6_LOW_1 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_POLARITY_LOW | PWR_WAKEUP6_SOURCE_SELECTION_1) /*!< PA5 : Wakeup pin 6 (low polarity) */ +#define PWR_WAKEUP_PIN6_LOW_2 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_POLARITY_LOW | PWR_WAKEUP6_SOURCE_SELECTION_2) /*!< PE7 : Wakeup pin 6 (low polarity) */ +#define PWR_WAKEUP_PIN6_LOW_3 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_POLARITY_LOW | PWR_WAKEUP6_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 6 (low polarity) */ + +#define PWR_WAKEUP_PIN7_LOW_0 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_POLARITY_LOW | PWR_WAKEUP7_SOURCE_SELECTION_0) /*!< PB15 : Wakeup pin 7 (low polarity) */ +#define PWR_WAKEUP_PIN7_LOW_1 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_POLARITY_LOW | PWR_WAKEUP7_SOURCE_SELECTION_1) /*!< PA6 : Wakeup pin 7 (low polarity) */ +#define PWR_WAKEUP_PIN7_LOW_2 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_POLARITY_LOW | PWR_WAKEUP7_SOURCE_SELECTION_2) /*!< PE8 : Wakeup pin 7 (low polarity) */ +#define PWR_WAKEUP_PIN7_LOW_3 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_POLARITY_LOW | PWR_WAKEUP7_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 7 (low polarity) */ + +#define PWR_WAKEUP_PIN8_LOW_0 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_POLARITY_LOW | PWR_WAKEUP8_SOURCE_SELECTION_0) /*!< PF2 : Wakeup pin 8 (low polarity) */ +#define PWR_WAKEUP_PIN8_LOW_1 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_POLARITY_LOW | PWR_WAKEUP8_SOURCE_SELECTION_1) /*!< PA7 : Wakeup pin 8 (low polarity) */ +#define PWR_WAKEUP_PIN8_LOW_2 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_POLARITY_LOW | PWR_WAKEUP8_SOURCE_SELECTION_2) /*!< PB10 : Wakeup pin 8 (low polarity) */ +#define PWR_WAKEUP_PIN8_LOW_3 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_POLARITY_LOW | PWR_WAKEUP8_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 8 (low polarity) */ +/** + * @} + */ + +/** @defgroup PWR_WakeUp_Pins PWR Wake Up Pins (Default polarity and default pin selection) + * @{ + */ +#define PWR_WAKEUP_PIN1 (PWR_WUCR1_WUPEN1) /*!< PA0 : Wakeup pin 1 (high polarity) */ +#define PWR_WAKEUP_PIN2 (PWR_WUCR1_WUPEN2) /*!< PA4 : Wakeup pin 2 (high polarity) */ +#define PWR_WAKEUP_PIN3 (PWR_WUCR1_WUPEN3) /*!< PE6 : Wakeup pin 3 (high polarity) */ +#define PWR_WAKEUP_PIN4 (PWR_WUCR1_WUPEN4) /*!< PA2 : Wakeup pin 4 (high polarity) */ +#define PWR_WAKEUP_PIN5 (PWR_WUCR1_WUPEN5) /*!< PC5 : Wakeup pin 5 (high polarity) */ +#define PWR_WAKEUP_PIN6 (PWR_WUCR1_WUPEN6) /*!< PB5 : Wakeup pin 6 (high polarity) */ +#define PWR_WAKEUP_PIN7 (PWR_WUCR1_WUPEN7) /*!< PB15 : Wakeup pin 7 (high polarity) */ +#define PWR_WAKEUP_PIN8 (PWR_WUCR1_WUPEN8) /*!< PF2 : Wakeup pin 8 (high polarity) */ +/** + * @} + */ + +/** @defgroup PWR_Items PWR Items + * @{ + */ +#define PWR_WKUP1 (PWR_SECCFGR_WUP1SEC) /*!< WUP1 secure protection */ +#define PWR_WKUP2 (PWR_SECCFGR_WUP2SEC) /*!< WUP2 secure protection */ +#define PWR_WKUP3 (PWR_SECCFGR_WUP3SEC) /*!< WUP3 secure protection */ +#define PWR_WKUP4 (PWR_SECCFGR_WUP4SEC) /*!< WUP4 secure protection */ +#define PWR_WKUP5 (PWR_SECCFGR_WUP5SEC) /*!< WUP5 secure protection */ +#define PWR_WKUP6 (PWR_SECCFGR_WUP6SEC) /*!< WUP6 secure protection */ +#define PWR_WKUP7 (PWR_SECCFGR_WUP7SEC) /*!< WUP7 secure protection */ +#define PWR_WKUP8 (PWR_SECCFGR_WUP8SEC) /*!< WUP8 secure protection */ +#define PWR_LPM (PWR_SECCFGR_LPMSEC) /*!< Low power modes secure protection */ +#define PWR_VDM (PWR_SECCFGR_VDMSEC) /*!< Voltage detection and monitoring secure protection */ +#define PWR_VB (PWR_SECCFGR_VBSEC) /*!< Backup domain secure protection */ +#define PWR_APC (PWR_SECCFGR_APCSEC) /*!< Pull-up/pull-down secure protection */ +#define PWR_ALL (PWR_WKUP1 | PWR_WKUP2 | PWR_WKUP3 | PWR_WKUP4 | \ + PWR_WKUP5 | PWR_WKUP7 | PWR_WKUP6 | PWR_WKUP8 | \ + PWR_LPM | PWR_VDM | PWR_VB | PWR_APC) +/** + * @} + */ + +/** @defgroup PWR_Attributes PWR Attributes + * @brief PWR Privilege/NPrivilege and Secure/NSecure Attributes + * @{ + */ +#define PWR_NSEC_PRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK | 0x01U) /*!< NSecure and Privileged attribute */ +#define PWR_NSEC_NPRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK) /*!< NSecure and NPrivileged attribute */ +#define PWR_SEC_PRIV (PWR_ITEM_ATTR_SEC_PRIV_MASK | 0x02U) /*!< Secure and Privileged attribute */ +#define PWR_SEC_NPRIV (PWR_ITEM_ATTR_SEC_PRIV_MASK) /*!< Secure and NPrivileged attribute */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @brief Check PWR flags are set or not. + * @param __FLAG__ : Specifies the flag to check. + * This parameter can be one of the following values : + * @arg @ref PWR_FLAG_VOSRDY : Voltage scaling ready flag. + * Indicates that the Vcore level at or above VOS selected level. + * @arg @ref PWR_FLAG_BOOSTRDY : EPOD booster ready flag. + * Indicates that EPOD booster ready, + * frequency could be higher than 50 MHz. + * @arg @ref PWR_FLAG_USBBOOSTRDY : USB EPOD booster ready flag. + * Indicates that USB EPOD booster ready, + * frequency could be higher than 50 MHz. + * This flag is available only for STM32U59xxx and STM32U5Axxx + * devices. + * @arg @ref PWR_FLAG_STOPF : Stop flag. + * Indicates that the device was resumed from Stop mode. + * @arg @ref PWR_FLAG_SBF : Standby flag. + * Indicates that the device was resumed from Standby mode. + * @arg @ref PWR_FLAG_VDDA2RDY : VDDA2 ready flag (versus 1.8 V threshold). + * Indicates that VDDA is equal or above the threshold + * of the VDDA voltage monitor 2 (around 1.8 V). + * @arg @ref PWR_FLAG_VDDA1RDY : VDDA1 ready flag (versus 1.6 V threshold). + * Indicates that VDDA is equal or above the threshold + * of the VDDA voltage monitor 1 (around 1.6 V). + * @arg @ref PWR_FLAG_VDDIO2RDY : VDDIO2 ready flag (versus 0.9 V threshold). + * Indicates that VDDIO2 is equal or above the threshold + * of the VDDIO2 voltage monitor (around 0.9 V). + * @arg @ref PWR_FLAG_VDDUSBRDY : VDDUSB ready flag (versus 1.2 V threshold). + * Indicates that VDDUSB is equal or above the threshold + * of the VDDUSB voltage monitor (around 1.2 V). + * @arg @ref PWR_FLAG_ACTVOSRDY : Currently applied VOS ready flag. + * Indicates that Vcore is equal to the current + * voltage scaling provided by ACTVOS. + * @arg @ref PWR_FLAG_PVDO VDD : Voltage detector output flag. + * Indicates that Vdd is equal or above + * the PVD threshold selected by PVDLS. + * @arg @ref PWR_FLAG_REGS : Regulator selection flag. + * Indicates the regulator selected. + * @arg @ref PWR_FLAG_TEMPH : Temperature level flag (versus high threshold). + * Indicates the temperature is equal or above high threshold. + * @arg @ref PWR_FLAG_TEMPL : Temperature level flag (versus low threshold). + * Indicates the temperature is equal or above low threshold. + * @arg @ref PWR_FLAG_VBATH : Backup domain voltage level flag (versus high threshold). + * Indicates the backup domain voltage + * level is equal or above high threshold. + * @arg @ref PWR_WAKEUP_FLAG1 : Wakeup flag 1. + * Indicates that a wakeup event was received from the WKUP line 1. + * @arg @ref PWR_WAKEUP_FLAG2 : Wakeup flag 2. + * Indicates that a wakeup event was received from the WKUP line 2. + * @arg @ref PWR_WAKEUP_FLAG3 : Wakeup flag 3. + * Indicates that a wakeup event was received from the WKUP line 3. + * @arg @ref PWR_WAKEUP_FLAG4 : Wakeup flag 4. + * Indicates that a wakeup event was received from the WKUP line 4. + * @arg @ref PWR_WAKEUP_FLAG5 : Wakeup flag 5. + * Indicates that a wakeup event was received from the WKUP line 5. + * @arg @ref PWR_WAKEUP_FLAG6 : Wakeup flag 6. + * Indicates that a wakeup event was received from the WKUP line 6. + * @arg @ref PWR_WAKEUP_FLAG7 : Wakeup flag 7. + * Indicates that a wakeup event was received from the WKUP line 7. + * @arg @ref PWR_WAKEUP_FLAG8 : Wakeup flag 8. + * Indicates that a wakeup event was received from the WKUP line 8. + * @retval The state of __FLAG__ (TRUE or FALSE). + */ +#if defined (PWR_FLAG_USBBOOSTRDY) +#define __HAL_PWR_GET_FLAG(__FLAG__) \ + ( \ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == PWR_VOSR_VOSRDY) : \ + ((__FLAG__) == PWR_FLAG_BOOSTRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == PWR_VOSR_BOOSTRDY) : \ + ((__FLAG__) == PWR_FLAG_USBBOOSTRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTRDY) == PWR_VOSR_USBBOOSTRDY) : \ + ((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->SR, PWR_SR_STOPF) == PWR_SR_STOPF) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->SR, PWR_SR_SBF) == PWR_SR_SBF) : \ + ((__FLAG__) == PWR_FLAG_VDDA2RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA2RDY) == PWR_SVMSR_VDDA2RDY) : \ + ((__FLAG__) == PWR_FLAG_VDDA1RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA1RDY) == PWR_SVMSR_VDDA1RDY) : \ + ((__FLAG__) == PWR_FLAG_VDDIO2RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDIO2RDY) == PWR_SVMSR_VDDIO2RDY) : \ + ((__FLAG__) == PWR_FLAG_VDDUSBRDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDUSBRDY) == PWR_SVMSR_VDDUSBRDY) : \ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY) == PWR_SVMSR_ACTVOSRDY) : \ + ((__FLAG__) == PWR_FLAG_PVDO) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO) == PWR_SVMSR_PVDO) : \ + ((__FLAG__) == PWR_FLAG_REGS) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS) == PWR_SVMSR_REGS) : \ + ((__FLAG__) == PWR_FLAG_TEMPH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == PWR_BDSR_TEMPH) : \ + ((__FLAG__) == PWR_FLAG_TEMPL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == PWR_BDSR_TEMPL) : \ + ((__FLAG__) == PWR_FLAG_VBATH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == PWR_BDSR_VBATH) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == PWR_WUSR_WUF1) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == PWR_WUSR_WUF2) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == PWR_WUSR_WUF3) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == PWR_WUSR_WUF4) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == PWR_WUSR_WUF5) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == PWR_WUSR_WUF6) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == PWR_WUSR_WUF7) : \ + (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) +#else +#define __HAL_PWR_GET_FLAG(__FLAG__) \ + ( \ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == PWR_VOSR_VOSRDY) : \ + ((__FLAG__) == PWR_FLAG_BOOSTRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == PWR_VOSR_BOOSTRDY) : \ + ((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->SR, PWR_SR_STOPF) == PWR_SR_STOPF) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->SR, PWR_SR_SBF) == PWR_SR_SBF) : \ + ((__FLAG__) == PWR_FLAG_VDDA2RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA2RDY) == PWR_SVMSR_VDDA2RDY) : \ + ((__FLAG__) == PWR_FLAG_VDDA1RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA1RDY) == PWR_SVMSR_VDDA1RDY) : \ + ((__FLAG__) == PWR_FLAG_VDDIO2RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDIO2RDY) == PWR_SVMSR_VDDIO2RDY) : \ + ((__FLAG__) == PWR_FLAG_VDDUSBRDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDUSBRDY) == PWR_SVMSR_VDDUSBRDY) : \ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY) == PWR_SVMSR_ACTVOSRDY) : \ + ((__FLAG__) == PWR_FLAG_PVDO) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO) == PWR_SVMSR_PVDO) : \ + ((__FLAG__) == PWR_FLAG_REGS) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS) == PWR_SVMSR_REGS) : \ + ((__FLAG__) == PWR_FLAG_TEMPH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == PWR_BDSR_TEMPH) : \ + ((__FLAG__) == PWR_FLAG_TEMPL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == PWR_BDSR_TEMPL) : \ + ((__FLAG__) == PWR_FLAG_VBATH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == PWR_BDSR_VBATH) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == PWR_WUSR_WUF1) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == PWR_WUSR_WUF2) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == PWR_WUSR_WUF3) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == PWR_WUSR_WUF4) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == PWR_WUSR_WUF5) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == PWR_WUSR_WUF6) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == PWR_WUSR_WUF7) : \ + (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) +#endif /* defined (PWR_FLAG_USBBOOSTRDY) */ + +/** @brief Clear PWR flags. + * @param __FLAG__ : Specifies the flag to clear. + * This parameter can be one of the following values : + * @arg @ref PWR_FLAG_STOPF : Stop flag. + * Indicates that the device was resumed from Stop mode. + * @arg @ref PWR_FLAG_SBF : Standby flag. + * Indicates that the device was resumed from Standby mode. + * @arg @ref PWR_WAKEUP_FLAG1 : Wakeup flag 1. + * Indicates that a wakeup event was received from the WKUP line 1. + * @arg @ref PWR_WAKEUP_FLAG2 : Wakeup flag 2. + * Indicates that a wakeup event was received from the WKUP line 2. + * @arg @ref PWR_WAKEUP_FLAG3 : Wakeup flag 3. + * Indicates that a wakeup event was received from the WKUP line 3. + * @arg @ref PWR_WAKEUP_FLAG4 : Wakeup flag 4. + * Indicates that a wakeup event was received from the WKUP line 4. + * @arg @ref PWR_WAKEUP_FLAG5 : Wakeup flag 5. + * Indicates that a wakeup event was received from the WKUP line 5. + * @arg @ref PWR_WAKEUP_FLAG6 : Wakeup flag 6. + * Indicates that a wakeup event was received from the WKUP line 6. + * @arg @ref PWR_WAKEUP_FLAG7 : Wakeup flag 7. + * Indicates that a wakeup event was received from the WKUP line 7. + * @arg @ref PWR_WAKEUP_FLAG8 : Wakeup flag 8. + * Indicates that a wakeup event was received from the WKUP line 8. + * @retval None. + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) \ + ( \ + ((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG8) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8)) : \ + (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF))) + +/** + * @brief Enable the PVD Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Event Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Event Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Generate a Software Interrupt on selected EXTI line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) + +/** + * @brief Check whether or not the PVD EXTI Interrupt flag is set. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_PVD) + +/** + * @brief Clear the PVD EXTI Interrupt flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() \ + do \ + { \ + WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD); \ + WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD); \ + } while(0) +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ + +/** @addtogroup PWR_Private_Constants PWR Private Constants + * @{ + */ +/* Define PVD extended interrupts and event line */ +#define PWR_EXTI_LINE_PVD (0x00010000UL) /*!< PVD EXTI Line */ + +/* Defines wake up lines shift */ +#define PWR_WUP_POLARITY_SHIFT (0x08U) /*!< Internal constant used to retrieve wakeup signal polarity */ +#define PWR_WUP_SELECT_SIGNAL_SHIFT (0x10U) /*!< Internal constant used to retrieve wakeup signal selection */ + +/* Defines wake up lines mask */ +#define PWR_EWUP_MASK (0x000000FFUL) /*!< Internal constant used to retrieve wakeup signal enable */ +#define PWR_WUP_POLARITY_MASK (0x0000FF00UL) /*!< Internal constant used to retrieve wakeup signal polarity */ +#define PWR_WUP_SELECT_MASK (0xFFFF0000UL) /*!< Internal constant used to retrieve wakeup signal selection */ + +/* Defines wake up lines selection */ +#define PWR_WAKEUP1_SOURCE_SELECTION_0 (0U) +#define PWR_WAKEUP1_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL1_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP1_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL1_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP2_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP2_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL2_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP2_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL2_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP3_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP3_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL3_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP3_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL3_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP4_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP4_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL4_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP4_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL4_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP5_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP5_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL5_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP5_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL5_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP6_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP6_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL6_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP6_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL6_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP6_SOURCE_SELECTION_3 ((PWR_WUCR3_WUSEL6_0 | PWR_WUCR3_WUSEL6_1) << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP7_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP7_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL7_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP7_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL7_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP7_SOURCE_SELECTION_3 ((PWR_WUCR3_WUSEL7_0 | PWR_WUCR3_WUSEL7_1) << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP8_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP8_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL8_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP8_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL8_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP8_SOURCE_SELECTION_3 ((PWR_WUCR3_WUSEL8_0 | PWR_WUCR3_WUSEL8_1) << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ + +/* Defines wake up lines low polarity */ +#define PWR_WAKEUP1_POLARITY_LOW (PWR_WUCR2_WUPP1 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP2_POLARITY_LOW (PWR_WUCR2_WUPP2 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP3_POLARITY_LOW (PWR_WUCR2_WUPP3 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP4_POLARITY_LOW (PWR_WUCR2_WUPP4 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP5_POLARITY_LOW (PWR_WUCR2_WUPP5 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP6_POLARITY_LOW (PWR_WUCR2_WUPP6 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP7_POLARITY_LOW (PWR_WUCR2_WUPP7 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP8_POLARITY_LOW (PWR_WUCR2_WUPP8 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ + +/* Defines attribute */ +#define PWR_ITEM_ATTR_NSEC_PRIV_MASK (0x10U) /*!< NSecure Privilege / NPrivilege attribute item mask */ +#define PWR_ITEM_ATTR_SEC_PRIV_MASK (0x20U) /*!< Secure Privilege / NPrivilege attribute item mask */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup PWR_Private_Macros PWR Private Macros + * @{ + */ +/* Wake up pins check macro */ +#define IS_PWR_WAKEUP_PIN(PIN) \ + (((PIN) == PWR_WAKEUP_PIN1_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN1_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN1_HIGH_2) ||\ + ((PIN) == PWR_WAKEUP_PIN2_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN2_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN2_HIGH_2) ||\ + ((PIN) == PWR_WAKEUP_PIN3_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN3_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN3_HIGH_2) ||\ + ((PIN) == PWR_WAKEUP_PIN4_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN4_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN4_HIGH_2) ||\ + ((PIN) == PWR_WAKEUP_PIN5_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN5_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN5_HIGH_2) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH_2) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH_3) ||\ + ((PIN) == PWR_WAKEUP_PIN7_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN7_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN7_HIGH_2) ||\ + ((PIN) == PWR_WAKEUP_PIN7_HIGH_3) ||\ + ((PIN) == PWR_WAKEUP_PIN8_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN8_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN8_HIGH_2) ||\ + ((PIN) == PWR_WAKEUP_PIN8_HIGH_3) ||\ + ((PIN) == PWR_WAKEUP_PIN1_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN1_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN1_LOW_2) ||\ + ((PIN) == PWR_WAKEUP_PIN2_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN2_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN2_LOW_2) ||\ + ((PIN) == PWR_WAKEUP_PIN3_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN3_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN3_LOW_2) ||\ + ((PIN) == PWR_WAKEUP_PIN4_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN4_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN4_LOW_2) ||\ + ((PIN) == PWR_WAKEUP_PIN5_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN5_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN5_LOW_2) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW_2) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW_3) ||\ + ((PIN) == PWR_WAKEUP_PIN7_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN7_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN7_LOW_2) ||\ + ((PIN) == PWR_WAKEUP_PIN7_LOW_3) ||\ + ((PIN) == PWR_WAKEUP_PIN8_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN8_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN8_LOW_2) ||\ + ((PIN) == PWR_WAKEUP_PIN8_LOW_3) ||\ + ((PIN) == PWR_WAKEUP_PIN1) ||\ + ((PIN) == PWR_WAKEUP_PIN2) ||\ + ((PIN) == PWR_WAKEUP_PIN3) ||\ + ((PIN) == PWR_WAKEUP_PIN4) ||\ + ((PIN) == PWR_WAKEUP_PIN5) ||\ + ((PIN) == PWR_WAKEUP_PIN6) ||\ + ((PIN) == PWR_WAKEUP_PIN7) ||\ + ((PIN) == PWR_WAKEUP_PIN8)) + +/* PVD level check macro */ +#define IS_PWR_PVD_LEVEL(LEVEL) \ + (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) ||\ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) ||\ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) ||\ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) + +/* PVD mode check macro */ +#define IS_PWR_PVD_MODE(MODE) \ + (((MODE) == PWR_PVD_MODE_NORMAL) ||\ + ((MODE) == PWR_PVD_MODE_IT_RISING) ||\ + ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) + +/* Sleep mode entry check macro */ +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\ + ((ENTRY) == PWR_SLEEPENTRY_WFE) ||\ + ((ENTRY) == PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR)) + +/* Stop mode entry check macro */ +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\ + ((ENTRY) == PWR_STOPENTRY_WFE) ||\ + ((ENTRY) == PWR_STOPENTRY_WFE_NO_EVT_CLEAR)) + +/* PWR items check macro */ +#define IS_PWR_ITEMS_ATTRIBUTES(ITEM) \ + ((((ITEM) & (~PWR_ALL)) == 0U) && ((ITEM) != 0U)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* PWR attribute check macro (Secure) */ +#define IS_PWR_ATTRIBUTES(ATTRIBUTES) \ + ((((~(((ATTRIBUTES) & 0xF0U) >> 4U)) & ((ATTRIBUTES) & 0x0FU)) == 0U) && (((ATTRIBUTES) & 0xFFFFFFCCU) == 0U)) +#else +/* PWR attribute check macro (NSecure) */ +#define IS_PWR_ATTRIBUTES(ATTRIBUTES) \ + (((ATTRIBUTES) == PWR_NSEC_NPRIV) || ((ATTRIBUTES) == PWR_NSEC_PRIV)) +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/* Include PWR HAL Extended module */ +#include "stm32u5xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit(void); +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 + * @{ + */ +/* Programmable voltage detector functions ************************************/ +HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *pConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); + +/* Wake up pins configuration functions ***************************************/ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPin); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPin); + +/* Low power modes configuration functions ************************************/ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SleepEntry); +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t StopEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +/* Sleep on exit and sev on pending configuration functions *******************/ +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); + +/* Interrupt handler functions ************************************************/ +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVDCallback(void); +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group3 + * @{ + */ +/* Privileges and security configuration functions ****************************/ +void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes); +HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32U5xx_HAL_PWR_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr_ex.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr_ex.h new file mode 100644 index 000000000..8086e6a02 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr_ex.h @@ -0,0 +1,1109 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_PWR_EX_H +#define STM32U5xx_HAL_PWR_EX_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Types PWR Extended Exported Types + * @{ + */ + +/** + * @brief PWR PVM configuration structure definition + */ +typedef struct +{ + uint32_t PVMType; /*!< Specifies which voltage is monitored. + This parameter can be a value of + @ref PWREx_PVM_Type. */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of + @ref PWREx_PVM_Mode. */ +} PWR_PVMTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants + * @{ + */ + +/** @defgroup PWREx_PVM_Type PWR Extended Voltage Monitoring Type + * @{ + */ +#define PWR_UVM PWR_SVMCR_UVMEN /*!< Independent USB voltage monitor (VDDUSB versus 1.2 V) */ +#define PWR_IO2VM PWR_SVMCR_IO2VMEN /*!< Independent VDDIO2 voltage monitor (VDDIO2 versus 0.9 V) */ +#define PWR_AVM1 PWR_SVMCR_AVM1EN /*!< Independent VDDA voltage monitor (VDDA versus 1.6 V) */ +#define PWR_AVM2 PWR_SVMCR_AVM2EN /*!< Independent VDDA voltage monitor (VDDA versus 1.8 V) */ +/** + * @} + */ + +/** @defgroup PWREx_PVM_Mode PWR Extended PVM Interrupt and Event Mode + * @{ + */ +#define PWR_PVM_MODE_NORMAL (0x00U) /*!< Basic Mode is used */ +#define PWR_PVM_MODE_IT_RISING (0x05U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVM_MODE_IT_FALLING (0x06U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVM_MODE_IT_RISING_FALLING (0x07U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVM_MODE_EVENT_RISING (0x09U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVM_MODE_EVENT_FALLING (0x0AU) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVM_MODE_EVENT_RISING_FALLING (0x0BU) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWREx_SRD_State PWREx SRD Domain State + * @{ + */ +#define PWR_SRD_DOMAIN_STOP (0U) /*!< SRD in Stop mode when system goes to Stop 0/1/2 mode */ +#define PWR_SRD_DOMAIN_RUN PWR_CR2_SRDRUN /*!< SRD in Run mode when system goes to Stop 0/1/2 mode */ +/** + * @} + */ + +/** @defgroup PWREx_RAM_Contents_Stop_Retention PWR Extended RAM Contents Stop Retention + * @{ + */ +/* SRAM1 pages retention defines */ +#define PWR_SRAM1_PAGE1_STOP (SRAM1_ID | PAGE01_ID) /*!< SRAM1 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE2_STOP (SRAM1_ID | PAGE02_ID) /*!< SRAM1 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE3_STOP (SRAM1_ID | PAGE03_ID) /*!< SRAM1 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#if defined (PWR_CR4_SRAM1PDS4) +#define PWR_SRAM1_PAGE4_STOP (SRAM1_ID | PAGE04_ID) /*!< SRAM1 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE5_STOP (SRAM1_ID | PAGE05_ID) /*!< SRAM1 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE6_STOP (SRAM1_ID | PAGE06_ID) /*!< SRAM1 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE7_STOP (SRAM1_ID | PAGE07_ID) /*!< SRAM1 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE8_STOP (SRAM1_ID | PAGE08_ID) /*!< SRAM1 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE9_STOP (SRAM1_ID | PAGE09_ID) /*!< SRAM1 page 9 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE10_STOP (SRAM1_ID | PAGE10_ID) /*!< SRAM1 page 10 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE11_STOP (SRAM1_ID | PAGE11_ID) /*!< SRAM1 page 11 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE12_STOP (SRAM1_ID | PAGE12_ID) /*!< SRAM1 page 12 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_FULL_STOP (SRAM1_ID | 0x0FFFU) /*!< SRAM1 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#else +#define PWR_SRAM1_FULL_STOP (SRAM1_ID | 0x07U) /*!< SRAM1 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR4_SRAM1PDS4) */ + +/* SRAM2 pages retention defines */ +#define PWR_SRAM2_PAGE1_STOP (SRAM2_ID | PAGE01_ID) /*!< SRAM2 page 1 (8 KB) retention in Stop modes (Stop 0, 1, 2) */ +#define PWR_SRAM2_PAGE2_STOP (SRAM2_ID | PAGE02_ID) /*!< SRAM2 page 2 (54 KB) retention in Stop modes (Stop 0, 1, 2) */ +#define PWR_SRAM2_FULL_STOP (SRAM2_ID | 0x03U) /*!< SRAM2 all pages retention in Stop modes (Stop 0, 1, 2) */ + +#if defined (PWR_CR2_SRAM3PDS1) +/* SRAM3 pages retention defines */ +#define PWR_SRAM3_PAGE1_STOP (SRAM3_ID | PAGE01_ID) /*!< SRAM3 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE2_STOP (SRAM3_ID | PAGE02_ID) /*!< SRAM3 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE3_STOP (SRAM3_ID | PAGE03_ID) /*!< SRAM3 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE4_STOP (SRAM3_ID | PAGE04_ID) /*!< SRAM3 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE5_STOP (SRAM3_ID | PAGE05_ID) /*!< SRAM3 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE6_STOP (SRAM3_ID | PAGE06_ID) /*!< SRAM3 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE7_STOP (SRAM3_ID | PAGE07_ID) /*!< SRAM3 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE8_STOP (SRAM3_ID | PAGE08_ID) /*!< SRAM3 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#if defined (PWR_CR4_SRAM3PDS9) +#define PWR_SRAM3_PAGE9_STOP (SRAM3_ID | PAGE09_ID) /*!< SRAM3 page 9 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE10_STOP (SRAM3_ID | PAGE10_ID) /*!< SRAM3 page 10 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE11_STOP (SRAM3_ID | PAGE11_ID) /*!< SRAM3 page 11 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE12_STOP (SRAM3_ID | PAGE12_ID) /*!< SRAM3 page 12 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE13_STOP (SRAM3_ID | PAGE13_ID) /*!< SRAM3 page 13 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_FULL_STOP (SRAM3_ID | 0x1FFFU) /*!< SRAM3 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#else +#define PWR_SRAM3_FULL_STOP (SRAM3_ID | 0xFFU) /*!< SRAM3 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR4_SRAM3PDS9) */ +#endif /* PWR_CR2_SRAM3PDS1 */ + +/* SRAM4 page retention defines */ +#define PWR_SRAM4_FULL_STOP (SRAM4_ID | PAGE01_ID) /*!< SRAM4 retention in Stop modes (Stop 0, 1, 2, 3) */ + +#if defined (PWR_CR4_SRAM5PDS1) +/* SRAM5 pages retention defines */ +#define PWR_SRAM5_PAGE1_STOP (SRAM5_ID | PAGE01_ID) /*!< SRAM5 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE2_STOP (SRAM5_ID | PAGE02_ID) /*!< SRAM5 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE3_STOP (SRAM5_ID | PAGE03_ID) /*!< SRAM5 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE4_STOP (SRAM5_ID | PAGE04_ID) /*!< SRAM5 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE5_STOP (SRAM5_ID | PAGE05_ID) /*!< SRAM5 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE6_STOP (SRAM5_ID | PAGE06_ID) /*!< SRAM5 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE7_STOP (SRAM5_ID | PAGE07_ID) /*!< SRAM5 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE8_STOP (SRAM5_ID | PAGE08_ID) /*!< SRAM5 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE9_STOP (SRAM5_ID | PAGE09_ID) /*!< SRAM5 page 9 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE10_STOP (SRAM5_ID | PAGE10_ID) /*!< SRAM5 page 10 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE11_STOP (SRAM5_ID | PAGE11_ID) /*!< SRAM5 page 11 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE12_STOP (SRAM5_ID | PAGE12_ID) /*!< SRAM5 page 12 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE13_STOP (SRAM5_ID | PAGE13_ID) /*!< SRAM5 page 13 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_FULL_STOP (SRAM5_ID | 0x1FFFU) /*!< SRAM5 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR4_SRAM5PDS1) */ + +#if defined (PWR_CR5_SRAM6PDS1) +/* SRAM5 pages retention defines */ +#define PWR_SRAM6_PAGE1_STOP (SRAM6_ID | PAGE01_ID) /*!< SRAM6 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE2_STOP (SRAM6_ID | PAGE02_ID) /*!< SRAM6 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE3_STOP (SRAM6_ID | PAGE03_ID) /*!< SRAM6 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE4_STOP (SRAM6_ID | PAGE04_ID) /*!< SRAM6 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE5_STOP (SRAM6_ID | PAGE05_ID) /*!< SRAM6 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE6_STOP (SRAM6_ID | PAGE06_ID) /*!< SRAM6 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE7_STOP (SRAM6_ID | PAGE07_ID) /*!< SRAM6 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE8_STOP (SRAM6_ID | PAGE08_ID) /*!< SRAM6 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_FULL_STOP (SRAM6_ID | 0xFFU) /*!< SRAM6 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR5_SRAM6PDS1) */ + +/* Cache RAMs retention defines */ +#define PWR_ICACHE_FULL_STOP (ICACHERAM_ID | PAGE01_ID) /*!< ICACHE page retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_DCACHE1_FULL_STOP (DCACHE1RAM_ID | PAGE01_ID) /*!< DCACHE1 page retention in Stop modes (Stop 0, 1, 2, 3) */ +#if defined (PWR_CR2_DC2RAMPDS) +#define PWR_DCACHE2_FULL_STOP (DCACHE2RAM_ID | PAGE01_ID) /*!< DCACHE2 page retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR2_DC2RAMPDS) */ + +#if defined (PWR_CR2_DMA2DRAMPDS) +/* DMA2D RAM retention defines */ +#define PWR_DMA2DRAM_FULL_STOP (DMA2DRAM_ID | PAGE01_ID) /*!< DMA2D RAM retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* PWR_CR2_DMA2DRAMPDS */ + +/* FMAC, FDCAN and USB RAMs retention defines */ +#define PWR_PERIPHRAM_FULL_STOP (PERIPHRAM_ID | PAGE01_ID) /*!< FMAC, FDCAN and USB RAM retention in Stop modes (Stop 0, 1, 2, 3) */ + +/* PKA32 RAM retention defines */ +#define PWR_PKA32RAM_FULL_STOP (PKARAM_ID | PAGE01_ID) /*!< PKA32 RAM retention in Stop modes (Stop 0, 1, 2, 3) */ + +#if defined (PWR_CR2_GPRAMPDS) +/* Graphic peripherals RAM retention defines */ +#define PWR_GRAPHICPRAM_FULL_STOP (GRAPHIPRAM_ID | PAGE01_ID) /*!< LTDC, GFXMMU retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR2_GPRAMPDS) */ + +#if defined (PWR_CR2_DSIRAMPDS) +/* DSI RAM retention defines */ +#define PWR_DSIRAM_FULL_STOP (DSIRAM_ID | PAGE01_ID) /*!< DSI RAM retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR2_DSIRAMPDS) */ + +#if defined (PWR_CR2_JPEGRAMPDS) +/* JPEG RAM retention defines */ +#define PWR_JPEGRAM_FULL_STOP (JPEGRAM_ID | PAGE01_ID) /*!< JPEG RAM retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR2_JPEGRAMPDS) */ +/** + * @} + */ + +/** @defgroup PWREx_SRAM2_Contents_Standby_Retention PWR Extended SRAM2 Contents Standby Retention + * @note For some products of the U5 family (please see the Reference Manual), + * the SRAM2 content is preserved based on the same defines in Stop 3 mode. + * @{ + */ +#define PWR_SRAM2_PAGE1_STANDBY PWR_CR1_RRSB1 /*!< SRAM2 page 1 (8 KB) retention in Stop 3 and Standby modes */ +#define PWR_SRAM2_PAGE2_STANDBY PWR_CR1_RRSB2 /*!< SRAM2 page 2 (54 KB) retention in Stop 3 and Standby modes */ +#define PWR_SRAM2_FULL_STANDBY (PWR_CR1_RRSB1 | PWR_CR1_RRSB2) /*!< SRAM2 all pages retention in Stop 3 and Standby modes */ +/** + * @} + */ + +/** @defgroup PWREx_SRAMx_Contents_Run_Retention PWR Extended SRAM Contents Run Retention + * @{ + */ +#define PWR_SRAM1_FULL_RUN PWR_CR1_SRAM1PD /*!< SRAM1 full retention in Run mode */ +#define PWR_SRAM2_FULL_RUN PWR_CR1_SRAM2PD /*!< SRAM2 full retention in Run mode */ +#if defined (PWR_CR1_SRAM3PD) +#define PWR_SRAM3_FULL_RUN PWR_CR1_SRAM3PD /*!< SRAM3 full retention in Run mode */ +#endif /* PWR_CR1_SRAM3PD */ +#define PWR_SRAM4_FULL_RUN PWR_CR1_SRAM4PD /*!< SRAM4 full retention in Run mode */ +#if defined (PWR_CR1_SRAM5PD) +#define PWR_SRAM5_FULL_RUN PWR_CR1_SRAM5PD /*!< SRAM5 full retention in Run mode */ +#endif /* defined (PWR_CR1_SRAM5PD) */ +#if defined (PWR_CR1_SRAM6PD) +#define PWR_SRAM6_FULL_RUN PWR_CR1_SRAM6PD /*!< SRAM6 full retention in Run mode */ +#endif /* defined (PWR_CR1_SRAM6PD) */ +/** + * @} + */ + +/** @defgroup PWREx_Supply_Configuration PWR Extended Supply Configuration + * @{ + */ +#define PWR_LDO_SUPPLY (0U) /*!< LDO supply */ +#define PWR_SMPS_SUPPLY (PWR_CR3_REGSEL) /*!< SMPS supply */ +/** + * @} + */ + +/** @defgroup PWREx_Regulator_Voltage_Scale PWR Extended Regulator Voltage Scale + * @{ + */ +#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_VOSR_VOS_0 | PWR_VOSR_VOS_1) /*!< Voltage scaling range 1 */ +#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_VOSR_VOS_1 /*!< Voltage scaling range 2 */ +#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_VOSR_VOS_0 /*!< Voltage scaling range 3 */ +#define PWR_REGULATOR_VOLTAGE_SCALE4 (0U) /*!< Voltage scaling range 4 */ +/** + * @} + */ + +/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR Extended Battery Charging Resistor Selection + * @{ + */ +#define PWR_BATTERY_CHARGING_RESISTOR_5 (0U) /*!< VBAT charging through a 5 kOhms resistor */ +#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_BDCR2_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ +/** + * @} + */ + +/** @defgroup PWREx_GPIO_Port PWR Extended GPIO Port + * @{ + */ +#define PWR_GPIO_A (0x00U) /*!< GPIO port A */ +#define PWR_GPIO_B (0x01U) /*!< GPIO port B */ +#define PWR_GPIO_C (0x02U) /*!< GPIO port C */ +#define PWR_GPIO_D (0x03U) /*!< GPIO port D */ +#define PWR_GPIO_E (0x04U) /*!< GPIO port E */ +#if defined (PWR_PUCRF_PU0) +#define PWR_GPIO_F (0x05U) /*!< GPIO port F */ +#endif /* PWR_PUCRF_PU0 */ +#define PWR_GPIO_G (0x06U) /*!< GPIO port G */ +#define PWR_GPIO_H (0x07U) /*!< GPIO port H */ +#if defined (PWR_PUCRI_PU0) +#define PWR_GPIO_I (0x08U) /*!< GPIO port I */ +#endif /* PWR_PUCRI_PU0 */ +#if defined (PWR_PUCRJ_PU0) +#define PWR_GPIO_J (0x09U) /*!< GPIO port J */ +#endif /* defined (PWR_PUCRJ_PU0) */ +/** + * @} + */ + +/** @defgroup PWREx_GPIO_Pin_Mask PWR Extended GPIO Pin Mask + * @{ + */ +#define PWR_GPIO_BIT_0 (0x0001U) /*!< GPIO port I/O pin 0 */ +#define PWR_GPIO_BIT_1 (0x0002U) /*!< GPIO port I/O pin 1 */ +#define PWR_GPIO_BIT_2 (0x0004U) /*!< GPIO port I/O pin 2 */ +#define PWR_GPIO_BIT_3 (0x0008U) /*!< GPIO port I/O pin 3 */ +#define PWR_GPIO_BIT_4 (0x0010U) /*!< GPIO port I/O pin 4 */ +#define PWR_GPIO_BIT_5 (0x0020U) /*!< GPIO port I/O pin 5 */ +#define PWR_GPIO_BIT_6 (0x0040U) /*!< GPIO port I/O pin 6 */ +#define PWR_GPIO_BIT_7 (0x0080U) /*!< GPIO port I/O pin 7 */ +#define PWR_GPIO_BIT_8 (0x0100U) /*!< GPIO port I/O pin 8 */ +#define PWR_GPIO_BIT_9 (0x0200U) /*!< GPIO port I/O pin 9 */ +#define PWR_GPIO_BIT_10 (0x0400U) /*!< GPIO port I/O pin 10 */ +#define PWR_GPIO_BIT_11 (0x0800U) /*!< GPIO port I/O pin 11 */ +#define PWR_GPIO_BIT_12 (0x1000U) /*!< GPIO port I/O pin 12 */ +#define PWR_GPIO_BIT_13 (0x2000U) /*!< GPIO port I/O pin 13 */ +#define PWR_GPIO_BIT_14 (0x4000U) /*!< GPIO port I/O pin 14 */ +#define PWR_GPIO_BIT_15 (0x8000U) /*!< GPIO port I/O pin 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros + * @{ + */ + +/** + * @brief Enable the UVM Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_UVM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_UVM) + +/** + * @brief Disable the UVM Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_UVM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_UVM) + +/** + * @brief Enable the UVM Event Line. + * @retval None. + */ +#define __HAL_PWR_UVM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_UVM) + +/** + * @brief Disable the UVM Event Line. + * @retval None. + */ +#define __HAL_PWR_UVM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_UVM) + +/** + * @brief Enable the UVM Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_UVM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_UVM) + +/** + * @brief Disable the UVM Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_UVM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_UVM) + +/** + * @brief Enable the UVM Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_UVM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_UVM) + +/** + * @brief Disable the UVM Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_UVM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_UVM) + +/** + * @brief Enable the UVM Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_UVM_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_UVM_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_UVM_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the UVM Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_UVM_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_UVM_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_UVM_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Generate a Software Interrupt on UVM EXTI Line. + * @retval None + */ +#define __HAL_PWR_UVM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_UVM) + +/** + * @brief Check whether the specified UVM EXTI flag is set or not. + * @retval EXTI UVM Line Status. + */ +#define __HAL_PWR_UVM_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_UVM) + +/** + * @brief Clear the UVM EXTI flag. + * @retval None. + */ +#define __HAL_PWR_UVM_EXTI_CLEAR_FLAG() \ + do \ + { \ + WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_UVM); \ + WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_UVM); \ + } while(0) + +/** + * @brief Enable the IO2VM Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_IO2VM) + +/** + * @brief Disable the IO2VM Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_IO2VM) + +/** + * @brief Enable the IO2VM Event Line. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_IO2VM) + +/** + * @brief Disable the IO2VM Event Line. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_IO2VM) + +/** + * @brief Enable the IO2VM Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_IO2VM) + +/** + * @brief Disable the IO2VM Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_IO2VM) + +/** + * @brief Enable the IO2VM Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_IO2VM) + +/** + * @brief Disable the IO2VM Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_IO2VM) + +/** + * @brief Enable the IO2VM Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the IO2VM Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Generate a Software Interrupt on IO2VM EXTI Line. + * @retval None + */ +#define __HAL_PWR_IO2VM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_IO2VM) + +/** + * @brief Check whether the specified IO2VM EXTI flag is set or not. + * @retval EXTI IO2VM Line Status. + */ +#define __HAL_PWR_IO2VM_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_IO2VM) + +/** + * @brief Clear the IO2VM EXTI flag. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_CLEAR_FLAG() \ + do \ + { \ + WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_IO2VM); \ + WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_IO2VM); \ + } while(0) + +/** + * @brief Enable the AVM1 Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_AVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVM1) + +/** + * @brief Disable the AVM1 Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_AVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVM1) + +/** + * @brief Enable the AVM1 Event Line. + * @retval None. + */ +#define __HAL_PWR_AVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVM1) + +/** + * @brief Disable the AVM1 Event Line. + * @retval None. + */ +#define __HAL_PWR_AVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVM1) + +/** + * @brief Enable the AVM1 Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_AVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVM1) + +/** + * @brief Disable the AVM1 Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_AVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVM1) + +/** + * @brief Enable the AVM1 Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVM1) + +/** + * @brief Disable the AVM1 Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVM1) + +/** + * @brief Enable the AVM1 Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_AVM1_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_AVM1_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the AVM1 Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_AVM1_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_AVM1_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Generate a Software Interrupt on AVM1 EXTI Line. + * @retval None + */ +#define __HAL_PWR_AVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVM1) + +/** + * @brief Check whether the specified AVM1 EXTI flag is set or not. + * @retval EXTI AVM1 Line Status. + */ +#define __HAL_PWR_AVM1_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_AVM1) + +/** + * @brief Clear the AVM1 EXTI flag. + * @retval None. + */ +#define __HAL_PWR_AVM1_EXTI_CLEAR_FLAG() \ + do \ + { \ + WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM1); \ + WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM1); \ + } while(0) + +/** + * @brief Enable the AVM2 Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_AVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVM2) + +/** + * @brief Disable the AVM2 Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_AVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVM2) + +/** + * @brief Enable the AVM2 Event Line. + * @retval None. + */ +#define __HAL_PWR_AVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVM2) + +/** + * @brief Disable the AVM2 Event Line. + * @retval None. + */ +#define __HAL_PWR_AVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVM2) + +/** + * @brief Enable the AVM2 Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_AVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVM2) + +/** + * @brief Disable the AVM2 Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_AVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVM2) + +/** + * @brief Enable the AVM2 Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVM2) + +/** + * @brief Disable the AVM2 Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVM2) + +/** + * @brief Enable the AVM2 Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_AVM2_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_AVM2_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the AVM2 Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_AVM2_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_AVM2_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Generate a Software Interrupt on AVM2 EXTI Line. + * @retval None + */ +#define __HAL_PWR_AVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVM2) + +/** + * @brief Check whether the specified AVM2 EXTI flag is set or not. + * @retval EXTI AVM2 Line Status. + */ +#define __HAL_PWR_AVM2_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_AVM2) + +/** + * @brief Clear the AVM2 EXTI flag. + * @retval None. + */ +#define __HAL_PWR_AVM2_EXTI_CLEAR_FLAG() \ + do \ + { \ + WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM2); \ + WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM2); \ + } while(0) + +/** + * @brief Configure the main internal regulator output voltage. + * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but + * doesn't check whether or not VOSREADY flag is set. User may resort + * to __HAL_PWR_GET_FLAG() macro to check VOSF bit state. + * @param __REGULATOR__ : Specifies the regulator output voltage to achieve a + * tradeoff between performance and power consumption. + * This parameter can be one of the following values : + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output scale 1. + * Provides a typical output voltage at 1.2 V. + * Used when system clock frequency is up to 160 MHz. + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output scale 2. + * Provides a typical output voltage at 1.1 V. + * Used when system clock frequency is up to 100 MHz. + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output scale 3. + * Provides a typical output voltage at 1.0 V. + * Used when system clock frequency is up to 50 MHz. + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE4 : Regulator voltage output scale 4. + * Provides a typical output voltage at 0.9 V. + * Used when system clock frequency is up to 24 MHz. + * @retval None. + */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ + do \ + { \ + __IO uint32_t tmpreg; \ + MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, (__REGULATOR__)); \ + tmpreg = READ_BIT(PWR->VOSR, PWR_VOSR_VOS); \ + UNUSED(tmpreg); \ + } while(0) +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ + +/** @addtogroup PWREx_Private_Constants PWR Extended Private Constants + * @{ + */ +/* PVM extended interrupts and event lines defines */ +#define PWR_EXTI_LINE_UVM (0x00080000UL) /* UVM EXTI Line */ +#define PWR_EXTI_LINE_IO2VM (0x00100000UL) /* IO2VM EXTI Line */ +#define PWR_EXTI_LINE_AVM1 (0x00200000UL) /* AVM1 EXTI Line */ +#define PWR_EXTI_LINE_AVM2 (0x00400000UL) /* AVM2 EXTI Line */ + +/* SRAM retention IDs */ +#define SRAM_ID_MASK (0xFFFFUL << 16U) +#define SRAM1_ID (0x01UL << 16U) +#define SRAM2_ID (0x01UL << 17U) +#if defined (PWR_CR2_SRAM3PDS1) +#define SRAM3_ID (0x01UL << 18U) +#endif /* PWR_CR2_SRAM3PDS1 */ +#define SRAM4_ID (0x01UL << 19U) +#define ICACHERAM_ID (0x01UL << 20U) +#define DCACHE1RAM_ID (0x01UL << 21U) +#if defined (PWR_CR2_DMA2DRAMPDS) +#define DMA2DRAM_ID (0x01UL << 22U) +#endif /* PWR_CR2_DMA2DRAMPDS */ +#define PERIPHRAM_ID (0x01UL << 23U) +#define PKARAM_ID (0x01UL << 24U) +#if defined (PWR_CR2_DC2RAMPDS) +#define DCACHE2RAM_ID (0x01UL << 25U) +#endif /* defined (PWR_CR2_DC2RAMPDS) */ +#if defined (PWR_CR2_GPRAMPDS) +#define GRAPHIPRAM_ID (0x01UL << 26U) +#endif /* defined (PWR_CR2_GPRAMPDS) */ +#if defined (PWR_CR2_DSIRAMPDS) +#define DSIRAM_ID (0x01UL << 27U) +#endif /* defined (PWR_CR2_DSIRAMPDS) */ +#if defined (PWR_CR4_SRAM5PDS1) +#define SRAM5_ID (0x01UL << 28U) +#endif /* defined (PWR_CR4_SRAM5PDS1) */ +#if defined (PWR_CR5_SRAM6PDS1) +#define SRAM6_ID (0x01UL << 29U) +#endif /* defined (PWR_CR5_SRAM6PDS1) */ +#if defined (PWR_CR2_JPEGRAMPDS) +#define JPEGRAM_ID (0x01UL << 30U) +#endif /* defined (PWR_CR2_JPEGRAMPDS)*/ + +/* SRAM page retention IDs */ +#define PAGE01_ID (0x01UL << 0U) +#define PAGE02_ID (0x01UL << 1U) +#define PAGE03_ID (0x01UL << 2U) +#define PAGE04_ID (0x01UL << 3U) +#define PAGE05_ID (0x01UL << 4U) +#define PAGE06_ID (0x01UL << 5U) +#define PAGE07_ID (0x01UL << 6U) +#define PAGE08_ID (0x01UL << 7U) +#define PAGE09_ID (0x01UL << 8U) +#define PAGE10_ID (0x01UL << 9U) +#define PAGE11_ID (0x01UL << 10U) +#define PAGE12_ID (0x01UL << 11U) +#define PAGE13_ID (0x01UL << 12U) + +/* All available RAM retention in Run mode define */ +#if defined (PWR_CR1_SRAM6PD) +#define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \ + PWR_SRAM3_FULL_RUN | PWR_SRAM4_FULL_RUN | \ + PWR_SRAM5_FULL_RUN | PWR_SRAM6_FULL_RUN) +#elif defined (PWR_CR1_SRAM5PD) +#define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \ + PWR_SRAM3_FULL_RUN | PWR_SRAM4_FULL_RUN | \ + PWR_SRAM5_FULL_RUN) +#elif defined (PWR_CR2_SRAM3PDS1) +#define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \ + PWR_SRAM3_FULL_RUN | PWR_SRAM4_FULL_RUN) +#else +#define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \ + PWR_SRAM4_FULL_RUN) +#endif /* defined (PWR_CR1_SRAM5PD) */ +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ + +/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros + * @{ + */ +/* PVM type check macro */ +#define IS_PWR_PVM_TYPE(TYPE) \ + (((TYPE) == PWR_UVM ) ||\ + ((TYPE) == PWR_IO2VM) ||\ + ((TYPE) == PWR_AVM1) ||\ + ((TYPE) == PWR_AVM2)) + +/* PVM mode check macro */ +#define IS_PWR_PVM_MODE(MODE) \ + (((MODE) == PWR_PVM_MODE_NORMAL) ||\ + ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ + ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ + ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ + ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ + ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ + ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) + +/* SRD state check macro */ +#define IS_PWR_SRD_STATE(SRD_STATE) \ + (((SRD_STATE) == PWR_SRD_DOMAIN_STOP) ||\ + ((SRD_STATE) == PWR_SRD_DOMAIN_RUN)) + +/* Supply selection check macro */ +#define IS_PWR_SUPPLY(PWR_SOURCE) \ + (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ + ((PWR_SOURCE) == PWR_SMPS_SUPPLY)) + +/* Voltage scaling range check macro */ +#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) \ + (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) ||\ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) ||\ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3) ||\ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE4)) + +/* Battery charging resistor selection check macro */ +#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) \ + (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ + ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) + +/* GPIO port check macro */ +#if defined (PWR_PUCRJ_PU0) +#define IS_PWR_GPIO_PORT(GPIO_PORT) \ + (((GPIO_PORT) == PWR_GPIO_A) ||\ + ((GPIO_PORT) == PWR_GPIO_B) ||\ + ((GPIO_PORT) == PWR_GPIO_C) ||\ + ((GPIO_PORT) == PWR_GPIO_D) ||\ + ((GPIO_PORT) == PWR_GPIO_E) ||\ + ((GPIO_PORT) == PWR_GPIO_F) ||\ + ((GPIO_PORT) == PWR_GPIO_G) ||\ + ((GPIO_PORT) == PWR_GPIO_H) ||\ + ((GPIO_PORT) == PWR_GPIO_I) ||\ + ((GPIO_PORT) == PWR_GPIO_J)) +#elif defined (PWR_PUCRF_PU0) && defined (PWR_PUCRI_PU0) +#define IS_PWR_GPIO_PORT(GPIO_PORT) \ + (((GPIO_PORT) == PWR_GPIO_A) ||\ + ((GPIO_PORT) == PWR_GPIO_B) ||\ + ((GPIO_PORT) == PWR_GPIO_C) ||\ + ((GPIO_PORT) == PWR_GPIO_D) ||\ + ((GPIO_PORT) == PWR_GPIO_E) ||\ + ((GPIO_PORT) == PWR_GPIO_F) ||\ + ((GPIO_PORT) == PWR_GPIO_G) ||\ + ((GPIO_PORT) == PWR_GPIO_H) ||\ + ((GPIO_PORT) == PWR_GPIO_I)) +#else +#define IS_PWR_GPIO_PORT(GPIO_PORT) \ + (((GPIO_PORT) == PWR_GPIO_A) ||\ + ((GPIO_PORT) == PWR_GPIO_B) ||\ + ((GPIO_PORT) == PWR_GPIO_C) ||\ + ((GPIO_PORT) == PWR_GPIO_D) ||\ + ((GPIO_PORT) == PWR_GPIO_E) ||\ + ((GPIO_PORT) == PWR_GPIO_G) ||\ + ((GPIO_PORT) == PWR_GPIO_H)) +#endif /* defined (PWR_PUCRJ_PU0) */ + +/* GPIO pin mask check macro */ +#define IS_PWR_GPIO_PIN_MASK(BIT_MASK) \ + ((((BIT_MASK) & GPIO_PIN_MASK) != 0U) && ((BIT_MASK) <= GPIO_PIN_MASK)) + +/* SRAM2 retention in Standby mode check macro */ +#define IS_PWR_SRAM2_STANDBY_RETENTION(CONTENT) \ + (((CONTENT) == PWR_SRAM2_PAGE1_STANDBY) ||\ + ((CONTENT) == PWR_SRAM2_PAGE2_STANDBY) ||\ + ((CONTENT) == PWR_SRAM2_FULL_STANDBY)) + +/* RAMs retention in Stop mode check macros */ +#define IS_PWR_SRAM1_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_SRAM1_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) + +#define IS_PWR_SRAM2_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_SRAM2_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) + +#if defined (PWR_CR2_SRAM3PDS1) +#define IS_PWR_SRAM3_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_SRAM3_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* PWR_CR2_SRAM3PDS1 */ + +#define IS_PWR_SRAM4_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_SRAM4_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) + +#if defined (PWR_CR4_SRAM5PDS1) +#define IS_PWR_SRAM5_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_SRAM5_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* defined (PWR_CR4_SRAM5PDS1) */ + +#if defined (PWR_CR5_SRAM6PDS1) +#define IS_PWR_SRAM6_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_SRAM6_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* defined (PWR_CR5_SRAM6PDS1) */ + +#define IS_PWR_ICACHE_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_ICACHE_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) + +#define IS_PWR_DCACHE1_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_DCACHE1_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) + +#if defined (PWR_CR2_DC2RAMPDS) +#define IS_PWR_DCACHE2_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_DCACHE2_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* defined (PWR_CR2_DC2RAMPDS) */ + +#if defined (PWR_CR2_DMA2DRAMPDS) +#define IS_PWR_DMA2DRAM_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_DMA2DRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* PWR_CR2_DMA2DRAMPDS */ + +#define IS_PWR_PERIPHRAM_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_PERIPHRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) + +#define IS_PWR_PKA32RAM_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_PKA32RAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) + +#if defined (PWR_CR2_GPRAMPDS) +#define IS_PWR_GRAPHICPRAM_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_GRAPHICPRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* defined (PWR_CR2_GPRAMPDS) */ + +#if defined (PWR_CR2_DSIRAMPDS) +#define IS_PWR_DSIRAM_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_DSIRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* defined (PWR_CR2_DSIRAMPDS) */ + +#if defined (PWR_CR2_JPEGRAMPDS) +#define IS_PWR_JPEGRAM_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_JPEGRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* defined (PWR_CR2_DSIRAMPDS) */ + +/* RAMs retention in Run mode check macro */ +#define IS_PWR_RAM_RUN_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_ALL_RAM_RUN_MASK)) == 0U) && ((RAMCONTENT) != 0U)) +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions + * @{ + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); +uint32_t HAL_PWREx_GetVoltageRange(void); +HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource); +uint32_t HAL_PWREx_GetSupplyConfig(void); +void HAL_PWREx_EnableFastSoftStart(void); +void HAL_PWREx_DisableFastSoftStart(void); +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions + * @{ + */ +void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); +void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); +void HAL_PWREx_EnterSTOP3Mode(uint8_t STOPEntry); +void HAL_PWREx_EnterSHUTDOWNMode(void); +void HAL_PWREx_ConfigSRDDomain(uint32_t SRDState); +void HAL_PWREx_EnableUltraLowPowerMode(void); +void HAL_PWREx_DisableUltraLowPowerMode(void); +void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin); +void HAL_PWREx_S3WUCallback(uint32_t WakeUpPin); +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group3 Voltage Monitoring Functions + * @{ + */ +void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue); +void HAL_PWREx_DisableBatteryCharging(void); +void HAL_PWREx_EnableVddUSB(void); +void HAL_PWREx_DisableVddUSB(void); +void HAL_PWREx_EnableVddIO2(void); +void HAL_PWREx_DisableVddIO2(void); +void HAL_PWREx_EnableVddA(void); +void HAL_PWREx_DisableVddA(void); +void HAL_PWREx_EnableUVM(void); +void HAL_PWREx_DisableUVM(void); +void HAL_PWREx_EnableIO2VM(void); +void HAL_PWREx_DisableIO2VM(void); +void HAL_PWREx_EnableAVM1(void); +void HAL_PWREx_DisableAVM1(void); +void HAL_PWREx_EnableAVM2(void); +void HAL_PWREx_DisableAVM2(void); +#if defined (PWR_VOSR_USBPWREN) +HAL_StatusTypeDef HAL_PWREx_EnableUSBHSTranceiverSupply(void); +void HAL_PWREx_DisableUSBHSTranceiverSupply(void); +#endif /* defined (PWR_VOSR_USBPWREN) */ +#if defined (PWR_CR1_FORCE_USBPWR) +void HAL_PWREx_EnableOTGHSPHYLowPowerRetention(void); +void HAL_PWREx_DisableOTGHSPHYLowPowerRetention(void); +#endif /* defined (PWR_CR1_FORCE_USBPWR) */ +#if defined (PWR_VOSR_VDD11USBDIS) +void HAL_PWREx_EnableVDD11USB(void); +void HAL_PWREx_DisableVDD11USB(void); +#endif /* defined (PWR_VOSR_VDD11USBDIS) */ +HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *pConfigPVM); +void HAL_PWREx_EnableMonitoring(void); +void HAL_PWREx_DisableMonitoring(void); +void HAL_PWREx_EnableUCPDStandbyMode(void); +void HAL_PWREx_DisableUCPDStandbyMode(void); +void HAL_PWREx_EnableUCPDDeadBattery(void); +void HAL_PWREx_DisableUCPDDeadBattery(void); +void HAL_PWREx_PVD_PVM_IRQHandler(void); +void HAL_PWREx_UVMCallback(void); +void HAL_PWREx_IO2VMCallback(void); +void HAL_PWREx_AVM1Callback(void); +void HAL_PWREx_AVM2Callback(void); +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group4 Memories Retention Functions + * @{ + */ +void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages); +void HAL_PWREx_DisableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages); +void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection); +void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection); +void HAL_PWREx_EnableRAMsContentRunRetention(uint32_t RAMSelection); +void HAL_PWREx_DisableRAMsContentRunRetention(uint32_t RAMSelection); +void HAL_PWREx_EnableFlashFastWakeUp(void); +void HAL_PWREx_DisableFlashFastWakeUp(void); +void HAL_PWREx_EnableSRAM4FastWakeUp(void); +void HAL_PWREx_DisableSRAM4FastWakeUp(void); +HAL_StatusTypeDef HAL_PWREx_EnableBkupRAMRetention(void); +void HAL_PWREx_DisableBkupRAMRetention(void); +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group5 I/O Pull-Up Pull-Down Configuration Functions + * @{ + */ +void HAL_PWREx_EnablePullUpPullDownConfig(void); +void HAL_PWREx_DisablePullUpPullDownConfig(void); +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin); +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin); +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin); +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* STM32U5xx_HAL_PWR_EX_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h new file mode 100644 index 000000000..64a2ee38b --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h @@ -0,0 +1,4843 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_RCC_H +#define STM32U5xx_HAL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ + + uint32_t PLLMBOOST; /*!< PLLMBOOST: Prescaler for EPOD booster input clock. + This parameter must be a value of @ref RCC_PLLMBOOST_EPOD_Clock_Divider */ + + uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ + + uint32_t PLLP; /*!< PLLP: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLLR; /*!< PLLR: Division factor for system clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 128 + Only division by 1 and even division factors are allowed */ + + uint32_t PLLRGE; /*!< PLLRGE: PLL1 clock Input range + This parameter must be a value of @ref RCC_PLL_VCI_Range */ + + uint32_t PLLFRACN; /*!< PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for + PLL1 VCO It should be a value between 0 and 8191 */ + +} RCC_PLLInitTypeDef; + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F + on the other devices */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + + uint32_t LSIDiv; /*!< The division factor of the LSI. + This parameter can be a value of @ref RCC_LSI_Div */ + + uint32_t MSIState; /*!< The new state of the MSI. + This parameter can be a value of @ref RCC_MSI_Config */ + + uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t MSIClockRange; /*!< The MSI frequency range. + This parameter can be a value of @ref RCC_MSI_Clock_Range */ + + uint32_t MSIKClockRange; /*!< The MSIK frequency range. + This parameter can be a value of @ref RCC_MSIK_Clock_Range */ + + uint32_t HSI48State; /*!< The new state of the HSI48. + This parameter can be a value of @ref RCC_HSI48_Config */ + + uint32_t SHSIState; /*!< The new state of the SHSI. + This parameter can be a value of @ref RCC_SHSI_Config */ + + uint32_t MSIKState; /*!< The new state of the MSIK. + This parameter can be a value of @ref RCC_MSIK_Config */ + + RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ + +} RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock + (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ + + uint32_t APB3CLKDivider; /*!< The APB3 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ +} RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ + +/* Defines used for Flags */ +#define CR_REG_INDEX (1U) +#define BDCR_REG_INDEX (2U) +#define CSR_REG_INDEX (3U) +#define CRRCR_REG_INDEX (4U) + +#define RCC_FLAG_MASK (0x1FU) +/** + * @} + */ + +/** @defgroup RCC_Reset_Flag Reset Flag + * @{ + */ +#define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */ +#define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */ +#define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ +#define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ + RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ + RCC_RESET_FLAG_LPWR) +/** + * @} + */ + +/** @defgroup RCC_Timeout_Value Timeout Values + * @{ + */ +#define RCC_DBP_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT +/** + * @} + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE 0x0UL /*!< Oscillator configuration unchanged */ +#define RCC_OSCILLATORTYPE_HSE 0x1UL /*!< HSE to configure */ +#define RCC_OSCILLATORTYPE_HSI 0x2UL /*!< HSI to configure */ +#define RCC_OSCILLATORTYPE_LSE 0x4UL /*!< LSE to configure */ +#define RCC_OSCILLATORTYPE_LSI 0x8UL /*!< LSI to configure */ +#define RCC_OSCILLATORTYPE_MSI 0x10UL /*!< MSI to configure */ +#define RCC_OSCILLATORTYPE_HSI48 0x20UL /*!< HSI48 to configure */ +#define RCC_OSCILLATORTYPE_MSIK 0x040U /*!< MSIK to configure */ +#define RCC_OSCILLATORTYPE_SHSI 0x80UL /*!< SHSI to configure */ +/* Defines Oscillator Masks */ +#define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI | \ + RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_MSIK | \ + RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_SHSI) /*!< All Oscillator to configure */ +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ +#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ +#define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ +#define RCC_HSE_BYPASS_DIGITAL (RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON) +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ +#define RCC_LSE_ON_RTC_ONLY RCC_BDCR_LSEON /*!< LSE clock activation for RTC only */ +#define RCC_LSE_ON (RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON) /*!< LSE clock activation for RCC and peripherals */ +#define RCC_LSE_BYPASS_RTC_ONLY (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ +#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ +#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_BDCR_LSION /*!< LSI clock activation */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Div LSI Div + * @{ + */ +#define RCC_LSI_DIV1 0U /*!< LSI clock is not divided */ +#define RCC_LSI_DIV128 RCC_BDCR_LSIPREDIV /*!< LSI clock is divided by 128 */ +/** + * @} + */ + +/** @defgroup RCC_MSI_Config MSI Config + * @{ + */ +#define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ +#define RCC_MSI_ON RCC_CR_MSISON /*!< MSI clock activation */ + +#define RCC_MSICALIBRATION_DEFAULT 0x10U /*!< Default MSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_HSI48_Config HSI48 Config + * @{ + */ +#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ +#define RCC_HSI48_ON RCC_CR_HSI48ON /*!< HSI48 clock activation */ +/** + * @} + */ + +/** @defgroup RCC_MSIK_Config MSIK Config + * @{ + */ +#define RCC_MSIK_OFF 0x00000000U /*!< MSIK clock deactivation */ +#define RCC_MSIK_ON RCC_CR_MSIKON /*!< MSIK clock activation */ +/** + * @} + */ + +/** @defgroup RCC_SHSI_Config SHSI Config + * @{ + */ +#define RCC_SHSI_OFF 0x00000000U /*!< SHSI clock deactivation */ +#define RCC_SHSI_ON RCC_CR_SHSION /*!< SHSI clock activation */ +/** + * @} + */ + +/** @defgroup RCC_PLL_Config RCC PLL Config + * @{ + */ +#define RCC_PLL_NONE 0x00000000U +#define RCC_PLL_OFF 0x00000001U +#define RCC_PLL_ON 0x00000002U +/** + * @} + */ + + +/** @defgroup RCC_PLL_Clock_Output RCC PLL Clock Output + * @{ + */ +#define RCC_PLL1_DIVP RCC_PLL1CFGR_PLL1PEN +#define RCC_PLL1_DIVQ RCC_PLL1CFGR_PLL1QEN +#define RCC_PLL1_DIVR RCC_PLL1CFGR_PLL1REN + +/** + * @} + */ + +/** @defgroup RCC_PLLMBOOST_EPOD_Clock_Divider PLLMBOOST EPOD Clock Divider + * @{ + */ +#define RCC_PLLMBOOST_DIV1 0x00000000U +#define RCC_PLLMBOOST_DIV2 RCC_PLL1CFGR_PLL1MBOOST_0 +#define RCC_PLLMBOOST_DIV4 RCC_PLL1CFGR_PLL1MBOOST_1 +#define RCC_PLLMBOOST_DIV6 (RCC_PLL1CFGR_PLL1MBOOST_1 | RCC_PLL1CFGR_PLL1MBOOST_0) +#define RCC_PLLMBOOST_DIV8 RCC_PLL1CFGR_PLL1MBOOST_2 +#define RCC_PLLMBOOST_DIV10 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_0) +#define RCC_PLLMBOOST_DIV12 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1) +#define RCC_PLLMBOOST_DIV14 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1| RCC_PLL1CFGR_PLL1MBOOST_0) +#define RCC_PLLMBOOST_DIV16 RCC_PLL1CFGR_PLL1MBOOST_3 +/** + * @} + */ + +/** @defgroup RCC_PLL_VCI_Range RCC PLL1 VCI Range + * @{ + */ +#define RCC_PLLVCIRANGE_0 0x00000000U +#define RCC_PLLVCIRANGE_1 (RCC_PLL1CFGR_PLL1RGE_1 | RCC_PLL1CFGR_PLL1RGE_0) +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source + * @{ + */ +#define RCC_PLLSOURCE_NONE 0x00000000U +#define RCC_PLLSOURCE_MSI RCC_PLL1CFGR_PLL1SRC_0 +#define RCC_PLLSOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1 +#define RCC_PLLSOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) + +/** + * @} + */ + + +/** @defgroup RCC_MSI_Clock_Range MSI Clock Range + * @{ + */ +#define RCC_MSIRANGE_0 0x00000000U /*!< MSI = 48 MHz */ +#define RCC_MSIRANGE_1 RCC_ICSCR1_MSISRANGE_0 /*!< MSI = 24 MHz */ +#define RCC_MSIRANGE_2 RCC_ICSCR1_MSISRANGE_1 /*!< MSI = 16 MHz */ +#define RCC_MSIRANGE_3 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1) /*!< MSI = 12 MHz */ +#define RCC_MSIRANGE_4 RCC_ICSCR1_MSISRANGE_2 /*!< MSI = 4 MHz */ +#define RCC_MSIRANGE_5 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 2 MHz */ +#define RCC_MSIRANGE_6 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 1.33 MHz */ +#define RCC_MSIRANGE_7 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 1 MHz */ +#define RCC_MSIRANGE_8 RCC_ICSCR1_MSISRANGE_3 /*!< MSI = 3.072 MHz */ +#define RCC_MSIRANGE_9 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 1.536 MHz */ +#define RCC_MSIRANGE_10 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 1.024 MHz */ +#define RCC_MSIRANGE_11 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 768 KHz */ +#define RCC_MSIRANGE_12 (RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 400 KHz */ +#define RCC_MSIRANGE_13 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 200 KHz */ +#define RCC_MSIRANGE_14 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 133 KHz */ +#define RCC_MSIRANGE_15 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1| RCC_ICSCR1_MSISRANGE_2 |\ + RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 100 KHz */ +/** + * @} + */ + +/** @defgroup RCC_MSIK_Clock_Range MSIK Clock Range + * @{ + */ +#define RCC_MSIKRANGE_0 0x00000000U /*!< MSIK = 48 MHz */ +#define RCC_MSIKRANGE_1 RCC_ICSCR1_MSIKRANGE_0 /*!< MSIK = 24 MHz */ +#define RCC_MSIKRANGE_2 RCC_ICSCR1_MSIKRANGE_1 /*!< MSIK = 16 MHz */ +#define RCC_MSIKRANGE_3 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1) /*!< MSIK = 12 MHz */ +#define RCC_MSIKRANGE_4 RCC_ICSCR1_MSIKRANGE_2 /*!< MSIK = 4 MHz */ +#define RCC_MSIKRANGE_5 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 2 MHz */ +#define RCC_MSIKRANGE_6 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1.33 MHz */ +#define RCC_MSIKRANGE_7 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1 MHz */ +#define RCC_MSIKRANGE_8 RCC_ICSCR1_MSIKRANGE_3 /*!< MSIK = 3.072 MHz */ +#define RCC_MSIKRANGE_9 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.536 MHz */ +#define RCC_MSIKRANGE_10 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.024 MHz */ +#define RCC_MSIKRANGE_11 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 768 KHz */ +#define RCC_MSIKRANGE_12 (RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 400 KHz */ +#define RCC_MSIKRANGE_13 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 200 KHz */ +#define RCC_MSIKRANGE_14 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 133 KHz */ +#define RCC_MSIKRANGE_15 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 |\ + RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 100 KHz */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ +#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ +#define RCC_CLOCKTYPE_PCLK3 0x00000010U /*!< PCLK3 to configure */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_MSI 0x00000000U /*!< MSI selection as system clock */ +#define RCC_SYSCLKSOURCE_HSI RCC_CFGR1_SW_0 /*!< HSI selection as system clock */ +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE selection as system clock */ +#define RCC_SYSCLKSOURCE_PLLCLK (RCC_CFGR1_SW_0 | RCC_CFGR1_SW_1) /*!< PLL1 selection as system clock */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_MSI 0x00000000U /*!< MSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR1_SWS_0 /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK (RCC_CFGR1_SWS_0 | RCC_CFGR1_SWS_1) /*!< PLL1 used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 0x00000000U /*!< SYSCLK not divided */ +#define RCC_SYSCLK_DIV2 RCC_CFGR2_HPRE_3 /*!< SYSCLK divided by 2 */ +#define RCC_SYSCLK_DIV4 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 4 */ +#define RCC_SYSCLK_DIV8 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 8 */ +#define RCC_SYSCLK_DIV16 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 16 */ +#define RCC_SYSCLK_DIV64 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 64 */ +#define RCC_SYSCLK_DIV128 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 128 */ +#define RCC_SYSCLK_DIV256 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 256 */ +#define RCC_SYSCLK_DIV512 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_APB3_Clock_Source APB1 APB2 APB3 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 (0x00000000U) /*!< HCLK not divided */ +#define RCC_HCLK_DIV2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */ +#define RCC_HCLK_DIV4 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 4 */ +#define RCC_HCLK_DIV8 (RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 8 */ +#define RCC_HCLK_DIV16 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_MCO_Index MCO Index + * @{ + */ +#define RCC_MCO1 0x00000000U +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ +#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR1_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ +#define RCC_MCO1SOURCE_MSI RCC_CFGR1_MCOSEL_1 /*!< MSI selection as MCO1 source */ +#define RCC_MCO1SOURCE_HSI (RCC_CFGR1_MCOSEL_0| RCC_CFGR1_MCOSEL_1) /*!< HSI selection as MCO1 source */ +#define RCC_MCO1SOURCE_HSE RCC_CFGR1_MCOSEL_2 /*!< HSE selection as MCO1 source */ +#define RCC_MCO1SOURCE_PLL1CLK (RCC_CFGR1_MCOSEL_0|RCC_CFGR1_MCOSEL_2) /*!< PLL1CLK selection as MCO1 source */ +#define RCC_MCO1SOURCE_LSI (RCC_CFGR1_MCOSEL_1|RCC_CFGR1_MCOSEL_2) /*!< LSI selection as MCO1 source */ +#define RCC_MCO1SOURCE_LSE (RCC_CFGR1_MCOSEL_0|RCC_CFGR1_MCOSEL_1|RCC_CFGR1_MCOSEL_2) /*!< LSE selection as MCO1 source */ +#define RCC_MCO1SOURCE_HSI48 RCC_CFGR1_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ +#define RCC_MCO1SOURCE_MSIK (RCC_CFGR1_MCOSEL_0| RCC_CFGR1_MCOSEL_3) /*!< MSIK selection as MCO1 source */ +/** + * @} + */ + +/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler + * @{ + */ +#define RCC_MCODIV_1 0x00000000U /*!< MCO is divided by 1 */ +#define RCC_MCODIV_2 RCC_CFGR1_MCOPRE_0 /*!< MCO is divided by 2 */ +#define RCC_MCODIV_4 RCC_CFGR1_MCOPRE_1 /*!< MCO is divided by 4 */ +#define RCC_MCODIV_8 (RCC_CFGR1_MCOPRE_0 | RCC_CFGR1_MCOPRE_1)/*!< MCO is divided by 8 */ +#define RCC_MCODIV_16 RCC_CFGR1_MCOPRE_2 /*!< MCO is divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_Interrupt Interrupts + * @{ + */ +#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define RCC_IT_MSIRDY RCC_CIFR_MSISRDYF /*!< MSI Ready Interrupt flag */ +#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ +#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ +#define RCC_IT_PLLRDY RCC_CIFR_PLL1RDYF /*!< PLL1 Ready Interrupt flag */ +#define RCC_IT_PLL2RDY RCC_CIFR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */ +#define RCC_IT_PLL3RDY RCC_CIFR_PLL3RDYF /*!< PLL3 Ready Interrupt flag */ +#define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ +#define RCC_IT_MSIKRDY RCC_CIFR_MSIKRDYF /*!< MSIK Ready Interrupt flag */ +#define RCC_IT_SHSIRDY RCC_CIFR_SHSIRDYF /*!< SHSI Ready Interrupt flag */ +/** + * @} + */ + +/** @defgroup RCC_Flag Flags + * Elements values convention: XXXYYYYYb + * - YYYYY : Flag position in the register + * - XXX : Register index + * - 001: CR register + * - 010: BDCR register + * - 011: CSR register + * - 100: CRRCR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSISRDY_Pos)) /*!< MSI Ready flag */ +#define RCC_FLAG_MSIKRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIKRDY_Pos)) /*!< MSI Ready flag */ +#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< HSI Ready flag */ +#define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< HSE Ready flag */ +#define RCC_FLAG_PLL1RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL1RDY_Pos)) /*!< PLL Ready flag */ +#define RCC_FLAG_PLL2RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) /*!< PLL2 Ready flag */ +#define RCC_FLAG_PLL3RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) /*!< PLL3 Ready flag */ +#define RCC_FLAG_SHSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_SHSIRDY_Pos)) /*!< SHSI Ready flag */ +#define RCC_FLAG_HSI48RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos)) /*!< HSI48 Ready flag */ + +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< LSE Ready flag */ +#define RCC_FLAG_LSESYSRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSESYSRDY_Pos)) /*!< LSESYS Ready flag */ +#define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)) /*!< LSE Clock Security System Interrupt flag */ +#define RCC_FLAG_LSIRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSIRDY_Pos)) /*!< LSI Ready flag */ +/* Flags in the CSR register */ +#define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos)) /*!< Remove reset flag */ +#define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)) /*!< Option Byte Loader reset flag */ +#define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ +#define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)) /*!< BOR reset flag */ +#define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ + +/** + * @} + */ + +/** @defgroup RCC_LSEDrive_Config LSE Drive Config + * @{ + */ +#define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ +#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ +#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ +#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ +/** + * @} + */ + +/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock + * @{ + */ +#define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ +#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR1_STOPWUCK /*!< HSI selection after wake-up from STOP */ +/** + * @} + */ + +/** @defgroup RCC_Stop_KernelWakeUpClock RCC Stop KernelWakeUpClock + * @{ + */ +#define RCC_STOP_KERWAKEUPCLOCK_MSI 0x00000000U /*!< MSI kernel clock selection after wake-up from STOP */ +#define RCC_STOP_KERWAKEUPCLOCK_HSI RCC_CFGR1_STOPKERWUCK /*!< HSI kernel clock selection after wake-up from STOP */ + +/** + * @} + */ + +/** @defgroup RCC_items RCC items + * @brief RCC items to configure attributes on + * @{ + */ +#define RCC_HSI RCC_SECCFGR_HSISEC +#define RCC_HSE RCC_SECCFGR_HSESEC +#define RCC_MSI RCC_SECCFGR_MSISEC +#define RCC_LSI RCC_SECCFGR_LSISEC +#define RCC_LSE RCC_SECCFGR_LSESEC +#define RCC_SYSCLK RCC_SECCFGR_SYSCLKSEC +#define RCC_PRESC RCC_SECCFGR_PRESCSEC +#define RCC_PLL1 RCC_SECCFGR_PLL1SEC +#define RCC_PLL2 RCC_SECCFGR_PLL2SEC +#define RCC_PLL3 RCC_SECCFGR_PLL3SEC +#define RCC_ICLK RCC_SECCFGR_ICLKSEC +#define RCC_HSI48 RCC_SECCFGR_HSI48SEC +#define RCC_RMVF RCC_SECCFGR_RMVFSEC +#define RCC_ALL (RCC_HSI|RCC_HSE|RCC_MSI|RCC_LSI|RCC_LSE|RCC_HSI48| \ + RCC_SYSCLK|RCC_PRESC|RCC_PLL1|RCC_PLL2| \ + RCC_PLL3|RCC_ICLK|RCC_RMVF) +/** + * @} + */ + +/** @defgroup RCC_attributes RCC attributes + * @brief RCC privilege/non-privilege and secure/non-secure attributes + * @{ + */ +#define RCC_NSEC_PRIV 0x00000001U /*!< Non-secure Privilege attribute item */ +#define RCC_NSEC_NPRIV 0x00000002U /*!< Non-secure Non-privilege attribute item */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define RCC_SEC_PRIV 0x00000010U /*!< Secure Privilege attribute item */ +#define RCC_SEC_NPRIV 0x00000020U /*!< Secure Non-privilege attribute item */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_FMAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TSC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* JPEG */ + +#define __HAL_RCC_RAMCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_FLASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_MDF1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(DMA2D) +#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GPU2D */ + +#if defined(DCACHE2) +#define __HAL_RCC_DCACHE2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* DCACHE2 */ + +#define __HAL_RCC_GTZC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DCACHE1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SRAM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) + +#define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) + +#define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) + +#define __HAL_RCC_MDF1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) + +#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) + +#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) +#endif /* JPEG */ + +#define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) + +#define __HAL_RCC_RAMCFG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) + +#if defined(DMA2D) +#define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN) +#endif /* GPU2D */ + +#if defined(DCACHE2) +#define __HAL_RCC_DCACHE2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN) +#endif /* DCACHE2 */ + +#define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) + +#define __HAL_RCC_BKPSRAM_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN) + +#define __HAL_RCC_DCACHE1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) + +#define __HAL_RCC_SRAM1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(GPIOF) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GPIOF */ + +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined (GPIOI) +#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GPIOI */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN); \ + UNUSED(tmpreg); \ + } while(0) + +#endif /* GPIOJ */ + +#define __HAL_RCC_ADC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN); \ + UNUSED(tmpreg); \ + } while(0) +#if defined (USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) +#define __HAL_RCC_USB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE /*!< alias define for compatibility with legacy code */ +#endif /* defined (USB_OTG_FS) */ + +#if defined(RCC_AHB2ENR1_USBPHYCEN) +#define __HAL_RCC_USBPHYC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* defined (RCC_AHB2ENR1_USBPHYCEN) */ + +#if defined(AES) +#define __HAL_RCC_AES_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* AES */ + +#if defined(HASH) +#define __HAL_RCC_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* HASH */ + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(PKA) +#define __HAL_RCC_PKA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* PKA */ + +#if defined(SAES) +#define __HAL_RCC_SAES_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SAES */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPIM */ + +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* OTFDEC1 */ + +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* OTFDEC2 */ + +#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(SDMMC2) +#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SDMMC2 */ + +#define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN); \ + UNUSED(tmpreg); \ + } while(0) +#if defined(SRAM3_BASE) +#define __HAL_RCC_SRAM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SRAM3_BASE */ + +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* FMC_BASE */ + +#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPI2 */ + +#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) + +#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN) + +#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN) + +#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN) + +#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) + +#if defined(GPIOF) +#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) +#endif /* GPIOF */ + +#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) + +#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) + +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) +#endif /* GPIOI */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN) +#endif /* GPIOJ */ + +#define __HAL_RCC_ADC12_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN) + +#define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) + +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) +#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ + +#if defined(RCC_AHB2ENR1_USBPHYCEN) +#define __HAL_RCC_USBPHYC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN) +#endif /* defined (RCC_AHB2ENR1_USBPHYCEN) */ + +#if defined(AES) +#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) +#endif /* AES */ + +#if defined(HASH) +#define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN) +#endif /* HASH */ + +#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) + +#if defined(PKA) +#define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) +#endif /* PKA */ + +#if defined(SAES) +#define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) +#endif /* SAES */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) +#endif /* OCTOSPIM */ + +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) +#endif /* OTFDEC1 */ + +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) +#endif /* OTFDEC2 */ + +#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) + +#if defined(SDMMC2) +#define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) +#endif /* SDMMC2 */ + +#define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) + +#if defined(SRAM3_BASE) +#define __HAL_RCC_SRAM3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) +#endif /* SRAM3_BASE */ + +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* HSPI1 */ + +#if defined (SRAM6_BASE) +#define __HAL_RCC_SRAM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SRAM6_BASE */ + +#if defined (SRAM5_BASE) +#define __HAL_RCC_SRAM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SRAM5_BASE */ + +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) +#endif /* FMC_BASE */ + +#define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) +#endif /* OCTOSPI2 */ + +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN) +#endif /* HSPI1 */ + +#if defined (SRAM6_BASE) +#define __HAL_RCC_SRAM6_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN) +#endif /* SRAM6_BASE */ + +#if defined (SRAM5_BASE) +#define __HAL_RCC_SRAM5_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN) +#endif /* SRAM5_BASE */ +/** + * @} + */ + +/** @defgroup BUS AHB APB Peripheral Clock Enable Disable + * @{ + */ +#define __HAL_RCC_AHB1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); + +#define __HAL_RCC_AHB2_1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); + +#define __HAL_RCC_AHB2_2_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); + +#define __HAL_RCC_AHB3_CLK_DISABLE() SET_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); + +#define __HAL_RCC_APB1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); + +#define __HAL_RCC_APB2_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); + +#define __HAL_RCC_APB3_CLK_DISABLE() SET_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); + +#define __HAL_RCC_AHB1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_AHB2_1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_AHB2_2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_AHB3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \ + tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_APB1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_APB2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_APB3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \ + tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \ + UNUSED(tmpreg); \ + } while(0) + +/** + * @} + */ + +/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3ENR Peripheral Clock Enable Disable + * @brief Enable or disable the AHB3ENR peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_LPGPIO1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ADC4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DAC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPDMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ADF1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GTZC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SRAM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPGPIO1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) + +#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) + +#define __HAL_RCC_ADC4_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) + +#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) + +#define __HAL_RCC_LPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) + +#define __HAL_RCC_ADF1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) + +#define __HAL_RCC_GTZC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) + +#define __HAL_RCC_SRAM4_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(USART2) +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* USART2 */ + +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ + UNUSED(tmpreg); \ + } while(0) + + +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* USART6 */ + +#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* I2C6 */ + +#define __HAL_RCC_FDCAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(UCPD1) +#define __HAL_RCC_UCPD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* UCPD1 */ + +#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) + +#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) + +#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) + +#define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) + +#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) + +#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) + +#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) + +#if defined(USART2) +#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) +#endif /* USART2 */ + +#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) + +#define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) + +#define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) + +#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) + +#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) + +#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) + +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN) +#endif /* USART6 */ + +#define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) + +#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) + +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN) +#endif /* I2C6 */ + +#define __HAL_RCC_FDCAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) + +#if defined(UCPD1) +#define __HAL_RCC_UCPD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) +#endif /* UCPD1 */ + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined (SAI2) +#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SAI2 */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_FS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* DSI */ + +#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) + +#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) + +#define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) + +#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) + +#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) + +#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) + +#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) + +#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) + +#if defined (SAI2) +#define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) +#endif /* SAI2 */ + +#if defined (USB_DRD_FS) +#define __HAL_RCC_USB_FS_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN) +#endif /* DSI */ + +/** + * @} + */ + +/** @defgroup RCC_APB3_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable + * @brief Enable or disable the APB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_COMP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_VREF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN) + +#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN) + +#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) + +#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) + +#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) + +#define __HAL_RCC_LPTIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) + +#define __HAL_RCC_LPTIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) + +#define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN) + +#define __HAL_RCC_COMP_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN) + +#define __HAL_RCC_VREF_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) + +#define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB1 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U) + +#define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U) + +#define __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U) + +#define __HAL_RCC_MDF1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) != 0U) + +#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) + +#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) != 0U) +#endif /* JPEG */ + +#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) + +#define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) != 0U) + +#if defined(DMA2D) +#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != 0U) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN) != 0U) +#endif /* GPU2D */ + +#if defined(DCACHE2) +#define __HAL_RCC_DCACHE2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN) != 0U) +#endif /* DCACHE2 */ + +#define __HAL_RCC_GTZC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) != 0U) + +#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN) != 0U) + +#define __HAL_RCC_DCACHE1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) != 0U) + +#define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) != 0U) + +#define __HAL_RCC_GPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) == 0U) + +#define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U) + +#define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U) + +#define __HAL_RCC_MDF1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) == 0U) + +#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U) + +#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) == 0U) +#endif /* JPEG */ + +#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U) + +#define __HAL_RCC_RAMCFG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) == 0U) + +#if defined (DMA2D) +#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == 0U) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN) == 0U) +#endif /* GPU2D */ + +#if defined(DCACHE2) +#define __HAL_RCC_DCACHE2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN) == 0U) +#endif /* DCACHE2 */ + +#define __HAL_RCC_GTZC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) == 0U) + +#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN) == 0U) + +#define __HAL_RCC_DCACHE1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) == 0U) + +#define __HAL_RCC_SRAM1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) == 0U) +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB2 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) != 0U) + +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN) != 0U) + +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN) != 0U) + +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN) != 0U) + +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) != 0U) + +#if defined(GPIOF) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) != 0U) +#endif /* GPIOF */ + +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) != 0U) + +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) != 0U) + +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) != 0U) +#endif /* GPIOI */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN) != 0U) +#endif /* GPIOJ */ + +#define __HAL_RCC_ADC12_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN) != 0U) + +#define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) != 0U) + +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) != 0U) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) +#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) != 0U) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ + +#if defined(AES) +#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) != 0U) +#endif /* AES */ + +#if defined(HASH) +#define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN) != 0U) +#endif /* HASH */ + +#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) != 0U) + +#if defined(PKA) +#define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) != 0U) +#endif /* PKA */ + +#if defined(SAES) +#define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) != 0U) +#endif /* SAES */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) != 0U) +#endif /* OCTOSPIM */ + +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) != 0U) +#endif /* OTFDEC1 */ + +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) != 0U) +#endif /* OTFDEC2 */ + +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) != 0U) + +#if defined(SDMMC2) +#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) != 0U) +#endif /* SDMMC2 */ + +#define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) != 0U) + +#if defined (SRAM3_BASE) +#define __HAL_RCC_SRAM3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) != 0U) +#endif /* SRAM3_BASE */ + +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) != 0U) +#endif /* FMC_BASE */ + +#define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) != 0U) + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) != 0U) +#endif /* OCTOSPI2 */ + +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2,RCC_AHB2ENR2_HSPI1EN) != 0U) +#endif /* HSPI1 */ + +#if defined (SRAM6_BASE) +#define __HAL_RCC_SRAM6_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN) != 0U) +#endif /* SRAM6_BASE */ + +#if defined (SRAM5_BASE) +#define __HAL_RCC_SRAM5_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN) != 0U) +#endif /* SRAM5_BASE */ + +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) == 0U) + +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN) == 0U) + +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN) == 0U) + +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN) == 0U) + +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) == 0U) + +#if defined(GPIOF) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) == 0U) +#endif /* GPIOF */ + +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) == 0U) + +#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) == 0U) + +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) == 0U) +#endif /* GPIOI */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN) == 0U) +#endif /* GPIOJ */ + +#define __HAL_RCC_ADC12_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN) == 0U) + +#define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) == 0U) + +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) == 0U) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) +#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) == 0U) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ + +#if defined(AES) +#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) == 0U) +#endif /* AES */ + +#if defined(HASH) +#define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN) == 0U) +#endif /* HASH */ + +#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) == 0U) + +#if defined(PKA) +#define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) == 0U) +#endif /* PKA */ + +#if defined(SAES) +#define __HAL_RCC_SAES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) == 0U) +#endif /* SAES */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) == 0U) +#endif /* OCTOSPIM */ + +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) == 0U) +#endif /* OTFDEC1 */ + +#if defined (OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) == 0U) +#endif /* OTFDEC2 */ + +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) == 0U) + +#if defined (SDMMC2) +#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) == 0U) +#endif /* SDMMC2 */ + +#define __HAL_RCC_SRAM2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) == 0U) + +#if defined (SRAM3_BASE) +#define __HAL_RCC_SRAM3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) == 0U) +#endif /* SRAM3_BASE */ + +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) == 0U) +#endif /* FMC_BASE */ + +#define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) == 0U) + +#if defined (OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) == 0U) +#endif /* OCTOSPI2 */ + +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN) == 0U) +#endif /* HSPI1 */ + +#if defined (SRAM6_BASE) +#define __HAL_RCC_SRAM6_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN) == 0U) +#endif /* SRAM6_BASE */ + +#if defined (SRAM5_BASE) +#define __HAL_RCC_SRAM5_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN) == 0U) +#endif /* SRAM5_BASE */ +/** + * @} + */ + +/** @defgroup RCC_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB3 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_LPGPIO1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) != 0U) + +#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) != 0U) + +#define __HAL_RCC_ADC4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) != 0U) + +#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) != 0U) + +#define __HAL_RCC_LPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) != 0U) + +#define __HAL_RCC_ADF1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) != 0U) + +#define __HAL_RCC_GTZC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) != 0U) + +#define __HAL_RCC_SRAM4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) != 0U) + +#define __HAL_RCC_LPGPIO1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) == 0U) + +#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) == 0U) + +#define __HAL_RCC_ADC4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) == 0U) + +#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) == 0U) + +#define __HAL_RCC_LPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) == 0U) + +#define __HAL_RCC_ADF1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) == 0U) + +#define __HAL_RCC_GTZC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) == 0U) + +#define __HAL_RCC_SRAM4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) == 0U) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB1 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) + +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) + +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) + +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U) + +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U) + +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U) + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) + +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) + +#if defined(USART2) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) +#endif /* USART2 */ + +#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) + +#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U) + +#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U) + +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) + +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) + +#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U) + +#if defined(USART6) +#define __HAL_RCC_USART6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN) != 0U) +#endif /* USART6 */ + +#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) + +#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) + +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN) != 0U) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN) != 0U) +#endif /* I2C6 */ + +#define __HAL_RCC_FDCAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) != 0U) + +#if defined (UCPD1) +#define __HAL_RCC_UCPD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U) +#endif /* UCPD1 */ + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U) + +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U) + +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U) + +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U) + +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U) + +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U) + +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U) + +#if defined(USART2) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U) +#endif /* USART2 */ + +#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U) + +#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U) + +#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U) + +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U) + +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U) + +#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U) + +#if defined(USART6) +#define __HAL_RCC_USART6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN) == 0U) +#endif /* USART6 */ + +#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) + +#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U) + +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN) == 0U) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN) == 0U) +#endif /* I2C6 */ + +#define __HAL_RCC_FDCAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) == 0U) + +#if defined(UCPD1) +#define __HAL_RCC_UCPD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U) +#endif /* UCPD1 */ + +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB2 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) + +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) + +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) + +#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) + +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) + +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) + +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) + +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) + +#if defined (SAI2) +#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) +#endif /* SAI2 */ + +#if defined (USB_DRD_FS) +#define __HAL_RCC_USB_FS_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) != 0U) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) != 0U) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN) != 0U) +#endif /* DSI */ + +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) + +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) + +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) + +#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) + +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) + +#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) + +#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) + +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) + +#if defined (SAI2) +#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) +#endif /* SAI2 */ + +#if defined (USB_DRD_FS) +#define __HAL_RCC_USB_FS_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) == 0U) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) == 0U) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN) == 0U) +#endif /* DSI */ + +/** + * @} + */ + +/** @defgroup RCC_APB3_Peripheral_Clock_Enable_Disable_Status APB3 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB3 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN) != 0U) + +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN) != 0U) + +#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) != 0U) + +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) != 0U) + +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) != 0U) + +#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) != 0U) + +#define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) != 0U) + +#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN) != 0U) + +#define __HAL_RCC_COMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN) != 0U) + +#define __HAL_RCC_VREF_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) != 0U) + +#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) != 0U) + +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN) == 0U) + +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN) == 0U) + +#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) == 0U) + +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) == 0U) + +#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) == 0U) + +#define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) == 0U) + +#define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) == 0U) + +#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN) == 0U) + +#define __HAL_RCC_COMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN) == 0U) + +#define __HAL_RCC_VREF_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) == 0U) + +#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) == 0U) +/** + * @} + */ + +/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x0007100FU) + +#define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) + +#define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) + +#define __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) + +#define __HAL_RCC_MDF1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_MDF1RST) + +#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_JPEGRST) +#endif /* JPEG */ + +#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) + +#define __HAL_RCC_RAMCFG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) + +#if defined(DMA2D) +#define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPU2DRST) +#endif /* GPU2D */ + +#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) + +#define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) + +#define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) + +#define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) + +#define __HAL_RCC_MDF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_MDF1RST) + +#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_JPEGRST) +#endif /* JPEG */ + +#define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) + +#define __HAL_RCC_RAMCFG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) + +#if defined(DMA2D) +#define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPU2DRST) +#endif /* GPU2D */ + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() do{\ + WRITE_REG(RCC->AHB2RSTR1, 0x19BF55FFU);\ + WRITE_REG(RCC->AHB2RSTR2, 0x00000111U);\ + }while(0) + +#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST) + +#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST) + +#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST) + +#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST) + +#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST) + +#if defined(GPIOF) +#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST) +#endif /* GPIOF */ + +#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST) + +#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST) + +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST) +#endif /* GPIOI */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOJRST) +#endif /* GPIOJ */ + +#define __HAL_RCC_ADC12_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC12RST) + +#define __HAL_RCC_DCMI_PSSI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST) + +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) +#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_FORCE_RESET /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ + +#if defined(AES) +#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST) +#endif /* AES */ + +#define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST) + +#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST) + +#if defined(PKA) +#define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST) +#endif /* PKA */ + +#if defined(SAES) +#define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST) +#endif /* SAES */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST) +#endif /* OCTOSPIM */ + +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST) +#endif /* OTFDEC1 */ + +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST) +#endif /* OTFDEC2 */ + +#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST) + +#if defined(SDMMC2) +#define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST) +#endif /* SDMMC2 */ + +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST) +#endif /* FMC_BASE */ + +#define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) + +#if defined (OCTOSPI2) +#define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST) +#endif /* OCTOSPI2 */ + +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_HSPI1RST) +#endif /* HSPI1 */ + +#define __HAL_RCC_AHB2_RELEASE_RESET() do{\ + WRITE_REG(RCC->AHB2RSTR1, 0x00000000U);\ + WRITE_REG(RCC->AHB2RSTR2, 0x00000000U);\ + }while(0) + +#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST) + +#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST) + +#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST) + +#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST) + +#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST) + +#if defined(GPIOF) +#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST) +#endif /* GPIOF */ + +#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST) + +#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST) + +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST) +#endif /* GPIOI */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOJRST) +#endif /* GPIOJ */ + +#define __HAL_RCC_ADC12_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC12RST) + +#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST) + +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) +#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ + +#if defined(AES) +#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST) +#endif /* AES */ + +#define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST) + +#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST) + +#if defined(PKA) +#define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST) +#endif /* PKA */ + +#if defined(SAES) +#define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST) +#endif /* SAES */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST) +#endif /* OCTOSPIM */ + +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST) +#endif /* OTFDEC1 */ + +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST) +#endif /* OTFDEC2 */ + +#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST) + +#if defined(SDMMC2) +#define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST) +#endif /* SDMMC2 */ + +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST) +#endif /* FMC_BASE */ + +#define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST) +#endif /* OCTOSPI2 */ + +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_HSPI1RST) +#endif /* HSPI1 */ + +/** + * @} + */ + +/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000661U) + +#define __HAL_RCC_LPGPIO1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPGPIO1RST) + +#define __HAL_RCC_ADC4_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADC4RST) + +#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_DAC1RST) + +#define __HAL_RCC_LPDMA1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPDMA1RST) + +#define __HAL_RCC_ADF1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADF1RST) + +#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U) + +#define __HAL_RCC_LPGPIO1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPGPIO1RST) + +#define __HAL_RCC_ADC4_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADC4RST) + +#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_DAC1RST) + +#define __HAL_RCC_LPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPDMA1RST) + +#define __HAL_RCC_ADF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADF1RST) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ + +#define __HAL_RCC_APB1_FORCE_RESET() do { \ + WRITE_REG(RCC->APB1RSTR1, 0x027E403FU); \ + WRITE_REG(RCC->APB1RSTR2, 0x00800222U); \ + } while(0) + +#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) + +#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) + +#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) + +#define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) + +#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) + +#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) + +#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) + +#if defined (USART2) +#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) +#endif /* USART2 */ + +#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) + +#define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) + +#define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) + +#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) + +#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) + +#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) + +#if defined(USART6) +#define __HAL_RCC_USART6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART6RST) +#endif /* USART6 */ + +#define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) + +#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) + +#if defined(I2C5) +#define __HAL_RCC_I2C5_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C5RST) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C6RST) +#endif /* I2C6 */ + +#define __HAL_RCC_FDCAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST) + +#if defined(UCPD1) +#define __HAL_RCC_UCPD_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) +#endif /* UCPD1 */ + +#define __HAL_RCC_APB1_RELEASE_RESET() do { \ + WRITE_REG(RCC->APB1RSTR1, 0x00000000U); \ + WRITE_REG(RCC->APB1RSTR2, 0x00000000U); \ + } while(0) + +#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) + +#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) + +#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) + +#define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) + +#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) + +#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) + +#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) + +#if defined(USART2) +#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) +#endif /* USART2 */ + +#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) + +#define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) + +#define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) + +#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) + +#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) + +#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) + +#if defined(USART6) +#define __HAL_RCC_USART6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART6RST) +#endif /* USART6 */ + +#define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) + +#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) + +#if defined(I2C5) +#define __HAL_RCC_I2C5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C5RST) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C6RST) +#endif /* I2C6 */ + +#define __HAL_RCC_FDCAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST) + +#if defined(UCPD1) +#define __HAL_RCC_UCPD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) +#endif /* UCPD1 */ + +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00677800U) + +#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) + +#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) + +#define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) + +#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) + +#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) + +#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) + +#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) + +#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) + +#if defined(SAI2) +#define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) +#endif /* SAI2 */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_FS_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIHOSTRST) +#endif /* DSI */ + +#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) + +#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) + +#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) + +#define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) + +#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) + +#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) + +#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) + +#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) + +#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) + +#if defined(SAI2) +#define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) +#endif /* SAI2 */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_FS_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIHOSTRST) +#endif /* DSI */ + +/** + * @} + */ + +/** @defgroup RCC_APB3_Force_Release_Reset APB3 Peripheral Force Release Reset + * @brief Force or release APB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB3_FORCE_RESET() WRITE_REG(RCC->APB3RSTR, 0x0010F8E2U) + +#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SYSCFGRST) + +#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI3RST) + +#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST) + +#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST) + +#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST) + +#define __HAL_RCC_LPTIM3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST) + +#define __HAL_RCC_LPTIM4_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST) + +#define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_OPAMPRST) + +#define __HAL_RCC_COMP_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_COMPRST) + +#define __HAL_RCC_VREF_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) + +#define __HAL_RCC_APB3_RELEASE_RESET() WRITE_REG(RCC->APB3RSTR, 0x00000000U) + +#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SYSCFGRST) + +#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI3RST) + +#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST) + +#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST) + +#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST) + +#define __HAL_RCC_LPTIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST) + +#define __HAL_RCC_LPTIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST) + +#define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_OPAMPRST) + +#define __HAL_RCC_COMP_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_COMPRST) + +#define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep and Stop) mode. + * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock + * is enabled only when a peripheral requests AHB clock. + * @{ + */ +#define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) + +#define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) + +#define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) + +#define __HAL_RCC_MDF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_MDF1SMEN) + +#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) + +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_JPEGSMEN) +#endif /* JPEG */ + +#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) + +#define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) + +#if defined(DMA2D) +#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPU2DSMEN) +#endif /* GPU2D */ + +#if defined(DCACHE2) +#define __HAL_RCC_DCACHE2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE2SMEN) +#endif /* DCACHE2 */ + +#define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) + +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_BKPSRAMSMEN) + +#define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) + +#define __HAL_RCC_DCACHE1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SMEN) + +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) + +#define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) + +#define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) + +#define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) + +#define __HAL_RCC_MDF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_MDF1SMEN) + +#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) + +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_JPEGSMEN) +#endif /* JPEG */ + +#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) + +#define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) + +#if defined(DMA2D) +#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPU2DSMEN) +#endif /* GPU2D */ + +#if defined(DCACHE2) +#define __HAL_RCC_DCACHE2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE2SMEN) +#endif /* DCACHE2 */ + +#define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) + +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_BKPSRAMSMEN) + +#define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) + +#define __HAL_RCC_DCACHE1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SMEN) + +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripheral_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep and Stop) mode. + * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock + * is enabled only when a peripheral requests AHB clock. + * @{ + */ +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOASMEN) + +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOBSMEN) + +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOCSMEN) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIODSMEN) + +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOESMEN) + +#if defined(GPIOF) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOFSMEN) +#endif /* GPIOF */ + +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOGSMEN) + +#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOHSMEN) + +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOISMEN) +#endif /* GPIOI */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOJSMEN) +#endif /* GPIOJ */ + +#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC12SMEN) + +#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_DCMI_PSSISMEN) + +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) +#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ + +#if defined(RCC_AHB2SMENR1_USBPHYCSMEN) +#define __HAL_RCC_USBPHYCCLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_USBPHYCSMEN) +#endif /* RCC_AHB2SMENR1_USBPHYCSMEN */ + +#if defined(AES) +#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN) +#endif /* AES */ + +#if defined(HASH) +#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_HASHSMEN) +#endif /* HASH */ + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_RNGSMEN) + +#if defined(PKA) +#define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_PKASMEN) +#endif /* PKA */ + +#if defined(SAES) +#define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SAESSMEN) +#endif /* SAES */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OCTOSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OCTOSPIMSMEN) +#endif /* OCTOSPIM */ + +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC1SMEN) +#endif /* OTFDEC1 */ + +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC2SMEN) +#endif /* OTFDEC2 */ + +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC1SMEN) + +#if defined(SDMMC2) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC2SMEN) +#endif /* SDMMC2 */ + +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM2SMEN) + +#if defined(SRAM3_BASE) +#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM3SMEN) +#endif /* SRAM3_BASE */ + +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_FSMCSMEN) +#endif /* FMC_BASE */ + +#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI1SMEN) + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI2SMEN) +#endif /* OCTOSPI2 */ + +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_HSPI1SMEN) +#endif /* HSPI1 */ + +#if defined(SRAM6_BASE) +#define __HAL_RCC_SRAM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM6SMEN) +#endif /* SRAM6_BASE */ + +#if defined(SRAM5_BASE) +#define __HAL_RCC_SRAM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM5SMEN) +#endif /* SRAM5_BASE */ + +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOASMEN) + +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOBSMEN) + +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOCSMEN) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIODSMEN) + +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOESMEN) + +#if defined(GPIOF) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOFSMEN) +#endif /* GPIOF */ + +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOGSMEN) + +#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOHSMEN) + +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOISMEN) +#endif /* GPIOI */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOJSMEN) +#endif /* GPIOJ */ + +#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC12SMEN) + +#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_DCMI_PSSISMEN) + +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) +#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ + +#if defined(RCC_AHB2SMENR1_USBPHYCSMEN) +#define __HAL_RCC_USBPHYCCLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_USBPHYCSMEN) +#endif /* RCC_AHB2SMENR1_USBPHYCSMEN */ + +#if defined(AES) +#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN) +#endif /* AES */ + +#if defined(HASH) +#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_HASHSMEN) +#endif /* HASH */ + +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_RNGSMEN) + +#if defined(PKA) +#define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_PKASMEN) +#endif /* PKA */ + +#if defined(SAES) +#define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SAESSMEN) +#endif /* SAES */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OCTOSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OCTOSPIMSMEN) +#endif /* OCTOSPIM */ + +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC1SMEN) +#endif /* OTFDEC1 */ + +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC2SMEN) +#endif /* OTFDEC2 */ + +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC1SMEN) + +#if defined(SDMMC2) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC2SMEN) +#endif /* SDMMC2 */ + +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM2SMEN) + +#if defined(SRAM3_BASE) +#define __HAL_RCC_SRAM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM3SMEN) +#endif /* SRAM3_BASE */ + +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_FSMCSMEN) +#endif /* FMC_BASE */ + +#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI1SMEN) + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI2SMEN) +#endif /* OCTOSPI2 */ + +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_HSPI1SMEN) +#endif /* HSPI1 */ + +#if defined(SRAM6_BASE) +#define __HAL_RCC_SRAM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM6SMEN) +#endif /* SRAM6_BASE */ + +#if defined(SRAM5_BASE) +#define __HAL_RCC_SRAM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM5SMEN) +#endif /* SRAM5_BASE */ + +/** + * @} + */ + +/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3SMENR Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB3SMENR peripheral clock during Low Power (Sleep and STOP ) mode. + * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock + * is enabled only when a peripheral requests AHB clock. + * @{ + */ +#define __HAL_RCC_LPGPIO1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN) + +#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN) + +#define __HAL_RCC_ADC4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADC4SMEN) + +#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SMEN) + +#define __HAL_RCC_LPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN) + +#define __HAL_RCC_ADF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SMEN) + +#define __HAL_RCC_GTZC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_GTZC2SMEN) + +#define __HAL_RCC_SRAM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SMEN) + +#define __HAL_RCC_LPGPIO1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN) + +#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN) + +#define __HAL_RCC_ADC4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADC4SMEN) + +#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SMEN) + +#define __HAL_RCC_LPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN) + +#define __HAL_RCC_ADF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SMEN) + +#define __HAL_RCC_GTZC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_GTZC2SMEN) + +#define __HAL_RCC_SRAM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SMEN) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep and Stop) mode. + * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock + * is enabled only when a peripheral requests APB clock. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) + +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) + +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) + +#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) + +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) + +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) + +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) + +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) + +#if defined(USART2) +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) +#endif /* USART2 */ + +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) + +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) + +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) + +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) + +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) + +#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) + +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART6SMEN) +#endif /* USART6 */ + +#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) + +#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) + +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C5SMEN) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C6SMEN) +#endif /* I2C6 */ + +#define __HAL_RCC_FDCAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN) + +#if defined(UCPD1) +#define __HAL_RCC_UCPD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) +#endif /* UCPD1 */ + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) + +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) + +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) + +#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) + +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) + +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) + +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) + +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) + +#if defined(USART2) +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) +#endif /* USART2 */ + +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) + +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) + +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) + +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) + +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) + +#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) + +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART6SMEN) +#endif /* USART6 */ + +#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) + +#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) + +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C5SMEN) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C6SMEN) +#endif /* I2C6 */ + +#define __HAL_RCC_FDCAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN) + +#if defined(UCPD1) +#define __HAL_RCC_UCPD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) +#endif /* UCPD1 */ + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep and Stop) mode. + * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP or STOP mode, the pseripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock + * is enabled only when a peripheral requests APB clock. + * @{ + */ +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) + +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) + +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) + +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) + +#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) + +#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) + +#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) + +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) + +#if defined(SAI2) +#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) +#endif /* SAI2 */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USBSMEN) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_GFXTIMSMEN) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSIHOSTSMEN) +#endif /* DSI */ + +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) + +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) + +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) + +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) + +#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) + +#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) + +#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) + +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) + +#if defined(SAI2) +#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) +#endif /* SAI2 */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USBSMEN) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_GFXTIMSMEN) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSIHOSTSMEN) +#endif /* DSI */ + +/** + * @} + */ + +/** @defgroup RCC_APB3_Clock_Sleep_Enable_Disable APB3 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB3 peripheral clock during Low Power (Sleep and Stop) mode. + * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock + * is enabled only when a peripheral requests APB clock. + * @{ + */ +#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SYSCFGSMEN) + +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SPI3SMEN) + +#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPUART1SMEN) + +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_I2C3SMEN) + +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM1SMEN) + +#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM3SMEN) + +#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM4SMEN) + +#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_OPAMPSMEN) + +#define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_COMPSMEN) + +#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_VREFSMEN) + +#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_RTCAPBSMEN) + +#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SYSCFGSMEN) + +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SPI3SMEN) + +#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPUART1SMEN) + +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_I2C3SMEN) + +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM1SMEN) + +#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM3SMEN) + +#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM4SMEN) + +#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_OPAMPSMEN) + +#define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_COMPSMEN) + +#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_VREFSMEN) + +#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_RTCAPBSMEN) + +/** + * @} + */ + +/** @brief Enable or disable peripheral bus clock when SRD domain is in DRUN + * @note After reset, peripheral clock is disabled when CPUs are in CSTOP + * @{ + */ +#define __HAL_RCC_SPI3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_SPI3AMEN) + +#define __HAL_RCC_LPUART1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPUART1AMEN) + +#define __HAL_RCC_I2C3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_I2C3AMEN) + +#define __HAL_RCC_LPTIM1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM1AMEN) + +#define __HAL_RCC_LPTIM3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM3AMEN) + +#define __HAL_RCC_LPTIM4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM4AMEN) + +#define __HAL_RCC_OPAMP_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_OPAMPAMEN) + +#define __HAL_RCC_COMP12_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_COMPAMEN) + +#define __HAL_RCC_ADC4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_ADC4AMEN) + +#define __HAL_RCC_VREF_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_VREFAMEN) + +#define __HAL_RCC_RTCAPB_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_RTCAPBAMEN) + +#define __HAL_RCC_LPGPIO1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPGPIO1AMEN) + +#define __HAL_RCC_DAC1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_DAC1AMEN) + +#define __HAL_RCC_LPDMA1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPDMA1AMEN) + +#define __HAL_RCC_ADF1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_ADF1AMEN) + +#define __HAL_RCC_SRAM4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_SRAM4AMEN) + +#define __HAL_RCC_SPI3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_SPI3AMEN) + +#define __HAL_RCC_LPUART1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPUART1AMEN) + +#define __HAL_RCC_I2C3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_I2C3AMEN) + +#define __HAL_RCC_LPTIM1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM1AMEN) + +#define __HAL_RCC_LPTIM3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM3AMEN) + +#define __HAL_RCC_LPTIM4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM4AMEN) + +#define __HAL_RCC_OPAMP_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_OPAMPAMEN) + +#define __HAL_RCC_COMP12_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_COMPAMEN) + +#define __HAL_RCC_ADC4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_ADC4AMEN) + +#define __HAL_RCC_VREF_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_VREFAMEN) + +#define __HAL_RCC_RTCAPB_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_RTCAPBAMEN) + +#define __HAL_RCC_LPGPIO1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPGPIO1AMEN) + +#define __HAL_RCC_DAC1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_DAC1AMEN) + +#define __HAL_RCC_LPDMA1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPDMA1AMEN) + +#define __HAL_RCC_ADF1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_ADF1AMEN) + +#define __HAL_RCC_SRAM4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_SRAM4AMEN) + +/** + * @} + */ + + +/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset + * @{ + */ + +/** @brief Macros to force or release the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @note The BKPSRAM is not affected by this reset. + * @retval None + */ +#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) + +#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) + +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration + * @{ + */ + +/** @brief Macros to enable or disable the RTC clock. + * @note As the RTC is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the RTC + * (to be done once after reset). + * @note These macros must be used after the RTC clock source was selected. + * @retval None + */ +#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +/** + * @} + */ + +/** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + * @retval None + */ +#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) + +#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) + +/** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x20. + * @retval None + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ + MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR3_HSITRIM_Pos) + +/** + * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) + * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs. + * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication + * speed because of the HSI startup time. + * @note The enable of this function has not effect on the HSION bit. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) + +#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) + +/** + * @brief Macros to enable or disable the force of the Internal Multi Speed kernel oscillator (MSIK) + * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs. + * @note Keeping the MSIK ON in STOP mode allows to avoid slowing down the communication + * speed because of the MSIK startup time. + * @note The enable of this function has not effect on the MSIKON bit. + * @note The MSIKERON must be configured at 0 before entreing stop 3 mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_MSIKSTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSIKERON) + +#define __HAL_RCC_MSIKSTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSIKERON) + +/** + * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). + * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after + * startup from Reset, wakeup from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * @note MSI can not be stopped if it is used as system clock source. + * In this case, you have to select another source of the system + * clock then stop the MSI. + * @note After enabling the MSI, the application software should wait on + * MSIRDY flag to be set indicating that MSI clock is stable and can + * be used as system clock source. + * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator + * clock cycles. + * @retval None + */ +#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSISON) + +#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSISON) + +/** + * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode + * @note After restart from Reset , the MSI clock is around 4 MHz. + * After stop the startup clock can be MSI (at any of its possible + * frequencies, the one that was used before entering stop mode) or HSI. + * After Standby its frequency can be selected between 4 possible values + * (1, 3.072, 4 or 8 MHz). + * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready + * (MSIRDY=1). + * @note The MSI clock range after reset can be modified on the fly. + * @param __MSIRANGEVALUE__: specifies the MSI clock range. + * This parameter must be one of the following values: + * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz + * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz + * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz + * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz + * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset) + * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz + * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz + * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz + * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz + * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz + * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz + * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz + * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz + * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz + * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz + * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz + * @retval None + */ +#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \ + do { \ + SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ + MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, (__MSIRANGEVALUE__)); \ + } while(0) + +/** + * @brief Macro configures the Internal Multi Speed kernel oscillator (MSIK) clock range in run mode + * @note After restart from Reset , the MSIK clock is around 4 MHz. + * After stop the startup clock can be MSIK (at any of its possible + * frequencies, the one that was used before entering stop mode) or HSI. + * After Standby its frequency can be selected between 4 possible values + * (1, 3.072, 4 or 8 MHz). + * @note MSIKRANGE can be modified when MSIK is OFF (MSIKON=0) or when MSIK is ready + * (MSIKRDY=1). + * @note The MSI clock range after reset can be modified on the fly. + * @param __MSIKRANGEVALUE__: specifies the MSI clock range. + * @arg @ref RCC_MSIKRANGE_0 MSIK clock is around 48 MHz + * @arg @ref RCC_MSIKRANGE_1 MSIK clock is around 24 KHz + * @arg @ref RCC_MSIKRANGE_2 MSIK clock is around 16 MHz + * @arg @ref RCC_MSIKRANGE_3 MSIK clock is around 12 MHz + * @arg @ref RCC_MSIKRANGE_4 MSIK clock is around 4 MHz (default after Reset) + * @arg @ref RCC_MSIKRANGE_5 MSIK clock is around 2 MHz + * @arg @ref RCC_MSIKRANGE_6 MSIK clock is around 1.33 MHz + * @arg @ref RCC_MSIKRANGE_7 MSIK clock is around 1 MHz + * @arg @ref RCC_MSIKRANGE_8 MSIK clock is around 3.072 MHz + * @arg @ref RCC_MSIKRANGE_9 MSIK clock is around 1.536 MHz + * @arg @ref RCC_MSIKRANGE_10 MSIK clock is around 1.024 MHz + * @arg @ref RCC_MSIKRANGE_11 MSIK clock is around 768 KHz + * @arg @ref RCC_MSIKRANGE_12 MSIK clock is around 400 KHz + * @arg @ref RCC_MSIKRANGE_13 MSIK clock is around 200 KHz + * @arg @ref RCC_MSIKRANGE_14 MSIK clock is around 133 KHz + * @arg @ref RCC_MSIKRANGE_15 MSIK clock is around 100 KHz + * @retval None + */ +#define __HAL_RCC_MSIK_RANGE_CONFIG(__MSIKRANGEVALUE__) \ + do { \ + SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ + MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE, (__MSIKRANGEVALUE__)); \ + } while(0) + +/** @brief Macros to enable or disable the MSI bias mode selection. + * @note By default the MSI bias is in continuous mode in order to maintain + * the output clocks accuracy. + * @note Setting this bit reduces the MSI consumption under range 4 but decrease its accuracy. + * @retval None + */ +#define __HAL_RCC_MSIBIAS_SELECTION_ENABLE() SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS) + +#define __HAL_RCC_MSIBIAS_SELECTION_DISABLE() CLEAR_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS) + +/** @brief Macros to enable or disable LSE clock glitch filter . + * @note The glitches on LSE can be filtred by setting the LSEGFON. + * @note LSEGFON must be written when the LSE is disabled (LSEON = 0 and LSERDY = 0). + * @retval None + */ + +#define __HAL_RCC_LSE_GLITCHFILTER_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSEGFON ) + +#define __HAL_RCC_LSE_GLITCHFILTER_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEGFON ) + +/** + * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode + * After Standby its frequency can be selected between 5 possible values (4, 2, 1.33, 1, or 3.072 MHz). + * @param __MSIRANGEVALUE__: specifies the MSI clock range. + * This parameter must be one of the following values: + * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset) + * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz + * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz + * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz + * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz + * @retval None + */ +#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) do {SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL);\ + MODIFY_REG(RCC->CSR, RCC_CSR_MSISSRANGE,\ + (__MSIRANGEVALUE__) >> (RCC_ICSCR1_MSISRANGE_Pos -\ + RCC_CSR_MSISSRANGE_Pos));\ + } while(0) +/** + * @brief Macro configures the Internal Multi Speed oscillator (MSIK) clock range after Standby mode + * After Standby its frequency can be selected between 5 possible values (4, 2, 1.33, 1, or 3.072 MHz). + * @param __MSIKRANGEVALUE__: specifies the MSIK clock range. + * This parameter must be one of the following values: + * @arg @ref RCC_MSIKRANGE_4 MSIK clock is around 4 MHz (default after Reset) + * @arg @ref RCC_MSIKRANGE_5 MSIK clock is around 2 MHz + * @arg @ref RCC_MSIKRANGE_6 MSIK clock is around 1.33 MHz + * @arg @ref RCC_MSIKRANGE_7 MSIK clock is around 1 MHz + * @arg @ref RCC_MSIKRANGE_8 MSIK clock is around 3.072 MHz + * @retval None + */ +#define __HAL_RCC_MSIK_STANDBY_RANGE_CONFIG(__MSIKRANGEVALUE__) \ + do { \ + SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ + MODIFY_REG(RCC->CSR, RCC_CSR_MSIKSRANGE, \ + (__MSIKRANGEVALUE__) >> (RCC_ICSCR1_MSIKRANGE_Pos - RCC_CSR_MSIKSRANGE_Pos)); \ + } while(0) + +/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode + * @retval MSI clock range. + * This parameter must be one of the following values: + * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz + * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz + * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz + * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz + * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz + * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz + * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz + * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz + * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz + * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz + * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz + * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz + * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz + * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz + * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz + * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz + */ +#define __HAL_RCC_GET_MSI_RANGE() ((READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) != 0U) ? \ + (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE)) : \ + (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISSRANGE) << \ + (RCC_ICSCR1_MSISRANGE_Pos - RCC_CSR_MSISSRANGE_Pos))) + +/** @brief Macro to get the Internal Multi Speed kernel oscillator (MSIK) clock range in run mode + * @retval MSIK clock range. + * This parameter must be one of the following values: + * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz + * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz + * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz + * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz + * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz + * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz + * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz + * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz + * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz + * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz + * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz + * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz + * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz + * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz + * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz + * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz + */ +#define __HAL_RCC_GET_MSIK_RANGE() ((READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) != 0U) ? \ + (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE)) : \ + (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSIKSRANGE) << \ + (RCC_ICSCR1_MSIKRANGE_Pos - RCC_CSR_MSIKSRANGE_Pos))) + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + * @retval None + */ +#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSION) + +#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION|RCC_BDCR_LSIPREDIV) + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY or shutdown modes. + * @param __STATE__: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. + * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. + * @arg @ref RCC_HSE_BYPASS_DIGITAL HSE oscillator bypassed through I/O Schmitt trigger . + * @retval None + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEEXT); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ + } \ + } while(0) + +/** @brief Macro to enable or disable the LSE system clock. + * @note This clock can be used by any peripheral when its source clock is the LSE or at system + * in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed. + * @note The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by + * the CSS on LSE, by a peripheral or any other source clock using LSE. + * @retval None + */ +#define __HAL_RCC_LSESYS_ENABLE() SET_BIT(RCC->BDCR,RCC_BDCR_LSESYSEN) + +#define __HAL_RCC_LSESYS_DISABLE() CLEAR_BIT(RCC->BDCR,RCC_BDCR_LSESYSEN) + +/** @brief Macro to set Low-speed clock (LSI) divider. + * @note This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). + * The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC. + * + * @param __DIVIDER__ : specifies the divider value + * This parameter can be one of the following values + * @arg @ref RCC_LSI_DIV1 + * @arg @ref RCC_LSI_DIV128 + * @retval None + */ +#define __HAL_RCC_LSI_DIV_CONFIG(__DIVIDER__) \ + do { \ + if((__DIVIDER__) == RCC_LSI_DIV128) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV); \ + } \ + } while(0) + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg @ref RCC_LSE_ON_RTC_ONLY Turn ON the LSE oscillator to be used only for RTC. + * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator to be used by any peripheral. + * @arg @ref RCC_LSE_BYPASS_RTC_ONLY LSE oscillator bypassed with external clock to be used only for RTC. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock to be used by any peripheral + * @retval None + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON_RTC_ONLY) \ + { \ + SET_BIT(RCC->BDCR,RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS_RTC_ONLY) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + } while(0) + +/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). + * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. + * @note After enabling the HSI48, the application software should wait on HSI48RDY + * flag to be set indicating that HSI48 clock is stable. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON) + +#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON) + +/** @brief Macros to enable or disable the Internal multi-speed RC oscillator clock (MSIK). + * @note if the peripheral requests its kernel clock in Stop 0 or Stop 1 mode,MSIK is woken up + * @note After enabling the MSIK, the application software should wait on MSIKRDY + * flag to be set indicating that MSIK clock is stable. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_MSIK_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSIKON) + +#define __HAL_RCC_MSIK_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSIKON) + +/** @brief Macros to enable or disable the secure Internal High Speed oscillator (SHSI). + * @note The SHSI is stopped by hardware when entering STOP and STANDBY modes. + * @note After enabling the SHSI, the application software should wait on SHSI + * flag to be set indicating that SHSI clock is stable. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_SHSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_SHSION) + +#define __HAL_RCC_SHSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_SHSION) + +/** @brief Macros to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it cannot be changed unless the + * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by + * a Power On Reset (POR). + * + * @param __RTC_CLKSOURCE__: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected + * + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + * @retval None + */ +#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ + MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) + +/** @brief Macro to get the RTC clock source. + * @retval The returned value can be one of the following: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected + */ +#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) + +/** @brief Macros to enable or disable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) +#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) + +/** + * @brief Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK) + * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL, + * This is mainly used to save Power. + * @param __PLL1_CLOCKOUT__: specifies the PLL clock to be outputted + * This parameter can be one of the following values: + * @arg RCC_PLL1_DIVP: This clock is used to generate an accurate clock to achieve, + * high-quality audio performance on SAI interface. + * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for the USB FS(48 MHz), + * the random analog generator (<=48 MHz) and the OCTOSPI1/2. + * @arg RCC_PLL1_DIVR: This Clock is used to generate the high speed system clock (up to 160MHz) + * @retval None + * + */ +#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLL1_CLOCKOUT__) SET_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) + +#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLL1_CLOCKOUT__) CLEAR_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) + +/** + * @brief Macro to get the PLL clock output enable status. + * @param __PLL1_CLOCKOUT__ specifies the PLL1 clock to be output. + * This parameter can be one of the following values: + * @arg RCC_PLL1_DIVP: This clock is used to generate an accurate clock to achieve, + * high-quality audio performance on SAI interface. + * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for the USB FS(48 MHz), + * the random analog generator (<=48 MHz) and the OCTOSPI1/2. + * @arg RCC_PLL1_DIVR: This Clock is used to generate the high speed system clock (up to 160MHz) + * @retval SET / RESET + */ +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLL1_CLOCKOUT__) READ_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) + +/** + * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO + * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 + * @retval None + */ +#define __HAL_RCC_PLL_FRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) + +#define __HAL_RCC_PLL_FRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) + +/** + * @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param __PLL1SOURCE__: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (__PLL1SOURCE__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 . + * + * @param __PLL1MBOOST__: specifies the division factor for the EPOD clock + * This parameter must be a value of @ref RCC_PLLMBOOST_EPOD_Clock_Divider. + * + * @param __PLL1M__: specifies the division factor for PLL VCO input clock + * This parameter must be a number between 1 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 16 MHz. + * + * @param __PLL1N__: specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between 4 and 512. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 128 and 544 MHz(Voltage range 1 or 2) + * between 128 and 330 MHZ (Voltage range 3) and not allowed for Voltage range 4. + * + * @param __PLL1P__: specifies the division factor for peripheral kernel clocks. + * This parameter must be a number between 1 and 128 + * + * @param __PLL1Q__: specifies the division factor for peripheral kernel clocks. + * This parameter must be a number between 1 and 128 + * + * @param __PLL1R__: specifies the division factor for system clock. + * This parameter must be a number between 1 and 128 (Only division by 1 and even division are allowed) + * + * @retval None + */ +#define __HAL_RCC_PLL_CONFIG(__PLL1SOURCE__, __PLL1MBOOST__,__PLL1M__, __PLL1N__, __PLL1P__, __PLL1Q__, __PLL1R__) \ + do{ MODIFY_REG(RCC->PLL1CFGR,(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M|\ + RCC_PLL1CFGR_PLL1MBOOST), ((__PLL1SOURCE__) << RCC_PLL1CFGR_PLL1SRC_Pos) |\ + (((__PLL1M__) - 1U) << RCC_PLL1CFGR_PLL1M_Pos) | (__PLL1MBOOST__));\ + MODIFY_REG(RCC->PLL1DIVR ,(RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1P | RCC_PLL1DIVR_PLL1Q |\ + RCC_PLL1DIVR_PLL1R), ( (((__PLL1N__) - 1U ) & RCC_PLL1DIVR_PLL1N) |\ + ((((__PLL1P__) -1U ) << RCC_PLL1DIVR_PLL1P_Pos) & \ + RCC_PLL1DIVR_PLL1P) | \ + ((((__PLL1Q__) -1U) << RCC_PLL1DIVR_PLL1Q_Pos) & \ + RCC_PLL1DIVR_PLL1Q) |\ + ((((__PLL1R__)- 1U) << RCC_PLL1DIVR_PLL1R_Pos) & \ + RCC_PLL1DIVR_PLL1R))); \ + } while(0) + +/** @brief Macro to configure the PLLs clock source. + * @note This function must be used only when all PLLs are disabled. + * @param __PLL1SOURCE__: specifies the PLLs entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + */ +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLL1SOURCE__) MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, (__PLL1SOURCE__)) + +/** + * @brief Macro to configure the main PLL clock Fractional Part Of The Multiplication Factor + * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO + * @param __PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO + * It should be a value between 0 and 8191 + * @note Warning: The software has to set correctly these bits to insure that the VCO + * output frequency is between its valid frequency range, which is: + * 192 to 836 MHz if PLL1VCOSEL = 0 + * 150 to 420 MHz if PLL1VCOSEL = 1. + * @retval None + */ +#define __HAL_RCC_PLL_FRACN_CONFIG(__PLL1FRACN__) WRITE_REG(RCC->PLL1FRACR, \ + (uint32_t)(__PLL1FRACN__) << \ + RCC_PLL1FRACR_PLL1FRACN_Pos) + +/** @brief Macro to select the PLL1 reference frequency range. + * @param __PLL1VCIRange__: specifies the PLL1 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLLVCIRANGE_0: Range frequency is between 4 and 8 MHz + * @arg RCC_PLLVCIRANGE_1: Range frequency is between 8 and 16 MHz + * @retval None + */ +#define __HAL_RCC_PLL_VCIRANGE(__PLL1VCIRange__) \ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, (__PLL1VCIRange__)) + +/** @brief Macro to get the oscillator used as PLL1 clock source. + * @retval The oscillator used as PLL1 clock source. The returned value can be one + * of the following: + * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC)) + +/** + * @brief Macro to configure the system clock source. + * @param __SYSCLKSOURCE__: specifies the system clock source. + * This parameter can be one of the following values: + * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_PLL1CLK: PLL1 output is used as system clock source. + * @retval None + */ +#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, (__SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_PLL1CLK: PLL1 used as system clock. + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR1 & RCC_CFGR1_SWS)) + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note The LSE drive can be decreased to the lower drive capability (LSEDRV = 0) + * when the LSE is ON. However, once LSEDRV is selected, the drive + * capability can not be increased if LSEON = 1. + * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. + * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. + * @retval None + */ +#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) + +/** + * @brief Macro to configure the wake up from stop clock. + * @note The selected clock is also used as emergency clock for the clock security system on HSE. + * @param __STOPWUCLK__: specifies the clock source used after wake up from stop. + * This parameter can be one of the following values: + * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source and CSS backup clock + * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source and CSS backup clock + * @retval None + */ +#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, (__STOPWUCLK__)) + +/** + * @brief Macro to configure the Kernel wake up from stop clock. + * @param __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop + * This parameter can be one of the following values: + * @arg RCC_STOP_KERWAKEUPCLOCK_MSI: MSI selected as Kernel clock source + * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source + * @retval None + */ +#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK, (__RCC_STOPKERWUCLK__)) + +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL1CLK Main PLL clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 + * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 + * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 + * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 + * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 + */ +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable + * the selected interrupts). + * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_MSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt + * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt + * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + * @retval None + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable + * the selected interrupts). + * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_MSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt + * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt + * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + * @retval None + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] + * bits to clear the selected interrupt pending bits. + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_MSIRDY MSI ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt + * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt + * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt + * @arg @ref RCC_IT_CSS HSE Clock security system interrupt + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + * @arg @ref RCC_IT_MSIKRDY MSIK ready interrupt + * @arg @ref RCC_IT_SHSIRDY SHSI ready interrupt + * @retval None + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) + +/** @brief Check whether the RCC interrupt has occurred or not. + * @param __INTERRUPT__: specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_MSIRDY MSI ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt + * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt + * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt + * @arg @ref RCC_IT_CSS HSE Clock security system interrupt + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + * @arg @ref RCC_IT_MSIKRDY MSIK ready interrupt + * @arg @ref RCC_IT_SHSIRDY SHSI ready interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, + * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. + * @retval None + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) + +/** @brief Check whether the selected RCC flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready + * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready + * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready + * @arg @ref RCC_FLAG_PLL1RDY Main PLL1 clock ready + * @arg @ref RCC_FLAG_PLL2RDY PLL2 clock ready + * @arg @ref RCC_FLAG_PLL3RDY PLL3 clock ready + * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready + * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready + * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection + * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready + * @arg @ref RCC_FLAG_BORRST BOR reset + * @arg @ref RCC_FLAG_OBLRST OBLRST reset + * @arg @ref RCC_FLAG_PINRST Pin reset + * @arg @ref RCC_FLAG_RMVF Remove reset Flag + * @arg @ref RCC_FLAG_SFTRST Software reset + * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset + * @arg @ref RCC_FLAG_LPWRRST Low Power reset + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_FLAG(__FLAG__) ((((((((__FLAG__) >> 5UL) == 1UL) ? RCC->CR : \ + ((((__FLAG__) >> 5UL) == 2UL) ? RCC->BDCR : \ + ((((__FLAG__) >> 5UL) == 3UL) ? RCC->CSR : RCC->CIFR)))) & \ + (1UL << ((__FLAG__) & RCC_FLAG_MASK))) != 0UL) ? 1U : 0U) +/** + * @} + */ +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_MSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) + +#define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 16U)) +#define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) +#define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) ||\ + ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) + +#define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_MSI) || \ + ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI)) +#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ + ((__RANGE__) == RCC_MSIRANGE_1) || \ + ((__RANGE__) == RCC_MSIRANGE_2) || \ + ((__RANGE__) == RCC_MSIRANGE_3) || \ + ((__RANGE__) == RCC_MSIRANGE_4) || \ + ((__RANGE__) == RCC_MSIRANGE_5) || \ + ((__RANGE__) == RCC_MSIRANGE_6) || \ + ((__RANGE__) == RCC_MSIRANGE_7) || \ + ((__RANGE__) == RCC_MSIRANGE_8) || \ + ((__RANGE__) == RCC_MSIRANGE_9) || \ + ((__RANGE__) == RCC_MSIRANGE_10) || \ + ((__RANGE__) == RCC_MSIRANGE_11) || \ + ((__RANGE__) == RCC_MSIRANGE_12) || \ + ((__RANGE__) == RCC_MSIRANGE_13) || \ + ((__RANGE__) == RCC_MSIRANGE_14) || \ + ((__RANGE__) == RCC_MSIRANGE_15)) + +#define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \ + ((__RANGE__) == RCC_MSIRANGE_5) || \ + ((__RANGE__) == RCC_MSIRANGE_6) || \ + ((__RANGE__) == RCC_MSIRANGE_7) || \ + ((__RANGE__) == RCC_MSIRANGE_8)) + +#define IS_RCC_MSIK_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIKRANGE_0) || \ + ((__RANGE__) == RCC_MSIKRANGE_1) || \ + ((__RANGE__) == RCC_MSIKRANGE_2) || \ + ((__RANGE__) == RCC_MSIKRANGE_3) || \ + ((__RANGE__) == RCC_MSIKRANGE_4) || \ + ((__RANGE__) == RCC_MSIKRANGE_5) || \ + ((__RANGE__) == RCC_MSIKRANGE_6) || \ + ((__RANGE__) == RCC_MSIKRANGE_7) || \ + ((__RANGE__) == RCC_MSIKRANGE_8) || \ + ((__RANGE__) == RCC_MSIKRANGE_9) || \ + ((__RANGE__) == RCC_MSIKRANGE_10) || \ + ((__RANGE__) == RCC_MSIKRANGE_11) || \ + ((__RANGE__) == RCC_MSIKRANGE_12) || \ + ((__RANGE__) == RCC_MSIKRANGE_13) || \ + ((__RANGE__) == RCC_MSIKRANGE_14) || \ + ((__RANGE__) == RCC_MSIKRANGE_15)) + +#define IS_RCC_MSIK_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIKRANGE_4) || \ + ((__RANGE__) == RCC_MSIKRANGE_5) || \ + ((__RANGE__) == RCC_MSIKRANGE_6) || \ + ((__RANGE__) == RCC_MSIKRANGE_7) || \ + ((__RANGE__) == RCC_MSIKRANGE_8)) + +/** + * @} + */ + +/* Include RCC HAL Extended module */ +#include "stm32u5xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions **********************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +uint32_t HAL_RCC_GetPCLK3Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pRCC_ClkInitStruct, uint32_t *pFLatency); +uint32_t HAL_RCC_GetResetSource(void); +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); + +/** + * @} + */ + +/* Attributes management functions ********************************************/ +void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes); +HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); + +/** + * @} + */ + +/** + * @} + */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_RCC_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc_ex.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc_ex.h new file mode 100644 index 000000000..dc7bf097c --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc_ex.h @@ -0,0 +1,2448 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_RCC_EX_H +#define STM32U5xx_HAL_RCC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief PLL2 Clock structure definition + */ +typedef struct +{ + uint32_t PLL2Source; /*!< RCC_PLL2Source: PLL2 entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ + + uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock. + This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ + + uint32_t PLL2P; /*!< PLL2P: Division factor for system clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLL2RGE; /*!< PLL2RGE: PLL2 clock Input range + This parameter must be a value of @ref RCC_PLL_VCI_Range */ + + uint32_t PLL2FRACN; /*!< PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for + PLL2 VCO It should be a value between 0 and 8191 */ + + uint32_t PLL2ClockOut; /*!< PLL2ClockOut: specifies PLL2 output clock to be enabled. + This parameter must be a value of @ref RCC_PLL2_Clock_Output */ +} RCC_PLL2InitTypeDef; + + +/** + * @brief PLL3 Clock structure definition + */ +typedef struct +{ + uint32_t PLL3Source; /*!< RCC_PLL3Source: PLL3 entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLL3M; /*!< PLL3M: Division factor for PLL3 VCO input clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ + + uint32_t PLL3N; /*!< PLL3N: Multiplication factor for PLL3 VCO output clock. + This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ + + uint32_t PLL3P; /*!< PLL3P: Division factor for system clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLL3Q; /*!< PLL3Q: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLL3R; /*!< PLL3R: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLL3RGE; /*!< PLL3RGE: PLL3 clock Input range + This parameter must be a value of @ref RCC_PLL_VCI_Range */ + + uint32_t PLL3FRACN; /*!< PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for + PLL3 VCO It should be a value between 0 and 8191 */ + + uint32_t PLL3ClockOut; /*!< PLL3ClockOut: specifies PLL3 output clock to be enabled. + This parameter must be a value of @ref RCC_PLL3_Clock_Output */ +} RCC_PLL3InitTypeDef; + +/** + * @brief RCC PLL1 Clocks structure definition + */ +typedef struct +{ + uint32_t PLL1_P_Frequency; + uint32_t PLL1_Q_Frequency; + uint32_t PLL1_R_Frequency; +} PLL1_ClocksTypeDef; + +/** + * @brief RCC PLL2 Clocks structure definition + */ +typedef struct +{ + uint32_t PLL2_P_Frequency; + uint32_t PLL2_Q_Frequency; + uint32_t PLL2_R_Frequency; +} PLL2_ClocksTypeDef; + +/** + * @brief RCC PLL3 Clocks structure definition + */ +typedef struct +{ + uint32_t PLL3_P_Frequency; + uint32_t PLL3_Q_Frequency; + uint32_t PLL3_R_Frequency; +} PLL3_ClocksTypeDef; + + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint64_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + RCC_PLL2InitTypeDef PLL2; /*!< PLL2structure parameters. + This parameter will be used only when PLL2 is selected as kernel clock Source + for some peripherals */ + + RCC_PLL3InitTypeDef PLL3; /*!< PLL3 structure parameters. + This parameter will be used only when PLL2 is selected as kernel clock Source + for some peripherals */ + + uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + +#if defined(USART2) + uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ +#endif /* USART2 */ + + uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. + This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ + + uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. + This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ + + uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. + This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ + +#if defined(USART6) + uint32_t Usart6ClockSelection; /*!< Specifies USART6 clock source. + This parameter can be a value of @ref RCCEx_USART6_Clock_Source */ +#endif /* USART6 */ + + uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. + This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. + This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ + + uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. + This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ + + uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. + This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ + + uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. + This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ + +#if defined(I2C5) + uint32_t I2c5ClockSelection; /*!< Specifies I2C5 clock source. + This parameter can be a value of @ref RCCEx_I2C5_Clock_Source */ +#endif /* I2C5 */ + +#if defined(I2C6) + uint32_t I2c6ClockSelection; /*!< Specifies I2C6 clock source. + This parameter can be a value of @ref RCCEx_I2C6_Clock_Source */ +#endif /* I2C6 */ + + uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. + This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ + + uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. + This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ + + uint32_t Lptim34ClockSelection; /*!< Specifies LPTIM3 and LPTIM4 clock source. + This parameter can be a value of @ref RCCEx_LPTIM34_Clock_Source */ + + uint32_t Fdcan1ClockSelection; /*!< Specifies FDCAN1 kernel clock source. + This parameter can be a value of @ref RCCEx_FDCAN1_Clock_Source */ + + uint32_t Mdf1ClockSelection; /*!< Specifies MDF1 kernel clock source. + This parameter can be a value of @ref RCCEx_MDF1_Clock_Source */ + + uint32_t Adf1ClockSelection; /*!< Specifies Adf1 kernel clock source. + This parameter can be a value of @ref RCCEx_ADF1_Clock_Source */ + + uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. + This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ + +#if defined (SAI2) + uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source. + This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ +#endif /* SAI2 */ + + uint32_t RngClockSelection; /*!< Specifies RNG clock source + This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ + +#if defined(SAES) + uint32_t SaesClockSelection; /*!< Specifies SAES clock source + This parameter can be a value of @ref RCCEx_SAES_Clock_Source */ +#endif /* SAES */ + + uint32_t IclkClockSelection; /*!< Specifies intermediate clock source used by USB, RNG and SDMMC1 + This parameter can be a value of @ref RCCEx_ICLK_Clock_Source */ + + uint32_t SdmmcClockSelection; /*!< Specifies SDMMC1/2 clock source. + This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source */ + + uint32_t AdcDacClockSelection; /*!< Specifies ADC1, ADC4 and DAC interface clock source. + This parameter can be a value of @ref RCCEx_ADCDAC_Clock_Source */ + + uint32_t Dac1ClockSelection; /*!< Specifies DAC1 interface clock source. + This parameter can be a value of @ref RCCEx_DAC1_Clock_Source */ + + uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source. + This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ + +#if defined(HSPI1) + uint32_t HspiClockSelection; /*!< Specifies HexaSPI clock source. + This parameter can be a value of @ref RCCEx_HSPI_Clock_Source */ +#endif /* HSPI1 */ + + uint32_t Spi1ClockSelection; /*!< Specifies SPI1 clock source + This parameter can be a value of @ref RCCEx_SPI1_Clock_Source */ + + uint32_t Spi2ClockSelection; /*!< Specifies SPI2 clock source + This parameter can be a value of @ref RCCEx_SPI2_Clock_Source */ + + uint32_t Spi3ClockSelection; /*!< Specifies SPI3 clock source + This parameter can be a value of @ref RCCEx_SPI3_Clock_Source */ + + uint32_t RTCClockSelection; /*!< Specifies RTC clock source. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + +#if defined(LTDC) + uint32_t LtdcClockSelection; /*!< Specifies LTDC clock source. + This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */ +#endif /* LTDC */ + +#if defined(DSI) + uint32_t DsiClockSelection; /*!< Specifies DSI clock source. + This parameter can be a value of @ref RCCEx_DSI_Clock_Source */ +#endif /* DSI */ + +#if defined(USB_OTG_HS) + uint32_t UsbPhyClockSelection; /*!< Specifies USB PHY clock source. + This parameter can be a value of @ref RCCEx_USBPHY_Clock_Source */ +#endif /* USB_OTG_HS */ + +} RCC_PeriphCLKInitTypeDef; + +#if defined(CRS) + +/** + * @brief RCC_CRS Init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. + This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ + + uint32_t Source; /*!< Specifies the SYNC signal source. + This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ + + uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. + This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ + + uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC + event. It can be calculated in using macro + __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) + This parameter must be a number between 0 and 0xFFFF or a value of + @ref RCCEx_CRS_ReloadValueDefault .*/ + + uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. + This parameter must be a number between 0 and 0xFF or a value of + @ref RCCEx_CRS_ErrorLimitDefault */ + + uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. + This parameter must be a number between 0 and 0x7F or a value of + @ref RCCEx_CRS_HSI48CalibrationDefault */ + +} RCC_CRSInitTypeDef; + +/** + * @brief RCC_CRS Synchronization structure definition + */ +typedef struct +{ + uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. + This parameter must be a number between 0 and 0x3F */ + + uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter + value latched in the time of the last SYNC event. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the + frequency error counter latched in the time of the last SYNC event. + It shows whether the actual frequency is below or above the target. + This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ + +} RCC_CRSSynchroInfoTypeDef; + +#endif /* CRS */ +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source + * @{ + */ +#define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ +#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ +/** + * @} + */ + +/** @defgroup RCCEx_MSI_Pll_Mode_Selection MSI Pll Mode Selection + * @{ + */ +#define RCC_MSIKPLL_MODE_SEL 0x00000000U /*!< PLL mode applied to MSIK (MSI kernel) clock output */ +#define RCC_MSISPLL_MODE_SEL RCC_CR_MSIPLLSEL /*!< PLL mode applied to MSIS (MSI system) clock output */ +/** + * @} + */ + +/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection + * @{ + */ +#define RCC_PERIPHCLK_USART1 ((uint64_t)0x00000001U) +#if defined(USART2) +#define RCC_PERIPHCLK_USART2 ((uint64_t)0x00000002U) +#endif /* USART2 */ +#define RCC_PERIPHCLK_USART3 ((uint64_t)0x00000004U) +#define RCC_PERIPHCLK_UART4 ((uint64_t)0x00000008U) +#define RCC_PERIPHCLK_UART5 ((uint64_t)0x00000010U) +#define RCC_PERIPHCLK_LPUART1 ((uint64_t)0x00000020U) +#define RCC_PERIPHCLK_I2C1 ((uint64_t)0x00000040U) +#define RCC_PERIPHCLK_I2C2 ((uint64_t)0x00000080U) +#define RCC_PERIPHCLK_I2C3 ((uint64_t)0x00000100U) +#define RCC_PERIPHCLK_LPTIM1 ((uint64_t)0x00000200U) +#define RCC_PERIPHCLK_LPTIM2 ((uint64_t)0x00000400U) +#define RCC_PERIPHCLK_LPTIM34 ((uint64_t)0x00000800U) +#if defined(SAES) +#define RCC_PERIPHCLK_SAES ((uint64_t)0x00001000U) +#endif /* SAES */ +#define RCC_PERIPHCLK_SAI1 ((uint64_t)0x00002000U) +#if defined(SAI2) +#define RCC_PERIPHCLK_SAI2 ((uint64_t)0x00004000U) +#endif /* SAI2 */ +#define RCC_PERIPHCLK_ADCDAC ((uint64_t)0x00008000U) +#define RCC_PERIPHCLK_MDF1 ((uint64_t)0x00010000U) +#define RCC_PERIPHCLK_ADF1 ((uint64_t)0x00020000U) +#define RCC_PERIPHCLK_RTC ((uint64_t)0x00040000U) +#define RCC_PERIPHCLK_RNG ((uint64_t)0x00080000U) +#define RCC_PERIPHCLK_ICLK ((uint64_t)0x00100000U) +#define RCC_PERIPHCLK_SDMMC ((uint64_t)0x00200000U) +#define RCC_PERIPHCLK_I2C4 ((uint64_t)0x00400000U) +#define RCC_PERIPHCLK_SPI1 ((uint64_t)0x00800000U) +#define RCC_PERIPHCLK_SPI2 ((uint64_t)0x01000000U) +#define RCC_PERIPHCLK_SPI3 ((uint64_t)0x02000000U) +#define RCC_PERIPHCLK_OSPI ((uint64_t)0x04000000U) +#define RCC_PERIPHCLK_FDCAN1 ((uint64_t)0x08000000U) +#define RCC_PERIPHCLK_DAC1 ((uint64_t)0x10000000U) +#if defined(USART6) +#define RCC_PERIPHCLK_USART6 ((uint64_t)0x20000000U) +#endif /* USART6 */ +#if defined(I2C5) +#define RCC_PERIPHCLK_I2C5 ((uint64_t)0x40000000U) +#endif /* I2C5 */ +#if defined(I2C6) +#define RCC_PERIPHCLK_I2C6 ((uint64_t)0x80000000U) +#endif /* I2C6 */ +#if defined(HSPI1) +#define RCC_PERIPHCLK_HSPI ((uint64_t)0x100000000U) +#endif /* HSPI1 */ +#if defined(LTDC) +#define RCC_PERIPHCLK_LTDC ((uint64_t)0x200000000U) +#endif /* LTDC */ +#if defined(DSI) +#define RCC_PERIPHCLK_DSI ((uint64_t)0x400000000U) +#endif /* DSI */ +#if defined(USB_OTG_HS) +#define RCC_PERIPHCLK_USBPHY ((uint64_t)0x800000000U) +#endif /* USB_OTG_HS */ +#if (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx)) +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \ + RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ + RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \ + RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_LTDC | \ + RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_USBPHY) +#elif defined (STM32U5G7xx) +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \ + RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ + RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \ + RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_LTDC | \ + RCC_PERIPHCLK_USBPHY | RCC_PERIPHCLK_SAES) +#elif defined (STM32U5F7xx) +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \ + RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ + RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \ + RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_LTDC | \ + RCC_PERIPHCLK_USBPHY) +#elif (defined(STM32U595xx) || defined(STM32U5A5xx)) +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \ + RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ + RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \ + RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_USBPHY) +#elif defined(STM32U585xx) +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 |RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM34 | \ + RCC_PERIPHCLK_SAES | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ + RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG |RCC_PERIPHCLK_ICLK | \ + RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | \ + RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 |RCC_PERIPHCLK_OSPI | \ + RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1) +#elif defined(STM32U575xx) +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 |RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM34 | \ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ + RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG |RCC_PERIPHCLK_ICLK | \ + RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | \ + RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 |RCC_PERIPHCLK_OSPI | \ + RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1) +#elif defined(STM32U535xx) +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 |RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ + RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 |RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | \ + RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM34 | \ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | \ + RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_I2C4 | \ + RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \ + RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1) +#else +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 |RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ + RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 |RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | \ + RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_SAES | \ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | \ + RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_I2C4 | \ + RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \ + RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1) +#endif /* (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx)) */ +/** + * @} + */ + + +/** @defgroup RCC_PLL2_Clock_Output RCC PLL2 Clock Output + * @{ + */ +#define RCC_PLL2_DIVP RCC_PLL2CFGR_PLL2PEN +#define RCC_PLL2_DIVQ RCC_PLL2CFGR_PLL2QEN +#define RCC_PLL2_DIVR RCC_PLL2CFGR_PLL2REN +/** + * @} + */ + +/** @defgroup RCC_PLL3_Clock_Output RCC PLL3 Clock Output + * @{ + */ +#define RCC_PLL3_DIVP RCC_PLL3CFGR_PLL3PEN +#define RCC_PLL3_DIVQ RCC_PLL3CFGR_PLL3QEN +#define RCC_PLL3_DIVR RCC_PLL3CFGR_PLL3REN +/** + * @} + */ + +/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK2 0x00000000U +#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR1_USART1SEL_0 +#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR1_USART1SEL_1 +#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR1_USART1SEL_0 | RCC_CCIPR1_USART1SEL_1) +/** + * @} + */ + +#if defined(USART2) +/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source + * @{ + */ +#define RCC_USART2CLKSOURCE_PCLK1 0x00000000U +#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR1_USART2SEL_0 +#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR1_USART2SEL_1 +#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR1_USART2SEL_0 | RCC_CCIPR1_USART2SEL_1) +/** + * @} + */ +#endif /* USART2 */ + +/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source + * @{ + */ +#define RCC_USART3CLKSOURCE_PCLK1 0x00000000U +#define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR1_USART3SEL_0 +#define RCC_USART3CLKSOURCE_HSI RCC_CCIPR1_USART3SEL_1 +#define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR1_USART3SEL_0 | RCC_CCIPR1_USART3SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source + * @{ + */ +#define RCC_UART4CLKSOURCE_PCLK1 0x00000000U +#define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR1_UART4SEL_0 +#define RCC_UART4CLKSOURCE_HSI RCC_CCIPR1_UART4SEL_1 +#define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR1_UART4SEL_0 | RCC_CCIPR1_UART4SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source + * @{ + */ +#define RCC_UART5CLKSOURCE_PCLK1 0x00000000U +#define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR1_UART5SEL_0 +#define RCC_UART5CLKSOURCE_HSI RCC_CCIPR1_UART5SEL_1 +#define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR1_UART5SEL_0 | RCC_CCIPR1_UART5SEL_1) +/** + * @} + */ + +#if defined(USART6) +/** @defgroup RCCEx_USART6_Clock_Source USART6 Clock Source + * @{ + */ +#define RCC_USART6CLKSOURCE_PCLK1 0x00000000U +#define RCC_USART6CLKSOURCE_SYSCLK RCC_CCIPR2_USART6SEL_0 +#define RCC_USART6CLKSOURCE_HSI RCC_CCIPR2_USART6SEL_1 +#define RCC_USART6CLKSOURCE_LSE (RCC_CCIPR2_USART6SEL_0 | RCC_CCIPR2_USART6SEL_1) +/** + * @} + */ +#endif /* USART6 */ + +/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source + * @{ + */ +#define RCC_LPUART1CLKSOURCE_PCLK3 0x00000000U +#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR3_LPUART1SEL_0 +#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR3_LPUART1SEL_1 +#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) +#define RCC_LPUART1CLKSOURCE_MSIK RCC_CCIPR3_LPUART1SEL_2 +/** + * @} + */ + +/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source + * @{ + */ +#define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U +#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR1_I2C1SEL_0 +#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR1_I2C1SEL_1 +#define RCC_I2C1CLKSOURCE_MSIK (RCC_CCIPR1_I2C1SEL_1 | RCC_CCIPR1_I2C1SEL_0) +/** + * @} + */ + +/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source + * @{ + */ +#define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U +#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR1_I2C2SEL_0 +#define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR1_I2C2SEL_1 +#define RCC_I2C2CLKSOURCE_MSIK (RCC_CCIPR1_I2C2SEL_1 | RCC_CCIPR1_I2C2SEL_0) +/** + * @} + */ + +/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source + * @{ + */ +#define RCC_I2C3CLKSOURCE_PCLK3 0x00000000U +#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR3_I2C3SEL_0 +#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR3_I2C3SEL_1 +#define RCC_I2C3CLKSOURCE_MSIK (RCC_CCIPR3_I2C3SEL_0 | RCC_CCIPR3_I2C3SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source + * @{ + */ +#define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U +#define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR1_I2C4SEL_0 +#define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR1_I2C4SEL_1 +#define RCC_I2C4CLKSOURCE_MSIK (RCC_CCIPR1_I2C4SEL_1 | RCC_CCIPR1_I2C4SEL_0) +/** + * @} + */ + +#if defined(I2C5) +/** @defgroup RCCEx_I2C5_Clock_Source I2C5 Clock Source + * @{ + */ +#define RCC_I2C5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C5CLKSOURCE_SYSCLK RCC_CCIPR2_I2C5SEL_0 +#define RCC_I2C5CLKSOURCE_HSI RCC_CCIPR2_I2C5SEL_1 +#define RCC_I2C5CLKSOURCE_MSIK (RCC_CCIPR2_I2C5SEL_1 | RCC_CCIPR2_I2C5SEL_0) +/** + * @} + */ +#endif /* I2C5 */ + +#if defined(I2C6) +/** @defgroup RCCEx_I2C6_Clock_Source I2C6 Clock Source + * @{ + */ +#define RCC_I2C6CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C6CLKSOURCE_SYSCLK RCC_CCIPR2_I2C6SEL_0 +#define RCC_I2C6CLKSOURCE_HSI RCC_CCIPR2_I2C6SEL_1 +#define RCC_I2C6CLKSOURCE_MSIK (RCC_CCIPR2_I2C6SEL_1 | RCC_CCIPR2_I2C6SEL_0) +/** + * @} + */ +#endif /* I2C6 */ + +/** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source + * @{ + */ +#define RCC_RNGCLKSOURCE_HSI48 0x00000000U +#define RCC_RNGCLKSOURCE_HSI48_DIV2 RCC_CCIPR2_RNGSEL_0 +#define RCC_RNGCLKSOURCE_HSI RCC_CCIPR2_RNGSEL_1 +/** + * @} + */ + +#if defined(SAES) +/** @defgroup RCCEx_SAES_Clock_Source RCCEx SAES Clock Source + * @{ + */ +#define RCC_SAESCLKSOURCE_SHSI 0x00000000U +#define RCC_SAESCLKSOURCE_SHSI_DIV2 RCC_CCIPR2_SAESSEL +/** + * @} + */ +#endif /* SAES */ + +/** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source + * @{ + */ +#define RCC_SPI1CLKSOURCE_PCLK2 0x00000000U +#define RCC_SPI1CLKSOURCE_SYSCLK RCC_CCIPR1_SPI1SEL_0 +#define RCC_SPI1CLKSOURCE_HSI RCC_CCIPR1_SPI1SEL_1 +#define RCC_SPI1CLKSOURCE_MSIK (RCC_CCIPR1_SPI1SEL_0 | RCC_CCIPR1_SPI1SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source + * @{ + */ +#define RCC_SPI2CLKSOURCE_PCLK1 0x00000000U +#define RCC_SPI2CLKSOURCE_SYSCLK RCC_CCIPR1_SPI2SEL_0 +#define RCC_SPI2CLKSOURCE_HSI RCC_CCIPR1_SPI2SEL_1 +#define RCC_SPI2CLKSOURCE_MSIK (RCC_CCIPR1_SPI2SEL_0 | RCC_CCIPR1_SPI2SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source + * @{ + */ +#define RCC_SPI3CLKSOURCE_PCLK3 0x00000000U +#define RCC_SPI3CLKSOURCE_SYSCLK RCC_CCIPR3_SPI3SEL_0 +#define RCC_SPI3CLKSOURCE_HSI RCC_CCIPR3_SPI3SEL_1 +#define RCC_SPI3CLKSOURCE_MSIK (RCC_CCIPR3_SPI3SEL_0 | RCC_CCIPR3_SPI3SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM34_Clock_Source LPTIM34 Clock Source + * @{ + */ +#define RCC_LPTIM34CLKSOURCE_MSIK 0x00000000U +#define RCC_LPTIM34CLKSOURCE_LSI RCC_CCIPR3_LPTIM34SEL_0 +#define RCC_LPTIM34CLKSOURCE_HSI RCC_CCIPR3_LPTIM34SEL_1 +#define RCC_LPTIM34CLKSOURCE_LSE (RCC_CCIPR3_LPTIM34SEL_0 | RCC_CCIPR3_LPTIM34SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source + * @{ + */ +#define RCC_LPTIM1CLKSOURCE_MSIK 0x00000000U +#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR3_LPTIM1SEL_0 +#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR3_LPTIM1SEL_1 +#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR3_LPTIM1SEL +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source + * @{ + */ +#define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U +#define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR1_LPTIM2SEL_0 +#define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR1_LPTIM2SEL_1 +#define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR1_LPTIM2SEL +/** + * @} + */ + +/** @defgroup RCCEx_FDCAN1_Clock_Source FDCAN1 Kernel Clock Source + * @{ + */ +#define RCC_FDCAN1CLKSOURCE_HSE 0x00000000U +#define RCC_FDCAN1CLKSOURCE_PLL1 RCC_CCIPR1_FDCANSEL_0 +#define RCC_FDCAN1CLKSOURCE_PLL2 RCC_CCIPR1_FDCANSEL_1 +/** + * @} + */ + +/** @defgroup RCCEx_ICLK_Clock_Source ICLK Clock Source + * @{ + */ +#define RCC_ICLK_CLKSOURCE_HSI48 0x00000000U +#define RCC_ICLK_CLKSOURCE_PLL2 RCC_CCIPR1_ICLKSEL_0 +#define RCC_ICLK_CLKSOURCE_PLL1 RCC_CCIPR1_ICLKSEL_1 +#define RCC_ICLK_CLKSOURCE_MSIK RCC_CCIPR1_ICLKSEL +/** + * @} + */ + +/** @defgroup RCCEx_ADCDAC_Clock_Source ADC1 Clock Source + * @{ + */ +#define RCC_ADCDACCLKSOURCE_HCLK 0x00000000U +#define RCC_ADCDACCLKSOURCE_SYSCLK RCC_CCIPR3_ADCDACSEL_0 +#define RCC_ADCDACCLKSOURCE_PLL2 RCC_CCIPR3_ADCDACSEL_1 +#define RCC_ADCDACCLKSOURCE_HSE (RCC_CCIPR3_ADCDACSEL_0 | RCC_CCIPR3_ADCDACSEL_1) +#define RCC_ADCDACCLKSOURCE_HSI RCC_CCIPR3_ADCDACSEL_2 +#define RCC_ADCDACCLKSOURCE_MSIK (RCC_CCIPR3_ADCDACSEL_0 | RCC_CCIPR3_ADCDACSEL_2) +/** + * @} + */ + +/** @defgroup RCCEx_MDF1_Clock_Source MDF1 Clock Source + * @{ + */ +#define RCC_MDF1CLKSOURCE_HCLK 0x00000000U +#define RCC_MDF1CLKSOURCE_PLL1 RCC_CCIPR2_MDF1SEL_0 +#define RCC_MDF1CLKSOURCE_PLL3 RCC_CCIPR2_MDF1SEL_1 +#define RCC_MDF1CLKSOURCE_PIN (RCC_CCIPR2_MDF1SEL_0 | RCC_CCIPR2_MDF1SEL_1) +#define RCC_MDF1CLKSOURCE_MSIK RCC_CCIPR2_MDF1SEL_2 +/** + * @} + */ + +/** @defgroup RCCEx_ADF1_Clock_Source ADF1 Clock Source + * @{ + */ +#define RCC_ADF1CLKSOURCE_HCLK 0x00000000U +#define RCC_ADF1CLKSOURCE_PLL1 RCC_CCIPR3_ADF1SEL_0 +#define RCC_ADF1CLKSOURCE_PLL3 RCC_CCIPR3_ADF1SEL_1 +#define RCC_ADF1CLKSOURCE_PIN (RCC_CCIPR3_ADF1SEL_0 | RCC_CCIPR3_ADF1SEL_1) +#define RCC_ADF1CLKSOURCE_MSIK RCC_CCIPR3_ADF1SEL_2 +/** + * @} + */ + +/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source + * @{ + */ +#define RCC_SAI1CLKSOURCE_PLL2 0x00000000U +#define RCC_SAI1CLKSOURCE_PLL3 RCC_CCIPR2_SAI1SEL_0 +#define RCC_SAI1CLKSOURCE_PLL1 RCC_CCIPR2_SAI1SEL_1 +#define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0) +#define RCC_SAI1CLKSOURCE_HSI RCC_CCIPR2_SAI1SEL_2 +/** + * @} + */ + +#if defined(SAI2) +/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source + * @{ + */ +#define RCC_SAI2CLKSOURCE_PLL2 0x00000000U +#define RCC_SAI2CLKSOURCE_PLL3 RCC_CCIPR2_SAI2SEL_0 +#define RCC_SAI2CLKSOURCE_PLL1 RCC_CCIPR2_SAI2SEL_1 +#define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0) +#define RCC_SAI2CLKSOURCE_HSI RCC_CCIPR2_SAI2SEL_2 +/** + * @} + */ +#endif /* SAI2 */ + +/** @defgroup RCCEx_SDMMC_Clock_Source SDMMC1/2 Clock Source + * @{ + */ +#define RCC_SDMMCCLKSOURCE_CLK48 0x00000000U +#define RCC_SDMMCCLKSOURCE_PLL1 RCC_CCIPR2_SDMMCSEL +/** + * @} + */ + +/** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source + * @{ + */ +#define RCC_OSPICLKSOURCE_SYSCLK 0x00000000U +#define RCC_OSPICLKSOURCE_MSIK RCC_CCIPR2_OCTOSPISEL_0 +#define RCC_OSPICLKSOURCE_PLL1 RCC_CCIPR2_OCTOSPISEL_1 +#define RCC_OSPICLKSOURCE_PLL2 (RCC_CCIPR2_OCTOSPISEL_1|RCC_CCIPR2_OCTOSPISEL_0) +/** + * @} + */ + +#if defined(HSPI1) +/** @defgroup RCCEx_HSPI_Clock_Source HexaSPI Clock Source + * @{ + */ +#define RCC_HSPICLKSOURCE_SYSCLK ((uint32_t)0x00000000U) +#define RCC_HSPICLKSOURCE_PLL1 RCC_CCIPR2_HSPISEL_0 +#define RCC_HSPICLKSOURCE_PLL2 RCC_CCIPR2_HSPISEL_1 +#define RCC_HSPICLKSOURCE_PLL3 RCC_CCIPR2_HSPISEL +/** + * @} + */ +#endif /* HSPI1 */ + +/** @defgroup RCCEx_DAC1_Clock_Source DAC1 Clock Source + * @{ + */ +#define RCC_DAC1CLKSOURCE_LSE 0x00000000U +#define RCC_DAC1CLKSOURCE_LSI RCC_CCIPR3_DAC1SEL +/** + * @} + */ + +/** @defgroup RCC_Timicsel_items RCC timicsel items + * @brief RCC Timicsel items to configure timicsel + * @{ + */ +#define RCC_TIMIC_HSI_256 RCC_CCIPR1_TIMICSEL_2 /*!= RCC_MSIRANGE_12) \ + {\ + MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM3), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\ + RCC_ICSCR2_MSITRIM3_Pos));\ + }\ + else if(__MSIRANGE__ >= RCC_MSIRANGE_8)\ + {\ + MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM2), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\ + RCC_ICSCR2_MSITRIM2_Pos));\ + }\ + else if(__MSIRANGE__ >= RCC_MSIRANGE_4)\ + {\ + MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM1), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\ + RCC_ICSCR2_MSITRIM1_Pos));\ + } \ + else /* if(__MSIRANGE__ >= RCC_MSIRANGE_0) */\ + { \ + MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM0), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\ + RCC_ICSCR2_MSITRIM0_Pos));\ + } \ + } while(0) + +/** @brief Macro to configure timer input capture clock source. + * @param __TIMICSOURCE__ : specifies the TIMIC clock source + * This parameter can be one or a combination of the following values: + * @arg RCC_TIMIC_HSI_256: HSI/256 selected for Timer16/17 and LPTimer2 + * @arg RCC_TIMIC_MSI_1024: MSIS/1024 selected for Timer16/17 and LPTimer2 + * @arg RCC_TIMIC_MSI_4: MSIS/4 selected for Timer16/17 and LPTimer2 + * @arg RCC_TIMIC_MSIK_1024: MSIK/1024 selected for Timer16/17 and LPTimer2 + * @arg RCC_TIMIC_MSIK_4 : MSIK/4 selected for Timer16/17 and LPTimer2 + * @note combination to be avoid : + * RCC_TIMIC_MSI_1024 and RCC_TIMIC_MSIK_1024 + * RCC_TIMIC_MSI_4 and RCC_TIMIC_MSIK_4 + * @retval None + */ +#define __HAL_RCC_TIMIC_CLK_CONFIG(__TIMICSOURCE__) \ + do \ + { \ + /*Disable All TIMIC SOURCE*/ \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL,(0x00000000)); \ + /*Select TIMIC clock SOURCE*/ \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL,(uint32_t)(__TIMICSOURCE__));\ + } while(0) + +/** @brief Macro to disable timer input capture clock source. + * @retval None + */ +#define __HAL_RCC_TIMIC_CLK_DISABLE() MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL,(0x00000000)) + +/** @brief Macros to enable or disable the PLL2. + * @note After enabling PLL2, the application software should wait on + * PLL2RDY flag to be set indicating that PLL2 clock is stable and can + * be used as kernel clock source. + * @note The PLL2 is disabled by hardware when entering STOP and STANDBY modes. + * @retval None + */ +#define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON) +#define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) + +/** @brief Macro to configure the PLL2 clock source. + * @note This function must be used only when all PLL2 is disabled. + * @param __PLL2SOURCE__: specifies the PLL2 entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL2 clock entry + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL2 clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL2 clock entry + */ +#define __HAL_RCC_PLL2_PLLSOURCE_CONFIG(__PLL2SOURCE__) MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC,\ + (__PLL2SOURCE__)) + +/** @brief Macro to get the oscillator used as PLL2 clock source. + * @retval The oscillator used as PLL2 clock source. The returned value can be one + * of the following: + * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL2_OSCSOURCE() ((uint32_t)(RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC)) + +/** @brief Macro to configures the PLL2 source, multiplication and division factors. + * @note This function must be used only when PLL2 is disabled. + * @param __PLL2SOURCE__: specifies the PLL2 entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL2 clock entry + * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL2 clock entry + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL2 clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL2 clock entry + * @param __PLL2M__ specifies the division factor of PLL2 input clock. + * This parameter must be a number between Min_Data = 1 and Max_Data = 16 + * @param __PLL2N__: specifies the multiplication factor for PLL2 VCO output clock + * This parameter must be a number between 4 and 512. + * @note You have to set the PLL2N parameter correctly to ensure that the VCO + * output frequency is between 64 and 344 MHz. + * PLL2 clock frequency = f(PLL2) multiplied by PLL2N + * @param __PLL2P__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * @param __PLL2Q__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * @param __PLL2R__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * @retval None + */ +#define __HAL_RCC_PLL2_CONFIG(__PLL2SOURCE__, __PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__) \ + do \ + { \ + MODIFY_REG(RCC->PLL2CFGR,(RCC_PLL2CFGR_PLL2SRC|RCC_PLL2CFGR_PLL2M), ((__PLL2SOURCE__)<< RCC_PLL2CFGR_PLL2SRC_Pos) |\ + (((__PLL2M__) - 1U) << RCC_PLL2CFGR_PLL2M_Pos));\ + MODIFY_REG(RCC->PLL2DIVR ,(RCC_PLL2DIVR_PLL2N|RCC_PLL2DIVR_PLL2P|RCC_PLL2DIVR_PLL2Q|\ + RCC_PLL2DIVR_PLL2R), ((((__PLL2N__) - 1U) & RCC_PLL2DIVR_PLL2N) | ((((__PLL2P__) -1U)<< \ + RCC_PLL2DIVR_PLL2P_Pos) & RCC_PLL2DIVR_PLL2P) |\ + ((((__PLL2Q__) -1U) << RCC_PLL2DIVR_PLL2Q_Pos)& \ + RCC_PLL2DIVR_PLL2Q) | ((((__PLL2R__)- 1U) << \ + RCC_PLL2DIVR_PLL2R_Pos) & \ + RCC_PLL2DIVR_PLL2R))); \ + } while(0) + +/** + * @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK) + * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL2, + * This is mainly used to save Power. + * @param __PLL2_CLOCKOUT__ specifies the PLL2 clock outputted. + * This parameter can be one or a combination of the following values: + * @arg RCC_PLL2_DIVP: This clock is used to generate an accurate clock to achieve + * high-quality audio performance on SAI interface. + * @arg RCC_PLL2_DIVQ: This clock is used to generate the clock for the USB FS (48 MHz), + * the random number generator (<=48 MHz). + * @arg RCC_PLL2_DIVR: Clock used to clock ADC peripheral. + * @retval None + */ +#define __HAL_RCC_PLL2CLKOUT_ENABLE(__PLL2_CLOCKOUT__) SET_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) +#define __HAL_RCC_PLL2CLKOUT_DISABLE(__PLL2_CLOCKOUT__) CLEAR_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) + +/** + * @brief Macro to get the PLL2 clock output enable status. + * @param __PLL2_CLOCKOUT__ specifies the PLL2 clock to be outputted. + * This parameter can be one of the following values: + * This parameter can be one or a combination of the following values: + * @arg RCC_PLL2_DIVP: This clock is used to generate an accurate clock to achieve + * high-quality audio performance on SAI interface. + * @arg RCC_PLL2_DIVQ: This clock is used to generate the clock for the USB FS (48 MHz), + * the random number generator (<=48 MHz). + * @arg RCC_PLL2_DIVR: Clock used to clock ADC peripheral. + * @retval SET / RESET + */ +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG(__PLL2_CLOCKOUT__) READ_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) + +/** + * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO + * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL2 + * @retval None + */ +#define __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) +#define __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) + +/** + * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor + * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO + * @param __PLL2FRACN__: Specifies Fractional Part Of The Multiplication factor for PLL2 VCO + * It should be a value between 0 and 8191 + * @note Warning: the software has to set correctly these bits to insure that the VCO + * output frequency is between its valid frequency range, which is: + * 192 to 836 MHz if PLL2VCOSEL = 0 + * 150 to 420 MHz if PLL2VCOSEL = 1 + * @retval None + */ +#define __HAL_RCC_PLL2FRACN_CONFIG(__PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN,\ + (uint32_t)(__PLL2FRACN__) << RCC_PLL2FRACR_PLL2FRACN_Pos) + +/** @brief Macro to select the PLL2 reference frequency range. + * @param __PLL2VCIRange__: specifies the PLL2 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLLVCIRANGE_0: Range frequency is between 4 and 8 MHz + * @arg RCC_PLLVCIRANGE_1: Range frequency is between 8 and 16 MHz + * @retval None + */ +#define __HAL_RCC_PLL2_VCIRANGE(__PLL2VCIRange__) \ + MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, (__PLL2VCIRange__)) + +/** @brief Macros to enable or disable the main PLL3. + * @note After enabling PLL3, the application software should wait on + * PLL3RDY flag to be set indicating that PLL3 clock is stable and can + * be used as kernel clock source. + * @note PLL3 is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) +#define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) + +/** @brief Macro to configure the PLL3 clock source. + * @note This function must be used only when all PLL3 is disabled. + * @param __PLL3SOURCE__: specifies the PLL3 entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL3 clock entry + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL3 clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL3 clock entry + * + */ +#define __HAL_RCC_PLL3_PLLSOURCE_CONFIG(__PLL3SOURCE__) MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC, \ + (__PLL3SOURCE__)) + +/** @brief Macro to get the oscillator used as PLL3 clock source. + * @retval The oscillator used as PLL3 clock source. The returned value can be one + * of the following: + * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL3_OSCSOURCE() ((uint32_t)(RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC)) + +/** @brief Macro to configures the PLL3 source, multiplication and division factors. + * @note This function must be used only when PLL3 is disabled. + * + * @param __PLL3SOURCE__: specifies the PLL3 entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL3 clock entry + * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL3 clock entry + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL3 clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL3 clock entry + * @param __PLL3M__ specifies the division factor of PLL3 input clock. + * This parameter must be a number between Min_Data = 1 and Max_Data = 16 + * @param __PLL3N__: specifies the multiplication factor for PLL3 VCO output clock + * This parameter must be a number between 4 and 512. + * @note You have to set the PLL3N parameter correctly to ensure that the VCO + * output frequency is between 64 and 344 MHz. + * PLL3 clock frequency = f(PLL3) multiplied by PLL3N + * @param __PLL3P__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * @param __PLL3Q__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * @param __PLL3R__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * @retval None + */ +#define __HAL_RCC_PLL3_CONFIG(__PLL3SOURCE__, __PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__) \ + do\ + {\ + MODIFY_REG(RCC->PLL3CFGR,(RCC_PLL3CFGR_PLL3SRC|RCC_PLL3CFGR_PLL3M), ((__PLL3SOURCE__) << RCC_PLL3CFGR_PLL3SRC_Pos)|\ + (((__PLL3M__) - 1U) << RCC_PLL3CFGR_PLL3M_Pos));\ + MODIFY_REG(RCC->PLL3DIVR ,(RCC_PLL3DIVR_PLL3N|RCC_PLL3DIVR_PLL3P|RCC_PLL3DIVR_PLL3Q|RCC_PLL3DIVR_PLL3R),\ + ((((__PLL3N__) - 1U) & RCC_PLL3DIVR_PLL3N) | ((((__PLL3P__) -1U) << RCC_PLL3DIVR_PLL3P_Pos) &\ + RCC_PLL3DIVR_PLL3P) | ((((__PLL3Q__) -1U) << \ + RCC_PLL3DIVR_PLL3Q_Pos) & \ + RCC_PLL3DIVR_PLL3Q) | \ + ((((__PLL3R__)- 1U) << RCC_PLL3DIVR_PLL3R_Pos) & RCC_PLL3DIVR_PLL3R))); \ + } while(0) + +/** + * @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor + * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO + * @param __PLL3FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL3 VCO + * It should be a value between 0 and 8191 + * @note Warning: the software has to set correctly these bits to insure that the VCO + * output frequency is between its valid frequency range, which is: + * 192 to 836 MHz if PLL3VCOSEL = 0 + * 150 to 420 MHz if PLL3VCOSEL = 1 + * @retval None + */ +#define __HAL_RCC_PLL3FRACN_CONFIG(__PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN, \ + (uint32_t)(__PLL3FRACN__) << RCC_PLL3FRACR_PLL3FRACN_Pos) + +/** @brief Macro to select the PLL3 reference frequency range. + * @param __PLL3VCIRange__: specifies the PLL1 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLLVCIRANGE_0: Range frequency is between 4 and 8 MHz + * @arg RCC_PLLVCIRANGE_1: Range frequency is between 8 and 16 MHz + * @retval None + */ +#define __HAL_RCC_PLL3_VCIRANGE(__PLL3VCIRange__) \ + MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3RGE, (__PLL3VCIRange__)) + +/** + * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO + * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL3 + * @retval None + */ +#define __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) +#define __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) + +/** + * @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK) + * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL3, + * This is mainly used to save Power. + * @param __PLL3_CLOCKOUT__: specifies the PLL3 clock to be outputted + * This parameter can be one of the following values: + * @arg RCC_PLL3_DIVP: This clock is used to generate an accurate clock to achieve + * high-quality audio performance on SAI interface. + * @retval None + */ +#define __HAL_RCC_PLL3CLKOUT_ENABLE(__PLL3_CLOCKOUT__) SET_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) +#define __HAL_RCC_PLL3CLKOUT_DISABLE(__PLL3_CLOCKOUT__) CLEAR_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) + +/** + * @brief Macro to get clock output enable status (PLL3_SAI2). + * @param __PLL3_CLOCKOUT__ specifies the PLL3 clock to be outputted. + * This parameter can be one of the following values: + * @arg RCC_PLL3_DIVP: This clock is used to generate an accurate clock to achieve + * high-quality audio performance on SAI interface. + * @retval SET / RESET + */ +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG(__PLL3_CLOCKOUT__) READ_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) + +/** @brief Macro to configure the ADC1, ADC2, ADC4 and DAC interface clock. + * @param __ADCDAC_CLKSOURCE__ specifies the ADC1, ADC4 and DAC digital interface clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock selected as ADC1, ADC2, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock selected as ADC1, ADC2 ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock selected as ADC1, ADC2 ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock selected as ADC1, ADC2 ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock selected as ADC1, ADC2 ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock selected as ADC1, ADC2 ADC4 and DAC clock + * @retval None + */ +#define __HAL_RCC_ADCDAC_CONFIG(__ADCDAC_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADCDACSEL, (uint32_t)(__ADCDAC_CLKSOURCE__)) + +/** @brief Macro to get the ADCDAC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock used as ADC1, ADC2, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock used as ADC1, ADC2, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock used as ADC1, ADC2, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock used as ADC1, ADC2, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock used as ADC1, ADC2, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock used as ADC1, ADC2, ADC4 and DAC clock + */ +#define __HAL_RCC_GET_ADCDAC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_ADCDACSEL))) + +/** @brief Macro to configure the CLK48 source (CLK48CLK). + * @param __CLK48_SOURCE__: specifies the CLK48 clock source. + * This parameter can be one of the following values: + * @arg RCC_CLK48CLKSOURCE_HSI48: HSI48 selected as CLK48 source + * @arg RCC_CLK48CLKSOURCE_PLL2 : PLL2 selected as CLK48 source + * @arg RCC_CLK48CLKSOURCE_PLL1 : PLL1 selected as CLK48 source + * @arg RCC_CLK48CLKSOURCE_MSIK : MSIK selected as CLK48 source + */ +#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL, (uint32_t)(__CLK48_SOURCE__)) + +/** @brief macro to get the CLK48 source. + * @retval The clock source can be one of the following values: + * @arg RCC_CLK48CLKSOURCE_HSI48: HSI48 used as CLK48 source + * @arg RCC_CLK48CLKSOURCE_PLL2 : PLL2 used as CLK48 source + * @arg RCC_CLK48CLKSOURCE_PLL1 : PLL1 used as CLK48 source + * @arg RCC_CLK48CLKSOURCE_MSIK : MSIK used as CLK48 source + */ +#define __HAL_RCC_GET_ICLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL))) + +/** @brief Macro to configure the FDCAN1 kernel clock (FDCAN1CLK). + * @param __FDCAN1_CLKSOURCE__ specifies the FDCAN1 kernel clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_FDCAN1CLKSOURCE_HSE HSE selected as FDCAN1 kernel clock + * @arg @ref RCC_FDCAN1CLKSOURCE_PLL1 PLL1 Clock selected as FDCAN1 kernel clock + * @arg @ref RCC_FDCAN1CLKSOURCE_PLL2 PLL2 Clock selected as FDCAN1 kernel clock + * @retval None + */ +#define __HAL_RCC_FDCAN1_CONFIG(__FDCAN1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL, (uint32_t)(__FDCAN1_CLKSOURCE__)) + +/** @brief Macro to get the FDCAN1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_FDCAN1CLKSOURCE_HSE HSE selected as FDCAN1 kernel clock + * @arg @ref RCC_FDCAN1CLKSOURCE_PLL1 PLL1 Clock selected as FDCAN1 kernel clock + * @arg @ref RCC_FDCAN1CLKSOURCE_PLL2 PLL2 Clock selected as FDCAN1 kernel clock + */ +#define __HAL_RCC_GET_FDCAN1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL))) + +/** @brief Macro to configure the LPTIM34 clock (LPTIM34CLK). + * @param __LPTIM34_CLKSOURCE__ specifies the LPTIM34 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPTIM34CLKSOURCE_MSIK MSIK selected as LPTIM34 clock + * @arg @ref RCC_LPTIM34CLKSOURCE_LSI LSI selected as LPTIM34 clock + * @arg @ref RCC_LPTIM34CLKSOURCE_HSI HSI selected as LPTIM34 clock + * @arg @ref RCC_LPTIM34CLKSOURCE_LSE LSE selected as LPTIM34 clock + * @retval None + */ +#define __HAL_RCC_LPTIM34_CONFIG(__LPTIM34_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPTIM34SEL, (uint32_t)(__LPTIM34_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM34 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPTIM34CLKSOURCE_MSIK MSIK selected as LPTIM34 clock + * @arg @ref RCC_LPTIM34CLKSOURCE_LSI LSI selected as LPTIM34 clock + * @arg @ref RCC_LPTIM34CLKSOURCE_HSI HSI selected as LPTIM34 clock + * @arg @ref RCC_LPTIM34CLKSOURCE_LSE LSE selected as LPTIM34 clock + */ +#define __HAL_RCC_GET_LPTIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPTIM34SEL))) + +/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). + * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPTIM1CLKSOURCE_MSIK MSIK selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_HSI HSI selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock + * @retval None + */ +#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPTIM1CLKSOURCE_MSIK MSIK selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_HSI HSI selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPTIM1SEL))) + +/** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). + * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSI LSI selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_HSI HSI selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock + * @retval None + */ +#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_HSI HSI selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock + */ +#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL))) + +/** @brief macro to configure the SPI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI1CLKSOURCE_PCLK2 : PCLK2 Clock selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_HSI : HSI Clock selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_MSIK : MSIK Clock selected as SPI1 clock + */ + +#define __HAL_RCC_SPI1_CONFIG(__SPI1CLKSource__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SPI1SEL, (uint32_t)(__SPI1CLKSource__)) + +/** @brief macro to get the SPI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI1CLKSOURCE_PCLK2 : PCLK2 Clock used as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_SYSCLK : SYSCLK Clock used as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_HSI : HSI Clock used as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_MSIK : MSIK Clock used as SPI1 clock + */ +#define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SPI1SEL))) + +/** @brief macro to configure the SPI2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI2CLKSOURCE_PCLK3 : PCLK3 selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_HSI : HSI Clock selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_MSIK : MSIK Clock selected as SPI2 clock + */ + +#define __HAL_RCC_SPI2_CONFIG(__SPI2CLKSource__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SPI2SEL, (uint32_t)(__SPI2CLKSource__)) + +/** @brief macro to get the SPI2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI2CLKSOURCE_PCLK1 : PCLK1 Clock used as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_SYSCLK : SYSCLK Clock used as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_HSI : HSI Clock used as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_MSIK : MSIK Clock used as SPI2 clock + */ +#define __HAL_RCC_GET_SPI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SPI2SEL))) + +/** @brief macro to configure the SPI3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI3CLKSOURCE_PCLK3 : PCLK3 selected as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_HSI : HSI Clock selected as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_MSIK : MSIK Clock selected as SPI3 clock + */ +#define __HAL_RCC_SPI3_CONFIG(__SPI3CLKSource__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL, (uint32_t)(__SPI3CLKSource__)) + +/** @brief macro to get the SPI3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI3CLKSOURCE_PCLK3 : PCLK3 used as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_SYSCLK : SYSCLK Clock used as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_HSI : HSI Clock used as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_MSIK : MSIK Clock used as SPI3 clock + */ +#define __HAL_RCC_GET_SPI3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL))) + + +/** @brief Macro to configure the I2C1 clock (I2C1CLK). + * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_MSIK MSIK selected as I2C1 clock + * @retval None + */ +#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) + +/** @brief Macro to get the I2C1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_MSIK MSIK selected as I2C1 clock + */ +#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL))) + +/** @brief Macro to configure the I2C2 clock (I2C2CLK). + * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_MSIK MSIK selected as I2C2 clock + * @retval None + */ +#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) + +/** @brief Macro to get the I2C2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_MSIK MSIK selected as I2C2 clock + */ +#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C2SEL))) + +/** @brief Macro to configure the I2C3 clock (I2C3CLK). + * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C3CLKSOURCE_PCLK3 : PCLK3 selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_HSI : HSI selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_MSIK : MSIK selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK : System Clock selected as I2C3 clock + * @retval None + */ +#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) + +/** @brief Macro to get the I2C3 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C3CLKSOURCE_PCLK3 : PCLK3 used as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_HSI : HSI used as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_MSIK : MSIK used as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK : System Clock used as I2C3 clock + */ +#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_I2C3SEL))) + +/** @brief Macro to configure the I2C4 clock (I2C4CLK). + * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock + * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock + * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock + * @arg @ref RCC_I2C4CLKSOURCE_MSIK MSIK selected as I2C4 clock + * @retval None + */ +#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) + +/** @brief Macro to get the I2C4 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock + * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock + * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock + * @arg @ref RCC_I2C4CLKSOURCE_MSIK MSIK selected as I2C4 clock + */ +#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C4SEL))) + +#if defined(I2C5) +/** @brief Macro to configure the I2C5 clock (I2C5CLK). + * + * @param __I2C5_CLKSOURCE__ specifies the I2C5 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C5CLKSOURCE_PCLK1 PCLK1 selected as I2C5 clock + * @arg @ref RCC_I2C5CLKSOURCE_SYSCLK System Clock selected as I2C5 clock + * @arg @ref RCC_I2C5CLKSOURCE_HSI HSI selected as I2C5 clock + * @arg @ref RCC_I2C5CLKSOURCE_MSIK MSIK selected as I2C5 clock + * @retval None + */ +#define __HAL_RCC_I2C5_CONFIG(__I2C5_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C5SEL, (uint32_t)(__I2C5_CLKSOURCE__)) + +/** @brief Macro to get the I2C5 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C5CLKSOURCE_PCLK1 PCLK1 selected as I2C5 clock + * @arg @ref RCC_I2C5CLKSOURCE_SYSCLK System Clock selected as I2C5 clock + * @arg @ref RCC_I2C5CLKSOURCE_HSI HSI selected as I2C5 clock + * @arg @ref RCC_I2C5CLKSOURCE_MSIK MSIK selected as I2C5 clock + */ +#define __HAL_RCC_GET_I2C5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C5SEL))) +#endif /* I2C5 */ + +#if defined(I2C6) +/** @brief Macro to configure the I2C6 clock (I2C6CLK). + * + * @param __I2C6_CLKSOURCE__ specifies the I2C6 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C6CLKSOURCE_PCLK1 PCLK1 selected as I2C6 clock + * @arg @ref RCC_I2C6CLKSOURCE_SYSCLK System Clock selected as I2C6 clock + * @arg @ref RCC_I2C6CLKSOURCE_HSI HSI selected as I2C6 clock + * @arg @ref RCC_I2C6CLKSOURCE_MSIK MSIK selected as I2C6 clock + * @retval None + */ +#define __HAL_RCC_I2C6_CONFIG(__I2C6_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C6SEL, (uint32_t)(__I2C6_CLKSOURCE__)) + +/** @brief Macro to get the I2C6 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C6CLKSOURCE_PCLK1 PCLK1 selected as I2C6 clock + * @arg @ref RCC_I2C6CLKSOURCE_SYSCLK System Clock selected as I2C6 clock + * @arg @ref RCC_I2C6CLKSOURCE_HSI HSI selected as I2C6 clock + * @arg @ref RCC_I2C6CLKSOURCE_MSIK MSIK selected as I2C6 clock + */ +#define __HAL_RCC_GET_I2C6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C6SEL))) +#endif /* I2C6 */ + +/** @brief Macro to configure the USART1 clock (USART1CLK). + * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK1 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock + * @retval None + */ +#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) + +/** @brief Macro to get the USART1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK1 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + */ +#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART1SEL))) + +#if defined(USART2) +/** @brief Macro to configure the USART2 clock (USART2CLK). + * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + * @retval None + */ +#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) + +/** @brief Macro to get the USART2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + */ +#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART2SEL))) +#endif /* USART2 */ + +/** @brief Macro to configure the USART3 clock (USART3CLK). + * + * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + * @retval None + */ +#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) + +/** @brief Macro to get the USART3 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + */ +#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART3SEL))) + +/** @brief Macro to configure the UART4 clock (UART4CLK). + * + * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock + * @retval None + */ +#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) + +/** @brief Macro to get the UART4 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock + */ +#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART4SEL))) + +/** @brief Macro to configure the UART5 clock (UART5CLK). + * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock + * @retval None + */ +#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) + +/** @brief Macro to get the UART5 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock + */ +#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART5SEL))) + +#if defined(USART6) +/** @brief Macro to configure the USART6 clock (USART6CLK). + * + * @param __USART6_CLKSOURCE__ specifies the USART6 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART6CLKSOURCE_PCLK1 PCLK1 selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_SYSCLK System Clock selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock + * @retval None + */ +#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) + +/** @brief Macro to get the USART6 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART6CLKSOURCE_PCLK1 PCLK1 selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_SYSCLK System Clock selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock + */ +#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USART6SEL))) +#endif /* USART6 */ + +/** @brief Macro to configure the LPUART1 clock (LPUART1CLK). + * + * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPUART1CLKSOURCE_PCLK3 PCLK3 selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_MSIK MSIK selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock + * @retval None + */ +#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) + +/** @brief Macro to get the LPUART1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPUART1CLKSOURCE_PCLK3 PCLK3 selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_MSIK MSIK selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock + */ +#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL))) + +/** @brief Macro to configure the OctoSPI clock. + * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock + * @arg @ref RCC_OSPICLKSOURCE_MSIK MSIK clock selected as OctoSPI clock + * @arg @ref RCC_OSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as OctoSPI clock + * @arg @ref RCC_OSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as OctoSPI clock + * @retval None + */ +#define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OCTOSPISEL, (uint32_t)(__OSPI_CLKSOURCE__)) + +/** @brief Macro to get the OctoSPI clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock + * @arg @ref RCC_OSPICLKSOURCE_MSIK MSIK clock selected as OctoSPI clock + * @arg @ref RCC_OSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as OctoSPI clock + * @arg @ref RCC_OSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as OctoSPI clock + */ +#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OCTOSPISEL))) + +#if defined(HSPI1) +/** @brief Macro to configure the HexaSPI clock. + * @param __HSPI_CLKSOURCE__ specifies the HexaSPI clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_HSPICLKSOURCE_SYSCLK System Clock selected as HexaSPI clock + * @arg @ref RCC_HSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as HexaSPI clock + * @arg @ref RCC_HSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as HexaSPI clock + * @arg @ref RCC_HSPICLKSOURCE_PLL3 PLL3 R divider clock selected as HexaSPI clock + * @retval None + */ +#define __HAL_RCC_HSPI_CONFIG(__HSPI_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_HSPISEL, (uint32_t)(__HSPI_CLKSOURCE__)) + +/** @brief Macro to get the HexaSPI clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_HSPICLKSOURCE_SYSCLK System Clock selected as HexaSPI clock + * @arg @ref RCC_HSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as HexaSPI clock + * @arg @ref RCC_HSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as HexaSPI clock + * @arg @ref RCC_HSPICLKSOURCE_PLL3 PLL3 R divider clock selected as HexaSPI clock + */ +#define __HAL_RCC_GET_HSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_HSPISEL))) +#endif /* HSPI1 */ + +/** @brief Macro to configure the SDMMC1/2 clock (SDMMCCLK). + * @param __SDMMC_CLKSOURCE__: specifies the SDMMC1/2 clock source. + * This parameter can be one of the following values: + * @arg RCC_SDMMCCLKSOURCE_CLK48: CLK48 selected as SDMMC1/2 clock + * @arg RCC_SDMMCCLKSOURCE_PLL1: PLL1 P selected as SDMMC1/2 clock + */ +#define __HAL_RCC_SDMMC_CONFIG(__SDMMC_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, (uint32_t)(__SDMMC_CLKSOURCE__)) + +/** @brief macro to get the SDMMC1/2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SDMMCCLKSOURCE_CLK48: CLK48 selected as SDMMC1/2 clock + * @arg RCC_SDMMCCLKSOURCE_PLL1: PLL1 P selected as SDMMC1/2 clock + */ +#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL))) + +/** @brief macro to configure the RNG clock (RNGCLK). + * @param __RNG_CLKSource__: specifies the RNG clock source. + * This parameter can be one of the following values: + * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock + * @arg RCC_RNGCLKSOURCE_HSI48_DIV2: HSI48/2 selected as RNG clock + * @arg RCC_RNGCLKSOURCE_HSI: HSI selected as RNG clock + */ +#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSource__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_RNGSEL, (uint32_t)(__RNG_CLKSource__)) + +/** @brief macro to get the RNG clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock + * @arg RCC_RNGCLKSOURCE_HSI48_DIV2: HSI48/2 selected as RNG clock + * @arg RCC_RNGCLKSOURCE_HSI: HSI selected as RNG clock + */ +#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_RNGSEL))) + +#if defined(SAES) +/** @brief macro to configure the SAES clock (SAESCLK). + * @param __SAES_CLKSource__: specifies the SAES clock source. + * This parameter can be one of the following values: + * @arg RCC_SAESCLKSOURCE_SHSI: SHSI selected as SAES clock + * @arg RCC_SAESCLKSOURCE_SHSI_DIV2: SHSI/2 selected as SAES clock + */ +#define __HAL_RCC_SAES_CONFIG(__SAES_CLKSource__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAESSEL, (uint32_t)(__SAES_CLKSource__)) + +/** @brief macro to get the SAES clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAESCLKSOURCE_SHSI: SHSI selected as SAES clock + * @arg RCC_SAESCLKSOURCE_SHSI_DIV2: SHSI/2 selected as SAES clock + */ +#define __HAL_RCC_GET_SAES_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAESSEL))) +#endif /* SAES */ + +/** + * @brief Macro to configure the SAI1 clock source. + * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived + * from the PLL2, system PLL or external clock (through a dedicated pin). + * This parameter can be one of the following values: + * @arg @ref RCC_SAI1CLKSOURCE_PLL2 SAI1 clock = PLL2 "P" clock (PLL2CLK) + * @arg @ref RCC_SAI1CLKSOURCE_PLL3 SAI1 clock = PLL3 "P" clock (PLL3CLK) + * @arg @ref RCC_SAI1CLKSOURCE_PLL1 SAI1 clock = PLL1 "P" clock (PLL1CLK) + * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) + * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 + * + * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLL3. + * @retval None + */ +#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__)) + +/** @brief Macro to get the SAI1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_SAI1CLKSOURCE_PLL2 SAI1 clock = PLL2 "P" clock (PLL2CLK) + * @arg @ref RCC_SAI1CLKSOURCE_PLL3 SAI1 clock = PLL3 "P" clock (PLL3CLK) + * @arg @ref RCC_SAI1CLKSOURCE_PLL1 SAI1 clock = PLL "P" clock (PLL1CLK) + * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) + * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 + * @note Despite returned values RCC_SAI1CLKSOURCE_PLL2 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 + * clock source when PLLs are disabled for devices without PLL3. + */ +#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL))) + +#if defined(SAI2) +/** + * @brief Macro to configure the SAI2 clock source. + * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived + * from the PLL3, system PLL or external clock (through a dedicated pin). + * This parameter can be one of the following values: + * @arg @ref RCC_SAI2CLKSOURCE_PLL2 SAI2 clock = PLL2 "P" clock (PLL2CLK) + * @arg @ref RCC_SAI2CLKSOURCE_PLL3 SAI2 clock = PLL3 "P" clock (PLL3CLK) + * @arg @ref RCC_SAI2CLKSOURCE_PLL1 SAI2 clock = PLL1 "P" clock (PLL1CLK) + * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) + * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 + * @retval None + */ +#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__)) + +/** @brief Macro to get the SAI2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_SAI2CLKSOURCE_PLL2 SAI2 clock = PLL2 "P" clock (PLL2CLK) + * @arg @ref RCC_SAI2CLKSOURCE_PLL3 SAI2 clock = PLL3 "P" clock (PLL3CLK) + * @arg @ref RCC_SAI2CLKSOURCE_PLL1 SAI2 clock = PLL1 "P" clock (PLL1CLK) + * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) + * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 + */ +#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL))) +#endif /* SAI2 */ + +/** @brief Macro to configure the MDF1 clock. + * @param __MDF1_CLKSOURCE__ specifies the MDF1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MDF1CLKSOURCE_HCLK HCLK Clock selected as MDF1 clock + * @arg @ref RCC_MDF1CLKSOURCE_PLL1 PLL1 P Clock selected as MDF1 clock + * @arg @ref RCC_MDF1CLKSOURCE_PLL3 PLL3 Q Clock selected as MDF1 clock + * @arg @ref RCC_MDF1CLKSOURCE_PIN External Clock (SAI1_EXTCLK) selected as MDF1 clock + * @arg @ref RCC_MDF1CLKSOURCE_MSIK MSIK Clock selected as MDF1 clock + * @retval None + */ +#define __HAL_RCC_MDF1_CONFIG(__MDF1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_MDF1SEL, (uint32_t)(__MDF1_CLKSOURCE__)) + +/** @brief Macro to get the MDF1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_MDF1CLKSOURCE_HCLK HCLK Clock used as MDF1 clock + * @arg @ref RCC_MDF1CLKSOURCE_PLL1 PLL1 Clock used as MDF1 clock + * @arg @ref RCC_MDF1CLKSOURCE_PLL3 PLL3 Clock used as MDF1 clock + * @arg @ref RCC_MDF1CLKSOURCE_PIN External Clock (SAI1_EXTCLK) used as MDF1 clock + * @arg @ref RCC_MDF1CLKSOURCE_MSIK MSIK Clock used as MDF1 clock + */ +#define __HAL_RCC_GET_MDF1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_MDF1SEL))) + +/** @brief Macro to configure the ADF1 clock. + * @param __ADF1_CLKSOURCE__ specifies the ADF1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_ADF1CLKSOURCE_HCLK HCLK Clock selected as ADF1 clock + * @arg @ref RCC_ADF1CLKSOURCE_PLL1 PLL1 P Clock selected as ADF1 clock + * @arg @ref RCC_ADF1CLKSOURCE_PLL3 PLL3 Q Clock selected as ADF1 clock + * @arg @ref RCC_ADF1CLKSOURCE_PIN External Clock (SAI1_EXTCLK) selected as ADF1 clock + * @arg @ref RCC_ADF1CLKSOURCE_MSIK MSI Clock selected as ADF1 clock + * @retval None + */ +#define __HAL_RCC_ADF1_CONFIG(__ADF1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADF1SEL, (uint32_t)(__ADF1_CLKSOURCE__)) + +/** @brief Macro to get the ADF1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ADF1CLKSOURCE_HCLK HCLK Clock used as ADF1 clock + * @arg @ref RCC_ADF1CLKSOURCE_PLL1 PLL1 P Clock used as ADF1 clock + * @arg @ref RCC_ADF1CLKSOURCE_PLL3 PLL3 Q Clock used as ADF1 clock + * @arg @ref RCC_ADF1CLKSOURCE_PIN External Clock (SAI1_EXTCLK) used as ADF1 clock + * @arg @ref RCC_ADF1CLKSOURCE_MSIK MSI Clock used as ADF1 clock + */ +#define __HAL_RCC_GET_ADF1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_ADF1SEL))) + +/** @brief Macro to configure the DAC1 interface clock. + * @param __DAC1_CLKSOURCE__ specifies the DAC1 digital interface clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_DAC1CLKSOURCE_LSE LSE clock selected as DAC1 clock + * @arg @ref RCC_DAC1CLKSOURCE_LSI LSI clock selected as DAC1 clock + * @retval None + */ +#define __HAL_RCC_DAC1_CONFIG(__DAC1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_DAC1SEL, (uint32_t)(__DAC1_CLKSOURCE__)) + +/** @brief Macro to get the DAC1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_DAC1CLKSOURCE_LSE LSE clock selected as DAC1 clock + * @arg @ref RCC_DAC1CLKSOURCE_LSI LSI clock selected as DAC1 clock + */ +#define __HAL_RCC_GET_DAC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_DAC1SEL))) + +#if defined(LTDC) + +/** @brief Macro to configure the LTDC clock. + * @param __LTDC_CLKSOURCE__ specifies the LTDC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LTDCCLKSOURCE_PLL3 PLL3 divider R clock selected as LTDC kernel clock + * @arg @ref RCC_LTDCCLKSOURCE_PLL2 PLL2 divider R clock selected as LTDC kernel clock + * @retval None + */ +#define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LTDCSEL, (__LTDC_CLKSOURCE__)) + +/** @brief Macro to get the LTDC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LTDCCLKSOURCE_PLL3 PLL3 divider R clock selected as LTDC kernel clock + * @arg @ref RCC_LTDCCLKSOURCE_PLL2 PLL2 divider R clock selected as LTDC kernel clock + */ +#define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LTDCSEL)) + +#endif /* LTDC */ + +#if defined(DSI) + +/** @brief Macro to configure the DSI clock. + * @param __DSI_CLKSOURCE__ specifies the DSI clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock + * @arg @ref RCC_DSICLKSOURCE_PLL3 PLL3 divider P clock selected as DSI clock (low power case) + * @retval None + */ +#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSIHOSTSEL, (__DSI_CLKSOURCE__)) + +/** @brief Macro to get the DSI clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock + * @arg @ref RCC_DSICLKSOURCE_PLL3 PLL3 divider P clock selected as DSI clock (low power case) + */ +#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSIHOSTSEL)) + +#endif /* DSI */ + +#if defined(USB_OTG_HS) + +/** @brief Macro to configure the USB PHY clock. + * @param __USBPHY_CLKSOURCE__ specifies the USB PHY clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USBPHYCLKSOURCE_HSE HSE clock selected as USB PHY clock + * @arg @ref RCC_USBPHYCLKSOURCE_HSE_DIV2 HSE clock div by 2 selected as USB PHY clock + * @arg @ref RCC_USBPHYCLKSOURCE_PLL1 PLL1 P divider clock selected as USB PHY clock + * @arg @ref RCC_USBPHYCLKSOURCE_PLL1_DIV2 PLL1 P divider clock div by 2 selected as USB PHY clock + * @retval None + */ +#define __HAL_RCC_USBPHY_CONFIG(__USBPHY_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBPHYCSEL, (__USBPHY_CLKSOURCE__)) + +/** @brief Macro to get the USB PHY clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USBPHYCLKSOURCE_HSE HSE clock selected as USB PHY clock + * @arg @ref RCC_USBPHYCLKSOURCE_HSE_DIV2 HSE clock div by 2 selected as USB PHY clock + * @arg @ref RCC_USBPHYCLKSOURCE_PLL1 PLL1 P divider clock selected as USB PHY clock + * @arg @ref RCC_USBPHYCLKSOURCE_PLL1_DIV2 PLL1 P divider clock div by 2 selected as USB PHY clock + */ +#define __HAL_RCC_GET_USBPHY_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USBPHYCSEL)) + +#endif /* USB_OTG_HS */ + +#if defined(RCC_CFGR2_PPRE_DPHY) + +/** @brief Macro to configure the DPHY clock. + * @param __PRESCALER__ specifies the DPHY clock source prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_HCLK_DIV1 HCLK divided by 1 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV2 HCLK divided by 2 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV4 HCLK divided by 4 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV8 HCLK divided by 8 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV16 HCLK divided by 16 selected as DPHY clock + * @retval None + */ +#define __HAL_RCC_DPHY_CONFIG(__PRESCALER__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE_DPHY, (__PRESCALER__) << 8UL) + +/** @brief Macro to get the DPHY clock prescaler configuration. + * @retval The clock source prescaler can be one of the following values: + * @arg @ref RCC_HCLK_DIV1 HCLK divided by 1 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV2 HCLK divided by 2 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV4 HCLK divided by 4 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV8 HCLK divided by 8 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV16 HCLK divided by 16 selected as DPHY clock + * @retval None + */ +#define __HAL_RCC_GET_DPHY_CONFIG() (READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE_DPHY) >> 8UL) + +#endif /* defined(RCC_CFGR2_PPRE_DPHY) */ + +#if defined(CRS) + +/** + * @brief Enable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) + +/** + * @brief Disable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) + +/** @brief Check whether the CRS interrupt has occurred or not. + * @param __INTERRUPT__ specifies the CRS interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) + +/** @brief Clear the CRS interrupt pending bits + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt + * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt + * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt + */ +#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) + +#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ + if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC |\ + ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ + } \ + } while(0) + +/** + * @brief Check whether the specified CRS flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @retval The new state of _FLAG_ (TRUE or FALSE). + */ +#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the CRS specified FLAG. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently + * RCC_CRS_FLAG_ERR + * @retval None + */ +#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | \ + RCC_CRS_FLAG_SYNCMISS)) + +#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ + if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \ + ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__FLAG__)); \ + } \ + } while(0) + +/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features + * @{ + */ +/** + * @brief Enable the oscillator clock for frequency error counter. + * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Disable the oscillator clock for frequency error counter. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Enable the automatic hardware adjustment of TRIM bits. + * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Enable or disable the automatic hardware adjustment of TRIM bits. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency + * of the synchronization source after prescaling. It is then decreased by one in order to + * reach the expected synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval None + */ +#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk); +void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks); +void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks); +void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks); +/** + * @} + */ + +/** @addtogroup RCCEx_Exported_Functions_Group2 + * @{ + */ + +HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(const RCC_PLL2InitTypeDef *PLL2Init); +HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); +HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(const RCC_PLL3InitTypeDef *PLL3Init); +HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void); +HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLFastStartup(void); +HAL_StatusTypeDef HAL_RCCEx_DisableMSIPLLFastStartup(void); +HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLModeSelection(uint32_t MSIPLLModeSelection); +void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); +void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); +void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange); +void HAL_RCCEx_StandbyMSIKRangeConfig(uint32_t MSIKRange); +void HAL_RCCEx_EnableLSECSS(void); +void HAL_RCCEx_DisableLSECSS(void); +void HAL_RCCEx_EnableLSECSS_IT(void); +void HAL_RCCEx_EnableMSIPLLUNLCK_IT(void); +void HAL_RCCEx_LSECSS_IRQHandler(void); +void HAL_RCCEx_LSECSS_Callback(void); +void HAL_RCCEx_MSIPLLUNLCK_IRQHandler(void); +void HAL_RCCEx_MSIPLLUNLCK_Callback(void); +void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); +void HAL_RCCEx_DisableLSCO(void); +void HAL_RCCEx_EnableMSIPLLMode(void); +void HAL_RCCEx_DisableMSIPLLMode(void); +/** + * @} + */ + +#if defined(CRS) + +/** @addtogroup RCCEx_Exported_Functions_Group3 + * @{ + */ +void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *const pInit); +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); +void HAL_RCCEx_CRS_IRQHandler(void); +void HAL_RCCEx_CRS_SyncOkCallback(void); +void HAL_RCCEx_CRS_SyncWarnCallback(void); +void HAL_RCCEx_CRS_ExpectedSyncCallback(void); +void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_RCC_EX_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng.h new file mode 100644 index 000000000..bb8836ad2 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng.h @@ -0,0 +1,390 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_rng.h + * @author MCD Application Team + * @brief Header file of RNG HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_RNG_H +#define STM32U5xx_HAL_RNG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +#if defined (RNG) + +/** @defgroup RNG RNG + * @brief RNG HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RNG_Exported_Types RNG Exported Types + * @{ + */ + +/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition + * @{ + */ +typedef struct +{ + uint32_t ClockErrorDetection; /*!< CED Clock error detection */ +} RNG_InitTypeDef; + +/** + * @} + */ + +/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition + * @{ + */ +typedef enum +{ + HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */ + HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */ + HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */ + HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */ + HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */ + +} HAL_RNG_StateTypeDef; + +/** + * @} + */ + +/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition + * @{ + */ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +typedef struct __RNG_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ +{ + RNG_TypeDef *Instance; /*!< Register base address */ + + RNG_InitTypeDef Init; /*!< RNG configuration parameters */ + + HAL_LockTypeDef Lock; /*!< RNG locking object */ + + __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ + + __IO uint32_t ErrorCode; /*!< RNG Error code */ + + uint32_t RandomNumber; /*!< Last Generated RNG Data */ + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< RNG Data Ready Callback */ + void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Error Callback */ + + void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp Init callback */ + void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp DeInit callback */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + +} RNG_HandleTypeDef; + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +/** + * @brief HAL RNG Callback ID enumeration definition + */ +typedef enum +{ + HAL_RNG_ERROR_CB_ID = 0x00U, /*!< RNG Error Callback ID */ + + HAL_RNG_MSPINIT_CB_ID = 0x01U, /*!< RNG MspInit callback ID */ + HAL_RNG_MSPDEINIT_CB_ID = 0x02U /*!< RNG MspDeInit callback ID */ + +} HAL_RNG_CallbackIDTypeDef; + +/** + * @brief HAL RNG Callback pointer definition + */ +typedef void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng); /*!< pointer to a common RNG callback function */ +typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< pointer to an RNG Data Ready specific callback function */ + +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RNG_Exported_Constants RNG Exported Constants + * @{ + */ + +/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition + * @{ + */ +#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */ +#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */ +#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */ +/** + * @} + */ + +/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition + * @{ + */ +#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */ +#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */ +#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */ +/** + * @} + */ + +/** @defgroup RNG_Exported_Constants_Group3 RNG Clock Error Detection + * @{ + */ +#define RNG_CED_ENABLE 0x00000000U /*!< Clock error detection Enabled */ +#define RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection Disabled */ +/** + * @} + */ + +/** @defgroup RNG_Error_Definition RNG Error Definition + * @{ + */ +#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ +#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */ +#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ +#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ +#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#define HAL_RNG_ERROR_RECOVERSEED 0x00000020U /*!< Recover Seed error */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RNG_Exported_Macros RNG Exported Macros + * @{ + */ + +/** @brief Reset RNG handle state + * @param __HANDLE__ RNG Handle + * @retval None + */ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_RNG_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET) +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + +/** + * @brief Enables the RNG peripheral. + * @param __HANDLE__ RNG Handle + * @retval None + */ +#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN) + +/** + * @brief Disables the RNG peripheral. + * @param __HANDLE__ RNG Handle + * @retval None + */ +#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN) + +/** + * @brief Check the selected RNG flag status. + * @param __HANDLE__ RNG Handle + * @param __FLAG__ RNG flag + * This parameter can be one of the following values: + * @arg RNG_FLAG_DRDY: Data ready + * @arg RNG_FLAG_CECS: Clock error current status + * @arg RNG_FLAG_SECS: Seed error current status + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clears the selected RNG flag status. + * @param __HANDLE__ RNG handle + * @param __FLAG__ RNG flag to clear + * @note WARNING: This is a dummy macro for HAL code alignment, + * flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only. + * @retval None + */ +#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */ + +/** + * @brief Enables the RNG interrupts. + * @param __HANDLE__ RNG Handle + * @retval None + */ +#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE) + +/** + * @brief Disables the RNG interrupts. + * @param __HANDLE__ RNG Handle + * @retval None + */ +#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE) + +/** + * @brief Checks whether the specified RNG interrupt has occurred or not. + * @param __HANDLE__ RNG Handle + * @param __INTERRUPT__ specifies the RNG interrupt status flag to check. + * This parameter can be one of the following values: + * @arg RNG_IT_DRDY: Data ready interrupt + * @arg RNG_IT_CEI: Clock error interrupt + * @arg RNG_IT_SEI: Seed error interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Clear the RNG interrupt status flags. + * @param __HANDLE__ RNG Handle + * @param __INTERRUPT__ specifies the RNG interrupt status flag to clear. + * This parameter can be one of the following values: + * @arg RNG_IT_CEI: Clock error interrupt + * @arg RNG_IT_SEI: Seed error interrupt + * @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY. + * @retval None + */ +#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__)) + +/** + * @} + */ + +/* Include RNG HAL Extended module */ +#include "stm32u5xx_hal_rng_ex.h" +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RNG_Exported_Functions RNG Exported Functions + * @{ + */ + +/** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions + * @{ + */ +HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng); +HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng); +void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng); +void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, + pRNG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit); +HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng); + +void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng); +void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng); +void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit); + +/** + * @} + */ + +/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions + * @{ + */ +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RNG_Private_Macros RNG Private Macros + * @{ + */ +#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \ + ((IT) == RNG_IT_SEI)) + +#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \ + ((FLAG) == RNG_FLAG_CECS) || \ + ((FLAG) == RNG_FLAG_SECS)) + +/** + * @brief Verify the RNG Clock Error Detection mode. + * @param __MODE__ RNG Clock Error Detection mode + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_RNG_CED(__MODE__) (((__MODE__) == RNG_CED_ENABLE) || \ + ((__MODE__) == RNG_CED_DISABLE)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup RNG_Private_Functions RNG Private functions + * @{ + */ +HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng); +/** + * @} + */ +/** + * @} + */ + +#endif /* RNG */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32U5xx_HAL_RNG_H */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h new file mode 100644 index 000000000..47d1f75be --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h @@ -0,0 +1,265 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_rng_ex.h + * @author MCD Application Team + * @brief Header file of RNG HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_RNG_EX_H +#define STM32U5xx_HAL_RNG_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +#if defined(RNG) +#if defined(RNG_CR_CONDRST) + +/** @defgroup RNGEx RNGEx + * @brief RNG Extension HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RNGEx_Exported_Types RNGEx Exported Types + * @brief RNGEx Exported types + * @{ + */ + +/** + * @brief RNGEx Configuration Structure definition + */ + +typedef struct +{ + uint32_t Config1; /*!< Config1 must be a value between 0 and 0x3F */ + uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ + uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ + uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can + be a value of @ref RNGEx_Clock_Divider_Factor */ + uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a + value of @ref RNGEx_NIST_Compliance */ + uint32_t AutoReset; /*!< automatic reset When a noise source error occurs + value of @ref RNGEx_Auto_Reset */ + uint32_t HealthTest; /*!< RNG health test control must be a value + between 0x0FFCABFF and 0x00005200 */ + uint32_t NoiseSource; /*!< RNG noise source control(Oscillator Enable signals) + must be a value between 0x0 and 0x0003FFFF */ +} RNG_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RNGEx_Exported_Constants RNGEx Exported Constants + * @{ + */ + +/** @defgroup RNGEx_Clock_Divider_Factor Value used to configure an internal + * programmable divider acting on the incoming RNG clock + * @{ + */ +#define RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */ +#define RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0) +/*!< 2 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1) +/*!< 4 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) +/*!< 8 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2) +/*!< 16 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) +/*!< 32 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) +/*!< 64 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) +/*!< 128 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3) +/*!< 256 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0) +/*!< 512 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1) +/*!< 1024 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) +/*!< 2048 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2) +/*!< 4096 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) +/*!< 8192 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) +/*!< 16384 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) +/*!< 32768 RNG clock cycles per internal RNG clock */ +/** + * @} + */ + +/** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration + * @{ + */ +#define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ +#define RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */ + +/** + * @} + */ +/** @defgroup RNGEx_Auto_Reset Auto Reset configuration + * @{ + */ +#define RNG_ARDIS_ENABLE (0x00000000UL) /*!< automatic reset after seed error*/ +#define RNG_ARDIS_DISABLE (RNG_CR_ARDIS) /*!< Disable automatic reset after seed error */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup RNGEx_Private_Types RNGEx Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RNGEx_Private_Variables RNGEx Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RNGEx_Private_Constants RNGEx Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RNGEx_Private_Macros RNGEx Private Macros + * @{ + */ + +#define IS_RNG_CLOCK_DIVIDER(__CLOCK_DIV__) (((__CLOCK_DIV__) == RNG_CLKDIV_BY_1) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_2) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_4) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_8) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_16) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_32) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_64) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_128) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_256) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_512) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_1024) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_2048) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_4096) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_8192) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_16384) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_32768)) + + +#define IS_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__) (((__NIST_COMPLIANCE__) == RNG_NIST_COMPLIANT) || \ + ((__NIST_COMPLIANCE__) == RNG_CUSTOM_NIST)) + +#define IS_RNG_CONFIG1(__CONFIG1__) ((__CONFIG1__) <= 0x3FUL) + +#define IS_RNG_CONFIG2(__CONFIG2__) ((__CONFIG2__) <= 0x07UL) + +#define IS_RNG_CONFIG3(__CONFIG3__) ((__CONFIG3__) <= 0xFUL) +#define IS_RNG_ARDIS(__ARDIS__) (((__ARDIS__) == RNG_ARDIS_ENABLE) || \ + ((__ARDIS__) == RNG_ARDIS_DISABLE)) + + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup RNGEx_Private_Functions RNGEx Private Functions + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RNGEx_Exported_Functions + * @{ + */ + +/** @addtogroup RNGEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf); +HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf); +HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); + +/** + * @} + */ + +/** @addtogroup RNGEx_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RNG_CR_CONDRST */ +#endif /* RNG */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32U5xx_HAL_RNG_EX_H */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi.h new file mode 100644 index 000000000..24fa33d53 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi.h @@ -0,0 +1,1135 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_spi.h + * @author MCD Application Team + * @brief Header file of SPI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_SPI_H +#define STM32U5xx_HAL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_Mode */ + + uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. + This parameter can be a value of @ref SPI_Direction */ + + uint32_t DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_Data_Size */ + + uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of + @ref SPI_Slave_Select_Management */ + + uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_Transmission */ + + uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. + This parameter can be a value of @ref SPI_TI_Mode */ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_CRC_Calculation */ + + uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be an odd number between + Min_Data = 0 and Max_Data = 65535 */ + + uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. + This parameter can be a value of @ref SPI_CRC_length */ + + uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . + This parameter can be a value of @ref SPI_NSSP_Mode + This mode is activated by the SSOM bit in the SPIx_CR2 register + and it takes effect only if the SPI interface is configured + as Motorola SPI master (FRF=0). */ + + uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal + (present on SS pin) is considered as active one. + This parameter can be a value of @ref SPI_NSS_Polarity */ + + uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref SPI_Fifo_Threshold */ + + uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for + the CRC calculation. This parameter can be a value of + @ref SPI_CRC_Calculation_Initialization_Pattern */ + + uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for + the CRC calculation. This parameter can be a value of + @ref SPI_CRC_Calculation_Initialization_Pattern */ + + uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle + periods, inserted additionally between active edge of SS + and first data transaction start in master mode. + This parameter can be a value of @ref SPI_Master_SS_Idleness */ + + uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) + inserted between two consecutive data frames in master mode. + This parameter can be a value of + @ref SPI_Master_InterData_Idleness */ + + uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode + and automatic management in order to avoid overrun condition. + This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/ + + uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state + This parameter can be a value of @ref SPI_Master_Keep_IO_State */ + + uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions + This parameter can be a value of @ref SPI_IO_Swap */ + + uint32_t ReadyMasterManagement; /*!< Specifies if RDY Signal is managed internally or not. + This parameter can be a value of @ref SPI_RDY_Master_Management */ + + uint32_t ReadyPolarity; /*!< Specifies which level of RDY Signal input (present on RDY pin) + is considered as active one. + This parameter can be a value of @ref SPI_RDY_Polarity */ +} SPI_InitTypeDef; + +/** + * @brief HAL SPI State structure definition + */ +typedef enum +{ + HAL_SPI_STATE_RESET = 0x00UL, /*!< Peripheral not Initialized */ + HAL_SPI_STATE_READY = 0x01UL, /*!< Peripheral Initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02UL, /*!< an internal process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x05UL, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x06UL, /*!< SPI error state */ + HAL_SPI_STATE_ABORT = 0x07UL /*!< SPI abort is ongoing */ +} HAL_SPI_StateTypeDef; + + +/** + * @brief SPI handle Structure definition + */ +typedef struct __SPI_HandleTypeDef +{ + SPI_TypeDef *Instance; /*!< SPI registers base address */ + + SPI_InitTypeDef Init; /*!< SPI communication parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< SPI Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< SPI Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ + + uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ + + void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ + + void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ + + DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ + + __IO uint32_t ErrorCode; /*!< SPI Error code */ + + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ + void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ + void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ + void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ + void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ + void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ + void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ + void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ + void (* SuspendCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Suspend callback */ + void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ + void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} SPI_HandleTypeDef; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) +/** + * @brief HAL SPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_SPI_TX_COMPLETE_CB_ID = 0x00UL, /*!< SPI Tx Completed callback ID */ + HAL_SPI_RX_COMPLETE_CB_ID = 0x01UL, /*!< SPI Rx Completed callback ID */ + HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02UL, /*!< SPI TxRx Completed callback ID */ + HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< SPI Tx Half Completed callback ID */ + HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< SPI Rx Half Completed callback ID */ + HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< SPI TxRx Half Completed callback ID */ + HAL_SPI_ERROR_CB_ID = 0x06UL, /*!< SPI Error callback ID */ + HAL_SPI_ABORT_CB_ID = 0x07UL, /*!< SPI Abort callback ID */ + HAL_SPI_SUSPEND_CB_ID = 0x08UL, /*!< SPI Suspend callback ID */ + HAL_SPI_MSPINIT_CB_ID = 0x09UL, /*!< SPI Msp Init callback ID */ + HAL_SPI_MSPDEINIT_CB_ID = 0x0AUL /*!< SPI Msp DeInit callback ID */ + +} HAL_SPI_CallbackIDTypeDef; + +/** + * @brief HAL SPI Callback pointer definition + */ +typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_FIFO_Type SPI FIFO Type + * @{ + */ +#define SPI_LOWEND_FIFO_SIZE 8UL +#define SPI_HIGHEND_FIFO_SIZE 16UL +/** + * @} + */ + +/** @defgroup SPI_Error_Code SPI Error Codes + * @{ + */ +#define HAL_SPI_ERROR_NONE (0x00000000UL) /*!< No error */ +#define HAL_SPI_ERROR_MODF (0x00000001UL) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC (0x00000002UL) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR (0x00000004UL) /*!< OVR error */ +#define HAL_SPI_ERROR_FRE (0x00000008UL) /*!< FRE error */ +#define HAL_SPI_ERROR_DMA (0x00000010UL) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG (0x00000020UL) /*!< Error on RXP/TXP/DXP/FTLVL/FRLVL Flag */ +#define HAL_SPI_ERROR_ABORT (0x00000040UL) /*!< Error during SPI Abort procedure */ +#define HAL_SPI_ERROR_UDR (0x00000080UL) /*!< Underrun error */ +#define HAL_SPI_ERROR_TIMEOUT (0x00000100UL) /*!< Timeout error */ +#define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknown error */ +#define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL) /*!< Requested operation not supported */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) +#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00001000UL) /*!< Invalid Callback error */ +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Mode SPI Mode + * @{ + */ +#define SPI_MODE_SLAVE (0x00000000UL) +#define SPI_MODE_MASTER SPI_CFG2_MASTER +/** + * @} + */ + +/** @defgroup SPI_Direction SPI Direction Mode + * @{ + */ +#define SPI_DIRECTION_2LINES (0x00000000UL) +#define SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0 +#define SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1 +#define SPI_DIRECTION_1LINE SPI_CFG2_COMM +/** + * @} + */ + +/** @defgroup SPI_Data_Size SPI Data Size + * @{ + */ +#define SPI_DATASIZE_4BIT (0x00000003UL) +#define SPI_DATASIZE_5BIT (0x00000004UL) +#define SPI_DATASIZE_6BIT (0x00000005UL) +#define SPI_DATASIZE_7BIT (0x00000006UL) +#define SPI_DATASIZE_8BIT (0x00000007UL) +#define SPI_DATASIZE_9BIT (0x00000008UL) +#define SPI_DATASIZE_10BIT (0x00000009UL) +#define SPI_DATASIZE_11BIT (0x0000000AUL) +#define SPI_DATASIZE_12BIT (0x0000000BUL) +#define SPI_DATASIZE_13BIT (0x0000000CUL) +#define SPI_DATASIZE_14BIT (0x0000000DUL) +#define SPI_DATASIZE_15BIT (0x0000000EUL) +#define SPI_DATASIZE_16BIT (0x0000000FUL) +#define SPI_DATASIZE_17BIT (0x00000010UL) +#define SPI_DATASIZE_18BIT (0x00000011UL) +#define SPI_DATASIZE_19BIT (0x00000012UL) +#define SPI_DATASIZE_20BIT (0x00000013UL) +#define SPI_DATASIZE_21BIT (0x00000014UL) +#define SPI_DATASIZE_22BIT (0x00000015UL) +#define SPI_DATASIZE_23BIT (0x00000016UL) +#define SPI_DATASIZE_24BIT (0x00000017UL) +#define SPI_DATASIZE_25BIT (0x00000018UL) +#define SPI_DATASIZE_26BIT (0x00000019UL) +#define SPI_DATASIZE_27BIT (0x0000001AUL) +#define SPI_DATASIZE_28BIT (0x0000001BUL) +#define SPI_DATASIZE_29BIT (0x0000001CUL) +#define SPI_DATASIZE_30BIT (0x0000001DUL) +#define SPI_DATASIZE_31BIT (0x0000001EUL) +#define SPI_DATASIZE_32BIT (0x0000001FUL) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity SPI Clock Polarity + * @{ + */ +#define SPI_POLARITY_LOW (0x00000000UL) +#define SPI_POLARITY_HIGH SPI_CFG2_CPOL +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase SPI Clock Phase + * @{ + */ +#define SPI_PHASE_1EDGE (0x00000000UL) +#define SPI_PHASE_2EDGE SPI_CFG2_CPHA +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_Management SPI Slave Select Management + * @{ + */ +#define SPI_NSS_SOFT SPI_CFG2_SSM +#define SPI_NSS_HARD_INPUT (0x00000000UL) +#define SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE +/** + * @} + */ + +/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode + * @{ + */ +#define SPI_NSS_PULSE_DISABLE (0x00000000UL) +#define SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler + * @{ + */ +#define SPI_BAUDRATEPRESCALER_BYPASS (0x80000000UL) +#define SPI_BAUDRATEPRESCALER_2 (0x00000000UL) +#define SPI_BAUDRATEPRESCALER_4 (0x10000000UL) +#define SPI_BAUDRATEPRESCALER_8 (0x20000000UL) +#define SPI_BAUDRATEPRESCALER_16 (0x30000000UL) +#define SPI_BAUDRATEPRESCALER_32 (0x40000000UL) +#define SPI_BAUDRATEPRESCALER_64 (0x50000000UL) +#define SPI_BAUDRATEPRESCALER_128 (0x60000000UL) +#define SPI_BAUDRATEPRESCALER_256 (0x70000000UL) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission + * @{ + */ +#define SPI_FIRSTBIT_MSB (0x00000000UL) +#define SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST +/** + * @} + */ + +/** @defgroup SPI_TI_Mode SPI TI Mode + * @{ + */ +#define SPI_TIMODE_DISABLE (0x00000000UL) +#define SPI_TIMODE_ENABLE SPI_CFG2_SP_0 +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation SPI CRC Calculation + * @{ + */ +#define SPI_CRCCALCULATION_DISABLE (0x00000000UL) +#define SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN +/** + * @} + */ + +/** @defgroup SPI_CRC_length SPI CRC Length + * @{ + */ +#define SPI_CRC_LENGTH_DATASIZE (0x00000000UL) +#define SPI_CRC_LENGTH_4BIT (0x00030000UL) +#define SPI_CRC_LENGTH_5BIT (0x00040000UL) +#define SPI_CRC_LENGTH_6BIT (0x00050000UL) +#define SPI_CRC_LENGTH_7BIT (0x00060000UL) +#define SPI_CRC_LENGTH_8BIT (0x00070000UL) +#define SPI_CRC_LENGTH_9BIT (0x00080000UL) +#define SPI_CRC_LENGTH_10BIT (0x00090000UL) +#define SPI_CRC_LENGTH_11BIT (0x000A0000UL) +#define SPI_CRC_LENGTH_12BIT (0x000B0000UL) +#define SPI_CRC_LENGTH_13BIT (0x000C0000UL) +#define SPI_CRC_LENGTH_14BIT (0x000D0000UL) +#define SPI_CRC_LENGTH_15BIT (0x000E0000UL) +#define SPI_CRC_LENGTH_16BIT (0x000F0000UL) +#define SPI_CRC_LENGTH_17BIT (0x00100000UL) +#define SPI_CRC_LENGTH_18BIT (0x00110000UL) +#define SPI_CRC_LENGTH_19BIT (0x00120000UL) +#define SPI_CRC_LENGTH_20BIT (0x00130000UL) +#define SPI_CRC_LENGTH_21BIT (0x00140000UL) +#define SPI_CRC_LENGTH_22BIT (0x00150000UL) +#define SPI_CRC_LENGTH_23BIT (0x00160000UL) +#define SPI_CRC_LENGTH_24BIT (0x00170000UL) +#define SPI_CRC_LENGTH_25BIT (0x00180000UL) +#define SPI_CRC_LENGTH_26BIT (0x00190000UL) +#define SPI_CRC_LENGTH_27BIT (0x001A0000UL) +#define SPI_CRC_LENGTH_28BIT (0x001B0000UL) +#define SPI_CRC_LENGTH_29BIT (0x001C0000UL) +#define SPI_CRC_LENGTH_30BIT (0x001D0000UL) +#define SPI_CRC_LENGTH_31BIT (0x001E0000UL) +#define SPI_CRC_LENGTH_32BIT (0x001F0000UL) +/** + * @} + */ + +/** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold + * @{ + */ +#define SPI_FIFO_THRESHOLD_01DATA (0x00000000UL) +#define SPI_FIFO_THRESHOLD_02DATA (0x00000020UL) +#define SPI_FIFO_THRESHOLD_03DATA (0x00000040UL) +#define SPI_FIFO_THRESHOLD_04DATA (0x00000060UL) +#define SPI_FIFO_THRESHOLD_05DATA (0x00000080UL) +#define SPI_FIFO_THRESHOLD_06DATA (0x000000A0UL) +#define SPI_FIFO_THRESHOLD_07DATA (0x000000C0UL) +#define SPI_FIFO_THRESHOLD_08DATA (0x000000E0UL) +#define SPI_FIFO_THRESHOLD_09DATA (0x00000100UL) +#define SPI_FIFO_THRESHOLD_10DATA (0x00000120UL) +#define SPI_FIFO_THRESHOLD_11DATA (0x00000140UL) +#define SPI_FIFO_THRESHOLD_12DATA (0x00000160UL) +#define SPI_FIFO_THRESHOLD_13DATA (0x00000180UL) +#define SPI_FIFO_THRESHOLD_14DATA (0x000001A0UL) +#define SPI_FIFO_THRESHOLD_15DATA (0x000001C0UL) +#define SPI_FIFO_THRESHOLD_16DATA (0x000001E0UL) +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern + * @{ + */ +#define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000UL) +#define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001UL) +/** + * @} + */ + +/** @defgroup SPI_NSS_Polarity SPI NSS Polarity + * @{ + */ +#define SPI_NSS_POLARITY_LOW (0x00000000UL) +#define SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP +/** + * @} + */ + +/** @defgroup SPI_Master_Keep_IO_State Keep IO State + * @{ + */ +#define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000UL) +#define SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR +/** + * @} + */ + +/** @defgroup SPI_IO_Swap Control SPI IO Swap + * @{ + */ +#define SPI_IO_SWAP_DISABLE (0x00000000UL) +#define SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP +/** + * @} + */ + +/** @defgroup SPI_Master_SS_Idleness SPI Master SS Idleness + * @{ + */ +#define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000UL) +#define SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001UL) +#define SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002UL) +#define SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003UL) +#define SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004UL) +#define SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005UL) +#define SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006UL) +#define SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007UL) +#define SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008UL) +#define SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009UL) +#define SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AUL) +#define SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BUL) +#define SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CUL) +#define SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DUL) +#define SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EUL) +#define SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FUL) +/** + * @} + */ + +/** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Idleness + * @{ + */ +#define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000UL) +#define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010UL) +#define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020UL) +#define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030UL) +#define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040UL) +#define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050UL) +#define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060UL) +#define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070UL) +#define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080UL) +#define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090UL) +#define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0UL) +#define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0UL) +#define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0UL) +#define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0UL) +#define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0UL) +#define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0UL) +/** + * @} + */ + +/** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend + * @{ + */ +#define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000UL) +#define SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX +/** + * @} + */ + +/** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior + * @{ + */ +#define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL) +#define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG +/** + * @} + */ + +/** @defgroup SPI_RDY_Master_Management SPI RDY Signal Input Master Management + * @{ + */ +#define SPI_RDY_MASTER_MANAGEMENT_INTERNALLY (0x00000000UL) +#define SPI_RDY_MASTER_MANAGEMENT_EXTERNALLY SPI_CFG2_RDIMM +/** + * @} + */ + +/** @defgroup SPI_RDY_Polarity SPI RDY Signal Input/Output Polarity + * @{ + */ +#define SPI_RDY_POLARITY_HIGH (0x00000000UL) +#define SPI_RDY_POLARITY_LOW SPI_CFG2_RDIOP +/** + * @} + */ + +/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition + * @{ + */ +#define SPI_IT_RXP SPI_IER_RXPIE +#define SPI_IT_TXP SPI_IER_TXPIE +#define SPI_IT_DXP SPI_IER_DXPIE +#define SPI_IT_EOT SPI_IER_EOTIE +#define SPI_IT_TXTF SPI_IER_TXTFIE +#define SPI_IT_UDR SPI_IER_UDRIE +#define SPI_IT_OVR SPI_IER_OVRIE +#define SPI_IT_CRCERR SPI_IER_CRCEIE +#define SPI_IT_FRE SPI_IER_TIFREIE +#define SPI_IT_MODF SPI_IER_MODFIE +#define SPI_IT_ERR (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR) +/** + * @} + */ + +/** @defgroup SPI_Flags_definition SPI Flags Definition + * @{ + */ +#define SPI_FLAG_RXP SPI_SR_RXP /* SPI status flag : Rx-Packet available flag */ +#define SPI_FLAG_TXP SPI_SR_TXP /* SPI status flag : Tx-Packet space available flag */ +#define SPI_FLAG_DXP SPI_SR_DXP /* SPI status flag : Duplex Packet flag */ +#define SPI_FLAG_EOT SPI_SR_EOT /* SPI status flag : End of transfer flag */ +#define SPI_FLAG_TXTF SPI_SR_TXTF /* SPI status flag : Transmission Transfer Filled flag */ +#define SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag : Underrun flag */ +#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag : Overrun flag */ +#define SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag : CRC error flag */ +#define SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag : TI mode frame format error flag */ +#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag : Mode fault flag */ +#define SPI_FLAG_SUSP SPI_SR_SUSP /* SPI status flag : Transfer suspend complete flag */ +#define SPI_FLAG_TXC SPI_SR_TXC /* SPI status flag : TxFIFO transmission complete flag */ +#define SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI status flag : Fifo reception level flag */ +#define SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI status flag : RxFIFO word not empty flag */ +/** + * @} + */ + +/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level + * @{ + */ +#define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */ +#define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) +#define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) +#define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup SPI_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @brief Reset SPI handle state. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @retval None + */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + +/** @brief Enable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg SPI_IT_RXP : Rx-Packet available interrupt + * @arg SPI_IT_TXP : Tx-Packet space available interrupt + * @arg SPI_IT_DXP : Duplex Packet interrupt + * @arg SPI_IT_EOT : End of transfer interrupt + * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt + * @arg SPI_IT_UDR : Underrun interrupt + * @arg SPI_IT_OVR : Overrun interrupt + * @arg SPI_IT_CRCERR : CRC error interrupt + * @arg SPI_IT_FRE : TI mode frame format error interrupt + * @arg SPI_IT_MODF : Mode fault interrupt + * @arg SPI_IT_ERR : Error interrupt + * @retval None + */ +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** @brief Disable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg SPI_IT_RXP : Rx-Packet available interrupt + * @arg SPI_IT_TXP : Tx-Packet space available interrupt + * @arg SPI_IT_DXP : Duplex Packet interrupt + * @arg SPI_IT_EOT : End of transfer interrupt + * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt + * @arg SPI_IT_UDR : Underrun interrupt + * @arg SPI_IT_OVR : Overrun interrupt + * @arg SPI_IT_CRCERR : CRC error interrupt + * @arg SPI_IT_FRE : TI mode frame format error interrupt + * @arg SPI_IT_MODF : Mode fault interrupt + * @arg SPI_IT_ERR : Error interrupt + * @retval None + */ +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified SPI interrupt source is enabled or not. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_RXP : Rx-Packet available interrupt + * @arg SPI_IT_TXP : Tx-Packet space available interrupt + * @arg SPI_IT_DXP : Duplex Packet interrupt + * @arg SPI_IT_EOT : End of transfer interrupt + * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt + * @arg SPI_IT_UDR : Underrun interrupt + * @arg SPI_IT_OVR : Overrun interrupt + * @arg SPI_IT_CRCERR : CRC error interrupt + * @arg SPI_IT_FRE : TI mode frame format error interrupt + * @arg SPI_IT_MODF : Mode fault interrupt + * @arg SPI_IT_ERR : Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXP : Rx-Packet available flag + * @arg SPI_FLAG_TXP : Tx-Packet space available flag + * @arg SPI_FLAG_DXP : Duplex Packet flag + * @arg SPI_FLAG_EOT : End of transfer flag + * @arg SPI_FLAG_TXTF : Transmission Transfer Filled flag + * @arg SPI_FLAG_UDR : Underrun flag + * @arg SPI_FLAG_OVR : Overrun flag + * @arg SPI_FLAG_CRCERR : CRC error flag + * @arg SPI_FLAG_FRE : TI mode frame format error flag + * @arg SPI_FLAG_MODF : Mode fault flag + * @arg SPI_FLAG_SUSP : Transfer suspend complete flag + * @arg SPI_FLAG_TXC : TxFIFO transmission complete flag + * @arg SPI_FLAG_FRLVL : Fifo reception level flag + * @arg SPI_FLAG_RXWNE : RxFIFO word not empty flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the SPI CRCERR pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC) + +/** @brief Clear the SPI MODF pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC)); + +/** @brief Clear the SPI OVR pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC) + +/** @brief Clear the SPI FRE pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC) + +/** @brief Clear the SPI UDR pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC) + +/** @brief Clear the SPI EOT pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC) + +/** @brief Clear the SPI UDR pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC) + +/** @brief Clear the SPI SUSP pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC) + +/** @brief Enable the SPI peripheral. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE) + +/** @brief Disable the SPI peripheral. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE) +/** + * @} + */ + + +/* Include SPI HAL Extension module */ +#include "stm32u5xx_hal_spi_ex.h" + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group2 IO operation functions + * @{ + */ +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); + +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); + + +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); + +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); + +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @{ + */ + +/* Peripheral State and Error functions ***************************************/ +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ + +/** @brief Set the SPI transmit-only mode in 1Line configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) + +/** @brief Set the SPI receive-only mode in 1Line configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) + +/** @brief Set the SPI transmit-only mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES_TX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_0) + +/** @brief Set the SPI receive-only mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES_RX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_1) + +/** @brief Set the SPI Transmit-Receive mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL) + +#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ + ((MODE) == SPI_MODE_MASTER)) + +#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ + ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((MODE) == SPI_DIRECTION_1LINE) || \ + ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) + +#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) + +#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ + ((MODE) == SPI_DIRECTION_1LINE) || \ + ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) + +#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ + ((MODE) == SPI_DIRECTION_1LINE) || \ + ((MODE) == SPI_DIRECTION_2LINES_RXONLY)) + +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \ + ((DATASIZE) == SPI_DATASIZE_31BIT) || \ + ((DATASIZE) == SPI_DATASIZE_30BIT) || \ + ((DATASIZE) == SPI_DATASIZE_29BIT) || \ + ((DATASIZE) == SPI_DATASIZE_28BIT) || \ + ((DATASIZE) == SPI_DATASIZE_27BIT) || \ + ((DATASIZE) == SPI_DATASIZE_26BIT) || \ + ((DATASIZE) == SPI_DATASIZE_25BIT) || \ + ((DATASIZE) == SPI_DATASIZE_24BIT) || \ + ((DATASIZE) == SPI_DATASIZE_23BIT) || \ + ((DATASIZE) == SPI_DATASIZE_22BIT) || \ + ((DATASIZE) == SPI_DATASIZE_21BIT) || \ + ((DATASIZE) == SPI_DATASIZE_20BIT) || \ + ((DATASIZE) == SPI_DATASIZE_22BIT) || \ + ((DATASIZE) == SPI_DATASIZE_19BIT) || \ + ((DATASIZE) == SPI_DATASIZE_18BIT) || \ + ((DATASIZE) == SPI_DATASIZE_17BIT) || \ + ((DATASIZE) == SPI_DATASIZE_16BIT) || \ + ((DATASIZE) == SPI_DATASIZE_15BIT) || \ + ((DATASIZE) == SPI_DATASIZE_14BIT) || \ + ((DATASIZE) == SPI_DATASIZE_13BIT) || \ + ((DATASIZE) == SPI_DATASIZE_12BIT) || \ + ((DATASIZE) == SPI_DATASIZE_11BIT) || \ + ((DATASIZE) == SPI_DATASIZE_10BIT) || \ + ((DATASIZE) == SPI_DATASIZE_9BIT) || \ + ((DATASIZE) == SPI_DATASIZE_8BIT) || \ + ((DATASIZE) == SPI_DATASIZE_7BIT) || \ + ((DATASIZE) == SPI_DATASIZE_6BIT) || \ + ((DATASIZE) == SPI_DATASIZE_5BIT) || \ + ((DATASIZE) == SPI_DATASIZE_4BIT)) + +/** + * @brief DataSize for limited instance + */ +#define IS_SPI_LIMITED_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ + ((DATASIZE) == SPI_DATASIZE_8BIT)) + +#define IS_SPI_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA)) + +/** + * @brief FifoThreshold for limited instance + */ +#define IS_SPI_LIMITED_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA)) + +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ + ((CPOL) == SPI_POLARITY_HIGH)) + +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ + ((CPHA) == SPI_PHASE_2EDGE)) + +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ + ((NSS) == SPI_NSS_HARD_INPUT) || \ + ((NSS) == SPI_NSS_HARD_OUTPUT)) + +#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ + ((NSSP) == SPI_NSS_PULSE_DISABLE)) + +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_BYPASS) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) + +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ + ((BIT) == SPI_FIRSTBIT_LSB)) + +#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ + ((MODE) == SPI_TIMODE_ENABLE)) + +#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ + ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) + +#define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \ + ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)) + +#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || \ + ((LENGTH) == SPI_CRC_LENGTH_32BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_31BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_30BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_29BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_28BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_27BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_26BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_25BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_24BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_23BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_22BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_21BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_20BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_19BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_18BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_17BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_16BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_15BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_14BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_13BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_12BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_11BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_10BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_9BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_7BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_6BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_4BIT)) + + +#define IS_SPI_LIMITED_TRANSFER_SIZE(SIZE) (((SIZE) < 0x3FFU) && ((SIZE) != 0U)) + +/** + * @brief CRC Length for limited instance + */ +#define IS_SPI_LIMITED_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_16BIT)) + + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL) + +#define IS_SPI_CRC_POLYNOMIAL_SIZE(POLYNOM, LENGTH) (((POLYNOM) >> (((LENGTH) >> SPI_CFG1_CRCSIZE_Pos) + 1UL)) == 0UL) + + + +#define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \ + ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED)) + +#define IS_SPI_RDY_MASTER_MANAGEMENT(MANAGEMENT) (((MANAGEMENT) == SPI_RDY_MASTER_MANAGEMENT_INTERNALLY) || \ + ((MANAGEMENT) == SPI_RDY_MASTER_MANAGEMENT_EXTERNALLY)) + +#define IS_SPI_RDY_POLARITY(POLARITY) (((POLARITY) == SPI_RDY_POLARITY_HIGH) || \ + ((POLARITY) == SPI_RDY_POLARITY_LOW)) + +#define IS_SPI_MASTER_RX_AUTOSUSP(MODE) (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \ + ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE)) + +#define IS_SPI_TRANSFER_SIZE(SIZE) (((SIZE) < 0xFFFFU) && ((SIZE) != 0U)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_SPI_H */ + +/** + * @} + */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi_ex.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi_ex.h new file mode 100644 index 000000000..5b3cdbcb5 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi_ex.h @@ -0,0 +1,254 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_spi_ex.h + * @author MCD Application Team + * @brief Header file of SPI HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_SPI_EX_H +#define STM32U5xx_HAL_SPI_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPIEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPIEx_Exported_Types SPIEx Exported Types + * @{ + */ + +/** + * @brief SPI Autonomous Mode Configuration structure definition + */ +typedef struct +{ + uint32_t TriggerState; /*!< Specifies the trigger state. This parameter can be a value + of @ref FunctionalState */ + + uint32_t TriggerSelection; /*!< Specifies the autonomous mode trigger signal selection. This parameter + can be a value of @ref SPI_AutonomousMode_TriggerSelection */ + + uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity sensitivity. This parameter + can be a value of @ref SPI_AutonomousMode_TriggerPolarity */ + +} SPI_AutonomousModeConfTypeDef; + + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPIEx_Exported_Constants SPIEx Exported Constants + * @{ + */ + +/** @defgroup FunctionalState SPI Autonomous Mode State + * @{ + */ +#define SPI_AUTO_MODE_DISABLE (0x00000000UL) +#define SPI_AUTO_MODE_ENABLE SPI_AUTOCR_TRIGEN +/** + * @} + */ + +/** @defgroup SPI_AutonomousMode_TriggerSelection Autonomous Mode Trigger Selection + * @{ + */ +#define SPI_TRIG_GRP1 (0x10000000U) /* Trigger Group for SPI1 and SPI2 */ +#if defined(SPI3) +#define SPI_TRIG_GRP2 (0x20000000U) /* Trigger Group for SPI3 */ +#endif /* GRP2_AVAILABILITY */ + +/* HW Trigger signal is GPDMA_CH0_TRG */ +#define SPI_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x00000000U)) +/* HW Trigger signal is GPDMA_CH1_TRG */ +#define SPI_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x1UL << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is GPDMA_CH2_TRG */ +#define SPI_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x2UL << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is GPDMA_CH3_TRG */ +#define SPI_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x3UL << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is EXTI4_TRG */ +#define SPI_GRP1_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x4UL << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is EXTI9_TRG */ +#define SPI_GRP1_EXTI9_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x5UL << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is LPTIM1_CH1_TRG */ +#define SPI_GRP1_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x6UL << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is LPTIM2_CH1_TRG */ +#define SPI_GRP1_LPTIM2_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x7UL << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is COMP1_TRG */ +#define SPI_GRP1_COMP1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x8UL << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is COMP2_TRG */ +#define SPI_GRP1_COMP2_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x9UL << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is RTC_ALRA_TRG */ +#define SPI_GRP1_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xAUL << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is RTC_WUT_TRG */ +#define SPI_GRP1_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xBUL << SPI_AUTOCR_TRIGSEL_Pos)) + +#if defined(SPI3) +/* HW Trigger signal is LPDMA_CH0_TRG */ +#define SPI_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x00000000U)) +/* HW Trigger signal is LPDMA_CH1_TRG */ +#define SPI_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x1UL << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is LPDMA_CH2_TRG */ +#define SPI_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x2UL << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is LPDMA_CH3_TRG */ +#define SPI_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x3UL << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is EXTI4_TRG */ +#define SPI_GRP2_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x4UL << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is EXTI8_TRG */ +#define SPI_GRP2_EXTI8_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x5UL << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is LPTIM1_CH1_TRG */ +#define SPI_GRP2_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x6UL << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is LPTIM3_CH1_TRG */ +#define SPI_GRP2_LPTIM3_CH1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x7UL << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is COMP1_TRG */ +#define SPI_GRP2_COMP1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x8UL << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is COMP2_TRG */ +#define SPI_GRP2_COMP2_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x9UL << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is RTC_ALRA_TRG */ +#define SPI_GRP2_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xAUL << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is RTC_WUT_TRG */ +#define SPI_GRP2_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xBUL << SPI_AUTOCR_TRIGSEL_Pos)) +#endif /* GRP2_AVAILABILITY */ +/** + * @} + */ + +/** @defgroup SPI_AutonomousMode_TriggerPolarity Autonomous Mode Trigger Polarity + * @{ + */ +#define SPI_TRIG_POLARITY_RISING (0x00000000UL) /* SPI HW Trigger signal on rising edge */ +#define SPI_TRIG_POLARITY_FALLING SPI_AUTOCR_TRIGPOL /* SPI HW Trigger signal on falling edge */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup SPIEx_Exported_Macros SPIEx Extended Exported Macros + * @{ + */ + +#define IS_SPI_AUTO_MODE(__MODE__) (((__MODE__) == SPI_AUTO_MODE_DISABLE) || \ + ((__MODE__) == SPI_AUTO_MODE_ENABLE)) + +#if defined(SPI_TRIG_GRP2) +#define IS_SPI_AUTONOMOUS_INSTANCE(__INSTANCE__) (IS_SPI_GRP1_INSTANCE(__INSTANCE__) || \ + IS_SPI_GRP2_INSTANCE(__INSTANCE__)) +#else +#define IS_SPI_AUTONOMOUS_INSTANCE(__INSTANCE__) IS_SPI_GRP1_INSTANCE(__INSTANCE__) +#endif /* SPI_TRIG_GRP2 */ + +#if defined(SPI_TRIG_GRP2) +#define IS_SPI_TRIG_SOURCE(__INSTANCE__, __SOURCE__) ((IS_SPI_GRP2_INSTANCE(__INSTANCE__)) ? \ + IS_SPI_GRP2_TRIG_SOURCE(__SOURCE__) : \ + IS_SPI_GRP1_TRIG_SOURCE(__SOURCE__)) +#endif /* SPI_TRIG_GRP2 */ + +#define IS_SPI_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SPI_GRP1_GPDMA_CH0_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_GPDMA_CH1_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_GPDMA_CH2_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_GPDMA_CH3_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_EXTI4_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_EXTI9_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_LPTIM1_CH1_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_LPTIM2_CH1_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_COMP1_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_COMP2_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_RTC_ALRA_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_RTC_WUT_TRG )) + +#define IS_SPI_GRP2_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SPI_GRP2_LPDMA_CH0_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_LPDMA_CH1_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_LPDMA_CH2_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_LPDMA_CH3_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_EXTI4_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_EXTI8_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_LPTIM1_CH1_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_LPTIM3_CH1_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_COMP1_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_COMP2_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_RTC_ALRA_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_RTC_WUT_TRG )) + +#define IS_SPI_AUTO_MODE_TRG_POL(__POLARITY__) (((__POLARITY__) == SPI_TRIG_POLARITY_RISING) || \ + ((__POLARITY__) == SPI_TRIG_POLARITY_FALLING)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPIEx_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/* IO operation functions *****************************************************/ +/** @addtogroup SPIEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, + uint32_t UnderrunBehaviour); +/** + * @} + */ + +/** @addtogroup SPI_Autonomous_Mode_Functions Autonomous Mode Functions + * @{ + */ +HAL_StatusTypeDef HAL_SPIEx_SetConfigAutonomousMode(SPI_HandleTypeDef *hspi, + const SPI_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_SPIEx_GetConfigAutonomousMode(const SPI_HandleTypeDef *hspi, + SPI_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_SPIEx_ClearConfigAutonomousMode(SPI_HandleTypeDef *hspi); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_SPI_EX_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h new file mode 100644 index 000000000..683d4a640 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h @@ -0,0 +1,1747 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_uart.h + * @author MCD Application Team + * @brief Header file of UART HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_UART_H +#define STM32U5xx_HAL_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Types UART Exported Types + * @{ + */ + +/** + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate register is computed using the following formula: + @note For LPUART : + Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler. + @note For UART : + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where uart_ker_ck_pres is the UART input clock divided by a prescaler */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UARTEx_Word_Length. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode. */ + + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control. */ + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, + to achieve higher speed (up to f_PCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. */ + + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. + This parameter can be a value of @ref UART_ClockPrescaler. */ + +} UART_InitTypeDef; + +/** + * @brief UART Advanced Features initialization structure definition + */ +typedef struct +{ + uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several + Advanced Features may be initialized at the same time . + This parameter can be a value of + @ref UART_Advanced_Features_Initialization_Type. */ + + uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. + This parameter can be a value of @ref UART_Tx_Inv. */ + + uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. + This parameter can be a value of @ref UART_Rx_Inv. */ + + uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic + vs negative/inverted logic). + This parameter can be a value of @ref UART_Data_Inv. */ + + uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. + This parameter can be a value of @ref UART_Rx_Tx_Swap. */ + + uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. + This parameter can be a value of @ref UART_Overrun_Disable. */ + +#if defined(HAL_DMA_MODULE_ENABLED) + uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. + This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. + This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ + + uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate + detection is carried out. + This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */ + + uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. + This parameter can be a value of @ref UART_MSB_First. */ +} UART_AdvFeatureInitTypeDef; + +/** + * @brief HAL UART State definition + * @note HAL UART State value is a combination of 2 different substates: + * gState and RxState (see @ref UART_State_Definition). + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef uint32_t HAL_UART_StateTypeDef; + +/** + * @brief HAL UART Reception type definition + * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. + * This parameter can be a value of @ref UART_Reception_Type_Values : + * HAL_UART_RECEPTION_STANDARD = 0x00U, + * HAL_UART_RECEPTION_TOIDLE = 0x01U, + * HAL_UART_RECEPTION_TORTO = 0x02U, + * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U, + */ +typedef uint32_t HAL_UART_RxTypeTypeDef; + +/** + * @brief HAL UART Rx Event type definition + * @note HAL UART Rx Event type value aims to identify which type of Event has occurred + * leading to call of the RxEvent callback. + * This parameter can be a value of @ref UART_RxEvent_Type_Values : + * HAL_UART_RXEVENT_TC = 0x00U, + * HAL_UART_RXEVENT_HT = 0x01U, + * HAL_UART_RXEVENT_IDLE = 0x02U, + */ +typedef uint32_t HAL_UART_RxEventTypeTypeDef; + +/** + * @brief UART handle Structure definition + */ +typedef struct __UART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< UART registers base address */ + + UART_InitTypeDef Init; /*!< UART communication parameters */ + + UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< UART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< UART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + + uint16_t Mask; /*!< UART Rx RDR register mask */ + + uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. + This parameter can be a value of @ref UARTEx_FIFO_mode. */ + + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ + + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ + + __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + + __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ + + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. This parameter + can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This + parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ + void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ + void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ + void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ + void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ + void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */ + void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */ + void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ + + void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ + void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +} UART_HandleTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL UART Callback ID enumeration definition + */ +typedef enum +{ + HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ + HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ + HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ + HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ + HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ + HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ + HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ + HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ + HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */ + HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */ + + HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ + HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ + +} HAL_UART_CallbackIDTypeDef; + +/** + * @brief HAL UART Callback pointer definition + */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef) +(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants UART Exported Constants + * @{ + */ + +/** @defgroup UART_State_Definition UART State Code Definition + * @{ + */ +#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState.Value is result + of combination (Or) between gState and RxState values */ +#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + +/** @defgroup UART_Error_Definition UART Error Definition + * @{ + */ +#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#endif /* HAL_DMA_MODULE_ENABLED */ +#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup UART_Stop_Bits UART Number of Stop Bits + * @{ + */ +#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ +#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ +#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ +#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ +/** + * @} + */ + +/** @defgroup UART_Parity UART Parity + * @{ + */ +#define UART_PARITY_NONE 0x00000000U /*!< No parity */ +#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ +/** + * @} + */ + +/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control + * @{ + */ +#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ +#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ +#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ +#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ +/** + * @} + */ + +/** @defgroup UART_Mode UART Transfer Mode + * @{ + */ +#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +/** + * @} + */ + +/** @defgroup UART_State UART State + * @{ + */ +#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ +#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ +/** + * @} + */ + +/** @defgroup UART_Over_Sampling UART Over Sampling + * @{ + */ +#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method + * @{ + */ +#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ +#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ +/** + * @} + */ + +/** @defgroup UART_ClockPrescaler UART Clock Prescaler + * @{ + */ +#define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define UART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define UART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define UART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define UART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define UART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define UART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ +/** + * @} + */ + +/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection + on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection + on falling edge */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection + on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection + on 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup UART_Receiver_Timeout UART Receiver Timeout + * @{ + */ +#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ +/** + * @} + */ + +/** @defgroup UART_LIN UART Local Interconnection Network mode + * @{ + */ +#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ +#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ +/** + * @} + */ + +/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection + * @{ + */ +#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ +#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ +/** + * @} + */ + +#if defined(HAL_DMA_MODULE_ENABLED) +/** @defgroup UART_DMA_Tx UART DMA Tx + * @{ + */ +#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ +#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ +/** + * @} + */ + +/** @defgroup UART_DMA_Rx UART DMA Rx + * @{ + */ +#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ +#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ +/** + * @} + */ +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection + * @{ + */ +#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ +#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ +/** + * @} + */ + +/** @defgroup UART_WakeUp_Methods UART WakeUp Methods + * @{ + */ +#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ +#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ +/** + * @} + */ + +/** @defgroup UART_Request_Parameters UART Request Parameters + * @{ + */ +#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ +#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ +#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ +#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ +/** + * @} + */ + +/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type + * @{ + */ +#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ +#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ +#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ +#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ +#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ +#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ +#endif /* HAL_DMA_MODULE_ENABLED */ +#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ +#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ +/** + * @} + */ + +/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ +#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ +#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion + * @{ + */ +#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ +#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap + * @{ + */ +#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ +#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ +/** + * @} + */ + +/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable + * @{ + */ +#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ +#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ +/** + * @} + */ + +/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ +/** + * @} + */ + +#if defined(HAL_DMA_MODULE_ENABLED) +/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error + * @{ + */ +#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ +#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ +/** + * @} + */ +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** @defgroup UART_MSB_First UART Advanced Feature MSB First + * @{ + */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received + first disable */ +#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received + first enable */ +/** + * @} + */ + +/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable + * @{ + */ +#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ +#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ +/** + * @} + */ + +/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable + * @{ + */ +#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ +#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ +/** + * @} + */ + +/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register + * @{ + */ +#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ +/** + * @} + */ + +/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection + * @{ + */ +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY 0x00000001U /*!< UART wake-up on receive data register + not empty or RXFIFO is not empty */ +/** + * @} + */ + +/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity + * @{ + */ +#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ +#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB + position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB + position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask + * @{ + */ +#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ +/** + * @} + */ + +/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value + * @{ + */ +#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ +/** + * @} + */ + +/** @defgroup UART_Flags UART Status Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define UART_FLAG_TXFT USART_ISR_TXFT /*!< UART TXFIFO threshold flag */ +#define UART_FLAG_RXFT USART_ISR_RXFT /*!< UART RXFIFO threshold flag */ +#define UART_FLAG_RXFF USART_ISR_RXFF /*!< UART RXFIFO Full flag */ +#define UART_FLAG_TXFE USART_ISR_TXFE /*!< UART TXFIFO Empty flag */ +#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ +#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ +#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ +#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ +#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ +#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ +#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ +#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ +#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ +#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ +#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ +#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ +#define UART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< UART transmit data register empty */ +#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */ +#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ +#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */ +#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */ +#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ +#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ +#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ +#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ +#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ +/** + * @} + */ + +/** @defgroup UART_Interrupt_definition UART Interrupts Definition + * Elements values convention: 000ZZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZZ : Flag position in the ISR register(5bits) + * Elements values convention: 000000000XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * Elements values convention: 0000ZZZZ00000000b + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ +#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ +#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ +#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ +#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ + +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ + +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ +/** + * @} + */ + +/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags + * @{ + */ +#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define UART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ +#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ +#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define UART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */ +#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ +#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ +#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ +#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ +/** + * @} + */ + +/** @defgroup UART_Reception_Type_Values UART Reception type values + * @{ + */ +#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ +#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ +#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */ +#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */ +/** + * @} + */ + +/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values + * @{ + */ +#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ +#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ +#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup UART_Exported_Macros UART Exported Macros + * @{ + */ + +/** @brief Reset UART handle states. + * @param __HANDLE__ UART handle. + * @retval None + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ + +/** @brief Flush the UART Data registers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ + } while(0U) + +/** @brief Clear the specified UART pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @retval None + */ +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the UART PE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) + +/** @brief Clear the UART FE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) + +/** @brief Clear the UART NE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) + +/** @brief Clear the UART ORE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) + +/** @brief Clear the UART IDLE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) + +/** @brief Clear the UART TX FIFO empty clear flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF) + +/** @brief Check whether the specified UART flag is set or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref UART_FLAG_TXFT TXFIFO threshold flag + * @arg @ref UART_FLAG_RXFT RXFIFO threshold flag + * @arg @ref UART_FLAG_RXFF RXFIFO Full flag + * @arg @ref UART_FLAG_TXFE TXFIFO Empty flag + * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag + * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) + * @arg @ref UART_FLAG_SBKF Send Break flag + * @arg @ref UART_FLAG_CMF Character match flag + * @arg @ref UART_FLAG_BUSY Busy flag + * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag + * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag + * @arg @ref UART_FLAG_CTS CTS Change flag + * @arg @ref UART_FLAG_LBDF LIN Break detection flag + * @arg @ref UART_FLAG_TXE Transmit data register empty flag + * @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag + * @arg @ref UART_FLAG_TC Transmission Complete flag + * @arg @ref UART_FLAG_RXNE Receive data register not empty flag + * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag + * @arg @ref UART_FLAG_RTOF Receiver Timeout flag + * @arg @ref UART_FLAG_IDLE Idle Line detection flag + * @arg @ref UART_FLAG_ORE Overrun Error flag + * @arg @ref UART_FLAG_NE Noise Error flag + * @arg @ref UART_FLAG_FE Framing Error flag + * @arg @ref UART_FLAG_PE Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Enable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Disable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Check whether the specified UART interrupt has occurred or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt to check. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) + +/** @brief Check whether the specified UART interrupt source is enabled or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + UART_IT_MASK))) != RESET) ? SET : RESET) + +/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt + * This parameter can be one of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @retval None + */ +#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific UART request flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __REQ__ specifies the request flag to set + * This parameter can be one of the following values: + * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request + * @arg @ref UART_SENDBREAK_REQUEST Send Break Request + * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request + * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request + * @retval None + */ +#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) + +/** @brief Enable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** @brief Enable CTS flow control. + * @note This macro allows to enable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ + } while(0U) + +/** @brief Disable CTS flow control. + * @note This macro allows to disable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ + } while(0U) + +/** @brief Enable RTS flow control. + * @note This macro allows to enable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ + } while(0U) + +/** @brief Disable RTS flow control. + * @note This macro allows to disable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ + } while(0U) +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +/** @brief Get UART clock division factor from clock prescaler value. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval UART clock division factor + */ +#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \ + (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) ? 1U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) ? 2U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) ? 4U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) ? 6U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) ? 8U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) ? 10U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) ? 12U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) + +/** @brief BRR division operation to set BRR register with LPUART. + * @param __PCLK__ LPUART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \ + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)) \ + ) + +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief Check whether or not UART instance is Low Power UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval SET (instance is LPUART) or RESET (instance isn't LPUART) + */ +#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance)) + +/** @brief Check UART Baud rate. + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on U5 (i.e. 160 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) + */ +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 20000000U) + +/** @brief Check UART assertion time. + * @param __TIME__ 5-bit value assertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** @brief Check UART deassertion time. + * @param __TIME__ 5-bit value deassertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** + * @brief Ensure that UART frame number of stop bits is valid. + * @param __STOPBITS__ UART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ + ((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_1_5) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) + +/** + * @brief Ensure that LPUART frame number of stop bits is valid. + * @param __STOPBITS__ LPUART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) + +/** + * @brief Ensure that UART frame parity is valid. + * @param __PARITY__ UART frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ + ((__PARITY__) == UART_PARITY_EVEN) || \ + ((__PARITY__) == UART_PARITY_ODD)) + +/** + * @brief Ensure that UART hardware flow control is valid. + * @param __CONTROL__ UART hardware flow control. + * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) + */ +#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ + (((__CONTROL__) == UART_HWCONTROL_NONE) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS) || \ + ((__CONTROL__) == UART_HWCONTROL_CTS) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) + +/** + * @brief Ensure that UART communication mode is valid. + * @param __MODE__ UART communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) + +/** + * @brief Ensure that UART state is valid. + * @param __STATE__ UART state. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ + ((__STATE__) == UART_STATE_ENABLE)) + +/** + * @brief Ensure that UART oversampling is valid. + * @param __SAMPLING__ UART oversampling. + * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) + */ +#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == UART_OVERSAMPLING_8)) + +/** + * @brief Ensure that UART frame sampling is valid. + * @param __ONEBIT__ UART frame sampling. + * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) + */ +#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ + ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) + +/** + * @brief Ensure that UART auto Baud rate detection mode is valid. + * @param __MODE__ UART auto Baud rate detection mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) + +/** + * @brief Ensure that UART receiver timeout setting is valid. + * @param __TIMEOUT__ UART receiver timeout setting. + * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) + */ +#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) + +/** @brief Check the receiver timeout value. + * @note The maximum UART receiver timeout value is 0xFFFFFF. + * @param __TIMEOUTVALUE__ receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) + +/** + * @brief Ensure that UART LIN state is valid. + * @param __LIN__ UART LIN state. + * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) + */ +#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ + ((__LIN__) == UART_LIN_ENABLE)) + +/** + * @brief Ensure that UART LIN break detection length is valid. + * @param __LENGTH__ UART LIN break detection length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Ensure that UART DMA TX state is valid. + * @param __DMATX__ UART DMA TX state. + * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) + */ +#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ + ((__DMATX__) == UART_DMA_TX_ENABLE)) + +/** + * @brief Ensure that UART DMA RX state is valid. + * @param __DMARX__ UART DMA RX state. + * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) + */ +#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ + ((__DMARX__) == UART_DMA_RX_ENABLE)) + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @brief Ensure that UART half-duplex state is valid. + * @param __HDSEL__ UART half-duplex state. + * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) + */ +#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ + ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) + +/** + * @brief Ensure that UART wake-up method is valid. + * @param __WAKEUP__ UART wake-up method . + * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) + */ +#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) + +/** + * @brief Ensure that UART request parameter is valid. + * @param __PARAM__ UART request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ + ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ + ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ + ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) + +/** + * @brief Ensure that UART advanced features initialization is valid. + * @param __INIT__ UART advanced features initialization. + * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) + */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) +#else +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Ensure that UART frame TX inversion setting is valid. + * @param __TXINV__ UART frame TX inversion setting. + * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ + ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX inversion setting is valid. + * @param __RXINV__ UART frame RX inversion setting. + * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ + ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) + +/** + * @brief Ensure that UART frame data inversion setting is valid. + * @param __DATAINV__ UART frame data inversion setting. + * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ + ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX/TX pins swap setting is valid. + * @param __SWAP__ UART frame RX/TX pins swap setting. + * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) + */ +#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ + ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) + +/** + * @brief Ensure that UART frame overrun setting is valid. + * @param __OVERRUN__ UART frame overrun setting. + * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) + */ +#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ + ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) + +/** + * @brief Ensure that UART auto Baud rate state is valid. + * @param __AUTOBAUDRATE__ UART auto Baud rate state. + * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \ + UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ + ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Ensure that UART DMA enabling or disabling on error setting is valid. + * @param __DMA__ UART DMA enabling or disabling on error setting. + * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) + */ +#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ + ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Ensure that UART frame MSB first setting is valid. + * @param __MSBFIRST__ UART frame MSB first setting. + * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) + */ +#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ + ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) + +/** + * @brief Ensure that UART stop mode state is valid. + * @param __STOPMODE__ UART stop mode state. + * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ + ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) + +/** + * @brief Ensure that UART mute mode state is valid. + * @param __MUTE__ UART mute mode state. + * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) + */ +#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ + ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) + +/** + * @brief Ensure that UART wake-up selection is valid. + * @param __WAKE__ UART wake-up selection. + * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) + */ +#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ + ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) + +/** + * @brief Ensure that UART driver enable polarity is valid. + * @param __POLARITY__ UART driver enable polarity. + * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) + */ +#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ + ((__POLARITY__) == UART_DE_POLARITY_LOW)) + +/** + * @brief Ensure that UART Prescaler is valid. + * @param __CLOCKPRESCALER__ UART Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256)) + +/** + * @} + */ + +/* Include UART HAL Extended module */ +#include "stm32u5xx_hal_uart_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); +void HAL_UART_MspInit(UART_HandleTypeDef *huart); +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +#endif /* HAL_DMA_MODULE_ENABLED */ +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); + +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); +void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); + +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************************/ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -----------------------------------------------------------*/ +/** @addtogroup UART_Private_Functions UART Private Functions + * @{ + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @} + */ + +/* Private variables -----------------------------------------------------------*/ +/** @defgroup UART_Private_variables UART Private variables + * @{ + */ +/* Prescaler Table used in BRR computation macros. + Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ +extern const uint16_t UARTPrescTable[12]; +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_UART_H */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h new file mode 100644 index 000000000..3715f445c --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h @@ -0,0 +1,545 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_uart_ex.h + * @author MCD Application Team + * @brief Header file of UART HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_UART_EX_H +#define STM32U5xx_HAL_UART_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup UARTEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Types UARTEx Exported Types + * @{ + */ + +/** + * @brief UART wake up from stop mode parameters + */ +typedef struct +{ + uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF). + This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. + If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must + be filled up. */ + + uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. + This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ + + uint8_t Address; /*!< UART/USART node address (7-bit long max). */ +} UART_WakeUpTypeDef; + +/** + * @brief UART Autonomous mode parameters + */ +typedef struct +{ + uint32_t AutonomousModeState; /*!< Specifies the autonomous mode state.This parameter can be a value of + @ref UARTEx_Autonomous_mode.*/ + + uint32_t TriggerSelection; /*!< Specifies which trigger will activate the Transmission automatically. + This parameter can be a value of @ref UARTEx_Autonomous_Trigger_selection + or @ref UARTEx_Low_Power_Autonomous_Trigger_selection.*/ + + uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity. + This parameter can be a value of @ref UARTEx_Autonomous_Trigger_Polarity */ + + uint32_t DataSize; /*!< Specifies the transmitted data size in byte */ + + uint32_t IdleFrame; /*!< Specifies whether the IDLE frame transmission is enabled or disabled. + This parameter can be a value of @ref UARTEx_Autonomous_IDLE_FRAME. */ +} UART_AutonomousModeConfTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants + * @{ + */ + +/** @defgroup UARTEx_Word_Length UARTEx Word Length + * @{ + */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ +/** + * @} + */ + +/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length + * @{ + */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ +/** + * @} + */ + +/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode + * @brief UART FIFO mode + * @{ + */ +#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level + * @brief UART TXFIFO threshold level + * @{ + */ +#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */ +#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */ +/** + * @} + */ + +/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level + * @brief UART RXFIFO threshold level + * @{ + */ +#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */ +#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */ +/** + * @} + */ + +/** @defgroup UARTEx_Autonomous_mode UARTEx Autonomous Mode + * @brief UART Autonomous mode + * @{ + */ +#define UART_AUTONOMOUS_MODE_DISABLE 0x00000000U /*!< Autonomous mode disable */ +#define UART_AUTONOMOUS_MODE_ENABLE USART_AUTOCR_TRIGEN /*!< Autonomous mode enable */ +/** + * @} + */ + +/** @defgroup UARTEx_Autonomous_Trigger_Polarity UARTEx Autonomous Trigger Polarity + * @brief UART Trigger polarity edge selection + * @{ + */ +#define UART_TRIG_POLARITY_RISING 0x00000000U /*!< UART triggered on rising edge */ +#define UART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< UART triggered on falling edge */ +/** + * @} + */ + +/** @defgroup UARTEx_Autonomous_IDLE_FRAME UARTEx Autonomous IDLE Frame + * @brief UART IDLE frame transmission + * @{ + */ +#define UART_IDLE_FRAME_ENABLE 0x00000000U /*!< IDLE Frame sent after enabling the transmitter */ +#define UART_IDLE_FRAME_DISABLE USART_AUTOCR_IDLEDIS /*!< IDLE Frame not sent after enabling the transmitter */ +/** + * @} + */ + +/** @defgroup UARTEx_Autonomous_Trigger_selection UARTEx Autonomous trigger selection + * @brief UART Autonomous Trigger selection + * @{ + */ +#define UART_GPDMA1_CH0_TCF_TRG 0U /*!< UART GPDMA1 channel0 Internal Trigger */ +#define UART_GPDMA1_CH1_TCF_TRG 1U /*!< UART GPDMA1 channel1 Internal Trigger */ +#define UART_GPDMA1_CH2_TCF_TRG 2U /*!< UART GPDMA1 channel2 Internal Trigger */ +#define UART_GPDMA1_CH3_TCF_TRG 3U /*!< UART GPDMA1 channel3 Internal Trigger */ +#define UART_EXTI_LINE6_TRG 4U /*!< UART EXTI line 6 Internal Trigger */ +#define UART_EXTI_LINE9_TRG 5U /*!< UART EXTI line 9 Internal Trigger */ +#define UART_LPTIM1_OUT_TRG 6U /*!< UART LPTIM1 out Internal Trigger */ +#define UART_LPTIM2_OUT_TRG 7U /*!< UART LPTIM2 out Internal Trigger */ +#define UART_COMP1_OUT_TRG 8U /*!< UART COMP1 out Internal Trigger */ +#define UART_COMP2_OUT_TRG 9U /*!< UART COMP2 out Internal Trigger */ +#define UART_RTC_ALRA_TRG 10U /*!< UART RTC alarm Internal Trigger */ +#define UART_RTC_WUT_TRG 11U /*!< UART RTC wakeup Internal Trigger */ +/** + * @} + */ + +/** @defgroup UARTEx_Low_Power_Autonomous_Trigger_selection UARTEx Low Power Autonomous trigger selection + * @brief LPUART Autonomous Trigger selection + * @{ + */ +#define LPUART_LPDMA1_CH0_TCF_TRG 0U /*!< LPUART LPDMA1 channel0 Internal Trigger */ +#define LPUART_LPDMA1_CH1_TCF_TRG 1U /*!< LPUART LPDMA1 channel1 Internal Trigger */ +#define LPUART_LPDMA1_CH2_TCF_TRG 2U /*!< LPUART LPDMA1 channel2 Internal Trigger */ +#define LPUART_LPDMA1_CH3_TCF_TRG 3U /*!< LPUART LPDMA1 channel3 Internal Trigger */ +#define LPUART_EXTI_LINE6_TRG 4U /*!< LPUART EXTI line 6 Internal Trigger */ +#define LPUART_EXTI_LINE8_TRG 5U /*!< LPUART EXTI line 8 Internal Trigger */ +#define LPUART_LPTIM1_OUT_TRG 6U /*!< LPUART LPTIM1 out Internal Trigger */ +#define LPUART_LPTIM3_OUT_TRG 7U /*!< LPUART LPTIM3 out Internal Trigger */ +#define LPUART_COMP1_OUT_TRG 8U /*!< LPUART COMP1 out Internal Trigger */ +#define LPUART_COMP2_OUT_TRG 9U /*!< LPUART COMP2 out Internal Trigger */ +#define LPUART_RTC_ALRA_TRG 10U /*!< LPUART RTC alarm Internal Trigger */ +#define LPUART_RTC_WUT_TRG 11U /*!< LPUART RTC wakeup Internal Trigger */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup UARTEx_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime); + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group2 + * @{ + */ + +void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); +void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); + +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); + +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#endif /* HAL_DMA_MODULE_ENABLED */ + +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart); + +/* Autonomous Mode Control functions **********************************************/ +HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart, + const UART_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(const UART_HandleTypeDef *huart, + UART_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart); + + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UARTEx_Private_Macros UARTEx Private Macros + * @{ + */ + +/** @brief Report the UART clock source. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval UART clocking source, written in __CLOCKSOURCE__. + */ +#if defined(USART6) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART6; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ + } while(0U) +#elif defined(USART2) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ + } while(0U) +#else +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ + } while(0U) +#endif /* USART6 */ + +/** @brief Report the UART mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @note If PCE = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. + */ +#define UART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU ; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +/** + * @brief Ensure that UART frame length is valid. + * @param __LENGTH__ UART frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ + ((__LENGTH__) == UART_WORDLENGTH_8B) || \ + ((__LENGTH__) == UART_WORDLENGTH_9B)) + +/** + * @brief Ensure that UART wake-up address length is valid. + * @param __ADDRESS__ UART wake-up address length. + * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) + */ +#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ + ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) + +/** + * @brief Ensure that UART TXFIFO threshold level is valid. + * @param __THRESHOLD__ UART TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that UART RXFIFO threshold level is valid. + * @param __THRESHOLD__ UART RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that UART Trigger polarity state is valid. + * @param __POLARITY__ UART Trigger polarity. + * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) + */ +#define IS_UART_TRIGGER_POLARITY(__POLARITY__) (((__POLARITY__) == UART_TRIG_POLARITY_RISING) ||\ + ((__POLARITY__) == UART_TRIG_POLARITY_FALLING)) + +/** + * @brief Ensure that UART IDLE Frame Transmit state is valid. + * @param __IDLE__ UART IDLE Frame Transmit state. + * @retval SET (__IDLE__ is valid) or RESET (__IDLE__ is invalid) + */ +#define IS_UART_IDLE_FRAME_TRANSMIT(__IDLE__) (((__IDLE__) == UART_IDLE_FRAME_ENABLE) ||\ + ((__IDLE__) == UART_IDLE_FRAME_DISABLE)) + +/** + * @brief Ensure that UART Trigger source selection is valid. + * @param __SOURCE__ UART Trigger source selection. + * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid) + */ +#define IS_UART_TRIGGER_SELECTION(__SOURCE__) ((__SOURCE__) <= 11U) + +/** + * @brief Ensure that LPUART Trigger source selection is valid. + * @param __SOURCE__ LPUART Trigger source selection. + * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid) + */ +#define IS_LPUART_TRIGGER_SELECTION(__SOURCE__) ((__SOURCE__) <= 11U) + +/** + * @brief Ensure that the number of transferred data is valid. + * @param __SOURCE__ UART TX data size. + * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid) + */ +#define IS_UART_TX_DATA_SIZE(__SOURCE__) ((__SOURCE__) <= 0xFFFFU) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_UART_EX_H */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart.h new file mode 100644 index 000000000..ba77e3f54 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart.h @@ -0,0 +1,1134 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_usart.h + * @author MCD Application Team + * @brief Header file of USART HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_USART_H +#define STM32U5xx_HAL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup USART_Exported_Types USART Exported Types + * @{ + */ + +/** + * @brief USART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the Usart communication baud rate. + The baud rate is computed using the following formula: + Baud Rate Register[15:4] = ((2 * fclk_pres) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * fclk_pres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where fclk_pres is the USART input clock frequency (fclk) + divided by a prescaler. + @note Oversampling by 8 is systematically applied to + achieve high baud rates. */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USARTEx_Word_Length. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode. */ + + uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity. */ + + uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase. */ + + uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit. */ + + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source. + This parameter can be a value of @ref USART_ClockPrescaler. */ +} USART_InitTypeDef; + +/** + * @brief HAL USART State structures definition + */ +typedef enum +{ + HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */ + HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */ + HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_USART_STATE_ERROR = 0x04U /*!< Error */ +} HAL_USART_StateTypeDef; + +/** + * @brief USART clock sources definitions + */ +typedef enum +{ + USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ +} USART_ClockSourceTypeDef; + +/** + * @brief USART handle Structure definition + */ +typedef struct __USART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< USART registers base address */ + + USART_InitTypeDef Init; /*!< USART communication parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< USART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< USART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */ + + uint16_t Mask; /*!< USART Rx RDR register mask */ + + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ + + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ + + uint32_t SlaveMode; /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value + of @ref USARTEx_Slave_Mode */ + + uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value + of @ref USARTEx_FIFO_mode. */ + + void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */ + +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_USART_StateTypeDef State; /*!< USART communication state */ + + __IO uint32_t ErrorCode; /*!< USART Error code */ + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */ + void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */ + void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */ + void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */ + void (* RxFifoFullCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Fifo Full Callback */ + void (* TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Fifo Empty Callback */ + + void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */ + void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */ +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +} USART_HandleTypeDef; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL USART Callback ID enumeration definition + */ +typedef enum +{ + HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */ + HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */ + HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */ + HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */ + HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */ + HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */ + HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */ + HAL_USART_RX_FIFO_FULL_CB_ID = 0x07U, /*!< USART Rx Fifo Full Callback ID */ + HAL_USART_TX_FIFO_EMPTY_CB_ID = 0x08U, /*!< USART Tx Fifo Empty Callback ID */ + + HAL_USART_MSPINIT_CB_ID = 0x09U, /*!< USART MspInit callback ID */ + HAL_USART_MSPDEINIT_CB_ID = 0x0AU /*!< USART MspDeInit callback ID */ + +} HAL_USART_CallbackIDTypeDef; + +/** + * @brief HAL USART Callback pointer definition + */ +typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */ + +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_Exported_Constants USART Exported Constants + * @{ + */ + +/** @defgroup USART_Error_Definition USART Error Definition + * @{ + */ +#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#endif /* HAL_DMA_MODULE_ENABLED */ +#define HAL_USART_ERROR_UDR (0x00000020U) /*!< SPI slave underrun error */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */ +/** + * @} + */ + +/** @defgroup USART_Stop_Bits USART Number of Stop Bits + * @{ + */ +#define USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< USART frame with 0.5 stop bit */ +#define USART_STOPBITS_1 0x00000000U /*!< USART frame with 1 stop bit */ +#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */ +#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_Parity USART Parity + * @{ + */ +#define USART_PARITY_NONE 0x00000000U /*!< No parity */ +#define USART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ +/** + * @} + */ + +/** @defgroup USART_Mode USART Mode + * @{ + */ +#define USART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define USART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +/** + * @} + */ + +/** @defgroup USART_Clock USART Clock + * @{ + */ +#define USART_CLOCK_DISABLE 0x00000000U /*!< USART clock disable */ +#define USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< USART clock enable */ +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity USART Clock Polarity + * @{ + */ +#define USART_POLARITY_LOW 0x00000000U /*!< Driver enable signal is active high */ +#define USART_POLARITY_HIGH USART_CR2_CPOL /*!< Driver enable signal is active low */ +/** + * @} + */ + +/** @defgroup USART_Clock_Phase USART Clock Phase + * @{ + */ +#define USART_PHASE_1EDGE 0x00000000U /*!< USART frame phase on first clock transition */ +#define USART_PHASE_2EDGE USART_CR2_CPHA /*!< USART frame phase on second clock transition */ +/** + * @} + */ + +/** @defgroup USART_Last_Bit USART Last Bit + * @{ + */ +#define USART_LASTBIT_DISABLE 0x00000000U /*!< USART frame last data bit clock pulse not output to SCLK pin */ +#define USART_LASTBIT_ENABLE USART_CR2_LBCL /*!< USART frame last data bit clock pulse output to SCLK pin */ +/** + * @} + */ + +/** @defgroup USART_ClockPrescaler USART Clock Prescaler + * @{ + */ +#define USART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define USART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define USART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define USART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define USART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define USART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define USART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define USART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define USART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define USART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define USART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define USART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ + +/** + * @} + */ + +/** @defgroup USART_Request_Parameters USART Request Parameters + * @{ + */ +#define USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ +/** + * @} + */ + +/** @defgroup USART_Flags USART Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define USART_FLAG_TXFT USART_ISR_TXFT /*!< USART TXFIFO threshold flag */ +#define USART_FLAG_RXFT USART_ISR_RXFT /*!< USART RXFIFO threshold flag */ +#define USART_FLAG_RXFF USART_ISR_RXFF /*!< USART RXFIFO Full flag */ +#define USART_FLAG_TXFE USART_ISR_TXFE /*!< USART TXFIFO Empty flag */ +#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */ +#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */ +#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */ +#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */ +#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */ +#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */ +#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */ +#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */ +#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */ +#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */ +#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */ +#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */ +#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */ +#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */ +#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */ +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition USART Interrupts Definition + * Elements values convention: 0000ZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ + +#define USART_IT_PE 0x0028U /*!< USART parity error interruption */ +#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */ +#define USART_IT_TXFNF 0x0727U /*!< USART TX FIFO not full interruption */ +#define USART_IT_TC 0x0626U /*!< USART transmission complete interruption */ +#define USART_IT_RXNE 0x0525U /*!< USART read data register not empty interruption */ +#define USART_IT_RXFNE 0x0525U /*!< USART RXFIFO not empty interruption */ +#define USART_IT_IDLE 0x0424U /*!< USART idle interruption */ +#define USART_IT_ERR 0x0060U /*!< USART error interruption */ +#define USART_IT_ORE 0x0300U /*!< USART overrun error interruption */ +#define USART_IT_NE 0x0200U /*!< USART noise error interruption */ +#define USART_IT_FE 0x0100U /*!< USART frame error interruption */ +#define USART_IT_RXFF 0x183FU /*!< USART RXFIFO full interruption */ +#define USART_IT_TXFE 0x173EU /*!< USART TXFIFO empty interruption */ +#define USART_IT_RXFT 0x1A7CU /*!< USART RXFIFO threshold reached interruption */ +#define USART_IT_TXFT 0x1B77U /*!< USART TXFIFO threshold reached interruption */ + +/** + * @} + */ + +/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags + * @{ + */ +#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define USART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ +#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ +#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */ +#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */ +#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */ +/** + * @} + */ + +/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask + * @{ + */ +#define USART_IT_MASK 0x001FU /*!< USART interruptions flags mask */ +#define USART_CR_MASK 0x00E0U /*!< USART control register mask */ +#define USART_CR_POS 5U /*!< USART control register position */ +#define USART_ISR_MASK 0x1F00U /*!< USART ISR register mask */ +#define USART_ISR_POS 8U /*!< USART ISR register position */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup USART_Exported_Macros USART Exported Macros + * @{ + */ + +/** @brief Reset USART handle state. + * @param __HANDLE__ USART handle. + * @retval None + */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_USART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** @brief Check whether the specified USART flag is set or not. + * @param __HANDLE__ specifies the USART Handle + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref USART_FLAG_TXFT TXFIFO threshold flag + * @arg @ref USART_FLAG_RXFT RXFIFO threshold flag + * @arg @ref USART_FLAG_RXFF RXFIFO Full flag + * @arg @ref USART_FLAG_TXFE TXFIFO Empty flag + * @arg @ref USART_FLAG_REACK Receive enable acknowledge flag + * @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref USART_FLAG_BUSY Busy flag + * @arg @ref USART_FLAG_UDR SPI slave underrun error flag + * @arg @ref USART_FLAG_TXE Transmit data register empty flag + * @arg @ref USART_FLAG_TXFNF TXFIFO not full flag + * @arg @ref USART_FLAG_TC Transmission Complete flag + * @arg @ref USART_FLAG_RXNE Receive data register not empty flag + * @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag + * @arg @ref USART_FLAG_RTOF Receiver Timeout flag + * @arg @ref USART_FLAG_IDLE Idle Line detection flag + * @arg @ref USART_FLAG_ORE OverRun Error flag + * @arg @ref USART_FLAG_NE Noise Error flag + * @arg @ref USART_FLAG_FE Framing Error flag + * @arg @ref USART_FLAG_PE Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified USART pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag + * @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag + * @retval None + */ +#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the USART PE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF) + +/** @brief Clear the USART FE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF) + +/** @brief Clear the USART NE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF) + +/** @brief Clear the USART ORE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF) + +/** @brief Clear the USART IDLE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF) + +/** @brief Clear the USART TX FIFO empty clear flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF) + +/** @brief Clear SPI slave underrun error flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF) + +/** @brief Enable the specified USART interrupt. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) + +/** @brief Disable the specified USART interrupt. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) + +/** @brief Check whether the specified USART interrupt has occurred or not. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_ORE OverRun Error interrupt + * @arg @ref USART_IT_NE Noise Error interrupt + * @arg @ref USART_IT_FE Framing Error interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\ + USART_ISR_POS))) != 0U) ? SET : RESET) + +/** @brief Check whether the specified USART interrupt source is enabled or not. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_ORE OverRun Error interrupt + * @arg @ref USART_IT_NE Noise Error interrupt + * @arg @ref USART_IT_FE Framing Error interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + USART_IT_MASK))) != 0U) ? SET : RESET) + +/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the USART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt. + * This parameter can be one of the following values: + * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @retval None + */ +#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific USART request flag. + * @param __HANDLE__ specifies the USART Handle. + * @param __REQ__ specifies the request flag to set. + * This parameter can be one of the following values: + * @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request + * + * @retval None + */ +#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the USART one bit sample method. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the USART one bit sample method. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) + +/** @brief Enable USART. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable USART. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup USART_Private_Macros USART Private Macros + * @{ + */ + +/** @brief Get USART clock division factor from clock prescaler value. + * @param __CLOCKPRESCALER__ USART prescaler value. + * @retval USART clock division factor + */ +#define USART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \ + (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) ? 1U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) ? 2U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) ? 4U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) ? 6U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) ? 8U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) ? 10U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) ? 12U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : 256U) + +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ USART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ USART prescaler value. + * @retval Division result + */ +#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)\ + (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\ + + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief Report the USART clock source. + * @param __HANDLE__ specifies the USART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval the USART clocking source, written in __CLOCKSOURCE__. + */ +#if defined(USART6) +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + switch(__HAL_RCC_GET_USART6_SOURCE()) \ + { \ + case RCC_USART6CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART6CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART6CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART6CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#elif defined(USART2) +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#else +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#endif /* USART6 */ + +/** @brief Check USART Baud rate. + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on U5 (i.e. 160 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ +#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 20000000U) + +/** + * @brief Ensure that USART frame number of stop bits is valid. + * @param __STOPBITS__ USART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \ + ((__STOPBITS__) == USART_STOPBITS_1) || \ + ((__STOPBITS__) == USART_STOPBITS_1_5) || \ + ((__STOPBITS__) == USART_STOPBITS_2)) + +/** + * @brief Ensure that USART frame parity is valid. + * @param __PARITY__ USART frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \ + ((__PARITY__) == USART_PARITY_EVEN) || \ + ((__PARITY__) == USART_PARITY_ODD)) + +/** + * @brief Ensure that USART communication mode is valid. + * @param __MODE__ USART communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) + +/** + * @brief Ensure that USART clock state is valid. + * @param __CLOCK__ USART clock state. + * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid) + */ +#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \ + ((__CLOCK__) == USART_CLOCK_ENABLE)) + +/** + * @brief Ensure that USART frame polarity is valid. + * @param __CPOL__ USART frame polarity. + * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) + */ +#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH)) + +/** + * @brief Ensure that USART frame phase is valid. + * @param __CPHA__ USART frame phase. + * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) + */ +#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE)) + +/** + * @brief Ensure that USART frame last bit clock pulse setting is valid. + * @param __LASTBIT__ USART frame last bit clock pulse setting. + * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) + */ +#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \ + ((__LASTBIT__) == USART_LASTBIT_ENABLE)) + +/** + * @brief Ensure that USART request parameter is valid. + * @param __PARAM__ USART request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST)) + +/** + * @brief Ensure that USART Prescaler is valid. + * @param __CLOCKPRESCALER__ USART Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_USART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256)) + +/** + * @} + */ + +/* Include USART HAL Extended module */ +#include "stm32u5xx_hal_usart_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USART_Exported_Functions USART Exported Functions + * @{ + */ + +/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart); +void HAL_USART_MspInit(USART_HandleTypeDef *husart); +void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart); +#endif /* HAL_DMA_MODULE_ENABLED */ +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart); + +void HAL_USART_IRQHandler(USART_HandleTypeDef *husart); +void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart); +void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart); + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State and Error functions ***************************************/ +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart); +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_USART_H */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart_ex.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart_ex.h new file mode 100644 index 000000000..8888f2fc7 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart_ex.h @@ -0,0 +1,394 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_usart_ex.h + * @author MCD Application Team + * @brief Header file of USART HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_USART_EX_H +#define STM32U5xx_HAL_USART_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup USARTEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup USARTEx_Exported_Types USARTEx Exported Types + * @{ + */ +/** + * @brief USART Autonomous mode parameters + */ +typedef struct +{ + uint32_t AutonomousModeState; /*!< Specifies the autonomous mode state.This parameter can be a value of + @ref USARTEx_Autonomous_mode.*/ + + uint32_t TriggerSelection; /*!< Specifies which trigger will activate the Transmission automatically. + This parameter can be a value of @ref USARTEx_Autonomous_Trigger_selection */ + + uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity. + This parameter can be a value of @ref USARTEx_Autonomous_Trigger_Polarity */ + + uint32_t DataSize; /*!< Specifies the transmitted data size in byte */ + + uint32_t IdleFrame; /*!< Specifies whether the IDLE frame transmission is enabled or disabled. + This parameter can be a value of @ref USARTEx_Autonomous_IDLE_FRAME. */ + +} USART_AutonomousModeConfTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants + * @{ + */ + +/** @defgroup USARTEx_Word_Length USARTEx Word Length + * @{ + */ +#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ +/** + * @} + */ + +/** @defgroup USARTEx_Slave_Select_management USARTEx Slave Select Management + * @{ + */ +#define USART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */ +#define USART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */ +/** + * @} + */ + + +/** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode enable + * @brief USART SLAVE mode + * @{ + */ +#define USART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */ +#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */ +/** + * @} + */ + +/** @defgroup USARTEx_FIFO_mode USARTEx FIFO mode + * @brief USART FIFO mode + * @{ + */ +#define USART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level + * @brief USART TXFIFO level + * @{ + */ +#define USART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ +#define USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ +#define USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ +#define USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ +#define USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ +#define USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ +/** + * @} + */ + +/** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level + * @brief USART RXFIFO level + * @{ + */ +#define USART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ +#define USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ +#define USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ +#define USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ +#define USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ +#define USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ +/** + * @} + */ + +/** @defgroup USARTEx_Autonomous_mode USARTEx Autonomous Mode + * @brief USART Autonomous mode + * @{ + */ +#define USART_AUTONOMOUS_MODE_DISABLE 0x00000000U /*!< Autonomous mode disable */ +#define USART_AUTONOMOUS_MODE_ENABLE USART_AUTOCR_TRIGEN /*!< Autonomous mode enable */ +/** + * @} + */ + +/** @defgroup USARTEx_Autonomous_Trigger_Polarity USARTEx Autonomous Trigger Polarity + * @brief USART Trigger polarity edge selection + * @{ + */ +#define USART_TRIG_POLARITY_RISING 0x00000000U /*!< USART triggered on rising edge */ +#define USART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< USART triggered on falling edge */ +/** + * @} + */ + +/** @defgroup USARTEx_Autonomous_IDLE_FRAME USARTEx Autonomous IDLE Frame + * @brief USART IDLE frame transmission + * @{ + */ +#define USART_IDLE_FRAME_ENABLE 0x00000000U /*!< IDLE Frame sent after enabling the transmitter */ +#define USART_IDLE_FRAME_DISABLE USART_AUTOCR_IDLEDIS /*!< IDLE Frame not sent after enabling the transmitter */ +/** + * @} + */ + +/** @defgroup USARTEx_Autonomous_Trigger_selection USARTEx Autonomous trigger selection + * @brief USART Autonomous Trigger selection + * @{ + */ +#define USART_GPDMA1_CH0_TCF_TRG 0U /*!< USART GPDMA1 channel0 Internal Trigger */ +#define USART_GPDMA1_CH1_TCF_TRG 1U /*!< USART GPDMA1 channel1 Internal Trigger */ +#define USART_GPDMA1_CH2_TCF_TRG 2U /*!< USART GPDMA1 channel2 Internal Trigger */ +#define USART_GPDMA1_CH3_TCF_TRG 3U /*!< USART GPDMA1 channel3 Internal Trigger */ +#define USART_EXTI_LINE6_TRG 4U /*!< USART EXTI line 6 Internal Trigger */ +#define USART_EXTI_LINE9_TRG 5U /*!< USART EXTI line 9 Internal Trigger */ +#define USART_LPTIM1_OUT_TRG 6U /*!< USART LPTIM1 out Internal Trigger */ +#define USART_LPTIM2_OUT_TRG 7U /*!< USART LPTIM2 out Internal Trigger */ +#define USART_COMP1_OUT_TRG 8U /*!< USART COMP1 out Internal Trigger */ +#define USART_COMP2_OUT_TRG 9U /*!< USART COMP2 out Internal Trigger */ +#define USART_RTC_ALRA_TRG 10U /*!< USART RTC alarm Internal Trigger */ +#define USART_RTC_WUT_TRG 11U /*!< USART RTC wakeup Internal Trigger */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup USARTEx_Private_Macros USARTEx Private Macros + * @{ + */ + +/** @brief Compute the USART mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @note If PCE = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @param __HANDLE__ specifies the USART Handle. + * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field. + */ +#define USART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +/** + * @brief Ensure that USART frame length is valid. + * @param __LENGTH__ USART frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \ + ((__LENGTH__) == USART_WORDLENGTH_8B) || \ + ((__LENGTH__) == USART_WORDLENGTH_9B)) + +/** + * @brief Ensure that USART Negative Slave Select (NSS) pin management is valid. + * @param __NSS__ USART Negative Slave Select pin management. + * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid) + */ +#define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \ + ((__NSS__) == USART_NSS_SOFT)) + +/** + * @brief Ensure that USART Slave Mode is valid. + * @param __STATE__ USART Slave Mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_USART_SLAVEMODE(__STATE__) (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \ + ((__STATE__) == USART_SLAVEMODE_ENABLE)) + +/** + * @brief Ensure that USART FIFO mode is valid. + * @param __STATE__ USART FIFO mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \ + ((__STATE__) == USART_FIFOMODE_ENABLE)) + +/** + * @brief Ensure that USART TXFIFO threshold level is valid. + * @param __THRESHOLD__ USART TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that USART RXFIFO threshold level is valid. + * @param __THRESHOLD__ USART RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8)) +/** + * @brief Ensure that USART Trigger polarity state is valid. + * @param __POLARITY__ USART Trigger polarity. + * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) + */ +#define IS_USART_TRIGGER_POLARITY(__POLARITY__) (((__POLARITY__) == USART_TRIG_POLARITY_RISING) ||\ + ((__POLARITY__) == USART_TRIG_POLARITY_FALLING)) + +/** + * @brief Ensure that USART IDLE Frame Transmit state is valid. + * @param __IDLE__ USART IDLE Frame Transmit state. + * @retval SET (__IDLE__ is valid) or RESET (__IDLE__ is invalid) + */ +#define IS_USART_IDLE_FRAME_TRANSMIT(__IDLE__) (((__IDLE__) == USART_IDLE_FRAME_ENABLE) ||\ + ((__IDLE__) == USART_IDLE_FRAME_DISABLE)) + +/** + * @brief Ensure that USART Trigger source selection is valid. + * @param __SOURCE__ USART Trigger source selection. + * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid) + */ +#define IS_USART_TRIGGER_SELECTION(__SOURCE__) ((__SOURCE__) <= 11U) + +/** + * @brief Ensure that the number of transferred data is valid. + * @param __SOURCE__ USART TX data size. + * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid) + */ +#define IS_USART_TX_DATA_SIZE(__SOURCE__) ((__SOURCE__) <= 0xFFFFU) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup USARTEx_Exported_Functions_Group1 + * @{ + */ + +/* IO operation functions *****************************************************/ +void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart); +void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart); + +/** + * @} + */ + +/** @addtogroup USARTEx_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig); +HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold); +HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold); +HAL_StatusTypeDef HAL_USARTEx_SetConfigAutonomousMode(USART_HandleTypeDef *husart, + const USART_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_USARTEx_GetConfigAutonomousMode(const USART_HandleTypeDef *husart, + USART_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_USARTEx_ClearConfigAutonomousMode(USART_HandleTypeDef *husart); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_USART_EX_H */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_bus.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_bus.h new file mode 100644 index 000000000..957512d07 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_bus.h @@ -0,0 +1,3223 @@ +/** + ****************************************************************************** + * @file stm32u5xx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB , APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB , APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_LL_BUS_H +#define STM32U5xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx.h" + +/** @addtogroup STM32U5xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_AHB1_GRP1_PERIPH_GPDMA1 RCC_AHB1ENR_GPDMA1EN +#define LL_AHB1_GRP1_PERIPH_CORDIC RCC_AHB1ENR_CORDICEN +#define LL_AHB1_GRP1_PERIPH_FMAC RCC_AHB1ENR_FMACEN +#define LL_AHB1_GRP1_PERIPH_MDF1 RCC_AHB1ENR_MDF1EN +#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN +#if defined(JPEG) +#define LL_AHB1_GRP1_PERIPH_JPEG RCC_AHB1ENR_JPEGEN +#endif /* defined(JPEG) */ +#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN +#define LL_AHB1_GRP1_PERIPH_RAMCFG RCC_AHB1ENR_RAMCFGEN +#if defined(DMA2D) +#define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN +#endif /* DMA2D */ +#if defined(GFXMMU) +#define LL_AHB1_GRP1_PERIPH_GFXMMU RCC_AHB1ENR_GFXMMUEN +#endif /* defined(GFXMMU) */ +#if defined(GPU2D) +#define LL_AHB1_GRP1_PERIPH_GPU2D RCC_AHB1ENR_GPU2DEN +#endif /* defined(GPU2D) */ +#if defined(DCACHE2) +#define LL_AHB1_GRP1_PERIPH_DCACHE2 RCC_AHB1ENR_DCACHE2EN +#endif /* defined(DCACHE2) */ +#define LL_AHB1_GRP1_PERIPH_GTZC1 RCC_AHB1ENR_GTZC1EN +#define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN +#define LL_AHB1_GRP1_PERIPH_ICACHE1 RCC_AHB1SMENR_ICACHESMEN +#define LL_AHB1_GRP1_PERIPH_DCACHE1 RCC_AHB1ENR_DCACHE1EN +#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1ENR_SRAM1EN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + * @{ + */ +#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR1_GPIOAEN +#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR1_GPIOBEN +#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR1_GPIOCEN +#define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR1_GPIODEN +#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR1_GPIOEEN +#if defined(GPIOF) +#define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR1_GPIOFEN +#endif /* GPIOF */ +#define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR1_GPIOGEN +#define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR1_GPIOHEN +#if defined (GPIOI) +#define LL_AHB2_GRP1_PERIPH_GPIOI RCC_AHB2ENR1_GPIOIEN +#endif /* GPIOI */ +#if defined (GPIOJ) +#define LL_AHB2_GRP1_PERIPH_GPIOJ RCC_AHB2ENR1_GPIOJEN +#endif /* defined (GPIOJ) */ +#define LL_AHB2_GRP1_PERIPH_ADC12 RCC_AHB2ENR1_ADC12EN +#define LL_AHB2_GRP1_PERIPH_DCMI_PSSI RCC_AHB2ENR1_DCMI_PSSIEN +#if defined(USB_OTG_FS) +#define LL_AHB2_GRP1_PERIPH_OTG_FS RCC_AHB2ENR1_OTGEN +/* Legacy define */ +#define LL_AHB2_GRP1_PERIPH_USBFS LL_AHB2_GRP1_PERIPH_OTG_FS +#elif defined(USB_OTG_HS) +#define LL_AHB2_GRP1_PERIPH_OTG_HS RCC_AHB2ENR1_OTGEN +/* Legacy define */ +#define LL_AHB2_GRP1_PERIPH_USBHS LL_AHB2_GRP1_PERIPH_OTG_HS +#endif /* defined(USB_OTG_HS) */ +#if defined(RCC_AHB2ENR1_USBPHYCEN) +#define LL_AHB2_GRP1_PERIPH_USBPHY RCC_AHB2ENR1_USBPHYCEN +#endif /* defined(RCC_AHB2ENR1_USBPHYCEN) */ +#if defined(AES) +#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR1_AESEN +#endif /* AES */ +#if defined(HASH) +#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR1_HASHEN +#endif /* HASH */ +#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR1_RNGEN +#define LL_AHB2_GRP1_PERIPH_PKA RCC_AHB2ENR1_PKAEN +#if defined(SAES) +#define LL_AHB2_GRP1_PERIPH_SAES RCC_AHB2ENR1_SAESEN +#endif /* SAES */ +#if defined(OCTOSPIM) +#define LL_AHB2_GRP1_PERIPH_OCTOSPIM RCC_AHB2ENR1_OCTOSPIMEN +#endif /* OCTOSPIM */ +#define LL_AHB2_GRP1_PERIPH_OTFDEC1 RCC_AHB2ENR1_OTFDEC1EN +#if defined (OTFDEC2) +#define LL_AHB2_GRP1_PERIPH_OTFDEC2 RCC_AHB2ENR1_OTFDEC2EN +#endif /* OTFDEC2 */ +#define LL_AHB2_GRP1_PERIPH_SDMMC1 RCC_AHB2ENR1_SDMMC1EN +#if defined(SDMMC2) +#define LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR1_SDMMC2EN +#endif /* SDMMC2 */ +#define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2ENR1_SRAM2EN +#if defined(SRAM3_BASE) +#define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2ENR1_SRAM3EN +#endif /* SRAM3_BASE */ + +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH + * @{ + */ +#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_AHB3_GRP1_PERIPH_LPGPIO1 RCC_AHB3ENR_LPGPIO1EN +#define LL_AHB3_GRP1_PERIPH_PWR RCC_AHB3ENR_PWREN +#define LL_AHB3_GRP1_PERIPH_ADC4 RCC_AHB3ENR_ADC4EN +#define LL_AHB3_GRP1_PERIPH_DAC1 RCC_AHB3ENR_DAC1EN +#define LL_AHB3_GRP1_PERIPH_LPDMA1 RCC_AHB3ENR_LPDMA1EN +#define LL_AHB3_GRP1_PERIPH_ADF1 RCC_AHB3ENR_ADF1EN +#define LL_AHB3_GRP1_PERIPH_GTZC2 RCC_AHB3ENR_GTZC2EN +#define LL_AHB3_GRP1_PERIPH_SRAM4 RCC_AHB3ENR_SRAM4EN + +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB2_GRP2_PERIPH AHB2 GRP2 PERIPH + * @{ + */ +#define LL_AHB2_GRP2_PERIPH_ALL 0xFFFFFFFFU +#if defined(FMC_BASE) +#define LL_AHB2_GRP2_PERIPH_FSMC RCC_AHB2ENR2_FSMCEN +#endif /* FMC_BASE */ +#define LL_AHB2_GRP2_PERIPH_OCTOSPI1 RCC_AHB2ENR2_OCTOSPI1EN +#if defined(OCTOSPI2) +#define LL_AHB2_GRP2_PERIPH_OCTOSPI2 RCC_AHB2ENR2_OCTOSPI2EN +#endif /* OCTOSPI2 */ +#if defined(HSPI1) +#define LL_AHB2_GRP2_PERIPH_HSPI1 RCC_AHB2ENR2_HSPI1EN +#endif /* defined(HSPI1) */ +#if defined(SRAM6_BASE) +#define LL_AHB2_GRP2_PERIPH_SRAM6 RCC_AHB2ENR2_SRAM6EN +#endif /* SRAM6_BASE */ +#if defined(SRAM5_BASE) +#define LL_AHB2_GRP2_PERIPH_SRAM5 RCC_AHB2ENR2_SRAM5EN +#endif /* SRAM5_BASE */ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN +#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN +#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN +#if defined(USART2) +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN +#endif /* USART2 */ +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN +#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN +#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN +#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN +#if defined(USART6) +#define LL_APB1_GRP1_PERIPH_USART6 RCC_APB1ENR1_USART6EN +#endif /* defined(USART6) */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH + * @{ + */ +#define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN +#define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN +#define LL_APB1_GRP2_PERIPH_FDCAN1 RCC_APB1ENR2_FDCAN1EN +#if defined(UCPD1) +#define LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1ENR2_UCPD1EN +#endif /* UCPD1 */ +#if defined(I2C5) +#define LL_APB1_GRP2_PERIPH_I2C5 RCC_APB1ENR2_I2C5EN +#endif /* defined(I2C5) */ +#if defined(I2C6) +#define LL_APB1_GRP2_PERIPH_I2C6 RCC_APB1ENR2_I2C6EN +#endif /* defined(I2C6) */ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN +#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN +#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN +#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN +#if defined(SAI2) +#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN +#endif /* SAI2 */ +#if defined(USB_DRD_FS) +#define LL_APB2_GRP1_PERIPH_USB_FS RCC_APB2ENR_USBEN +#endif /* USB_DRD_FS */ +#if defined(GFXTIM) +#define LL_APB2_GRP1_PERIPH_GFXTIM RCC_APB2ENR_GFXTIMEN +#endif /* GFXTIM */ +#if defined(LTDC) +#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN +#endif /* defined(LTDC) */ +#if defined(DSI) +#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIHOSTEN +#endif /* defined(DSI) */ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH + * @{ + */ +#define LL_APB3_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB3_GRP1_PERIPH_SYSCFG RCC_APB3ENR_SYSCFGEN +#define LL_APB3_GRP1_PERIPH_SPI3 RCC_APB3ENR_SPI3EN +#define LL_APB3_GRP1_PERIPH_LPUART1 RCC_APB3ENR_LPUART1EN +#define LL_APB3_GRP1_PERIPH_I2C3 RCC_APB3ENR_I2C3EN +#define LL_APB3_GRP1_PERIPH_LPTIM1 RCC_APB3ENR_LPTIM1EN +#define LL_APB3_GRP1_PERIPH_LPTIM3 RCC_APB3ENR_LPTIM3EN +#define LL_APB3_GRP1_PERIPH_LPTIM4 RCC_APB3ENR_LPTIM4EN +#define LL_APB3_GRP1_PERIPH_OPAMP RCC_APB3ENR_OPAMPEN +#define LL_APB3_GRP1_PERIPH_COMP RCC_APB3ENR_COMPEN +#define LL_APB3_GRP1_PERIPH_VREF RCC_APB3ENR_VREFEN +#define LL_APB3_GRP1_PERIPH_RTCAPB RCC_APB3ENR_RTCAPBEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_SRDAMR_GRP1_PERIPH SRDAMR GRP1 PERIPH + * @{ + */ +#define LL_SRDAMR_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_SRDAMR_GRP1_PERIPH_SPI3 RCC_SRDAMR_SPI3AMEN +#define LL_SRDAMR_GRP1_PERIPH_LPUART1 RCC_SRDAMR_LPUART1AMEN +#define LL_SRDAMR_GRP1_PERIPH_I2C3 RCC_SRDAMR_I2C3AMEN +#define LL_SRDAMR_GRP1_PERIPH_LPTIM1 RCC_SRDAMR_LPTIM1AMEN +#define LL_SRDAMR_GRP1_PERIPH_LPTIM3 RCC_SRDAMR_LPTIM3AMEN +#define LL_SRDAMR_GRP1_PERIPH_LPTIM4 RCC_SRDAMR_LPTIM4AMEN +#define LL_SRDAMR_GRP1_PERIPH_OPAMP RCC_SRDAMR_OPAMPAMEN +#define LL_SRDAMR_GRP1_PERIPH_COMP RCC_SRDAMR_COMPAMEN +#define LL_SRDAMR_GRP1_PERIPH_VREF RCC_SRDAMR_VREFAMEN +#define LL_SRDAMR_GRP1_PERIPH_RTCAPB RCC_SRDAMR_RTCAPBAMEN +#define LL_SRDAMR_GRP1_PERIPH_ADC4 RCC_SRDAMR_ADC4AMEN +#define LL_SRDAMR_GRP1_PERIPH_LPGPIO1 RCC_SRDAMR_LPGPIO1AMEN +#define LL_SRDAMR_GRP1_PERIPH_DAC1 RCC_SRDAMR_DAC1AMEN +#define LL_SRDAMR_GRP1_PERIPH_LPDMA1 RCC_SRDAMR_LPDMA1AMEN +#define LL_SRDAMR_GRP1_PERIPH_ADF1 RCC_SRDAMR_ADF1AMEN +#define LL_SRDAMR_GRP1_PERIPH_SRAM4 RCC_SRDAMR_SRAM4AMEN +/** + * @} + */ +/** @defgroup LL_RCC_Aliased_Constants LL RCC Aliased Constants maintained for legacy purpose + * @{ + */ +#define LL_AHB2_GRP1_PERIPH_ADC1 LL_AHB2_GRP1_PERIPH_ADC12 +#define LL_SRDAMR_GRP1_PERIPH_SPI3AMEN LL_SRDAMR_GRP1_PERIPH_SPI3 +#define LL_SRDAMR_GRP1_PERIPH_LPUART1AMEN LL_SRDAMR_GRP1_PERIPH_LPUART1 +#define LL_SRDAMR_GRP1_PERIPH_I2C3AMEN LL_SRDAMR_GRP1_PERIPH_I2C3 +#define LL_SRDAMR_GRP1_PERIPH_LPTIM1AMEN LL_SRDAMR_GRP1_PERIPH_LPTIM1 +#define LL_SRDAMR_GRP1_PERIPH_LPTIM3AMEN LL_SRDAMR_GRP1_PERIPH_LPTIM3 +#define LL_SRDAMR_GRP1_PERIPH_LPTIM4AMEN LL_SRDAMR_GRP1_PERIPH_LPTIM4 +#define LL_SRDAMR_GRP1_PERIPH_OPAMPAMEN LL_SRDAMR_GRP1_PERIPH_OPAMP +#define LL_SRDAMR_GRP1_PERIPH_COMPAMEN LL_SRDAMR_GRP1_PERIPH_COMP +#define LL_SRDAMR_GRP1_PERIPH_VREFAMEN LL_SRDAMR_GRP1_PERIPH_VREF +#define LL_SRDAMR_GRP1_PERIPH_RTCAPBAMEN LL_SRDAMR_GRP1_PERIPH_RTCAPB +#define LL_SRDAMR_GRP1_PERIPH_ADC4AMEN LL_SRDAMR_GRP1_PERIPH_ADC4 +#define LL_SRDAMR_GRP1_PERIPH_LPGPIO1AMEN LL_SRDAMR_GRP1_PERIPH_LPGPIO1 +#define LL_SRDAMR_GRP1_PERIPH_DAC1AMEN LL_SRDAMR_GRP1_PERIPH_DAC1 +#define LL_SRDAMR_GRP1_PERIPH_LPDMA1AMEN LL_SRDAMR_GRP1_PERIPH_LPDMA1 +#define LL_SRDAMR_GRP1_PERIPH_ADF1AMEN LL_SRDAMR_GRP1_PERIPH_ADF1 +#define LL_SRDAMR_GRP1_PERIPH_SRAM4AMEN LL_SRDAMR_GRP1_PERIPH_SRAM4 +/** + * @} + */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 bus clock. + * @rmtoll CFGR2 AHB1DIS LL_AHB1_GRP1_EnableBusClock + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableBusClock(void) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); + (void)(tmpreg); +} + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR CORDICEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR FMACEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR MDF1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR JPEGEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR RAMCFGEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPU2DEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DCACHE2EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GTZC1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DCACHE1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR SRAM1EN LL_AHB1_GRP1_EnableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR CORDICEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR FMACEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR MDF1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR JPEGEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR RAMCFGEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPU2DEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DCACHE2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GTZC1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DCACHEEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR SRAM1EN LL_AHB1_GRP1_IsEnabledClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB1 bus clock. + * @note except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1. + * @rmtoll CFGR2 AHB1DIS LL_AHB1_GRP1_DisableBusClock + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableBusClock(void) +{ + SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR CORDICEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR FMACEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR MDF1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR JPEGEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR RAMCFGEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPU2DEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DCACHE2EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GTZC1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DCACHEEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR SRAM1EN LL_AHB1_GRP1_DisableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1ENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR CORDICRSTR LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR FMACRSTR LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR MDF1RSTR LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR JPEGRSTR LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA2DRSTR LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GFXMMURSTR LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPU2DRSTR LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DCACHE2RSTR LL_AHB1_GRP1_ForceReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR CORDICRSTR LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR FMACRSTR LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR MDF1RSTR LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR JPEGRSTR LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA2DRSTR LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GFXMMURSTR LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPU2DRSTR LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DCACHE2RSTR LL_AHB1_GRP1_ReleaseReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR CORDICSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR FMACSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR MDF1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR JPEGSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR GPU2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR DCACHE2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR BKPSRAMSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR ICACHESMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR DCACHESMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clocks in Sleep and Stop modes is enabled or not + * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR CORDICSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR FMACSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR MDF1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR CRCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR JPEGSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR TSCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR GPU2DSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR DCACHE2SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR BKPSRAMSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR ICACHESMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR DCACHESMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB1SMENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR CORDICSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR FMACSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR MDF1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR JPEGSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR GPU2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR DCACHE2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR BKPSRAMSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR ICACHESMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR DCACHESMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1SMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + * @{ + */ + +/** + * @brief Enable AHB2_1 bus clock. + * @rmtoll CFGR2 AHB2DIS1 LL_AHB2_GRP1_EnableBusClock + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableBusClock(void) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); + (void)(tmpreg); +} + +/** + * @brief Enable AHB2 peripherals clock. + * @rmtoll AHB2ENR1 GPIOAEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 GPIOBEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 GPIOCEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 GPIODEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 GPIOEEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 GPIOFEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 GPIOGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 GPIOHEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 GPIOIEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 GPIOJEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 ADC12EN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 DCMI_PSSIEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 OTGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 USBPHYCEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 AESEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 HASHEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 RNGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 PKAEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 SAESEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 OCTOSPIMEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 OTFDEC1EN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 OTFDEC2EN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 SDMMC1EN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 SDMMC2EN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 SRAM2EN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 SRAM3EN LL_AHB2_GRP1_EnableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2ENR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2ENR1, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR1 GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 GPIODEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 GPIOIEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 GPIOJEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 ADC12EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 DCMI_PSSIEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 OTGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 USBPHYCEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 AESEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 HASHEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 RNGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 PKAEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 SAESEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 OCTOSPIMEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 OTFDEC1EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 OTFDEC2EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 SDMMC1EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 SDMMC2EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 SRAM2EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 SRAM3EN LL_AHB2_GRP1_IsEnabledClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB2ENR1, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB2_1 bus clock. + * @note except for SRAM2 and SRAM3. + * @rmtoll CFGR2 AHB2DIS1 LL_AHB2_GRP1_DisableBusClock + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableBusClock(void) +{ + SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); +} + +/** + * @brief Disable AHB2 peripherals clock. + * @rmtoll AHB2ENR1 GPIOAEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 GPIOBEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 GPIOCEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 GPIODEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 GPIOEEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 GPIOFEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 GPIOGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 GPIOHEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 GPIOIEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 GPIOJEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 ADC12EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 DCMI_PSSIEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 OTGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 USBPHYCEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 AESEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 HASHEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 RNGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 PKAEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 SAESEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 OSPIMEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 OTFDEC1EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 OTFDEC2EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 SDMMC1EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 SDMMC2EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 SRAM2EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 SRAM3EN LL_AHB2_GRP1_DisableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2ENR1, Periphs); +} + +/** + * @brief Force AHB2 peripherals reset. + * @rmtoll AHB2RSTR1 GPIOARST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 GPIOBRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 GPIOCRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 GPIODRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 GPIOERST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 GPIOFRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 GPIOGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 GPIOHRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 GPIOIRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 GPIOJRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 ADC12RST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 DCMI_PSSIRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 OTGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 USBPHYCRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 AESRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 HASHRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 RNGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 PKARST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 SAESRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 OCTOSPIMRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 OTFDEC1RST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 OTFDEC2RST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 SDMMC1RST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 SDMMC2RST LL_AHB2_GRP1_ForceReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB2RSTR1, Periphs); +} + +/** + * @brief Release AHB2 peripherals reset. + * @rmtoll AHB2RSTR1 GPIOARST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 GPIOBRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 GPIOCRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 GPIODRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 GPIOERST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 GPIOFRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 GPIOGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 GPIOHRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 GPIOIRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 GPIOJRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 ADC12RST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 DCMI_PSSIRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 OTGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 USBPHYCRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 AESRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 HASHRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 RNGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 PKARST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 SAESRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 OCTOSPIMRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 OTFDEC1RST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 OTFDEC2RST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 SDMMC1RST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 SDMMC2RST LL_AHB2_GRP1_ReleaseReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2RSTR1, Periphs); +} + +/** + * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB2SMENR1 GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 GPIOJSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 ADC12SMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 DCMI_PSSISMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 OTGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2ENR1 USBPHYCEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 PKASMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 SAESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 OSPIMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 OTFDEC1SMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 OTFDEC2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 SDMMC2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2SMENR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2SMENR1, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clocks in Sleep and Stop modes is enabled or not + * @rmtoll AHB2SMENR1 GPIOASMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 GPIOBSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 GPIOCSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 GPIODSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 GPIOESMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 GPIOFSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 GPIOGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 GPIOISMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 GPIOJSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 ADC12SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 DCMI_PSSISMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 OTGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 USBPHYCMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 AESSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 HASHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 RNGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 PKASMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 SAESSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 OSPIMSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 OTFDEC1SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 OTFDEC2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 SDMMC1SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 SDMMC2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 SRAM2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 SRAM3SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB2SMENR1, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB2SMENR1 GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 GPIOJSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 ADC12SMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 DCMI_PSSISMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 OTGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 USBPHYCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 PKASMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 SAESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 OSPIMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 OTFDEC1SMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 OTFDEC2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 SDMMC2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 SRAM3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2SMENR1, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB3 AHB3 + * @{ + */ + +/** + * @brief Enable AHB3 bus clock. + * @rmtoll CFGR2 AHB3DIS LL_AHB3_GRP1_EnableBusClock + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_EnableBusClock(void) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); + tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); + (void)(tmpreg); +} + +/** + * @brief Enable AHB3 peripherals clock. + * @rmtoll AHB3ENR LPGPIO1EN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR PWREN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR ADC4EN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR DAC1EN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR LPDMA1EN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR ADF1EN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR GTZC2EN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR SRAM4EN LL_AHB3_GRP1_EnableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 + * @arg @ref LL_AHB3_GRP1_PERIPH_PWR + * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4 + * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1 + * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2 + * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4 + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB3 peripheral clock is enabled or not + * @rmtoll AHB3ENR LPGPIO1EN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR PWREN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR ADC4EN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR DAC1EN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR LPDMA1EN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR ADF1EN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR GTZC2EN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR SRAM4EN LL_AHB3_GRP1_IsEnabledClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 + * @arg @ref LL_AHB3_GRP1_PERIPH_PWR + * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4 + * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1 + * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2 + * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4 + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB3 bus clock. + * @rmtoll CFGR2 AHB3DIS LL_AHB3_GRP1_DisableBusClock + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_DisableBusClock(void) +{ + SET_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); +} + +/** + * @brief Disable AHB3 peripherals clock. + * @rmtoll AHB3ENR LPGPIO1EN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR PWREN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR ADC4EN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR DAC1EN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR LPDMA1EN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR ADF1EN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR GTZC2EN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR SRAM4EN LL_AHB3_GRP1_DisableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 + * @arg @ref LL_AHB3_GRP1_PERIPH_PWR + * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4 + * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1 + * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2 + * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4 + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3ENR, Periphs); +} + +/** + * @brief Force AHB3 peripherals reset. + * @rmtoll AHB3RSTR LPGPIO1RST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR PWRRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR ADC4RST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR DAC1RST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR LPDMA1RST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR ADF1RST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR GTZC2RST LL_AHB3_GRP1_ForceReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 + * @arg @ref LL_AHB3_GRP1_PERIPH_PWR + * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4 + * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1 + * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2 + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Release AHB3 peripherals reset. + * @rmtoll AHB3RSTR LPGPIO1RST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR PWRRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR ADC4RST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR DAC1RST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR LPDMA1RST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR ADF1RST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR GTZC2RST LL_AHB3_GRP1_ReleaseReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 + * @arg @ref LL_AHB3_GRP1_PERIPH_PWR + * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4 + * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1 + * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2 + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB3SMENR LPGPIO1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n + * AHB3SMENR PWRSMEN LL_AHB3_GRP1_EnableClockStopSleep\n + * AHB3SMENR ADC4SMEN LL_AHB3_GRP1_EnableClockStopSleep\n + * AHB3SMENR DAC1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n + * AHB3SMENR LPDMA1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n + * AHB3SMENR ADF1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n + * AHB3SMENR GTZC2SMEN LL_AHB3_GRP1_EnableClockStopSleep\n + * AHB3SMENR SRAM4SMEN LL_AHB3_GRP1_EnableClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 + * @arg @ref LL_AHB3_GRP1_PERIPH_PWR + * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4 + * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1 + * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2 + * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4 + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB3 peripheral clocks in Sleep and Stop modes is enabled or not + * @rmtoll AHB3SMENR LPGPIO1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n + * AHB3SMENR PWRSMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n + * AHB3SMENR ADC4SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n + * AHB3SMENR DAC1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n + * AHB3SMENR LPDMA1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n + * AHB3SMENR ADF1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n + * AHB3SMENR GTZC2SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n + * AHB3SMENR SRAM4SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 + * @arg @ref LL_AHB3_GRP1_PERIPH_PWR + * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4 + * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1 + * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2 + * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4 + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB3SMENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB3SMENR LPGPIO1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n + * AHB3SMENR PWRSMEN LL_AHB3_GRP1_DisableClockStopSleep\n + * AHB3SMENR ADC4SMEN LL_AHB3_GRP1_DisableClockStopSleep\n + * AHB3SMENR DAC1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n + * AHB3SMENR LPDMA1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n + * AHB3SMENR ADF1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n + * AHB3SMENR GTZC2SMEN LL_AHB3_GRP1_DisableClockStopSleep\n + * AHB3SMENR SRAM4SMEN LL_AHB3_GRP1_DisableClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 + * @arg @ref LL_AHB3_GRP1_PERIPH_PWR + * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4 + * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1 + * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2 + * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4 + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3SMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB2_GRP2_PERIPH AHB2 GRP2 PERIPH + * @{ + */ + +/** + * @brief Enable AHB2_2 bus clock. + * @rmtoll CFGR2 AHB2DIS2 LL_AHB2_GRP2_EnableBusClock + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP2_EnableBusClock(void) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); + (void)(tmpreg); +} + +/** + * @brief Enable AHB2 peripherals clock. + * @rmtoll AHB2ENR2 FSMCEN LL_AHB2_GRP2_EnableClock\n + * AHB2ENR2 OCTOSPI1EN LL_AHB2_GRP2_EnableClock\n + * AHB2ENR2 OCTOSPI2EN LL_AHB2_GRP2_EnableClock\n + * AHB2ENR2 HSPI1EN LL_AHB2_GRP2_EnableClock\n + * AHB2ENR2 SRAM6EN LL_AHB2_GRP2_EnableClock\n + * AHB2ENR2 SRAM5EN LL_AHB2_GRP2_EnableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP2_PERIPH_ALL + * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*) + * + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2ENR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2ENR2, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR2 FSMCEN LL_AHB2_GRP2_IsEnabledClock\n + * AHB2ENR2 OCTOSPI1EN LL_AHB2_GRP2_IsEnabledClock\n + * AHB2ENR2 OCTOSPI2EN LL_AHB2_GRP2_IsEnabledClock\n + * AHB2ENR2 HSPI1EN LL_AHB2_GRP2_IsEnabledClock\n + * AHB2ENR2 SRAM6EN LL_AHB2_GRP2_DisableClock\n + * AHB2ENR2 SRAM5EN LL_AHB2_GRP2_IsEnabledClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP2_PERIPH_ALL + * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*) + * + * (*) value not defined in all devices. + * @retval None + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB2_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB2ENR2, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB2_2 bus clock. + * @rmtoll CFGR2 AHB2DIS2 LL_AHB2_GRP2_DisableBusClock + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP2_DisableBusClock(void) +{ + SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); +} + +/** + * @brief Disable AHB2 peripherals clock. + * @rmtoll AHB2ENR2 FSMCEN LL_AHB2_GRP2_DisableClock\n + * AHB2ENR2 OCTOSPI1EN LL_AHB2_GRP2_DisableClock\n + * AHB2ENR2 OCTOSPI2EN LL_AHB2_GRP2_DisableClock\n + * AHB2ENR2 HSPI1EN LL_AHB2_GRP2_DisableClock\n + * AHB2ENR2 SRAM6EN LL_AHB2_GRP2_DisableClock\n + * AHB2ENR2 SRAM5EN LL_AHB2_GRP2_DisableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP2_PERIPH_ALL + * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2ENR2, Periphs); +} + +/** + * @brief Force AHB2 peripherals reset. + * @rmtoll AHB2RSTR2 FSMCRST LL_AHB2_GRP2_ForceReset\n + * AHB2RSTR2 OCTOSPI1RST LL_AHB2_GRP2_ForceReset\n + * AHB2RSTR2 OCTOSPI2RST LL_AHB2_GRP2_ForceReset\n + * AHB2RSTR2 HSPI1RST LL_AHB2_GRP2_ForceReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP2_PERIPH_ALL + * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP2_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB2RSTR2, Periphs); +} + +/** + * @brief Release AHB2 peripherals reset. + * @rmtoll AHB2RSTR2 FSMCRST LL_AHB2_GRP2_ReleaseReset\n + * AHB2RSTR2 OCTOSPI1RST LL_AHB2_GRP2_ReleaseReset\n + * AHB2RSTR2 OCTOSPI2RST LL_AHB2_GRP2_ReleaseReset\n + * AHB2RSTR2 HSPI1RST LL_AHB2_GRP2_ReleaseReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP2_PERIPH_ALL + * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP2_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2RSTR2, Periphs); +} + +/** + * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB2SMENR2 FSMCSMEN LL_AHB2_GRP2_EnableClockStopSleep\n + * AHB2SMENR2 OCTOSPI1SMEN LL_AHB2_GRP2_EnableClockStopSleep\n + * AHB2SMENR2 OCTOSPI2SMEN LL_AHB2_GRP2_EnableClockStopSleep\n + * AHB2SMENR2 HSPI1SMEN LL_AHB2_GRP2_EnableClockStopSleep\n + * AHB2SMENR2 SRAM6SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n + * AHB2SMENR2 SRAM5SMEN LL_AHB2_GRP2_EnableClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP2_PERIPH_ALL + * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP2_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2SMENR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2SMENR2, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clocks in Sleep and Stop modes is enabled or not + * @rmtoll AHB2SMENR2 FSMCSMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n + * AHB2SMENR2 OCTOSPI1SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n + * AHB2SMENR2 OCTOSPI2SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n + * AHB2SMENR2 HSPI1SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n + * AHB2SMENR2 SRAM6SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n + * AHB2SMENR2 SRAM5SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP2_PERIPH_ALL + * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB2_GRP2_IsEnabledClockStopSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB2SMENR2, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB2SMENR2 FSMCSMEN LL_AHB2_GRP2_DisableClockStopSleep\n + * AHB2SMENR2 OCTOSPI1SMEN LL_AHB2_GRP2_DisableClockStopSleep\n + * AHB2SMENR2 OCTOSPI2SMEN LL_AHB2_GRP2_DisableClockStopSleep\n + * AHB2SMENR2 HSPI1SMEN LL_AHB2_GRP2_DisableClockStopSleep\n + * AHB2SMENR2 SRAM6SMEN LL_AHB2_GRP2_DisableClockStopSleep\n + * AHB2SMENR2 SRAM5SMEN LL_AHB2_GRP2_DisableClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP2_PERIPH_ALL + * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP2_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2SMENR2, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable APB1 bus clock. + * @rmtoll CFGR2 APB1DIS LL_APB1_GRP1_EnableBusClock + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableBusClock(void) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); + (void)(tmpreg); +} + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 USART6N LL_APB1_GRP1_EnableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); + (void)tmpreg; +} + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n + * APB1ENR2 I2C5EN LL_APB1_GRP2_EnableClock\n + * APB1ENR2 I2C6EN LL_APB1_GRP2_EnableClock\n + * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock\n + * APB1ENR2 FDCAN1EN LL_APB1_GRP2_EnableClock\n + * APB1ENR2 UCPD1EN LL_APB1_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR2, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 USART6EN LL_APB1_GRP1_IsEnabledClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n + * APB1ENR2 I2C5EN LL_APB1_GRP2_IsEnabledClock\n + * APB1ENR2 I2C6EN LL_APB1_GRP2_IsEnabledClock\n + * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock\n + * APB1ENR2 FDCAN1EN LL_APB1_GRP2_IsEnabledClock\n + * APB1ENR2 UCPD1EN LL_APB1_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 bus clock. + * @note except for IWDG. + * @rmtoll CFGR2 APB1DIS LL_APB1_GRP1_DisableBusClock + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableBusClock(void) +{ + SET_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 USART6EN LL_APB1_GRP1_DisableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR1, Periphs); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n + * APB1ENR2 I2C5EN LL_APB1_GRP2_DisableClock\n + * APB1ENR2 I2C6EN LL_APB1_GRP2_DisableClock\n + * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock\n + * APB1ENR2 FDCAN1EN LL_APB1_GRP2_DisableClock\n + * APB1ENR2 UCPD1EN LL_APB1_GRP2_DisableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR2, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 USART6RST LL_APB1_GRP1_ForceReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR1, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTR2 I2C4RST LL_APB1_GRP2_DisableClock\n + * APB1RSTR2 I2C5RST LL_APB1_GRP2_DisableClock\n + * APB1RSTR2 I2C6RST LL_APB1_GRP2_DisableClock\n + * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_DisableClock\n + * APB1RSTR2 FDCAN1RST LL_APB1_GRP2_DisableClock\n + * APB1RSTR2 UCPDRST LL_APB1_GRP2_DisableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR2, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 USART6RST LL_APB1_GRP1_ReleaseReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR1, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n + * APB1RSTR2 I2C5RST LL_APB1_GRP2_ReleaseReset\n + * APB1RSTR2 I2C6RST LL_APB1_GRP2_ReleaseReset\n + * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset\n + * APB1RSTR2 FDCAN1RST LL_APB1_GRP2_ReleaseReset\n + * APB1RSTR2 UCPD1RST LL_APB1_GRP2_ReleaseReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR2, Periphs); +} + +/** + * @brief Enable APB1 peripheral clocks in Sleep and Stop modes + * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 USART6SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1SMENR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not + * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * APB1SMENR1 USART2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * APB1SMENR1 USART3SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * APB1SMENR1 UART4SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * APB1SMENR1 UART5SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * APB1SMENR1 CRSSMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * APB1SMENR1 USART6SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1SMENR1, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 peripheral clocks in Sleep and Stop modes + * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 USART6SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1SMENR1, Periphs); +} + +/** + * @brief Enable APB1 peripheral clocks in Sleep and Stop modes + * @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n + * APB1SMENR2 I2C5SMEN LL_APB1_GRP2_EnableClockStopSleep\n + * APB1SMENR2 I2C6SMEN LL_APB1_GRP2_EnableClockStopSleep\n + * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep\n + * APB1SMENR2 FDCAN1SMEN LL_APB1_GRP2_EnableClockStopSleep\n + * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_EnableClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1SMENR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not + * @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n + * APB1SMENR2 I2C5SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n + * APB1SMENR2 I2C6SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n + * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n + * APB1SMENR2 FDCAN1SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n + * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_IsEnabledClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockStopSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1SMENR2, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 peripheral clocks in Sleep and Stop modes + * @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n + * APB1SMENR2 I2C5SMEN LL_APB1_GRP2_DisableClockStopSleep\n + * APB1SMENR2 I2C6SMEN LL_APB1_GRP2_DisableClockStopSleep\n + * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep\n + * APB1SMENR2 FDCAN1SMEN LL_APB1_GRP2_DisableClockStopSleep\n + * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_DisableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1SMENR2, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable APB2 bus clock. + * @rmtoll CFGR2 APB2DIS LL_APB2_GRP1_EnableBusClock + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableBusClock(void) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); + (void)(tmpreg); +} + +/** + * @brief Enable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USBEN LL_APB2_GRP1_EnableClock\n + * APB2ENR GFXTIMEN LL_APB2_GRP1_EnableClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n + * APB2ENR DSIHOSTEN LL_APB2_GRP1_EnableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USBEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR GFXTIMEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DSIHOSTEN LL_APB2_GRP1_IsEnabledClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB2 bus clock. + * @rmtoll CFGR2 APB2DIS LL_APB2_GRP1_DisableBusClock + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableBusClock(void) +{ + SET_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USBEN LL_APB2_GRP1_DisableClock\n + * APB2ENR GFXTIMEN LL_APB2_GRP1_DisableClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n + * APB2ENR DSIHOSTEN LL_APB2_GRP1_DisableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USBRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR GFXTIMRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR DSIHOSTRST LL_APB2_GRP1_ForceReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USBRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR GFXTIMRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR DSIHOSTRST LL_APB2_GRP1_ReleaseReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Enable APB2 peripheral clocks in Sleep and Stop modes + * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR USBSMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR GFXTIMSMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR LTDCSMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR DSIHOSTSMEN LL_APB2_GRP1_EnableClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM(*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2SMENR, Periphs); + (void)tmpreg; +} + + +/** + * @brief Check if APB2 peripheral clocks in Sleep and Stop modes is enabled or not + * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * APB2SMENR SPI1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * APB2SMENR TIM8SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * APB2SMENR USART1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * APB2SMENR TIM15SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * APB2SMENR TIM16SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * APB2SMENR TIM17SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * APB2SMENR SAI1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * APB2SMENR SAI2SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * APB2SMENR USBSMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * APB2SMENR GFXTIMSMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * APB2SMENR LTDCSMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * APB2SMENR DSIHOSTSMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB2SMENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB2 peripheral clocks in Sleep and Stop modes + * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR USBSMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR GFXTIMSMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR LTDCSMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR DSIHOSTSMEN LL_APB2_GRP1_DisableClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2SMENR, Periphs); +} + +/** + * @} + */ + + +/** @defgroup BUS_LL_EF_APB3 APB3 + * @{ + */ + +/** + * @brief Enable APB3 bus clock. + * @rmtoll CFGR2 APB3DIS LL_APB3_GRP1_EnableBusClock + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_EnableBusClock(void) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); + tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); + (void)(tmpreg); +} + +/** + * @brief Enable APB3 peripherals clock. + * @rmtoll APB3ENR SYSCFGEN LL_APB3_GRP1_EnableClock\n + * APB3ENR SPI3EN LL_APB3_GRP1_EnableClock\n + * APB3ENR LPUART1EN LL_APB3_GRP1_EnableClock\n + * APB3ENR I2C3EN LL_APB3_GRP1_EnableClock\n + * APB3ENR LPTIM1EN LL_APB3_GRP1_EnableClock\n + * APB3ENR LPTIM3EN LL_APB3_GRP1_EnableClock\n + * APB3ENR LPTIM4EN LL_APB3_GRP1_EnableClock\n + * APB3ENR OPAMPEN LL_APB3_GRP1_EnableClock\n + * APB3ENR COMPEN LL_APB3_GRP1_EnableClock\n + * APB3ENR VREFEN LL_APB3_GRP1_EnableClock\n + * APB3ENR RTCAPBEN LL_APB3_GRP1_EnableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB3_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP + * @arg @ref LL_APB3_GRP1_PERIPH_COMP + * @arg @ref LL_APB3_GRP1_PERIPH_VREF + * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB3 peripheral clock is enabled or not + * @rmtoll APB3ENR SYSCFGEN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR SPI3EN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR LPUART1EN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR I2C3EN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR LPTIM1EN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR LPTIM3EN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR LPTIM4EN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR OPAMPEN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR COMPEN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR VREFEN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR RTCAPBEN LL_APB3_GRP1_IsEnabledClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB3_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP + * @arg @ref LL_APB3_GRP1_PERIPH_COMP + * @arg @ref LL_APB3_GRP1_PERIPH_VREF + * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB3 bus clock. + * @rmtoll CFGR2 APB3DIS LL_APB3_GRP1_DisableBusClock + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_DisableBusClock(void) +{ + SET_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB3ENR SYSCFGEN LL_APB3_GRP1_DisableClock\n + * APB3ENR SPI3EN LL_APB3_GRP1_DisableClock\n + * APB3ENR LPUART1EN LL_APB3_GRP1_DisableClock\n + * APB3ENR I2C3EN LL_APB3_GRP1_DisableClock\n + * APB3ENR LPTIM1EN LL_APB3_GRP1_DisableClock\n + * APB3ENR LPTIM3EN LL_APB3_GRP1_DisableClock\n + * APB3ENR LPTIM4EN LL_APB3_GRP1_DisableClock\n + * APB3ENR OPAMPEN LL_APB3_GRP1_DisableClock\n + * APB3ENR COMPEN LL_APB3_GRP1_DisableClock\n + * APB3ENR VREFEN LL_APB3_GRP1_DisableClock\n + * APB3ENR RTCAPBEN LL_APB3_GRP1_DisableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB3_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP + * @arg @ref LL_APB3_GRP1_PERIPH_COMP + * @arg @ref LL_APB3_GRP1_PERIPH_VREF + * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB3ENR, Periphs); +} + +/** + * @brief Force APB3 peripherals reset. + * @rmtoll APB3RSTR SYSCFGRST LL_APB3_GRP1_ForceReset\n + * APB3RSTR SPI3RST LL_APB3_GRP1_ForceReset\n + * APB3RSTR LPUART1RST LL_APB3_GRP1_ForceReset\n + * APB3RSTR I2C3RST LL_APB3_GRP1_ForceReset\n + * APB3RSTR LPTIM1RST LL_APB3_GRP1_ForceReset\n + * APB3RSTR LPTIM3RST LL_APB3_GRP1_ForceReset\n + * APB3RSTR LPTIM4RST LL_APB3_GRP1_ForceReset\n + * APB3RSTR OPAMPRST LL_APB3_GRP1_ForceReset\n + * APB3RSTR COMPRST LL_APB3_GRP1_ForceReset\n + * APB3RSTR VREFRST LL_APB3_GRP1_ForceReset\n + * APB3RSTR RTCAPBRST LL_APB3_GRP1_ForceReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB3_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP + * @arg @ref LL_APB3_GRP1_PERIPH_COMP + * @arg @ref LL_APB3_GRP1_PERIPH_VREF + * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB3RSTR, Periphs); +} + +/** + * @brief Release APB3 peripherals reset. + * @rmtoll APB3RSTR SYSCFGRST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR SPI3RST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR LPUART1RST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR I2C3RST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR LPTIM1RST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR LPTIM3RST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR LPTIM4RST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR OPAMPRST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR COMPRST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR VREFRST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR RTCAPBRST LL_APB3_GRP1_ReleaseReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB3_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP + * @arg @ref LL_APB3_GRP1_PERIPH_COMP + * @arg @ref LL_APB3_GRP1_PERIPH_VREF + * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB3RSTR, Periphs); +} + +/** + * @brief Enable APB3 peripheral clocks in Sleep and Stop modes + * @rmtoll APB3SMENR SYSCFGSMEN LL_APB3_GRP1_EnableClockStopSleep\n + * APB3SMENR SPI3SMEN LL_APB3_GRP1_EnableClockStopSleep\n + * APB3SMENR LPUART1SMEN LL_APB3_GRP1_EnableClockStopSleep\n + * APB3SMENR I2C3SMEN LL_APB3_GRP1_EnableClockStopSleep\n + * APB3SMENR LPTIM1SMEN LL_APB3_GRP1_EnableClockStopSleep\n + * APB3SMENR LPTIM3SMEN LL_APB3_GRP1_EnableClockStopSleep\n + * APB3SMENR LPTIM4SMEN LL_APB3_GRP1_EnableClockStopSleep\n + * APB3SMENR OPAMPSMEN LL_APB3_GRP1_EnableClockStopSleep\n + * APB3SMENR COMPSMEN LL_APB3_GRP1_EnableClockStopSleep\n + * APB3SMENR VREFSMEN LL_APB3_GRP1_EnableClockStopSleep\n + * APB3SMENR RTCAPBSMEN LL_APB3_GRP1_EnableClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB3_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP + * @arg @ref LL_APB3_GRP1_PERIPH_COMP + * @arg @ref LL_APB3_GRP1_PERIPH_VREF + * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB3SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB3SMENR, Periphs); + (void)tmpreg; +} + + +/** + * @brief Check if APB3 peripheral clocks in Sleep and Stop modes is enabled or not + * @rmtoll APB3SMENR SYSCFGSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n + * APB3SMENR SPI3SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n + * APB3SMENR LPUART1SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n + * APB3SMENR I2C3SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n + * APB3SMENR LPTIM1SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n + * APB3SMENR LPTIM3SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n + * APB3SMENR LPTIM4SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n + * APB3SMENR OPAMPSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n + * APB3SMENR COMPSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n + * APB3SMENR VREFSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n + * APB3SMENR RTCAPBSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB3_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP + * @arg @ref LL_APB3_GRP1_PERIPH_COMP + * @arg @ref LL_APB3_GRP1_PERIPH_VREF + * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB3SMENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB3 peripheral clocks in Sleep and Stop modes + * @rmtoll APB3SMENR SYSCFGSMEN LL_APB3_GRP1_DisableClockStopSleep\n + * APB3SMENR SPI3SMEN LL_APB3_GRP1_DisableClockStopSleep\n + * APB3SMENR LPUART1SMEN LL_APB3_GRP1_DisableClockStopSleep\n + * APB3SMENR I2C3SMEN LL_APB3_GRP1_DisableClockStopSleep\n + * APB3SMENR LPTIM1SMEN LL_APB3_GRP1_DisableClockStopSleep\n + * APB3SMENR LPTIM3SMEN LL_APB3_GRP1_DisableClockStopSleep\n + * APB3SMENR LPTIM4SMEN LL_APB3_GRP1_DisableClockStopSleep\n + * APB3SMENR OPAMPSMEN LL_APB3_GRP1_DisableClockStopSleep\n + * APB3SMENR COMPSMEN LL_APB3_GRP1_DisableClockStopSleep\n + * APB3SMENR VREFSMEN LL_APB3_GRP1_DisableClockStopSleep\n + * APB3SMENR RTCAPBSMEN LL_APB3_GRP1_DisableClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB3_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP + * @arg @ref LL_APB3_GRP1_PERIPH_COMP + * @arg @ref LL_APB3_GRP1_PERIPH_VREF + * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB3SMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_SRDAMR SRDAMR + * @{ + */ + +/** + * @brief Enable SRDAMR peripheral clocks in autonomous mode + * @rmtoll SRDAMR SPI3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR LPUART1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR I2C3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR LPTIM1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR LPTIM3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR LPTIM4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR OPAMPAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR COMPAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR VREFAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR VREFRST LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR RTCAPBAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR ADC4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR LPGPIO1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR DAC1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR LPDMA1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR ADF1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR SRAM4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_SRDAMR_GRP1_PERIPH_ALL + * @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMP + * @arg @ref LL_SRDAMR_GRP1_PERIPH_COMP + * @arg @ref LL_SRDAMR_GRP1_PERIPH_VREF + * @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPB + * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4 + * @retval None + */ +__STATIC_INLINE void LL_SRDAMR_GRP1_EnableAutonomousClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->SRDAMR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->SRDAMR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if SRDAMR peripheral clock is enabled or not + * @rmtoll SRDAMR SPI3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR LPUART1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR I2C3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR LPTIM1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR LPTIM3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR LPTIM4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR OPAMPAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR COMPAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR VREFAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR VREFRST LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR RTCAPBAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR ADC4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR LPGPIO1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR DAC1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR LPDMA1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR ADF1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR SRAM4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_SRDAMR_GRP1_PERIPH_ALL + * @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMP + * @arg @ref LL_SRDAMR_GRP1_PERIPH_COMP + * @arg @ref LL_SRDAMR_GRP1_PERIPH_VREF + * @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPB + * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4 + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SRDAMR_GRP1_IsEnabledAutonomousClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->SRDAMR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable SRDAMR peripheral clocks in Sleep and Stop modes + * @rmtoll SRDAMR SPI3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR LPUART1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR I2C3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR LPTIM1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR LPTIM3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR LPTIM4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR OPAMPAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR COMPAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR VREFAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR VREFRST LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR RTCAPBAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR ADC4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR LPGPIO1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR DAC1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR LPDMA1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR ADF1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR SRAM4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_SRDAMR_GRP1_PERIPH_ALL + * @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMP + * @arg @ref LL_SRDAMR_GRP1_PERIPH_COMP + * @arg @ref LL_SRDAMR_GRP1_PERIPH_VREF + * @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPB + * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4 + * @retval None + */ +__STATIC_INLINE void LL_SRDAMR_GRP1_DisableAutonomousClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->SRDAMR, Periphs); +} +/** + * @} + */ + +/** + * @} + */ +#endif /* defined(RCC) */ + +/** + * @} + */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_LL_BUS_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h new file mode 100644 index 000000000..cae2a44ff --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h @@ -0,0 +1,1320 @@ +/** + ****************************************************************************** + * @file stm32u5xx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick with + HCLK source or @ref LL_Init1msTick_HCLK_Div8, @ref LL_Init1msTick_LSI or + @ref LL_Init1msTick_LSE with external source + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) API to access to MCU info (CPUID register) + (+) API to enable fault handler (SHCSR accesses) + (+) API to enable and disable the MPU secure and non-secure + (+) API to configure the region of MPU secure and non-secure + (+) API to configure the attributes region of MPU secure and non-secure + + @endverbatim + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_LL_CORTEX_H +#define STM32U5xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx.h" + +/** @addtogroup STM32U5xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CORTEX_LL_EC_REGION_ACCESS CORTEX LL MPU Region Access Attributes + * @{ + */ +/* Register MPU_RBAR (Cortex-M33) : bits [4:0] */ +#define MPU_ACCESS_MSK (MPU_RBAR_SH_Msk|MPU_RBAR_AP_Msk|MPU_RBAR_XN_Msk) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX LL Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_EXTERNAL 0x00000000U /*!< External clock source selected as SysTick + clock source */ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick + clock source */ +/** Legacy definitions for backward compatibility purpose + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 LL_SYSTICK_CLKSOURCE_EXTERNAL +/** + */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type + * @{ + */ +#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ +#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ +#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ +#define LL_HANDLER_FAULT_SECURE SCB_SHCSR_SECUREFAULTENA_Msk /*!< Secure fault */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes + * @{ + */ +/* Device memory attributes */ +#define LL_MPU_DEVICE_NGNRNE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ +#define LL_MPU_DEVICE_NGNRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ +#define LL_MPU_DEVICE_NGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ +#define LL_MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ + +/* Normal memory attributes */ +/* Non-cacheable memory attribute */ +#define LL_MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable */ + +/* Cacheable memory attributes: combination of cache write policy, transient and allocation */ +/* - cache write policy */ +#define LL_MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through */ +#define LL_MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back */ +/* - transient mode attribute */ +#define LL_MPU_TRANSIENT 0x0U /*!< Normal memory, transient */ +#define LL_MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient */ +/* - allocation attribute */ +#define LL_MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate */ +#define LL_MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate */ +#define LL_MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate */ +#define LL_MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Region_Enable CORTEX LL MPU Region Enable + * @{ + */ +#define LL_MPU_REGION_ENABLE 1U +#define LL_MPU_REGION_DISABLE 0U +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) /*!< Execute attribute */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) /*!< Execute never attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable + * @{ + */ +#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) /*!< Not shareable attribute */ +#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) /*!< Outer shareable attribute */ +#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) /*!< Inner shareable attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes + * @{ + */ +#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) /*!< Read/write privileged-only attribute */ +#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) /*!< Read/write privileged/unprivileged attribute */ +#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) /*!< Read-only privileged-only attribute */ +#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) /*!< Read-only privileged/unprivileged attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Region_Index CORTEX LL MPU Region Index + * @{ + */ +#define LL_MPU_REGION_NUMBER0 0U +#define LL_MPU_REGION_NUMBER1 1U +#define LL_MPU_REGION_NUMBER2 2U +#define LL_MPU_REGION_NUMBER3 3U +#define LL_MPU_REGION_NUMBER4 4U +#define LL_MPU_REGION_NUMBER5 5U +#define LL_MPU_REGION_NUMBER6 6U +#define LL_MPU_REGION_NUMBER7 7U +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Attributes_Index CORTEX LL MPU Memory Attributes Index + * @{ + */ +#define LL_MPU_ATTRIBUTES_NUMBER0 0U +#define LL_MPU_ATTRIBUTES_NUMBER1 1U +#define LL_MPU_ATTRIBUTES_NUMBER2 2U +#define LL_MPU_ATTRIBUTES_NUMBER3 3U +#define LL_MPU_ATTRIBUTES_NUMBER4 4U +#define LL_MPU_ATTRIBUTES_NUMBER5 5U +#define LL_MPU_ATTRIBUTES_NUMBER6 6U +#define LL_MPU_ATTRIBUTES_NUMBER7 7U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX LL Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @brief CORTEX SYSTICK LL module driver + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_EXTERNAL + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + if (Source == LL_SYSTICK_CLKSOURCE_HCLK) + { + SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } + else + { + CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_EXTERNAL + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE CORTEX LL LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_HANDLER CORTEX LL HANDLER + * @{ + */ + +/** + * @brief Enable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_EnableFault\n + * SCB_SHCSR BUSFAULTENA LL_HANDLER_EnableFault\n + * SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault\n + * SCB_SHCSR SECUREFAULTENA LL_HANDLER_EnableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @arg @ref LL_HANDLER_FAULT_SECURE (*) + * + * (*) value applicable in secure when the system implements the security. + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) +{ + /* Enable the system handler fault */ + SET_BIT(SCB->SHCSR, Fault); +} + +/** + * @brief Disable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_DisableFault\n + * SCB_SHCSR BUSFAULTENA LL_HANDLER_DisableFault\n + * SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault\n + * SCB_SHCSR SECUREFAULTENA LL_HANDLER_DisableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @arg @ref LL_HANDLER_FAULT_SECURE (*) + * + * (*) value applicable in secure when the system implements the security. + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) +{ + /* Disable the system handler fault */ + CLEAR_BIT(SCB->SHCSR, Fault); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO CORTEX LL MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Architecture version + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture + * @retval Value should be equal to 0xF for Cortex-M33 ("ARMv8-M with Main Extension") + */ +__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xD21 for Cortex-M33 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MPU CORTEX LL MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param MPU_Control This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ + + /* Enable the MPU*/ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable non-secure MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param MPU_Control This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ + + /* Enable the MPU*/ + MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */ + + /* Disable MPU */ + WRITE_REG(MPU->CTRL, 0U); + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Disable the non-secure MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable_NS + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable_NS(void) +{ + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */ + + /* Disable MPU*/ + WRITE_REG(MPU_NS->CTRL, 0U); + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} +#endif /* __ARM_FEATURE_CMSE */ + + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Check if non-secure MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled_NS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled_NS(void) +{ + return ((READ_BIT(MPU_NS->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Enable the MPU region */ + SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +/** + * @brief Check if MPU region is enabled or not + * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region(uint32_t Region) +{ + /* Set region index */ + WRITE_REG(MPU->RNR, Region); + + /* Return MPU region status */ + return ((READ_BIT(MPU->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable a non-secure MPU region + * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Enable the MPU region */ + SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} + +/** + * @brief Check if non-secure MPU region is enabled or not + * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region_NS(uint32_t Region) +{ + /* Set region index */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Return non-secure MPU region status */ + return ((READ_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Disable a MPU region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * MPU_RLAR ENABLE LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Disable the MPU region */ + CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Disable a non-secure MPU region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion_NS\n + * MPU_RLAR ENABLE LL_MPU_DisableRegion_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Disable the MPU region */ + CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Configure and enable a MPU region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion\n + * MPU_RLAR ADDR LL_MPU_ConfigRegion\n + * MPU_RBAR XN LL_MPU_ConfigRegion\n + * MPU_RBAR AP LL_MPU_ConfigRegion\n + * MPU_RBAR SH LL_MPU_ConfigRegion\n + * MPU_RLAR EN LL_MPU_ConfigRegion\n + * MPU_RLAR AttrIndx LL_MPU_ConfigRegion\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE + * or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO + * or @ref LL_MPU_REGION_ALL_RO + * @param AttrIndx This parameter can be one of the following values: + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 + * @param BaseAddress Value of region base address + * @param LimitAddress Value of region limit address + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress, + uint32_t LimitAddress) +{ + /* Set region index */ + WRITE_REG(MPU->RNR, Region); + + /* Set region base address and region access attributes */ + WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); + + /* Set region limit address, memory attributes index and enable region */ + WRITE_REG(MPU->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk)); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure and enable a non-secure MPU region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion_NS\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion_NS\n + * MPU_RLAR ADDR LL_MPU_ConfigRegion_NS\n + * MPU_RBAR XN LL_MPU_ConfigRegion_NS\n + * MPU_RBAR AP LL_MPU_ConfigRegion_NS\n + * MPU_RBAR SH LL_MPU_ConfigRegion_NS\n + * MPU_RLAR EN LL_MPU_ConfigRegion_NS\n + * MPU_RLAR AttrIndx LL_MPU_ConfigRegion_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE + * or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO + * or @ref LL_MPU_REGION_ALL_RO + * @param AttrIndx This parameter can be one of the following values: + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 + * @param BaseAddress Value of region base address + * @param LimitAddress Value of region limit address + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, + uint32_t BaseAddress, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set region base address and region access attributes */ + WRITE_REG(MPU_NS->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); + + /* Set region limit address, memory attributes index and enable region */ + WRITE_REG(MPU_NS->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk)); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Configure a MPU region address range + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress\n + * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress\n + * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param BaseAddress Value of region base address + * @param LimitAddress Value of region limit address + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Modify region base address */ + MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); + + /* Modify region limit address */ + MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure a non-secure MPU region address range + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress_NS\n + * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress_NS\n + * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param BaseAddress Value of region base address + * @param LimitAddress Value of region limit address + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set base address */ + MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); + + /* Set limit address */ + MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Configure a MPU attributes index + * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes\n + * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes\n + * @param AttIndex This parameter can be one of the following values: + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 + * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attributes) +{ + /* When selected index is in range [0;3] */ + if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) + { + /* Modify Attr field of MPU_MAIR0 accordingly */ + MODIFY_REG(MPU->MAIR0, (0xFFUL << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); + } + /* When selected index is in range [4;7] */ + else + { + /* Modify Attr field of MPU_MAIR1 accordingly */ + MODIFY_REG(MPU->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure a non-secure MPU attributes index + * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes_NS\n + * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes_NS\n + * @param AttIndex This parameter can be one of the following values: + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 + * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Attributes) +{ + /* When selected index is in range [0;3] */ + if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) + { + /* Modify Attr field of MPU_MAIR0_NS accordingly */ + MODIFY_REG(MPU_NS->MAIR0, (0xFFUL << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); + } + /* When selected index is in range [4;7] */ + else + { + /* Modify Attr field of MPU_MAIR1_NS accordingly */ + MODIFY_REG(MPU_NS->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); + } +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Configure a MPU region limit address + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress\n + * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param LimitAddress Value of region limit address + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Set limit address */ + MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); +} + +/** + * @brief Get a MPU region limit address + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk)); +} + +/** + * @brief Configure a MPU region base address + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress\n + * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param BaseAddress Value of region base address + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseAddress) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Set base address */ + MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); +} + +/** + * @brief Get a MPU region base address + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk)); +} + +/** + * @brief Configure a MPU region access attributes and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess\n + * MPU_RBAR XN LL_MPU_SetRegionAccess\n + * MPU_RBAR AP LL_MPU_SetRegionAccess\n + * MPU_RBAR SH LL_MPU_SetRegionAccess\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE + * or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO + * or @ref LL_MPU_REGION_ALL_RO + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Set base address */ + MODIFY_REG(MPU->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK)); +} + +/** + * @brief Get a MPU region access attributes + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess\n + * MPU_RBAR XN LL_MPU_GetRegionAccess\n + * MPU_RBAR AP LL_MPU_GetRegionAccess\n + * MPU_RBAR SH LL_MPU_GetRegionAccess\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk))); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure a non-secure MPU region limit address + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress_NS\n + * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param LimitAddress Value of region limit address + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set limit address */ + MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); +} + +/** + * @brief Get a non-secure MPU region limit address + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk)); +} + +/** + * @brief Configure a non-secure MPU region base address + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress_NS\n + * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param BaseAddress Value of region base address + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t BaseAddress) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set base address */ + MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); +} + +/** + * @brief Get a non-secure MPU region base address + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk)); +} + +/** + * @brief Configure a non-secure MPU region access attributes and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess_NS\n + * MPU_RBAR XN LL_MPU_SetRegionAccess_NS\n + * MPU_RBAR AP LL_MPU_SetRegionAccess_NS\n + * MPU_RBAR SH LL_MPU_SetRegionAccess_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE + * or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO + * or @ref LL_MPU_REGION_ALL_RO + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set base address Attributes */ + MODIFY_REG(MPU_NS->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK)); +} + +/** + * @brief Get a non-secure MPU region access attributes + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess_NS\n + * MPU_RBAR XN LL_MPU_GetRegionAccess_NS\n + * MPU_RBAR AP LL_MPU_GetRegionAccess_NS\n + * MPU_RBAR SH LL_MPU_GetRegionAccess_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk))); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_LL_CORTEX_H */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_crs.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_crs.h new file mode 100644 index 000000000..678c2e799 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_crs.h @@ -0,0 +1,796 @@ +/** + ****************************************************************************** + * @file stm32u5xx_ll_crs.h + * @author MCD Application Team + * @brief Header file of CRS LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_LL_CRS_H +#define STM32U5xx_LL_CRS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx.h" + +/** @addtogroup STM32U5xx_LL_Driver + * @{ + */ + +#if defined(CRS) + +/** @defgroup CRS_LL CRS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CRS_LL_Private_Constants CRS Private Constants + * @{ + */ + +/* Defines used for the bit position in the register and perform offsets*/ +#define CRS_POSITION_TRIM (CRS_CR_TRIM_Pos) /* bit position in CR reg */ +#define CRS_POSITION_FECAP (CRS_ISR_FECAP_Pos) /* bit position in ISR reg */ +#define CRS_POSITION_FELIM (CRS_CFGR_FELIM_Pos) /* bit position in CFGR reg */ + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants + * @{ + */ + +/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_CRS_ReadReg function + * @{ + */ +#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF +#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF +#define LL_CRS_ISR_ERRF CRS_ISR_ERRF +#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF +#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR +#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS +#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF +/** + * @} + */ + +/** @defgroup CRS_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions + * @{ + */ +#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE +#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE +#define LL_CRS_CR_ERRIE CRS_CR_ERRIE +#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider + * @{ + */ +#define LL_CRS_SYNC_DIV_1 0x00000000U /*!< Synchro Signal not divided (default) */ +#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source + * @{ + */ +#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ +#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity + * @{ + */ +#define LL_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ +#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction + * @{ + */ +#define LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ +#define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values + * @{ + */ +/** + * @brief Reset value of the RELOAD field + * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz + * and a synchronization signal frequency of 1 kHz (SOF signal from USB) + */ +#define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU + +/** + * @brief Reset value of Frequency error limit. + */ +#define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U + +/** + * @brief Reset value of the HSI48 Calibration field + * @note The default value is 64, which corresponds to the middle of the trimming interval. + * The trimming step is specified in the product datasheet. + * A higher TRIM value corresponds to a higher output frequency. + */ +#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros + * @{ + */ + +/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload + * @{ + */ + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between + * the target frequency and the frequency of the synchronization source after + * prescaling. It is then decreased by one in order to reach the expected + * synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval Reload value (in Hz) + */ +#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions + * @{ + */ + +/** @defgroup CRS_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable Frequency error counter + * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified + * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void) +{ + SET_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Disable Frequency error counter + * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Check if Frequency error counter is enabled or not + * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void) +{ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Disable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Check if Automatic trimming is enabled or not + * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL); +} + +/** + * @brief Set HSI48 oscillator smooth trimming + * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only + * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming + * @param Value a number between Min_Data = 0 and Max_Data = 127 + * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM); +} + +/** + * @brief Get HSI48 oscillator smooth trimming + * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming + * @retval a number between Min_Data = 0 and Max_Data = 127 + */ +__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) +{ + return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM); +} + +/** + * @brief Set counter reload value + * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter + * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF + * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT + * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_) + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); +} + +/** + * @brief Get counter reload value + * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter + * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); +} + +/** + * @brief Set frequency error limit + * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit + * @param Value a number between Min_Data = 0 and Max_Data = 255 + * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM); +} + +/** + * @brief Get frequency error limit + * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit + * @retval A number between Min_Data = 0 and Max_Data = 255 + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM); +} + +/** + * @brief Set division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); +} + +/** + * @brief Get division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV)); +} + +/** + * @brief Set SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); +} + +/** + * @brief Get SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC)); +} + +/** + * @brief Set input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); +} + +/** + * @brief Get input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL)); +} + +/** + * @brief Configure CRS for the synchronization + * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n + * CFGR RELOAD LL_CRS_ConfigSynchronization\n + * CFGR FELIM LL_CRS_ConfigSynchronization\n + * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n + * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n + * CFGR SYNCPOL LL_CRS_ConfigSynchronization + * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 127 + * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF + * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 + * @param Settings This parameter can be a combination of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 + * or @ref LL_CRS_SYNC_DIV_8 or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 + * or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB + * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, + uint32_t ReloadValue, uint32_t Settings) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue); + MODIFY_REG(CRS->CFGR, + CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, + ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_CRS_Management CRS_Management + * @{ + */ + +/** + * @brief Generate software SYNC event + * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Get the frequency error direction latched in the time of the last + * SYNC event + * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP + * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** + * @brief Get the frequency error counter value latched in the time of the last SYNC event + * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture + * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if SYNC event OK signal occurred or not + * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if SYNC warning signal occurred or not + * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if Synchronization or trimming error signal occurred or not + * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL); +} + +/** + * @brief Check if Expected SYNC signal occurred or not + * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL); +} + +/** + * @brief Check if SYNC error signal occurred or not + * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL); +} + +/** + * @brief Check if SYNC missed error signal occurred or not + * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL); +} + +/** + * @brief Check if Trimming overflow or underflow occurred or not + * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the SYNC event OK flag + * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); +} + +/** + * @brief Clear the SYNC warning flag + * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); +} + +/** + * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also + * the ERR flag + * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); +} + +/** + * @brief Clear Expected SYNC flag + * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Disable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Check if SYNC event OK interrupt is enabled or not + * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Disable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Check if SYNC warning interrupt is enabled or not + * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ERR(void) +{ + SET_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Disable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ERR(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Check if Synchronization or trimming error interrupt is enabled or not + * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Disable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Check if Expected SYNC interrupt is enabled or not + * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_CRS_DeInit(void); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRS) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_LL_CRS_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h new file mode 100644 index 000000000..7d7cd47dc --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h @@ -0,0 +1,7058 @@ +/** + ****************************************************************************** + * @file stm32u5xx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### LL DMA driver acronyms ##### + ============================================================================== + [..] Acronyms table : + ========================================= + || Acronym || || + ========================================= + || SRC || Source || + || DEST || Destination || + || ADDR || Address || + || ADDRS || Addresses || + || INC || Increment / Incremented || + || DEC || Decrement / Decremented || + || BLK || Block || + || RPT || Repeat / Repeated || + || TRIG || Trigger || + ========================================= + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_LL_DMA_H +#define STM32U5xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx.h" + +/** @addtogroup STM32U5xx_LL_Driver + * @{ + */ + +#if (defined (GPDMA1) || defined (LPDMA1)) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +#define DMA_CHANNEL0_OFFSET (0x00000050UL) +#define DMA_CHANNEL1_OFFSET (0x000000D0UL) +#define DMA_CHANNEL2_OFFSET (0x00000150UL) +#define DMA_CHANNEL3_OFFSET (0x000001D0UL) +#define DMA_CHANNEL4_OFFSET (0x00000250UL) +#define DMA_CHANNEL5_OFFSET (0x000002D0UL) +#define DMA_CHANNEL6_OFFSET (0x00000350UL) +#define DMA_CHANNEL7_OFFSET (0x000003D0UL) +#define DMA_CHANNEL8_OFFSET (0x00000450UL) +#define DMA_CHANNEL9_OFFSET (0x000004D0UL) +#define DMA_CHANNEL10_OFFSET (0x00000550UL) +#define DMA_CHANNEL11_OFFSET (0x000005D0UL) +#define DMA_CHANNEL12_OFFSET (0x00000650UL) +#define DMA_CHANNEL13_OFFSET (0x000006D0UL) +#define DMA_CHANNEL14_OFFSET (0x00000750UL) +#define DMA_CHANNEL15_OFFSET (0x000007D0UL) + +#define LL_DMA_CHANNEL_MAX LL_DMA_CHANNEL_15 + +/* Array used to get the DMA Channel register offset versus Channel index LL_DMA_CHANNEL_x */ +static const uint32_t LL_DMA_CH_OFFSET_TAB[] = +{ + DMA_CHANNEL0_OFFSET, DMA_CHANNEL1_OFFSET, DMA_CHANNEL2_OFFSET, DMA_CHANNEL3_OFFSET, + DMA_CHANNEL4_OFFSET, DMA_CHANNEL5_OFFSET, DMA_CHANNEL6_OFFSET, DMA_CHANNEL7_OFFSET, + DMA_CHANNEL8_OFFSET, DMA_CHANNEL9_OFFSET, DMA_CHANNEL10_OFFSET, DMA_CHANNEL11_OFFSET, + DMA_CHANNEL12_OFFSET, DMA_CHANNEL13_OFFSET, DMA_CHANNEL14_OFFSET, DMA_CHANNEL15_OFFSET, +}; + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ + +/** + * @brief LL DMA init structure definition. + */ +typedef struct +{ + uint32_t SrcAddress; /*!< This field specify the data transfer source address. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcAddress(). */ + + uint32_t DestAddress; /*!< This field specify the data transfer destination address. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestAddress(). */ + + uint32_t Direction; /*!< This field specify the data transfer direction. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t BlkHWRequest; /*!< This field specify the hardware request unity. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkHWRequest(). */ + + uint32_t DataAlignment; /*!< This field specify the transfer data alignment. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDataAlignment(). */ + + uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes. + Programming this field is not mandatory for LPDMA channels. + This parameter must be a value between Min_Data = 1 and Max_Data = 64. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcBurstLength(). */ + + uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes. + Programming this field is not mandatory for LPDMA channels. + This parameter must be a value between Min_Data = 1 and Max_Data = 64. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestBurstLength(). */ + + uint32_t SrcDataWidth; /*!< This field specify the source data width. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcDataWidth(). */ + + uint32_t DestDataWidth; /*!< This field specify the destination data width. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestDataWidth(). */ + + uint32_t SrcIncMode; /*!< This field specify the source burst increment mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcIncMode(). */ + + uint32_t DestIncMode; /*!< This field specify the destination burst increment mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestIncMode(). */ + + uint32_t Priority; /*!< This field specify the channel priority level. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetChannelPriorityLevel(). */ + + uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkDataLength(). */ + + uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value between 1 and 2048 Min_Data = 0 + and Max_Data = 0x000007FF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkRptCount(). */ + + uint32_t TriggerMode; /*!< This field specify the trigger mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetTriggerMode(). */ + + uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetTriggerPolarity(). */ + + uint32_t TriggerSelection; /*!< This field specify the trigger event selection. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetHWTrigger(). */ + + uint32_t Request; /*!< This field specify the peripheral request selection. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetPeriphRequest(). */ + + uint32_t TransferEventMode; /*!< This field specify the transfer event mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetTransferEventMode(). */ + + uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange. + Programming this field is not mandatory for LPDMA channels. + This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestHWordExchange(). */ + + uint32_t DestByteExchange; /*!< This field specify the destination byte exchange. + Programming this field is not mandatory for LPDMA channels. + This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestByteExchange(). */ + + uint32_t SrcByteExchange; /*!< This field specify the source byte exchange. + Programming this field is not mandatory for LPDMA channels. + This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcByteExchange(). */ + + uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port. + Programming this field is not mandatory for LPDMA channels. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcAllocatedPort(). */ + + uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port. + Programming this field is not mandatory for LPDMA channels. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestAllocatedPort(). */ + + uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port. + Programming this field is not mandatory for LPDMA channels. + This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkAllocatedPort(). */ + + uint32_t LinkStepMode; /*!< This field specify the link step mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkStepMode(). */ + + uint32_t SrcAddrUpdateMode; /*!< This field specify the source address update mode. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcAddrUpdate(). */ + + uint32_t DestAddrUpdateMode; /*!< This field specify the destination address update mode. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestAddrUpdate(). */ + + uint32_t SrcAddrOffset; /*!< This field specifies the source address offset. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value Between 0 to 0x00001FFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcAddrUpdateValue(). */ + + uint32_t DestAddrOffset; /*!< This field specifies the destination address offset. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value Between 0 to 0x00001FFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestAddrUpdateValue(). */ + + uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkRptSrcAddrUpdate(). */ + + uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkRptDestAddrUpdate(). */ + + uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value Between 0 to 0x0000FFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkRptSrcAddrUpdateValue(). */ + + uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value Between 0 to 0x0000FFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkRptDestAddrUpdateValue(). */ + + uint32_t LinkedListBaseAddr; /*!< This field specify the linked list base address. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value Between 0 to 0xFFFF0000 (where the 4 first + bytes are always forced to 0). + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkedListBaseAddr(). */ + + uint32_t LinkedListAddrOffset; /*!< Specifies the linked list address offset. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value Between 0 to 0x0000FFFC. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkedListAddrOffset(). */ + +} LL_DMA_InitTypeDef; + + +/** + * @brief LL DMA init linked list structure definition. + */ +typedef struct +{ + uint32_t Priority; /*!< This field specify the channel priority level. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetChannelPriorityLevel(). */ + + uint32_t LinkStepMode; /*!< This field specify the link step mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkStepMode(). */ + + uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port. + Programming this field is not mandatory for LPDMA channels. + This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkAllocatedPort(). */ + + uint32_t TransferEventMode; /*!< This field specify the transfer event mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetTransferEventMode(). */ +} LL_DMA_InitLinkedListTypeDef; + + +/** + * @brief LL DMA node init structure definition. + */ +typedef struct +{ + /* CTR1 register fields ****************************************************** + If any CTR1 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CTR1 register fields and enable update + CTR1 register in UpdateRegisters fields if it is not enabled in the + previous node. + + If the node to be created is for LPDMA channels, there is no need to fill + the following fields for CTR1 register : + - DestAllocatedPort. + - DestHWordExchange. + - DestByteExchange. + - DestBurstLength. + - SrcAllocatedPort. + - SrcByteExchange. + - SrcBurstLength. + + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t DestSecure; /*!< This field specify the destination secure. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE. */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. */ + + uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange. + This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. */ + + uint32_t DestByteExchange; /*!< This field specify the destination byte exchange. + This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. */ + + uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes. + This parameter must be a value between Min_Data = 1 and Max_Data = 64. */ + + uint32_t DestIncMode; /*!< This field specify the destination increment mode. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. */ + + uint32_t DestDataWidth; /*!< This field specify the destination data width. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t SrcSecure; /*!< This field specify the source secure. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE. */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. */ + + uint32_t SrcByteExchange; /*!< This field specify the source byte exchange. + This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. */ + + uint32_t DataAlignment; /*!< This field specify the transfer data alignment. + This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. */ + + uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes. + This parameter must be a value between Min_Data = 1 and Max_Data = 64. */ + + uint32_t SrcIncMode; /*!< This field specify the source increment mode. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. */ + + uint32_t SrcDataWidth; /*!< This field specify the source data width. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. */ + + + /* CTR2 register fields ****************************************************** + If any CTR2 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CTR2 register fields and enable update + CTR2 register in UpdateRegisters fields if it is not enabled in the + previous node. + + For all node created, filling all fields is mandatory. + */ + uint32_t TransferEventMode; /*!< This field specify the transfer event mode. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. */ + + uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. */ + + uint32_t TriggerSelection; /*!< This field specify the trigger event selection. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. */ + + uint32_t TriggerMode; /*!< This field specify the trigger mode. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. */ + + uint32_t BlkHWRequest; /*!< This field specify the hardware request unity. + This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. */ + + uint32_t Direction; /*!< This field specify the transfer direction. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. */ + + uint32_t Request; /*!< This field specify the peripheral request selection. + This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. */ + + + /* CBR1 register fields ****************************************************** + If any CBR1 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CBR1 register fields and enable update + CBR1 register in UpdateRegisters fields if it is not enabled in the + previous node. + + If the node to be created is not for 2D addressing channels, there is no + need to fill the following fields for CBR1 register : + - BlkReptDestAddrUpdate. + - BlkRptSrcAddrUpdate. + - DestAddrUpdate. + - SrcAddrUpdate. + - BlkRptCount. + */ + uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode. + This parameter can be a value of + @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE. */ + + uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode. + This parameter can be a value of + @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE. */ + + uint32_t DestAddrUpdateMode; /*!< This field specify the Destination address update mode. + This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE. */ + + uint32_t SrcAddrUpdateMode; /*!< This field specify the Source address update mode. + This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE. */ + + uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block. + This parameter can be a value between 1 and 2048 Min_Data = 0 + and Max_Data = 0x000007FF. */ + + uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes. + This parameter must be a value between Min_Data = 0 + and Max_Data = 0x0000FFFF. */ + + /* CSAR register fields ****************************************************** + If any CSAR fields need to be updated comparing to previous node, it is + mandatory to update the new value in CSAR register fields and enable update + CSAR register in UpdateRegisters fields if it is not enabled in the + previous node. + + For all node created, filling all fields is mandatory. + */ + uint32_t SrcAddress; /*!< This field specify the transfer source address. + This parameter must be a value between Min_Data = 0 + and Max_Data = 0xFFFFFFFF. */ + + + /* CDAR register fields ****************************************************** + If any CDAR fields need to be updated comparing to previous node, it is + mandatory to update the new value in CDAR register fields and enable update + CDAR register in UpdateRegisters fields if it is not enabled in the + previous node. + + For all node created, filling all fields is mandatory. + */ + uint32_t DestAddress; /*!< This field specify the transfer destination address. + This parameter must be a value between Min_Data = 0 + and Max_Data = 0xFFFFFFFF. */ + + /* CTR3 register fields ****************************************************** + If any CTR3 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CTR3 register fields and enable update + CTR3 register in UpdateRegisters fields if it is not enabled in the + previous node. + + This register is used only for 2D addressing channels. + If used channel is linear addressing, this register will be overwritten by + CLLR register in memory. + When this register is enabled on UpdateRegisters and the selected channel + is linear addressing, LL APIs will discard this register update in memory. + */ + uint32_t DestAddrOffset; /*!< This field specifies the destination address offset. + This parameter can be a value Between 0 to 0x00001FFF. */ + + uint32_t SrcAddrOffset; /*!< This field specifies the source address offset. + This parameter can be a value Between 0 to 0x00001FFF. */ + + + /* CBR2 register fields ****************************************************** + If any CBR2 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CBR2 register fields and enable update + CBR2 register in UpdateRegisters fields if it is not enabled in the + previous node. + + This register is used only for 2D addressing channels. + If used channel is linear addressing, this register will be discarded in + memory. When this register is enabled on UpdateRegisters and the selected + channel is linear addressing, LL APIs will discard this register update in + memory. + */ + uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset. + This parameter can be a value Between 0 to 0x0000FFFF. */ + + uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset. + This parameter can be a value Between 0 to 0x0000FFFF. */ + + /* CLLR register fields ****************************************************** + If any CLLR fields need to be updated comparing to previous node, it is + mandatory to update the new value in CLLR register fields and enable update + CLLR register in UpdateRegisters fields if it is not enabled in the + previous node. + + If used channel is linear addressing, there is no need to enable/disable + CTR3 and CBR2 register in UpdateRegisters fields as they will be discarded + by LL APIs. + */ + uint32_t UpdateRegisters; /*!< Specifies the linked list register update. + This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE. */ + + /* DMA Node type field ******************************************************* + This parameter defines node types as node size and node content varies + between channels. + Thanks to this fields, linked list queue could be created independently + from channel selection. So, one queue could be executed by all DMA channels. + */ + uint32_t NodeType; /*!< Specifies the node type to be created. + This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_NODE_TYPE. */ +} LL_DMA_InitNodeTypeDef; + +/** + * @brief LL DMA linked list node structure definition. + * @note For 2D addressing channels, the maximum node size is : + * (4 Bytes * 8 registers = 32 Bytes). + * For GPDMA linear addressing channels, the maximum node size is : + * (4 Bytes * 6 registers = 24 Bytes). + * For LPDMA linear addressing channels, the maximum node size is : + * (4 Bytes * 6 registers = 24 Bytes). + */ +typedef struct +{ + __IO uint32_t LinkRegisters[8U]; + +} LL_DMA_LinkNodeTypeDef; +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_LL_EC_CHANNEL Channel + * @{ + */ +#define LL_DMA_CHANNEL_0 (0x00U) +#define LL_DMA_CHANNEL_1 (0x01U) +#define LL_DMA_CHANNEL_2 (0x02U) +#define LL_DMA_CHANNEL_3 (0x03U) +#define LL_DMA_CHANNEL_4 (0x04U) +#define LL_DMA_CHANNEL_5 (0x05U) +#define LL_DMA_CHANNEL_6 (0x06U) +#define LL_DMA_CHANNEL_7 (0x07U) +#define LL_DMA_CHANNEL_8 (0x08U) +#define LL_DMA_CHANNEL_9 (0x09U) +#define LL_DMA_CHANNEL_10 (0x0AU) +#define LL_DMA_CHANNEL_11 (0x0BU) +#define LL_DMA_CHANNEL_12 (0x0CU) +#define LL_DMA_CHANNEL_13 (0x0DU) +#define LL_DMA_CHANNEL_14 (0x0EU) +#define LL_DMA_CHANNEL_15 (0x0FU) +#if defined (USE_FULL_LL_DRIVER) +#define LL_DMA_CHANNEL_ALL (0x10U) +#endif /* USE_FULL_LL_DRIVER */ +/** + * @} + */ + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EC_CLLR_OFFSET CLLR offset + * @{ + */ +#define LL_DMA_CLLR_OFFSET0 (0x00U) +#define LL_DMA_CLLR_OFFSET1 (0x01U) +#define LL_DMA_CLLR_OFFSET2 (0x02U) +#define LL_DMA_CLLR_OFFSET3 (0x03U) +#define LL_DMA_CLLR_OFFSET4 (0x04U) +#define LL_DMA_CLLR_OFFSET5 (0x05U) +#define LL_DMA_CLLR_OFFSET6 (0x06U) +#define LL_DMA_CLLR_OFFSET7 (0x07U) +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup DMA_LL_EC_PRIORITY_LEVEL Priority Level + * @{ + */ +#define LL_DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low Weight */ +#define LL_DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid Weight */ +#define LL_DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High Weight */ +#define LL_DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : High Priority */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT Linked List Allocated Port + * @{ + */ +#define LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Linked List Allocated Port 0 */ +#define LL_DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Linked List Allocated Port 1 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_LINK_STEP_MODE Link Step Mode + * @{ + */ +#define LL_DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel execute the full linked list */ +#define LL_DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel execute one node of the linked list */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DEST_HALFWORD_EXCHANGE Destination Half-Word Exchange + * @{ + */ +#define LL_DMA_DEST_HALFWORD_PRESERVE 0x00000000U /*!< No destination Half-Word exchange when destination data width + is word */ +#define LL_DMA_DEST_HALFWORD_EXCHANGE DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width + is word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DEST_BYTE_EXCHANGE Destination Byte Exchange + * @{ + */ +#define LL_DMA_DEST_BYTE_PRESERVE 0x00000000U /*!< No destination Byte exchange when destination data width > Byte */ +#define LL_DMA_DEST_BYTE_EXCHANGE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width > Byte */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SRC_BYTE_EXCHANGE Source Byte Exchange + * @{ + */ +#define LL_DMA_SRC_BYTE_PRESERVE 0x00000000U /*!< No source Byte exchange when source data width is word */ +#define LL_DMA_SRC_BYTE_EXCHANGE DMA_CTR1_SBX /*!< Source Byte exchange when source data width is word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_ALLOCATED_PORT Source Allocated Port + * @{ + */ +#define LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source Allocated Port 0 */ +#define LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source Allocated Port 1 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_ALLOCATED_PORT Destination Allocated Port + * @{ + */ +#define LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination Allocated Port 0 */ +#define LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination Allocated Port 1 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_INCREMENT_MODE Destination Increment Mode + * @{ + */ +#define LL_DMA_DEST_FIXED 0x00000000U /*!< Destination fixed single/burst */ +#define LL_DMA_DEST_INCREMENT DMA_CTR1_DINC /*!< Destination incremented single/burst */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_DATA_WIDTH Destination Data Width + * @{ + */ +#define LL_DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination Data Width : Byte */ +#define LL_DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination Data Width : HalfWord */ +#define LL_DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination Data Width : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DATA_ALIGNMENT Data Alignment + * @{ + */ +#define LL_DMA_DATA_ALIGN_ZEROPADD 0x00000000U /*!< If src data width < dest data width : + => Right Aligned padded with 0 up to destination + data width. + If src data width > dest data width : + => Right Aligned Left Truncated down to destination + data width. */ +#define LL_DMA_DATA_ALIGN_SIGNEXTPADD DMA_CTR1_PAM_0 /*!< If src data width < dest data width : + => Right Aligned padded with sign extended up to destination + data width. + If src data width > dest data width : + => Left Aligned Right Truncated down to the destination + data width */ +#define LL_DMA_DATA_PACK_UNPACK DMA_CTR1_PAM_1 /*!< If src data width < dest data width : + => Packed at the destination data width (Not Available + for LPDMA) + If src data width > dest data width : + => Unpacked at the destination data width (Not Available + for LPDMA) */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_INCREMENT_MODE Source Increment Mode + * @{ + */ +#define LL_DMA_SRC_FIXED 0x00000000U /*!< Source fixed single/burst */ +#define LL_DMA_SRC_INCREMENT DMA_CTR1_SINC /*!< Source incremented single/burst */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_DATA_WIDTH Source Data Width + * @{ + */ +#define LL_DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source Data Width : Byte */ +#define LL_DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source Data Width : HalfWord */ +#define LL_DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source Data Width : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_BLKHW_REQUEST Block Hardware Request + * @{ + */ +#define LL_DMA_HWREQUEST_SINGLEBURST 0x00000000U /*!< Hardware request is driven by a peripheral with a hardware + request/acknowledge protocol at a burst level */ +#define LL_DMA_HWREQUEST_BLK DMA_CTR2_BREQ /*!< Hardware request is driven by a peripheral with a hardware + request/acknowledge protocol at a block level */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRANSFER_EVENT_MODE Transfer Event Mode + * @{ + */ +#define LL_DMA_TCEM_BLK_TRANSFER 0x00000000U /*!< The TC (and the HT) event is generated at the + (respectively half) end of each block */ +#define LL_DMA_TCEM_RPT_BLK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC (and the HT) event is generated at the + (respectively half) end of the repeated block */ +#define LL_DMA_TCEM_EACH_LLITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC (and the HT) event is generated at the + (respectively half) end of each linked-list item */ +#define LL_DMA_TCEM_LAST_LLITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC (and the HT) event is generated at the + (respectively half) end of the last linked-list item */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRIGGER_POLARITY Trigger Polarity + * @{ + */ +#define LL_DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. + Masked trigger event */ +#define LL_DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising + edge of the selected trigger event input */ +#define LL_DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling + edge of the selected trigger event input */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRIGGER_MODE Transfer Trigger Mode + * @{ + */ +#define LL_DMA_TRIGM_BLK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) + one hit trigger */ +#define LL_DMA_TRIGM_RPT_BLK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) + one hit trigger */ +#define LL_DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) + one hit trigger */ +#define LL_DMA_TRIGM_SINGLBURST_TRANSFER DMA_CTR2_TRIGM /*!< A Single/Burst transfer is conditioned by (at least) + one hit trigger */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRANSFER_DIRECTION Transfer Direction + * @{ + */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE Block Repeat Source Address Update Mode + * @{ + */ +#define LL_DMA_BLKRPT_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each block + transfer by source update value */ +#define LL_DMA_BLKRPT_SRC_ADDR_DECREMENT DMA_CBR1_BRSDEC /*!< Source address pointer is decremented after each block + transfer by source update value */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE Block Repeat Destination Address Update Mode + * @{ + */ +#define LL_DMA_BLKRPT_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address is incremented after each block + transfer by destination update value */ +#define LL_DMA_BLKRPT_DEST_ADDR_DECREMENT DMA_CBR1_BRDDEC /*!< Destination address is decremented after each block + transfer by destination update value */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SRC_ADDR_UPDATE_MODE Burst Source Address Update Mode + * @{ + */ +#define LL_DMA_BURST_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each burst + transfer by source update value */ +#define LL_DMA_BURST_SRC_ADDR_DECREMENT DMA_CBR1_SDEC /*!< Source address pointer is decremented after each burst + transfer by source update value */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DEST_ADDR_UPDATE_MODE Burst Destination Address Update Mode + * @{ + */ +#define LL_DMA_BURST_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address pointer is incremented after each + burst transfer by destination update value */ +#define LL_DMA_BURST_DEST_ADDR_DECREMENT DMA_CBR1_DDEC /*!< Destination address pointer is decremented after each + burst transfer by destination update value */ +/** + * @} + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute + * @{ + */ +#define LL_DMA_CHANNEL_NSEC 0x00000000U /*!< NSecure channel */ +#define LL_DMA_CHANNEL_SEC 0x00000001U /*!< Secure channel */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute + * @{ + */ +#define LL_DMA_CHANNEL_SRC_NSEC 0x00000000U /*!< NSecure transfer from the source */ +#define LL_DMA_CHANNEL_SRC_SEC DMA_CTR1_SSEC /*!< Secure transfer from the source */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE Destination Security Attribute + * @{ + */ +#define LL_DMA_CHANNEL_DEST_NSEC 0x00000000U /*!< NSecure transfer from the destination */ +#define LL_DMA_CHANNEL_DEST_SEC DMA_CTR1_DSEC /*!< Secure transfer from the destination */ +/** + * @} + */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** @defgroup DMA_LL_EC_LINKEDLIST_NODE_TYPE Linked list node type + * @{ + */ +#define LL_DMA_LPDMA_LINEAR_NODE 0x00U /*!< LPDMA node : linear addressing node */ +#define LL_DMA_GPDMA_LINEAR_NODE 0x01U /*!< GPDMA node : linear addressing node */ +#define LL_DMA_GPDMA_2D_NODE 0x02U /*!< GPDMA node : 2 dimension addressing node */ + +/** + * @} + */ + +/** @defgroup DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE Linked list register update + * @{ + */ +#define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2 /*!< Update CTR2 register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CTR3 DMA_CLLR_UT3 /*!< Update CTR3 register from memory : + available only for 2D addressing DMA channels */ +#define LL_DMA_UPDATE_CBR2 DMA_CLLR_UB2 /*!< Update CBR2 register from memory : + available only for 2D addressing DMA channels */ +#define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory : + available for all DMA channels */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_REQUEST_SELECTION Request Selection + * @{ + */ +/* GPDMA1 Hardware Requests */ +#define LL_GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW Request is ADC1 */ +#define LL_GPDMA1_REQUEST_ADC4 1U /*!< GPDMA1 HW Request is ADC4 */ +#define LL_GPDMA1_REQUEST_DAC1_CH1 2U /*!< GPDMA1 HW Request is DAC1_CH1 */ +#define LL_GPDMA1_REQUEST_DAC1_CH2 3U /*!< GPDMA1 HW Request is DAC1_CH2 */ +#define LL_GPDMA1_REQUEST_TIM6_UP 4U /*!< GPDMA1 HW Request is TIM6_UP */ +#define LL_GPDMA1_REQUEST_TIM7_UP 5U /*!< GPDMA1 HW Request is TIM7_UP */ +#define LL_GPDMA1_REQUEST_SPI1_RX 6U /*!< GPDMA1 HW Request is SPI1_RX */ +#define LL_GPDMA1_REQUEST_SPI1_TX 7U /*!< GPDMA1 HW Request is SPI1_TX */ +#define LL_GPDMA1_REQUEST_SPI2_RX 8U /*!< GPDMA1 HW Request is SPI2_RX */ +#define LL_GPDMA1_REQUEST_SPI2_TX 9U /*!< GPDMA1 HW Request is SPI2_TX */ +#define LL_GPDMA1_REQUEST_SPI3_RX 10U /*!< GPDMA1 HW Request is SPI3_RX */ +#define LL_GPDMA1_REQUEST_SPI3_TX 11U /*!< GPDMA1 HW Request is SPI3_TX */ +#define LL_GPDMA1_REQUEST_I2C1_RX 12U /*!< GPDMA1 HW Request is I2C1_RX */ +#define LL_GPDMA1_REQUEST_I2C1_TX 13U /*!< GPDMA1 HW Request is I2C1_TX */ +#define LL_GPDMA1_REQUEST_I2C1_EVC 14U /*!< GPDMA1 HW Request is I2C1_EVC */ +#define LL_GPDMA1_REQUEST_I2C2_RX 15U /*!< GPDMA1 HW Request is I2C2_RX */ +#define LL_GPDMA1_REQUEST_I2C2_TX 16U /*!< GPDMA1 HW Request is I2C2_TX */ +#define LL_GPDMA1_REQUEST_I2C2_EVC 17U /*!< GPDMA1 HW Request is I2C2_EVC */ +#define LL_GPDMA1_REQUEST_I2C3_RX 18U /*!< GPDMA1 HW Request is I2C3_RX */ +#define LL_GPDMA1_REQUEST_I2C3_TX 19U /*!< GPDMA1 HW Request is I2C3_TX */ +#define LL_GPDMA1_REQUEST_I2C3_EVC 20U /*!< GPDMA1 HW Request is I2C3_EVC */ +#define LL_GPDMA1_REQUEST_I2C4_RX 21U /*!< GPDMA1 HW Request is I2C4_RX */ +#define LL_GPDMA1_REQUEST_I2C4_TX 22U /*!< GPDMA1 HW Request is I2C4_TX */ +#define LL_GPDMA1_REQUEST_I2C4_EVC 23U /*!< GPDMA1 HW Request is I2C4_EVC */ +#define LL_GPDMA1_REQUEST_USART1_RX 24U /*!< GPDMA1 HW Request is USART1_RX */ +#define LL_GPDMA1_REQUEST_USART1_TX 25U /*!< GPDMA1 HW Request is USART1_TX */ +#if defined(USART2) +#define LL_GPDMA1_REQUEST_USART2_RX 26U /*!< GPDMA1 HW Request is USART2_RX */ +#define LL_GPDMA1_REQUEST_USART2_TX 27U /*!< GPDMA1 HW Request is USART2_TX */ +#endif /* USART2 */ +#define LL_GPDMA1_REQUEST_USART3_RX 28U /*!< GPDMA1 HW Request is USART3_RX */ +#define LL_GPDMA1_REQUEST_USART3_TX 29U /*!< GPDMA1 HW Request is USART3_TX */ +#define LL_GPDMA1_REQUEST_UART4_RX 30U /*!< GPDMA1 HW Request is UART4_RX */ +#define LL_GPDMA1_REQUEST_UART4_TX 31U /*!< GPDMA1 HW Request is UART4_TX */ +#define LL_GPDMA1_REQUEST_UART5_RX 32U /*!< GPDMA1 HW Request is UART5_RX */ +#define LL_GPDMA1_REQUEST_UART5_TX 33U /*!< GPDMA1 HW Request is UART5_TX */ +#define LL_GPDMA1_REQUEST_LPUART1_RX 34U /*!< GPDMA1 HW Request is LPUART1_RX */ +#define LL_GPDMA1_REQUEST_LPUART1_TX 35U /*!< GPDMA1 HW Request is LPUART1_TX */ +#define LL_GPDMA1_REQUEST_SAI1_A 36U /*!< GPDMA1 HW Request is SAI1_A */ +#define LL_GPDMA1_REQUEST_SAI1_B 37U /*!< GPDMA1 HW Request is SAI1_B */ +#if defined(SAI2) +#define LL_GPDMA1_REQUEST_SAI2_A 38U /*!< GPDMA1 HW Request is SAI2_A */ +#define LL_GPDMA1_REQUEST_SAI2_B 39U /*!< GPDMA1 HW Request is SAI2_B */ +#endif /* SAI2 */ +#define LL_GPDMA1_REQUEST_OCTOSPI1 40U /*!< GPDMA1 HW Request is OCTOSPI1 */ +#if defined(OCTOSPI2) +#define LL_GPDMA1_REQUEST_OCTOSPI2 41U /*!< GPDMA1 HW Request is OCTOSPI2 */ +#endif /* OCTOSPI2 */ +#define LL_GPDMA1_REQUEST_TIM1_CH1 42U /*!< GPDMA1 HW Request is TIM1_CH1 */ +#define LL_GPDMA1_REQUEST_TIM1_CH2 43U /*!< GPDMA1 HW Request is TIM1_CH2 */ +#define LL_GPDMA1_REQUEST_TIM1_CH3 44U /*!< GPDMA1 HW Request is TIM1_CH3 */ +#define LL_GPDMA1_REQUEST_TIM1_CH4 45U /*!< GPDMA1 HW Request is TIM1_CH4 */ +#define LL_GPDMA1_REQUEST_TIM1_UP 46U /*!< GPDMA1 HW Request is TIM1_UP */ +#define LL_GPDMA1_REQUEST_TIM1_TRIG 47U /*!< GPDMA1 HW Request is TIM1_TRIG */ +#define LL_GPDMA1_REQUEST_TIM1_COM 48U /*!< GPDMA1 HW Request is TIM1_COM */ +#define LL_GPDMA1_REQUEST_TIM8_CH1 49U /*!< GPDMA1 HW Request is TIM8_CH1 */ +#define LL_GPDMA1_REQUEST_TIM8_CH2 50U /*!< GPDMA1 HW Request is TIM8_CH2 */ +#define LL_GPDMA1_REQUEST_TIM8_CH3 51U /*!< GPDMA1 HW Request is TIM8_CH3 */ +#define LL_GPDMA1_REQUEST_TIM8_CH4 52U /*!< GPDMA1 HW Request is TIM8_CH4 */ +#define LL_GPDMA1_REQUEST_TIM8_UP 53U /*!< GPDMA1 HW Request is TIM8_UP */ +#define LL_GPDMA1_REQUEST_TIM8_TRIG 54U /*!< GPDMA1 HW Request is TIM8_TRIG */ +#define LL_GPDMA1_REQUEST_TIM8_COM 55U /*!< GPDMA1 HW Request is TIM8_COM */ +#define LL_GPDMA1_REQUEST_TIM2_CH1 56U /*!< GPDMA1 HW Request is TIM2_CH1 */ +#define LL_GPDMA1_REQUEST_TIM2_CH2 57U /*!< GPDMA1 HW Request is TIM2_CH2 */ +#define LL_GPDMA1_REQUEST_TIM2_CH3 58U /*!< GPDMA1 HW Request is TIM2_CH3 */ +#define LL_GPDMA1_REQUEST_TIM2_CH4 59U /*!< GPDMA1 HW Request is TIM2_CH4 */ +#define LL_GPDMA1_REQUEST_TIM2_UP 60U /*!< GPDMA1 HW Request is TIM2_UP */ +#define LL_GPDMA1_REQUEST_TIM3_CH1 61U /*!< GPDMA1 HW Request is TIM3_CH1 */ +#define LL_GPDMA1_REQUEST_TIM3_CH2 62U /*!< GPDMA1 HW Request is TIM3_CH2 */ +#define LL_GPDMA1_REQUEST_TIM3_CH3 63U /*!< GPDMA1 HW Request is TIM3_CH3 */ +#define LL_GPDMA1_REQUEST_TIM3_CH4 64U /*!< GPDMA1 HW Request is TIM3_CH4 */ +#define LL_GPDMA1_REQUEST_TIM3_UP 65U /*!< GPDMA1 HW Request is TIM3_UP */ +#define LL_GPDMA1_REQUEST_TIM3_TRIG 66U /*!< GPDMA1 HW Request is TIM3_TRIG */ +#define LL_GPDMA1_REQUEST_TIM4_CH1 67U /*!< GPDMA1 HW Request is TIM4_CH1 */ +#define LL_GPDMA1_REQUEST_TIM4_CH2 68U /*!< GPDMA1 HW Request is TIM4_CH2 */ +#define LL_GPDMA1_REQUEST_TIM4_CH3 69U /*!< GPDMA1 HW Request is TIM4_CH3 */ +#define LL_GPDMA1_REQUEST_TIM4_CH4 70U /*!< GPDMA1 HW Request is TIM4_CH4 */ +#define LL_GPDMA1_REQUEST_TIM4_UP 71U /*!< GPDMA1 HW Request is TIM4_UP */ +#define LL_GPDMA1_REQUEST_TIM5_CH1 72U /*!< GPDMA1 HW Request is TIM5_CH1 */ +#define LL_GPDMA1_REQUEST_TIM5_CH2 73U /*!< GPDMA1 HW Request is TIM5_CH2 */ +#define LL_GPDMA1_REQUEST_TIM5_CH3 74U /*!< GPDMA1 HW Request is TIM5_CH3 */ +#define LL_GPDMA1_REQUEST_TIM5_CH4 75U /*!< GPDMA1 HW Request is TIM5_CH4 */ +#define LL_GPDMA1_REQUEST_TIM5_UP 76U /*!< GPDMA1 HW Request is TIM5_UP */ +#define LL_GPDMA1_REQUEST_TIM5_TRIG 77U /*!< GPDMA1 HW Request is TIM5_TRIG */ +#define LL_GPDMA1_REQUEST_TIM15_CH1 78U /*!< GPDMA1 HW Request is TIM15_CH1 */ +#define LL_GPDMA1_REQUEST_TIM15_UP 79U /*!< GPDMA1 HW Request is TIM15_UP */ +#define LL_GPDMA1_REQUEST_TIM15_TRIG 80U /*!< GPDMA1 HW Request is TIM15_TRIG */ +#define LL_GPDMA1_REQUEST_TIM15_COM 81U /*!< GPDMA1 HW Request is TIM15_COM */ +#define LL_GPDMA1_REQUEST_TIM16_CH1 82U /*!< GPDMA1 HW Request is TIM16_CH1 */ +#define LL_GPDMA1_REQUEST_TIM16_UP 83U /*!< GPDMA1 HW Request is TIM16_UP */ +#define LL_GPDMA1_REQUEST_TIM17_CH1 84U /*!< GPDMA1 HW Request is TIM17_CH1 */ +#define LL_GPDMA1_REQUEST_TIM17_UP 85U /*!< GPDMA1 HW Request is TIM17_UP */ +#define LL_GPDMA1_REQUEST_DCMI_PSSI 86U /*!< GPDMA1 HW Request is DCMI_PSSI */ +#define LL_GPDMA1_REQUEST_AES_IN 87U /*!< GPDMA1 HW Request is AES_IN */ +#define LL_GPDMA1_REQUEST_AES_OUT 88U /*!< GPDMA1 HW Request is AES_OUT */ +#define LL_GPDMA1_REQUEST_HASH_IN 89U /*!< GPDMA1 HW Request is HASH_IN */ +#if defined(UCPD1) +#define LL_GPDMA1_REQUEST_UCPD1_TX 90U /*!< GPDMA1 HW Request is UCPD1_TX */ +#define LL_GPDMA1_REQUEST_UCPD1_RX 91U /*!< GPDMA1 HW Request is UCPD1_RX */ +#endif /* UCPD1 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT0 92U /*!< GPDMA1 HW Request is MDF1_FLT0 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT1 93U /*!< GPDMA1 HW Request is MDF1_FLT1 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT2 94U /*!< GPDMA1 HW Request is MDF1_FLT2 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT3 95U /*!< GPDMA1 HW Request is MDF1_FLT3 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT4 96U /*!< GPDMA1 HW Request is MDF1_FLT4 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT5 97U /*!< GPDMA1 HW Request is MDF1_FLT5 */ +#define LL_GPDMA1_REQUEST_ADF1_FLT0 98U /*!< GPDMA1 HW Request is ADF1_FLT0 */ +#define LL_GPDMA1_REQUEST_FMAC_READ 99U /*!< GPDMA1 HW Request is FMAC_READ */ +#define LL_GPDMA1_REQUEST_FMAC_WRITE 100U /*!< GPDMA1 HW Request is FMAC_WRITE */ +#define LL_GPDMA1_REQUEST_CORDIC_READ 101U /*!< GPDMA1 HW Request is CORDIC_READ */ +#define LL_GPDMA1_REQUEST_CORDIC_WRITE 102U /*!< GPDMA1 HW Request is CORDIC_WRITE */ +#define LL_GPDMA1_REQUEST_SAES_IN 103U /*!< GPDMA1 HW Request is SAES_IN */ +#define LL_GPDMA1_REQUEST_SAES_OUT 104U /*!< GPDMA1 HW Request is SAES_OUT */ +#define LL_GPDMA1_REQUEST_LPTIM1_IC1 105U /*!< GPDMA1 HW Request is LPTIM1_IC1 */ +#define LL_GPDMA1_REQUEST_LPTIM1_IC2 106U /*!< GPDMA1 HW Request is LPTIM1_IC2 */ +#define LL_GPDMA1_REQUEST_LPTIM1_UE 107U /*!< GPDMA1 HW Request is LPTIM1_UE */ +#define LL_GPDMA1_REQUEST_LPTIM2_IC1 108U /*!< GPDMA1 HW Request is LPTIM2_IC1 */ +#define LL_GPDMA1_REQUEST_LPTIM2_IC2 109U /*!< GPDMA1 HW Request is LPTIM2_IC2 */ +#define LL_GPDMA1_REQUEST_LPTIM2_UE 110U /*!< GPDMA1 HW Request is LPTIM2_UE */ +#define LL_GPDMA1_REQUEST_LPTIM3_IC1 111U /*!< GPDMA1 HW Request is LPTIM3_IC1 */ +#define LL_GPDMA1_REQUEST_LPTIM3_IC2 112U /*!< GPDMA1 HW Request is LPTIM3_IC2 */ +#define LL_GPDMA1_REQUEST_LPTIM3_UE 113U /*!< GPDMA1 HW Request is LPTIM3_UE */ +#if defined (HSPI1_BASE) +#define LL_GPDMA1_REQUEST_HSPI1 114U /*!< GPDMA1 HW request is HSPI1 */ +#endif /* HSPI1_BASE */ +#if defined (I2C5) +#define LL_GPDMA1_REQUEST_I2C5_RX 115U /*!< GPDMA1 HW request is I2C5_RX */ +#define LL_GPDMA1_REQUEST_I2C5_TX 116U /*!< GPDMA1 HW request is I2C5_TX */ +#define LL_GPDMA1_REQUEST_I2C5_EVC 117U /*!< GPDMA1 HW request is I2C5_EVC */ +#endif /* I2C5 */ +#if defined (I2C6) +#define LL_GPDMA1_REQUEST_I2C6_RX 118U /*!< GPDMA1 HW request is I2C6_RX */ +#define LL_GPDMA1_REQUEST_I2C6_TX 119U /*!< GPDMA1 HW request is I2C6_TX */ +#define LL_GPDMA1_REQUEST_I2C6_EVC 120U /*!< GPDMA1 HW request is I2C6_EVC */ +#endif /* I2C6 */ +#if defined (USART6) +#define LL_GPDMA1_REQUEST_USART6_RX 121U /*!< GPDMA1 HW request is USART6_RX */ +#define LL_GPDMA1_REQUEST_USART6_TX 122U /*!< GPDMA1 HW request is USART6_TX */ +#endif /* USART6 */ +#if defined (ADC2) +#define LL_GPDMA1_REQUEST_ADC2 123U /*!< GPDMA1 HW request is ADC2 */ +#endif /* ADC2 */ +#if defined (JPEG) +#define LL_GPDMA1_REQUEST_JPEG_RX 124U /*!< GPDMA1 HW request is JPEG_TX */ +#define LL_GPDMA1_REQUEST_JPEG_TX 125U /*!< GPDMA1 HW request is JPEG_RX */ +#endif /* JPEG */ + +/* GPDMA1 Hardware Requests aliases */ +#define LL_GPDMA1_REQUEST_DCMI LL_GPDMA1_REQUEST_DCMI_PSSI + +/* LPDMA1 Hardware Requests */ +#define LL_LPDMA1_REQUEST_LPUART1_RX 0U /*!< LPDMA1 HW Request is LPUART1_RX */ +#define LL_LPDMA1_REQUEST_LPUART1_TX 1U /*!< LPDMA1 HW Request is LPUART1_TX */ +#define LL_LPDMA1_REQUEST_SPI3_RX 2U /*!< LPDMA1 HW Request is SPI3_RX */ +#define LL_LPDMA1_REQUEST_SPI3_TX 3U /*!< LPDMA1 HW Request is SPI3_TX */ +#define LL_LPDMA1_REQUEST_I2C3_RX 4U /*!< LPDMA1 HW Request is I2C3_RX */ +#define LL_LPDMA1_REQUEST_I2C3_TX 5U /*!< LPDMA1 HW Request is I2C3_TX */ +#define LL_LPDMA1_REQUEST_I2C3_EVC 6U /*!< LPDMA1 HW Request is I2C3_EVC */ +#define LL_LPDMA1_REQUEST_ADC4 7U /*!< LPDMA1 HW Request is ADC4 */ +#define LL_LPDMA1_REQUEST_DAC1_CH1 8U /*!< LPDMA1 HW Request is DAC1_CH1 */ +#define LL_LPDMA1_REQUEST_DAC1_CH2 9U /*!< LPDMA1 HW Request is DAC1_CH2 */ +#define LL_LPDMA1_REQUEST_ADF1_FLT0 10U /*!< LPDMA1 HW Request is ADF1_FLT0 */ +#define LL_LPDMA1_REQUEST_LPTIM1_IC1 11U /*!< LPDMA1 HW Request is LPTIM1_IC1 */ +#define LL_LPDMA1_REQUEST_LPTIM1_IC2 12U /*!< LPDMA1 HW Request is LPTIM1_IC2 */ +#define LL_LPDMA1_REQUEST_LPTIM1_UE 13U /*!< LPDMA1 HW Request is LPTIM1_UE */ +#define LL_LPDMA1_REQUEST_LPTIM3_IC1 14U /*!< LPDMA1 HW Request is LPTIM3_IC1 */ +#define LL_LPDMA1_REQUEST_LPTIM3_IC2 15U /*!< LPDMA1 HW Request is LPTIM3_IC2 */ +#define LL_LPDMA1_REQUEST_LPTIM3_UE 16U /*!< LPDMA1 HW Request is LPTIM3_UE */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRIGGER_SELECTION Trigger Selection + * @{ + */ +/* GPDMA1 Hardware Triggers */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger is EXTI_LINE0 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger is EXTI_LINE1 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger is EXTI_LINE2 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger is EXTI_LINE3 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger is EXTI_LINE4 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger is EXTI_LINE5 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger is EXTI_LINE6 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger is EXTI_LINE7 */ +#define LL_GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger is TAMP_TRG1 */ +#define LL_GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger is TAMP_TRG2 */ +#define LL_GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger is TAMP_TRG3 */ +#define LL_GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger is LPTIM1_CH1 */ +#define LL_GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger is LPTIM1_CH2 */ +#define LL_GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger is LPTIM2_CH1 */ +#define LL_GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger is LPTIM2_CH2 */ +#define LL_GPDMA1_TRIGGER_LPTIM4_OUT 15U /*!< GPDMA1 HW Trigger is LPTIM4_OUT */ +#define LL_GPDMA1_TRIGGER_COMP1_OUT 16U /*!< GPDMA1 HW Trigger is COMP1_OUT */ +#if defined(COMP2) +#define LL_GPDMA1_TRIGGER_COMP2_OUT 17U /*!< GPDMA1 HW Trigger is COMP2_OUT */ +#endif /* COMP2 */ +#define LL_GPDMA1_TRIGGER_RTC_ALRA_TRG 18U /*!< GPDMA1 HW Trigger is RTC_ALRA_TRG */ +#define LL_GPDMA1_TRIGGER_RTC_ALRB_TRG 19U /*!< GPDMA1 HW Trigger is RTC_ALRB_TRG */ +#define LL_GPDMA1_TRIGGER_RTC_WUT_TRG 20U /*!< GPDMA1 HW Trigger is RTC_WUT_TRG */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< GPDMA1 HW Trigger is GPDMA1_CH0_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< GPDMA1 HW Trigger is GPDMA1_CH1_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF 24U /*!< GPDMA1 HW Trigger is GPDMA1_CH2_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF 25U /*!< GPDMA1 HW Trigger is GPDMA1_CH3_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF 26U /*!< GPDMA1 HW Trigger is GPDMA1_CH4_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF 27U /*!< GPDMA1 HW Trigger is GPDMA1_CH5_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF 28U /*!< GPDMA1 HW Trigger is GPDMA1_CH6_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF 29U /*!< GPDMA1 HW Trigger is GPDMA1_CH7_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF 30U /*!< GPDMA1 HW Trigger is GPDMA1_CH8_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF 31U /*!< GPDMA1 HW Trigger is GPDMA1_CH9_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF 32U /*!< GPDMA1 HW Trigger is GPDMA1_CH10_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF 33U /*!< GPDMA1 HW Trigger is GPDMA1_CH11_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF 34U /*!< GPDMA1 HW Trigger is GPDMA1_CH12_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF 35U /*!< GPDMA1 HW Trigger is GPDMA1_CH13_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF 36U /*!< GPDMA1 HW Trigger is GPDMA1_CH14_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF 37U /*!< GPDMA1 HW Trigger is GPDMA1_CH15_TCF */ +#define LL_GPDMA1_TRIGGER_LPDMA1_CH0_TCF 38U /*!< GPDMA1 HW Trigger is LPDMA1_CH0_TCF */ +#define LL_GPDMA1_TRIGGER_LPDMA1_CH1_TCF 39U /*!< GPDMA1 HW Trigger is LPDMA1_CH1_TCF */ +#define LL_GPDMA1_TRIGGER_LPDMA1_CH2_TCF 40U /*!< GPDMA1 HW Trigger is LPDMA1_CH2_TCF */ +#define LL_GPDMA1_TRIGGER_LPDMA1_CH3_TCF 41U /*!< GPDMA1 HW Trigger is LPDMA1_CH3_TCF */ +#define LL_GPDMA1_TRIGGER_TIM2_TRGO 42U /*!< GPDMA1 HW Trigger is TIM2_TRGO */ +#define LL_GPDMA1_TRIGGER_TIM15_TRGO 43U /*!< GPDMA1 HW Trigger is TIM15_TRGO */ +#define LL_GPDMA1_TRIGGER_ADC4_AWD1 57U /*!< GPDMA1 HW Trigger is ADC4_AWD1 */ +#define LL_GPDMA1_TRIGGER_ADC1_AWD1 58U /*!< GPDMA1 HW Trigger is ADC1_AWD1 */ +#if defined (TIM3_TRGO_TRIGGER_SUPPORT) +#define LL_GPDMA1_TRIGGER_TIM3_TRGO 44U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ +#endif /* TIM3_TRGO_TRIGGER_SUPPORT */ +#if defined (TIM4_TRGO_TRIGGER_SUPPORT) +#define LL_GPDMA1_TRIGGER_TIM4_TRGO 45U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ +#endif /* TIM4_TRGO_TRIGGER_SUPPORT */ +#if defined (TIM5_TRGO_TRIGGER_SUPPORT) +#define LL_GPDMA1_TRIGGER_TIM5_TRGO 46U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */ +#endif /* TIM5_TRGO_TRIGGER_SUPPORT */ +#if defined (LTDC) +#define LL_GPDMA1_TRIGGER_LTDC_LI 47U /*!< GPDMA1 HW Trigger signal is LTDC_LI */ +#endif /* LTDC */ +#if defined (DSI) +#define LL_GPDMA1_TRIGGER_DSI_TE 48U /*!< GPDMA1 HW Trigger signal is DSI_TE */ +#define LL_GPDMA1_TRIGGER_DSI_ER 49U /*!< GPDMA1 HW Trigger signal is DSI_ER */ +#endif /* DSI */ +#if defined (DMA2D) +#define LL_GPDMA1_TRIGGER_DMA2D_TC 50U /*!< GPDMA1 HW Trigger signal is DMA2D_TC */ +#define LL_GPDMA1_TRIGGER_DMA2D_CTC 51U /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */ +#define LL_GPDMA1_TRIGGER_DMA2D_TW 52U /*!< GPDMA1 HW Trigger signal is DMA2D_TW */ +#endif /* DMA2D */ +#if defined (GPU2D) +#define LL_GPDMA1_TRIGGER_GPU2D_FLAG0 53U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG0 */ +#define LL_GPDMA1_TRIGGER_GPU2D_FLAG1 54U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG1 */ +#define LL_GPDMA1_TRIGGER_GPU2D_FLAG2 55U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG2 */ +#define LL_GPDMA1_TRIGGER_GPU2D_FLAG3 56U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG3 */ +#endif /* GPU2D */ +#if defined (GFXTIM) +#define LL_GPDMA1_TRIGGER_GFXTIM_EVT3 59U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT3 */ +#define LL_GPDMA1_TRIGGER_GFXTIM_EVT2 60U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT2 */ +#define LL_GPDMA1_TRIGGER_GFXTIM_EVT1 61U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT1 */ +#define LL_GPDMA1_TRIGGER_GFXTIM_EVT0 62U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT0 */ +#endif /* GFXTIM */ +#if defined (JPEG) +#define LL_GPDMA1_TRIGGER_JPEG_EOC 63U /*!< GPDMA1 HW Trigger signal is JPEG_EOC */ +#define LL_GPDMA1_TRIGGER_JPEG_IFNF 64U /*!< GPDMA1 HW Trigger signal is JPEG_IFNF */ +#define LL_GPDMA1_TRIGGER_JPEG_IFT 65U /*!< GPDMA1 HW Trigger signal is JPEG_IFT */ +#define LL_GPDMA1_TRIGGER_JPEG_OFNE 66U /*!< GPDMA1 HW Trigger signal is JPEG_OFNE */ +#define LL_GPDMA1_TRIGGER_JPEG_OFT 67U /*!< GPDMA1 HW Trigger signal is JPEG_OFT */ +#endif /* JPEG */ + +/* LPDMA1 triggers */ +#define LL_LPDMA1_TRIGGER_EXTI_LINE0 0U /*!< LPDMA1 HW Trigger is EXTI_LINE0 */ +#define LL_LPDMA1_TRIGGER_EXTI_LINE1 1U /*!< LPDMA1 HW Trigger is EXTI_LINE1 */ +#define LL_LPDMA1_TRIGGER_EXTI_LINE2 2U /*!< LPDMA1 HW Trigger is EXTI_LINE2 */ +#define LL_LPDMA1_TRIGGER_EXTI_LINE3 3U /*!< LPDMA1 HW Trigger is EXTI_LINE3 */ +#define LL_LPDMA1_TRIGGER_EXTI_LINE4 4U /*!< LPDMA1 HW Trigger is EXTI_LINE4 */ +#define LL_LPDMA1_TRIGGER_TAMP_TRG1 5U /*!< LPDMA1 HW Trigger is TAMP_TRG1 */ +#define LL_LPDMA1_TRIGGER_TAMP_TRG2 6U /*!< LPDMA1 HW Trigger is TAMP_TRG2 */ +#define LL_LPDMA1_TRIGGER_TAMP_TRG3 7U /*!< LPDMA1 HW Trigger is TAMP_TRG3 */ +#define LL_LPDMA1_TRIGGER_LPTIM1_CH1 8U /*!< LPDMA1 HW Trigger is LPTIM1_CH1 */ +#define LL_LPDMA1_TRIGGER_LPTIM1_CH2 9U /*!< LPDMA1 HW Trigger is LPTIM1_CH2 */ +#define LL_LPDMA1_TRIGGER_LPTIM3_CH1 10U /*!< LPDMA1 HW Trigger is LPTIM3_CH1 */ +#define LL_LPDMA1_TRIGGER_LPTIM4_OUT 11U /*!< LPDMA1 HW Trigger is LPTIM4_OUT */ +#define LL_LPDMA1_TRIGGER_COMP1_OUT 12U /*!< LPDMA1 HW Trigger is COMP1_OUT */ +#if defined(COMP2) +#define LL_LPDMA1_TRIGGER_COMP2_OUT 13U /*!< LPDMA1 HW Trigger is COMP2_OUT */ +#endif /* COMP2 */ +#define LL_LPDMA1_TRIGGER_RTC_ALRA_TRG 14U /*!< LPDMA1 HW Trigger is RTC_ALRA_TRG */ +#define LL_LPDMA1_TRIGGER_RTC_ALRB_TRG 15U /*!< LPDMA1 HW Trigger is RTC_ALRB_TRG */ +#define LL_LPDMA1_TRIGGER_RTC_WUT_TRG 16U /*!< LPDMA1 HW Trigger is RTC_WUT_TRG */ +#define LL_LPDMA1_TRIGGER_ADC4_AWD1 17U /*!< LPDMA1 HW Trigger is ADC4_AWD1 */ +#define LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF 18U /*!< LPDMA1 HW Trigger is LPDMA1_CH0_TCF */ +#define LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF 19U /*!< LPDMA1 HW Trigger is LPDMA1_CH1_TCF */ +#define LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF 20U /*!< LPDMA1 HW Trigger is LPDMA1_CH2_TCF */ +#define LL_LPDMA1_TRIGGER_LPDMA1_CH3_TCF 21U /*!< LPDMA1 HW Trigger is LPDMA1_CH3_TCF */ +#define LL_LPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< LPDMA1 HW Trigger is GPDMA1_CH0_TCF */ +#define LL_LPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< LPDMA1 HW Trigger is GPDMA1_CH1_TCF */ +#define LL_LPDMA1_TRIGGER_GPDMA1_CH4_TCF 24U /*!< LPDMA1 HW Trigger is GPDMA1_CH4_TCF */ +#define LL_LPDMA1_TRIGGER_GPDMA1_CH5_TCF 25U /*!< LPDMA1 HW Trigger is GPDMA1_CH5_TCF */ +#define LL_LPDMA1_TRIGGER_GPDMA1_CH6_TCF 26U /*!< LPDMA1 HW Trigger is GPDMA1_CH6_TCF */ +#define LL_LPDMA1_TRIGGER_GPDMA1_CH7_TCF 27U /*!< LPDMA1 HW Trigger is GPDMA1_CH7_TCF */ +#define LL_LPDMA1_TRIGGER_GPDMA1_CH12_TCF 28U /*!< LPDMA1 HW Trigger is GPDMA1_CH12_TCF */ +#define LL_LPDMA1_TRIGGER_GPDMA1_CH13_TCF 29U /*!< LPDMA1 HW Trigger is GPDMA1_CH13_TCF */ +#define LL_LPDMA1_TRIGGER_TIM2_TRGO 30U /*!< LPDMA1 HW Trigger is TIM2_TRGO */ +#define LL_LPDMA1_TRIGGER_TIM15_TRGO 31U /*!< LPDMA1 HW Trigger is TIM15_TRGO */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_COMMON_WRITE_READ_REGISTERS Common Write and Read Registers macros + * @{ + */ +/** + * @brief Write a value in DMA register. + * @param __INSTANCE__ DMA Instance. + * @param __REG__ Register to be written. + * @param __VALUE__ Value to be written in the register. + * @retval None. + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register. + * @param __INSTANCE__ DMA Instance. + * @param __REG__ Register to be read. + * @retval Register value. + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely + * @{ + */ +/** + * @brief Convert DMAx_Channely into DMAx. + * @param __CHANNEL_INSTANCE__ DMAx_Channely. + * @retval DMAx. + */ +#define LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ + (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)GPDMA1_Channel15)) ? LPDMA1 : GPDMA1) + +/** + * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y. + * @param __CHANNEL_INSTANCE__ DMAx_Channely. + * @retval LL_DMA_CHANNEL_y. + */ +#define LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ + (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)LPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)LPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)LPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)LPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel8)) ? LL_DMA_CHANNEL_8 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel9)) ? LL_DMA_CHANNEL_9 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel10)) ? LL_DMA_CHANNEL_10 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel11)) ? LL_DMA_CHANNEL_11 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel12)) ? LL_DMA_CHANNEL_12 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel13)) ? LL_DMA_CHANNEL_13 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel14)) ? LL_DMA_CHANNEL_14 : \ + LL_DMA_CHANNEL_15) + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely. + * @param __DMA_INSTANCE__ DMAx. + * @param __CHANNEL__ LL_DMA_CHANNEL_y. + * @retval DMAx_Channely. + */ +#define LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ + ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \ + ? GPDMA1_Channel0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \ + ? LPDMA1_Channel0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \ + ? GPDMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \ + ? LPDMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \ + ? GPDMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \ + ? LPDMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \ + ? GPDMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \ + ? LPDMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \ + ? GPDMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \ + ? GPDMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \ + ? GPDMA1_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \ + ? GPDMA1_Channel7 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) \ + ? GPDMA1_Channel8 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_9))) \ + ? GPDMA1_Channel9 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_10)))\ + ? GPDMA1_Channel10 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_11)))\ + ? GPDMA1_Channel11 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_12)))\ + ? GPDMA1_Channel12 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_13)))\ + ? GPDMA1_Channel13 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_14)))\ + ? GPDMA1_Channel14 : GPDMA1_Channel15) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR EN LL_DMA_EnableChannel + * @param DMAx DMAx Instance. + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); +} + +/** + * @brief Disable channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR EN LL_DMA_DisableChannel + * @param DMAx DMAx Instance. + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, + (DMA_CCR_SUSP | DMA_CCR_RESET)); +} + +/** + * @brief Check if channel is enabled or disabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR EN LL_DMA_IsEnabledChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN) + == (DMA_CCR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Reset channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR RESET LL_DMA_ResetChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ResetChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_RESET); +} + +/** + * @brief Suspend channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSP LL_DMA_SuspendChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SuspendChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP); +} + +/** + * @brief Resume channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSP LL_DMA_ResumeChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ResumeChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP); +} + +/** + * @brief Check if channel is suspended. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSP LL_DMA_IsSuspendedChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsSuspendedChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP) + == (DMA_CCR_SUSP)) ? 1UL : 0UL); +} + +/** + * @brief Set linked-list base address. + * @note This API is used for all available DMA channels. + * @rmtoll CLBAR LBA LL_DMA_SetLinkedListBaseAddr + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param LinkedListBaseAddr Between 0 to 0xFFFF0000 (where the 4 LSB bytes + * are always 0) + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t LinkedListBaseAddr) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLBAR, + DMA_CLBAR_LBA, + (LinkedListBaseAddr & DMA_CLBAR_LBA)); +} + +/** + * @brief Get linked-list base address. + * @note This API is used for all available DMA channels. + * @rmtoll CLBAR LBA LL_DMA_GetLinkedListBaseAddr + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Value between 0 to 0xFFFF0000 (where the 4 LSB bytes are always 0) + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA)); +} + +/** + * @brief Configure all parameters linked to channel control. + * @note This API is used for all available DMA channels. + * For LPDMA channels, LAP field programming is discarded. + * @rmtoll CCR PRIO LL_DMA_ConfigControl\n + * CCR LAP LL_DMA_ConfigControl\n + * CCR LSM LL_DMA_ConfigControl + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT or @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT or + * @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT or @ref LL_DMA_HIGH_PRIORITY + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 or @ref LL_DMA_LINK_ALLOCATED_PORT1 + * @arg @ref LL_DMA_LSM_FULL_EXECUTION or @ref LL_DMA_LSM_1LINK_EXECUTION + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration); +} + +/** + * @brief Set priority level. + * @note This API is used for all available DMA channels. + * @rmtoll CCR PRIO LL_DMA_SetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT + * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT + * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT + * @arg @ref LL_DMA_HIGH_PRIORITY + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO, Priority); +} + +/** + * @brief Get Channel priority level. + * @note This API is used for all available DMA channels. + * @rmtoll CCR PRIO LL_DMA_GetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT + * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT + * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT + * @arg @ref LL_DMA_HIGH_PRIORITY + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO)); +} + +/** + * @brief Set linked-list allocated port. + * @note This API is not used for LPDMA channels. + * @rmtoll CCR LAP LL_DMA_SetLinkAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param LinkAllocatedPort This parameter can be one of the following values: + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkAllocatedPort) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_LAP, LinkAllocatedPort); +} + +/** + * @brief Get linked-list allocated port. + * @note This API is not used for LPDMA channels. + * @rmtoll CCR LAP LL_DMA_GetLinkAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LAP)); +} + +/** + * @brief Set link step mode. + * @note This API is used for all available DMA channels. + * @rmtoll CCR LSM LL_DMA_SetLinkStepMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param LinkStepMode This parameter can be one of the following values: + * @arg @ref LL_DMA_LSM_FULL_EXECUTION + * @arg @ref LL_DMA_LSM_1LINK_EXECUTION + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkStepMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM, LinkStepMode); +} + +/** + * @brief Get Link step mode. + * @note This API is used for all available DMA channels. + * @rmtoll CCR LSM LL_DMA_GetLinkStepMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_LSM_FULL_EXECUTION + * @arg @ref LL_DMA_LSM_1LINK_EXECUTION + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM)); +} + +/** + * @brief Configure data transfer. + * @note This API is used for all available DMA channels. + * For LPDMA channels DAP, DHX, DBX, SAP, SBX fields programming is + * discarded. + * @rmtoll CTR1 DAP LL_DMA_ConfigTransfer\n + * CTR1 DHX LL_DMA_ConfigTransfer\n + * CTR1 DBX LL_DMA_ConfigTransfer\n + * CTR1 DINC LL_DMA_ConfigTransfer\n + * CTR1 SAP LL_DMA_ConfigTransfer\n + * CTR1 SBX LL_DMA_ConfigTransfer\n + * CTR1 PAM LL_DMA_ConfigTransfer\n + * CTR1 SINC LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 or @ref LL_DMA_DEST_ALLOCATED_PORT1 + * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE or @ref LL_DMA_DEST_HALFWORD_EXCHANGE + * @arg @ref LL_DMA_DEST_BYTE_PRESERVE or @ref LL_DMA_DEST_BYTE_EXCHANGE + * @arg @ref LL_DMA_SRC_BYTE_PRESERVE or @ref LL_DMA_SRC_BYTE_EXCHANGE + * @arg @ref LL_DMA_DEST_FIXED or @ref LL_DMA_DEST_INCREMENT + * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE or @ref LL_DMA_DEST_DATAWIDTH_HALFWORD or + * @ref LL_DMA_DEST_DATAWIDTH_WORD + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 or @ref LL_DMA_SRC_ALLOCATED_PORT1 + * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD or @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD or + * @ref LL_DMA_DATA_PACK_UNPACK + * @arg @ref LL_DMA_SRC_FIXED or @ref LL_DMA_SRC_INCREMENT + * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE or @ref LL_DMA_SRC_DATAWIDTH_HALFWORD or + * @ref LL_DMA_SRC_DATAWIDTH_WORD + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR1, + DMA_CTR1_DAP | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_DINC | DMA_CTR1_SINC | \ + DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); +} + +/** + * @brief Configure source and destination burst length. + * @note This API is not used for LPDMA channels. + * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength\n + * @rmtoll CTR1 SBL_1 LL_DMA_SetDestBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcBurstLength Between 1 to 64 + * @param DestBurstLength Between 1 to 64 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength, + uint32_t DestBurstLength) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR1, + (DMA_CTR1_SBL_1 | DMA_CTR1_DBL_1), (((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1) | \ + (((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1)); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure all secure parameters linked to DMA channel. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR SEC LL_DMA_ConfigChannelSecure\n + * @rmtoll CTR1 SSEC LL_DMA_ConfigChannelSecure\n + * @rmtoll CTR1 DSEC LL_DMA_ConfigChannelSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_CHANNEL_NSEC or @ref LL_DMA_CHANNEL_SEC + * @arg @ref LL_DMA_CHANNEL_SRC_NSEC or @ref LL_DMA_CHANNEL_SRC_SEC + * @arg @ref LL_DMA_CHANNEL_DEST_NSEC or @ref LL_DMA_CHANNEL_DEST_SEC + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << Channel), ((Configuration & LL_DMA_CHANNEL_SEC) << Channel)); + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + (DMA_CTR1_SSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC))); +} + +/** + * @brief Enable security attribute of the DMA transfer to the destination. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DSEC LL_DMA_EnableChannelDestSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC); +} + +/** + * @brief Disable security attribute of the DMA transfer to the destination. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DSEC LL_DMA_DisableChannelDestSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC); +} +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Check security attribute of the DMA transfer to the destination. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DSEC LL_DMA_IsEnabledChannelDestSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC) + == (DMA_CTR1_DSEC)) ? 1UL : 0UL); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable security attribute of the DMA transfer from the source. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SSEC LL_DMA_EnableChannelSrcSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); +} + +/** + * @brief Disable security attribute of the DMA transfer from the source. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SSEC LL_DMA_DisableChannelSrcSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); +} +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Check security attribute of the DMA transfer from the source. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SSEC LL_DMA_IsEnabledChannelSrcSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC) + == (DMA_CTR1_SSEC)) ? 1UL : 0UL); +} + +/** + * @brief Set destination allocated port. + * @note This API is not used for LPDMA channels. + * @rmtoll CTR1 DAP LL_DMA_SetDestAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestAllocatedPort This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAllocatedPort) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP, + DestAllocatedPort); +} + +/** + * @brief Get destination allocated port. + * @note This API is not used for LPDMA channels. + * @rmtoll CTR1 DAP LL_DMA_GetDestAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP)); +} + +/** + * @brief Set destination half-word exchange. + * @note This API is not used for LPDMA channels. + * @rmtoll CTR1 DHX LL_DMA_SetDestHWordExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestHWordExchange This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE + * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestHWordExchange) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX, + DestHWordExchange); +} + +/** + * @brief Get destination half-word exchange. + * @note This API is not used for LPDMA channels. + * @rmtoll CTR1 DHX LL_DMA_GetDestHWordExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE + * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX)); +} + +/** + * @brief Set destination byte exchange. + * @note This API is not used for LPDMA channels. + * @rmtoll CTR1 DBX LL_DMA_SetDestByteExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestByteExchange This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_BYTE_PRESERVE + * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestByteExchange) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX, + DestByteExchange); +} + +/** + * @brief Get destination byte exchange. + * @note This API is not used for LPDMA channels. + * @rmtoll CTR1 DBX LL_DMA_GetDestByteExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_BYTE_PRESERVE + * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX)); +} + +/** + * @brief Set source byte exchange. + * @note This API is not used for LPDMA channels. + * @rmtoll CTR1 SBX LL_DMA_SetSrcByteExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcByteExchange This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_BYTE_PRESERVE + * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcByteExchange) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX, + SrcByteExchange); +} + +/** + * @brief Get source byte exchange. + * @note This API is not used for LPDMA channels. + * @rmtoll CTR1 SBX LL_DMA_GetSrcByteExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_BYTE_PRESERVE + * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX)); +} + +/** + * @brief Set destination burst length. + * @note This API is not used for LPDMA channels. + * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestBurstLength Between 1 to 64 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestBurstLength) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBL_1, + ((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1); +} + +/** + * @brief Get destination burst length. + * @note This API is not used for LPDMA channels. + * @rmtoll CTR1 DBL_1 LL_DMA_GetDestBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 1 to 64. + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U); +} + +/** + * @brief Set destination increment mode. + * @note This API is not used for LPDMA channels. + * @rmtoll CTR1 DINC LL_DMA_SetDestIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestInc This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_FIXED + * @arg @ref LL_DMA_DEST_INCREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestInc) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC, DestInc); +} + +/** + * @brief Get destination increment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DINC LL_DMA_GetDestIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_FIXED + * @arg @ref LL_DMA_DEST_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC)); +} + +/** + * @brief Set destination data width. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DDW_LOG2 LL_DMA_SetDestDataWidth + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestDataWidth This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE + * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD + * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestDataWidth) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2, + DestDataWidth); +} + +/** + * @brief Get destination data width. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DDW_LOG2 LL_DMA_GetDestDataWidth + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE + * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD + * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2)); +} + +/** + * @brief Set source allocated port. + * @note This API is not used for LPDMA channels. + * @rmtoll CTR1 SAP LL_DMA_SetSrcAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcAllocatedPort This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAllocatedPort) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP, + SrcAllocatedPort); +} + +/** + * @brief Get source allocated port. + * @note This API is not used for LPDMA channels. + * @rmtoll CTR1 SAP LL_DMA_GetSrcAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP)); +} + +/** + * @brief Set data alignment mode. + * @note This API is used for all available DMA channels. + * For LPDMA channels, PAM field is reduced to one bit. + * @rmtoll CTR1 PAM LL_DMA_SetDataAlignment + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DataAlignment This parameter can be one of the following values: + * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD + * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD + * @arg @ref LL_DMA_DATA_PACK_UNPACK (This value is not allowed for LPDMA channels) + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DataAlignment) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM, + DataAlignment); +} + +/** + * @brief Get data alignment mode. + * @note This API is used for all available DMA channels. + * For LPDMA channels, PAM field is reduced to one bit. + * @rmtoll CTR1 PAM LL_DMA_GetDataAlignment + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD + * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD + * @arg @ref LL_DMA_DATA_PACK_UNPACK (This value is not allowed for LPDMA channels) + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM)); +} + +/** + * @brief Set source burst length. + * @note This API is not used for LPDMA channels. + * @rmtoll CTR1 SBL_1 LL_DMA_SetSrcBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcBurstLength Between 1 to 64 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBL_1, + ((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1); +} + +/** + * @brief Get source burst length. + * @note This API is not used for LPDMA channels. + * @rmtoll CTR1 SBL_1 LL_DMA_GetSrcBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 1 to 64 + * @retval None. + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U); +} + +/** + * @brief Set source increment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SINC LL_DMA_SetSrcIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcInc This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_FIXED + * @arg @ref LL_DMA_SRC_INCREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcInc) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC, SrcInc); +} + +/** + * @brief Get source increment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SINC LL_DMA_GetSrcIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_FIXED + * @arg @ref LL_DMA_SRC_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC)); +} + +/** + * @brief Set source data width. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SDW_LOG2 LL_DMA_SetSrcDataWidth + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcDataWidth This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE + * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD + * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcDataWidth) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2, + SrcDataWidth); +} + +/** + * @brief Get Source Data width. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SDW_LOG2 LL_DMA_GetSrcDataWidth + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE + * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD + * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2)); +} + +/** + * @brief Configure channel transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TCEM LL_DMA_ConfigChannelTransfer\n + * CTR2 TRIGPOL LL_DMA_ConfigChannelTransfer\n + * CTR2 TRIGM LL_DMA_ConfigChannelTransfer\n + * CTR2 BREQ LL_DMA_ConfigChannelTransfer\n + * CTR2 DREQ LL_DMA_ConfigChannelTransfer\n + * CTR2 SWREQ LL_DMA_ConfigChannelTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_TCEM_BLK_TRANSFER or @ref LL_DMA_TCEM_RPT_BLK_TRANSFER or + * @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER or @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER + * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST or @ref LL_DMA_HWREQUEST_BLK + * @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_TRIG_POLARITY_RISING or + * @ref LL_DMA_TRIG_POLARITY_FALLING + * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER or @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER or + * @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER or @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or + * @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, + (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_BREQ), + Configuration); +} + +/** + * @brief Set transfer event mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TCEM LL_DMA_SetTransferEventMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param TransferEventMode This parameter can be one of the following values: + * @arg @ref LL_DMA_TCEM_BLK_TRANSFER + * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER + * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER + * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TransferEventMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, + DMA_CTR2_TCEM, + TransferEventMode); +} + +/** + * @brief Get transfer event mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TCEM LL_DMA_GetTransferEventMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_TCEM_BLK_TRANSFER + * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER + * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER + * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER + */ +__STATIC_INLINE uint32_t LL_DMA_GetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM)); +} + +/** + * @brief Set trigger polarity. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGPOL LL_DMA_SetTriggerPolarity + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param TriggerPolarity This parameter can be one of the following values: + * @arg @ref LL_DMA_TRIG_POLARITY_MASKED + * @arg @ref LL_DMA_TRIG_POLARITY_RISING + * @arg @ref LL_DMA_TRIG_POLARITY_FALLING + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerPolarity) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL, + TriggerPolarity); +} + +/** + * @brief Get trigger polarity. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGPOL LL_DMA_GetTriggerPolarity + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_TRIG_POLARITY_MASKED + * @arg @ref LL_DMA_TRIG_POLARITY_RISING + * @arg @ref LL_DMA_TRIG_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, + DMA_CTR2_TRIGPOL)); +} + +/** + * @brief Set trigger Mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGM LL_DMA_SetTriggerMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param TriggerMode This parameter can be one of the following values: + * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER + * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels) + * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER + * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, + DMA_CTR2_TRIGM, + TriggerMode); +} + +/** + * @brief Get trigger Mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGM LL_DMA_GetTriggerMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER + * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels) + * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER + * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER + */ +__STATIC_INLINE uint32_t LL_DMA_GetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM)); +} + +/** + * @brief Set destination hardware and software transfer request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 DREQ LL_DMA_SetDataTransferDirection\n + * @rmtoll CTR2 SWREQ LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH (This value is not allowed for LPDMA channels) + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY (This value is not allowed for LPDMA channels) + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + DMA_CTR2_DREQ | DMA_CTR2_SWREQ, Direction); +} + +/** + * @brief Get destination hardware and software transfer request. + * @note This API is used for all available DMA channels. + * For LPDMA channels, DREQ fields programming is discarded. + * @rmtoll CTR2 DREQ LL_DMA_GetDataTransferDirection\n + * @rmtoll CTR2 SWREQ LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH (This value is not allowed for LPDMA channels) + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY (This value is not allowed for LPDMA channels) + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + DMA_CTR2_DREQ | DMA_CTR2_SWREQ)); +} + +/** + * @brief Set block hardware request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 BREQ LL_DMA_SetBlkHWRequest\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkHWRequest This parameter can be one of the following values: + * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST + * @arg @ref LL_DMA_HWREQUEST_BLK + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkHWRequest) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ, + BlkHWRequest); +} + +/** + * @brief Get block hardware request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 BREQ LL_DMA_GetBlkHWRequest\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST + * @arg @ref LL_DMA_HWREQUEST_BLK + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ)); +} + +/** + * @brief Set hardware request. + * @note This API is used for all available DMA channels. + * For LPDMA channels, REQSEL fields is reduced to 5 bits. + * @rmtoll CTR2 REQSEL LL_DMA_SetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_GPDMA1_REQUEST_ADC1 + * @arg @ref LL_GPDMA1_REQUEST_ADC4 + * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH1 + * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP + * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C1_EVC + * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C2_EVC + * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C3_EVC + * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C4_EVC + * @arg @ref LL_GPDMA1_REQUEST_USART1_RX + * @arg @ref LL_GPDMA1_REQUEST_USART1_TX + * @arg @ref LL_GPDMA1_REQUEST_USART2_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART2_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART3_RX + * @arg @ref LL_GPDMA1_REQUEST_USART3_TX + * @arg @ref LL_GPDMA1_REQUEST_UART4_RX + * @arg @ref LL_GPDMA1_REQUEST_UART4_TX + * @arg @ref LL_GPDMA1_REQUEST_UART5_RX + * @arg @ref LL_GPDMA1_REQUEST_UART5_TX + * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX + * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX + * @arg @ref LL_GPDMA1_REQUEST_SAI1_A + * @arg @ref LL_GPDMA1_REQUEST_SAI1_B + * @arg @ref LL_GPDMA1_REQUEST_SAI2_A (*) + * @arg @ref LL_GPDMA1_REQUEST_SAI2_B (*) + * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1 + * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM8_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM8_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP + * @arg @ref LL_GPDMA1_REQUEST_DCMI_PSSI + * @arg @ref LL_GPDMA1_REQUEST_AES_IN + * @arg @ref LL_GPDMA1_REQUEST_AES_OUT + * @arg @ref LL_GPDMA1_REQUEST_HASH_IN + * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT0 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT1 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT2 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT3 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT4 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT5 + * @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0 + * @arg @ref LL_GPDMA1_REQUEST_FMAC_READ + * @arg @ref LL_GPDMA1_REQUEST_FMAC_WRITE + * @arg @ref LL_GPDMA1_REQUEST_CORDIC_READ + * @arg @ref LL_GPDMA1_REQUEST_CORDIC_WRITE + * @arg @ref LL_GPDMA1_REQUEST_SAES_IN + * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE + * @arg @ref LL_GPDMA1_REQUEST_HSPI1 (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C5_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C5_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C5_EVC (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C6_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C6_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C6_EVC (*) + * @arg @ref LL_GPDMA1_REQUEST_USART6_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART6_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_ADC2 (*) + * @arg @ref LL_GPDMA1_REQUEST_JPEG_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_JPEG_TX (*) + * + * @arg @ref LL_LPDMA1_REQUEST_LPUART1_RX + * @arg @ref LL_LPDMA1_REQUEST_LPUART1_TX + * @arg @ref LL_LPDMA1_REQUEST_SPI3_RX + * @arg @ref LL_LPDMA1_REQUEST_SPI3_TX + * @arg @ref LL_LPDMA1_REQUEST_I2C3_RX + * @arg @ref LL_LPDMA1_REQUEST_I2C3_TX + * @arg @ref LL_LPDMA1_REQUEST_I2C3_EVC + * @arg @ref LL_LPDMA1_REQUEST_ADC4 + * @arg @ref LL_LPDMA1_REQUEST_DAC1_CH1 + * @arg @ref LL_LPDMA1_REQUEST_DAC1_CH2 + * @arg @ref LL_LPDMA1_REQUEST_ADF1_FLT0 + * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC1 + * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC2 + * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_UE + * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC1 + * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC2 + * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_UE + * + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, + DMA_CTR2_REQSEL, Request); +} + +/** + * @brief Get hardware request. + * @note This API is used for all available DMA channels. + * For LPDMA channels, REQSEL fields is reduced to 5 bits. + * @rmtoll CTR2 REQSEL LL_DMA_GetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPDMA1_REQUEST_ADC1 + * @arg @ref LL_GPDMA1_REQUEST_ADC4 + * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH1 + * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP + * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C1_EVC + * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C2_EVC + * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C3_EVC + * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C4_EVC + * @arg @ref LL_GPDMA1_REQUEST_USART1_RX + * @arg @ref LL_GPDMA1_REQUEST_USART1_TX + * @arg @ref LL_GPDMA1_REQUEST_USART2_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART2_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART3_RX + * @arg @ref LL_GPDMA1_REQUEST_USART3_TX + * @arg @ref LL_GPDMA1_REQUEST_UART4_RX + * @arg @ref LL_GPDMA1_REQUEST_UART4_TX + * @arg @ref LL_GPDMA1_REQUEST_UART5_RX + * @arg @ref LL_GPDMA1_REQUEST_UART5_TX + * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX + * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX + * @arg @ref LL_GPDMA1_REQUEST_SAI1_A + * @arg @ref LL_GPDMA1_REQUEST_SAI1_B + * @arg @ref LL_GPDMA1_REQUEST_SAI2_A (*) + * @arg @ref LL_GPDMA1_REQUEST_SAI2_B (*) + * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1 + * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM8_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM8_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP + * @arg @ref LL_GPDMA1_REQUEST_DCMI_PSSI + * @arg @ref LL_GPDMA1_REQUEST_AES_IN + * @arg @ref LL_GPDMA1_REQUEST_AES_OUT + * @arg @ref LL_GPDMA1_REQUEST_HASH_IN + * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT0 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT1 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT2 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT3 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT4 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT5 + * @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0 + * @arg @ref LL_GPDMA1_REQUEST_FMAC_READ + * @arg @ref LL_GPDMA1_REQUEST_FMAC_WRITE + * @arg @ref LL_GPDMA1_REQUEST_CORDIC_READ + * @arg @ref LL_GPDMA1_REQUEST_CORDIC_WRITE + * @arg @ref LL_GPDMA1_REQUEST_SAES_IN + * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE + * @arg @ref LL_GPDMA1_REQUEST_HSPI1 (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C5_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C5_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C5_EVC (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C6_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C6_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C6_EVC (*) + * @arg @ref LL_GPDMA1_REQUEST_USART6_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART6_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_ADC2 (*) + * @arg @ref LL_GPDMA1_REQUEST_JPEG_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_JPEG_TX (*) + * + * @arg @ref LL_LPDMA1_REQUEST_LPUART1_RX + * @arg @ref LL_LPDMA1_REQUEST_LPUART1_TX + * @arg @ref LL_LPDMA1_REQUEST_SPI3_RX + * @arg @ref LL_LPDMA1_REQUEST_SPI3_TX + * @arg @ref LL_LPDMA1_REQUEST_I2C3_RX + * @arg @ref LL_LPDMA1_REQUEST_I2C3_TX + * @arg @ref LL_LPDMA1_REQUEST_I2C3_EVC + * @arg @ref LL_LPDMA1_REQUEST_ADC4 + * @arg @ref LL_LPDMA1_REQUEST_DAC1_CH1 + * @arg @ref LL_LPDMA1_REQUEST_DAC1_CH2 + * @arg @ref LL_LPDMA1_REQUEST_ADF1_FLT0 + * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC1 + * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC2 + * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_UE + * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC1 + * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC2 + * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_UE + * + * @note (*) Availability depends on devices. + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, + DMA_CTR2_REQSEL)); +} + +/** + * @brief Set hardware trigger. + * @note This API is used for all available DMA channels. + * For LPDMA channels, TRIGSEL fields is reduced to 5 bits. + * @rmtoll CTR2 TRIGSEL LL_DMA_SetHWTrigger + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Trigger This parameter can be one of the following values: + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3 + * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1 + * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2 + * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_OUT + * @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT + * @arg @ref LL_GPDMA1_TRIGGER_COMP2_OUT (*) + * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG + * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG + * @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF + * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH0_TCF + * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH1_TCF + * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH2_TCF + * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH3_TCF + * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO (*) + * @arg @ref LL_GPDMA1_TRIGGER_TIM4_TRGO (*) + * @arg @ref LL_GPDMA1_TRIGGER_TIM5_TRGO (*) + * @arg @ref LL_GPDMA1_TRIGGER_LTDC_LI (*) + * @arg @ref LL_GPDMA1_TRIGGER_DSI_TE (*) + * @arg @ref LL_GPDMA1_TRIGGER_DSI_ER (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TC (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_CTC (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TW (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG0 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG1 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG2 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG3 (*) + * @arg @ref LL_GPDMA1_TRIGGER_ADC4_AWD1 + * @arg @ref LL_GPDMA1_TRIGGER_ADC1_AWD1 + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT3 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT2 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT1 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT0 (*) + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_EOC (*) + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFNF (*) + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFT (*) + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFNE (*) + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFT (*) + * + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE0 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE1 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE2 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE3 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE4 + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG1 + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG2 + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG3 + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM3_CH1 + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM4_OUT + * @arg @ref LL_LPDMA1_TRIGGER_COMP1_OUT + * @arg @ref LL_LPDMA1_TRIGGER_COMP2_OUT (*) + * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRA_TRG + * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRB_TRG + * @arg @ref LL_LPDMA1_TRIGGER_RTC_WUT_TRG + * @arg @ref LL_LPDMA1_TRIGGER_ADC4_AWD1 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH3_TCF + * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH0_TCF + * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH1_TCF + * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH4_TCF + * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH5_TCF + * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH6_TCF + * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH7_TCF + * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH12_TCF + * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH13_TCF + * @arg @ref LL_LPDMA1_TRIGGER_TIM2_TRGO + * @arg @ref LL_LPDMA1_TRIGGER_TIM15_TRGO + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Trigger) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, + DMA_CTR2_TRIGSEL, + (Trigger << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL); +} + +/** + * @brief Get hardware triggers. + * @note This API is used for all available DMA channels. + * For LPDMA channels, TRIGSEL fields is reduced to 5 bits. + * @rmtoll CTR2 TRIGSEL LL_DMA_GetHWTrigger + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3 + * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1 + * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2 + * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_OUT + * @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT + * @arg @ref LL_GPDMA1_TRIGGER_COMP2_OUT (*) + * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG + * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG + * @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF + * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH0_TCF + * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH1_TCF + * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH2_TCF + * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH3_TCF + * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO (*) + * @arg @ref LL_GPDMA1_TRIGGER_TIM4_TRGO (*) + * @arg @ref LL_GPDMA1_TRIGGER_TIM5_TRGO (*) + * @arg @ref LL_GPDMA1_TRIGGER_LTDC_LI (*) + * @arg @ref LL_GPDMA1_TRIGGER_DSI_TE (*) + * @arg @ref LL_GPDMA1_TRIGGER_DSI_ER (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TC (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_CTC (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TW (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG0 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG1 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG2 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG3 (*) + * @arg @ref LL_GPDMA1_TRIGGER_ADC4_AWD1 + * @arg @ref LL_GPDMA1_TRIGGER_ADC1_AWD1 + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT3 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT2 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT1 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT0 (*) + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_EOC (*) + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFNF (*) + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFT (*) + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFNE (*) + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFT (*) + * + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE0 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE1 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE2 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE3 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE4 + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG1 + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG2 + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG3 + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM3_CH1 + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM4_OUT + * @arg @ref LL_LPDMA1_TRIGGER_COMP1_OUT + * @arg @ref LL_LPDMA1_TRIGGER_COMP2_OUT (*) + * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRA_TRG + * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRB_TRG + * @arg @ref LL_LPDMA1_TRIGGER_RTC_WUT_TRG + * @arg @ref LL_LPDMA1_TRIGGER_ADC4_AWD1 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH3_TCF + * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH0_TCF + * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH1_TCF + * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH4_TCF + * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH5_TCF + * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH6_TCF + * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH7_TCF + * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH12_TCF + * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH13_TCF + * @arg @ref LL_LPDMA1_TRIGGER_TIM2_TRGO + * @arg @ref LL_LPDMA1_TRIGGER_TIM15_TRGO + * @note (*) Availability depends on devices. + */ +__STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, + DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos); +} + +/** + * @brief Configure addresses update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRDDEC LL_DMA_ConfigBlkRptAddrUpdate\n + * CBR1 BRSDEC LL_DMA_ConfigBlkRptAddrUpdate\n + * CBR1 DDEC LL_DMA_ConfigBlkRptAddrUpdate\n + * CBR1 SDEC LL_DMA_ConfigBlkRptAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT + * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT + * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT or @ref LL_DMA_BURST_DEST_ADDR_DECREMENT + * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT or @ref LL_DMA_BURST_SRC_ADDR_DECREMENT + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_BRDDEC | DMA_CBR1_BRSDEC | DMA_CBR1_DDEC | DMA_CBR1_SDEC, Configuration); +} + +/** + * @brief Configure DMA Block number of data and repeat Count. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BNDT LL_DMA_ConfigBlkCounters\n + * CBR1 BRC LL_DMA_ConfigBlkCounters + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkDataLength Block transfer length + Value between 0 to 0x0000FFFF + * @param BlkRptCount Block repeat counter + * Value between 0 to 0x000007FF + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigBlkCounters(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength, + uint32_t BlkRptCount) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + (DMA_CBR1_BNDT | DMA_CBR1_BRC), (BlkDataLength | (BlkRptCount << DMA_CBR1_BRC_Pos))); +} + +/** + * @brief Set block repeat destination address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRDDEC LL_DMA_SetBlkRptDestAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkRptDestAddrUpdate This parameter can be one of the following values: + * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT + * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t BlkRptDestAddrUpdate) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_BRDDEC, + BlkRptDestAddrUpdate); +} + +/** + * @brief Get block repeat destination address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRDDEC LL_DMA_GetBlkRptDestAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT + * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_BRDDEC)); +} + +/** + * @brief Set block repeat source address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRSDEC LL_DMA_SetBlkRptSrcAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkRptSrcAddrUpdate This parameter can be one of the following values: + * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT + * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t BlkRptSrcAddrUpdate) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_BRSDEC, + BlkRptSrcAddrUpdate); +} + +/** + * @brief Get block repeat source address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRSDEC LL_DMA_GetBlkRptSrcAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT + * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_BRSDEC)); +} + +/** + * @brief Set destination address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 DDEC LL_DMA_SetDestAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestAddrUpdate This parameter can be one of the following values: + * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT + * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrUpdate) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_DDEC, + DestAddrUpdate); +} + +/** + * @brief Get destination address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 DDEC LL_DMA_GetDestAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT + * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_DDEC)); +} + +/** + * @brief Set source address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 SDEC LL_DMA_SetSrcAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcAddrUpdate This parameter can be one of the following values: + * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT + * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrUpdate) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_SDEC, + SrcAddrUpdate); +} + +/** + * @brief Get source address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 SDEC LL_DMA_GetSrcAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT + * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_SDEC)); +} + +/** + * @brief Set block repeat count. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRC LL_DMA_SetBlkRptCount + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkRptCount Block repeat counter + * Value between 0 to 0x000007FF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptCount) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_BRC, + (BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC); +} + +/** + * @brief Get block repeat count. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRC LL_DMA_GetBlkRptCount + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x000007FF + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos); +} + +/** + * @brief Set block data length in bytes to transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CBR1 BNDT LL_DMA_SetBlkDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkDataLength Between 0 to 0x0000FFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_BNDT, + BlkDataLength); +} + +/** + * @brief Get block data length in bytes to transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CBR1 BNDT LL_DMA_GetBlkDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x0000FFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_BNDT)); +} + +/** + * @brief Configure the source and destination addresses. + * @note This API is used for all available DMA channels. + * @note This API must not be called when the DMA Channel is enabled. + * @rmtoll CSAR SA LL_DMA_ConfigAddresses\n + * CDAR DA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcAddress Between 0 to 0xFFFFFFFF + * @param DestAddress Between 0 to 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t + DestAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CDAR, DestAddress); +} + +/** + * @brief Set source address. + * @note This API is used for all available DMA channels. + * @rmtoll CSAR SA LL_DMA_SetSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcAddress Between 0 to 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSAR, SrcAddress); +} + +/** + * @brief Get source address. + * @note This API is used for all available DMA channels. + * @rmtoll CSAR SA LL_DMA_GetSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSAR)); +} + +/** + * @brief Set destination address. + * @note This API is used for all available DMA channels. + * @rmtoll CDAR DA LL_DMA_SetDestAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestAddress Between 0 to 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CDAR, DestAddress); +} + +/** + * @brief Get destination address. + * @note This API is used for all available DMA channels. + * @rmtoll CDAR DA LL_DMA_GetDestAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CDAR)); +} + +/** + * @brief Configure source and destination addresses offset. + * @note This API is used only for 2D addressing channels. + * @note This API must not be called when the DMA Channel is enabled. + * @rmtoll CTR3 DAO LL_DMA_ConfigAddrUpdateValue\n + * CTR3 SAO LL_DMA_ConfigAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestAddrOffset Between 0 to 0x00001FFF + * @param SrcAddrOffset Between 0 to 0x00001FFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset, + uint32_t DestAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR3, + (SrcAddrOffset & DMA_CTR3_SAO) | ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO)); +} + +/** + * @brief Set destination address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CTR3 DAO LL_DMA_SetDestAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestAddrOffset Between 0 to 0x00001FFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR3, + DMA_CTR3_DAO, + ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO)); +} + +/** + * @brief Get destination address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CDAR DAO LL_DMA_GetDestAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x00001FFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR3, + DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos); +} + +/** + * @brief Set source address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CTR3 SAO LL_DMA_SetSrcAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcAddrOffset Between 0 to 0x00001FFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR3, + DMA_CTR3_SAO, + SrcAddrOffset & DMA_CTR3_SAO); +} + +/** + * @brief Get source address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CTR3 SAO LL_DMA_GetSrcAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x00001FFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR3, + DMA_CTR3_SAO)); +} + +/** + * @brief Configure the block repeated source and destination addresses offset. + * @note This API is used only for 2D addressing channels. + * @note This API must not be called when the DMA Channel is enabled. + * @rmtoll CBR2 BRDAO LL_DMA_ConfigBlkRptAddrUpdateValue\n + * CBR2 BRSAO LL_DMA_ConfigBlkRptAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF + * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t BlkRptSrcAddrOffset, uint32_t BlkRptDestAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR2, + ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO) | (BlkRptSrcAddrOffset & DMA_CBR2_BRSAO)); +} + +/** + * @brief Set block repeated destination address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR2 BRDAO LL_DMA_SetBlkRptDestAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t BlkRptDestAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR2, + DMA_CBR2_BRDAO, + ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO)); +} + +/** + * @brief Get block repeated destination address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR2 BRDAO LL_DMA_GetBlkRptDestAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x0000FFFF. + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR2, + DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos); +} + +/** + * @brief Set block repeated source address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR2 BRSAO LL_DMA_SetBlkRptSrcAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t BlkRptSrcAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR2, + DMA_CBR2_BRSAO, + BlkRptSrcAddrOffset); +} + +/** + * @brief Get block repeated source address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR2 BRSAO LL_DMA_GetBlkRptSrcAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x0000FFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR2, + DMA_CBR2_BRSAO)); +} + +/** + * @brief Configure registers update and node address offset during the link transfer. + * @note This API is used for all available DMA channels. + * For linear addressing channels, UT3 and UB2 fields are discarded. + * @rmtoll CLLR UT1 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UT2 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UB1 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR USA LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UDA LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UT3 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UB2 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR ULL LL_DMA_ConfigLinkUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param RegistersUpdate This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_UPDATE_CTR1 + * @arg @ref LL_DMA_UPDATE_CTR2 + * @arg @ref LL_DMA_UPDATE_CBR1 + * @arg @ref LL_DMA_UPDATE_CSAR + * @arg @ref LL_DMA_UPDATE_CDAR + * @arg @ref LL_DMA_UPDATE_CTR3 (This value is allowed only for 2D addressing channels) + * @arg @ref LL_DMA_UPDATE_CBR2 (This value is allowed only for 2D addressing channels) + * @arg @ref LL_DMA_UPDATE_CLLR + * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigLinkUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t RegistersUpdate, + uint32_t LinkedListAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ + DMA_CLLR_UB2 | DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA))); +} + +/** + * @brief Enable CTR1 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT1 LL_DMA_EnableCTR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UT1); +} + +/** + * @brief Disable CTR1 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT1 LL_DMA_DisableCTR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UT1); +} + +/** + * @brief Check if CTR1 update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT1 LL_DMA_IsEnabledCTR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UT1) + == (DMA_CLLR_UT1)) ? 1UL : 0UL); +} + +/** + * @brief Enable CTR2 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT2 LL_DMA_EnableCTR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UT2); +} + +/** + * @brief Disable CTR2 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT2 LL_DMA_DisableCTR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UT2); +} + +/** + * @brief Check if CTR2 update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT2 LL_DMA_IsEnabledCTR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UT2) + == (DMA_CLLR_UT2)) ? 1UL : 0UL); +} + +/** + * @brief Enable CBR1 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UB1 LL_DMA_EnableCBR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UB1); +} + +/** + * @brief Disable CBR1 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UB1 LL_DMA_DisableCBR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UB1); +} + +/** + * @brief Check if CBR1 update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UB1 LL_DMA_IsEnabledCBR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UB1) + == (DMA_CLLR_UB1)) ? 1UL : 0UL); +} + +/** + * @brief Enable CSAR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR USA LL_DMA_EnableCSARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_USA); +} + +/** + * @brief Disable CSAR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR USA LL_DMA_DisableCSARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_USA); +} + +/** + * @brief Check if CSAR update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR USA LL_DMA_IsEnabledCSARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_USA) + == (DMA_CLLR_USA)) ? 1UL : 0UL); +} + +/** + * @brief Enable CDAR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UDA LL_DMA_EnableCDARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UDA); +} + +/** + * @brief Disable CDAR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UDA LL_DMA_DisableCDARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UDA); +} + +/** + * @brief Check if CDAR update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UDA LL_DMA_IsEnabledCDARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UDA) + == (DMA_CLLR_UDA)) ? 1UL : 0UL); +} + +/** + * @brief Enable CTR3 update during the link transfer. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UT3 LL_DMA_EnableCTR3Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UT3); +} + +/** + * @brief Disable CTR3 update during the link transfer. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UT3 LL_DMA_DisableCTR3Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UT3); +} + +/** + * @brief Check if CTR3 update during the link transfer is enabled. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UT3 LL_DMA_IsEnabledCTR3Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UT3) + == (DMA_CLLR_UT3)) ? 1UL : 0UL); +} + +/** + * @brief Enable CBR2 update during the link transfer. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UB2 LL_DMA_EnableCBR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UB2); +} + +/** + * @brief Disable CBR2 update during the link transfer. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UB2 LL_DMA_DisableCBR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UB2); +} + +/** + * @brief Check if CBR2 update during the link transfer is enabled. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UB2 LL_DMA_IsEnabledCBR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UB2) + == (DMA_CLLR_UB2)) ? 1UL : 0UL); +} + +/** + * @brief Enable CLLR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR ULL LL_DMA_EnableCLLRUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_ULL); +} + +/** + * @brief Disable CLLR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR ULL LL_DMA_DisableCLLRUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_ULL); +} + +/** + * @brief Check if CLLR update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR ULL LL_DMA_IsEnabledCLLRUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_ULL) + == (DMA_CLLR_ULL)) ? 1UL : 0UL); +} + +/** + * @brief Set linked list address offset. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR LA LL_DMA_SetLinkedListAddrOffset + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t LinkedListAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_LA, + (LinkedListAddrOffset & DMA_CLLR_LA)); +} + +/** + * @brief Get linked list address offset. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR LA LL_DMA_GetLinkedListAddrOffset + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x0000FFFC. + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_LA) >> DMA_CLLR_LA_Pos); +} + +/** + * @brief Get FIFO level. + * @note This API is not used for LPDMA channels. + * @rmtoll CSR FIFOL LL_DMA_GetFIFOLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x000000FF. + */ +__STATIC_INLINE uint32_t LL_DMA_GetFIFOLevel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, + DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable the DMA channel secure attribute. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR SECx LL_DMA_EnableChannelSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))); +} + +/** + * @brief Disable the DMA channel secure attribute. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR SECx LL_DMA_DisableChannelSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))); +} +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Check if DMA channel secure is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR SECx LL_DMA_IsEnabledChannelSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) + == (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); +} + +/** + * @brief Enable the DMA channel privilege attribute. + * @note This API is used for all available DMA channels. + * @rmtoll PRIVCFGR PRIVx LL_DMA_EnableChannelPrivilege + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))); +} + +/** + * @brief Disable the DMA channel privilege attribute. + * @note This API is used for all available DMA channels. + * @rmtoll PRIVCFGR PRIVx LL_DMA_DisableChannelPrivilege + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))); +} + +/** + * @brief Check if DMA Channel privilege is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll PRIVCFGR PRIVx LL_DMA_IsEnabledChannelPrivilege + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) + == (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable the DMA channel lock attributes. + * @note This API is used for all available DMA channels. + * @rmtoll RCFGLOCKR LOCKx LL_DMA_EnableChannelLockAttribute + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelLockAttribute(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))); +} +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Check if DMA channel attributes are locked. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR LOCKx LL_DMA_IsEnabledChannelLockAttribute + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) + == (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management Flag Management + * @{ + */ + +/** + * @brief Clear trigger overrun flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR TOF LL_DMA_ClearFlag_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_TOF); +} + +/** + * @brief Clear suspension flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR SUSPF LL_DMA_ClearFlag_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_SUSPF); +} + +/** + * @brief Clear user setting error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR USEF LL_DMA_ClearFlag_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_USEF); +} + +/** + * @brief Clear link transfer error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR ULEF LL_DMA_ClearFlag_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_ULEF); +} + +/** + * @brief Clear data transfer error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR DTEF LL_DMA_ClearFlag_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_DTEF); +} + +/** + * @brief Clear half transfer flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR HTF LL_DMA_ClearFlag_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_HTF); +} + +/** + * @brief Clear transfer complete flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR TCF LL_DMA_ClearFlag_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_TCF); +} + +/** + * @brief Get trigger overrun flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR TOF LL_DMA_IsActiveFlag_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, + DMA_CSR_TOF) + == (DMA_CSR_TOF)) ? 1UL : 0UL); +} + +/** + * @brief Get suspension flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR SUSPF LL_DMA_IsActiveFlag_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, + DMA_CSR_SUSPF) + == (DMA_CSR_SUSPF)) ? 1UL : 0UL); +} + +/** + * @brief Get user setting error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR USEF LL_DMA_IsActiveFlag_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, + DMA_CSR_USEF) + == (DMA_CSR_USEF)) ? 1UL : 0UL); +} + +/** + * @brief Get user setting error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR ULEF LL_DMA_IsActiveFlag_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, + DMA_CSR_ULEF) + == (DMA_CSR_ULEF)) ? 1UL : 0UL); +} + +/** + * @brief Get data transfer error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR DTEF LL_DMA_IsActiveFlag_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, + DMA_CSR_DTEF) + == (DMA_CSR_DTEF)) ? 1UL : 0UL); +} + +/** + * @brief Get half transfer flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR HTF LL_DMA_IsActiveFlag_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, + DMA_CSR_HTF) + == (DMA_CSR_HTF)) ? 1UL : 0UL); +} + +/** + * @brief Get transfer complete flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR TCF LL_DMA_IsActiveFlag_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, + DMA_CSR_TCF) + == (DMA_CSR_TCF)) ? 1UL : 0UL); +} + +/** + * @brief Get idle flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR IDLEF LL_DMA_IsActiveFlag_IDLE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, + DMA_CSR_IDLEF) + == (DMA_CSR_IDLEF)) ? 1UL : 0UL); +} + +/** + * @brief Check if nsecure masked interrupt is active. + * @note This API is used for all available DMA channels. + * @rmtoll MISR MISx LL_DMA_IsActiveFlag_MIS + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_MIS(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->MISR, (DMA_MISR_MIS0 << (Channel & 0x0FU))) + == (DMA_MISR_MIS0 << (Channel & 0x0FU))) ? 1UL : 0UL); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Check if secure masked interrupt is active. + * @note This API is used for all available DMA channels. + * @rmtoll SMISR MISx LL_DMA_IsActiveFlag_SMIS + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->SMISR, (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) + == (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); +} +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable trigger overrun interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TOIE LL_DMA_EnableIT_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_TOIE); +} + +/** + * @brief Enable suspension interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSPIE LL_DMA_EnableIT_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_SUSPIE); +} + +/** + * @brief Enable user setting error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR USEIE LL_DMA_EnableIT_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_USEIE); +} + +/** + * @brief Enable update link transfer error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR ULEIE LL_DMA_EnableIT_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_ULEIE); +} + +/** + * @brief Enable data transfer error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR DTEIE LL_DMA_EnableIT_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_DTEIE); +} + +/** + * @brief Enable half transfer complete interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_HTIE); +} + +/** + * @brief Enable transfer complete interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_TCIE); +} + +/** + * @brief Disable trigger overrun interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TOIE LL_DMA_DisableIT_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_TOIE); +} + +/** + * @brief Disable suspension interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSPIE LL_DMA_DisableIT_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_SUSPIE); +} + +/** + * @brief Disable user setting error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR USEIE LL_DMA_DisableIT_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_USEIE); +} + +/** + * @brief Disable update link transfer error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR ULEIE LL_DMA_DisableIT_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_ULEIE); +} + +/** + * @brief Disable data transfer error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR DTEIE LL_DMA_DisableIT_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_DTEIE); +} + +/** + * @brief Disable half transfer complete interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_HTIE); +} + +/** + * @brief Disable transfer complete interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_TCIE); +} + +/** + * @brief Check if trigger overrun interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TOIE LL_DMA_IsEnabledIT_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_TOIE) + == DMA_CCR_TOIE) ? 1UL : 0UL); +} + +/** + * @brief Check if suspension interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSPIE LL_DMA_IsEnabledIT_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_SUSPIE) + == DMA_CCR_SUSPIE) ? 1UL : 0UL); +} + +/** + * @brief Check if user setting error interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR USEIE LL_DMA_IsEnabledIT_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_USEIE) + == DMA_CCR_USEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if update link transfer error interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR ULEIE LL_DMA_IsEnabledIT_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_ULEIE) + == DMA_CCR_ULEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if data transfer error interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR DTEIE LL_DMA_IsEnabledIT_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_DTEIE) + == DMA_CCR_DTEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if half transfer complete interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_HTIE) + == DMA_CCR_HTIE) ? 1UL : 0UL); +} + +/** + * @brief Check if transfer complete interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_TCIE) + == DMA_CCR_TCIE) ? 1UL : 0UL); +} +/** + * @} + */ + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); + +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); +void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct); +void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct); + +uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, + LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct); +uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); + +uint32_t LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode); +void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx, + LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx); +void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* GPDMA1 || LPDMA1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32U5xx_LL_DMA_H */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_exti.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_exti.h new file mode 100644 index 000000000..e021b83b4 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_exti.h @@ -0,0 +1,1507 @@ +/** + ****************************************************************************** + * @file stm32u5xx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_LL_EXTI_H +#define STM32U5xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx.h" + +/** @addtogroup STM32U5xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +#define LL_EXTI_REGISTER_PINPOS_SHFT 16U /*!< Define used to shift pin position in EXTICR register */ + +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */ +#define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */ +#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR1_IM18) +#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ +#endif /* EXTI_IMR1_IM18 */ +#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ +#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */ +#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */ +#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */ +#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ +#if defined(EXTI_IMR1_IM24) +#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */ +#endif /* EXTI_IMR1_IM24 */ +#if defined(EXTI_IMR1_IM25) +#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ +#endif /* EXTI_IMR1_IM25 */ +#if defined(EXTI_IMR1_IM24) && defined(EXTI_IMR1_IM25) +#define LL_EXTI_LINE_ALL_0_31 0x03FFFFFFU /*!< ALL Extended line */ +#else +#define LL_EXTI_LINE_ALL_0_31 0x00FFFFFFU /*!< ALL Extended line */ +#endif /* defined(EXTI_IMR1_IM24) && defined(EXTI_IMR1_IM25) */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE 0x00000000U /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup SYSTEM_LL_EC_EXTI_PORT EXTI EXTI PORT + * @{ + */ +#define LL_EXTI_EXTI_PORTA 0U /*!< EXTI PORT A */ +#define LL_EXTI_EXTI_PORTB EXTI_EXTICR1_EXTI0_0 /*!< EXTI PORT B */ +#define LL_EXTI_EXTI_PORTC EXTI_EXTICR1_EXTI0_1 /*!< EXTI PORT C */ +#define LL_EXTI_EXTI_PORTD (EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT D */ +#define LL_EXTI_EXTI_PORTE EXTI_EXTICR1_EXTI0_2 /*!< EXTI PORT E */ +#if defined(GPIOF) +#define LL_EXTI_EXTI_PORTF (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT F */ +#endif /* GPIOF */ +#define LL_EXTI_EXTI_PORTG (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1) /*!< EXTI PORT G */ +#define LL_EXTI_EXTI_PORTH (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT H */ +#if defined(GPIOI) +#define LL_EXTI_EXTI_PORTI EXTI_EXTICR1_EXTI0_3 /*!< EXTI PORT I */ +#endif /* GPIOI */ +#if defined(GPIOJ) +#define LL_EXTI_EXTI_PORTJ (EXTI_EXTICR1_EXTI0_3 | EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT J */ +#endif /* GPIOJ */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_LINE EXTI EXTI LINE + * @{ + */ +#define LL_EXTI_EXTI_LINE0 ((0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_EXTI_EXTI_LINE1 ((8U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_EXTI_EXTI_LINE2 ((16U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_16 | EXTICR[0] */ +#define LL_EXTI_EXTI_LINE3 ((24U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_24 | EXTICR[0] */ +#define LL_EXTI_EXTI_LINE4 ((0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_EXTI_EXTI_LINE5 ((8U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_EXTI_EXTI_LINE6 ((16U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_16 | EXTICR[1] */ +#define LL_EXTI_EXTI_LINE7 ((24U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_24 | EXTICR[1] */ +#define LL_EXTI_EXTI_LINE8 ((0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_EXTI_EXTI_LINE9 ((8U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_EXTI_EXTI_LINE10 ((16U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_16 | EXTICR[2] */ +#define LL_EXTI_EXTI_LINE11 ((24U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_24 | EXTICR[2] */ +#define LL_EXTI_EXTI_LINE12 ((0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_EXTI_EXTI_LINE13 ((8U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_EXTI_EXTI_LINE14 ((16U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_16 | EXTICR[3] */ +#define LL_EXTI_EXTI_LINE15 ((24U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_24 | EXTICR[3] */ +/** + * @} + */ +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR1, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR1, ExtiLine); + +} + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR1, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); + +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR1, ExtiLine); + +} + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR1, ExtiLine); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER1, ExtiLine); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Falling Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR1 FPIFx LL_EXTI_IsActiveFallingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Read ExtLine Combination Falling Flag for Lines in range 0 to 31 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR1 FPIFx LL_EXTI_ReadFallingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->FPR1, ExtiLine)); +} + +/** + * @brief Clear ExtLine Falling Flags for Lines in range 0 to 31 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR1 FPIFx LL_EXTI_ClearFallingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->FPR1, ExtiLine); +} + +/** + * @brief Check if the ExtLine Rising Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR1 RPIFx LL_EXTI_IsActiveRisingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Read ExtLine Combination Rising Flag for Lines in range 0 to 31 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR1 RPIFx LL_EXTI_ReadRisingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->RPR1, ExtiLine)); +} + +/** + * @brief Clear ExtLine Rising Flags for Lines in range 0 to 31 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR1 RPIFx LL_EXTI_ClearRisingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearRisingFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->RPR1, ExtiLine); +} + +/** + * @} + */ +/** @defgroup EXTI_LL_EF_Config EF configuration functions + * @{ + */ + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll EXTI_EXTICR1 EXTI0 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI1 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI2 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI3 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI4 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI5 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI6 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI7 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI8 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI9 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI10 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI11 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI12 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI13 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI14 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI15 LL_EXTI_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_EXTI_EXTI_PORTA + * @arg @ref LL_EXTI_EXTI_PORTB + * @arg @ref LL_EXTI_EXTI_PORTC + * @arg @ref LL_EXTI_EXTI_PORTD + * @arg @ref LL_EXTI_EXTI_PORTE + * @arg @ref LL_EXTI_EXTI_PORTF (*) + * @arg @ref LL_EXTI_EXTI_PORTG + * @arg @ref LL_EXTI_EXTI_PORTH + * @arg @ref LL_EXTI_EXTI_PORTI (*) + * @arg @ref LL_EXTI_EXTI_PORTJ (*) + * + * (*) value not defined in all devices + * @param Line This parameter can be one of the following values: + * @arg @ref LL_EXTI_EXTI_LINE0 + * @arg @ref LL_EXTI_EXTI_LINE1 + * @arg @ref LL_EXTI_EXTI_LINE2 + * @arg @ref LL_EXTI_EXTI_LINE3 + * @arg @ref LL_EXTI_EXTI_LINE4 + * @arg @ref LL_EXTI_EXTI_LINE5 + * @arg @ref LL_EXTI_EXTI_LINE6 + * @arg @ref LL_EXTI_EXTI_LINE7 + * @arg @ref LL_EXTI_EXTI_LINE8 + * @arg @ref LL_EXTI_EXTI_LINE9 + * @arg @ref LL_EXTI_EXTI_LINE10 + * @arg @ref LL_EXTI_EXTI_LINE11 + * @arg @ref LL_EXTI_EXTI_LINE12 + * @arg @ref LL_EXTI_EXTI_LINE13 + * @arg @ref LL_EXTI_EXTI_LINE14 + * @arg @ref LL_EXTI_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(EXTI->EXTICR[Line & 0x03U], EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT), \ + Port << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll EXTI_EXTICR1 EXTI0 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR1 EXTI1 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR1 EXTI2 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR1 EXTI3 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR2 EXTI4 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR2 EXTI5 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR2 EXTI6 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR2 EXTI7 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR3 EXTI8 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR3 EXTI9 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR3 EXTI10 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR3 EXTI11 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR4 EXTI12 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR4 EXTI13 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR4 EXTI14 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR4 EXTI15 LL_EXTI_GetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_EXTI_EXTI_LINE0 + * @arg @ref LL_EXTI_EXTI_LINE1 + * @arg @ref LL_EXTI_EXTI_LINE2 + * @arg @ref LL_EXTI_EXTI_LINE3 + * @arg @ref LL_EXTI_EXTI_LINE4 + * @arg @ref LL_EXTI_EXTI_LINE5 + * @arg @ref LL_EXTI_EXTI_LINE6 + * @arg @ref LL_EXTI_EXTI_LINE7 + * @arg @ref LL_EXTI_EXTI_LINE8 + * @arg @ref LL_EXTI_EXTI_LINE9 + * @arg @ref LL_EXTI_EXTI_LINE10 + * @arg @ref LL_EXTI_EXTI_LINE11 + * @arg @ref LL_EXTI_EXTI_LINE12 + * @arg @ref LL_EXTI_EXTI_LINE13 + * @arg @ref LL_EXTI_EXTI_LINE14 + * @arg @ref LL_EXTI_EXTI_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_EXTI_EXTI_PORTA + * @arg @ref LL_EXTI_EXTI_PORTB + * @arg @ref LL_EXTI_EXTI_PORTC + * @arg @ref LL_EXTI_EXTI_PORTD + * @arg @ref LL_EXTI_EXTI_PORTE + * @arg @ref LL_EXTI_EXTI_PORTF (*) + * @arg @ref LL_EXTI_EXTI_PORTG + * @arg @ref LL_EXTI_EXTI_PORTH + * @arg @ref LL_EXTI_EXTI_PORTI (*) + * @arg @ref LL_EXTI_EXTI_PORTJ (*) + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line) +{ + return (uint32_t)(READ_BIT(EXTI->EXTICR[Line & 0x03U], + (EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT))) >> + (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); +} +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Secure_Management Secure_Management + * @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + * @brief Enable ExtiLine Secure attribute for Lines in range 0 to 31 + * @rmtoll SECCFGR1 SECx LL_EXTI_EnableSecure_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableSecure_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SECCFGR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Secure attribute for Lines in range 0 to 31 + * @rmtoll SECCFGR1 SECx LL_EXTI_DisableSecure_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableSecure_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->SECCFGR1, ExtiLine); +} + +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Indicate if ExtiLine Secure attribute is enabled for Lines in range 0 to 31 + * @rmtoll SECCFGR1 SECx LL_EXTI_IsEnabledSecure_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledSecure_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->SECCFGR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Privilege_Management Privilege_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Privilege attribute for Lines in range 0 to 31 + * @rmtoll PRIVCFGR1 PRIVx LL_EXTI_EnablePrivilege_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnablePrivilege_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->PRIVCFGR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Privilege attribute for Lines in range 0 to 31 + * @rmtoll PRIVCFGR1 PRIVx LL_EXTI_DisablePrivilege_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisablePrivilege_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->PRIVCFGR1, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine Privilege attribute is enabled for Lines in range 0 to 31 + * @rmtoll PRIVCFGR1 PRIVx LL_EXTI_IsEnabledPrivilege_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledPrivilege_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PRIVCFGR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the secure and privilege configuration registers. + * @rmtoll LOCKR LOCK LL_EXTI_LockAttributes + * @retval None + */ +__STATIC_INLINE void LL_EXTI_LockAttributes(void) +{ + SET_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); +} + +/** + * @brief Return the secure and privilege configuration registers LOCK status + * @rmtoll LOCKR LOCK LL_EXTI_GetLockAttributes + * @retval 1 if the secure and privilege configuration registers have been locked else 0. + */ +__STATIC_INLINE uint32_t LL_EXTI_GetLockAttributes(void) +{ + return READ_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +ErrorStatus LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_LL_EXTI_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_gpio.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_gpio.h new file mode 100644 index 000000000..730888c30 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_gpio.h @@ -0,0 +1,1183 @@ +/** + ****************************************************************************** + * @file stm32u5xx_ll_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_LL_GPIO_H +#define STM32U5xx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx.h" + +/** @addtogroup STM32U5xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || \ + defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) + +/** @defgroup GPIO_LL GPIO + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function + @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function + @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function + @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function + @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function + @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | \ + GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | \ + GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 | \ + GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \ + GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \ + GPIO_BSRR_BS15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */ +#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */ +/** + * @} + */ +#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW +#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM +#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH +#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ +#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ +#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ +#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ +#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ +#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ +#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ +#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)), + (Mode << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos))); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos))) >> + (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin)); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)), + (Speed << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos))); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << \ + (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos))) >> \ + (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)), + (Pull << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos))); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << \ + (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos))) >> \ + (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)), + (Alternate << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos))) >> + (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)), + (Alternate << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos))) >> + (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)); +} + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx) +{ + return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * Value between 0 and 0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BRR, PinMask); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); +} + +/** + * @brief Enable speed optimization for several pin of dedicated port. + * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding + * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must + * be kept at reset value. + * @note It must be used only if the I/O supply voltage is below 2.7 V. + * @rmtoll HSLVR HSLVy LL_GPIO_EnableHighSPeedLowVoltage + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + SET_BIT(GPIOx->HSLVR, PinMask); +} + + +/** + * @brief Disable speed optimization for several pin of dedicated port. + * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding + * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must + * be kept at reset value. + * @note It must be used only if the I/O supply voltage is below 2.7 V. + * @rmtoll HSLVR HSLVy LL_GPIO_DisableHighSPeedLowVoltage + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + CLEAR_BIT(GPIOx->HSLVR, PinMask); +} + +/** + * @brief Return if speed optimization for several pin of dedicated port is enabled or not. + * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding + * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must + * be kept at reset value. + * @note It must be used only if the I/O supply voltage is below 2.7 V. + * @rmtoll HSLVR HSLVy LL_GPIO_IsEnabledHighSPeedLowVoltage + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsEnabledHighSPeedLowVoltage(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->HSLVR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + * @brief Enable secure write only access for several pin of dedicated port. + * @rmtoll SECCFGR SECy LL_GPIO_EnablePinSecure + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_EnablePinSecure(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + SET_BIT(GPIOx->SECCFGR, PinMask); +} + + +/** + * @brief Disable secure write only access for several pin of dedicated port. + * @rmtoll SECCFGR SECy LL_GPIO_DisablePinSecure + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_DisablePinSecure(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + CLEAR_BIT(GPIOx->SECCFGR, PinMask); +} + +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Return if secure write only access for several pin of dedicated port is enabled or not. + * @rmtoll SECCFGR SECy LL_GPIO_IsEnabledPinSecure + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsEnabledPinSecure(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->SECCFGR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || \ + defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ)*/ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_LL_GPIO_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_icache.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_icache.h new file mode 100644 index 000000000..f419b8131 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_icache.h @@ -0,0 +1,782 @@ +/** + ****************************************************************************** + * @file stm32u5xx_ll_icache.h + * @author MCD Application Team + * @brief Header file of ICACHE LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion ------------------------------------*/ +#ifndef STM32U5xx_LL_ICACHE_H +#define STM32U5xx_LL_ICACHE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -----------------------------------------------------------------*/ +#include "stm32u5xx.h" + +/** @addtogroup STM32U5xx_LL_Driver + * @{ + */ + +#if defined(ICACHE) + +/** @defgroup ICACHE_LL ICACHE + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ICACHE_LL_REGION_CONFIG ICACHE Exported Configuration structure + * @{ + */ + +/** + * @brief LL ICACHE region configuration structure definition + */ +typedef struct +{ + uint32_t BaseAddress; /*!< Configures the C-AHB base address to be remapped */ + + uint32_t RemapAddress; /*!< Configures the remap address to be remapped */ + + uint32_t Size; /*!< Configures the region size. + This parameter can be a value of @ref ICACHE_LL_EC_Region_Size */ + + uint32_t TrafficRoute; /*!< Selects the traffic route. + This parameter can be a value of @ref ICACHE_LL_EC_Traffic_Route */ + + uint32_t OutputBurstType; /*!< Selects the output burst type. + This parameter can be a value of @ref ICACHE_LL_EC_Output_Burst_Type */ +} LL_ICACHE_RegionTypeDef; + +/** + * @} + */ + +/* Exported constants -------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Exported_Constants ICACHE Exported Constants + * @{ + */ + +/** @defgroup ICACHE_LL_EC_WaysSelection Ways selection + * @{ + */ +#define LL_ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */ +#define LL_ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Monitor_Type Monitor type + * @{ + */ +#define LL_ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitor counter */ +#define LL_ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitor counter */ +#define LL_ICACHE_MONITOR_ALL (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< All monitors counters */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_ICACHE_ReadReg function + * @{ + */ +#define LL_ICACHE_SR_BUSYF ICACHE_SR_BUSYF /*!< Busy flag */ +#define LL_ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF /*!< Busy end flag */ +#define LL_ICACHE_SR_ERRF ICACHE_SR_ERRF /*!< Cache error flag */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_ICACHE_WriteReg function + * @{ + */ +#define LL_ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF /*!< Busy end flag */ +#define LL_ICACHE_FCR_CERRF ICACHE_FCR_CERRF /*!< Cache error flag */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_ICACHE_ReadReg and LL_ICACHE_WriteReg functions + * @{ + */ +#define LL_ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE /*!< Busy end interrupt */ +#define LL_ICACHE_IER_ERRIE ICACHE_IER_ERRIE /*!< Cache error interrupt */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Region Remapped Region number + * @{ + */ +#define LL_ICACHE_REGION_0 0U /*!< Region 0 */ +#define LL_ICACHE_REGION_1 1U /*!< Region 1 */ +#define LL_ICACHE_REGION_2 2U /*!< Region 2 */ +#define LL_ICACHE_REGION_3 3U /*!< Region 3 */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Region_Size Remapped Region size + * @{ + */ +#define LL_ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */ +#define LL_ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */ +#define LL_ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */ +#define LL_ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */ +#define LL_ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */ +#define LL_ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */ +#define LL_ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Traffic_Route Remapped Traffic route + * @{ + */ +#define LL_ICACHE_MASTER1_PORT 0U /*!< Master1 port */ +#define LL_ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Output_Burst_Type Remapped Output burst type + * @{ + */ +#define LL_ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */ +#define LL_ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ----------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Exported_Macros ICACHE Exported Macros + * @{ + */ + +/** @defgroup ICACHE_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in ICACHE register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_ICACHE_WriteReg(__REG__, __VALUE__) WRITE_REG(ICACHE->__REG__, (__VALUE__)) + +/** + * @brief Read a value in ICACHE register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_ICACHE_ReadReg(__REG__) READ_REG(ICACHE->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Exported_Functions ICACHE Exported Functions + * @{ + */ + +/** @defgroup ICACHE_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable the ICACHE. + * @rmtoll CR EN LL_ICACHE_Enable + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_Enable(void) +{ + SET_BIT(ICACHE->CR, ICACHE_CR_EN); +} + +/** + * @brief Disable the ICACHE. + * @rmtoll CR EN LL_ICACHE_Disable + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_Disable(void) +{ + CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); +} + +/** + * @brief Return if ICACHE is enabled or not. + * @rmtoll CR EN LL_ICACHE_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabled(void) +{ + return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) == (ICACHE_CR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Select the ICACHE operating mode. + * @rmtoll CR WAYSEL LL_ICACHE_SetMode + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_ICACHE_1WAY + * @arg @ref LL_ICACHE_2WAYS + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetMode(uint32_t Mode) +{ + MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, Mode); +} + +/** + * @brief Get the selected ICACHE operating mode. + * @rmtoll CR WAYSEL LL_ICACHE_GetMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_ICACHE_1WAY + * @arg @ref LL_ICACHE_2WAYS + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetMode(void) +{ + return (READ_BIT(ICACHE->CR, ICACHE_CR_WAYSEL)); +} + +/** + * @brief Invalidate the ICACHE. + * @note Until the BSYEND flag is set, the cache is bypassed. + * @rmtoll CR CACHEINV LL_ICACHE_Invalidate + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_Invalidate(void) +{ + SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_Monitors Monitors + * @{ + */ + +/** + * @brief Enable the hit/miss monitor(s). + * @rmtoll CR HITMEN LL_ICACHE_EnableMonitors + * @rmtoll CR MISSMEN LL_ICACHE_EnableMonitors + * @param Monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_EnableMonitors(uint32_t Monitors) +{ + SET_BIT(ICACHE->CR, Monitors); +} + +/** + * @brief Disable the hit/miss monitor(s). + * @rmtoll CR HITMEN LL_ICACHE_DisableMonitors + * @rmtoll CR MISSMEN LL_ICACHE_DisableMonitors + * @param Monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_DisableMonitors(uint32_t Monitors) +{ + CLEAR_BIT(ICACHE->CR, Monitors); +} + +/** + * @brief Check if the monitor(s) is(are) enabled or disabled. + * @rmtoll CR HITMEN LL_ICACHE_IsEnabledMonitors + * @rmtoll CR MISSMEN LL_ICACHE_IsEnabledMonitors + * @param Monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval State of parameter value (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledMonitors(uint32_t Monitors) +{ + return ((READ_BIT(ICACHE->CR, Monitors) == (Monitors)) ? 1UL : 0UL); +} + +/** + * @brief Reset the hit/miss monitor(s). + * @rmtoll CR HITMRST LL_ICACHE_ResetMonitors + * @rmtoll CR MISSMRST LL_ICACHE_ResetMonitors + * @param Monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_ResetMonitors(uint32_t Monitors) +{ + /* Reset */ + SET_BIT(ICACHE->CR, (Monitors << 2U)); + /* Release reset */ + CLEAR_BIT(ICACHE->CR, (Monitors << 2U)); +} + +/** + * @brief Get the Hit monitor. + * @note Upon reaching the 32-bit maximum value, hit monitor does not wrap. + * @rmtoll HMONR HITMON LL_ICACHE_GetHitMonitor + * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetHitMonitor(void) +{ + return (ICACHE->HMONR); +} + +/** + * @brief Get the Miss monitor. + * @note Upon reaching the 16-bit maximum value, miss monitor does not wrap. + * @rmtoll MMONR MISSMON LL_ICACHE_GetMissMonitor + * @retval Value between Min_Data=0 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetMissMonitor(void) +{ + return (ICACHE->MMONR); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable BSYEND interrupt. + * @rmtoll IER BSYENDIE LL_ICACHE_EnableIT_BSYEND + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_EnableIT_BSYEND(void) +{ + SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); +} + +/** + * @brief Disable BSYEND interrupt. + * @rmtoll IER BSYENDIE LL_ICACHE_DisableIT_BSYEND + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_DisableIT_BSYEND(void) +{ + CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); +} + +/** + * @brief Check if the BSYEND Interrupt is enabled or disabled. + * @rmtoll IER BSYENDIE LL_ICACHE_IsEnabledIT_BSYEND + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_BSYEND(void) +{ + return ((READ_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE) == (ICACHE_IER_BSYENDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable ERR interrupt. + * @rmtoll IER ERRIE LL_ICACHE_EnableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_EnableIT_ERR(void) +{ + SET_BIT(ICACHE->IER, ICACHE_IER_ERRIE); +} + +/** + * @brief Disable ERR interrupt. + * @rmtoll IER ERRIE LL_ICACHE_DisableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_DisableIT_ERR(void) +{ + CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE); +} + +/** + * @brief Check if the ERR Interrupt is enabled or disabled. + * @rmtoll IER ERRIE LL_ICACHE_IsEnabledIT_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_ERR(void) +{ + return ((READ_BIT(ICACHE->IER, ICACHE_IER_ERRIE) == (ICACHE_IER_ERRIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Indicate the status of an ongoing operation flag. + * @rmtoll SR BUSYF LL_ICACHE_IsActiveFlag_BUSY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BUSY(void) +{ + return ((READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == (ICACHE_SR_BUSYF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of an operation end flag. + * @rmtoll SR BSYEND LL_ICACHE_IsActiveFlag_BSYEND + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BSYEND(void) +{ + return ((READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == (ICACHE_SR_BSYENDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of an error flag. + * @rmtoll SR ERRF LL_ICACHE_IsActiveFlag_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_ERR(void) +{ + return ((READ_BIT(ICACHE->SR, ICACHE_SR_ERRF) == (ICACHE_SR_ERRF)) ? 1UL : 0UL); +} + +/** + * @brief Clear busy end of operation flag. + * @rmtoll FCR CBSYENDF LL_ICACHE_ClearFlag_BSYEND + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_ClearFlag_BSYEND(void) +{ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); +} + +/** + * @brief Clear error flag. + * @rmtoll FCR ERRF LL_ICACHE_ClearFlag_ERR + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_ClearFlag_ERR(void) +{ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_REGION_Management REGION_Management + * @{ + */ + +/** + * @brief Enable the remapped memory region. + * @note The region must have been already configured. + * @rmtoll CRRx REN LL_ICACHE_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_EnableRegion(uint32_t Region) +{ + SET_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_REN); +} + +/** + * @brief Disable the remapped memory region. + * @rmtoll CRRx REN LL_ICACHE_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_DisableRegion(uint32_t Region) +{ + CLEAR_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_REN); +} + +/** + * @brief Return if remapped memory region is enabled or not. + * @rmtoll CRRx REN LL_ICACHE_IsEnabledRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(uint32_t Region) +{ + return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_REN) == (ICACHE_CRRx_REN)) ? 1UL : 0UL); +} + +/** + * @brief Select the memory remapped region base address. + * @note The useful bits depends on RSIZE as described in the Reference Manual. + * @rmtoll CRRx BASEADDR LL_ICACHE_SetRegionBaseAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param Address Alias address in the Code region + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(uint32_t Region, uint32_t Address) +{ + MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_BASEADDR, ((Address & 0x1FFFFFFFU) >> 21U)); +} + +/** + * @brief Get the memory remapped region base address. + * @note The base address is the alias in the Code region. + * @note The useful bits depends on RSIZE as described in the Reference Manual. + * @rmtoll CRRx BASEADDR LL_ICACHE_GetRegionBaseAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Address Alias address in the Code region + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionBaseAddress(uint32_t Region) +{ + return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_BASEADDR) << 21U); +} + +/** + * @brief Select the memory remapped region address. + * @note The useful bits depends on RSIZE as described in the Reference Manual. + * @rmtoll CRRx REMAPADDR LL_ICACHE_SetRegionRemapAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param Address Memory address to remap + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(uint32_t Region, uint32_t Address) +{ + MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_REMAPADDR, ((Address >> 21U) << ICACHE_CRRx_REMAPADDR_Pos)); +} + +/** + * @brief Get the memory remapped region address. + * @note The useful bits depends on RSIZE as described in the Reference Manual. + * @rmtoll CRRx REMAPADDR LL_ICACHE_GetRegionRemapAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Address Remapped memory address + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionRemapAddress(uint32_t Region) +{ + return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_REMAPADDR) >> ICACHE_CRRx_REMAPADDR_Pos) << 21U); +} + +/** + * @brief Select the memory remapped region size. + * @rmtoll CRRx RSIZE LL_ICACHE_SetRegionSize + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param Size This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGIONSIZE_2MB + * @arg @ref LL_ICACHE_REGIONSIZE_4MB + * @arg @ref LL_ICACHE_REGIONSIZE_8MB + * @arg @ref LL_ICACHE_REGIONSIZE_16MB + * @arg @ref LL_ICACHE_REGIONSIZE_32MB + * @arg @ref LL_ICACHE_REGIONSIZE_64MB + * @arg @ref LL_ICACHE_REGIONSIZE_128MB + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetRegionSize(uint32_t Region, uint32_t Size) +{ + MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_RSIZE, (Size << ICACHE_CRRx_RSIZE_Pos)); +} + +/** + * @brief Get the selected the memory remapped region size. + * @rmtoll CRRx RSIZE LL_ICACHE_GetRegionSize + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ICACHE_REGIONSIZE_2MB + * @arg @ref LL_ICACHE_REGIONSIZE_4MB + * @arg @ref LL_ICACHE_REGIONSIZE_8MB + * @arg @ref LL_ICACHE_REGIONSIZE_16MB + * @arg @ref LL_ICACHE_REGIONSIZE_32MB + * @arg @ref LL_ICACHE_REGIONSIZE_64MB + * @arg @ref LL_ICACHE_REGIONSIZE_128MB + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionSize(uint32_t Region) +{ + return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_RSIZE) >> ICACHE_CRRx_RSIZE_Pos); +} + +/** + * @brief Select the memory remapped region output burst type. + * @rmtoll CRRx HBURST LL_ICACHE_SetRegionOutputBurstType + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param Type This parameter can be one of the following values: + * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP + * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetRegionOutputBurstType(uint32_t Region, uint32_t Type) +{ + MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_HBURST, Type); +} + +/** + * @brief Get the selected the memory remapped region output burst type. + * @rmtoll CRRx HBURST LL_ICACHE_GetRegionOutputBurstType + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP + * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionOutputBurstType(uint32_t Region) +{ + return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_HBURST)); +} + +/** + * @brief Select the memory remapped region cache master port. + * @rmtoll CRRx MSTSEL LL_ICACHE_SetRegionMasterPort + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param Port This parameter can be one of the following values: + * @arg @ref LL_ICACHE_MASTER1_PORT + * @arg @ref LL_ICACHE_MASTER2_PORT + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetRegionMasterPort(uint32_t Region, uint32_t Port) +{ + MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_MSTSEL, Port); +} + +/** + * @brief Get the selected the memory remapped region cache master port. + * @rmtoll CRRx MSTSEL LL_ICACHE_GetRegionMasterPort + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ICACHE_MASTER1_PORT + * @arg @ref LL_ICACHE_MASTER2_PORT + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionMasterPort(uint32_t Region) +{ + return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_MSTSEL)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ICACHE_LL_EF_REGION_Init Region Initialization functions + * @{ + */ + +void LL_ICACHE_ConfigRegion(uint32_t Region, const LL_ICACHE_RegionTypeDef *const pICACHE_RegionStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ICACHE */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_LL_ICACHE_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpuart.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpuart.h new file mode 100644 index 000000000..84ef08309 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpuart.h @@ -0,0 +1,2765 @@ +/** + ****************************************************************************** + * @file stm32u5xx_ll_lpuart.h + * @author MCD Application Team + * @brief Header file of LPUART LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_LL_LPUART_H +#define STM32U5xx_LL_LPUART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx.h" + +/** @addtogroup STM32U5xx_LL_Driver + * @{ + */ + +#if defined (LPUART1) + +/** @defgroup LPUART_LL LPUART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables + * @{ + */ +/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */ +static const uint16_t LPUART_PRESCALER_TAB[] = +{ + (uint16_t)1, + (uint16_t)2, + (uint16_t)4, + (uint16_t)6, + (uint16_t)8, + (uint16_t)10, + (uint16_t)12, + (uint16_t)16, + (uint16_t)32, + (uint16_t)64, + (uint16_t)128, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256 +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants + * @{ + */ +/* Defines used in Baud Rate related macros and corresponding register setting computation */ +#define LPUART_LPUARTDIV_FREQ_MUL 256U +#define LPUART_BRR_MASK 0x000FFFFFU +#define LPUART_BRR_MIN_VALUE 0x00000300U +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures + * @{ + */ + +/** + * @brief LL LPUART Init Structure definition + */ +typedef struct +{ + uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. + This parameter can be a value of @ref LPUART_LL_EC_PRESCALER. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetPrescaler().*/ + + uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref LPUART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref LPUART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref LPUART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetHWFlowCtrl().*/ + +} LL_LPUART_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants + * @{ + */ + +/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_LPUART_WriteReg function + * @{ + */ +#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_LPUART_ReadReg function + * @{ + */ +#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions + * @{ + */ +#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty + interrupt enable */ +#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO + not full interrupt enable */ +#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold + * @{ + */ +#define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DIRECTION Direction + * @{ + */ +#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */ +#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler + * @{ + */ +#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap + * @{ + */ +#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + * @{ + */ +#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + * @{ + */ +#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion + * @{ + */ +#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received + in positive/direct logic. (1=H, 0=L) */ +#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received + in negative/inverse logic. (1=L, 0=H). + The parity bit is also inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_BITORDER Bit Order + * @{ + */ +#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, + following the start bit */ +#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, + following the start bit */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection + * @{ + */ +#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested + when there is space in the receive buffer */ +#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted + when the nCTS input is asserted (tied to 0)*/ +#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity + * @{ + */ +#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection + * @brief LPUART Autonomous Trigger selection + * @{ + */ +#define LL_LPUART_LPDMA1_CH0_TCF_TRG 0U /*!< LPUART LPDMA1 channel0 Internal Trigger */ +#define LL_LPUART_LPDMA1_CH1_TCF_TRG 1U /*!< LPUART LPDMA1 channel1 Internal Trigger */ +#define LL_LPUART_LPDMA1_CH2_TCF_TRG 2U /*!< LPUART LPDMA1 channel2 Internal Trigger */ +#define LL_LPUART_LPDMA1_CH3_TCF_TRG 3U /*!< LPUART LPDMA1 channel3 Internal Trigger */ +#define LL_LPUART_EXTI_LINE6_TRG 4U /*!< LPUART EXTI line 6 Internal Trigger */ +#define LL_LPUART_EXTI_LINE8_TRG 5U /*!< LPUART EXTI line 8 Internal Trigger */ +#define LL_LPUART_LPTIM1_OUT_TRG 6U /*!< LPUART LPTIM1 out Internal Trigger */ +#define LL_LPUART_LPTIM3_OUT_TRG 7U /*!< LPUART LPTIM3 out Internal Trigger */ +#define LL_LPUART_COMP1_OUT_TRG 8U /*!< LPUART COMP1 out Internal Trigger */ +#define LL_LPUART_COMP2_OUT_TRG 9U /*!< LPUART COMP2 out Internal Trigger */ +#define LL_LPUART_RTC_ALRA_TRG 10U /*!< LPUART RTC alarm Internal Trigger */ +#define LL_LPUART_RTC_WUT_TRG 11U /*!< LPUART RTC wakeup Internal Trigger */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity + * @brief LPUART Autonomous Trigger Polarity + * @{ + */ +#define LL_LPUART_TRIG_POLARITY_RISING 0x00000000U /*!< LPUART triggered on rising edge */ +#define LL_LPUART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< LPUART triggered on falling edge */ +/** + * @} + */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros + * @{ + */ + +/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in LPUART register + * @param __INSTANCE__ LPUART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in LPUART register + * @param __INSTANCE__ LPUART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros + * @{ + */ + +/** + * @brief Compute LPUARTDIV value according to Peripheral Clock and + * expected Baud Rate (20-bit value of LPUARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @param __BAUDRATE__ Baud Rate value to achieve + * @retval LPUARTDIV value to be used for BRR register filling + */ +#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\ + ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\ + * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions + * @{ + */ + +/** @defgroup LPUART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief LPUART Enable + * @rmtoll CR1 UE LL_LPUART_Enable + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_UE); +} + +/** + * @brief LPUART Disable + * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the LPUART is kept, but all the status + * flags, in the LPUARTx_ISR are set to their default values. + * @note In order to go into low-power mode without generating errors on the line, + * the TE bit must be reset before and the software must wait + * for the TC bit in the LPUART_ISR to be set before resetting the UE bit. + * The DMA requests are also reset when UE = 0 so the DMA channel must + * be disabled before resetting the UE bit. + * @rmtoll CR1 UE LL_LPUART_Disable + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if LPUART is enabled + * @rmtoll CR1 UE LL_LPUART_IsEnabled + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); +} + +/** + * @brief FIFO Mode Enable + * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief FIFO Mode Disable + * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief Indicate if FIFO Mode is enabled + * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure TX FIFO Threshold + * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold + * @param LPUARTx LPUART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Return TX FIFO Threshold Configuration + * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Configure RX FIFO Threshold + * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold + * @param LPUARTx LPUART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Return RX FIFO Threshold Configuration + * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Configure TX and RX FIFOs Threshold + * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n + * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold + * @param LPUARTx LPUART Instance + * @param TXThreshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @param RXThreshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \ + (RXThreshold << USART_CR3_RXFTCFG_Pos)); +} + +/** + * @brief LPUART enabled in STOP Mode + * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that + * LPUART clock selection is HSI or LSE in RCC. + * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief LPUART disabled in STOP Mode + * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode + * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief Indicate if LPUART is enabled in STOP Mode + * (able to wake up MCU from Stop mode or not) + * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); +} + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n + * CR1 TE LL_LPUART_SetTransferDirection + * @param LPUARTx LPUART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_LPUART_DIRECTION_NONE + * @arg @ref LL_LPUART_DIRECTION_RX + * @arg @ref LL_LPUART_DIRECTION_TX + * @arg @ref LL_LPUART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n + * CR1 TE LL_LPUART_GetTransferDirection + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DIRECTION_NONE + * @arg @ref LL_LPUART_DIRECTION_RX + * @arg @ref LL_LPUART_DIRECTION_TX + * @arg @ref LL_LPUART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled) + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_LPUART_SetParity\n + * CR1 PCE LL_LPUART_SetParity + * @param LPUARTx LPUART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_LPUART_GetParity\n + * CR1 PCE LL_LPUART_GetParity + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod + * @param LPUARTx LPUART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_IDLELINE + * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_IDLELINE + * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_LPUART_SetDataWidth + * @param LPUARTx LPUART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_LPUART_GetDataWidth + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M)); +} + +/** + * @brief Allow switch between Mute Mode and Active mode + * @rmtoll CR1 MME LL_LPUART_EnableMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + * @rmtoll CR1 MME LL_LPUART_DisableMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Indicate if switch between Mute Mode and Active mode is allowed + * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); +} + +/** + * @brief Configure Clock source prescaler for baudrate generator and oversampling + * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler + * @param LPUARTx LPUART Instance + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); +} + +/** + * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling + * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER)); +} + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength + * @param LPUARTx LPUART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function + * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n + * CR1 PCE LL_LPUART_ConfigCharacter\n + * CR1 M LL_LPUART_ConfigCharacter\n + * CR2 STOP LL_LPUART_ConfigCharacter + * @param LPUARTx LPUART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Configure TX/RX pins swapping setting. + * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap + * @param LPUARTx LPUART Instance + * @param SwapConfig This parameter can be one of the following values: + * @arg @ref LL_LPUART_TXRX_STANDARD + * @arg @ref LL_LPUART_TXRX_SWAPPED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig); +} + +/** + * @brief Retrieve TX/RX pins swapping configuration. + * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_TXRX_STANDARD + * @arg @ref LL_LPUART_TXRX_SWAPPED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP)); +} + +/** + * @brief Configure RX pin active level logic + * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel + * @param LPUARTx LPUART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod); +} + +/** + * @brief Retrieve RX pin active level logic configuration + * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV)); +} + +/** + * @brief Configure TX pin active level logic + * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel + * @param LPUARTx LPUART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod); +} + +/** + * @brief Retrieve TX pin active level logic configuration + * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV)); +} + +/** + * @brief Configure Binary data logic. + * + * @note Allow to define how Logical data from the data register are send/received : + * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) + * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic + * @param LPUARTx LPUART Instance + * @param DataLogic This parameter can be one of the following values: + * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic); +} + +/** + * @brief Retrieve Binary data configuration + * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE + */ +__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV)); +} + +/** + * @brief Configure transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder + * @param LPUARTx LPUART Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_LPUART_BITORDER_LSBFIRST + * @arg @ref LL_LPUART_BITORDER_MSBFIRST + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder); +} + +/** + * @brief Return transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_BITORDER_LSBFIRST + * @arg @ref LL_LPUART_BITORDER_MSBFIRST + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST)); +} + +/** + * @brief Set Address of the LPUART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. + * (b7-b4 should be set to 0) + * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. + * (This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with 7-bit address mark detection. + * The MSB of the character sent by the transmitter should be equal to 1. + * It may also be used for character detection during normal reception, + * Mute mode inactive (for example, end of block detection in ModBus protocol). + * In this case, the whole received character (8-bit) is compared to the ADD[7:0] + * value and CMF flag is set on match) + * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n + * CR2 ADDM7 LL_LPUART_ConfigNodeAddress + * @param LPUARTx LPUART Instance + * @param AddressLen This parameter can be one of the following values: + * @arg @ref LL_LPUART_ADDRESS_DETECT_4B + * @arg @ref LL_LPUART_ADDRESS_DETECT_7B + * @param NodeAddress 4 or 7 bit Address of the LPUART node. + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, + (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); +} + +/** + * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2. + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * If 7-bit Address Detection is selected in ADDM7, + * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) + * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress + * @param LPUARTx LPUART Instance + * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +} + +/** + * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) + * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_ADDRESS_DETECT_4B + * @arg @ref LL_LPUART_ADDRESS_DETECT_7B + */ +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7)); +} + +/** + * @brief Enable RTS HW Flow Control + * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n + * CR3 CTSE LL_LPUART_SetHWFlowCtrl + * @param LPUARTx LPUART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_LPUART_HWCONTROL_NONE + * @arg @ref LL_LPUART_HWCONTROL_RTS + * @arg @ref LL_LPUART_HWCONTROL_CTS + * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n + * CR3 CTSE LL_LPUART_GetHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_HWCONTROL_NONE + * @arg @ref LL_LPUART_HWCONTROL_RTS + * @arg @ref LL_LPUART_HWCONTROL_CTS + * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Enable Overrun detection + * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Disable Overrun detection + * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Indicate if Overrun detection is enabled + * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); +} + +/** + * @brief Configure LPUART BRR register for achieving expected Baud Rate value. + * + * @note Compute and set LPUARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock and expected Baud Rate values + * @note Peripheral clock and Baud Rate values provided as function parameters should be valid + * (Baud rate value != 0). + * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, + * a care should be taken when generating high baud rates using high PeriphClk + * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate]. + * @rmtoll BRR BRR LL_LPUART_SetBaudRate + * @param LPUARTx LPUART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t BaudRate) +{ + if (BaudRate != 0U) + { + LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); + } +} + +/** + * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @rmtoll BRR BRR LL_LPUART_GetBaudRate + * @param LPUARTx LPUART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk, + uint32_t PrescalerValue) +{ + uint32_t lpuartdiv; + uint32_t brrresult; + uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue])); + + lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK; + + if (lpuartdiv >= LPUART_BRR_MIN_VALUE) + { + brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); + } + else + { + brrresult = 0x0UL; + } + + return (brrresult); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature + * @{ + */ + +/** + * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime + * @param LPUARTx LPUART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); +} + +/** + * @brief Return DEDT (Driver Enable De-Assertion Time) + * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime + * @param LPUARTx LPUART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : c + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); +} + +/** + * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime + * @param LPUARTx LPUART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); +} + +/** + * @brief Return DEAT (Driver Enable Assertion Time) + * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime + * @param LPUARTx LPUART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); +} + +/** + * @brief Enable Driver Enable (DE) Mode + * @rmtoll CR3 DEM LL_LPUART_EnableDEMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Disable Driver Enable (DE) Mode + * @rmtoll CR3 DEM LL_LPUART_DisableDEMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Indicate if Driver Enable (DE) Mode is enabled + * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); +} + +/** + * @brief Select Driver Enable Polarity + * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity + * @param LPUARTx LPUART Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_LPUART_DE_POLARITY_HIGH + * @arg @ref LL_LPUART_DE_POLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity); +} + +/** + * @brief Return Driver Enable Polarity + * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DE_POLARITY_HIGH + * @arg @ref LL_LPUART_DE_POLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP)); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the LPUART Parity Error Flag is set or not + * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Framing Error Flag is set or not + * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Noise error detected Flag is set or not + * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART OverRun Error Flag is set or not + * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART IDLE line detected Flag is set or not + * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not + * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmission Complete Flag is set or not + * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not + * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS interrupt Flag is set or not + * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS Flag is set or not + * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Busy Flag is set or not + * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Character Match Flag is set or not + * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Send Break Flag is set or not + * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not + * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not + * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not + * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO Empty Flag is set or not + * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO Full Flag is set or not + * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO Threshold Flag is set or not + * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO Threshold Flag is set or not + * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); +} + +/** + * @brief Clear Parity Error Flag + * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_PECF); +} + +/** + * @brief Clear Framing Error Flag + * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_FECF); +} + +/** + * @brief Clear Noise detected Flag + * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_NECF); +} + +/** + * @brief Clear OverRun Error Flag + * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF); +} + +/** + * @brief Clear IDLE line detected Flag + * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF); +} + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF); +} + +/** + * @brief Clear CTS Interrupt Flag + * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF); +} + +/** + * @brief Clear Character Match Flag + * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); +} + +#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Enable TX Empty and TX FIFO Not Full Interrupt + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable Character Match Interrupt + * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Enable TX FIFO Empty Interrupt + * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Enable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). + * - 0: Interrupt is inhibited + * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. + * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Enable TX FIFO Threshold Interrupt + * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Enable RX FIFO Threshold Interrupt + * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); +} + +#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Disable TX Empty and TX FIFO Not Full Interrupt + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable Character Match Interrupt + * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Disable TX FIFO Empty Interrupt + * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Disable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). + * - 0: Interrupt is inhibited + * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. + * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable TX FIFO Threshold Interrupt + * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Disable RX FIFO Threshold Interrupt + * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Character Match Interrupt is enabled or disabled. + * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled + * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled + * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS Interrupt is enabled or disabled. + * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled + * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled + * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Disable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Indicate if DMA Disabling on Reception Error is disabled + * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); +} + +/** + * @brief Get the LPUART data register address used for DMA transfer + * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n + * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr + * @param LPUARTx LPUART Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) + { + /* return address of TDR register */ + data_reg_addr = (uint32_t) &(LPUARTx->TDR); + } + else + { + /* return address of RDR register */ + data_reg_addr = (uint32_t) &(LPUARTx->RDR); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll RDR RDR LL_LPUART_ReceiveData8 + * @param LPUARTx LPUART Instance + * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx) +{ + return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll RDR RDR LL_LPUART_ReceiveData9 + * @param LPUARTx LPUART Instance + * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx) +{ + return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll TDR TDR LL_LPUART_TransmitData8 + * @param LPUARTx LPUART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value) +{ + LPUARTx->TDR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll TDR TDR LL_LPUART_TransmitData9 + * @param LPUARTx LPUART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value) +{ + LPUARTx->TDR = Value & 0x1FFUL; +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request Break sending + * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ); +} + +/** + * @brief Put LPUART in mute mode and set the RWU flag + * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ); +} + +/** + * @brief Request a Receive Data and FIFO flush + * @note Allows to discard the received data without reading them, and avoid an overrun + * condition. + * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); +} + +/** + * @brief Request a Transmit data FIFO flush + * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This + * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register). + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_AutonomousMode Configuration functions related to Autonomous mode feature + * @{ + */ + +/** + * @brief Enable Selected Trigger + * @rmtoll AUTOCR TRIGEN LL_LPUART_Enable_SelectedTrigger + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Enable_SelectedTrigger(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN); +} + +/** + * @brief Disable Selected Trigger + * @rmtoll AUTOCR TRIGEN LL_LPUART_Disable_SelectedTrigger + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Disable_SelectedTrigger(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN); +} + +/** + * @brief Indicate if selected Trigger is disabled or enabled + * @rmtoll AUTOCR TRIGEN LL_LPUART_IsEnabled_SelectedTrigger + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabled_SelectedTrigger(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN) == (USART_AUTOCR_TRIGEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable Autonomous Send Idle Frame feature + * @rmtoll AUTOCR IDLEDIS LL_LPUART_Enable_AutonomousSendIdleFrame + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Enable_AutonomousSendIdleFrame(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS); +} + +/** + * @brief Disable Autonomous Send Idle Frame feature + * @rmtoll AUTOCR IDLEDIS LL_LPUART_Disable_AutonomousSendIdleFrame + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Disable_AutonomousSendIdleFrame(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS); +} + +/** + * @brief Indicate if Autonomous send Idle Frame feature is disabled or enabled + * @rmtoll AUTOCR IDLEDIS LL_LPUART_IsEnabled_AutonomousSendIdleFrame + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabled_AutonomousSendIdleFrame(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS) == (USART_AUTOCR_IDLEDIS)) ? 0UL : 1UL); +} + +/** + * @brief Configure the Number of transferred data in bytes + * @rmtoll AUTOCR TDN LL_LPUART_SetNbTxData + * @param LPUARTx LPUART Instance + * @param Nbdata This parameter can be a value between 0 and 0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetNbTxData(USART_TypeDef *LPUARTx, uint32_t Nbdata) +{ + MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TDN, (uint16_t)Nbdata); +} + +/** + * @brief Retrieve the Number of transferred data in bytes + * @rmtoll AUTOCR TDN LL_LPUART_GetNbTxData + * @param LPUARTx LPUART Instance + * @retval Returned value can be a value between 0 and 0xFFFF + */ +__STATIC_INLINE uint32_t LL_LPUART_GetNbTxData(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TDN)); +} + +/** + * @brief Set the trigger polarity + * @rmtoll AUTOCR TRIGPOL LL_LPUART_SetTriggerPolarity + * @param LPUARTx LPUART Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_LPUART_TRIG_POLARITY_RISING + * @arg @ref LL_LPUART_TRIG_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTriggerPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity) +{ + MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TRIGPOL, Polarity); +} + +/** + * @brief Get the trigger polarity + * @rmtoll AUTOCR TRIGPOL LL_LPUART_GetTriggerPolarity + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_TRIG_POLARITY_RISING + * @arg @ref LL_LPUART_TRIG_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTriggerPolarity(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGPOL)); +} + +/** + * @brief Set the selected trigger + * @rmtoll AUTOCR TRIGSEL LL_LPUART_SetSelectedTrigger + * @param LPUARTx LPUART Instance + * @param Trigger This parameter can be one of the following values: + * @arg @ref LL_LPUART_LPDMA1_CH0_TCF_TRG + * @arg @ref LL_LPUART_LPDMA1_CH1_TCF_TRG + * @arg @ref LL_LPUART_LPDMA1_CH2_TCF_TRG + * @arg @ref LL_LPUART_LPDMA1_CH3_TCF_TRG + * @arg @ref LL_LPUART_EXTI_LINE6_TRG + * @arg @ref LL_LPUART_EXTI_LINE8_TRG + * @arg @ref LL_LPUART_LPTIM1_OUT_TRG + * @arg @ref LL_LPUART_LPTIM3_OUT_TRG + * @arg @ref LL_LPUART_COMP1_OUT_TRG + * @arg @ref LL_LPUART_COMP2_OUT_TRG + * @arg @ref LL_LPUART_RTC_ALRA_TRG + * @arg @ref LL_LPUART_RTC_WUT_TRG + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetSelectedTrigger(USART_TypeDef *LPUARTx, uint32_t Trigger) +{ + MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TRIGSEL, (Trigger << USART_AUTOCR_TRIGSEL_Pos)); +} + +/** + * @brief Get the selected trigger + * @rmtoll AUTOCR TRIGSEL LL_LPUART_GetSelectedTrigger + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_LPDMA1_CH0_TCF_TRG + * @arg @ref LL_LPUART_LPDMA1_CH1_TCF_TRG + * @arg @ref LL_LPUART_LPDMA1_CH2_TCF_TRG + * @arg @ref LL_LPUART_LPDMA1_CH3_TCF_TRG + * @arg @ref LL_LPUART_EXTI_LINE6_TRG + * @arg @ref LL_LPUART_EXTI_LINE8_TRG + * @arg @ref LL_LPUART_LPTIM1_OUT_TRG + * @arg @ref LL_LPUART_LPTIM3_OUT_TRG + * @arg @ref LL_LPUART_COMP1_OUT_TRG + * @arg @ref LL_LPUART_COMP2_OUT_TRG + * @arg @ref LL_LPUART_RTC_ALRA_TRG + * @arg @ref LL_LPUART_RTC_WUT_TRG + */ +__STATIC_INLINE uint32_t LL_LPUART_GetSelectedTrigger(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx); +ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct); +void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LPUART1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_LL_LPUART_H */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pwr.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pwr.h new file mode 100644 index 000000000..8b7fe9fda --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pwr.h @@ -0,0 +1,3394 @@ +/** + ****************************************************************************** + * @file stm32u5xx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_LL_PWR_H +#define STM32U5xx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx.h" + +/** @addtogroup STM32U5xx_LL_Driver + * @{ + */ + +#if defined (PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_SR_CSSF PWR_SR_CSSF /*!< Clear Stop and Standby flags */ +#define LL_PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1 /*!< Clear Wakeup flag 1 */ +#define LL_PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2 /*!< Clear Wakeup flag 2 */ +#define LL_PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3 /*!< Clear Wakeup flag 3 */ +#define LL_PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4 /*!< Clear Wakeup flag 4 */ +#define LL_PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5 /*!< Clear Wakeup flag 5 */ +#define LL_PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6 /*!< Clear Wakeup flag 6 */ +#define LL_PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7 /*!< Clear Wakeup flag 7 */ +#define LL_PWR_WUSCR_CWUF8 PWR_WUSCR_CWUF8 /*!< Clear Wakeup flag 8 */ +#define LL_PWR_WUSCR_CWUF_ALL PWR_WUSCR_CWUF /*!< Clear all Wakeup flags */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_FLAG_VOSRDY PWR_VOSR_VOSRDY /*!< Voltage scaling ready flag */ +#define LL_PWR_FLAG_BOOSTRDY PWR_VOSR_BOOSTRDY /*!< VOS EPOD booster ready flag */ +#if defined (PWR_VOSR_USBBOOSTRDY) +#define LL_PWR_FLAG_USBBOOSTRDY PWR_VOSR_USBBOOSTRDY /*!< USB EPOD booster ready flag */ +#endif /* defined (PWR_VOSR_USBBOOSTRDY) */ +#define LL_PWR_FLAG_STOPF PWR_SR_STOPF /*!< Stop flag */ +#define LL_PWR_FLAG_SBF PWR_SR_SBF /*!< Standby flag */ +#define LL_PWR_FLAG_VDDA2RDY PWR_SVMSR_VDDA2RDY /*!< VDDA ready flag (versus 1.8 V threshold) */ +#define LL_PWR_FLAG_VDDA1RDY PWR_SVMSR_VDDA1RDY /*!< VDDA ready flag (versus 1.6 V threshold) */ +#define LL_PWR_FLAG_VDDIO2RDY PWR_SVMSR_VDDIO2RDY /*!< VDDIO2 ready flag */ +#define LL_PWR_FLAG_VDDUSBRDY PWR_SVMSR_VDDUSBRDY /*!< VDDUSB ready flag */ +#define LL_PWR_FLAG_ACTVOSRDY PWR_SVMSR_ACTVOSRDY /*!< Currently applied VOS ready flag */ +#define LL_PWR_FLAG_PVDO PWR_SR2_PVDO /*!< VDD voltage detector output flag */ +#define LL_PWR_FLAG_REGS PWR_SVMSR_REGS /*!< Regulator selection flag */ +#define LL_PWR_FLAG_TEMPH PWR_BDSR_TEMPH /*!< Temperature level flag (versus high threshold) */ +#define LL_PWR_FLAG_TEMPL PWR_BDSR_TEMPL /*!< Temperature level flag (versus low threshold) */ +#define LL_PWR_FLAG_VBATH PWR_BDSR_VBATH /*!< Backup domain voltage level flag (versus high threshold) */ + +#define LL_PWR_WAKEUP_FLAG1 PWR_WUSR_WUF1 /*!< Wakeup flag 1 */ +#define LL_PWR_WAKEUP_FLAG2 PWR_WUSR_WUF2 /*!< Wakeup flag 2 */ +#define LL_PWR_WAKEUP_FLAG3 PWR_WUSR_WUF3 /*!< Wakeup flag 3 */ +#define LL_PWR_WAKEUP_FLAG4 PWR_WUSR_WUF4 /*!< Wakeup flag 4 */ +#define LL_PWR_WAKEUP_FLAG5 PWR_WUSR_WUF5 /*!< Wakeup flag 5 */ +#define LL_PWR_WAKEUP_FLAG6 PWR_WUSR_WUF6 /*!< Wakeup flag 6 */ +#define LL_PWR_WAKEUP_FLAG7 PWR_WUSR_WUF7 /*!< Wakeup flag 7 */ +#define LL_PWR_WAKEUP_FLAG8 PWR_WUSR_WUF8 /*!< Wakeup flag 8 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_LOW_POWER_MODE_SELCTION Low Power Mode Selection + * @{ + */ +#define LL_PWR_STOP0_MODE (0U) /*!< Stop 0 mode */ +#define LL_PWR_STOP1_MODE PWR_CR1_LPMS_0 /*!< Stop 1 mode */ +#define LL_PWR_STOP2_MODE PWR_CR1_LPMS_1 /*!< Stop 2 mode */ +#define LL_PWR_STOP3_MODE (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) /*!< Stop 3 mode */ +#define LL_PWR_STANDBY_MODE PWR_CR1_LPMS_2 /*!< Standby mode */ +#define LL_PWR_SHUTDOWN_MODE (PWR_CR1_LPMS_2 | PWR_CR1_LPMS_1) /*!< Shutdown mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_SRAM2_SB_CONTENTS_RETENTION PWR SRAM2 Content Retention in Standby Mode + * @note For some products of the U5 family (please see the Reference Manual), + * the SRAM2 content is preserved based on the same defines in Stop 3 mode. + * @{ + */ +#define LL_PWR_SRAM2_SB_NO_RETENTION 0U /*!< SRAM2 no retention in Stop 3 and Standby mode */ +#define LL_PWR_SRAM2_SB_PAGE1_RETENTION PWR_CR1_RRSB1 /*!< SRAM2 page 1 (8 KB) retention in Stop 3 and Standby mode */ +#define LL_PWR_SRAM2_SB_PAGE2_RETENTION PWR_CR1_RRSB2 /*!< SRAM2 page 2 (54 KB) retention in Stop 3 and Standby mode */ +#define LL_PWR_SRAM2_SB_FULL_RETENTION (PWR_CR1_RRSB1 | PWR_CR1_RRSB2) /*!< SRAM2 all pages retention in Stop 3 and Standby mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_SRAM1_STOP_CONTENTS_RETENTION PWR SRAM1 Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_SRAM1_STOP_NO_RETENTION 0U /*!< SRAM1 no retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE1_RETENTION (PWR_CR2_SRAM1PDS1) /*!< SRAM1 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE2_RETENTION (PWR_CR2_SRAM1PDS2) /*!< SRAM1 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE3_RETENTION (PWR_CR2_SRAM1PDS3) /*!< SRAM1 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#if defined (PWR_CR4_SRAM1PDS4) +#define LL_PWR_SRAM1_STOP_PAGE4_RETENTION (PWR_CR4_SRAM1PDS4) /*!< SRAM1 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE5_RETENTION (PWR_CR4_SRAM1PDS5) /*!< SRAM1 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE6_RETENTION (PWR_CR4_SRAM1PDS6) /*!< SRAM1 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE7_RETENTION (PWR_CR4_SRAM1PDS7) /*!< SRAM1 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE8_RETENTION (PWR_CR4_SRAM1PDS8) /*!< SRAM1 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE9_RETENTION (PWR_CR4_SRAM1PDS9) /*!< SRAM1 page 9 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE10_RETENTION (PWR_CR4_SRAM1PDS10) /*!< SRAM1 page 10 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE11_RETENTION (PWR_CR4_SRAM1PDS11) /*!< SRAM1 page 11 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE12_RETENTION (PWR_CR4_SRAM1PDS12) /*!< SRAM1 page 12 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR4_SRAM1PDS4) */ +#define LL_PWR_SRAM1_STOP_1_3_RETENTION (PWR_CR2_SRAM1PDS1 | PWR_CR2_SRAM1PDS2 | \ + PWR_CR2_SRAM1PDS3) /*!< SRAM1 pages (1 to 3) retention in Stop mode (Stop 0, 1, 2, 3) */ +#if defined (PWR_CR4_SRAM1PDS4) +#define LL_PWR_SRAM1_STOP_4_12_RETENTION (PWR_CR4_SRAM1PDS4 | PWR_CR4_SRAM1PDS5 | \ + PWR_CR4_SRAM1PDS6 | PWR_CR4_SRAM1PDS7 | \ + PWR_CR4_SRAM1PDS8 | PWR_CR4_SRAM1PDS9 | \ + PWR_CR4_SRAM1PDS10 | PWR_CR4_SRAM1PDS11 | \ + PWR_CR4_SRAM1PDS12) /*!< SRAM1 pages (4 to 12) retention in Stop mode (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR4_SRAM1PDS4) */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_SRAM2_STOP_CONTENTS_RETENTION PWR SRAM2 Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_SRAM2_STOP_NO_RETENTION 0U /*!< SRAM2 no retention in Stop mode (Stop 0, 1, 2) */ +#define LL_PWR_SRAM2_STOP_PAGE1_RETENTION (PWR_CR2_SRAM2PDS1) /*!< SRAM2 page 1 (8 KB) retention in Stop mode (Stop 0, 1, 2) */ +#define LL_PWR_SRAM2_STOP_PAGE2_RETENTION (PWR_CR2_SRAM2PDS2) /*!< SRAM2 page 2 (54 KB) retention in Stop mode (Stop 0, 1, 2) */ +#define LL_PWR_SRAM2_STOP_FULL_RETENTION (PWR_CR2_SRAM2PDS1 | PWR_CR2_SRAM2PDS2) /*!< SRAM2 all pages retention in Stop mode (Stop 0, 1, 2) */ +/** + * @} + */ + +#if defined (PWR_CR2_SRAM3PDS1) +/** @defgroup PWR_LL_EC_SRAM3_STOP_CONTENTS_RETENTION PWR SRAM3 Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_SRAM3_STOP_NO_RETENTION 0U /*!< SRAM3 no retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE1_RETENTION (PWR_CR2_SRAM3PDS1) /*!< SRAM3 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE2_RETENTION (PWR_CR2_SRAM3PDS2) /*!< SRAM3 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE3_RETENTION (PWR_CR2_SRAM3PDS3) /*!< SRAM3 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE4_RETENTION (PWR_CR2_SRAM3PDS4) /*!< SRAM3 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE5_RETENTION (PWR_CR2_SRAM3PDS5) /*!< SRAM3 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE6_RETENTION (PWR_CR2_SRAM3PDS6) /*!< SRAM3 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE7_RETENTION (PWR_CR2_SRAM3PDS7) /*!< SRAM3 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE8_RETENTION (PWR_CR2_SRAM3PDS8) /*!< SRAM3 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#if defined (PWR_CR4_SRAM3PDS9) +#define LL_PWR_SRAM3_STOP_PAGE9_RETENTION (PWR_CR4_SRAM3PDS9) /*!< SRAM3 page 9 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE10_RETENTION (PWR_CR4_SRAM3PDS10) /*!< SRAM3 page 10 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE11_RETENTION (PWR_CR4_SRAM3PDS11) /*!< SRAM3 page 11 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE12_RETENTION (PWR_CR4_SRAM3PDS12) /*!< SRAM3 page 12 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE13_RETENTION (PWR_CR4_SRAM3PDS13) /*!< SRAM3 page 13 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR4_SRAM3PDS9) */ +#define LL_PWR_SRAM3_STOP_1_8_RETENTION (PWR_CR2_SRAM3PDS1 | PWR_CR2_SRAM3PDS2 | PWR_CR2_SRAM3PDS3 | \ + PWR_CR2_SRAM3PDS4 | PWR_CR2_SRAM3PDS5 | PWR_CR2_SRAM3PDS6 | \ + PWR_CR2_SRAM3PDS7 | PWR_CR2_SRAM3PDS8) /*!< SRAM3 pages (1 to 8) retention in Stop modes (Stop 0, 1, 2, 3) */ +#if defined (PWR_CR4_SRAM3PDS9) +#define LL_PWR_SRAM3_STOP_9_13_RETENTION (PWR_CR4_SRAM3PDS9 | PWR_CR4_SRAM3PDS10 | PWR_CR4_SRAM3PDS11 | \ + PWR_CR4_SRAM3PDS12 | PWR_CR4_SRAM3PDS13) /*!< SRAM3 pages (9 to 13) retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR4_SRAM3PDS9) */ +/** + * @} + */ +#endif /* PWR_CR2_SRAM3PDS1 */ + +/** @defgroup PWR_LL_EC_SRAM4_STOP_CONTENTS_RETENTION PWR SRAM4 Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_SRAM4_STOP_NO_RETENTION 0U /*!< SRAM4 no retention in Stop mode (Stop 0, 1, 2) */ +#define LL_PWR_SRAM4_STOP_FULL_RETENTION PWR_CR2_SRAM4PDS /*!< SRAM4 retention in Stop mode (Stop 0, 1, 2) */ +/** + * @} + */ + +#if defined (PWR_CR4_SRAM5PDS1) +/** @defgroup PWR_LL_EC_SRAM5_STOP_CONTENTS_RETENTION PWR SRAM5 Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_SRAM5_STOP_NO_RETENTION 0U /*!< SRAM5 no retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE1_RETENTION (PWR_CR4_SRAM5PDS1) /*!< SRAM5 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE2_RETENTION (PWR_CR4_SRAM5PDS2) /*!< SRAM5 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE3_RETENTION (PWR_CR4_SRAM5PDS3) /*!< SRAM5 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE4_RETENTION (PWR_CR4_SRAM5PDS4) /*!< SRAM5 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE5_RETENTION (PWR_CR4_SRAM5PDS5) /*!< SRAM5 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE6_RETENTION (PWR_CR4_SRAM5PDS6) /*!< SRAM5 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE7_RETENTION (PWR_CR4_SRAM5PDS7) /*!< SRAM5 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE8_RETENTION (PWR_CR4_SRAM5PDS8) /*!< SRAM5 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE9_RETENTION (PWR_CR4_SRAM5PDS9) /*!< SRAM5 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE10_RETENTION (PWR_CR4_SRAM5PDS10) /*!< SRAM5 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE11_RETENTION (PWR_CR4_SRAM5PDS11) /*!< SRAM5 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE12_RETENTION (PWR_CR4_SRAM5PDS12) /*!< SRAM5 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE13_RETENTION (PWR_CR4_SRAM5PDS13) /*!< SRAM5 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_FULL_RETENTION (PWR_CR4_SRAM5PDS1 | PWR_CR4_SRAM5PDS2 | PWR_CR4_SRAM5PDS3 | \ + PWR_CR4_SRAM5PDS4 | PWR_CR4_SRAM5PDS5 | PWR_CR4_SRAM5PDS6 | \ + PWR_CR4_SRAM5PDS7 | PWR_CR4_SRAM5PDS8 | PWR_CR4_SRAM5PDS9 | \ + PWR_CR4_SRAM5PDS10 | PWR_CR4_SRAM5PDS11 | PWR_CR4_SRAM5PDS12 | \ + PWR_CR4_SRAM5PDS13) /*!< SRAM5 pages (1 to 13) retention in Stop modes (Stop 0, 1, 2, 3) */ +/** + * @} + */ +#endif /* defined (PWR_CR4_SRAM5PDS1) */ + +#if defined (PWR_CR5_SRAM6PDS1) +/** @defgroup PWR_LL_EC_SRAM6_STOP_CONTENTS_RETENTION PWR SRAM6 Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_SRAM6_STOP_NO_RETENTION 0U /*!< SRAM6 no retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM6_STOP_PAGE1_RETENTION (PWR_CR5_SRAM6PDS1) /*!< SRAM6 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM6_STOP_PAGE2_RETENTION (PWR_CR5_SRAM6PDS2) /*!< SRAM6 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM6_STOP_PAGE3_RETENTION (PWR_CR5_SRAM6PDS3) /*!< SRAM6 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM6_STOP_PAGE4_RETENTION (PWR_CR5_SRAM6PDS4) /*!< SRAM6 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM6_STOP_PAGE5_RETENTION (PWR_CR5_SRAM6PDS5) /*!< SRAM6 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM6_STOP_PAGE6_RETENTION (PWR_CR5_SRAM6PDS6) /*!< SRAM6 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM6_STOP_PAGE7_RETENTION (PWR_CR5_SRAM6PDS7) /*!< SRAM6 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM6_STOP_PAGE8_RETENTION (PWR_CR5_SRAM6PDS8) /*!< SRAM6 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM6_STOP_FULL_RETENTION (PWR_CR5_SRAM6PDS1 | PWR_CR5_SRAM6PDS2 | PWR_CR5_SRAM6PDS3 | \ + PWR_CR5_SRAM6PDS4 | PWR_CR5_SRAM6PDS5 | PWR_CR5_SRAM6PDS6 | \ + PWR_CR5_SRAM6PDS7 | \ + PWR_CR5_SRAM6PDS8) /*!< SRAM6 pages (1 to 8) retention in Stop modes (Stop 0, 1, 2, 3) */ +/** + * @} + */ +#endif /* defined (PWR_CR5_SRAM6PDS1) */ + +/** @defgroup PWR_LL_EC_ICACHERAM_STOP_CONTENTS_RETENTION PWR ICACHE Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_ICACHERAM_STOP_NO_RETENTION 0U /*!< ICACHE SRAM no retention in Stop mode (Stop 0, 1, 2) */ +#define LL_PWR_ICACHERAM_STOP_FULL_RETENTION PWR_CR2_ICRAMPDS /*!< ICACHE SRAM retention in Stop mode (Stop 0, 1, 2) */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_DCACHE1RAM_STOP_CONTENTS_RETENTION PWR DCACHE1 Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_DCACHE1RAM_STOP_NO_RETENTION 0U /*!< DCACHE1 SRAM no retention in Stop mode (Stop 0, 1, 2) */ +#define LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION PWR_CR2_DC1RAMPDS /*!< DCACHE1 SRAM retention in Stop mode (Stop 0, 1, 2) */ +/** + * @} + */ + +#if defined (PWR_CR2_DC2RAMPDS) +/** @defgroup PWR_LL_EC_DCACHE2RAM_STOP_CONTENTS_RETENTION PWR DCACHE2 Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_DCACHE2RAM_STOP_NO_RETENTION 0U /*!< DCACHE2 SRAM no retention in Stop mode (Stop 0, 1, 2) */ +#define LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION PWR_CR2_DC2RAMPDS /*!< DCACHE2 SRAM retention in Stop mode (Stop 0, 1, 2) */ +/** + * @} + */ +#endif /* defined (PWR_CR2_DC2RAMPDS) */ + +#if defined (PWR_CR2_DMA2DRAMPDS) +/** @defgroup PWR_LL_EC_DMA2DRAM_STOP_CONTENTS_RETENTION PWR DMA2DRAM Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_DMA2DRAM_STOP_NO_RETENTION 0U /*!< DMA2D SRAM no retention in Stop mode (Stop 0, 1, 2) */ +#define LL_PWR_DMA2DRAM_STOP_FULL_RETENTION PWR_CR2_DMA2DRAMPDS /*!< DMA2D SRAM retention in Stop mode (Stop 0, 1, 2) */ +/** + * @} + */ +#endif /* PWR_CR2_DMA2DRAMPDS */ + +/** @defgroup PWR_LL_EC_PERIPHRAM_STOP_CONTENTS_RETENTION PWR PERIPHRAM Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_PERIPHRAM_STOP_NO_RETENTION 0U /*!< FMAC, FDCAN and USB SRAM no retention in Stop mode (Stop 0, 1, 2) */ +#define LL_PWR_PERIPHRAM_STOP_FULL_RETENTION PWR_CR2_PRAMPDS /*!< FMAC, FDCAN and USB SRAM retention in Stop mode (Stop 0, 1, 2) */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_PKARAM_STOP_CONTENTS_RETENTION PWR PKARAM Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_PKARAM_STOP_NO_RETENTION 0U /*!< PKA32 SRAM no retention in Stop mode (Stop 0, 1, 2) */ +#define LL_PWR_PKARAM_STOP_FULL_RETENTION PWR_CR2_PKARAMPDS /*!< PKA32 SRAM retention in Stop mode (Stop 0, 1, 2) */ +/** + * @} + */ + +#if defined (PWR_CR2_GPRAMPDS) +/** @defgroup PWR_LL_EC_GPRAM_STOP_CONTENTS_RETENTION PWR GPRAM Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_GRAPHICPERIPHRAM_STOP_NO_RETENTION 0U /*!< Graphic peripherals (LTDC, GFXMMU) SRAM no retention in Stop mode (Stop 0, 1, 2) */ +#define LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION PWR_CR2_GPRAMPDS /*!< Graphic peripherals (LTDC, GFXMMU) SRAM retention in Stop mode (Stop 0, 1, 2) */ +/** + * @} + */ +#endif /* defined (PWR_CR2_GPRAMPDS) */ + +#if defined (PWR_CR2_DSIRAMPDS) +/** @defgroup PWR_LL_EC_DSIRAM_STOP_CONTENTS_RETENTION PWR DSI RAM Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_DSIRAM_STOP_NO_RETENTION 0U /*!< DSI SRAM no retention in Stop mode (Stop 0, 1, 2) */ +#define LL_PWR_DSIRAM_STOP_FULL_RETENTION PWR_CR2_DSIRAMPDS /*!< DSI SRAM retention in Stop mode (Stop 0, 1, 2) */ +/** + * @} + */ +#endif /* defined (PWR_CR2_JPEGRAMPDS) */ + +#if defined (PWR_CR2_JPEGRAMPDS) +/** @defgroup PWR_LL_EC_JPEGRAM_STOP_CONTENTS_RETENTION PWR JPEG RAM Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_JPEGRAM_STOP_NO_RETENTION 0U /*!< JPEG SRAM no retention in Stop mode (Stop 0, 1, 2) */ +#define LL_PWR_JPEGRAM_STOP_FULL_RETENTION PWR_CR2_JPEGRAMPDS /*!< JPEG SRAM retention in Stop mode (Stop 0, 1, 2) */ +/** + * @} + */ +#endif /* defined (PWR_CR2_JPEGRAMPDS) */ + +/** @defgroup PWR_LL_EC_SRAM1_RUN_CONTENTS_RETENTION PWR SRAM1 Content Retention in Run Mode + * @{ + */ +#define LL_PWR_SRAM1_RUN_NO_RETENTION 0U /*!< SRAM1 no retention in Run mode */ +#define LL_PWR_SRAM1_RUN_FULL_RETENTION PWR_CR1_SRAM1PD /*!< SRAM1 retention in Run mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_SRAM2_RUN_CONTENTS_RETENTION PWR SRAM2 Content Retention in Run Mode + * @{ + */ +#define LL_PWR_SRAM2_RUN_NO_RETENTION 0U /*!< SRAM2 no retention in Run mode */ +#define LL_PWR_SRAM2_RUN_FULL_RETENTION PWR_CR1_SRAM2PD /*!< SRAM2 retention in Run mode */ +/** + * @} + */ + +#if defined (PWR_CR1_SRAM3PD) +/** @defgroup PWR_LL_EC_SRAM3_RUN_CONTENTS_RETENTION PWR SRAM3 Content Retention in Run Mode + * @{ + */ +#define LL_PWR_SRAM3_RUN_NO_RETENTION 0U /*!< SRAM3 no retention in Run mode */ +#define LL_PWR_SRAM3_RUN_FULL_RETENTION PWR_CR1_SRAM3PD /*!< SRAM3 retention in Run mode */ +/** + * @} + */ +#endif /* PWR_CR1_SRAM3PD */ + +/** @defgroup PWR_LL_EC_SRAM4_RUN_CONTENTS_RETENTION PWR SRAM4 Content Retention in Run Mode + * @{ + */ +#define LL_PWR_SRAM4_RUN_NO_RETENTION 0U /*!< SRAM4 no retention in Run mode */ +#define LL_PWR_SRAM4_RUN_FULL_RETENTION PWR_CR1_SRAM4PD /*!< SRAM4 retention in Run mode */ +/** + * @} + */ + +#if defined (PWR_CR1_SRAM5PD) +/** @defgroup PWR_LL_EC_SRAM5_RUN_CONTENTS_RETENTION PWR SRAM5 Content Retention in Run Mode + * @{ + */ +#define LL_PWR_SRAM5_RUN_NO_RETENTION 0U /*!< SRAM5 no retention in Run mode */ +#define LL_PWR_SRAM5_RUN_FULL_RETENTION PWR_CR1_SRAM5PD /*!< SRAM5 retention in Run mode */ +/** + * @} + */ +#endif /* defined (PWR_CR1_SRAM5PD) */ + +#if defined (PWR_CR1_SRAM6PD) +/** @defgroup PWR_LL_EC_SRAM6_RUN_CONTENTS_RETENTION PWR SRAM6 Content Retention in Run Mode + * @{ + */ +#define LL_PWR_SRAM6_RUN_NO_RETENTION 0U /*!< SRAM6 no retention in Run mode */ +#define LL_PWR_SRAM6_RUN_FULL_RETENTION PWR_CR1_SRAM6PD /*!< SRAM6 retention in Run mode */ +/** + * @} + */ +#endif /* defined (PWR_CR1_SRAM6PD) */ + +/** @defgroup PWR_LL_EC_SRD_MODE PWR Smart Run Domain Mode + * @{ + */ +#define LL_PWR_SRD_STOP_MODE 0U /*!< SmartRun domain AHB3 and APB3 clocks disabled by default in Stop mode (Stop 0, 1, 2) */ +#define LL_PWR_SRD_RUN_MODE PWR_CR2_SRDRUN /*!< SmartRun domain AHB3 and APB3 clocks kept enabled in Stop mode (Stop 0, 1, 2) */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGULATOR_SUPPLY_SELECTION PWR Regulator Supply Selection + * @{ + */ +#define LL_PWR_LDO_SUPPLY 0U /*!< LDO regulator supply */ +#define LL_PWR_SMPS_SUPPLY PWR_CR3_REGSEL /*!< SMPS regulator supply */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_VOLTAGE_SCALING_RANGE_SELECTION PWR Voltage scaling range selection + * @{ + */ +#define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_VOSR_VOS /*!< Voltage scaling range 1 */ +#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_VOSR_VOS_1 /*!< Voltage scaling range 2 */ +#define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_VOSR_VOS_0 /*!< Voltage scaling range 3 */ +#define LL_PWR_REGU_VOLTAGE_SCALE4 0x00000000U /*!< Voltage scaling range 4 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_PVD_LEVEL_SELECTION PWR Power Voltage Detector Level Selection + * @{ + */ +#define LL_PWR_PVDLEVEL_0 0U /*!< Voltage threshold detected by PVD 2.0 V */ +#define LL_PWR_PVDLEVEL_1 PWR_SVMCR_PVDLS_0 /*!< Voltage threshold detected by PVD 2.2 V */ +#define LL_PWR_PVDLEVEL_2 PWR_SVMCR_PVDLS_1 /*!< Voltage threshold detected by PVD 2.4 V */ +#define LL_PWR_PVDLEVEL_3 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_1) /*!< Voltage threshold detected by PVD 2.5 V */ +#define LL_PWR_PVDLEVEL_4 PWR_SVMCR_PVDLS_2 /*!< Voltage threshold detected by PVD 2.6 V */ +#define LL_PWR_PVDLEVEL_5 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_2) /*!< Voltage threshold detected by PVD 2.8 V */ +#define LL_PWR_PVDLEVEL_6 (PWR_SVMCR_PVDLS_1 | PWR_SVMCR_PVDLS_2) /*!< Voltage threshold detected by PVD 2.9 V */ +#define LL_PWR_PVDLEVEL_7 PWR_SVMCR_PVDLS /*!< External input analog voltage on PVD_IN + pin, compared to internal VREFINT level */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN PWR Wake Up Pin + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 PWR_WUCR1_WUPEN1 /*!< Wakeup pin 1 enable */ +#define LL_PWR_WAKEUP_PIN2 PWR_WUCR1_WUPEN2 /*!< Wakeup pin 2 enable */ +#define LL_PWR_WAKEUP_PIN3 PWR_WUCR1_WUPEN3 /*!< Wakeup pin 3 enable */ +#define LL_PWR_WAKEUP_PIN4 PWR_WUCR1_WUPEN4 /*!< Wakeup pin 4 enable */ +#define LL_PWR_WAKEUP_PIN5 PWR_WUCR1_WUPEN5 /*!< Wakeup pin 5 enable */ +#define LL_PWR_WAKEUP_PIN6 PWR_WUCR1_WUPEN6 /*!< Wakeup pin 6 enable */ +#define LL_PWR_WAKEUP_PIN7 PWR_WUCR1_WUPEN7 /*!< Wakeup pin 7 enable */ +#define LL_PWR_WAKEUP_PIN8 PWR_WUCR1_WUPEN8 /*!< Wakeup pin 8 enable */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN_SELECTION PWR Wakeup Pin Selection + * @{ + */ +#define LL_PWR_WAKEUP_PIN_SELECTION_0 0UL /*!< Wakeup pin selection 0 */ +#define LL_PWR_WAKEUP_PIN_SELECTION_1 PWR_WUCR3_WUSEL1_0 /*!< Wakeup pin selection 1 */ +#define LL_PWR_WAKEUP_PIN_SELECTION_2 PWR_WUCR3_WUSEL1_1 /*!< Wakeup pin selection 2 */ +#define LL_PWR_WAKEUP_PIN_SELECTION_3 PWR_WUCR3_WUSEL1 /*!< Wakeup pin selection 3 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_CHARGING_RESISTOR_SELECTION PWR VBAT Charging Resistor Selection + * @{ + */ +#define LL_PWR_BATT_CHARG_RESISTOR_5K 0U /*!< Charge the battery through a 5 kO resistor */ +#define LL_PWR_BATT_CHARG_RESISTOR_1_5K PWR_BDCR2_VBRS /*!< Charge the battery through a 1.5 kO resistor */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GPIO_PORT_SELECTION PWR GPIO Port Selection + * @{ + */ +#define LL_PWR_GPIO_PORTA (&(PWR->PUCRA)) /*!< GPIO port A */ +#define LL_PWR_GPIO_PORTB (&(PWR->PUCRB)) /*!< GPIO port B */ +#define LL_PWR_GPIO_PORTC (&(PWR->PUCRC)) /*!< GPIO port C */ +#define LL_PWR_GPIO_PORTD (&(PWR->PUCRD)) /*!< GPIO port D */ +#define LL_PWR_GPIO_PORTE (&(PWR->PUCRE)) /*!< GPIO port E */ +#ifdef PWR_PUCRF_PU0 +#define LL_PWR_GPIO_PORTF (&(PWR->PUCRF)) /*!< GPIO port F */ +#endif /* PWR_PUCRF_PU0 */ +#define LL_PWR_GPIO_PORTG (&(PWR->PUCRG)) /*!< GPIO port G */ +#define LL_PWR_GPIO_PORTH (&(PWR->PUCRH)) /*!< GPIO port H */ +#ifdef PWR_PUCRI_PU0 +#define LL_PWR_GPIO_PORTI (&(PWR->PUCRI)) /*!< GPIO port I */ +#endif /* PWR_PUCRI_PU0 */ +#if defined (PWR_PUCRJ_PU0) +#define LL_PWR_GPIO_PORTJ (&(PWR->PUCRJ)) /*!< GPIO port J */ +#endif /* defined (PWR_PUCRJ_PU0) */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GPIO_PIN_MASK PWR GPIO Pin Mask + * @{ + */ +#define LL_PWR_GPIO_PIN_0 (0x0001U) /*!< GPIO port I/O pin 0 */ +#define LL_PWR_GPIO_PIN_1 (0x0002U) /*!< GPIO port I/O pin 1 */ +#define LL_PWR_GPIO_PIN_2 (0x0004U) /*!< GPIO port I/O pin 2 */ +#define LL_PWR_GPIO_PIN_3 (0x0008U) /*!< GPIO port I/O pin 3 */ +#define LL_PWR_GPIO_PIN_4 (0x0010U) /*!< GPIO port I/O pin 4 */ +#define LL_PWR_GPIO_PIN_5 (0x0020U) /*!< GPIO port I/O pin 5 */ +#define LL_PWR_GPIO_PIN_6 (0x0040U) /*!< GPIO port I/O pin 6 */ +#define LL_PWR_GPIO_PIN_7 (0x0080U) /*!< GPIO port I/O pin 7 */ +#define LL_PWR_GPIO_PIN_8 (0x0100U) /*!< GPIO port I/O pin 8 */ +#define LL_PWR_GPIO_PIN_9 (0x0200U) /*!< GPIO port I/O pin 9 */ +#define LL_PWR_GPIO_PIN_10 (0x0400U) /*!< GPIO port I/O pin 10 */ +#define LL_PWR_GPIO_PIN_11 (0x0800U) /*!< GPIO port I/O pin 11 */ +#define LL_PWR_GPIO_PIN_12 (0x1000U) /*!< GPIO port I/O pin 12 */ +#define LL_PWR_GPIO_PIN_13 (0x2000U) /*!< GPIO port I/O pin 13 */ +#define LL_PWR_GPIO_PIN_14 (0x4000U) /*!< GPIO port I/O pin 14 */ +#define LL_PWR_GPIO_PIN_15 (0x8000U) /*!< GPIO port I/O pin 15 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_ITEMS_SECURE_ATTRIBUTE PWR Items Secure Attribute + * @{ + */ +#define LL_PWR_WAKEUP_PIN1_NSEC 0U /*!< Wake up pin 1 nsecure mode */ +#define LL_PWR_WAKEUP_PIN1_SEC PWR_SECCFGR_WUP1SEC /*!< Wake up pin 1 secure mode */ +#define LL_PWR_WAKEUP_PIN2_NSEC 0U /*!< Wake up pin 2 nsecure mode */ +#define LL_PWR_WAKEUP_PIN2_SEC PWR_SECCFGR_WUP2SEC /*!< Wake up pin 2 secure mode */ +#define LL_PWR_WAKEUP_PIN3_NSEC 0U /*!< Wake up pin 3 nsecure mode */ +#define LL_PWR_WAKEUP_PIN3_SEC PWR_SECCFGR_WUP3SEC /*!< Wake up pin 3 secure mode */ +#define LL_PWR_WAKEUP_PIN4_NSEC 0U /*!< Wake up pin 4 nsecure mode */ +#define LL_PWR_WAKEUP_PIN4_SEC PWR_SECCFGR_WUP4SEC /*!< Wake up pin 4 secure mode */ +#define LL_PWR_WAKEUP_PIN5_NSEC 0U /*!< Wake up pin 5 nsecure mode */ +#define LL_PWR_WAKEUP_PIN5_SEC PWR_SECCFGR_WUP5SEC /*!< Wake up pin 5 secure mode */ +#define LL_PWR_WAKEUP_PIN6_NSEC 0U /*!< Wake up pin 6 nsecure mode */ +#define LL_PWR_WAKEUP_PIN6_SEC PWR_SECCFGR_WUP6SEC /*!< Wake up pin 6 secure mode */ +#define LL_PWR_WAKEUP_PIN7_NSEC 0U /*!< Wake up pin 7 nsecure mode */ +#define LL_PWR_WAKEUP_PIN7_SEC PWR_SECCFGR_WUP7SEC /*!< Wake up pin 7 secure mode */ +#define LL_PWR_WAKEUP_PIN8_NSEC 0U /*!< Wake up pin 8 nsecure mode */ +#define LL_PWR_WAKEUP_PIN8_SEC PWR_SECCFGR_WUP8SEC /*!< Wake up pin 8 secure mode */ + +#define LL_PWR_LPM_NSEC 0U /*!< Low-power modes nsecure mode */ +#define LL_PWR_LPM_SEC PWR_SECCFGR_LPMSEC /*!< Low-power modes secure mode */ +#define LL_PWR_VDM_NSEC 0U /*!< Voltage detection and monitoring nsecure mode */ +#define LL_PWR_VDM_SEC PWR_SECCFGR_VDMSEC /*!< Voltage detection and monitoring secure mode */ +#define LL_PWR_VB_NSEC 0U /*!< Backup domain nsecure mode */ +#define LL_PWR_VB_SEC PWR_SECCFGR_VBSEC /*!< Backup domain secure mode */ +#define LL_PWR_APC_NSEC 0U /*!< Pull-up/pull-down nsecure mode */ +#define LL_PWR_APC_SEC PWR_SECCFGR_APCSEC /*!< Pull-up/pull-down secure mode */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common Write and Read Registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register. + * @param __REG__ Register to be written. + * @param __VALUE__ Value to be written in the register. + * @retval None. + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register. + * @param __REG__ Register to be read. + * @retval Register value. + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_CONFIGURATION PWR Configuration + * @{ + */ + +/** + * @brief Set system power mode. + * @rmtoll CR1 LPMS LL_PWR_SetPowerMode + * @param Mode : This parameter can be one of the following values: + * @arg @ref LL_PWR_STOP0_MODE + * @arg @ref LL_PWR_STOP1_MODE + * @arg @ref LL_PWR_STOP2_MODE + * @arg @ref LL_PWR_STOP3_MODE + * @arg @ref LL_PWR_STANDBY_MODE + * @arg @ref LL_PWR_SHUTDOWN_MODE + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t Mode) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, Mode); +} + +/** + * @brief Get system power mode. + * @rmtoll CR1 LPMS LL_PWR_GetPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_STOP0_MODE + * @arg @ref LL_PWR_STOP1_MODE + * @arg @ref LL_PWR_STOP2_MODE + * @arg @ref LL_PWR_STOP3_MODE + * @arg @ref LL_PWR_STANDBY_MODE + * @arg @ref LL_PWR_SHUTDOWN_MODE + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_LPMS)); +} + +/** + * @brief Set the SRAM2 page(s) retention in Standby mode. + * @rmtoll CR1 RRSB1 LL_PWR_SetSRAM2SBRetention\n + * @rmtoll CR1 RRSB2 LL_PWR_SetSRAM2SBRetention + * @param SRAM2PageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION + * @arg @ref LL_PWR_SRAM2_SB_PAGE1_RETENTION + * @arg @ref LL_PWR_SRAM2_SB_PAGE2_RETENTION + * @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM2SBRetention(uint32_t SRAM2PageRetention) +{ + MODIFY_REG(PWR->CR1, LL_PWR_SRAM2_SB_FULL_RETENTION, SRAM2PageRetention); +} + +/** + * @brief Get the SRAM2 page(s) retention in Standby mode. + * @rmtoll CR1 RRSB1 LL_PWR_GetSRAM2SBRetention\n + * @rmtoll CR1 RRSB2 LL_PWR_GetSRAM2SBRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION + * @arg @ref LL_PWR_SRAM2_SB_PAGE1_RETENTION + * @arg @ref LL_PWR_SRAM2_SB_PAGE2_RETENTION + * @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM2SBRetention(void) +{ + return (READ_BIT(PWR->CR1, (PWR_CR1_RRSB1 | PWR_CR1_RRSB2))); +} + +/** + * @brief Enable BOR ultra low power mode. + * @rmtoll CR1 UPLMEN LL_PWR_EnableUltraLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUltraLowPowerMode(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_ULPMEN); +} + +/** + * @brief Disable BOR ultra low-power mode. + * @rmtoll CR1 UPLMEN LL_PWR_DisableUltraLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUltraLowPowerMode(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN); +} + +/** + * @brief Check if BOR ultra low power mode is enabled. + * @rmtoll CR1 UPLMEN LL_PWR_IsEnabledUltraLowPowerMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPowerMode(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_ULPMEN) == (PWR_CR1_ULPMEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the SRAM1 retention in Run mode. + * @rmtoll CR1 SRAM1PD LL_PWR_SetSRAM1RunRetention\n + * @param SRAM1Retention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM1_RUN_NO_RETENTION + * @arg @ref LL_PWR_SRAM1_RUN_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM1RunRetention(uint32_t SRAM1Retention) +{ + MODIFY_REG(PWR->CR1, LL_PWR_SRAM1_RUN_FULL_RETENTION, ((~SRAM1Retention) & LL_PWR_SRAM1_RUN_FULL_RETENTION)); +} + +/** + * @brief Get the SRAM1 retention in Run mode. + * @rmtoll CR1 SRAM1PD LL_PWR_GetSRAM1RunRetention\n + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM1_RUN_NO_RETENTION + * @arg @ref LL_PWR_SRAM1_RUN_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM1RunRetention(void) +{ + return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM1_RUN_FULL_RETENTION))) & LL_PWR_SRAM1_RUN_FULL_RETENTION); +} + +/** + * @brief Set the SRAM2 retention in Run mode. + * @rmtoll CR1 SRAM2PD LL_PWR_SetSRAM2RunRetention\n + * @param SRAM2Retention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM2_RUN_NO_RETENTION + * @arg @ref LL_PWR_SRAM2_RUN_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM2RunRetention(uint32_t SRAM2Retention) +{ + MODIFY_REG(PWR->CR1, LL_PWR_SRAM2_RUN_FULL_RETENTION, ((~SRAM2Retention) & LL_PWR_SRAM2_RUN_FULL_RETENTION)); +} + +/** + * @brief Get the SRAM2 retention in Run mode. + * @rmtoll CR1 SRAM2PD LL_PWR_GetSRAM2RunRetention\n + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM2_RUN_NO_RETENTION + * @arg @ref LL_PWR_SRAM2_RUN_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM2RunRetention(void) +{ + return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM2_RUN_FULL_RETENTION))) & LL_PWR_SRAM2_RUN_FULL_RETENTION); +} + +#if defined (PWR_CR1_SRAM3PD) +/** + * @brief Set the SRAM3 retention in Run mode. + * @rmtoll CR1 SRAM3PD LL_PWR_SetSRAM3RunRetention\n + * @param SRAM3Retention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM3_RUN_NO_RETENTION + * @arg @ref LL_PWR_SRAM3_RUN_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM3RunRetention(uint32_t SRAM3Retention) +{ + MODIFY_REG(PWR->CR1, LL_PWR_SRAM3_RUN_FULL_RETENTION, ((~SRAM3Retention) & LL_PWR_SRAM3_RUN_FULL_RETENTION)); +} + +/** + * @brief Get the SRAM3 retention in Run mode. + * @rmtoll CR1 SRAM3PD LL_PWR_GetSRAM3RunRetention\n + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM3_RUN_NO_RETENTION + * @arg @ref LL_PWR_SRAM3_RUN_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM3RunRetention(void) +{ + return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM3_RUN_FULL_RETENTION))) & LL_PWR_SRAM3_RUN_FULL_RETENTION); +} +#endif /* PWR_CR1_SRAM3PD */ + +/** + * @brief Set the SRAM4 retention in Run mode. + * @rmtoll CR1 SRAM4PD LL_PWR_SetSRAM4RunRetention\n + * @param SRAM4Retention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM4_RUN_NO_RETENTION + * @arg @ref LL_PWR_SRAM4_RUN_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM4RunRetention(uint32_t SRAM4Retention) +{ + MODIFY_REG(PWR->CR1, LL_PWR_SRAM4_RUN_FULL_RETENTION, ((~SRAM4Retention) & LL_PWR_SRAM4_RUN_FULL_RETENTION)); +} + +/** + * @brief Get the SRAM4 retention in Run mode. + * @rmtoll CR1 SRAM4PD LL_PWR_GetSRAM4RunRetention\n + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM4_RUN_NO_RETENTION + * @arg @ref LL_PWR_SRAM4_RUN_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM4RunRetention(void) +{ + return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM4_RUN_FULL_RETENTION))) & LL_PWR_SRAM4_RUN_FULL_RETENTION); +} + +#if defined (PWR_CR1_SRAM5PD) +/** + * @brief Set the SRAM5 retention in Run mode. + * @rmtoll CR1 SRAM5PD LL_PWR_SetSRAM5RunRetention\n + * @param SRAM5Retention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM5_RUN_NO_RETENTION + * @arg @ref LL_PWR_SRAM5_RUN_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM5RunRetention(uint32_t SRAM5Retention) +{ + MODIFY_REG(PWR->CR1, LL_PWR_SRAM5_RUN_FULL_RETENTION, ((~SRAM5Retention) & LL_PWR_SRAM5_RUN_FULL_RETENTION)); +} + +/** + * @brief Get the SRAM5 retention in Run mode. + * @rmtoll CR1 SRAM5PD LL_PWR_GetSRAM5RunRetention\n + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM5_RUN_NO_RETENTION + * @arg @ref LL_PWR_SRAM5_RUN_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM5RunRetention(void) +{ + return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM5_RUN_FULL_RETENTION))) & LL_PWR_SRAM5_RUN_FULL_RETENTION); +} +#endif /* defined (PWR_CR1_SRAM5PD) */ + +#if defined (PWR_CR1_SRAM6PD) +/** + * @brief Set the SRAM6 retention in Run mode. + * @rmtoll CR1 SRAM6PD LL_PWR_SetSRAM6RunRetention\n + * @param SRAM6Retention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM6_RUN_NO_RETENTION + * @arg @ref LL_PWR_SRAM6_RUN_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM6RunRetention(uint32_t SRAM6Retention) +{ + MODIFY_REG(PWR->CR1, LL_PWR_SRAM6_RUN_FULL_RETENTION, ((~SRAM6Retention) & LL_PWR_SRAM6_RUN_FULL_RETENTION)); +} + +/** + * @brief Get the SRAM6 retention in Run mode. + * @rmtoll CR1 SRAM6PD LL_PWR_GetSRAM6RunRetention\n + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM6_RUN_NO_RETENTION + * @arg @ref LL_PWR_SRAM6_RUN_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM6RunRetention(void) +{ + return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM6_RUN_FULL_RETENTION))) & LL_PWR_SRAM6_RUN_FULL_RETENTION); +} +#endif /* defined (PWR_CR1_SRAM6PD) */ + +#if defined (PWR_CR1_FORCE_USBPWR) +/** + * @brief Enable OTG_HS PHY power during low power modes (Stop2, Stop 3 and Standby). + * @rmtoll CR1 FORCE_USBPWR LL_PWR_EnableOTGHSPHYLowPowerRetention + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableOTGHSPHYLowPowerRetention(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR); +} + +/** + * @brief Disable OTG_HS PHY power during low power modes (Stop2, Stop 3 and Standby). + * @rmtoll CR1 FORCE_USBPWR LL_PWR_DisableOTGHSPHYLowPowerRetention + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableOTGHSPHYLowPowerRetention(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR); +} + +/** + * @brief Check if OTG_HS PHY power during low power modes (Stop2, Stop 3 and Standby) is enabled. + * @rmtoll CR1 FORCE_USBPWR LL_PWR_IsEnabledOTGHSPHYLowPowerRetention + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledOTGHSPHYLowPowerRetention(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR) == (PWR_CR1_FORCE_USBPWR)) ? 1UL : 0UL); +} +#endif /* defined (PWR_CR1_FORCE_USBPWR) */ + +/** + * @brief Set the SRAM1 page(s) (From page 1 to page 3) retention in Stop mode. + * @rmtoll CR2 SRAM1PDS1 LL_PWR_SetSRAM1StopRetention_1_3\n + * @rmtoll CR2 SRAM1PDS2 LL_PWR_SetSRAM1StopRetention_1_3\n + * @rmtoll CR2 SRAM1PDS3 LL_PWR_SetSRAM1StopRetention_1_3 + * @param SRAM1PageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_1_3_RETENTION + * Or can be a combination of the following values: + * @arg @ref LL_PWR_SRAM1_STOP_PAGE1_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE2_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE3_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM1StopRetention_1_3(uint32_t SRAM1PageRetention) +{ + MODIFY_REG(PWR->CR2, LL_PWR_SRAM1_STOP_1_3_RETENTION, ((~SRAM1PageRetention) & LL_PWR_SRAM1_STOP_1_3_RETENTION)); +} + +#if defined (PWR_CR4_SRAM1PDS4) +/** + * @brief Set the SRAM1 page(s) (From page 4 to page 12) retention in Stop mode. + * @rmtoll CR2 SRAM1PDS4 LL_PWR_SetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS5 LL_PWR_SetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS6 LL_PWR_SetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS7 LL_PWR_SetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS8 LL_PWR_SetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS9 LL_PWR_SetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS10 LL_PWR_SetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS11 LL_PWR_SetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS12 LL_PWR_SetSRAM1StopRetention_4_12 + * @param SRAM1PageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_4_12_RETENTION + * Or can be a combination of the following values: + * @arg @ref LL_PWR_SRAM1_STOP_PAGE4_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE5_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE6_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE7_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE8_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE9_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE10_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE11_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE12_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM1StopRetention_4_12(uint32_t SRAM1PageRetention) +{ + MODIFY_REG(PWR->CR4, LL_PWR_SRAM1_STOP_4_12_RETENTION, ((~SRAM1PageRetention) & LL_PWR_SRAM1_STOP_4_12_RETENTION)); +} +#endif /* defined (PWR_CR4_SRAM1PDS4) */ + +/** + * @brief Get the SRAM1 page(s) (From page 1 to page 3) retention in Stop mode. + * @rmtoll CR2 SRAM1PDS1 LL_PWR_GetSRAM1StopRetention_1_3\n + * @rmtoll CR2 SRAM1PDS2 LL_PWR_GetSRAM1StopRetention_1_3\n + * @rmtoll CR2 SRAM1PDS3 LL_PWR_GetSRAM1StopRetention_1_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_1_3_RETENTION + * Or a combination of the following values: + * @arg @ref LL_PWR_SRAM1_STOP_PAGE1_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE2_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE3_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM1StopRetention_1_3(void) +{ + return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM1_STOP_1_3_RETENTION))) & LL_PWR_SRAM1_STOP_1_3_RETENTION); +} + +#if defined (PWR_CR4_SRAM1PDS4) +/** + * @brief Get the SRAM1 page(s) (From page 4 to page 12) retention in Stop mode. + * @rmtoll CR2 SRAM1PDS4 LL_PWR_GetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS5 LL_PWR_GetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS6 LL_PWR_GetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS7 LL_PWR_GetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS8 LL_PWR_GetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS9 LL_PWR_GetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS10 LL_PWR_GetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS11 LL_PWR_GetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS12 LL_PWR_GetSRAM1StopRetention_4_12 + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_4_12_RETENTION + * Or a combination of the following values: + * @arg @ref LL_PWR_SRAM1_STOP_PAGE4_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE5_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE6_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE7_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE8_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE9_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE10_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE11_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE12_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM1StopRetention_4_12(void) +{ + return ((~(READ_BIT(PWR->CR4, LL_PWR_SRAM1_STOP_4_12_RETENTION))) & LL_PWR_SRAM1_STOP_4_12_RETENTION); +} +#endif /* defined (PWR_CR4_SRAM1PDS4) */ + +/** + * @brief Set the SRAM2 page(s) retention in Stop mode. + * @rmtoll CR2 SRAM2PDS1 LL_PWR_SetSRAM2StopRetention\n + * @rmtoll CR2 SRAM2PDS2 LL_PWR_SetSRAM2StopRetention + * @param SRAM2PageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM2_STOP_PAGE1_RETENTION + * @arg @ref LL_PWR_SRAM2_STOP_PAGE2_RETENTION + * @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM2StopRetention(uint32_t SRAM2PageRetention) +{ + MODIFY_REG(PWR->CR2, LL_PWR_SRAM2_STOP_FULL_RETENTION, ((~SRAM2PageRetention) & LL_PWR_SRAM2_STOP_FULL_RETENTION)); +} + +/** + * @brief Get the SRAM2 page(s) retention in Stop mode. + * @rmtoll CR2 SRAM2PDS1 LL_PWR_GetSRAM2StopRetention\n + * @rmtoll CR2 SRAM2PDS2 LL_PWR_GetSRAM2StopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM2_STOP_PAGE1_RETENTION + * @arg @ref LL_PWR_SRAM2_STOP_PAGE2_RETENTION + * @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM2StopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM2_STOP_FULL_RETENTION))) & LL_PWR_SRAM2_STOP_FULL_RETENTION); +} + +#if defined (PWR_CR2_SRAM3PDS1) +/** + * @brief Set the SRAM3 page(s) (From page 1 to page 8) retention in Stop mode. + * @rmtoll CR2 SRAM3PDS1 LL_PWR_SetSRAM3StopRetention_1_8\n + * @rmtoll CR2 SRAM3PDS2 LL_PWR_SetSRAM3StopRetention_1_8\n + * @rmtoll CR2 SRAM3PDS3 LL_PWR_SetSRAM3StopRetention_1_8\n + * @rmtoll CR2 SRAM3PDS4 LL_PWR_SetSRAM3StopRetention_1_8\n + * @rmtoll CR2 SRAM3PDS5 LL_PWR_SetSRAM3StopRetention_1_8\n + * @rmtoll CR2 SRAM3PDS6 LL_PWR_SetSRAM3StopRetention_1_8\n + * @rmtoll CR2 SRAM3PDS7 LL_PWR_SetSRAM3StopRetention_1_8\n + * @rmtoll CR2 SRAM3PDS8 LL_PWR_SetSRAM3StopRetention_1_8 + * @param SRAM3PageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_1_8_RETENTION + * Or can be a combination of the following values: + * @arg @ref LL_PWR_SRAM3_STOP_PAGE1_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE2_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE3_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE4_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE5_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE6_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE7_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE8_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM3StopRetention_1_8(uint32_t SRAM3PageRetention) +{ + MODIFY_REG(PWR->CR2, LL_PWR_SRAM3_STOP_1_8_RETENTION, ((~SRAM3PageRetention) & LL_PWR_SRAM3_STOP_1_8_RETENTION)); +} + +#if defined (PWR_CR4_SRAM3PDS9) +/** + * @brief Set the SRAM3 page(s) (From page 9 to page 13) retention in Stop mode. + * @rmtoll CR2 SRAM3PDS9 LL_PWR_SetSRAM3StopRetention_9_13\n + * @rmtoll CR2 SRAM3PDS10 LL_PWR_SetSRAM3StopRetention_9_13\n + * @rmtoll CR2 SRAM3PDS11 LL_PWR_SetSRAM3StopRetention_9_13\n + * @rmtoll CR2 SRAM3PDS12 LL_PWR_SetSRAM3StopRetention_9_13\n + * @rmtoll CR2 SRAM3PDS13 LL_PWR_SetSRAM3StopRetention_9_13 + * @param SRAM3PageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_9_13_RETENTION + * Or can be a combination of the following values: + * @arg @ref LL_PWR_SRAM3_STOP_PAGE9_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE10_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE11_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE12_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE13_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM3StopRetention_9_13(uint32_t SRAM3PageRetention) +{ + MODIFY_REG(PWR->CR4, LL_PWR_SRAM3_STOP_9_13_RETENTION, ((~SRAM3PageRetention) & LL_PWR_SRAM3_STOP_9_13_RETENTION)); +} +#endif /* defined (PWR_CR4_SRAM3PDS9) */ + +/** + * @brief Get the SRAM3 page(s) (From page 1 to page 8) retention in Stop mode. + * @rmtoll CR2 SRAM3PDS1 LL_PWR_GetSRAM3StopRetention_1_8\n + * @rmtoll CR2 SRAM3PDS2 LL_PWR_GetSRAM3StopRetention_1_8\n + * @rmtoll CR2 SRAM3PDS3 LL_PWR_GetSRAM3StopRetention_1_8\n + * @rmtoll CR2 SRAM3PDS4 LL_PWR_GetSRAM3StopRetention_1_8\n + * @rmtoll CR2 SRAM3PDS5 LL_PWR_GetSRAM3StopRetention_1_8\n + * @rmtoll CR2 SRAM3PDS6 LL_PWR_GetSRAM3StopRetention_1_8\n + * @rmtoll CR2 SRAM3PDS7 LL_PWR_GetSRAM3StopRetention_1_8\n + * @rmtoll CR2 SRAM3PDS8 LL_PWR_GetSRAM3StopRetention_1_8 + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_1_8_RETENTION + * Or can be a combination of the following values: + * @arg @ref LL_PWR_SRAM3_STOP_PAGE1_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE2_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE3_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE4_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE5_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE6_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE7_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE8_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM3StopRetention_1_8(void) +{ + return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM3_STOP_1_8_RETENTION))) & LL_PWR_SRAM3_STOP_1_8_RETENTION); +} + +#if defined (PWR_CR4_SRAM3PDS9) +/** + * @brief Get the SRAM3 page(s) (From page 9 to page 13) retention in Stop mode. + * @rmtoll CR2 SRAM3PDS9 LL_PWR_SetSRAM3StopRetention_9_13\n + * @rmtoll CR2 SRAM3PDS10 LL_PWR_SetSRAM3StopRetention_9_13\n + * @rmtoll CR2 SRAM3PDS11 LL_PWR_SetSRAM3StopRetention_9_13\n + * @rmtoll CR2 SRAM3PDS12 LL_PWR_SetSRAM3StopRetention_9_13\n + * @rmtoll CR2 SRAM3PDS13 LL_PWR_SetSRAM3StopRetention_9_13 + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_9_13_RETENTION + * Or can be a combination of the following values: + * @arg @ref LL_PWR_SRAM3_STOP_PAGE9_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE10_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE11_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE12_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE13_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM3StopRetention_9_13(void) +{ + return ((~(READ_BIT(PWR->CR4, LL_PWR_SRAM3_STOP_9_13_RETENTION))) & LL_PWR_SRAM3_STOP_9_13_RETENTION); +} +#endif /* defined (PWR_CR4_SRAM3PDS9) */ +#endif /* PWR_CR2_SRAM3PDS1 */ + +/** + * @brief Set the SRAM4 page retention in Stop mode. + * @rmtoll CR2 SRAM4PDS LL_PWR_SetSRAM4StopRetention\n + * @param SRAM4PageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM4_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM4_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM4StopRetention(uint32_t SRAM4PageRetention) +{ + MODIFY_REG(PWR->CR2, LL_PWR_SRAM4_STOP_FULL_RETENTION, ((~SRAM4PageRetention) & LL_PWR_SRAM4_STOP_FULL_RETENTION)); +} + +/** + * @brief Get the SRAM4 page retention in Stop mode. + * @rmtoll CR2 SRAM4PDS LL_PWR_GetSRAM4StopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM4_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM4_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM4StopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM4_STOP_FULL_RETENTION))) & LL_PWR_SRAM4_STOP_FULL_RETENTION); +} + +#if defined (PWR_CR4_SRAM5PDS1) +/** + * @brief Set the SRAM5 page(s) retention in Stop mode. + * @rmtoll CR4 SRAM5PDS1 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS2 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS3 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS4 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS5 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS6 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS7 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS8 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS9 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS10 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS11 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS12 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS13 LL_PWR_SetSRAM5StopRetention + * @param SRAM5PageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM5_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_FULL_RETENTION + * Or can be a combination of the following values: + * @arg @ref LL_PWR_SRAM5_STOP_PAGE1_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE2_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE3_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE4_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE5_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE6_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE7_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE8_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE9_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE10_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE11_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE12_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE13_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM5StopRetention(uint32_t SRAM5PageRetention) +{ + MODIFY_REG(PWR->CR4, LL_PWR_SRAM5_STOP_FULL_RETENTION, ((~SRAM5PageRetention) & LL_PWR_SRAM5_STOP_FULL_RETENTION)); +} + +/** + * @brief Get the SRAM5 page(s) retention in Stop mode. + * @rmtoll CR4 SRAM5PDS1 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS2 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS3 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS4 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS5 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS6 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS7 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS8 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS9 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS10 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS11 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS12 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS13 LL_PWR_GetSRAM5StopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM5_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_FULL_RETENTION + * Or can be a combination of the following values: + * @arg @ref LL_PWR_SRAM5_STOP_PAGE1_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE2_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE3_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE4_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE5_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE6_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE7_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE8_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE9_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE10_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE11_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE12_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE13_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM5StopRetention(void) +{ + return ((~(READ_BIT(PWR->CR4, LL_PWR_SRAM5_STOP_FULL_RETENTION))) & LL_PWR_SRAM5_STOP_FULL_RETENTION); +} +#endif /* defined (PWR_CR4_SRAM5PDS1) */ + +#if defined (PWR_CR5_SRAM6PDS1) +/** + * @brief Set the SRAM6 page(s) retention in Stop mode. + * @rmtoll CR5 SRAM6PDS1 LL_PWR_SetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS2 LL_PWR_SetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS3 LL_PWR_SetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS4 LL_PWR_SetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS5 LL_PWR_SetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS6 LL_PWR_SetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS7 LL_PWR_SetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS8 LL_PWR_SetSRAM6StopRetention + * @param SRAM6PageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM6_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_FULL_RETENTION + * Or can be a combination of the following values: + * @arg @ref LL_PWR_SRAM6_STOP_PAGE1_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE2_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE3_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE4_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE5_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE6_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE7_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE8_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM6StopRetention(uint32_t SRAM6PageRetention) +{ + MODIFY_REG(PWR->CR5, LL_PWR_SRAM6_STOP_FULL_RETENTION, ((~SRAM6PageRetention) & LL_PWR_SRAM6_STOP_FULL_RETENTION)); +} + +/** + * @brief Get the SRAM6 page(s) retention in Stop mode. + * @rmtoll CR5 SRAM6PDS1 LL_PWR_GetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS2 LL_PWR_GetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS3 LL_PWR_GetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS4 LL_PWR_GetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS5 LL_PWR_GetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS6 LL_PWR_GetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS7 LL_PWR_GetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS8 LL_PWR_GetSRAM6StopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM6_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_FULL_RETENTION + * Or can be a combination of the following values: + * @arg @ref LL_PWR_SRAM6_STOP_PAGE1_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE2_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE3_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE4_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE5_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE6_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE7_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE8_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM6StopRetention(void) +{ + return ((~(READ_BIT(PWR->CR5, LL_PWR_SRAM6_STOP_FULL_RETENTION))) & LL_PWR_SRAM6_STOP_FULL_RETENTION); +} +#endif /* defined (PWR_CR5_SRAM6PDS1) */ + +/** + * @brief Set the ICACHE SRAM page retention in Stop mode. + * @rmtoll CR2 ICRAMPDS LL_PWR_SetICacheRAMStopRetention\n + * @param ICachePageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_ICACHERAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_ICACHERAM_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetICacheRAMStopRetention(uint32_t ICachePageRetention) +{ + MODIFY_REG(PWR->CR2, LL_PWR_ICACHERAM_STOP_FULL_RETENTION, + ((~ICachePageRetention) & LL_PWR_ICACHERAM_STOP_FULL_RETENTION)); +} + +/** + * @brief Get the ICACHE SRAM page retention in Stop mode. + * @rmtoll CR2 ICRAMPDS LL_PWR_GetICacheRAMStopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_ICACHERAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_ICACHERAM_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetICacheRAMStopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, LL_PWR_ICACHERAM_STOP_FULL_RETENTION))) & LL_PWR_ICACHERAM_STOP_FULL_RETENTION); +} + +/** + * @brief Set the DCACHE1 SRAM page retention in Stop mode. + * @rmtoll CR2 DC1RAMPDS LL_PWR_SetDCache1RAMStopRetention\n + * @param DCache1PageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_DCACHE1RAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetDCache1RAMStopRetention(uint32_t DCache1PageRetention) +{ + MODIFY_REG(PWR->CR2, LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION, + ((~DCache1PageRetention) & LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION)); +} + +/** + * @brief Get the DCACHE1 SRAM page retention in Stop mode. + * @rmtoll CR2 DC1RAMPDS LL_PWR_GetDCache1RAMStopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_DCACHE1RAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetDCache1RAMStopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION))) & LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION); +} + +#if defined (PWR_CR2_DC2RAMPDS) +/** + * @brief Set the DCACHE2 SRAM page retention in Stop mode. + * @rmtoll CR2 DC2RAMPDS LL_PWR_SetDCache2RAMStopRetention\n + * @param DCache2PageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_DCACHE2RAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetDCache2RAMStopRetention(uint32_t DCache2PageRetention) +{ + MODIFY_REG(PWR->CR2, LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION, + ((~DCache2PageRetention) & LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION)); +} + +/** + * @brief Get the DCACHE2 SRAM page retention in Stop mode. + * @rmtoll CR2 DC2RAMPDS LL_PWR_GetDCache2RAMStopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_DCACHE2RAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetDCache2RAMStopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION))) & LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION); +} +#endif /* defined (PWR_CR2_DC2RAMPDS) */ + +#if defined (PWR_CR2_DMA2DRAMPDS) +/** + * @brief Set the DMA2D SRAM page retention in Stop mode. + * @rmtoll CR2 DMA2DRAMPDS LL_PWR_SetDMA2DRAMStopRetention\n + * @param DMA2DRAMPageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_DMA2DRAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_DMA2DRAM_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetDMA2DRAMStopRetention(uint32_t DMA2DRAMPageRetention) +{ + MODIFY_REG(PWR->CR2, LL_PWR_DMA2DRAM_STOP_FULL_RETENTION, + ((~DMA2DRAMPageRetention) & LL_PWR_DMA2DRAM_STOP_FULL_RETENTION)); +} + +/** + * @brief Get the DMA2D SRAM page retention in Stop mode. + * @rmtoll CR2 DMA2DRAMPDS LL_PWR_GetDMA2DRAMStopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_DMA2DRAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_DMA2DRAM_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetDMA2DRAMStopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, LL_PWR_DMA2DRAM_STOP_FULL_RETENTION))) & LL_PWR_DMA2DRAM_STOP_FULL_RETENTION); +} +#endif /* PWR_CR2_DMA2DRAMPDS */ + +/** + * @brief Set the FMAC, FDCAN and USB SRAMs pages retention in Stop mode. + * @rmtoll CR2 PRAMPDS LL_PWR_SetPeriphRAMStopRetention\n + * @param PriphRAMPageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_PERIPHRAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_PERIPHRAM_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPeriphRAMStopRetention(uint32_t PriphRAMPageRetention) +{ + MODIFY_REG(PWR->CR2, LL_PWR_PERIPHRAM_STOP_FULL_RETENTION, + ((~PriphRAMPageRetention) & LL_PWR_PERIPHRAM_STOP_FULL_RETENTION)); +} + +/** + * @brief Get the FMAC, FDCAN and USB SRAMs pages retention in Stop mode. + * @rmtoll CR2 PRAMPDS LL_PWR_GetPeriphRAMStopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PERIPHRAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_PERIPHRAM_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetPeriphRAMStopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, LL_PWR_PERIPHRAM_STOP_FULL_RETENTION))) & LL_PWR_PERIPHRAM_STOP_FULL_RETENTION); +} + +#if defined (PWR_CR2_PKARAMPDS) +/** + * @brief Set the PKA32 SRAM page retention in Stop mode. + * @rmtoll CR2 PKARAMPDS LL_PWR_SetPKARAMStopRetention + * @param PKARAMPageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_PKARAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_PKARAM_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPKARAMStopRetention(uint32_t PKARAMPageRetention) +{ + MODIFY_REG(PWR->CR2, LL_PWR_PKARAM_STOP_FULL_RETENTION, ((~PKARAMPageRetention) & LL_PWR_PKARAM_STOP_FULL_RETENTION)); +} + +/** + * @brief Get the PKA32 SRAM page retention in Stop mode. + * @rmtoll CR2 PKARAMPDS LL_PWR_GetPKARAMStopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PKARAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_PKARAM_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetPKARAMStopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, LL_PWR_PKARAM_STOP_FULL_RETENTION))) & LL_PWR_PKARAM_STOP_FULL_RETENTION); +} +#endif /* defined (PWR_CR2_PKARAMPDS) */ + +#if defined (PWR_CR2_GPRAMPDS) +/** + * @brief Set the Graphic peripherals (LTDC, GFXMMU) SRAM page retention in Stop mode. + * @rmtoll CR2 GPRAMPDS LL_PWR_SetGraphicPeriphRAMStopRetention + * @param GraphicPeriphRAMPageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_GRAPHICPERIPHRAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetGraphicPeriphRAMStopRetention(uint32_t GraphicPeriphRAMPageRetention) +{ + MODIFY_REG(PWR->CR2, LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION, + ((~GraphicPeriphRAMPageRetention) & LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION)); +} + +/** + * @brief Get the Graphic peripherals (LTDC, GFXMMU) SRAM page retention in Stop mode. + * @rmtoll CR2 GPRAMPDS LL_PWR_GetGraphicPeriphRAMStopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_GRAPHICPERIPHRAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetGraphicPeriphRAMStopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION))) & + LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION); +} +#endif /* defined (PWR_CR2_GPRAMPDS) */ + +#if defined (PWR_CR2_DSIRAMPDS) +/** + * @brief Set the DSI SRAM page retention in Stop mode. + * @rmtoll CR2 DSIRAMPDS LL_PWR_SetDSIRAMStopRetention + * @param DSIRAMPageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_DSIRAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_DSIRAM_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetDSIRAMStopRetention(uint32_t DSIRAMPageRetention) +{ + MODIFY_REG(PWR->CR2, LL_PWR_DSIRAM_STOP_FULL_RETENTION, ((~DSIRAMPageRetention) & LL_PWR_DSIRAM_STOP_FULL_RETENTION)); +} + +/** + * @brief Get the DSI SRAM page retention in Stop mode. + * @rmtoll CR2 DSIRAMPDS LL_PWR_GetDSIRAMStopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_DSIRAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_DSIRAM_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetDSIRAMStopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, LL_PWR_DSIRAM_STOP_FULL_RETENTION))) & LL_PWR_DSIRAM_STOP_FULL_RETENTION); +} +#endif /* defined (PWR_CR2_DSIRAMPDS) */ + +#if defined (PWR_CR2_JPEGRAMPDS) +/** + * @brief Set the JPEG SRAM page retention in Stop mode. + * @rmtoll CR2 JPEGRAMPDS LL_PWR_SetJPEGRAMStopRetention + * @param JPEGRAMPageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_JPEGRAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_JPEGRAM_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetJPEGRAMStopRetention(uint32_t JPEGRAMPageRetention) +{ + MODIFY_REG(PWR->CR2, LL_PWR_JPEGRAM_STOP_FULL_RETENTION, + ((~JPEGRAMPageRetention) & LL_PWR_JPEGRAM_STOP_FULL_RETENTION)); +} + +/** + * @brief Get the JPEG SRAM page retention in Stop mode. + * @rmtoll CR2 JPEGRAMPDS LL_PWR_GetJPEGRAMStopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_JPEGRAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_JPEGRAM_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetJPEGRAMStopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, LL_PWR_JPEGRAM_STOP_FULL_RETENTION))) & LL_PWR_JPEGRAM_STOP_FULL_RETENTION); +} +#endif /* defined (PWR_CR2_JPEGRAMPDS) */ + +/** + * @brief Enable the flash memory fast wakeup from Stop mode (Stop 0, 1). + * @rmtoll CR2 FLASHFWU LL_PWR_EnableFlashFastWakeUp + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFlashFastWakeUp(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_FLASHFWU); +} + +/** + * @brief Disable the flash memory fast wakeup from Stop mode (Stop 0, 1). + * @rmtoll CR2 FLASHFWU LL_PWR_DisableFlashFastWakeUp + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFlashFastWakeUp(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_FLASHFWU); +} + +/** + * @brief Check if the flash memory fast wakeup from Stop mode (Stop 0, 1) + * is enabled. + * @rmtoll CR2 FLASHFWU LL_PWR_IsEnabledFlashFastWakeUp + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashFastWakeUp(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_FLASHFWU) == (PWR_CR2_FLASHFWU)) ? 1UL : 0UL); +} + +/** + * @brief Enable the SRAM4 memory fast wakeup from Stop mode (Stop 0, 1, 2). + * @rmtoll CR2 SRAM4FWU LL_PWR_EnableSRAM4FastWakeUp + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableSRAM4FastWakeUp(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_SRAM4FWU); +} + +/** + * @brief Disable the SRAM4 memory fast wakeup from Stop mode (Stop 0, 1, 2). + * @rmtoll CR2 SRAM4FWU LL_PWR_DisableSRAM4FastWakeUp + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableSRAM4FastWakeUp(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_SRAM4FWU); +} + +/** + * @brief Check if the SRAM4 memory fast wakeup from Stop mode (Stop 0, 1, 2). + * is enabled. + * @rmtoll CR2 SRAM4FWU LL_PWR_IsEnabledSRAM4FastWakeUp + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM4FastWakeUp(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_SRAM4FWU) == (PWR_CR2_SRAM4FWU)) ? 1UL : 0UL); +} + +/** + * @brief Set the smart run domain mode. + * @rmtoll CR2 SRDRUN LL_PWR_SetSmartRunDomainMode + * @param SRDMode : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRD_RUN_MODE + * @arg @ref LL_PWR_SRD_STOP_MODE + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSmartRunDomainMode(uint32_t SRDMode) +{ + MODIFY_REG(PWR->CR2, PWR_CR2_SRDRUN, SRDMode); +} + +/** + * @brief Get the smart run domain mode. + * @rmtoll CR2 SRDRUN LL_PWR_GetSmartRunDomainMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRD_RUN_MODE + * @arg @ref LL_PWR_SRD_STOP_MODE + */ +__STATIC_INLINE uint32_t LL_PWR_GetSmartRunDomainMode(void) +{ + return (READ_BIT(PWR->CR2, PWR_CR2_SRDRUN)); +} + +/** + * @brief Set the VCore regulator supply. + * @rmtoll CR3 REGSEL LL_PWR_SetRegulatorSupply + * @param RegulatorSupply : This parameter can be one of the following values: + * @arg @ref LL_PWR_LDO_SUPPLY + * @arg @ref LL_PWR_SMPS_SUPPLY + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulatorSupply(uint32_t RegulatorSupply) +{ + MODIFY_REG(PWR->CR3, PWR_CR3_REGSEL, RegulatorSupply); +} + +/** + * @brief Get the VCore regulator supply. + * @rmtoll CR3 REGSEL LL_PWR_GetRegulatorSupply + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_LDO_SUPPLY + * @arg @ref LL_PWR_SMPS_SUPPLY + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulatorSupply(void) +{ + return (READ_BIT(PWR->CR3, PWR_CR3_REGSEL)); +} + +/** + * @brief Enable the fast soft start for selected regulator. + * @rmtoll CR3 FSTEN LL_PWR_EnableFastSoftStart + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFastSoftStart(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_FSTEN); +} + +/** + * @brief Disable the fast soft start for selected regulator. + * @rmtoll CR3 FSTEN LL_PWR_DisableFastSoftStart + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFastSoftStart(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_FSTEN); +} + +/** + * @brief Check if the fast soft start for selected regulator is enabled. + * @rmtoll CR3 FSTEN LL_PWR_IsEnabledFastSoftStart + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledFastSoftStart(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_FSTEN) == (PWR_CR3_FSTEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the regulator supply output voltage. + * @rmtoll VOSR VOS LL_PWR_SetRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) +{ + MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, VoltageScaling); +} + +/** + * @brief Get the regulator supply output voltage. + * @rmtoll VOSR VOS LL_PWR_GetRegulVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4 + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(PWR->VOSR, PWR_VOSR_VOS)); +} + +/** + * @brief Enable the EPOD (Embedded Power Distribution) booster. + * @rmtoll VOSR BOOSTEN LL_PWR_EnableEPODBooster + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableEPODBooster(void) +{ + SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN); +} + +/** + * @brief Disable the EPOD (Embedded Power Distribution) booster. + * @rmtoll VOSR BOOSTEN LL_PWR_DisableEPODBooster + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableEPODBooster(void) +{ + CLEAR_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN); +} + +/** + * @brief Check if the EPOD (Embedded Power Distribution) booster is enabled. + * @rmtoll VOSR BOOSTEN LL_PWR_IsEnabledEPODBooster + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledEPODBooster(void) +{ + return ((READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) == (PWR_VOSR_BOOSTEN)) ? 1UL : 0UL); +} + +#if defined (PWR_VOSR_USBPWREN) +/** + * @brief Enable the USB power supply. + * @rmtoll VOSR USBPWREN LL_PWR_EnableUSBPowerSupply + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUSBPowerSupply(void) +{ + SET_BIT(PWR->VOSR, PWR_VOSR_USBPWREN); +} + +/** + * @brief Disable the USB power supply. + * @rmtoll VOSR USBPWREN LL_PWR_DisableUSBPowerSupply + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUSBPowerSupply(void) +{ + CLEAR_BIT(PWR->VOSR, PWR_VOSR_USBPWREN); +} + +/** + * @brief Check if the USB power supply is enabled. + * @rmtoll VOSR USBPWREN LL_PWR_IsEnabledUSBPowerSupply + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBPowerSupply(void) +{ + return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBPWREN) == (PWR_VOSR_USBPWREN)) ? 1UL : 0UL); +} +#endif /* defined (PWR_VOSR_USBPWREN) */ + +#if defined (PWR_VOSR_USBBOOSTEN) +/** + * @brief Enable the USB EPOD (Embedded Power Distribution) booster. + * @rmtoll VOSR USBBOOSTEN LL_PWR_EnableUSBEPODBooster + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUSBEPODBooster(void) +{ + SET_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN); +} + +/** + * @brief Disable the USB EPOD (Embedded Power Distribution) booster. + * @rmtoll VOSR USBBOOSTEN LL_PWR_DisableUSBEPODBooster + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUSBEPODBooster(void) +{ + CLEAR_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN); +} + +/** + * @brief Check if the USB EPOD (Embedded Power Distribution) booster is enabled. + * @rmtoll VOSR USBBOOSTEN LL_PWR_IsEnabledUSBEPODBooster + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBEPODBooster(void) +{ + return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN) == (PWR_VOSR_USBBOOSTEN)) ? 1UL : 0UL); +} +#endif /* defined (PWR_VOSR_USBBOOSTEN) */ + +#if defined (PWR_VOSR_VDD11USBDIS) +/** + * @brief Enable the VDD11USB. + * @rmtoll VOSR VDD11USBDIS LL_PWR_EnableVDD11USB + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVDD11USB(void) +{ + CLEAR_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS); +} + +/** + * @brief Disable the VDD11USB. + * @rmtoll VOSR VDD11USBDIS LL_PWR_DisableVDD11USB + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVDD11USB(void) +{ + SET_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS); +} + +/** + * @brief Check if the VDD11USB is enabled. + * @rmtoll VOSR VDD11USBDIS LL_PWR_IsEnabledVDD11USB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVDD11USB(void) +{ + return ((READ_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS) == (0U)) ? 1UL : 0UL); +} +#endif /* defined (PWR_VOSR_VDD11USBDIS) */ + +/** + * @brief Set the Power voltage detector level. + * @rmtoll SVMCR PVDLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->SVMCR, PWR_SVMCR_PVDLS, PVDLevel); +} + +/** + * @brief Get the Power voltage detector level. + * @rmtoll SVMCR PVDLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return (READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDLS)); +} + +/** + * @brief Enable the power voltage detector. + * @rmtoll SVMCR PVDE LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_PVDE); +} + +/** + * @brief Disable the power voltage detector. + * @rmtoll SVMCR PVDE LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_PVDE); +} + +/** + * @brief Check if the power voltage detector is enabled. + * @rmtoll SVMCR PVDE LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDE) == (PWR_SVMCR_PVDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the independent USB supply. + * @rmtoll SVMCR USV LL_PWR_EnableVddUSB + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddUSB(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_USV); +} +#define LL_PWR_EnableVDDUSB LL_PWR_EnableVddUSB /* for legacy purpose */ + +/** + * @brief Disable the independent USB supply. + * @rmtoll SVMCR USV LL_PWR_DisableVDDUSB + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddUSB(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_USV); +} +#define LL_PWR_DisableVDDUSB LL_PWR_DisableVddUSB /* for legacy purpose */ + +/** + * @brief Check if the independent USB supply is enabled. + * @rmtoll SVMCR USV LL_PWR_IsEnabledVddUSB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) +{ + return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_USV) == (PWR_SVMCR_USV)) ? 1UL : 0UL); +} +#define LL_PWR_IsEnabledVDDUSB LL_PWR_IsEnabledVddUSB /* for legacy purpose */ + +/** + * @brief Enable the independent I/Os supply. + * @rmtoll SVMCR IO2SV LL_PWR_EnableVddIO2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddIO2(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV); +} +#define LL_PWR_EnableVDDIO2 LL_PWR_EnableVddIO2 /* for legacy purpose */ + +/** + * @brief Disable the independent I/Os supply. + * @rmtoll SVMCR IO2SV LL_PWR_DisableVddIO2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddIO2(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV); +} +#define LL_PWR_DisableVDDIO2 LL_PWR_DisableVddIO2 /* for legacy purpose */ + +/** + * @brief Check if the independent I/Os supply is enabled. + * @rmtoll SVMCR IO2SV LL_PWR_IsEnabledVddIO2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) +{ + return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV) == (PWR_SVMCR_IO2SV)) ? 1UL : 0UL); +} +#define LL_PWR_IsEnabledVDDIO2 LL_PWR_IsEnabledVddIO2 /* for legacy purpose */ + +/** + * @brief Enable the independent analog supply. + * @rmtoll SVMCR ASV LL_PWR_EnableVddA + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddA(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_ASV); +} +#define LL_PWR_EnableVDDA LL_PWR_EnableVddA /* for legacy purpose */ + +/** + * @brief Disable the independent analog supply. + * @rmtoll SVMCR ASV LL_PWR_DisableVddA + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddA(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_ASV); +} +#define LL_PWR_DisableVDDA LL_PWR_DisableVddA /* for legacy purpose */ + +/** + * @brief Check if the independent analog supply is enabled. + * @rmtoll SVMCR ASV LL_PWR_IsEnabledVddA + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddA(void) +{ + return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_ASV) == (PWR_SVMCR_ASV)) ? 1UL : 0UL); +} +#define LL_PWR_IsEnabledVDDA LL_PWR_IsEnabledVddA /* for legacy purpose */ + +/** + * @brief Enable the independent USB supply monitor. + * @rmtoll SVMCR UVMEN LL_PWR_EnableVddUSBMonitor + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddUSBMonitor(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN); +} +#define LL_PWR_EnableVDDUSBMonitor LL_PWR_EnableVddUSBMonitor /* for legacy purpose */ + +/** + * @brief Disable the independent USB supply monitor. + * @rmtoll SVMCR UVMEN LL_PWR_DisableVddUSBMonitor + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddUSBMonitor(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN); +} +#define LL_PWR_DisableVDDUSBMonitor LL_PWR_DisableVddUSBMonitor /* for legacy purpose */ + +/** + * @brief Check if the independent USB supply monitor is enabled. + * @rmtoll SVMCR UVMEN LL_PWR_IsEnabledVddUSBMonitor + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSBMonitor(void) +{ + return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN) == (PWR_SVMCR_UVMEN)) ? 1UL : 0UL); +} +#define LL_PWR_IsEnabledVDDUSBMonitor LL_PWR_IsEnabledVddUSBMonitor /* for legacy purpose */ + +/** + * @brief Enable the independent I/Os supply monitor. + * @rmtoll SVMCR IO2VMEN LL_PWR_EnableVddIO2Monitor + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddIO2Monitor(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN); +} +#define LL_PWR_EnableVDDIO2Monitor LL_PWR_EnableVddIO2Monitor /* for legacy purpose */ + +/** + * @brief Disable the independent I/Os supply monitor. + * @rmtoll SVMCR IO2VMEN LL_PWR_DisableVddIO2Monitor + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddIO2Monitor(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN); +} +#define LL_PWR_DisableVDDIO2Monitor LL_PWR_DisableVddIO2Monitor /* for legacy purpose */ + +/** + * @brief Check if the independent I/Os supply monitor is enabled. + * @rmtoll SVMCR IO2VMEN LL_PWR_IsEnabledVddIO2Monitor + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2Monitor(void) +{ + return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN) == (PWR_SVMCR_IO2VMEN)) ? 1UL : 0UL); +} +#define LL_PWR_IsEnabledVDDIO2Monitor LL_PWR_IsEnabledVddIO2Monitor /* for legacy purpose */ + +/** + * @brief Enable the independent analog supply monitor 1. + * @rmtoll SVMCR AVM1EN LL_PWR_EnableVddAMonitor1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddAMonitor1(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN); +} +#define LL_PWR_EnableVDDAMonitor1 LL_PWR_EnableVddAMonitor1 /* for legacy purpose */ + +/** + * @brief Disable the independent analog supply monitor 1. + * @rmtoll SVMCR AVM1EN LL_PWR_DisableVddAMonitor1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddAMonitor1(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN); +} +#define LL_PWR_DisableVDDAMonitor1 LL_PWR_DisableVddAMonitor1 /* for legacy purpose */ + +/** + * @brief Check if the independent analog supply monitor 1 is enabled. + * @rmtoll SVMCR AVM1EN LL_PWR_IsEnabledVddAMonitor1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddAMonitor1(void) +{ + return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN) == (PWR_SVMCR_AVM1EN)) ? 1UL : 0UL); +} +#define LL_PWR_IsEnabledVDDAMonitor1 LL_PWR_IsEnabledVddAMonitor1 /* for legacy purpose */ + +/** + * @brief Enable the independent analog supply monitor 2. + * @rmtoll SVMCR AVM2EN LL_PWR_EnableVddAMonitor2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddAMonitor2(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN); +} +#define LL_PWR_EnableVDDAMonitor2 LL_PWR_EnableVddAMonitor2 /* for legacy purpose */ + +/** + * @brief Disable the independent analog supply monitor 2. + * @rmtoll SVMCR AVM2EN LL_PWR_DisableVddAMonitor2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddAMonitor2(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN); +} +#define LL_PWR_DisableVDDAMonitor2 LL_PWR_DisableVddAMonitor2 /* for legacy purpose */ + +/** + * @brief Check if the independent analog supply monitor 2 is enabled. + * @rmtoll SVMCR AVM2EN LL_PWR_IsEnabledVddAMonitor2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddAMonitor2(void) +{ + return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN) == (PWR_SVMCR_AVM2EN)) ? 1UL : 0UL); +} +#define LL_PWR_IsEnabledVDDAMonitor2 LL_PWR_IsEnabledVddAMonitor2 /* for legacy purpose */ + +/** + * @brief Enable the wake up pin_x. + * @rmtoll WUCR1 WUPENx LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->WUCR1, WakeUpPin); +} + +/** + * @brief Disable the wake up pin_x. + * @rmtoll WUCR1 WUPENx LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->WUCR1, WakeUpPin); +} + +/** + * @brief Check if the wake up pin_x is enabled. + * @rmtoll WUCR1 WUPENx LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->WUCR1, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); +} + +/** + * @brief Set the wake up pin polarity low for the event detection. + * @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + SET_BIT(PWR->WUCR2, WakeUpPin); +} + +/** + * @brief Set the wake up pin polarity high for the event detection. + * @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityHigh + * @param WakeUpPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->WUCR2, WakeUpPin); +} + +/** + * @brief Get the wake up pin polarity for the event detection. + * @rmtoll WUCR2 WUPPx LL_PWR_GetWakeUpPinPolarity + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval State of bit (1 : polarity or 0 : polarity high). + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPolarity(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->WUCR2, WakeUpPin) == WakeUpPin) ? 1UL : 0UL); +} + +/** + * @brief Set the wakeup pin_x selection 0. + * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal0Selection + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinSignal0Selection(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)), + (LL_PWR_WAKEUP_PIN_SELECTION_0 << (POSITION_VAL(WakeUpPin) * 2U))); +} + +/** + * @brief Set the wakeup pin_x selection 1. + * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal1Selection + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinSignal1Selection(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)), + (LL_PWR_WAKEUP_PIN_SELECTION_1 << (POSITION_VAL(WakeUpPin) * 2U))); +} + +/** + * @brief Set the wakeup pin_x selection 2. + * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal2Selection + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinSignal2Selection(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)), + (LL_PWR_WAKEUP_PIN_SELECTION_2 << (POSITION_VAL(WakeUpPin) * 2U))); +} + +/** + * @brief Set the wakeup pin_x selection 3. + * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal3Selection + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinSignal3Selection(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)), + (LL_PWR_WAKEUP_PIN_SELECTION_3 << (POSITION_VAL(WakeUpPin) * 2U))); +} + +/** + * @brief Get the wakeup pin_x selection. + * @rmtoll WUCR3 WUSELx LL_PWR_GetWakeUpPinSignalSelection + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinSignalSelection(uint32_t WakeUpPin) +{ + return (READ_BIT(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)))); +} + +/** + * @brief Enable backup regulator. + * @rmtoll BDCR1 BREN LL_PWR_EnableBkUpRegulator + * @note When this bit is set, the backup RAM content is kept in Standby and + * VBAT modes. If BREN is reset, the backup RAM can still be used in + * Run, Sleep and Stop modes. However, its content is lost in Standby, + * Shutdown and VBAT modes. This bit can be written only when the + * regulator is LDO, which must be configured before switching to SMPS. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void) +{ + SET_BIT(PWR->BDCR1, PWR_BDCR1_BREN); +} + +/** + * @brief Disable backup regulator + * @rmtoll BDCR1 BREN LL_PWR_DisableBkUpRegulator + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void) +{ + CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_BREN); +} + +/** + * @brief Check if the backup regulator is enabled + * @rmtoll BDCR1 BREN LL_PWR_IsEnabledBkUpRegulator + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void) +{ + return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_BREN) == (PWR_BDCR1_BREN)) ? 1UL : 0UL); +} + +/** + * @brief Enable the backup domain voltage and temperature monitoring. + * @rmtoll BDCR1 MONEN LL_PWR_EnableMonitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableMonitoring(void) +{ + SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); +} + +/** + * @brief Disable the backup domain voltage and temperature monitoring. + * @rmtoll BDCR1 MONEN LL_PWR_DisableMonitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableMonitoring(void) +{ + CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); +} + +/** + * @brief Check if the backup domain voltage and temperature monitoring is + * enabled. + * @rmtoll BDCR1 MONEN LL_PWR_IsEnabledMonitoring + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void) +{ + return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_MONEN) == (PWR_BDCR1_MONEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable battery charging. + * @rmtoll BDCR2 VBE LL_PWR_EnableBatteryCharging + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void) +{ + SET_BIT(PWR->BDCR2, PWR_BDCR2_VBE); +} + +/** + * @brief Disable battery charging. + * @rmtoll BDCR2 VBE LL_PWR_DisableBatteryCharging + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) +{ + CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_VBE); +} + +/** + * @brief Check if battery charging is enabled. + * @rmtoll BDCR2 VBE LL_PWR_IsEnabledBatteryCharging + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) +{ + return ((READ_BIT(PWR->BDCR2, PWR_BDCR2_VBE) == (PWR_BDCR2_VBE)) ? 1UL : 0UL); +} + +/** + * @brief Set the Battery charge resistor impedance + * @rmtoll BDCR2 VBRS LL_PWR_SetBattChargResistor + * @param Resistor This parameter can be one of the following values: + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_1_5K + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor) +{ + MODIFY_REG(PWR->BDCR2, PWR_BDCR2_VBRS, Resistor); +} + +/** + * @brief Get the Battery charge resistor impedance + * @rmtoll BDCR2 VBRS LL_PWR_GetBattChargResistor + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_1_5K + */ +__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void) +{ + return (uint32_t)(READ_BIT(PWR->BDCR2, PWR_BDCR2_VBRS)); +} + +/** + * @brief Enable access to the backup domain. + * @rmtoll DBPR DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->DBPR, PWR_DBPR_DBP); +} + +/** + * @brief Disable access to the backup domain. + * @rmtoll DBPR DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->DBPR, PWR_DBPR_DBP); +} + +/** + * @brief Check if the access to backup domain is enabled. + * @rmtoll DBPR DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return ((READ_BIT(PWR->DBPR, PWR_DBPR_DBP) == (PWR_DBPR_DBP)) ? 1UL : 0UL); +} + +#ifdef UCPD1 +/** + * @brief Enable the USB Type-C and Power Delivery memorization in Standby mode. + * @note This function must be called just before entering Standby mode. + * @rmtoll UCPDR UCPD_STDBY LL_PWR_EnableUCPDStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void) +{ + SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY); +} + +/** + * @brief Disable the USB Type-C and Power Delivery memorization in Standby mode. + * @note This function must be called after exiting Standby mode and before any + * UCPD configuration update. + * @rmtoll UCPDR UCPD_STDBY LL_PWR_DisableUCPDStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void) +{ + CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY); +} + +/** + * @brief Check the USB Type-C and Power Delivery Standby mode memorization state. + * @rmtoll UCPDR UCPD_STDBY LL_PWR_IsEnabledUCPDStandbyMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void) +{ + return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY) == (PWR_UCPDR_UCPD_STDBY)) ? 1UL : 0UL); +} + +/** + * @brief Enable the USB Type-C and power delivery dead battery pull-down behavior + * on UCPD CC1 and CC2 pins. + * @note After exiting reset, the USB Type-C dead battery behavior is enabled, + * which may have a pull-down effect on CC1 and CC2 pins. It is recommended + * to disable it in all cases, either to stop this pull-down or to hand over + * control to the UCPD (which should therefore be initialized before doing the disable). + * @rmtoll UCPDR UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void) +{ + CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); +} + +/** + * @brief Disable the USB Type-C and power delivery dead battery pull-down behavior + * on UCPD CC1 and CC2 pins. + * @note After exiting reset, the USB Type-C dead battery behavior is enabled, + * which may have a pull-down effect on CC1 and CC2 pins. It is recommended + * to disable it in all cases, either to stop this pull-down or to hand over + * control to the UCPD (which should therefore be initialized before doing the disable). + * @rmtoll UCPDR UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void) +{ + SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); +} + +/** + * @brief Check the USB Type-C and power delivery dead battery pull-down behavior + * on UCPD CC1 and CC2 pins. + * @note After exiting reset, the USB Type-C dead battery behavior is enabled, + * which may have a pull-down effect on CC1 and CC2 pins. It is recommended + * to disable it in all cases, either to stop this pull-down or to hand over + * control to the UCPD (which should therefore be initialized before doing the disable). + * @rmtoll UCPDR UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery + * @retval State of feature (1 : enabled; 0 : disabled). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void) +{ + return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS) == (PWR_UCPDR_UCPD_DBDIS)) ? 0UL : 1UL); +} +#endif /* UCPD1 */ + +/** + * @brief Enable the pull-up and pull-down configuration. + * @rmtoll APCR APC LL_PWR_EnablePUPDConfig + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePUPDConfig(void) +{ + SET_BIT(PWR->APCR, PWR_APCR_APC); +} + +/** + * @brief Disable the pull-up and pull-down configuration. + * @rmtoll APCR APC LL_PWR_DisablePUPDConfig + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePUPDConfig(void) +{ + CLEAR_BIT(PWR->APCR, PWR_APCR_APC); +} + +/** + * @brief Check if the pull-up and pull-down configuration is enabled. + * @rmtoll APCR APC LL_PWR_IsEnabledPUPDConfig + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDConfig(void) +{ + return ((READ_BIT(PWR->APCR, PWR_APCR_APC) == (PWR_APCR_APC)) ? 1UL : 0UL); +} + +/** + * @brief Enable GPIO pull-up in Standby and Shutdown modes + * @rmtoll PUCRx PUx LL_PWR_EnableGPIOPullUp + * @param GPIOPort This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_PORTA + * @arg @ref LL_PWR_GPIO_PORTB + * @arg @ref LL_PWR_GPIO_PORTC + * @arg @ref LL_PWR_GPIO_PORTD + * @arg @ref LL_PWR_GPIO_PORTE + * @arg @ref LL_PWR_GPIO_PORTF + * @arg @ref LL_PWR_GPIO_PORTG + * @arg @ref LL_PWR_GPIO_PORTH + * @arg @ref LL_PWR_GPIO_PORTI + * @arg @ref LL_PWR_GPIO_PORTJ (*) + * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices. + * @param GPIOPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_2 + * @arg @ref LL_PWR_GPIO_PIN_3 + * @arg @ref LL_PWR_GPIO_PIN_4 + * @arg @ref LL_PWR_GPIO_PIN_5 + * @arg @ref LL_PWR_GPIO_PIN_6 + * @arg @ref LL_PWR_GPIO_PIN_7 + * @arg @ref LL_PWR_GPIO_PIN_8 + * @arg @ref LL_PWR_GPIO_PIN_9 + * @arg @ref LL_PWR_GPIO_PIN_10 + * @arg @ref LL_PWR_GPIO_PIN_11 + * @arg @ref LL_PWR_GPIO_PIN_12 + * @arg @ref LL_PWR_GPIO_PIN_13 + * @arg @ref LL_PWR_GPIO_PIN_14 + * @arg @ref LL_PWR_GPIO_PIN_15 + * @retval None. + */ +__STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIOPort, uint32_t GPIOPin) +{ + SET_BIT(*((uint32_t *)GPIOPort), GPIOPin); +} + +/** + * @brief Disable GPIO pull-up in Standby and Shutdown modes + * @rmtoll PUCRx PUx LL_PWR_DisableGPIOPullUp + * @param GPIOPort This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_PORTA + * @arg @ref LL_PWR_GPIO_PORTB + * @arg @ref LL_PWR_GPIO_PORTC + * @arg @ref LL_PWR_GPIO_PORTD + * @arg @ref LL_PWR_GPIO_PORTE + * @arg @ref LL_PWR_GPIO_PORTF + * @arg @ref LL_PWR_GPIO_PORTG + * @arg @ref LL_PWR_GPIO_PORTH + * @arg @ref LL_PWR_GPIO_PORTI + * @arg @ref LL_PWR_GPIO_PORTJ (*) + * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices. + * @param GPIOPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_2 + * @arg @ref LL_PWR_GPIO_PIN_3 + * @arg @ref LL_PWR_GPIO_PIN_4 + * @arg @ref LL_PWR_GPIO_PIN_5 + * @arg @ref LL_PWR_GPIO_PIN_6 + * @arg @ref LL_PWR_GPIO_PIN_7 + * @arg @ref LL_PWR_GPIO_PIN_8 + * @arg @ref LL_PWR_GPIO_PIN_9 + * @arg @ref LL_PWR_GPIO_PIN_10 + * @arg @ref LL_PWR_GPIO_PIN_11 + * @arg @ref LL_PWR_GPIO_PIN_12 + * @arg @ref LL_PWR_GPIO_PIN_13 + * @arg @ref LL_PWR_GPIO_PIN_14 + * @arg @ref LL_PWR_GPIO_PIN_15 + * @retval None. + */ +__STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIOPort, uint32_t GPIOPin) +{ + CLEAR_BIT(*((uint32_t *)GPIOPort), GPIOPin); +} + +/** + * @brief Check if GPIO pull-up in Standby and Shutdown modes is enabled + * @rmtoll PUCRx PUx LL_PWR_IsEnabledGPIOPullUp + * @param GPIOPort This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_PORTA + * @arg @ref LL_PWR_GPIO_PORTB + * @arg @ref LL_PWR_GPIO_PORTC + * @arg @ref LL_PWR_GPIO_PORTD + * @arg @ref LL_PWR_GPIO_PORTE + * @arg @ref LL_PWR_GPIO_PORTF + * @arg @ref LL_PWR_GPIO_PORTG + * @arg @ref LL_PWR_GPIO_PORTH + * @arg @ref LL_PWR_GPIO_PORTI + * @arg @ref LL_PWR_GPIO_PORTJ (*) + * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices. + * @param GPIOPin This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_2 + * @arg @ref LL_PWR_GPIO_PIN_3 + * @arg @ref LL_PWR_GPIO_PIN_4 + * @arg @ref LL_PWR_GPIO_PIN_5 + * @arg @ref LL_PWR_GPIO_PIN_6 + * @arg @ref LL_PWR_GPIO_PIN_7 + * @arg @ref LL_PWR_GPIO_PIN_8 + * @arg @ref LL_PWR_GPIO_PIN_9 + * @arg @ref LL_PWR_GPIO_PIN_10 + * @arg @ref LL_PWR_GPIO_PIN_11 + * @arg @ref LL_PWR_GPIO_PIN_12 + * @arg @ref LL_PWR_GPIO_PIN_13 + * @arg @ref LL_PWR_GPIO_PIN_14 + * @arg @ref LL_PWR_GPIO_PIN_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIOPort, uint32_t GPIOPin) +{ + return ((READ_BIT(*((uint32_t *)(GPIOPort)), GPIOPin) == (GPIOPin)) ? 1UL : 0UL); +} + +/** + * @brief Enable GPIO pull-down in Standby and Shutdown modes. + * @rmtoll PDCRx PDx LL_PWR_EnableGPIOPullDown + * @param GPIOPort This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_PORTA + * @arg @ref LL_PWR_GPIO_PORTB + * @arg @ref LL_PWR_GPIO_PORTC + * @arg @ref LL_PWR_GPIO_PORTD + * @arg @ref LL_PWR_GPIO_PORTE + * @arg @ref LL_PWR_GPIO_PORTF + * @arg @ref LL_PWR_GPIO_PORTG + * @arg @ref LL_PWR_GPIO_PORTH + * @arg @ref LL_PWR_GPIO_PORTI + * @arg @ref LL_PWR_GPIO_PORTJ (*) + * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices. + * @param GPIOPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_2 + * @arg @ref LL_PWR_GPIO_PIN_3 + * @arg @ref LL_PWR_GPIO_PIN_4 + * @arg @ref LL_PWR_GPIO_PIN_5 + * @arg @ref LL_PWR_GPIO_PIN_6 + * @arg @ref LL_PWR_GPIO_PIN_7 + * @arg @ref LL_PWR_GPIO_PIN_8 + * @arg @ref LL_PWR_GPIO_PIN_9 + * @arg @ref LL_PWR_GPIO_PIN_10 + * @arg @ref LL_PWR_GPIO_PIN_11 + * @arg @ref LL_PWR_GPIO_PIN_12 + * @arg @ref LL_PWR_GPIO_PIN_13 + * @arg @ref LL_PWR_GPIO_PIN_14 + * @arg @ref LL_PWR_GPIO_PIN_15 + * @retval None. + */ +__STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIOPort, uint32_t GPIOPin) +{ + SET_BIT(*((__IO uint32_t *)(GPIOPort + 4U)), GPIOPin); +} + +/** + * @brief Disable GPIO pull-down in Standby and Shutdown modes. + * @rmtoll PDCRx PDx LL_PWR_DisableGPIOPullDown + * @param GPIOPort This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_PORTA + * @arg @ref LL_PWR_GPIO_PORTB + * @arg @ref LL_PWR_GPIO_PORTC + * @arg @ref LL_PWR_GPIO_PORTD + * @arg @ref LL_PWR_GPIO_PORTE + * @arg @ref LL_PWR_GPIO_PORTF + * @arg @ref LL_PWR_GPIO_PORTG + * @arg @ref LL_PWR_GPIO_PORTH + * @arg @ref LL_PWR_GPIO_PORTI + * @arg @ref LL_PWR_GPIO_PORTJ (*) + * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices. + * @param GPIOPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_2 + * @arg @ref LL_PWR_GPIO_PIN_3 + * @arg @ref LL_PWR_GPIO_PIN_4 + * @arg @ref LL_PWR_GPIO_PIN_5 + * @arg @ref LL_PWR_GPIO_PIN_6 + * @arg @ref LL_PWR_GPIO_PIN_7 + * @arg @ref LL_PWR_GPIO_PIN_8 + * @arg @ref LL_PWR_GPIO_PIN_9 + * @arg @ref LL_PWR_GPIO_PIN_10 + * @arg @ref LL_PWR_GPIO_PIN_11 + * @arg @ref LL_PWR_GPIO_PIN_12 + * @arg @ref LL_PWR_GPIO_PIN_13 + * @arg @ref LL_PWR_GPIO_PIN_14 + * @arg @ref LL_PWR_GPIO_PIN_15 + * @retval None. + */ +__STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIOPort, uint32_t GPIOPin) +{ + CLEAR_BIT(*((__IO uint32_t *)(GPIOPort + 4U)), GPIOPin); +} + +/** + * @brief Check if GPIO pull-down in Standby and Shutdown modes is enabled + * @rmtoll PDCRx PDx LL_PWR_IsEnabledGPIOPullUp + * @param GPIOPort This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_PORTA + * @arg @ref LL_PWR_GPIO_PORTB + * @arg @ref LL_PWR_GPIO_PORTC + * @arg @ref LL_PWR_GPIO_PORTD + * @arg @ref LL_PWR_GPIO_PORTE + * @arg @ref LL_PWR_GPIO_PORTF + * @arg @ref LL_PWR_GPIO_PORTG + * @arg @ref LL_PWR_GPIO_PORTH + * @arg @ref LL_PWR_GPIO_PORTI + * @arg @ref LL_PWR_GPIO_PORTJ (*) + * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices. + * @param GPIOPin This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_2 + * @arg @ref LL_PWR_GPIO_PIN_3 + * @arg @ref LL_PWR_GPIO_PIN_4 + * @arg @ref LL_PWR_GPIO_PIN_5 + * @arg @ref LL_PWR_GPIO_PIN_6 + * @arg @ref LL_PWR_GPIO_PIN_7 + * @arg @ref LL_PWR_GPIO_PIN_8 + * @arg @ref LL_PWR_GPIO_PIN_9 + * @arg @ref LL_PWR_GPIO_PIN_10 + * @arg @ref LL_PWR_GPIO_PIN_11 + * @arg @ref LL_PWR_GPIO_PIN_12 + * @arg @ref LL_PWR_GPIO_PIN_13 + * @arg @ref LL_PWR_GPIO_PIN_14 + * @arg @ref LL_PWR_GPIO_PIN_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIOPort, uint32_t GPIOPin) +{ + return ((READ_BIT(*((__IO uint32_t *)(GPIOPort + 4U)), GPIOPin) == (GPIOPin)) ? 1UL : 0UL); +} + +/** + * @brief Get currently voltage scaling applied to VCORE. + * @rmtoll SVMSR ACTVOS[1:0] LL_PWR_GetRegulCurrentVOS + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4 + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulCurrentVOS(void) +{ + return (READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOS)); +} +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management + * @{ + */ + +/** + * @brief Indicate whether the EPOD (Embedded Power Distribution) booster is + * ready OR not. + * @rmtoll VOSR BOOSTRDY LL_PWR_IsActiveFlag_BOOST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BOOST(void) +{ + return ((READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == (PWR_VOSR_BOOSTRDY)) ? 1UL : 0UL); +} + +#if defined (PWR_VOSR_USBBOOSTRDY) +/** + * @brief Indicate whether the USB EPOD (Embedded Power Distribution) booster is + * ready OR not. + * @rmtoll VOSR USBBOOSTRDY LL_PWR_IsActiveFlag_USBBOOST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USBBOOST(void) +{ + return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTRDY) == (PWR_VOSR_USBBOOSTRDY)) ? 1UL : 0UL); +} +#endif /* defined (PWR_VOSR_USBBOOSTRDY) */ + +/** + * @brief Indicate whether the regulator voltage output is above voltage + * scaling range or not. + * @rmtoll VOSR VOSRDY LL_PWR_IsActiveFlag_VOS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) +{ + return ((READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == (PWR_VOSR_VOSRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the system was in standby mode or not. + * @rmtoll SR SBF LL_PWR_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) +{ + return ((READ_BIT(PWR->SR, PWR_SR_SBF) == (PWR_SR_SBF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the system was in stop mode or not. + * @rmtoll SR STOPF LL_PWR_IsActiveFlag_STOP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void) +{ + return ((READ_BIT(PWR->SR, PWR_SR_STOPF) == (PWR_SR_STOPF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the regulator supply is LDO or SMPS. + * @rmtoll SVMSR REGS LL_PWR_IsActiveFlag_REGULATOR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGULATOR(void) +{ + return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS) == (PWR_SVMSR_REGS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VDD voltage is below the threshold or not. + * @rmtoll SVMSR PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO) == (PWR_SVMSR_PVDO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the regulator voltage output is equal to current + * used voltage scaling range or not. + * @rmtoll SVMSR ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void) +{ + return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY) == (PWR_SVMSR_ACTVOSRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VDDUSB is below the threshold of monitor or not. + * @rmtoll SVMSR VDDUSBRDY LL_PWR_IsActiveFlag_VDDUSB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDUSB(void) +{ + return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDUSBRDY) == (PWR_SVMSR_VDDUSBRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VDDIO2 is below the threshold of monitor or not. + * @rmtoll SVMSR VDDIO2RDY LL_PWR_IsActiveFlag_VDDIO2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO2(void) +{ + return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDIO2RDY) == (PWR_SVMSR_VDDIO2RDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VDDA1 is below the threshold of monitor 1 or + * not. + * @rmtoll SVMSR VDDA1RDY LL_PWR_IsActiveFlag_VDDA1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDA1(void) +{ + return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA1RDY) == (PWR_SVMSR_VDDA1RDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VDDA2 is below the threshold of monitor 2 or + * not. + * @rmtoll SVMSR VDDA2RDY LL_PWR_IsActiveFlag_VDDA2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDA2(void) +{ + return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA2RDY) == (PWR_SVMSR_VDDA2RDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VBAT level is below high threshold or not. + * @rmtoll BDSR VBATH LL_PWR_IsActiveFlag_VBATH + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void) +{ + return ((READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == (PWR_BDSR_VBATH)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the CPU temperature level is above low threshold or + * not. + * @rmtoll BDSR TEMPL LL_PWR_IsActiveFlag_TEMPL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void) +{ + return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == (PWR_BDSR_TEMPL)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the CPU temperature level is below high threshold + * or not. + * @rmtoll BDSR TEMPH LL_PWR_IsActiveFlag_TEMPH + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void) +{ + return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == (PWR_BDSR_TEMPH)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 1. + * @rmtoll WUSR WUF1 LL_PWR_IsActiveFlag_WU1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == (PWR_WUSR_WUF1)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 2. + * @rmtoll WUSR WUF2 LL_PWR_IsActiveFlag_WU2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == (PWR_WUSR_WUF2)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 3. + * @rmtoll WUSR WUF3 LL_PWR_IsActiveFlag_WU3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == (PWR_WUSR_WUF3)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 4. + * @rmtoll WUSR WUF4 LL_PWR_IsActiveFlag_WU4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == (PWR_WUSR_WUF4)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 5. + * @rmtoll WUSR WUF5 LL_PWR_IsActiveFlag_WU5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == (PWR_WUSR_WUF5)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 6. + * @rmtoll WUSR WUF6 LL_PWR_IsActiveFlag_WU6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == (PWR_WUSR_WUF6)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 7. + * @rmtoll WUSR WUF7 LL_PWR_IsActiveFlag_WU7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU7(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == (PWR_WUSR_WUF7)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 8. + * @rmtoll WUSR WUF8 LL_PWR_IsActiveFlag_WU8 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU8(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == (PWR_WUSR_WUF8)) ? 1UL : 0UL); +} + +/** + * @brief Clear stop flag. + * @rmtoll SR CSSF LL_PWR_ClearFlag_STOP + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_STOP(void) +{ + WRITE_REG(PWR->SR, PWR_SR_CSSF); +} + +/** + * @brief Clear standby flag. + * @rmtoll SR CSSF LL_PWR_ClearFlag_SB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) +{ + WRITE_REG(PWR->SR, PWR_SR_CSSF); +} + +/** + * @brief Clear wake up flag 1. + * @rmtoll WUSCR CWUF1 LL_PWR_ClearFlag_WU1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF1); +} + +/** + * @brief Clear wake up flag 2. + * @rmtoll WUSCR CWUF2 LL_PWR_ClearFlag_WU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF2); +} + +/** + * @brief Clear wake up flag 3. + * @rmtoll WUSCR CWUF3 LL_PWR_ClearFlag_WU3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF3); +} + +/** + * @brief Clear wake up flag 4. + * @rmtoll WUSCR CWUF4 LL_PWR_ClearFlag_WU4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF4); +} + +/** + * @brief Clear wake up flag 5. + * @rmtoll WUSCR CWUF5 LL_PWR_ClearFlag_WU5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF5); +} + +/** + * @brief Clear wake up flag 6. + * @rmtoll WUSCR CWUF6 LL_PWR_ClearFlag_WU6 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF6); +} + +/** + * @brief Clear wake up flag 7. + * @rmtoll WUSCR CWUF7 LL_PWR_ClearFlag_WU7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU7(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF7); +} + +/** + * @brief Clear wake up flag 8. + * @rmtoll WUSCR CWUF8 LL_PWR_ClearFlag_WU8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU8(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF8); +} + +/** + * @brief Clear all wake up flags. + * @rmtoll WUSCR CWUF LL_PWR_ClearFlag_WU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF); +} +/** + * @} + */ + +/** @defgroup PWR_LL_EF_ATTRIBUTE_MANAGEMENT PWR Attribute Management + * @{ + */ + +/** + * @brief Enable privileged mode for nsecure items. + * @rmtoll PRIVCFGR NSPRIV LL_PWR_EnableNSecurePrivilege + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableNSecurePrivilege(void) +{ + SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); +} + +/** + * @brief Disable privileged mode for nsecure items. + * @rmtoll PRIVCFGR NSPRIV LL_PWR_DisableNSecurePrivilege + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableNSecurePrivilege(void) +{ + CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); +} + +/** + * @brief Check if privileged mode for nsecure items is enabled. + * @rmtoll PRIVCFGR NSPRIV LL_PWR_IsEnabledNSecurePrivilege + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledNSecurePrivilege(void) +{ + return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV) == PWR_PRIVCFGR_NSPRIV) ? 1UL : 0UL); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable privileged mode for secure items. + * @rmtoll PRIVCFGR SPRIV LL_PWR_EnableSecurePrivilege + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableSecurePrivilege(void) +{ + SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); +} + +/** + * @brief Disable privileged mode for secure items. + * @rmtoll PRIVCFGR SPRIV LL_PWR_DisableSecurePrivilege + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableSecurePrivilege(void) +{ + CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Check if privileged mode for secure items is enabled. + * @rmtoll PRIVCFGR SPRIV LL_PWR_IsEnabledSecurePrivilege + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledSecurePrivilege(void) +{ + return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV) == PWR_PRIVCFGR_SPRIV) ? 1UL : 0UL); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure secure attribute mode. + * @note This API can be executed only by CPU in secure mode. + * @rmtoll SECCFGR WUP1SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP2SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP3SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP4SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP5SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP6SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP7SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP8SEC LL_PWR_ConfigSecure\n + * SECCFGR LPMSEC LL_PWR_ConfigSecure\n + * SECCFGR VDMSEC LL_PWR_ConfigSecure\n + * SECCFGR VBSEC LL_PWR_ConfigSecure\n + * SECCFGR APCSEC LL_PWR_ConfigSecure + * @param SecureConfig This parameter can be the full combination + * of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC + * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC + * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC + * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC + * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC + * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC + * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC + * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC + * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC + * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC + * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC + * @arg @ref LL_PWR_APC_NSEC or LL_PWR_APC_SEC + * @retval None. + */ +__STATIC_INLINE void LL_PWR_ConfigSecure(uint32_t SecureConfig) +{ + WRITE_REG(PWR->SECCFGR, SecureConfig); +} + +/** + * @brief Get secure attribute configuration. + * @note This API can be executed only by CPU in secure mode. + * @rmtoll SECCFGR WUP1SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP2SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP3SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP4SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP5SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP6SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP7SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP8SEC LL_PWR_GetConfigSecure\n + * SECCFGR LPMSEC LL_PWR_GetConfigSecure\n + * SECCFGR VDMSEC LL_PWR_GetConfigSecure\n + * SECCFGR VBSEC LL_PWR_GetConfigSecure\n + * SECCFGR APCSEC LL_PWR_GetConfigSecure + * @retval Returned value is the combination of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC + * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC + * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC + * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC + * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC + * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC + * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC + * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC + * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC + * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC + * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC + * @arg @ref LL_PWR_APC_NSEC or LL_PWR_APC_SEC + */ +__STATIC_INLINE uint32_t LL_PWR_GetConfigSecure(void) +{ + return (READ_REG(PWR->SECCFGR)); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/** + * @} + */ + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* defined (USE_FULL_LL_DRIVER) */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32U5xx_LL_PWR_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rcc.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rcc.h new file mode 100644 index 000000000..24ec089d5 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rcc.h @@ -0,0 +1,6120 @@ +/** + ****************************************************************************** + * @file stm32u5xx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_LL_RCC_H +#define STM32U5xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx.h" + +/** @addtogroup STM32U5xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Constants RCC Private Constants + * @{ + */ +/* Defines used to perform offsets*/ +/* Offset used to access to RCC_CCIPR1 and RCC_CCIPR2 registers */ +#define RCC_OFFSET_CCIPR1 0UL +#define RCC_OFFSET_CCIPR2 0x04UL +#define RCC_OFFSET_CCIPR3 0x08UL + +/* Defines used for security configuration extension */ +#define RCC_SECURE_MASK 0x1FFFU +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ + uint32_t PCLK3_Frequency; /*!< PCLK3 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ + +#if !defined (HSI48_VALUE) +#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ +#endif /* HSI48_VALUE */ + +#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) +#define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */ +#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ + +#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) +#define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */ +#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSIPRE LSI prescaler + * @{ + */ +#define LL_RCC_LSI_DIV_1 0x00000000U /*!< LSI divided by 1 */ +#define LL_RCC_LSI_DIV_128 RCC_BDCR_LSIPREDIV /*!< LSI divided by 128 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */ +#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MSI_OSCILLATOR MSI clock Trimming + * @{ + */ +#define LL_RCC_MSI_OSCILLATOR_0 0x00000000U /*!< MSI clock trimming for ranges 0 to 3 */ +#define LL_RCC_MSI_OSCILLATOR_1 0x00000005U /*!< MSI clock trimming for ranges 4 to 7 */ +#define LL_RCC_MSI_OSCILLATOR_2 0x0000000AU /*!< MSI clock trimming for ranges 8 to 11 */ +#define LL_RCC_MSI_OSCILLATOR_3 0x0000000FU /*!< MSI clock trimming for ranges 12 to 15 */ +/** + * @} + */ + + +/** @defgroup RCC_LL_EC_MSISRANGE MSIS Clock Range + * @{ + */ +#define LL_RCC_MSISRANGE_0 0x00000000U /*!< MSIS = 48 MHz */ +#define LL_RCC_MSISRANGE_1 RCC_ICSCR1_MSISRANGE_0 /*!< MSIS = 24 MHz */ +#define LL_RCC_MSISRANGE_2 RCC_ICSCR1_MSISRANGE_1 /*!< MSIS = 16 MHz */ +#define LL_RCC_MSISRANGE_3 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1) /*!< MSIS = 12 MHz */ +#define LL_RCC_MSISRANGE_4 RCC_ICSCR1_MSISRANGE_2 /*!< MSIS = 4 MHz */ +#define LL_RCC_MSISRANGE_5 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2) /*!< MSIS = 2 MHz */ +#define LL_RCC_MSISRANGE_6 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSIS = 1.5 MHz */ +#define LL_RCC_MSISRANGE_7 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSIS = 1 MHz */ +#define LL_RCC_MSISRANGE_8 RCC_ICSCR1_MSISRANGE_3 /*!< MSIS = 3.072 MHz */ +#define LL_RCC_MSISRANGE_9 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 1.536 MHz */ +#define LL_RCC_MSISRANGE_10 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 1.024 MHz */ +#define LL_RCC_MSISRANGE_11 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 768 KHz */ +#define LL_RCC_MSISRANGE_12 (RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 400 KHz */ +#define LL_RCC_MSISRANGE_13 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 200 KHz */ +#define LL_RCC_MSISRANGE_14 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 150 KHz */ +#define LL_RCC_MSISRANGE_15 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1| RCC_ICSCR1_MSISRANGE_2 | \ + RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 100 KHz */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MSIKRANGE MSIK Clock Range + * @{ + */ +#define LL_RCC_MSIKRANGE_0 0x00000000U /*!< MSIK = 48 MHz */ +#define LL_RCC_MSIKRANGE_1 RCC_ICSCR1_MSIKRANGE_0 /*!< MSIK = 24 MHz */ +#define LL_RCC_MSIKRANGE_2 RCC_ICSCR1_MSIKRANGE_1 /*!< MSIK = 16 MHz */ +#define LL_RCC_MSIKRANGE_3 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1) /*!< MSIK = 12 MHz */ +#define LL_RCC_MSIKRANGE_4 RCC_ICSCR1_MSIKRANGE_2 /*!< MSIK = 4 MHz */ +#define LL_RCC_MSIKRANGE_5 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 2 MHz */ +#define LL_RCC_MSIKRANGE_6 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1.5 MHz */ +#define LL_RCC_MSIKRANGE_7 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1 MHz */ +#define LL_RCC_MSIKRANGE_8 RCC_ICSCR1_MSIKRANGE_3 /*!< MSIK = 3.072 MHz */ +#define LL_RCC_MSIKRANGE_9 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.536 MHz */ +#define LL_RCC_MSIKRANGE_10 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.024 MHz */ +#define LL_RCC_MSIKRANGE_11 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 768 KHz */ +#define LL_RCC_MSIKRANGE_12 (RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 400 KHz */ +#define LL_RCC_MSIKRANGE_13 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 200 KHz */ +#define LL_RCC_MSIKRANGE_14 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 150 KHz */ +#define LL_RCC_MSIKRANGE_15 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | \ + RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 100 KHz */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MSISSRANGE MSIS range after Standby mode + * @{ + */ +#define LL_RCC_MSISSRANGE_4 RCC_CSR_MSISSRANGE_2 /*!< MSIS = 4 MHz */ +#define LL_RCC_MSISSRANGE_5 (RCC_CSR_MSISSRANGE_2 | RCC_CSR_MSISSRANGE_0) /*!< MSIS = 2 MHz */ +#define LL_RCC_MSISSRANGE_6 (RCC_CSR_MSISSRANGE_2 | RCC_CSR_MSISSRANGE_1) /*!< MSIS = 1.5 MHz */ +#define LL_RCC_MSISSRANGE_7 (RCC_CSR_MSISSRANGE_0 | RCC_CSR_MSISSRANGE_2 | RCC_CSR_MSISSRANGE_1) /*!< MSIS = 1 MHz */ +#define LL_RCC_MSISSRANGE_8 RCC_CSR_MSISSRANGE_3 /*!< MSIS = 3.072 MHz*/ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MSIKSRANGE MSIK range after Standby mode + * @{ + */ +#define LL_RCC_MSIKSRANGE_4 RCC_CSR_MSIKSRANGE_2 /*!< MSIK = 4 MHz */ +#define LL_RCC_MSIKSRANGE_5 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_0) /*!< MSIK = 2 MHz */ +#define LL_RCC_MSIKSRANGE_6 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_1) /*!< MSIK = 1.5 MHz */ +#define LL_RCC_MSIKSRANGE_7 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_1 | RCC_CSR_MSIKSRANGE_0) /*!< MSIK = 1 MHz */ +#define LL_RCC_MSIKSRANGE_8 RCC_CSR_MSIKSRANGE_3 /*!< MSIK = 3.072 MHz*/ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MSIPLLMODE MSIS/MSIK Pll Mode + * @{ + */ +#define LL_RCC_PLLMODE_MSIS RCC_CR_MSIPLLSEL /*!< MSIS selection for Pll Mode */ +#define LL_RCC_PLLMODE_MSIK 0U /*!< MSIK selection for Pll Mode */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MSIBIASMODE MSI BIAS Mode + * @{ + */ +#define LL_RCC_MSIBIASMODE_SAMPLING RCC_ICSCR1_MSIBIAS /*!< Sampling mode selection for MSI*/ +#define LL_RCC_MSIBIASMODE_CONTINUOUS 0U /*!< Continuous mode selection for MSI*/ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_HSEEXT EXTERNAL HSE Mode + * @{ + */ +#define LL_RCC_HSE_ANALOG_MODE 0U /*!< HSE clock used as ANALOG clock source */ +#define LL_RCC_HSE_DIGITAL_MODE RCC_CR_HSEEXT /*!< HSE clock used as DIGITAL clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection + * @{ + */ +#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */ +#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */ +/** + * @} + */ + + +/** @defgroup RCC_LL_EC_PLL1MBOOST_DIV EPOD prescaler + * @{ + */ +#define LL_RCC_PLL1MBOOST_DIV_1 0x00000000U /*!< PLL1CLK not divided */ +#define LL_RCC_PLL1MBOOST_DIV_2 RCC_PLL1CFGR_PLL1MBOOST_0 /*!< PLL1CLK divided by 2 */ +#define LL_RCC_PLL1MBOOST_DIV_4 RCC_PLL1CFGR_PLL1MBOOST_1 /*!< PLL1CLK divided by 4 */ +#define LL_RCC_PLL1MBOOST_DIV_6 (RCC_PLL1CFGR_PLL1MBOOST_1 | RCC_PLL1CFGR_PLL1MBOOST_0) /*!< PLL1CLK divided by 6 */ +#define LL_RCC_PLL1MBOOST_DIV_8 RCC_PLL1CFGR_PLL1MBOOST_2 /*!< PLL1CLK divided by 8 */ +#define LL_RCC_PLL1MBOOST_DIV_10 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_0) /*!< PLL1CLK divided by 10 */ +#define LL_RCC_PLL1MBOOST_DIV_12 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1) /*!< PLL1CLK divided by 12 */ +#define LL_RCC_PLL1MBOOST_DIV_14 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1 | \ + RCC_PLL1CFGR_PLL1MBOOST_0) /*!< PLL1CLK divided by 14 */ +#define LL_RCC_PLL1MBOOST_DIV_16 RCC_PLL1CFGR_PLL1MBOOST_3 /*!< PLL1CLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_MSIS 0x00000000U /*!< MSIS selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR1_SW_0 /*!< HSI oscillator selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PLL1 (RCC_CFGR1_SW_1 | RCC_CFGR1_SW_0) /*!< PLL selection as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_MSIS 0x00000000U /*!< MSIS used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR1_SWS_0 /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 (RCC_CFGR1_SWS_1 | RCC_CFGR1_SWS_0) /*!< PLL1 used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR2_HPRE_3 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_1) /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 16 */ +#define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2) /*!< SYSCLK divided by 64 */ +#define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 128 */ +#define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1) /*!< SYSCLK divided by 256 */ +#define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1 | \ + RCC_CFGR2_HPRE_0)/*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSTICK_CLKSOURCE SYSTICK clock source selection + * @{ + */ +#define LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 0x00000000U /*!< HCLKDIV8 clock used as SYSTICK clock source */ +#define LL_RCC_SYSTICK_CLKSOURCE_LSI RCC_CCIPR1_SYSTICKSEL_0 /*!< LSI clock used as SYSTICK clock source */ +#define LL_RCC_SYSTICK_CLKSOURCE_LSE RCC_CCIPR1_SYSTICKSEL_1 /*!< LSE clock used as SYSTICK clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_DIV_4 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_DIV_8 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1) /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_DIV_16 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) + * @{ + */ +#define LL_RCC_APB2_DIV_1 0x00000000U /*!< HCLK not divided */ +#define LL_RCC_APB2_DIV_2 RCC_CFGR2_PPRE2_2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB2_DIV_4 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 4 */ +#define LL_RCC_APB2_DIV_8 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1) /*!< HCLK divided by 8 */ +#define LL_RCC_APB2_DIV_16 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 16 */ +/** + * @} + */ + + +/** @defgroup RCC_LL_EC_APB3_DIV APB high-speed prescaler (APB3) + * @{ + */ +#define LL_RCC_APB3_DIV_1 0x00000000U /*!< HCLK not divided */ +#define LL_RCC_APB3_DIV_2 RCC_CFGR3_PPRE3_2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB3_DIV_4 (RCC_CFGR3_PPRE3_2 | RCC_CFGR3_PPRE3_0) /*!< HCLK divided by 4 */ +#define LL_RCC_APB3_DIV_8 (RCC_CFGR3_PPRE3_2 | RCC_CFGR3_PPRE3_1) /*!< HCLK divided by 8 */ +#define LL_RCC_APB3_DIV_16 (RCC_CFGR3_PPRE3_2 | RCC_CFGR3_PPRE3_1 | RCC_CFGR3_PPRE3_0) /*!< HCLK divided by 16 */ +/** + * @} + */ + +#if defined(RCC_CFGR2_PPRE_DPHY) +/** @defgroup RCC_LL_EC_DPHY_DIV DSI PHY clock prescaler (DCLK) + * @{ + */ +#define LL_RCC_DPHY_DIV_1 0x00000000U /*!< DCLK not divided */ +#define LL_RCC_DPHY_DIV_2 RCC_CFGR2_PPRE_DPHY_2 /*!< DCLK divided by 2 */ +#define LL_RCC_DPHY_DIV_4 (RCC_CFGR2_PPRE_DPHY_2 | RCC_CFGR2_PPRE_DPHY_0) /*!< DCLK divided by 4 */ +#define LL_RCC_DPHY_DIV_8 (RCC_CFGR2_PPRE_DPHY_2 | RCC_CFGR2_PPRE_DPHY_1) /*!< DCLK divided by 8 */ +#define LL_RCC_DPHY_DIV_16 (RCC_CFGR2_PPRE_DPHY_2 | RCC_CFGR2_PPRE_DPHY_1 | RCC_CFGR2_PPRE_DPHY_0) /*!< DCLK divided by 16 */ +/** + * @} + */ +#endif /* RCC_CFGR2_PPRE_DPHY */ + +/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection + * @{ + */ +#define LL_RCC_STOP_WAKEUPCLOCK_MSIS 0x00000000U /*!< MSIS selection after wake-up from STOP */ +#define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR1_STOPWUCK /*!< HSI selection after wake-up from STOP */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_STOP_WAKEUPKERCLOCK Wakeup from Stop kernel clock automatic enable selection + * @{ + */ +#define LL_RCC_STOP_WAKEUPKERCLOCK_MSIK 0x00000000U /*!< MSIK oscillator automatically enabled when exiting Stop mode */ +#define LL_RCC_STOP_WAKEUPKERCLOCK_HSI RCC_CFGR1_STOPKERWUCK /*!< HSI oscillator automatically enabled when exiting Stop mode */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */ +#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR1_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_MSIS RCC_CFGR1_MCOSEL_1 /*!< MSIS selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_1) /*!< HSI selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR1_MCOSEL_2 /*!< HSE selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_2) /*!< Main PLL selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR1_MCOSEL_1 | RCC_CFGR1_MCOSEL_2) /*!< LSI selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_1| RCC_CFGR1_MCOSEL_2)/*!< LSE selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR1_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_MSIK (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_3) /*!< MSIK selection as MCO1 source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO not divided */ +#define LL_RCC_MCO1_DIV_2 RCC_CFGR1_MCOPRE_0 /*!< MCO divided by 2 */ +#define LL_RCC_MCO1_DIV_4 RCC_CFGR1_MCOPRE_1 /*!< MCO divided by 4 */ +#define LL_RCC_MCO1_DIV_8 (RCC_CFGR1_MCOPRE_1 | RCC_CFGR1_MCOPRE_0) /*!< MCO divided by 8 */ +#define LL_RCC_MCO1_DIV_16 RCC_CFGR1_MCOPRE_2 /*!< MCO divided by 16 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USART_CLKSOURCE Peripheral USARTx clock source selection + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE_PCLK2 ((RCC_OFFSET_CCIPR1 << 24U)| (RCC_CCIPR1_USART1SEL_Pos << 16U)) /*!< PCLK2 clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL_0 >> RCC_CCIPR1_USART1SEL_Pos)) /*!< SYSCLK clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL_1 >> RCC_CCIPR1_USART1SEL_Pos)) /*!< HSI clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL >> RCC_CCIPR1_USART1SEL_Pos)) /*!< LSE clock used as USART1 clock source */ +#if defined(USART2) +#define LL_RCC_USART2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U)) /*!< PCLK1 clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL_0 >> RCC_CCIPR1_USART2SEL_Pos)) /*!< SYSCLK clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL_1 >> RCC_CCIPR1_USART2SEL_Pos)) /*!< HSI clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL >> RCC_CCIPR1_USART2SEL_Pos)) /*!< LSE clock used as USART2 clock source */ +#endif /* USART2 */ +#define LL_RCC_USART3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U)) /*!< PCLK3 clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U) | (RCC_CCIPR1_USART3SEL_0 >> RCC_CCIPR1_USART3SEL_Pos)) /*!< SYSCLK clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U) | (RCC_CCIPR1_USART3SEL_1 >> RCC_CCIPR1_USART3SEL_Pos)) /*!< HSI clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U) | (RCC_CCIPR1_USART3SEL >> RCC_CCIPR1_USART3SEL_Pos)) /*!< LSE clock used as USART3 clock source */ +#if defined (RCC_CCIPR2_USART6SEL) +#define LL_RCC_USART6_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U)) /*!< PCLK1 clock used as USART6 clock source */ +#define LL_RCC_USART6_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | (RCC_CCIPR2_USART6SEL_0 >> RCC_CCIPR2_USART6SEL_Pos)) /*!< SYSCLK clock used as USART6 clock source */ +#define LL_RCC_USART6_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | (RCC_CCIPR2_USART6SEL_1 >> RCC_CCIPR2_USART6SEL_Pos)) /*!< HSI clock used as USART6 clock source */ +#define LL_RCC_USART6_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | (RCC_CCIPR2_USART6SEL >> RCC_CCIPR2_USART6SEL_Pos)) /*!< LSE clock used as USART6 clock source */ +/* Legacy define */ +#define LL_RCC_USART6_CLKSOURCE_PCLK2 LL_RCC_USART6_CLKSOURCE_PCLK1 +#endif /* RCC_CCIPR2_USART6SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_UART_CLKSOURCE Peripheral UARTx clock source selection + * @{ + */ +#define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR1_UART4SEL << 16U) /*!< PCLK1 clock used as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL_1) /*!< HSI clock used as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL) /*!< LSE clock used as UART4 clock source */ +#define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR1_UART5SEL << 16U) /*!< PCLK1 clock used as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL_1) /*!< HSI clock used as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL) /*!< LSE clock used as UART5 clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPUART_CLKSOURCE Peripheral LPUARTx clock source selection + * @{ + */ +#define LL_RCC_LPUART1_CLKSOURCE_PCLK3 0x00000000U /*!< PCLK3 clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR3_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR3_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) /*!< LSE clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_MSIK RCC_CCIPR3_LPUART1SEL_2 /*!< MSIK clock used as LPUART1 clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2C_CLKSOURCE Peripheral I2Cx clock source selection + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \ + (RCC_CCIPR1_I2C1SEL_0 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \ + (RCC_CCIPR1_I2C1SEL_1 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \ + (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< MSIK clock used as I2C1 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \ + (RCC_CCIPR1_I2C2SEL_0 >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \ + (RCC_CCIPR1_I2C2SEL_1 >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \ + (RCC_CCIPR1_I2C2SEL >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< MSIK clock used as I2C2 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_PCLK3 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U)) /*!< PCLK3 clock used as I2C3 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \ + (RCC_CCIPR3_I2C3SEL_0 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \ + (RCC_CCIPR3_I2C3SEL_1 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \ + (RCC_CCIPR3_I2C3SEL >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< MSIK clock used as I2C3 clock source */ +#define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */ +#define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \ + (RCC_CCIPR1_I2C4SEL_0 >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */ +#define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \ + (RCC_CCIPR1_I2C4SEL_1 >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */ +#define LL_RCC_I2C4_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \ + (RCC_CCIPR1_I2C4SEL >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< MSIK clock used as I2C4 clock source */ +#if defined (RCC_CCIPR2_I2C5SEL) +#define LL_RCC_I2C5_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C5 clock source */ +#define LL_RCC_I2C5_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \ + (RCC_CCIPR2_I2C5SEL_0 >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< SYSCLK clock used as I2C5 clock source */ +#define LL_RCC_I2C5_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \ + (RCC_CCIPR2_I2C5SEL_1 >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< HSI clock used as I2C5 clock source */ +#define LL_RCC_I2C5_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \ + (RCC_CCIPR2_I2C5SEL >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< MSIK clock used as I2C5 clock source */ +#endif /* RCC_CCIPR2_I2C5SEL */ +#if defined (RCC_CCIPR2_I2C6SEL) +#define LL_RCC_I2C6_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C6 clock source */ +#define LL_RCC_I2C6_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \ + (RCC_CCIPR2_I2C6SEL_0 >> RCC_CCIPR2_I2C6SEL_Pos)) /*!< SYSCLK clock used as I2C6 clock source */ +#define LL_RCC_I2C6_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \ + (RCC_CCIPR2_I2C6SEL_1 >> RCC_CCIPR2_I2C6SEL_Pos)) /*!< HSI clock used as I2C6 clock source */ +#define LL_RCC_I2C6_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \ + (RCC_CCIPR2_I2C6SEL >> RCC_CCIPR2_I2C6SEL_Pos)) /*!< MSIK clock used as I2C6 clock source */ +#endif /* RCC_CCIPR2_I2C6SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPI_CLKSOURCE Peripheral SPIx clock source selection + * @{ + */ +#define LL_RCC_SPI1_CLKSOURCE_PCLK2 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U)) /*!< PCLK2 clock used as SPI1 clock source */ +#define LL_RCC_SPI1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \ + (RCC_CCIPR1_SPI1SEL_0 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SYSCLK clock used as SPI1 clock source */ +#define LL_RCC_SPI1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \ + (RCC_CCIPR1_SPI1SEL_1 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< HSI clock used as SPI1 clock source */ +#define LL_RCC_SPI1_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \ + (RCC_CCIPR1_SPI1SEL >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< MSIK clock used as SPI1 clock source */ +#define LL_RCC_SPI2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U)) /*!< PCLK1 clock used as SPI2 clock source */ +#define LL_RCC_SPI2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \ + (RCC_CCIPR1_SPI2SEL_0 >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< SYSCLK clock used as SPI2 clock source */ +#define LL_RCC_SPI2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \ + (RCC_CCIPR1_SPI2SEL_1 >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< HSI clock used as SPI2 clock source */ +#define LL_RCC_SPI2_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \ + (RCC_CCIPR1_SPI2SEL >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< MSIK clock used as SPI2 clock source */ +#define LL_RCC_SPI3_CLKSOURCE_PCLK3 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U)) /*!< PCLK3 clock used as SPI3 clock source */ +#define LL_RCC_SPI3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \ + (RCC_CCIPR3_SPI3SEL_0 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SYSCLK clock used as SPI3 clock source */ +#define LL_RCC_SPI3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \ + (RCC_CCIPR3_SPI3SEL_1 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< HSI clock used as SPI3 clock source */ +#define LL_RCC_SPI3_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \ + (RCC_CCIPR3_SPI3SEL >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< MSIK clock used as SPI3 clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIM_CLKSOURCE Peripheral LPTIMx clock source selection + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U)) /*!< MSIK clock used as LPTIM1 clock source */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \ + (RCC_CCIPR3_LPTIM1SEL_0 >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LSI clock used as LPTIM1 clock source */ +#define LL_RCC_LPTIM1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \ + (RCC_CCIPR3_LPTIM1SEL_1 >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< HSI clock used as LPTIM1 clock source */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \ + (RCC_CCIPR3_LPTIM1SEL >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LSE clock used as LPTIM1 clock source */ +#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U)) /*!< PCLK1 clock used as LPTIM2 clock source */ +#define LL_RCC_LPTIM2_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \ + (RCC_CCIPR1_LPTIM2SEL_0 >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LSI clock used as LPTIM2 clock source */ +#define LL_RCC_LPTIM2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \ + (RCC_CCIPR1_LPTIM2SEL_1 >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< HSI clock used as LPTIM2 clock source */ +#define LL_RCC_LPTIM2_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \ + (RCC_CCIPR1_LPTIM2SEL >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LSE clock used as LPTIM2 clock source */ +#define LL_RCC_LPTIM34_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U)) /*!< MSIK clock used as LPTIM34 clock source*/ +#define LL_RCC_LPTIM34_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \ + (RCC_CCIPR3_LPTIM34SEL_0 >> RCC_CCIPR3_LPTIM34SEL_Pos)) /*!< LSI clock used as LPTIM34 clock source */ +#define LL_RCC_LPTIM34_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \ + (RCC_CCIPR3_LPTIM34SEL_1 >> RCC_CCIPR3_LPTIM34SEL_Pos)) /*!< HSI clock used as LPTIM34 clock source */ +#define LL_RCC_LPTIM34_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \ + (RCC_CCIPR3_LPTIM34SEL >> RCC_CCIPR3_LPTIM34SEL_Pos)) /*!< LSE clock used as LPTIM34 clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN kernel clock source selection + * @{ + */ +#define LL_RCC_FDCAN_CLKSOURCE_HSE 0x00000000U /*!< HSE clock used as FDCAN kernel clock source */ +#define LL_RCC_FDCAN_CLKSOURCE_PLL1 RCC_CCIPR1_FDCANSEL_0 /*!< PLL1 Q clock used as FDCAN kernel clock source */ +#define LL_RCC_FDCAN_CLKSOURCE_PLL2 RCC_CCIPR1_FDCANSEL_1 /*!< PLL2 P clock used as FDCAN kernel clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SAI_CLKSOURCE Peripheral SAIx clock source selection + * @{ + */ +#define LL_RCC_SAI1_CLKSOURCE_PLL2 (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLL2 clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PLL3 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLL3 clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PLL1 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< PLL1 clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | \ + RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */ +#if defined(SAI2) +#define LL_RCC_SAI2_CLKSOURCE_PLL2 (RCC_CCIPR2_SAI2SEL << 16U) /*!< PLL2 clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PLL3 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0) /*!< PLL3 clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PLL1 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1) /*!< PLL1clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2) /*!< HSI clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) | (RCC_CCIPR2_SAI2SEL_1 | \ + RCC_CCIPR2_SAI2SEL_0)) /*!< External input clock used as SAI2 clock source */ +#endif /* SAI2 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SDMMC_KERNELCLKSOURCE Peripheral SDMMC1/2 kernel clock source selection + * @{ + */ +#define LL_RCC_SDMMC12_KERNELCLKSOURCE_48CLK 0x00000000U /*!< 48MHz clock from internal multiplexor used as SDMMC1/2 clock source */ +#define LL_RCC_SDMMC12_KERNELCLKSOURCE_PLL1 RCC_CCIPR2_SDMMCSEL /*!< PLL1 "P" used as SDMMC1/2 clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SDMMC12_CLKSOURCE Peripheral SDMMC clock source selection + * @{ + */ +#define LL_RCC_SDMMC12_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as SDMMC1/2 clock source */ +#define LL_RCC_SDMMC12_CLKSOURCE_PLL2 RCC_CCIPR1_ICLKSEL_0 /*!< PLL2 "Q" clock used as SDMMC1/2 clock source */ +#define LL_RCC_SDMMC12_CLKSOURCE_PLL1 RCC_CCIPR1_ICLKSEL_1 /*!< PLL1 "Q" clock used as SDMMC1/2 clock source */ +#define LL_RCC_SDMMC12_CLKSOURCE_MSIK RCC_CCIPR1_ICLKSEL /*!< MSIK clock used as SDMMC1/2 clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as RNG clock source */ +#define LL_RCC_RNG_CLKSOURCE_HSI48_DIV2 RCC_CCIPR2_RNGSEL_0 /*!< HSI48/2 clock used as RNG clock source */ +#define LL_RCC_RNG_CLKSOURCE_HSI RCC_CCIPR2_RNGSEL_1 /*!< HSI clock used as RNG clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + * @{ + */ +#define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */ +#define LL_RCC_USB_CLKSOURCE_PLL2 RCC_CCIPR1_ICLKSEL_0 /*!< PLL2 "Q" clock used as USB clock source */ +#define LL_RCC_USB_CLKSOURCE_PLL1 RCC_CCIPR1_ICLKSEL_1 /*!< PLL1 "Q" clock used as USB clock source */ +#define LL_RCC_USB_CLKSOURCE_MSIK RCC_CCIPR1_ICLKSEL /*!< MSIK clock used as USB clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADCDAC_CLKSOURCE Peripheral ADCx and DAC1 clock source selection + * @{ + */ +#define LL_RCC_ADCDAC_CLKSOURCE_HCLK 0x00000000U /*!< No clock used as ADCx/DAC1 clock source */ +#define LL_RCC_ADCDAC_CLKSOURCE_SYSCLK RCC_CCIPR3_ADCDACSEL_0 /*!< SYSCLK clock used as ADCx/DAC1 clock source */ +#define LL_RCC_ADCDAC_CLKSOURCE_PLL2 RCC_CCIPR3_ADCDACSEL_1 /*!< PLL2 clock used as ADCx/DAC1 clock source */ +#define LL_RCC_ADCDAC_CLKSOURCE_HSI RCC_CCIPR3_ADCDACSEL_2 /*!< HSI clock used as ADCx/DAC1 clock source */ +#define LL_RCC_ADCDAC_CLKSOURCE_HSE (RCC_CCIPR3_ADCDACSEL_1 | RCC_CCIPR3_ADCDACSEL_0) /*!< HSE clock used as ADCx/DAC1 clock source */ +#define LL_RCC_ADCDAC_CLKSOURCE_MSIK (RCC_CCIPR3_ADCDACSEL_2 | RCC_CCIPR3_ADCDACSEL_0) /*!< MSIK clock used as ADCx/DAC1 clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_DAC1_CLKSOURCE Peripheral DAC1 clock source selection + * @{ + */ +#define LL_RCC_DAC1_CLKSOURCE_LSE 0x00000000U /*!< LSE clock used as DAC1 clock */ +#define LL_RCC_DAC1_CLKSOURCE_LSI RCC_CCIPR3_DAC1SEL /*!< LSI clock used as DAC1 clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADF1_CLKSOURCE Peripheral ADF1 clock source selection + * @{ + */ +#define LL_RCC_ADF1_CLKSOURCE_HCLK 0x00000000U /*!< HCLK clock used as ADF1 clock */ +#define LL_RCC_ADF1_CLKSOURCE_PLL1 RCC_CCIPR3_ADF1SEL_0 /*!< PLL1 clock used as ADF1 clock */ +#define LL_RCC_ADF1_CLKSOURCE_PLL3 RCC_CCIPR3_ADF1SEL_1 /*!< PLL3 clock used as ADF1 clock */ +#define LL_RCC_ADF1_CLKSOURCE_MSIK RCC_CCIPR3_ADF1SEL_2 /*!< MSIK clock used as ADF1 clock */ +#define LL_RCC_ADF1_CLKSOURCE_PIN (RCC_CCIPR3_ADF1SEL_1 | RCC_CCIPR3_ADF1SEL_0) /*!< PIN SAI1_EXTCLK clock used as ADF1 clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MDF1_CLKSOURCE Peripheral MDF1 clock source selection + * @{ + */ +#define LL_RCC_MDF1_CLKSOURCE_HCLK 0x00000000U /*!< HCLK clock used as MDF1 clock */ +#define LL_RCC_MDF1_CLKSOURCE_PLL1 RCC_CCIPR2_MDF1SEL_0 /*!< PLL1 clock used as MDF1 clock */ +#define LL_RCC_MDF1_CLKSOURCE_PLL3 RCC_CCIPR2_MDF1SEL_1 /*!< PLL3 clock used as MDF1 clock */ +#define LL_RCC_MDF1_CLKSOURCE_MSIK RCC_CCIPR2_MDF1SEL_2 /*!< MSIK clock used as MDF1 clock */ +#define LL_RCC_MDF1_CLKSOURCE_PIN (RCC_CCIPR2_MDF1SEL_1 | RCC_CCIPR2_MDF1SEL_0) /*!< PIN SAI1_EXTCLK clock used as MDF1 clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_OCTOSPI_CLKSOURCE Peripheral OCTOSPI kernel clock source selection + * @{ + */ +#define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock used as OctoSPI kernel clock source */ +#define LL_RCC_OCTOSPI_CLKSOURCE_MSIK RCC_CCIPR2_OCTOSPISEL_0 /*!< MSIK clock used as OctoSPI kernel clock source */ +#define LL_RCC_OCTOSPI_CLKSOURCE_PLL1 RCC_CCIPR2_OCTOSPISEL_1 /*!< PLL1 "Q" clock used as OctoSPI kernel clock source */ +#define LL_RCC_OCTOSPI_CLKSOURCE_PLL2 (RCC_CCIPR2_OCTOSPISEL_1|RCC_CCIPR2_OCTOSPISEL_0) /*!< PLL2 "Q" clock used as OctoSPI kernel clock source */ +/** + * @} + */ + +#if defined (HSPI1) +/** @defgroup RCC_LL_EC_HSPI1_CLKSOURCE Peripheral HSPI1 kernel clock source selection + * @{ + */ +#define LL_RCC_HSPI_CLKSOURCE_SYSCLK (0x00000000U) +#define LL_RCC_HSPI_CLKSOURCE_PLL1 RCC_CCIPR2_HSPISEL_0 +#define LL_RCC_HSPI_CLKSOURCE_PLL2 RCC_CCIPR2_HSPISEL_1 +#define LL_RCC_HSPI_CLKSOURCE_PLL3 RCC_CCIPR2_HSPISEL +/** + * @} + */ +#endif /* HSPI1 */ + +/** @defgroup RCC_LL_EC_TIM_INPUT_CAPTURE_CLOCKSource TIM Input capture clock source selection + * @{ + */ +#define LL_RCC_TIMIC_CLKSOURCE_NONE 0x00000000U /*!< No clock available for TIM16/TIM17 and LPTIM2 input capture */ +#define LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256 RCC_CCIPR1_TIMICSEL_2 /*!< HSI/256 selected for TIM16/TIM17 and LPTIM2 input capture */ +#define LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024 RCC_CCIPR1_TIMICSEL_2 /*!< MSIS/1024 selected for TIM16/TIM17 and LPTIM2 input capture */ +#define LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_1) /*!< MSIS/4 selected for TIM16/TIM17 and LPTIM2 input capture */ +#define LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV4 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_0) /*!< MSIK/4 selected for TIM16/TIM17 and LPTIM2 input capture */ +#define LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV1024 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_1 | \ + RCC_CCIPR1_TIMICSEL_0) /*!< MSIK/1024 selected for TIM16/TIM17 and LPTIM2 input capture */ +/** + * @} + */ + + +#if defined(SAES) +/** @defgroup RCC_LL_EC_SAES_CLKSOURCE Peripheral SAES clock source selection + * @{ + */ +#define LL_RCC_SAES_CLKSOURCE_SHSI 0x00000000U /*!< SHSI clock used as SAES clock source */ +#define LL_RCC_SAES_CLKSOURCE_SHSI_DIV2 RCC_CCIPR2_SAESSEL /*!< SHSI_DIV2 clock used as SAES clock source */ +/** + * @} + */ +#endif /* SAES */ + +/** @defgroup RCC_LL_EC_USART Peripheral USARTx get clock source + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_USART1SEL_Pos << 16U) | \ + (RCC_CCIPR1_USART1SEL >> RCC_CCIPR1_USART1SEL_Pos)) /*!< USART1 Clock source selection */ +#if defined(USART2) +#define LL_RCC_USART2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_USART2SEL_Pos << 16U) | \ + (RCC_CCIPR1_USART2SEL >> RCC_CCIPR1_USART2SEL_Pos)) /*!< USART2 Clock source selection */ +#endif /* USART2 */ +#define LL_RCC_USART3_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_USART3SEL_Pos << 16U) | \ + (RCC_CCIPR1_USART3SEL >> RCC_CCIPR1_USART3SEL_Pos)) /*!< USART3 Clock source selection */ +#if defined (RCC_CCIPR2_USART6SEL) +#define LL_RCC_USART6_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | \ + (RCC_CCIPR2_USART6SEL >> RCC_CCIPR2_USART6SEL_Pos)) /*!< USART6 Clock source selection */ +#endif /* RCC_CCIPR2_USART6SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_UART Peripheral UARTx get clock source + * @{ + */ +#define LL_RCC_UART4_CLKSOURCE RCC_CCIPR1_UART4SEL /*!< UART4 Clock source selection */ +#define LL_RCC_UART5_CLKSOURCE RCC_CCIPR1_UART5SEL /*!< UART5 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPI Peripheral SPIx get clock source + * @{ + */ +#define LL_RCC_SPI1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \ + (RCC_CCIPR1_SPI1SEL >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SPI1 Clock source selection */ +#define LL_RCC_SPI2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \ + (RCC_CCIPR1_SPI2SEL >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< SPI2 Clock source selection */ +#define LL_RCC_SPI3_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \ + (RCC_CCIPR3_SPI3SEL >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SPI3 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPUART Peripheral LPUARTx get clock source + * @{ + */ +#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR3_LPUART1SEL /*!< LPUART1 Clock source selection */ +/** + * @} + */ + +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE_PHY (RCC_CCIPR2_DSIHOSTSEL) +#define LL_RCC_DSI_CLKSOURCE_PLL3 (0x00000000U) +/** + * @} + */ +#endif /* DSI */ + +#if defined(LTDC) +/** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection + * @{ + */ +#define LL_RCC_LTDC_CLKSOURCE_PLL2 (RCC_CCIPR2_LTDCSEL) +#define LL_RCC_LTDC_CLKSOURCE_PLL3 (0x00000000U) +/** + * @} + */ +#endif /* LTDC */ + +#if defined (RCC_CCIPR2_USBPHYCSEL) +/** @defgroup RCC_LL_EC_USBPHY_CLKSOURCE Peripheral USBPHY clock source selection + * @{ + */ +#define LL_RCC_USBPHYCLKSOURCE_HSE (0x00000000U) /*!< HSE clock selected as USBPHYC clock */ +#define LL_RCC_USBPHYCLKSOURCE_HSE_DIV2 RCC_CCIPR2_USBPHYCSEL_1 /*!< HSE clock divided by 2 selected as USBPHYC clock */ +#define LL_RCC_USBPHYCLKSOURCE_PLL1 RCC_CCIPR2_USBPHYCSEL_0 /*!< PLL1 divider P selected as USBPHYC clock */ +#define LL_RCC_USBPHYCLKSOURCE_PLL1_DIV2 (RCC_CCIPR2_USBPHYCSEL_1 | RCC_CCIPR2_USBPHYCSEL_0) /*!< PLL1 divider P divided by 2 selected as USBPHYC clock */ +/** + * @} + */ +#endif /* RCC_CCIPR2_USBPHYCSEL */ + +/** @defgroup RCC_LL_EC_I2C Peripheral I2Cx get clock source + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \ + (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */ +#define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \ + (RCC_CCIPR1_I2C2SEL >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */ +#define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \ + (RCC_CCIPR3_I2C3SEL >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */ +#define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \ + (RCC_CCIPR1_I2C4SEL >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */ +#if defined (RCC_CCIPR2_I2C5SEL) +#define LL_RCC_I2C5_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \ + (RCC_CCIPR2_I2C5SEL >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< I2C1 Clock source selection */ +#endif /* RCC_CCIPR2_I2C5SEL */ +#if defined (RCC_CCIPR2_I2C6SEL) +#define LL_RCC_I2C6_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \ + (RCC_CCIPR2_I2C6SEL >> RCC_CCIPR2_I2C6SEL_Pos)) /*!< I2C1 Clock source selection */ +#endif /* RCC_CCIPR2_I2C6SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIM Peripheral LPTIMx get clock source + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \ + (RCC_CCIPR3_LPTIM1SEL >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LPTIM1 Clock source selection */ +#define LL_RCC_LPTIM2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \ + (RCC_CCIPR1_LPTIM2SEL >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LPTIM2 Clock source selection */ +#define LL_RCC_LPTIM34_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \ + (RCC_CCIPR3_LPTIM34SEL >> RCC_CCIPR3_LPTIM34SEL_Pos)) /*!< LPTIM3 and LPTIM4 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SAI Peripheral SAIx get clock source + * @{ + */ +#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */ +#if defined (SAI2) +#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL /*!< SAI2 Clock source selection */ +#endif /* SAI2 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SDMMC_KERNEL Peripheral SDMMC get kernel clock source + * @{ + */ +#define LL_RCC_SDMMC_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL /*!< SDMMC1/2 Kernel Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SDMMC1/2 Peripheral SDMMC get clock source + * @{ + */ +#define LL_RCC_SDMMC_CLKSOURCE RCC_CCIPR1_ICLKSEL /*!< SDMMC1/2 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR2_RNGSEL /*!< RNG Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + * @{ + */ +#define LL_RCC_USB_CLKSOURCE RCC_CCIPR1_ICLKSEL /*!< USB Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADCDAC Peripheral ADCDAC get clock source + * @{ + */ +#define LL_RCC_ADCDAC_CLKSOURCE RCC_CCIPR3_ADCDACSEL /*!< ADCDACs Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MDF1 Peripheral MDF1 get clock source + * @{ + */ +#define LL_RCC_MDF1_CLKSOURCE RCC_CCIPR2_MDF1SEL /* MDF1 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_DAC1 Peripheral DAC1 get clock source + * @{ + */ +#define LL_RCC_DAC1_CLKSOURCE RCC_CCIPR3_DAC1SEL /* DAC1 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADF1 Peripheral ADF1 get clock source + * @{ + */ +#define LL_RCC_ADF1_CLKSOURCE RCC_CCIPR3_ADF1SEL /*!< ADF1 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get kernel clock source + * @{ + */ +#define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR1_FDCANSEL /*!< FDCAN Kernel Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source + * @{ + */ +#define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR2_OCTOSPISEL /*!< OctoSPI Clock source selection */ +/** + * @} + */ +#if defined (HSPI1) +/** @defgroup RCC_LL_EC_HSPI Peripheral HSPI get clock source + * @{ + */ +#define LL_RCC_HSPI_CLKSOURCE RCC_CCIPR2_HSPISEL /*!< HSPI Clock source selection */ +/** + * @} + */ +#endif /* HSPI */ + +#if defined(SAES) +/** @defgroup RCC_LL_EC_SAES Peripheral SAES get clock source + * @{ + */ +#define LL_RCC_SAES_CLKSOURCE RCC_CCIPR2_SAESSEL /*!< SAES Clock source selection */ +/** + * @} + */ +#endif /* SAES */ + +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE RCC_CCIPR2_DSIHOSTSEL +/** + * @} + */ +#endif /* DSI */ + +#if defined(LTDC) +/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source + * @{ + */ +#define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR2_LTDCSEL +/** + * @} + */ +#endif /* LTDC */ + +#if defined (RCC_CCIPR2_USBPHYCSEL) +/** @defgroup RCC_LL_EC_USBPHY Peripheral USBPHY get clock source + * @{ + */ +#define LL_RCC_USBPHY_CLKSOURCE RCC_CCIPR2_USBPHYCSEL +/** + * @} + */ +#endif /* RCC_CCIPR2_USBPHYCSEL */ + +/** @defgroup RCC_LL_EC_PLL1SOURCE PLL1 entry clock source + * @{ + */ +#define LL_RCC_PLL1SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL1 entry clock source */ +#define LL_RCC_PLL1SOURCE_MSIS RCC_PLL1CFGR_PLL1SRC_0 /*!< MSIS clock selected as main PLL1 entry clock source */ +#define LL_RCC_PLL1SOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1 /*!< HSI clock selected as main PLL1 entry clock source */ +#define LL_RCC_PLL1SOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) /*!< HSE clock selected as main PLL1 entry clock source */ + +#define LL_RCC_PLLSOURCE_NONE LL_RCC_PLL1SOURCE_NONE /*!< alias define for compatibility with legacy code */ +#define LL_RCC_PLLSOURCE_MSIS LL_RCC_PLL1SOURCE_MSIS /*!< alias define for compatibility with legacy code */ +#define LL_RCC_PLLSOURCE_HSI LL_RCC_PLL1SOURCE_HSI /*!< alias define for compatibility with legacy code */ +#define LL_RCC_PLLSOURCE_HSE LL_RCC_PLL1SOURCE_HSE /*!< alias define for compatibility with legacy code */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input ranges + * @{ + */ +#define LL_RCC_PLLINPUTRANGE_4_8 0x00000000U /*!< VCO input range: 4 to 8 MHz */ +#define LL_RCC_PLLINPUTRANGE_8_16 RCC_PLL1CFGR_PLL1RGE /*!< VCO input range: 8 to 16 MHz */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL2SOURCE PLL2 entry clock source + * @{ + */ +#define LL_RCC_PLL2SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL2 entry clock source */ +#define LL_RCC_PLL2SOURCE_MSIS RCC_PLL2CFGR_PLL2SRC_0 /*!< MSIS clock selected as main PLL2 entry clock source */ +#define LL_RCC_PLL2SOURCE_HSI RCC_PLL2CFGR_PLL2SRC_1 /*!< HSI clock selected as main PLL2 entry clock source */ +#define LL_RCC_PLL2SOURCE_HSE (RCC_PLL2CFGR_PLL2SRC_0 | RCC_PLL2CFGR_PLL2SRC_1) /*!< HSE clock selected as main PLL2 entry clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL3SOURCE PLL3 entry clock source + * @{ + */ +#define LL_RCC_PLL3SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL3 entry clock source */ +#define LL_RCC_PLL3SOURCE_MSIS RCC_PLL3CFGR_PLL3SRC_0 /*!< MSIS clock selected as main PLL3 entry clock source */ +#define LL_RCC_PLL3SOURCE_HSI RCC_PLL3CFGR_PLL3SRC_1 /*!< HSI clock selected as main PLL3 entry clock source */ +#define LL_RCC_PLL3SOURCE_HSE (RCC_PLL3CFGR_PLL3SRC_0 | RCC_PLL3CFGR_PLL3SRC_1) /*!< HSE clock selected as main PLL3 entry clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection + * @{ + */ +#define LL_RCC_MSIRANGESEL_STANDBY 0U /*!< MSI Range is provided by MSISRANGE */ +#define LL_RCC_MSIRANGESEL_RUN 1U /*!< MSI Range is provided by MSISRANGE */ +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Security_Services Security Services + * @note Only available when system implements security (TZEN=1) + * @{ + */ +#define LL_RCC_ALL_NSEC 0U /*!< No security on RCC resources (default) */ +#define LL_RCC_ALL_SEC RCC_SECURE_MASK /*!< Security on all RCC resources */ + +#define LL_RCC_HSI_SEC RCC_SECCFGR_HSISEC /*!< HSI clock configuration security */ +#define LL_RCC_HSI_NSEC 0U /*!< HSI clock configuration secure/non-secure access */ +#define LL_RCC_HSE_SEC RCC_SECCFGR_HSESEC /*!< HSE clock configuration security */ +#define LL_RCC_HSE_NSEC 0U /*!< HSE clock configuration secure/non-secure access */ +#define LL_RCC_MSI_SEC RCC_SECCFGR_MSISEC /*!< MSI clock configuration security */ +#define LL_RCC_MSI_NSEC 0U /*!< MSI clock configuration secure/non-secure access */ +#define LL_RCC_LSE_SEC RCC_SECCFGR_LSESEC /*!< LSE clock configuration security */ +#define LL_RCC_LSE_NSEC 0U /*!< LSE clock configuration secure/non-secure access */ +#define LL_RCC_LSI_SEC RCC_SECCFGR_LSISEC /*!< LSI clock configuration security */ +#define LL_RCC_LSI_NSEC 0U /*!< LSI clock configuration secure/non-secure access */ +#define LL_RCC_SYSCLK_SEC RCC_SECCFGR_SYSCLKSEC /*!< SYSCLK clock; STOPWUCK and MCO output configuration security */ +#define LL_RCC_SYSCLK_NSEC 0U /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure/non-secure access */ +#define LL_RCC_PRESCALERS_SEC RCC_SECCFGR_PRESCSEC /*!< AHBx/APBx prescaler configuration security */ +#define LL_RCC_PRESCALERS_NSEC 0U /*!< AHBx/APBx prescaler configuration secure/non-secure access */ +#define LL_RCC_PLL1_SEC RCC_SECCFGR_PLL1SEC /*!< PLL1 clock configuration security */ +#define LL_RCC_PLL1_NSEC 0U /*!< main PLL1 clock configuration secure/non-secure access */ +#define LL_RCC_PLL2_SEC RCC_SECCFGR_PLL2SEC /*!< PLL2 clock configuration security */ +#define LL_RCC_PLL2_NSEC 0U /*!< main PLL2 clock configuration secure/non-secure access */ +#define LL_RCC_PLL3_SEC RCC_SECCFGR_PLL3SEC /*!< PLL3 clock configuration security */ +#define LL_RCC_PLL3_NSEC 0U /*!< main PLL3 clock configuration secure/non-secure access */ +#define LL_RCC_ICLK_SEC RCC_SECCFGR_ICLKSEC /*!< ICLK clock source selection security */ +#define LL_RCC_ICLK_NSEC 0U /*!< ICLK clock source selection secure/non-secure access */ +#define LL_RCC_HSI48_SEC RCC_SECCFGR_HSI48SEC /*!< HSI48 clock configuration security */ +#define LL_RCC_HSI48_NSEC 0U /*!< HSI48 clock configuration secure/non-secure access */ +#define LL_RCC_RESET_FLAGS_SEC RCC_SECCFGR_RMVFSEC /*!< Remove reset flag security */ +#define LL_RCC_RESET_FLAGS_NSEC 0U + +#define LL_RCC_PLL_SEC LL_RCC_PLL1_NSEC /*!< alias define for compatibility with legacy code */ +#define LL_RCC_PLL_NSEC LL_RCC_PLL1_NSEC /*!< alias define for compatibility with legacy code */ +#define LL_RCC_CLK48M_SEC LL_RCC_ICLK_SEC /*!< alias define for compatibility with legacy code */ +#define LL_RCC_CLK48M_NSEC LL_RCC_ICLK_NSEC /*!< alias define for compatibility with legacy code */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +/** + * @brief Helper macro to calculate the PLL1CLK frequency on system domain + * @note ex: @ref __LL_RCC_CALC_PLL1CLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (), + * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetR ()); + * @param __INPUTFREQ__ PLL1 Input frequency (based on MSI/HSE/HSI) + * @param __PLL1M__ parameter can be a value between 1 and 16 + * @param __PLL1N__ parameter can be a value between 4 and 512 + * @param __PLL1R__ parameter can be a value between 1 and 128 (Only division by 1 and even division are allowed) + * @retval PLL1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL1CLK_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1R__) ((((__INPUTFREQ__) /(__PLL1M__)) * \ + (__PLL1N__)) / (__PLL1R__)) +#define __LL_RCC_CALC_PLLCLK_FREQ __LL_RCC_CALC_PLL1CLK_FREQ /*!< alias for compatibility with legacy code */ + +/** + * @brief Helper macro to calculate the PLL1CLK frequency used on SAI domain + * @note ex: @ref __LL_RCC_CALC_PLL1CLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (), + * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetP ()); + * @param __INPUTFREQ__ PLL1 Input frequency (based on MSI/HSE/HSI) + * @param __PLL1M__ parameter can be a value between 1 and 16 + * @param __PLL1N__ parameter can be a value between 4 and 512 + * @param __PLL1P__ parameter can be a value between 1 and 128 + * @retval PLL1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL1CLK_SAI_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1P__) ((((__INPUTFREQ__) \ + /(__PLL1M__)) * (__PLL1N__)) / (__PLL1P__)) +#define __LL_RCC_CALC_PLLCLK_SAI_FREQ __LL_RCC_CALC_PLL1CLK_SAI_FREQ /*!< alias for compatibility with legacy code */ + +/** + * @brief Helper macro to calculate the PLL1CLK frequency used on 48M domain + * @note ex: @ref __LL_RCC_CALC_PLL1CLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (), + * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetQ ()); + * @param __INPUTFREQ__ PLL1 Input frequency (based on MSI/HSE/HSI) + * @param __PLL1M__ parameter can be a value between 1 and 16 + * @param __PLL1N__ parameter can be a value between 4 and 512 + * @param __PLL1Q__ parameter can be a value between 1 and 128 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL1CLK_48M_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1Q__) ((((__INPUTFREQ__) \ + /(__PLL1M__)) * (__PLL1N__)) / (__PLL1Q__)) +#define __LL_RCC_CALC_PLLCLK_48M_FREQ __LL_RCC_CALC_PLL1CLK_48M_FREQ /*!< alias for compatibility with legacy code */ + +/** + * @brief Helper macro to calculate the PLL2 frequency used for SAI domain + * @note ex: @ref __LL_RCC_CALC_PLL2CLK_SAI_FREQ (HSE_ALUE,@ref LL_RCC_PLL2_GetDivider (), + * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLL2M__ parameter can be a value between 1 and 16 + * @param __PLL2N__ parameter can be a value between 4 and 512 + * @param __PLL2P__ parameter can be a value between 1 and 128 + * @retval PLL2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL2CLK_SAI_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2P__) ((((__INPUTFREQ__) \ + /(__PLL2M__)) * (__PLL2N__)) / (__PLL2P__)) + +/** + * @brief Helper macro to calculate the PLL2 frequency used on 48M domain + * @note ex: @ref __LL_RCC_CALC_PLL2CLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL2_GetDivider (), + * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLL2M__ parameter can be a value between 1 and 16 + * @param __PLL2N__ parameter can be a value between 4 and 512 + * @param __PLL2Q__ parameter can be a value between 1 and 128 + * @retval PLL2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL2CLK_48M_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2Q__) ((((__INPUTFREQ__) \ + /(__PLL2M__)) * (__PLL2N__)) / (__PLL2Q__)) + +/** + * @brief Helper macro to calculate the PLL2 frequency used on ADC domain + * @note ex: @ref __LL_RCC_CALC_PLL2CLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL2_GetDivider (), + * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetR ()); + * @param __INPUTFREQ__ PLL2 Input frequency (based on MSI/HSE/HSI) + * @param __PLL2M__ parameter can be a value between 1 and 16 + * @param __PLL2N__ parameter can be a value between 4 and 512 + * @param __PLL2R__ parameter can be a value between 1 and 128 + * @retval PLL2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL2CLK_ADC_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2R__) ((((__INPUTFREQ__) \ + /(__PLL2M__)) * (__PLL2N__)) / (__PLL2R__)) + +/** + * @brief Helper macro to calculate the PLL3 frequency used for SAI domain + * @note ex: @ref __LL_RCC_CALC_PLL3CLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetDivider (), + * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetP ()); + * @param __INPUTFREQ__ PLL3 Input frequency (based on MSI/HSE/HSI) + * @param __PLL3M__ parameter can be a value between 1 and 16 + * @param __PLL3N__ parameter can be a value between 4 and 512 + * @param __PLL3P__ parameter can be a value between 1 and 128 + * @retval PLL3 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL3CLK_SAI_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3P__)((((__INPUTFREQ__) \ + /(__PLL3M__)) * (__PLL3N__)) / (__PLL3P__)) + +/** + * @brief Helper macro to calculate the PLL2 frequency used on 48M domain + * @note ex: @ref __LL_RCC_CALC_PLL3CLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetDivider (), + * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetQ ()); + * @param __INPUTFREQ__ PLL3 Input frequency (based on MSI/HSE/HSI) + * @param __PLL3M__ parameter can be a value between 1 and 16 + * @param __PLL3N__ parameter can be a value between 4 and 512 + * @param __PLL3Q__ parameter can be a value between 1 and 128 + * @retval PLL3 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL3CLK_48M_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3Q__) ((((__INPUTFREQ__) \ + /(__PLL3M__)) * (__PLL3N__)) / (__PLL3Q__)) + +#if defined(HSPI1) || defined(LTDC) +/** + * @brief Helper macro to calculate the PLL3 frequency used on HSPI domain + * @note ex: @ref __LL_RCC_CALC_PLL3CLK_HSPI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetDivider (), + * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetQ ()); + * @param __INPUTFREQ__ PLL3 Input frequency (based on MSI/HSE/HSI) + * @param __PLL3M__ parameter can be a value between 1 and 16 + * @param __PLL3N__ parameter can be a value between 4 and 512 + * @param __PLL3R__ parameter can be a value between 1 and 128 + * @retval PLL3 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL3CLK_HSPI_LTDC_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3R__) ((((__INPUTFREQ__) \ + /(__PLL3M__)) * (__PLL3N__)) / (__PLL3R__)) +/* Legacy define */ +#define __LL_RCC_CALC_PLL3CLK_HSPI_FREQ __LL_RCC_CALC_PLL3CLK_HSPI_LTDC_FREQ +#endif /* HSPI1 || LTDC */ + +/** + * @brief Helper macro to calculate the HCLK frequency + * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK) + * @param __AHBPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> \ + AHBPrescTable[((__AHBPRESCALER__)& RCC_CFGR2_HPRE) \ + >> RCC_CFGR2_HPRE_Pos]) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> \ + (APBPrescTable[((__APB1PRESCALER__)& \ + RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos])) + +/** + * @brief Helper macro to calculate the PCLK2 frequency (ABP2) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB2PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval PCLK2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >>\ + APBPrescTable[(__APB2PRESCALER__) >> \ + RCC_CFGR2_PPRE2_Pos]) + +/** + * @brief Helper macro to calculate the PCLK3 frequency (ABP3) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB3PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB3_DIV_1 + * @arg @ref LL_RCC_APB3_DIV_2 + * @arg @ref LL_RCC_APB3_DIV_4 + * @arg @ref LL_RCC_APB3_DIV_8 + * @arg @ref LL_RCC_APB3_DIV_16 + * @retval PCLK3 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> \ + APBPrescTable[(__APB3PRESCALER__) >> \ + RCC_CFGR3_PPRE3_Pos]) + +/** + * @brief Helper macro to calculate the MSIS frequency (in Hz) + * @note __MSISSEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect() + * @note if __MSISSEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY, + * __MSISRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby() + * else by LL_RCC_MSI_GetRange() + * ex: __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + * (LL_RCC_MSI_IsEnabledRangeSelect()? + * LL_RCC_MSI_GetRange(): + * LL_RCC_MSI_GetRangeAfterStandby())) + * @param __MSISSEL__ This parameter can be one of the following values: + * @arg @ref LL_RCC_MSIRANGESEL_STANDBY + * @arg @ref LL_RCC_MSIRANGESEL_RUN + * @param __MSISRANGE__ This parameter can be one of the following values: + * @arg @ref LL_RCC_MSISRANGE_0 + * @arg @ref LL_RCC_MSISRANGE_1 + * @arg @ref LL_RCC_MSISRANGE_2 + * @arg @ref LL_RCC_MSISRANGE_3 + * @arg @ref LL_RCC_MSISRANGE_4 + * @arg @ref LL_RCC_MSISRANGE_5 + * @arg @ref LL_RCC_MSISRANGE_6 + * @arg @ref LL_RCC_MSISRANGE_7 + * @arg @ref LL_RCC_MSISRANGE_8 + * @arg @ref LL_RCC_MSISRANGE_9 + * @arg @ref LL_RCC_MSISRANGE_10 + * @arg @ref LL_RCC_MSISRANGE_11 + * @arg @ref LL_RCC_MSISRANGE_12 + * @arg @ref LL_RCC_MSISRANGE_13 + * @arg @ref LL_RCC_MSISRANGE_14 + * @arg @ref LL_RCC_MSISRANGE_15 + * @retval MSI clock frequency (in Hz) + */ +#define __LL_RCC_CALC_MSIS_FREQ(__MSISSEL__, __MSISRANGE__) (((__MSISSEL__) == LL_RCC_MSIRANGESEL_RUN) ? \ + (MSIRangeTable[((__MSISRANGE__) >> 28U) & 0x0FU]) : \ + (MSIRangeTable[((__MSISRANGE__) >> 12U) & 0x0FU])) + + +/** + * @brief Helper macro to calculate the MSIK frequency (in Hz) + * @note __MSIKSEL__ can be retrieved thanks to function LL_RCC_MSIK_IsEnabledRangeSelect() + * @note if __MSIKSEL__ is equal to LL_RCC_MSIKRANGESEL_STANDBY, + * __MSIKRANGE__can be retrieved by LL_RCC_MSIK_GetRangeAfterStandby() + * else by LL_RCC_MSIK_GetRange() + * ex: __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSIK_IsEnabledRangeSelect(), + * (LL_RCC_MSIK_IsEnabledRangeSelect()? + * LL_RCC_MSIK_GetRange(): + * LL_RCC_MSIK_GetRangeAfterStandby())) + * @param __MSIKSEL__ This parameter can be one of the following values: + * @arg @ref LL_RCC_MSIRANGESEL_STANDBY + * @arg @ref LL_RCC_MSIRANGESEL_RUN + * @param __MSIKRANGE__ This parameter can be one of the following values: + * @arg @ref LL_RCC_MSIKRANGE_0 + * @arg @ref LL_RCC_MSIKRANGE_1 + * @arg @ref LL_RCC_MSIKRANGE_2 + * @arg @ref LL_RCC_MSIKRANGE_3 + * @arg @ref LL_RCC_MSIKRANGE_4 + * @arg @ref LL_RCC_MSIKRANGE_5 + * @arg @ref LL_RCC_MSIKRANGE_6 + * @arg @ref LL_RCC_MSIKRANGE_7 + * @arg @ref LL_RCC_MSIKRANGE_8 + * @arg @ref LL_RCC_MSIKRANGE_9 + * @arg @ref LL_RCC_MSIKRANGE_10 + * @arg @ref LL_RCC_MSIKRANGE_11 + * @arg @ref LL_RCC_MSIKRANGE_12 + * @arg @ref LL_RCC_MSIKRANGE_13 + * @arg @ref LL_RCC_MSIKRANGE_14 + * @arg @ref LL_RCC_MSIKRANGE_15 + * @retval MSIK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_MSIK_FREQ(__MSIKSEL__, __MSIKRANGE__) (((__MSIKSEL__) == LL_RCC_MSIRANGESEL_RUN) ? \ + (MSIRangeTable[((__MSIKRANGE__) >> 24U) & 0x0FU]) : \ + (MSIRangeTable[((__MSIKRANGE__) >> 8U) & 0x0FU])) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL); +} + +/** + * @brief Set external HSE clock mode + * @note This bit can be written only if the HSE oscillator is disabled + * @rmtoll CR HSEEXT LL_RCC_HSE_SetClockMode + * @param HSEMode This parameter can be one of the following values: + * @arg @ref LL_RCC_HSE_ANALOG_MODE + * @arg @ref LL_RCC_HSE_DIGITAL_MODE + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_SetClockMode(uint32_t HSEMode) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSEEXT, HSEMode); +} + +/** + * @brief Get External HSE clock mode + * @rmtoll CR HSEEXT LL_RCC_HSE_GetClockMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_HSE_ANALOG_MODE + * @arg @ref LL_RCC_HSE_DIGITAL_MODE + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_GetClockMode(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSEEXT)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI even in stop mode + * @note HSI oscillator is forced ON even in Stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Disable HSI in stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Check if HSI is enabled in stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL); +} + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll ICSCR3 HSICAL LL_RCC_HSI_GetCalibration + * @retval Between Min_Data = 0 and Max_Data = 127 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR3, RCC_ICSCR3_HSICAL) >> RCC_ICSCR3_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 64, which, when added to the HSICAL value, + * should trim the HSI to 16 MHz +/- 1 % + * @rmtoll ICSCR3 HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value Between Min_Data = 0 and Max_Data = 127 + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, Value << RCC_ICSCR3_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll ICSC3R HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval Between Min_Data = 0 and Max_Data = 127 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR3, RCC_ICSCR3_HSITRIM) >> RCC_ICSCR3_HSITRIM_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI48 HSI48 + * @{ + */ + +/** + * @brief Enable HSI48 + * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSI48ON); +} + +/** + * @brief Disable HSI48 + * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); +} + +/** + * @brief Check if HSI48 oscillator Ready + * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == RCC_CR_HSI48RDY) ? 1UL : 0UL); +} + +/** + * @brief Get HSI48 Calibration value + * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +} + +/** + * @brief Enable Clock security system on LSE. + * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Disable Clock security system on LSE. + * @note Clock security system can be disabled only after a LSE + * failure detection. In that case it MUST be disabled by software. + * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL); +} + +/** + * @brief Enable LSE oscillator propagation for system clock + * @rmtoll BDCR LSESYSEN LL_RCC_LSE_EnablePropagation + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); +} + +/** + * @brief Check if LSESYS oscillator Ready + * @rmtoll BDCR LSESYSRDY LL_RCC_LSESYS_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSESYS_IsReady(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == RCC_BDCR_LSESYSRDY) ? 1UL : 0UL); +} + +/** + * @brief Disable LSE oscillator propagation for system clock + * @rmtoll BDCR LSESYSEN LL_RCC_LSE_DisablePropagation + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); +} + +/** + * @brief Check if LSE oscillator propagation for system clock Ready + * @rmtoll BDCR LSESYSRDY LL_RCC_LSE_IsPropagationReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationReady(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == RCC_BDCR_LSESYSRDY) ? 1UL : 0UL); +} + +/** + * @brief Check if CSS on LSE failure Detection + * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL); +} + +/** + * @brief Enable LSE clock glitch filter. + * @note The glitches on LSE can be filtred by setting the LSEGFON. + * @note LSEGFON must be written when the LSE is disabled (LSEON = 0 and LSERDY = 0). + * @rmtoll BDCR LSEGFON LL_RCC_LSE_EnableGlitchFilter + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableGlitchFilter(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEGFON); +} + +/** + * @brief Disable LSE clock glitch filter. + * @note LSEGFON must be written when the LSE is disabled (LSEON = 0 and LSERDY = 0). + * @rmtoll BDCR LSEGFON LL_RCC_LSE_DisableGlitchFilter + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableGlitchFilter(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEGFON); +} + +/** + * @brief Check if LSE clock glitch filter is enabled + * @rmtoll BDCR LSEGFON LL_RCC_LSE_IsGlitchFilterEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsGlitchFilterEnabled(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSEGFON) == RCC_BDCR_LSEGFON) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll BDCR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll BDCR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll BDCR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) == RCC_BDCR_LSIRDY) ? 1UL : 0UL); +} + +/** + * @brief Set LSI prescaler + * @rmtoll BDCR LSIPREDIV LL_RCC_LSI_SetPrescaler + * @param LSIPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_LSI_DIV_1 + * @arg @ref LL_RCC_LSI_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_SetPrescaler(uint32_t LSIPrescaler) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSIPREDIV, LSIPrescaler); +} + +/** + * @brief Get LSI prescaler + * @rmtoll BDCR LSIPREDIV LL_RCC_LSI_GetPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSI_DIV_1 + * @arg @ref LL_RCC_LSI_DIV_128 + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_GetPrescaler(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MSIK MSIK + * @{ + */ + +/** + * @brief Enable MSIK oscillator + * @rmtoll CR MSIKON LL_RCC_MSIK_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSIK_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_MSIKON); +} + +/** + * @brief Disable MSIK oscillator + * @rmtoll CR MSIKON LL_RCC_MSIK_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSIK_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_MSIKON); +} + +/** + * @brief Check if MSIK oscillator Ready + * @rmtoll CR MSIKRDY LL_RCC_MSIK_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_MSIK_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_MSIKRDY) == RCC_CR_MSIKRDY) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_SHSI SHSI + * @{ + */ + +/** + * @brief Enable SHSI oscillator + * @rmtoll CR SHSION LL_RCC_SHSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_SHSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_SHSION); +} + +/** + * @brief Disable SHSI oscillator + * @rmtoll CR SHSION LL_RCC_SHSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_SHSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_SHSION); +} + +/** + * @brief Check if SHSI oscillator Ready + * @rmtoll CR SHSIRDY LL_RCC_SHSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_SHSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_SHSIRDY) == RCC_CR_SHSIRDY) ? 1UL : 0UL); +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MSI MSI + * @{ + */ + +/** + * @brief Enable MSIS oscillator + * @rmtoll CR MSISON LL_RCC_MSIS_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSIS_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_MSISON); +} +#define LL_RCC_MSI_Enable LL_RCC_MSIS_Enable /*!< alias define for compatibility with legacy code */ + +/** + * @brief Disable MSIS oscillator + * @rmtoll CR MSISON LL_RCC_MSIS_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSIS_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_MSISON); +} +#define LL_RCC_MSI_Disable LL_RCC_MSIS_Disable /*!< alias define for compatibility with legacy code */ + +/** + * @brief Check if MSIS oscillator Ready + * @rmtoll CR MSISRDY LL_RCC_MSIS_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_MSIS_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_MSISRDY) == RCC_CR_MSISRDY) ? 1UL : 0UL); +} +#define LL_RCC_MSI_IsReady LL_RCC_MSIS_IsReady /*!< alias define for compatibility with legacy code */ + +/** + * @brief Enable MSI PLL-mode (Hardware auto calibration with LSE) + * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) + * and ready (LSERDY set by hardware) + * @note hardware protection to avoid enabling MSIPLLEN if LSE is not + * ready + * @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_MSIPLLEN); +} + +/** + * @brief Disable MSI-PLL mode + * @note cleared by hardware when LSE is disabled (LSEON = 0) or when + * the Clock Security System on LSE detects a LSE failure + * @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN); +} + +/** + * @brief Check if MSI-PLL mode has been enabled or not + * @rmtoll CR MSIPLLEN LL_RCC_IsEnabledPLLMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledPLLMode(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == RCC_CR_MSIPLLEN) ? 1UL : 0UL); +} + +/** + * @brief Set clock source in PLL mode + * @rmtoll CR MSIPLLSEL LL_RCC_SetMSIPLLMode + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLMODE_MSIS + * @arg @ref LL_RCC_PLLMODE_MSIK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetMSIPLLMode(uint32_t Source) +{ + MODIFY_REG(RCC->CR, RCC_CR_MSIPLLSEL, Source); +} + +/** + * @brief Get Clock source in PLL Mode + * @rmtoll CR MSIPLLSEL LL_RCC_GetMSIPLLMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLMODE_MSIS + * @arg @ref LL_RCC_PLLMODE_MSIK + */ +__STATIC_INLINE uint32_t LL_RCC_GetMSIPLLMode(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIPLLSEL)); +} + +/** + * @brief Enable MSI fast mode + * @rmtoll CR MSIPLLFAST LL_RCC_Enable_MSIPLLFAST + * @note This bit is used only if PLL mode is selected. + */ +__STATIC_INLINE void LL_RCC_Enable_MSIPLLFAST(void) +{ + SET_BIT(RCC->CR, RCC_CR_MSIPLLFAST); +} + +/** + * @brief Disable MSI fast mode + * @rmtoll CR MSIPLLFAST LL_RCC_Disable_MSIPLLFAST + * @note This bit is used only if PLL mode is selected. + */ +__STATIC_INLINE void LL_RCC_Disable_MSIPLLFAST(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLFAST); +} + +/** + * @brief Check if MSI PLL Fast Mode is enable + * @rmtoll CR MSIPLLFAST LL_RCC_MSI_IsEnabledMSIPLLFAST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledMSIPLLFAST(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_MSIPLLFAST) == RCC_CR_MSIPLLFAST) ? 1UL : 0UL); +} + +/** + * @brief Set MSI Bias mode + * @rmtoll ICSCR1 MSIBIAS LL_RCC_MSI_SetMSIBiasMode + * @param BiasMode This parameter can be one of the following values: + * @arg @ref LL_RCC_MSIBIASMODE_CONTINUOUS + * @arg @ref LL_RCC_MSIBIASMODE_SAMPLING + + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_SetMSIBiasMode(uint32_t BiasMode) +{ + MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS, BiasMode); +} + +/** + * @brief Get MSI Bias mode + * @rmtoll ICSCR1 MSIBIAS LL_RCC_MSI_GetMSIBiasMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_MSIBIASMODE_CONTINUOUS + * @arg @ref LL_RCC_MSIBIASMODE_SAMPLING + + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_GetMSIBiasMode(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS)); +} + +/** + * @brief Enable MSIK even in stop mode + * @note MSIK oscillator is forced ON even in Stop mode + * @rmtoll CR MSIKERON LL_RCC_MSIK_EnableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSIK_EnableInStopMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_MSIKERON); +} + +/** + * @brief Disable MSIK in stop mode + * @rmtoll CR MSIKERON LL_RCC_MSIK_DisableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSIK_DisableInStopMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_MSIKERON); +} + +/** + * @brief Check if MSIK is enabled in stop mode + * @rmtoll CR MSIKERON LL_RCC_MSIK_IsEnabledInStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_MSIK_IsEnabledInStopMode(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_MSIKERON) == RCC_CR_MSIKERON) ? 1UL : 0UL); +} + +/** + * @brief Enable MSI clock range selection with MSIRANGE register + * @note Write 0 has no effect. After a standby or a reset + * MSIRGSEL is at 0 and the MSI range value is provided by + * MSISRANGE + * @rmtoll ICSCR1 MSIRGSEL LL_RCC_MSI_EnableRangeSelection + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void) +{ + SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); +} + +/** + * @brief Check if MSI clock range is selected with MSIRANGE register + * @rmtoll ICSCR1 MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void) +{ + return ((READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == RCC_ICSCR1_MSIRGSEL) ? 1UL : 0UL); +} + +/** + * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode. + * @rmtoll ICSCR1 MSISRANGE LL_RCC_MSIS_SetRange + * @param Range This parameter can be one of the following values: + * @arg @ref LL_RCC_MSISRANGE_0 + * @arg @ref LL_RCC_MSISRANGE_1 + * @arg @ref LL_RCC_MSISRANGE_2 + * @arg @ref LL_RCC_MSISRANGE_3 + * @arg @ref LL_RCC_MSISRANGE_4 + * @arg @ref LL_RCC_MSISRANGE_5 + * @arg @ref LL_RCC_MSISRANGE_6 + * @arg @ref LL_RCC_MSISRANGE_7 + * @arg @ref LL_RCC_MSISRANGE_8 + * @arg @ref LL_RCC_MSISRANGE_9 + * @arg @ref LL_RCC_MSISRANGE_10 + * @arg @ref LL_RCC_MSISRANGE_11 + * @arg @ref LL_RCC_MSISRANGE_12 + * @arg @ref LL_RCC_MSISRANGE_13 + * @arg @ref LL_RCC_MSISRANGE_14 + * @arg @ref LL_RCC_MSISRANGE_15 + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSIS_SetRange(uint32_t Range) +{ + MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, Range); +} +#define LL_RCC_MSI_SetRange LL_RCC_MSIS_SetRange /*!< alias define for compatibility with legacy code */ + +/** + * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode. + * @rmtoll ICSCR1 MSISRANGE LL_RCC_MSIS_GetRange + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_MSISRANGE_0 + * @arg @ref LL_RCC_MSISRANGE_1 + * @arg @ref LL_RCC_MSISRANGE_2 + * @arg @ref LL_RCC_MSISRANGE_3 + * @arg @ref LL_RCC_MSISRANGE_4 + * @arg @ref LL_RCC_MSISRANGE_5 + * @arg @ref LL_RCC_MSISRANGE_6 + * @arg @ref LL_RCC_MSISRANGE_7 + * @arg @ref LL_RCC_MSISRANGE_8 + * @arg @ref LL_RCC_MSISRANGE_9 + * @arg @ref LL_RCC_MSISRANGE_10 + * @arg @ref LL_RCC_MSISRANGE_11 + * @arg @ref LL_RCC_MSISRANGE_12 + * @arg @ref LL_RCC_MSISRANGE_13 + * @arg @ref LL_RCC_MSISRANGE_14 + * @arg @ref LL_RCC_MSISRANGE_15 + */ +__STATIC_INLINE uint32_t LL_RCC_MSIS_GetRange(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE)); +} +#define LL_RCC_MSI_GetRange LL_RCC_MSIS_GetRange /*!< alias define for compatibility with legacy code */ + +/** + * @brief Configure MSIS range used after standby + * @rmtoll CSR MSISSRANGE LL_RCC_MSIS_SetRangeAfterStandby + * @param Range This parameter can be one of the following values: + * @arg @ref LL_RCC_MSISSRANGE_4 + * @arg @ref LL_RCC_MSISSRANGE_5 + * @arg @ref LL_RCC_MSISSRANGE_6 + * @arg @ref LL_RCC_MSISSRANGE_7 + * @arg @ref LL_RCC_MSISSRANGE_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSIS_SetRangeAfterStandby(uint32_t Range) +{ + MODIFY_REG(RCC->CSR, RCC_CSR_MSISSRANGE, Range); +} +#define LL_RCC_MSI_SetRangeAfterStandby LL_RCC_MSIS_SetRangeAfterStandby /*!< alias define for compatibility with legacy code */ + +/** + * @brief Get MSIS range used after standby + * @rmtoll CSR MSISSRANGE LL_RCC_MSIS_GetRangeAfterStandby + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_MSISSRANGE_4 + * @arg @ref LL_RCC_MSISSRANGE_5 + * @arg @ref LL_RCC_MSISSRANGE_6 + * @arg @ref LL_RCC_MSISSRANGE_7 + * @arg @ref LL_RCC_MSISSRANGE_8 + */ +__STATIC_INLINE uint32_t LL_RCC_MSIS_GetRangeAfterStandby(void) +{ + return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISSRANGE)); +} +#define LL_RCC_MSI_GetRangeAfterStandby LL_RCC_MSIS_GetRangeAfterStandby /*!< alias define for compatibility with legacy code */ + +/** + * @brief Set MSI OSCILLATORx Calibration trimming + * @note user-programmable trimming value that is added to the MSICALx + * @rmtoll ICSCR2 MSITRIMx LL_RCC_MSI_SetCalibTrimming + * @param Value Between Min_Data = 0 and Max_Data = 31 + * @param Oscillator This parameter can be one of the following values: + * @arg @ref LL_RCC_MSI_OSCILLATOR_0 + * @arg @ref LL_RCC_MSI_OSCILLATOR_1 + * @arg @ref LL_RCC_MSI_OSCILLATOR_2 + * @arg @ref LL_RCC_MSI_OSCILLATOR_3 + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value, uint32_t Oscillator) +{ + MODIFY_REG(RCC->ICSCR2, (RCC_ICSCR2_MSITRIM0 >> Oscillator), Value << (RCC_ICSCR2_MSITRIM0_Pos - Oscillator)); +} + +/** + * @brief Get MSI OSCILLATORx Calibration trimming + * @rmtoll ICSCR2 MSITRIMx LL_RCC_MSI_GetCalibTrimming + * @retval Between 0 and 31 + * @param Oscillator This parameter can be one of the following values: + * @arg @ref LL_RCC_MSI_OSCILLATOR_0 + * @arg @ref LL_RCC_MSI_OSCILLATOR_1 + * @arg @ref LL_RCC_MSI_OSCILLATOR_2 + * @arg @ref LL_RCC_MSI_OSCILLATOR_3 + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(uint32_t Oscillator) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR2, + (RCC_ICSCR2_MSITRIM0 >> Oscillator)) >> (RCC_ICSCR2_MSITRIM0_Pos - Oscillator)); +} + +/** + * @brief Get MSI OSCILLATORx Calibration value + * @note When MSITRIMx is written, MSICALx is updated with the sum of + * MSITRIMx and the factory trim value + * @rmtoll ICSCR1 MSICALx LL_RCC_MSI_GetCalibration + * @param Oscillator This parameter can be one of the following values: + * @arg @ref LL_RCC_MSI_OSCILLATOR_0 + * @arg @ref LL_RCC_MSI_OSCILLATOR_1 + * @arg @ref LL_RCC_MSI_OSCILLATOR_2 + * @arg @ref LL_RCC_MSI_OSCILLATOR_3 + * @retval Between Min_Data = 0 and Max_Data = 31 + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(uint32_t Oscillator) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR1, (RCC_ICSCR1_MSICAL0 >> Oscillator)) >> (RCC_ICSCR1_MSICAL0_Pos - Oscillator)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MSIK MSIK + * @{ + */ + +/** + * @brief Configure the Internal Multi Speed oscillator (MSIK) clock range in run mode. + * @rmtoll ICSCR1 MSIKRANGE LL_RCC_MSIK_SetRange + * @param Range This parameter can be one of the following values: + * @arg @ref LL_RCC_MSIKRANGE_0 + * @arg @ref LL_RCC_MSIKRANGE_1 + * @arg @ref LL_RCC_MSIKRANGE_2 + * @arg @ref LL_RCC_MSIKRANGE_3 + * @arg @ref LL_RCC_MSIKRANGE_4 + * @arg @ref LL_RCC_MSIKRANGE_5 + * @arg @ref LL_RCC_MSIKRANGE_6 + * @arg @ref LL_RCC_MSIKRANGE_7 + * @arg @ref LL_RCC_MSIKRANGE_8 + * @arg @ref LL_RCC_MSIKRANGE_9 + * @arg @ref LL_RCC_MSIKRANGE_10 + * @arg @ref LL_RCC_MSIKRANGE_11 + * @arg @ref LL_RCC_MSIKRANGE_12 + * @arg @ref LL_RCC_MSIKRANGE_13 + * @arg @ref LL_RCC_MSIKRANGE_14 + * @arg @ref LL_RCC_MSIKRANGE_15 + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSIK_SetRange(uint32_t Range) +{ + MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE, Range); +} + +/** + * @brief Get the Internal Multi Speed oscillator (MSIK) clock range in run mode. + * @rmtoll ICSCR1 MSIKRANGE LL_RCC_MSIK_GetRange + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_MSIKRANGE_0 + * @arg @ref LL_RCC_MSIKRANGE_1 + * @arg @ref LL_RCC_MSIKRANGE_2 + * @arg @ref LL_RCC_MSIKRANGE_3 + * @arg @ref LL_RCC_MSIKRANGE_4 + * @arg @ref LL_RCC_MSIKRANGE_5 + * @arg @ref LL_RCC_MSIKRANGE_6 + * @arg @ref LL_RCC_MSIKRANGE_7 + * @arg @ref LL_RCC_MSIKRANGE_8 + * @arg @ref LL_RCC_MSIKRANGE_9 + * @arg @ref LL_RCC_MSIKRANGE_10 + * @arg @ref LL_RCC_MSIKRANGE_11 + * @arg @ref LL_RCC_MSIKRANGE_12 + * @arg @ref LL_RCC_MSIKRANGE_13 + * @arg @ref LL_RCC_MSIKRANGE_14 + * @arg @ref LL_RCC_MSIKRANGE_15 + */ +__STATIC_INLINE uint32_t LL_RCC_MSIK_GetRange(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE)); +} + +/** + * @brief Configure MSIK range used after standby + * @rmtoll CSR MSIKSRANGE LL_RCC_MSIK_SetRangeAfterStandby + * @param Range This parameter can be one of the following values: + * @arg @ref LL_RCC_MSIKSRANGE_4 + * @arg @ref LL_RCC_MSIKSRANGE_5 + * @arg @ref LL_RCC_MSIKSRANGE_6 + * @arg @ref LL_RCC_MSIKSRANGE_7 + * @arg @ref LL_RCC_MSIKSRANGE_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSIK_SetRangeAfterStandby(uint32_t Range) +{ + MODIFY_REG(RCC->CSR, RCC_CSR_MSIKSRANGE, Range); +} + +/** + * @brief Get MSIK range used after standby + * @rmtoll CSR MSIKSRANGE LL_RCC_MSIK_GetRangeAfterStandby + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_MSIKSRANGE_4 + * @arg @ref LL_RCC_MSIKSRANGE_5 + * @arg @ref LL_RCC_MSIKSRANGE_6 + * @arg @ref LL_RCC_MSIKSRANGE_7 + * @arg @ref LL_RCC_MSIKSRANGE_8 + */ +__STATIC_INLINE uint32_t LL_RCC_MSIK_GetRangeAfterStandby(void) +{ + return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSIKSRANGE)); +} +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSCO LSCO + * @{ + */ + +/** + * @brief Enable Low speed clock + * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); +} + +/** + * @brief Disable Low speed clock + * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); +} + +/** + * @brief Configure Low speed clock selection + * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source); +} + +/** + * @brief Get Low speed clock selection + * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR1 SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_MSIS + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR1 SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSIS + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS)); +} + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR2 HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, Prescaler); +} + +/** + * @brief Set Systick clock source + * @rmtoll CCIPR1 SYSTICKSEL LL_RCC_SetSystickClockSource + * @param SystickSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSystickClockSource(uint32_t SystickSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, SystickSource); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR2 PPRE1 LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, Prescaler); +} + +/** + * @brief Set APB2 prescaler + * @rmtoll CFGR2 PPRE2 LL_RCC_SetAPB2Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, Prescaler); +} + +/** + * @brief Set APB3 prescaler + * @rmtoll CFGR3 PPRE3 LL_RCC_SetAPB3Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB3_DIV_1 + * @arg @ref LL_RCC_APB3_DIV_2 + * @arg @ref LL_RCC_APB3_DIV_4 + * @arg @ref LL_RCC_APB3_DIV_8 + * @arg @ref LL_RCC_APB3_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, Prescaler); +} + +#if defined(RCC_CFGR2_PPRE_DPHY) +/** + * @brief Set DPHY clock prescaler + * @rmtoll CFGR2 PPRE_DPHY LL_RCC_SetDPHYPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_DPHY_DIV_1 + * @arg @ref LL_RCC_DPHY_DIV_2 + * @arg @ref LL_RCC_DPHY_DIV_4 + * @arg @ref LL_RCC_DPHY_DIV_8 + * @arg @ref LL_RCC_DPHY_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDPHYPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE_DPHY, Prescaler); +} +#endif /* RCC_CFGR2_PPRE_DPHY */ + +/** + * @brief Get AHB prescaler + * @rmtoll CFGR2 HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_HPRE)); +} + +/** + * @brief Get Sysctick clock source + * @rmtoll CCIPR1 SYSTICKSEL LL_RCC_SetSystickClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 + */ +__STATIC_INLINE uint32_t LL_RCC_GetSystickClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR2 PPRE1 LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE1)); +} + +/** + * @brief Get APB2 prescaler + * @rmtoll CFGR2 PPRE2 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE2)); +} + +/** + * @brief Get APB3 prescaler + * @rmtoll CFGR3 PPRE3 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB3_DIV_1 + * @arg @ref LL_RCC_APB3_DIV_2 + * @arg @ref LL_RCC_APB3_DIV_4 + * @arg @ref LL_RCC_APB3_DIV_8 + * @arg @ref LL_RCC_APB3_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_PPRE3)); +} + +#if defined(RCC_CFGR2_PPRE_DPHY) +/** + * @brief Get DPHY clock prescaler + * @rmtoll CFGR2 PPRE_DPHY LL_RCC_GetDPHYPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DPHY_DIV_1 + * @arg @ref LL_RCC_DPHY_DIV_2 + * @arg @ref LL_RCC_DPHY_DIV_4 + * @arg @ref LL_RCC_DPHY_DIV_8 + * @arg @ref LL_RCC_DPHY_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetDPHYPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE_DPHY)); +} +#endif /* RCC_CFGR2_PPRE_DPHY */ + +/** + * @brief Set Clock After Wake-Up From Stop mode + * @rmtoll CFGR1 STOPWUCK LL_RCC_SetClkAfterWakeFromStop + * @param Clock This parameter can be one of the following values: + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSIS + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock) +{ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, Clock); +} + +/** + * @brief Get Clock After Wake-Up From Stop mode + * @rmtoll CFGR1 STOPWUCK LL_RCC_GetClkAfterWakeFromStop + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSIS + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_STOPWUCK)); +} + +/** + * @brief Set Kernel Clock After Wake-Up From Stop mode + * @rmtoll CFGR1 STOPKERWUCK LL_RCC_SetKerClkAfterWakeFromStop + * @param Clock This parameter can be one of the following values: + * @arg @ref LL_RCC_STOP_WAKEUPKERCLOCK_MSIK + * @arg @ref LL_RCC_STOP_WAKEUPKERCLOCK_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetKerClkAfterWakeFromStop(uint32_t Clock) +{ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK, Clock); +} + +/** + * @brief Get Kernel Clock After Wake-Up From Stop mode + * @rmtoll CFGR1 STOPKERWUCK LL_RCC_GetKerClkAfterWakeFromStop + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_STOP_WAKEUPKERCLOCK_MSIK + * @arg @ref LL_RCC_STOP_WAKEUPKERCLOCK_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetKerClkAfterWakeFromStop(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR1 MCOSEL LL_RCC_ConfigMCO\n + * CFGR1 MCOPRE LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO1SOURCE_MSIS + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_HSI48 + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK + * @arg @ref LL_RCC_MCO1SOURCE_LSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_8 + * @arg @ref LL_RCC_MCO1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE, MCOxSource | MCOxPrescaler); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure USARTx clock source + * @rmtoll CCIPR1 USART1SEL LL_RCC_SetUSARTClockSource\n + * CCIPR1 USART2SEL LL_RCC_SetUSARTClockSource\n + * CCIPR1 USART3SEL LL_RCC_SetUSARTClockSource\n + * CCIPR2 USART6SEL LL_RCC_SetUSARTClockSource + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*) + * + * (*) Availability depends on devices. + + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +{ + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (USARTxSource >> 24U)); + MODIFY_REG(*reg, 3UL << ((USARTxSource & 0x001F0000U) >> 16U), ((USARTxSource & 0x000000FFU) << \ + ((USARTxSource & 0x001F0000U) >> 16U))); +} + +/** + * @brief Configure UARTx clock source + * @rmtoll CCIPR1 UART4SEL LL_RCC_SetUARTClockSource\n + * CCIPR1 UART5SEL LL_RCC_SetUARTClockSource + * @param UARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) +{ + MODIFY_REG(RCC->CCIPR1, UARTxSource >> 16U, (UARTxSource & 0x0000FFFFU)); +} + +/** + * @brief Configure LPUARTx clock source + * @rmtoll CCIPR3 LPUART1SEL LL_RCC_SetLPUARTClockSource + * @param LPUARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_MSIK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) +{ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, LPUARTxSource); +} + +/** + * @brief Configure I2Cx clock source + * @rmtoll CCIPR1 I2C1SEL LL_RCC_SetI2CClockSource\n + * CCIPR1 I2C2SEL LL_RCC_SetI2CClockSource\n + * CCIPR3 I2C3SEL LL_RCC_SetI2CClockSource\n + * CCIPR1 I2C4SEL LL_RCC_SetI2CClockSource + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_MSIK + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_MSIK + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_MSIK + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_MSIK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +{ + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2CxSource >> 24U)); + MODIFY_REG(*reg, 3UL << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((I2CxSource & 0x000000FFU) << \ + (((I2CxSource & 0x00FF0000U) >> 16U) & \ + 0x1FU))); +} + +/** + * @brief Configure SPIx clock source + * @rmtoll CCIPR1 SPI1SEL LL_RCC_SetSPIClockSource\n + * CCIPR1 SPI1SEL LL_RCC_SetSPIClockSource\n + * CCIPR1 SPI2SEL LL_RCC_SetSPIClockSource\n + * CCIPR3 SPI3SEL LL_RCC_SetSPIClockSource + * @param SPIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI1_CLKSOURCE_MSIK + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SPI2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI2_CLKSOURCE_MSIK + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_SPI3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI3_CLKSOURCE_MSIK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t SPIxSource) +{ + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIxSource >> 24U)); + MODIFY_REG(*reg, 3UL << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((SPIxSource & 0x000000FFU) << \ + (((SPIxSource & 0x00FF0000U) >> 16U) & \ + 0x1FU))); +} + +/** + * @brief Configure LPTIMx clock source + * @rmtoll CCIPR1 LPTIM2SEL LL_RCC_SetLPTIMClockSource\n + * CCIPR3 LPTIM2SEL LL_RCC_SetLPTIMClockSource\n + * CCIPR3 LPTIM34SEL LL_RCC_SetLPTIMClockSource + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_MSIK + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_MSIK + * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) +{ + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMxSource >> 24U)); + MODIFY_REG(*reg, 3UL << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((LPTIMxSource & 0x000000FFU) << \ + (((LPTIMxSource & 0x00FF0000U) >> 16U) & \ + 0x1FU))); +} + +/** + * @brief Configure FDCAN kernel clock source + * @rmtoll CCIPR1 FDCANSEL LL_RCC_SetFDCANClockSource + * @param FDCANxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1 + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL, FDCANxSource); +} + +/** + * @brief Configure SAIx clock source + * @rmtoll CCIPR2 SAI1SEL LL_RCC_SetSAIClockSource\n + * CCIPR2 SAI2SEL LL_RCC_SetSAIClockSource + * @param SAIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1 + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2 + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3 + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1 (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2 (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3 (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI (*) + * + * (*) Availability depends on devices. + * + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) +{ + MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU)); +} + +/** + * @brief Configure SDMMC1/2 kernel clock source + * @rmtoll CCIPR2 SDMMCSEL LL_RCC_SetSDMMCKernelClockSource + * @param SDMMCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC12_KERNELCLKSOURCE_48CLK + * @arg @ref LL_RCC_SDMMC12_KERNELCLKSOURCE_PLL1 "P" + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource); +} + +/** + * @brief Configure SDMMC1/2 clock source + * @rmtoll CCIPR1 ICLKSEL LL_RCC_SetSDMMCClockSource + * @param SDMMCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL1 + * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL2 + * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_MSIK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL, SDMMCxSource); +} + +/** + * @brief Configure RNG clock source + * @rmtoll CCIPR2 RNGSEL LL_RCC_SetRNGClockSource + * @param RNGxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48_DIV2 + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_RNGSEL, RNGxSource); +} + +#if defined(RCC_CCIPR2_USBPHYCSEL) +/** + * @brief Configure USBPHY clock source + * @rmtoll CCIPR2 USBPHYCSEL LL_RCC_SetUSBPHYClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_USBPHYCLKSOURCE_HSE + * @arg @ref LL_RCC_USBPHYCLKSOURCE_HSE_DIV2 + * @arg @ref LL_RCC_USBPHYCLKSOURCE_PLL1 + * @arg @ref LL_RCC_USBPHYCLKSOURCE_PLL1_DIV2 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBPHYClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBPHYCSEL, Source); +} +#endif /* RCC_CCIPR2_USBPHYCSEL */ + +/** + * @brief Configure USB clock source + * @rmtoll CCIPR1 ICLKSEL LL_RCC_SetUSBClockSource + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1 + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL2 + * @arg @ref LL_RCC_USB_CLKSOURCE_MSIK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL, USBxSource); +} + +/** + * @brief Configure ADC clock source + * @rmtoll CCIPR3 ADCDACSEL LL_RCC_SetADCDACClockSource + * @param ADCxDAC1Source This parameter can be one of the following values: + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PLL2 + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSE + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSI + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_MSIK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADCDACClockSource(uint32_t ADCxDAC1Source) +{ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADCDACSEL, ADCxDAC1Source); +} + +/** + * @brief Configure DAC1 clock source + * @rmtoll CCIPR3 DAC1SEL LL_RCC_SetDAC1ClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DAC1_CLKSOURCE_LSE + * @arg @ref LL_RCC_DAC1_CLKSOURCE_LSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDAC1ClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_DAC1SEL, Source); +} + +/** + * @brief Configure ADF1 clock source + * @rmtoll CCIPR3 ADF1SEL LL_RCC_SetADF1ClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_ADF1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL1 + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL3 + * @arg @ref LL_RCC_ADF1_CLKSOURCE_MSIK + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PIN + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADF1ClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADF1SEL, Source); +} + +/** + * @brief Configure MDF1 clock source + * @rmtoll CCIPR3 MDF1SEL LL_RCC_SetMDF1ClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_MDF1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL1 + * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL3 + * @arg @ref LL_RCC_MDF1_CLKSOURCE_MSIK + * @arg @ref LL_RCC_MDF1_CLKSOURCE_PIN + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetMDF1ClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_MDF1SEL, Source); +} + +/** + * @brief Configure OCTOSPI kernel clock source + * @rmtoll CCIPR2 OSPISEL LL_RCC_SetOCTOSPIClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSIK + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL1 + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL2 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OCTOSPISEL, Source); +} + +#if defined (HSPI1) +/** + * @brief Configure HSPI kernel clock source + * @rmtoll CCIPR2 HSPISEL LL_RCC_SetHSPIClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_HSPI_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL1 + * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL2 + * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL3 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetHSPIClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_HSPISEL, Source); +} +#endif /* HSPI1 */ + +#if defined(SAES) +/** + * @brief Configure SAES clock source + * @rmtoll CCIPR2 SAESSEL LL_RCC_SetSAESClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SAES_CLKSOURCE_SHSI + * @arg @ref LL_RCC_SAES_CLKSOURCE_SHSI_DIV2 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSAESClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAESSEL, Source); +} +#endif /* SAES */ + +#if defined(DSI) +/** + * @brief Configure DSIx clock source + * @rmtoll CCIPR2 DSISEL LL_RCC_SetDSIClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL3 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSIHOSTSEL, Source); +} +#endif /* DSI */ + +#if defined(LTDC) +/** + * @brief Configure LTDCx clock source + * @rmtoll CCIPR2 LTDCSEL LL_RCC_SetLTDCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL2 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL3 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LTDCSEL, Source); +} +#endif /* LTDC */ +/** + * @brief Get USARTx clock source + * @rmtoll CCIPR1 USART1SEL LL_RCC_GetUSARTClockSource\n + * CCIPR1 USART2SEL LL_RCC_GetUSARTClockSource\n + * CCIPR1 USART3SEL LL_RCC_GetUSARTClockSource\n + * CCIPR2 USART6SEL LL_RCC_GetUSARTClockSource + * @param USARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE + * @arg @ref LL_RCC_USART6_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*) + * + * (*) Availability depends on devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +{ + __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (USARTx >> 24U)); + return (uint32_t)((READ_BIT(*reg, 3UL << ((USARTx & 0x001F0000U) >> 16U)) >> \ + ((USARTx & 0x001F0000U) >> 16U)) | (USARTx & 0xFFFF0000U)); +} + +/** + * @brief Get UARTx clock source + * @rmtoll CCIPR1 UART4SEL LL_RCC_GetUARTClockSource\n + * CCIPR1 UART5SEL LL_RCC_GetUARTClockSource + * @param UARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE + * @arg @ref LL_RCC_UART5_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR1, UARTx) | (UARTx << 16U)); +} + +/** + * @brief Get LPUARTx clock source + * @rmtoll CCIPR1 LPUART1SEL LL_RCC_GetLPUARTClockSource + * @param LPUARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR3, LPUARTx)); +} + +/** + * @brief Get I2Cx clock source + * @rmtoll CCIPR1 I2C1SEL LL_RCC_GetI2CClockSource\n + * CCIPR1 I2C2SEL LL_RCC_GetI2CClockSource\n + * CCIPR3 I2C3SEL LL_RCC_GetI2CClockSource\n + * CCIPR1 I2C4SEL LL_RCC_GetI2CClockSource + * @param I2Cx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @arg @ref LL_RCC_I2C2_CLKSOURCE + * @arg @ref LL_RCC_I2C3_CLKSOURCE + * @arg @ref LL_RCC_I2C4_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +{ + __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2Cx >> 24U)); + return (uint32_t)((READ_BIT(*reg, (3UL << (((I2Cx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> \ + (((I2Cx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (I2Cx & 0xFFFF0000UL)); +} + +/** + * @brief Get SPIx clock source + * @rmtoll CCIPR1 SPI1SEL LL_RCC_GetSPIClockSource\n + * CCIPR1 SPI2SEL LL_RCC_GetSPIClockSource\n + * CCIPR3 SPI3SEL LL_RCC_GetSPIClockSource + * @param SPIx This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI1_CLKSOURCE + * @arg @ref LL_RCC_SPI2_CLKSOURCE + * @arg @ref LL_RCC_SPI3_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI1_CLKSOURCE_MSIK + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SPI2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI2_CLKSOURCE_MSIK + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_SPI3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI3_CLKSOURCE_MSIK + */ +__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t SPIx) +{ + __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIx >> 24U)); + return (uint32_t)((READ_BIT(*reg, (3UL << (((SPIx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> \ + (((SPIx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (SPIx & 0xFFFF0000UL)); +} + +/** + * @brief Get LPTIMx clock source + * @rmtoll CCIPR1 LPTIM2SEL LL_RCC_GetLPTIMClockSource\n + * CCIPR3 LPTIM2SEL LL_RCC_GetLPTIMClockSource\n + * CCIPR3 LPTIM34SEL LL_RCC_GetLPTIMClockSource + * @param LPTIMx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE + * @arg @ref LL_RCC_LPTIM34_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_MSIK + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_MSIK + * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) +{ + __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMx >> 24U)); + return (uint32_t)((READ_BIT(*reg, (3UL << (((LPTIMx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> \ + (((LPTIMx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (LPTIMx & 0xFFFF0000UL)); +} + +/** + * @brief Set Tim Input capture clock source + * @rmtoll CCIPR1 TIMICSEL LL_RCC_SetTIMICClockSource + * @param TIMICSource This parameter can be one of the following combined values: + * @arg @ref LL_RCC_TIMIC_CLKSOURCE_NONE + * @arg @ref LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256 + * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024 + * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4 + * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV4 + * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV1024 + * @note HSI, MSI and MSIK clocks without division are also available when TIMICSEL[2] is 1. + * @note combination to be avoided : + * LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024 and LL_RCC_CLKSOURCE_TIMIC_MSIK_DIV1024 + * LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4 and LL_RCC_CLKSOURCE_TIMIC_MSIK_DIV4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetTIMICClockSource(uint32_t TIMICSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL, TIMICSource); +} + +/** + * @brief Get Tim Input capture clock source + * @rmtoll CCIPR1 TIMICSEL LL_RCC_GetTIMICClockSource + * @retval Returned value can be one of the following combined values: + * @arg @ref LL_RCC_TIMIC_CLKSOURCE_NONE + * @arg @ref LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256 + * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024 + * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4 + * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV4 + * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV1024 + */ +__STATIC_INLINE uint32_t LL_RCC_GetTIMICClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL)); +} + +/** + * @brief Get FDCAN kernel clock source + * @rmtoll CCIPR1 FDCANSEL LL_RCC_GetFDCANClockSource + * @param FDCANx This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1 + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2 + */ +__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR1, FDCANx)); +} + +/** + * @brief Get SAIx clock source + * @rmtoll CCIPR2 SAI1SEL LL_RCC_GetSAIClockSource\n + * CCIPR2 SAI2SEL LL_RCC_GetSAIClockSource + * @param SAIx This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE + * @arg @ref LL_RCC_SAI2_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1 + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2 + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3 + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1 (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2 (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3 (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI (*) + * + * (*) Availability depends on devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U)); +} + +/** + * @brief Get SDMMCx kernel clock source + * @rmtoll CCIPR2 SDMMCSEL LL_RCC_GetSDMMCKernelClockSource + * @param SDMMCx This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC_KERNELCLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SDMMC12_KERNELCLKSOURCE_48CLK + * @arg @ref LL_RCC_SDMMC12_KERNELCLKSOURCE_PLL1 "P" + */ +__STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx)); +} + +/** + * @brief Get SDMMC1/2 clock source + * @rmtoll CCIPR1 ICLKSEL LL_RCC_GetSDMMCClockSource + * @param SDMMCx This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL1 + * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL2 + * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_MSIK + */ +__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR1, SDMMCx)); +} + +/** + * @brief Get RNGx clock source + * @rmtoll CCIPR2 RNGSEL LL_RCC_GetRNGClockSource + * @param RNGx This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48_DIV2 + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, RNGx)); +} + +#if defined(RCC_CCIPR2_USBPHYCSEL) +/** + * @brief Get USBPHYx clock source + * @rmtoll CCIPR2 USBPHYCSEL LL_RCC_GetUSBPHYClockSource + * @param USBPHYx This parameter can be one of the following values: + * @arg @ref LL_RCC_USBPHY_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USBPHYCLKSOURCE_HSE + * @arg @ref LL_RCC_USBPHYCLKSOURCE_HSE_DIV2 + * @arg @ref LL_RCC_USBPHYCLKSOURCE_PLL1 + * @arg @ref LL_RCC_USBPHYCLKSOURCE_PLL1_DIV2 + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBPHYClockSource(uint32_t USBPHYx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, USBPHYx)); +} +#endif /* RCC_CCIPR2_USBPHYCSEL */ + +/** + * @brief Get USBx clock source + * @rmtoll CCIPR1 ICLKSEL LL_RCC_GetUSBClockSource + * @param USBx This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1 + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL2 + * @arg @ref LL_RCC_USB_CLKSOURCE_MSIK + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR1, USBx)); +} + +/** + * @brief Get ADCx clock source + * @rmtoll CCIPR3 ADCDACSEL LL_RCC_SetADCDACClockSource + * @param ADCxDAC1 This parameter can be one of the following values: + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PLL2 + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_MSIK + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCDACClockSource(uint32_t ADCxDAC1) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR3, ADCxDAC1)); +} + +/** + * @brief Get DFSDM Audio Clock Source + * @rmtoll CCIPR3 ADF1SEL LL_RCC_GetADF1ClockSource + * @param ADF1x This parameter can be one of the following values: + * @arg @ref LL_RCC_ADF1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADF1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL1 + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL3 + * @arg @ref LL_RCC_ADF1_CLKSOURCE_MSIK + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PIN + */ +__STATIC_INLINE uint32_t LL_RCC_GetADF1ClockSource(uint32_t ADF1x) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR3, ADF1x)); +} + +/** + * @brief Get DAC1 Clock Source + * @rmtoll CCIPR3 DAC1SEL LL_RCC_GetDAC1ClockSource + * @param DAC1x This parameter can be one of the following values: + * @arg @ref LL_RCC_DAC1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DAC1_CLKSOURCE_LSE + * @arg @ref LL_RCC_DAC1_CLKSOURCE_LSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetDAC1ClockSource(uint32_t DAC1x) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR3, DAC1x)); +} + +/** + * @brief Get MDF1 Clock Source + * @rmtoll CCIPR2 MDF1SEL LL_RCC_GetMDF1ClockSource + * @param MDF1x This parameter can be one of the following values: + * @arg @ref LL_RCC_MDF1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_MDF1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL1 + * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL3 + * @arg @ref LL_RCC_MDF1_CLKSOURCE_MSIK + * @arg @ref LL_RCC_MDF1_CLKSOURCE_PIN + */ +__STATIC_INLINE uint32_t LL_RCC_GetMDF1ClockSource(uint32_t MDF1x) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, MDF1x)); +} + +/** + * @brief Get OCTOSPI clock source + * @rmtoll CCIPR2 OSPISEL LL_RCC_GetOCTOSPIClockSource + * @param OCTOSPIx This parameter can be one of the following values: + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSIK + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL1 + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL2 + */ +__STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx)); +} + +#if defined (HSPI1) +/** + * @brief Get HSPI clock source + * @rmtoll CCIPR2 HSPISEL LL_RCC_GetHSPIClockSource + * @param HSPIx This parameter can be one of the following values: + * @arg @ref LL_RCC_HSPI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_HSPI_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL1 + * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL2 + * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL3 + */ +__STATIC_INLINE uint32_t LL_RCC_GetHSPIClockSource(uint32_t HSPIx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, HSPIx)); +} +#endif /* HSPI1 */ +/** + * @} + */ + +#if defined(SAES) +/** + * @brief Get SAES kernel clock source + * @rmtoll CCIPR2 SAESSEL LL_RCC_GetSAESClockSource + * @param SAESx This parameter can be one of the following values: + * @arg @ref LL_RCC_SAES_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SAES_CLKSOURCE_SHSI + * @arg @ref LL_RCC_SAES_CLKSOURCE_SHSI_DIV2 + */ +__STATIC_INLINE uint32_t LL_RCC_GetSAESClockSource(uint32_t SAESx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, SAESx)); +} +#endif /* SAES */ + +#if defined(DSI) +/** + * @brief Get DSI clock source + * @rmtoll CCIPR2 DSISEL LL_RCC_GetDSIClockSource + * @param DSIx This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL3 + */ +__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, DSIx)); +} +#endif /* DSI */ + +#if defined(LTDC) +/** + * @brief Get LTDC clock source + * @rmtoll CCIPR2 LTDCSEL LL_RCC_GetLTDCClockSource + * @param LTDCx This parameter can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL2 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL3 + */ +__STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, LTDCx)); +} +#endif /* LTDC */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed anymore unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == RCC_BDCR_RTCEN) ? 1UL : 0UL); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @} + */ + + +/** @defgroup RCC_LL_EF_PLL1 PLL1 + * @{ + */ + +/** + * @brief Enable PLL1 + * @rmtoll CR PLL1ON LL_RCC_PLL1_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL1ON); +} +#define LL_RCC_PLL_Enable LL_RCC_PLL1_Enable /*!< alias for compatibility with legacy code */ + +/** + * @brief Disable PLL1 + * @note Cannot be disabled if the PLL1 clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL1_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); +} +#define LL_RCC_PLL_Disable LL_RCC_PLL1_Disable /*!< alias for compatibility with legacy code */ + +/** + * @brief Check if PLL1 Ready + * @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == RCC_CR_PLL1RDY) ? 1UL : 0UL); +} +#define LL_RCC_PLL_IsReady LL_RCC_PLL1_IsReady /*!< alias for compatibility with legacy code */ + +/** + * @brief Configure PLL1 used for SYSCLK Domain + * @note PLL1 Source, PLLM, PLLN and PLLR can be written only when PLL1 is disabled. + * @note PLLN/PLLR can be written only when PLL is disabled. + * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_SYS\n + * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_SYS\n + * PLL1CFGR PLL1N LL_RCC_PLL1_ConfigDomain_SYS\n + * PLL1CFGR PLL1R LL_RCC_PLL1_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL1SOURCE_NONE + * @arg @ref LL_RCC_PLL1SOURCE_MSIS + * @arg @ref LL_RCC_PLL1SOURCE_HSI + * @arg @ref LL_RCC_PLL1SOURCE_HSE + * @param PLLM parameter can be a value between 1 and 16 + * @param PLLR parameter can be a value between 1 and 128 (Only division by 1 and even division are allowed) + * @param PLLN parameter can be a value between 4 and 512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \ + ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos)); + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1R, ((PLLN - 1UL) << \ + RCC_PLL1DIVR_PLL1N_Pos) | ((PLLR - 1UL) << \ + RCC_PLL1DIVR_PLL1R_Pos)); +} +#define LL_RCC_PLL_ConfigDomain_SYS LL_RCC_PLL1_ConfigDomain_SYS /*!< alias for compatibility with legacy code */ + +/** + * @brief Configure PLL1 used for SAI domain clock + * @note PLL1 Source, PLLM, PLLN and PLLPDIV can be written only when PLL1 is disabled. + * @note This can be selected for SAI1 or SAI2 + * @rmtoll PLLC1FGR PLL1SRC LL_RCC_PLL1_ConfigDomain_SAI\n + * PLLC1FGR PLL1M LL_RCC_PLL1_ConfigDomain_SAI\n + * PLLC1FGR PLL1N LL_RCC_PLL1_ConfigDomain_SAI\n + * PLLC1FGR PLL1P LL_RCC_PLL1_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL1SOURCE_NONE + * @arg @ref LL_RCC_PLL1SOURCE_MSIS + * @arg @ref LL_RCC_PLL1SOURCE_HSI + * @arg @ref LL_RCC_PLL1SOURCE_HSE + * @param PLLM parameter can be a value between 1 and 16 + * @param PLLN parameter can be a value between 4 and 512 + * @param PLLP parameter can be a value between 1 and 128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \ + ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos)); + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1P, ((PLLN - 1UL) << \ + RCC_PLL1DIVR_PLL1N_Pos) | ((PLLP - 1UL) << \ + RCC_PLL1DIVR_PLL1P_Pos)); +} +#define LL_RCC_PLL_ConfigDomain_SAI LL_RCC_PLL1_ConfigDomain_SAI /*!< alias for compatibility with legacy code */ + +/** + * @brief Configure PLL1 used for 48Mhz domain clock + * @note PLL1 Source, PLLM, PLLN and PLLQ can be written only when PLL1 is disabled. + * @note This can be selected for USB, SDMMC + * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_48M\n + * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_48M\n + * PLL1CFGR PLL1N LL_RCC_PLL1_ConfigDomain_48M\n + * PLL1CFGR PLL1Q LL_RCC_PLL1_ConfigDomain_48M + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL1SOURCE_NONE + * @arg @ref LL_RCC_PLL1SOURCE_MSIS + * @arg @ref LL_RCC_PLL1SOURCE_HSI + * @arg @ref LL_RCC_PLL1SOURCE_HSE + * @param PLLM parameter can be a value between 1 and 16 + * @param PLLN parameter can be a value between 4 and 512 + * @param PLLQ parameter can be a value between 1 and 128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \ + ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos)); + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1Q, ((PLLN - 1UL) << \ + RCC_PLL1DIVR_PLL1N_Pos) | ((PLLQ - 1UL) << \ + RCC_PLL1DIVR_PLL1Q_Pos)); +} +#define LL_RCC_PLL_ConfigDomain_48M LL_RCC_PLL1_ConfigDomain_48M /*!< alias for compatibility with legacy code */ + +/** + * @brief Configure PLL clock source + * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_SetMainSource + * @param PLL1Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL1SOURCE_NONE + * @arg @ref LL_RCC_PLL1SOURCE_MSIS + * @arg @ref LL_RCC_PLL1SOURCE_HSI + * @arg @ref LL_RCC_PLL1SOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_SetMainSource(uint32_t PLL1Source) +{ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, PLL1Source); +} +#define LL_RCC_PLL_SetMainSource LL_RCC_PLL1_SetMainSource /*!< alias for compatibility with legacy code */ + +/** + * @brief Get the oscillator used as PLL1 clock source. + * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL1SOURCE_NONE + * @arg @ref LL_RCC_PLL1SOURCE_MSIS + * @arg @ref LL_RCC_PLL1SOURCE_HSI + * @arg @ref LL_RCC_PLL1SOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC)); +} +#define LL_RCC_PLL_GetMainSource LL_RCC_PLL1_GetMainSource /*!< alias for compatibility with legacy code */ + +/** + * @brief Set Main PLL1 multiplication factor for VCO + * @rmtoll PLL1CFGR PLL1N LL_RCC_PLL1_SetN + * @param PLL1N parameter can be a value between 4 and 512 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t PLL1N) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N, (PLL1N - 1UL) << RCC_PLL1DIVR_PLL1N_Pos); +} +#define LL_RCC_PLL_SetN LL_RCC_PLL1_SetN /*!< alias for compatibility with legacy code */ + +/** + * @brief Get Main PLL1 multiplication factor for VCO + * @rmtoll PLL1CFGR PLL1N LL_RCC_PLL1_GetN + * @retval Between 4 and 512 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1UL); +} +#define LL_RCC_PLL_GetN LL_RCC_PLL1_GetN /*!< alias for compatibility with legacy code */ + +/** + * @brief Set Main PLL1 division factor for PLL1P + * @note Used for SAI1 and SAI2 clock + * @rmtoll PLL1CFGR PLL1P LL_RCC_PLL1_SetP + * @param PLL1P parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t PLL1P) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P, (PLL1P - 1UL) << RCC_PLL1DIVR_PLL1P_Pos); +} +#define LL_RCC_PLL_SetP LL_RCC_PLL1_SetP /*!< alias for compatibility with legacy code */ + +/** + * @brief Get Main PLL1 division factor for PLL1P + * @note Used for SAI1 and SAI2 clock + * @rmtoll PLL1CFGR PLL1P LL_RCC_PLL1_GetP + * @retval Between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1UL); +} +#define LL_RCC_PLL_GetP LL_RCC_PLL1_GetP /*!< alias for compatibility with legacy code */ + +/** + * @brief Set Main PLL division factor for PLLQ + * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock) + * @rmtoll PLLCFGR PLL1Q LL_RCC_PLL1_SetQ + * @param PLL1Q parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t PLL1Q) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q, (PLL1Q - 1UL) << RCC_PLL1DIVR_PLL1Q_Pos); +} +#define LL_RCC_PLL_SetQ LL_RCC_PLL1_SetQ /*!< alias for compatibility with legacy code */ + +/** + * @brief Get Main PLL division factor for PLLQ + * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock) + * @rmtoll PLL1CFGR PLL1Q LL_RCC_PLL1_GetQ + * @retval Between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1UL); +} +#define LL_RCC_PLL_GetQ LL_RCC_PLL1_GetQ /*!< alias for compatibility with legacy code */ + +/** + * @brief Set Main PLL division factor for PLL1R + * @note Used for PLL1CLK selected for USB, SDMMC (48 MHz clock) + * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_SetR + * @param PLL1R parameter can be a value between 1 and 128 (Only division by 1 and even division are allowed) + */ +__STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t PLL1R) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R, (PLL1R - 1UL) << RCC_PLL1DIVR_PLL1R_Pos); +} +#define LL_RCC_PLL_SetR LL_RCC_PLL1_SetR /*!< alias for compatibility with legacy code */ + +/** + * @brief Get Main PLL1 division factor for PLL1R + * @note Used for PLL1CLK (system clock) + * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_GetR + * @retval Between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1UL); +} +#define LL_RCC_PLL_GetR LL_RCC_PLL1_GetR /*!< alias for compatibility with legacy code */ + +/** + * @brief Set Division factor for the main PLL and other PLL + * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_SetDivider + * @param PLL1M parameter can be a value between 1 and 16 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetDivider(uint32_t PLL1M) +{ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (PLL1M - 1UL) << RCC_PLL1CFGR_PLL1M_Pos); +} +#define LL_RCC_PLL_SetDivider LL_RCC_PLL1_SetDivider /*!< alias for compatibility with legacy code */ + +/** + * @brief Get Division factor for the main PLL and other PLL + * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_GetDivider + * @retval Between 1 and 16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetDivider(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1UL); +} +#define LL_RCC_PLL_GetDivider LL_RCC_PLL1_GetDivider /*!< alias for compatibility with legacy code */ + +/** + * @brief Enable PLL1 output mapped on SAI domain clock + * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_EnableDomain_SAI + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_EnableDomain_SAI(void) +{ + SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN); +} +#define LL_RCC_PLL_EnableDomain_SAI LL_RCC_PLL1_EnableDomain_SAI /*!< alias for compatibility with legacy code */ + +/** + * @brief Disable PLL1 output mapped on SAI domain clock + * @note Cannot be disabled if the PLL1 clock is used as the system + * clock + * @note In order to save power, when the PLL1CLK of the PLL1 is + * not used, should be 0 + * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_DisableDomain_SAI + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_DisableDomain_SAI(void) +{ + CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN); +} +#define LL_RCC_PLL_DisableDomain_SAI LL_RCC_PLL1_DisableDomain_SAI /*!< alias for compatibility with legacy code */ + +/** + * @brief Check if PLL1 output mapped on SAI domain clock is enabled + * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_IsEnabledDomain_SAI + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_SAI(void) +{ + return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN) == (RCC_PLL1CFGR_PLL1PEN)) ? 1UL : 0UL); +} +#define LL_RCC_PLL_IsEnabledDomain_SAI LL_RCC_PLL1_IsEnabledDomain_SAI /*!< alias for compatibility with legacy code */ + +/** + * @brief Enable PLL output mapped on 48MHz domain clock + * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_EnableDomain_48M + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_EnableDomain_48M(void) +{ + SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN); +} + +/** + * @brief Disable PLL1 output mapped on 48MHz domain clock + * @note Cannot be disabled if the PLL clock is used as the system + * clock + * @note In order to save power, when the PLL1CLK of the PLL1 is + * not used, should be 0 + * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_DisableDomain_48M + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_DisableDomain_48M(void) +{ + CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN); +} +#define LL_RCC_PLL_DisableDomain_48M LL_RCC_PLL1_DisableDomain_48M /*!< alias for compatibility with legacy code */ + +/** + * @brief Check if PLL1 output mapped on 48M domain clock is enabled + * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_IsEnabledDomain_48M + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_48M(void) +{ + return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN) == (RCC_PLL1CFGR_PLL1QEN)) ? 1UL : 0UL); +} +#define LL_RCC_PLL_IsEnabledDomain_48M LL_RCC_PLL1_IsEnabledDomain_48M /*!< alias for compatibility with legacy code */ + +/** + * @brief Enable PLL1 output mapped on SYSCLK domain + * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_EnableDomain_SYS + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_EnableDomain_SYS(void) +{ + SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); +} +#define LL_RCC_PLL_EnableDomain_SYS LL_RCC_PLL1_EnableDomain_SYS /*!< alias for compatibility with legacy code */ + +/** + * @brief Disable PLL1 output mapped on SYSCLK domain + * @note Cannot be disabled if the PLL1 clock is used as the system + * clock + * @note In order to save power, when the PLL1CLK of the PLL1 is + * not used, Main PLL1 should be 0 + * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_DisableDomain_SYS + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_DisableDomain_SYS(void) +{ + CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); +} +#define LL_RCC_PLL_DisableDomain_SYS LL_RCC_PLL1_DisableDomain_SYS /*!< alias for compatibility with legacy code */ + +/** + * @brief Check if PLL1 output mapped on SYS domain clock is enabled + * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_IsEnabledDomain_SYS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_SYS(void) +{ + return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN) == (RCC_PLL1CFGR_PLL1REN)) ? 1UL : 0UL); +} +#define LL_RCC_PLL_IsEnabledDomain_SYS LL_RCC_PLL1_IsEnabledDomain_SYS /*!< alias for compatibility with legacy code */ + +/** + * @brief Enable PLL1 FRACN + * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void) +{ + SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN); +} +#define LL_RCC_PLLFRACN_Enable LL_RCC_PLL1FRACN_Enable /*!< alias for compatibility with legacy code */ + +/** + * @brief Check if PLL1 FRACN is enabled + * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) == RCC_PLL1CFGR_PLL1FRACEN) ? 1UL : 0UL); +} +#define LL_RCC_PLLFRACN_IsEnabled LL_RCC_PLL1FRACN_IsEnabled /*!< alias for compatibility with legacy code */ + +/** + * @brief Disable PLL1 FRACN + * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void) +{ + CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN); +} +#define LL_RCC_PLLFRACN_Disable LL_RCC_PLL1FRACN_Disable /*!< alias for compatibility with legacy code */ + +/** + * @brief Set PLL1 FRACN Coefficient + * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_SetFRACN + * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN, FRACN << RCC_PLL1FRACR_PLL1FRACN_Pos); +} +#define LL_RCC_PLL_SetFRACN LL_RCC_PLL1_SetFRACN /*!< alias for compatibility with legacy code */ + +/** + * @brief Get PLL1 FRACN Coefficient + * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_GetFRACN + * @retval A value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos); +} +#define LL_RCC_PLL_GetFRACN LL_RCC_PLL1_GetFRACN /*!< alias for compatibility with legacy code */ + +/** + * @brief Set PLL1 VCO Input Range + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange + * @param InputRange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange) +{ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, InputRange); +} +#define LL_RCC_PLL_SetVCOInputRange LL_RCC_PLL1_SetVCOInputRange /*!< alias for compatibility with legacy code */ + +/** + * @brief Set PLL1 EPOD Prescaler booster input clock + * @rmtoll PLL1CFGR PLL1MBOOST LL_RCC_SetPll1EPodPrescaler + * @param BoostDiv This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL1MBOOST_DIV_1 + * @arg @ref LL_RCC_PLL1MBOOST_DIV_2 + * @arg @ref LL_RCC_PLL1MBOOST_DIV_4 + * @arg @ref LL_RCC_PLL1MBOOST_DIV_6 + * @arg @ref LL_RCC_PLL1MBOOST_DIV_8 + * @arg @ref LL_RCC_PLL1MBOOST_DIV_10 + * @arg @ref LL_RCC_PLL1MBOOST_DIV_12 + * @arg @ref LL_RCC_PLL1MBOOST_DIV_14 + * @arg @ref LL_RCC_PLL1MBOOST_DIV_16 + */ +__STATIC_INLINE void LL_RCC_SetPll1EPodPrescaler(uint32_t BoostDiv) +{ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1MBOOST, BoostDiv); +} + +/** + * @brief Get PLL1 EPOD Prescaler booster input clock + * @rmtoll PLL1CFGR PLL1MBOOST LL_RCC_GetPll1EPodPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL1MBOOST_DIV_1 + * @arg @ref LL_RCC_PLL1MBOOST_DIV_2 + * @arg @ref LL_RCC_PLL1MBOOST_DIV_4 + * @arg @ref LL_RCC_PLL1MBOOST_DIV_6 + * @arg @ref LL_RCC_PLL1MBOOST_DIV_8 + * @arg @ref LL_RCC_PLL1MBOOST_DIV_10 + * @arg @ref LL_RCC_PLL1MBOOST_DIV_12 + * @arg @ref LL_RCC_PLL1MBOOST_DIV_14 + * @arg @ref LL_RCC_PLL1MBOOST_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetPll1EPodPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1MBOOST)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLL2 PLL2 + * @{ + */ + +/** + * @brief Enable PLL2 + * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL2ON); +} + +/** + * @brief Disable PLL2 + * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); +} + +/** + * @brief Check if PLL2 Ready + * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == RCC_CR_PLL2RDY) ? 1UL : 0UL); +} + +/** + * @brief Configure PLL2 used for 48Mhz domain clock + * @note PLL2 Source, PLLM, PLLN and PLLQ can be written only when PLL2 is disabled. + * @note This can be selected for USB, SDMMC + * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_ConfigDomain_48M\n + * PLL2CFGR PLL2M LL_RCC_PLL2_ConfigDomain_48M\n + * PLL2CFGR PLL2N LL_RCC_PLL2_ConfigDomain_48M\n + * PLL2CFGR PLL2Q LL_RCC_PLL2_ConfigDomain_48M + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL2SOURCE_NONE + * @arg @ref LL_RCC_PLL2SOURCE_MSIS + * @arg @ref LL_RCC_PLL2SOURCE_HSI + * @arg @ref LL_RCC_PLL2SOURCE_HSE + * @param PLLM parameter can be a value between 1 and 16 + * @param PLLN parameter can be a value between 4 and 512 + * @param PLLQ parameter can be a value between 1 and 128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M, Source | \ + ((PLLM - 1UL) << RCC_PLL2CFGR_PLL2M_Pos)); + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N | RCC_PLL2DIVR_PLL2Q, ((PLLN - 1UL) << \ + RCC_PLL2DIVR_PLL2N_Pos) | ((PLLQ - 1UL) << \ + RCC_PLL2DIVR_PLL2Q_Pos)); +} + +/** + * @brief Configure PLL2 used for SAI domain clock + * @note PLL1 Source, PLLM, PLLN and PLL2P can be written only when PLL1 is disabled. + * @note This can be selected for SAI1 or SAI2 + * @rmtoll PLLC2FGR PLL2SRC LL_RCC_PLL2_ConfigDomain_SAI\n + * PLLC2FGR PLL2M LL_RCC_PLL2_ConfigDomain_SAI\n + * PLLC2FGR PLL2N LL_RCC_PLL2_ConfigDomain_SAI\n + * PLLC2FGR PLL2P LL_RCC_PLL2_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL2SOURCE_NONE + * @arg @ref LL_RCC_PLL2SOURCE_MSIS + * @arg @ref LL_RCC_PLL2SOURCE_HSI + * @arg @ref LL_RCC_PLL2SOURCE_HSE + * @param PLLM parameter can be a value between 1 and 16 + * @param PLLN parameter can be a value between 4 and 512 + * @param PLLP parameter can be a value between 1 and 128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M, Source | \ + ((PLLM - 1UL) << RCC_PLL2CFGR_PLL2M_Pos)); + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N | RCC_PLL2DIVR_PLL2P, ((PLLN - 1UL) << \ + RCC_PLL2DIVR_PLL2N_Pos) | ((PLLP - 1UL) << \ + RCC_PLL2DIVR_PLL2P_Pos)); +} + +/** + * @brief Configure PLL2 used for ADC domain clock + * @note PLL2SRC/PLL2M/PLL2N/PLL2R can be written only when PLL2 is disabled. + * @note This can be selected for ADC + * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_ConfigDomain_ADC\n + * PLL2CFGR PLL2M LL_RCC_PLL2_ConfigDomain_ADC\n + * PLL2CFGR PLL2N LL_RCC_PLL2_ConfigDomain_ADC\n + * PLL2CFGR PLL2R LL_RCC_PLL2_ConfigDomain_ADC + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL2SOURCE_NONE + * @arg @ref LL_RCC_PLL2SOURCE_MSIS + * @arg @ref LL_RCC_PLL2SOURCE_HSI + * @arg @ref LL_RCC_PLL2SOURCE_HSE + * @param PLLM parameter can be a value between 1 and 16 + * @param PLLR parameter can be a value between 1 and 128 + * @param PLLN parameter can be a value between 4 and 512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M, Source | \ + ((PLLM - 1UL) << RCC_PLL2CFGR_PLL2M_Pos)); + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N | RCC_PLL2DIVR_PLL2R, ((PLLN - 1UL) << \ + RCC_PLL2DIVR_PLL2N_Pos) | ((PLLR - 1UL) << \ + RCC_PLL2DIVR_PLL2R_Pos)); +} + +/** + * @brief Configure PLL2 clock source + * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_SetSource + * @param PLL2Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL2SOURCE_NONE + * @arg @ref LL_RCC_PLL2SOURCE_MSIS + * @arg @ref LL_RCC_PLL2SOURCE_HSI + * @arg @ref LL_RCC_PLL2SOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_SetSource(uint32_t PLL2Source) +{ + MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC, PLL2Source); +} + +/** + * @brief Get the oscillator used as PLL2 clock source. + * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL2SOURCE_NONE + * @arg @ref LL_RCC_PLL2SOURCE_MSIS + * @arg @ref LL_RCC_PLL2SOURCE_HSI + * @arg @ref LL_RCC_PLL2SOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC)); +} + +/** + * @brief Set Main PLL2 multiplication factor for VCO + * @rmtoll PLL2CFGR PLL2N LL_RCC_PLL2_SetN + * @param PLL2N parameter can be a value between 4 and 512 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t PLL2N) +{ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N, (PLL2N - 1UL) << RCC_PLL2DIVR_PLL2N_Pos); +} + +/** + * @brief Get Main PLL2 multiplication factor for VCO + * @rmtoll PLL2CFGR PLL2N LL_RCC_PLL2_GetN + * @retval Between 4 and 512 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N) >> RCC_PLL2DIVR_PLL2N_Pos) + 1UL); +} + + +/** + * @brief Set Main PLL2 division factor for PLL2P + * @note Used for SAI1 and SAI2 clock + * @rmtoll PLL2CFGR PLL2P LL_RCC_PLL2_SetP + * @param PLL2P parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t PLL2P) +{ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2P, (PLL2P - 1UL) << RCC_PLL2DIVR_PLL2P_Pos); +} + +/** + * @brief Get Main PLL2 division factor for PLL2P + * @note Used for SAI1 and SAI2 clock + * @rmtoll PLL2CFGR PLL2P LL_RCC_PLL2_GetP + * @retval Between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + 1UL); +} + + +/** + * @brief Set Main PLL division factor for PLLQ + * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock) + * @rmtoll PLLCFGR PLL2Q LL_RCC_PLL2_SetQ + * @param PLL2Q parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t PLL2Q) +{ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q, (PLL2Q - 1UL) << RCC_PLL2DIVR_PLL2Q_Pos); +} + +/** + * @brief Get Main PLL division factor for PLLQ + * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock) + * @rmtoll PLL2CFGR PLL2Q LL_RCC_PLL2_GetQ + * @retval Between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1UL); +} + +/** + * @brief Set Main PLL division factor for PLLQ + * @note Used for PLL2CLK selected for USB, SDMMC (48 MHz clock) + * @rmtoll PLL2CFGR PLL2R LL_RCC_PLL2_SetR + * @param PLL2R parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t PLL2R) +{ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2R, (PLL2R - 1UL) << RCC_PLL2DIVR_PLL2R_Pos); +} + +/** + * @brief Get Main PLL2 division factor for PLL2R + * @note Used for PLL2CLK (system clock) + * @rmtoll PLL2DIVR PLL2R LL_RCC_PLL2_GetR + * @retval Between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1UL); +} + +/** + * @brief Set Division factor for the main PLL and other PLL + * @rmtoll PLL2CFGR PLL2M LL_RCC_PLL2_SetDivider + * @param PLL2M parameter can be a value between 1 and 16 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetDivider(uint32_t PLL2M) +{ + MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2M, (PLL2M - 1UL) << RCC_PLL2CFGR_PLL2M_Pos); +} + +/** + * @brief Get Division factor for the main PLL and other PLL + * @rmtoll PLL2CFGR PLL2M LL_RCC_PLL2_GetDivider + * @retval Between 1 and 16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetDivider(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1UL); +} + +/** + * @brief Enable PLL2 output mapped on SAI domain clock + * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2_EnableDomain_SAI + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_EnableDomain_SAI(void) +{ + SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN); +} + +/** + * @brief Disable PLL2 output mapped on SAI domain clock + * @note In order to save power, when of the PLL2 is + * not used, should be 0 + * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2_DisableDomain_SAI + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_DisableDomain_SAI(void) +{ + CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN); +} + +/** + * @brief Check if PLL2 output mapped on SAI domain clock is enabled + * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2_IsEnabledDomain_SAI + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledDomain_SAI(void) +{ + return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN) == (RCC_PLL2CFGR_PLL2PEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL2 output mapped on 48MHz domain clock + * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2_EnableDomain_48M + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_EnableDomain_48M(void) +{ + SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN); +} + +/** + * @brief Disable PLL2 output mapped on 48MHz domain clock + * @note In order to save power, when of the PLL2 48M is + * not used, should be 0 + * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2_DisableDomain_48M + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_DisableDomain_48M(void) +{ + CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN); +} + +/** + * @brief Check if PLL2 output mapped on 48M domain clock is enabled + * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2_IsEnabledDomain_48M + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledDomain_48M(void) +{ + return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN) == (RCC_PLL2CFGR_PLL2QEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL2 output mapped on ADC domain clock + * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2_EnableDomain_ADC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_EnableDomain_ADC(void) +{ + SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN); +} + +/** + * @brief Disable PLL2 output mapped on ADC domain clock + * @note In order to save power, when of the PLL2 ADC is + * not used, Main PLL2ADC should be 0 + * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2_DisableDomain_ADC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_DisableDomain_ADC(void) +{ + CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN); +} + +/** + * @brief Check if PLL2 output mapped on ADC domain clock is enabled + * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2_IsEnabledDomain_ADC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledDomain_ADC(void) +{ + return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN) == (RCC_PLL2CFGR_PLL2REN)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL2 FRACN + * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void) +{ + SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN); +} + +/** + * @brief Check if PLL2 FRACN is enabled + * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) == RCC_PLL2CFGR_PLL2FRACEN) ? 1UL : 0UL); +} + +/** + * @brief Disable PLL2 FRACN + * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void) +{ + CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN); +} + +/** + * @brief Set PLL2 FRACN Coefficient + * @rmtoll PLL2FRACR PLL2FRACN LL_RCC_PLL2_SetFRACN + * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN, FRACN << RCC_PLL2FRACR_PLL2FRACN_Pos); +} + +/** + * @brief Get PLL2 FRACN Coefficient + * @rmtoll PLL2FRACR PLL2FRACN LL_RCC_PLL2_GetFRACN + * @retval A value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN) >> RCC_PLL2FRACR_PLL2FRACN_Pos); +} + +/** + * @brief Set PLL2 VCO Input Range + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR PLL2RGE LL_RCC_PLL2_SetVCOInputRange + * @param InputRange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange) +{ + MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, InputRange); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLL3 PLL3 + * @{ + */ + +/** + * @brief Enable PLL3 + * @rmtoll CR PLL3ON LL_RCC_PLL3_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL3ON); +} + +/** + * @brief Disable PLL3 + * @rmtoll CR PLL3ON LL_RCC_PLL3_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); +} + +/** + * @brief Check if PLL3 Ready + * @rmtoll CR PLL3RDY LL_RCC_PLL3_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == RCC_CR_PLL3RDY) ? 1UL : 0UL); +} + +/** + * @brief Configure PLL3 used for SAI domain clock + * @note PLL3SRC/PLL3M/PLL3N/PLL3PDIV can be written only when PLL3 is disabled. + * @note This can be selected for SAI1 or SAI2 + * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_ConfigDomain_SAI\n + * PLL3CFGR PLL3M LL_RCC_PLL3_ConfigDomain_SAI\n + * PLL3CFGR PLL3N LL_RCC_PLL3_ConfigDomain_SAI\n + * PLL3DIVR PLL3P LL_RCC_PLL3_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL3SOURCE_NONE + * @arg @ref LL_RCC_PLL3SOURCE_MSIS + * @arg @ref LL_RCC_PLL3SOURCE_HSI + * @arg @ref LL_RCC_PLL3SOURCE_HSE + * @param PLLM parameter can be a value between 1 and 16 + * @param PLLN parameter can be a value between 4 and 512 + * @param PLLP parameter can be a value between 1 and 128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC | RCC_PLL3CFGR_PLL3M, Source | \ + ((PLLM - 1UL) << RCC_PLL3CFGR_PLL3M_Pos)); + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N | RCC_PLL3DIVR_PLL3P, ((PLLN - 1UL) << \ + RCC_PLL3DIVR_PLL3N_Pos) | ((PLLP - 1UL) << \ + RCC_PLL3DIVR_PLL3P_Pos)); +} + + +/** + * @brief Configure PLL3 used for 48Mhz domain clock + * @note PLL3 Source, PLLM, PLLN and PLLQ can be written only when PLL3 is disabled. + * @note This can be selected for USB, SDMMC + * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_ConfigDomain_48M\n + * PLL3CFGR PLL3M LL_RCC_PLL3_ConfigDomain_48M\n + * PLL3CFGR PLL3N LL_RCC_PLL3_ConfigDomain_48M\n + * PLL3CFGR PLL3Q LL_RCC_PLL3_ConfigDomain_48M + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL3SOURCE_NONE + * @arg @ref LL_RCC_PLL3SOURCE_MSIS + * @arg @ref LL_RCC_PLL3SOURCE_HSI + * @arg @ref LL_RCC_PLL3SOURCE_HSE + * @param PLLM parameter can be a value between 1 and 16 + * @param PLLN parameter can be a value between 4 and 512 + * @param PLLQ parameter can be a value between 1 and 128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC | RCC_PLL3CFGR_PLL3M, Source | \ + ((PLLM - 1UL) << RCC_PLL3CFGR_PLL3M_Pos)); + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N | RCC_PLL3DIVR_PLL3Q, ((PLLN - 1UL) << \ + RCC_PLL3DIVR_PLL3N_Pos) | ((PLLQ - 1UL) << \ + RCC_PLL3DIVR_PLL3Q_Pos)); +} + + +#if defined(LTDC) || defined(HSPI1) + +/** + * @brief Configure PLL3 used for HSPI_LTDC domain clock + * @note PLL3 Source, PLLM, PLLN and PLLR can be written only when PLL3 is disabled. + * @note This can be selected for HSPI and LTDC + * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_ConfigDomain_HSPI_LTDC\n + * PLL3CFGR PLL3M LL_RCC_PLL3_ConfigDomain_HSPI_LTDC\n + * PLL3CFGR PLL3N LL_RCC_PLL3_ConfigDomain_HSPI_LTDC\n + * PLL3CFGR PLL3R LL_RCC_PLL3_ConfigDomain_HSPI_LTDC + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL3SOURCE_NONE + * @arg @ref LL_RCC_PLL3SOURCE_MSIS + * @arg @ref LL_RCC_PLL3SOURCE_HSI + * @arg @ref LL_RCC_PLL3SOURCE_HSE + * @param PLLM parameter can be a value between 1 and 16 + * @param PLLN parameter can be a value between 4 and 512 + * @param PLLR parameter can be a value between 1 and 128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_ConfigDomain_HSPI_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC | RCC_PLL3CFGR_PLL3M, Source | \ + ((PLLM - 1UL) << RCC_PLL3CFGR_PLL3M_Pos)); + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N | RCC_PLL3DIVR_PLL3R, ((PLLN - 1UL) << \ + RCC_PLL3DIVR_PLL3N_Pos) | ((PLLR - 1UL) << \ + RCC_PLL3DIVR_PLL3R_Pos)); +} + +#endif /* LTDC || HSPI1 */ + +/** + * @brief Configure PLL3 clock source + * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_SetSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL3SOURCE_NONE + * @arg @ref LL_RCC_PLL3SOURCE_MSIS + * @arg @ref LL_RCC_PLL3SOURCE_HSI + * @arg @ref LL_RCC_PLL3SOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_SetSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL3 clock source. + * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL3SOURCE_NONE + * @arg @ref LL_RCC_PLL3SOURCE_MSIS + * @arg @ref LL_RCC_PLL3SOURCE_HSI + * @arg @ref LL_RCC_PLL3SOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC)); +} + +/** + * @brief Set Main PLL3 multiplication factor for VCO + * @rmtoll PLL3CFGR PLL3N LL_RCC_PLL3_SetN + * @param PLL3N parameter can be a value between 4 and 512 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t PLL3N) +{ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N, (PLL3N - 1UL) << RCC_PLL3DIVR_PLL3N_Pos); +} + +/** + * @brief Get Main PLL3 multiplication factor for VCO + * @rmtoll PLL3CFGR PLL3N LL_RCC_PLL3_GetN + * @retval Between 4 and 512 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N) >> RCC_PLL3DIVR_PLL3N_Pos) + 1UL); +} + + +/** + * @brief Set Main PLL3 division factor for PLL3P + * @note Used for SAI1 and SAI2 clock + * @rmtoll PLL3CFGR PLL3P LL_RCC_PLL3_SetP + * @param PLL3P parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t PLL3P) +{ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3P, (PLL3P - 1UL) << RCC_PLL3DIVR_PLL3P_Pos); +} + +/** + * @brief Get Main PLL3 division factor for PLL3P + * @note Used for SAI1 and SAI2 clock + * @rmtoll PLL3CFGR PLL3P LL_RCC_PLL3_GetP + * @retval Between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + 1UL); +} + + +/** + * @brief Set Main PLL division factor for PLLQ + * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock) + * @rmtoll PLLCFGR PLL3Q LL_RCC_PLL3_SetQ + * @param PLL3Q parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t PLL3Q) +{ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3Q, (PLL3Q - 1UL) << RCC_PLL3DIVR_PLL3Q_Pos); +} + +/** + * @brief Get Main PLL division factor for PLLQ + * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock) + * @rmtoll PLL3CFGR PLL3Q LL_RCC_PLL3_GetQ + * @retval Between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + 1UL); +} + +/** + * @brief Set Main PLL division factor for PLLQ + * @note Used for PLL3CLK selected for USB, SDMMC (48 MHz clock) + * @rmtoll PLL3CFGR PLL3R LL_RCC_PLL3_SetR + * @param PLL3R parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t PLL3R) +{ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3R, (PLL3R - 1UL) << RCC_PLL3DIVR_PLL3R_Pos); +} + +/** + * @brief Get Main PLL3 division factor for PLL3R + * @note Used for PLL3CLK (system clock) + * @rmtoll PLL3DIVR PLL3R LL_RCC_PLL3_GetR + * @retval Between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + 1UL); +} + +/** + * @brief Set Division factor for the main PLL and other PLL + * @rmtoll PLL3CFGR PLL3M LL_RCC_PLL3_SetDivider + * @param PLL3M parameter can be a value between 1 and 16 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetDivider(uint32_t PLL3M) +{ + MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3M, (PLL3M - 1UL) << RCC_PLL3CFGR_PLL3M_Pos); +} + +/** + * @brief Get Division factor for the main PLL and other PLL + * @rmtoll PLL3CFGR PLL3M LL_RCC_PLL3_GetDivider + * @retval Between 1 and 16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetDivider(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos) + 1UL); +} + +/** + * @brief Enable PLL3 output mapped on SAI domain clock + * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3_EnableDomain_SAI + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_EnableDomain_SAI(void) +{ + SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN); +} + +/** + * @brief Disable PLL3 output mapped on SAI domain clock + * @note In order to save power, when of the PLLSAI2 is + * not used, should be 0 + * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3_DisableDomain_SAI + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_DisableDomain_SAI(void) +{ + CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN); +} + +/** + * @brief Check if PLL3 output mapped on SAI domain clock is enabled + * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3_IsEnabledDomain_SAI + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledDomain_SAI(void) +{ + return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN) == (RCC_PLL3CFGR_PLL3PEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL2 output mapped on 48MHz domain clock + * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3_EnableDomain_48M + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_EnableDomain_48M(void) +{ + SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN); +} + +/** + * @brief Disable PLL3 output mapped on 48MHz domain clock + * @note In order to save power, when of the PLL3 is + * not used, should be 0 + * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3_DisableDomain_48M + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_DisableDomain_48M(void) +{ + CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN); +} + +/** + * @brief Check if PLL3 output mapped on 48M domain clock is enabled + * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3_IsEnabledDomain_48M + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledDomain_48M(void) +{ + return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN) == (RCC_PLL3CFGR_PLL3QEN)) ? 1UL : 0UL); +} + +#if defined(LTDC) || defined(HSPI1) + +/** + * @brief Enable PLL3 output mapped on HSPI_LTDC domain clock + * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3_EnableDomain_HSPI_LTDC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_EnableDomain_HSPI_LTDC(void) +{ + SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN); +} + +/** + * @brief Disable PLL3 output mapped on HSPI_LTDC domain clock + * @note In order to save power, when of the PLL3 is + * not used, should be 0 + * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3_DisableDomain_HSPI_LTDC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_DisableDomain_HSPI_LTDC(void) +{ + CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN); +} + +/** + * @brief Check if PLL3 output mapped on HSPI_LTDC domain clock is enabled + * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3_IsEnabledDomain_HSPI_LTDC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledDomain_HSPI_LTDC(void) +{ + return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN) == (RCC_PLL3CFGR_PLL3REN)) ? 1UL : 0UL); +} + +#endif /* LTDC || HSPI1 */ + + +/** + * @brief Enable PLL3 FRACN + * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void) +{ + SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN); +} + +/** + * @brief Check if PLL3 FRACN is enabled + * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) == RCC_PLL3CFGR_PLL3FRACEN) ? 1UL : 0UL); +} + +/** + * @brief Disable PLL3 FRACN + * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void) +{ + CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN); +} + +/** + * @brief Set PLL3 FRACN Coefficient + * @rmtoll PLL3FRACR PLL3FRACN LL_RCC_PLL3_SetFRACN + * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN, FRACN << RCC_PLL3FRACR_PLL3FRACN_Pos); +} + +/** + * @brief Get PLL3 FRACN Coefficient + * @rmtoll PLL3FRACR PLL3FRACN LL_RCC_PLL3_GetFRACN + * @retval A value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN) >> RCC_PLL3FRACR_PLL3FRACN_Pos); +} + +/** + * @brief Set PLL3 VCO Input Range + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3CFGR PLL3RGE LL_RCC_PLL3_SetVCOInputRange + * @param InputRange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange) +{ + MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3RGE, InputRange); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PRIV Privileged mode + * @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable Secure Privileged mode + * @rmtoll PRIVCFGR SPRIV LL_RCC_EnableSecPrivilegedMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableSecPrivilegedMode(void) +{ + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); +} + +/** + * @brief Disable Secure Privileged mode + * @rmtoll PRIVCFGR SPRIV LL_RCC_DisableSecPrivilegedMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableSecPrivilegedMode(void) +{ + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); +} + +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Check if Secure Privileged mode has been enabled or not + * @rmtoll PRIVCFGR SPRIV LL_RCC_IsEnabledSecPrivilegedMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledSecPrivilegedMode(void) +{ + return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV) == RCC_PRIVCFGR_SPRIV) ? 1UL : 0UL); +} + +/** + * @brief Enable Non Secure Privileged mode + * @rmtoll PRIVCFGR NSPRIV LL_RCC_EnableNSecPrivilegedMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableNSecPrivilegedMode(void) +{ + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); +} + +/** + * @brief Disable Non Secure Privileged mode + * @rmtoll PRIVCFGR NSPRIV LL_RCC_DisableNSecPrivilegedMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableNSecPrivilegedMode(void) +{ + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); +} + +/** + * @brief Check if Non Secure Privileged mode has been enabled or not + * @rmtoll PRIVCFGR NSPRIV LL_RCC_IsEnabledNSecPrivilegedMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledNSecPrivilegedMode(void) +{ + return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV) == RCC_PRIVCFGR_NSPRIV) ? 1UL : 0UL); +} + + +/** + * @brief Enable privileged mode + * @note User should use LL_RCC_EnableSecPrivilegedMode() to enable Secure privilege + * User should use LL_RCC_EnableNSecPrivilegedMode() to enable Non-secure privilege + * This API is kept for legacy purpose only + * @rmtoll PRIVCFGR SPRIV LL_RCC_EnablePrivilegedMode + * @rmtoll PRIVCFGR NSPRIV LL_RCC_EnablePrivilegedMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnablePrivilegedMode(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); +#else + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +/** + * @brief Disable Privileged mode + * @note User should use LL_RCC_DisableSecPrivilegedMode() to disable Secure privilege + * User should use LL_RCC_DisableNSecPrivilegedMode() to disable Non-secure privilege + * This API is kept for legacy purpose only + * @rmtoll CR PRIV LL_RCC_DisablePrivilegedMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisablePrivilegedMode(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); +#else + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +/** + * @brief Check if Privileged mode has been enabled or not + * @note User should use LL_RCC_IsEnabledSecPrivilegedMode() to check Secure privilege setting + * User should use LL_RCC_IsEnabledNSecPrivilegedMode() to check Non-secure privilege setting + * This API is kept for legacy purpose only + * @rmtoll CR PRIV LL_RCC_IsEnabledPrivilegedMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledPrivilegedMode(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV) == RCC_PRIVCFGR_SPRIV) ? 1UL : 0UL); +#else + return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV) == RCC_PRIVCFGR_NSPRIV) ? 1UL : 0UL); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); +} + +/** + * @brief Clear MSI ready interrupt flag + * @rmtoll CICR MSISRDYC LL_RCC_ClearFlag_MSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_MSISRDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); +} + + +/** + * @brief Clear HSI48 ready interrupt flag + * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC); +} + +/** + * @brief Clear PLL1 ready interrupt flag + * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLL1RDYC); +} + +/** + * @brief Clear PLL2 ready interrupt flag + * @rmtoll CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC); +} + +/** + * @brief Clear PLL3 ready interrupt flag + * @rmtoll CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC); +} + +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_CSSC); +} + +/** + * @brief Clear MSIK ready interrupt flag + * @rmtoll CICR MSIKRDYC LL_RCC_ClearFlag_MSIKRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_MSIKRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_MSIKRDYC); +} + +/** + * @brief Clear SHSI ready interrupt flag + * @rmtoll CICR SHSIRDYC LL_RCC_ClearFlag_SHSIRDY + * @retval None + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +__STATIC_INLINE void LL_RCC_ClearFlag_SHSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_SHSIRDYC); +} +#endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/ + + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if MSI ready interrupt occurred or not + * @rmtoll CIFR MSISRDYF LL_RCC_IsActiveFlag_MSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSISRDYF) == RCC_CIFR_MSISRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI48 ready interrupt occurred or not + * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL); +} +/** + * @brief Check if PLL1 ready interrupt occurred or not + * @rmtoll CIFR PLL1RDYF LL_RCC_IsActiveFlag_PLL1RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL1RDYF) == RCC_CIFR_PLL1RDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 ready interrupt occurred or not + * @rmtoll CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == RCC_CIFR_PLL2RDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 ready interrupt occurred or not + * @rmtoll CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == RCC_CIFR_PLL3RDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == RCC_CIFR_CSSF) ? 1UL : 0UL); +} + +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIFR MSIKRDYF LL_RCC_IsActiveFlag_MSIKRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIKRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIKRDYF) == RCC_CIFR_MSIKRDYF) ? 1UL : 0UL); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIFR SHSIRDYF LL_RCC_IsActiveFlag_SHSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_SHSIRDYF) == RCC_CIFR_SHSIRDYF) ? 1UL : 0UL); +} +#endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/ + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag is set or not. + * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag BOR reset is set or not. + * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == RCC_CSR_BORRSTF) ? 1UL : 0UL); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Enable MSI ready interrupt + * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_MSISRDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Enable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); +} + +/** + * @brief Enable PLL1 ready interrupt + * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); +} + +/** + * @brief Enable PLL2 ready interrupt + * @rmtoll CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE); +} + +/** + * @brief Enable PLL3 ready interrupt + * @rmtoll CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE); +} + +/** + * @brief Enable MSIKRDYIE ready interrupt + * @rmtoll CIER MSIKRDYIE LL_RCC_EnableIT_MSIKRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_MSIKRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_MSIKRDYIE); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable SHSIRDYIE ready interrupt + * @rmtoll CIER SHSIRDYIE LL_RCC_EnableIT_SHSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_SHSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_SHSIRDYIE); +} +#endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/ + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Disable MSI ready interrupt + * @rmtoll CIER MSISRDYIE LL_RCC_DisableIT_MSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_MSISRDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Disable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); +} + +/** + * @brief Disable PLL1 ready interrupt + * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); +} + +/** + * @brief Disable PLL2 ready interrupt + * @rmtoll CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE); +} + +/** + * @brief Disable PLL3 ready interrupt + * @rmtoll CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE); +} + +/** + * @brief Disable MSIKRDYIE ready interrupt + * @rmtoll CIER MSIKRDYIE LL_RCC_DisableIT_MSIKRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_MSIKRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_MSIKRDYIE); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Disable SHSIRDYIE ready interrupt + * @rmtoll CIER SHSIRDYIE LL_RCC_DisableIT_SHSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_SHSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_SHSIRDYIE); +} +#endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/ + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if MSI ready interrupt source is enabled or disabled. + * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_MSISRDYIE) == RCC_CIER_MSISRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSI48 ready interrupt source is enabled or disabled. + * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL); +} +/** + * @brief Checks if PLL1 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnabledIT_PLL1RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL1RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL2 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL3 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL3RDYIE LL_RCC_IsEnabledIT_PLL3RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL3RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if MSIK ready interrupt source is enabled or disabled. + * @rmtoll CIER MSIKRDYIE LL_RCC_IsEnabledIT_MSIKRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIKRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_MSIKRDYIE) == RCC_CIER_MSIKRDYIE) ? 1UL : 0UL); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Checks if SHSI ready interrupt source is enabled or disabled. + * @rmtoll CIER SHSIRDYIE LL_RCC_IsEnabledIT_SHSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_SHSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_SHSIRDYIE) == RCC_CIER_SHSIRDYIE) ? 1UL : 0UL); +} +#endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Security_Services Security Services + * @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure RCC resources security + * @note Only available from secure state when system implements security (TZEN=1) + * @rmtoll SECCFGR HSISEC LL_RCC_ConfigSecure\n + * SECCFGR HSESEC LL_RCC_ConfigSecure\n + * SECCFGR MSISEC LL_RCC_ConfigSecure\n + * SECCFGR LSISEC LL_RCC_ConfigSecure\n + * SECCFGR LSESEC LL_RCC_ConfigSecure\n + * SECCFGR SYSCLKSEC LL_RCC_ConfigSecure\n + * SECCFGR PRESCSEC LL_RCC_ConfigSecure\n + * SECCFGR PLL1SEC LL_RCC_ConfigSecure\n + * SECCFGR PLL2SEC LL_RCC_ConfigSecure\n + * SECCFGR PLL3SEC LL_RCC_ConfigSecure\n + * SECCFGR CLK48MSEC LL_RCC_ConfigSecure\n + * SECCFGR HSI48SEC LL_RCC_ConfigSecure\n + * SECCFGR RMVFSEC LL_RCC_ConfigSecure + * @param SecureConfig This parameter can be one or a combination of the following values: + * @arg @ref LL_RCC_ALL_NSEC & LL_RCC_ALL_SEC + * @arg @ref LL_RCC_HSI_SEC & LL_RCC_HSI_NSEC + * @arg @ref LL_RCC_HSE_SEC & LL_RCC_HSE_NSEC + * @arg @ref LL_RCC_MSI_SEC & LL_RCC_MSI_NSEC + * @arg @ref LL_RCC_LSE_SEC & LL_RCC_LSE_NSEC + * @arg @ref LL_RCC_LSI_SEC & LL_RCC_LSI_NSEC + * @arg @ref LL_RCC_SYSCLK_SEC & LL_RCC_SYSCLK_NSEC + * @arg @ref LL_RCC_PRESCALERS_SEC & LL_RCC_PRESCALERS_NSEC + * @arg @ref LL_RCC_PLL1_SEC & LL_RCC_PLL1_NSEC + * @arg @ref LL_RCC_PLL2_SEC & LL_RCC_PLL2_NSEC + * @arg @ref LL_RCC_PLL3_SEC & LL_RCC_PLL3_NSEC + * @arg @ref LL_RCC_CLK48M_SEC & LL_RCC_CLK48M_NSEC + * @arg @ref LL_RCC_HSI48_SEC & LL_RCC_HSI48_NSEC + * @arg @ref LL_RCC_RESET_FLAGS_SEC & LL_RCC_RESET_FLAGS_NSEC + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigSecure(uint32_t SecureConfig) +{ + WRITE_REG(RCC->SECCFGR, SecureConfig); +} +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Get RCC resources security status + * @note Only available from secure state when system implements security (TZEN=1) + * @rmtoll SECCFGR HSISEC LL_RCC_GetConfigSecure\n + * SECCFGR HSESEC LL_RCC_GetConfigSecure\n + * SECCFGR MSISEC LL_RCC_GetConfigSecure\n + * SECCFGR LSISEC LL_RCC_GetConfigSecure\n + * SECCFGR LSESEC LL_RCC_GetConfigSecure\n + * SECCFGR SYSCLKSEC LL_RCC_GetConfigSecure\n + * SECCFGR PRESCSEC LL_RCC_GetConfigSecure\n + * SECCFGR PLL1SEC LL_RCC_GetConfigSecure\n + * SECCFGR PLL2SEC LL_RCC_GetConfigSecure\n + * SECCFGR PLL3SEC LL_RCC_GetConfigSecure\n + * SECCFGR CLK48MSEC LL_RCC_GetConfigSecure\n + * SECCFGR HSI48SEC LL_RCC_GetConfigSecure\n + * SECCFGR RMVFSEC LL_RCC_GetConfigSecure + * @retval Returned value can be one or a combination of the following values: + * @arg @ref LL_RCC_ALL_NSEC & LL_RCC_ALL_SEC + * @arg @ref LL_RCC_HSI_SEC & LL_RCC_HSI_NSEC + * @arg @ref LL_RCC_HSE_SEC & LL_RCC_HSE_NSEC + * @arg @ref LL_RCC_MSI_SEC & LL_RCC_MSI_NSEC + * @arg @ref LL_RCC_LSE_SEC & LL_RCC_LSE_NSEC + * @arg @ref LL_RCC_LSI_SEC & LL_RCC_LSI_NSEC + * @arg @ref LL_RCC_SYSCLK_SEC & LL_RCC_SYSCLK_NSEC + * @arg @ref LL_RCC_PRESCALERS_SEC & LL_RCC_PRESCALERS_NSEC + * @arg @ref LL_RCC_PLL1_SEC & LL_RCC_PLL1_NSEC + * @arg @ref LL_RCC_PLL2_SEC & LL_RCC_PLL2_NSEC + * @arg @ref LL_RCC_PLL3_SEC & LL_RCC_PLL3_NSEC + * @arg @ref LL_RCC_CLK48M_SEC & LL_RCC_CLK48M_NSEC + * @arg @ref LL_RCC_HSI48_SEC & LL_RCC_HSI48_NSEC + * @arg @ref LL_RCC_RESET_FLAGS_SEC & LL_RCC_RESET_FLAGS_NSEC + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_GetConfigSecure(void) +{ + return (uint32_t)(READ_BIT(RCC->SECCFGR, RCC_SECURE_MASK)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource); +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); +uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource); +uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); +uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource); +uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); +uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +uint32_t LL_RCC_GetADCDACClockFreq(uint32_t ADCxSource); +uint32_t LL_RCC_GetADF1ClockFreq(uint32_t ADF1Source); +uint32_t LL_RCC_GetMDF1ClockFreq(uint32_t MDF1Source); +uint32_t LL_RCC_GetDAC1ClockFreq(uint32_t DAC1Source); +uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource); +#if defined(SAES) +uint32_t LL_RCC_GetSAESClockFreq(uint32_t SAESxSource); +#endif /* SAES */ +uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource); +#if defined(DSI) +uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); +#endif /* DSI */ +#if defined(HSPI1) +uint32_t LL_RCC_GetHSPIClockFreq(uint32_t HSPIxSource); +#endif /* HSPI1 */ +#if defined(LTDC) +uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); +#endif /* defined(LTDC) */ +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32u5xx_LL_RCC_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h new file mode 100644 index 000000000..ae3631a11 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h @@ -0,0 +1,765 @@ +/** + ****************************************************************************** + * @file stm32u5xx_ll_rng.h + * @author MCD Application Team + * @brief Header file of RNG LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_LL_RNG_H +#define STM32U5xx_LL_RNG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx.h" + +/** @addtogroup STM32U5xx_LL_Driver + * @{ + */ + +#if defined (RNG) + +/** @defgroup RNG_LL RNG + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures + * @{ + */ + + +/** + * @brief LL RNG Init Structure Definition + */ +typedef struct +{ + uint32_t ClockErrorDetection; /*!< Clock error detection. + This parameter can be one value of @ref RNG_LL_CED. + This parameter can be modified using unitary + functions @ref LL_RNG_EnableClkErrorDetect(). */ +} LL_RNG_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants + * @{ + */ + +/** @defgroup RNG_LL_CED Clock Error Detection + * @{ + */ +#define LL_RNG_CED_ENABLE 0x00000000U /*!< Clock error detection enabled */ +#define LL_RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */ +/** + * @} + */ +/** @defgroup RNG_LL_ARDIS Auto reset disable + * @{ + */ +#define LL_RNG_ARDIS_ENABLE 0x00000000U /*!< ARDIS enabled automatic reset to clear SECS bit*/ +#define LL_RNG_ARDIS_DISABLE RNG_CR_ARDIS /*!< ARDIS disabled no automatic reset to clear SECS bit*/ +/** + * @} + */ + +/** @defgroup RNG_LL_Clock_Divider_Factor Value used to configure an internal + * programmable divider acting on the incoming RNG clock + * @{ + */ +#define LL_RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */ +#define LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0) /*!< 2 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1) /*!< 4 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 8 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2) /*!< 16 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 32 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 64 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 128 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3) /*!< 256 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0) /*!< 512 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1) /*!< 1024 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 2048 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2) /*!< 4096 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 8192 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 16384 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 32768 RNG clock cycles per internal RNG clock */ +/** + * @} + */ + +/** @defgroup RNG_LL_NIST_Compliance NIST Compliance configuration + * @{ + */ +#define LL_RNG_NIST_COMPLIANT (0x00000000UL) /*!< Default NIST compliant configuration*/ +#define LL_RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */ + +/** + * @} + */ + +/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RNG_ReadReg function + * @{ + */ +#define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */ +#define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */ +#define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */ +#define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */ +#define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */ +/** + * @} + */ + +/** @defgroup RNG_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros + * @{ + */ +#define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RNG_LL_Exported_Macros RNG Exported Macros + * @{ + */ + +/** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RNG register + * @param __INSTANCE__ RNG Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RNG register + * @param __INSTANCE__ RNG Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RNG_LL_Exported_Functions RNG Exported Functions + * @{ + */ +/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions + * @{ + */ + +/** + * @brief Enable Random Number Generation + * @rmtoll CR RNGEN LL_RNG_Enable + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx) +{ + SET_BIT(RNGx->CR, RNG_CR_RNGEN); +} + +/** + * @brief Disable Random Number Generation + * @rmtoll CR RNGEN LL_RNG_Disable + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx) +{ + CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN); +} + +/** + * @brief Check if Random Number Generator is enabled + * @rmtoll CR RNGEN LL_RNG_IsEnabled + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable Clock Error Detection + * @rmtoll CR CED LL_RNG_EnableClkErrorDetect + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx) +{ + MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_ENABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Disable RNG Clock Error Detection + * @rmtoll CR CED LL_RNG_DisableClkErrorDetect + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx) +{ + MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_DISABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Check if RNG Clock Error Detection is enabled + * @rmtoll CR CED LL_RNG_IsEnabledClkErrorDetect + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL); +} + +/** + * @brief Set RNG Conditioning Soft Reset bit + * @rmtoll CR CONDRST LL_RNG_EnableCondReset + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_EnableCondReset(RNG_TypeDef *RNGx) +{ + SET_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Reset RNG Conditioning Soft Reset bit + * @rmtoll CR CONDRST LL_RNG_DisableCondReset + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx) +{ + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Check if RNG Conditioning Soft Reset bit is set + * @rmtoll CR CONDRST LL_RNG_IsEnabledCondReset + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL); +} + +/** + * @brief Enable RNG Config Lock + * @rmtoll CR CONFIGLOCK LL_RNG_ConfigLock + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx) +{ + SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK); +} + +/** + * @brief Check if RNG Config Lock is enabled + * @rmtoll CR CONFIGLOCK LL_RNG_IsConfigLocked + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL); +} + +/** + * @brief Enable NIST Compliance + * @rmtoll CR NISTC LL_RNG_EnableNistCompliance + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx) +{ + MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_NIST_COMPLIANT | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Disable NIST Compliance + * @rmtoll CR NISTC LL_RNG_DisableNistCompliance + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx) +{ + MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Check if NIST Compliance is enabled + * @rmtoll CR NISTC LL_RNG_IsEnabledNistCompliance + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL); +} + +/** + * @brief Set RNG Config1 Configuration field value + * @rmtoll CR RNG_CONFIG1 LL_RNG_SetConfig1 + * @param RNGx RNG Instance + * @param Config1 Value between 0 and 0x3F + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1) +{ + MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1 | RNG_CR_CONDRST, (Config1 << RNG_CR_RNG_CONFIG1_Pos) | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Get RNG Config1 Configuration field value + * @rmtoll CR RNG_CONFIG1 LL_RNG_GetConfig1 + * @param RNGx RNG Instance + * @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F + */ +__STATIC_INLINE uint32_t LL_RNG_GetConfig1(const RNG_TypeDef *RNGx) +{ + return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos); +} + +/** + * @brief Set RNG Config2 Configuration field value + * @rmtoll CR RNG_CONFIG2 LL_RNG_SetConfig2 + * @param RNGx RNG Instance + * @param Config2 Value between 0 and 0x7 + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2) +{ + MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2 | RNG_CR_CONDRST, (Config2 << RNG_CR_RNG_CONFIG2_Pos) | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Get RNG Config2 Configuration field value + * @rmtoll CR RNG_CONFIG2 LL_RNG_GetConfig2 + * @param RNGx RNG Instance + * @retval Returned Value expressed on 3 bits : Value between 0 and 0x7 + */ +__STATIC_INLINE uint32_t LL_RNG_GetConfig2(const RNG_TypeDef *RNGx) +{ + return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos); +} + +/** + * @brief Set RNG Config3 Configuration field value + * @rmtoll CR RNG_CONFIG3 LL_RNG_SetConfig3 + * @param RNGx RNG Instance + * @param Config3 Value between 0 and 0xF + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3) +{ + MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3 | RNG_CR_CONDRST, (Config3 << RNG_CR_RNG_CONFIG3_Pos) | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Get RNG Config3 Configuration field value + * @rmtoll CR RNG_CONFIG3 LL_RNG_GetConfig3 + * @param RNGx RNG Instance + * @retval Returned Value expressed on 4 bits : Value between 0 and 0xF + */ +__STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx) +{ + return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos); +} + +/** + * @brief Set RNG Clock divider factor + * @rmtoll CR CLKDIV LL_RNG_SetClockDivider + * @param RNGx RNG Instance + * @param Divider can be one of the following values: + * @arg @ref LL_RNG_CLKDIV_BY_1 + * @arg @ref LL_RNG_CLKDIV_BY_2 + * @arg @ref LL_RNG_CLKDIV_BY_4 + * @arg @ref LL_RNG_CLKDIV_BY_8 + * @arg @ref LL_RNG_CLKDIV_BY_16 + * @arg @ref LL_RNG_CLKDIV_BY_32 + * @arg @ref LL_RNG_CLKDIV_BY_64 + * @arg @ref LL_RNG_CLKDIV_BY_128 + * @arg @ref LL_RNG_CLKDIV_BY_256 + * @arg @ref LL_RNG_CLKDIV_BY_512 + * @arg @ref LL_RNG_CLKDIV_BY_1024 + * @arg @ref LL_RNG_CLKDIV_BY_2048 + * @arg @ref LL_RNG_CLKDIV_BY_4096 + * @arg @ref LL_RNG_CLKDIV_BY_8192 + * @arg @ref LL_RNG_CLKDIV_BY_16384 + * @arg @ref LL_RNG_CLKDIV_BY_32768 + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider) +{ + MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, Divider | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Get RNG Clock divider factor + * @rmtoll CR CLKDIV LL_RNG_GetClockDivider + * @param RNGx RNG Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RNG_CLKDIV_BY_1 + * @arg @ref LL_RNG_CLKDIV_BY_2 + * @arg @ref LL_RNG_CLKDIV_BY_4 + * @arg @ref LL_RNG_CLKDIV_BY_8 + * @arg @ref LL_RNG_CLKDIV_BY_16 + * @arg @ref LL_RNG_CLKDIV_BY_32 + * @arg @ref LL_RNG_CLKDIV_BY_64 + * @arg @ref LL_RNG_CLKDIV_BY_128 + * @arg @ref LL_RNG_CLKDIV_BY_256 + * @arg @ref LL_RNG_CLKDIV_BY_512 + * @arg @ref LL_RNG_CLKDIV_BY_1024 + * @arg @ref LL_RNG_CLKDIV_BY_2048 + * @arg @ref LL_RNG_CLKDIV_BY_4096 + * @arg @ref LL_RNG_CLKDIV_BY_8192 + * @arg @ref LL_RNG_CLKDIV_BY_16384 + * @arg @ref LL_RNG_CLKDIV_BY_32768 + */ +__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(const RNG_TypeDef *RNGx) +{ + return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV); +} +/** + * @} + */ + +/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Indicate if the RNG Data ready Flag is set or not + * @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if the Clock Error Current Status Flag is set or not + * @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if the Seed Error Current Status Flag is set or not + * @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if the Clock Error Interrupt Status Flag is set or not + * @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if the Seed Error Interrupt Status Flag is set or not + * @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL); +} + +/** + * @brief Clear Clock Error interrupt Status (CEIS) Flag + * @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx) +{ + WRITE_REG(RNGx->SR, ~RNG_SR_CEIS); +} + +/** + * @brief Clear Seed Error interrupt Status (SEIS) Flag + * @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx) +{ + WRITE_REG(RNGx->SR, ~RNG_SR_SEIS); +} + +/** + * @} + */ + +/** @defgroup RNG_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable Random Number Generator Interrupt + * (applies for either Seed error, Clock Error or Data ready interrupts) + * @rmtoll CR IE LL_RNG_EnableIT + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx) +{ + SET_BIT(RNGx->CR, RNG_CR_IE); +} + +/** + * @brief Disable Random Number Generator Interrupt + * (applies for either Seed error, Clock Error or Data ready interrupts) + * @rmtoll CR IE LL_RNG_DisableIT + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx) +{ + CLEAR_BIT(RNGx->CR, RNG_CR_IE); +} + +/** + * @brief Check if Random Number Generator Interrupt is enabled + * (applies for either Seed error, Clock Error or Data ready interrupts) + * @rmtoll CR IE LL_RNG_IsEnabledIT + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RNG_LL_EF_Data_Management Data Management + * @{ + */ + +/** + * @brief Return32-bit Random Number value + * @rmtoll DR RNDATA LL_RNG_ReadRandData32 + * @param RNGx RNG Instance + * @retval Generated 32-bit random value + */ +__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx) +{ + return (uint32_t)(READ_REG(RNGx->DR)); +} + +/** + * @} + */ + +/** + * @brief Enable Auto reset + * @rmtoll CR ARDIS LL_RNG_EnableArdis + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_EnableArdis(RNG_TypeDef *RNGx) +{ + MODIFY_REG(RNGx->CR, RNG_CR_ARDIS | RNG_CR_CONDRST, LL_RNG_ARDIS_ENABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Disable Auto reset + * @rmtoll CR ARDIS LL_RNG_DisableArdis + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_DisableArdis(RNG_TypeDef *RNGx) +{ + MODIFY_REG(RNGx->CR, RNG_CR_ARDIS | RNG_CR_CONDRST, LL_RNG_ARDIS_DISABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Check if RNG Auto reset is enabled + * @rmtoll CR ARDIS LL_RNG_IsEnabledArdis + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledArdis(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_ARDIS) != (RNG_CR_ARDIS)) ? 1UL : 0UL); +} + +/** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control + * @{ + */ + +/** + * @brief Set RNG Health Test Control + * @rmtoll HTCR HTCFG LL_RNG_SetHealthConfig + * @param RNGx RNG Instance + * @param HTCFG can be values of 32 bits + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) +{ +#if defined(RNG_HTCR_NIST_VALUE) + /* For NIST compliance we can fin the recommended value in the application note AN4230 */ +#endif /* defined(RNG_HTCR_NIST_VALUE) */ + WRITE_REG(RNGx->HTCR, HTCFG); +} + +/** + * @brief Get RNG Health Test Control + * @rmtoll HTCR HTCFG LL_RNG_GetHealthConfig + * @param RNGx RNG Instance + * @retval Return 32-bit RNG Health Test configuration + */ +__STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(const RNG_TypeDef *RNGx) +{ + return (uint32_t)READ_REG(RNGx->HTCR); +} + +/** + * @} + */ +#if defined(RNG_NSCR_NIST_VALUE) + +/** @defgroup RNG_LL_EF_Noise_Test_Control Noise Test Control + * @{ + */ + +/** + * @brief Set RNG Noise Test Control + * @rmtoll NSCR NOISECFG LL_RNG_SetNoiseConfig + * @param RNGx RNG Instance + * @param NOISECFG can be values of 32 bits + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetNoiseConfig(RNG_TypeDef *RNGx, uint32_t NOISECFG) +{ + /* For NIST compliance we can fin the recommended value in the application note AN4230 */ + WRITE_REG(RNGx->NSCR, NOISECFG); +} + +/** + * @brief Get RNG Noise Test Control + * @rmtoll NSCR NOISECFG LL_RNG_GetNoiseConfig + * @param RNGx RNG Instance + * @retval Return 32-bit RNG Noise Test configuration + */ +__STATIC_INLINE uint32_t LL_RNG_GetNoiseConfig(const RNG_TypeDef *RNGx) +{ + + return (uint32_t)READ_REG(RNGx->NSCR); +} + +/** + * @} + */ + +#endif /* defined(RNG_NSCR_NIST_VALUE) */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct); +void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); +ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RNG */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32U5xx_LL_RNG_H */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_spi.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_spi.h new file mode 100644 index 000000000..028747fd3 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_spi.h @@ -0,0 +1,2744 @@ +/** + ****************************************************************************** + * @file stm32u5xx_ll_spi.h + * @author MCD Application Team + * @brief Header file of SPI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_LL_SPI_H +#define STM32U5xx_LL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx.h" + +/** @addtogroup STM32U5xx_LL_Driver + * @{ + */ + +#if defined(SPI1) || defined(SPI2) || defined(SPI3) + +/** @defgroup SPI_LL SPI + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_SPI_UNDERRUN_BEHAV_LAST_RECEIVED LL_SPI_UDR_CONFIG_LAST_RECEIVED +/** +@endcond + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Private_Macros SPI Private Macros + * @{ + */ +#if defined(IS_SPI_GRP2_INSTANCE) +#define IS_LL_SPI_GRP1_INSTANCE(__INSTANCE__) IS_SPI_GRP1_INSTANCE(__INSTANCE__) +#define IS_LL_SPI_GRP2_INSTANCE(__INSTANCE__) IS_SPI_GRP2_INSTANCE(__INSTANCE__) +#else +#define IS_LL_SPI_GRP1_INSTANCE(__INSTANCE__) IS_SPI_GRP1_INSTANCE(__INSTANCE__) +#endif /* SPI_TRIG_GRP2 */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Init structures definition + */ +typedef struct +{ + uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetTransferDirection().*/ + + uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). + This parameter can be a value of @ref SPI_LL_EC_MODE. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetMode().*/ + + uint32_t DataWidth; /*!< Specifies the SPI data width. + This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetDataWidth().*/ + + uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_LL_EC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetClockPolarity().*/ + + uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_LL_EC_PHASE. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetClockPhase().*/ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. + + This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetNSSMode().*/ + + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure + the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetBaudRatePrescaler().*/ + + uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetTransferBitOrder().*/ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. + + This feature can be modified afterwards using unitary functions + @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + + uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be a number between Min_Data = 0x00 + and Max_Data = 0xFFFFFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetCRCPolynomial().*/ + +} LL_SPI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_SPI_ReadReg function + * @{ + */ +#define LL_SPI_SR_RXP (SPI_SR_RXP) +#define LL_SPI_SR_TXP (SPI_SR_TXP) +#define LL_SPI_SR_DXP (SPI_SR_DXP) +#define LL_SPI_SR_EOT (SPI_SR_EOT) +#define LL_SPI_SR_TXTF (SPI_SR_TXTF) +#define LL_SPI_SR_UDR (SPI_SR_UDR) +#define LL_SPI_SR_CRCE (SPI_SR_CRCE) +#define LL_SPI_SR_MODF (SPI_SR_MODF) +#define LL_SPI_SR_OVR (SPI_SR_OVR) +#define LL_SPI_SR_TIFRE (SPI_SR_TIFRE) +#define LL_SPI_SR_SUSP (SPI_SR_SUSP) +#define LL_SPI_SR_TXC (SPI_SR_TXC) +#define LL_SPI_SR_RXWNE (SPI_SR_RXWNE) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + * @{ + */ +#define LL_SPI_IER_RXPIE (SPI_IER_RXPIE) +#define LL_SPI_IER_TXPIE (SPI_IER_TXPIE) +#define LL_SPI_IER_DXPIE (SPI_IER_DXPIE) +#define LL_SPI_IER_EOTIE (SPI_IER_EOTIE) +#define LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE) +#define LL_SPI_IER_UDRIE (SPI_IER_UDRIE) +#define LL_SPI_IER_OVRIE (SPI_IER_OVRIE) +#define LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE) +#define LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE) +#define LL_SPI_IER_MODFIE (SPI_IER_MODFIE) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_MODE Mode + * @{ + */ +#define LL_SPI_MODE_MASTER (SPI_CFG2_MASTER) +#define LL_SPI_MODE_SLAVE (0x00000000UL) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_SS_LEVEL SS Level + * @{ + */ +#define LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI) +#define LL_SPI_SS_LEVEL_LOW (0x00000000UL) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_SS_IDLENESS SS Idleness + * @{ + */ +#define LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL) +#define LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1) +#define LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1) +#define LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2) +#define LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1) +#define LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3) +#define LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1) +#define LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2) +#define LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1) +#define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3\ + | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness + * @{ + */ +#define LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL) +#define LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1) +#define LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1) +#define LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2) +#define LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1) +#define LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3) +#define LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1) +#define LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2) +#define LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1) +#define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3\ + | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All + * @{ + */ +#define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL) +#define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All + * @{ + */ +#define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL) +#define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register + * @{ + */ +#define LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL) +#define LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PROTOCOL Protocol + * @{ + */ +#define LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL) +#define LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PHASE Phase + * @{ + */ +#define LL_SPI_PHASE_1EDGE (0x00000000UL) +#define LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_POLARITY Polarity + * @{ + */ +#define LL_SPI_POLARITY_LOW (0x00000000UL) +#define LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity + * @{ + */ +#define LL_SPI_NSS_POLARITY_LOW (0x00000000UL) +#define LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler + * @{ + */ +#define LL_SPI_BAUDRATEPRESCALER_BYPASS (SPI_CFG1_BPASS) +#define LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL) +#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0) +#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1) +#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0) +#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2) +#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0) +#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1) +#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BIT_ORDER Bit Order + * @{ + */ +#define LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST) +#define LL_SPI_MSB_FIRST (0x00000000UL) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode + * @{ + */ +#define LL_SPI_FULL_DUPLEX (0x00000000UL) +#define LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0) +#define LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1) +#define LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1) +#define LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_DATAWIDTH Data Width + * @{ + */ +#define LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2) +#define LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3) +#define LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2) +#define LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3\ + | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4) +#define LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2) +#define LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3) +#define LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2) +#define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\ + | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold + * @{ + */ +#define LL_SPI_FIFO_TH_01DATA (0x00000000UL) +#define LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2) +#define LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3) +#define LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2) +#define LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3\ + | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation + * @{ + */ +#define LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL) /*!< CRC calculation disabled */ +#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN) /*!< CRC calculation enabled */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup SPI_LL_EC_CRC CRC + * @{ + */ +#define LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2) +#define LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3) +#define LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2) +#define LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3\ + | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4) +#define LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2) +#define LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4\ + | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3) +#define LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4\ + | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2) +#define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4\ + | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4\ + | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3\ + | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_NSS_MODE NSS Mode + * @{ + */ +#define LL_SPI_NSS_SOFT (SPI_CFG2_SSM) +#define LL_SPI_NSS_HARD_INPUT (0x00000000UL) +#define LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel + * @{ + */ +#define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */ +#define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) +#define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) +#define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection + * @brief SPI Autonomous Trigger selection + * @{ + */ +#define LL_SPI_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for SPI1 and SPI2 */ +#if defined(SPI3) +#define LL_SPI_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for SPI3 */ +#endif /* SPI3 */ + +/*!< HW Trigger signal is GPDMA_CH0_TRG */ +#define LL_SPI_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x00000000U)) +/*!< HW Trigger signal is GPDMA_CH1_TRG */ +#define LL_SPI_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH2_TRG */ +#define LL_SPI_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH3_TRG */ +#define LL_SPI_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI4_TRG */ +#define LL_SPI_GRP1_EXTI4_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI9_TRG */ +#define LL_SPI_GRP1_EXTI9_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM1_CH1_TRG */ +#define LL_SPI_GRP1_LPTIM1_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM2_CH1_TRG */ +#define LL_SPI_GRP1_LPTIM2_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP1_TRG */ +#define LL_SPI_GRP1_COMP1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP2_TRG */ +#define LL_SPI_GRP1_COMP2_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_ALRA_TRG */ +#define LL_SPI_GRP1_RTC_ALRA_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_WUT_TRG */ +#define LL_SPI_GRP1_RTC_WUT_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos)) + +#if defined(LL_SPI_TRIG_GRP2) +/*!< HW Trigger signal is LPDMA_CH0_TRG */ +#define LL_SPI_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x00000000U)) +/*!< HW Trigger signal is LPDMA_CH1_TRG */ +#define LL_SPI_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPDMA_CH2_TRG */ +#define LL_SPI_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPDMA_CH3_TRG */ +#define LL_SPI_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI4_TRG */ +#define LL_SPI_GRP2_EXTI4_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI8_TRG */ +#define LL_SPI_GRP2_EXTI8_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM1_CH1_TRG */ +#define LL_SPI_GRP2_LPTIM1_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM3_CH1_TRG */ +#define LL_SPI_GRP2_LPTIM3_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP1_TRG */ +#define LL_SPI_GRP2_COMP1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP2_TRG */ +#define LL_SPI_GRP2_COMP2_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_ALRA_TRG */ +#define LL_SPI_GRP2_RTC_ALRA_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_WUT_TRG */ +#define LL_SPI_GRP2_RTC_WUT_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos)) +#endif /* LL_SPI_TRIG_GRP2 */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity + * @brief SPI Autonomous Trigger Polarity + * @{ + */ +#define LL_SPI_TRIG_POLARITY_RISING 0x00000000U /*!< SPI triggered on rising edge */ +#define LL_SPI_TRIG_POLARITY_FALLING SPI_AUTOCR_TRIGPOL /*!< SPI triggered on falling edge */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable SPI peripheral + * @rmtoll CR1 SPE LL_SPI_Enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Disable SPI peripheral + * @note When disabling the SPI, follow the procedure described in the Reference Manual. + * @rmtoll CR1 SPE LL_SPI_Disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Check if SPI peripheral is enabled + * @rmtoll CR1 SPE LL_SPI_IsEnabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); +} + +/** + * @brief Swap the MOSI and MISO pin + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 IOSWP LL_SPI_EnableIOSwap + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIOSwap(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP); +} + +/** + * @brief Restore default function for MOSI and MISO pin + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 IOSWP LL_SPI_DisableIOSwap + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP); +} + +/** + * @brief Check if MOSI and MISO pin are swapped + * @rmtoll CFG2 IOSWP LL_SPI_IsEnabledIOSwap + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL); +} + +/** + * @brief Enable GPIO control + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 AFCNTR LL_SPI_EnableGPIOControl + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR); +} + +/** + * @brief Disable GPIO control + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 AFCNTR LL_SPI_DisableGPIOControl + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR); +} + +/** + * @brief Check if GPIO control is active + * @rmtoll CFG2 AFCNTR LL_SPI_IsEnabledGPIOControl + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL); +} + +/** + * @brief Set SPI Mode to Master or Slave + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 MASTER LL_SPI_SetMode + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode); +} + +/** + * @brief Get SPI Mode (Master or Slave) + * @rmtoll CFG2 MASTER LL_SPI_GetMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + */ +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER)); +} + +/** + * @brief Configure the Idleness applied by master between active edge of SS and first send data + * @rmtoll CFG2 MSSI LL_SPI_SetMasterSSIdleness + * @param SPIx SPI Instance + * @param MasterSSIdleness This parameter can be one of the following values: + * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t MasterSSIdleness) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness); +} + +/** + * @brief Get the configured Idleness applied by master + * @rmtoll CFG2 MSSI LL_SPI_GetMasterSSIdleness + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE + */ +__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI)); +} + +/** + * @brief Configure the idleness applied by master between data frame + * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness + * @param SPIx SPI Instance + * @param MasterInterDataIdleness This parameter can be one of the following values: + * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_MIDI, MasterInterDataIdleness); +} + +/** + * @brief Get the configured inter data idleness + * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE + */ +__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI)); +} + +/** + * @brief Set transfer size + * @note Count is the number of frame to be transferred + * @rmtoll CR2 TSIZE LL_SPI_SetTransferSize + * @param SPIx SPI Instance + * @param Count 0..0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count); +} + +/** + * @brief Get transfer size + * @note Count is the number of frame to be transferred + * @rmtoll CR2 TSIZE LL_SPI_GetTransferSize + * @param SPIx SPI Instance + * @retval 0..0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE)); +} + +/** + * @brief Lock the AF configuration of associated IOs + * @note Once this bit is set, the AF configuration remains locked until a hardware reset occurs. + * the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist. + * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_IOLOCK); +} + +/** + * @brief Check if the AF configuration is locked. + * @rmtoll CR1 IOLOCK LL_SPI_IsEnabledIOLock + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL); +} + +/** + * @brief Set Tx CRC Initialization Pattern + * @rmtoll CR1 TCRCINI LL_SPI_SetTxCRCInitPattern + * @param SPIx SPI Instance + * @param TXCRCInitAll This parameter can be one of the following values: + * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN + * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_TCRCINI, TXCRCInitAll); +} + +/** + * @brief Get Tx CRC Initialization Pattern + * @rmtoll CR1 TCRCINI LL_SPI_GetTxCRCInitPattern + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN + * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI)); +} + +/** + * @brief Set Rx CRC Initialization Pattern + * @rmtoll CR1 RCRCINI LL_SPI_SetRxCRCInitPattern + * @param SPIx SPI Instance + * @param RXCRCInitAll This parameter can be one of the following values: + * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN + * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCRCInitAll) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, RXCRCInitAll); +} + +/** + * @brief Get Rx CRC Initialization Pattern + * @rmtoll CR1 RCRCINI LL_SPI_GetRxCRCInitPattern + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN + * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI)); +} + +/** + * @brief Set internal SS input level ignoring what comes from PIN. + * @note This configuration has effect only with config LL_SPI_NSS_SOFT + * @rmtoll CR1 SSI LL_SPI_SetInternalSSLevel + * @param SPIx SPI Instance + * @param SSLevel This parameter can be one of the following values: + * @arg @ref LL_SPI_SS_LEVEL_HIGH + * @arg @ref LL_SPI_SS_LEVEL_LOW + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLevel) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel); +} + +/** + * @brief Get internal SS input level + * @rmtoll CR1 SSI LL_SPI_GetInternalSSLevel + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_SS_LEVEL_HIGH + * @arg @ref LL_SPI_SS_LEVEL_LOW + */ +__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI)); +} + +/** + * @brief Enable CRC computation on 33/17 bits + * @rmtoll CR1 CRC33_17 LL_SPI_EnableFullSizeCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CRC33_17); +} + +/** + * @brief Disable CRC computation on 33/17 bits + * @rmtoll CR1 CRC33_17 LL_SPI_DisableFullSizeCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_CRC33_17); +} + +/** + * @brief Check if Enable CRC computation on 33/17 bits is enabled + * @rmtoll CR1 CRC33_17 LL_SPI_IsEnabledFullSizeCRC + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL); +} + +/** + * @brief Suspend an ongoing transfer for Master configuration + * @rmtoll CR1 CSUSP LL_SPI_SuspendMasterTransfer + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CSUSP); +} + +/** + * @brief Start effective transfer on wire for Master configuration + * @rmtoll CR1 CSTART LL_SPI_StartMasterTransfer + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CSTART); +} + +/** + * @brief Check if there is an unfinished master transfer + * @rmtoll CR1 CSTART LL_SPI_IsActiveMasterTransfer + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL); +} + +/** + * @brief Enable Master Rx auto suspend in case of overrun + * @rmtoll CR1 MASRX LL_SPI_EnableMasterRxAutoSuspend + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_MASRX); +} + +/** + * @brief Disable Master Rx auto suspend in case of overrun + * @rmtoll CR1 MASRX LL_SPI_DisableMasterRxAutoSuspend + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_MASRX); +} + +/** + * @brief Check if Master Rx auto suspend is activated + * @rmtoll CR1 MASRX LL_SPI_IsEnabledMasterRxAutoSuspend + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL); +} + +/** + * @brief Set Underrun behavior + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 UDRCFG LL_SPI_SetUDRConfiguration + * @param SPIx SPI Instance + * @param UDRConfig This parameter can be one of the following values: + * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN + * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig) +{ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig); +} + +/** + * @brief Get Underrun behavior + * @rmtoll CFG1 UDRCFG LL_SPI_GetUDRConfiguration + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN + * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED + */ +__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG)); +} + + +/** + * @brief Set Serial protocol used + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 SP LL_SPI_SetStandard + * @param SPIx SPI Instance + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard); +} + +/** + * @brief Get Serial protocol used + * @rmtoll CFG2 SP LL_SPI_GetStandard + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + */ +__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP)); +} + +/** + * @brief Set Clock phase + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 CPHA LL_SPI_SetClockPhase + * @param SPIx SPI Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPHA, ClockPhase); +} + +/** + * @brief Get Clock phase + * @rmtoll CFG2 CPHA LL_SPI_GetClockPhase + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA)); +} + +/** + * @brief Set Clock polarity + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 CPOL LL_SPI_SetClockPolarity + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPOL, ClockPolarity); +} + +/** + * @brief Get Clock polarity + * @rmtoll CFG2 CPOL LL_SPI_GetClockPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL)); +} + +/** + * @brief Set NSS polarity + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 SSIOP LL_SPI_SetNSSPolarity + * @param SPIx SPI Instance + * @param NSSPolarity This parameter can be one of the following values: + * @arg @ref LL_SPI_NSS_POLARITY_LOW + * @arg @ref LL_SPI_NSS_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolarity) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSIOP, NSSPolarity); +} + +/** + * @brief Get NSS polarity + * @rmtoll CFG2 SSIOP LL_SPI_GetNSSPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_NSS_POLARITY_LOW + * @arg @ref LL_SPI_NSS_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP)); +} + +/** + * @brief Set Baudrate Prescaler + * @note This configuration can not be changed when SPI is enabled. + * SPI BaudRate = fPCLK/Pescaler. + * @rmtoll CFG1 MBR LL_SPI_SetBaudRatePrescaler\n + * CFG1 BPASS LL_SPI_SetBaudRatePrescaler + * @param SPIx SPI Instance + * @param Baudrate This parameter can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate) +{ + MODIFY_REG(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS), Baudrate); +} + +/** + * @brief Get Baudrate Prescaler + * @rmtoll CFG1 MBR LL_SPI_GetBaudRatePrescaler\n + * CFG1 BPASS LL_SPI_GetBaudRatePrescaler + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS))); +} + +/** + * @brief Set Transfer Bit Order + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 LSBFRST LL_SPI_SetTransferBitOrder + * @param SPIx SPI Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_LSBFRST, BitOrder); +} + +/** + * @brief Get Transfer Bit Order + * @rmtoll CFG2 LSBFRST LL_SPI_GetTransferBitOrder + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST)); +} + +/** + * @brief Set Transfer Mode + * @note This configuration can not be changed when SPI is enabled except for half duplex direction + * using LL_SPI_SetHalfDuplexDirection. + * @rmtoll CR1 HDDIR LL_SPI_SetTransferDirection\n + * CFG2 COMM LL_SPI_SetTransferDirection + * @param SPIx SPI Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_TX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, TransferDirection & SPI_CR1_HDDIR); + MODIFY_REG(SPIx->CFG2, SPI_CFG2_COMM, TransferDirection & SPI_CFG2_COMM); +} + +/** + * @brief Get Transfer Mode + * @rmtoll CR1 HDDIR LL_SPI_GetTransferDirection\n + * CFG2 COMM LL_SPI_GetTransferDirection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_TX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) +{ + uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR); + uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM); + return (Hddir | Comm); +} + +/** + * @brief Set direction for Half-Duplex Mode + * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex. + * @rmtoll CR1 HDDIR LL_SPI_SetHalfDuplexDirection + * @param SPIx SPI Instance + * @param HalfDuplexDirection This parameter can be one of the following values: + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, HalfDuplexDirection & SPI_CR1_HDDIR); +} + +/** + * @brief Get direction for Half-Duplex Mode + * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex. + * @rmtoll CR1 HDDIR LL_SPI_GetHalfDuplexDirection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + */ +__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM); +} + +/** + * @brief Set Frame Data Size + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 DSIZE LL_SPI_SetDataWidth + * @param SPIx SPI Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_4BIT + * @arg @ref LL_SPI_DATAWIDTH_5BIT + * @arg @ref LL_SPI_DATAWIDTH_6BIT + * @arg @ref LL_SPI_DATAWIDTH_7BIT + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_9BIT + * @arg @ref LL_SPI_DATAWIDTH_10BIT + * @arg @ref LL_SPI_DATAWIDTH_11BIT + * @arg @ref LL_SPI_DATAWIDTH_12BIT + * @arg @ref LL_SPI_DATAWIDTH_13BIT + * @arg @ref LL_SPI_DATAWIDTH_14BIT + * @arg @ref LL_SPI_DATAWIDTH_15BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + * @arg @ref LL_SPI_DATAWIDTH_17BIT + * @arg @ref LL_SPI_DATAWIDTH_18BIT + * @arg @ref LL_SPI_DATAWIDTH_19BIT + * @arg @ref LL_SPI_DATAWIDTH_20BIT + * @arg @ref LL_SPI_DATAWIDTH_21BIT + * @arg @ref LL_SPI_DATAWIDTH_22BIT + * @arg @ref LL_SPI_DATAWIDTH_23BIT + * @arg @ref LL_SPI_DATAWIDTH_24BIT + * @arg @ref LL_SPI_DATAWIDTH_25BIT + * @arg @ref LL_SPI_DATAWIDTH_26BIT + * @arg @ref LL_SPI_DATAWIDTH_27BIT + * @arg @ref LL_SPI_DATAWIDTH_28BIT + * @arg @ref LL_SPI_DATAWIDTH_29BIT + * @arg @ref LL_SPI_DATAWIDTH_30BIT + * @arg @ref LL_SPI_DATAWIDTH_31BIT + * @arg @ref LL_SPI_DATAWIDTH_32BIT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) +{ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth); +} + +/** + * @brief Get Frame Data Size + * @rmtoll CFG1 DSIZE LL_SPI_GetDataWidth + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_4BIT + * @arg @ref LL_SPI_DATAWIDTH_5BIT + * @arg @ref LL_SPI_DATAWIDTH_6BIT + * @arg @ref LL_SPI_DATAWIDTH_7BIT + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_9BIT + * @arg @ref LL_SPI_DATAWIDTH_10BIT + * @arg @ref LL_SPI_DATAWIDTH_11BIT + * @arg @ref LL_SPI_DATAWIDTH_12BIT + * @arg @ref LL_SPI_DATAWIDTH_13BIT + * @arg @ref LL_SPI_DATAWIDTH_14BIT + * @arg @ref LL_SPI_DATAWIDTH_15BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + * @arg @ref LL_SPI_DATAWIDTH_17BIT + * @arg @ref LL_SPI_DATAWIDTH_18BIT + * @arg @ref LL_SPI_DATAWIDTH_19BIT + * @arg @ref LL_SPI_DATAWIDTH_20BIT + * @arg @ref LL_SPI_DATAWIDTH_21BIT + * @arg @ref LL_SPI_DATAWIDTH_22BIT + * @arg @ref LL_SPI_DATAWIDTH_23BIT + * @arg @ref LL_SPI_DATAWIDTH_24BIT + * @arg @ref LL_SPI_DATAWIDTH_25BIT + * @arg @ref LL_SPI_DATAWIDTH_26BIT + * @arg @ref LL_SPI_DATAWIDTH_27BIT + * @arg @ref LL_SPI_DATAWIDTH_28BIT + * @arg @ref LL_SPI_DATAWIDTH_29BIT + * @arg @ref LL_SPI_DATAWIDTH_30BIT + * @arg @ref LL_SPI_DATAWIDTH_31BIT + * @arg @ref LL_SPI_DATAWIDTH_32BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE)); +} + +/** + * @brief Set threshold of FIFO that triggers a transfer event + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 FTHLV LL_SPI_SetFIFOThreshold + * @param SPIx SPI Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_SPI_FIFO_TH_01DATA + * @arg @ref LL_SPI_FIFO_TH_02DATA + * @arg @ref LL_SPI_FIFO_TH_03DATA + * @arg @ref LL_SPI_FIFO_TH_04DATA + * @arg @ref LL_SPI_FIFO_TH_05DATA + * @arg @ref LL_SPI_FIFO_TH_06DATA + * @arg @ref LL_SPI_FIFO_TH_07DATA + * @arg @ref LL_SPI_FIFO_TH_08DATA + * @arg @ref LL_SPI_FIFO_TH_09DATA + * @arg @ref LL_SPI_FIFO_TH_10DATA + * @arg @ref LL_SPI_FIFO_TH_11DATA + * @arg @ref LL_SPI_FIFO_TH_12DATA + * @arg @ref LL_SPI_FIFO_TH_13DATA + * @arg @ref LL_SPI_FIFO_TH_14DATA + * @arg @ref LL_SPI_FIFO_TH_15DATA + * @arg @ref LL_SPI_FIFO_TH_16DATA + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) +{ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold); +} + +/** + * @brief Get threshold of FIFO that triggers a transfer event + * @rmtoll CFG1 FTHLV LL_SPI_GetFIFOThreshold + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_FIFO_TH_01DATA + * @arg @ref LL_SPI_FIFO_TH_02DATA + * @arg @ref LL_SPI_FIFO_TH_03DATA + * @arg @ref LL_SPI_FIFO_TH_04DATA + * @arg @ref LL_SPI_FIFO_TH_05DATA + * @arg @ref LL_SPI_FIFO_TH_06DATA + * @arg @ref LL_SPI_FIFO_TH_07DATA + * @arg @ref LL_SPI_FIFO_TH_08DATA + * @arg @ref LL_SPI_FIFO_TH_09DATA + * @arg @ref LL_SPI_FIFO_TH_10DATA + * @arg @ref LL_SPI_FIFO_TH_11DATA + * @arg @ref LL_SPI_FIFO_TH_12DATA + * @arg @ref LL_SPI_FIFO_TH_13DATA + * @arg @ref LL_SPI_FIFO_TH_14DATA + * @arg @ref LL_SPI_FIFO_TH_15DATA + * @arg @ref LL_SPI_FIFO_TH_16DATA + */ +__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV)); +} + +/** + * @brief Enable CRC + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 CRCEN LL_SPI_EnableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); +} + +/** + * @brief Disable CRC + * @rmtoll CFG1 CRCEN LL_SPI_DisableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); +} + +/** + * @brief Check if CRC is enabled + * @rmtoll CFG1 CRCEN LL_SPI_IsEnabledCRC + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL); +} + +/** + * @brief Set CRC Length + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 CRCSIZE LL_SPI_SetCRCWidth + * @param SPIx SPI Instance + * @param CRCLength This parameter can be one of the following values: + * @arg @ref LL_SPI_CRC_4BIT + * @arg @ref LL_SPI_CRC_5BIT + * @arg @ref LL_SPI_CRC_6BIT + * @arg @ref LL_SPI_CRC_7BIT + * @arg @ref LL_SPI_CRC_8BIT + * @arg @ref LL_SPI_CRC_9BIT + * @arg @ref LL_SPI_CRC_10BIT + * @arg @ref LL_SPI_CRC_11BIT + * @arg @ref LL_SPI_CRC_12BIT + * @arg @ref LL_SPI_CRC_13BIT + * @arg @ref LL_SPI_CRC_14BIT + * @arg @ref LL_SPI_CRC_15BIT + * @arg @ref LL_SPI_CRC_16BIT + * @arg @ref LL_SPI_CRC_17BIT + * @arg @ref LL_SPI_CRC_18BIT + * @arg @ref LL_SPI_CRC_19BIT + * @arg @ref LL_SPI_CRC_20BIT + * @arg @ref LL_SPI_CRC_21BIT + * @arg @ref LL_SPI_CRC_22BIT + * @arg @ref LL_SPI_CRC_23BIT + * @arg @ref LL_SPI_CRC_24BIT + * @arg @ref LL_SPI_CRC_25BIT + * @arg @ref LL_SPI_CRC_26BIT + * @arg @ref LL_SPI_CRC_27BIT + * @arg @ref LL_SPI_CRC_28BIT + * @arg @ref LL_SPI_CRC_29BIT + * @arg @ref LL_SPI_CRC_30BIT + * @arg @ref LL_SPI_CRC_31BIT + * @arg @ref LL_SPI_CRC_32BIT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) +{ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength); +} + +/** + * @brief Get CRC Length + * @rmtoll CFG1 CRCSIZE LL_SPI_GetCRCWidth + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_CRC_4BIT + * @arg @ref LL_SPI_CRC_5BIT + * @arg @ref LL_SPI_CRC_6BIT + * @arg @ref LL_SPI_CRC_7BIT + * @arg @ref LL_SPI_CRC_8BIT + * @arg @ref LL_SPI_CRC_9BIT + * @arg @ref LL_SPI_CRC_10BIT + * @arg @ref LL_SPI_CRC_11BIT + * @arg @ref LL_SPI_CRC_12BIT + * @arg @ref LL_SPI_CRC_13BIT + * @arg @ref LL_SPI_CRC_14BIT + * @arg @ref LL_SPI_CRC_15BIT + * @arg @ref LL_SPI_CRC_16BIT + * @arg @ref LL_SPI_CRC_17BIT + * @arg @ref LL_SPI_CRC_18BIT + * @arg @ref LL_SPI_CRC_19BIT + * @arg @ref LL_SPI_CRC_20BIT + * @arg @ref LL_SPI_CRC_21BIT + * @arg @ref LL_SPI_CRC_22BIT + * @arg @ref LL_SPI_CRC_23BIT + * @arg @ref LL_SPI_CRC_24BIT + * @arg @ref LL_SPI_CRC_25BIT + * @arg @ref LL_SPI_CRC_26BIT + * @arg @ref LL_SPI_CRC_27BIT + * @arg @ref LL_SPI_CRC_28BIT + * @arg @ref LL_SPI_CRC_29BIT + * @arg @ref LL_SPI_CRC_30BIT + * @arg @ref LL_SPI_CRC_31BIT + * @arg @ref LL_SPI_CRC_32BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE)); +} + +/** + * @brief Set NSS Mode + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 SSM LL_SPI_SetNSSMode\n + * CFG2 SSOE LL_SPI_SetNSSMode + * @param SPIx SPI Instance + * @param NSS This parameter can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE, NSS); +} + +/** + * @brief Set NSS Mode + * @rmtoll CFG2 SSM LL_SPI_GetNSSMode\n + * CFG2 SSOE LL_SPI_GetNSSMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + */ +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE)); +} + +/** + * @brief Enable NSS pulse mgt + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 SSOM LL_SPI_EnableNSSPulseMgt + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM); +} + +/** + * @brief Disable NSS pulse mgt + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 SSOM LL_SPI_DisableNSSPulseMgt + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG2, SPI_CFG2_SSOM); +} + +/** + * @brief Check if NSS pulse is enabled + * @rmtoll CFG2 SSOM LL_SPI_IsEnabledNSSPulse + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if there is enough data in FIFO to read a full packet + * @rmtoll SR RXP LL_SPI_IsActiveFlag_RXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL); +} + +/** + * @brief Check if there is enough space in FIFO to hold a full packet + * @rmtoll SR TXP LL_SPI_IsActiveFlag_TXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL); +} + +/** + * @brief Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet + * @rmtoll SR DXP LL_SPI_IsActiveFlag_DXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL); +} + +/** + * @brief Check that end of transfer event occurred + * @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL); +} + +/** + * @brief Check that all required data has been filled in the fifo according to transfer size + * @rmtoll SR TXTF LL_SPI_IsActiveFlag_TXTF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL); +} + +/** + * @brief Get Underrun error flag + * @rmtoll SR UDR LL_SPI_IsActiveFlag_UDR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); +} + +/** + * @brief Get CRC error flag + * @rmtoll SR CRCE LL_SPI_IsActiveFlag_CRCERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL); +} + +/** + * @brief Get Mode fault error flag + * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); +} + +/** + * @brief Get Overrun error flag + * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get TI Frame format error flag + * @rmtoll SR TIFRE LL_SPI_IsActiveFlag_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL); +} + +/** + * @brief Check if a suspend operation is done + * @rmtoll SR SUSP LL_SPI_IsActiveFlag_SUSP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL); +} + +/** + * @brief Check if last TxFIFO or CRC frame transmission is completed + * @rmtoll SR TXC LL_SPI_IsActiveFlag_TXC + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL); +} + +/** + * @brief Check if at least one 32-bit data is available in RxFIFO + * @rmtoll SR RXWNE LL_SPI_IsActiveFlag_RXWNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL); +} + +/** + * @brief Get number of data framed remaining in current TSIZE + * @rmtoll SR CTSIZE LL_SPI_GetRemainingDataFrames + * @param SPIx SPI Instance + * @retval 0..0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos); +} + +/** + * @brief Get RxFIFO packing Level + * @rmtoll SR RXPLVL LL_SPI_GetRxFIFOPackingLevel + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_RX_FIFO_0PACKET + * @arg @ref LL_SPI_RX_FIFO_1PACKET + * @arg @ref LL_SPI_RX_FIFO_2PACKET + * @arg @ref LL_SPI_RX_FIFO_3PACKET + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL)); +} + +/** + * @brief Clear End Of Transfer flag + * @rmtoll IFCR EOTC LL_SPI_ClearFlag_EOT + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_EOTC); +} + +/** + * @brief Clear TXTF flag + * @rmtoll IFCR TXTFC LL_SPI_ClearFlag_TXTF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_TXTFC); +} + +/** + * @brief Clear Underrun error flag + * @rmtoll IFCR UDRC LL_SPI_ClearFlag_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_UDRC); +} + +/** + * @brief Clear Overrun error flag + * @rmtoll IFCR OVRC LL_SPI_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_OVRC); +} + +/** + * @brief Clear CRC error flag + * @rmtoll IFCR CRCEC LL_SPI_ClearFlag_CRCERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_CRCEC); +} + +/** + * @brief Clear Mode fault error flag + * @rmtoll IFCR MODFC LL_SPI_ClearFlag_MODF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_MODFC); +} + +/** + * @brief Clear Frame format error flag + * @rmtoll IFCR TIFREC LL_SPI_ClearFlag_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_TIFREC); +} + +/** + * @brief Clear SUSP flag + * @rmtoll IFCR SUSPC LL_SPI_ClearFlag_SUSP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_SUSPC); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Rx Packet available IT + * @rmtoll IER RXPIE LL_SPI_EnableIT_RXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXPIE); +} + +/** + * @brief Enable Tx Packet space available IT + * @rmtoll IER TXPIE LL_SPI_EnableIT_TXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXPIE); +} + +/** + * @brief Enable Duplex Packet available IT + * @rmtoll IER DXPIE LL_SPI_EnableIT_DXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_DXPIE); +} + +/** + * @brief Enable End Of Transfer IT + * @rmtoll IER EOTIE LL_SPI_EnableIT_EOT + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_EOTIE); +} + +/** + * @brief Enable TXTF IT + * @rmtoll IER TXTFIE LL_SPI_EnableIT_TXTF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXTFIE); +} + +/** + * @brief Enable Underrun IT + * @rmtoll IER UDRIE LL_SPI_EnableIT_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_UDRIE); +} + +/** + * @brief Enable Overrun IT + * @rmtoll IER OVRIE LL_SPI_EnableIT_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_OVRIE); +} + +/** + * @brief Enable CRC Error IT + * @rmtoll IER CRCEIE LL_SPI_EnableIT_CRCERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_CRCEIE); +} + +/** + * @brief Enable TI Frame Format Error IT + * @rmtoll IER TIFREIE LL_SPI_EnableIT_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TIFREIE); +} + +/** + * @brief Enable MODF IT + * @rmtoll IER MODFIE LL_SPI_EnableIT_MODF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_MODFIE); +} + +/** + * @brief Disable Rx Packet available IT + * @rmtoll IER RXPIE LL_SPI_DisableIT_RXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_RXPIE); +} + +/** + * @brief Disable Tx Packet space available IT + * @rmtoll IER TXPIE LL_SPI_DisableIT_TXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_TXPIE); +} + +/** + * @brief Disable Duplex Packet available IT + * @rmtoll IER DXPIE LL_SPI_DisableIT_DXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_DXPIE); +} + +/** + * @brief Disable End Of Transfer IT + * @rmtoll IER EOTIE LL_SPI_DisableIT_EOT + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_EOTIE); +} + +/** + * @brief Disable TXTF IT + * @rmtoll IER TXTFIE LL_SPI_DisableIT_TXTF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_TXTFIE); +} + +/** + * @brief Disable Underrun IT + * @rmtoll IER UDRIE LL_SPI_DisableIT_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_UDRIE); +} + +/** + * @brief Disable Overrun IT + * @rmtoll IER OVRIE LL_SPI_DisableIT_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_OVRIE); +} + +/** + * @brief Disable CRC Error IT + * @rmtoll IER CRCEIE LL_SPI_DisableIT_CRCERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_CRCEIE); +} + +/** + * @brief Disable TI Frame Format Error IT + * @rmtoll IER TIFREIE LL_SPI_DisableIT_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_TIFREIE); +} + +/** + * @brief Disable MODF IT + * @rmtoll IER MODFIE LL_SPI_DisableIT_MODF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_MODFIE); +} + +/** + * @brief Check if Rx Packet available IT is enabled + * @rmtoll IER RXPIE LL_SPI_IsEnabledIT_RXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx Packet space available IT is enabled + * @rmtoll IER TXPIE LL_SPI_IsEnabledIT_TXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Duplex Packet available IT is enabled + * @rmtoll IER DXPIE LL_SPI_IsEnabledIT_DXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if End Of Transfer IT is enabled + * @rmtoll IER EOTIE LL_SPI_IsEnabledIT_EOT + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if TXTF IT is enabled + * @rmtoll IER TXTFIE LL_SPI_IsEnabledIT_TXTF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Underrun IT is enabled + * @rmtoll IER UDRIE LL_SPI_IsEnabledIT_UDR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Overrun IT is enabled + * @rmtoll IER OVRIE LL_SPI_IsEnabledIT_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if CRC Error IT is enabled + * @rmtoll IER CRCEIE LL_SPI_IsEnabledIT_CRCERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if TI Frame Format Error IT is enabled + * @rmtoll IER TIFREIE LL_SPI_IsEnabledIT_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if MODF IT is enabled + * @rmtoll IER MODFIE LL_SPI_IsEnabledIT_MODF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CFG1 RXDMAEN LL_SPI_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CFG1 RXDMAEN LL_SPI_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CFG1 RXDMAEN LL_SPI_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CFG1 TXDMAEN LL_SPI_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CFG1 TXDMAEN LL_SPI_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CFG1 TXDMAEN LL_SPI_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL); +} +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll TXDR TXDR LL_SPI_DMA_GetTxRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(const SPI_TypeDef *SPIx) +{ + return (uint32_t) &(SPIx->TXDR); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll RXDR RXDR LL_SPI_DMA_GetRxRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(const SPI_TypeDef *SPIx) +{ + return (uint32_t) &(SPIx->RXDR); +} +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DATA_Management DATA_Management + * @{ + */ + +/** + * @brief Read Data Register + * @rmtoll RXDR . LL_SPI_ReceiveData8 + * @param SPIx SPI Instance + * @retval 0..0xFF + */ +__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */ +{ + return (*((__IO uint8_t *)&SPIx->RXDR)); +} + +/** + * @brief Read Data Register + * @rmtoll RXDR . LL_SPI_ReceiveData16 + * @param SPIx SPI Instance + * @retval 0..0xFFFF + */ +__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */ +{ +#if defined (__GNUC__) + __IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR)); + return (*spirxdr); +#else + return (*((__IO uint16_t *)&SPIx->RXDR)); +#endif /* __GNUC__ */ +} + +/** + * @brief Read Data Register + * @rmtoll RXDR . LL_SPI_ReceiveData32 + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */ +{ + return (*((__IO uint32_t *)&SPIx->RXDR)); +} + +/** + * @brief Write Data Register + * @rmtoll TXDR . LL_SPI_TransmitData8 + * @param SPIx SPI Instance + * @param TxData 0..0xFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) +{ + *((__IO uint8_t *)&SPIx->TXDR) = TxData; +} + +/** + * @brief Write Data Register + * @rmtoll TXDR . LL_SPI_TransmitData16 + * @param SPIx SPI Instance + * @param TxData 0..0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ +#if defined (__GNUC__) + __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR); + *spitxdr = TxData; +#else + *((__IO uint16_t *)&SPIx->TXDR) = TxData; +#endif /* __GNUC__ */ +} + +/** + * @brief Write Data Register + * @rmtoll TXDR . LL_SPI_TransmitData32 + * @param SPIx SPI Instance + * @param TxData 0..0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData) +{ + *((__IO uint32_t *)&SPIx->TXDR) = TxData; +} + +/** + * @brief Set polynomial for CRC calcul + * @rmtoll CRCPOLY CRCPOLY LL_SPI_SetCRCPolynomial + * @param SPIx SPI Instance + * @param CRCPoly 0..0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) +{ + WRITE_REG(SPIx->CRCPOLY, CRCPoly); +} + +/** + * @brief Get polynomial for CRC calcul + * @rmtoll CRCPOLY CRCPOLY LL_SPI_GetCRCPolynomial + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->CRCPOLY)); +} + +/** + * @brief Set the underrun pattern + * @rmtoll UDRDR UDRDR LL_SPI_SetUDRPattern + * @param SPIx SPI Instance + * @param Pattern 0..0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern) +{ + WRITE_REG(SPIx->UDRDR, Pattern); +} + +/** + * @brief Get the underrun pattern + * @rmtoll UDRDR UDRDR LL_SPI_GetUDRPattern + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->UDRDR)); +} + +/** + * @brief Get Rx CRC + * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->RXCRC)); +} + +/** + * @brief Get Tx CRC + * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->TXCRC)); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_AutonomousMode Configuration functions related to Autonomous mode feature + * @{ + */ + +/** + * @brief Enable Selected Trigger + * @rmtoll AUTOCR TRIGEN LL_SPI_Enable_SelectedTrigger + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void LL_SPI_Enable_SelectedTrigger(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN); +} + +/** + * @brief Disable Selected Trigger + * @rmtoll AUTOCR TRIGEN LL_SPI_Disable_SelectedTrigger + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void LL_SPI_Disable_SelectedTrigger(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN); +} + +/** + * @brief Indicate if selected Trigger is disabled or enabled + * @rmtoll AUTOCR TRIGEN LL_SPI_IsEnabled_SelectedTrigger + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabled_SelectedTrigger(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN) == (SPI_AUTOCR_TRIGEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the trigger polarity + * @rmtoll AUTOCR TRIGPOL LL_SPI_SetTriggerPolarity + * @param SPIx SPI Instance. + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_SPI_TRIG_POLARITY_RISING + * @arg @ref LL_SPI_TRIG_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTriggerPolarity(SPI_TypeDef *SPIx, uint32_t Polarity) +{ + MODIFY_REG(SPIx->AUTOCR, SPI_AUTOCR_TRIGPOL, Polarity); +} + +/** + * @brief Get the trigger polarity + * @rmtoll AUTOCR TRIGPOL LL_SPI_GetTriggerPolarity + * @param SPIx SPI Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_TRIG_POLARITY_RISING + * @arg @ref LL_SPI_TRIG_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_SPI_GetTriggerPolarity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGPOL)); +} + +/** + * @brief Set the selected trigger + * @rmtoll AUTOCR TRIGSEL LL_SPI_SetSelectedTrigger + * @param SPIx SPI Instance. + * @param Trigger This parameter can be one of the following values: + * @arg @ref LL_SPI_GRP1_GPDMA_CH0_TCF_TRG + * @arg @ref LL_SPI_GRP1_GPDMA_CH1_TCF_TRG + * @arg @ref LL_SPI_GRP1_GPDMA_CH2_TCF_TRG + * @arg @ref LL_SPI_GRP1_GPDMA_CH3_TCF_TRG + * @arg @ref LL_SPI_GRP1_EXTI4_TRG + * @arg @ref LL_SPI_GRP1_EXTI9_TRG + * @arg @ref LL_SPI_GRP1_LPTIM1_CH1_TRG + * @arg @ref LL_SPI_GRP1_LPTIM2_CH1_TRG + * @arg @ref LL_SPI_GRP1_COMP1_TRG + * @arg @ref LL_SPI_GRP1_COMP2_TRG + * @arg @ref LL_SPI_GRP1_RTC_ALRA_TRG + * @arg @ref LL_SPI_GRP1_RTC_WUT_TRG + * @arg @ref LL_SPI_GRP2_LPDMA_CH0_TCF_TRG + * @arg @ref LL_SPI_GRP2_LPDMA_CH1_TCF_TRG + * @arg @ref LL_SPI_GRP2_LPDMA_CH2_TCF_TRG + * @arg @ref LL_SPI_GRP2_LPDMA_CH3_TCF_TRG + * @arg @ref LL_SPI_GRP2_EXTI4_TRG + * @arg @ref LL_SPI_GRP2_EXTI8_TRG + * @arg @ref LL_SPI_GRP2_LPTIM1_CH1_TRG + * @arg @ref LL_SPI_GRP2_LPTIM3_CH1_TRG + * @arg @ref LL_SPI_GRP2_COMP1_TRG + * @arg @ref LL_SPI_GRP2_COMP2_TRG + * @arg @ref LL_SPI_GRP2_RTC_ALRA_TRG + * @arg @ref LL_SPI_GRP2_RTC_WUT_TRG + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetSelectedTrigger(SPI_TypeDef *SPIx, uint32_t Trigger) +{ + MODIFY_REG(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL, (Trigger & SPI_AUTOCR_TRIGSEL_Msk)); +} + +/** + * @brief Get the selected trigger + * @rmtoll AUTOCR TRIGSEL LL_SPI_GetSelectedTrigger + * @param SPIx SPI Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_GRP1_GPDMA_CH0_TCF_TRG + * @arg @ref LL_SPI_GRP1_GPDMA_CH1_TCF_TRG + * @arg @ref LL_SPI_GRP1_GPDMA_CH2_TCF_TRG + * @arg @ref LL_SPI_GRP1_GPDMA_CH3_TCF_TRG + * @arg @ref LL_SPI_GRP1_EXTI4_TRG + * @arg @ref LL_SPI_GRP1_EXTI9_TRG + * @arg @ref LL_SPI_GRP1_LPTIM1_CH1_TRG + * @arg @ref LL_SPI_GRP1_LPTIM2_CH1_TRG + * @arg @ref LL_SPI_GRP1_COMP1_TRG + * @arg @ref LL_SPI_GRP1_COMP2_TRG + * @arg @ref LL_SPI_GRP1_RTC_ALRA_TRG + * @arg @ref LL_SPI_GRP1_RTC_WUT_TRG + * @arg @ref LL_SPI_GRP2_LPDMA_CH0_TCF_TRG + * @arg @ref LL_SPI_GRP2_LPDMA_CH1_TCF_TRG + * @arg @ref LL_SPI_GRP2_LPDMA_CH2_TCF_TRG + * @arg @ref LL_SPI_GRP2_LPDMA_CH3_TCF_TRG + * @arg @ref LL_SPI_GRP2_EXTI4_TRG + * @arg @ref LL_SPI_GRP2_EXTI8_TRG + * @arg @ref LL_SPI_GRP2_LPTIM1_CH1_TRG + * @arg @ref LL_SPI_GRP2_LPTIM3_CH1_TRG + * @arg @ref LL_SPI_GRP2_COMP1_TRG + * @arg @ref LL_SPI_GRP2_COMP2_TRG + * @arg @ref LL_SPI_GRP2_RTC_ALRA_TRG + * @arg @ref LL_SPI_GRP2_RTC_WUT_TRG + */ +__STATIC_INLINE uint32_t LL_SPI_GetSelectedTrigger(const SPI_TypeDef *SPIx) +{ +#if defined(LL_SPI_TRIG_GRP2) + if (IS_LL_SPI_GRP2_INSTANCE(SPIx)) + { + return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP2)); + } + else + { + return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP1)); + } +#else + return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP1)); +#endif /* LL_SPI_TRIG_GRP2 */ +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); +void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ +/** + * @} + */ +/** + * @} + */ + + +#endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_LL_SPI_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h new file mode 100644 index 000000000..275a4da59 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h @@ -0,0 +1,2316 @@ +/** + ****************************************************************************** + * @file stm32u5xx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + (+) Access to VREFBUF registers + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_LL_SYSTEM_H +#define STM32U5xx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx.h" + +/** @addtogroup STM32U5xx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ + +/** + * @brief Power-down in Run mode Flash key + */ +#define LL_FLASH_PDKEY1_1 0x04152637U /*!< Flash Bank1 power down key1 */ +#define LL_FLASH_PDKEY1_2 0xFAFBFCFDU /*!< Flash Bank1 power down key2: used with FLASH_PDKEY1 + to unlock the RUN_PD bit in FLASH_ACR */ + +#define LL_FLASH_PDKEY2_1 0x40516273U /*!< Flash Bank2 power down key1 */ +#define LL_FLASH_PDKEY2_2 0xAFBFCFDFU /*!< Flash Bank2 power down key2: used with FLASH_PDKEY2_1 + to unlock the RUN_PD bit in FLASH_ACR */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_CS1 SYSCFG Vdd compensation cell Code selection + * @{ + */ +#define LL_SYSCFG_VDD_CELL_CODE 0U /*VDD I/Os code from the cell + (available in the SYSCFG_CCVR)*/ +#define LL_SYSCFG_VDD_REGISTER_CODE SYSCFG_CCCSR_CS1 /*VDD I/Os code from the SYSCFG compensation + cell code register (SYSCFG_CCCR)*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_CS2 SYSCFG VddIO2 compensation cell Code selection + * @{ + */ +#define LL_SYSCFG_VDDIO2_CELL_CODE 0U /*VDDIO2 I/Os code from the cell + (available in the SYSCFG_CCVR)*/ +#define LL_SYSCFG_VDDIO2_REGISTER_CODE SYSCFG_CCCSR_CS2 /*VDDIO2 I/Os code from the SYSCFG compensation + cell code register (SYSCFG_CCCR)*/ +/** + * @} + */ + +#if defined(SYSCFG_CCCSR_CS3) +/** @defgroup SYSTEM_LL_EC_CS3 SYSCFG VddHSPI compensation cell Code selection + * @{ + */ +#define LL_SYSCFG_VDDHSPI_CELL_CODE 0U /*VDD HSPI I/Os code from the cell + (available in the SYSCFG_CCVR)*/ +#define LL_SYSCFG_VDDHSPI_REGISTER_CODE SYSCFG_CCCSR_CS3 /*VDD HSPI I/Os code from the SYSCFG compensation + cell code register (SYSCFG_CCCR)*/ +/** + * @} + */ +#endif /* SYSCFG_CCCSR_CS3 */ + +/** @defgroup SYSTEM_LL_EC_ERASE_MEMORIES_STATUS SYSCFG MEMORIES ERASE STATUS + * @{ + */ +#define LL_SYSCFG_MEMORIES_ERASE_ON_GOING 0U /*Memory erase on going*/ +#define LL_SYSCFG_MEMORIES_ERASE_ENDED SYSCFG_MESR_MCLR /*Memory erase done */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_FASTMODEPLUS SYSCFG FASTMODEPLUS + * @{ + */ +#define LL_SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define LL_SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define LL_SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define LL_SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +/** + * @} + */ + +#if defined(SYSCFG_CFGR1_ENDCAP) +/** @defgroup SYSTEM_LL_DECOUPLING_CAPACITANCE SYSCFG DECOUPLING CAPACITANCE + * @{ + */ +#define LL_SYSCFG_HSPI_CAPACITANCE_OFF 0x00000000U /*!< Decoupling with no capacitance value on HSPI supply */ +#define LL_SYSCFG_HSPI_CAPACITANCE_1_DIV_3 SYSCFG_CFGR1_ENDCAP_0 /*!< Decoupling with 1/3 of capacitance value on HSPI supply */ +#define LL_SYSCFG_HSPI_CAPACITANCE_2_DIV_3 SYSCFG_CFGR1_ENDCAP_1 /*!< Decoupling with 2/3 of capacitance value on HSPI supply */ +#define LL_SYSCFG_HSPI_CAPACITANCE_FULL SYSCFG_CFGR1_ENDCAP /*!< Decoupling with full capacitance value on HSPI supply */ +/** + * @} + */ +#endif /* SYSCFG_CFGR1_ENDCAP */ + +/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK + * @{ + */ +#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal + with Break Input of TIM1/8/15/16/17 */ +#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection + with TIM1/8/15/16/17 Break Input and also the PVDE + and PLS bits of the Power Control Interface */ +#define LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM ECC double error signal + with Break Input of TIM1/8/15/16/17 */ +#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM33 + with Break Input of TIM1/15/16/17 */ +/** + * @} + */ + +#if defined(SYSCFG_OTGHSPHYCR_CLKSEL) +/** @defgroup SYSTEM_LL_OTG_PHY_CLOCK_FREQUENCY SYSCFG OTG High-speed (HS) PHY reference clock frequency selection + * @{ + */ +#define LL_SYSCFG_OTGHSPHY_CLK_16MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1) /*!< Reference clock freqeuncy is 16 Mhz */ +#define LL_SYSCFG_OTGHSPHY_CLK_19_2MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< Reference clock freqeuncy is 19.2 Mhz */ +#define LL_SYSCFG_OTGHSPHY_CLK_20MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< Reference clock freqeuncy is 20 Mhz */ +#define LL_SYSCFG_OTGHSPHY_CLK_24MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< Reference clock freqeuncy is 24 Mhz */ +#define LL_SYSCFG_OTGHSPHY_CLK_26MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_2 | \ + SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< Reference clock freqeuncy is 26 Mhz */ +#define LL_SYSCFG_OTGHSPHY_CLK_32MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | \ + SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< Reference clock freqeuncy is 32 Mhz */ +/** + * @} + */ +#endif /* SYSCFG_OTGHSPHYCR_CLKSEL */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE) +/** @defgroup SYSTEM_LL_OTG_PHYTUNER_DISCONNECT_THRESTHOLD SYSCFG OTG High-speed (HS) PHYTUNER disconnnect threshold + * @{ + */ +#define LL_SYSCFG_OTGHSPHY_DISCONNECT_5_9PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1 /*!< +5.9% (recommended value) */ +#define LL_SYSCFG_OTGHSPHY_DISCONNECT_0PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0 /*!< 0% (default value) */ +/** + * @} + */ +#endif /* SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE) +/** @defgroup SYSTEM_LL_OTG_SQUELSH SYSCFG OTG High-speed (HS) PHY Squelch threshold adjustment + * @{ + */ +#define LL_SYSCFG_OTGHSPHY_SQUELCH_15PERCENT 0x00000000U /*!< +15% (recommended value) */ +#define LL_SYSCFG_OTGHSPHY_SQUELCH_0PERCENT (SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0 | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1) /*!< 0% (default value) */ +/** + * @} + */ +#endif /* SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE) +/** @defgroup SYSTEM_LL_OTG_TRANSMITTER_PREEMPHASIS_CURRENT SYSCFG OTG High-speed (HS) transmitter preemphasis current control + * @{ + */ +#define LL_SYSCFG_OTGHSPHY_PREEMP_DISABLED 0x00000000U /*!< HS transmitter preemphasis circuit disabled */ +#define LL_SYSCFG_OTGHSPHY_PREEMP_1X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */ +#define LL_SYSCFG_OTGHSPHY_PREEMP_2X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */ +#define LL_SYSCFG_OTGHSPHY_PREEMP_3X (SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | \ + SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1) /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */ +/** + * @} + */ +#endif /* SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE */ + +/** @defgroup SYSCFG_Lock_items SYSCFG Lock items + * @{ + */ +#define LL_SYSCFG_MPU_NSEC SYSCFG_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or non-secure only) */ +#define LL_SYSCFG_VTOR_NSEC SYSCFG_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or non-secure only) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define LL_SYSCFG_SAU (SYSCFG_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */ +#define LL_SYSCFG_MPU_SEC (SYSCFG_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only) */ +#define LL_SYSCFG_VTOR_AIRCR_SEC (SYSCFG_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure code only) */ +#define LL_SYSCFG_LOCK_ALL (LL_SYSCFG_MPU_NSEC | LL_SYSCFG_VTOR_NSEC | LL_SYSCFG_SAU | LL_SYSCFG_MPU_SEC | \ + LL_SYSCFG_VTOR_AIRCR_SEC) /*!< All */ +#else +#define LL_SYSCFG_LOCK_ALL (LL_SYSCFG_MPU_NSEC | LL_SYSCFG_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_SECURE_ATTRIBUTES Secure attributes + * @note Only available when system implements security (TZEN=1) + * @{ + */ +#define LL_SYSCFG_CLOCK_SEC SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock configuration secure-only access */ +#define LL_SYSCFG_CLOCK_NSEC 0U /*!< SYSCFG clock configuration secure/non-secure access */ +#define LL_SYSCFG_CLASSB_SEC SYSCFG_SECCFGR_CLASSBSEC /*!< Class B configuration secure-only access */ +#define LL_SYSCFG_CLASSB_NSEC 0U /*!< Class B configuration secure/non-secure access */ +#define LL_SYSCFG_FPU_SEC SYSCFG_SECCFGR_FPUSEC /*!< FPU configuration secure-only access */ +#define LL_SYSCFG_FPU_NSEC 0U /*!< FPU configuration secure/non-secure access */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment + * @{ + */ +#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ +#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/ +#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP2_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP /*!< The I2C4 SMBus timeout is frozen*/ +#define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP2_I2C5_STOP DBGMCU_APB1FZR2_DBG_I2C5_STOP /*!< The I2C5 SMBus timeout is frozen*/ +#define LL_DBGMCU_APB1_GRP2_I2C6_STOP DBGMCU_APB1FZR2_DBG_I2C6_STOP /*!< The I2C6 SMBus timeout is frozen*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/ +#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is halted*/ +#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is halted*/ +#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/ +#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB3_GRP1_I2C3_STOP DBGMCU_APB3FZR_DBG_I2C3_STOP /*!< The counter clock of I2C3 is stopped when the core is halted*/ +#define LL_DBGMCU_APB3_GRP1_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/ +#define LL_DBGMCU_APB3_GRP1_LPTIM3_STOP DBGMCU_APB3FZR_DBG_LPTIM3_STOP /*!< The counter clock of LPTIM3 is stopped when the core is halted*/ +#define LL_DBGMCU_APB3_GRP1_LPTIM4_STOP DBGMCU_APB3FZR_DBG_LPTIM4_STOP /*!< The counter clock of LPTIM4 is stopped when the core is halted*/ +#define LL_DBGMCU_APB3_GRP1_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP /*!< The counter clock of RTC is stopped when the core is halted*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_AHB1_GRP1_STOP_IP DBGMCU AHB1 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP DBGMCU_AHB1FZR_DBG_GPDMA0_STOP /*!< The counter clock of GPDMA0 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_STOP /*!< The counter clock of GPDMA1 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP DBGMCU_AHB1FZR_DBG_GPDMA2_STOP /*!< The counter clock of GPDMA2 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP DBGMCU_AHB1FZR_DBG_GPDMA3_STOP /*!< The counter clock of GPDMA3 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP DBGMCU_AHB1FZR_DBG_GPDMA4_STOP /*!< The counter clock of GPDMA4 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP DBGMCU_AHB1FZR_DBG_GPDMA5_STOP /*!< The counter clock of GPDMA5 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP DBGMCU_AHB1FZR_DBG_GPDMA6_STOP /*!< The counter clock of GPDMA6 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP DBGMCU_AHB1FZR_DBG_GPDMA7_STOP /*!< The counter clock of GPDMA7 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP DBGMCU_AHB1FZR_DBG_GPDMA8_STOP /*!< The counter clock of GPDMA8 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP DBGMCU_AHB1FZR_DBG_GPDMA9_STOP /*!< The counter clock of GPDMA9 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP DBGMCU_AHB1FZR_DBG_GPDMA10_STOP /*!< The counter clock of GPDMA10 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP DBGMCU_AHB1FZR_DBG_GPDMA11_STOP /*!< The counter clock of GPDMA11 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP DBGMCU_AHB1FZR_DBG_GPDMA12_STOP /*!< The counter clock of GPDMA12 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP DBGMCU_AHB1FZR_DBG_GPDMA13_STOP /*!< The counter clock of GPDMA13 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP DBGMCU_AHB1FZR_DBG_GPDMA14_STOP /*!< The counter clock of GPDMA14 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP DBGMCU_AHB1FZR_DBG_GPDMA15_STOP /*!< The counter clock of GPDMA15 is stopped when the core is halted*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_AHB3_GRP1_STOP_IP DBGMCU AHB3 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_AHB3_GRP1_LPDMA0_STOP DBGMCU_AHB3FZR_DBG_LPDMA0_STOP /*!< The counter clock of LPDMA0 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB3_GRP1_LPDMA1_STOP DBGMCU_AHB3FZR_DBG_LPDMA1_STOP /*!< The counter clock of LPDMA1 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB3_GRP1_LPDMA2_STOP DBGMCU_AHB3FZR_DBG_LPDMA2_STOP /*!< The counter clock of LPDMA2 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB3_GRP1_LPDMA3_STOP DBGMCU_AHB3FZR_DBG_LPDMA3_STOP /*!< The counter clock of LPDMA3 is stopped when the core is halted*/ +/** + * @} + */ + +#if defined(VREFBUF) +/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE + * @{ + */ +#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ +#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */ +#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREF_OUT3) */ +#define LL_VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1) /*!< Voltage reference scale 3 (VREF_OUT4) */ +/** + * @} + */ +#endif /* VREFBUF */ + +/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + * @{ + */ +#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH zero wait state */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH one wait state */ +#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH two wait states */ +#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH three wait states */ +#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH four wait states */ +#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait states */ +#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ +#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */ +#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */ +#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */ +#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */ +#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */ +#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */ +#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */ +#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */ +#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + * @{ + */ + +/** + * @brief Enable I/O analog switches supplied by VDD. + * @rmtoll SYSCFG_CFGR1 ANASWVDD LL_SYSCFG_EnableAnalogSwitchVdd + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableAnalogSwitchVdd(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); +} + +/** + * @brief Disable I/O analog switches supplied by VDD. + * @note I/O analog switches are supplied by VDDA or booster + * when booster in on. + * Dedicated voltage booster (supplied by VDD) is the recommended + * configuration with low VDDA voltage operation. + * @rmtoll SYSCFG_CFGR1 ANASWVDD LL_SYSCFG_DisableAnalogSwitchVdd + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableAnalogSwitchVdd(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); +} + +/** + * @brief Enable I/O analog switch voltage booster. + * @note When voltage booster is enabled, I/O analog switches are supplied + * by a dedicated voltage booster, from VDD power domain. This is + * the recommended configuration with low VDDA voltage operation. + * @note The I/O analog switch voltage booster is relevant for peripherals + * using I/O in analog input: ADC, COMP, OPAMP. + * However, COMP and OPAMP inputs have a high impedance and + * voltage booster do not impact performance significantly. + * Therefore, the voltage booster is mainly intended for + * usage with ADC. + * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); +} + +/** + * @brief Disable I/O analog switch voltage booster. + * @note When voltage booster is enabled, I/O analog switches are supplied + * by a dedicated voltage booster, from VDD power domain. This is + * the recommended configuration with low VDDA voltage operation. + * @note The I/O analog switch voltage booster is relevant for peripherals + * using I/O in analog input: ADC, COMP, OPAMP. + * However, COMP and OPAMP inputs have a high impedance and + * voltage booster do not impact performance significantly. + * Therefore, the voltage booster is mainly intended for + * usage with ADC. + * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); +} + +/** + * @brief Enable the fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR1 PBx_FMP LL_SYSCFG_EnableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB8 + * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB9 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus); +} + +/** + * @brief Disable the fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR1 PBx_FMP LL_SYSCFG_DisableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB8 + * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB9 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); +} + +#if defined(SYSCFG_CFGR1_ENDCAP) +/** + * @brief Set decoupling capacitance on HSPI supply. + * @rmtoll SYSCFG_CFGR1 ENDCAP LL_SYSCFG_SetHSPIDecouplingCapacitance + * @param Capacitance This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_OFF + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_1_DIV_3 + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_2_DIV_3 + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_FULL + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetHSPIDecouplingCapacitance(uint32_t Capacitance) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ENDCAP, Capacitance); +} + +/** + * @brief Get decoupling capacitance on HSPI supply. + * @rmtoll SYSCFG_CFGR1 ENDCAP LL_SYSCFG_GetHSPIDecouplingCapacitance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_OFF + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_1_DIV_3 + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_2_DIV_3 + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_FULL + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetHSPIDecouplingCapacitance(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ENDCAP)); +} +#endif /* SYSCFG_CFGR1_ENDCAP */ + +#if defined(SYSCFG_CFGR1_SRAMCACHED) +/** + * @brief Enable the cachability of internal SRAMs by DCACHE2. + * @rmtoll SYSCFG_CFGR1 SRAMCACHED LL_SYSCFG_EnableSRAMsCachability + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableSRAMsCachability(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED); +} + +/** + * @brief Disable the cachability of internal SRAMs by DCACHE2. + * @rmtoll SYSCFG_CFGR1 SRAMCACHED LL_SYSCFG_DisableSRAMsCachability + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableSRAMsCachability(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED); +} + +/** + * @brief Check if internal SRAMs cachability by DCACHE2 is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 SRAMCACHED LL_SYSCFG_IsEnabledSRAMsCachability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledSRAMsCachability(void) +{ + return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED) == SYSCFG_CFGR1_SRAMCACHED) ? 1UL : 0UL); +} +#endif /* SYSCFG_CFGR1_SRAMCACHED */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_FPU_IT_MANAGEMENT FPU interrupt management + * @{ + */ + +/** + * @brief Enable Floating Point Unit Invalid operation Interrupt. + * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void) +{ + SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0); +} + +/** + * @brief Enable Floating Point Unit Divide-by-zero Interrupt. + * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void) +{ + SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1); +} + +/** + * @brief Enable Floating Point Unit Underflow Interrupt. + * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void) +{ + SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2); +} + +/** + * @brief Enable Floating Point Unit Overflow Interrupt. + * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void) +{ + SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3); +} + +/** + * @brief Enable Floating Point Unit Input denormal Interrupt. + * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void) +{ + SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4); +} + +/** + * @brief Enable Floating Point Unit Inexact Interrupt. + * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void) +{ + SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5); +} + +/** + * @brief Disable Floating Point Unit Invalid operation Interrupt. + * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void) +{ + CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0); +} + +/** + * @brief Disable Floating Point Unit Divide-by-zero Interrupt. + * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void) +{ + CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1); +} + +/** + * @brief Disable Floating Point Unit Underflow Interrupt. + * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void) +{ + CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2); +} + +/** + * @brief Disable Floating Point Unit Overflow Interrupt. + * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void) +{ + CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3); +} + +/** + * @brief Disable Floating Point Unit Input denormal Interrupt. + * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void) +{ + CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4); +} + +/** + * @brief Disable Floating Point Unit Inexact Interrupt. + * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void) +{ + CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5); +} + +/** + * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void) +{ + return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0) == SYSCFG_FPUIMR_FPU_IE_0) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void) +{ + return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1) == SYSCFG_FPUIMR_FPU_IE_1) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void) +{ + return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2) == SYSCFG_FPUIMR_FPU_IE_2) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void) +{ + return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3) == SYSCFG_FPUIMR_FPU_IE_3) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void) +{ + return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4) == SYSCFG_FPUIMR_FPU_IE_4) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void) +{ + return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5) == SYSCFG_FPUIMR_FPU_IE_5) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_CPU_LOCK CPU secure/non-secure lock + * @{ + */ + +/** + * @brief Lock the secure or non-secure VTOR registers. + * @rmtoll CSLCKR/CNSLCKR LOCKSVTAIRCR/LOCKNSVTOR LL_SYSCFG_LockVTOR + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockVTOR(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SET_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSVTAIRCR); +#else + SET_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSVTOR); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +/** + * @brief Check the lock state of secure or non-secure VTOR registers. + * @rmtoll CSLCKR/CNSLCKR LOCKSVTAIRCR/LOCKNSVTOR LL_SYSCFG_IsLockedVTOR + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsLockedVTOR(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + return ((READ_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSVTAIRCR) == SYSCFG_CSLCKR_LOCKSVTAIRCR) ? 1UL : 0UL); +#else + return ((READ_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSVTOR) == SYSCFG_CNSLCKR_LOCKNSVTOR) ? 1UL : 0UL); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the non-secure VTOR registers. + * @rmtoll CNSLCKR LOCKNSVTOR LL_SYSCFG_LockVTOR_NS + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockVTOR_NS(void) +{ + SET_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSVTOR); +} + +/** + * @brief Check the lock state of non-secure VTOR registers. + * @rmtoll CNSLCKR LOCKNSVTOR LL_SYSCFG_IsLockedVTOR_NS + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsLockedVTOR_NS(void) +{ + return ((READ_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSVTOR) == SYSCFG_CNSLCKR_LOCKNSVTOR) ? 1UL : 0UL); +} +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Lock the secure or non-secure MPU registers. + * @rmtoll CSLCKR/CNSLCKR LOCKNSMPU/LOCKSMPU LL_SYSCFG_LockMPU + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockMPU(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SET_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSMPU); +#else + SET_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSMPU); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +/** + * @brief Check the lock state of secure or non-secure MPU registers. + * @rmtoll CSLCKR/CNSLCKR LOCKNSMPU/LOCKSMPU LL_SYSCFG_IsLockedMPU + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsLockedMPU(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + return ((READ_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSMPU) == SYSCFG_CSLCKR_LOCKSMPU) ? 1UL : 0UL); +#else + return ((READ_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSMPU) == SYSCFG_CNSLCKR_LOCKNSMPU) ? 1UL : 0UL); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the non-secure MPU registers. + * @rmtoll CNSLCKR LOCKNSMPU LL_SYSCFG_LockMPU_NS + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockMPU_NS(void) +{ + SET_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSMPU); +} + +/** + * @brief Check the lock state of non-secure MPU registers. + * @rmtoll CNSLCKR LOCKNSMPU LL_SYSCFG_IsLockedMPU_NS + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsLockedMPU_NS(void) +{ + return ((READ_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSMPU) == SYSCFG_CNSLCKR_LOCKNSMPU) ? 1UL : 0UL); +} + +/** + * @brief Lock the secure SAU registers. + * @rmtoll CSLCKR LOCKSAU LL_SYSCFG_LockSAU + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockSAU(void) +{ + SET_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSAU); +} + +/** + * @brief Check the lock state of secure SAU registers. + * @rmtoll CSLCKR LOCKSAU LL_SYSCFG_IsLockedSAU + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsLockedSAU(void) +{ + return ((READ_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSAU) == SYSCFG_CSLCKR_LOCKSAU) ? 1UL : 0UL); +} +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Lock the secure or non-secure CPU registers. + * @rmtoll CSLCKR/CNSLCKR LOCKSVTAIRCR/LOCKNSVTOR LL_SYSCFG_LockConfig + * @param Item Item(s) to set lock on. + * This parameter can be a combination of: + * @arg @ref LL_SYSCFG_MPU_NSEC + * @arg @ref LL_SYSCFG_VTOR_NSEC + * @arg @ref LL_SYSCFG_SAU + * @arg @ref LL_SYSCFG_MPU_SEC + * @arg @ref LL_SYSCFG_VTOR_AIRCR_SEC + * @arg @ref LL_SYSCFG_LOCK_ALL + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockConfig(uint32_t Item) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + MODIFY_REG(SYSCFG->CSLCKR, (SYSCFG_CSLCKR_LOCKSVTAIRCR | SYSCFG_CSLCKR_LOCKSMPU | SYSCFG_CSLCKR_LOCKSAU), Item); +#else + MODIFY_REG(SYSCFG->CNSLCKR, (SYSCFG_CNSLCKR_LOCKNSVTOR | SYSCFG_CNSLCKR_LOCKNSMPU), Item); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the non-secure CPU registers. + * @rmtoll CSLCKR/CNSLCKR LOCKSVTAIRCR/LOCKNSVTOR LL_SYSCFG_LockConfig_NS + * @param Item Item(s) to set lock on. + * This parameter can be a combination of: + * @arg @ref LL_SYSCFG_MPU_NSEC + * @arg @ref LL_SYSCFG_VTOR_NSEC + * @arg @ref LL_SYSCFG_LOCK_ALL + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockConfig_NS(uint32_t Item) +{ + MODIFY_REG(SYSCFG->CNSLCKR, (SYSCFG_CNSLCKR_LOCKNSVTOR | SYSCFG_CNSLCKR_LOCKNSMPU), Item); +} +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_TIMER_BREAK Timer break inputs + * @{ + */ + +/** + * @brief Set connections to TIM1/8/15/16/17 Break inputs. + * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs + * @param Break This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) +{ + MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break); +} + +/** + * @brief Get connections to TIM1/8/15/16/17 Break inputs. + * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | \ + SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL)); +} + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_Secure_Management Secure Management + * @{ + */ + +/** + * @brief Clear Status of End of Erase for ICACHE and PKA RAMs + * @rmtoll MESR IPMEE LL_SYSCFG_ClearEraseEndStatus + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_ClearEraseEndStatus(void) +{ + SET_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE); +} + +/** + * @brief Get Status of End of Erase for ICACHE and PKA RAMs + * @rmtoll MESR IPMEE LL_SYSCFG_GetEraseEndStatus + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done + * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseEndStatus(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE)); +} + +/** + * @brief Clear Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams + * @rmtoll MESR MCLR LL_SYSCFG_ClearEraseAfterResetStatus + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_ClearEraseAfterResetStatus(void) +{ + SET_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR); +} + +/** + * @brief Get Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams + * @rmtoll MESR MCLR LL_SYSCFG_GetEraseAfterResetStatus + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done + * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseAfterResetStatus(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR)); +} + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_COMPENSATION SYSCFG Compensation cell + * @{ + */ + +/** + * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDD. + * @rmtoll CCVR PCV1 LL_SYSCFG_GetPMOSVddCompensationValue + * @retval Returned value is the PMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationValue(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV1)); +} + +/** + * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDD. + * @rmtoll CCVR NCV1 LL_SYSCFG_GetNMOSVddCompensationValue + * @retval Returned value is the NMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationValue(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV1)); +} + +/** + * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDDIO2. + * @rmtoll CCVR PCV2 LL_SYSCFG_GetPMOSVddIO2CompensationValue + * @retval Returned value is the PMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationValue(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV2)); +} + +/** + * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDDIO2. + * @rmtoll CCVR NCV2 LL_SYSCFG_GetNMOSVddIO2CompensationValue + * @retval Returned value is the NMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationValue(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV2)); +} + +#if defined(SYSCFG_CCVR_PCV3) +/** + * @brief Get the compensation cell value of the HSPI IO PMOS transistor supplied by VDD. + * @rmtoll CCVR PCV3 LL_SYSCFG_GetPMOSVddHSPICompensationValue + * @retval Returned value is the PMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddHSPICompensationValue(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV3)); +} + +/** + * @brief Get the compensation cell value of the HSPI IO NMOS transistor supplied by VDD. + * @rmtoll CCVR NCV3 LL_SYSCFG_GetNMOSVddHSPICompensationValue + * @retval Returned value is the NMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddHSPICompensationValue(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV3)); +} +#endif /* SYSCFG_CCVR_PCV3 */ + +/** + * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD. + * @rmtoll CCCR PCC1 LL_SYSCFG_SetPMOSVddCompensationCode + * @param PMOSCode PMOS compensation code + * This code is applied to the PMOS compensation cell when the CS1 bit of the + * SYSCFG_CCCSR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetPMOSVddCompensationCode(uint32_t PMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC1, PMOSCode << SYSCFG_CCCR_PCC1_Pos); +} + +/** + * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDD. + * @rmtoll CCCR PCC1 LL_SYSCFG_GetPMOSVddCompensationCode + * @retval Returned value is the PMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC1)); +} + +/** + * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2. + * @rmtoll CCCR PCC2 LL_SYSCFG_SetPMOSVddIO2CompensationCode + * @param PMOSCode PMOS compensation code + * This code is applied to the PMOS compensation cell when the CS2 bit of the + * SYSCFG_CCCSR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetPMOSVddIO2CompensationCode(uint32_t PMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC2, PMOSCode << SYSCFG_CCCR_PCC2_Pos); +} + +/** + * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2. + * @rmtoll CCCR PCC2 LL_SYSCFG_GetPMOSVddIO2CompensationCode + * @retval Returned value is the PMOS compensation + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC2)); +} + +#if defined(SYSCFG_CCCR_PCC3) +/** + * @brief Set the compensation cell code of the HSPI IO PMOS transistor supplied by VDD. + * @rmtoll CCCR PCC3 LL_SYSCFG_SetPMOSVddHSPICompensationCode + * @param PMOSCode PMOS compensation code + * This code is applied to the PMOS compensation cell when the CS3 bit of the + * SYSCFG_CCCSR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetPMOSVddHSPICompensationCode(uint32_t PMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC3, PMOSCode << SYSCFG_CCCR_PCC3_Pos); +} + +/** + * @brief Get the compensation cell code of the HSPI IO PMOS transistor supplied by VDD. + * @rmtoll CCCR PCC3 LL_SYSCFG_GetPMOSVddHSPICompensationCode + * @retval Returned value is the PMOS compensation + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddHSPICompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC3)); +} +#endif /* SYSCFG_CCCR_PCC3 */ + +/** + * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD. + * @rmtoll CCCR PCC2 LL_SYSCFG_SetNMOSVddCompensationCode + * @param NMOSCode NMOS compensation code + * This code is applied to the NMOS compensation cell when the CS2 bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetNMOSVddCompensationCode(uint32_t NMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC1, NMOSCode << SYSCFG_CCCR_NCC1_Pos); +} + +/** + * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDD. + * @rmtoll CCCR NCC1 LL_SYSCFG_GetNMOSVddCompensationCode + * @retval Returned value is the Vdd compensation cell code for NMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC1)); +} + +/** + * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2. + * @rmtoll CCCR NCC2 LL_SYSCFG_SetNMOSVddIO2CompensationCode + * @param NMOSCode NMOS compensation code + * This code is applied to the NMOS compensation cell when the CS2 bit of the + * SYSCFG_CMPCR is set + * Value between 0 and 15 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetNMOSVddIO2CompensationCode(uint32_t NMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC2, NMOSCode << SYSCFG_CCCR_NCC2_Pos); +} + +/** + * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2. + * @rmtoll CCCR NCC2 LL_SYSCFG_GetNMOSVddIO2CompensationCode + * @retval Returned value is the NMOS compensation cell code + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC2)); +} + +#if defined(SYSCFG_CCCR_NCC3) +/** + * @brief Set the compensation cell code of the HSPI IO NMOS transistor supplied by VDD. + * @rmtoll CCCR NCC3 LL_SYSCFG_SetNMOSVddHSPICompensationCode + * @param NMOSCode NMOS compensation code + * This code is applied to the NMOS compensation cell when the CS3 bit of the + * SYSCFG_CCCSR is set + * Value between 0 and 15 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetNMOSVddHSPICompensationCode(uint32_t NMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC3, NMOSCode << SYSCFG_CCCR_NCC3_Pos); +} + +/** + * @brief Get the compensation cell code of the HSPI IO NMOS transistor supplied by VDD. + * @rmtoll CCCR NCC3 LL_SYSCFG_GetNMOSVddHSPICompensationCode + * @retval Returned value is the NMOS compensation cell code + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddHSPICompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC3)); +} +#endif /* SYSCFG_CCCR_NCC3 */ + +/** + * @brief Enable the Compensation Cell of GPIO supplied by VDD. + * @rmtoll CCCSR EN1 LL_SYSCFG_EnableVddCompensationCell + * @note The vdd compensation cell can be used only when the device supply + * voltage ranges from 1.71 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableVddCompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1); +} + +/** + * @brief Enable the Compensation Cell of GPIO supplied by VDDIO2. + * @rmtoll CCCSR EN2 LL_SYSCFG_EnableVddIO2CompensationCell + * @note The Vdd I/O compensation cell can be used only when the device supply + * voltage ranges from 1.08 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableVddIO2CompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2); +} + +#if defined(SYSCFG_CCCSR_EN3) +/** + * @brief Enable the Compensation Cell of HSPI IO supplied by VDD. + * @rmtoll CCCSR EN3 LL_SYSCFG_EnableVddHSPICompensationCell + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableVddHSPICompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3); +} +#endif /* SYSCFG_CCCSR_EN3 */ + +/** + * @brief Disable the Compensation Cell of GPIO supplied by VDD. + * @rmtoll CCCSR EN1 LL_SYSCFG_DisableVddCompensationCell + * @note The Vdd compensation cell can be used only when the device supply + * voltage ranges from 1.71 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableVddCompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1); +} + +/** + * @brief Disable the Compensation Cell of GPIO supplied by VDDIO2. + * @rmtoll CCCSR EN2 LL_SYSCFG_DisableVddIO2CompensationCell + * @note The Vdd I/O compensation cell can be used only when the device supply + * voltage ranges from 1.08 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableVddIO2CompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2); +} + +#if defined(SYSCFG_CCCSR_EN3) +/** + * @brief Disable the Compensation Cell of HSPI IO supplied by VDD. + * @rmtoll CCCSR EN3 LL_SYSCFG_DisableVddHSPICompensationCell + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableVddHSPICompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3); +} +#endif /* SYSCFG_CCCSR_EN3 */ + +/** + * @brief Check if the Compensation Cell of GPIO supplied by VDD is enabled. + * @rmtoll CCCSR EN1 LL_SYSCFG_IsEnabled_VddCompensationCell + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddCompensationCell(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1) == SYSCFG_CCCSR_EN1) ? 1UL : 0UL); +} + +/** + * @brief Check if the Compensation Cell of GPIO supplied by VDDIO2 is enabled. + * @rmtoll CCCSR EN2 LL_SYSCFG_IsEnabled_VddIO2CompensationCell + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddIO2CompensationCell(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2) == SYSCFG_CCCSR_EN2) ? 1UL : 0UL); +} + +#if defined(SYSCFG_CCCSR_EN3) +/** + * @brief Check if the Compensation Cell of HSPI IO supplied by VDD is enabled. + * @rmtoll CCCSR EN3 LL_SYSCFG_IsEnabled_VddHSPICompensationCell + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddHSPICompensationCell(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3) == SYSCFG_CCCSR_EN3) ? 1UL : 0UL); +} +#endif /* SYSCFG_CCCSR_EN3 */ + +/** + * @brief Get Compensation Cell ready Flag of GPIO supplied by VDD. + * @rmtoll CCCSR RDY1 LL_SYSCFG_IsActiveFlag_VddCMPCR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddCMPCR(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY1) == (SYSCFG_CCCSR_RDY1)) ? 1UL : 0UL); +} + +/** + * @brief Get Compensation Cell ready Flag of GPIO supplied by VDDIO2. + * @rmtoll CCCSR RDY2 LL_SYSCFG_IsActiveFlag_VddIO2CMPCR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddIO2CMPCR(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY2) == (SYSCFG_CCCSR_RDY2)) ? 1UL : 0UL); +} + +#if defined(SYSCFG_CCCSR_RDY3) +/** + * @brief Get Compensation Cell ready Flag of HSPI IO supplied by VDD. + * @rmtoll CCCSR RDY3 LL_SYSCFG_IsActiveFlag_VddHSPICMPCR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddHSPICMPCR(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY3) == (SYSCFG_CCCSR_RDY3)) ? 1UL : 0UL); +} +#endif /* SYSCFG_CCCSR_RDY3 */ + +/** + * @brief Set the compensation cell code selection of GPIO supplied by VDD. + * @rmtoll CCCSR CS1 LL_SYSCFG_SetVddCellCompensationCode + * @param CompCode: Selects the code to be applied for the Vdd compensation cell + * This parameter can be one of the following values: + * @arg LL_SYSCFG_VDD_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_VDD_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR) + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetVddCellCompensationCode(uint32_t CompCode) +{ + SET_BIT(SYSCFG->CCCSR, CompCode); +} + +/** + * @brief Set the compensation cell code selection of GPIO supplied by VDDIO2. + * @rmtoll CCCSR CS2 LL_SYSCFG_SetVddIO2CellCompensationCode + * @param CompCode: Selects the code to be applied for the VddIO compensation cell + * This parameter can be one of the following values: + * @arg LL_SYSCFG_VDDIO2_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_VDDIO2_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR) + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetVddIO2CellCompensationCode(uint32_t CompCode) +{ + SET_BIT(SYSCFG->CCCSR, CompCode); +} + +#if defined(SYSCFG_CCCSR_CS3) +/** + * @brief Set the compensation cell code selection of HSPI IO supplied by VDD. + * @rmtoll CCCSR CS3 LL_SYSCFG_SetVddHSPICellCompensationCode + * @param CompCode: Selects the code to be applied for the VddIO compensation cell + * This parameter can be one of the following values: + * @arg LL_SYSCFG_VDDHSPI_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_VDDHSPI_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR) + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetVddHSPICellCompensationCode(uint32_t CompCode) +{ + SET_BIT(SYSCFG->CCCSR, CompCode); +} +#endif /* SYSCFG_CCCSR_CS3 */ + +/** + * @brief Get the compensation cell code selection of GPIO supplied by VDD. + * @rmtoll CCCSR CS1 LL_SYSCFG_GetVddCellCompensationCode + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_VDD_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_VDD_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR) + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetVddCellCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS1)); +} + +/** + * @brief Get the compensation cell code selection of GPIO supplied by VDDIO2. + * @rmtoll CCCSR CS2 LL_SYSCFG_GetVddIO2CellCompensationCode + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_VDDIO2_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_VDDIO2_REGISTER_CODE: Selected Code is from the SYSCFG compensation + cell code register (SYSCFG_CCCR) + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetVddIO2CellCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS2)); +} + +#if defined(SYSCFG_CCCSR_CS3) +/** + * @brief Get the compensation cell code selection of HSPI IO supplied by VDD. + * @rmtoll CCCSR CS3 LL_SYSCFG_GetVddHSPICellCompensationCode + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_VDDHSPI_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_VDDHSPI_REGISTER_CODE: Selected Code is from the SYSCFG compensation + cell code register (SYSCFG_CCCR) + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetVddHSPICellCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS3)); +} +#endif /* SYSCFG_CCCSR_CS3 */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_OTGPHY OTG HS PHY configurations + * @{ + */ + +#if defined(SYSCFG_OTGHSPHYCR_EN) +/** + * @brief Enable the OTG high-speed PHY. + * @rmtoll SYSCFG_OTGHSPHYCR EN LL_SYSCFG_EnableOTGPHY + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableOTGPHY(void) +{ + SET_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN); +} + +/** + * @brief Disable the OTG high-speed PHY. + * @rmtoll SYSCFG_OTGHSPHYCR EN LL_SYSCFG_DisableOTGPHY + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableOTGPHY(void) +{ + CLEAR_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN); +} + +/** + * @brief Check if the OTG high-speed PHY is enabled or disabled. + * @rmtoll SYSCFG_OTGHSPHYCR EN LL_SYSCFG_IsEnabledOTGPHY + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledOTGPHY(void) +{ + return ((READ_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN) == SYSCFG_OTGHSPHYCR_EN) ? 1UL : 0UL); +} +#endif /* SYSCFG_OTGHSPHYCR_EN */ + +#if defined(SYSCFG_OTGHSPHYCR_PDCTRL) +/** + * @brief Enable the OTG high-speed PHY common block power-down control. + * @rmtoll SYSCFG_OTGHSPHYCR PDCTRL LL_SYSCFG_EnableOTGPHYPowerDown + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableOTGPHYPowerDown(void) +{ + SET_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL); +} + +/** + * @brief Disable the OTG high-speed PHY common block power-down control. + * @rmtoll SYSCFG_OTGHSPHYCR PDCTRL LL_SYSCFG_DisableOTGPHYPowerDown + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableOTGPHYPowerDown(void) +{ + CLEAR_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL); +} + +/** + * @brief Check if the OTG high-speed PHY common block power-down is enabled or disabled. + * @rmtoll SYSCFG_OTGHSPHYCR PDCTRL LL_SYSCFG_IsEnabledOTGPHYPowerDown + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledOTGPHYPowerDown(void) +{ + return ((READ_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL) == SYSCFG_OTGHSPHYCR_PDCTRL) ? 1UL : 0UL); +} +#endif /* SYSCFG_OTGHSPHYCR_PDCTRL */ + +#if defined(SYSCFG_OTGHSPHYCR_CLKSEL) +/** + * @brief Set the OTG high-speed PHY reference clock frequency selection. + * @rmtoll SYSCFG_OTGHSPHYCR CLKSEL LL_SYSCFG_SetOTGPHYReferenceClockFrequency + * @param ClockFrequency This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_16MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_19_2MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_20MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_24MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_26MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_32MHZ + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetOTGPHYReferenceClockFrequency(uint32_t ClockFrequency) +{ + MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_CLKSEL, ClockFrequency); +} + +/** + * @brief Get the OTG high-speed PHY reference clock frequency selection. + * @rmtoll SYSCFG_OTGHSPHYCR CLKSEL LL_SYSCFG_GetOTGPHYReferenceClockFrequency + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_16MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_19_2MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_20MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_24MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_26MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_32MHZ + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetOTGPHYReferenceClockFrequency(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_CLKSEL)); +} +#endif /* SYSCFG_OTGHSPHYCR_CLKSEL */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE) +/** + * @brief Set the OTG high-speed PHY disconnect threshold adjustment. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 COMPDISTUNE LL_SYSCFG_SetOTGPHYDisconnectThresholdAdjustment + * @param DisconnectThreshold This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_DISCONNECT_5_9PERCENT + * @arg @ref LL_SYSCFG_OTGHSPHY_DISCONNECT_0PERCENT + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetOTGPHYDisconnectThresholdAdjustment(uint32_t DisconnectThreshold) +{ + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE, DisconnectThreshold); +} + +/** + * @brief Get the OTG high-speed PHY disconnect threshold adjustment. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 COMPDISTUNE LL_SYSCFG_GetOTGPHYDisconnectThresholdAdjustment + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_DISCONNECT_5_9PERCENT + * @arg @ref LL_SYSCFG_OTGHSPHY_DISCONNECT_0PERCENT + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetOTGPHYDisconnectThresholdAdjustment(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE)); +} +#endif /* SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_SQRXTUNE) +/** + * @brief Set the voltage level for the threshold used to detect valid high-speed data. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 SQRXTUNE LL_SYSCFG_SetOTGPHYSquelchThresholdAdjustment + * @param SquelchThreshold This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_SQUELCH_15PERCENT + * @arg @ref LL_SYSCFG_OTGHSPHY_SQUELCH_0PERCENT + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetOTGPHYSquelchThresholdAdjustment(uint32_t SquelchThreshold) +{ + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_SQRXTUNE, SquelchThreshold); +} + +/** + * @brief Get the voltage level for the threshold used to detect valid high-speed data. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 SQRXTUNE LL_SYSCFG_GetOTGPHYSquelchThresholdAdjustment + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_SQUELCH_15PERCENT + * @arg @ref LL_SYSCFG_OTGHSPHY_SQUELCH_0PERCENT + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetOTGPHYSquelchThresholdAdjustment(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_SQRXTUNE)); +} +#endif /* SYSCFG_OTGHSPHYTUNER2_SQRXTUNE */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE) +/** + * @brief Set the OTG high-speed PHY transmitter preemphasis current control. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 TXPREEMPAMPTUNE LL_SYSCFG_SetOTGPHYTransmitterPreemphasisCurrent + * @param PreemphasisCurrent This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_DISABLED + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_1X + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_2X + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_3X + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetOTGPHYTransmitterPreemphasisCurrent(uint32_t PreemphasisCurrent) +{ + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE, PreemphasisCurrent); +} + +/** + * @brief Get the OTG high-speed PHY transmitter preemphasis current control. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 TXPREEMPAMPTUNE LL_SYSCFG_GetOTGPHYTransmitterPreemphasisCurrent + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_DISABLED + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_1X + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_2X + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_3X + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetOTGPHYTransmitterPreemphasisCurrent(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE)); +} +#endif /* SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_Secure_Management Secure Management + * @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure Secure mode. + * @note Only available from secure state when system implements security (TZEN=1) + * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n + * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n + * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure + * @param Configuration This parameter shall be the full combination + * of the following values: + * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC + * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC + * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_ConfigSecure(uint32_t Configuration) +{ + WRITE_REG(SYSCFG->SECCFGR, Configuration); +} +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Get Secure mode configuration. + * @note Only available when system implements security (TZEN=1) + * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n + * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n + * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure + * @retval Returned value is the combination of the following values: + * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC + * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC + * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetConfigSecure(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->SECCFGR, 0xBU)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415) + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Enable the Debug Clock Trace + * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_EnableTraceClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableTraceClock(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN); +} + +/** + * @brief Disable the Debug Clock Trace + * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_DisableTraceClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableTraceClock(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN); +} + + +/** + * @brief Check if clock trace is enabled or disabled. + * @rmtoll DBGMCU_CR_TRACE_CLKEN LL_DBGMCU_IsEnabledTraceClock + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTraceClock(void) +{ + return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN) == DBGMCU_CR_TRACE_CLKEN) ? 1UL : 0UL); +} + +/** + * @brief Set Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment + * @param PinAssignment This parameter can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) +{ + MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); +} + +/** + * @brief Get Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment + * @retval Returned value can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); +} + +/** + * @brief Freeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1FZR1, Periphs); +} + +/** + * @brief Freeze APB1 peripherals (group2 peripherals) + * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_I2C5_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP2_I2C6_STOP (*) + * @retval None + * @note (*) Availability depends on devices. + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1FZR2, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1FZR1, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group2 peripherals) + * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1FZR2, Periphs); +} + +/** + * @brief Freeze APB2 peripherals + * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZR, Periphs); +} + +/** + * @brief Unfreeze APB2 peripherals + * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB2FZR, Periphs); +} + +/** + * @brief Freeze APB3 peripherals + * @rmtoll DBGMCU_APB3FZ DBG_TIMx_STOP LL_DBGMCU_APB3_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB3_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM1_STOP + * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM3_STOP + * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM4_STOP + * @arg @ref LL_DBGMCU_APB3_GRP1_RTC_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB3FZR, Periphs); +} + +/** + * @brief Unfreeze APB3 peripherals + * @rmtoll DBGMCU_APB3FZR DBG_TIMx_STOP LL_DBGMCU_APB3_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB3_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM1_STOP + * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM3_STOP + * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM4_STOP + * @arg @ref LL_DBGMCU_APB3_GRP1_RTC_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB3FZR, Periphs); +} + +/** + * @brief Freeze AHB1 peripherals + * @rmtoll DBGMCU_AHB1FZ DBG_GPDMAx_STOP LL_DBGMCU_AHB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_AHB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->AHB1FZR, Periphs); +} + +/** + * @brief Unfreeze AHB1 peripherals + * @rmtoll DBGMCU_AHB1FZ DBG_GPDMAx_STOP LL_DBGMCU_AHB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->AHB1FZR, Periphs); +} + +/** + * @brief Freeze AHB3 peripherals + * @rmtoll DBGMCU_AHB3FZ DBG_LPDMAx_STOP LL_DBGMCU_AHB3_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA0_STOP + * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA1_STOP + * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA2_STOP + * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA3_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_AHB3_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->AHB3FZR, Periphs); +} + +/** + * @brief Unfreeze AHB3 peripherals + * @rmtoll DBGMCU_AHB3FZ DBG_LPDMAx_STOP LL_DBGMCU_AHB3_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA0_STOP + * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA1_STOP + * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA2_STOP + * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA3_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_AHB3_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->AHB3FZR, Periphs); +} + +/** + * @} + */ + +#if defined(VREFBUF) +/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF + * @{ + */ + +/** + * @brief Enable Internal voltage reference + * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_Enable(void) +{ + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} + +/** + * @brief Disable Internal voltage reference + * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_Disable(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} + +/** + * @brief Enable high impedance (VREF+pin is high impedance) + * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void) +{ + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ); +} + +/** + * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output) + * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ); +} + +/** + * @brief Set the Voltage reference scale + * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling + * @param Scale This parameter can be one of the following values: + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE3 + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale) +{ + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale); +} + +/** + * @brief Get the Voltage reference scale + * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE3 + */ +__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS)); +} + +/** + * @brief Check if Voltage reference buffer is ready + * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void) +{ + return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == VREFBUF_CSR_VRR) ? 1UL : 0UL); +} + +/** + * @brief Get the trimming code for VREFBUF calibration + * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming + * @retval Between 0 and 0x3F + */ +__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void) +{ + return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM)); +} + +/** + * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage) + * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming + * @param Value Between 0 and 0x3F + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value) +{ + WRITE_REG(VREFBUF->CCR, Value); +} + +/** + * @} + */ +#endif /* VREFBUF */ + +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + * @arg @ref LL_FLASH_LATENCY_8 + * @arg @ref LL_FLASH_LATENCY_9 + * @arg @ref LL_FLASH_LATENCY_10 + * @arg @ref LL_FLASH_LATENCY_11 + * @arg @ref LL_FLASH_LATENCY_12 + * @arg @ref LL_FLASH_LATENCY_13 + * @arg @ref LL_FLASH_LATENCY_14 + * @arg @ref LL_FLASH_LATENCY_15 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + * @arg @ref LL_FLASH_LATENCY_8 + * @arg @ref LL_FLASH_LATENCY_9 + * @arg @ref LL_FLASH_LATENCY_10 + * @arg @ref LL_FLASH_LATENCY_11 + * @arg @ref LL_FLASH_LATENCY_12 + * @arg @ref LL_FLASH_LATENCY_13 + * @arg @ref LL_FLASH_LATENCY_14 + * @arg @ref LL_FLASH_LATENCY_15 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @brief Enable Flash Power-down mode during run mode or Low-power run mode + * @note Flash memory can be put in power-down mode only when the code is executed + * from RAM + * @note Flash must not be accessed when power down is enabled + * @note Flash must not be put in power-down while a program or an erase operation + * is on-going + * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n + * FLASH_PDKEYR PDKEY1_1 LL_FLASH_EnableRunPowerDown\n + * FLASH_PDKEYR PDKEY1_2 LL_FLASH_EnableRunPowerDown\n + * FLASH_PDKEYR PDKEY2_1 LL_FLASH_EnableRunPowerDown\n + * FLASH_PDKEYR PDKEY2_2 LL_FLASH_EnableRunPowerDown + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void) +{ + /* Following values must be written consecutively to unlock the RUN_PD bit in + FLASH_ACR */ + WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_1); + WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_2); + WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_1); + WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_2); + + /*Request to enter flash in power mode */ + SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ1 | FLASH_ACR_PDREQ2); +} + +/** + * @brief Enable flash Power-down mode during run mode or Low-power run mode of bank1 + * @note Bank 1 of flash memory can be put in power-down mode only when the code is executed + * from RAM + * @note Bank1 of flash must not be accessed when power down is enabled + * @note Bank1 of flash must not be put in power-down while a program or an erase operation + * is on-going + * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n + * FLASH_PDKEYR PDKEY1_1 LL_FLASH_EnableRunPowerDown\n + * FLASH_PDKEYR PDKEY1_2 LL_FLASH_EnableRunPowerDown\n + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableRunPowerDownBank1(void) +{ + /* Following values must be written consecutively to unlock the RUN_PD bit in + FLASH_ACR */ + WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_1); + WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_2); + + /*Request to enter flash in power mode */ + SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ1); +} + +/** + * @brief Enable flash Power-down mode during run mode or Low-power run mode of Bank2 + * @note Bank 2 of flash memory can be put in power-down mode only when the code is executed + * from RAM + * @note Bank2 of flash must not be accessed when power down is enabled + * @note Bank2 of flash must not be put in power-down while a program or an erase operation + * is on-going + * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n + * FLASH_PDKEYR PDKEY2_1 LL_FLASH_EnableRunPowerDown\n + * FLASH_PDKEYR PDKEY2_2 LL_FLASH_EnableRunPowerDown\n + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableRunPowerDownBank2(void) +{ + /* Following values must be written consecutively to unlock the RUN_PD bit in + FLASH_ACR */ + WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_1); + WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_2); + + /*Request to enter flash in power mode */ + SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ2); +} + +/** + * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode + * @note Flash must not be put in power-down while a program or an erase operation + * is on-going + * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); +} + +/** + * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode + * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); +} +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32u5xx_LL_SYSTEM_H */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usart.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usart.h new file mode 100644 index 000000000..4c4b9c9ca --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usart.h @@ -0,0 +1,4492 @@ +/** + ****************************************************************************** + * @file stm32u5xx_ll_usart.h + * @author MCD Application Team + * @brief Header file of USART LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_LL_USART_H +#define STM32U5xx_LL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx.h" + +/** @addtogroup STM32U5xx_LL_Driver + * @{ + */ + +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) + +/** @defgroup USART_LL USART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Variables USART Private Variables + * @{ + */ +/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */ +static const uint32_t USART_PRESCALER_TAB[] = +{ + 1UL, + 2UL, + 4UL, + 6UL, + 8UL, + 10UL, + 12UL, + 16UL, + 32UL, + 64UL, + 128UL, + 256UL, + 256UL, + 256UL, + 256UL, + 256UL +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Constants USART Private Constants + * @{ + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_Private_Macros USART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_ES_INIT USART Exported Init structures + * @{ + */ + +/** + * @brief LL USART Init Structure definition + */ +typedef struct +{ + uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. + This parameter can be a value of @ref USART_LL_EC_PRESCALER. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetPrescaler().*/ + + uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetHWFlowCtrl().*/ + + uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. + This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetOverSampling().*/ + +} LL_USART_InitTypeDef; + +/** + * @brief LL USART Clock Init Structure definition + */ +typedef struct +{ + uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_CLOCK. + + USART HW configuration can be modified afterwards using unitary functions + @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput(). + For more details, refer to description of this function. */ + + uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_LL_EC_POLARITY. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPolarity(). + For more details, refer to description of this function. */ + + uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_LL_EC_PHASE. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPhase(). + For more details, refer to description of this function. */ + + uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetLastClkPulseOutput(). + For more details, refer to description of this function. */ + +} LL_USART_ClockInitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Constants USART Exported Constants + * @{ + */ + +/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_USART_WriteReg function + * @{ + */ +#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */ +#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */ +#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */ +#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */ +#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */ +#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag */ +#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_USART_ReadReg function + * @{ + */ +#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */ +#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */ +#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */ +#define LL_USART_ISR_UDR USART_ISR_UDR /*!< SPI Slave underrun error flag */ +#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */ +#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */ +#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#define LL_USART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_USART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */ +#define LL_USART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_USART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions + * @{ + */ +#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ +#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ +#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */ +#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */ +#define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ +#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */ +#define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold + * @{ + */ +#define LL_USART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ +#define LL_USART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ +#define LL_USART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ +#define LL_USART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ +#define LL_USART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ +#define LL_USART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DIRECTION Communication Direction + * @{ + */ +#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ +#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling + * @{ + */ +#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EC_CLOCK Clock Signal + * @{ + */ + +#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ +#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse + * @{ + */ +#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ +#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ +#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ +#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler + * @{ + */ +#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */ +#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */ +#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap + * @{ + */ +#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + * @{ + */ +#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + * @{ + */ +#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion + * @{ + */ +#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ +#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_BITORDER Bit Order + * @{ + */ +#define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ +#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection + * @{ + */ +#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */ +#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */ +#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */ +#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection + * @{ + */ +#define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ +#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ +#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power + * @{ + */ +#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */ +#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length + * @{ + */ +#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */ +#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity + * @{ + */ +#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger Selection + * @brief USART Autonomous Trigger selection + * @{ + */ +#define LL_USART_GPDMA1_CH0_TCF_TRG 0U /*!< USART GPDMA1 channel0 Internal Trigger */ +#define LL_USART_GPDMA1_CH1_TCF_TRG 1U /*!< USART GPDMA1 channel1 Internal Trigger */ +#define LL_USART_GPDMA1_CH2_TCF_TRG 2U /*!< USART GPDMA1 channel2 Internal Trigger */ +#define LL_USART_GPDMA1_CH3_TCF_TRG 3U /*!< USART GPDMA1 channel3 Internal Trigger */ +#define LL_USART_EXTI_LINE6_TRG 4U /*!< USART EXTI line 6 Internal Trigger */ +#define LL_USART_EXTI_LINE9_TRG 5U /*!< USART EXTI line 9 Internal Trigger */ +#define LL_USART_LPTIM1_OUT_TRG 6U /*!< USART LPTIM1 out Internal Trigger */ +#define LL_USART_LPTIM2_OUT_TRG 7U /*!< USART LPTIM2 out Internal Trigger */ +#define LL_USART_COMP1_OUT_TRG 8U /*!< USART COMP1 out Internal Trigger */ +#define LL_USART_COMP2_OUT_TRG 9U /*!< USART COMP2 out Internal Trigger */ +#define LL_USART_RTC_ALRA_TRG 10U /*!< USART RTC alarm Internal Trigger */ +#define LL_USART_RTC_WUT_TRG 11U /*!< USART RTC wakeup Internal Trigger */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity + * @brief USART Autonomous Trigger Polarity + * @{ + */ +#define LL_USART_TRIG_POLARITY_RISING 0x00000000U /*!< USART triggered on rising edge */ +#define LL_USART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< USART triggered on falling edge */ +/** + * @} + */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Macros USART Exported Macros + * @{ + */ + +/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper + * @{ + */ + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case + */ +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case + */ +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USART_LL_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief USART Enable + * @rmtoll CR1 UE LL_USART_Enable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief USART Disable (all USART prescalers and outputs are disabled) + * @note When USART is disabled, USART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the USART is kept, but all the status + * flags, in the USARTx_ISR are set to their default values. + * @rmtoll CR1 UE LL_USART_Disable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if USART is enabled + * @rmtoll CR1 UE LL_USART_IsEnabled + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); +} + +/** + * @brief FIFO Mode Enable + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_EnableFIFO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief FIFO Mode Disable + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_DisableFIFO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief Indicate if FIFO Mode is enabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure TX FIFO Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold + * @param USARTx USART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Return TX FIFO Threshold Configuration + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Configure RX FIFO Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold + * @param USARTx USART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Return RX FIFO Threshold Configuration + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Configure TX and RX FIFOs Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n + * CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold + * @param USARTx USART Instance + * @param TXThreshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @param RXThreshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | + (RXThreshold << USART_CR3_RXFTCFG_Pos)); +} + +/** + * @brief USART enabled in STOP Mode. + * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that + * USART clock selection is HSI or LSE in RCC. + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_EnableInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief USART disabled in STOP Mode. + * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_DisableInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); +} + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_USART_EnableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_USART_DisableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_USART_EnableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_USART_DisableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_SetTransferDirection\n + * CR1 TE LL_USART_SetTransferDirection + * @param USARTx USART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) +{ + ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_GetTransferDirection\n + * CR1 TE LL_USART_GetTransferDirection + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled). + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (9th or 8th bit depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_USART_SetParity\n + * CR1 PCE LL_USART_SetParity + * @param USARTx USART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_USART_GetParity\n + * CR1 PCE LL_USART_GetParity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod + * @param USARTx USART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M0 LL_USART_SetDataWidth\n + * CR1 M1 LL_USART_SetDataWidth + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M0 LL_USART_GetDataWidth\n + * CR1 M1 LL_USART_GetDataWidth + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); +} + +/** + * @brief Allow switch between Mute Mode and Active mode + * @rmtoll CR1 MME LL_USART_EnableMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + * @rmtoll CR1 MME LL_USART_DisableMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Indicate if switch between Mute Mode and Active mode is allowed + * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); +} + +/** + * @brief Set Oversampling to 8-bit or 16-bit mode + * @rmtoll CR1 OVER8 LL_USART_SetOverSampling + * @param USARTx USART Instance + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); +} + +/** + * @brief Return Oversampling mode + * @rmtoll CR1 OVER8 LL_USART_GetOverSampling + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); +} + +/** + * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput + * @param USARTx USART Instance + * @param LastBitClockPulse This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); +} + +/** + * @brief Retrieve Clock pulse of the last data bit output configuration + * (Last bit Clock pulse output to the SCLK pin or not) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + */ +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); +} + +/** + * @brief Select the phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_SetClockPhase + * @param USARTx USART Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); +} + +/** + * @brief Return phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_GetClockPhase + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); +} + +/** + * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_SetClockPolarity + * @param USARTx USART Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); +} + +/** + * @brief Return polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_GetClockPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); +} + +/** + * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function + * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function + * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function + * @rmtoll CR2 CPHA LL_USART_ConfigClock\n + * CR2 CPOL LL_USART_ConfigClock\n + * CR2 LBCL LL_USART_ConfigClock + * @param USARTx USART Instance + * @param Phase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @param LBCPOutput This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); +} + +/** + * @brief Configure Clock source prescaler for baudrate generator and oversampling + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll PRESC PRESCALER LL_USART_SetPrescaler + * @param USARTx USART Instance + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); +} + +/** + * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll PRESC PRESCALER LL_USART_GetPrescaler + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER)); +} + +/** + * @brief Enable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Disable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Indicate if Clock output on SCLK pin is enabled + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_USART_SetStopBitsLength + * @param USARTx USART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_USART_GetStopBitsLength + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_USART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_USART_SetParity() function + * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_USART_ConfigCharacter\n + * CR1 PCE LL_USART_ConfigCharacter\n + * CR1 M0 LL_USART_ConfigCharacter\n + * CR1 M1 LL_USART_ConfigCharacter\n + * CR2 STOP LL_USART_ConfigCharacter + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Configure TX/RX pins swapping setting. + * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap + * @param USARTx USART Instance + * @param SwapConfig This parameter can be one of the following values: + * @arg @ref LL_USART_TXRX_STANDARD + * @arg @ref LL_USART_TXRX_SWAPPED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); +} + +/** + * @brief Retrieve TX/RX pins swapping configuration. + * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TXRX_STANDARD + * @arg @ref LL_USART_TXRX_SWAPPED + */ +__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); +} + +/** + * @brief Configure RX pin active level logic + * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel + * @param USARTx USART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod); +} + +/** + * @brief Retrieve RX pin active level logic configuration + * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); +} + +/** + * @brief Configure TX pin active level logic + * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel + * @param USARTx USART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod); +} + +/** + * @brief Retrieve TX pin active level logic configuration + * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); +} + +/** + * @brief Configure Binary data logic. + * @note Allow to define how Logical data from the data register are send/received : + * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) + * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic + * @param USARTx USART Instance + * @param DataLogic This parameter can be one of the following values: + * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic); +} + +/** + * @brief Retrieve Binary data configuration + * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE + */ +__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); +} + +/** + * @brief Configure transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder + * @param USARTx USART Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSBFIRST + * @arg @ref LL_USART_BITORDER_MSBFIRST + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder); +} + +/** + * @brief Return transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSBFIRST + * @arg @ref LL_USART_BITORDER_MSBFIRST + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); +} + +/** + * @brief Enable Auto Baud-Rate Detection + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_ABREN); +} + +/** + * @brief Disable Auto Baud-Rate Detection + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN); +} + +/** + * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); +} + +/** + * @brief Set Auto Baud-Rate mode bits + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode + * @param USARTx USART Instance + * @param AutoBaudRateMode This parameter can be one of the following values: + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME + * @retval None + */ +__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode); +} + +/** + * @brief Return Auto Baud-Rate mode + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME + */ +__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); +} + +/** + * @brief Enable Receiver Timeout + * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_RTOEN); +} + +/** + * @brief Disable Receiver Timeout + * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN); +} + +/** + * @brief Indicate if Receiver Timeout feature is enabled + * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); +} + +/** + * @brief Set Address of the USART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. + * (b7-b4 should be set to 0) + * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. + * (This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with 7-bit address mark detection. + * The MSB of the character sent by the transmitter should be equal to 1. + * It may also be used for character detection during normal reception, + * Mute mode inactive (for example, end of block detection in ModBus protocol). + * In this case, the whole received character (8-bit) is compared to the ADD[7:0] + * value and CMF flag is set on match) + * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n + * CR2 ADDM7 LL_USART_ConfigNodeAddress + * @param USARTx USART Instance + * @param AddressLen This parameter can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4B + * @arg @ref LL_USART_ADDRESS_DETECT_7B + * @param NodeAddress 4 or 7 bit Address of the USART node. + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, + (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); +} + +/** + * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * If 7-bit Address Detection is selected in ADDM7, + * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) + * @rmtoll CR2 ADD LL_USART_GetNodeAddress + * @param USARTx USART Instance + * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +} + +/** + * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) + * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4B + * @arg @ref LL_USART_ADDRESS_DETECT_7B + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); +} + +/** + * @brief Enable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n + * CR3 CTSE LL_USART_SetHWFlowCtrl + * @param USARTx USART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n + * CR3 CTSE LL_USART_GetHWFlowCtrl + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Enable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Disable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Indicate if One bit sampling method is enabled + * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); +} + +/** + * @brief Enable Overrun detection + * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Disable Overrun detection + * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Indicate if Overrun detection is enabled + * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); +} + +/** + * @brief Configure USART BRR register for achieving expected Baud Rate value. + * @note Compute and set USARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values + * @note Peripheral clock and Baud rate values provided as function parameters should be valid + * (Baud rate value != 0) + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + * @rmtoll BRR BRR LL_USART_SetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t OverSampling, + uint32_t BaudRate) +{ + uint32_t usartdiv; + uint32_t brrtemp; + + if (PrescalerValue > LL_USART_PRESCALER_DIV256) + { + /* Do not overstep the size of USART_PRESCALER_TAB */ + } + else if (BaudRate == 0U) + { + /* Can Not divide per 0 */ + } + else if (OverSampling == LL_USART_OVERSAMPLING_8) + { + usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + USARTx->BRR = brrtemp; + } + else + { + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); + } +} + +/** + * @brief Return current Baud Rate value, according to USARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock and Oversampling mode values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + * @rmtoll BRR BRR LL_USART_GetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t OverSampling) +{ + uint32_t usartdiv; + uint32_t brrresult = 0x0U; + uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue])); + + usartdiv = USARTx->BRR; + + if (usartdiv == 0U) + { + /* Do not perform a division by 0 */ + } + else if (OverSampling == LL_USART_OVERSAMPLING_8) + { + usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; + if (usartdiv != 0U) + { + brrresult = (periphclkpresc * 2U) / usartdiv; + } + } + else + { + if ((usartdiv & 0xFFFFU) != 0U) + { + brrresult = periphclkpresc / usartdiv; + } + } + return (brrresult); +} + +/** + * @brief Set Receiver Time Out Value (expressed in nb of bits duration) + * @rmtoll RTOR RTO LL_USART_SetRxTimeout + * @param USARTx USART Instance + * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout) +{ + MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout); +} + +/** + * @brief Get Receiver Time Out Value (expressed in nb of bits duration) + * @rmtoll RTOR RTO LL_USART_GetRxTimeout + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + */ +__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); +} + +/** + * @brief Set Block Length value in reception + * @rmtoll RTOR BLEN LL_USART_SetBlockLength + * @param USARTx USART Instance + * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) +{ + MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); +} + +/** + * @brief Get Block Length value in reception + * @rmtoll RTOR BLEN LL_USART_GetBlockLength + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature + * @{ + */ + +/** + * @brief Enable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_EnableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Disable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_DisableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Indicate if IrDA mode is enabled + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_IsEnabledIrda + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); +} + +/** + * @brief Configure IrDA Power Mode (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode + * @param USARTx USART Instance + * @param PowerMode This parameter can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_IRDA_POWER_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); +} + +/** + * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); +} + +/** + * @brief Set Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); +} + +/** + * @brief Return Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler + * @param USARTx USART Instance + * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature + * @{ + */ + +/** + * @brief Enable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Disable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Indicate if Smartcard NACK transmission is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); +} + +/** + * @brief Enable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_EnableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Disable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_DisableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Indicate if Smartcard mode is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); +} + +/** + * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. + * In transmission mode, it specifies the number of automatic retransmission retries, before + * generating a transmission error (FE bit set). + * In reception mode, it specifies the number or erroneous reception trials, before generating a + * reception error (RXNE and PE bits set) + * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount + * @param USARTx USART Instance + * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); +} + +/** + * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount + * @param USARTx USART Instance + * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); +} + +/** + * @brief Set Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); +} + +/** + * @brief Return Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler + * @param USARTx USART Instance + * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime + * @param USARTx USART Instance + * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); +} + +/** + * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime + * @param USARTx USART Instance + * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature + * @{ + */ +/** + * @brief Enable SPI Synchronous Slave mode + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_EnableSPISlave + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Disable SPI Synchronous Slave mode + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_DisableSPISlave + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Indicate if SPI Synchronous Slave mode is enabled + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable SPI Slave Selection using NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @note SPI Slave Selection depends on NSS input pin + * (The slave is selected when NSS is low and deselected when NSS is high). + * @rmtoll CR2 DIS_NSS LL_USART_EnableSPISlaveSelect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS); +} + +/** + * @brief Disable SPI Slave Selection using NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @note SPI Slave will be always selected and NSS input pin will be ignored. + * @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS); +} + +/** + * @brief Indicate if SPI Slave Selection depends on NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature + * @{ + */ + +/** + * @brief Set LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen + * @param USARTx USART Instance + * @param LINBDLength This parameter can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); +} + +/** + * @brief Return LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + */ +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); +} + +/** + * @brief Enable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_EnableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Disable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_DisableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Indicate if LIN mode is enabled + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature + * @{ + */ + +/** + * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime + * @param USARTx USART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); +} + +/** + * @brief Return DEDT (Driver Enable De-Assertion Time) + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime + * @param USARTx USART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); +} + +/** + * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime + * @param USARTx USART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); +} + +/** + * @brief Return DEAT (Driver Enable Assertion Time) + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime + * @param USARTx USART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); +} + +/** + * @brief Enable Driver Enable (DE) Mode + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_EnableDEMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Disable Driver Enable (DE) Mode + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_DisableDEMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Indicate if Driver Enable (DE) Mode is enabled + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); +} + +/** + * @brief Select Driver Enable Polarity + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity + * @param USARTx USART Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_DE_POLARITY_HIGH + * @arg @ref LL_USART_DE_POLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity); +} + +/** + * @brief Return Driver Enable Polarity + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DE_POLARITY_HIGH + * @arg @ref LL_USART_DE_POLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services + * @{ + */ + +/** + * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) + * @note In UART mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Asynchronous Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n + * CR2 CLKEN LL_USART_ConfigAsyncMode\n + * CR3 SCEN LL_USART_ConfigAsyncMode\n + * CR3 IREN LL_USART_ConfigAsyncMode\n + * CR3 HDSEL LL_USART_ConfigAsyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) +{ + /* In Asynchronous mode, the following bits must be kept cleared: + - LINEN, CLKEN bits in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Synchronous Mode + * @note In Synchronous mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the USART in Synchronous mode. + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * @note Other remaining configurations items related to Synchronous Mode + * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n + * CR2 CLKEN LL_USART_ConfigSyncMode\n + * CR3 SCEN LL_USART_ConfigSyncMode\n + * CR3 IREN LL_USART_ConfigSyncMode\n + * CR3 HDSEL LL_USART_ConfigSyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) +{ + /* In Synchronous mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); + /* set the UART/USART in Synchronous mode */ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in LIN Mode + * @note In LIN mode, the following bits must be kept cleared: + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also set the UART/USART in LIN mode. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function + * @note Other remaining configurations items related to LIN Mode + * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using + * dedicated functions + * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n + * CR2 STOP LL_USART_ConfigLINMode\n + * CR2 LINEN LL_USART_ConfigLINMode\n + * CR3 IREN LL_USART_ConfigLINMode\n + * CR3 SCEN LL_USART_ConfigLINMode\n + * CR3 HDSEL LL_USART_ConfigLINMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) +{ + /* In LIN mode, the following bits must be kept cleared: + - STOP and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); + /* Set the UART/USART in LIN mode */ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode + * @note In Half Duplex mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * This function also sets the UART/USART in Half Duplex mode. + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function + * @note Other remaining configurations items related to Half Duplex Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n + * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n + * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n + * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n + * CR3 IREN LL_USART_ConfigHalfDuplexMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) +{ + /* In Half Duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); + /* set the UART/USART in Half Duplex mode */ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Smartcard Mode + * @note In Smartcard mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also configures Stop bits to 1.5 bits and + * sets the USART in Smartcard mode (SCEN bit). + * Clock Output is also enabled (CLKEN). + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function + * @note Other remaining configurations items related to Smartcard Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n + * CR2 STOP LL_USART_ConfigSmartcardMode\n + * CR2 CLKEN LL_USART_ConfigSmartcardMode\n + * CR3 HDSEL LL_USART_ConfigSmartcardMode\n + * CR3 SCEN LL_USART_ConfigSmartcardMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) +{ + /* In Smartcard mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); + /* Configure Stop bits to 1.5 bits */ + /* Synchronous mode is activated by default */ + SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); + /* set the UART/USART in Smartcard mode */ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Irda Mode + * @note In IRDA mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the UART/USART in IRDA mode (IREN bit). + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function + * @note Other remaining configurations items related to Irda Mode + * (as Baud Rate, Word length, Power mode, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n + * CR2 CLKEN LL_USART_ConfigIrdaMode\n + * CR2 STOP LL_USART_ConfigIrdaMode\n + * CR3 SCEN LL_USART_ConfigIrdaMode\n + * CR3 HDSEL LL_USART_ConfigIrdaMode\n + * CR3 IREN LL_USART_ConfigIrdaMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) +{ + /* In IRDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register, + - SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); + /* set the UART/USART in IRDA mode */ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Multi processor Mode + * (several USARTs connected in a network, one of the USARTs can be the master, + * its TX output connected to the RX inputs of the other slaves USARTs). + * @note In MultiProcessor mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Multi processor Mode + * (as Baud Rate, Wake Up Method, Node address, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n + * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n + * CR3 SCEN LL_USART_ConfigMultiProcessMode\n + * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n + * CR3 IREN LL_USART_ConfigMultiProcessMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) +{ + /* In Multi Processor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the USART Parity Error Flag is set or not + * @rmtoll ISR PE LL_USART_IsActiveFlag_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Framing Error Flag is set or not + * @rmtoll ISR FE LL_USART_IsActiveFlag_FE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Noise error detected Flag is set or not + * @rmtoll ISR NE LL_USART_IsActiveFlag_NE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART OverRun Error Flag is set or not + * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART IDLE line detected Flag is set or not + * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); +} + +#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmission Complete Flag is set or not + * @rmtoll ISR TC LL_USART_IsActiveFlag_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); +} + +#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART LIN Break Detection Flag is set or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS interrupt Flag is set or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS Flag is set or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receiver Time Out Flag is set or not + * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART End Of Block Flag is set or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the SPI Slave Underrun error flag is set or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Auto-Baud Rate Error Flag is set or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Auto-Baud Rate Flag is set or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Busy Flag is set or not + * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Character Match Flag is set or not + * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Send Break Flag is set or not + * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not + * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not + * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receive Enable Acknowledge Flag is set or not + * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Empty Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Full Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not + * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Threshold Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Threshold Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); +} + +/** + * @brief Clear Parity Error Flag + * @rmtoll ICR PECF LL_USART_ClearFlag_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_PECF); +} + +/** + * @brief Clear Framing Error Flag + * @rmtoll ICR FECF LL_USART_ClearFlag_FE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_FECF); +} + +/** + * @brief Clear Noise Error detected Flag + * @rmtoll ICR NECF LL_USART_ClearFlag_NE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_NECF); +} + +/** + * @brief Clear OverRun Error Flag + * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_ORECF); +} + +/** + * @brief Clear IDLE line detected Flag + * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_IDLECF); +} + +/** + * @brief Clear TX FIFO Empty Flag + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TXFECF); +} + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll ICR TCCF LL_USART_ClearFlag_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TCCF); +} + +/** + * @brief Clear Smartcard Transmission Complete Before Guard Time Flag + * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF); +} + +/** + * @brief Clear LIN Break Detection Flag + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_LBDCF); +} + +/** + * @brief Clear CTS Interrupt Flag + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_CTSCF); +} + +/** + * @brief Clear Receiver Time Out Flag + * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_RTOCF); +} + +/** + * @brief Clear End Of Block Flag + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); +} + +/** + * @brief Clear SPI Slave Underrun Flag + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_UDRCF); +} + +/** + * @brief Clear Character Match Flag + * @rmtoll ICR CMCF LL_USART_ClearFlag_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_CMCF); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_EnableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Enable TX Empty and TX FIFO Not Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_EnableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable Character Match Interrupt + * @rmtoll CR1 CMIE LL_USART_EnableIT_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Enable Receiver Timeout Interrupt + * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE); +} + +/** + * @brief Enable End Of Block Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE); +} + +/** + * @brief Enable TX FIFO Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Enable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_USART_EnableIT_RXFF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Enable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. + * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Enable TX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +} + +/** + * @brief Enable RX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_DisableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Disable TX Empty and TX FIFO Not Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_DisableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable Character Match Interrupt + * @rmtoll CR1 CMIE LL_USART_DisableIT_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Disable Receiver Timeout Interrupt + * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); +} + +/** + * @brief Disable End Of Block Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); +} + +/** + * @brief Disable TX FIFO Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Disable RX FIFO Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Disable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. + * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable TX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +} + +/** + * @brief Disable RX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Check if the USART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); +} + +#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled. + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); +} + +#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Character Match Interrupt is enabled or disabled. + * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled. + * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART End Of Block Interrupt is enabled or disabled. + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS Interrupt is enabled or disabled. + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled. + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Disable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Indicate if DMA Disabling on Reception Error is disabled + * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n + * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr + * @param USARTx USART Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) + { + /* return address of TDR register */ + data_reg_addr = (uint32_t) &(USARTx->TDR); + } + else + { + /* return address of RDR register */ + data_reg_addr = (uint32_t) &(USARTx->RDR); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll RDR RDR LL_USART_ReceiveData8 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) +{ + return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll RDR RDR LL_USART_ReceiveData9 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) +{ + return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll TDR TDR LL_USART_TransmitData8 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) +{ + USARTx->TDR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll TDR TDR LL_USART_TransmitData9 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) +{ + USARTx->TDR = (uint16_t)(Value & 0x1FFUL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request an Automatic Baud Rate measurement on next received data frame + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ); +} + +/** + * @brief Request Break sending + * @rmtoll RQR SBKRQ LL_USART_RequestBreakSending + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ); +} + +/** + * @brief Put USART in mute mode and set the RWU flag + * @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ); +} + +/** + * @brief Request a Receive Data and FIFO flush + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @note Allows to discard the received data without reading them, and avoid an overrun + * condition. + * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ); +} + +/** + * @brief Request a Transmit data and FIFO flush + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + +/** + * @} + */ + +/** @defgroup USART_LL_Autonomous_Mode Configuration functions related to Autonomous mode feature + * @{ + */ + +/** + * @brief Enable Selected Trigger + * @rmtoll AUTOCR TRIGEN LL_USART_Enable_SelectedTrigger + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Enable_SelectedTrigger(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGEN); +} + +/** + * @brief Disable Selected Trigger + * @rmtoll AUTOCR TRIGEN LL_USART_Disable_SelectedTrigger + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Disable_SelectedTrigger(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGEN); +} + +/** + * @brief Indicate if Selected Trigger is disabled or enabled + * @rmtoll AUTOCR TRIGEN LL_USART_IsEnabled_SelectedTrigger + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabled_SelectedTrigger(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGEN) == (USART_AUTOCR_TRIGEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable Autonomous Send Idle Frame feature + * @rmtoll AUTOCR IDLEDIS LL_USART_Enable_AutonomousSendIdleFrame + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Enable_AutonomousSendIdleFrame(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->AUTOCR, USART_AUTOCR_IDLEDIS); +} + +/** + * @brief Disable Autonomous Send Idle Frame feature + * @rmtoll AUTOCR IDLEDIS LL_USART_Disable_AutonomousSendIdleFrame + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Disable_AutonomousSendIdleFrame(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->AUTOCR, USART_AUTOCR_IDLEDIS); +} + +/** + * @brief Indicate if Autonomous send Idle Frame feature is disabled or enabled + * @rmtoll AUTOCR IDLEDIS LL_USART_IsEnabled_AutonomousSendIdleFrame + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabled_AutonomousSendIdleFrame(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->AUTOCR, USART_AUTOCR_IDLEDIS) == (USART_AUTOCR_IDLEDIS)) ? 0UL : 1UL); +} + +/** + * @brief Configure the Number of transferred data in bytes + * @rmtoll AUTOCR TDN LL_USART_SetNbTxData + * @param USARTx USART Instance + * @param Nbdata This parameter can be a value between 0 and 0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetNbTxData(USART_TypeDef *USARTx, uint32_t Nbdata) +{ + MODIFY_REG(USARTx->AUTOCR, USART_AUTOCR_TDN, (uint16_t)Nbdata); +} + +/** + * @brief Retrieve the Number of transferred data in bytes + * @rmtoll AUTOCR TDN LL_USART_GetNbTxData + * @param USARTx USART Instance + * @retval Returned value can be a value between 0 and 0xFFFF + */ +__STATIC_INLINE uint32_t LL_USART_GetNbTxData(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TDN)); +} + +/** + * @brief Set the trigger polarity + * @rmtoll AUTOCR TRIGPOL LL_USART_SetTriggerPolarity + * @param USARTx USART Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_TRIG_POLARITY_RISING + * @arg @ref LL_USART_TRIG_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTriggerPolarity(USART_TypeDef *USARTx, uint32_t Polarity) +{ + MODIFY_REG(USARTx->AUTOCR, USART_AUTOCR_TRIGPOL, Polarity); +} + +/** + * @brief Get the trigger polarity + * @rmtoll AUTOCR TRIGPOL LL_USART_GetTriggerPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TRIG_POLARITY_RISING + * @arg @ref LL_USART_TRIG_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_USART_GetTriggerPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGPOL)); +} + +/** + * @brief Set the selected trigger + * @rmtoll AUTOCR TRIGSEL LL_USART_SetSelectedTrigger + * @param USARTx USART Instance + * @param Trigger This parameter can be one of the following values: + * @arg @ref LL_USART_GPDMA1_CH0_TCF_TRG + * @arg @ref LL_USART_GPDMA1_CH1_TCF_TRG + * @arg @ref LL_USART_GPDMA1_CH2_TCF_TRG + * @arg @ref LL_USART_GPDMA1_CH3_TCF_TRG + * @arg @ref LL_USART_EXTI_LINE6_TRG + * @arg @ref LL_USART_EXTI_LINE9_TRG + * @arg @ref LL_USART_LPTIM1_OUT_TRG + * @arg @ref LL_USART_LPTIM2_OUT_TRG + * @arg @ref LL_USART_COMP1_OUT_TRG + * @arg @ref LL_USART_COMP2_OUT_TRG + * @arg @ref LL_USART_RTC_ALRA_TRG + * @arg @ref LL_USART_RTC_WUT_TRG + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSelectedTrigger(USART_TypeDef *USARTx, uint32_t Trigger) +{ + MODIFY_REG(USARTx->AUTOCR, USART_AUTOCR_TRIGSEL, (Trigger << USART_AUTOCR_TRIGSEL_Pos)); +} + +/** + * @brief Get the selected trigger + * @rmtoll AUTOCR TRIGSEL LL_USART_GetSelectedTrigger + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_GPDMA1_CH0_TCF_TRG + * @arg @ref LL_USART_GPDMA1_CH1_TCF_TRG + * @arg @ref LL_USART_GPDMA1_CH2_TCF_TRG + * @arg @ref LL_USART_GPDMA1_CH3_TCF_TRG + * @arg @ref LL_USART_EXTI_LINE6_TRG + * @arg @ref LL_USART_EXTI_LINE9_TRG + * @arg @ref LL_USART_LPTIM1_OUT_TRG + * @arg @ref LL_USART_LPTIM2_OUT_TRG + * @arg @ref LL_USART_COMP1_OUT_TRG + * @arg @ref LL_USART_COMP2_OUT_TRG + * @arg @ref LL_USART_RTC_ALRA_TRG + * @arg @ref LL_USART_RTC_WUT_TRG + */ +__STATIC_INLINE uint32_t LL_USART_GetSelectedTrigger(const USART_TypeDef *USARTx) +{ + return (uint32_t)((READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct); +void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_LL_USART_H */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_utils.h b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_utils.h new file mode 100644 index 000000000..88e5b2dec --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_utils.h @@ -0,0 +1,356 @@ +/** + ****************************************************************************** + * @file stm32u5xx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32U5xx_LL_UTILS_H +#define __STM32U5xx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx.h" + +/** @addtogroup STM32U5xx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @brief Package data register base address + */ +#define PACKAGE_BASE_ADDRESS PACKAGE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ + +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLM; /*!< Division factor for PLL VCO input clock. + This parameter can be a value of @ref RCC_LL_EC_PLL1MBOOST_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_ConfigDomain_SYS(). */ + + uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 8 and Max_Data = 86 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_ConfigDomain_SYS(). */ + + uint32_t PLLR; /*!< Division for the main system clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_ConfigDomain_SYS(). */ +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB2Prescaler(). */ + + uint32_t APB3CLKDivider; /*!< The APB3 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB3_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB3Prescaler(). */ + +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ +/** + * @} + */ + +/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE + * @{ + */ +#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP72_SMPS 0x00000001U /*!< WLCSP72 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA132 0x00000003U /*!< UFBGA132 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000004U /*!< LQFP144 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP48 0x00000005U /*!< LQFP48 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000007U /*!< UFBGA169 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP64_SMPS 0x00000008U /*!< LQFP64 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_WLSCP90_SMPS 0x00000009U /*!< WLSCP90 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x0000000AU /*!< LQFP100 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA132_SMPS 0x0000000BU /*!< UFBGA132 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x0000000CU /*!< LQFP144 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_LQFP48_SMPS 0x0000000DU /*!< LQFP48 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS 0x0000000FU /*!< UFBGA169 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA64 0x00000012U /*!< UFBGA64 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA100 0x00000013U /*!< UFBGA100 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100_DSI_SMPS 0x00000014U /*!< LQFP100 DSI with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_DSI_SMPS 0x00000015U /*!< LQFP144 DSI with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA144_SMPS 0x00000019U /*!< UFBGA144 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP208_SMPS 0x0000001BU /*!< WLCSP208 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA216_SMPS 0x0000001CU /*!< TFBGA216 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA100_SMPS 0x0000001DU /*!< UFBGA100 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP56_SMPS 0x0000001EU /*!< WLCSP56 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP150_SMPS 0x0000001FU /*!< WLCSP150 or WLCSP150 DSI with internal package type */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40]) + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU); +} + +/** + * @brief Get Package type + * @retval Returned value can be one of the following values: + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100 + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA132 + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144 + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48 + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169 + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_WLSCP90_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA132_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP144 + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144 + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP144_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP208_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA216_SMPS + */ +__STATIC_INLINE uint32_t LL_GetPackageType(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU); +} + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Number of ticks + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + +void LL_Init1msTick(uint32_t HCLKFrequency); +void LL_Init1msTick_HCLK_Div8(uint32_t HCLKFrequency); +void LL_Init1msTick_LSE(void); +void LL_Init1msTick_LSI(void); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup LL_UTILS_Aliased_Functions LL UTILS Aliased Functions maintained for legacy purpose + * @{ + */ +#define LL_PLL1_ConfigSystemClock_MSI LL_PLL_ConfigSystemClock_MSI /* for legacy purpose */ +#define LL_PLL1_ConfigSystemClock_HSI LL_PLL_ConfigSystemClock_HSI /* for legacy purpose */ +#define LL_PLL1_ConfigSystemClock_HSE LL_PLL_ConfigSystemClock_HSE /* for legacy purpose */ +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32U5xx_LL_UTILS_H */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/LICENSE.md b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/LICENSE.md new file mode 100644 index 000000000..9226612ae --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/LICENSE.md @@ -0,0 +1,27 @@ +Copyright 2021 STMicroelectronics. +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its contributors +may be used to endorse or promote products derived from this software without +specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/LICENSE.txt b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/LICENSE.txt new file mode 100644 index 000000000..3edc4d146 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the BSD-3-Clause license shall apply. +You may obtain a copy of the BSD-3-Clause at: +https://opensource.org/licenses/BSD-3-Clause diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c new file mode 100644 index 000000000..cb2e9c166 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c @@ -0,0 +1,1098 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver + * @{ + */ + +#ifdef HAL_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup HAL_Private_Defines HAL Private Defines + * @{ + */ +/** + * @brief STM32U5xx HAL Driver version number 1.6.2 + */ +#define __STM32U5xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ +#define __STM32U5xx_HAL_VERSION_SUB1 (0x06UL) /*!< [23:16] sub1 version */ +#define __STM32U5xx_HAL_VERSION_SUB2 (0x02UL) /*!< [15:8] sub2 version */ +#define __STM32U5xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ +#define __STM32U5xx_HAL_VERSION ((__STM32U5xx_HAL_VERSION_MAIN << 24U)\ + |(__STM32U5xx_HAL_VERSION_SUB1 << 16U)\ + |(__STM32U5xx_HAL_VERSION_SUB2 << 8U )\ + |(__STM32U5xx_HAL_VERSION_RC)) + +#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms (to be confirmed) */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Exported variables --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the Flash interface the NVIC allocation and initial clock + configuration. It initializes the systick also when timeout is needed + and the backup domain when enabled. + (+) De-Initializes common part of the HAL. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief Configure the Flash prefetch, the time base source, NVIC and any required global low + * level hardware by calling the HAL_MspInit() callback function to be optionally defined + * in user file stm32u5xx_hal_msp.c. + * + * @note HAL_Init() function is called at the beginning of program after reset and before + * the clock configuration. + * + * @note In the default implementation the System Timer (SysTick) is used as source of time base. + * The SysTick configuration is based on MSI clock, as MSI is the clock + * used after a system Reset and the NVIC configuration is set to Priority group 4. + * Once done, time base tick starts incrementing: the tick variable counter is incremented + * each 1ms in the SysTick_Handler() interrupt handler. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + /* Configure Flash prefetch */ +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]; + + /* Select HCLK as SysTick clock source */ + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + return HAL_ERROR; + } + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the systick. + * This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_AHB1_FORCE_RESET(); + __HAL_RCC_AHB1_RELEASE_RESET(); + + __HAL_RCC_AHB2_FORCE_RESET(); + __HAL_RCC_AHB2_RELEASE_RESET(); + + __HAL_RCC_AHB3_FORCE_RESET(); + __HAL_RCC_AHB3_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + uint32_t ticknumber = 0U; + uint32_t systicksel; + + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ + if ((uint32_t)uwTickFreq == 0UL) + { + return HAL_ERROR; + } + + /* Check Clock source to calculate the tickNumber */ + if (READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) == SysTick_CTRL_CLKSOURCE_Msk) + { + /* HCLK selected as SysTick clock source */ + ticknumber = SystemCoreClock / (1000UL / (uint32_t)uwTickFreq); + } + else + { + systicksel = HAL_SYSTICK_GetCLKSourceConfig(); + switch (systicksel) + { + /* HCLK_DIV8 selected as SysTick clock source */ + case SYSTICK_CLKSOURCE_HCLK_DIV8: + /* Calculate tick value */ + ticknumber = (SystemCoreClock / (8000UL / (uint32_t)uwTickFreq)); + break; + /* LSI selected as SysTick clock source */ + case SYSTICK_CLKSOURCE_LSI: + /* Calculate tick value */ + ticknumber = (LSI_VALUE / (1000UL / (uint32_t)uwTickFreq)); + break; + /* LSE selected as SysTick clock source */ + case SYSTICK_CLKSOURCE_LSE: + /* Calculate tick value */ + ticknumber = (LSE_VALUE / (1000UL / (uint32_t)uwTickFreq)); + break; + default: + /* Nothing to do */ + break; + } + } + + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(ticknumber) > 0U) + { + return HAL_ERROR; + } + + /* Configure the SysTick IRQ priority */ + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during SLEEP mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += (uint32_t)uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval Status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32U5xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); +} + +/** + * @brief Return the first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return (READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Return the second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Return the third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @} + */ + + +/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions + * @brief HAL Debug functions + * +@verbatim + =============================================================================== + ##### HAL Debug functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief Enable the Debug Module during STOP0/STOP1/STOP2 modes. + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP0/STOP1/STOP2 modes. + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode. + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode. + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions + * @brief HAL SYSCFG configuration functions + * +@verbatim + =============================================================================== + ##### HAL SYSCFG configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the Voltage reference buffer + (+) Enable/Disable the Voltage reference buffer + (+) Enable/Disable the I/O analog switch voltage booster + +@endverbatim + * @{ + */ + +/** + * @brief Configure the internal voltage reference buffer voltage scale. + * @param VoltageScaling: specifies the output voltage to achieve + * This parameter can be one of the following values: + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 1.5 V. + * This requires VDDA equal to or higher than 1.8 V. + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT1 around 1.8 V. + * This requires VDDA equal to or higher than 2.1 V. + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT1 around 2.048 V. + * This requires VDDA equal to or higher than 2.4 V. + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT1 around 2.5 V. + * This requires VDDA equal to or higher than 2.8 V. + * @retval None + */ +void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); + + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling); +} + +/** + * @brief Configure the internal voltage reference buffer high impedance mode. + * @param Mode: specifies the high impedance mode + * This parameter can be one of the following values: + * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. + * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. + * @retval None + */ +void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); + + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); +} + +/** + * @brief Tune the Internal Voltage Reference buffer (VREFBUF). + * @retval None + */ +void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); + + MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue); +} + +/** + * @brief Enable the Internal Voltage Reference buffer (VREFBUF). + * @retval HAL_OK/HAL_TIMEOUT + */ +HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) +{ + uint32_t tickstart; + + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait for VRR bit */ + while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL) + { + if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable the Internal Voltage Reference buffer (VREFBUF). + * + * @retval None + */ +void HAL_SYSCFG_DisableVREFBUF(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} + +/** + * @brief Enable the I/O analog switch voltage booster + * + * @retval None + */ +void HAL_SYSCFG_EnableIOAnalogBooster(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); +} + +/** + * @brief Disable the I/O analog switch voltage booster + * + * @retval None + */ +void HAL_SYSCFG_DisableIOAnalogBooster(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); +} + +/** + * @brief Enable the I/O analog switch voltage selection + * + * @retval None + */ +void HAL_SYSCFG_EnableIOAnalogVoltageSelection(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); +} + +/** + * @brief Disable the I/O analog switch voltage selection + * + * @retval None + */ +void HAL_SYSCFG_DisableIOAnalogVoltageSelection(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); +} + +#if defined(SYSCFG_CFGR1_ENDCAP) +/** + * @brief Set decoupling capacitance on HSPI supply. + * @rmtoll SYSCFG_CFGR1 ENDCAP HAL_SYSCFG_SetHSPIDecouplingCapacitance + * @param Capacitance This parameter can be one of the following values: + * @arg @ref SYSCFG_HSPI_CAPACITANCE_OFF + * @arg @ref SYSCFG_HSPI_CAPACITANCE_1_DIV_3 + * @arg @ref SYSCFG_HSPI_CAPACITANCE_2_DIV_3 + * @arg @ref SYSCFG_HSPI_CAPACITANCE_FULL + * @retval None + */ +void HAL_SYSCFG_SetHSPIDecouplingCapacitance(uint32_t Capacitance) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_DECOUPLING_CAPACITANCE(Capacitance)); + + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ENDCAP, Capacitance); +} + +/** + * @brief Get decoupling capacitance on HSPI supply. + * @rmtoll SYSCFG_CFGR1 ENDCAP HAL_SYSCFG_GetHSPIDecouplingCapacitance + * @retval Returned value can be one of the following values: + * @arg @ref SYSCFG_HSPI_CAPACITANCE_OFF + * @arg @ref SYSCFG_HSPI_CAPACITANCE_1_DIV_3 + * @arg @ref SYSCFG_HSPI_CAPACITANCE_2_DIV_3 + * @arg @ref SYSCFG_HSPI_CAPACITANCE_FULL + */ +uint32_t HAL_SYSCFG_GetHSPIDecouplingCapacitance(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ENDCAP)); +} +#endif /* SYSCFG_CFGR1_ENDCAP */ + +#if defined(SYSCFG_CFGR1_SRAMCACHED) +/** + * @brief Enable the Cacheability of internal SRAMx by DCACHE2 + * + * @retval None + */ +void HAL_SYSCFG_EnableSRAMCached(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED); +} + +/** + * @brief Disable the Cacheability of internal SRAMx by DCACHE2 + * + * @retval None + */ +void HAL_SYSCFG_DisableSRAMCached(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED); +} +#endif /* SYSCFG_CFGR1_SRAMCACHED */ + +/** + * @brief Enable the Compensation Cell of GPIO supplied by VDD + * @rmtoll CCCSR EN1 HAL_SYSCFG_EnableVddCompensationCell + * @note The vdd compensation cell can be used only when the device supply + * voltage ranges from 1.71 to 3.6 V + * @retval None + */ +void HAL_SYSCFG_EnableVddCompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1); +} + +/** + * @brief Enable the Compensation Cell of GPIO supplied by VDDIO2 + * @rmtoll CCCSR EN2 HAL_SYSCFG_EnableVddIO2CompensationCell + * @note The Vdd I/O compensation cell can be used only when the device supply + * voltage ranges from 1.08 to 3.6 V + * @retval None + */ +void HAL_SYSCFG_EnableVddIO2CompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2); +} + +#if defined(SYSCFG_CCCSR_EN3) +/** + * @brief Enable the Compensation Cell of HSPI IO supplied by VDD + * @rmtoll CCCSR EN3 HAL_SYSCFG_EnableVddHSPICompensationCell + * @retval None + */ +void HAL_SYSCFG_EnableVddHSPICompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3); +} +#endif /* SYSCFG_CCCSR_EN3 */ + +/** + * @brief Disable the Compensation Cell of GPIO supplied by VDD + * @rmtoll CCCSR EN1 HAL_SYSCFG_DisableVddCompensationCell + * @note The Vdd compensation cell can be used only when the device supply + * voltage ranges from 1.71 to 3.6 V + * @retval None + */ +void HAL_SYSCFG_DisableVddCompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1); +} + +/** + * @brief Disable the Compensation Cell of GPIO supplied by VDDIO2 + * @rmtoll CCCSR EN2 HAL_SYSCFG_DisableVddIO2CompensationCell + * @note The Vdd I/O compensation cell can be used only when the device supply + * voltage ranges from 1.08 to 3.6 V + * @retval None + */ +void HAL_SYSCFG_DisableVddIO2CompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2); +} + +#if defined(SYSCFG_CCCSR_EN3) +/** + * @brief Disable the Compensation Cell of HSPI IO supplied by VDD + * @rmtoll CCCSR EN3 HAL_SYSCFG_DisableVddHSPICompensationCell + * @retval None + */ +void HAL_SYSCFG_DisableVddHSPICompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3); +} +#endif /* SYSCFG_CCCSR_EN3 */ +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group5 HAL SYSCFG lock management functions + * @brief SYSCFG lock management functions. + * +@verbatim + =============================================================================== + ##### SYSCFG lock functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Lock the SYSCFG item(s). + * @note Setting lock(s) depends on privilege mode in secure/non-secure code + * Lock(s) cleared only at system reset + * @param Item Item(s) to set lock on. + * This parameter can be a combination of @ref SYSCFG_Lock_items + * @retval None + */ +void HAL_SYSCFG_Lock(uint32_t Item) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_LOCK_ITEMS(Item)); + + /* Privilege secure/non-secure locks */ + SYSCFG->CNSLCKR = (0xFFFFU & Item); /* non-secure lock item in 16 lowest bits */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Privilege secure only locks */ + SYSCFG->CSLCKR = ((0xFFFF0000U & Item) >> 16U); /* Secure-only lock item in 16 highest bits */ +#endif /* __ARM_FEATURE_CMSE */ +} + +/** + * @brief Get the lock state of SYSCFG item. + * @note Getting lock(s) depends on privilege mode in secure/non-secure code + * @param pItem pointer to return locked items + * the return value can be a combination of @ref SYSCFG_Lock_items + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem) +{ + uint32_t tmp_lock; + + /* Check null pointer */ + if (pItem == NULL) + { + return HAL_ERROR; + } + + /* Get the non-secure lock state */ + tmp_lock = SYSCFG->CNSLCKR; + + /* Get the secure lock state in secure code */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + tmp_lock |= (SYSCFG->CSLCKR << 16U); +#endif /* __ARM_FEATURE_CMSE */ + + /* Return overall lock status */ + *pItem = tmp_lock; + + return HAL_OK; +} + +/** + * @} + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** @defgroup HAL_Exported_Functions_Group6 HAL SYSCFG attributes management functions + * @brief SYSCFG attributes management functions. + * +@verbatim + =============================================================================== + ##### SYSCFG attributes functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configure the SYSCFG item attribute(s). + * @note Available attributes are to secure SYSCFG items, so this function is + * only available in secure + * @param Item Item(s) to set attributes on. + * This parameter can be a one or a combination of @ref SYSCFG_Attributes_items + * @param Attributes specifies the secure/non-secure attributes. + * @retval None + */ +void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_SYSCFG_ITEMS_ATTRIBUTES(Item)); + assert_param(IS_SYSCFG_ATTRIBUTES(Attributes)); + + tmp = SYSCFG_S->SECCFGR; + + /* Set or reset Item */ + if ((Attributes & SYSCFG_SEC) != 0x00U) + { + tmp |= Item; + } + else + { + tmp &= ~Item; + } + + /* Set secure attributes */ + SYSCFG_S->SECCFGR = tmp; +} + +/** + * @brief Get the attribute of a SYSCFG item. + * @note Available attributes are to secure SYSCFG items, so this function is + * only available in secure + * @param Item Single item to get secure/non-secure attribute from. + * @param pAttributes pointer to return the attribute. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes) +{ + /* Check null pointer */ + if (pAttributes == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SYSCFG_ITEMS_ATTRIBUTES(Item)); + + /* Get the secure attribute state */ + if ((SYSCFG_S->SECCFGR & Item) != 0U) + { + *pAttributes = SYSCFG_SEC; + } + else + { + *pAttributes = SYSCFG_NSEC; + } + + return HAL_OK; +} + +/** + * @} + */ + +#endif /* __ARM_FEATURE_CMSE */ + +#ifdef SYSCFG_OTGHSPHYCR_EN +/** + * @brief Enable the OTG PHY . + * @param OTGPHYConfig Defines the OTG PHY configuration. + This parameter can be one of @ref SYSCFG_OTG_PHY_Enable + * @retval None + */ +void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_CONFIG(OTGPHYConfig)); + + MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN, OTGPHYConfig); +} + +/** + * @brief Set the OTG PHY Power Down config. + * @param PowerDownConfig Defines the OTG PHY Power down configuration. + This parameter can be one of @ref SYSCFG_OTG_PHY_PowerDown + * @retval None + */ +void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(PowerDownConfig)); + + MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL, PowerDownConfig); +} + +/** + * @brief Set the OTG PHY reference clock selection. + * @param RefClkSelection Defines the OTG PHY reference clock selection. + This parameter can be one of the @ref SYSCFG_OTG_PHY_RefenceClockSelection + * @retval None + */ +void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClkSelection) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(RefClkSelection)); + + MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_CLKSEL, RefClkSelection); +} + +/** + * @brief Set the OTG PHY Disconnect Threshold. + * @param DisconnectThreshold Defines the voltage level for the threshold used to detect a disconnect event. + This parameter can be one of the @ref SYSCFG_OTG_PHYTUNER_DisconnectThreshold + * @retval None + */ + +void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_DISCONNECT(DisconnectThreshold)); + + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE, DisconnectThreshold); +} + +/** + * @brief Adjust the voltage level for the threshold used to detect valid high speed data. + * @param SquelchThreshold Defines the voltage level. + This parameter can be onez of the @ref SYSCFG_OTG_PHYTUNER_SquelchThreshold + + * @retval None + */ + +void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_SQUELCH(SquelchThreshold)); + + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_SQRXTUNE, SquelchThreshold); +} + +/** + * @brief Set the OTG PHY Current config. + * @param PreemphasisCurrent Defines the current configuration. + This parameter can be one of the @ref SYSCFG_OTG_PHYTUNER_PreemphasisCurrent + + * @retval None + */ + +void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_PREEMPHASIS(PreemphasisCurrent)); + + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE, PreemphasisCurrent); +} + +#endif /* SYSCFG_OTGHSPHYCR_EN */ + +/** + * @} + */ + +#endif /* HAL_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c new file mode 100644 index 000000000..88eeaf26a --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c @@ -0,0 +1,836 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and Configuration functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M33 exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function. + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest pre-emption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure SysTick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x0F). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32u5xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + [..] + *** How to configure MPU using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the Memory Protection Unit (MPU). + + (#) Disable the MPU using HAL_MPU_Disable(). + (#) Configure the necessary MPU memory attributes using HAL_MPU_ConfigMemoryAttributes(). + (#) Configure the necessary MPU regions using HAL_MPU_ConfigRegion() ennsuring that the MPU region configuration link to + the right MPU attributes number. + (#) Enable the MPU using HAL_MPU_Enable() function. + + -@- The memory management fault exception is enabled in HAL_MPU_Enable() function and the system will enter the memory + management fault handler MemManage_Handler() when an illegal memory access is performed. + -@- If the MPU has previously been programmed, disable the unused regions to prevent any previous region configuration + from affecting the new MPU configuration. + -@- MPU APIs ending with '_NS' allow to control the non-secure Memory Protection Unit (MPU_NS) from the secure context + and the same sequence as above applies to configure the non-secure MPU. + + @endverbatim + ****************************************************************************** + + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. + +======================================================================================================================== + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description +======================================================================================================================== + NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority + | | | 4 bits for subpriority +------------------------------------------------------------------------------------------------------------------------ + NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority + | | | 3 bits for subpriority +------------------------------------------------------------------------------------------------------------------------ + NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority +------------------------------------------------------------------------------------------------------------------------ + NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bit for subpriority +------------------------------------------------------------------------------------------------------------------------ + NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bit for subpriority +======================================================================================================================== + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Functions CORTEX Private Functions + * @{ + */ +static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const pMPU_RegionInit); +static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + SysTick functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Set the priority grouping field (pre-emption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup: The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, + * 1 bit for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, + * 0 bit for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Set the priority of an interrupt. + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32u5xxxx.h)) + * @param PreemptPriority: The pre-emption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority: the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup; + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enable a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32u5xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disable a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32u5xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiate a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + if ((TicksNumb - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + /* Reload value impossible */ + return (1UL); + } + + /* Set reload register */ + WRITE_REG(SysTick->LOAD, (uint32_t)(TicksNumb - 1UL)); + + /* Load the SysTick Counter Value */ + WRITE_REG(SysTick->VAL, 0UL); + + /* Enable SysTick IRQ and SysTick Timer */ + SET_BIT(SysTick->CTRL, (SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk)); + + /* Function successful */ + return (0UL); +} +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ + +/** + * @brief Get the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Get the priority of an interrupt. + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32u5xxxx.h)) + * @param PriorityGroup: the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, + * 1 bit for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, + * 0 bit for subpriority + * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority: Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, + uint32_t *const pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Set Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32u5xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Get Pending Interrupt (read the pending register in the NVIC + * and return the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32u5xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clear the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32u5xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Get active interrupt (read the active register in NVIC and return the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32u5xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/** + * @brief Configure the SysTick clock source. + * @param CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + switch (CLKSource) + { + /* Select HCLK as Systick clock source */ + case SYSTICK_CLKSOURCE_HCLK: + SET_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk); + break; + /* Select HCLK_DIV8 as Systick clock source */ + case SYSTICK_CLKSOURCE_HCLK_DIV8: + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk); + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, (0x00000000U)); + break; + /* Select LSI as Systick clock source */ + case SYSTICK_CLKSOURCE_LSI: + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk); + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_0); + break; + /* Select LSE as Systick clock source */ + case SYSTICK_CLKSOURCE_LSE: + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk); + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_1); + break; + default: + /* Nothing to do */ + break; + } +} + +/** + * @brief Get the SysTick clock source configuration. + * @retval SysTick clock source that can be one of the following values: + * @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + */ +uint32_t HAL_SYSTICK_GetCLKSourceConfig(void) +{ + uint32_t systick_source; + uint32_t systick_rcc_source; + + /* Read SysTick->CTRL register for internal or external clock source */ + if (READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) != 0U) + { + /* Internal clock source */ + systick_source = SYSTICK_CLKSOURCE_HCLK; + } + else + { + /* External clock source, check the selected one in RCC */ + systick_rcc_source = READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL); + + switch (systick_rcc_source) + { + case (0x00000000U): + systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8; + break; + + case (RCC_CCIPR1_SYSTICKSEL_0): + systick_source = SYSTICK_CLKSOURCE_LSI; + break; + + case (RCC_CCIPR1_SYSTICKSEL_1): + systick_source = SYSTICK_CLKSOURCE_LSE; + break; + + default: + systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8; + break; + } + } + return systick_source; +} + +/** + * @brief Handle SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + + +/** + * @brief Enable the MPU. + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ + + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable the non-secure MPU. + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ + + /* Enable the MPU */ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Disable the MPU. + * @retval None + */ +void HAL_MPU_Disable(void) +{ + __DMB(); /* Force any outstanding transfers to complete before disabling MPU */ + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU */ + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Disable the non-secure MPU. + * @retval None + */ +void HAL_MPU_Disable_NS(void) +{ + __DMB(); /* Force any outstanding transfers to complete before disabling MPU */ + + /* Disable fault exceptions */ + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU */ + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Enable the MPU Region. + * @retval None + * @param RegionNumber Specifies the index of the region to enable. + * this parameter can be a value of @ref CORTEX_MPU_Region_Number + */ +void HAL_MPU_EnableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable the non-secure MPU Region. + * @retval None + * @param RegionNumber Specifies the index of the region to enable. + * this parameter can be a value of @ref CORTEX_MPU_Region_Number + */ +void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU_NS->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} +#endif /*__ARM_FEATURE_CMSE*/ + +/** + * @brief Disable the MPU Region. + * @retval None + * @param RegionNumber Specifies the index of the region to disable. + * this parameter can be a value of @ref CORTEX_MPU_Region_Number + */ +void HAL_MPU_DisableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Disable the non-secure MPU Region. + * @retval None + * @param RegionNumber Specifies the index of the region to disable. + * this parameter can be a value of @ref CORTEX_MPU_Region_Number + */ +void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU_NS->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} +#endif /*__ARM_FEATURE_CMSE*/ + +/** + * @brief Initialize and configure the Region and the memory to be protected. + * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit) +{ + MPU_ConfigRegion(MPU, pMPU_RegionInit); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Initialize and configure the Region and the memory to be protected for non-secure MPU. + * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit) +{ + MPU_ConfigRegion(MPU_NS, pMPU_RegionInit); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Initialize and configure the memory attributes. + * @param pMPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit) +{ + MPU_ConfigMemoryAttributes(MPU, pMPU_AttributesInit); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Initialize and configure the memory attributes for non-secure MPU. + * @param pMPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit) +{ + MPU_ConfigMemoryAttributes(MPU_NS, pMPU_AttributesInit); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup CORTEX_Private_Functions + * @{ + */ +static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const pMPU_RegionInit) +{ + /* Check the parameters */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + assert_param(IS_MPU_INSTANCE(MPUx)); +#endif /* __ARM_FEATURE_CMSE */ + assert_param(IS_MPU_REGION_NUMBER(pMPU_RegionInit->Number)); + assert_param(IS_MPU_REGION_ENABLE(pMPU_RegionInit->Enable)); + assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission)); + assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable)); + + /* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */ + __DMB(); + + /* Set the Region number */ + MPUx->RNR = pMPU_RegionInit->Number; + + /* Disable the Region */ + CLEAR_BIT(MPUx->RLAR, MPU_RLAR_EN_Msk); + + MPUx->RBAR = (((uint32_t)pMPU_RegionInit->BaseAddress & 0xFFFFFFE0UL) | + ((uint32_t)pMPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) | + ((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) | + ((uint32_t)pMPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos)); + + MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) | + ((uint32_t)pMPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) | + ((uint32_t)pMPU_RegionInit->Enable << MPU_RLAR_EN_Pos)); +} + + +static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit) +{ + __IO uint32_t *p_mair; + uint32_t attr_values; + uint32_t attr_number; + + /* Check the parameters */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + assert_param(IS_MPU_INSTANCE(MPUx)); +#endif /* __ARM_FEATURE_CMSE */ + assert_param(IS_MPU_ATTRIBUTES_NUMBER(pMPU_AttributesInit->Number)); + /* No need to check Attributes value as all 0x0..0xFF possible */ + + /* Follow ARM recommendation with Data Memory Barrier prior to MPUx configuration */ + __DMB(); + + if (pMPU_AttributesInit->Number < MPU_ATTRIBUTES_NUMBER4) + { + /* Program MPU_MAIR0 */ + p_mair = &(MPUx->MAIR0); + attr_number = pMPU_AttributesInit->Number; + } + else + { + /* Program MPU_MAIR1 */ + p_mair = &(MPUx->MAIR1); + attr_number = (uint32_t)pMPU_AttributesInit->Number - 4U; + } + + attr_values = *(p_mair); + attr_values &= ~(0xFFUL << (attr_number * 8U)); + *(p_mair) = attr_values | ((uint32_t)pMPU_AttributesInit->Attributes << (attr_number * 8U)); +} +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c new file mode 100644 index 000000000..5207ddfde --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c @@ -0,0 +1,1690 @@ +/** + ********************************************************************************************************************** + * @file stm32u5xx_hal_dma.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following functionalities of the Direct Memory Access + * (DMA) peripheral: + * + Initialization/De-Initialization Functions + * + I/O Operation Functions + * + State and Errors Functions + * + DMA Attributes Functions + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + @verbatim + ====================================================================================================================== + ##### How to use this driver ##### + ====================================================================================================================== + + [..] + DMA transfer modes are divided to 2 major categories : + (+) Normal transfers (legacy) + (+) Linked-list transfers + + [..] + Normal transfers mode is initialized via the standard module and linked-list mode is configured via the extended + module. + + [..] + Additionally to linked-list capability, all advanced DMA features are managed and configured via the extended + module as extensions to normal mode. + Advanced features are : + (+) Repeated block feature. + (+) Trigger feature. + (+) Data handling feature. + + [..] + DMA Legacy circular transfer, is replaced by circular linked-list configuration. + + + *** Initialization and De-Initialization *** + ============================================ + [..] + For a given channel, enable and configure the peripheral to be connected to the DMA Channel (except for internal + SRAM/FLASH memories: no initialization is necessary) please refer to Reference manual for connection between + peripherals and DMA requests. + + [..] + For a given channel, use HAL_DMA_Init function to program the required configuration for normal transfer through + the following parameters: + + (+) Request : Specifies the DMA channel request + Request parameters : + (++) can be a value of DMA_Request_Selection + + (+) BlkHWRequest : Specifies the Block hardware request mode for DMA channel + (++) can be a value of DMA_Block_Request + + (+) Direction : Specifies the transfer direction for DMA channel + (++) can be a value of DMA_Transfer_Direction + + (+) SrcInc : Specifies the source increment mode for the DMA channel + (++) can be a value of DMA_Source_Increment_Mode + + (+) DestInc : Specifies the destination increment mode for the DMA channel + (++) can be a value of DMA_Destination_Increment_Mode + + (+) SrcDataWidth : Specifies the source data width for the DMA channel + (++) can be a value of DMA_Source_Data_Width + + (+) DestDataWidth : Specifies the destination data width for the DMA channel + (++) can be a value of DMA_Destination_Data_Width + + (+) Priority : Specifies the priority for the DMA channel + (++) can be a value of DMA_Priority_Level + + (+) SrcBurstLength : Specifies the source burst length (number of beats) for the DMA channel + (++) can be a value of between 1 and 64 + + (+) DestBurstLength : Specifies the destination burst length (number of beats) for the DMA channel + (++) can be a value of between 1 and 64 + + (+) TransferAllocatedPort : Specifies the source and destination allocated ports + (++) can be a value of DMA_Transfer_Allocated_Port + + (+) TransferEventMode : Specifies the transfer event mode for the DMA channel + (++) can be a value of DMA_Transfer_Event_Mode + + (+) Mode : Specifies the transfer mode for the DMA channel + (++) can be DMA_NORMAL + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start a DMA normal transfer after the configuration of source address, destination + address and the size of data to be transferred. + + (+) Use HAL_DMA_PollForTransfer() to poll for selected transfer level. In this case a fixed Timeout can be + configured by User depending on his application. + Transfer level can be : + (++) HAL_DMA_HALF_TRANSFER + (++) HAL_DMA_FULL_TRANSFER + For circular transfer, this API returns an HAL_ERROR with HAL_DMA_ERROR_NOT_SUPPORTED error code. + + (+) Use HAL_DMA_Abort() function to abort any ongoing DMA transfer in blocking mode. + This API returns HAL_ERROR when there is no ongoing transfer or timeout is reached when disabling the DMA + channel. (This API should not be called from an interrupt service routine) + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + + (+) Use HAL_DMA_RegisterCallback() function to register user callbacks from the following list : + (++) XferCpltCallback : transfer complete callback. + (++) XferHalfCpltCallback : half transfer complete callback. + (++) XferErrorCallback : transfer error callback. + (++) XferAbortCallback : transfer abort complete callback. + (++) XferSuspendCallback : transfer suspend complete callback. + + (+) Use HAL_DMA_Start_IT() to start the DMA transfer after the enable of DMA interrupts and the configuration + of source address,destination address and the size of data to be transferred. + + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() interrupt subroutine to handle any DMA interrupt. + + (+) Use HAL_DMA_Abort_IT() function to abort any on-going DMA transfer in non-blocking mode. + This API will suspend immediately the DMA channel execution. When the transfer is effectively suspended, + an interrupt is generated and HAL_DMA_IRQHandler() will reset the channel and execute the callback + XferAbortCallback. (This API could be called from an interrupt service routine) + + + *** State and errors *** + ======================== + [..] + (+) Use HAL_DMA_GetState() function to get the DMA state. + (+) Use HAL_DMA_GetError() function to get the DMA error code. + + + *** Security and privilege attributes *** + ========================================= + [..] + (+) Use HAL_DMA_ConfigChannelAttributes() function to configure DMA channel security and privilege attributes. + (++) Security : at channel level, at source level and at destination level. + (++) Privilege : at channel level. + (+) Use HAL_DMA_GetConfigChannelAttributes() function to get the DMA channel attributes. + (+) Use HAL_DMA_LockChannelAttributes() function to lock the DMA channel security and privilege attributes + configuration. This API can be called once after each system boot. + If called again, HAL_DMA_ConfigChannelAttributes() API has no effect. + Unlock is done either by a system boot or a by an RCC reset. + (+) Use HAL_DMA_GetLockChannelAttributes() function to get the attributes lock status. + + + *** DMA HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE : Enable the specified DMA Channel. + (+) __HAL_DMA_DISABLE : Disable the specified DMA Channel. + (+) __HAL_DMA_GET_FLAG : Get the DMA Channel pending flags. + (+) __HAL_DMA_CLEAR_FLAG : Clear the DMA Channel pending flags. + (+) __HAL_DMA_ENABLE_IT : Enable the specified DMA Channel interrupts. + (+) __HAL_DMA_DISABLE_IT : Disable the specified DMA Channel interrupts. + (+) __HAL_DMA_GET_IT_SOURCE : Check whether the specified DMA Channel interrupt has occurred or not. + + [..] + (@) You can refer to the header file of the DMA HAL driver for more useful macros. + + @endverbatim + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef ---------------------------------------------------------------------------------------------------*/ +/* Private constants -------------------------------------------------------------------------------------------------*/ +/* Private macro -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize); +static void DMA_Init(DMA_HandleTypeDef const *const hdma); + +/* Exported functions ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * +@verbatim + ====================================================================================================================== + ##### Initialization and de-initialization functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the DMA channel in normal mode. + + [..] + (+) The HAL_DMA_Init() function follows the DMA channel configuration procedures as described in reference manual. + (+) The HAL_DMA_DeInit() function allows to de-initialize the DMA channel. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef and + * create the associated handle. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + if (hdma->Init.Direction != DMA_MEMORY_TO_MEMORY) + { + assert_param(IS_DMA_REQUEST(hdma->Init.Request)); + } + assert_param(IS_DMA_BLOCK_HW_REQUEST(hdma->Init.BlkHWRequest)); + assert_param(IS_DMA_SOURCE_INC(hdma->Init.SrcInc)); + assert_param(IS_DMA_DESTINATION_INC(hdma->Init.DestInc)); + assert_param(IS_DMA_SOURCE_DATA_WIDTH(hdma->Init.SrcDataWidth)); + assert_param(IS_DMA_DESTINATION_DATA_WIDTH(hdma->Init.DestDataWidth)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + assert_param(IS_DMA_TCEM_EVENT_MODE(hdma->Init.TransferEventMode)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + /* Check DMA channel instance */ + if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) + { + assert_param(IS_DMA_BURST_LENGTH(hdma->Init.SrcBurstLength)); + assert_param(IS_DMA_BURST_LENGTH(hdma->Init.DestBurstLength)); + assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(hdma->Init.TransferAllocatedPort)); + } + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Initialize the callbacks */ + if (hdma->State == HAL_DMA_STATE_RESET) + { + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + } + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA channel is effectively disabled */ + while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Initialize the DMA channel registers */ + DMA_Init(hdma); + + /* Update DMA channel operation mode */ + hdma->Mode = hdma->Init.Mode; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA channel when it is configured in normal mode. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma) +{ + + DMA_TypeDef *p_dma_instance; + + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Disable the selected DMA Channel */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA channel is effectively disabled */ + while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Reset DMA Channel registers */ + hdma->Instance->CLBAR = 0U; + hdma->Instance->CCR = 0U; + hdma->Instance->CTR1 = 0U; + hdma->Instance->CTR2 = 0U; + hdma->Instance->CBR1 = 0U; + hdma->Instance->CSAR = 0U; + hdma->Instance->CDAR = 0U; + hdma->Instance->CLLR = 0U; + + /* Reset 2D Addressing registers */ + if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) + { + hdma->Instance->CTR3 = 0U; + hdma->Instance->CBR2 = 0U; + } + + /* Clear privilege attribute */ + CLEAR_BIT(p_dma_instance->PRIVCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Clear secure attribute */ + CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | + DMA_FLAG_TO)); + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + + /* Clean DMA queue */ + hdma->LinkedListQueue = NULL; + + /* Clean DMA parent */ + if (hdma->Parent != NULL) + { + hdma->Parent = NULL; + } + + /* Update DMA channel operation mode */ + hdma->Mode = DMA_NORMAL; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * +@verbatim + ====================================================================================================================== + ##### IO operation functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Configure the source, destination address and data size and Start DMA transfer in normal mode + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + (+) Register and Unregister DMA callbacks + + [..] + (+) The HAL_DMA_Start() function allows to start the DMA channel transfer in normal mode (Blocking mode). + (+) The HAL_DMA_Start_IT() function allows to start the DMA channel transfer in normal mode (Non-blocking mode). + (+) The HAL_DMA_Abort() function allows to abort any on-going transfer (Blocking mode). + (+) The HAL_DMA_Abort_IT() function allows to abort any on-going transfer (Non-blocking mode). + (+) The HAL_DMA_PollForTransfer() function allows to poll on half transfer and transfer complete (Blocking mode). + This API cannot be used for circular transfers. + (+) The HAL_DMA_IRQHandler() function allows to handle any DMA channel interrupt (Non-blocking mode). + (+) The HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback() functions allow respectively to register and + unregister user customized callbacks. + User callbacks are called under HAL_DMA_IRQHandler(). + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA channel transfer in normal mode (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for + * the specified DMA Channel. + * @param SrcAddress : The source data address. + * @param DstAddress : The destination data address. + * @param SrcDataSize : The length of data to be transferred from source to destination in bytes. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize)); + + /* Process locked */ + __HAL_LOCK(hdma); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source address, destination address, the data size and clear flags */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize); + + /* Enable DMA channel */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Starts the DMA channel transfer in normal mode with interrupts enabled (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param SrcAddress : The source data address. + * @param DstAddress : The destination data address. + * @param SrcDataSize : The length of data to be transferred from source to destination in bytes. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize)); + + /* Process locked */ + __HAL_LOCK(hdma); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source address, destination address, the data size and clear flags */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize); + + /* Enable common interrupts: Transfer Complete and Transfer Errors ITs */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO)); + + /* Check half transfer complete callback */ + if (hdma->XferHalfCpltCallback != NULL) + { + /* If Half Transfer complete callback is set, enable the corresponding IT */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); + } + + /* Check Half suspend callback */ + if (hdma->XferSuspendCallback != NULL) + { + /* If Transfer suspend callback is set, enable the corresponding IT */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP); + } + + /* Enable DMA channel */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Abort any on-going DMA channel transfer (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @note After suspending a DMA channel, a wait until the DMA channel is effectively stopped is added. If a channel + * is suspended while a data transfer is on-going, the current data will be transferred and the channel will be + * effectively suspended only after the transfer of any on-going data is finished. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Suspend the channel */ + hdma->Instance->CCR |= DMA_CCR_SUSP; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_SUSPEND; + + /* Check if the DMA Channel is suspended */ + while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ERROR; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Reset the channel */ + hdma->Instance->CCR |= DMA_CCR_RESET; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Clear all status flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | + DMA_FLAG_TO)); + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + + /* Clear remaining data size to ensure loading linked-list from memory next start */ + hdma->Instance->CBR1 = 0U; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + return HAL_OK; +} + +/** + * @brief Abort any on-going DMA channel transfer in interrupt mode (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + return HAL_ERROR; + } + else + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Suspend the channel and activate suspend interrupt */ + hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE); + } + + return HAL_OK; +} + +/** + * @brief Polling for transfer status (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param CompleteLevel : Specifies the DMA level complete. + * @param Timeout : Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma, + HAL_DMA_LevelCompleteTypeDef CompleteLevel, + uint32_t Timeout) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + uint32_t level_flag; + uint32_t tmp_csr; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_LEVEL_COMPLETE(CompleteLevel)); + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + /* Polling mode is not supported in circular mode */ + if ((hdma->Mode & DMA_LINKEDLIST_CIRCULAR) == DMA_LINKEDLIST_CIRCULAR) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + level_flag = ((CompleteLevel == HAL_DMA_FULL_TRANSFER) ? DMA_FLAG_IDLE : DMA_FLAG_HT); + + /* Get DMA channel status */ + tmp_csr = hdma->Instance->CSR; + + while ((tmp_csr & level_flag) == 0U) + { + /* Check for the timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; + + /* + If timeout, abort the current transfer. + Note that the Abort function will + - Clear all transfer flags. + - Unlock. + - Set the State. + */ + (void)HAL_DMA_Abort(hdma); + + return HAL_ERROR; + } + } + + /* Get a newer CSR register value */ + tmp_csr = hdma->Instance->CSR; + } + + /* Check trigger overrun flag */ + if ((tmp_csr & DMA_FLAG_TO) != 0U) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TO; + + /* Clear the error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO); + } + + /* Check error flags */ + if ((tmp_csr & (DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE)) != 0U) + { + /* Check the data transfer error flag */ + if ((tmp_csr & DMA_FLAG_DTE) != 0U) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DTE; + + /* Clear the error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE); + } + + /* Check the update link error flag */ + if ((tmp_csr & DMA_FLAG_ULE) != 0U) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_ULE; + + /* Clear the error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE); + } + + /* Check the user setting error flag */ + if ((tmp_csr & DMA_FLAG_USE) != 0U) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_USE; + + /* Clear the error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE); + } + + /* Reset the channel */ + hdma->Instance->CCR |= DMA_CCR_RESET; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + /* Clear the transfer level flag */ + if (CompleteLevel == HAL_DMA_HALF_TRANSFER) + { + /* Clear the Half Transfer flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT); + } + else if (CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the transfer flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT)); + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Handle DMA interrupt request (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval None. + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) +{ + const DMA_TypeDef *p_dma_instance = GET_DMA_INSTANCE(hdma); + uint32_t global_it_flag = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + uint32_t global_active_flag_ns = IS_DMA_GLOBAL_ACTIVE_FLAG_NS(p_dma_instance, global_it_flag); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t global_active_flag_s = IS_DMA_GLOBAL_ACTIVE_FLAG_S(p_dma_instance, global_it_flag); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* Global Interrupt Flag management *********************************************************************************/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if ((global_active_flag_s == 0U) && (global_active_flag_ns == 0U)) +#else + if (global_active_flag_ns == 0U) +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + { + return; /* the global interrupt flag for the current channel is down , nothing to do */ + } + + /* Data Transfer Error Interrupt management *************************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_DTE) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DTE) != 0U) + { + /* Clear the transfer error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE); + + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DTE; + } + } + + /* Update Linked-list Error Interrupt management ********************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_ULE) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_ULE) != 0U) + { + /* Clear the update linked-list error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE); + + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_ULE; + } + } + + /* User Setting Error Interrupt management **************************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_USE) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_USE) != 0U) + { + /* Clear the user setting error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE); + + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_USE; + } + } + + /* Trigger Overrun Interrupt management *****************************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TO) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TO) != 0U) + { + /* Clear the trigger overrun flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO); + + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TO; + } + } + + /* Half Transfer Complete Interrupt management **********************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_HT) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) + { + /* Clear the half transfer flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT); + + /* Check half transfer complete callback */ + if (hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + + /* Suspend Transfer Interrupt management ****************************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_SUSP) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_SUSP) != 0U) + { + /* Clear the block transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_SUSP); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_ABORT) + { + /* Disable the suspend transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_SUSP); + + /* Reset the channel internal state and reset the FIFO */ + hdma->Instance->CCR |= DMA_CCR_RESET; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + + /* Clear remaining data size to ensure loading linked-list from memory next start */ + hdma->Instance->CBR1 = 0U; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Check transfer abort callback */ + if (hdma->XferAbortCallback != NULL) + { + /* Transfer abort callback */ + hdma->XferAbortCallback(hdma); + } + + return; + } + else + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_SUSPEND; + + /* Check transfer suspend callback */ + if (hdma->XferSuspendCallback != NULL) + { + /* Transfer suspend callback */ + hdma->XferSuspendCallback(hdma); + } + } + } + } + + /* Transfer Complete Interrupt management ***************************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TC) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) + { + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* If linked-list transfer */ + if (hdma->Instance->CLLR == 0U) + { + if (hdma->Instance->CBR1 == 0U) + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + } + } + else + { + /* If normal transfer */ + if (hdma->Instance->CBR1 == 0U) + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + } + } + + /* Clear TC and HT transfer flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT)); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Check transfer complete callback */ + if (hdma->XferCpltCallback != NULL) + { + /* Channel Transfer Complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } + + /* Manage error case ************************************************************************************************/ + if (hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + /* Reset the channel internal state and reset the FIFO */ + hdma->Instance->CCR |= DMA_CCR_RESET; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Check transfer error callback */ + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } +} + +/** + * @brief Register callback according to specified ID. + * @note The HAL_DMA_RegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET + * to register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enumeration. + * @param pCallback : Pointer to private callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, + HAL_DMA_CallbackIDTypeDef CallbackID, + void (*const pCallback)(DMA_HandleTypeDef *const _hdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Check callback ID */ + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + { + /* Register transfer complete callback */ + hdma->XferCpltCallback = pCallback; + break; + } + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + { + /* Register half transfer callback */ + hdma->XferHalfCpltCallback = pCallback; + break; + } + + case HAL_DMA_XFER_ERROR_CB_ID: + { + /* Register transfer error callback */ + hdma->XferErrorCallback = pCallback; + break; + } + + case HAL_DMA_XFER_ABORT_CB_ID: + { + /* Register abort callback */ + hdma->XferAbortCallback = pCallback; + break; + } + + case HAL_DMA_XFER_SUSPEND_CB_ID: + { + /* Register suspend callback */ + hdma->XferSuspendCallback = pCallback; + break; + } + + default: + { + /* Update error status */ + status = HAL_ERROR; + break; + } + } + } + else + { + /* Update error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister callback according to specified ID. + * @note The HAL_DMA_UnRegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET + * to un-register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enum. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, + HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Check callback ID */ + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + { + /* UnRegister transfer complete callback */ + hdma->XferCpltCallback = NULL; + break; + } + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + { + /* UnRegister half transfer callback */ + hdma->XferHalfCpltCallback = NULL; + break; + } + + case HAL_DMA_XFER_ERROR_CB_ID: + { + /* UnRegister transfer error callback */ + hdma->XferErrorCallback = NULL; + break; + } + + case HAL_DMA_XFER_ABORT_CB_ID: + { + /* UnRegister abort callback */ + hdma->XferAbortCallback = NULL; + break; + } + + case HAL_DMA_XFER_SUSPEND_CB_ID: + { + /* UnRegister suspend callback */ + hdma->XferSuspendCallback = NULL; + break; + } + + case HAL_DMA_XFER_ALL_CB_ID: + { + /* UnRegister all available callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + break; + } + + default: + { + /* Update error status */ + status = HAL_ERROR; + break; + } + } + } + else + { + /* Update error status */ + status = HAL_ERROR; + } + + return status; +} +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * +@verbatim + ====================================================================================================================== + ##### State and Errors functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Check the DMA state + (+) Get error code + + [..] + (+) The HAL_DMA_GetState() function allows to get the DMA channel state. + (+) The HAL_DMA_DeInit() function allows to get the DMA channel error code. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA channel state. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval DMA state. + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma) +{ + /* Return the DMA channel state */ + return hdma->State; +} + +/** + * @brief Return the DMA channel error code. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval DMA Error Code. + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma) +{ + /* Return the DMA channel error code */ + return hdma->ErrorCode; +} +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group4 + * +@verbatim + ====================================================================================================================== + ##### DMA Attributes functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Configure DMA channel secure and privilege attributes. + (+) Get DMA channel secure and privilege attributes. + (+) Lock DMA channel secure and privilege attributes configuration. + (+) Check whether DMA channel secure and privilege attributes configuration is locked or not. + + [..] + (+) The HAL_DMA_ConfigChannelAttributes() function allows to configure DMA channel security and privilege + attributes. + (+) The HAL_DMA_GetConfigChannelAttributes() function allows to get DMA channel security and privilege attributes + configuration. + (+) The HAL_DMA_LockChannelAttributes() function allows to lock the DMA channel security and privilege attributes. + (+) The HAL_DMA_GetLockChannelAttributes() function allows to get the DMA channel security and privilege + attributes lock status. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the DMA channel security and privilege attribute(s). + * @note These attributes cannot be modified when the corresponding lock state is enabled. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for + * the specified DMA Channel. + * @param ChannelAttributes : Specifies the DMA channel secure/privilege attributes. + * This parameter can be a one or a combination of @ref DMA_Channel_Attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, uint32_t ChannelAttributes) +{ + DMA_TypeDef *p_dma_instance; + uint32_t channel_idx; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ATTRIBUTES(ChannelAttributes)); + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Get channel index */ + channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Check DMA channel privilege attribute management */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_PRIV_MASK) == DMA_CHANNEL_ATTR_PRIV_MASK) + { + /* Configure DMA channel privilege attribute */ + if ((ChannelAttributes & DMA_CHANNEL_PRIV) == DMA_CHANNEL_PRIV) + { + p_dma_instance->PRIVCFGR |= channel_idx; + } + else + { + p_dma_instance->PRIVCFGR &= (~channel_idx); + } + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Check DMA channel security attribute management */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_MASK) == DMA_CHANNEL_ATTR_SEC_MASK) + { + /* Configure DMA channel security attribute */ + if ((ChannelAttributes & DMA_CHANNEL_SEC) == DMA_CHANNEL_SEC) + { + p_dma_instance->SECCFGR |= channel_idx; + } + else + { + p_dma_instance->SECCFGR &= (~channel_idx); + } + } + + /* Channel source security attribute management */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_SRC_MASK) == DMA_CHANNEL_ATTR_SEC_SRC_MASK) + { + /* Configure DMA channel source security attribute */ + if ((ChannelAttributes & DMA_CHANNEL_SRC_SEC) == DMA_CHANNEL_SRC_SEC) + { + hdma->Instance->CTR1 |= DMA_CTR1_SSEC; + } + else + { + hdma->Instance->CTR1 &= (~DMA_CTR1_SSEC); + } + } + + /* Channel destination security attribute management */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_DEST_MASK) == DMA_CHANNEL_ATTR_SEC_DEST_MASK) + { + /* Configure DMA channel destination security attribute */ + if ((ChannelAttributes & DMA_CHANNEL_DEST_SEC) == DMA_CHANNEL_DEST_SEC) + { + hdma->Instance->CTR1 |= DMA_CTR1_DSEC; + } + else + { + hdma->Instance->CTR1 &= (~DMA_CTR1_DSEC); + } + } +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + return HAL_OK; +} + +/** + * @brief Get the DMA channel security and privilege attributes. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * for the specified DMA Channel. + * @param pChannelAttributes : Pointer to the returned attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma, + uint32_t *const pChannelAttributes) +{ + const DMA_TypeDef *p_dma_instance; + uint32_t attributes; + uint32_t channel_idx; + + /* Check the DMA peripheral handle and channel attributes parameters */ + if ((hdma == NULL) || (pChannelAttributes == NULL)) + { + return HAL_ERROR; + } + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Get channel index */ + channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Get DMA channel privilege attribute */ + attributes = ((p_dma_instance->PRIVCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NPRIV : DMA_CHANNEL_PRIV; + + /* Get DMA channel security attribute */ + attributes |= ((p_dma_instance->SECCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NSEC : DMA_CHANNEL_SEC; + + /* Get DMA channel source security attribute */ + attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_SSEC) == 0U) ? DMA_CHANNEL_SRC_NSEC : DMA_CHANNEL_SRC_SEC; + + /* Get DMA channel destination security attribute */ + attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_DSEC) == 0U) ? DMA_CHANNEL_DEST_NSEC : DMA_CHANNEL_DEST_SEC; + + /* return value */ + *pChannelAttributes = attributes; + + return HAL_OK; +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the DMA channel security and privilege attribute(s). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma) +{ + DMA_TypeDef *p_dma_instance; + uint32_t channel_idx; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Get channel index */ + channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Lock the DMA channel privilege and security attributes */ + p_dma_instance->RCFGLOCKR |= channel_idx; + + return HAL_OK; +} +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Get the security and privilege attribute lock state of a DMA channel. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param pLockState : Pointer to lock state (returned value can be DMA_CHANNEL_ATTRIBUTE_UNLOCKED or + * DMA_CHANNEL_ATTRIBUTE_LOCKED). + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, uint32_t *const pLockState) +{ + const DMA_TypeDef *p_dma_instance; + uint32_t channel_idx; + + /* Check the DMA peripheral handle and lock state parameters */ + if ((hdma == NULL) || (pLockState == NULL)) + { + return HAL_ERROR; + } + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Get channel index */ + channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Get channel lock attribute state */ + *pLockState = ((p_dma_instance->RCFGLOCKR & channel_idx) == 0U) ? DMA_CHANNEL_ATTRIBUTE_UNLOCKED : \ + DMA_CHANNEL_ATTRIBUTE_LOCKED; + + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ + + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @brief DMA Private Functions + * @{ + */ + +/** + * @brief Set the DMA channel normal transfer parameters. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param SrcAddress : The source data address. + * @param DstAddress : The destination data address. + * @param SrcDataSize : The length of data to be transferred from source to destination in bytes. + * @retval None. + */ +static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize) +{ + /* Configure the DMA channel data size */ + MODIFY_REG(hdma->Instance->CBR1, DMA_CBR1_BNDT, (SrcDataSize & DMA_CBR1_BNDT)); + + /* Clear all interrupt flags */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | + DMA_FLAG_TO); + + /* Configure DMA channel source address */ + hdma->Instance->CSAR = SrcAddress; + + /* Configure DMA channel destination address */ + hdma->Instance->CDAR = DstAddress; +} + +/** + * @brief Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval None. + */ +static void DMA_Init(DMA_HandleTypeDef const *const hdma) +{ + uint32_t tmpreg; + + /* Prepare DMA Channel Control Register (CCR) value *****************************************************************/ + tmpreg = hdma->Init.Priority; + + /* Write DMA Channel Control Register (CCR) */ + MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg); + + /* Prepare DMA Channel Transfer Register (CTR1) value ***************************************************************/ + tmpreg = hdma->Init.DestInc | hdma->Init.DestDataWidth | hdma->Init.SrcInc | hdma->Init.SrcDataWidth; + + /* Add parameters specific to GPDMA */ + if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) + { + tmpreg |= (hdma->Init.TransferAllocatedPort | + (((hdma->Init.DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1) | + (((hdma->Init.SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1)); + } + + /* Write DMA Channel Transfer Register 1 (CTR1) */ + MODIFY_REG(hdma->Instance->CTR1, ~(DMA_CTR1_SSEC | DMA_CTR1_DSEC), tmpreg); + + /* Prepare DMA Channel Transfer Register 2 (CTR2) value *************************************************************/ + tmpreg = hdma->Init.BlkHWRequest | (hdma->Init.Request & DMA_CTR2_REQSEL) | hdma->Init.TransferEventMode; + + /* Memory to Peripheral Transfer */ + if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) + { + tmpreg |= DMA_CTR2_DREQ; + } + } + /* Memory to Memory Transfer */ + else if ((hdma->Init.Direction) == DMA_MEMORY_TO_MEMORY) + { + tmpreg |= DMA_CTR2_SWREQ; + } + else + { + /* Nothing to do */ + } + + /* Write DMA Channel Transfer Register 2 (CTR2) */ + MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM | + DMA_CTR2_BREQ | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_REQSEL), tmpreg); + + + /* Write DMA Channel Block Register 1 (CBR1) ************************************************************************/ + WRITE_REG(hdma->Instance->CBR1, 0U); + + /* If 2D Addressing is supported by current channel */ + if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) + { + /* Write DMA Channel Transfer Register 3 (CTR3) *******************************************************************/ + WRITE_REG(hdma->Instance->CTR3, 0U); + + /* Write DMA Channel Block Register 2 (CBR2) **********************************************************************/ + WRITE_REG(hdma->Instance->CBR2, 0U); + } + + /* Write DMA Channel linked-list address register (CLLR) ************************************************************/ + WRITE_REG(hdma->Instance->CLLR, 0U); +} +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c new file mode 100644 index 000000000..12bfe615a --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c @@ -0,0 +1,4718 @@ +/** + ********************************************************************************************************************** + * @file stm32u5xx_hal_dma_ex.c + * @author MCD Application Team + * @brief DMA Extension HAL module driver + * This file provides firmware functions to manage the following functionalities of the DMA extension + * peripheral: + * + Linked-List Initialization and De-Initialization Functions + * + Linked-List I/O Operation Functions + * + Linked-List Management Functions + * + Data Handling, Repeated Block and Trigger Configuration Functions + * + Suspend and Resume Operation Functions + * + FIFO Status Function + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + @verbatim + ====================================================================================================================== + ##### How to use this driver ##### + ====================================================================================================================== + [..] + Alternatively to the normal programming mode, a DMA channel can be programmed by a list of transfers, known as + linked-list (list of Node items). Each node is defined by its data structure. + Each node specifies a standalone DMA channel. + When enabled, the DMA channel fetch the first linked-list node from SRAM (known as head node). When executed, the + next linked list node will be fetched and executed. This operation is repeated until the end of the whole + linked-list queue. Optionally, the linked-list can be linear where the last linked-list queue node is not linked + to another queue node or circular where the last linked-list node is linked to any linked-list queue node. + + (+) Linear linked-list: + The DMA channel fetch and execute all DMA linked-list queue from first node (head node) to last node + (tail node) ones. When the last node is completed, the DMA channel remains in idle state and another + transfer can be lunched. + + (+) Circular linked-list: + The DMA channel fetch and execute all DMA linked-list queue from first node (head node) to last node (tail + node). When last node is executed, the DMA channel fetches the first circular node another time and repeat + the same sequence in an infinite loop (Circular transfer). To stop the DMA channel, an abort operation is + required. This linked-list mode replaces the legacy circular transfers. + + [..] + In order to reduce linked-list queue executing time and power consumption, the DMA channel supports executing the + dynamic linked-list format. In fact, the DMA supports the execution of 2 types of linked-list formats : static and + dynamic. + + (+) Static linked-list: + The static linked-list format refers to the full linked-list node where all DMA channel parameters are + fetched and executed independently of the redundancy of information. + + (+) Dynamic linked-list: + The dynamic linked-list format refer to the customized linked-list node where only DMA channel necessary + parameters are fetched and executed (Example: data size = 20 on previous node, and data size = 20 on the + current node => No need to update it). + + For linked-list transfers, the DMA channel can execute the linked-list queue node by node. This feature is named + link step mode. When activated, enabling the DMA channel first time allows to fetch the head node from memory + then it stops. Then, another DMA channel enable is needed to execute the node. After that, keeping enabling the + DMA channel is needed to execute each node until the end of linked-list queue. When the linked-list queue is + circular, enabling the DMA channel in an infinite loop is required to keep the DMA channel running. This feature + is useful for debug purpose or asynchronously executing queue nodes. + + [..] + Each DMA channel transfer (normal or linked-list), is highly configurable according to DMA channel instance + integrated in devices. These configuration can be : + + (+) Repeated block configuration : + If the feature is supported, the DMA channel can performs a repeated block transfers. Named also 2 + dimension addressing transfers, this feature can transfer n iteration of programmed block transfer (Block + transfer is the legacy data size). Additional to the repeat count of a block, DMA channel addresses can + jump after at burst and block level. The jump length is a programmable parameter defined by DMA user. + (++) Jump at burst level : + The DMA channel keep an empty area, between each 2 consecutive bursts transmitted. + (++) Jump at block level : + The DMA channel keep an empty area, between each 2 consecutive blocks transmitted. + + (+) Trigger : + The DMA channel transfers can be conditioned by hardware signals edges (rising or falling) named hardware + triggers. Trigger condition can be applied at : + (++) Single/Burst level : + Each single/burst data transmission is conditioned by a signal trigger hit. + (++) Block level : + Each block data transmission is conditioned by a signal trigger hit. + (++) Repeated block level : + Each repeated block data transmission is conditioned by a signal trigger hit. + (++) Node level : + Each node execution is conditioned by a signal trigger hit. + The DMA channel can report a trigger overrun when detects more than 2 trigger signal edges before + executing the current transfer. + + (+) Data handling : + The data handling feature is a FIFO capability that can be : + (++) Padding pattern : + Padding selected pattern (zero padding or sign extension) when the source data width is smaller + than the destination data width at single level. + (++) Truncation : + Truncate section from the source data single when the source data width is bigger than the + destination data width. + (++) Pack/Unpack : + Pack a set of data when source data width is smaller than the destination data width. + Unpack a set of data when source data width is bigger than the destination data width. + (++) Exchange : + Exchange data at byte and half-word on the destination and at byte level on the source. + + [..] + Each DMA channel transfer (normal or linked-list) when it is active, can be suspended and resumed at run time + application. When trying to suspend an ongoing transfer, the DMA channel isn't suspended instantly but complete + the current ongoing single/burst then it stops. + When the DMA channel is suspended, the current transfer can be resumed instantly. + + [..] + The DMA channel that supports FIFO, can report in real time the number of beats remains on destination (Output) + FIFO level. + + *** Linked-List Initialization and De-Initialization operation *** + ================================================================== + [..] + Differently from normal transfers, DMA channel initialization and de-initialization need less parameters as the + remaining transfer parameters are defined by linked-list nodes. + + (+) Use HAL_DMAEx_List_Init() to initialize a DMA channel in linked-list mode according to programmed fields. + When called, the DMA channel will be ready to execute linked-list queues. + + (+) Use HAL_DMAEx_List_DeInit() to de-initialize a DMA channel in linked-list mode. + When called, the DMA channel will be in reset. It is mandatory to reinitialize it for next transfer. + + *** Linked-List I/O Operation *** + ================================= + [..] + (+) Use HAL_DMAEx_List_Start() to start a DMA transfer in linked-list mode after the configuration of + linked-list queue base address and offset in polling mode (Blocking mode). + + (+) Use HAL_DMAEx_List_Start_IT() to start a DMA transfer in linked-list mode after the configuration of + linked-list queue base address and offset in interrupt mode (Non-blocking mode). + + *** Linked-List Management *** + ============================== + [..] + The linked-list management is a software processing independently of DMA channel hardware. It allows to reset, + build, create, insert, remove, replace, circularize, convert both nodes and queue in order to perform DMA + channel transfers in linked-list mode. + Linked-list APIs and types are adapted to reduce memory footprint. + + *** Linked-list nodes building *** + [..] + At node level, the operations that can be done are building a new linked-list node or get a linked-list node + information from a built node. The linked-list nodes have two forms according to 2 dimensions addressing + capability. The linear addressing nodes contains the information of all DMA channel features except the 2 + dimension addressing features and the 2 dimensions addressing nodes contain the information of all available + features. + + (+) Use HAL_DMAEx_List_BuildNode() to build the DMA linked-list node according to the specified parameters. + Build operation allow to convert the specified parameter in values known by the DMA channel and place them + in memory. + Placing DMA linked-list in SRAM must be done in accordance to product specification to ensure that the + link access port can access to the specified SRAM. + (++) The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte + addressable space. + + (+) Use HAL_DMAEx_List_GetNodeConfig() to get the specified configuration parameter on building node. + This API can be used when need to change few parameter to build new node. + + *** Inserting nodes to linked-list queue *** + [..] + In order to build a sequence of DMA transaction with different configuration, we need to insert built node at + linked-list queue (node present an elementary DMA transaction) in linked-list queue on any position to have the + full flexibility of ordering nodes or extend the sequence of queue transactions. + + (+) Use HAL_DMAEx_List_InsertNode() to insert new built node in any queue position of linked-list queue + according to selecting previous node. When calling this API with previous node parameter is NULL, the + inserted node will be placed at the head of the linked-list queue. + (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned. + (++) This API must be called for static queues format. + (++) This API shall be avoided when adding new node at the head or the tail of queue (overhead of + footprint and performance : use HAL_DMAEx_List_InsertNode_Head() or HAL_DMAEx_List_InsertNode_Tail() + instead). + + (+) Use HAL_DMAEx_List_InsertNode_Head() to insert new built node at the head of linked-list queue. The head + node will not be overwritten but will be the second queue node. + (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_InsertNode_Tail() to insert new built node at the tail of linked-list queue. The tail + node will not be overwritten but will be the penultimate queue node. + (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned. + (++) This API must be called for static queues format. + + *** Removing nodes from linked-list queue *** + [..] + There is some cases when removing a node from linked-list queue is needed (need to remove an elementary DMA + transaction). Removing node allows to unlink a node from DMA linked-list queue (NOT DELETED), so the removed node + can be reused for another queue or to be added to the same queue without need to rebuild it in next step. + + (+) Use HAL_DMAEx_List_RemoveNode() to remove any yet built and inserted node from linked-list queue according + to selected node. + (++) This API must be called for static queues format. + (++) This API shall be avoided when removing the head or the tail of linked-list queue (overhead of + footprint and performance : use HAL_DMAEx_List_RemoveNode_Head() or HAL_DMAEx_List_RemoveNode_Tail() + instead). + + (+) Use HAL_DMAEx_List_RemoveNode_Head() to remove the head node from linked-list queue. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_RemoveNode_Tail() to remove the tail node from linked-list queue. + (++) This API must be called for static queues format. + + *** Replacing nodes on linked-list queue *** + [..] + There is some cases when replacing a node from linked-list queue is needed (need to replace an elementary DMA + transfer, by another one that have not the same configuration). Replacing node allows to unlink the node to be + replaced from DMA linked-list queue (NOT DELETED) and link instead a new node. So the replaced node can be reused + for another queue or to be added to the same queue without need to rebuild it in next step and the new node cannot + be reused except when remove it or replaced in next step. + + (+) Use HAL_DMAEx_List_ReplaceNode() to replace any yet built and inserted node on linked-list queue according + to selected node. + (++) This API must be called for static queues format. + (++) This API shall be avoided when replacing the head or the tail linked-list queue (overhead of + footprint and performance : use HAL_DMAEx_List_ReplaceNode_Head() or + HAL_DMAEx_List_ReplaceNode_Tail() instead). + + (+) Use HAL_DMAEx_List_ReplaceNode_Head() to replace the head node of linked-list queue. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_ReplaceNode_Tail() to replace the tail node from linked-list queue. + (++) This API must be called for static queues format. + + *** Reset linked-list queue *** + [..] + After finishing using a linked-list queue, it can be reset and cleared and it's content nodes will be + unlinked (NOT DELETED) and reused on another queue. + + (+) Use HAL_DMAEx_List_ResetQ() to reset a linked-list queue and unlink all it's content nodes. + (++) This API must be called for ready state queues. + (++) This API must be called for static queues format. + + *** Inserting linked-list queue *** + [..] + To ensure the flexibility of building linked-list queue by their targeted functionalities (Example: 3 nodes for + action 1 and 5 nodes for action 2), it is possible to build a queue for action 1 that contains action 1 nodes and + a queue for action 2 that contains action 2 nodes then concatenating the 2 queues. So, there are some cases where + the management of linked-list at queue granularity is needed. + + (+) Use HAL_DMAEx_List_InsertQ() to insert source linked-list queue to a destination linked-list queue + according to selecting previous node. + (++) This API must be called for static queues format. + (++) This API shall be avoided when inserting source linked-list queue at the head or the tail of + destination queue (overhead of footprint and performance : use HAL_DMAEx_List_InsertQ_Head() or + HAL_DMAEx_List_InsertQ_Tail() instead). + + (+) Use HAL_DMAEx_List_InsertQ_Head() to insert a source linked-list queue at the head of linked-list + destination queue. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_InsertQ_Tail() to insert a source linked-list queue at the tail of linked-list + destination queue. + (++) This API must be called for static queues format. + + *** Circularizing linked-list queue *** + [..] + In order to perform tasks in infinite loop with DMA channel, it is possible to circularize the linked-list queues. + Circularizing queue allows to link last linked-list queue node to any previous node of the same queue (This node + is named first circular queue). When the first circular node is the head node, all linked-list queue nodes will be + executed in infinite loop. When the first circular node is not the head nodes, all precedent nodes are executed + once and all remaining nodes are executed in an infinite loop. + + (+) Use HAL_DMAEx_List_SetCircularModeConfig() to circularize the linked-list queue according to first + circular node selected. + (++) This API must be called for static queues format. + (++) This API shall be avoided when first circular node is the head linked-list queue node (overhead of + footprint and performance : use HAL_DMAEx_List_SetCircularMode() instead). + + (+) Use HAL_DMAEx_List_SetCircularMode() to circularize the linked-list queue with linking last queue node + with first queue node. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_ClearCircularMode() to clear any linked-list queue circular configuration. + (++) This API must be called for static queues format. + + + *** Converting linked-list queue *** + [..] + To have the best DMA channel linked-list queue execution, it is recommended to convert yet build linked-list queue + to dynamic format (Static is the default format). When linked-list queue becomes dynamic, all queue nodes are + optimized and only changed parameters will be updated between nodes. So, the DMA will fetch only changes + parameters instead of the whole node. + + (+) Use HAL_DMAEx_List_ConvertQToDynamic() to convert a linked-list queue to dynamic format. + (++) This API must be called for ready state queues. + (++) This API must be called for static queues format. + (++) This API must be called as the last API before starting the DMA channel in linked-list mode. + + (+) Use HAL_DMAEx_List_ConvertQToStatic() to convert a linked-list queue to static format. + (++) This API must be called for ready state queues. + (++) This API must be called for dynamic queues format. + (++) This API must be called as the first API after the full execution of linked-list queue when the + execution mode is linear (not circular) if it is dynamic and a linked-list queue management is + needed. + (++) This API must be called as the first API after the aborting the execution of the current linked-list + queue when the execution mode is linear (not circular) if it is dynamic and a linked-list queue + management is needed. + + [..] + When converting a circular queue to dynamic format and when the first circular node is the last queue node, it is + recommended to duplicate the last circular node in order to ensure the full optimization when calling + HAL_DMAEx_List_ConvertQToDynamic() API. In this case, updated information are only addresses which allow to reduce + 4 words of update for linear nodes per node execution and 6 words update for 2 dimensions addressing nodes per + node execution. + + + *** Linking linked-list queue to DMA channel *** + [..] + In order to have the possibility of the creation of an infinity queues (limited by available memory size), the + building of linked-list queue is fully independent from DMA channels. It is possible to build all needed queues if + their size is less then available memory at startup time, then linking each time when needed a linked-list queue + to an idle DMA channel. + + (+) Use HAL_DMAEx_List_LinkQ() to link a ready linked-list queue to ready DMA channel. + (++) This API supports the two format of linked-list (Static and dynamic). + (++) This API must be called for ready state queues and DMA channels. + + (+) Use HAL_DMAEx_List_ConvertQToStatic() to unlink a ready linked-list queue to ready DMA channel. + (++) This API supports the two format of linked-list (Static and dynamic). + (++) This API must be called for ready state queues and DMA channels. + + *** User sequence *** + [..] + To use cleanly the DMA linked-list library, ensure to apply the following call sequences : + + (+) Linear transfer : + Linked-list queue building + (++) HAL_DMAEx_List_BuildNode() + (++) HAL_DMAEx_List_InsertNode_Tail() + . + . + . + (++) HAL_DMAEx_List_BuildNode() + (++) HAL_DMAEx_List_InsertNode_Tail() + (++) HAL_DMAEx_List_ConvertQToDynamic() + Linked-list queue execution + (++) HAL_DMAEx_List_Init() + (++) HAL_DMAEx_List_LinkQ() + (++) HAL_DMAEx_List_Start() / HAL_DMAEx_List_Start_IT() + (++) HAL_DMAEx_List_UnLinkQ() + (++) HAL_DMAEx_List_DeInit() + + (+) Circular transfer : + Linked-list queue building + (++) HAL_DMAEx_List_BuildNode() + (++) HAL_DMAEx_List_InsertNode_Tail() + . + . + . + (++) HAL_DMAEx_List_BuildNode() + (++) HAL_DMAEx_List_InsertNode_Tail() + (++) HAL_DMAEx_List_SetCircularModeConfig() / HAL_DMAEx_List_SetCircularMode() + (++) HAL_DMAEx_List_ConvertQToDynamic() + Linked-list queue execution + (++) HAL_DMAEx_List_Init() + (++) HAL_DMAEx_List_LinkQ() + (++) HAL_DMAEx_List_Start() / HAL_DMAEx_List_Start_IT() + (++) HAL_DMA_Abort() / HAL_DMA_Abort_IT() + (++) HAL_DMAEx_List_UnLinkQ() + (++) HAL_DMAEx_List_DeInit() + + + *** Data Handling *** + ===================== + [..] + In order to avoid some CPU data processing in several cases, the DMA channel provides some features related to + FIFO capabilities titled data handling. + (++) Padding pattern + Padding selected pattern (zero padding or sign extension) when the source data width is smaller + than the destination data width at single level. + Zero padding (Source : 0xABAB ------> Destination : 0xABAB0000) + Sign bit extension (Source : 0x0ABA ------> Destination : 0x00000ABA) + (Source : 0xFABA ------> Destination : 0xFFFFFABA) + (++) Truncation : + Truncate section from the source data single when the source data width is bigger than the + destination data width. + Left truncation (Source : 0xABABCDCD ------> Destination : 0xCDCD) + Right truncation (Source : 0xABABCDCD ------> Destination : 0xABAB) + (++) Pack/Unpack : + Pack a set of data when source data width is smaller than the destination data width. + Unpack a set of data when source data width is bigger than the destination data width. + Pack (Source : 0xAB, 0xCD ------> Destination : 0xABCD) + UnPack (Source : 0xABCD ------> Destination : 0xAB, 0xCD) + (++) Exchange : + Exchange data at byte and half-word on the destination and at byte level on the source. + Considering source and destination are both word type. Exchange operation can be as follows. + In examples below, one exchange setting is enabled at a time. + Source byte exchange only (Source : 0xAB12CD34 ------> Destination : 0xABCD1234) + Destination byte exchange only (Source : 0xAB12CD34 ------> Destination : 0x12AB34CD) + Destination half-word exchange only (Source : 0xAB12CD34 ------> Destination : 0xCD34AB12) + + (+) Use HAL_DMAEx_ConfigDataHandling() to configure data handling features. Previous elementary explained + can be combined according to application needs. + (++) This API is complementary of normal transfers. + (++) This API must not be called for linked-list transfers as data handling information are configured at + node level. + + *** User sequence *** + [..] + To configure cleanly the DMA channel data handling, ensure to apply the following call sequence : + + (+) Linear transfer : + (++) HAL_DMA_Init() + (++) HAL_DMAEx_ConfigDataHandling() + (++) HAL_DMA_Start() + + *** Repeated Block *** + ====================== + [..] + When available, this feature is used when the data size is higher then 65535 bytes (Maximum block size) or for + scattering / gathering data. + (++) Gather data + Source Destination + 0xAA 0xAA + 0xBB 0xAA + 0xAA ==> 0xAA + 0xCC + 0xAA + (++) Scatter data + Source Destination + 0xAA 0xAA + 0xAA 0xBB + 0xAA ==> 0xAA + 0xBB + 0xAA + + (+) Use HAL_DMAEx_ConfigRepeatBlock() to configure data repeated block feature. Jump addresses and + incrementing or decrementing on source and destination can be combined to have the need application + behavior. + (++) This API is complementary of normal transfers. + (++) This API must not be called for linked-list transfers as repeated block information are configured at + node level. + (++) This API must be called only for DMA channel that supports repeated block feature. + + *** User sequence *** + [..] + To configure cleanly the DMA channel repeated block, ensure to apply the following call sequence : + + (+) Linear transfer : + (++) HAL_DMA_Init() + (++) HAL_DMAEx_ConfigRepeatBlock() + (++) HAL_DMA_Start() + + *** Trigger Configuration *** + ============================= + [..] + When application needs that DMA transfers are conditioned by internal or external events, the trigger feature can + do that. Trigger signals are a set of device signal that are linked to DMA trigger inputs that allows to start the + DMA transfers. + To setup a trigger transfers, three DMA channel parameters are needed: + + (+) Trigger mode + This parameter specifies the trig level. + (++) Block level + (++) Repeated block level + (++) Node level + (++) Single / Burst level + + (+) Trigger polarity + This parameter specifies the DMA trigger sensitivity (Rising or falling). + + (+) Trigger selection + This parameter specifies the DMA trigger hardware signal. + + (+) Use HAL_DMAEx_ConfigTrigger() to configure trigger feature. + (++) This API is complementary to normal transfers APIs. + (++) This API must not be called for linked-list transfers as trigger information are configured at + node level. + + *** User sequence *** + [..] + To configure cleanly the DMA channel trigger, ensure to apply the following call sequence : + (+) Linear transfer : + (++) HAL_DMA_Init() + (++) HAL_DMAEx_ConfigTrigger() + (++) HAL_DMA_Start() + + *** Suspend and resume operation *** + ==================================== + [..] + There are several cases when needs to suspend a DMA current transfer (Example: liberate bandwidth for more + priority DMA channel transfer). Suspending DMA channel (same as abort) is available in polling (blocking mode) and + interrupt (non-blocking mode) modes. When suspended, a DMA channel can be instantly resumed. + + (+) Use HAL_DMAEx_Suspend() to suspend an ongoing DMA channel transfer in polling mode (Blocking mode). + + (+) Use HAL_DMAEx_Suspend_IT() to suspend an ongoing DMA channel transfer in interrupt mode (Non-blocking + mode). + + (+) Use HAL_DMAEx_Resume() to resume a suspended DMA channel transfer execution. + + *** FIFO status *** + =================== + [..] + In several cases, the information of FIFO level is useful to inform at application level how to process remaining + data. When not empty, the DMA channel FIFO cannot be flashed only by reset. + + (+) Use HAL_DMAEx_GetFifoLevel() to get the DMA channel FIFO level (available beats in FIFO). + + @endverbatim + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA Extended HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private Constants -------------------------------------------------------------------------------------------------*/ +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +static void DMA_List_Init(DMA_HandleTypeDef const *const hdma); +static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, + DMA_NodeTypeDef *const pNode); +static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, + DMA_NodeTypeDef const *const pNode); +#if defined ( __GNUC__ ) && !defined (__CC_ARM) +static __attribute__((noinline)) uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, \ + DMA_NodeTypeDef const *const pNode2, \ + DMA_NodeTypeDef const *const pNode3); +#else +static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, + DMA_NodeTypeDef const *const pNode2, + DMA_NodeTypeDef const *const pNode3); +#endif /* __GNUC__ && !__CC_ARM */ +static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, + DMA_NodeTypeDef const *const pNode2, + DMA_NodeTypeDef const *const pNode3); +static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode, + uint32_t *const cllr_mask, + uint32_t *const cllr_offset); +static uint32_t DMA_List_FindNode(DMA_QListTypeDef const *const pQList, + DMA_NodeTypeDef const *const pNode, + DMA_NodeInQInfoTypeDef *const NodeInfo); +static void DMA_List_ResetQueueNodes(DMA_QListTypeDef const *const pQList, + DMA_NodeInQInfoTypeDef const *const NodeInfo); +static void DMA_List_FillNode(DMA_NodeTypeDef const *const pSrcNode, + DMA_NodeTypeDef *const pDestNode); +static void DMA_List_ConvertNodeToDynamic(uint32_t ContextNodeAddr, + uint32_t CurrentNodeAddr, + uint32_t RegisterNumber); +static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr, + uint32_t CurrentNodeAddr, + uint32_t RegisterNumber); +static void DMA_List_UpdateDynamicQueueNodesCLLR(DMA_QListTypeDef const *const pQList, + uint32_t LastNode_IsCircular); +static void DMA_List_UpdateStaticQueueNodesCLLR(DMA_QListTypeDef const *const pQList, + uint32_t operation); +static void DMA_List_FormatNode(DMA_NodeTypeDef *const pNode, + uint32_t RegisterIdx, + uint32_t RegisterNumber, + uint32_t Format); +static void DMA_List_ClearUnusedFields(DMA_NodeTypeDef *const pNode, + uint32_t FirstUnusedField); +static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList); + +/* Exported functions ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + +/** @addtogroup DMAEx_Exported_Functions_Group1 + * +@verbatim + ====================================================================================================================== + ##### Linked-List Initialization and De-Initialization Functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the DMA channel in linked-list mode. + [..] + (+) The HAL_DMAEx_List_Init() function follows the DMA channel linked-list mode configuration procedures as + described in reference manual. + (+) The HAL_DMAEx_List_DeInit() function allows to de-initialize the DMA channel in linked-list mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA channel in linked-list mode according to the specified parameters in the + * DMA_InitLinkedListTypeDef and create the associated handle. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA channel handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_PRIORITY(hdma->InitLinkedList.Priority)); + assert_param(IS_DMA_LINK_STEP_MODE(hdma->InitLinkedList.LinkStepMode)); + assert_param(IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(hdma->InitLinkedList.TransferEventMode)); + assert_param(IS_DMA_LINKEDLIST_MODE(hdma->InitLinkedList.LinkedListMode)); + /* Check DMA channel instance */ + if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) + { + assert_param(IS_DMA_LINK_ALLOCATED_PORT(hdma->InitLinkedList.LinkAllocatedPort)); + } + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA channel is effectively disabled */ + while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Initialize the DMA channel registers */ + DMA_List_Init(hdma); + + /* Update DMA channel operation mode */ + hdma->Mode = hdma->InitLinkedList.LinkedListMode; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA channel when it is configured in linked-list mode. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) +{ + + /* Get DMA instance */ + DMA_TypeDef *p_dma_instance; + + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Disable the selected DMA Channel */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA channel is effectively disabled */ + while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Reset DMA Channel registers */ + hdma->Instance->CCR = 0U; + hdma->Instance->CLBAR = 0U; + hdma->Instance->CTR1 = 0U; + hdma->Instance->CTR2 = 0U; + hdma->Instance->CBR1 = 0U; + hdma->Instance->CSAR = 0U; + hdma->Instance->CDAR = 0U; + hdma->Instance->CLLR = 0U; + + /* Reset 2D Addressing registers */ + if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) + { + hdma->Instance->CTR3 = 0U; + hdma->Instance->CBR2 = 0U; + } + + + /* Clear privilege attribute */ + CLEAR_BIT(p_dma_instance->PRIVCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Clear secure attribute */ + CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | + DMA_FLAG_TO)); + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + + /* Check the linked-list queue */ + if (hdma->LinkedListQueue != NULL) + { + /* Update the queue state and error code */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Clean DMA queue */ + hdma->LinkedListQueue = NULL; + } + + /* Clean DMA parent */ + if (hdma->Parent != NULL) + { + hdma->Parent = NULL; + } + + /* Update DMA channel operation mode */ + hdma->Mode = DMA_NORMAL; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group2 + * +@verbatim + ====================================================================================================================== + ##### Linked-List IO Operation Functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Configure to start DMA transfer in linked-list mode. + + [..] + (+) The HAL_DMAEx_List_Start() function allows to start the DMA channel transfer in linked-list mode (Blocking + mode). + (+) The HAL_DMAEx_List_Start_IT() function allows to start the DMA channel transfer in linked-list mode + (Non-blocking mode). + (++) It is mandatory to register a linked-list queue to be executed by a DMA channel before starting + transfer otherwise a HAL_ERROR will be returned. + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA channel transfer in linked-list mode (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma) +{ + HAL_DMA_StateTypeDef dma_state; + uint32_t ccr_value; + uint32_t cllr_mask; + + /* Check the DMA peripheral handle and the linked-list queue parameters */ + if ((hdma == NULL) || (hdma->LinkedListQueue == NULL)) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + dma_state = hdma->State; + ccr_value = hdma->Instance->CCR & DMA_CCR_LSM; + if ((dma_state == HAL_DMA_STATE_READY) || ((dma_state == HAL_DMA_STATE_BUSY) && (ccr_value != 0U))) + { + /* Check DMA channel state is ready */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Process locked */ + __HAL_LOCK(hdma); + + /* Update the DMA channel and the queue states */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the DMA channel and the queue error codes */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(hdma->LinkedListQueue->Head, &cllr_mask, NULL); + + /* Update DMA registers for linked-list transfer */ + hdma->Instance->CLBAR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLBAR_LBA); + hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; + } + + /* Enable DMA channel */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Starts the DMA channel transfer in linked-list mode with interrupts enabled (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma) +{ + HAL_DMA_StateTypeDef dma_state; + uint32_t ccr_value; + uint32_t cllr_mask; + + /* Check the DMA peripheral handle and the linked-list queue parameters */ + if ((hdma == NULL) || (hdma->LinkedListQueue == NULL)) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + dma_state = hdma->State; + ccr_value = hdma->Instance->CCR & DMA_CCR_LSM; + if ((dma_state == HAL_DMA_STATE_READY) || ((dma_state == HAL_DMA_STATE_BUSY) && (ccr_value != 0U))) + { + /* Check DMA channel state is ready */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Process locked */ + __HAL_LOCK(hdma); + + /* Update the DMA channel and the queue states */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the DMA channel and the queue error codes */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Enable common interrupts: Transfer Complete and Transfer Errors ITs */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO)); + + /* Check half transfer complete callback */ + if (hdma->XferHalfCpltCallback != NULL) + { + /* If half transfer complete callback is set, enable the corresponding IT */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); + } + + /* Check suspend callback */ + if (hdma->XferSuspendCallback != NULL) + { + /* If transfer suspend callback is set, enable the corresponding IT */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP); + } + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(hdma->LinkedListQueue->Head, &cllr_mask, NULL); + + /* Update DMA registers for linked-list transfer */ + hdma->Instance->CLBAR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLBAR_LBA); + hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; + } + + /* Enable DMA channel */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Change the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group3 + * +@verbatim + ====================================================================================================================== + ##### Linked-List Management Functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Build linked-list node. + (+) Get linked-list node configuration. + (+) Insert node to linked-list queue in any queue position. + (+) Remove any node from linked-list queue. + (+) Replace any node from linked-list queue. + (+) Reset linked-list queue. + (+) Insert linked-list queue in any queue position. + (+) Set circular mode configuration to linked-list queue. + (+) Clear circular mode configuration from linked-list queue. + (+) Convert static linked-list queue to dynamic format. + (+) Convert dynamic linked-list queue to static format. + (+) Link linked-list queue to DMA channel. + (+) Unlink linked-list queue from DMA channel. + + [..] + (+) The HAL_DMAEx_List_BuildNode() function allows to build linked-list node. + Node type can be : + (++) 2 dimensions addressing node. + (++) Linear addressing node. + + (+) The HAL_DMAEx_List_GetNodeConfig() function allows to get the linked-list node configuration from built node. + + (+) The HAL_DMAEx_List_InsertNode() function allows to insert built linked-list node to static linked-list queue + according to selected position. + + (+) The HAL_DMAEx_List_InsertNode_Head() and HAL_DMAEx_List_InsertNode_Tail() functions allow to insert built + linked-list node to the head (respectively the tail) of static linked-list queue. + + (+) The HAL_DMAEx_List_RemoveNode() function allows to remove selected built linked-list node from static + linked-list queue. + + (+) The HAL_DMAEx_List_RemoveNode_Head() and HAL_DMAEx_List_RemoveNode_Tail() functions allow to remove the head + (respectively the tail) built linked-list node from static linked-list queue. + + (+) The HAL_DMAEx_List_ReplaceNode() function allows to replace selected built linked-list node from static + linked-list queue. + + (+) The HAL_DMAEx_List_ReplaceNode_Head() and HAL_DMAEx_List_ReplaceNode_Tail() functions allow to replace the + head (respectively the tail) built linked-list node of static linked-list queue. + + (+) The HAL_DMAEx_List_ResetQ() function allows to reset static linked-list queue and unlink all built linked-list + nodes. + + (+) The HAL_DMAEx_List_InsertQ() function allows to insert static linked-list source queue to static linked-list + destination queue according to selected position. + + (+) The HAL_DMAEx_List_InsertQ_Head() and HAL_DMAEx_List_InsertQ_Tail() functions allow to insert static + linked-list source queue to the head (respectively the tail) of static linked-list destination queue. + + (+) The HAL_DMAEx_List_SetCircularModeConfig() function allows to link the last static linked-list queue node to + the selected first circular node. + + (+) The HAL_DMAEx_List_SetCircularMode() function allows to link the last static linked-list queue node to the + first static linked-list queue node. + + (+) The HAL_DMAEx_List_ClearCircularMode() function allows to unlink the last static linked-list queue node from + any first circular node position. + + (+) The HAL_DMAEx_List_ConvertQToDynamic() function allows to convert the static linked-list queue to dynamic + format. (Optimized queue execution) + + (+) The HAL_DMAEx_List_ConvertQToStatic() function allows to convert the dynamic linked-list queue to static + format. (Not optimized queue execution) + + (+) The HAL_DMAEx_List_LinkQ() function allows to link the (Dynamic / Static) linked-list queue to DMA channel to + be executed. + + (+) The HAL_DMAEx_List_UnLinkQ() function allows to unlink the (Dynamic / Static) linked-list queue from DMA + channel when execution is completed. + +@endverbatim + * @{ + */ + +/** + * @brief Build a DMA channel node according to the specified parameters in the DMA_NodeConfTypeDef. + * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the + * specified DMA linked-list Node. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @note The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte + * addressable space. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, + DMA_NodeTypeDef *const pNode) +{ + /* Check the node configuration and physical node parameters */ + if ((pNodeConfig == NULL) || (pNode == NULL)) + { + return HAL_ERROR; + } + + /* Check node type parameter */ + assert_param(IS_DMA_NODE_TYPE(pNodeConfig->NodeType)); + + /* Check DMA channel basic transfer parameters */ + assert_param(IS_DMA_SOURCE_INC(pNodeConfig->Init.SrcInc)); + assert_param(IS_DMA_DESTINATION_INC(pNodeConfig->Init.DestInc)); + assert_param(IS_DMA_SOURCE_DATA_WIDTH(pNodeConfig->Init.SrcDataWidth)); + assert_param(IS_DMA_DESTINATION_DATA_WIDTH(pNodeConfig->Init.DestDataWidth)); + assert_param(IS_DMA_DATA_ALIGNMENT(pNodeConfig->DataHandlingConfig.DataAlignment)); + assert_param(IS_DMA_REQUEST(pNodeConfig->Init.Request)); + assert_param(IS_DMA_DIRECTION(pNodeConfig->Init.Direction)); + assert_param(IS_DMA_TCEM_EVENT_MODE(pNodeConfig->Init.TransferEventMode)); + assert_param(IS_DMA_BLOCK_HW_REQUEST(pNodeConfig->Init.BlkHWRequest)); + assert_param(IS_DMA_MODE(pNodeConfig->Init.Mode)); + + /* Check DMA channel parameters */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA) + { + assert_param(IS_DMA_BURST_LENGTH(pNodeConfig->Init.SrcBurstLength)); + assert_param(IS_DMA_BURST_LENGTH(pNodeConfig->Init.DestBurstLength)); + assert_param(IS_DMA_DATA_EXCHANGE(pNodeConfig->DataHandlingConfig.DataExchange)); + assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(pNodeConfig->Init.TransferAllocatedPort)); + } + + /* Check DMA channel trigger parameters */ + assert_param(IS_DMA_TRIGGER_POLARITY(pNodeConfig->TriggerConfig.TriggerPolarity)); + if (pNodeConfig->TriggerConfig.TriggerPolarity != DMA_TRIG_POLARITY_MASKED) + { + assert_param(IS_DMA_TRIGGER_MODE(pNodeConfig->TriggerConfig.TriggerMode)); + assert_param(IS_DMA_TRIGGER_SELECTION(pNodeConfig->TriggerConfig.TriggerSelection)); + } + + /* Check DMA channel repeated block parameters */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + assert_param(IS_DMA_REPEAT_COUNT(pNodeConfig->RepeatBlockConfig.RepeatCount)); + assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.SrcAddrOffset)); + assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset)); + assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset)); + assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset)); + } + + /* Check DMA channel security and privilege attributes parameters */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->SrcSecure)); + assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->DestSecure)); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* Build the DMA channel node */ + DMA_List_BuildNode(pNodeConfig, pNode); + + return HAL_OK; +} + +/** + * @brief Get a DMA channel node configuration. + * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the + * specified DMA linked-list Node. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, + DMA_NodeTypeDef const *const pNode) +{ + /* Check the node configuration and physical node parameters */ + if ((pNodeConfig == NULL) || (pNode == NULL)) + { + return HAL_ERROR; + } + + /* Get the DMA channel node configuration */ + DMA_List_GetNodeConfig(pNodeConfig, pNode); + + return HAL_OK; +} + +/** + * @brief Insert new node in any queue position of linked-list queue according to selecting previous node. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pPrevNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers + * configurations. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pPrevNode, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pPrevNode, pNewNode) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pPrevNode, pNewNode) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Empty queue */ + if (pQList->Head == NULL) + { + /* Add only new node to queue */ + if (pPrevNode == NULL) + { + pQList->Head = pNewNode; + pQList->NodeNumber = 1U; + } + /* Add previous node then new node to queue */ + else + { + pQList->Head = pPrevNode; + pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + pQList->NodeNumber = 2U; + } + } + /* Not empty queue */ + else + { + /* Add new node at the head of queue */ + if (pPrevNode == NULL) + { + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; + pQList->Head = pNewNode; + } + /* Add new node according to selected position */ + else + { + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pQList, pPrevNode, &node_info) == 0U) + { + /* Selected node is the last queue node */ + if (node_info.currentnode_pos == pQList->NodeNumber) + { + /* Check if queue is circular */ + if (pQList->FirstCircularNode != NULL) + { + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; + } + + pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + } + /* Selected node is not the last queue node */ + else + { + pNewNode->LinkRegisters[cllr_offset] = pPrevNode->LinkRegisters[cllr_offset]; + pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + } + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + } + + /* Increment queue node number */ + pQList->NodeNumber++; + } + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Insert new node at the head of linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Empty queue */ + if (pQList->Head == NULL) + { + pQList->Head = pNewNode; + } + /* Not empty queue */ + else + { + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; + pQList->Head = pNewNode; + } + + /* Increment queue node number */ + pQList->NodeNumber++; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Insert new node at the tail of linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Empty queue */ + if (pQList->Head == NULL) + { + pQList->Head = pNewNode; + } + /* Not empty queue */ + else + { + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Check if queue is circular */ + if (pQList->FirstCircularNode != NULL) + { + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; + } + + ((DMA_NodeTypeDef *)node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + } + + /* Increment queue node number */ + pQList->NodeNumber++; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Remove node from any linked-list queue position. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNode) +{ + uint32_t previousnode_addr; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the node parameters */ + if ((pQList == NULL) || (pNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNode, NULL, &cllr_offset); + + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pQList, pNode, &node_info) == 0U) + { + /* Removed node is the head node */ + if (node_info.currentnode_pos == 1U) + { + /* Check if first circular node queue is the first node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr)) + { + /* Find last queue node */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + + /* Update the queue head node */ + pQList->Head = (DMA_NodeTypeDef *)(((uint32_t)pQList->Head & DMA_CLBAR_LBA) + + (pNode->LinkRegisters[cllr_offset] & DMA_CLLR_LA)); + /* Unlink node to be removed */ + pNode->LinkRegisters[cllr_offset] = 0U; + } + /* Removed node is the last node */ + else if (node_info.currentnode_pos == pQList->NodeNumber) + { + /* Clear CLLR for previous node */ + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear CLLR for last node */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + /* Removed node is in the middle */ + else + { + /* Store previous node address to be updated later */ + previousnode_addr = node_info.previousnode_addr; + + /* Check if first circular node queue is the current node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr)) + { + /* Find last queue node */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + + /* Link previous node */ + ((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[cllr_offset] = pNode->LinkRegisters[cllr_offset]; + + /* Unlink node to be removed */ + pNode->LinkRegisters[cllr_offset] = 0U; + } + + /* Decrement node number */ + pQList->NodeNumber--; + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + + /* Check if queue is empty */ + if (pQList->NodeNumber == 0U) + { + /* Clean empty queue parameter */ + DMA_List_CleanQueue(pQList); + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Remove the head node from linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + uint32_t current_addr; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Queue contains only one node */ + if (pQList->NodeNumber == 1U) + { + pQList->Head->LinkRegisters[cllr_offset] = 0U; + pQList->FirstCircularNode = 0U; + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + } + /* Queue contains more then one node */ + else + { + /* Check if first circular node queue is the first node */ + if (pQList->FirstCircularNode == pQList->Head) + { + /* Find last queue node */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + + current_addr = pQList->Head->LinkRegisters[cllr_offset] & DMA_CLLR_LA; + pQList->Head->LinkRegisters[cllr_offset] = 0U; + pQList->Head = ((DMA_NodeTypeDef *)(current_addr + ((uint32_t)pQList->Head & DMA_CLBAR_LBA))); + } + + /* Decrement node number */ + pQList->NodeNumber--; + + /* Check if queue is empty */ + if (pQList->NodeNumber == 0U) + { + /* Clean empty queue parameter */ + DMA_List_CleanQueue(pQList); + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Remove the tail node from linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Queue contains only one node */ + if (pQList->NodeNumber == 1U) + { + pQList->Head->LinkRegisters[cllr_offset] = 0U; + pQList->FirstCircularNode = 0U; + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + } + /* Queue contains more then one node */ + else + { + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear CLLR for previous node */ + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear CLLR for last node */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + + /* Decrement node number */ + pQList->NodeNumber--; + + /* Check if queue is empty */ + if (pQList->NodeNumber == 0U) + { + /* Clean empty queue parameter */ + DMA_List_CleanQueue(pQList); + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Replace node in linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pOldNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list old node registers + * configurations. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pOldNode, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the nodes parameters */ + if ((pQList == NULL) || (pOldNode == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pOldNode, pNewNode) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pOldNode, pNewNode) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pQList, pOldNode, &node_info) == 0U) + { + /* Replaced node is the head node */ + if (node_info.currentnode_pos == 1U) + { + pNewNode->LinkRegisters[cllr_offset] = + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset]; + pQList->Head = pNewNode; + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Check if first circular node queue is the first node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr)) + { + /* Find last queue node */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + } + /* Replaced node is the last */ + else if (node_info.currentnode_pos == pQList->NodeNumber) + { + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Check if first circular node queue is the last node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr))) + { + /* Link first circular node to new node */ + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + /* Check if first circular node queue is not the last node */ + else if (pQList->FirstCircularNode != NULL) + { + /* Link first circular node to new node */ + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + } + /* Replaced node is in the middle */ + else + { + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + pNewNode->LinkRegisters[cllr_offset] = + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset]; + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Check if first circular node queue is the current node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr))) + { + /* Find last node and get its position in selected queue */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Link last queue node to new node */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + } + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Replace the head node of linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_offset; + uint32_t cllr_mask; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Check if first circular node queue is the first node */ + if (pQList->FirstCircularNode == pQList->Head) + { + /* Find last queue node */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + + /* Replace head node */ + pNewNode->LinkRegisters[cllr_offset] = pQList->Head->LinkRegisters[cllr_offset]; + pQList->Head->LinkRegisters[cllr_offset] = 0U; + pQList->Head = pNewNode; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Replace the tail node of linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Find last node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Link previous node to new node */ + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Clear CLLR for current node */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Check if first circular node queue is the last node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr))) + { + /* Link first circular node to new node */ + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + /* Check if first circular node queue is not the last node */ + else if (pQList->FirstCircularNode != NULL) + { + /* Link first circular node to new node */ + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + + /* Check if queue contains one node */ + if (pQList->NodeNumber == 1U) + { + pQList->Head = pNewNode; + } + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Reset the linked-list queue and unlink queue nodes. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check queue state */ + if (pQList->State == HAL_DMA_QUEUE_STATE_BUSY) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_BUSY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Check the queue */ + if (pQList->Head != NULL) + { + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Reset selected queue nodes */ + node_info.cllr_offset = cllr_offset; + DMA_List_ResetQueueNodes(pQList, &node_info); + } + + /* Reset head node address */ + pQList->Head = NULL; + + /* Reset node number */ + pQList->NodeNumber = 0U; + + /* Reset first circular node */ + pQList->FirstCircularNode = NULL; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Insert a source linked-list queue to a destination linked-list queue according to selecting previous node. + * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information. + * @param pPrevNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers + * configurations. + * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, + DMA_NodeTypeDef const *const pPrevNode, + DMA_QListTypeDef *const pDestQList) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef src_q_node_info; + DMA_NodeInQInfoTypeDef dest_q_node_info; + + /* Check the source and destination queues and the previous node parameters */ + if ((pSrcQList == NULL) || (pDestQList == NULL)) + { + return HAL_ERROR; + } + + /* Check the source queue */ + if (pSrcQList->Head == NULL) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check the source queue type */ + if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check the destination queue type */ + if (pDestQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check the source queue circularity */ + if (pSrcQList->FirstCircularNode != NULL) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the source queue state */ + pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset); + + /* Empty destination queue */ + if (pDestQList->Head == NULL) + { + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber = pSrcQList->NodeNumber; + } + /* Not empty destination queue */ + else + { + /* Previous node is empty */ + if (pPrevNode == NULL) + { + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Check if first circular node queue is the first node */ + if (pDestQList->FirstCircularNode == pDestQList->Head) + { + /* Find node and get its position in selected queue */ + dest_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info); + + /* Link destination queue tail node to new first circular node */ + ((DMA_NodeTypeDef *)dest_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + + /* Set the head node of source queue as the first circular node */ + pDestQList->FirstCircularNode = pSrcQList->Head; + } + + /* Link the last node of source queue to the fist node of destination queue */ + ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pDestQList->Head & DMA_CLLR_LA) | cllr_mask; + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber += pSrcQList->NodeNumber; + } + /* Previous node is not empty */ + else + { + /* Find node and get its position in selected queue */ + dest_q_node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pDestQList, pPrevNode, &dest_q_node_info) == 0U) + { + /* Selected node is the last destination queue node */ + if (dest_q_node_info.currentnode_pos == pDestQList->NodeNumber) + { + /* Link the first node of source queue to the last node of destination queue */ + ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + pDestQList->NodeNumber += pSrcQList->NodeNumber; + + /* Check if first circular node queue is not empty */ + if (pDestQList->FirstCircularNode != NULL) + { + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Find first circular node */ + (void)DMA_List_FindNode(pDestQList, pDestQList->FirstCircularNode, &dest_q_node_info); + + /* Link last source queue node to first destination queue */ + ((DMA_NodeTypeDef *)src_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + (dest_q_node_info.currentnode_addr & DMA_CLLR_LA) | cllr_mask; + } + } + /* Selected node is not the last destination queue node */ + else + { + /* Link the first node of source queue to the previous node of destination queue */ + ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Link the last node of source queue to the next node of destination queue */ + ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + (dest_q_node_info.nextnode_addr & DMA_CLLR_LA) | cllr_mask; + + /* Update queues counter */ + pDestQList->NodeNumber += pSrcQList->NodeNumber; + } + } + else + { + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + } + } + + /* Clean the source queue variable as it is obsolete */ + DMA_List_CleanQueue(pSrcQList); + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(src_q_node_info); + UNUSED(dest_q_node_info); + + return HAL_OK; +} + +/** + * @brief Insert a source linked-list queue at the head of destination queue. + * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information. + * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, + DMA_QListTypeDef *const pDestQList) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef src_q_node_info; + DMA_NodeInQInfoTypeDef dest_q_node_info; + + /* Check the source and destination queues and the previous node parameters */ + if ((pSrcQList == NULL) || (pDestQList == NULL)) + { + return HAL_ERROR; + } + + /* Check the source queue */ + if (pSrcQList->Head == NULL) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check the source queue type */ + if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check the destination queue type */ + if (pDestQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the source queue state */ + pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset); + + /* Empty destination queue */ + if (pDestQList->Head == NULL) + { + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber = pSrcQList->NodeNumber; + } + /* Not empty destination queue */ + else + { + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Check if first circular node queue is the first node */ + if (pDestQList->FirstCircularNode == pDestQList->Head) + { + /* Find node and get its position in selected queue */ + dest_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info); + + /* Link destination queue tail node to new first circular node */ + ((DMA_NodeTypeDef *)dest_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + + /* Set the head node of source queue as the first circular node */ + pDestQList->FirstCircularNode = pSrcQList->Head; + } + + /* Link the last node of source queue to the fist node of destination queue */ + ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pDestQList->Head & DMA_CLLR_LA) | cllr_mask; + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber += pSrcQList->NodeNumber; + } + + /* Clean the source queue variable as it is obsolete */ + DMA_List_CleanQueue(pSrcQList); + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(src_q_node_info); + UNUSED(dest_q_node_info); + + return HAL_OK; +} + +/** + * @brief Insert a source linked-list queue at the tail of destination queue. + * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information. + * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, + DMA_QListTypeDef *const pDestQList) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef src_q_node_info; + DMA_NodeInQInfoTypeDef dest_q_node_info; + + /* Check the source and destination queues and the previous node parameters */ + if ((pSrcQList == NULL) || (pDestQList == NULL)) + { + return HAL_ERROR; + } + + /* Check the source queue */ + if (pSrcQList->Head == NULL) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check the source queue type */ + if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check the destination queue type */ + if (pDestQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the source queue state */ + pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset); + + /* Empty destination queue */ + if (pDestQList->Head == NULL) + { + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber = pSrcQList->NodeNumber; + } + /* Not empty destination queue */ + else + { + /* Find node and get its position in selected queue */ + dest_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info); + + /* Update source queue last node CLLR to link it with destination first node */ + ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + pDestQList->NodeNumber += pSrcQList->NodeNumber; + + /* Check if first circular node queue is not empty */ + if (pDestQList->FirstCircularNode != NULL) + { + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Find first circular node */ + (void)DMA_List_FindNode(pDestQList, pDestQList->FirstCircularNode, &dest_q_node_info); + + /* Link last source queue node to first destination queue */ + ((DMA_NodeTypeDef *)src_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + (dest_q_node_info.currentnode_addr & DMA_CLLR_LA) | cllr_mask; + } + } + + /* Clean the source queue variable as it is obsolete */ + DMA_List_CleanQueue(pSrcQList); + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(src_q_node_info); + + return HAL_OK; +} + +/** + * @brief Set circular mode configuration for linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pFirstCircularNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list first circular node + * registers configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pFirstCircularNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the first circular node parameters */ + if ((pQList == NULL) || (pFirstCircularNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue circular mode */ + if (pQList->FirstCircularNode != NULL) + { + if (pQList->FirstCircularNode == pFirstCircularNode) + { + return HAL_OK; + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pFirstCircularNode, &cllr_mask, &cllr_offset); + + /* Find the first circular node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pQList, pFirstCircularNode, &node_info) == 0U) + { + /* Find the last queue node and get its position in selected queue */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Set circular mode */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pFirstCircularNode & DMA_CLLR_LA) | cllr_mask; + + /* Update first circular node in queue */ + pQList->FirstCircularNode = pFirstCircularNode; + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Set circular mode for linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue circular mode */ + if (pQList->FirstCircularNode != NULL) + { + if (pQList->FirstCircularNode == pQList->Head) + { + return HAL_OK; + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, &cllr_mask, &cllr_offset); + + /* Find the last queue node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Set circular mode */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; + + /* Update linked-list circular state */ + pQList->FirstCircularNode = pQList->Head; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Clear circular mode for linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue circular mode */ + if (pQList->FirstCircularNode == NULL) + { + return HAL_OK; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Find the last queue node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear circular mode */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Update linked-list circular configuration */ + pQList->FirstCircularNode = NULL; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Convert a linked-list queue to dynamic (Optimized DMA queue execution). + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + uint32_t currentnode_addr; + DMA_NodeTypeDef context_node; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check if queue is dynamic */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + return HAL_OK; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Check queue circularity */ + if (pQList->FirstCircularNode != 0U) + { + /* Find the last queue node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + } + + /* Set current node address */ + currentnode_addr = (uint32_t)pQList->Head; + + /* Store register value */ + DMA_List_FillNode(pQList->Head, &context_node); + + /* Convert all nodes to dyncamic (Bypass head node) */ + for (uint32_t node_count = 1U; node_count < pQList->NodeNumber; node_count++) + { + /* Update node address */ + MODIFY_REG(currentnode_addr, DMA_CLLR_LA, (context_node.LinkRegisters[cllr_offset] & DMA_CLLR_LA)); + + /* Bypass the first circular node when first circular node isn't the last queue node */ + if (((uint32_t)pQList->FirstCircularNode != 0U) && + ((uint32_t)pQList->FirstCircularNode != node_info.currentnode_addr) && + ((uint32_t)pQList->FirstCircularNode == currentnode_addr)) + { + /* Copy first circular node to context node */ + DMA_List_FillNode(pQList->FirstCircularNode, &context_node); + } + else + { + /* Convert current node to dynamic */ + DMA_List_ConvertNodeToDynamic((uint32_t)&context_node, currentnode_addr, (cllr_offset + 1U)); + } + } + + /* Check if first circular node is the last node queue */ + if (((uint32_t)pQList->FirstCircularNode != 0U) && + ((uint32_t)pQList->FirstCircularNode != node_info.currentnode_addr)) + { + /* Update all queue nodes CLLR */ + DMA_List_UpdateDynamicQueueNodesCLLR(pQList, LASTNODE_ISNOT_CIRCULAR); + } + else + { + /* Update all queue nodes CLLR */ + DMA_List_UpdateDynamicQueueNodesCLLR(pQList, LASTNODE_IS_CIRCULAR); + } + + /* Set queue type */ + pQList->Type = QUEUE_TYPE_DYNAMIC; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Convert a linked-list queue to static (Not optimized DMA queue execution). + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + uint32_t currentnode_addr; + DMA_NodeTypeDef context_node; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check if queue is static */ + if (pQList->Type == QUEUE_TYPE_STATIC) + { + return HAL_OK; + } + + /* Set current node address */ + currentnode_addr = (uint32_t)pQList->Head; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Set all CLLR queue nodes to their default positions */ + DMA_List_UpdateStaticQueueNodesCLLR(pQList, UPDATE_CLLR_POSITION); + + /* Convert all nodes to static (Bypass head node) */ + for (uint32_t node_count = 1U; node_count < pQList->NodeNumber; node_count++) + { + /* Update context node register values */ + DMA_List_FillNode((DMA_NodeTypeDef *)currentnode_addr, &context_node); + + /* Update node address */ + MODIFY_REG(currentnode_addr, DMA_CLLR_LA, (context_node.LinkRegisters[cllr_offset] & DMA_CLLR_LA)); + + /* Convert current node to static */ + DMA_List_ConvertNodeToStatic((uint32_t)&context_node, currentnode_addr, (cllr_offset + 1U)); + } + + /* Set all CLLR queue nodes to their default values */ + DMA_List_UpdateStaticQueueNodesCLLR(pQList, UPDATE_CLLR_VALUE); + + /* Set queue type */ + pQList->Type = QUEUE_TYPE_STATIC; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Link linked-list queue to a DMA channel. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma, + DMA_QListTypeDef *const pQList) +{ + HAL_DMA_StateTypeDef state; + + /* Check the DMA channel handle and the queue parameters */ + if ((hdma == NULL) || (pQList == NULL)) + { + return HAL_ERROR; + } + + /* Get DMA state */ + state = hdma->State; + + /* Check DMA channel state */ + if ((hdma->State == HAL_DMA_STATE_BUSY) || (state == HAL_DMA_STATE_SUSPEND)) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + /* Check queue state */ + if (pQList->State == HAL_DMA_QUEUE_STATE_BUSY) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_BUSY; + + return HAL_ERROR; + } + + /* Check linearity compatibility */ + if ((IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) == 0U) && + ((pQList->Head->NodeInfo & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_UNSUPPORTED; + + return HAL_ERROR; + } + + /* Check circularity compatibility */ + if (hdma->Mode == DMA_LINKEDLIST_CIRCULAR) + { + /* Check first circular node */ + if (pQList->FirstCircularNode == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + } + else + { + /* Check first circular node */ + if (pQList->FirstCircularNode != NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + } + + /* Register queue to DMA handle */ + hdma->LinkedListQueue = pQList; + + return HAL_OK; +} + +/** + * @brief Unlink linked-list queue from a DMA channel. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma) +{ + HAL_DMA_StateTypeDef state; + + /* Check the DMA channel parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Get DMA state */ + state = hdma->State; + + /* Check DMA channel state */ + if ((hdma->State == HAL_DMA_STATE_BUSY) || (state == HAL_DMA_STATE_SUSPEND)) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + /* Clear queue information from DMA channel handle */ + hdma->LinkedListQueue = NULL; + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group4 + * +@verbatim + ====================================================================================================================== + ##### Data handling, repeated block and trigger configuration functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Configure DMA channel data handling. + (+) Configure DMA channel repeated block. + (+) Configure DMA channel trigger. + + [..] + (+) The HAL_DMAEx_ConfigDataHandling() function allows to configure DMA channel data handling. + (++) GPDMA data handling : byte-based reordering, packing/unpacking, padding/truncation, sign extension + and left/right alignment. + (++) LPDMA data handling : byte-based padding/truncation, sign extension and left/right alignment. + + (+) The HAL_DMAEx_ConfigTrigger() function allows to configure DMA channel HW triggers. + + (+) The HAL_DMAEx_ConfigRepeatBlock() function allows to configure DMA channel repeated block. + (++) This feature is available only for channel that supports 2 dimensions addressing capability. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the DMA channel data handling according to the specified parameters in the + * DMA_DataHandlingConfTypeDef. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * for the specified DMA Channel. + * @param pConfigDataHandling : Pointer to a DMA_DataHandlingConfTypeDef structure that contains the data handling + * configuration. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma, + DMA_DataHandlingConfTypeDef const *const pConfigDataHandling) +{ + /* Check the DMA peripheral handle and data handling parameters */ + if ((hdma == NULL) || (pConfigDataHandling == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_DATA_ALIGNMENT(pConfigDataHandling->DataAlignment)); + assert_param(IS_DMA_DATA_EXCHANGE(pConfigDataHandling->DataExchange)); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + MODIFY_REG(hdma->Instance->CTR1, (DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_PAM), + (pConfigDataHandling->DataAlignment | pConfigDataHandling->DataExchange)); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Configure the DMA channel trigger according to the specified parameters in the DMA_TriggerConfTypeDef. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for + * the specified DMA Channel. + * @param pConfigTrigger : Pointer to a DMA_TriggerConfTypeDef structure that contains the trigger configuration. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma, + DMA_TriggerConfTypeDef const *const pConfigTrigger) +{ + /* Check the DMA peripheral handle and trigger parameters */ + if ((hdma == NULL) || (pConfigTrigger == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_TRIGGER_POLARITY(pConfigTrigger->TriggerPolarity)); + assert_param(IS_DMA_TRIGGER_MODE(pConfigTrigger->TriggerMode)); + assert_param(IS_DMA_TRIGGER_SELECTION(pConfigTrigger->TriggerSelection)); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM), + (pConfigTrigger->TriggerPolarity | pConfigTrigger->TriggerMode | + (pConfigTrigger->TriggerSelection << DMA_CTR2_TRIGSEL_Pos))); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Configure the DMA channel repeated block according to the specified parameters in the + * DMA_RepeatBlockConfTypeDef. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * for the specified DMA Channel. + * @param pConfigRepeatBlock : Pointer to a DMA_RepeatBlockConfTypeDef structure that contains the repeated block + * configuration. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma, + DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock) +{ + uint32_t tmpreg1; + uint32_t tmpreg2; + + /* Check the DMA peripheral handle and repeated block parameters */ + if ((hdma == NULL) || (pConfigRepeatBlock == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_REPEAT_COUNT(pConfigRepeatBlock->RepeatCount)); + assert_param(IS_DMA_BURST_ADDR_OFFSET(pConfigRepeatBlock->SrcAddrOffset)); + assert_param(IS_DMA_BURST_ADDR_OFFSET(pConfigRepeatBlock->DestAddrOffset)); + assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pConfigRepeatBlock->BlkSrcAddrOffset)); + assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pConfigRepeatBlock->BlkDestAddrOffset)); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Store repeat block count */ + tmpreg1 = ((pConfigRepeatBlock->RepeatCount - 1U) << DMA_CBR1_BRC_Pos); + + /* Check the sign of single/burst destination address offset value */ + if (pConfigRepeatBlock->DestAddrOffset < 0) + { + /* Store single/burst destination address offset configuration (signed case) */ + tmpreg1 |= DMA_CBR1_DDEC; + tmpreg2 = (uint32_t)(- pConfigRepeatBlock->DestAddrOffset); + tmpreg2 = tmpreg2 << DMA_CTR3_DAO_Pos; + } + else + { + /* Store single/burst destination address offset configuration (unsigned case) */ + tmpreg2 = ((uint32_t)pConfigRepeatBlock->DestAddrOffset << DMA_CTR3_DAO_Pos); + } + + /* Check the sign of single/burst source address offset value */ + if (pConfigRepeatBlock->SrcAddrOffset < 0) + { + /* Store single/burst source address offset configuration (signed case) */ + tmpreg1 |= DMA_CBR1_SDEC; + tmpreg2 |= (uint32_t)(- pConfigRepeatBlock->SrcAddrOffset); + } + else + { + /* Store single/burst source address offset configuration (unsigned case) */ + tmpreg2 |= (uint32_t)pConfigRepeatBlock->SrcAddrOffset; + } + + /* Write DMA Channel Transfer Register 3 (CTR3) */ + WRITE_REG(hdma->Instance->CTR3, tmpreg2); + + /* Check the sign of block destination address offset value */ + if (pConfigRepeatBlock->BlkDestAddrOffset < 0) + { + /* Store block destination address offset configuration (signed case) */ + tmpreg1 |= DMA_CBR1_BRDDEC; + tmpreg2 = (uint32_t)(- pConfigRepeatBlock->BlkDestAddrOffset); + tmpreg2 = tmpreg2 << DMA_CBR2_BRDAO_Pos; + } + else + { + /* Store block destination address offset configuration (unsigned case) */ + tmpreg2 = ((uint32_t)pConfigRepeatBlock->BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos); + } + + /* Check the sign of block source address offset value */ + if (pConfigRepeatBlock->BlkSrcAddrOffset < 0) + { + /* Store block source address offset configuration (signed case) */ + tmpreg1 |= DMA_CBR1_BRSDEC; + tmpreg2 |= (uint32_t)(- pConfigRepeatBlock->BlkSrcAddrOffset); + } + else + { + /* Store block source address offset configuration (unsigned case) */ + tmpreg2 |= (uint32_t)pConfigRepeatBlock->BlkSrcAddrOffset; + } + + /* Write DMA Channel block register 2 (CBR2) */ + WRITE_REG(hdma->Instance->CBR2, tmpreg2); + + /* Write DMA Channel block register 1 (CBR1) */ + WRITE_REG(hdma->Instance->CBR1, tmpreg1); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group5 + * +@verbatim + ====================================================================================================================== + ##### Suspend and resume operation functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Suspend any ongoing DMA channel transfer. + (+) Resume any suspended DMA channel transfer. + + [..] + (+) The HAL_DMAEx_Suspend() function allows to suspend any ongoing DMA channel transfer in polling mode (Blocking + mode). + + (+) The HAL_DMAEx_Suspend_IT() function allows to suspend any ongoing DMA channel transfer in interrupt mode + (Non-blocking mode). + + (+) The HAL_DMAEx_Resume() function allows to resume any suspended DMA channel transfer. + +@endverbatim + * @{ + */ + +/** + * @brief Suspend any ongoing DMA channel transfer in polling mode (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA channel. + * @note After suspending a DMA channel, a check for wait until the DMA channel is effectively suspended is added. If + * a channel is suspended while a data transfer is ongoing, the current data will be transferred and the + * channel will be effectively suspended only after the transfer of this single/burst data is finished. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Suspend the channel */ + hdma->Instance->CCR |= DMA_CCR_SUSP; + + /* Check if the DMA channel is suspended */ + while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U) + { + /* Check for the timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_SUSPEND; + } + + return HAL_OK; +} + +/** + * @brief Suspend any ongoing DMA channel transfer in polling mode (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Suspend the DMA channel and activate suspend interrupt */ + hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE); + } + + return HAL_OK; +} + +/** + * @brief Resume any suspended DMA channel transfer. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_SUSPEND) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Resume the DMA channel */ + hdma->Instance->CCR &= (~DMA_CCR_SUSP); + + /* Clear the suspend flag */ + hdma->Instance->CFCR |= DMA_CFCR_SUSPF; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_BUSY; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group6 + * +@verbatim + ====================================================================================================================== + ##### Fifo status function ##### + ====================================================================================================================== + [..] + This section provides function allowing to get DMA channel FIFO level. + + [..] + (+) The HAL_DMAEx_GetFifoLevel() function allows to return the number of available write beats in the FIFO, in + units of the programmed destination data. + (++) This API is available only for DMA channels that supports FIFO. + +@endverbatim + * @{ + */ + +/** + * @brief Get and returns the DMA channel FIFO level. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval Returns the number of available beats in FIFO. + */ +uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma) +{ + return ((hdma->Instance->CSR & DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos); +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Functions DMAEx Private Functions + * @brief DMAEx Private Functions + * @{ + */ + +/** + * @brief Initialize the DMA handle according to the specified parameters in the DMA_InitTypeDef. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval None. + */ +static void DMA_List_Init(DMA_HandleTypeDef const *const hdma) +{ + uint32_t tmpreg; + + /* Prepare DMA Channel Control Register (CCR) value */ + tmpreg = hdma->InitLinkedList.Priority | hdma->InitLinkedList.LinkStepMode; + + /* Check DMA channel instance */ + if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) + { + tmpreg |= hdma->InitLinkedList.LinkAllocatedPort; + } + + /* Write DMA Channel Control Register (CCR) */ + MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg); + + /* Write DMA Channel Control Register (CTR1) */ + WRITE_REG(hdma->Instance->CTR1, 0U); + + /* Write DMA Channel Control Register (CTR2) */ + WRITE_REG(hdma->Instance->CTR2, hdma->InitLinkedList.TransferEventMode); + + /* Write DMA Channel Control Register (CBR1) */ + WRITE_REG(hdma->Instance->CBR1, 0U); + + /* Write DMA Channel Control Register (CSAR) */ + WRITE_REG(hdma->Instance->CSAR, 0U); + + /* Write DMA Channel Control Register (CDAR) */ + WRITE_REG(hdma->Instance->CDAR, 0U); + + /* If 2D Addressing is supported by current channel */ + if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) + { + /* Write DMA Channel Control Register (CTR3) */ + WRITE_REG(hdma->Instance->CTR3, 0U); + + /* Write DMA Channel Control Register (CBR2) */ + WRITE_REG(hdma->Instance->CBR2, 0U); + } + + /* Write DMA Channel linked-list address register (CLLR) */ + WRITE_REG(hdma->Instance->CLLR, 0U); +} + +/** + * @brief Build a DMA channel node according to the specified parameters in the DMA_NodeConfTypeDef. + * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the + * specified DMA linked-list Node. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @retval None. + */ +static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, + DMA_NodeTypeDef *const pNode) +{ + int32_t blockoffset; + + /* Update CTR1 register value ***************************************************************************************/ + /* Prepare DMA channel transfer register (CTR1) value */ + pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] = pNodeConfig->Init.DestInc | + pNodeConfig->Init.DestDataWidth | + pNodeConfig->DataHandlingConfig.DataAlignment | + pNodeConfig->Init.SrcInc | + pNodeConfig->Init.SrcDataWidth; + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* set source channel security attribute */ + if (pNodeConfig->SrcSecure == DMA_CHANNEL_SRC_SEC) + { + pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_SSEC; + } + + /* set destination channel security attribute */ + if (pNodeConfig->DestSecure == DMA_CHANNEL_DEST_SEC) + { + pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_DSEC; + } +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* Add parameters related to DMA configuration */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA) + { + /* Prepare DMA channel transfer register (CTR1) value */ + pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= + (pNodeConfig->Init.TransferAllocatedPort | pNodeConfig->DataHandlingConfig.DataExchange | + (((pNodeConfig->Init.DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1) | + (((pNodeConfig->Init.SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1)); + } + /*********************************************************************************** CTR1 register value is updated */ + + + /* Update CTR2 register value ***************************************************************************************/ + /* Prepare DMA channel transfer register 2 (CTR2) value */ + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] = pNodeConfig->Init.TransferEventMode | + (pNodeConfig->Init.Request & (DMA_CTR2_REQSEL | DMA_CTR2_SWREQ)); + + /* Check for memory to peripheral transfer */ + if ((pNodeConfig->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Check for GPDMA */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA) + { + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= DMA_CTR2_DREQ; + } + } + /* Memory to memory transfer */ + else if ((pNodeConfig->Init.Direction) == DMA_MEMORY_TO_MEMORY) + { + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= DMA_CTR2_SWREQ; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + + /* Check if trigger feature is active */ + if (pNodeConfig->TriggerConfig.TriggerPolarity != DMA_TRIG_POLARITY_MASKED) + { + /* Prepare DMA channel transfer register 2 (CTR2) value */ + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= + pNodeConfig->TriggerConfig.TriggerMode | pNodeConfig->TriggerConfig.TriggerPolarity | + ((pNodeConfig->TriggerConfig.TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL); + } + /*********************************************************************************** CTR2 register value is updated */ + + + /* Update CBR1 register value ***************************************************************************************/ + /* Prepare DMA channel block register 1 (CBR1) value */ + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (pNodeConfig->DataSize & DMA_CBR1_BNDT); + + /* If 2D addressing is supported by the selected DMA channel */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + /* Set the new CBR1 Register value */ + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= + (((pNodeConfig->RepeatBlockConfig.RepeatCount - 1U) << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC); + + /* If the source address offset is negative, set SDEC bit */ + if (pNodeConfig->RepeatBlockConfig.SrcAddrOffset < 0) + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_SDEC; + } + else + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_SDEC); + } + + /* If the destination address offset is negative, set DDEC bit */ + if (pNodeConfig->RepeatBlockConfig.DestAddrOffset < 0) + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_DDEC; + } + else + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_DDEC); + } + + /* If the repeated block source address offset is negative, set BRSEC bit */ + if (pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset < 0) + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_BRSDEC; + } + else + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_BRSDEC); + } + + /* if the repeated block destination address offset is negative, set BRDEC bit */ + if (pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset < 0) + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_BRDDEC; + } + else + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_BRDDEC); + } + } + /*********************************************************************************** CBR1 register value is updated */ + + + /* Update CSAR register value ***************************************************************************************/ + pNode->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = pNodeConfig->SrcAddress; + /*********************************************************************************** CSAR register value is updated */ + + + /* Update CDAR register value ***************************************************************************************/ + pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = pNodeConfig->DstAddress; + /*********************************************************************************** CDAR register value is updated */ + + /* Check if the selected channel is 2D addressing */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + /* Update CTR3 register value *************************************************************************************/ + /* Write new CTR3 Register value : source address offset */ + if (pNodeConfig->RepeatBlockConfig.SrcAddrOffset < 0) + { + blockoffset = (- pNodeConfig->RepeatBlockConfig.SrcAddrOffset); + pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] = ((uint32_t)blockoffset & DMA_CTR3_SAO); + } + else + { + pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] = + ((uint32_t)pNodeConfig->RepeatBlockConfig.SrcAddrOffset & DMA_CTR3_SAO); + } + + /* Write new CTR3 Register value : destination address offset */ + if (pNodeConfig->RepeatBlockConfig.DestAddrOffset < 0) + { + blockoffset = (- pNodeConfig->RepeatBlockConfig.DestAddrOffset); + pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] |= (((uint32_t)blockoffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO); + } + else + { + pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] |= + (((uint32_t)pNodeConfig->RepeatBlockConfig.DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO); + } + /********************************************************************************* CTR3 register value is updated */ + + + /* Update CBR2 register value *************************************************************************************/ + /* Write new CBR2 Register value : repeated block source address offset */ + if (pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset < 0) + { + blockoffset = (- pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset); + pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] = ((uint32_t)blockoffset & DMA_CBR2_BRSAO); + } + else + { + pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] = + ((uint32_t)pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset & DMA_CBR2_BRSAO); + } + + /* Write new CBR2 Register value : repeated block destination address offset */ + if (pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset < 0) + { + blockoffset = (- pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset); + pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] |= + (((uint32_t)blockoffset & DMA_CBR2_BRSAO) << DMA_CBR2_BRDAO_Pos); + } + else + { + pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] |= + (((uint32_t)pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO); + } + /********************************************************************************* CBR2 register value is updated */ + } + + /* Update node information value ************************************************************************************/ + /* Set node information */ + pNode->NodeInfo = pNodeConfig->NodeType; + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + pNode->NodeInfo |= (NODE_CLLR_2D_DEFAULT_OFFSET << NODE_CLLR_IDX_POS); + } + else + { + pNode->NodeInfo |= (NODE_CLLR_LINEAR_DEFAULT_OFFSET << NODE_CLLR_IDX_POS); + } + /******************************************************************************** Node information value is updated */ +} + +/** + * @brief Get a DMA channel node configuration. + * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the + * specified DMA linked-list Node. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @retval None. + */ +static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, + DMA_NodeTypeDef const *const pNode) +{ + uint16_t offset; + + /* Get node information *********************************************************************************************/ + pNodeConfig->NodeType = (pNode->NodeInfo & NODE_TYPE_MASK); + /*************************************************************************************** Node type value is updated */ + + + /* Get CTR1 fields values *******************************************************************************************/ + pNodeConfig->Init.SrcInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SINC; + pNodeConfig->Init.DestInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DINC; + pNodeConfig->Init.SrcDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SDW_LOG2; + pNodeConfig->Init.DestDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; + pNodeConfig->Init.SrcBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & + DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U; + pNodeConfig->Init.DestBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & + DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U; + pNodeConfig->Init.TransferAllocatedPort = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & + (DMA_CTR1_SAP | DMA_CTR1_DAP); + pNodeConfig->DataHandlingConfig.DataExchange = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & + (DMA_CTR1_SBX | DMA_CTR1_DBX | DMA_CTR1_DHX); + pNodeConfig->DataHandlingConfig.DataAlignment = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_PAM; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SSEC) != 0U) + { + pNodeConfig->SrcSecure = DMA_CHANNEL_SRC_SEC; + } + else + { + pNodeConfig->SrcSecure = DMA_CHANNEL_SRC_NSEC; + } + + if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DSEC) != 0U) + { + pNodeConfig->DestSecure = DMA_CHANNEL_DEST_SEC; + } + else + { + pNodeConfig->DestSecure = DMA_CHANNEL_DEST_NSEC; + } +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + /*********************************************************************************** CTR1 fields values are updated */ + + + /* Get CTR2 fields values *******************************************************************************************/ + if ((pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_SWREQ) != 0U) + { + pNodeConfig->Init.Request = DMA_REQUEST_SW; + pNodeConfig->Init.Direction = DMA_MEMORY_TO_MEMORY; + } + else + { + pNodeConfig->Init.Request = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_REQSEL; + + if ((pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_DREQ) != 0U) + { + pNodeConfig->Init.Direction = DMA_MEMORY_TO_PERIPH; + } + else + { + pNodeConfig->Init.Direction = DMA_PERIPH_TO_MEMORY; + } + } + + pNodeConfig->Init.BlkHWRequest = (pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_BREQ); + pNodeConfig->TriggerConfig.TriggerMode = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TRIGM; + pNodeConfig->TriggerConfig.TriggerPolarity = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TRIGPOL; + pNodeConfig->TriggerConfig.TriggerSelection = (pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & + DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos; + pNodeConfig->Init.TransferEventMode = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TCEM; + /*********************************************************************************** CTR2 fields values are updated */ + + + /* Get CBR1 fields **************************************************************************************************/ + pNodeConfig->DataSize = pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BNDT; + + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + pNodeConfig->RepeatBlockConfig.RepeatCount = + ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos) + 1U; + } + else + { + pNodeConfig->RepeatBlockConfig.RepeatCount = 1U; + } + /*********************************************************************************** CBR1 fields values are updated */ + + + /* Get CSAR field ***************************************************************************************************/ + pNodeConfig->SrcAddress = pNode->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET]; + /************************************************************************************** CSAR field value is updated */ + + + /* Get CDAR field ***************************************************************************************************/ + pNodeConfig->DstAddress = pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET]; + /************************************************************************************** CDAR field value is updated */ + + /* Check if the selected channel is 2D addressing */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + /* Get CTR3 field *************************************************************************************************/ + offset = (uint16_t)(pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] & DMA_CTR3_SAO); + pNodeConfig->RepeatBlockConfig.SrcAddrOffset = (int32_t)offset; + + offset = (uint16_t)((pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] & DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos); + pNodeConfig->RepeatBlockConfig.DestAddrOffset = (int32_t)offset; + + if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_SDEC) != 0U) + { + pNodeConfig->RepeatBlockConfig.SrcAddrOffset *= (-1); + } + + if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_DDEC) != 0U) + { + pNodeConfig->RepeatBlockConfig.DestAddrOffset *= (-1); + } + /************************************************************************************ CTR3 field value is updated */ + + + /* Get CBR2 fields ************************************************************************************************/ + offset = (uint16_t)(pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] & DMA_CBR2_BRSAO); + pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset = (int32_t)offset; + + offset = (uint16_t)((pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] & DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos); + pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset = (int32_t)offset; + + if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRSDEC) != 0U) + { + pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset *= (-1); + } + + if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRDDEC) != 0U) + { + pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset *= (-1); + } + /************************************************************************************ CBR2 field value is updated */ + } + else + { + /* Get CTR3 field *************************************************************************************************/ + pNodeConfig->RepeatBlockConfig.SrcAddrOffset = 0; + pNodeConfig->RepeatBlockConfig.DestAddrOffset = 0; + /************************************************************************************ CTR3 field value is updated */ + + + /* Get CBR2 fields ************************************************************************************************/ + pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset = 0; + pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset = 0; + /************************************************************************************ CBR2 field value is updated */ + } +} + +/** + * @brief Check nodes base addresses compatibility. + * @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations. + * @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations. + * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. + * @retval Return 0 when nodes addresses are compatible, 1 otherwise. + */ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) +static __attribute__((noinline)) uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, \ + DMA_NodeTypeDef const *const pNode2, \ + DMA_NodeTypeDef const *const pNode3) +#else +static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, + DMA_NodeTypeDef const *const pNode2, + DMA_NodeTypeDef const *const pNode3) +#endif /* __GNUC__ && !__CC_ARM */ +{ + uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3) & DMA_CLBAR_LBA); + uint32_t ref = 0U; + + /* Check node 1 address */ + if ((uint32_t)pNode1 != 0U) + { + ref = (uint32_t)pNode1; + } + /* Check node 2 address */ + else if ((uint32_t)pNode2 != 0U) + { + ref = (uint32_t)pNode2; + } + /* Check node 3 address */ + else if ((uint32_t)pNode3 != 0U) + { + ref = (uint32_t)pNode3; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + + /* Check addresses compatibility */ + if (temp != ((uint32_t)ref & DMA_CLBAR_LBA)) + { + return 1U; + } + + return 0U; +} + +/** + * @brief Check nodes types compatibility. + * @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations. + * @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations. + * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. + * @retval Return 0 when nodes types are compatible, otherwise nodes types are not compatible. + */ +static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, + DMA_NodeTypeDef const *const pNode2, + DMA_NodeTypeDef const *const pNode3) +{ + uint32_t ref = 0U; + + /* Check node 1 parameter */ + if (pNode1 != NULL) + { + ref = pNode1->NodeInfo & NODE_TYPE_MASK; + } + /* Check node 2 parameter */ + else if (pNode2 != NULL) + { + ref = pNode2->NodeInfo & NODE_TYPE_MASK; + } + /* Check node 3 parameter */ + else if (pNode3 != NULL) + { + ref = pNode3->NodeInfo & NODE_TYPE_MASK; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + + /* Check node 2 parameter */ + if (pNode2 != NULL) + { + /* Check node type compatibility */ + if (ref != (pNode2->NodeInfo & NODE_TYPE_MASK)) + { + return 2U; + } + } + + /* Check node 3 parameter */ + if (pNode3 != NULL) + { + /* Check node type compatibility */ + if (ref != (pNode3->NodeInfo & NODE_TYPE_MASK)) + { + return 3U; + } + } + + return 0U; +} + +/** + * @brief Check nodes types compatibility. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @param cllr_mask : Pointer to CLLR register mask value. + * @param cllr_offset : Pointer to CLLR register offset value. + * @retval None. + */ +static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode, + uint32_t *const cllr_mask, + uint32_t *const cllr_offset) +{ + /* Check node type */ + if ((pNode->NodeInfo & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + /* Update CLLR register mask value */ + if (cllr_mask != NULL) + { + *cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | + DMA_CLLR_UB2 | DMA_CLLR_ULL; + } + + /* Update CLLR register offset */ + if (cllr_offset != NULL) + { + *cllr_offset = NODE_CLLR_2D_DEFAULT_OFFSET; + } + } + /* Update CLLR and register number for linear addressing node */ + else + { + /* Update CLLR register mask value */ + if (cllr_mask != NULL) + { + *cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_ULL; + } + + /* Update CLLR register offset */ + if (cllr_offset != NULL) + { + *cllr_offset = NODE_CLLR_LINEAR_DEFAULT_OFFSET; + } + } +} + +/** + * @brief Find node in queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers configurations. + * @param NodeInfo : Pointer to a DMA_NodeInQInfoTypeDef structure that contains node linked to queue information. + * @retval Return 0 when node is found in selected queue, otherwise node is not found. + */ +static uint32_t DMA_List_FindNode(DMA_QListTypeDef const *const pQList, + DMA_NodeTypeDef const *const pNode, + DMA_NodeInQInfoTypeDef *const NodeInfo) +{ + uint32_t node_idx = 0U; + uint32_t currentnode_address = 0U; + uint32_t previousnode_address = 0U; + uint32_t cllr_offset = NodeInfo->cllr_offset; + + /* Find last node in queue */ + if (pNode == NULL) + { + /* Check that previous node is linked to the selected queue */ + while (node_idx < pQList->NodeNumber) + { + /* Get head node address */ + if (node_idx == 0U) + { + currentnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA; + } + /* Calculate nodes addresses */ + else + { + previousnode_address = currentnode_address; + currentnode_address = + ((DMA_NodeTypeDef *)(currentnode_address + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA; + } + + /* Increment node index */ + node_idx++; + } + } + /* Find selected node node in queue */ + else + { + /* Check that previous node is linked to the selected queue */ + while ((node_idx < pQList->NodeNumber) && (currentnode_address != ((uint32_t)pNode & DMA_CLLR_LA))) + { + /* Get head node address */ + if (node_idx == 0U) + { + currentnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA; + } + /* Calculate nodes addresses */ + else + { + previousnode_address = currentnode_address; + currentnode_address = + ((DMA_NodeTypeDef *)(currentnode_address + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA; + } + + /* Increment node index */ + node_idx++; + } + } + + /* Check stored address */ + if (pNode != NULL) + { + if (currentnode_address != ((uint32_t)pNode & DMA_CLLR_LA)) + { + return 1U; + } + } + + /* Update current node position */ + NodeInfo->currentnode_pos = node_idx; + + /* Update previous node address */ + NodeInfo->previousnode_addr = previousnode_address | ((uint32_t)pQList->Head & DMA_CLBAR_LBA); + + /* Update current node address */ + NodeInfo->currentnode_addr = currentnode_address | ((uint32_t)pQList->Head & DMA_CLBAR_LBA); + + /* Update next node address */ + if (((DMA_NodeTypeDef *)NodeInfo->currentnode_addr)->LinkRegisters[cllr_offset] != 0U) + { + NodeInfo->nextnode_addr = (((DMA_NodeTypeDef *)NodeInfo->currentnode_addr)->LinkRegisters[cllr_offset] & + DMA_CLLR_LA) | ((uint32_t)pQList->Head & DMA_CLBAR_LBA); + } + + return 0U; +} + +/** + * @brief Reset queue nodes. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param NodeInfo : Pointer to a DMA_NodeInQInfoTypeDef structure that contains node linked to queue information. + * @retval None. + */ +static void DMA_List_ResetQueueNodes(DMA_QListTypeDef const *const pQList, + DMA_NodeInQInfoTypeDef const *const NodeInfo) +{ + uint32_t node_idx = 0U; + uint32_t currentnode_address = 0U; + uint32_t previousnode_address; + uint32_t cllr_offset = NodeInfo->cllr_offset; + + /* Check that previous node is linked to the selected queue */ + while (node_idx < pQList->NodeNumber) + { + /* Get head node address */ + if (node_idx == 0U) + { + previousnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA; + currentnode_address = (pQList->Head->LinkRegisters[cllr_offset] & DMA_CLLR_LA); + } + /* Calculate nodes addresses */ + else + { + previousnode_address = currentnode_address; + currentnode_address = + ((DMA_NodeTypeDef *)(currentnode_address + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA; + } + + /* Reset node */ + ((DMA_NodeTypeDef *)(previousnode_address + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] = 0U; + + /* Increment node index */ + node_idx++; + } +} + +/** + * @brief Fill source node registers values by destination nodes registers values. + * @param pSrcNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list source node registers + * configurations. + * @param pDestNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list destination node registers + * configurations. + * @retval None. + */ +static void DMA_List_FillNode(DMA_NodeTypeDef const *const pSrcNode, + DMA_NodeTypeDef *const pDestNode) +{ + /* Repeat for all register nodes */ + for (uint32_t reg_idx = 0U; reg_idx < NODE_MAXIMUM_SIZE; reg_idx++) + { + pDestNode->LinkRegisters[reg_idx] = pSrcNode->LinkRegisters[reg_idx]; + } + + /* Fill node information */ + pDestNode->NodeInfo = pSrcNode->NodeInfo; +} + +/** + * @brief Convert node to dynamic. + * @param ContextNodeAddr : The context node address. + * @param CurrentNodeAddr : The current node address to be converted. + * @param RegisterNumber : The register number to be converted. + * @retval None. + */ +static void DMA_List_ConvertNodeToDynamic(uint32_t ContextNodeAddr, + uint32_t CurrentNodeAddr, + uint32_t RegisterNumber) +{ + uint32_t currentnode_reg_counter = 0U; + uint32_t contextnode_reg_counter = 0U; + uint32_t cllr_idx = RegisterNumber - 1U; + DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; + DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr; + uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, + DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL + }; + + /* Update ULL position according to register number */ + update_link[cllr_idx] = update_link[NODE_MAXIMUM_SIZE - 1U]; + + /* Repeat for all node registers */ + while (contextnode_reg_counter != RegisterNumber) + { + /* Check if register values are equal (exception for CSAR, CDAR and CLLR registers) */ + if ((context_node->LinkRegisters[contextnode_reg_counter] == + current_node->LinkRegisters[currentnode_reg_counter]) && + (contextnode_reg_counter != NODE_CSAR_DEFAULT_OFFSET) && + (contextnode_reg_counter != NODE_CDAR_DEFAULT_OFFSET) && + (contextnode_reg_counter != (RegisterNumber - 1U))) + { + /* Format the node according to unused registers */ + DMA_List_FormatNode(current_node, currentnode_reg_counter, RegisterNumber, NODE_DYNAMIC_FORMAT); + + /* Update CLLR index */ + cllr_idx --; + + /* Update CLLR fields */ + current_node->LinkRegisters[cllr_idx] &= ~update_link[contextnode_reg_counter]; + } + else + { + /* Update context node register fields with new values */ + context_node->LinkRegisters[contextnode_reg_counter] = current_node->LinkRegisters[currentnode_reg_counter]; + + /* Update CLLR fields */ + current_node->LinkRegisters[cllr_idx] |= update_link[contextnode_reg_counter]; + + /* Increment current node number register counter */ + currentnode_reg_counter++; + } + + /* Increment context node number register counter */ + contextnode_reg_counter++; + } + + /* Update node information */ + MODIFY_REG(current_node->NodeInfo, NODE_CLLR_IDX, ((currentnode_reg_counter - 1U) << NODE_CLLR_IDX_POS)); + + /* Clear unused node fields */ + DMA_List_ClearUnusedFields(current_node, currentnode_reg_counter); +} + +/** + * @brief Convert node to static. + * @param ContextNodeAddr : The context node address. + * @param CurrentNodeAddr : The current node address to be converted. + * @param RegisterNumber : The register number to be converted. + * @retval None. + */ +static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr, + uint32_t CurrentNodeAddr, + uint32_t RegisterNumber) +{ + uint32_t contextnode_reg_counter = 0U; + uint32_t cllr_idx; + uint32_t cllr_mask; + const DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; + DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr; + uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, + DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL + }; + + /* Update ULL position according to register number */ + update_link[RegisterNumber - 1U] = update_link[NODE_MAXIMUM_SIZE - 1U]; + + /* Get context node CLLR information */ + cllr_idx = (context_node->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + cllr_mask = context_node->LinkRegisters[cllr_idx]; + + /* Repeat for all node registers */ + while (contextnode_reg_counter != RegisterNumber) + { + /* Check if node field is dynamic */ + if ((cllr_mask & update_link[contextnode_reg_counter]) == 0U) + { + /* Format the node according to unused registers */ + DMA_List_FormatNode(current_node, contextnode_reg_counter, RegisterNumber, NODE_STATIC_FORMAT); + + /* Update node field */ + current_node->LinkRegisters[contextnode_reg_counter] = context_node->LinkRegisters[contextnode_reg_counter]; + } + + /* Increment context node number register counter */ + contextnode_reg_counter++; + } + + /* Update node information */ + MODIFY_REG(current_node->NodeInfo, NODE_CLLR_IDX, ((RegisterNumber - 1U) << NODE_CLLR_IDX_POS)); +} + +/** + * @brief Format the node according to unused registers. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @param RegisterIdx : The first register index to be formatted. + * @param RegisterNumber : The number of node registers. + * @param Format : The format type. + * @retval None. + */ +static void DMA_List_FormatNode(DMA_NodeTypeDef *const pNode, + uint32_t RegisterIdx, + uint32_t RegisterNumber, + uint32_t Format) +{ + if (Format == NODE_DYNAMIC_FORMAT) + { + /* Repeat for all registers to be formatted */ + for (uint32_t reg_idx = RegisterIdx; reg_idx < (RegisterNumber - 1U); reg_idx++) + { + pNode->LinkRegisters[reg_idx] = pNode->LinkRegisters[reg_idx + 1U]; + } + } + else + { + /* Repeat for all registers to be formatted */ + for (uint32_t reg_idx = (RegisterNumber - 2U); reg_idx > RegisterIdx; reg_idx--) + { + pNode->LinkRegisters[reg_idx] = pNode->LinkRegisters[reg_idx - 1U]; + } + } +} + +/** + * @brief Clear unused register fields. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @param FirstUnusedField : The first unused field to be cleared. + * @retval None. + */ +static void DMA_List_ClearUnusedFields(DMA_NodeTypeDef *const pNode, + uint32_t FirstUnusedField) +{ + /* Repeat for all unused fields */ + for (uint32_t reg_idx = FirstUnusedField; reg_idx < NODE_MAXIMUM_SIZE; reg_idx++) + { + pNode->LinkRegisters[reg_idx] = 0U; + } +} + +/** + * @brief Update CLLR for all dynamic queue nodes. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param LastNode_IsCircular : The first circular node is the last queue node or not. + * @retval None. + */ +static void DMA_List_UpdateDynamicQueueNodesCLLR(DMA_QListTypeDef const *const pQList, + uint32_t LastNode_IsCircular) +{ + uint32_t previous_cllr_offset; + uint32_t current_cllr_offset = 0U; + uint32_t previousnode_addr; + uint32_t currentnode_addr = (uint32_t)pQList->Head; + uint32_t cllr_mask; + uint32_t node_idx = 0U; + + /* Repeat for all register nodes */ + while (node_idx < pQList->NodeNumber) + { + /* Get head node address */ + if (node_idx == 0U) + { + /* Get current node information */ + current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + } + /* Calculate nodes addresses */ + else + { + /* Get previous node information */ + previousnode_addr = currentnode_addr; + previous_cllr_offset = current_cllr_offset; + + /* Get current node information */ + currentnode_addr = (((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] & DMA_CLLR_LA) + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA); + current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + + /* Calculate CLLR register value to be updated */ + cllr_mask = (((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] & ~DMA_CLLR_LA) | + (((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] & DMA_CLLR_LA); + + /* Set new CLLR value to previous node */ + ((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] = cllr_mask; + } + + /* Increment node index */ + node_idx++; + } + + /* Check queue circularity */ + if (pQList->FirstCircularNode != 0U) + { + /* First circular queue is not last queue node */ + if (LastNode_IsCircular == 0U) + { + /* Get CLLR node information */ + DMA_List_GetCLLRNodeInfo(((DMA_NodeTypeDef *)currentnode_addr), &cllr_mask, NULL); + + /* Update CLLR register for last circular node */ + ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] = + ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; + } + /* First circular queue is last queue node */ + else + { + /* Disable CLLR updating */ + ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] &= ~DMA_CLLR_ULL; + } + } + else + { + /* Clear CLLR register for last node */ + ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] = 0U; + } +} + +/** + * @brief Update CLLR for all static queue nodes. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param operation : The operation type. + * @retval None. + */ +static void DMA_List_UpdateStaticQueueNodesCLLR(DMA_QListTypeDef const *const pQList, + uint32_t operation) +{ + uint32_t currentnode_addr = (uint32_t)pQList->Head; + uint32_t current_cllr_offset = ((uint32_t)pQList->Head->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + uint32_t cllr_default_offset; + uint32_t cllr_default_mask; + uint32_t cllr_mask; + uint32_t node_idx = 0U; + + /* Get CLLR node information */ + DMA_List_GetCLLRNodeInfo(pQList->Head, &cllr_default_mask, &cllr_default_offset); + + /* Repeat for all register nodes (Bypass last queue node) */ + while (node_idx < pQList->NodeNumber) + { + if (operation == UPDATE_CLLR_POSITION) + { + /* Get CLLR value */ + cllr_mask = ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset]; + } + else + { + /* Calculate CLLR value */ + cllr_mask = (((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] & DMA_CLLR_LA) | + cllr_default_mask; + } + + /* Set new CLLR value to default position */ + if ((node_idx == (pQList->NodeNumber - 1U)) && (pQList->FirstCircularNode == NULL)) + { + ((DMA_NodeTypeDef *)(currentnode_addr))->LinkRegisters[cllr_default_offset] = 0U; + } + else + { + ((DMA_NodeTypeDef *)(currentnode_addr))->LinkRegisters[cllr_default_offset] = cllr_mask; + } + + /* Update current node address with next node address */ + currentnode_addr = (currentnode_addr & DMA_CLBAR_LBA) | (cllr_mask & DMA_CLLR_LA); + + /* Update current CLLR offset with next CLLR offset */ + current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + + /* Increment node index */ + node_idx++; + } +} + +/** + * @brief Clean linked-list queue variable. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval None. + */ +static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList) +{ + /* Clear head node */ + pQList->Head = NULL; + + /* Clear first circular queue node */ + pQList->FirstCircularNode = NULL; + + /* Reset node number */ + pQList->NodeNumber = 0U; + + /* Reset queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_RESET; + + /* Reset queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Reset queue type */ + pQList->Type = QUEUE_TYPE_STATIC; +} +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_exti.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_exti.c new file mode 100644 index 000000000..65d95190e --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_exti.c @@ -0,0 +1,845 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two diffenrents + interrupt pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +#define EXTI_MODE_OFFSET 0x04U /* byte offset between IMR/EMR registers */ +#define EXTI_CONFIG_OFFSET 0x08U /* byte offset between Rising/Falling configuration registers */ +#define EXTI_PRIVCFGR_OFFSET 0x04U /* byte offset between PRIVCFGR1/PRIVCFGR2 registers */ +#define EXTI_SECCFGR_OFFSET 0x04U /* byte offset between SECCFGR1/SECCFGR2 registers */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0U) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store rising trigger mode */ + *regaddr = regval; + + /* Configure falling trigger */ + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store falling trigger mode */ + *regaddr = regval; + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL]; + regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store interrupt mode */ + *regaddr = regval; + + /* Configure event mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store event mode */ + *regaddr = regval; + + return HAL_OK; +} + + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + const __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configiguration structure */ + pExtiConfig->Line = hexti->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* 1] Get core mode : interrupt */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0U) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0U) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0U) + { + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0U) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + + /* Get falling configuration */ + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0U) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL]; + pExtiConfig->GPIOSel = (regval >> (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))) & EXTI_EXTICR1_EXTI0; + } + } + + return HAL_OK; +} + + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* 1] Clear interrupt mode */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 2] Clear event mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0U) + { + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL]; + regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + } + } + + return HAL_OK; +} + + +/** + * @brief Register callback for a dedicaated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, + void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->RisingCallback = pPendingCbfn; + hexti->FallingCallback = pPendingCbfn; + break; + + case HAL_EXTI_RISING_CB_ID: + hexti->RisingCallback = pPendingCbfn; + break; + + case HAL_EXTI_FALLING_CB_ID: + hexti->FallingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t maskline; + uint32_t offset; + + /* Compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get rising edge pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & maskline); + + if (regval != 0U) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call rising callback */ + if (hexti->RisingCallback != NULL) + { + hexti->RisingCallback(); + } + } + + /* Get falling edge pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & maskline); + + if (regval != 0U) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call rising callback */ + if (hexti->FallingCallback != NULL) + { + hexti->FallingCallback(); + } + } +} + + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING + * @arg @ref EXTI_TRIGGER_FALLING + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + const __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + if (Edge != EXTI_TRIGGER_RISING) + { + /* Get falling edge pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + else + { + /* Get rising edge pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + + /* return 1 if bit is set else 0 */ + regval = ((*regaddr & maskline) >> linepos); + return regval; +} + + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING + * @arg @ref EXTI_TRIGGER_FALLING + * @retval None. + */ +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + + if (Edge != EXTI_TRIGGER_RISING) + { + /* Get falling edge pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + else + { + /* Get falling edge pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + + /* Clear Pending bit */ + *regaddr = maskline; +} + + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + + regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset)); + *regaddr = maskline; +} + + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group3 EXTI line attributes management functions + * @brief EXTI attributes management functions. + * +@verbatim + =============================================================================== + ##### EXTI attributes functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configure the EXTI line attribute(s). + * @note Available attributes are to secure EXTI line and set EXT line as privileged. + * Default state is not secure and unprivileged access allowed. + * @note Secure and non-secure attributes can only be set from the secure + * state when the system implements the security (TZEN=1). + * @note Security and privilege attributes can be set independently. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @param LineAttributes can be one or a combination of the following values: + * @arg @ref EXTI_LINE_PRIV Privileged-only access + * @arg @ref EXTI_LINE_NPRIV Privileged/Non-privileged access + * @arg @ref EXTI_LINE_SEC Secure-only access + * @arg @ref EXTI_LINE_NSEC Secure/Non-secure access + * @retval None + */ +void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + assert_param(IS_EXTI_LINE_ATTRIBUTES(LineAttributes)); + + /* compute line register offset and line mask */ + offset = ((ExtiLine & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (ExtiLine & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* Configure privilege or non-privilege attributes */ + regaddr = (__IO uint32_t *)(&EXTI->PRIVCFGR1 + (EXTI_PRIVCFGR_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((LineAttributes & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) + { + regval |= maskline; + } + else if ((LineAttributes & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV) + { + regval &= ~maskline; + } + else + { + /* do nothing */ + } + + /* Store privilege or non-privilege attribute */ + *regaddr = regval; + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + + /* Configure secure or non-secure attributes */ + regaddr = (__IO uint32_t *)(&EXTI->SECCFGR1 + (EXTI_SECCFGR_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((LineAttributes & EXTI_LINE_SEC) == EXTI_LINE_SEC) + { + regval |= maskline; + } + else if ((LineAttributes & EXTI_LINE_NSEC) == EXTI_LINE_NSEC) + { + regval &= ~maskline; + } + else + { + /* do nothing */ + } + + /* Store secure or non-secure attribute */ + *regaddr = regval; + +#endif /* __ARM_FEATURE_CMSE */ +} + +/** + * @brief Get the EXTI line attribute(s). + * @note Secure and non-secure attributes are only available from secure state + * when the system implements the security (TZEN=1) + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @param pLineAttributes: pointer to return line attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes) +{ + const __IO uint32_t *regaddr; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + uint32_t attributes; + + /* Check null pointer */ + if (pLineAttributes == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Compute line register offset and line mask */ + offset = ((ExtiLine & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (ExtiLine & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* Get privilege or non-privilege attribute */ + regaddr = (__IO uint32_t *)(&EXTI->PRIVCFGR1 + (EXTI_PRIVCFGR_OFFSET * offset)); + + if ((*regaddr & maskline) != 0U) + { + attributes = EXTI_LINE_PRIV; + } + else + { + attributes = EXTI_LINE_NPRIV; + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + + /* Get secure or non-secure attribute */ + regaddr = (__IO uint32_t *)(&EXTI->SECCFGR1 + (EXTI_SECCFGR_OFFSET * offset)); + + if ((*regaddr & maskline) != 0U) + { + attributes |= EXTI_LINE_SEC; + } + else + { + attributes |= EXTI_LINE_NSEC; + } + +#endif /* __ARM_FEATURE_CMSE */ + + /* return value */ + *pLineAttributes = attributes; + + return HAL_OK; +} +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the secure and privilege configuration registers. + * @retval None + */ +void HAL_EXTI_LockAttributes(void) +{ + SET_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); +} + +/** + * @brief Return the secure and privilege configuration registers LOCK status + * @retval 1 if the secure and privilege configuration registers have been locked else 0. + */ +uint32_t HAL_EXTI_GetLockAttributes(void) +{ + return READ_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash.c new file mode 100644 index 000000000..c2210e222 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash.c @@ -0,0 +1,774 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + + [..] The Flash memory interface manages CPU AHB C-Bus accesses to the Flash memory. + It implements the erase and program Flash memory operations and the read + and write protection mechanisms. + + [..] The Flash memory interface implements the TrustZone security features (TZ) supported + by ARM Cortex-M33 core (CM33). + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Option bytes programming + (+) TrustZone aware + (+) Watermark-based area protection including the secure hide area + (+) Block-based page protection + (+) Error code correction (ECC) : Data in flash are 137-bits word + (9 bits added per quad-word) + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32U5xx devices. + + (#) Flash Memory IO Programming functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Program functions: quad-words and burst program (8 quad-words) + (++) There are two modes of programming : + (+++) Polling mode using HAL_FLASH_Program() function + (+++) Interrupt mode using HAL_FLASH_Program_IT() function + + (#) Interrupts and flags management functions : + (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() + (++) Callback functions are called when the flash operations are finished : + HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise + HAL_FLASH_OperationErrorCallback() + (++) Get error flag status by calling HAL_GetError() + + (#) Option bytes management functions : + (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and + HAL_FLASH_OB_Lock() functions + (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function. + In this case, a reset is generated + + [..] + In addition to these functions, this driver includes a set of macros allowing + to handle the following operations: + (+) Set the latency + (+) Enable/Disable the Flash power-down during low-power run and sleep modes + (+) Enable/Disable the Flash interrupts + (+) Monitor the Flash flags status + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +/** + * @brief Variable used for Program/Erase sectors under interruption + */ +FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \ + .ErrorCode = HAL_FLASH_ERROR_NONE, \ + .ProcedureOnGoing = 0U, \ + .Address = 0U, \ + .Bank = FLASH_BANK_1, \ + .Page = 0U, \ + .NbPagesToErase = 0U + }; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +static void FLASH_Program_QuadWord(uint32_t Address, uint32_t DataAddress); +static void FLASH_Program_Burst(uint32_t Address, uint32_t DataAddress); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim + =============================================================================== + ##### Programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FLASH + program operations. + +@endverbatim + * @{ + */ + +/** + * @brief Program a quad-word or a burst of 8 quad-words at a specified address. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address specifies the address to be programmed. + * This parameter shall be aligned to the Flash word (128 bits) + * @param DataAddress specifies the address of data to be programmed. + * This parameter shall be 32-bit aligned + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress) +{ + HAL_StatusTypeDef status; + __IO uint32_t *reg_cr; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Set current operation type */ + pFlash.ProcedureOnGoing = TypeProgram; + + /* Access to SECCR or NSCR depends on operation type */ + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); + + if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_QUADWORD) + { + /* Program a quad-word (128-bit) at a specified address */ + FLASH_Program_QuadWord(Address, DataAddress); + } + else + { + /* Program a burst of 8 quad-words at a specified address */ + FLASH_Program_Burst(Address, DataAddress); + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG (and BWR Bit in Burst programming mode) */ + CLEAR_BIT((*reg_cr), (TypeProgram & ~(FLASH_NON_SECURE_MASK))); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + /* return status */ + return status; +} + +/** + * @brief Program a quad-word or a burst of 8 quad-words at a specified address with interrupt enabled. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address specifies the address to be programmed. + * This parameter shall be aligned to the Flash word (128 bits) + * @param DataAddress specifies the address of data to be programmed. + * This parameter shall be 32-bit aligned + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress) +{ + HAL_StatusTypeDef status; + __IO uint32_t *reg_cr; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = TypeProgram; + pFlash.Address = Address; + + /* Access to SECCR or NSCR depends on operation type */ + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); + + /* Enable End of Operation and Error interrupts */ + (*reg_cr) |= (FLASH_IT_EOP | FLASH_IT_OPERR); + + if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_QUADWORD) + { + /* Program a quad-word (128-bit) at a specified address */ + FLASH_Program_QuadWord(Address, DataAddress); + } + else + { + /* Program a burst of 8 quad-words at a specified address */ + FLASH_Program_Burst(Address, DataAddress); + } + } + + return status; +} + +/** + * @brief Handle FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t param = 0U; + uint32_t error; + __IO uint32_t *reg_cr; + __IO uint32_t *reg_sr; + + /* Access to CR and SR registers depends on operation type */ + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); + reg_sr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECSR) : &(FLASH_NS->NSSR); + + /* Save Flash errors */ + error = (*reg_sr) & FLASH_FLAG_SR_ERRORS; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + error |= (FLASH->NSSR & FLASH_FLAG_OPTWERR); +#endif /* __ARM_FEATURE_CMSE */ + + /* Set parameter of the callback */ + if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_PAGES) + { + param = pFlash.Page; + } + else if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE) + { + param = pFlash.Bank; + } + else if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_QUADWORD) + { + param = pFlash.Address; + } + else if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_BURST) + { + param = pFlash.Address; + } + else + { + /* Empty statement (to be compliant MISRA 15.7) */ + } + + /* Clear operation bit on the on-going procedure */ + CLEAR_BIT((*reg_cr), (pFlash.ProcedureOnGoing & ~(FLASH_NON_SECURE_MASK))); + + /* Check FLASH operation error flags */ + if (error != 0U) + { + /* Save the error code */ + pFlash.ErrorCode |= error; + + /* Clear error programming flags */ + (*reg_sr) = error; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if ((error & FLASH_FLAG_OPTWERR) != 0U) + { + FLASH->NSSR = FLASH_FLAG_OPTWERR; + } +#endif /* __ARM_FEATURE_CMSE */ + + /* Stop the procedure ongoing */ + pFlash.ProcedureOnGoing = 0U; + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(param); + } + + /* Check FLASH End of Operation flag */ + if (((*reg_sr) & FLASH_FLAG_EOP) != 0U) + { + /* Clear FLASH End of Operation pending bit */ + (*reg_sr) = FLASH_FLAG_EOP; + + if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_PAGES) + { + /* Nb of pages to erase can be decreased */ + pFlash.NbPagesToErase--; + + /* Check if there are still pages to erase */ + if (pFlash.NbPagesToErase != 0U) + { + /* Increment page number */ + pFlash.Page++; + FLASH_PageErase(pFlash.Page, pFlash.Bank); + } + else + { + /* No more pages to Erase */ + pFlash.ProcedureOnGoing = 0U; + param = 0xFFFFFFFFU; + } + } + else + { + /*Clear the procedure ongoing*/ + pFlash.ProcedureOnGoing = 0U; + } + + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(param); + } + + if (pFlash.ProcedureOnGoing == 0U) + { + /* Disable End of Operation and Error interrupts */ + (*reg_cr) &= ~(FLASH_IT_EOP | FLASH_IT_OPERR); + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } +} + +/** + * @brief FLASH end of operation interrupt callback. + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: Bank number which has been requested to erase + * Page Erase: Page which has been erased + * (if 0xFFFFFFFF, it means that all the selected pages have been erased) + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback. + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: Bank number which has been requested to erase + * Page Erase: Page number which returned an error + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief Management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (READ_BIT(FLASH->NSCR, FLASH_NSCR_LOCK) != 0U) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->NSKEYR, FLASH_KEY1); + WRITE_REG(FLASH->NSKEYR, FLASH_KEY2); + + /* verify Flash is unlocked */ + if (READ_BIT(FLASH->NSCR, FLASH_NSCR_LOCK) != 0U) + { + status = HAL_ERROR; + } + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (status == HAL_OK) + { + if (READ_BIT(FLASH->SECCR, FLASH_SECCR_LOCK) != 0U) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->SECKEYR, FLASH_KEY1); + WRITE_REG(FLASH->SECKEYR, FLASH_KEY2); + + /* verify Flash is unlocked */ + if (READ_BIT(FLASH->SECCR, FLASH_SECCR_LOCK) != 0U) + { + status = HAL_ERROR; + } + } + } +#endif /* __ARM_FEATURE_CMSE */ + + return status; +} + +/** + * @brief Lock the FLASH control register access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Set the LOCK Bit to lock the FLASH Registers access */ + SET_BIT(FLASH->NSCR, FLASH_NSCR_LOCK); + + /* verify Flash is locked */ + if (READ_BIT(FLASH->NSCR, FLASH_NSCR_LOCK) != 0U) + { + status = HAL_OK; + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (status == HAL_OK) + { + SET_BIT(FLASH->SECCR, FLASH_SECCR_LOCK); + + /* verify Flash is locked */ + if (READ_BIT(FLASH->SECCR, FLASH_SECCR_LOCK) != 0U) + { + status = HAL_OK; + } + } +#endif /* __ARM_FEATURE_CMSE */ + + return status; +} + +/** + * @brief Unlock the FLASH Option Bytes Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if (READ_BIT(FLASH->NSCR, FLASH_NSCR_OPTLOCK) != 0U) + { + /* Authorizes the Option Byte register programming */ + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + + /* Verify that the Option Bytes are unlocked */ + if (READ_BIT(FLASH->NSCR, FLASH_NSCR_OPTLOCK) != 0U) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Bytes Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + SET_BIT(FLASH->NSCR, FLASH_NSCR_OPTLOCK); + + /* Verify that the Option Bytes are locked */ + if (READ_BIT(FLASH->NSCR, FLASH_NSCR_OPTLOCK) != 0U) + { + return HAL_OK; + } + + return HAL_ERROR; +} + +/** + * @brief Launch the option byte loading. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + /* Set the bit to force the option byte reloading */ + SET_BIT(FLASH->NSCR, FLASH_NSCR_OBL_LAUNCH); + + /* We should not reach here : Option byte launch generates Option byte reset + so return error */ + return HAL_ERROR; +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time Errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode The returned value can be: + * @arg HAL_FLASH_ERROR_NONE: No error set + * @arg HAL_FLASH_ERROR_OP: FLASH Operation error + * @arg HAL_FLASH_ERROR_PROG: FLASH Programming error + * @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error + * @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error + * @arg HAL_FLASH_ERROR_SIZ: FLASH Size error + * @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error + * @arg HAL_FLASH_ERROR_OPTW: FLASH Option modification error + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + /* Wait for the FLASH operation to complete by polling on BUSY and WDW flags to be reset. + Even if the FLASH operation fails, the BUSY & WDW flags will be reset, and an error flag will be set */ + + uint32_t tickstart = HAL_GetTick(); + uint32_t error; + __IO uint32_t *reg_sr; + + /* Access to SECSR or NSSR registers depends on operation type */ + reg_sr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECSR) : &(FLASH_NS->NSSR); + + while (((*reg_sr) & (FLASH_FLAG_BSY | FLASH_FLAG_WDW)) != 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH operation error flags */ + error = ((*reg_sr) & FLASH_FLAG_SR_ERRORS); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + error |= (FLASH->NSSR & FLASH_FLAG_OPTWERR); +#endif /* __ARM_FEATURE_CMSE */ + + if (error != 0U) + { + /*Save the error code*/ + pFlash.ErrorCode |= error; + + /* Clear error programming flags */ + (*reg_sr) = error; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if ((error & FLASH_FLAG_OPTWERR) != 0U) + { + FLASH->NSSR = FLASH_FLAG_OPTWERR; + } +#endif /* __ARM_FEATURE_CMSE */ + + return HAL_ERROR; + } + + /* Check FLASH End of Operation flag */ + if (((*reg_sr) & FLASH_FLAG_EOP) != 0U) + { + /* Clear FLASH End of Operation pending bit */ + (*reg_sr) = FLASH_FLAG_EOP; + } + + /* If there is no error flag set */ + return HAL_OK; +} + +/** + * @brief Program a quad-word (128-bit) at a specified address. + * @param Address specifies the address to be programmed. + * @param DataAddress specifies the address of data to be programmed. + * @retval None + */ +static void FLASH_Program_QuadWord(uint32_t Address, uint32_t DataAddress) +{ + uint8_t index = 4; + uint32_t *dest_addr = (uint32_t *)Address; + uint32_t *src_addr = (uint32_t *)DataAddress; + uint32_t primask_bit; + __IO uint32_t *reg_cr; + + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Access to SECCR or NSCR registers depends on operation type */ + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); + + /* Set PG bit */ + SET_BIT((*reg_cr), FLASH_NSCR_PG); + + /* Enter critical section: Disable interrupts to avoid any interruption during the loop */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Program the quad-word */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + index--; + } while (index != 0U); + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} + +/** + * @brief Program a burst of 8x quad-words at a specified address. + * @param Address: specifies the address to be programmed. + * @param DataAddress: specifies the address where the data are stored. + * @retval None + */ +static void FLASH_Program_Burst(uint32_t Address, uint32_t DataAddress) +{ + uint8_t burst_index = FLASH_NB_WORDS_IN_BURST; + uint32_t *dest_addr = (uint32_t *)Address; + uint32_t *src_addr = (uint32_t *)DataAddress; + uint32_t primask_bit; + __IO uint32_t *reg_cr; + + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address)); + + /* Access to SECCR or NSCR registers depends on operation type */ + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); + + /* Set PG and BWR bits */ + SET_BIT((*reg_cr), (FLASH_NSCR_PG | FLASH_NSCR_BWR)); + + /* Enter critical section: Disable interrupts to avoid any interruption during the loop */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Program the burst */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + burst_index--; + } while (burst_index != 0U); + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash_ex.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash_ex.c new file mode 100644 index 000000000..df267a706 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash_ex.c @@ -0,0 +1,1698 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the FLASH extended peripheral: + * + Extended programming operations functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### Flash Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the FLASH interface for STM32U5xx + devices contains the following additional features + + (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write + capability (RWW) + (+) Dual bank memory organization + (+) Watermark-based secure area including the secure hide areas + (+) Block-based secure pages + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32U5xx devices. It includes: + (#) Flash Memory Erase functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Erase function: page Erase and Bank/Mass Erase + (++) There are two modes of erase : + (+++) Polling Mode using HAL_FLASHEx_Erase() + (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() + + (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to: + (++) Configure the write protection for each area + (++) Set the Read protection Level + (++) Program the user Option Bytes + (++) Configure the watermark security for each area including the secure hide areas + (++) Configure the boot lock (BOOT_LOCK) + (++) Configure the Boot addresses + + (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to: + (++) Get the value of a write protection area + (++) Know if the read protection is activated + (++) Get the value of the user Option Bytes + (++) Get the configuration of a watermark security area including the secure hide areas + (++) Get the boot lock (BOOT_LOCK) configuration + (++) Get the value of a boot address + + (#) Block-based secure / privilege area configuration function: Use HAL_FLASHEx_ConfigBBAttributes() + (++) Bit-field allowing to secure or un-secure each page + (++) Bit-field allowing to privilege or un-privilege each page + + (#) Get the block-based secure / privilege area configuration function: Use HAL_FLASHEx_GetBBSec() + (++) Return the configuration of the block-based security and privilege for all the pages + + (#) Activation of the secure hide area function: Use HAL_FLASHEx_EnableSecHideProtection() + (++) Deny the access to the secure hide area + + (#) Privilege mode configuration function: Use HAL_FLASHEx_ConfigPrivMode() + (++) FLASH register can be protected against non-privilege accesses + + (#) Get the privilege mode configuration function: Use HAL_FLASHEx_GetPrivMode() + (++) Return if the FLASH registers are protected against non-privilege accesses + + (#) Security inversion configuration function: Use HAL_FLASHEx_ConfigSecInversion() + (++) FLASH secure state can be override + + (#) Get the security inversion configuration function: Use HAL_FLASHEx_GetSecInversion() + (++) Return if FLASH secure state is override + + (#) Enable bank low-power mode function: Use HAL_FLASHEx_EnablePowerDown() + (++) Enable low-power mode for Flash Bank 1 and/or Bank 2 + + (#) Enable low-power read mode function: Use HAL_FLASHEx_ConfigLowPowerRead() + (++) Enable low-power read mode for Flash memory + + (#) Get the low-power read mode configuration function: Use HAL_FLASHEx_GetLowPowerRead() + (++) Return if FLASH is in low-power read mode or normal read mode + + (#) Get Flash operation function: Use HAL_FLASHEx_GetOperation() + (++) Return information about the on-going Flash operation. After a + system reset, return information about the interrupted Flash operation, if any. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH Extended HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +static void FLASH_MassErase(uint32_t Banks); +static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRPEndOffset, + FunctionalState WRPLock); +static void FLASH_OB_RDPConfig(uint32_t RDPLevel); +static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +static void FLASH_OB_WMSECConfig(uint32_t WMSecConfig, uint32_t WMSecStartPage, uint32_t WMSecEndPage, + uint32_t WMHDPEndPage); +static void FLASH_OB_BootLockConfig(uint32_t BootLockConfig); +#endif /* __ARM_FEATURE_CMSE */ +static void FLASH_OB_BootAddrConfig(uint32_t BootAddrConfig, uint32_t BootAddr); +static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRPEndOffset, + FunctionalState *WRPLock); +static uint32_t FLASH_OB_GetRDP(void); +static uint32_t FLASH_OB_GetUser(void); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +static void FLASH_OB_GetWMSEC(uint32_t *WMSecConfig, uint32_t *WMSecStartPage, uint32_t *WMSecEndPage, + uint32_t *WMHDPEndPage); +static uint32_t FLASH_OB_GetBootLock(void); +#endif /* __ARM_FEATURE_CMSE */ +static void FLASH_OB_GetBootAddr(uint32_t BootAddrConfig, uint32_t *BootAddr); +static void FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType, uint32_t RDPKey1, uint32_t RDPKey2); +/** + * @} + */ + +/* Exported functions -------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions + * @brief Extended IO operation functions + * +@verbatim + =============================================================================== + ##### Extended programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extended FLASH + programming operations Operations. + +@endverbatim + * @{ + */ +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages. + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] PageError pointer to variable that contains the configuration + * information on faulty page in case of error (0xFFFFFFFF means that all + * the pages have been correctly erased). + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) +{ + HAL_StatusTypeDef status; + uint32_t page_index; + __IO uint32_t *reg_cr; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Current operation type */ + pFlash.ProcedureOnGoing = pEraseInit->TypeErase; + + /* Access to SECCR or NSCR depends on operation type */ + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH->NSCR); + + if ((pEraseInit->TypeErase & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE) + { + /* Mass erase to be done */ + FLASH_MassErase(pEraseInit->Banks); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + else + { + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFFU; + + for (page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++) + { + FLASH_PageErase(page_index, pEraseInit->Banks); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty page */ + *PageError = page_index; + break; + } + } + } + + /* If the erase operation is completed, disable the associated bits */ + CLEAR_BIT((*reg_cr), (pEraseInit->TypeErase) & (~(FLASH_NON_SECURE_MASK))); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled. + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status; + __IO uint32_t *reg_cr; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = pEraseInit->TypeErase; + pFlash.Bank = pEraseInit->Banks; + + /* Access to SECCR or NSCR depends on operation type */ + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH->NSCR); + + /* Enable End of Operation and Error interrupts */ + (*reg_cr) |= (FLASH_IT_EOP | FLASH_IT_OPERR); + + if ((pEraseInit->TypeErase & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE) + { + /* Mass erase to be done */ + FLASH_MassErase(pEraseInit->Banks); + } + else + { + /* Erase by page to be done */ + pFlash.NbPagesToErase = pEraseInit->NbPages; + pFlash.Page = pEraseInit->Page; + + /* Erase first page and wait for IT */ + FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks); + } + } + + return status; +} + +/** + * @brief Program Option bytes. + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @note To configure any option bytes, the option lock bit OPTLOCK must be + * cleared with the call of HAL_FLASH_OB_Unlock() function. + * @note New option bytes configuration will be taken into account in two cases: + * - after an option bytes launch through the call of HAL_FLASH_OB_Launch() + * - after a power reset (BOR reset or exit from Standby/Shutdown modes) + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Write protection configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U) + { + /* Configure of Write protection on the selected area */ + FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset, pOBInit->WRPLock); + } + + /* Read protection configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U) + { + /* Configure the Read protection level */ + FLASH_OB_RDPConfig(pOBInit->RDPLevel); + } + + /* Read protection key configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_RDPKEY) != 0U) + { + /* Configure the Read protection key */ + FLASH_OB_RDPKeyConfig(pOBInit->RDPKeyType, pOBInit->RDPKey1, pOBInit->RDPKey2); + } + + /* User Configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U) + { + /* Configure the user option bytes */ + FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig); + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Watermark secure configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_WMSEC) != 0U) + { + /* Configure the watermark-based secure area */ + FLASH_OB_WMSECConfig(pOBInit->WMSecConfig, pOBInit->WMSecStartPage, pOBInit->WMSecEndPage, + pOBInit->WMHDPEndPage); + } + + /* Unique boot entry point configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_BOOT_LOCK) != 0U) + { + /* Configure the unique boot entry point */ + FLASH_OB_BootLockConfig(pOBInit->BootLock); + } +#endif /* __ARM_FEATURE_CMSE */ + + /* Boot address configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_BOOTADDR) != 0U) + { + /* Configure the boot address */ + FLASH_OB_BootAddrConfig(pOBInit->BootAddrConfig, pOBInit->BootAddr); + } + + /* Set OPTSTRT Bit */ + SET_BIT(FLASH->NSCR, FLASH_NSCR_OPTSTRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Get the Option bytes configuration. + * @param pOBInit pointer to an FLASH_OBInitStruct structure that contains the + * configuration information. + * @note The fields pOBInit->WRPArea, pOBInit->WMSecConfig and pOBInit->BootAddrConfig + * should indicate which area/address is requested for the WRP, WM Security or + * Boot Address, else no information will be returned + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER); + + if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) || + (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB)) + { + pOBInit->OptionType |= OPTIONBYTE_WRP; + /* Get write protection on the selected area */ + FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset), &(pOBInit->WRPLock)); + } + + /* Get Read protection level */ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /* Get the user option bytes */ + pOBInit->USERConfig = FLASH_OB_GetUser(); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Get the configuration of the watermark secure area for the selected area */ + if ((pOBInit->WMSecConfig == OB_WMSEC_AREA1) || (pOBInit->WMSecConfig == OB_WMSEC_AREA2)) + { + pOBInit->OptionType |= OPTIONBYTE_WMSEC; + FLASH_OB_GetWMSEC(&(pOBInit->WMSecConfig), &(pOBInit->WMSecStartPage), &(pOBInit->WMSecEndPage), + &(pOBInit->WMHDPEndPage)); + } + + pOBInit->OptionType |= OPTIONBYTE_BOOT_LOCK; + + /* Get the configuration of the unique boot entry point */ + pOBInit->BootLock = FLASH_OB_GetBootLock(); +#endif /* __ARM_FEATURE_CMSE */ + + /* Get the value of the selected boot address */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if ((pOBInit->BootAddrConfig == OB_BOOTADDR_NS0) || (pOBInit->BootAddrConfig == OB_BOOTADDR_NS1) || + (pOBInit->BootAddrConfig == OB_BOOTADDR_SEC0)) +#else + if ((pOBInit->BootAddrConfig == OB_BOOTADDR_NS0) || (pOBInit->BootAddrConfig == OB_BOOTADDR_NS1)) +#endif /* __ARM_FEATURE_CMSE */ + { + pOBInit->OptionType |= OPTIONBYTE_BOOTADDR; + FLASH_OB_GetBootAddr(pOBInit->BootAddrConfig, &(pOBInit->BootAddr)); + } +} + +/** + * @brief Configure the block-based secure area. + * + * @param pBBAttributes pointer to an FLASH_BBAttributesTypeDef structure that + * contains the configuration information for the programming. + * + * @note The field pBBAttributes->Bank should indicate which area is requested + * for the block-based attributes. + * @note The field pBBAttributes->BBAttributesType should indicate which + * block-base attribute type is requested: Secure or Privilege. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes) +{ + HAL_StatusTypeDef status; + uint8_t index; + __IO uint32_t *reg; + + /* Check the parameters */ + assert_param(IS_FLASH_BANK_EXCLUSIVE(pBBAttributes->Bank)); + assert_param(IS_FLASH_BB_EXCLUSIVE(pBBAttributes->BBAttributesType)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Set the first Block-Based register to write */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (pBBAttributes->BBAttributesType == FLASH_BB_SEC) + { + if (pBBAttributes->Bank == FLASH_BANK_1) + { + reg = &(FLASH->SECBB1R1); + } + else + { + reg = &(FLASH->SECBB2R1); + } + } + else +#endif /* __ARM_FEATURE_CMSE */ + { + if (pBBAttributes->Bank == FLASH_BANK_1) + { + reg = &(FLASH->PRIVBB1R1); + } + else + { + reg = &(FLASH->PRIVBB2R1); + } + } + + /* Modify the register values and check that new attributes are taken in account */ + for (index = 0; index < FLASH_BLOCKBASED_NB_REG; index++) + { + *reg = pBBAttributes->BBAttributes_array[index]; + if ((*reg) != pBBAttributes->BBAttributes_array[index]) + { + status = HAL_ERROR; + } + reg++; + } + + /* ISB instruction is called to be sure next instructions are performed with correct attributes */ + __ISB(); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Return the block-based attributes. + * + * @param pBBAttributes [in/out] pointer to an FLASH_BBAttributesTypeDef structure + * that contains the configuration information. + * @note The field pBBAttributes->Bank should indicate which area is requested + * for the block-based attributes. + * @note The field pBBAttributes->BBAttributesType should indicate which + * block-base attribute type is requested: Secure or Privilege. + * + * @retval None + */ +void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes) +{ + uint8_t index; + __IO uint32_t *reg; + + /* Check the parameters */ + assert_param(IS_FLASH_BANK_EXCLUSIVE(pBBAttributes->Bank)); + assert_param(IS_FLASH_BB_EXCLUSIVE(pBBAttributes->BBAttributesType)); + + /* Set the first Block-Based register to read */ + if (pBBAttributes->BBAttributesType == FLASH_BB_SEC) + { + if (pBBAttributes->Bank == FLASH_BANK_1) + { + reg = &(FLASH->SECBB1R1); + } + else + { + reg = &(FLASH->SECBB2R1); + } + } + else + { + if (pBBAttributes->Bank == FLASH_BANK_1) + { + reg = &(FLASH->PRIVBB1R1); + } + else + { + reg = &(FLASH->PRIVBB2R1); + } + } + + /* Read the register values */ + for (index = 0; index < FLASH_BLOCKBASED_NB_REG; index++) + { + pBBAttributes->BBAttributes_array[index] = (*reg); + reg++; + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Activation of the protection of the secure hide area. + * + * @param Banks indicate the bank concerned by the activation + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be protected + * @arg FLASH_BANK_2: Bank2 to be protected + * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be protected + * + * @retval None + */ +void HAL_FLASHEx_EnableSecHideProtection(uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + + if ((Banks & FLASH_BANK_1) != 0U) + { + SET_BIT(FLASH->SECHDPCR, FLASH_SECHDPCR_HDP1_ACCDIS); + } + + if ((Banks & FLASH_BANK_2) != 0U) + { + SET_BIT(FLASH->SECHDPCR, FLASH_SECHDPCR_HDP2_ACCDIS); + } +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group2 FLASHEx Exported Functions Group2 + * @{ + */ + +/** + * @brief Configuration of the privilege attribute. + * + * @param PrivMode indicate privilege mode configuration + * This parameter can be one of the following values: + * @arg FLASH_SPRIV_GRANTED: access to secure Flash registers is granted to privileged + * or unprivileged access + * @arg FLASH_SPRIV_DENIED: access to secure Flash registers is denied + * to unprivileged access + * @arg FLASH_NSPRIV_GRANTED: access to non-secure Flash registers is granted to privileged + * or unprivileged access + * @arg FLASH_NSPRIV_DENIED: access to non-secure Flash registers is denied + * to unprivilege access + * + * @retval None + */ +void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode) +{ + /* Check the parameters */ + assert_param(IS_FLASH_CFGPRIVMODE(PrivMode)); + + MODIFY_REG(FLASH->PRIVCFGR, (FLASH_PRIVCFGR_SPRIV | FLASH_PRIVCFGR_NSPRIV), PrivMode); +} + +/** + * @brief Return the value of the privilege attribute. + * + * @retval It indicates the privilege mode configuration. + * This return value can be one of the following values: + * @arg FLASH_SPRIV_GRANTED: access to secure Flash registers is granted to privileged + * or unprivileged access + * @arg FLASH_SPRIV_DENIED: access to secure Flash registers is denied + * to unprivileged access + * @arg FLASH_NSPRIV_GRANTED: access to non-secure Flash registers is granted to privileged + * or unprivileged access + * @arg FLASH_NSPRIV_DENIED: access to Flash registers is denied + * to unprivilege accessP + */ +uint32_t HAL_FLASHEx_GetPrivMode(void) +{ + return (FLASH->PRIVCFGR & (FLASH_PRIVCFGR_SPRIV | FLASH_PRIVCFGR_NSPRIV)); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configuration of the security inversion. + * + * @param SecInvState indicate the flash security state configuration + * This parameter can be one of the following values: + * @arg FLASH_SEC_INV_DISABLE: Security state of Flash is not inverted + * @arg FLASH_SEC_INV_ENABLE: Security state of Flash is inverted + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_FLASH_CFGSECINV(SecInvState)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + MODIFY_REG(FLASH->SECCR, FLASH_SECCR_INV, SecInvState); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Return the value of the security inversion. + * + * @retval It indicates the flash security state configuration + * This return value can be one of the following values: + * @arg FLASH_SEC_INV_DISABLE: Security state of Flash is not inverted + * @arg FLASH_SEC_INV_ENABLE: Security state of Flash is inverted + */ +uint32_t HAL_FLASHEx_GetSecInversion(void) +{ + return (FLASH->SECCR & FLASH_SECCR_INV); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Enable the Power-down Mode for Flash Banks + * @param Banks indicate which bank to put in power-down mode + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Flash Bank 1 + * @arg FLASH_BANK_2: Flash Bank 2 + * @arg FLASH_BANK_BOTH: Flash Bank 1 and Bank 2 + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_EnablePowerDown(uint32_t Banks) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + + /* Request power-down mode for Bank 1 */ + if ((Banks & FLASH_BANK_1) != 0U) + { + /* Check PD1 and PDREQ1 bits (Bank 1 is not in power-down mode and not being + already under power-down request) */ + if ((FLASH->NSSR & FLASH_NSSR_PD1) != 0U) + { + status = HAL_ERROR; + } + else if ((FLASH->ACR & FLASH_ACR_PDREQ1) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Unlock PDREQ1 bit */ + WRITE_REG(FLASH->PDKEY1R, FLASH_PDKEY1_1); + WRITE_REG(FLASH->PDKEY1R, FLASH_PDKEY1_2); + + /* Set PDREQ1 in FLASH_ACR register */ + SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ1); + + /* Check PD1 bit */ + tickstart = HAL_GetTick(); + while (((FLASH->NSSR & FLASH_NSSR_PD1) != FLASH_NSSR_PD1)) + { + if ((HAL_GetTick() - tickstart) > FLASH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /* Request power-down mode for Bank 2 */ + if ((Banks & FLASH_BANK_2) != 0U) + { + /* Check PD2 and PDREQ2 bits (Bank 2 is not in power-down mode and not being + already under power-down request) */ + if ((FLASH->NSSR & FLASH_NSSR_PD2) != 0U) + { + status = HAL_ERROR; + } + else if ((FLASH->ACR & FLASH_ACR_PDREQ2) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Unlock PDREQ2 bit */ + WRITE_REG(FLASH->PDKEY2R, FLASH_PDKEY2_1); + WRITE_REG(FLASH->PDKEY2R, FLASH_PDKEY2_2); + + /* Set PDREQ2 in FLASH_ACR register */ + SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ2); + + /* Check PD2 bit */ + tickstart = HAL_GetTick(); + while (((FLASH->NSSR & FLASH_NSSR_PD2) != FLASH_NSSR_PD2)) + { + if ((HAL_GetTick() - tickstart) > FLASH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + return status; +} + +/** + * @brief Configuration of the Low-Power read Mode. + * + * @param ConfigLPM indicate the Low-Power read Mode configuration. + * This parameter can be one of the following values: + * @arg FLASH_LPM_ENABLE: Flash is in low-power read mode + * @arg FLASH_LPM_DISABLE: Flash is in normal read mode + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_ConfigLowPowerRead(uint32_t ConfigLPM) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_FLASH_CFGLPM(ConfigLPM)); + + /* Set LPM Bit in FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LPM, ConfigLPM); + + /* Check that low power read mode has been activated */ + if (READ_BIT(FLASH->ACR, FLASH_ACR_LPM) != ConfigLPM) + { + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Return the value of the Low-Power read Mode. + * + * @retval It indicates the flash low-power read mode configuration + * This return value can be one of the following values: + * @arg FLASH_LPM_ENABLE: Flash is in low-power read mode + * @arg FLASH_LPM_DISABLE: Flash is in normal read mode + */ +uint32_t HAL_FLASHEx_GetLowPowerRead(void) +{ + return (FLASH->ACR & FLASH_ACR_LPM); +} + +/** + * @brief Return the on-going Flash Operation. After a system reset, return + * the interrupted Flash operation, if any. + * @param pFlashOperation [out] pointer to a FLASH_OperationTypeDef structure + * that contains the Flash operation information. + * + * @retval None + */ +void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation) +{ + uint32_t opsr_reg = FLASH->OPSR; + + /* Get Flash operation Type */ + pFlashOperation->OperationType = opsr_reg & FLASH_OPSR_CODE_OP; + + /* Get Flash operation memory */ + pFlashOperation->FlashArea = opsr_reg & (FLASH_OPSR_SYSF_OP | FLASH_OPSR_BK_OP); + + /* Get Flash operation address */ + pFlashOperation->Address = opsr_reg & FLASH_OPSR_ADDR_OP; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ +/** + * @brief Mass erase of FLASH memory. + * @param Banks Banks to be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased + * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + * @retval None + */ +static void FLASH_MassErase(uint32_t Banks) +{ + __IO uint32_t *reg_cr; + + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + + /* Access to SECCR or NSCR registers depends on operation type */ + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); + + /* Set the Mass Erase Bit for the bank 1 and proceed to erase */ + if ((Banks & FLASH_BANK_1) != 0U) + { + SET_BIT((*reg_cr), FLASH_NSCR_MER1 | FLASH_NSCR_STRT); + } + + /* Set the Mass Erase Bit for the bank 2 and proceed to erase */ + if ((Banks & FLASH_BANK_2) != 0U) + { + SET_BIT((*reg_cr), FLASH_NSCR_MER2 | FLASH_NSCR_STRT); + } +} + +/** + * @brief Erase the specified FLASH memory page. + * @param Page FLASH page to erase + * This parameter must be a value between 0 and (max number of pages in the bank - 1) + * @param Banks Bank(s) where the page will be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Page in bank 1 to be erased + * @arg FLASH_BANK_2: Page in bank 2 to be erased + * @retval None + */ +void FLASH_PageErase(uint32_t Page, uint32_t Banks) +{ + __IO uint32_t *reg_cr; + + /* Check the parameters */ + assert_param(IS_FLASH_PAGE(Page)); + assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks)); + + /* Access to SECCR or NSCR registers depends on operation type */ + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); + + if ((Banks & FLASH_BANK_1) != 0U) + { + CLEAR_BIT((*reg_cr), FLASH_NSCR_BKER); + } + else + { + SET_BIT((*reg_cr), FLASH_NSCR_BKER); + } + + /* Proceed to erase the page */ + MODIFY_REG((*reg_cr), (FLASH_NSCR_PNB | FLASH_NSCR_PER | FLASH_NSCR_STRT), \ + ((Page << FLASH_NSCR_PNB_Pos) | FLASH_NSCR_PER | FLASH_NSCR_STRT)); +} + +/** + * @brief Configure the write protection of the desired pages. + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase Flash memory if the CPU debug + * features are connected (JTAG or single wire) or boot code is being + * executed from RAM or System flash, even if WRP is not activated. + * @note To configure the WRP options, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_OB_Unlock() function. + * @note To validate the WRP options, the option bytes must be reloaded + * through the call of the HAL_FLASH_OB_Launch() function. + * + * @param WRPArea specifies the area to be configured. + * This parameter can be one of the following values: + * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A + * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B + * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A + * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B + * + * @param WRPStartOffset specifies the start page of the write protected area + * This parameter can be page number between 0 and (max number of pages in the bank - 1) + * + * @param WRPEndOffset specifies the end page of the write protected area + * This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1) + * + * @param WRPLock enables the lock of the write protected area + * This parameter can be set to ENABLE or DISABLE + * + * @retval None + */ +static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRPEndOffset, + FunctionalState WRPLock) +{ + /* Check the parameters */ + assert_param(IS_OB_WRPAREA(WRPArea)); + assert_param(IS_FLASH_PAGE(WRPStartOffset)); + assert_param(IS_FLASH_PAGE(WRPEndOffset)); + assert_param(IS_FUNCTIONAL_STATE(WRPLock)); + + /* Configure the write protected area */ + if (WRPArea == OB_WRPAREA_BANK1_AREAA) + { + FLASH->WRP1AR = (((uint32_t)(~WRPLock) << FLASH_WRP1AR_UNLOCK_Pos) | \ + (WRPEndOffset << FLASH_WRP1AR_WRP1A_PEND_Pos) | \ + WRPStartOffset); + } + else if (WRPArea == OB_WRPAREA_BANK1_AREAB) + { + FLASH->WRP1BR = (((uint32_t)(~WRPLock) << FLASH_WRP1BR_UNLOCK_Pos) | \ + (WRPEndOffset << FLASH_WRP1BR_WRP1B_PEND_Pos) | \ + WRPStartOffset); + } + else if (WRPArea == OB_WRPAREA_BANK2_AREAA) + { + FLASH->WRP2AR = (((uint32_t)(~WRPLock) << FLASH_WRP2AR_UNLOCK_Pos) | \ + (WRPEndOffset << FLASH_WRP2AR_WRP2A_PEND_Pos) | \ + WRPStartOffset); + } + else if (WRPArea == OB_WRPAREA_BANK2_AREAB) + { + FLASH->WRP2BR = (((uint32_t)(~WRPLock) << FLASH_WRP2BR_UNLOCK_Pos) | \ + (WRPEndOffset << FLASH_WRP2BR_WRP2B_PEND_Pos) | \ + WRPStartOffset); + } + else + { + /* Empty statement (to be compliant MISRA 15.7) */ + } +} + +/** + * @brief Set the read protection level. + * + * @note To configure the RDP level, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_OB_Unlock() function. + * @note To validate the RDP level, the option bytes must be reloaded + * through the call of the HAL_FLASH_OB_Launch() function. + * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible + * to go back to other levels !!! + * + * @param RDPLevel specifies the read protection level. + * This parameter can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_0_5: No debug access to secure area + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + * + * @retval None + */ +static void FLASH_OB_RDPConfig(uint32_t RDPLevel) +{ + /* Check the parameters */ + assert_param(IS_OB_RDP_LEVEL(RDPLevel)); + + /* Configure the RDP level in the option bytes register */ + MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel); +} + +/** + * @brief Set the read protection key. + * @param RDPKeyType specifies the read protection key type. + * This parameter can be one of the following values: + * @arg OB_RDP_KEY_OEM1: OEM1 key + * @arg OB_RDP_KEY_OEM2: OEM2 key + * @param RDPKey1 specifies the RDP key 1. + * @param RDPKey2 specifies the RDP key 2. + * @retval None + */ +static void FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType, uint32_t RDPKey1, uint32_t RDPKey2) +{ + /* Check the parameters */ + assert_param(IS_OB_RDP_KEY_TYPE(RDPKeyType)); + + /* Configure the RDP OEM key */ + if (RDPKeyType == OB_RDP_KEY_OEM1) + { + WRITE_REG(FLASH->OEM1KEYR1, RDPKey1); + WRITE_REG(FLASH->OEM1KEYR2, RDPKey2); + } + else + { + WRITE_REG(FLASH->OEM2KEYR1, RDPKey1); + WRITE_REG(FLASH->OEM2KEYR2, RDPKey2); + } +} + +/** + * @brief Program the FLASH User Option Byte. + * + * @note To configure the user option bytes, the option lock bit OPTLOCK must + * be cleared with the call of the HAL_FLASH_OB_Unlock() function. + * @note To validate the user option bytes, the option bytes must be reloaded + * through the call of the HAL_FLASH_OB_Launch() function. + * @param UserType: The FLASH User Option Bytes to be modified. + * This parameter can be a combination of @ref FLASH_OB_USER_Type + * @param UserConfig The selected User Option Bytes values. + * This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, + * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, + * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST, + * @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP, + * @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW, + * @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK, + * @ref FLASH_OB_USER_BKPRAM_RST, @ref FLASH_OB_USER_SRAM3_ECC, + * @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM2_RST, + * @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0, + * @ref FLASH_OB_USER_PA15_PUPEN, @ref FLASH_OB_USER_IO_VDD_HSLV, + * @ref FLASH_OB_USER_IO_VDDIO2_HSLV and @ref OB_USER_TZEN + * @retval None + */ +static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) +{ + uint32_t optr_reg_val = 0; + uint32_t optr_reg_mask = 0; + + /* Check the parameters */ + assert_param(IS_OB_USER_TYPE(UserType)); + + if ((UserType & OB_USER_BOR_LEV) != 0U) + { + /* BOR level option byte should be modified */ + assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV)); + + /* Set value and mask for BOR level option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV); + optr_reg_mask |= FLASH_OPTR_BOR_LEV; + } + + if ((UserType & OB_USER_NRST_STOP) != 0U) + { + /* nRST_STOP option byte should be modified */ + assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP)); + + /* Set value and mask for nRST_STOP option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP); + optr_reg_mask |= FLASH_OPTR_nRST_STOP; + } + + if ((UserType & OB_USER_NRST_STDBY) != 0U) + { + /* nRST_STDBY option byte should be modified */ + assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY)); + + /* Set value and mask for nRST_STDBY option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY); + optr_reg_mask |= FLASH_OPTR_nRST_STDBY; + } + + if ((UserType & OB_USER_NRST_SHDW) != 0U) + { + /* nRST_SHDW option byte should be modified */ + assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW)); + + /* Set value and mask for nRST_SHDW option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW); + optr_reg_mask |= FLASH_OPTR_nRST_SHDW; + } + + if ((UserType & OB_USER_SRAM_RST) != 0U) + { + /* SRAM_RST option byte should be modified */ + assert_param(IS_OB_USER_SRAM_RST(UserConfig & FLASH_OPTR_SRAM_RST)); + + /* Set value and mask for SRAM_RST option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM_RST); + optr_reg_mask |= FLASH_OPTR_SRAM_RST; + } + + if ((UserType & OB_USER_IWDG_SW) != 0U) + { + /* IWDG_SW option byte should be modified */ + assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW)); + + /* Set value and mask for IWDG_SW option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW); + optr_reg_mask |= FLASH_OPTR_IWDG_SW; + } + + if ((UserType & OB_USER_IWDG_STOP) != 0U) + { + /* IWDG_STOP option byte should be modified */ + assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP)); + + /* Set value and mask for IWDG_STOP option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP); + optr_reg_mask |= FLASH_OPTR_IWDG_STOP; + } + + if ((UserType & OB_USER_IWDG_STDBY) != 0U) + { + /* IWDG_STDBY option byte should be modified */ + assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY)); + + /* Set value and mask for IWDG_STDBY option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY); + optr_reg_mask |= FLASH_OPTR_IWDG_STDBY; + } + + if ((UserType & OB_USER_WWDG_SW) != 0U) + { + /* WWDG_SW option byte should be modified */ + assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW)); + + /* Set value and mask for WWDG_SW option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW); + optr_reg_mask |= FLASH_OPTR_WWDG_SW; + } + + if ((UserType & OB_USER_SWAP_BANK) != 0U) + { + /* SWAP_BANK option byte should be modified */ + assert_param(IS_OB_USER_SWAP_BANK(UserConfig & FLASH_OPTR_SWAP_BANK)); + + /* Set value and mask for SWAP_BANK option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_SWAP_BANK); + optr_reg_mask |= FLASH_OPTR_SWAP_BANK; + } + + if ((UserType & OB_USER_DUALBANK) != 0U) + { + /* DUALBANK option byte should be modified */ + assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK)); + + /* Set value and mask for DUALBANK option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK); + optr_reg_mask |= FLASH_OPTR_DUALBANK; + } + + if ((UserType & OB_USER_BKPRAM_ECC) != 0U) + { + /* BKPRAM_ECC option byte should be modified */ + assert_param(IS_OB_USER_BKPRAM_ECC(UserConfig & FLASH_OPTR_BKPRAM_ECC)); + + /* Set value and mask for BKPRAM_ECC option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_BKPRAM_ECC); + optr_reg_mask |= FLASH_OPTR_BKPRAM_ECC; + } +#if defined(SRAM3_BASE) + if ((UserType & OB_USER_SRAM3_ECC) != 0U) + { + /* SRAM3_ECC option byte should be modified */ + assert_param(IS_OB_USER_SRAM3_ECC(UserConfig & FLASH_OPTR_SRAM3_ECC)); + + /* Set value and mask for SRAM3_ECC option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM3_ECC); + optr_reg_mask |= FLASH_OPTR_SRAM3_ECC; + } +#endif /* SRAM3_BASE */ + if ((UserType & OB_USER_SRAM2_ECC) != 0U) + { + /* SRAM2_ECC option byte should be modified */ + assert_param(IS_OB_USER_SRAM2_ECC(UserConfig & FLASH_OPTR_SRAM2_ECC)); + + /* Set value and mask for SRAM2_ECC option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_ECC); + optr_reg_mask |= FLASH_OPTR_SRAM2_ECC; + } + + if ((UserType & OB_USER_SRAM2_RST) != 0U) + { + /* SRAM2_RST option byte should be modified */ + assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST)); + + /* Set value and mask for SRAM2_RST option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST); + optr_reg_mask |= FLASH_OPTR_SRAM2_RST; + } + + if ((UserType & OB_USER_NSWBOOT0) != 0U) + { + /* nSWBOOT0 option byte should be modified */ + assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0)); + + /* Set value and mask for nSWBOOT0 option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0); + optr_reg_mask |= FLASH_OPTR_nSWBOOT0; + } + + if ((UserType & OB_USER_NBOOT0) != 0U) + { + /* nBOOT0 option byte should be modified */ + assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0)); + + /* Set value and mask for nBOOT0 option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0); + optr_reg_mask |= FLASH_OPTR_nBOOT0; + } + + if ((UserType & OB_USER_PA15_PUPEN) != 0U) + { + /* PA15_PUPEN option byte should be modified */ + assert_param(IS_OB_USER_PA15_PUPEN(UserConfig & FLASH_OPTR_PA15_PUPEN)); + + /* Set value and mask for nBOOT0 option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_PA15_PUPEN); + optr_reg_mask |= FLASH_OPTR_PA15_PUPEN; + } + + if ((UserType & OB_USER_IO_VDD_HSLV) != 0U) + { + /* IO_VDD_HSLV option byte should be modified */ + assert_param(IS_OB_USER_IO_VDD_HSLV(UserConfig & FLASH_OPTR_IO_VDD_HSLV)); + + /* Set value and mask for IO_VDD_HSLV option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_IO_VDD_HSLV); + optr_reg_mask |= FLASH_OPTR_IO_VDD_HSLV; + } + + if ((UserType & OB_USER_IO_VDDIO2_HSLV) != 0U) + { + /* IO_VDDIO2_HSLV option byte should be modified */ + assert_param(IS_OB_USER_IO_VDDIO2_HSLV(UserConfig & FLASH_OPTR_IO_VDDIO2_HSLV)); + + /* Set value and mask for IO_VDDIO2_HSLV option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_IO_VDDIO2_HSLV); + optr_reg_mask |= FLASH_OPTR_IO_VDDIO2_HSLV; + } + + if ((UserType & OB_USER_TZEN) != 0U) + { + /* TZEN option byte should be modified */ + assert_param(IS_OB_USER_TZEN(UserConfig & FLASH_OPTR_TZEN)); + + /* Set value and mask for TZEN option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_TZEN); + optr_reg_mask |= FLASH_OPTR_TZEN; + } + + /* Configure the option bytes register */ + MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure the watermarked-based secure area. + * + * @param WMSecConfig specifies the area to be configured. + * This parameter can be a combination of the following values: + * @arg OB_WMSEC_AREA1 or @arg OB_WMSEC_AREA2: Select Flash Secure Area 1 or Area 2 + * @arg OB_WMSEC_SECURE_AREA_CONFIG: configure Flash Secure Area + * @arg OB_WMSEC_HDP_AREA_CONFIG: configure Flash secure hide Area + * @arg OB_WMSEC_HDP_AREA_ENABLE: enable secure hide Area in Secure Area + * @arg OB_WMSEC_HDP_AREA_DISABLE: disable secure hide Area in Secure Area + * + * @param WMSecStartPage specifies the start page of the secure area + * This parameter can be page number between 0 and (max number of pages in the bank - 1) + * + * @param WMSecEndPage specifies the end page of the secure area + * This parameter can be page number between WMSecStartPage and (max number of pages in the bank - 1) + * + * @param WMHDPEndPage specifies the end page of the secure hide area + * This parameter can be a page number between WMSecStartPage and WMSecEndPage + * + * @retval None + */ +static void FLASH_OB_WMSECConfig(uint32_t WMSecConfig, uint32_t WMSecStartPage, uint32_t WMSecEndPage, + uint32_t WMHDPEndPage) +{ + uint32_t tmp_secwm1 = 0U; + uint32_t tmp_secwm2 = 0U; + + /* Check the parameters */ + assert_param(IS_OB_WMSEC_CONFIG(WMSecConfig)); + assert_param(IS_OB_WMSEC_AREA_EXCLUSIVE(WMSecConfig & 0x3U)); + assert_param(IS_FLASH_PAGE(WMSecStartPage)); + assert_param(IS_FLASH_PAGE(WMSecEndPage)); + assert_param(IS_FLASH_PAGE(WMHDPEndPage)); + + /* Read SECWM registers */ + if ((WMSecConfig & OB_WMSEC_AREA1) != 0U) + { + tmp_secwm1 = FLASH->SECWM1R1; + tmp_secwm2 = FLASH->SECWM1R2; + } + else if ((WMSecConfig & OB_WMSEC_AREA2) != 0U) + { + tmp_secwm1 = FLASH->SECWM2R1; + tmp_secwm2 = FLASH->SECWM2R2; + } + else + { + /* Nothing to do */ + } + + /* Configure Secure Area */ + if ((WMSecConfig & OB_WMSEC_SECURE_AREA_CONFIG) != 0U) + { + tmp_secwm1 = ((WMSecEndPage << FLASH_SECWM1R1_SECWM1_PEND_Pos) | WMSecStartPage); + } + + /* Configure Secure Hide Area */ + if ((WMSecConfig & OB_WMSEC_HDP_AREA_CONFIG) != 0U) + { + tmp_secwm2 &= (~FLASH_SECWM1R2_HDP1_PEND); + tmp_secwm2 |= (WMHDPEndPage << FLASH_SECWM1R2_HDP1_PEND_Pos); + } + + /* Enable Secure Hide Area */ + if ((WMSecConfig & OB_WMSEC_HDP_AREA_ENABLE) != 0U) + { + tmp_secwm2 |= FLASH_SECWM1R2_HDP1EN; + } + + /* Disable Secure Hide Area */ + if ((WMSecConfig & OB_WMSEC_HDP_AREA_DISABLE) != 0U) + { + tmp_secwm2 &= (~FLASH_SECWM1R2_HDP1EN); + } + + /* Write SECWM registers */ + if ((WMSecConfig & OB_WMSEC_AREA1) != 0U) + { + FLASH->SECWM1R1 = tmp_secwm1; + FLASH->SECWM1R2 = tmp_secwm2; + } + else if ((WMSecConfig & OB_WMSEC_AREA2) != 0U) + { + FLASH->SECWM2R1 = tmp_secwm1; + FLASH->SECWM2R2 = tmp_secwm2; + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief Configure the boot lock. + * + * @param BootLockConfig specifies the activation of the BOOT_LOCK. + * This parameter can be one of the following values: + * @arg OB_BOOT_LOCK_DISABLE: Boot Lock mode deactivated + * @arg OB_BOOT_LOCK_ENABLE: Boot Lock mode activated + * + * @retval None + */ +static void FLASH_OB_BootLockConfig(uint32_t BootLockConfig) +{ + /* Check the parameters */ + assert_param(IS_OB_BOOT_LOCK(BootLockConfig)); + + /* Configure the option bytes register */ + MODIFY_REG(FLASH->SECBOOTADD0R, FLASH_SECBOOTADD0R_BOOT_LOCK, BootLockConfig); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Configure the boot address. + * + * @param BootAddrConfig specifies the area to be configured. + * This parameter can be one of the following values: + * @arg OB_BOOTADDR_NS0: Non-secure boot address 0 + * @arg OB_BOOTADDR_NS1: Non-secure boot address 1 + * @arg OB_BOOTADDR_SEC0: Secure boot address 0 + * + * @param BootAddr: specifies the address used for the boot + * This parameter can be page number between 0 and 0xFFFFFF00 + * + * @retval None + */ +static void FLASH_OB_BootAddrConfig(uint32_t BootAddrConfig, uint32_t BootAddr) +{ + /* Check the parameters */ + assert_param(IS_OB_BOOTADDR_CONFIG(BootAddrConfig)); + + if (BootAddrConfig == OB_BOOTADDR_NS0) + { + FLASH->NSBOOTADD0R = BootAddr; + } + else if (BootAddrConfig == OB_BOOTADDR_NS1) + { + FLASH->NSBOOTADD1R = BootAddr; + } +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + else if (BootAddrConfig == OB_BOOTADDR_SEC0) + { + MODIFY_REG(FLASH->SECBOOTADD0R, FLASH_SECBOOTADD0R_SECBOOTADD0, BootAddr); + } +#endif /* __ARM_FEATURE_CMSE */ + else + { + /* Empty statement (to be compliant MISRA 15.7) */ + } +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * + * @param[in] WRPArea specifies the area to be returned. + * This parameter can be one of the following values: + * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A + * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B + * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A + * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B + * + * @param[out] WRPStartOffset specifies the address where to copied the start page + * of the write protected area + * + * @param[out] WRPEndOffset specifies the address where to copied the end page of + * the write protected area + * + * @param[out] WRPLock specifies the lock status of the write protected area. + * The returned value can be ENABLE or DISABLE + * + * @retval None + */ +static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRPEndOffset, + FunctionalState *WRPLock) +{ + /* Get the configuration of the write protected area */ + if (WRPArea == OB_WRPAREA_BANK1_AREAA) + { + *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_PSTRT); + *WRPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_PEND) >> FLASH_WRP1AR_WRP1A_PEND_Pos); + *WRPLock = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_UNLOCK) != 0U) ? DISABLE : ENABLE; + } + else if (WRPArea == OB_WRPAREA_BANK1_AREAB) + { + *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_PSTRT); + *WRPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_PEND) >> FLASH_WRP1BR_WRP1B_PEND_Pos); + *WRPLock = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_UNLOCK) != 0U) ? DISABLE : ENABLE; + } + else if (WRPArea == OB_WRPAREA_BANK2_AREAA) + { + *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_PSTRT); + *WRPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_PEND) >> FLASH_WRP2AR_WRP2A_PEND_Pos); + *WRPLock = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_UNLOCK) != 0U) ? DISABLE : ENABLE; + } + else if (WRPArea == OB_WRPAREA_BANK2_AREAB) + { + *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_PSTRT); + *WRPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_PEND) >> FLASH_WRP2BR_WRP2B_PEND_Pos); + *WRPLock = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_UNLOCK) != 0U) ? DISABLE : ENABLE; + } + else + { + /* Empty statement (to be compliant MISRA 15.7) */ + } +} + +/** + * @brief Return the FLASH Read Protection level. + * @retval FLASH ReadOut Protection Level. + * This return value can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_0_5: No debug access to secure area + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + */ +static uint32_t FLASH_OB_GetRDP(void) +{ + uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP); + + if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_0_5) && (rdp_level != OB_RDP_LEVEL_2)) + { + return (OB_RDP_LEVEL_1); + } + else + { + return rdp_level; + } +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval The FLASH User Option Bytes values. + * The return value can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, + * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, + * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST, + * @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP, + * @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW, + * @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK, + * @ref FLASH_OB_USER_BKPRAM_RST, @ref FLASH_OB_USER_SRAM3_ECC, + * @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM2_RST, + * @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0, + * @ref FLASH_OB_USER_PA15_PUPEN, @ref FLASH_OB_USER_IO_VDD_HSLV, + * @ref FLASH_OB_USER_IO_VDDIO2_HSLV and @ref OB_USER_TZEN + */ +static uint32_t FLASH_OB_GetUser(void) +{ + uint32_t user_config = READ_REG(FLASH->OPTR); + CLEAR_BIT(user_config, FLASH_OPTR_RDP); + + return user_config; +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Return the watermarked-based secure area configuration. + * + * @param WMSecConfig [in/out] specifies the area to be returned. + * This parameter can be one of the following values: + * @arg OB_WMSEC_AREA1: select Flash Secure Area 1 + * @arg OB_WMSEC_AREA2: select Flash Secure Area 2 + * When return from the function, this parameter will be a combinaison of the following values: + * @arg OB_WMSEC_AREAA or @arg OB_WMSEC_AREAB: selected Flash Secure Area A or Area B + * @arg OB_WMSEC_HDP_AREA_ENABLE: Secure Hide Area in Secure Area enabled + * @arg OB_WMSEC_HDP_AREA_DISABLE: Secure Hide Area in Secure Area disabled + * + * @param WMSecStartPage [out] specifies the start page of the secure area + * + * @param WMSecEndPage [out] specifies the end page of the secure area + * + * @param WMHDPEndPage [out] specifies the end page of the secure hide area + * + * + * @retval None + */ +static void FLASH_OB_GetWMSEC(uint32_t *WMSecConfig, uint32_t *WMSecStartPage, uint32_t *WMSecEndPage, + uint32_t *WMHDPEndPage) +{ + uint32_t tmp_secwm1 = 0U; + uint32_t tmp_secwm2 = 0U; + + /* Check the parameters */ + assert_param(IS_OB_WMSEC_CONFIG(*WMSecConfig)); + assert_param(IS_FLASH_BANK_EXCLUSIVE((*WMSecConfig) & 0x3U)); + + /* Read SECWM registers */ + if (((*WMSecConfig) & OB_WMSEC_AREA1) != 0U) + { + tmp_secwm1 = FLASH->SECWM1R1; + tmp_secwm2 = FLASH->SECWM1R2; + } + else if (((*WMSecConfig) & OB_WMSEC_AREA2) != 0U) + { + tmp_secwm1 = FLASH->SECWM2R1; + tmp_secwm2 = FLASH->SECWM2R2; + } + else + { + /* Empty statement (to be compliant MISRA 15.7) */ + } + + /* Configuration of secure area */ + *WMSecStartPage = (tmp_secwm1 & FLASH_SECWM1R1_SECWM1_PSTRT); + *WMSecEndPage = ((tmp_secwm1 & FLASH_SECWM1R1_SECWM1_PEND) >> FLASH_SECWM1R1_SECWM1_PEND_Pos); + + /* Configuration of secure hide area */ + *WMHDPEndPage = ((tmp_secwm2 & FLASH_SECWM1R2_HDP1_PEND) >> FLASH_SECWM1R2_HDP1_PEND_Pos); + + if ((tmp_secwm2 & FLASH_SECWM1R2_HDP1EN) == 0U) + { + *WMSecConfig = ((*WMSecConfig) | OB_WMSEC_HDP_AREA_DISABLE); + } + else + { + *WMSecConfig = ((*WMSecConfig) | OB_WMSEC_HDP_AREA_ENABLE); + } + +} + +/** + * @brief Return the boot lock configuration. + * + * @retval Value of Boot Lock configuration. + * It can be one of the following values: + * @arg OB_BOOT_LOCK_DISABLE: Boot Lock mode deactivated + * @arg OB_BOOT_LOCK_ENABLE: Boot Lock mode activated + */ +static uint32_t FLASH_OB_GetBootLock(void) +{ + return (FLASH->SECBOOTADD0R & FLASH_SECBOOTADD0R_BOOT_LOCK); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Return the boot address. + * + * @param[in] BootAddrConfig specifies the area to be returned. + * This parameter can be one of the following values: + * @arg OB_BOOTADDR_NS0: Non-secure boot address 0 + * @arg OB_BOOTADDR_NS1: Non-secure boot address 1 + * @arg OB_BOOTADDR_SEC0: Secure boot address 0 + * + * @param[out] BootAddr specifies the boot address value + * + * @retval None + */ +static void FLASH_OB_GetBootAddr(uint32_t BootAddrConfig, uint32_t *BootAddr) +{ + if (BootAddrConfig == OB_BOOTADDR_NS0) + { + *BootAddr = (FLASH->NSBOOTADD0R & FLASH_NSBOOTADD0R_NSBOOTADD0); + } + else if (BootAddrConfig == OB_BOOTADDR_NS1) + { + *BootAddr = (FLASH->NSBOOTADD1R & FLASH_NSBOOTADD1R_NSBOOTADD1); + } +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + else if (BootAddrConfig == OB_BOOTADDR_SEC0) + { + *BootAddr = (FLASH->SECBOOTADD0R & FLASH_SECBOOTADD0R_SECBOOTADD0); + } +#endif /* __ARM_FEATURE_CMSE */ + else + { + /* Empty statement (to be compliant MISRA 15.7) */ + } +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpio.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpio.c new file mode 100644 index 000000000..32fb262ca --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpio.c @@ -0,0 +1,990 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (++) Input mode + (++) Analog mode + (++) Output mode + (++) Alternate function mode + (++) External interrupt/event lines + + (+) During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + (+) All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + (+) The external interrupt/event controller consists of up to 39 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To set the level of several pins and reset level of several other pins in + same cycle, use HAL_GPIO_WriteMultipleStatePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup GPIO_Private_Defines GPIO Private Defines + * @{ + */ +#define GPIO_MODE (0x00000003U) +#define EXTI_MODE (0x10000000U) +#define GPIO_MODE_IT (0x00010000U) +#define GPIO_MODE_EVT (0x00020000U) +#define RISING_EDGE (0x00100000U) +#define FALLING_EDGE (0x00200000U) +#define GPIO_OUTPUT_TYPE (0x00000010U) +#define GPIO_NUMBER (16U) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Variables GPIO Private Variables + * @{ + */ + +/* LPGPIO Mapping */ +static const LPGPIO_MapTypeDef LPGPIO_Map[GPIO_NUMBER] = +{ + /* LPGPIO Pins Port Pin */ + /* Pin 0:*/ {GPIOA, 1}, + /* Pin 1:*/ {GPIOA, 3}, + /* Pin 2:*/ {GPIOA, 6}, + /* Pin 3:*/ {GPIOB, 1}, + /* Pin 4:*/ {GPIOB, 10}, + /* Pin 5:*/ {GPIOC, 2}, + /* Pin 6:*/ {GPIOD, 13}, + /* Pin 7:*/ {GPIOD, 2}, + /* Pin 8:*/ {GPIOC, 10}, + /* Pin 9:*/ {GPIOB, 0}, + /* Pin 10:*/ {GPIOC, 12}, + /* Pin 11:*/ {GPIOB, 3}, + /* Pin 12:*/ {GPIOB, 4}, + /* Pin 13:*/ {GPIOE, 0}, + /* Pin 14:*/ {GPIOE, 2}, + /* Pin 15:*/ {GPIOE, 3}, +}; + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GPIOx/LPGPIOx peripheral according to the specified parameters in the pGPIO_Init. + * @note If GPIOx/LPGPIOx peripheral pin is used in EXTI_MODE and the pin is secure in case + * the system implements the security (TZEN=1), it is up to the secure application to + * insure that the corresponding EXTI line is set secure. + * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the corresponding + * peripheral for STM32U5 family + * @param pGPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) +{ + uint32_t tmp; + uint32_t iocurrent; + uint32_t pin_position; + uint32_t position = 0U; + GPIO_TypeDef *p_gpio; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(pGPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(pGPIO_Init->Mode)); + + /* Save GPIO port address */ + p_gpio = GPIOx; + + /* Configure the port pins */ + while (((pGPIO_Init->Pin) >> position) != 0U) + { + /* Get current io position */ + iocurrent = (pGPIO_Init->Pin) & (1UL << position); + + /* Save Pin Position */ + pin_position = position; + + if (iocurrent != 0U) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Alternate function mode selection */ + if (GPIOx == LPGPIO1) + { + /* MODER configuration */ + tmp = GPIOx->MODER; + tmp &= ~(LPGPIO_MODER_MOD0 << position); + tmp |= ((pGPIO_Init->Mode & GPIO_MODE_OUTPUT_PP) << position); + GPIOx->MODER = tmp; + + /* Save GPIO Port and pin index */ + p_gpio = LPGPIO_Map[position].GPIO_PORT; + pin_position = LPGPIO_Map[position].Pin_Pos; + + /* Configure Alternate function mapped with the current IO */ + tmp = p_gpio->AFR[(pin_position) >> 3U]; + tmp &= ~(0x0FUL << (((pin_position) & 0x07U) * 4U)); + tmp |= ((GPIO_AF11_LPGPIO1 & 0x0FUL) << (((pin_position) & 0x07U) * 4U)); + p_gpio->AFR[(pin_position) >> 3U] = tmp; + + /* Configure IO Direction mode (Alternate) */ + tmp = p_gpio->MODER; + tmp &= ~(GPIO_MODER_MODE0 << (pin_position * GPIO_MODER_MODE1_Pos)); + tmp |= ((GPIO_MODE_AF_PP & 0x0FUL) << (pin_position * GPIO_MODER_MODE1_Pos)); + p_gpio->MODER = tmp; + } + else if ((pGPIO_Init->Mode == GPIO_MODE_AF_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(pGPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + tmp = GPIOx->AFR[position >> 3U]; + tmp &= ~(0x0FUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); + tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); + GPIOx->AFR[position >> 3U] = tmp; + + /* Configure IO Direction mode (Alternate) */ + tmp = p_gpio->MODER; + tmp &= ~(GPIO_MODER_MODE0 << (pin_position * GPIO_MODER_MODE1_Pos)); + tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (pin_position * GPIO_MODER_MODE1_Pos)); + p_gpio->MODER = tmp; + } + else + { + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + tmp = p_gpio->MODER; + tmp &= ~(GPIO_MODER_MODE0 << (pin_position * GPIO_MODER_MODE1_Pos)); + tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (pin_position * GPIO_MODER_MODE1_Pos)); + p_gpio->MODER = tmp; + } + + /* In case of Output or Alternate function mode selection */ + if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) || + (pGPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(pGPIO_Init->Speed)); + + /* Configure the IO Speed */ + tmp = p_gpio->OSPEEDR; + tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (pin_position * GPIO_OSPEEDR_OSPEED1_Pos)); + tmp |= (pGPIO_Init->Speed << (pin_position * GPIO_OSPEEDR_OSPEED1_Pos)); + p_gpio->OSPEEDR = tmp; + + /* Configure the IO Output Type */ + tmp = p_gpio->OTYPER; + tmp &= ~(GPIO_OTYPER_OT0 << pin_position); + tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << pin_position); + p_gpio->OTYPER = tmp; + } + + if ((pGPIO_Init->Mode != GPIO_MODE_ANALOG) || + ((pGPIO_Init->Mode == GPIO_MODE_ANALOG) && (pGPIO_Init->Pull != GPIO_PULLUP))) + { + /* Check the Pull parameters */ + assert_param(IS_GPIO_PULL(pGPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + tmp = p_gpio->PUPDR; + tmp &= ~(GPIO_PUPDR_PUPD0 << (pin_position * GPIO_PUPDR_PUPD1_Pos)); + tmp |= ((pGPIO_Init->Pull) << (pin_position * GPIO_PUPDR_PUPD1_Pos)); + p_gpio->PUPDR = tmp; + } + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((pGPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + { + tmp = EXTI->EXTICR[position >> 2U]; + tmp &= ~((0x0FUL) << (EXTI_EXTICR1_EXTI1_Pos * (position & 0x03U))); + tmp |= (GPIO_GET_INDEX(GPIOx) << (EXTI_EXTICR1_EXTI1_Pos * (position & 0x03U))); + EXTI->EXTICR[position >> 2U] = tmp; + + /* Clear Rising Falling edge configuration */ + tmp = EXTI->RTSR1; + tmp &= ~((uint32_t)iocurrent); + if ((pGPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + { + tmp |= iocurrent; + } + EXTI->RTSR1 = tmp; + + tmp = EXTI->FTSR1; + tmp &= ~((uint32_t)iocurrent); + if ((pGPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + { + tmp |= iocurrent; + } + EXTI->FTSR1 = tmp; + + /* Clear EXTI line configuration */ + tmp = EXTI->EMR1; + tmp &= ~((uint32_t)iocurrent); + if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + { + tmp |= iocurrent; + } + EXTI->EMR1 = tmp; + + tmp = EXTI->IMR1; + tmp &= ~((uint32_t)iocurrent); + if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + { + tmp |= iocurrent; + } + EXTI->IMR1 = tmp; + } + } + position++; + } +} + +/** + * @brief De-initialize the GPIOx peripheral registers to their default reset values. + * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding + * peripheral for STM32U5 family + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t tmp; + uint32_t iocurrent; + uint32_t pin_position; + uint32_t position = 0U; + GPIO_TypeDef *p_gpio; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Save GPIO port address */ + p_gpio = GPIOx; + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0U) + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1UL << position); + + /*Save Pin Position */ + pin_position = position; + + if (iocurrent != 0U) + { + /* In case of LPGPIO port selected */ + if (GPIOx == LPGPIO1) + { + /* Configure LP/IO in Input Mode */ + p_gpio = LPGPIO_Map[pin_position].GPIO_PORT; + pin_position = LPGPIO_Map[position].Pin_Pos; + LPGPIO1->MODER &= ~(1U << pin_position); + } + else + { + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + tmp = EXTI->EXTICR[position >> 2U]; + tmp &= ((0x0FUL) << (8U * (position & 0x03U))); + if (tmp == (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U)))) + { + /* Clear EXTI line configuration */ + EXTI->IMR1 &= ~(iocurrent); + EXTI->EMR1 &= ~(iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR1 &= ~(iocurrent); + EXTI->FTSR1 &= ~(iocurrent); + + tmp = (0x0FUL) << (8U * (position & 0x03U)); + EXTI->EXTICR[position >> 2U] &= ~tmp; + } + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO in Analog Mode */ + p_gpio->MODER |= (GPIO_MODER_MODE0 << (pin_position * GPIO_MODER_MODE1_Pos)); + + /* Configure the default Alternate Function in current IO */ + p_gpio->AFR[pin_position >> 3U] &= ~(0x0FUL << ((pin_position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); + + /* Configure the default value for IO Speed */ + p_gpio->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (pin_position * GPIO_OSPEEDR_OSPEED1_Pos)); + + /* Configure the default value IO Output Type */ + p_gpio->OTYPER &= ~(GPIO_OTYPER_OT0 << pin_position); + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + p_gpio->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (pin_position * GPIO_PUPDR_PUPD1_Pos)); + } + + position++; + } +} + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @brief GPIO/LPGPIO Read, Write, Toggle, Lock and EXTI management functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Read the specified input port pin. + * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding + * peripheral for STM32U5 family + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != 0U) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + + return bitstatus; +} + +/** + * @brief Set or clear the selected data port bit. + * @note This function uses GPIOx_BSRR/LPGPIOx_BSRR and GPIOx_BRR/LPGPIOx_BRR registers to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding + * peripheral for STM32U5 family + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @param PinState: specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + +/** + * @brief Set and clear several pins of a dedicated port in same cycle. + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. + * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding + * peripheral for STM32U5 family + * @param PinReset specifies the port bits to be reset + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. + * @param PinSet specifies the port bits to be set + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. + * @note Both PinReset and PinSet combinations shall not get any common bit, else + * assert would be triggered. + * @note At least one of the two parameters used to set or reset shall be different from zero. + * @retval None + */ +void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet) +{ + uint32_t tmp; + + /* Check the parameters */ + /* Make sure at least one parameter is different from zero and that there is no common pin */ + assert_param(IS_GPIO_PIN((uint32_t)PinReset | (uint32_t)PinSet)); + assert_param(IS_GPIO_COMMON_PIN(PinReset, PinSet)); + + tmp = (((uint32_t)PinReset << 16) | PinSet); + GPIOx->BSRR = tmp; +} + +/** + * @brief Toggle the specified GPIO pin. + * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding + * peripheral for STM32U5 family + * @param GPIO_Pin specifies the pin to be toggled. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** + * @brief Lock GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding + * peripheral for STM32U5 family + * @param GPIO_Pin: specifies the port bits to be locked. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t iocurrent; + uint32_t pin_locked; + uint32_t pin_position; + uint32_t position = 0U; + GPIO_TypeDef *p_gpio; + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Save GPIO port address */ + p_gpio = GPIOx; + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0U) + { + /* Get current io position */ + iocurrent = GPIO_Pin & (1UL << position); + + if (iocurrent != 0U) + { + + /* In case of LPGPIO Port */ + if (GPIOx == LPGPIO1) + { + /* Save GPIO Port and pin index */ + p_gpio = LPGPIO_Map[position].GPIO_PORT; + pin_position = (1UL << (LPGPIO_Map[position].Pin_Pos)); + + /* Save gpio pin locked */ + pin_locked = p_gpio->LCKR; + + /* Apply lock key write sequence */ + tmp |= (pin_locked | pin_position); + } + else + { + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Save GPIO Pin pos*/ + pin_position = (1UL << position); + + /* Save gpio pin locked */ + pin_locked = p_gpio->LCKR; + + /* Apply lock key write sequence */ + tmp |= (pin_locked | pin_position); + } + + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + p_gpio->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + p_gpio->LCKR = pin_position; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + p_gpio->LCKR = tmp; + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + tmp = p_gpio->LCKR; + + /* read again in order to confirm lock is active */ + if ((p_gpio->LCKR & GPIO_LCKR_LCKK) != GPIO_LCKR_LCKK) + { + return HAL_ERROR; + } + } + position++; + } + return HAL_OK; +} + +/** + * @brief Enable speed optimization for several pin of dedicated port. + * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding + * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must + * be kept at reset value. + * @note It must be used only if the I/O supply voltage is below 2.7 V. + * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding + * peripheral for STM32U5 family + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t iocurrent; + uint32_t pin_position; + uint32_t position = 0U; + GPIO_TypeDef *p_gpio; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Save GPIO port address */ + p_gpio = GPIOx; + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0U) + { + /* Get current io position */ + iocurrent = GPIO_Pin & (1UL << position); + + if (iocurrent != 0U) + { + /* In case of LPGPIO Port */ + if (GPIOx == LPGPIO1) + { + /* Get GPIO pin position */ + position = POSITION_VAL(GPIO_Pin); + + /* Save GPIO Port and pin index */ + p_gpio = LPGPIO_Map[position].GPIO_PORT; + pin_position = (1UL << (LPGPIO_Map[position].Pin_Pos)); + } + else + { + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Save GPIO pin pos */ + pin_position = (1UL << position); + } + /* Set HSLVR gpio pin */ + SET_BIT(p_gpio->HSLVR, pin_position); + } + position++; + } +} + +/** + * @brief Disable speed optimization for several pin of dedicated port. + * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding + * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must + * be kept at reset value. + * @note It must be used only if the I/O supply voltage is below 2.7 V. + * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding + * peripheral for STM32U5 family + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t iocurrent; + uint32_t pin_position; + uint32_t position = 0U; + GPIO_TypeDef *p_gpio; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Save GPIO port address */ + p_gpio = GPIOx; + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0U) + { + /* Get current io position */ + iocurrent = GPIO_Pin & (1UL << position); + + if (iocurrent != 0U) + { + /* In case of LPGPIO Port */ + if (GPIOx == LPGPIO1) + { + /* Get GPIO pin position */ + position = POSITION_VAL(GPIO_Pin); + + /* Save GPIO Port and pin index */ + p_gpio = LPGPIO_Map[position].GPIO_PORT; + pin_position = (1UL << (LPGPIO_Map[position].Pin_Pos)); + } + else + { + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Save GPIO pin pos */ + pin_position = (1UL << position); + } + /* Clear HSLVR gpio pin */ + CLEAR_BIT(p_gpio->HSLVR, pin_position); + } + position++; + } +} + +/** + * @brief Handle EXTI interrupt request. + * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0U) + { + __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin); + HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin); + } + + if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0U) + { + __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin); + HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line rising detection callback. + * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file + */ +} + +/** + * @brief EXTI line falling detection callback. + * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** @defgroup GPIO_Exported_Functions_Group3 IO attributes management functions + * @brief GPIO attributes management functions. + * +@verbatim + =============================================================================== + ##### IO attributes functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configure the GPIO pins attributes. + * @note Available attributes are to secure GPIO pin(s), so this function is + * only available in secure + * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding + * peripheral for STM32U5 family + * @param GPIO_Pin: specifies the pin(s) to configure the secure attribute + * @param PinAttributes: specifies the pin(s) to be set in secure mode, other being set non secured. + * @retval None + */ +void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes) +{ + uint32_t iocurrent; + uint32_t pin_position; + uint32_t position = 0U; + GPIO_TypeDef *p_gpio; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ATTRIBUTES(PinAttributes)); + + /* Save GPIO port address */ + p_gpio = GPIOx; + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0U) + { + /* Get current io position */ + iocurrent = GPIO_Pin & (1UL << position); + + /* Save pin position */ + pin_position = position; + + if (iocurrent != 0U) + { + /* In case of LPGPIO Port */ + if (GPIOx == LPGPIO1) + { + /* Save GPIO Port and pin index */ + p_gpio = LPGPIO_Map[position].GPIO_PORT; + pin_position = LPGPIO_Map[position].Pin_Pos; + } + else + { + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + } + + /* Configure the IO secure attribute */ + MODIFY_REG(p_gpio->SECCFGR, (GPIO_SECCFGR_SEC0 << pin_position), (PinAttributes << pin_position)); + } + position++; + } +} + +/** + * @brief Get the GPIO pins attributes. + * @note Available attributes are to secure GPIO pin(s), so this function is + * only available in secure + * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding + * peripheral for STM32U5 family + * @param GPIO_Pin: specifies the single pin to get the secure attribute from + * @param pPinAttributes: pointer to return the pin attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, + uint32_t *pPinAttributes) +{ + uint32_t iocurrent; + uint32_t pin_position; + uint32_t position = 0U; + const GPIO_TypeDef *p_gpio; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_SINGLE_PIN(GPIO_Pin)); + + /* Check null pointer */ + if (pPinAttributes == NULL) + { + return HAL_ERROR; + } + + /* Get secure attribute of the port pin */ + while ((GPIO_Pin >> position) != 0U) + { + /* Get current io position */ + iocurrent = GPIO_Pin & (1UL << position); + + if (iocurrent != 0U) + { + /* In case of LPGPIO Port */ + if (GPIOx == LPGPIO1) + { + /* Save GPIO Port and pin index */ + p_gpio = LPGPIO_Map[position].GPIO_PORT; + pin_position = LPGPIO_Map[position].Pin_Pos; + } + else + { + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Save GPIO port address */ + p_gpio = GPIOx; + + pin_position = (1UL << position); + } + + /* Get the IO secure attribute */ + if ((p_gpio->SECCFGR & (GPIO_SECCFGR_SEC0 << pin_position)) != 0U) + { + *pPinAttributes = GPIO_PIN_SEC; + } + else + { + *pPinAttributes = GPIO_PIN_NSEC; + } + + break; + } + position++; + } + + return HAL_OK; +} + +/** + * @} + */ + +#endif /* __ARM_FEATURE_CMSE */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c new file mode 100644 index 000000000..023a52131 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c @@ -0,0 +1,2210 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_gtzc.c + * @author MCD Application Team + * @brief GTZC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of GTZC peripheral: + * + TZSC Initialization and Configuration functions + * + TZSC-MPCWM Initialization and Configuration functions + * + MPCBB Initialization and Configuration functions + * + TZSC, TZSC-MPCWM and MPCBB Lock functions + * + TZIC Initialization and Configuration functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### GTZC main features ##### + ============================================================================== + [..] + (+) Global TrustZone Controller (GTZC) composed of three sub-blocks: + (++) TZSC: TrustZone security controller + This sub-block defines the secure/privileged state of master and slave + peripherals. It also controls the secure/privileged state of subregions + for the watermark memory peripheral controller (MPCWM). + (++) MPCBB: Block-Based memory protection controller + This sub-block defines the secure/privileged state of all blocks + (512-byte pages) of the associated SRAM. + (++) TZIC: TrustZone illegal access controller + This sub-block gathers all illegal access events in the system and + generates a secure interrupt towards NVIC. + + (+) These sub-blocks are used to configure TrustZone system security in + a product having bus agents with programmable-security and privileged + attributes (securable) such as: + (++) on-chip RAM with programmable secure and/or privilege blocks (pages) + (++) AHB and APB peripherals with programmable security and/or privilege access + (++) AHB master granted as secure and/or privilege + (++) off-chip memories with secure and/or privilege areas + + [..] + (+) TZIC accessible only with secure privileged transactions. + (+) Secure and non-secure access supported for privileged and unprivileged + part of TZSC and MPCBB + (+) Set of registers to define product security settings: + (++) Secure and privilege blocks for internal memories + (++) Secure and privilege regions for external memories + (++) Secure and privileged access mode for securable peripherals + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The GTZC HAL driver can be used as follows: + + (#) Configure or get back securable peripherals attributes using + HAL_GTZC_TZSC_ConfigPeriphAttributes() / HAL_GTZC_TZSC_GetConfigPeriphAttributes() + + (#) Configure or get back MPCWM memories attributes using + HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes() / HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes() + + (#) Lock TZSC sub-block or get lock status using HAL_GTZC_TZSC_Lock() / + HAL_GTZC_TZSC_GetLock() + + (#) Configure or get back MPCBB memories complete configuration using + HAL_GTZC_MPCBB_ConfigMem() / HAL_GTZC_MPCBB_GetConfigMem() + + (#) Configure or get back MPCBB memories attributes using + HAL_GTZC_MPCBB_ConfigMemAttributes() / HAL_GTZC_MPCBB_GetConfigMemAttributes() + + (#) Lock MPCBB configuration or get lock status using HAL_GTZC_MPCBB_Lock() / + HAL_GTZC_MPCBB_GetLock() + + (#) Lock MPCBB super-blocks or get lock status using HAL_GTZC_MPCBB_LockConfig() / + HAL_GTZC_MPCBB_GetLockConfig() + + (#) Illegal access detection can be configured through TZIC sub-block using + following functions: HAL_GTZC_TZIC_DisableIT() / HAL_GTZC_TZIC_EnableIT() + + (#) Illegal access flags can be retrieved through HAL_GTZC_TZIC_GetFlag() and + HAL_GTZC_TZIC_ClearFlag() functions + + (#) Illegal access interrupt service routines are served by HAL_GTZC_IRQHandler() + and user can add his own code using HAL_GTZC_TZIC_Callback() + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup GTZC GTZC + * @brief GTZC HAL module driver + * @{ + */ + +#ifdef HAL_GTZC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ + +/** @defgroup GTZC_Private_Constants GTZC Private Constants + * @{ + */ + +/* Definitions for TZSC_MPCWM */ +#define TZSC_MPCWM1_MEM_SIZE 0x10000000U /* 256MB max size */ +#define TZSC_MPCWM2_MEM_SIZE 0x10000000U /* 256MB max size */ +#define TZSC_MPCWM3_MEM_SIZE 0x10000000U /* 256MB max size */ +#define TZSC_MPCWM4_MEM_SIZE 0x00000800U /* 2KB max size */ +#define TZSC_MPCWM5_MEM_SIZE 0x10000000U /* 256MB max size */ +#if defined (HSPI1) +#define TZSC_MPCWM6_MEM_SIZE 0x10000000U /* 256MB max size */ +#endif /* HSPI1 */ + +/* Definitions for GTZC TZSC & TZIC ALL register values */ +/* TZSC1 / TZIC1 instances */ +#if defined(STM32U599xx) || defined(STM32U595xx) || defined(STM32U5A9xx) || defined (STM32U5A5xx) +#define TZSC1_SECCFGR1_ALL (0x00EFFFFFUL) +#define TZSC1_SECCFGR2_ALL (0x000007FFUL) +#define TZSC1_SECCFGR3_ALL (0x0FFFFFFFUL) + +#define TZSC1_PRIVCFGR1_ALL (0x00EFFFFFUL) +#define TZSC1_PRIVCFGR2_ALL (0x000007FFUL) +#define TZSC1_PRIVCFGR3_ALL (0x0FFFFFFFUL) + +#define TZIC1_IER1_ALL (0x00EFFFFFUL) +#define TZIC1_IER2_ALL (0x000007FFUL) +#define TZIC1_IER3_ALL (0x0FFFFFFFUL) +#define TZIC1_IER4_ALL (0xFF1FC01FUL) + +#define TZIC1_FCR1_ALL (0x00EFFFFFUL) +#define TZIC1_FCR2_ALL (0x000007FFUL) +#define TZIC1_FCR3_ALL (0x0FFFFFFFUL) +#define TZIC1_FCR4_ALL (0xFF1FC01FUL) + +#elif defined(STM32U5F9xx) || defined(STM32U5G9xx) +#define TZSC1_SECCFGR1_ALL (0x00EFFFFFUL) +#define TZSC1_SECCFGR2_ALL (0x00000FFFUL) +#define TZSC1_SECCFGR3_ALL (0x1FFFFFFFUL) + +#define TZSC1_PRIVCFGR1_ALL (0x00EFFFFFUL) +#define TZSC1_PRIVCFGR2_ALL (0x00000FFFUL) +#define TZSC1_PRIVCFGR3_ALL (0x1FFFFFFFUL) + +#define TZIC1_IER1_ALL (0x00EFFFFFUL) +#define TZIC1_IER2_ALL (0x00000FFFUL) +#define TZIC1_IER3_ALL (0x1FFFFFFFUL) +#define TZIC1_IER4_ALL (0xFFDFC01FUL) + +#define TZIC1_FCR1_ALL (0x00EFFFFFUL) +#define TZIC1_FCR2_ALL (0x00000FFFUL) +#define TZIC1_FCR3_ALL (0x1FFFFFFFUL) +#define TZIC1_FCR4_ALL (0xFFDFC01FUL) +#else +#define TZSC1_SECCFGR1_ALL (0x000FFFFFUL) +#define TZSC1_SECCFGR2_ALL (0x000001FFUL) +#define TZSC1_SECCFGR3_ALL (0x007FFFFFUL) + +#define TZSC1_PRIVCFGR1_ALL (0x000FFFFFUL) +#define TZSC1_PRIVCFGR2_ALL (0x000001FFUL) +#define TZSC1_PRIVCFGR3_ALL (0x007FFFFFUL) + +#define TZIC1_IER1_ALL (0x000FFFFFUL) +#define TZIC1_IER2_ALL (0x000001FFUL) +#define TZIC1_IER3_ALL (0x007FFFFFUL) +#define TZIC1_IER4_ALL (0x3F0FC01FUL) + +#define TZIC1_FCR1_ALL (0x000FFFFFUL) +#define TZIC1_FCR2_ALL (0x000001FFUL) +#define TZIC1_FCR3_ALL (0x007FFFFFUL) +#define TZIC1_FCR4_ALL (0x3F0FC01FUL) +#endif /* STM32U599xx || STM32U595xx || STM32U5A9xx || STM32U5A5xx */ + +/* TZSC2 / TZIC2 instances */ +#define TZSC2_SECCFGR1_ALL (0x00001BFFUL) + +#define TZSC2_PRIVCFGR1_ALL (0x00001BFFUL) + +#define TZIC2_IER1_ALL (0x00001BFFUL) +#define TZIC2_IER2_ALL (0x0300C07FUL) + +#define TZIC2_FCR1_ALL (0x00001BFFUL) +#define TZIC2_FCR2_ALL (0x0300C07FUL) + +#define REG_SIZE 32U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup GTZC_Private_Macros GTZC Private Macros + * @{ + */ + +#define IS_ADDRESS_IN(mem, address) \ + ( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \ + && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \ + || ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \ + && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) ) + +#define IS_ADDRESS_IN_S(mem, address) \ + ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \ + && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) + +#define IS_ADDRESS_IN_NS(mem, address) \ + ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \ + && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) + +#define GTZC_BASE_ADDRESS(mem)\ + ( mem ## _BASE ) + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup GTZC_Exported_Functions GTZC Exported Functions + * @{ + */ + +/** @defgroup GTZC_Exported_Functions_Group1 TZSC Configuration functions + * @brief TZSC Configuration functions + * + @verbatim + ============================================================================== + ##### TZSC Configuration functions ##### + ============================================================================== + [..] + This section provides functions allowing to configure TZSC + TZSC: TrustZone Security Controller +@endverbatim + * @{ + */ + +/** + * @brief Configure TZSC on a single peripheral or on all peripherals. + * @note Secure and non-secure attributes can only be set from the secure + * state when the system implements the security (TZEN=1). + * @note Privilege and non-privilege attributes can only be set from the + * privilege state when TZEN=0 or TZEN=1 + * @note Security and privilege attributes can be set independently. + * @note Default state is non-secure and unprivileged access allowed. + * @param PeriphId Peripheral identifier + * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId. + * Use GTZC_PERIPH_ALL to select all peripherals. + * @param PeriphAttributes Peripheral attributes, see @ref GTZC_TZSC_PeriphAttributes. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, + uint32_t PeriphAttributes) +{ + uint32_t register_address; + + /* check entry parameters */ + if ((PeriphAttributes > (GTZC_TZSC_PERIPH_SEC | GTZC_TZSC_PERIPH_PRIV)) + || (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER) + || (((PeriphId & GTZC_PERIPH_ALL) != 0U) + && (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) != 0U))) + { + return HAL_ERROR; + } + + if ((PeriphId & GTZC_PERIPH_ALL) != 0U) + { + /* special case where same attributes are applied to all peripherals */ + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* secure configuration */ + if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC) + { + SET_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL); + SET_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL); + SET_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL); + SET_BIT(GTZC_TZSC2->SECCFGR1, TZSC2_SECCFGR1_ALL); + } + else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC) + { + CLEAR_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL); + CLEAR_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL); + CLEAR_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL); + CLEAR_BIT(GTZC_TZSC2->SECCFGR1, TZSC2_SECCFGR1_ALL); + } + else + { + /* do nothing */ + } +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* privilege configuration */ + if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV) + { + SET_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL); + SET_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL); + SET_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL); + SET_BIT(GTZC_TZSC2->PRIVCFGR1, TZSC2_PRIVCFGR1_ALL); + } + else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV) + { + CLEAR_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL); + CLEAR_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL); + CLEAR_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL); + CLEAR_BIT(GTZC_TZSC2->PRIVCFGR1, TZSC2_PRIVCFGR1_ALL); + } + else + { + /* do nothing */ + } + } + else + { + /* common case where only one peripheral is configured */ + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* secure configuration */ + register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->SECCFGR1) + + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId)); + if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC) + { + SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); + } + else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC) + { + CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); + } + else + { + /* do nothing */ + } +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* privilege configuration */ + register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->PRIVCFGR1) + + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId)); + if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV) + { + SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); + } + else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV) + { + CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); + } + else + { + /* do nothing */ + } + } + return HAL_OK; +} + +/** + * @brief Get TZSC configuration on a single peripheral or on all peripherals. + * @param PeriphId Peripheral identifier. + * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId. + * Use GTZC_PERIPH_ALL to select all peripherals. + * @param PeriphAttributes Peripheral attribute pointer. + * This parameter can be a value of @ref GTZC_TZSC_PeriphAttributes. + * If PeriphId target a single peripheral, pointer on a single element. + * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array of + * GTZC_TZSC_PERIPH_NUMBER elements is to be provided. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, + uint32_t *PeriphAttributes) +{ + uint32_t i; + uint32_t reg_value; + uint32_t register_address; + + /* check entry parameters */ + if ((PeriphAttributes == NULL) + || (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER) + || (((PeriphId & GTZC_PERIPH_ALL) != 0U) + && (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) != 0U))) + { + return HAL_ERROR; + } + + if ((PeriphId & GTZC_PERIPH_ALL) != 0U) + { + /* get secure configuration: read each register and deploy each bit value + * of corresponding index in the destination array + */ + reg_value = READ_REG(GTZC_TZSC1->SECCFGR1); + for (i = 0U; i < 32U; i++) + { + if (((reg_value & (1UL << i)) >> i) != 0U) + { + PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC; + } + else + { + PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC; + } + } + + reg_value = READ_REG(GTZC_TZSC1->SECCFGR2); + for (i = 32U; i < 64U; i++) + { + if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U) + { + PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC; + } + else + { + PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC; + } + } + + reg_value = READ_REG(GTZC_TZSC1->SECCFGR3); + for (i = 64U; i < 96U; i++) + { + if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U) + { + PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC; + } + else + { + PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC; + } + } + + reg_value = READ_REG(GTZC_TZSC2->SECCFGR1); + for (i = 96U; i < GTZC_TZSC_PERIPH_NUMBER; i++) + { + if (((reg_value & (1UL << (i - 96U))) >> (i - 96U)) != 0U) + { + PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC; + } + else + { + PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC; + } + } + + /* get privilege configuration: read each register and deploy each bit value + * of corresponding index in the destination array + */ + reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR1); + for (i = 0U; i < 32U; i++) + { + if (((reg_value & (1UL << i)) >> i) != 0U) + { + PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV; + } + else + { + PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV; + } + } + + reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR2); + for (i = 32U; i < 64U; i++) + { + if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U) + { + PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV; + } + else + { + PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV; + } + } + + reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR3); + for (i = 64U; i < 96U; i++) + { + if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U) + { + PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV; + } + else + { + PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV; + } + } + + reg_value = READ_REG(GTZC_TZSC2->PRIVCFGR1); + for (i = 96U; i < GTZC_TZSC_PERIPH_NUMBER; i++) + { + if (((reg_value & (1UL << (i - 96U))) >> (i - 96U)) != 0U) + { + PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV; + } + else + { + PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV; + } + } + } + else + { + /* common case where only one peripheral is configured */ + + /* secure configuration */ + register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->SECCFGR1) + + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId)); + + if (((READ_BIT(*(__IO uint32_t *)register_address, + 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId)) + != 0U) + { + *PeriphAttributes = GTZC_TZSC_PERIPH_SEC; + } + else + { + *PeriphAttributes = GTZC_TZSC_PERIPH_NSEC; + } + + /* privilege configuration */ + register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->PRIVCFGR1) + + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId)); + if (((READ_BIT(*(__IO uint32_t *)register_address, + 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId)) + != 0U) + { + *PeriphAttributes |= GTZC_TZSC_PERIPH_PRIV; + } + else + { + *PeriphAttributes |= GTZC_TZSC_PERIPH_NPRIV; + } + } + return HAL_OK; +} + +/** + * @} + */ + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** @defgroup GTZC_Exported_Functions_Group2 MPCWM Configuration functions + * @brief MPCWM Configuration functions + * + @verbatim + ============================================================================== + ##### MPCWM Configuration functions ##### + ============================================================================== + [..] + This section provides functions allowing to configure MPCWM + MPCWM is Memory Protection Controller WaterMark +@endverbatim + * @{ + */ + +/** + * @brief Configure a TZSC-MPCWM area. + * @param MemBaseAddress WM identifier. + * @param pMPCWM_Desc TZSC-MPCWM descriptor pointer. + * The structure description is available in @ref GTZC_Exported_Types. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, + const MPCWM_ConfigTypeDef *pMPCWM_Desc) +{ + uint32_t register_address; + uint32_t reg_value; + uint32_t size; + /* granularity value depends on selected memory */ + uint32_t granularity = (MemBaseAddress == BKPSRAM_BASE) ? \ + GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1; + + /* check entry parameters */ + if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2) || +#if defined (FMC_BANK3) + (((MemBaseAddress == BKPSRAM_BASE) || (MemBaseAddress == FMC_BANK3)) && +#else + ((MemBaseAddress == BKPSRAM_BASE) && +#endif /* FMC_BANK3 */ + (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2)) || + ((pMPCWM_Desc->Offset % granularity) != 0U) || + ((pMPCWM_Desc->Length % granularity) != 0U)) + { + return HAL_ERROR; + } + + /* check descriptor content vs. memory capacity */ + switch (MemBaseAddress) + { + case OCTOSPI1_BASE: + size = TZSC_MPCWM1_MEM_SIZE; + if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1) + { + register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1AR); + } + else + { + /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2 + * (Parameter already checked) + */ + register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR); + } + break; +#if defined (FMC_BANK1) + case FMC_BANK1: + size = TZSC_MPCWM2_MEM_SIZE; + if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1) + { + register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR); + } + else + { + /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2 + * (Parameter already checked) + */ + register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR); + } + break; +#endif /* FMC_BANK1 */ +#if defined (FMC_BANK3) + case FMC_BANK3: + /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1 + * (Parameter already checked) + */ + size = TZSC_MPCWM3_MEM_SIZE; + register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR); + break; +#endif /* FMC_BANK3 */ + case BKPSRAM_BASE: + /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1 + * (Parameter already checked) + */ + size = TZSC_MPCWM4_MEM_SIZE; + register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR); + break; +#if defined (OCTOSPI2_BASE) + case OCTOSPI2_BASE: + size = TZSC_MPCWM5_MEM_SIZE; + if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1) + { + register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5AR); + } + else + { + /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2 + * (Parameter already checked) + */ + register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR); + } + break; +#endif /* OCTOSPI2_BASE */ +#if defined (HSPI1) + case HSPI1_BASE: + size = TZSC_MPCWM6_MEM_SIZE; + if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1) + { + register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6AR); + } + else + { + /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2 + * (Parameter already checked) + */ + register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6BR); + } + break; +#endif /* HSPI1 */ + default: + return HAL_ERROR; + break; + } + + if ((pMPCWM_Desc->Offset > size) || + ((pMPCWM_Desc->Offset + pMPCWM_Desc->Length) > size)) + { + return HAL_ERROR; + } + + /* Write watermark start and length value */ + reg_value = ((pMPCWM_Desc->Offset / granularity) + << GTZC_TZSC_MPCWMR_SUBZ_START_Pos) & GTZC_TZSC_MPCWMR_SUBZ_START_Msk; + reg_value |= ((pMPCWM_Desc->Length / granularity) + << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk; + MODIFY_REG(*(__IO uint32_t *)register_address, GTZC_TZSC_MPCWMR_SUBZ_START_Msk | \ + GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk, reg_value); + + /* Write watermark configuration value */ + reg_value = (pMPCWM_Desc->Attribute << GTZC_TZSC_MPCWM_CFGR_SEC_Pos) | \ + pMPCWM_Desc->Lock | \ + pMPCWM_Desc->AreaStatus; + MODIFY_REG(*(__IO uint32_t *)(register_address - 4U), (GTZC_TZSC_MPCWM_CFGR_PRIV | GTZC_TZSC_MPCWM_CFGR_SEC | \ + GTZC_TZSC_MPCWM_CFGR_SRLOCK | GTZC_TZSC_MPCWM_CFGR_SREN), \ + reg_value); + + return HAL_OK; +} + +/** + * @brief Get a TZSC-MPCWM area configuration. + * @param MemBaseAddress WM identifier. + * @param pMPCWM_Desc pointer to a TZSC-MPCWM descriptor. + * When the WaterMark memory supports two sub-regions A and B. pMPCWM_Desc argument must point to an array of + * two MPCWM_ConfigTypeDef structures. + * The structure description is available in @ref GTZC_Exported_Types. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, + MPCWM_ConfigTypeDef *pMPCWM_Desc) +{ + uint32_t register_address_regionA; + uint32_t register_address_regionB = 0U; + uint32_t reg_value; + uint32_t granularity = (MemBaseAddress == BKPSRAM_BASE) ? \ + GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1; + + /* Loading the subregion A & B addresses into their specific variables */ + switch (MemBaseAddress) + { + case OCTOSPI1_BASE: + register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM1AR); + register_address_regionB = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR); + break; +#if defined (FMC_BANK1) + case FMC_BANK1: + register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR); + register_address_regionB = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR); + break; +#endif /* FMC_BANK1 */ +#if defined (FMC_BANK3) + case FMC_BANK3: + register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR); + break; +#endif /* FMC_BANK3 */ + case BKPSRAM_BASE: + register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR); + break; +#if defined (OCTOSPI2_BASE) + case OCTOSPI2_BASE: + register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM5AR); + register_address_regionB = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR); + break; +#endif /* OCTOSPI2_BASE */ +#if defined (HSPI1) + case HSPI1_BASE: + register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM6AR); + register_address_regionB = (uint32_t) &(GTZC_TZSC1_S->MPCWM6BR); + break; +#endif /* HSPI1 */ + default: + return HAL_ERROR; + break; + } + + /* read register and update the descriptor for first area*/ + reg_value = READ_REG(*(__IO uint32_t *)register_address_regionA); + pMPCWM_Desc[0].AreaId = GTZC_TZSC_MPCWM_ID1; + pMPCWM_Desc[0].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk) + >> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity; + pMPCWM_Desc[0].Length = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk) + >> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity; + + /* read configuration register and update the descriptor for first area*/ + reg_value = READ_REG(*(__IO uint32_t *)(register_address_regionA - 4U)); + pMPCWM_Desc[0].Attribute = (reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \ + GTZC_TZSC_MPCWM_CFGR_SEC)) >> GTZC_TZSC_MPCWM_CFGR_SEC_Pos; + pMPCWM_Desc[0].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK; + pMPCWM_Desc[0].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN; + + if (register_address_regionB != 0U) + { + /* read register and update the descriptor for second area*/ + reg_value = READ_REG(*(__IO uint32_t *)register_address_regionB); + pMPCWM_Desc[1].AreaId = GTZC_TZSC_MPCWM_ID2; + pMPCWM_Desc[1].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk) + >> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity; + pMPCWM_Desc[1].Length = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk) + >> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity; + + /* read configuration register and update the descriptor for second area*/ + reg_value = READ_REG(*(__IO uint32_t *)(register_address_regionB - 4U)); + pMPCWM_Desc[1].Attribute = (reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \ + GTZC_TZSC_MPCWM_CFGR_SEC)) >> GTZC_TZSC_MPCWM_CFGR_SEC_Pos; + pMPCWM_Desc[1].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK; + pMPCWM_Desc[1].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup GTZC_Exported_Functions_Group3 TZSC Lock functions + * @brief TZSC Lock functions + * + @verbatim + ============================================================================== + ##### TZSC Lock functions ##### + ============================================================================== + [..] + This section provides functions allowing to manage the TZSC (TrustZone + Security Controller) lock. It includes lock enable, and current value read. +@endverbatim + * @{ + */ + +/** + * @brief Lock TZSC configuration. + * @note This function locks the configuration of TZSC_SECCFGRx and TZSC_PRIVCFGRx + * registers until next reset + * @param TZSC_Instance TZSC sub-block instance. + */ +void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance) +{ + SET_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk); +} + +/** + * @brief Get TZSC configuration lock state. + * @param TZSC_Instance TZSC sub-block instance. + * @retval Lock State (GTZC_TZSC_LOCK_OFF or GTZC_TZSC_LOCK_ON) + */ +uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance) +{ + return READ_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk); +} + +/** + * @} + */ +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** @defgroup GTZC_Exported_Functions_Group4 MPCBB Configuration functions + * @brief MPCBB Configuration functions + * + @verbatim + ============================================================================== + ##### MPCBB Configuration functions ##### + ============================================================================== + [..] + This section provides functions allowing to configure MPCBB + MPCBB is Memory Protection Controller Block Base +@endverbatim + * @{ + */ + +/** + * @brief Set a complete MPCBB configuration on the SRAM passed as parameter. + * @param MemBaseAddress MPCBB identifier. + * @param pMPCBB_desc pointer to MPCBB descriptor. + * The structure description is available in @ref GTZC_Exported_Types. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, + const MPCBB_ConfigTypeDef *pMPCBB_desc) +{ + GTZC_MPCBB_TypeDef *mpcbb_ptr; + uint32_t mem_size; + uint32_t size_in_superblocks; + uint32_t i; + + /* check entry parameters */ + if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) + && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) +#if defined (SRAM3_BASE) + && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) +#endif /* SRAM3_BASE */ + && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) +#if defined (SRAM5_BASE) + && !(IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + && !(IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) +#endif /* SRAM6_BASE */ + ) + || ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE) + && (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE)) + || ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED) + && (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED))) + { + return HAL_ERROR; + } + + if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB1; + mem_size = GTZC_MEM_SIZE(SRAM1); + } + else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB2; + mem_size = GTZC_MEM_SIZE(SRAM2); + } +#if defined (SRAM3_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB3; + mem_size = GTZC_MEM_SIZE(SRAM3); + } +#endif /* SRAM3_BASE */ + else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB4; + mem_size = GTZC_MEM_SIZE(SRAM4); + } +#if defined (SRAM5_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB5; + mem_size = GTZC_MEM_SIZE(SRAM5); + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB6; + mem_size = GTZC_MEM_SIZE(SRAM6); + } +#endif /* SRAM6_BASE */ + else + { + return HAL_ERROR; + } + + /* translate mem_size in number of super-blocks */ + size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE); + + /* write PRIVCFGR register information */ + for (i = 0U; i < size_in_superblocks; i++) + { + WRITE_REG(mpcbb_ptr->PRIVCFGR[i], + pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i]); + } + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t size_mask; + uint32_t reg_value; + + /* write SECCFGR register information */ + for (i = 0U; i < size_in_superblocks; i++) + { + WRITE_REG(mpcbb_ptr->SECCFGR[i], + pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]); + } + +#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk) + if (size_in_superblocks >= 32U) + { + size_mask = 0xFFFFFFFFU; + MODIFY_REG(mpcbb_ptr->CFGLOCKR2, 0x000FFFFFUL, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[1]); + } + else +#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */ + { + size_mask = (1UL << (size_in_superblocks & 0x1FU)) - 1U; + } + /* limitation: code not portable with memory > 512K */ + MODIFY_REG(mpcbb_ptr->CFGLOCKR1, size_mask, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0]); + + /* write InvertSecureState and SecureRWIllegalMode properties */ + reg_value = pMPCBB_desc->InvertSecureState; + reg_value |= pMPCBB_desc->SecureRWIllegalMode; + + /* write configuration and lock register information */ + MODIFY_REG(mpcbb_ptr->CR, + GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value); +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + return HAL_OK; +} + +/** + * @brief Get a complete MPCBB configuration on the SRAM passed as parameter. + * @param MemBaseAddress MPCBB identifier. + * @param pMPCBB_desc pointer to a MPCBB descriptor. + * The structure description is available in @ref GTZC_Exported_Types. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, + MPCBB_ConfigTypeDef *pMPCBB_desc) +{ + GTZC_MPCBB_TypeDef *mpcbb_ptr; + uint32_t mem_size; + uint32_t size_in_superblocks; + uint32_t i; + + /* check entry parameters */ + if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) + && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) +#if defined (SRAM3_BASE) + && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) +#endif /* SRAM3_BASE */ + && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) +#if defined (SRAM5_BASE) + && !(IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + && !(IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) +#endif /* SRAM6_BASE */ + ) + { + return HAL_ERROR; + } + + /* read InvertSecureState and SecureRWIllegalMode properties */ + /* assume their Position/Mask is identical for all sub-blocks */ + if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB1; + mem_size = GTZC_MEM_SIZE(SRAM1); + } + else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB2; + mem_size = GTZC_MEM_SIZE(SRAM2); + } +#if defined (SRAM3_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB3; + mem_size = GTZC_MEM_SIZE(SRAM3); + } +#endif /* SRAM3_BASE */ + else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB4; + mem_size = GTZC_MEM_SIZE(SRAM4); + } +#if defined (SRAM5_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB5; + mem_size = GTZC_MEM_SIZE(SRAM5); + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB6; + mem_size = GTZC_MEM_SIZE(SRAM6); + } +#endif /* SRAM6_BASE */ + else + { + return HAL_ERROR; + } + + /* translate mem_size in number of super-blocks */ + size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE); + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t reg_value; + + /* read configuration and lock register information */ + reg_value = READ_REG(mpcbb_ptr->CR); + pMPCBB_desc->InvertSecureState = (reg_value & GTZC_MPCBB_CR_INVSECSTATE_Msk); + pMPCBB_desc->SecureRWIllegalMode = (reg_value & GTZC_MPCBB_CR_SRWILADIS_Msk); + + /* limitation: code not portable with memory > 512K */ + pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->CFGLOCKR1); + +#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk) + pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[1] = READ_REG(mpcbb_ptr->CFGLOCKR2); +#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */ + +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* read SECCFGR / PRIVCFGR registers information */ + for (i = 0U; i < size_in_superblocks; i++) + { + pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i] = mpcbb_ptr->SECCFGR[i]; + pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i] = mpcbb_ptr->PRIVCFGR[i]; + } + + return HAL_OK; +} + +/** + * @brief Set a MPCBB attribute configuration on the SRAM passed as parameter + * for a number of blocks. + * @param MemAddress MPCBB identifier, and start block to configure + * (must be 512 Bytes aligned). + * @param NbBlocks Number of blocks to configure + * (Block size is 512 Bytes). + * @param pMemAttributes pointer to an array (containing "NbBlocks" elements), + * with each element must be GTZC_MPCBB_BLOCK_NSEC or GTZC_MPCBB_BLOCK_SEC, + * and GTZC_MPCBB_BLOCK_NPRIV or GTZC_MPCBB_BLOCK_PRIV. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, + uint32_t NbBlocks, + const uint32_t *pMemAttributes) +{ + GTZC_MPCBB_TypeDef *mpcbb_ptr; + uint32_t base_address; + uint32_t end_address; + uint32_t block_start; + uint32_t offset_reg_start; + uint32_t offset_bit_start; + uint32_t i; + uint32_t do_attr_change; + + /* firstly check that MemAddress is well 512 Bytes aligned */ + if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U) + { + return HAL_ERROR; + } + + /* check entry parameters and deduce physical base address */ + end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U; + if (((IS_ADDRESS_IN_NS(SRAM1, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM1, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB1; + base_address = SRAM1_BASE_NS; + } + else if (((IS_ADDRESS_IN_S(SRAM1, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM1, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB1; + base_address = SRAM1_BASE_S; + } + else if (((IS_ADDRESS_IN_NS(SRAM2, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM2, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB2; + base_address = SRAM2_BASE_NS; + } + else if (((IS_ADDRESS_IN_S(SRAM2, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM2, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB2; + base_address = SRAM2_BASE_S; + } +#if defined (SRAM3_BASE) + else if (((IS_ADDRESS_IN_NS(SRAM3, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM3, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB3; + base_address = SRAM3_BASE_NS; + } + else if (((IS_ADDRESS_IN_S(SRAM3, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM3, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB3; + base_address = SRAM3_BASE_S; + } +#endif /* SRAM3_BASE */ + else if (((IS_ADDRESS_IN_NS(SRAM4, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM4, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB4; + base_address = SRAM4_BASE_NS; + } + else if (((IS_ADDRESS_IN_S(SRAM4, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM4, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB4; + base_address = SRAM4_BASE_S; + } +#if defined (SRAM5_BASE) + else if (((IS_ADDRESS_IN_NS(SRAM5, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM5, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB5; + base_address = SRAM5_BASE_NS; + } + else if (((IS_ADDRESS_IN_S(SRAM5, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM5, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB5; + base_address = SRAM5_BASE_S; + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if (((IS_ADDRESS_IN_NS(SRAM6, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM6, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB6; + base_address = SRAM6_BASE_NS; + } + else if (((IS_ADDRESS_IN_S(SRAM6, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM6, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB6; + base_address = SRAM6_BASE_S; + } +#endif /* SRAM6_BASE */ + else + { + return HAL_ERROR; + } + + /* get start coordinates of the configuration */ + block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE; + offset_reg_start = block_start / 32U; + offset_bit_start = block_start % 32U; + + for (i = 0U; i < NbBlocks; i++) + { + /* Indicate change done for protection attributes */ + do_attr_change = 0U; + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* secure configuration */ + if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_SEC) == GTZC_MPCBB_BLOCK_SEC) + { + SET_BIT(mpcbb_ptr->SECCFGR[offset_reg_start], + 1UL << (offset_bit_start % 32U)); + do_attr_change = 1U; + } + else if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_NSEC) == GTZC_MPCBB_BLOCK_NSEC) + { + CLEAR_BIT(mpcbb_ptr->SECCFGR[offset_reg_start], + 1UL << (offset_bit_start % 32U)); + do_attr_change = 1U; + } + else + { + /* nothing to do */ + } +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* privilege configuration */ + if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_PRIV) == GTZC_MPCBB_BLOCK_PRIV) + { + SET_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start], + 1UL << (offset_bit_start % 32U)); + } + else if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_NPRIV) == GTZC_MPCBB_BLOCK_NPRIV) + { + CLEAR_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start], + 1UL << (offset_bit_start % 32U)); + } + else + { + /* if no change is done for security and privilege attributes: break the loop */ + if (do_attr_change == 0U) + { + break; + } + } + + offset_bit_start++; + if (offset_bit_start == 32U) + { + offset_bit_start = 0U; + offset_reg_start++; + } + } + + /* an unexpected value in pMemAttributes array leads to error status */ + if (i != NbBlocks) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Get a MPCBB attribute configuration on the SRAM passed as parameter + * for a number of blocks. + * @param MemAddress MPCBB identifier, and start block to get configuration + * (must be 512 Bytes aligned). + * @param NbBlocks Number of blocks to get configuration. + * @param pMemAttributes pointer to an array (containing "NbBlocks" elements), + * with each element will be GTZC_MPCBB_BLOCK_NSEC or GTZC_MPCBB_BLOCK_SEC, + * and GTZC_MPCBB_BLOCK_NPRIV or GTZC_MPCBB_BLOCK_PRIV. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, + uint32_t NbBlocks, + uint32_t *pMemAttributes) +{ + GTZC_MPCBB_TypeDef *mpcbb_ptr; + uint32_t base_address; + uint32_t end_address; + uint32_t block_start; + uint32_t offset_reg_start; + uint32_t offset_bit_start; + uint32_t i; + + /* firstly check that MemAddress is well 512 Bytes aligned */ + if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U) + { + return HAL_ERROR; + } + + /* check entry parameters and deduce physical base address */ + end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U; + if ((IS_ADDRESS_IN_NS(SRAM1, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM1, end_address))) + { + mpcbb_ptr = GTZC_MPCBB1_NS; + base_address = SRAM1_BASE_NS; + } + else if ((IS_ADDRESS_IN_S(SRAM1, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM1, end_address))) + { + mpcbb_ptr = GTZC_MPCBB1_S; + base_address = SRAM1_BASE_S; + } + else if ((IS_ADDRESS_IN_NS(SRAM2, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM2, end_address))) + { + mpcbb_ptr = GTZC_MPCBB2_NS; + base_address = SRAM2_BASE_NS; + } + else if ((IS_ADDRESS_IN_S(SRAM2, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM2, end_address))) + { + mpcbb_ptr = GTZC_MPCBB2_S; + base_address = SRAM2_BASE_S; + } +#if defined (SRAM3_BASE) + else if ((IS_ADDRESS_IN_NS(SRAM3, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM3, end_address))) + { + mpcbb_ptr = GTZC_MPCBB3_NS; + base_address = SRAM3_BASE_NS; + } + else if ((IS_ADDRESS_IN_S(SRAM3, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM3, end_address))) + { + mpcbb_ptr = GTZC_MPCBB3_S; + base_address = SRAM3_BASE_S; + } +#endif /* SRAM3_BASE */ + else if ((IS_ADDRESS_IN_NS(SRAM4, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM4, end_address))) + { + mpcbb_ptr = GTZC_MPCBB4_NS; + base_address = SRAM4_BASE_NS; + } + else if ((IS_ADDRESS_IN_S(SRAM4, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM4, end_address))) + { + mpcbb_ptr = GTZC_MPCBB4_S; + base_address = SRAM4_BASE_S; + } +#if defined (SRAM5_BASE) + else if ((IS_ADDRESS_IN_NS(SRAM5, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM5, end_address))) + { + mpcbb_ptr = GTZC_MPCBB5_NS; + base_address = SRAM5_BASE_NS; + } + else if ((IS_ADDRESS_IN_S(SRAM5, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM5, end_address))) + { + mpcbb_ptr = GTZC_MPCBB5_S; + base_address = SRAM5_BASE_S; + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if ((IS_ADDRESS_IN_NS(SRAM6, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM6, end_address))) + { + mpcbb_ptr = GTZC_MPCBB6_NS; + base_address = SRAM6_BASE_NS; + } + else if ((IS_ADDRESS_IN_S(SRAM6, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM6, end_address))) + { + mpcbb_ptr = GTZC_MPCBB6_S; + base_address = SRAM6_BASE_S; + } +#endif /* SRAM6_BASE */ + else + { + return HAL_ERROR; + } + + /* get start coordinates of the configuration */ + block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE; + offset_reg_start = block_start / 32U; + offset_bit_start = block_start % 32U; + + for (i = 0U; i < NbBlocks; i++) + { + pMemAttributes[i] = (READ_BIT(mpcbb_ptr->SECCFGR[offset_reg_start], + 1UL << (offset_bit_start % 32U)) + >> (offset_bit_start % 32U)) | GTZC_ATTR_SEC_MASK; + pMemAttributes[i] |= ((READ_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start], + 1UL << (offset_bit_start % 32U)) + >> (offset_bit_start % 32U)) << 1U) | GTZC_ATTR_PRIV_MASK; + + offset_bit_start++; + if (offset_bit_start == 32U) + { + offset_bit_start = 0U; + offset_reg_start++; + } + } + + return HAL_OK; +} + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock MPCBB super-blocks on the SRAM passed as parameter. + * @param MemAddress MPCBB start-address of super-block to configure + * (must be 16KBytes aligned). + * @param NbSuperBlocks Number of super-blocks to configure. + * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements), + * with for each element: + * value 0 super-block is unlocked, value 1 super-block is locked + * (corresponds to GTZC_MPCBB_SUPERBLOCK_UNLOCKED and + * GTZC_MPCBB_SUPERBLOCK_LOCKED values). + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, + uint32_t NbSuperBlocks, + const uint32_t *pLockAttributes) +{ + __IO uint32_t *reg_mpcbb; + uint32_t base_address; + uint32_t superblock_start; + uint32_t offset_bit_start; + uint32_t i = 0U; + + /* firstly check that MemAddress is well 16KBytes aligned */ + if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U) + { + return HAL_ERROR; + } + + /* check entry parameters */ + if ((IS_ADDRESS_IN(SRAM1, MemAddress)) + && (IS_ADDRESS_IN(SRAM1, (MemAddress + + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM1); + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCKR1; + } + else if ((IS_ADDRESS_IN(SRAM2, MemAddress)) + && (IS_ADDRESS_IN(SRAM2, (MemAddress + + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM2); + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCKR1; + } +#if defined (SRAM3_BASE) + else if ((IS_ADDRESS_IN(SRAM3, MemAddress)) + && (IS_ADDRESS_IN(SRAM3, (MemAddress + + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM3); + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB3_S->CFGLOCKR1; + } +#endif /* SRAM3_BASE */ + else if ((IS_ADDRESS_IN(SRAM4, MemAddress)) + && (IS_ADDRESS_IN(SRAM4, (MemAddress + + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM4); + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB4_S->CFGLOCKR1; + } +#if defined (SRAM5_BASE) + else if ((IS_ADDRESS_IN(SRAM5, MemAddress)) + && (IS_ADDRESS_IN(SRAM5, (MemAddress + + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM5); + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB5_S->CFGLOCKR1; + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if ((IS_ADDRESS_IN(SRAM6, MemAddress)) + && (IS_ADDRESS_IN(SRAM6, (MemAddress + + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM6); + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB6_S->CFGLOCKR1; + } +#endif /* SRAM6_BASE */ + else + { + return HAL_ERROR; + } + + /* get start coordinates of the configuration */ + superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE; + offset_bit_start = superblock_start % 32U; + + /* First 32 super-blocks */ + while ((i < NbSuperBlocks) && (i < 32U) && (superblock_start < 32U)) + { + if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_LOCKED) + { + SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U)); + } + else if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_UNLOCKED) + { + CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U)); + } + else + { + break; + } + + offset_bit_start++; + i++; + } + +#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk) + if ((NbSuperBlocks > 32U) || (superblock_start >= 32U)) + { + /* Point to second configuration lock register */ + reg_mpcbb++; + + /* Remaining super-blocks */ + for (; i < NbSuperBlocks; i++) + { + if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_LOCKED) + { + SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U)); + } + else if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_UNLOCKED) + { + CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U)); + } + else + { + break; + } + + offset_bit_start++; + } + } +#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */ + + /* an unexpected value in pLockAttributes array leads to an error status */ + if (i != NbSuperBlocks) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Get MPCBB super-blocks lock configuration on the SRAM passed as parameter. + * @param MemAddress MPCBB start-address of super-block to get configuration + * (must be 16KBytes aligned). + * @param NbSuperBlocks Number of super-blocks to get configuration. + * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements), + * with for each element: + * value 0 super-block is unlocked, value 1 super-block is locked + * (corresponds to GTZC_MPCBB_SUPERBLOCK_UNLOCKED and + * GTZC_MPCBB_SUPERBLOCK_LOCKED values). + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, + uint32_t NbSuperBlocks, + uint32_t *pLockAttributes) +{ + __IO uint32_t *reg_mpcbb; + uint32_t base_address; + uint32_t superblock_start; + uint32_t offset_bit_start; + uint32_t i = 0U; + + /* firstly check that MemAddress is well 16KBytes aligned */ + if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U) + { + return HAL_ERROR; + } + + /* check entry parameters */ + if ((IS_ADDRESS_IN(SRAM1, MemAddress)) + && (IS_ADDRESS_IN(SRAM1, (MemAddress + + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM1); + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCKR1; + } + else if ((IS_ADDRESS_IN(SRAM2, MemAddress)) + && (IS_ADDRESS_IN(SRAM2, (MemAddress + + (NbSuperBlocks + * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM2); + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCKR1; + } +#if defined (SRAM3_BASE) + else if ((IS_ADDRESS_IN(SRAM3, MemAddress)) + && (IS_ADDRESS_IN(SRAM3, (MemAddress + + (NbSuperBlocks + * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM3); + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB3_S->CFGLOCKR1; + } +#endif /* SRAM3_BASE */ + else if ((IS_ADDRESS_IN(SRAM4, MemAddress)) + && (IS_ADDRESS_IN(SRAM4, (MemAddress + + (NbSuperBlocks + * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM4); + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB4_S->CFGLOCKR1; + } +#if defined (SRAM5_BASE) + else if ((IS_ADDRESS_IN(SRAM5, MemAddress)) + && (IS_ADDRESS_IN(SRAM5, (MemAddress + + (NbSuperBlocks + * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM5); + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB5_S->CFGLOCKR1; + } +#endif /* SRAM5_BASE */ + +#if defined (SRAM6_BASE) + else if ((IS_ADDRESS_IN(SRAM6, MemAddress)) + && (IS_ADDRESS_IN(SRAM6, (MemAddress + + (NbSuperBlocks + * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM6); + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB6_S->CFGLOCKR1; + } +#endif /* SRAM6_BASE */ + else + { + return HAL_ERROR; + } + + /* Get start coordinates of the configuration */ + superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE; + offset_bit_start = superblock_start % 32U; + + while ((i < NbSuperBlocks) && (i < 32U) && (superblock_start < 32U)) + { + pLockAttributes[i] = ((*reg_mpcbb) & (1UL << (offset_bit_start % 32U))) + >> (offset_bit_start % 32U); + offset_bit_start++; + i++; + } + +#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk) + if ((NbSuperBlocks > 32U) || (superblock_start >= 32U)) + { + /* Point to second configuration lock register */ + reg_mpcbb++; + + /* Remaining super-blocks */ + for (; i < NbSuperBlocks; i++) + { + pLockAttributes[i] = ((*reg_mpcbb) & (1UL << (offset_bit_start % 32U))) + >> (offset_bit_start % 32U); + offset_bit_start++; + } + } +#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */ + + return HAL_OK; +} + +/** + * @brief Lock a MPCBB configuration on the SRAM base address passed as parameter. + * @note This functions locks the control register of the MPCBB until next reset. + * @param MemBaseAddress MPCBB identifier. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress) +{ + /* check entry parameters */ + if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) + { + SET_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } + else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) + { + SET_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } +#if defined (SRAM3_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) + { + SET_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } +#endif /* SRAM3_BASE*/ + else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) + { + SET_BIT(GTZC_MPCBB4_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } +#if defined (SRAM5_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) + { + SET_BIT(GTZC_MPCBB5_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) + { + SET_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } +#endif /* SRAM6_BASE */ + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Get MPCBB configuration lock state on the SRAM base address passed as parameter. + * @param MemBaseAddress MPCBB identifier. + * @param pLockState pointer to Lock State (GTZC_MPCBB_LOCK_OFF or GTZC_MPCBB_LOCK_ON). + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, + uint32_t *pLockState) +{ + /* check entry parameters */ + if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) + { + *pLockState = READ_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } + else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) + { + *pLockState = READ_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } +#if defined (SRAM3_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) + { + *pLockState = READ_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } +#endif /* SRAM3_BASE */ + else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) + { + *pLockState = READ_BIT(GTZC_MPCBB4_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } +#if defined (SRAM5_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) + { + *pLockState = READ_BIT(GTZC_MPCBB5_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) + { + *pLockState = READ_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } +#endif /* SRAM6_BASE */ + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup GTZC_Exported_Functions_Group5 TZIC Configuration and Control functions + * @brief TZIC Configuration and Control functions + * + @verbatim + ============================================================================== + ##### TZIC Configuration and Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to configure and control TZIC + TZIC is Trust Zone Interrupt Controller +@endverbatim + * @{ + */ + +/** + * @brief Disable the interrupt associated to a single TZIC peripheral or on all peripherals. + * @param PeriphId Peripheral identifier. + * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId. + * Use GTZC_PERIPH_ALL to select all peripherals. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId) +{ + uint32_t register_address; + + /* check entry parameters */ + if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER) + || (((PeriphId & GTZC_PERIPH_ALL) != 0U) + && (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U))) + { + return HAL_ERROR; + } + + if ((PeriphId & GTZC_PERIPH_ALL) != 0U) + { + /* same configuration is applied to all peripherals */ + WRITE_REG(GTZC_TZIC1->IER1, 0U); + WRITE_REG(GTZC_TZIC1->IER2, 0U); + WRITE_REG(GTZC_TZIC1->IER3, 0U); + WRITE_REG(GTZC_TZIC1->IER4, 0U); + WRITE_REG(GTZC_TZIC2->IER1, 0U); + WRITE_REG(GTZC_TZIC2->IER2, 0U); + } + else + { + /* common case where only one peripheral is configured */ + register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->IER1) + + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId)); + CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); + } + + return HAL_OK; +} + +/** + * @brief Enable the interrupt associated to a single TZIC peripheral or on all peripherals. + * @param PeriphId Peripheral identifier. + * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId. + * Use GTZC_PERIPH_ALL to select all peripherals. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId) +{ + uint32_t register_address; + + /* check entry parameters */ + if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER) + || (((PeriphId & GTZC_PERIPH_ALL) != 0U) + && (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U))) + { + return HAL_ERROR; + } + + if ((PeriphId & GTZC_PERIPH_ALL) != 0U) + { + /* same configuration is applied to all peripherals */ + WRITE_REG(GTZC_TZIC1->IER1, TZIC1_IER1_ALL); + WRITE_REG(GTZC_TZIC1->IER2, TZIC1_IER2_ALL); + WRITE_REG(GTZC_TZIC1->IER3, TZIC1_IER3_ALL); + WRITE_REG(GTZC_TZIC1->IER4, TZIC1_IER4_ALL); + WRITE_REG(GTZC_TZIC2->IER1, TZIC2_IER1_ALL); + WRITE_REG(GTZC_TZIC2->IER2, TZIC2_IER2_ALL); + } + else + { + /* common case where only one peripheral is configured */ + register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->IER1) + + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId)); + SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); + } + + return HAL_OK; +} + +/** + * @brief Get TZIC flag on a single TZIC peripheral or on all peripherals. + * @param PeriphId Peripheral identifier. + * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId. + * Use GTZC_PERIPH_ALL to select all peripherals. + * @param pFlag Pointer to the flags. + * If PeriphId target a single peripheral, pointer on a single element. + * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array + * of GTZC_TZIC_PERIPH_NUMBER elements. + * Element content is either GTZC_TZIC_NO_ILA_EVENT + * or GTZC_TZSC_ILA_EVENT_PENDING. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag) +{ + uint32_t i; + uint32_t reg_value; + uint32_t register_address; + + /* check entry parameters */ + if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER) + || (((PeriphId & GTZC_PERIPH_ALL) != 0U) + && (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U))) + { + return HAL_ERROR; + } + + if ((PeriphId & GTZC_PERIPH_ALL) != 0U) + { + /* special case where it is applied to all peripherals */ + reg_value = READ_REG(GTZC_TZIC1->SR1); + for (i = 0U; i < REG_SIZE; i++) + { + pFlag[i] = (reg_value & (1UL << i)) >> i; + } + + reg_value = READ_REG(GTZC_TZIC1->SR2); + for (i = REG_SIZE; i < (2U * REG_SIZE); i++) + { + pFlag[i] = (reg_value & (1UL << (i - 32U))) >> (i - 32U); + } + + reg_value = READ_REG(GTZC_TZIC1->SR3); + for (i = 2U * REG_SIZE; i < (3U * REG_SIZE); i++) + { + pFlag[i] = (reg_value & (1UL << (i - 64U))) >> (i - 64U); + } + + reg_value = READ_REG(GTZC_TZIC1->SR4); + for (i = 3U * REG_SIZE; i < (4U * REG_SIZE); i++) + { + pFlag[i] = (reg_value & (1UL << (i - 96U))) >> (i - 96U); + } + + reg_value = READ_REG(GTZC_TZIC2->SR1); + for (i = 4U * REG_SIZE; i < (5U * REG_SIZE); i++) + { + pFlag[i] = (reg_value & (1UL << (i - 128U))) >> (i - 128U); + } + + reg_value = READ_REG(GTZC_TZIC2->SR2); + for (i = 5U * REG_SIZE; i < GTZC_TZIC_PERIPH_NUMBER; i++) + { + pFlag[i] = (reg_value & (1UL << (i - 160U))) >> (i - 160U); + } + } + else + { + /* common case where only one peripheral is concerned */ + register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->SR1) + + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId)); + *pFlag = READ_BIT(*(__IO uint32_t *)register_address, + 1UL << GTZC_GET_PERIPH_POS(PeriphId)) >> GTZC_GET_PERIPH_POS(PeriphId); + } + + return HAL_OK; +} + +/** + * @brief Clear TZIC flag on a single TZIC peripheral or on all peripherals. + * @param PeriphId Peripheral identifier. + * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId. + * Use GTZC_PERIPH_ALL to select all peripherals. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId) +{ + uint32_t register_address; + + /* check entry parameters */ + if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER) + || (((PeriphId & GTZC_PERIPH_ALL) != 0U) + && (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U))) + { + return HAL_ERROR; + } + + if ((PeriphId & GTZC_PERIPH_ALL) != 0U) + { + /* same configuration is applied to all peripherals */ + WRITE_REG(GTZC_TZIC1->FCR1, TZIC1_FCR1_ALL); + WRITE_REG(GTZC_TZIC1->FCR2, TZIC1_FCR2_ALL); + WRITE_REG(GTZC_TZIC1->FCR3, TZIC1_FCR3_ALL); + WRITE_REG(GTZC_TZIC1->FCR4, TZIC1_FCR4_ALL); + WRITE_REG(GTZC_TZIC2->FCR1, TZIC2_FCR1_ALL); + WRITE_REG(GTZC_TZIC2->FCR2, TZIC2_FCR2_ALL); + } + else + { + /* common case where only one peripheral is configured */ + register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->FCR1) + + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId)); + SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup GTZC_Exported_Functions_Group6 IRQ related functions + * @brief IRQ related functions + * + @verbatim + ============================================================================== + ##### TZIC IRQ Handler and Callback functions ##### + ============================================================================== + [..] + This section provides functions allowing to treat ISR and provide user callback + @endverbatim + * @{ + */ + +/** + * @brief This function handles GTZC TZIC interrupt request. + * @retval None. + */ +void HAL_GTZC_IRQHandler(void) +{ + uint32_t position; + uint32_t flag; + uint32_t ier_itsources; + uint32_t sr_flags; + + /*********************************************************************/ + /****************************** TZIC1 ******************************/ + /*********************************************************************/ + + /* Get current IT Flags and IT sources value on 1st register of TZIC1 */ + ier_itsources = READ_REG(GTZC_TZIC1_S->IER1); + sr_flags = READ_REG(GTZC_TZIC1_S->SR1); + + /* Get Mask interrupt and then clear them */ + flag = ier_itsources & sr_flags; + if (flag != 0U) + { + WRITE_REG(GTZC_TZIC1_S->FCR1, flag); + + /* Loop on flag to check, which ones have been raised */ + position = 0U; + while ((flag >> position) != 0U) + { + if ((flag & (1UL << position)) != 0U) + { + HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG1 | position); + } + + /* Position bit to be updated */ + position++; + } + } + + /* Get current IT Flags and IT sources value on 2nd register of TZIC1 */ + ier_itsources = READ_REG(GTZC_TZIC1_S->IER2); + sr_flags = READ_REG(GTZC_TZIC1_S->SR2); + + /* Get Mask interrupt and then clear them */ + flag = ier_itsources & sr_flags; + if (flag != 0U) + { + WRITE_REG(GTZC_TZIC1_S->FCR2, flag); + + /* Loop on flag to check, which ones have been raised */ + position = 0U; + while ((flag >> position) != 0U) + { + if ((flag & (1UL << position)) != 0U) + { + HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG2 | position); + } + + /* Position bit to be updated */ + position++; + } + } + + /* Get current IT Flags and IT sources value on 3rd register of TZIC1 */ + ier_itsources = READ_REG(GTZC_TZIC1_S->IER3); + sr_flags = READ_REG(GTZC_TZIC1_S->SR3); + + /* Get Mask interrupt and then clear them */ + flag = ier_itsources & sr_flags; + if (flag != 0U) + { + WRITE_REG(GTZC_TZIC1_S->FCR3, flag); + + /* Loop on flag to check, which ones have been raised */ + position = 0U; + while ((flag >> position) != 0U) + { + if ((flag & (1UL << position)) != 0U) + { + HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG3 | position); + } + + /* Position bit to be updated */ + position++; + } + } + + /* Get current IT Flags and IT sources value on 4th register of TZIC1 */ + ier_itsources = READ_REG(GTZC_TZIC1_S->IER4); + sr_flags = READ_REG(GTZC_TZIC1_S->SR4); + + /* Get Mask interrupt and then clear them */ + flag = ier_itsources & sr_flags; + if (flag != 0U) + { + WRITE_REG(GTZC_TZIC1_S->FCR4, flag); + + /* Loop on flag to check, which ones have been raised */ + position = 0U; + while ((flag >> position) != 0U) + { + if ((flag & (1UL << position)) != 0U) + { + HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG4 | position); + } + + /* Position bit to be updated */ + position++; + } + } + + /*********************************************************************/ + /****************************** TZIC2 ******************************/ + /*********************************************************************/ + + /* Get current IT Flags and IT sources value on 1st register of TZIC2 */ + ier_itsources = READ_REG(GTZC_TZIC2_S->IER1); + sr_flags = READ_REG(GTZC_TZIC2_S->SR1); + + /* Get Mask interrupt and then clear them */ + flag = ier_itsources & sr_flags; + if (flag != 0U) + { + WRITE_REG(GTZC_TZIC2_S->FCR1, flag); + + /* Loop on flag to check, which ones have been raised */ + position = 0U; + while ((flag >> position) != 0U) + { + if ((flag & (1UL << position)) != 0U) + { + HAL_GTZC_TZIC_Callback(GTZC2_PERIPH_REG1 | position); + } + + /* Position bit to be updated */ + position++; + } + } + + /* Get current IT Flags and IT sources value on 2nd register of TZIC2 */ + ier_itsources = READ_REG(GTZC_TZIC2_S->IER2); + sr_flags = READ_REG(GTZC_TZIC2_S->SR2); + + /* Get Mask interrupt and then clear them */ + flag = ier_itsources & sr_flags; + if (flag != 0U) + { + WRITE_REG(GTZC_TZIC2_S->FCR2, flag); + + /* Loop on flag to check, which ones have been raised */ + position = 0U; + while ((flag >> position) != 0U) + { + if ((flag & (1UL << position)) != 0U) + { + HAL_GTZC_TZIC_Callback(GTZC2_PERIPH_REG2 | position); + } + + /* Position bit to be updated */ + position++; + } + } +} + +/** + * @brief GTZC TZIC sub-block interrupt callback. + * @param PeriphId Peripheral identifier triggering the illegal access. + * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId + * @retval None. + */ +__weak void HAL_GTZC_TZIC_Callback(uint32_t PeriphId) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(PeriphId); + + /* NOTE: This function should not be modified. When the callback is needed, + * the HAL_GTZC_TZIC_Callback is to be implemented in the user file + */ +} + +/** + * @} + */ + +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @} + */ + +#endif /*HAL_GTZC_MODULE_ENABLED*/ + +/** + * @} + */ + +/** + * @} + */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c new file mode 100644 index 000000000..eab49cd8c --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c @@ -0,0 +1,7874 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for + the transmit or receive channel + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx channel + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx channel + + (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, + Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. + + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + + *** Interrupt mode or DMA mode IO sequential operation *** + ========================================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in + no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with + start condition, address and data to transfer without a final stop condition, + an then permit a call the same master sequential interface several times + (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() + or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to + transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to + transfer + if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition + after several call of the same master sequential interface several times + (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or + Receive sequence permit to call the opposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after + each call of the same master sequential + interface. + Usage can, transfer several bytes one by one with a restart with slave address between + each bytes using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic + generation of STOP condition. + + (+) Different sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() + HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction request by master + (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function HAL_I2C_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). + [..] + Use function HAL_I2C_UnRegisterCallback to reset a callback to the default + weak function. + HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). + [..] + By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() + or HAL_I2C_Init() function. + [..] + When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup I2C_Private_Define I2C Private Define + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ +#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + +#define MAX_NBYTE_SIZE 255U +#define SLAVE_ADDR_SHIFT 7U +#define SLAVE_ADDR_MSK 0x06U + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ + (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ + (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) +/*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) +/*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + + +/* Private define to centralize the enable/disable of Interrupts */ +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT + and @ref I2C_XFER_RX_IT */ + +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error + and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */ + +/* Private define Sequential Transfer Options default/reset value */ +#define I2C_NO_OPTION_FRAME (0xFFFF0000U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup I2C_Private_Macro + * @{ + */ +#if defined(HAL_DMA_MODULE_ENABLED) +/* Macro to get remaining data to transfer on DMA side */ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__)) +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +#if defined(HAL_DMA_MODULE_ENABLED) +/* Private functions to handle DMA transfer */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +#endif /* HAL_DMA_MODULE_ENABLED */ + +/* Private functions to handle IT transfer */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + +/* Private functions to handle IT transfer */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); + +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +#if defined(HAL_DMA_MODULE_ENABLED) +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +#endif /* HAL_DMA_MODULE_ENABLED */ + +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); + +/* Private functions to centralize the enable/disable of Interrupts */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + +/* Private function to treat different error callback */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + +/* Private function to flush TXDR register */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + +/* Private function to handle start, restart or stop a transfer */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request); + +/* Private function to Convert Specific options */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Clock Timing + (++) Own Address 1 + (++) Addressing mode (Master, Slave) + (++) Dual Addressing mode + (++) Own Address 2 + (++) Own Address 2 Mask + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + /* Init the I2C Callback settings */ + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + + if (hi2c->MspInitCallback == NULL) + { + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + } + else + { + /* Clear the I2C ADD10 bit */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + (hi2c->Init.OwnAddress2Masks << 8)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + if (hi2c->MspDeInitCallback == NULL) + { + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Initialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User I2C Callback + * To be used instead of the weak predefined callback + * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = pCallback; + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = pCallback; + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = pCallback; + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = pCallback; + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = pCallback; + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an I2C Callback + * I2C callback is redirected to the weak predefined callback + * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register the Slave Address Match I2C Callback + * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Slave Address Match I2C Callback + * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + (++) HAL_I2C_Master_Seq_Transmit_IT() + (++) HAL_I2C_Master_Seq_Receive_IT() + (++) HAL_I2C_Slave_Seq_Transmit_IT() + (++) HAL_I2C_Slave_Seq_Receive_IT() + (++) HAL_I2C_EnableListen_IT() + (++) HAL_I2C_DisableListen_IT() + (++) HAL_I2C_Master_Abort_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + (++) HAL_I2C_Master_Seq_Transmit_DMA() + (++) HAL_I2C_Master_Seq_Receive_DMA() + (++) HAL_I2C_Slave_Seq_Transmit_DMA() + (++) HAL_I2C_Slave_Seq_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_AddrCallback() + (++) HAL_I2C_ListenCpltCallback() + (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_WRITE); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + uint16_t tmpXferCount; + HAL_StatusTypeDef error; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* If 10bit addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Wait until DIR flag is set Transmitter mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until AF flag is set */ + error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart); + + if (error != HAL_OK) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + + tmpXferCount = hi2c->XferCount; + if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U)) + { + /* Reset ErrorCode to NONE */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + } + else + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Wait until DIR flag is reset Receiver mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + /* Check if the Autonomous mode is enabled */ + if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_NO_START_WRITE); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + /* Check if the Autonomous mode is enabled */ + if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_NO_START_READ); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + /* Check if the Autonomous mode is enabled */ + if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, + I2C_GENERATE_NO_START_WRITE); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + /* Check if the Autonomous mode is enabled */ + if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, + I2C_GENERATE_NO_START_READ); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + if (hi2c->XferCount != 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, + (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + do + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + } + + do + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->XferSize = 0U; + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) +{ + uint32_t tickstart; + + __IO uint32_t I2C_Trials = 0UL; + + HAL_StatusTypeDef status = HAL_OK; + + FlagStatus tmp1; + FlagStatus tmp2; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + do + { + /* Generate Start */ + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + + while ((tmp1 == RESET) && (tmp2 == RESET)) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + status = HAL_ERROR; + } + } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + } + else + { + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + } + + /* Increment Trials */ + I2C_Trials++; + + if ((I2C_Trials < Trials) && (status == HAL_ERROR)) + { + status = HAL_OK; + } + + } while (I2C_Trials < Trials); + + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort DMA Xfer if any */ + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + +#if defined(HAL_DMA_MODULE_ENABLED) + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Enable the Address Match interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Disable the Address Match interrupt */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; + + if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM)) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Set State at HAL_I2C_STATE_ABORT */ + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Get current IT Flags and IT sources value */ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + + /* I2C events treatment -------------------------------------*/ + if (hi2c->XferISR != NULL) + { + hi2c->XferISR(hi2c, itflags, itsources); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + uint32_t tmperror; + + /* I2C Bus error interrupt occurred ------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the Error Callback in case of Error detected */ + if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + { + I2C_ITError(hi2c, tmperror); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** + * @brief Return the I2C error code. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + hi2c->XferOptions, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + if (hi2c->Memaddress == 0xFFFFFFFFU) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t tmpITFlags = ITFlags; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, tmpITFlags); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + if (hi2c->XferCount > 0U) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + + if ((hi2c->XferCount == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, tmpITFlags); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Data have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hi2c->XferCount > 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + else + { + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t xfermode; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable TC interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); + + if (hi2c->XferCount != 0U) + { + /* Recover Slave address */ + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + xfermode = hi2c->XferOptions; + } + else + { + xfermode = I2C_AUTOEND_MODE; + } + } + + /* Set the new XferSize in Nbytes register */ + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + if (hi2c->XferCount != 0U) + { + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error and NACK interrupt for data transfer */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t treatdmanack = 0U; + HAL_I2C_StateTypeDef tmpstate; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + /* So clear Flag NACKF only */ + if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || + (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + { + /* Split check of hdmarx, for MISRA compliance */ + if (hi2c->hdmarx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) + { + treatdmanack = 1U; + } + } + } + + /* Split check of hdmatx, for MISRA compliance */ + if (hi2c->hdmatx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) + { + treatdmanack = 1U; + } + } + } + + if (treatdmanack == 1U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else + { + /* Only Clear NACK Flag, no DMA treatment is pending */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TC flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief I2C Address complete process callback. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint8_t transferdirection; + uint16_t slaveaddrcode; + uint16_t ownadd1code; + uint16_t ownadd2code; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(ITFlags); + + /* In case of Listen state, need to inform upper layer of address match code event */ + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + transferdirection = I2C_GET_DIR(hi2c); + slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + + /* If 10bits addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) + { + slaveaddrcode = ownadd1code; + hi2c->AddrEventCount++; + if (hi2c->AddrEventCount == 2U) + { + /* Reset Address Event counter */ + hi2c->AddrEventCount = 0U; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + slaveaddrcode = ownadd2code; + + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* else 7 bits addressing mode is selected */ + else + { + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* Else clear address flag only */ + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief I2C Master sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Slave sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Master complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + __IO uint32_t tmpreg; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Reset handle parameters */ + hi2c->XferISR = NULL; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set acknowledge error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmpreg = (uint8_t)hi2c->Instance->RXDR; + UNUSED(tmpreg); + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Slave complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + uint32_t tmpITFlags = ITFlags; + uint32_t tmpoptions = hi2c->XferOptions; + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else if (tmpstate == HAL_I2C_STATE_LISTEN) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_NONE; + } + else + { + /* Do nothing */ + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + if (hi2c->hdmatx != NULL) + { + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); + } + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); + } + } + else + { + /* Do nothing */ + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if (hi2c->XferSize > 0U) + { + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + } + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ + I2C_ITSlaveSeqCplt(hi2c); + + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Listen complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Reset handle parameters */ + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if (hi2c->XferSize > 0U) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + /* Disable all Interrupts*/ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} + +/** + * @brief I2C interrupts error process. + * @param hi2c I2C handle. + * @param ErrorCode Error code to handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +{ + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + +#if defined(HAL_DMA_MODULE_ENABLED) + uint32_t tmppreviousstate; +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset handle parameters */ + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferCount = 0U; + + /* Set new error code */ + hi2c->ErrorCode |= ErrorCode; + + /* Disable Interrupts */ + if ((tmpstate == HAL_I2C_STATE_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Disable all interrupts, except interrupts related to LISTEN state */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* keep HAL_I2C_STATE_LISTEN if set */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + } + else + { + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If state is an abort treatment on going, don't change state */ + /* This change will be do later */ + if (hi2c->State != HAL_I2C_STATE_ABORT) + { + /* Set HAL_I2C_STATE_READY */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + } + hi2c->XferISR = NULL; + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort DMA TX transfer if any */ + tmppreviousstate = hi2c->PreviousState; + + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + /* Abort DMA RX transfer if any */ + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + I2C_TreatErrorCallback(hi2c); + } +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Tx data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + { + hi2c->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA I2C master transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef dmaxferstatus = HAL_OK; + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + + if (dmaxferstatus != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tmpoptions = hi2c->XferOptions; + + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + + +/** + * @brief DMA I2C master receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef dmaxferstatus = HAL_OK; + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, + hi2c->XferSize); + } + + if (dmaxferstatus != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + + +/** + * @brief DMA I2C slave receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tmpoptions = hi2c->XferOptions; + + if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +} + + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Reset AbortCpltCallback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferAbortCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferAbortCallback = NULL; + } + + I2C_TreatErrorCallback(hi2c); +} + +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief This function handles I2C Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Flag Specifies the I2C flag to check. + * @param Status The actual Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + HAL_StatusTypeDef status = HAL_OK; + + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + + /* Check if a STOPF is detected */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK)) + { + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + status = HAL_OK; + } + + /* Check a no-acknowledge have been detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + status = HAL_ERROR; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + } + + /* Check for the Timeout */ + if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + status = HAL_ERROR; + } + } + } + return status; +} + +/** + * @brief This function handles errors detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t itflag = hi2c->Instance->ISR; + uint32_t error_code = 0; + uint32_t tickstart = Tickstart; + uint32_t tmp1; + HAL_I2C_ModeTypeDef tmp2; + + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) + { + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOP Flag is set or timeout occurred */ + /* AutoEnd should be initiate after AF */ + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); + tmp2 = hi2c->Mode; + + /* In case of I2C still busy, try to regenerate a STOP manually */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ + (tmp1 != I2C_CR2_STOP) && \ + (tmp2 != HAL_I2C_MODE_SLAVE)) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + + /* Update Tick with new reference */ + tickstart = HAL_GetTick(); + } + + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) + { + error_code |= HAL_I2C_ERROR_TIMEOUT; + + status = HAL_ERROR; + + break; + } + } + } + } + } + + /* In case STOP Flag is detected, clear it */ + if (status == HAL_OK) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + error_code |= HAL_I2C_ERROR_AF; + + status = HAL_ERROR; + } + + /* Refresh Content of Status register */ + itflag = hi2c->Instance->ISR; + + /* Then verify if an additional errors occurs */ + /* Check if a Bus error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) + { + error_code |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + + status = HAL_ERROR; + } + + /* Check if an Over-Run/Under-Run error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) + { + error_code |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + + status = HAL_ERROR; + } + + /* Check if an Arbitration Loss error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) + { + error_code |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + + status = HAL_ERROR; + } + + if (status != HAL_OK) + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode |= error_code; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } + + return status; +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hi2c I2C handle. + * @param DevAddress Specifies the slave address to be programmed. + * @param Size Specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_RELOAD_MODE Enable Reload mode . + * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. + * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. + * @param Request New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). + * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. + * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_TRANSFER_MODE(Mode)); + assert_param(IS_TRANSFER_REQUEST(Request)); + + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ + MODIFY_REG(hi2c->Instance->CR2, \ + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP)), tmp); +} + +/** + * @brief Manage the enabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + +#if defined(HAL_DMA_MODULE_ENABLED) + if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ + (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ + (hi2c->XferISR != I2C_Mem_ISR_DMA)) +#endif /* HAL_DMA_MODULE_ENABLED */ + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + } + +#if defined(HAL_DMA_MODULE_ENABLED) + else + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Enable interrupts only at the end */ + /* to avoid the risk of I2C interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_I2C_ENABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Manage the disabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Disable TC and TXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Disable TC and RXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Disable ADDR, NACK and STOP interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_I2C_DISABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +{ + /* if user set XferOptions to I2C_OTHER_FRAME */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to I2C_FIRST_FRAME */ + if (hi2c->XferOptions == I2C_OTHER_FRAME) + { + hi2c->XferOptions = I2C_FIRST_FRAME; + } + /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ + else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + { + hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; + } + else + { + /* Nothing to do */ + } +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c_ex.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c_ex.c new file mode 100644 index 000000000..ef1b495c3 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c_ex.c @@ -0,0 +1,502 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C Extended peripheral: + * + Filter Mode Functions + * + WakeUp Mode Functions + * + FastModePlus Functions + * + Autonomous Mode Functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### I2C peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32U5xx + devices contains the following additional features + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + (+) Disable or enable wakeup from Stop mode(s) + (+) Disable or enable Fast Mode Plus + (+) Configure Autonomous mode + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure Noise Filter and Wake Up Feature + (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + (#) Configure the enable or disable of I2C Wake Up Mode using the functions : + (++) HAL_I2CEx_EnableWakeUp() + (++) HAL_I2CEx_DisableWakeUp() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_I2CEx_ConfigFastModePlus() + (#) Set or get or clear the autonomous mode configuration using these functions : + (++) HAL_I2CEx_SetConfigAutonomousMode() + (++) HAL_I2CEx_GetConfigAutonomousMode() + (++) HAL_I2CEx_ClearConfigAutonomousMode() + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C Extended HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @brief Filter Mode Functions + * +@verbatim + =============================================================================== + ##### Filter Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + +@endverbatim + * @{ + */ + +/** + * @brief Configure I2C Analog noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure I2C Digital noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8U; + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @brief WakeUp Mode Functions + * +@verbatim + =============================================================================== + ##### WakeUp Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Wake Up Feature + +@endverbatim + * @{ + */ + +/** + * @brief Enable I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 |= I2C_CR1_WUPEN; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Configure I2C Fast Mode Plus. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param FastModePlus New state of the Fast Mode Plus. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_FASTMODEPLUS(FastModePlus)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + if (FastModePlus == I2C_FASTMODEPLUS_ENABLE) + { + /* Set I2Cx FMP bit */ + hi2c->Instance->CR1 |= (I2C_CR1_FMP); + } + else + { + /* Reset I2Cx FMP bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_FMP); + } + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group4 Autonomous Mode Functions + * @brief Autonomous Mode Functions + * +@verbatim + =============================================================================== + ##### Autonomous Mode functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Autonomous Mode + +@endverbatim + * @{ + */ + +/** + * @brief Set Autonomous Mode configuration + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param sConfig Pointer to a I2C_AutonomousModeConfTypeDef structure that contains + * the configuration information of the autonomous mode for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, + const I2C_AutonomousModeConfTypeDef *sConfig) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_I2C_TRIG_INPUT_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_TRIG_SOURCE(hi2c->Instance, sConfig->TriggerSelection)); + assert_param(IS_I2C_AUTO_MODE_TRG_POL(sConfig->TriggerPolarity)); + + /* Disable the selected I2C peripheral to be able to configure AUTOCR */ + __HAL_I2C_DISABLE(hi2c); + + /* I2Cx AUTOCR Configuration */ + WRITE_REG(hi2c->Instance->AUTOCR, + (sConfig->TriggerState | \ + ((sConfig->TriggerSelection) & I2C_AUTOCR_TRIGSEL_Msk) | \ + sConfig->TriggerPolarity)); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Get Autonomous Mode configuration + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param sConfig Pointer to a I2C_AutonomousModeConfTypeDef structure that contains + * the configuration information of the autonomous mode for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_GetConfigAutonomousMode(const I2C_HandleTypeDef *hi2c, + I2C_AutonomousModeConfTypeDef *sConfig) +{ + uint32_t autocr_tmp; + + /* Check the parameters */ + assert_param(IS_I2C_TRIG_INPUT_INSTANCE(hi2c->Instance)); + + autocr_tmp = hi2c->Instance->AUTOCR; + + sConfig->TriggerState = (autocr_tmp & I2C_AUTOCR_TRIGEN); + if (IS_I2C_GRP2_INSTANCE(hi2c->Instance)) + { + sConfig->TriggerSelection = ((autocr_tmp & I2C_AUTOCR_TRIGSEL) | I2C_TRIG_GRP2); + } + else + { + sConfig->TriggerSelection = ((autocr_tmp & I2C_AUTOCR_TRIGSEL) | I2C_TRIG_GRP1); + } + sConfig->TriggerPolarity = (autocr_tmp & I2C_AUTOCR_TRIGPOL); + + return HAL_OK; +} + +/** + * @brief Clear Autonomous Mode configuration + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_I2C_TRIG_INPUT_INSTANCE(hi2c->Instance)); + + /* Disable the selected I2C peripheral to be able to clear AUTOCR */ + __HAL_I2C_DISABLE(hi2c); + + CLEAR_REG(hi2c->Instance->AUTOCR); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_icache.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_icache.c new file mode 100644 index 000000000..f0741fcce --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_icache.c @@ -0,0 +1,651 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_icache.c + * @author MCD Application Team + * @brief ICACHE HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Instruction Cache (ICACHE). + * + Initialization and Configuration + * + Invalidate functions + * + Monitoring management + * + Memory address remap management + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### ICACHE main features ##### + ============================================================================== + [..] + The Instruction Cache (ICACHE) is introduced on C-AHB code bus of + Cortex-M33 processor to improve performance when fetching instruction + and data from both internal and external memories. It allows close to + zero wait states performance. + + (+) The ICACHE provides two performance counters (Hit and Miss), + cache invalidate maintenance operation, error management and TrustZone + security support. + + (+) The ICACHE provides additionally the possibility to remap input address + falling into up to four memory regions (used to remap aliased code in + external memories to the internal Code region, for execution) + + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The ICACHE HAL driver can be used as follows: + + (#) Optionally configure the Instruction Cache mode with + HAL_ICACHE_ConfigAssociativityMode() if the default configuration + does not suit the application requirements. + + (#) Enable and disable the Instruction Cache with respectively + HAL_ICACHE_Enable() and HAL_ICACHE_Disable(). + Use HAL_ICACHE_IsEnabled() to get the Instruction Cache status. + To ensure a deterministic cache behavior after power on, system reset or after + a call to @ref HAL_ICACHE_Disable(), the application must call + @ref HAL_ICACHE_WaitForInvalidateComplete(). Indeed on power on, system reset + or cache disable, an automatic cache invalidation procedure is launched and the + cache is bypassed until the operation completes. + + (#) Initiate the cache maintenance invalidation procedure with either + HAL_ICACHE_Invalidate() (blocking mode) or HAL_ICACHE_Invalidate_IT() + (interrupt mode). When interrupt mode is used, the callback function + HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate + procedure is complete. The function HAL_ICACHE_WaitForInvalidateComplete() + may be called to wait for the end of the invalidate procedure automatically + initiated when disabling the Instruction Cache with HAL_ICACHE_Disable(). + The cache operation is bypassed during the invalidation procedure. + + (#) Use the performance monitoring counters for Hit and Miss with the following + functions: HAL_ICACHE_Monitor_Start(), HAL_ICACHE_Monitor_Stop(), + HAL_ICACHE_Monitor_Reset(), HAL_ICACHE_Monitor_GetHitValue() and + HAL_ICACHE_Monitor_GetMissValue() + + (#) Enable and disable up to four regions to remap input address from external + memories to the internal Code region for execution with + HAL_ICACHE_EnableRemapRegion() and HAL_ICACHE_DisableRemapRegion() + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup ICACHE ICACHE + * @brief HAL ICACHE module driver + * @{ + */ +#if defined(ICACHE) && defined (HAL_ICACHE_MODULE_ENABLED) + +/* Private typedef -----------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup ICACHE_Private_Constants ICACHE Private Constants + * @{ + */ +#define ICACHE_INVALIDATE_TIMEOUT_VALUE 1U /* 1ms */ +#define ICACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ICACHE_Private_Macros ICACHE Private Macros + * @{ + */ + +#define IS_ICACHE_ASSOCIATIVITY_MODE(__MODE__) (((__MODE__) == ICACHE_1WAY) || \ + ((__MODE__) == ICACHE_2WAYS)) + +#define IS_ICACHE_MONITOR_TYPE(__TYPE__) (((__TYPE__) == ICACHE_MONITOR_HIT_MISS) || \ + ((__TYPE__) == ICACHE_MONITOR_HIT) || \ + ((__TYPE__) == ICACHE_MONITOR_MISS)) + +#define IS_ICACHE_REGION_NUMBER(__NUMBER__) ((__NUMBER__) < 4U) + +#define IS_ICACHE_REGION_SIZE(__SIZE__) (((__SIZE__) == ICACHE_REGIONSIZE_2MB) || \ + ((__SIZE__) == ICACHE_REGIONSIZE_4MB) || \ + ((__SIZE__) == ICACHE_REGIONSIZE_8MB) || \ + ((__SIZE__) == ICACHE_REGIONSIZE_16MB) || \ + ((__SIZE__) == ICACHE_REGIONSIZE_32MB) || \ + ((__SIZE__) == ICACHE_REGIONSIZE_64MB) || \ + ((__SIZE__) == ICACHE_REGIONSIZE_128MB)) + +#define IS_ICACHE_REGION_TRAFFIC_ROUTE(__TRAFFICROUTE__) (((__TRAFFICROUTE__) == ICACHE_MASTER1_PORT) || \ + ((__TRAFFICROUTE__) == ICACHE_MASTER2_PORT)) + +#define IS_ICACHE_REGION_OUTPUT_BURST_TYPE(__OUTPUTBURSTTYPE_) (((__OUTPUTBURSTTYPE_) == ICACHE_OUTPUT_BURST_WRAP) || \ + ((__OUTPUTBURSTTYPE_) == ICACHE_OUTPUT_BURST_INCR)) + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup ICACHE_Exported_Functions ICACHE Exported Functions + * @{ + */ + +/** @defgroup ICACHE_Exported_Functions_Group1 Initialization and control functions + * @brief Initialization and control functions + * + @verbatim + ============================================================================== + ##### Initialization and control functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize and control the + Instruction Cache (mode, invalidate procedure, performance counters). + @endverbatim + * @{ + */ + +/** + * @brief Configure the Instruction Cache cache associativity mode selection. + * @param AssociativityMode Associativity mode selection + * This parameter can be one of the following values: + * @arg ICACHE_1WAY 1-way cache (direct mapped cache) + * @arg ICACHE_2WAYS 2-ways set associative cache (default) + * @retval HAL status (HAL_OK/HAL_ERROR) + */ +HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ICACHE_ASSOCIATIVITY_MODE(AssociativityMode)); + + /* Check cache is not enabled */ + if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) + { + status = HAL_ERROR; + } + else + { + MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, AssociativityMode); + } + + return status; +} + +/** + * @brief DeInitialize the Instruction Cache. + * @retval HAL status (HAL_OK) + */ +HAL_StatusTypeDef HAL_ICACHE_DeInit(void) +{ + /* Reset interrupt enable value */ + WRITE_REG(ICACHE->IER, 0U); + + /* Clear any pending flags */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); + + /* Disable cache then set default associative mode value */ + CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); + WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL); + + /* Stop monitor and reset monitor values */ + CLEAR_BIT(ICACHE->CR, ICACHE_MONITOR_HIT_MISS); + SET_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); + CLEAR_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); + + /* Reset regions configuration values */ + WRITE_REG(ICACHE->CRR0, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR1, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR2, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR3, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + + return HAL_OK; +} + +/** + * @brief Enable the Instruction Cache. + * @note This function always returns HAL_OK even if there is any ongoing + * cache operation. The Instruction Cache is bypassed until the + * cache operation completes. + * @retval HAL status (HAL_OK) + */ +HAL_StatusTypeDef HAL_ICACHE_Enable(void) +{ + SET_BIT(ICACHE->CR, ICACHE_CR_EN); + + return HAL_OK; +} + +/** + * @brief Disable the Instruction Cache. + * @note This function waits for the cache being disabled but + * not for the end of the automatic cache invalidation procedure. + * @retval HAL status (HAL_OK/HAL_TIMEOUT) + */ +HAL_StatusTypeDef HAL_ICACHE_Disable(void) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* Make sure BSYENDF is reset before to disable the instruction cache */ + /* as it automatically starts a cache invalidation procedure */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + + CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for instruction cache being disabled */ + while (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) + { + if ((HAL_GetTick() - tickstart) > ICACHE_DISABLE_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) + { + status = HAL_TIMEOUT; + break; + } + } + } + + return status; +} + +/** + * @brief Check whether the Instruction Cache is enabled or not. + * @retval Status (0: disabled, 1: enabled) + */ +uint32_t HAL_ICACHE_IsEnabled(void) +{ + return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) ? 1UL : 0UL); +} + +/** + * @brief Invalidate the Instruction Cache. + * @note This function waits for the end of cache invalidation procedure + * and clears the associated BSYENDF flag. + * @retval HAL status (HAL_OK/HAL_ERROR/HAL_TIMEOUT) + */ +HAL_StatusTypeDef HAL_ICACHE_Invalidate(void) +{ + HAL_StatusTypeDef status; + + /* Check if no ongoing operation */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == 0U) + { + /* Launch cache invalidation */ + SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); + } + + status = HAL_ICACHE_WaitForInvalidateComplete(); + + return status; +} + +/** + * @brief Invalidate the Instruction Cache with interrupt. + * @note This function launches cache invalidation and returns. + * User application shall resort to interrupt generation to check + * the end of the cache invalidation with the BSYENDF flag and the + * HAL_ICACHE_InvalidateCompleteCallback() callback. + * @retval HAL status (HAL_OK/HAL_ERROR) + */ +HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check no ongoing operation */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Make sure BSYENDF is reset before to start cache invalidation */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + + /* Enable end of cache invalidation interrupt */ + SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); + + /* Launch cache invalidation */ + SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); + } + + return status; +} + +/** + * @brief Wait for the end of the Instruction Cache invalidate procedure. + * @note This function checks and clears the BSYENDF flag when set. + * @retval HAL status (HAL_OK/HAL_TIMEOUT) + */ +HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* Check if ongoing invalidation operation */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for end of cache invalidation */ + while (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U) + { + if ((HAL_GetTick() - tickstart) > ICACHE_INVALIDATE_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U) + { + status = HAL_TIMEOUT; + break; + } + } + } + } + + /* Clear BSYENDF */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + + return status; +} + + +/** + * @brief Start the Instruction Cache performance monitoring. + * @param MonitorType Monitoring type + * This parameter can be one of the following values: + * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring + * @arg ICACHE_MONITOR_HIT Hit monitoring + * @arg ICACHE_MONITOR_MISS Miss monitoring + * @retval HAL status (HAL_OK) + */ +HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType) +{ + /* Check the parameters */ + assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); + + SET_BIT(ICACHE->CR, MonitorType); + + return HAL_OK; +} + +/** + * @brief Stop the Instruction Cache performance monitoring. + * @note Stopping the monitoring does not reset the values. + * @param MonitorType Monitoring type + * This parameter can be one of the following values: + * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring + * @arg ICACHE_MONITOR_HIT Hit monitoring + * @arg ICACHE_MONITOR_MISS Miss monitoring + * @retval HAL status (HAL_OK) + */ +HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType) +{ + /* Check the parameters */ + assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); + + CLEAR_BIT(ICACHE->CR, MonitorType); + + return HAL_OK; +} + +/** + * @brief Reset the Instruction Cache performance monitoring values. + * @param MonitorType Monitoring type + * This parameter can be one of the following values: + * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring + * @arg ICACHE_MONITOR_HIT Hit monitoring + * @arg ICACHE_MONITOR_MISS Miss monitoring + * @retval HAL status (HAL_OK) + */ +HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType) +{ + /* Check the parameters */ + assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); + + /* Force/Release reset */ + SET_BIT(ICACHE->CR, (MonitorType << 2U)); + CLEAR_BIT(ICACHE->CR, (MonitorType << 2U)); + + return HAL_OK; +} + +/** + * @brief Get the Instruction Cache performance Hit monitoring value. + * @note Upon reaching the 32-bit maximum value, monitor does not wrap. + * @retval Hit monitoring value + */ +uint32_t HAL_ICACHE_Monitor_GetHitValue(void) +{ + return (ICACHE->HMONR); +} + +/** + * @brief Get the Instruction Cache performance Miss monitoring value. + * @note Upon reaching the 32-bit maximum value, monitor does not wrap. + * @retval Miss monitoring value + */ +uint32_t HAL_ICACHE_Monitor_GetMissValue(void) +{ + return (ICACHE->MMONR); +} + +/** + * @} + */ + +/** @defgroup ICACHE_Exported_Functions_Group2 IRQ and callback functions + * @brief IRQ and callback functions + * + @verbatim + ============================================================================== + ##### IRQ and callback functions ##### + ============================================================================== + [..] + This section provides functions allowing to handle ICACHE global interrupt + and the associated callback functions. + @endverbatim + * @{ + */ + +/** + * @brief Handle the Instruction Cache interrupt request. + * @note This function should be called under the ICACHE_IRQHandler(). + * @note This function respectively disables the interrupt and clears the + * flag of any pending flag before calling the associated user callback. + * @retval None + */ +void HAL_ICACHE_IRQHandler(void) +{ + /* Get current interrupt flags and interrupt sources value */ + uint32_t itflags = READ_REG(ICACHE->SR); + uint32_t itsources = READ_REG(ICACHE->IER); + + /* Check Instruction cache Error interrupt flag */ + if (((itflags & itsources) & ICACHE_FLAG_ERROR) != 0U) + { + /* Disable error interrupt */ + CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE); + + /* Clear ERR pending flag */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); + + /* Instruction cache error interrupt user callback */ + HAL_ICACHE_ErrorCallback(); + } + + /* Check Instruction cache BusyEnd interrupt flag */ + if (((itflags & itsources) & ICACHE_FLAG_BUSYEND) != 0U) + { + /* Disable end of cache invalidation interrupt */ + CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); + + /* Clear BSYENDF pending flag */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + + /* Instruction cache busyend interrupt user callback */ + HAL_ICACHE_InvalidateCompleteCallback(); + } +} + +/** + * @brief Cache invalidation complete callback. + */ +__weak void HAL_ICACHE_InvalidateCompleteCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_ICACHE_InvalidateCompleteCallback() should be implemented in the user file + */ +} + +/** + * @brief Error callback. + */ +__weak void HAL_ICACHE_ErrorCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_ICACHE_ErrorCallback() should be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup ICACHE_Exported_Functions_Group3 Memory remapped regions functions + * @brief Memory remapped regions functions + * + @verbatim + ============================================================================== + ##### Memory remapped regions functions ##### + ============================================================================== + [..] + This section provides functions allowing to manage the remapping of + external memories to internal Code for execution. + @endverbatim + * @{ + */ + +/** + * @brief Configure and enable a region for memory remapping. + * @note The Instruction Cache and the region must be disabled. + * @param Region Region number + This parameter can be a value of @arg @ref ICACHE_Region + * @param pRegionConfig Pointer to structure of ICACHE region configuration parameters + * @retval HAL status (HAL_OK/HAL_ERROR) + */ +HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t *p_reg; + uint32_t value; + + /* Check the parameters */ + assert_param(IS_ICACHE_REGION_NUMBER(Region)); + assert_param(IS_ICACHE_REGION_SIZE(pRegionConfig->Size)); + assert_param(IS_ICACHE_REGION_TRAFFIC_ROUTE(pRegionConfig->TrafficRoute)); + assert_param(IS_ICACHE_REGION_OUTPUT_BURST_TYPE(pRegionConfig->OutputBurstType)); + + /* Check cache is not enabled */ + if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Get region control register address */ + p_reg = &(ICACHE->CRR0) + (1U * Region); + + /* Check region is not already enabled */ + if ((*p_reg & ICACHE_CRRx_REN) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Region 2MB: BaseAddress size 8 bits, RemapAddress size 11 bits */ + /* Region 4MB: BaseAddress size 7 bits, RemapAddress size 10 bits */ + /* Region 8MB: BaseAddress size 6 bits, RemapAddress size 9 bits */ + /* Region 16MB: BaseAddress size 5 bits, RemapAddress size 8 bits */ + /* Region 32MB: BaseAddress size 4 bits, RemapAddress size 7 bits */ + /* Region 64MB: BaseAddress size 3 bits, RemapAddress size 6 bits */ + /* Region 128MB: BaseAddress size 2 bits, RemapAddress size 5 bits */ + value = ((pRegionConfig->BaseAddress & 0x1FFFFFFFU) >> 21U) & \ + (0xFFU & ~(pRegionConfig->Size - 1U)); + value |= ((pRegionConfig->RemapAddress >> 5U) & \ + ((uint32_t)(0x7FFU & ~(pRegionConfig->Size - 1U)) << ICACHE_CRRx_REMAPADDR_Pos)); + value |= (pRegionConfig->Size << ICACHE_CRRx_RSIZE_Pos) | pRegionConfig->TrafficRoute | \ + pRegionConfig->OutputBurstType; + *p_reg = (value | ICACHE_CRRx_REN); + } + } + + return status; +} + +/** + * @brief Disable the memory remapping for a predefined region. + * @param Region Region number + This parameter can be a value of @arg @ref ICACHE_Region + * @retval HAL status (HAL_OK/HAL_ERROR) + */ +HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t *p_reg; + + /* Check the parameters */ + assert_param(IS_ICACHE_REGION_NUMBER(Region)); + + /* Check cache is not enabled */ + if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Get region control register address */ + p_reg = &(ICACHE->CRR0) + (1U * Region); + + *p_reg &= ~ICACHE_CRRx_REN; + } + + return status; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ICACHE && HAL_ICACHE_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c new file mode 100644 index 000000000..29304a020 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c @@ -0,0 +1,968 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization/De-Initialization Functions. + * + Peripheral Control Functions. + * + PWR Attributes Functions. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### PWR peripheral overview ##### + ============================================================================== + [..] + (#) The Power control (PWR) provides an overview of the supply architecture + for the different power domains and of the supply configuration + controller. + + (#) Domain architecture overview for the U5 devices: + (+) U5 devices have 2 power domains (CD and SRD). + The core domain (CD) contains a CPU (Cortex-M33), a Flash memory and + some peripherals dedicated for general purpose. The SRD domain + contains the system control and low-power peripherals. + + (#) Every entity has low power mode as described below : + (#) The CPU low power modes are : + (+) CPU CRun. + (+) CPU CSleep. + (+) CPU CStop. + (#) The system low power modes are : + (+) Run. + (+) Stop 0. + (+) Stop 1. + (+) Stop 2. + (+) Stop 3. + (+) Standby. + (+) Shutdown. + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) After startup, power management peripheral is not active by default. Use + __HAL_RCC_PWR_CLK_ENABLE() macro to enable power interface. + + (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions + to enable/disable access to the backup domain (RCC Backup domain control + register RCC_BDCR, RTC registers, TAMP registers, backup registers and + backup SRAM). + + (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event + mode and voltage threshold) in order to set up the Programmed Voltage + Detector, then use HAL_PWR_EnablePVD() and HAL_PWR_DisablePVD() + functions to start and stop the PVD detection. + (+) PVD level can be one of the following values : + (++) 2V0 + (++) 2V2 + (++) 2V4 + (++) 2V5 + (++) 2V6 + (++) 2V8 + (++) 2V9 + (++) External input analog voltage PVD_IN (compared internally to + VREFINT) + + (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions + with the right parameter to configure the wake up pin polarity (Low or + High), the wake up pin selection and to enable and disable it. + + (#) Call HAL_PWR_EnterSLEEPMode() function to enter the CPU in Sleep mode. + Wake-up from Sleep mode could be following to an event or an + interrupt according to low power mode intrinsic request called (__WFI() + or __WFE()). + + (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0 + mode. Wake-up from Stop 0 mode could be following to an event or an + interrupt according to low power mode intrinsic request called (__WFI() + or __WFE()). (Regulator state on U5 devices is managed internally but + regulator parameter is kept for product compatibility). + + (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in + Standby mode. Wake-up from Standby mode can be following only by an + interrupt. + + (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to + enable and disable the Cortex-M33 re-entry in Sleep mode after an + interruption handling is over. + + (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions + to configure the Cortex-M33 to wake-up after any pending event / interrupt + even if it's disabled or has insufficient priority to cause exception + entry. + + (#) Call HAL_PWR_PVD_IRQHandler() under PVD_AVD_IRQHandler() function to + handle the PWR PVD interrupt request. + + (#) Call HAL_PWR_ConfigAttributes() function to configure PWR item secure and + privilege attributes and call HAL_PWR_GetConfigAttributes() function to + get the attribute configuration for the selected item. + + *** PWR HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in PWR HAL driver. + + (+) __HAL_PWR_GET_FLAG() : Get the PWR pending flags. + (+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#if defined (HAL_PWR_MODULE_ENABLED) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup PWR_Private_Defines PWR Private Defines + * @{ + */ + +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +#define PVD_RISING_EDGE (0x01U) /*!< Mask for rising edge set as PVD trigger */ +#define PVD_FALLING_EDGE (0x02U) /*!< Mask for falling edge set as PVD trigger */ +#define PVD_MODE_IT (0x04U) /*!< Mask for interruption yielded by PVD threshold crossing */ +#define PVD_MODE_EVT (0x08U) /*!< Mask for event yielded by PVD threshold crossing */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @brief Initialization and de-Initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and De-Initialization Functions ##### + =============================================================================== + [..] + This section provides functions allowing to deinitialize power peripheral + and to manage backup domain access. + + [..] + After system reset, the backup domain (RCC Backup domain control register + RCC_BDCR, RTC registers, TAMP registers, backup registers and backup SRAM) + is protected against possible unwanted write accesses. + The HAL_PWR_EnableBkUpAccess() function enables the access to the backup + domain. + The HAL_PWR_DisableBkUpAccess() function disables the access to the backup + domain. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitialize the HAL PWR peripheral registers to their default reset + * values. + * @note This functionality is not available in this product. + * The prototype is kept just to maintain compatibility with other + * products. + * @retval None. + */ +void HAL_PWR_DeInit(void) +{ +} + +/** + * @brief Enable access to the backup domain (RCC Backup domain control + * register RCC_BDCR, RTC registers, TAMP registers, backup registers + * and backup SRAM). + * @note After a system reset, the backup domain is protected against + * possible unwanted write accesses. + * @retval None. + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->DBPR, PWR_DBPR_DBP); +} + +/** + * @brief Disable access to the backup domain (RCC Backup domain control + * register RCC_BDCR, RTC registers, TAMP registers, backup registers + * and backup SRAM). + * @retval None. + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->DBPR, PWR_DBPR_DBP); +} +/** + * @} + */ + + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions + * @brief Low power modes configuration functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This section provides functions allowing to control power peripheral. + + *** PVD configuration *** + ========================= + [..] + (+) The PVD can be used to monitor the VDD power supply by comparing it + to a threshold selected by the PVDLS[2:0] bits in the PWR supply + voltage monitoring control register (PWR_SVMCR) and can be enabled by + setting the PVDE bit. + + (+) A PVDO flag is available in the PWR supply voltage monitoring control + register (PWR_SVMCR) to indicate if VDD is higher or lower than the + PVD threshold. This event is internally connected to the EXTI line 16 + and can generate an interrupt if enabled through the EXTI registers. + It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. + + (+) The PVD can remain active in Stop 0, Stop 1, Stop 2 modes, and the PVM + interrupt can wake up from the Stop mode. The PVD is not functional in + Stop 3 mode. + + (+) During Stop 1, Stop 2 and Stop 3 modes, it is possible to set the PVD + in ultra-low-power mode to further reduce the current consumption by + setting the ULPMEN bit in PWR_CR1 register. + + *** Wake-up pin configuration *** + ================================= + [..] + (+) Wake-up pin is used to wake up the system from Stop 3, Standby and + Shutdown mode. + The pin selection is configurable through the WUCR3 register to map + internal signal to wake up pin line. + The pin polarity is configurable through the WUCR2 register to be + active on rising or falling edges. + + (+) There are up to 24 wake-up signals that can be mapped to up to 8 + wake-up lines in the STM32U5 family. + + *** Low Power modes configuration *** + ===================================== + [..] + This section presents 3 principles low-power modes : + (+) Sleep mode : Cortex-M33 is stopped and all PWR domains are remaining + active (powered and clocked). + + (+) Stop 0 mode : Cortex-M33 is stopped, clocks are stopped and the + regulator is running. + + (+) Standby mode : All PWR domains enter DSTANDBY mode and the VCORE + supply regulator is powered off. + + *** Sleep mode *** + ================== + [..] + (+) Entry : + The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode() + function. + + (++) PWR_SLEEPENTRY_WFI : Enter SLEEP mode with WFI instruction. + (++) PWR_SLEEPENTRY_WFE : Enter SLEEP mode with WFE instruction and + clear of pending events before. + (++) PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR: Enter SLEEP mode with WFE instruction and + no clear of pending event before. + + -@@- The Regulator parameter is not used for the STM32U5 family and is + kept as parameter just to maintain compatibility with other families. + + (+) Exit : + According to Sleep entry, any event when entry is __WFE() intrinsic + and any interrupt when entry is __WFI() intrinsic can wake up the + device from Sleep mode. + + *** Stop 0 mode *** + =================== + [..] + The Stop 0 mode is based on the Cortex-M33 Deepsleep mode combined with + the peripheral clock gating. The voltage regulator is configured in main + regulator mode. In Stop 0 mode, all clocks in the VCORE domain are stopped. + The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled. + Some peripherals with the LPBAM capability can switch on HSI16 or MSIS or + MSIK for transferring data. All SRAMs and register contents are preserved, + but the SRAMs can be totally or partially switched off to further reduced + consumption. + The BOR is always available in Stop 0 mode. + + (+) Entry: + The Stop mode is entered using the HAL_PWR_EnterSTOPMode() function + with : + + (++) StopEntry: + (+++) PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + (+++) PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction and + clear of pending events before. + (+++) PWR_STOPENTRY_WFE_NO_EVT_CLEAR: Enter STOP mode with WFE instruction and + no clear of pending event before. + + -@@- The Regulator parameter is not used for the STM32U5 family and is + kept as parameter just to maintain compatibility with other families. + + (+) Exit: + Any EXTI line configured in interrupt mode (the corresponding EXTI + interrupt vector must be enabled in the NVIC). The interrupt source + can be external interrupts or peripherals with wakeup capability. + Any peripheral interrupt occurring when the AHB/APB clocks are present + due to an autonomous peripheral clock request (the peripheral vector + must be enabled in the NVIC). + + *** Standby mode *** + ==================== + [..] + The Standby mode is used to achieve the lowest power consumption with BOR. + The internal regulator is switched off so that the VCORE domain is powered + off. + The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and the HSE crystal + oscillators are also switched off. + The RTC can remain active (Standby mode with RTC, Standby mode without + RTC). + The Brownout reset (BOR) always remains active in Standby mode. + The state of each I/O during Standby mode can be selected by software: + I/O with internal pull-up, internal pull-down or floating. + After entering Standby mode, SRAMs and register contents are lost except + for registers and backup SRAM in the Backup domain and Standby circuitry. + Optionally, the full SRAM2 or 8 Kbytes or 56 Kbytes can be retained in + Standby mode, supplied by the low-power regulator (Standby with RAM2 + retention mode). + The BORL (Brownout reset detector low) can be configured in ultra low + power mode to further reduce power consumption during Standby mode. + The device exits Standby mode upon an external reset (NRST pin), an IWDG + reset, WKUP pin event (configurable rising or falling edge), an RTC event + occurs (alarm, periodic wakeup, timestamp), or a tamper detection. + The system clock after wakeup is MSIS up to 4 MHz. + + (++) Entry: + The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() + function. + + (++) Exit: + WKUPx pin edge, RTC event, external Reset in NRST pin, IWDG Reset, + BOR reset. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the voltage threshold detected by the Programmed Voltage + * Detector (PVD). + * @param pConfigPVD : Pointer to a PWR_PVDTypeDef structure that contains the + * PVD configuration information (PVDLevel and EventMode). + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *pConfigPVD) +{ + /* Check the PVD parameter */ + if (pConfigPVD == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(pConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(pConfigPVD->Mode)); + + /* Set PVDLS[2:0] bits according to PVDLevel value */ + MODIFY_REG(PWR->SVMCR, PWR_SVMCR_PVDLS, pConfigPVD->PVDLevel); + + /* Disable PVD Event/Interrupt */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure the PVD in interrupt mode */ + if ((pConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure the PVD in event mode */ + if ((pConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the PVD in rising edge */ + if ((pConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + /* Configure the PVD in falling edge */ + if ((pConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } + + return HAL_OK; +} + +/** + * @brief Enable the programmable voltage detector (PVD). + * @retval None. + */ +void HAL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_PVDE); +} + +/** + * @brief Disable the programmable voltage detector (PVD). + * @retval None. + */ +void HAL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_PVDE); +} + +/** + * @brief Enable the wake up line functionality. + * @note Wake up lines are used to wake up the system from Stop 3, Standby and + * Shutdown modes. + * @param WakeUpPin : Specifies which wake up line to enable. This parameter + * can be one of PWR_WakeUp_Pins_High_Polarity define + * group where every param select the wake up line, the + * wake up source with high polarity detection and the wake + * up selected I/O or can be one of + * PWR_WakeUp_Pins_Low_Polarity define group where every + * param select the wake up line, the wake up source with + * low polarity and the wake up selected I/O or can be one + * of PWR_WakeUp_Pins define group where every param select + * the wake up line, the wake up source with + * high polarity and the first wake up I/O. + * @retval None. + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPin)); + + /* Specifies the wake up line polarity for the event detection (rising or falling edge) */ + MODIFY_REG(PWR->WUCR2, (PWR_EWUP_MASK & WakeUpPin), (WakeUpPin >> PWR_WUP_POLARITY_SHIFT)); + + /* Specifies the wake up line I/O selection */ + MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(PWR_EWUP_MASK & WakeUpPin) * 2U)), + (WakeUpPin >> PWR_WUP_SELECT_SIGNAL_SHIFT)); + + /* Enable wake-up line */ + SET_BIT(PWR->WUCR1, (PWR_EWUP_MASK & WakeUpPin)); +} + +/** + * @brief Disable the wake up line functionality. + * @param WakeUpPin : Specifies the wake up line to disable. + * This parameter can be a combination of all the following + * values : + * @arg @ref PWR_WAKEUP_PIN1 + * @arg @ref PWR_WAKEUP_PIN2 + * @arg @ref PWR_WAKEUP_PIN3 + * @arg @ref PWR_WAKEUP_PIN4 + * @arg @ref PWR_WAKEUP_PIN6 + * @arg @ref PWR_WAKEUP_PIN5 + * @arg @ref PWR_WAKEUP_PIN7 + * @arg @ref PWR_WAKEUP_PIN8 + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPin)); + + /* Disable wake-up pin */ + CLEAR_BIT(PWR->WUCR1, (PWR_EWUP_MASK & WakeUpPin)); +} + +/** + * @brief Enter the CPU in Sleep mode. + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * @note CPU clock is off and all peripherals including Cortex-M33 core such + * as NVIC and SysTick can run and wake up the CPU when an interrupt + * or an event occurs. + * @param Regulator : Specifies the regulator state in Sleep mode. + * This parameter can be one of the following values : + * @arg @ref PWR_MAINREGULATOR_ON + * @arg @ref PWR_LOWPOWERREGULATOR_ON + * @note This parameter is not available in this product. + * The parameter is kept just to maintain compatibility with other + * products. + * @param SleepEntry : Specifies if Sleep mode is entered with WFI or WFE + * instruction. + * @arg PWR_SLEEPENTRY_WFI : Enter SLEEP mode with WFI instruction. + * @arg PWR_SLEEPENTRY_WFE : Enter SLEEP mode with WFE instruction and + * clear of pending events before. + * @arg PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR : Enter SLEEP mode with WFE instruction and + * no clear of pending event before. + * @retval None. + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SleepEntry) +{ + UNUSED(Regulator); + + /* Check the parameter */ + assert_param(IS_PWR_SLEEP_ENTRY(SleepEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Sleep mode entry */ + if (SleepEntry == PWR_SLEEPENTRY_WFI) + { + /* Wait For Interrupt Request */ + __WFI(); + } + else + { + if (SleepEntry != PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR) + { + /* Clear all pending event */ + __SEV(); + __WFE(); + } + + /* Request Wait For Event */ + __WFE(); + } +} + +/** + * @brief Enter the whole system to Stop 0 mode. + * @note In Stop 0 mode, the regulator remains in main regulator mode, + * allowing a very fast wakeup time but with much higher consumption + * comparing to other Stop modes. + * @note Stop 0 offers the largest number of active peripherals and wakeup + * sources, a smaller wakeup time but a higher consumption. + * Stop mode achieves the lowest power consumption while retaining + * the content of SRAM and registers. All clocks in the VCORE domain + * are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and + * the HSE crystal oscillators are disabled. The LSE or LSI is still + * running. + * @note The system clock when exiting from Stop mode can be either MSIS up + * to 24 MHz or HSI16, depending on software configuration. + * @param Regulator : Specifies the regulator state in Stop mode. + * This parameter can be one of the following values : + * @arg @ref PWR_MAINREGULATOR_ON + * @arg @ref PWR_LOWPOWERREGULATOR_ON + * @note This parameter is not available in this product. + * The parameter is kept just to maintain compatibility with other + * products. + * @param StopEntry : Specifies if Stop mode is entered with WFI or WFE + * instruction. + * This parameter can be one of the following values : + * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction and + * clear of pending events before. + * @arg PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and + * no clear of pending event before. + * @retval None. + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t StopEntry) +{ + UNUSED(Regulator); + + /* Check the parameter */ + assert_param(IS_PWR_STOP_ENTRY(StopEntry)); + + /* Select Stop 0 mode */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, 0U); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry */ + if (StopEntry == PWR_STOPENTRY_WFI) + { + /* Wait For Interrupt Request */ + __WFI(); + } + else + { + if (StopEntry != PWR_STOPENTRY_WFE_NO_EVT_CLEAR) + { + /* Clear all pending event */ + __SEV(); + __WFE(); + } + + /* Request Wait For Event */ + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Enter the whole system to Standby mode. + * @note The Standby mode is used to achieve the lowest power consumption + * with BOR. The internal regulator is switched off so that the VCORE + * domain is powered off. The PLL, the MSI (MSIS and MSIK) RC, the + * HSI16 RC and the HSE crystal oscillators are also switched off. + * @note After entering Standby mode, SRAMs and register contents are lost + * except for registers and backup SRAM in the Backup domain and + * Standby circuitry. Optionally, the full SRAM2 or 8 Kbytes or 56 + * Kbytes can be retained in Standby mode, supplied by the low-power + * regulator (Standby with RAM2 retention mode) through + * HAL_PWREx_EnableSRAM2ContentStandbyRetention(). + * @note The state of each I/O during Standby mode can be selected by + * software : I/O with internal pull-up through + * HAL_PWREx_EnableGPIOPullUp() and internal pull-down through + * HAL_PWREx_EnableGPIOPullDown(). + * @retval None. + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select Standby mode */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_2); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Wait For Interrupt Request */ + __WFI(); +} + +/** + * @brief Indicate SLEEP-ON-EXIT feature when returning from handler mode to + * thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor re-enters Sleep mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run + * only on interruptions handling. + * @retval None. + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex-M33 System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Disable SLEEP-ON-EXIT feature when returning from handler mode to + * thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor re-enters Sleep mode when an interruption handling is over. + * @retval None. + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex-M33 System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Enable CORTEX SEV-ON-PEND feature. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, any + * pending event / interrupt even if it's disabled or has insufficient + * priority to cause exception entry wakes up the Cortex-M33. + * @retval None. + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex-M33 System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief Disable CORTEX SEVONPEND feature. + * @note Resets SEVONPEND bit of SCR register. When this bit is reset, only enabled + * pending event / interrupt to cause exception entry wakes up the Cortex-M33. + * @retval None. + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex-M33 System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_AVD_IRQHandler(). + * @retval None. + */ +void HAL_PWR_PVD_IRQHandler(void) +{ + uint32_t rising_flag; + uint32_t falling_flag; + + /* Get pending flags */ + rising_flag = READ_REG(EXTI->RPR1); + falling_flag = READ_REG(EXTI->FPR1); + + /* Check PWR EXTI flags for PVD */ + if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVD) != 0U) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + + /* Clear PVD EXTI pending bit */ + WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD); + WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD); + } +} + +/** + * @brief PWR PVD interrupt callback. + * @retval None. + */ +__weak void HAL_PWR_PVDCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback can be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group3 Attributes Management Functions + * @brief Attributes management functions + * +@verbatim + =============================================================================== + ##### PWR Attributes Functions ##### + =============================================================================== + [..] + When the TrustZone security is activated by the TZEN option bit in the + FLASH_OPTR register, some PWR register fields can be secured against + non-secure access. + The PWR TrustZone security allows the following features to be secured + through the PWR_SECCFGR register : + + (++) Low-power mode. + (++) Wake-up (WKUP) pins. + (++) Voltage detection and monitoring. + (++) VBAT mode. + (++) I/Os pull-up/pull-down configuration. + + Other PWR configuration bits are secure when : + (++) The system clock selection is secure in RCC: the voltage scaling + (VOS) configuration and the regulator booster (BOOSTEN) are secure. + (++) A GPIO is configured as secure: its corresponding bit for pull-up / + pull-down configuration in Standby mode is secure. + (++) The UCPD1 is secure in the GTZC: the PWR_UCPDR register is secure. + + A non-secure access to a secure-protected register bit is denied : + (++) The secured bits are not written (WI) with a non-secure write access. + (++) The secured bits are read as 0 (RAZ) with a non-secure read access. + + [..] + When the TrustZone security is disabled (TZEN = 0), PWR_SECCFGR is RAZ/WI + and all other registers are non-secure. + + [..] + By default, after a reset, all PWR registers can be read or written with + both privileged and unprivileged accesses, except PWR_PRIVCFGR that can be + written with privileged access only. PWR_PRIVCFGR can be read by secure + and non secure, privileged and unprivileged accesses. + The SPRIV bit in PWR_PRIVCFGR can be written with secure privileged access + only. This bit configures the privileged access of all PWR secure + functions (defined by PWR_SECCFGR, GTZC, RCC or GPIO). + When the SPRIV bit is set in PWR_PRIVCFGR: + (++) The PWR secure bits can be written only with privileged access, + including PWR_SECCFGR. + (++) The PWR secure bits can be read only with privileged access except + PWR_SECCFGR and PWR_PRIVCFGR that can be read by privileged or + unprivileged access. + (++) An unprivileged access to a privileged PWR bit or register is + discarded : the bits are read as zero and the write to these bits is + ignored (RAZ/WI). + The NSPRIV bit of PWR_PRIVCFGR can be written with privileged access only, + secure or non-secure. This bit configures the privileged access of all PWR + securable functions that are configured as non-secure (defined by + PWR_SECCFGR, GTZC, RCC or GPIO). + When the NSPRIV bit is set in PWR_PRIVCFGR : + (++) The PWR securable bits that are configured as non-secure, can be + written only with privileged access. + (++) The PWR securable bits that are configured as non-secure, can be read + only with privileged access except PWR_PRIVCFGR that can be read by + privileged or unprivileged accesses. + (++) The VOSRDY and BOOSTRDY bits in PWR_VOSR, PWR_SR, PWR_SVMSR, PWR_BDSR + and PWR_WUSR, can be read with privileged or unprivileged accesses. + (++) An unprivileged access to a privileged PWR bit or register is + discarded : the bits are read as zero and the write to these bits is + ignored (RAZ/WI). + +@endverbatim + * @{ + */ + +/** + * @brief Configure the PWR item attributes. + * @note Available attributes are security and privilege protection. + * @note Security attribute can only be set only by secure access. + * @note Privilege attribute for secure items can be managed only by a secure + * privileged access. + * @note Privilege attribute for nsecure items can be managed by a secure + * privileged access or by a nsecure privileged access. + * @note As the privileged attributes concern either all secure or all non-secure + * PWR resources accesses and not each PWR individual items access attribute, + * the application must ensure that the privilege access attribute configurations + * are coherent amongst the security level set on PWR individual items so not to + * overwrite a previous more restricted access rule (consider either all secure + * and/or all non-secure PWR resources accesses by privileged-only transactions + * or privileged and unprivileged transactions). + * @param Item : Specifies the item(s) to set attributes on. + * This parameter can be a combination of @ref PWR_Items. + * @param Attributes : Specifies the available attribute(s). + * This parameter can be one of @ref PWR_Attributes. + * @retval None. + */ +void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes) +{ + /* Check the parameters */ + assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item)); + assert_param(IS_PWR_ATTRIBUTES(Attributes)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Secure item management (TZEN = 1) */ + if ((Attributes & PWR_ITEM_ATTR_SEC_PRIV_MASK) == PWR_ITEM_ATTR_SEC_PRIV_MASK) + { + /* Privilege item management */ + if ((Attributes & PWR_SEC_PRIV) == PWR_SEC_PRIV) + { + SET_BIT(PWR->SECCFGR, Item); + SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); + } + else + { + SET_BIT(PWR->SECCFGR, Item); + CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); + } + } + /* NSecure item management */ + else + { + /* Privilege item management */ + if ((Attributes & PWR_NSEC_PRIV) == PWR_NSEC_PRIV) + { + CLEAR_BIT(PWR->SECCFGR, Item); + SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); + } + else + { + CLEAR_BIT(PWR->SECCFGR, Item); + CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); + } + } +#else + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); + + /* NSecure item management (TZEN = 0) */ + if ((Attributes & PWR_ITEM_ATTR_NSEC_PRIV_MASK) == PWR_ITEM_ATTR_NSEC_PRIV_MASK) + { + /* Privilege item management */ + if ((Attributes & PWR_NSEC_PRIV) == PWR_NSEC_PRIV) + { + SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); + } + else + { + CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); + } + } +#endif /* __ARM_FEATURE_CMSE */ +} + +/** + * @brief Get attribute(s) of a PWR item. + * @param Item : Specifies the item(s) to get attributes of. + * This parameter can be one of @ref PWR_Items. + * @param pAttributes : Pointer to return attribute(s). + * Returned value could be one of @ref PWR_Attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes) +{ + uint32_t attributes; + + /* Check attribute pointer */ + if (pAttributes == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Check item security */ + if ((PWR->SECCFGR & Item) == Item) + { + /* Get Secure privileges attribute */ + attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_SPRIV) == 0U) ? PWR_SEC_NPRIV : PWR_SEC_PRIV; + } + else + { + /* Get Non-Secure privileges attribute */ + attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV; + } +#else + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); + /* Get Non-Secure privileges attribute */ + attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV; +#endif /* __ARM_FEATURE_CMSE */ + + /* return value */ + *pAttributes = attributes; + + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (HAL_PWR_MODULE_ENABLED) */ +/** + * @} + */ + +/** + * @} + */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c new file mode 100644 index 000000000..15b487453 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c @@ -0,0 +1,2811 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller extension peripheral : + * + Power Supply Control Functions + * + Low Power Control Functions + * + Voltage Monitoring Functions + * + Memories Retention Functions + * + I/O Pull-Up Pull-Down Configuration Functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Call HAL_PWREx_ControlVoltageScaling() and HAL_PWREx_GetVoltageRange() to + set / get the voltage scaling range. + (+) Voltage scaling can be one of the following values : + (++) voltage output scale 1 : 1V2 + => Used when system clock frequency is up to 160 MHz + (++) voltage output scale 2 : 1V1 + => Used when system clock frequency is up to 100 MHz + (++) voltage output scale 3 : 1V0 + => Used when system clock frequency is up to 50 MHz + (++) voltage output scale 4 : 0V9 + => Used when system clock frequency is up to 24 MHz + + (#) Call HAL_PWREx_EnableFastSoftStart() and HAL_PWREx_DisableFastSoftStart() + to enable / disable the fast software startup for the current regulator. + + (#) Call HAL_PWREx_EnterSTOP1Mode() function to enter the whole system to + Stop 1 mode. Wake-up from Stop 1 mode could be following to an event or + an interrupt according to low power mode intrinsic request called + (__WFI() or __WFE()). (Regulator state on U5 devices is managed + internally but regulator parameter is kept for product compatibility). + + (#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the whole system to + Stop 2 mode. Wake-up from Stop 2 mode could be following to an event or + an interrupt according to low power mode intrinsic request called + (__WFI() or __WFE()). (Regulator state on U5 devices is managed + internally but regulator parameter is kept for product compatibility). + + (#) Call HAL_PWREx_EnterSTOP3Mode() function to enter the whole system to + Stop 3 mode. Wake-up from Stop 3 mode could be following to an event or + an interrupt according to low power mode intrinsic request called + (__WFI() or __WFE()). (Regulator state on U5 devices is managed + internally but regulator parameter is kept for product compatibility). + + (#) Call HAL_PWREx_EnterSHUTDOWNMode() function to enter the whole system in + Shutdown mode. Wake-up from Shutdown mode can be following to an external + reset (NRST pin), a WKUP pin event (configurable rising or falling edge), + or an RTC event occurs (alarm, periodic wakeup, timestamp), or a tamper + detection. + + (#) Call HAL_PWREx_ConfigSRDDomain() to force in Run mode or to enter in Stop + mode Smart Run Domain when the system enters Stop mode (Stop 0/1/2). + + (#) Call HAL_PWREx_EnableUltraLowPowerMode() and + HAL_PWREx_DisableUltraLowPowerMode() to enable / disable the BOR ultra + low power mode. + + (#) Call HAL_PWREx_S3WU_IRQHandler() function to handle the PWR Stop 3 wake + up interrupt request. + + (#) Call HAL_PWREx_EnableBatteryCharging() and + HAL_PWREx_DisableBatteryCharging() to enable / disable the battery + charging capability when VDD alimentation is available. + + (#) Call HAL_PWREx_EnableVddUSB(), HAL_PWREx_EnableVddIO2() and + HAL_PWREx_EnableVddA() to enable respectively VDDUSB, VDDIO2 and VDDA + electrical and logical isolation. + It is recommended to disable VDDUSB, VDDIO2 and VDDA electrical and + logical isolation through HAL_PWREx_DisableVddUSB(), + HAL_PWREx_DisableVddIO2() and HAL_PWREx_DisableVddA(). + + (#) Call HAL_PWREx_ConfigPVM() after setting parameters to be configured + (event mode and PVD type) in order to set up the Peripheral Voltage + Monitor, then use HAL_PWREx_EnableUVM(), HAL_PWREx_EnableIO2VM(), + HAL_PWREx_EnableAVM1() and HAL_PWREx_EnableAVM2() functions to start the + PVM VDDx monitoring and use HAL_PWREx_DisableUVM(), + HAL_PWREx_DisableIO2VM(), HAL_PWREx_DisableAVM1() and + HAL_PWREx_DisableAVM2() to stop the PVM VDDx monitoring. + (+) PVM monitored voltages are : + (++) VDDUSB versus 1V2 + (++) VDDIO2 versus 0V9 + (++) VDDA versus 1V6 + (++) VDDA versus 1V8 + + (#) Call HAL_PWREx_EnableUSBHSTranceiverSupply() and + HAL_PWREx_DisableUSBHSTranceiverSupply() to enable / disable the internal + USB HS transceiver supply. + (+) This feature is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + and STM32U5Gxxx devices + + (#) Call HAL_PWREx_EnableOTGHSPHYLowPowerRetention() and + HAL_PWREx_DisableOTGHSPHYLowPowerRetention() to enable / disable OTG_HS PHY power during + low power modes (Stop2, Stop3 and Standby). + (+) This feature is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + and STM32U5Gxxx devices + + (#) Call HAL_PWREx_EnableVDD11USB() and + HAL_PWREx_DisableVDD11USB() to enable/ disable the VDD11USB. + (+) This feature is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + and STM32U5Gxxx devices + + (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring() to + enable / disable the VBAT and temperature monitoring. + + (#) Call HAL_PWREx_EnableUCPDStandbyMode() and + HAL_PWREx_DisableUCPDStandbyMode() to enable / disable the UCPD + configuration memorization in Standby mode. + + (#) Call HAL_PWREx_EnableUCPDDeadBattery() and + HAL_PWREx_DisableUCPDDeadBattery() to enable / disable the dead battery + behavior. + + (#) Call HAL_PWREx_PVD_PVM_IRQHandler() function to handle the PWR PVD and + PVM interrupt request. + + (#) Call HAL_PWREx_EnableSRAM2ContentStandbyRetention() and + HAL_PWREx_DisableSRAM2ContentStandbyRetention() to + enable / disable the SRAM2 content retention in Stop 3 and Standby low + power modes. + + (#) Call HAL_PWREx_EnableRAMsContentStopRetention() and + HAL_PWREx_DisableRAMsContentStopRetention() to + enable / disable the RAMs content retention in Stop mode (Stop 0/1/2/3). + (+) Retained RAM can be one of the following RAMs : + (++) SRAM1 + (++) SRAM2 + (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx, + STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) + (++) SRAM4 + (++) SRAM5 (available only for STM32U59xxx, STM32U5Axxx, + STM32U5Fxxx and STM32U5Gxxx devices) + (++) SRAM6 (available only for STM32U5Fxxx and STM32U5Gxxx devices) + (++) ICACHE + (++) DMA2DRAM (available only for STM32U575xx, STM32U585xx, STM32U59xxx, + STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) + (++) PKA32RAM + (++) DCACHE1 + (++) FMAC + (++) FDCAN + (++) USB + (++) DCACHE2 (available only for STM32U59xxx, STM32U5Axxx, + STM32U5Fxxx and STM32U5Gxxx devices) + (++) LTDC (available only for STM32U59xxx, STM32U5Axxx, + STM32U5Fxxx and STM32U5Gxxx devices) + (++) GFXMMU (available only for STM32U59xxx, STM32U5Axxx, + STM32U5Fxxx and STM32U5Gxxx devices) + (++) DSI (available only for STM32U59xxx, STM32U5Axxx, + STM32U5Fxxx and STM32U5Gxxx devices) + (++) JPEG (available only for STM32U5Fxxx and STM32U5Gxxx devices) + + (#) Call HAL_PWREx_EnableRAMsContentRunRetention() and + HAL_PWREx_DisableRAMsContentRunRetention() to + enable / disable the RAMs content retention in Run mode. + (+) Retained RAM can be one of the following RAMs : + (++) SRAM1 + (++) SRAM2 + (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx, + STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) + (++) SRAM4 + (++) SRAM5 (available only for STM32U59xxx, STM32U5Axxx, + STM32U5Fxxx and STM32U5Gxxx devices) + (++) SRAM6 (available only for STM32U5Fxxx and STM32U5Gxxx devices) + + (#) Call HAL_PWREx_EnableFlashFastWakeUp() and + HAL_PWREx_DisableFlashFastWakeUp() to enable / disable the flash memory + fast wakeup from Stop mode (Stop 0/1). + + (#) Call HAL_PWREx_EnableSRAM4FastWakeUp() and + HAL_PWREx_DisableSRAM4FastWakeUp() to enable / disable the SRAM4 memory + fast wakeup from Stop mode (Stop 0/1/2). + + (#) Call HAL_PWREx_EnableBkupRAMRetention() and + HAL_PWREx_DisableBkupRAMRetention() to enable / disable the Backup RAM + content retention in Standby, Shutdown and VBAT modes. + + (#) Call HAL_PWREx_EnablePullUpPullDownConfig() and + HAL_PWREx_DisablePullUpPullDownConfig() to I/O enable / disable pull-up + and pull-down configuration. + + (#) Call HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() to + apply respectively pull-up and pull-down to selected I/O. + Call HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() to + disable applied respectively pull-up and pull-down to selected I/O. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR Extended HAL module driver + * @{ + */ + +#if defined (HAL_PWR_MODULE_ENABLED) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines + * @{ + */ +#if defined (PWR_PUCRJ_PU0) +/* PORTI pins mask */ +#define PWR_PORTI_AVAILABLE_PINS (0xFFFFU) +/* PORTJ pins mask */ +#define PWR_PORTJ_AVAILABLE_PINS (0x0FFFU) +#else +/* PORTI pins mask */ +#define PWR_PORTI_AVAILABLE_PINS (0x00FFU) +#endif /* defined (PWR_PUCRJ_PU0) */ + +/* Time out value of flags setting */ +#define PWR_FLAG_SETTING_DELAY (0x32U) + +/** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask + * @{ + */ +#define PVM_RISING_EDGE (0x01U) /*!< Mask for rising edge set as PVM trigger */ +#define PVM_FALLING_EDGE (0x02U) /*!< Mask for falling edge set as PVM trigger */ +#define PVM_MODE_IT (0x04U) /*!< Mask for interruption yielded by PVM threshold crossing */ +#define PVM_MODE_EVT (0x08U) /*!< Mask for event yielded by PVM threshold crossing */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions + * @brief Power supply control functions + * +@verbatim + =============================================================================== + ##### Power supply control functions ##### + =============================================================================== + [..] + This section provides functions allowing to control power supply. + + [..] + (+) The STM32U5 Series devices embed two regulators : one LDO (linear + voltage regulator) and one SMPS (step down converter) in parallel to + provide the VCORE supply for digital peripherals, SRAM1, SRAM2, SRAM3 + and SRAM4 and embedded Flash memory. + + (+) The SMPS allows the power consumption to be reduced but some + peripherals can be perturbed by the noise generated by the SMPS, + requiring the application to switch to LDO when running this + peripheral in order to reach the best performances. + + (+) The LDO and the SMPS regulators have two modes: Main regulator mode + (used when performance is needed), and Low-power regulator mode. LDO + or SMPS can be used in all voltage scaling ranges, and in all Stop + modes. + + (+) After reset, the regulator is the LDO, in Range 4. Switching to SMPS + provides lower consumption in particular at high VDD voltage. It is + possible to switch from LDO to SMPS, or from SMPS to LDO on the fly in + any range, by configuring the REGSEL bit. It is recommended to switch + first to SMPS before changing the voltage range. + + (+) When exiting the Stop or Standby modes, the regulator is the same than + when entering low power modes. The voltage range is the Range 4. + + (+) Both regulators can provide four different voltages (voltage scaling) + and can operate in Stop modes. + Voltage scaling ranges can be one of the following values : + (++) voltage output scale 1 : 1V2 + => Used when system clock frequency is up to 160 MHz + (++) voltage output scale 2 : 1V1 + => Used when system clock frequency is up to 100 MHz + (++) voltage output scale 3 : 1V0 + => Used when system clock frequency is up to 50 MHz + (++) voltage output scale 4 : 0V9 + => Used when system clock frequency is up to 24 MHz + +@endverbatim + * @{ + */ + +/** + * @brief Configure the main internal regulator output voltage to achieve + * a tradeoff between performance and power consumption. + * @param VoltageScaling : Specifies the regulator output voltage scale. + * This parameter can be one of the following values : + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output scale 1. + * Provides a typical output voltage at 1.2 V. + * Used when system clock frequency is up to 160 MHz. + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output scale 2. + * Provides a typical output voltage at 1.1 V. + * Used when system clock frequency is up to 100 MHz. + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output scale 3. + * Provides a typical output voltage at 1.0 V. + * Used when system clock frequency is up to 50 MHz. + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE4 : Regulator voltage output scale 4. + * Provides a typical output voltage at 0.9 V. + * Used when system clock frequency is up to 24 MHz. + * @note Before moving to voltage scaling 2, it is mandatory to ensure that + * the system frequency is between 50 MHz and 100 MHz. + * @note Before moving to voltage scaling 3, it is mandatory to ensure that + * the system frequency is between 24 MHz and 50 MHz. + * @note Before moving to voltage scaling 4, it is mandatory to ensure that + * the system frequency is below 24 MHz. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +{ + uint32_t timeout; + uint32_t vos_old; + + /* Check the parameter */ + assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); + + /* Get the current voltage scale applied */ + vos_old = READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOS); + + /* No change, nothing to do */ + if (vos_old == VoltageScaling) + { + /* Enable USB BOOST after wake up from Stop mode */ + if (VoltageScaling > PWR_REGULATOR_VOLTAGE_SCALE3) + { + /* Enable USB BOOST */ + SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN); + } + + return HAL_OK; + } + + /* Check voltage scaling level */ + /* + * The Embedded power distribution (EPOD) must be enabled before switching to + * voltage scale 1 / 2 from voltage scale lower. + */ + if (VoltageScaling > PWR_REGULATOR_VOLTAGE_SCALE3) + { + MODIFY_REG(PWR->VOSR, (PWR_VOSR_VOS | PWR_VOSR_BOOSTEN), (VoltageScaling | PWR_VOSR_BOOSTEN)); + } + else + { + MODIFY_REG(PWR->VOSR, (PWR_VOSR_VOS | PWR_VOSR_BOOSTEN), VoltageScaling); + } + + /* Wait until VOSRDY is raised */ + timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U; + while (HAL_IS_BIT_CLR(PWR->VOSR, PWR_VOSR_VOSRDY) && (timeout != 0U)) + { + timeout--; + } + + /* Check time out */ + if (timeout != 0U) + { + /* Wait until ACTVOSRDY is raised */ + timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U; + while ((HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY)) && (timeout != 0U)) + { + timeout--; + } + } + + /* Check time out */ + if (timeout == 0U) + { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief Return Voltage Scaling Range. + * @retval Applied voltage scaling value. + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + return (PWR->SVMSR & PWR_SVMSR_ACTVOS); +} + +/** + * @brief Configure the system Power Supply. + * @param SupplySource : Specifies the Power Supply source to set after a + * system startup. + * This parameter can be one of the following values : + * @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power Domains. + * @arg PWR_SMPS_SUPPLY : The SMPS regulator supplies the Vcore Power Domains. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource) +{ + uint32_t timeout; + + /* Check the parameter */ + assert_param(IS_PWR_SUPPLY(SupplySource)); + + /* Set maximum time out */ + timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U; + + /* Configure the LDO as system regulator supply */ + if (SupplySource == PWR_LDO_SUPPLY) + { + /* Set the power supply configuration */ + CLEAR_BIT(PWR->CR3, PWR_CR3_REGSEL); + + /* Wait until system switch on new regulator */ + while (HAL_IS_BIT_SET(PWR->SVMSR, PWR_SVMSR_REGS) && (timeout != 0U)) + { + timeout--; + } + } + /* Configure the SMPS as system regulator supply */ + else + { + /* Set the power supply configuration */ + SET_BIT(PWR->CR3, PWR_CR3_REGSEL); + + /* Wait until system switch on new regulator */ + while (HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_REGS) && (timeout != 0U)) + { + timeout--; + } + } + + /* Check time out */ + if (timeout == 0U) + { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief Get the power supply configuration. + * @retval The supply configured. + */ +uint32_t HAL_PWREx_GetSupplyConfig(void) +{ + return (PWR->SVMSR & PWR_SVMSR_REGS); +} + +/** + * @brief Enable fast soft start for the current regulator. + * @retval None. + */ +void HAL_PWREx_EnableFastSoftStart(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_FSTEN); +} + +/** + * @brief Disable fast soft start for the current regulator. + * @retval None. + */ +void HAL_PWREx_DisableFastSoftStart(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_FSTEN); +} +/** + * @} + */ + + +/** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions + * @brief Low power control functions + * +@verbatim + =============================================================================== + ##### Low power control functions ##### + =============================================================================== + [..] + This section provides functions allowing to control low power modes. + + *** Low Power modes configuration *** + ===================================== + [..] + This section presents 4 principles low power modes : + (+) Stop 1 mode : Cortex-M33 is stopped, clocks are stopped and the + regulator is in low power mode. Several peripheral can + operate in this mode. + + (+) Stop 2 mode : Cortex-M33 is stopped, clocks are stopped and the + regulator is in low power mode. Only autonomous + peripherals can operate in this mode. + + (+) Stop 3 mode : Cortex-M33 is stopped, clocks are stopped and the + regulator is in low power mode. No peripheral can + operate in this mode. Only RAMs content is preserved. + + (+) Shutdown mode : All PWR domains enter Shutdown mode and the VCORE + supply regulator is powered off. The SRAMs and + register contents are lost except for registers in the + Backup domain. + + *** Stop 1 mode *** + =================== + [..] + The Stop 1 mode is based on the Cortex-M33 Deepsleep mode combined with + the peripheral clock gating. The voltage regulator is configured in low + power mode. In Stop 1 mode, all clocks in the VCORE domain are stopped. + The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled. + Some peripherals with the LPBAM capability can switch on HSI16 or MSIS or + MSIK for transferring data. All SRAMs and register contents are preserved, + but the SRAMs can be totally or partially switched off to further reduced + consumption. + The BOR is always available in Stop 1 mode. + + (+) Entry: + The Stop 1 mode is entered by using the HAL_PWREx_EnterSTOP1Mode() + function. + + (++) PWR_STOPENTRY_WFI: enter Stop 1 mode with WFI instruction. + (++) PWR_STOPENTRY_WFE: enter Stop 1 mode with WFE instruction. + + (+) Exit: + Any EXTI line configured in interrupt mode (the corresponding EXTI + interrupt vector must be enabled in the NVIC). The interrupt source + can be external interrupts or peripherals with wakeup capability. + Any peripheral interrupt occurring when the AHB/APB clocks are present + due to an autonomous peripheral clock request (the peripheral vector + must be enabled in the NVIC) + Any EXTI line configured in event mode. + + *** Stop 2 mode *** + =================== + [..] + The Stop 2 mode is based on the Cortex-M33 Deepsleep mode combined with + peripheral clock gating. In Stop 2 mode, all clocks in the VCORE domain + are stopped. + The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled. + Some peripherals with the LPBAM capability can switch on HSI16 or MSIS or + MSIK for transferring data. All SRAMs and register contents are preserved, + but the SRAMs can be totally or partially switched off to further reduce + consumption. + The BOR is always available in Stop 2 mode. + + (+) Entry: + The Stop 2 mode is entered by using the HAL_PWREx_EnterSTOP2Mode() + function. + + (++) PWR_STOPENTRY_WFI: enter Stop 2 mode with WFI instruction. + (++) PWR_STOPENTRY_WFE: enter Stop 2 mode with WFE instruction. + + (+) Exit: + Any EXTI line configured in interrupt mode (the corresponding EXTI + interrupt vector must be enabled in the NVIC). The interrupt source + can be external interrupts or peripherals with wakeup capability. + Any peripheral interrupt occurring when the AHB/APB clocks are present + due to an autonomous peripheral clock request (the peripheral vector + must be enabled in the NVIC) + Any EXTI line configured in event mode. + + *** Stop 3 mode *** + =================== + [..] + The Stop 3 mode is based on the Cortex-M33 Deepsleep mode combined with + peripheral clock gating. In Stop 3 mode, all clocks in the VCORE domain + are stopped. + The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled. + All SRAMs and register contents are preserved, but the SRAMs can be + totally or partially switched off to further reduce consumption. + The BOR is always available in Stop 3 mode. + + (+) Entry: + The Stop 3 mode is entered by using the HAL_PWREx_EnterSTOP3Mode() + function. + + (++) PWR_STOPENTRY_WFI: enter Stop 3 mode with WFI instruction. + (++) PWR_STOPENTRY_WFE: enter Stop 3 mode with WFE instruction. + + (+) Exit: + WKUPx pin edge, RTC or TAMP event, external Reset in NRST pin, IWDG + Reset, BOR reset. + + *** Shutdown mode *** + ==================== + [..] + The lowest power consumption is reached in Shutdown mode. It is based on + the Deepsleep mode with the voltage regulator disabled. The VCORE domain + is consequently powered off. + The PLL, HSI16, MSIS, MSIK and HSE oscillators are also switched off. + The SRAMs and register contents are lost except for registers in the + Backup domain. + The BOR is not available in Shutdown mode. + No power voltage monitoring is possible in this mode, therefore the switch + to Backup domain is not supported. + + (+) Entry: + The Shutdown mode is entered by using the HAL_PWREx_EnterSHUTDOWNMode() + function. + + (+) Exit: + WKUPx pin edge, RTC/TAMP event, external Reset in NRST pin. + +@endverbatim + * @{ + */ + +/** + * @brief Enter the whole system to Stop 1 mode. + * @note Stop 1 offers the largest number of active peripherals and wakeup + * sources, a smaller wakeup time but a higher consumption. + * @note Stop mode achieves the lowest power consumption while retaining + * the content of SRAM and registers. All clocks in the VCORE domain + * are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and + * the HSE crystal oscillators are disabled. The LSE or LSI is still + * running. + * @note The system clock when exiting from Stop mode can be either MSIS up + * to 24 MHz or HSI16, depending on software configuration. + * @param STOPEntry : Specifies if Stop mode is entered with WFI or WFE + * instruction. + * This parameter can be one of the following values : + * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait + * For Interrupt request. + * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait + * For Event request. + * @retval None. + */ +void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Stop 1 mode */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_0); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Enter the whole system to Stop 2 mode. + * @note In Stop 2 mode, all clocks in the VCORE domain are stopped. The PLL, + * MSIS, MSIK, HSI16 and HSE oscillators are disabled. + * @note Stop mode achieves the lowest power consumption while retaining + * the content of SRAM and registers. All clocks in the VCORE domain + * are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and + * the HSE crystal oscillators are disabled. The LSE or LSI is still + * running. + * @note The system clock when exiting from Stop mode can be either MSIS up + * to 24 MHz or HSI16, depending on software configuration. + * @param STOPEntry : Specifies if Stop mode is entered with WFI or WFE + * instruction. + * This parameter can be one of the following values : + * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait + * For Interrupt request. + * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait + * For Event request. + * @retval None. + */ +void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Stop 2 mode */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_1); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Enter the whole system to Stop 3 mode. + * @note Stop 3 is the lowest power mode with full retention, but the + * functional peripherals and sources of wakeup are reduced to the same + * ones than in Standby mode. + * @note Stop mode achieves the lowest power consumption while retaining + * the content of SRAM and registers. All clocks in the VCORE domain + * are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and + * the HSE crystal oscillators are disabled. The LSE or LSI is still + * running. + * @note The system clock when exiting from Stop mode can be either MSIS up + * to 24 MHz or HSI16, depending on software configuration. + * @param STOPEntry : Specifies if Stop mode is entered with WFI or WFE + * instruction. + * This parameter can be one of the following values : + * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait + * For Interrupt request. + * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait + * For Event request. + * @retval None. + */ +void HAL_PWREx_EnterSTOP3Mode(uint8_t STOPEntry) +{ + /* Check the parameter */ + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Set Stop mode 3 */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1)); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Enter the whole system to Shutdown mode. + * @note Shutdown mode allows the lowest power consumption. The internal + * regulator is switched off so that the VCORE domain is powered off. + * The PLL, the HSI16, the MSI (MSIS and MSIK), the LSI and the HSE + * oscillators are also switched off. + * @note The SRAMs and register contents are lost except for registers in the + * Backup domain. The BOR is not available in Shutdown mode. No power + * voltage monitoring is possible in this mode, therefore the switch to + * Backup domain is not supported. + * @retval None. + */ +void HAL_PWREx_EnterSHUTDOWNMode(void) +{ + /* Set Shutdown mode */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_2)); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* This option is used to ensure that store operations are completed */ +#if defined (__CC_ARM) + __force_stores(); +#endif /* (__CC_ARM)*/ + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief Configure the SRD domain when the System in Stop 0/1/2 mode. + * @param SRDState : Specifies the SRD state. + * This parameter can be one of the following values : + * @arg PWR_SRD_DOMAIN_STOP : SRD in Stop mode when system + * goes to Stop 0/1/2 mode + * @arg PWR_SRD_DOMAIN_RUN : SRD in Run mode when system + * goes to Stop 0/1/2 mode + * @retval None. + */ +void HAL_PWREx_ConfigSRDDomain(uint32_t SRDState) +{ + /* Check the parameter */ + assert_param(IS_PWR_SRD_STATE(SRDState)); + + /* Config the SRD domain */ + MODIFY_REG(PWR->CR2, PWR_CR2_SRDRUN, SRDState); +} + +/** + * @brief Enable BOR ultra-low power mode. + * @note BOR operating can be in discontinuous (ultra-low power) mode in + * Stop 1, Stop 2, Stop 3 and Standby modes and when the regulator is + * in Range 4 (Run, Sleep or Stop 0 mode). + * @retval None. + */ +void HAL_PWREx_EnableUltraLowPowerMode(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_ULPMEN); +} + +/** + * @brief Disable BOR ultra-low power mode. + * @retval None. + */ +void HAL_PWREx_DisableUltraLowPowerMode(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN); +} + +/** + * @brief This function handles the PWR Wake up from Stop 3 interrupt request. + * @note This API should be called under the PWR_S3WU_IRQHandler(). + * @param WakeUpPin : Specifies the wakeup pin interrupt to be handled. + * This parameter can be a combination of @ref PWR_WakeUp_Pins. + * @retval None. + */ +void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) +{ + /* Check PWR wake up line 1 */ + if ((WakeUpPin & PWR_WAKEUP_PIN1) != 0U) + { + if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) != 0U) + { + /* Clear PWR wake up flag line 1 */ + SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1); + + /* PWR S3WU interrupt user callback */ + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN1); + } + } + + /* Check PWR wake up line 2 */ + if ((WakeUpPin & PWR_WAKEUP_PIN2) != 0U) + { + if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) != 0U) + { + /* Clear PWR wake up flag line 2 */ + SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2); + + /* PWR S3WU interrupt user callback */ + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN2); + } + } + + /* Check PWR wake up line 3 */ + if ((WakeUpPin & PWR_WAKEUP_PIN3) != 0U) + { + if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) != 0U) + { + /* Clear PWR wake up flag line 3 */ + SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3); + + /* PWR S3WU interrupt user callback */ + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN3); + } + } + + /* Check PWR wake up line 4 */ + if ((WakeUpPin & PWR_WAKEUP_PIN4) != 0U) + { + if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) != 0U) + { + /* Clear PWR wake up flag line 4 */ + SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4); + + /* PWR S3WU interrupt user callback */ + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN4); + } + } + + /* Check PWR wake up line 5 */ + if ((WakeUpPin & PWR_WAKEUP_PIN5) != 0U) + { + if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) != 0U) + { + /* Clear PWR wake up flag line 5 */ + SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5); + + /* PWR S3WU interrupt user callback */ + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN5); + } + } + + /* Check PWR wake up line 6 */ + if ((WakeUpPin & PWR_WAKEUP_PIN6) != 0U) + { + if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) != 0U) + { + /* Clear PWR wake up flag line 6 */ + SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6); + + /* PWR S3WU interrupt user callback */ + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN6); + } + } + + /* Check PWR wake up line 7 */ + if ((WakeUpPin & PWR_WAKEUP_PIN7) != 0U) + { + if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) != 0U) + { + /* Clear PWR wake up flag line 7 */ + SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7); + + /* PWR S3WU interrupt user callback */ + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN7); + } + } + + /* Check PWR wake up line 8 */ + if ((WakeUpPin & PWR_WAKEUP_PIN8) != 0U) + { + if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) != 0U) + { + /* Clear PWR wake up flag line 8 */ + SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8); + + /* PWR S3WU interrupt user callback */ + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN8); + } + } +} + +/** + * @brief PWR S3WU interrupt callback. + * @param WakeUpPin : Specifies the wakeup pin interrupt to be handled. + * This parameter can be a combination of @ref PWR_WakeUp_Pins. + * @retval None. + */ +__weak void HAL_PWREx_S3WUCallback(uint32_t WakeUpPin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(WakeUpPin); + + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_S3WU_IRQHandler() API can be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group3 Voltage Monitoring Functions + * @brief Voltage monitoring functions + * +@verbatim + =============================================================================== + ##### Voltage Monitoring Functions ##### + =============================================================================== + [..] + This section provides functions allowing voltage monitoring. + + *** PVM configuration *** + ========================= + [..] + (+) The supplies (VDDA, VDDIO2 and VDDUSB) can be independent from VDD and + can be monitored with four peripheral voltage monitoring (PVM): + + (++) The UVM monitors the USB supply VDDUSB. VDDUSBRDY indicates if + the VDDUSB independent power supply is higher or lower than the + VUVM threshold. + (++) The IO2VM monitors the PG[15:2] supply VDDIO2. VDDIO2RDY + indicates if the VDDIO2 independent power supply is higher or + lower than the VIO2VM threshold. + (++) The AVM1 monitors the analog supply VDDA. VDDA1RDY indicates if + the VDDA independent power supply is higher or lower than the + VAVM1 threshold. + (++) The AVM2 monitors the analog supply VDDA. VDDA2RDY indicates if + the VDDA independent power supply is higher or lower than the + VAVM2 threshold. + + (+) Each PVM output is connected to an EXTI line and can generate an + interrupt if enabled through the EXTI registers. The PVMx output + interrupt is generated when the independent power supply drops below + the PVM threshold and/or when it rises above the PVM threshold, + depending on EXTI line rising/falling edge configuration. + + (+) Each PVM can remain active in Stop 0, Stop 1, Stop 2 modes, and the + PVM interrupt can wake up from the Stop mode. The PVM is not + functional in Stop 3 mode. + + *** VBAT charging *** + ===================== + [..] + When VDD is present, it is possible to charge the external battery on VBAT + through an internal resistance. + The VBAT charging is done either through a 5 kOhm resistor or through a 1.5 + kOhm resistor depending on the VBRS bit value in the PWR_BDCR2 register. + The battery charging is enabled by setting VBE bit in the PWR_BDCR2 + register. It is automatically disabled in VBAT mode. + + *** Backup domain monitoring *** + ================================ + [..] + When the Backup domain voltage and temperature monitoring is enabled + (MONEN = 1 in the PWR_BDCR1 register), the Backup domain voltage and the + temperature are monitored. + If the Backup domain voltage monitoring internal tamper is enabled in the + TAMP peripheral (ITAMP1E = 1 in the TAMP_CR1 register), a tamper event is + generated when the Backup domain voltage is above the functional range. + In case the Backup domain voltage is below the functional range, + a Brownout reset is generated, erasing all device including Backup domain. + + *** Backup domain battery *** + ============================= + [..] + (+) To retain the content of the backup registers and supply the RTC + function when VDD is turned off, the VBAT pin can be connected to an + optional backup voltage supplied by a battery or by another source. + The VBAT pin powers the RTC unit, the LSE oscillator and the PC13 to + PC15 I/Os, allowing the RTC to operate even when the main power supply + is turned off. The backup SRAM is optionally powered by VBAT pin when + the BREN bit is set in the PWR Backup domain control register 1 + (PWR_BDCR1). + The switch to the VBAT supply is controlled by the power down reset + embedded in the Reset block. + + (+) After exiting reset, the USB Type-C (dead battery) behavior is enabled, + which may have a pull-down effect on CC1 and CC2 pins. It is + recommended to disable it in all cases, either to stop this pull-down + or to handover control to the UCPD (the UCPD must be initialized + before doing the disable). + +@endverbatim + * @{ + */ + +/** + * @brief Configure the voltage monitor threshold detected by the Peripheral + * voltage monitoring (PVM). + * @param pConfigPVM : Pointer to a PWR_PVMTypeDef structure that contains the + * PVM configuration information (PVMType and EventMode). + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *pConfigPVM) +{ + /* Check the PVM parameter */ + if (pConfigPVM == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_PWR_PVM_TYPE(pConfigPVM->PVMType)); + assert_param(IS_PWR_PVM_MODE(pConfigPVM->Mode)); + + /* Check the peripheral voltage monitor type */ + switch (pConfigPVM->PVMType) + { + case PWR_UVM: /* Independent USB voltage monitor */ + + /* Disable EXTI UVM event and interrupt */ + __HAL_PWR_UVM_EXTI_DISABLE_EVENT(); + __HAL_PWR_UVM_EXTI_DISABLE_IT(); + __HAL_PWR_UVM_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_UVM_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure the UVM in interrupt mode */ + if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + { + __HAL_PWR_UVM_EXTI_ENABLE_IT(); + } + + /* Configure the UVM in event mode */ + if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + { + __HAL_PWR_UVM_EXTI_ENABLE_EVENT(); + } + + /* Configure the UVM in rising edge */ + if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + { + __HAL_PWR_UVM_EXTI_ENABLE_RISING_EDGE(); + } + + /* Configure the UVM in falling edge */ + if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + { + __HAL_PWR_UVM_EXTI_ENABLE_FALLING_EDGE(); + } + + break; + + case PWR_IO2VM: /* Independent I/Os voltage monitor */ + + /* Disable EXTI IO2VM event and interrupt */ + __HAL_PWR_IO2VM_EXTI_DISABLE_EVENT(); + __HAL_PWR_IO2VM_EXTI_DISABLE_IT(); + __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure the IO2VM in interrupt mode */ + if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + { + __HAL_PWR_IO2VM_EXTI_ENABLE_IT(); + } + + /* Configure the IO2VM in event mode */ + if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + { + __HAL_PWR_IO2VM_EXTI_ENABLE_EVENT(); + } + + /* Configure the IO2VM in rising edge */ + if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + { + __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE(); + } + + /* Configure the IO2VM in falling edge */ + if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + { + __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE(); + } + + break; + + case PWR_AVM1: /* VDDA Independent analog supply voltage monitor 1 (1.6V threshold) */ + + /* Disable EXTI AVM1 event and interrupt */ + __HAL_PWR_AVM1_EXTI_DISABLE_EVENT(); + __HAL_PWR_AVM1_EXTI_DISABLE_IT(); + __HAL_PWR_AVM1_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_AVM1_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure the AVM1 in interrupt mode */ + if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + { + __HAL_PWR_AVM1_EXTI_ENABLE_IT(); + } + + /* Configure the AVM1 in event mode */ + if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + { + __HAL_PWR_AVM1_EXTI_ENABLE_EVENT(); + } + + /* Configure the AVM1 in rising edge */ + if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + { + __HAL_PWR_AVM1_EXTI_ENABLE_RISING_EDGE(); + } + + /* Configure the AVM1 in falling edge */ + if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + { + __HAL_PWR_AVM1_EXTI_ENABLE_FALLING_EDGE(); + } + + break; + + case PWR_AVM2: /* VDDA Independent analog supply voltage monitor 2 (1.8V threshold) */ + + /* Disable EXTI AVM2 event and interrupt */ + __HAL_PWR_AVM2_EXTI_DISABLE_EVENT(); + __HAL_PWR_AVM2_EXTI_DISABLE_IT(); + __HAL_PWR_AVM2_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_AVM2_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure the AVM2 in interrupt mode */ + if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + { + __HAL_PWR_AVM2_EXTI_ENABLE_IT(); + } + + /* Configure the AVM2 in event mode */ + if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + { + __HAL_PWR_AVM2_EXTI_ENABLE_EVENT(); + } + + /* Configure the AVM2 in rising edge */ + if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + { + __HAL_PWR_AVM2_EXTI_ENABLE_RISING_EDGE(); + } + + /* Configure the AVM2 in falling edge */ + if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + { + __HAL_PWR_AVM2_EXTI_ENABLE_FALLING_EDGE(); + } + + break; + + default: /* No valid voltage monitor selected */ + return HAL_ERROR; + break; + } + + return HAL_OK; +} + +/** + * @brief Enable VDDUSB supply. + * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply + * is present for consumption saving. + * @retval None. + */ +void HAL_PWREx_EnableVddUSB(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_USV); +} + +/** + * @brief Disable VDDUSB supply. + * @retval None. + */ +void HAL_PWREx_DisableVddUSB(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_USV); +} + +/** + * @brief Enable VDDIO2 supply. + * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply + * is present for consumption saving. + * @retval None. + */ +void HAL_PWREx_EnableVddIO2(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV); +} + +/** + * @brief Disable VDDIO2 supply. + * @retval None. + */ +void HAL_PWREx_DisableVddIO2(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV); +} + +/** + * @brief Enable VDDA supply. + * @note Remove VDDA electrical and logical isolation, once VDDA supply is + * present for consumption saving. + * @retval None. + */ +void HAL_PWREx_EnableVddA(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_ASV); +} + +/** + * @brief Disable VDDA supply. + * @retval None. + */ +void HAL_PWREx_DisableVddA(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_ASV); +} + +/** + * @brief Enable the UVM Voltage Monitoring : VDDUSB versus 1.2 V. + * @retval None. + */ +void HAL_PWREx_EnableUVM(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN); +} + +/** + * @brief Disable the UVM Voltage Monitoring : VDDUSB versus 1.2 V. + * @retval None. + */ +void HAL_PWREx_DisableUVM(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN); +} + +/** + * @brief Enable the IO2VM Voltage Monitoring : VDDIO2 versus 0.9 V. + * @retval None. + */ +void HAL_PWREx_EnableIO2VM(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN); +} + +/** + * @brief Disable the IO2VM Voltage Monitoring : VDDIO2 versus 0.9 V. + * @retval None. + */ +void HAL_PWREx_DisableIO2VM(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN); +} + +/** + * @brief Enable the AVM1 Voltage Monitoring : VDDA versus 1.6 V. + * @retval None. + */ +void HAL_PWREx_EnableAVM1(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN); +} + +/** + * @brief Disable the AVM1 Voltage Monitoring : VDDA versus 1.6 V. + * @retval None. + */ +void HAL_PWREx_DisableAVM1(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN); +} + +/** + * @brief Enable the AVM2 Voltage Monitoring : VDDA versus 1.8 V. + * @retval None. + */ +void HAL_PWREx_EnableAVM2(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN); +} + +/** + * @brief Disable the AVM2 Voltage Monitoring : VDDA versus 1.8 V. + * @retval None. + */ +void HAL_PWREx_DisableAVM2(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN); +} + +/** + * @brief Enable the VBAT and temperature monitoring. + * @retval None. + */ +void HAL_PWREx_EnableMonitoring(void) +{ + SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); +} + +/** + * @brief Disable the VBAT and temperature monitoring. + * @retval None. + */ +void HAL_PWREx_DisableMonitoring(void) +{ + CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); +} + +#if defined (PWR_VOSR_USBPWREN) +/** + * @brief Enable the internal USB HS transceiver supply. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_EnableUSBHSTranceiverSupply(void) +{ + uint32_t vos; + + /* Get the system applied voltage scaling range */ + vos = HAL_PWREx_GetVoltageRange(); + + /* Check the system applied voltage scaling range */ + if ((vos == PWR_REGULATOR_VOLTAGE_SCALE1) || (vos == PWR_REGULATOR_VOLTAGE_SCALE2)) + { + SET_BIT(PWR->VOSR, (PWR_VOSR_USBPWREN | PWR_VOSR_USBBOOSTEN)); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disable the internal USB HS transceiver supply. + * @retval HAL status. + */ +void HAL_PWREx_DisableUSBHSTranceiverSupply(void) +{ + CLEAR_BIT(PWR->VOSR, (PWR_VOSR_USBPWREN | PWR_VOSR_USBBOOSTEN)); +} +#endif /* defined (PWR_VOSR_USBPWREN) */ + +#if defined (PWR_CR1_FORCE_USBPWR) +/** + * @brief Enable OTG_HS PHY power during low power modes (Stop2, Stop3 and Standby). + * @retval None. + */ +void HAL_PWREx_EnableOTGHSPHYLowPowerRetention(void) +{ + /* Set FORCE_USBPWR bit */ + SET_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR); +} + +/** + * @brief Disable OTG_HS PHY power during low power modes (Stop2, Stop3 and Standby). + * @retval None. + */ +void HAL_PWREx_DisableOTGHSPHYLowPowerRetention(void) +{ + /* Clear FORCE_USBPWR bit */ + CLEAR_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR); +} +#endif /* defined (PWR_CR1_FORCE_USBPWR) */ + +#if defined (PWR_VOSR_VDD11USBDIS) +/** + * @brief Enable the VDD11USB. + * @retval None. + */ +void HAL_PWREx_EnableVDD11USB(void) +{ + /* Clear VDD11USBDIS bit */ + CLEAR_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS); +} + +/** + * @brief Disable the VDD11USB. + * @retval None. + */ +void HAL_PWREx_DisableVDD11USB(void) +{ + /* Set VDD11USBDIS bit */ + SET_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS); +} +#endif /* defined (PWR_VOSR_VDD11USBDIS) */ + +#ifdef UCPD1 +/** + * @brief Enable UCPD configuration memorization in Standby mode. + * @retval None. + */ +void HAL_PWREx_EnableUCPDStandbyMode(void) +{ + SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY); +} + +/** + * @brief Disable UCPD configuration memorization in Standby mode. + * @note This function must be called on exiting the Standby mode and before + * any UCPD configuration update. + * @retval None. + */ +void HAL_PWREx_DisableUCPDStandbyMode(void) +{ + CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY); +} + +/** + * @brief Enable dead battery behavior. + * @note After exiting reset, the USB Type-C (dead battery) behavior is + * enabled, which may have a pull-down effect on CC1 and CC2 pins. + * It is recommended to disable it in all cases, either to stop this + * pull-down or to handover control to the UCPD (the UCPD must be + * initialized before doing the disable). + * @retval None. + */ +void HAL_PWREx_EnableUCPDDeadBattery(void) +{ + CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); +} + +/** + * @brief Disable dead battery behavior. + * @note After exiting reset, the USB Type-C (dead battery) behavior is + * enabled, which may have a pull-down effect on CC1 and CC2 pins. + * It is recommended to disable it in all cases, either to stop this + * pull-down or to handover control to the UCPD (the UCPD must be + * initialized before doing the disable). + * @retval None. + */ +void HAL_PWREx_DisableUCPDDeadBattery(void) +{ + SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); +} +#endif /* UCPD1 */ + +/** + * @brief Enable the Battery charging. + * @note When VDD is present, charge the external battery through an internal + * resistor. + * @param ResistorValue : Specifies the charging resistor. + * This parameter can be one of the following values : + * @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor. + * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor. + * @retval None. + */ +void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue) +{ + /* Check the parameter */ + assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorValue)); + + /* Specify the charging resistor */ + MODIFY_REG(PWR->BDCR2, PWR_BDCR2_VBRS, ResistorValue); + + /* Enable the Battery charging */ + SET_BIT(PWR->BDCR2, PWR_BDCR2_VBE); +} + +/** + * @brief Disable the Battery charging. + * @retval None. + */ +void HAL_PWREx_DisableBatteryCharging(void) +{ + CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_VBE); +} + +/** + * @brief This function handles the PWR PVD/PVM interrupt request. + * @note This API should be called under the PVD_PVM_IRQHandler(). + * @retval None. + */ +void HAL_PWREx_PVD_PVM_IRQHandler(void) +{ + uint32_t rising_flag; + uint32_t falling_flag; + + /* Get pending flags */ + rising_flag = READ_REG(EXTI->RPR1); + falling_flag = READ_REG(EXTI->FPR1); + + /* Check PWR exti flags for PVD */ + if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVD) != 0U) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + + /* Clear PVD exti pending bit */ + WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD); + WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD); + } + + /* Check PWR exti flags for UVM */ + if (((rising_flag | falling_flag) & PWR_EXTI_LINE_UVM) != 0U) + { + /* PWR UVM interrupt user callback */ + HAL_PWREx_UVMCallback(); + + /* Clear UVM exti pending bit */ + WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_UVM); + WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_UVM); + } + + /* Check PWR exti flags for IO2VM */ + if (((rising_flag | falling_flag) & PWR_EXTI_LINE_IO2VM) != 0U) + { + /* PWR IO2VM interrupt user callback */ + HAL_PWREx_IO2VMCallback(); + + /* Clear IO2VM exti pending bit */ + WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_IO2VM); + WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_IO2VM); + } + + /* Check PWR exti flags for AVM1 */ + if (((rising_flag | falling_flag) & PWR_EXTI_LINE_AVM1) != 0U) + { + /* PWR AVM1 interrupt user callback */ + HAL_PWREx_AVM1Callback(); + + /* Clear AVM1 exti pending bit */ + WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM1); + WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM1); + } + + /* Check PWR exti flags for AVM2 */ + if (((rising_flag | falling_flag) & PWR_EXTI_LINE_AVM2) != 0U) + { + /* PWR AVM2 interrupt user callback */ + HAL_PWREx_AVM2Callback(); + + /* Clear AVM2 exti pending bit */ + WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM2); + WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM2); + } +} + +/** + * @brief PWR UVM interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_UVMCallback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_UVMCallback() API can be implemented in the user file + */ +} + +/** + * @brief PWR IO2VM interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_IO2VMCallback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_IO2VMCallback() API can be implemented in the user file + */ +} + +/** + * @brief PWR AVM1 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_AVM1Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_AVM1Callback() API can be implemented in the user file + */ +} + +/** + * @brief PWR AVM2 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_AVM2Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_AVM2Callback() API can be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group4 Memories Retention Functions + * @brief Memories retention functions + * +@verbatim + =============================================================================== + ##### Memories Retention Functions ##### + =============================================================================== + [..] + Several STM32U5 devices RAMs are configurable to keep / lose RAMs content + during Stop mode (Stop 0/1/2/3). + (+) Retained content RAMs in Stop modes are : + (++) SRAM1 + (++) SRAM2 + (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx, + STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) + (++) SRAM4 + (++) ICACHE + (++) DMA2DRAM (available only for STM32U575xx, STM32U585xx, STM32U59xxx, + STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) + (++) PKA32RAM + (++) DCACHE + (++) FMAC + (++) FDCAN + (++) USB + + [..] + Several STM32U5 devices RAMs are configurable to keep / lose RAMs content + during Run mode. + (+) Retained content RAMs in Run modes are : + (++) SRAM1 + (++) SRAM2 + (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx, + STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) + (++) SRAM4 + + [..] + SRAM2 is configurable to keep / lose its content in Stop 3 and Standby + modes. The SRAM2 retention feature granularity is at pages level. + + [..] + BKPRAM is configurable to keep / lose its content in Standby, Shutdown and + VBAT modes. + +@endverbatim + * @{ + */ + +/** + * @brief Enable SRAM2 page(s) content retention in Stop 3 and Standby mode. + * @note When RRSx bit is set, SRAM2 is powered by the low-power regulator in + * Stop 3 and Standby mode and its content is kept. + * @param SRAM2Pages : Specifies the SRAM2 pages. + * This parameter can be one of the following values : + * @arg PWR_SRAM2_PAGE1_STANDBY : SRAM2 page 1 retention. + * @arg PWR_SRAM2_PAGE2_STANDBY : SRAM2 page 2 retention. + * @arg PWR_SRAM2_FULL_STANDBY : SRAM2 page 1 and page 2 retention. + * @retval None. + */ +void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages) +{ + /* Check the parameters */ + assert_param(IS_PWR_SRAM2_STANDBY_RETENTION(SRAM2Pages)); + + /* Set RRSx bit(s) */ + SET_BIT(PWR->CR1, SRAM2Pages); +} + +/** + * @brief Disable SRAM2 page(s) content retention in Stop 3 and Standby mode. + * @note When RRSx bit is reset, SRAM2 is powered off in Stop 3 and Standby + * mode and its content is lost. + * @param SRAM2Pages : Specifies the SRAM2 pages. + * This parameter can be one of the following values : + * @arg PWR_SRAM2_PAGE1_STANDBY : SRAM2 page 1 retention. + * @arg PWR_SRAM2_PAGE2_STANDBY : SRAM2 page 2 retention. + * @arg PWR_SRAM2_FULL_STANDBY : SRAM2 page 1 and page 2 retention. + * @retval None. + */ +void HAL_PWREx_DisableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages) +{ + /* Check the parameters */ + assert_param(IS_PWR_SRAM2_STANDBY_RETENTION(SRAM2Pages)); + + /* Clear RRSx bit(s) */ + CLEAR_BIT(PWR->CR1, SRAM2Pages); +} + +/** + * @brief Enable RAM page(s) content retention in Stop mode (Stop 0, 1, 2, 3). + * @note When enabling content retention for a given RAM, memory kept powered + * in Stop mode. (Not optimized power consumption) + * @param RAMSelection: Specifies RAM page(s) to be retained in Stop mode. + * This parameter can be one or a combination of the same + * memory @ref PWREx_RAM_Contents_Stop_Retention. + * @retval None. + */ +void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) +{ + uint32_t dummy; + + /* Check RAM ID */ + switch (RAMSelection & SRAM_ID_MASK) + { + /* SRAM 1 Stop retention */ + case SRAM1_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_SRAM1_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID); + CLEAR_BIT(PWR->CR2, dummy); + +#if defined (PWR_CR4_SRAM1PDS4) + /* Calculate pages mask */ + dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID)) >> 0x03U; + CLEAR_BIT(PWR->CR4, dummy); +#endif /* defined (PWR_CR4_SRAM1PDS4) */ + + break; + } + + /* SRAM 2 Stop retention */ + case SRAM2_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_SRAM2_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_SRAM2_FULL_STOP) & ~SRAM_ID_MASK; + CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM2PDS1_Pos)); + + break; + } + +#if defined (PWR_CR2_SRAM3PDS1) + /* SRAM 3 Stop retention */ + case SRAM3_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_SRAM3_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID | + PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID); + CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM3PDS1_Pos)); + +#if defined (PWR_CR4_SRAM3PDS9) + /* Calculate pages mask */ + dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID | + PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID)) >> 0x08U; + CLEAR_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM3PDS9_Pos)); +#endif /* defined (PWR_CR4_SRAM3PDS9) */ + + break; + } +#endif /* PWR_CR2_SRAM3PDS1 */ + + /* SRAM 4 Stop retention */ + case SRAM4_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_SRAM4_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_SRAM4_FULL_STOP) & ~SRAM_ID_MASK; + CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM4PDS_Pos)); + + break; + } + + /* ICACHE RAM Stop retention */ + case ICACHERAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_ICACHE_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_ICACHE_FULL_STOP) & ~SRAM_ID_MASK; + CLEAR_BIT(PWR->CR2, dummy << PWR_CR2_ICRAMPDS_Pos); + + break; + } + + /* DCACHE1 RAM Stop retention */ + case DCACHE1RAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_DCACHE1_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP) & ~SRAM_ID_MASK; + CLEAR_BIT(PWR->CR2, dummy << PWR_CR2_DC1RAMPDS_Pos); + + break; + } + +#if defined (PWR_CR2_DMA2DRAMPDS) + /* DMA2D RAM Stop retention */ + case DMA2DRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_DMA2DRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP) & ~SRAM_ID_MASK; + CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DMA2DRAMPDS_Pos)); + + break; + } +#endif /* PWR_CR2_DMA2DRAMPDS */ + + /* FMAC, FDCAN and USB RAM Stop retention */ + case PERIPHRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_PERIPHRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP) & ~SRAM_ID_MASK; + CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_PRAMPDS_Pos)); + + break; + } + +#if defined (PWR_CR2_PKARAMPDS) + /* PKA32 RAM Stop retention */ + case PKARAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_PKA32RAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP) & ~SRAM_ID_MASK; + CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_PKARAMPDS_Pos)); + + break; + } +#endif /* PWR_CR2_PKARAMPDS */ + +#if defined (PWR_CR2_DC2RAMPDS) + /* DCACHE2 RAM Stop retention */ + case DCACHE2RAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_DCACHE2_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_DCACHE2_FULL_STOP) & ~SRAM_ID_MASK; + CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DC2RAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_DC2RAMPDS) */ + +#if defined (PWR_CR2_GPRAMPDS) + /* LTDC and GFXMMU RAM Stop retention */ + case GRAPHIPRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_GRAPHICPRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_GRAPHICPRAM_FULL_STOP) & ~SRAM_ID_MASK; + CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_GPRAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_GPRAMPDS) */ + +#if defined (PWR_CR2_DSIRAMPDS) + /* DSI RAM Stop retention */ + case DSIRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_DSIRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_DSIRAM_FULL_STOP) & ~SRAM_ID_MASK; + CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DSIRAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_DSIRAMPDS) */ + +#if defined (PWR_CR2_JPEGRAMPDS) + /* JPEG RAM Stop retention */ + case JPEGRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_JPEGRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_JPEGRAM_FULL_STOP) & ~SRAM_ID_MASK; + CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_JPEGRAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_JPEGRAMPDS) */ + +#if defined (PWR_CR4_SRAM5PDS1) + /* SRAM 5 Stop retention */ + case SRAM5_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_SRAM5_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = ((RAMSelection & PWR_SRAM5_FULL_STOP) & ~SRAM_ID_MASK); + CLEAR_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM5PDS1_Pos)); + + break; + } +#endif /* defined (PWR_CR4_SRAM5PDS1) */ + +#if defined (PWR_CR5_SRAM6PDS1) + /* SRAM 6 Stop retention */ + case SRAM6_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_SRAM6_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = ((RAMSelection & PWR_SRAM6_FULL_STOP) & ~SRAM_ID_MASK); + CLEAR_BIT(PWR->CR5, (dummy << PWR_CR5_SRAM6PDS1_Pos)); + + break; + } +#endif /* defined (PWR_CR5_SRAM6PDS1) */ + + default: + { + return; + break; + } + } +} + +/** + * @brief Disable RAM page(s) content lost in Stop mode (Stop 0, 1, 2, 3). + * @note When disabling content lost for a given RAM, memory powered down + * in Stop mode. (Optimized power consumption) + * @param RAMSelection: Specifies RAM page(s) to be lost in Stop mode. + * This parameter can be one or a combination of the same + * memory @ref PWREx_RAM_Contents_Stop_Retention. + * @retval None. + */ +void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) +{ + uint32_t dummy; + + /* Check RAM ID */ + switch (RAMSelection & SRAM_ID_MASK) + { + /* SRAM 1 Stop retention */ + case SRAM1_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_SRAM1_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID); + SET_BIT(PWR->CR2, dummy); +#if defined (PWR_CR4_SRAM1PDS4) + /* Calculate pages mask */ + dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID)) >> 0x03U; + SET_BIT(PWR->CR4, dummy); +#endif /* defined (PWR_CR4_SRAM1PDS4) */ + + break; + } + + /* SRAM 2 Stop retention */ + case SRAM2_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_SRAM2_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_SRAM2_FULL_STOP) & ~SRAM_ID_MASK; + SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM2PDS1_Pos)); + + break; + } + +#if defined (PWR_CR2_SRAM3PDS1) + /* SRAM 3 Stop retention */ + case SRAM3_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_SRAM3_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID | + PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID); + SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM3PDS1_Pos)); + +#if defined (PWR_CR4_SRAM3PDS9) + /* Calculate pages mask */ + dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID | + PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID)) >> 0x08U; + SET_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM3PDS9_Pos)); +#endif /* defined (PWR_CR4_SRAM3PDS9) */ + + break; + } +#endif /* PWR_CR2_SRAM3PDS1 */ + + /* SRAM 4 Stop retention */ + case SRAM4_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_SRAM4_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_SRAM4_FULL_STOP) & ~SRAM_ID_MASK; + SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM4PDS_Pos)); + + break; + } + + /* ICACHE RAM Stop retention */ + case ICACHERAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_ICACHE_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_ICACHE_FULL_STOP) & ~SRAM_ID_MASK; + SET_BIT(PWR->CR2, (dummy << PWR_CR2_ICRAMPDS_Pos)); + + break; + } + + /* DCACHE1 RAM Stop retention */ + case DCACHE1RAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_DCACHE1_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP) & ~SRAM_ID_MASK; + SET_BIT(PWR->CR2, (dummy << PWR_CR2_DC1RAMPDS_Pos)); + + break; + } + +#if defined (PWR_CR2_DMA2DRAMPDS) + /* DMA2D RAM Stop retention */ + case DMA2DRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_DMA2DRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP) & ~SRAM_ID_MASK; + SET_BIT(PWR->CR2, (dummy << PWR_CR2_DMA2DRAMPDS_Pos)); + + break; + } +#endif /* PWR_CR2_DMA2DRAMPDS */ + + /* FMAC, FDCAN and USB RAM Stop retention */ + case PERIPHRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_PERIPHRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP) & ~SRAM_ID_MASK; + SET_BIT(PWR->CR2, (dummy << PWR_CR2_PRAMPDS_Pos)); + + break; + } + +#if defined (PWR_CR2_PKARAMPDS) + /* PKA32 RAM Stop retention */ + case PKARAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_PKA32RAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP) & ~SRAM_ID_MASK; + SET_BIT(PWR->CR2, (dummy << PWR_CR2_PKARAMPDS_Pos)); + + break; + } +#endif /* PWR_CR2_PKARAMPDS */ + +#if defined (PWR_CR2_DC2RAMPDS) + /* DCACHE2 RAM Stop retention */ + case DCACHE2RAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_DCACHE2_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_DCACHE2_FULL_STOP) & ~SRAM_ID_MASK; + SET_BIT(PWR->CR2, (dummy << PWR_CR2_DC2RAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_DC2RAMPDS) */ + +#if defined (PWR_CR2_GPRAMPDS) + /* LTDC and GFXMMU RAM Stop retention */ + case GRAPHIPRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_GRAPHICPRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_GRAPHICPRAM_FULL_STOP) & ~SRAM_ID_MASK; + SET_BIT(PWR->CR2, (dummy << PWR_CR2_GPRAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_GPRAMPDS) */ + +#if defined (PWR_CR2_DSIRAMPDS) + /* DSI RAM Stop retention */ + case DSIRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_DSIRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_DSIRAM_FULL_STOP) & ~SRAM_ID_MASK; + SET_BIT(PWR->CR2, (dummy << PWR_CR2_DSIRAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_DSIRAMPDS) */ + +#if defined (PWR_CR2_JPEGRAMPDS) + /* JPEG RAM Stop retention */ + case JPEGRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_JPEGRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_JPEGRAM_FULL_STOP) & ~SRAM_ID_MASK; + SET_BIT(PWR->CR2, (dummy << PWR_CR2_JPEGRAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_JPEGRAMPDS) */ + +#if defined (PWR_CR4_SRAM5PDS1) + /* SRAM 5 Stop retention */ + case SRAM5_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_SRAM5_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = ((RAMSelection & PWR_SRAM5_FULL_STOP) & ~SRAM_ID_MASK); + SET_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM5PDS1_Pos)); + + break; + } +#endif /* defined (PWR_CR4_SRAM5PDS1) */ + +#if defined (PWR_CR5_SRAM6PDS1) + /* SRAM 6 Stop retention */ + case SRAM6_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_SRAM6_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = ((RAMSelection & PWR_SRAM6_FULL_STOP) & ~SRAM_ID_MASK); + SET_BIT(PWR->CR5, (dummy << PWR_CR5_SRAM6PDS1_Pos)); + + break; + } +#endif /* defined (PWR_CR5_SRAM6PDS1) */ + + default: + { + return; + break; + } + } +} + +/** + * @brief Enable RAMs full content retention in Run mode. + * @param RAMSelection : Specifies the SRAM content to be retained in Run mode. + * This parameter can be one or a combination of the following values : + * @arg PWR_SRAM1_FULL_RUN : SRAM1 full content retention. + * @arg PWR_SRAM2_FULL_RUN : SRAM2 full content retention. + * @arg PWR_SRAM3_FULL_RUN : SRAM3 full content retention (available only for STM32U575xx, + * STM32U585xx STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + and STM32U5Gxxx devices). + * @arg PWR_SRAM4_FULL_RUN : SRAM4 full content retention. + * @arg PWR_SRAM5_FULL_RUN : SRAM5 full content retention (available only for + * STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + * and STM32U5Gxxx devices). + * @arg PWR_SRAM6_FULL_RUN : SRAM6 full content retention (available only for + * STM32U5Fxxx and STM32U5Gxxx devices). + * @retval None. + */ +void HAL_PWREx_EnableRAMsContentRunRetention(uint32_t RAMSelection) +{ + /* Check the parameters */ + assert_param(IS_PWR_RAM_RUN_RETENTION(RAMSelection)); + + /* Enable RAM retention in Run mode */ + CLEAR_BIT(PWR->CR1, RAMSelection); +} + +/** + * @brief Disable RAMs full content retention in Run mode. + * @param RAMSelection : Specifies the SRAM content to be lost in Run mode. + * This parameter can be one or a combination of the following values : + * @arg PWR_SRAM1_FULL_RUN : SRAM1 full content lost. + * @arg PWR_SRAM2_FULL_RUN : SRAM2 full content lost. + * @arg PWR_SRAM3_FULL_RUN : SRAM3 full content lost (available only for STM32U575xx, + * STM32U585xx STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + and STM32U5Gxxx devices). + * @arg PWR_SRAM4_FULL_RUN : SRAM4 full content lost. + * @arg PWR_SRAM5_FULL_RUN : SRAM5 full content retention (available only for + * STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + * and STM32U5Gxxx devices). + * @arg PWR_SRAM6_FULL_RUN : SRAM6 full content retention (available only for + * STM32U5Fxxx and STM32U5Gxxx devices). + * @retval None. + */ +void HAL_PWREx_DisableRAMsContentRunRetention(uint32_t RAMSelection) +{ + /* Check the parameters */ + assert_param(IS_PWR_RAM_RUN_RETENTION(RAMSelection)); + + /* Disable RAM retention in Run mode */ + SET_BIT(PWR->CR1, RAMSelection); +} + +/** + * @brief Enable the Backup RAM retention in Standby, Shutdown and VBAT modes. + * @note If BREN is reset, the backup RAM can still be used in Run, Sleep and + * Stop modes. However, its content is lost in Standby, Shutdown and + * VBAT modes. + * @note This bit can be enabled only when LDO regulator is selected as + * source supply. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWREx_EnableBkupRAMRetention(void) +{ + /* + Backup RAM retention in Standby, Shutdown and VBAT should be enabled + when the Vcore is alimented by the LDO regulator + */ + if (HAL_PWREx_GetSupplyConfig() == PWR_LDO_SUPPLY) + { + SET_BIT(PWR->BDCR1, PWR_BDCR1_BREN); + } + /* SMPS regulator selected */ + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disable the Backup RAM retention in Standby, Shutdown and VBAT modes. + * @note If BREN is reset, the backup RAM can still be used in Run, Sleep and + * Stop modes. However, its content is lost in Standby, Shutdown and + * VBAT modes. This bit can be writte + * @retval None. + */ +void HAL_PWREx_DisableBkupRAMRetention(void) +{ + CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_BREN); +} + +/** + * @brief Enable the flash memory fast wakeup from Stop 0 and Stop 1 modes. + * @note This feature is used to obtain the best trade-off between low-power + * consumption and wakeup time when exiting the Stop 0 or Stop 1 modes. + * When this feature is enabled, the Flash memory remains in normal + * mode in Stop 0 and Stop 1 modes, which offers a faster startup time + * with higher consumption. + * @retval None. + */ +void HAL_PWREx_EnableFlashFastWakeUp(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_FLASHFWU); +} + +/** + * @brief Disable the Flash Power Down in Stop mode. + * @note This feature is used to obtain the best trade-off between low-power + * consumption and wakeup time when exiting the Stop 0 or Stop 1 modes. + * When this feature is disabled, the Flash memory enters low-power + * mode in Stop 0 and Stop 1 modes, which causes a slower startup time + * with lower consumption. + * @retval None. + */ +void HAL_PWREx_DisableFlashFastWakeUp(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_FLASHFWU); +} + +/** + * @brief Enable the SRAM4 memory fast wakeup from Stop 0, Stop 1 and Stop 2 modes. + * @note This bit is used to obtain the best trade-off between low-power consumption + * and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting + * Stop 0, Stop 1 and Stop 2 modes, and also increases the LPDMA access time + * to SRAM4 during Stop modes. + * @retval None. + */ +void HAL_PWREx_EnableSRAM4FastWakeUp(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_SRAM4FWU); +} + +/** + * @brief Disable the SRAM4 memory fast wakeup from Stop 0, Stop 1 and Stop 2 modes. + * @note This bit is used to obtain the best trade-off between low-power consumption + * and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting + * Stop 0, Stop 1 and Stop 2 modes, and also increases the LPDMA access time + * to SRAM4 during Stop modes. + * @retval None. + */ +void HAL_PWREx_DisableSRAM4FastWakeUp(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_SRAM4FWU); +} +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group5 I/O Pull-Up Pull-Down Configuration Functions + * @brief I/O pull-up / pull-down configuration functions + * +@verbatim + =============================================================================== + ##### IO Pull-Up Pull-Down Configuration Functions ##### + =============================================================================== + [..] + In Standby and Shutdown mode, pull up and pull down can be configured to + maintain an I/O in the selected state. If the APC bit in the PWR_APCR + register is set, the I/Os can be configured either with a pull-up through + PWR_PUCRx registers (x=A,B,C,D,E,F,G,H,I,J), or with a pull-down through + PWR_PDCRx registers (x=A,B,C,D,E,F,G,H,I,J)), or can be kept in analog state + if none of the PWR_PUCRx or PWR_PDCRx register is set. + (+) Port J is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + and STM32U5Gxxx devices. + + [..] + The pull-down configuration has highest priority over pull-up + configuration in case both PWR_PUCRx and PWR_PDCRx are set for the same + I/O. + This configuration is lost when exiting the Shutdown but not from Standby + mode. + +@endverbatim + * @{ + */ + +/** + * @brief Enable pull-up and pull-down configuration. + * @note When APC bit is set, the I/O pull-up and pull-down configurations + * defined in PWR_PUCRx and PWR_PDCRx registers are applied in Standby + * and Shutdown modes. + * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the + * corresponding PDy bit of PWR_PDCRx register is also set (pull-down + * configuration priority is higher). HAL_PWREx_EnableGPIOPullUp() and + * HAL_PWREx_EnableGPIOPullDown() API's ensure there is no conflict + * when setting PUy or PDy bit. + * @retval None. + */ +void HAL_PWREx_EnablePullUpPullDownConfig(void) +{ + SET_BIT(PWR->APCR, PWR_APCR_APC); +} + +/** + * @brief Disable pull-up and pull-down configuration. + * @note When APC bit is cleared, the I/O pull-up and pull-down configurations + * defined in PWR_PUCRx and PWR_PDCRx registers are not applied in + * Standby and Shutdown modes. + * @retval None. + */ +void HAL_PWREx_DisablePullUpPullDownConfig(void) +{ + CLEAR_BIT(PWR->APCR, PWR_APCR_APC); +} + +/** + * @brief Enable GPIO pull-up state in Standby and Shutdown modes. + * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O + * in pull-up state in Standby and Shutdown modes. + * @note This state is effective in Standby and Shutdown modes only if APC + * bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @note The configuration is lost when exiting the Shutdown mode due to the + * power-on reset, maintained when exiting the Standby mode. + * @note To avoid any conflict at Standby and Shutdown modes exits, the + * corresponding PDy bit of PWR_PDCRx register is cleared unless it is + * reserved. + * @note Even if a PUy bit to set is reserved, the other PUy bits entered as + * input parameter at the same time are set. + * @param GPIO_Port : Specify the IO port. + * This parameter can be a value of + * @ref PWREx_GPIO_Port. + * @param GPIO_Pin : Specify the I/O pins numbers. + * This parameter can be a value of + * @ref PWREx_GPIO_Pin_Mask. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_PWR_GPIO_PORT(GPIO_Port)); + assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin)); + + /* Check GPIO port */ + switch (GPIO_Port) + { + case PWR_GPIO_A: /* Apply Pull Up to GPIO port A */ + SET_BIT(PWR->PUCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_14)))); + CLEAR_BIT(PWR->PDCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15)))); + break; + + case PWR_GPIO_B: /* Apply Pull Up to GPIO port B */ + SET_BIT(PWR->PUCRB, GPIO_Pin); + CLEAR_BIT(PWR->PDCRB, (GPIO_Pin & (~(PWR_GPIO_BIT_4)))); + break; + + case PWR_GPIO_C: /* Apply Pull Up to GPIO port C */ + SET_BIT(PWR->PUCRC, GPIO_Pin); + CLEAR_BIT(PWR->PDCRC, GPIO_Pin); + break; + + case PWR_GPIO_D: /* Apply Pull Up to GPIO port D */ + SET_BIT(PWR->PUCRD, GPIO_Pin); + CLEAR_BIT(PWR->PDCRD, GPIO_Pin); + break; + + case PWR_GPIO_E: /* Apply Pull Up to GPIO port E */ + SET_BIT(PWR->PUCRE, GPIO_Pin); + CLEAR_BIT(PWR->PDCRE, GPIO_Pin); + break; + +#ifdef PWR_PUCRF_PU0 + case PWR_GPIO_F: /* Apply Pull Up to GPIO port F */ + SET_BIT(PWR->PUCRF, GPIO_Pin); + CLEAR_BIT(PWR->PDCRF, GPIO_Pin); + break; +#endif /* PWR_PUCRF_PU0 */ + + case PWR_GPIO_G: /* Apply Pull Up to GPIO port G */ + SET_BIT(PWR->PUCRG, GPIO_Pin); + CLEAR_BIT(PWR->PDCRG, GPIO_Pin); + break; + + case PWR_GPIO_H: /* Apply Pull Up to GPIO port H */ + SET_BIT(PWR->PUCRH, GPIO_Pin); + CLEAR_BIT(PWR->PDCRH, GPIO_Pin); + break; + +#ifdef PWR_PUCRI_PU0 + case PWR_GPIO_I: /* Apply Pull Up to GPIO port I */ + SET_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); + CLEAR_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); + break; +#endif /* PWR_PUCRI_PU0 */ + +#if defined (PWR_PUCRJ_PU0) + case PWR_GPIO_J: /* Apply Pull Up to GPIO port J */ + SET_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); + CLEAR_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); + break; +#endif /* defined (PWR_PUCRJ_PU0) */ + + default: + return HAL_ERROR; + break; + } + + return HAL_OK; +} + +/** + * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes. + * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure + * the I/O in pull-up state in Standby and Shutdown modes. + * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as + * input parameter at the same time are reset. + * @param GPIO_Port : Specify the IO port. + * This parameter can be a value of + * @ref PWREx_GPIO_Port. + * @param GPIO_Pin : Specify the I/O pins numbers. + * This parameter can be a value of + * @ref PWREx_GPIO_Pin_Mask. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_PWR_GPIO_PORT(GPIO_Port)); + assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin)); + + /* Check GPIO port */ + switch (GPIO_Port) + { + case PWR_GPIO_A: /* Disable Pull Up for GPIO port A */ + CLEAR_BIT(PWR->PUCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_14)))); + break; + + case PWR_GPIO_B: /* Disable Pull Up for GPIO port B */ + CLEAR_BIT(PWR->PUCRB, GPIO_Pin); + break; + + case PWR_GPIO_C: /* Disable Pull Up for GPIO port C */ + CLEAR_BIT(PWR->PUCRC, GPIO_Pin); + break; + + case PWR_GPIO_D: /* Disable Pull Up for GPIO port D */ + CLEAR_BIT(PWR->PUCRD, GPIO_Pin); + break; + + case PWR_GPIO_E: /* Disable Pull Up for GPIO port E */ + CLEAR_BIT(PWR->PUCRE, GPIO_Pin); + break; + +#ifdef PWR_PUCRF_PU0 + case PWR_GPIO_F: /* Disable Pull Up for GPIO port F */ + CLEAR_BIT(PWR->PUCRF, GPIO_Pin); + break; +#endif /* PWR_PUCRF_PU0 */ + + case PWR_GPIO_G: /* Disable Pull Up for GPIO port G */ + CLEAR_BIT(PWR->PUCRG, GPIO_Pin); + break; + + case PWR_GPIO_H: /* Disable Pull Up for GPIO port H */ + CLEAR_BIT(PWR->PUCRH, GPIO_Pin); + break; + +#ifdef PWR_PUCRI_PU0 + case PWR_GPIO_I: /* Disable Pull Up for GPIO port I */ + CLEAR_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); + break; +#endif /* PWR_PUCRI_PU0 */ + +#if defined (PWR_PUCRJ_PU0) + case PWR_GPIO_J: /* Disable Pull Up for GPIO port J */ + CLEAR_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); + break; +#endif /* defined (PWR_PUCRJ_PU0) */ + + default: + return HAL_ERROR; + break; + } + + return HAL_OK; +} + +/** + * @brief Enable GPIO pull-down state in Standby and Shutdown modes. + * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O + * in pull-down state in Standby and Shutdown modes. + * @note This state is effective in Standby and Shutdown modes only if APC bit + * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @note The configuration is lost when exiting the Shutdown mode due to the + * power-on reset, maintained when exiting the Standby mode. + * @note To avoid any conflict at Standby and Shutdown modes exits, the + * corresponding PUy bit of PWR_PUCRx register is cleared unless it is + * reserved. + * @note Even if a PDy bit to set is reserved, the other PDy bits entered as + * input parameter at the same time are set. + * @param GPIO_Port : Specify the IO port. + * This parameter can be a value of + * @ref PWREx_GPIO_Port. + * @param GPIO_Pin : Specify the I/O pins numbers. + * This parameter can be a value of + * @ref PWREx_GPIO_Pin_Mask. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_PWR_GPIO_PORT(GPIO_Port)); + assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin)); + + /* Check GPIO port */ + switch (GPIO_Port) + { + case PWR_GPIO_A: /* Apply Pull Down to GPIO port A */ + SET_BIT(PWR->PDCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15)))); + CLEAR_BIT(PWR->PUCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_14)))); + break; + + case PWR_GPIO_B: /* Apply Pull Down to GPIO port B */ + SET_BIT(PWR->PDCRB, (GPIO_Pin & (~(PWR_GPIO_BIT_4)))); + CLEAR_BIT(PWR->PUCRB, GPIO_Pin); + break; + + case PWR_GPIO_C: /* Apply Pull Down to GPIO port C */ + SET_BIT(PWR->PDCRC, GPIO_Pin); + CLEAR_BIT(PWR->PUCRC, GPIO_Pin); + break; + + case PWR_GPIO_D: /* Apply Pull Down to GPIO port D */ + SET_BIT(PWR->PDCRD, GPIO_Pin); + CLEAR_BIT(PWR->PUCRD, GPIO_Pin); + break; + + case PWR_GPIO_E: /* Apply Pull Down to GPIO port E */ + SET_BIT(PWR->PDCRE, GPIO_Pin); + CLEAR_BIT(PWR->PUCRE, GPIO_Pin); + break; + +#ifdef PWR_PUCRF_PU0 + case PWR_GPIO_F: /* Apply Pull Down to GPIO port F */ + SET_BIT(PWR->PDCRF, GPIO_Pin); + CLEAR_BIT(PWR->PUCRF, GPIO_Pin); + break; +#endif /* PWR_PUCRF_PU0 */ + + case PWR_GPIO_G: /* Apply Pull Down to GPIO port G */ + SET_BIT(PWR->PDCRG, GPIO_Pin); + CLEAR_BIT(PWR->PUCRG, GPIO_Pin); + break; + + case PWR_GPIO_H: /* Apply Pull Down to GPIO port H */ + SET_BIT(PWR->PDCRH, GPIO_Pin); + CLEAR_BIT(PWR->PUCRH, GPIO_Pin); + break; + +#ifdef PWR_PUCRI_PU0 + case PWR_GPIO_I: /* Apply Pull Down to GPIO port I */ + SET_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); + CLEAR_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); + break; +#endif /* PWR_PUCRI_PU0 */ + +#if defined (PWR_PUCRJ_PU0) + case PWR_GPIO_J: /* Apply Pull Down to GPIO port J */ + SET_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); + CLEAR_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); + break; +#endif /* defined (PWR_PUCRJ_PU0) */ + + default: + return HAL_ERROR; + break; + } + + return HAL_OK; +} + +/** + * @brief Disable GPIO pull-down state in Standby and Shutdown modes. + * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O + * in pull-down state in Standby and Shutdown modes. + * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input + * parameter at the same time are reset. + * @param GPIO_Port : Specify the IO port. + * This parameter can be a value of + * @ref PWREx_GPIO_Port. + * @param GPIO_Pin : Specify the I/O pins numbers. + * This parameter can be a value of + * @ref PWREx_GPIO_Pin_Mask. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_PWR_GPIO_PORT(GPIO_Port)); + assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin)); + + /* Check GPIO port */ + switch (GPIO_Port) + { + case PWR_GPIO_A: /* Disable Pull Down for GPIO port A */ + CLEAR_BIT(PWR->PDCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15)))); + break; + + case PWR_GPIO_B: /* Disable Pull Down for GPIO port B */ + CLEAR_BIT(PWR->PDCRB, (GPIO_Pin & (~(PWR_GPIO_BIT_4)))); + break; + + case PWR_GPIO_C: /* Disable Pull Down for GPIO port C */ + CLEAR_BIT(PWR->PDCRC, GPIO_Pin); + break; + + case PWR_GPIO_D: /* Disable Pull Down for GPIO port D */ + CLEAR_BIT(PWR->PDCRD, GPIO_Pin); + break; + + case PWR_GPIO_E: /* Disable Pull Down for GPIO port E */ + CLEAR_BIT(PWR->PDCRE, GPIO_Pin); + break; + +#ifdef PWR_PUCRF_PU0 + case PWR_GPIO_F: /* Disable Pull Down for GPIO port F */ + CLEAR_BIT(PWR->PDCRF, GPIO_Pin); + break; +#endif /* PWR_PUCRF_PU0 */ + + case PWR_GPIO_G: /* Disable Pull Down for GPIO port G */ + CLEAR_BIT(PWR->PDCRG, GPIO_Pin); + break; + + case PWR_GPIO_H: /* Disable Pull Down for GPIO port H */ + CLEAR_BIT(PWR->PDCRH, GPIO_Pin); + break; + +#ifdef PWR_PUCRI_PU0 + case PWR_GPIO_I: /* Disable Pull Down for GPIO port I */ + CLEAR_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); + break; +#endif /* PWR_PUCRI_PU0 */ + +#if defined (PWR_PUCRJ_PU0) + case PWR_GPIO_J: /* Disable Pull Down for GPIO port J */ + CLEAR_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); + break; +#endif /* defined (PWR_PUCRJ_PU0) */ + + default: + return HAL_ERROR; + break; + } + + return HAL_OK; +} +/** + * @} + */ + +#endif /* defined (HAL_PWR_MODULE_ENABLED) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c new file mode 100644 index 000000000..fccf443b0 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c @@ -0,0 +1,2304 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Multiple Speed Internal oscillator + (4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache + and I-Cache are disabled, and all peripherals are off except internal + SRAM, Flash and JTAG. + + (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses: + all peripherals mapped on these busses are running at MSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in analog mode, except the JTAG pins which + are assigned to be used for debug purpose. + + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB busses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals which clocks are not + derived from the System clock (SAIx, SYSTICK, RTC, ADC, USB OTG FS/USB FS/SDMMC1/RNG) + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +#define PLLDIVR_RESET_VALUE (0x01010280U) +#define PLL_FRAC_WAIT_VALUE 1U /* PLL Fractional part waiting time before new latch enable : 1 ms */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_Private_Macros + * @{ + */ +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U)) + +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS) || ((__HSE__) == RCC_HSE_BYPASS_DIGITAL)) + +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \ + ((__LSE__) == RCC_LSE_BYPASS)) + +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) + +#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR3_HSITRIM >>\ + RCC_ICSCR3_HSITRIM_Pos)) + +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) + +#define IS_RCC_LSIDIV(__LSIDIV__) (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128)) + +#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) + +#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U) + +#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) + +#define IS_RCC_SHSI(__SHSI__) (((__SHSI__) == RCC_SHSI_OFF) || ((__SHSI__) == RCC_SHSI_ON)) + +#define IS_RCC_MSIK(__MSIK__) (((__MSIK__) == RCC_MSIK_OFF) || ((__MSIK__) == RCC_MSIK_ON)) + +#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \ + ((PLL) == RCC_PLL_ON)) + +#define IS_RCC_PLLMBOOST_VALUE(VALUE) (((VALUE) == RCC_PLLMBOOST_DIV1) || \ + ((VALUE) == RCC_PLLMBOOST_DIV2) || \ + ((VALUE) == RCC_PLLMBOOST_DIV4) || \ + ((VALUE) == RCC_PLLMBOOST_DIV6) || \ + ((VALUE) == RCC_PLLMBOOST_DIV8) || \ + ((VALUE) == RCC_PLLMBOOST_DIV10) || \ + ((VALUE) == RCC_PLLMBOOST_DIV12) || \ + ((VALUE) == RCC_PLLMBOOST_DIV14) || \ + ((VALUE) == RCC_PLLMBOOST_DIV16)) + +#define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \ + ((VALUE) == RCC_PLL1_DIVQ) || \ + ((VALUE) == RCC_PLL1_DIVR)) + +#define IS_RCC_PLLRGE_VALUE(VALUE) (((VALUE) == RCC_PLLVCIRANGE_0) || \ + ((VALUE) == RCC_PLLVCIRANGE_1)) + +#define IS_RCC_PLL_FRACN_VALUE(VALUE) ((VALUE) <= 8191U) + +#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x1FU)) + +#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) + +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ + ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ + ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ + ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ + ((__HCLK__) == RCC_SYSCLK_DIV512)) + +#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ + ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ + ((__PCLK__) == RCC_HCLK_DIV16)) + +#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) + +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLL1CLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)|| \ + ((__SOURCE__) == RCC_MCO1SOURCE_MSIK)) + +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ + ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ + ((__DIV__) == RCC_MCODIV_16)) + +#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ + ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) + +#define IS_RCC_ITEM_ATTRIBUTES(ITEM) ((0U < (ITEM)) && ((ITEM) <= 0x1FFFU)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_SEC_PRIV) || \ + ((ATTRIBUTES) == RCC_SEC_NPRIV) || \ + ((ATTRIBUTES) == RCC_NSEC_PRIV) || \ + ((ATTRIBUTES) == RCC_NSEC_NPRIV)) +#else +#define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_NSEC_NPRIV) || ((ATTRIBUTES) == RCC_NSEC_PRIV)) +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +#define LSI_TIMEOUT_VALUE 5UL /* 5 ms (LSI maximum timeout is LSI startup time + LSI_VALUE/128 when + LSI prediv is used) */ +#define HSI48_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ +#define SHSI_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ +#define MSIK_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ +#define PLL_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ +#define CLOCKSWITCH_TIMEOUT_VALUE 5000UL /* 5 s */ +#define EPOD_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() + +#define MCO1_GPIO_PORT GPIOA + +#define MCO1_PIN GPIO_PIN_8 + +#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \ + (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__))) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCC_Private_Functions RCC Private Functions + * @{ + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal and external oscillators + (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 + and APB2). + + [..] Internal/external clock and PLL configuration + (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + + (+) MSI (Multiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ. + It can be used to generate the clock for the USB FS or USB OTG FS (48 MHz). + The number of flash wait states is automatically adjusted when MSI range is updated with + HAL_RCC_OscConfig() and the MSI is used as System clock source. + + (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also optionally as RTC clock source. + + (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source. + + (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks: + (++) The first output is used to generate the high speed system clock (up to 80MHz). + (++) The second output is used to generate the clock for the USB FS or USB OTG FS (48 MHz), + the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). + (++) The third output is used to generate an accurate clock to achieve + high-quality audio performance on SAI interface. + + (+) PLL2 (clocked by HSI, HSE or MSI) providing up to three independent output clocks: + (++) The first output is used to generate SAR ADC1 clock. + (++) The second output is used to generate the clock for the USB Fs or USB OTG FS (48 MHz), + the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). + (++) The Third output is used to generate an accurate clock to achieve + high-quality audio performance on SAI interface. + + (+) PLL3 (clocked by HSI , HSE or MSI) providing up to two independent output clocks: + (++) The first output is used to generate SAR ADC4 clock. + (++) The second output is used to generate an accurate clock to achieve + high-quality audio performance on SAI interface. + + (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs + (HSE used directly or through PLL as System clock source), the System clock + is automatically switched to HSI and an interrupt is generated if enabled. + The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) + exception vector. + + (+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE or + main PLL clock (through a configurable prescaler) on PA8 pin. + + [..] System, AHB and APB busses clocks configuration + (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI, + HSE and main PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these busses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + + (+@) SAI: the SAI clock can be derived either from a specific PLL (PLL2) or (PLL3) or + from an external clock mapped on the SAI_CKIN pin. + You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock. + (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 2 to 31. + You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function + to configure this clock. + (+@) USB FS, USB OTG FS, SDMMC1 and RNG: USB OTG FS or USB FS requires a frequency equal to 48 MHz + to work correctly, while the SDMMC1 and RNG peripherals require a frequency + equal or lower than to 48 MHz. This clock is derived of the main PLL or PLL2 + through PLLQ divider. You have to enable the peripheral clock and use + HAL_RCCEx_PeriphCLKConfig() function to configure this clock. + (+@) IWDG clock which is always the LSI clock. + + + (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz. + The clock source frequency should be adapted depending on the device voltage range + as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter. + + @endverbatim + + + Table 1. HCLK clock frequency for STM32U5xx devices + +-------------------------------------------------------+----------------------------------------+ + | Latency | HCLK clock frequency (MHz) 0.9V-1.2V | + | |-------------------------------------|---------------------+------------------| + | | voltage range 1 | voltage range 2 | voltage range 3 | voltage range 4 | + | | 1.1 V - 1.2V | 1.0 V - 1.1V | 0.9 V - 1.0V | 0.9V | + |-----------------|------------------|------------------|---------------------|------------------| + |0WS(1 CPU cycles)| 0 < HCLK <= 32 | 0 < HCLK <= 25 | 0 < HCLK <= 12.5 | 0 < HCLK <= 8 | + |-----------------|------------------|------------------|---------------------|------------------| + |1WS(2 CPU cycles)| 32 < HCLK <= 64 | 25 < HCLK <= 50 | 12.5 < HCLK <= 25 | 8 < HCLK <= 16 | + |-----------------|------------------|------------------|---------------------|------------------| + |2WS(3 CPU cycles)| 64 < HCLK <= 96 | 50 < HCLK <= 75 | 25 < HCLK <= 37.5 | 16 < HCLK <= 24 | + |-----------------|------------------|------------------|---------------------|------------------| + |3WS(4 CPU cycles)| 96 < HCLK <= 128 | 75 < HCLK <= 100 | 37.5 < HCLK <= 50 | - | + |-----------------|------------------|------------------|---------------------|------------------| + |4WS(5 CPU cycles)|128 < HCLK <= 160 | - | - | - | + +-----------------+------------------+------------------+---------------------+------------------+ + * @{ + */ + +/** + * @brief Reset the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - MSI ON and used as system clock source + * - HSE, HSI, PLL, PLL2 and PLLISAI2 OFF + * - AHB, APB1 and APB2 prescaler set to 1 + * - CSS, MCO1 OFF + * - All interrupts disabled + * - All interrupt and reset flags cleared + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + tickstart = HAL_GetTick(); + + /* Set MSION bit */ + SET_BIT(RCC->CR, RCC_CR_MSISON); + + /* Insure MSIRDY bit is set before writing default MSIRANGE value */ + while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set MSIRANGE default value */ + MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, RCC_MSIRANGE_4); + + /* Set MSITRIM default value */ + WRITE_REG(RCC->ICSCR2, 0x00084210U); + + /* Set MSIKRANGE default value */ + MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE, RCC_MSIKRANGE_4); + + /* Set MSIRGSEL default value */ + MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL, 0x0U); + + tickstart = HAL_GetTick(); + + /* Reset CFGR register (MSI is selected as system clock source) */ + CLEAR_REG(RCC->CFGR1); + CLEAR_REG(RCC->CFGR2); + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS) != 0U) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset MSIKON, HSECSSON , HSEON, HSEBYP, HSION, HSIKERON, PLL1ON, PLL2ON, PLL3ON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_MSIKON | RCC_CR_MSIPLLSEL | RCC_CR_MSIPLLFAST | RCC_CR_MSIKERON | RCC_CR_CSSON | \ + RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON | RCC_CR_HSI48ON | \ + RCC_CR_HSEON | RCC_CR_SHSION); + + /* Reset HSEBYP & HSEEXT bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP | RCC_CR_HSEEXT); + + tickstart = HAL_GetTick(); + + /* Clear PLL1ON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); + + /* Wait till PLL1 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + tickstart = HAL_GetTick(); + + /* Reset PLL2N bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); + + /* Wait till PLL2 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + tickstart = HAL_GetTick(); + + /* Reset PLL3 bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); + + /* Wait till PLL3 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset PLL1CFGR register */ + CLEAR_REG(RCC->PLL1CFGR); + + /* Reset PLL1DIVR register */ + WRITE_REG(RCC->PLL1DIVR, PLLDIVR_RESET_VALUE); + + /* Reset PLL1FRACR register */ + CLEAR_REG(RCC->PLL1FRACR); + + /* Reset PLL2CFGR register */ + CLEAR_REG(RCC->PLL2CFGR); + + /* Reset PLL2DIVR register */ + WRITE_REG(RCC->PLL2DIVR, PLLDIVR_RESET_VALUE); + + /* Reset PLL2FRACR register */ + CLEAR_REG(RCC->PLL2FRACR); + + /* Reset PLL3CFGR register */ + CLEAR_REG(RCC->PLL3CFGR); + + /* Reset PLL3DIVR register */ + WRITE_REG(RCC->PLL3DIVR, PLLDIVR_RESET_VALUE); + + /* Reset PLL3FRACR register */ + CLEAR_REG(RCC->PLL3FRACR); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIER); + + /* Clear all interrupts flags */ + WRITE_REG(RCC->CICR, 0xFFFFFFFFU); + + /* Reset all CSR flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = MSI_VALUE; + + /* Decreasing the number of wait states because of lower CPU frequency */ + + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) + { + return HAL_ERROR; + } + + /* Adapt Systick interrupt period */ + return (HAL_InitTick(TICK_INT_PRIORITY)); + +} + +/** + * @brief Initialize the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param pRCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this function. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this function. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruct) +{ + uint32_t tickstart; + HAL_StatusTypeDef status; + uint32_t sysclk_source; + uint32_t pll_config; + FlagStatus pwrboosten = RESET; + uint32_t temp1_pllckcfg; + uint32_t temp2_pllckcfg; + + /* Check Null pointer */ + if (pRCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(pRCC_OscInitStruct->OscillatorType)); + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); + + /*----------------------------- MSI Configuration --------------------------*/ + if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + { + /* Check the parameters */ + assert_param(IS_RCC_MSI(pRCC_OscInitStruct->MSIState)); + assert_param(IS_RCC_MSICALIBRATION_VALUE(pRCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(pRCC_OscInitStruct->MSIClockRange)); + + /*Check if MSI is used as system clock or as PLL source when PLL is selected as system clock*/ + + if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) || + ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_MSI))) + { + if (pRCC_OscInitStruct->MSIState == RCC_MSI_OFF) + { + return HAL_ERROR; + } + + /* Otherwise, just the calibration and MSI range change are allowed */ + else + { + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device */ + if (pRCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) + { + /* Decrease number of wait states update if necessary */ + /* Only possible when MSI is the System clock source */ + if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) + { + if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK) + { + return HAL_ERROR; + } + } + + /* Selects the Multiple Speed oscillator (MSI) clock range */ + __HAL_RCC_MSI_RANGE_CONFIG(pRCC_OscInitStruct->MSIClockRange); + /* Adjusts the Multiple Speed oscillator (MSI) calibration value */ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \ + (pRCC_OscInitStruct->MSIClockRange)); + } + else + { + /* Else, keep current flash latency while decreasing applies */ + /* Selects the Multiple Speed oscillator (MSI) clock range */ + __HAL_RCC_MSI_RANGE_CONFIG(pRCC_OscInitStruct->MSIClockRange); + /* Adjusts the Multiple Speed oscillator (MSI) calibration value */ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \ + (pRCC_OscInitStruct->MSIClockRange)); + + if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) + { + if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK) + { + return HAL_ERROR; + } + } + } + + /* Update the SystemCoreClock global variable */ + (void) HAL_RCC_GetHCLKFreq(); + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + if (status != HAL_OK) + { + return status; + } + } + } + else + { + /* Check the MSI State */ + if (pRCC_OscInitStruct->MSIState != RCC_MSI_OFF) + { + /* Enable the Internal High Speed oscillator (MSI) */ + __HAL_RCC_MSI_ENABLE(); + + tickstart = HAL_GetTick(); + + /* Wait till MSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Selects the Multiple Speed oscillator (MSI) clock range */ + __HAL_RCC_MSI_RANGE_CONFIG(pRCC_OscInitStruct->MSIClockRange); + /* Adjusts the Multiple Speed oscillator (MSI) calibration value */ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \ + (pRCC_OscInitStruct->MSIClockRange)); + + } + else + { + /* Disable the Internal High Speed oscillator (MSI) */ + __HAL_RCC_MSI_DISABLE(); + + tickstart = HAL_GetTick(); + + /* Wait till MSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------- HSE Configuration ------------------------*/ + if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(pRCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) || + ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) + { + if (pRCC_OscInitStruct->HSEState == RCC_HSE_OFF) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(pRCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if (pRCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(pRCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(pRCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) || + ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) + { + /* When HSI is used as system clock it will not be disabled */ + if (pRCC_OscInitStruct->HSIState == RCC_HSI_OFF) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value */ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(pRCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if (pRCC_OscInitStruct->HSIState != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI) */ + __HAL_RCC_HSI_ENABLE(); + + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value */ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(pRCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI) */ + __HAL_RCC_HSI_DISABLE(); + + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(pRCC_OscInitStruct->LSIState)); + + FlagStatus pwrclkchanged = RESET; + + /* Update LSI configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->DBPR, PWR_DBPR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + /* Check the LSI State */ + if (pRCC_OscInitStruct->LSIState != RCC_LSI_OFF) + { + uint32_t bdcr_temp = RCC->BDCR; + + /* Check LSI division factor */ + assert_param(IS_RCC_LSIDIV(pRCC_OscInitStruct->LSIDiv)); + + if (pRCC_OscInitStruct->LSIDiv != (bdcr_temp & RCC_BDCR_LSIPREDIV)) + { + if (((bdcr_temp & RCC_BDCR_LSIRDY) == RCC_BDCR_LSIRDY) && \ + ((bdcr_temp & RCC_BDCR_LSION) != RCC_BDCR_LSION)) + { + /* If LSIRDY is set while LSION is not enabled, LSIPREDIV can't be updated */ + /* The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC */ + return HAL_ERROR; + } + + /* Turn off LSI before changing RCC_BDCR_LSIPREDIV */ + if ((bdcr_temp & RCC_BDCR_LSION) == RCC_BDCR_LSION) + { + __HAL_RCC_LSI_DISABLE(); + + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set LSI division factor */ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSIPREDIV, pRCC_OscInitStruct->LSIDiv); + } + + /* Enable the Internal Low Speed oscillator (LSI) */ + __HAL_RCC_LSI_ENABLE(); + + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI) */ + __HAL_RCC_LSI_DISABLE(); + + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSE(pRCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->DBPR, PWR_DBPR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + if ((pRCC_OscInitStruct->LSEState & RCC_BDCR_LSEON) != 0U) + { + if ((pRCC_OscInitStruct->LSEState & RCC_BDCR_LSEBYP) != 0U) + { + /* LSE oscillator bypass enable */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); + } + else + { + /* LSE oscillator enable */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); + } + } + else + { + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); + } + + /* Check the LSE State */ + if (pRCC_OscInitStruct->LSEState != RCC_LSE_OFF) + { + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Enable LSESYS additionally if requested */ + if ((pRCC_OscInitStruct->LSEState & RCC_BDCR_LSESYSEN) != 0U) + { + SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); + + /* Wait till LSESYS is ready */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Make sure LSESYSEN/LSESYSRDY are reset */ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); + + /* Wait till LSESYSRDY is cleared */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN) != 0U) + { + /* Reset LSESYSEN once LSE is disabled */ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); + + /* Wait till LSESYSRDY is cleared */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + /*------------------------------ HSI48 Configuration -----------------------*/ + if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI48(pRCC_OscInitStruct->HSI48State)); + + /* Check the HSI48 State */ + if (pRCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) + { + /* Enable the Internal High Speed oscillator (HSI48) */ + __HAL_RCC_HSI48_ENABLE(); + + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal High Speed oscillator (HSI48) */ + __HAL_RCC_HSI48_DISABLE(); + + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /*------------------------------ SHSI Configuration -----------------------*/ + if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_SHSI) == RCC_OSCILLATORTYPE_SHSI) + { + /* Check the parameters */ + assert_param(IS_RCC_SHSI(pRCC_OscInitStruct->SHSIState)); + + /* Check the SHSI State */ + if (pRCC_OscInitStruct->SHSIState != RCC_SHSI_OFF) + { + /* Enable the Secure Internal High Speed oscillator (SHSI) */ + __HAL_RCC_SHSI_ENABLE(); + + tickstart = HAL_GetTick(); + + /* Wait till SHSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_SHSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > SHSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Secure Internal High Speed oscillator (SHSI) */ + __HAL_RCC_SHSI_DISABLE(); + + tickstart = HAL_GetTick(); + + /* Wait till SHSI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_SHSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > SHSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ MSIK Configuration -----------------------*/ + if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSIK) == RCC_OSCILLATORTYPE_MSIK) + { + /* Check the parameters */ + assert_param(IS_RCC_MSIK(pRCC_OscInitStruct->MSIKState)); + assert_param(IS_RCC_MSIK_CLOCK_RANGE(pRCC_OscInitStruct->MSIKClockRange)); + assert_param(IS_RCC_MSICALIBRATION_VALUE(pRCC_OscInitStruct->MSICalibrationValue)); + + /* Check the MSIK State */ + if (pRCC_OscInitStruct->MSIKState != RCC_MSIK_OFF) + { + + /* Selects the Multiple Speed of kernel high speed oscillator (MSIK) clock range .*/ + __HAL_RCC_MSIK_RANGE_CONFIG(pRCC_OscInitStruct->MSIKClockRange); + /* Adjusts the Multiple Speed of kernel high speed oscillator (MSIK) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \ + (pRCC_OscInitStruct->MSIClockRange)); + + /* Enable the Internal kernel High Speed oscillator (MSIK) */ + __HAL_RCC_MSIK_ENABLE(); + + tickstart = HAL_GetTick(); + + /* Wait till MSIK is ready */ + while (READ_BIT(RCC->CR, RCC_CR_MSIKRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > MSIK_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal High Speed Kernel oscillator (MSIK) */ + __HAL_RCC_MSIK_DISABLE(); + + tickstart = HAL_GetTick(); + + /* Wait till MSIK is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_MSIKRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > MSIK_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(pRCC_OscInitStruct->PLL.PLLState)); + + if ((pRCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if ((pRCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLMBOOST_VALUE(pRCC_OscInitStruct->PLL.PLLMBOOST)); + assert_param(IS_RCC_PLLSOURCE(pRCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(pRCC_OscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(pRCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(pRCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(pRCC_OscInitStruct->PLL.PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(pRCC_OscInitStruct->PLL.PLLR)); + + /* Disable the main PLL */ + __HAL_RCC_PLL_DISABLE(); + + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + /*Disable EPOD to configure PLL1MBOOST*/ + if (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) == PWR_VOSR_BOOSTEN) + { + pwrboosten = SET; + } + CLEAR_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN); + + /* Configure the main PLL clock source, multiplication and division factors */ + __HAL_RCC_PLL_CONFIG(pRCC_OscInitStruct->PLL.PLLSource, + pRCC_OscInitStruct->PLL.PLLMBOOST, + pRCC_OscInitStruct->PLL.PLLM, + pRCC_OscInitStruct->PLL.PLLN, + pRCC_OscInitStruct->PLL.PLLP, + pRCC_OscInitStruct->PLL.PLLQ, + pRCC_OscInitStruct->PLL.PLLR); + + assert_param(IS_RCC_PLL_FRACN_VALUE(pRCC_OscInitStruct->PLL.PLLFRACN)); + + /* Disable PLL1FRACN */ + __HAL_RCC_PLL_FRACN_DISABLE(); + + /* Configure PLL PLL1FRACN */ + __HAL_RCC_PLL_FRACN_CONFIG(pRCC_OscInitStruct->PLL.PLLFRACN); + + /* Enable PLL1FRACN */ + __HAL_RCC_PLL_FRACN_ENABLE(); + + assert_param(IS_RCC_PLLRGE_VALUE(pRCC_OscInitStruct->PLL.PLLRGE)); + + /* Select PLL1 input reference frequency range: VCI */ + __HAL_RCC_PLL_VCIRANGE(pRCC_OscInitStruct->PLL.PLLRGE); + + if (pwrboosten == SET) + { + /* Enable the EPOD to reach max frequency */ + SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN); + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + + /* Enable the main PLL */ + __HAL_RCC_PLL_ENABLE(); + + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Enable PLL System Clock output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); + + } + else + { + /* Disable the main PLL */ + __HAL_RCC_PLL_DISABLE(); + + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Unselect main PLL clock source and disable main PLL outputs to save power */ + RCC->PLL1CFGR &= ~(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1PEN | RCC_PLL1CFGR_PLL1QEN | RCC_PLL1CFGR_PLL1REN); + + } + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + temp1_pllckcfg = RCC->PLL1CFGR; + temp2_pllckcfg = RCC->PLL1DIVR; + if (((pRCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1SRC) != pRCC_OscInitStruct->PLL.PLLSource) || + ((READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1M) >> \ + RCC_PLL1CFGR_PLL1M_Pos) != (pRCC_OscInitStruct->PLL.PLLM - 1U)) || + (READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1MBOOST) != pRCC_OscInitStruct->PLL.PLLMBOOST) || + (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1N) != (pRCC_OscInitStruct->PLL.PLLN - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1P) >> \ + RCC_PLL1DIVR_PLL1P_Pos) != (pRCC_OscInitStruct->PLL.PLLP - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1Q) >> \ + RCC_PLL1DIVR_PLL1Q_Pos) != (pRCC_OscInitStruct->PLL.PLLQ - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1R) >> \ + RCC_PLL1DIVR_PLL1R_Pos) != (pRCC_OscInitStruct->PLL.PLLR - 1U))) + { + return HAL_ERROR; + } + + /* FRACN1 on-the-fly value update */ + if ((READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN) >> \ + RCC_PLL1FRACR_PLL1FRACN_Pos) != (pRCC_OscInitStruct->PLL.PLLFRACN)) + { + assert_param(IS_RCC_PLL_FRACN_VALUE(pRCC_OscInitStruct->PLL.PLLFRACN)); + + /* Disable PLL1FRACN. */ + __HAL_RCC_PLL_FRACN_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait at least 2 CK_REF (PLL1 input source divided by M) period to make sure next latched value + will be taken into account. */ + while ((HAL_GetTick() - tickstart) < PLL_FRAC_WAIT_VALUE) + { + } + + /* Configure PLL PLL1FRACN */ + __HAL_RCC_PLL_FRACN_CONFIG(pRCC_OscInitStruct->PLL.PLLFRACN); + + /* Enable PLL1FRACN to latch the new value. */ + __HAL_RCC_PLL_FRACN_ENABLE(); + } + } + } + return HAL_OK; +} + +/** + * @brief Initialize the CPU, AHB and APB busses clocks according to the specified + * parameters in the pRCC_ClkInitStruct. + * @param pRCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency + * This parameter can be one of the following values: + * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle + * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle + * @arg FLASH_LATENCY_2 FLASH 2 Latency cycles + * @arg FLASH_LATENCY_3 FLASH 3 Latency cycles + * @arg FLASH_LATENCY_4 FLASH 4 Latency cycles + * @arg FLASH_LATENCY_5 FLASH 5 Latency cycles + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The MSI is used by default as system clock source after + * startup from Reset, wake-up from STANDBY mode. After restart from Reset, + * the MSI frequency is set to its default value 4 MHz. + * @note The HSI can be selected as system clock source after wakeup + * from STOP modes or in case of failure of the HSE used directly or indirectly + * as system clock (if the Clock Security System CSS is enabled). + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source is ready. + * @note You can use HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * + * @note Depending on the device voltage range, the software has to set correctly + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_ClkInitStruct, uint32_t FLatency) +{ + HAL_StatusTypeDef status; + uint32_t tickstart; + + /* Check Null pointer */ + if (pRCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(pRCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /* Increasing the BUS frequency divider */ + /*-------------------------- PCLK3 Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3) + { + if ((pRCC_ClkInitStruct->APB3CLKDivider) > (RCC->CFGR3 & RCC_CFGR3_PPRE3)) + { + assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, pRCC_ClkInitStruct->APB3CLKDivider); + } + } + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + if ((pRCC_ClkInitStruct->APB2CLKDivider) > ((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4)) + { + assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pRCC_ClkInitStruct->APB2CLKDivider) << 4)); + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + if ((pRCC_ClkInitStruct->APB1CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE1)) + { + assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pRCC_ClkInitStruct->APB1CLKDivider); + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + if ((pRCC_ClkInitStruct->AHBCLKDivider) > (RCC->CFGR2 & RCC_CFGR2_HPRE)) + { + assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider); + } + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(pRCC_ClkInitStruct->SYSCLKSource)); + FlagStatus pwrclkchanged = RESET; + + /* PLL is selected as System Clock Source */ + if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + tickstart = HAL_GetTick(); + /* Check if EPOD is enabled */ + if (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) != 0U) + { + /* Wait till BOOST is ready */ + while (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > EPOD_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + + /* Check the PLL ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U) + { + return HAL_ERROR; + } + } + else + { + /* HSE is selected as System Clock Source */ + if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + return HAL_ERROR; + } + } + /* MSI is selected as System Clock Source */ + else if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) + { + /* Check the MSI ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + return HAL_ERROR; + } + } + } + + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, pRCC_ClkInitStruct->SYSCLKSource); + + tickstart = HAL_GetTick(); + + if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + + /* Decreasing the BUS frequency divider */ + /*-------------------------- HCLK Configuration --------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + if ((pRCC_ClkInitStruct->AHBCLKDivider) < (RCC->CFGR2 & RCC_CFGR2_HPRE)) + { + assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider); + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + if ((pRCC_ClkInitStruct->APB1CLKDivider) < (RCC->CFGR2 & RCC_CFGR2_PPRE1)) + { + assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pRCC_ClkInitStruct->APB1CLKDivider); + } + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + if ((pRCC_ClkInitStruct->APB2CLKDivider) < ((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4)) + { + assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pRCC_ClkInitStruct->APB2CLKDivider) << 4)); + } + } + + /*-------------------------- PCLK3 Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3) + { + if ((pRCC_ClkInitStruct->APB3CLKDivider) < (RCC->CFGR3 & RCC_CFGR3_PPRE3)) + { + assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, (pRCC_ClkInitStruct->APB3CLKDivider)); + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]; + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + + return status; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to: + + (+) Output clock to MCO pin. + (+) Retrieve current clock frequencies. + (+) Enable the Clock Security System. + +@endverbatim + * @{ + */ + +/** + * @brief Select the clock source to output on MCO pin(PA8). + * @note PA8 should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * For STM32U5xx family this parameter can have only one value: + * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO + * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL1CLK main PLL clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 + * @param RCC_MCODiv specifies the MCO prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock + * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock + * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock + * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef gpio_initstruct; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(RCC_MCOx); + + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* MCO Clock Enable */ + MCO1_CLK_ENABLE(); + + /* Configure the MCO1 pin in alternate function mode */ + gpio_initstruct.Pin = MCO1_PIN; + gpio_initstruct.Mode = GPIO_MODE_AF_PP; + gpio_initstruct.Speed = GPIO_SPEED_FREQ_HIGH; + gpio_initstruct.Pull = GPIO_NOPULL; + gpio_initstruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio_initstruct); + + /* Mask MCOSEL[] and MCOPRE[] bits then set MCO1 clock source and prescaler */ + MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE), (RCC_MCOSource | RCC_MCODiv)); +} + +/** + * @brief Return the SYSCLK frequency. + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is MSI, function returns values based on MSI + * Value as defined by the MSI range. + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**), + * HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32u5xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32u5xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t msirange = 0U; + uint32_t pllsource; + uint32_t pllr; + uint32_t pllm; + uint32_t pllfracen; + uint32_t sysclockfreq = 0U; + uint32_t sysclk_source; + uint32_t pll_oscsource; + float_t fracn1; + float_t pllvco; + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE(); + + if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) || + ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_oscsource == RCC_PLLSOURCE_MSI))) + { + /* MSI or PLL with MSI source used as system clock source */ + + /* Get SYSCLK source */ + if (READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U) + { + /* MSISRANGE from RCC_CSR applies */ + msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos; + } + else + { + /* MSIRANGE from RCC_CR applies */ + msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos; + } + /*MSI frequency range in HZ*/ + msirange = MSIRangeTable[msirange]; + + if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) + { + /* MSI used as system clock source */ + sysclockfreq = msirange; + } + } + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + { + /* HSI used as system clock source */ + sysclockfreq = HSI_VALUE; + } + else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) + { + /* HSE used as system clock source */ + sysclockfreq = HSE_VALUE; + } + else + { + /* Nothing to do */ + } + + if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + /* PLL used as system clock source + PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); + pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; + pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \ + RCC_PLL1FRACR_PLL1FRACN_Pos)); + + switch (pllsource) + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1 / (float_t)0x2000) + (float_t)1U); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1 / (float_t)0x2000) + (float_t)1U); + break; + + case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ + default: + pllvco = ((float_t) msirange / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1 / (float_t)0x2000) + (float_t)1U); + break; + } + + pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U); + sysclockfreq = (uint32_t)(float_t)((float_t)pllvco / (float_t)pllr); + } + + return sysclockfreq; +} + +/** + * @brief Return the HCLK frequency. + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. + * @retval HCLK frequency in Hz + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]; + return SystemCoreClock; +} + +/** + * @brief Return the PCLK1 frequency. + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR2 & RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos]); +} + +/** + * @brief Return the PCLK2 frequency. + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR2 & RCC_CFGR2_PPRE2) >> RCC_CFGR2_PPRE2_Pos]); +} + +/** + * @brief Return the PCLK3 frequency. + * @note Each time PCLK3 changes, this function must be called to update the + * right PCLK3 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK3 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK3Freq(void) +{ + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR3 & RCC_CFGR3_PPRE3) >> RCC_CFGR3_PPRE3_Pos]); +} +/** + * @brief Get the pRCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param pRCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) +{ + uint32_t regval; + uint32_t reg1val; + uint32_t reg2val; + + /* Check the parameters */ + assert_param(pRCC_OscInitStruct != (void *)NULL); + + /* Set all possible values for the Oscillator type parameter ---------------*/ + pRCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \ + RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48; + + /* Get Control register */ + regval = RCC->CR; + + /* Get the HSE configuration -----------------------------------------------*/ + pRCC_OscInitStruct->HSEState = (regval & (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_HSEEXT)); + + /* Get the MSI configuration -----------------------------------------------*/ + pRCC_OscInitStruct->MSIState = regval & RCC_CR_MSISON; + + reg1val = RCC->ICSCR1; + reg2val = RCC->ICSCR2; + + pRCC_OscInitStruct->MSIClockRange = (uint32_t)((reg1val & RCC_ICSCR1_MSISRANGE)); + if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_12) + { + pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM3) >> \ + RCC_ICSCR2_MSITRIM3_Pos); + } + else if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_8) + { + pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM2) >> \ + RCC_ICSCR2_MSITRIM2_Pos); + } + else if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_4) + { + pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM1) >> \ + RCC_ICSCR2_MSITRIM1_Pos); + } + else /*if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_0)*/ + { + pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM0) >> \ + RCC_ICSCR2_MSITRIM0_Pos); + } + + + /* Get the HSI configuration -----------------------------------------------*/ + pRCC_OscInitStruct->HSIState = regval & RCC_CR_HSION; + pRCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR3 & RCC_ICSCR3_HSITRIM) >> RCC_ICSCR3_HSITRIM_Pos); + + /* Get BDCR register */ + regval = RCC->BDCR; + + /* Get the LSE configuration -----------------------------------------------*/ + pRCC_OscInitStruct->LSEState = (regval & (RCC_BDCR_LSEON | RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSEN)); + + /* Get the LSI configuration -----------------------------------------------*/ + pRCC_OscInitStruct->LSIState = regval & RCC_BDCR_LSION; + + /* Get Control register */ + regval = RCC->CR; + + /* Get the HSI48 configuration ---------------------------------------------*/ + pRCC_OscInitStruct->HSI48State = regval & RCC_CR_HSI48ON; + + /* Get the PLL configuration -----------------------------------------------*/ + if ((regval & RCC_CR_PLL1ON) == RCC_CR_PLL1ON) + { + pRCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + pRCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + + reg1val = RCC->PLL1CFGR; + reg2val = RCC->PLL1DIVR; + + pRCC_OscInitStruct->PLL.PLLSource = (uint32_t)(reg1val & RCC_PLL1CFGR_PLL1SRC); + pRCC_OscInitStruct->PLL.PLLM = (uint32_t)(((reg1val & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U); + pRCC_OscInitStruct->PLL.PLLN = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1U); + pRCC_OscInitStruct->PLL.PLLQ = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1U); + pRCC_OscInitStruct->PLL.PLLR = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U); + pRCC_OscInitStruct->PLL.PLLP = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1U); + pRCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((reg1val & RCC_PLL1CFGR_PLL1RGE)); + pRCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \ + RCC_PLL1FRACR_PLL1FRACN_Pos)); + pRCC_OscInitStruct->PLL.PLLMBOOST = (uint32_t)(((reg1val & RCC_PLL1CFGR_PLL1MBOOST) >> \ + RCC_PLL1CFGR_PLL1MBOOST_Pos)); +} + +/** + * @brief Configure the pRCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param pRCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * will be configured. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pRCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Check the parameters */ + assert_param(pRCC_ClkInitStruct != (void *)NULL); + assert_param(pFLatency != (void *)NULL); + + /* Set all possible values for the Clock type parameter --------------------*/ + pRCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | \ + RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; + + /* Get the SYSCLK configuration --------------------------------------------*/ + pRCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR1 & RCC_CFGR1_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + pRCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + pRCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + pRCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4); + + /* Get the APB3 configuration ----------------------------------------------*/ + pRCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->CFGR3 & RCC_CFGR3_PPRE3); + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +} + +/** + * @brief Get and clear reset flags + * @note Once reset flags are retrieved, this API is clearing them in order + * to isolate next reset reason. + * @retval can be a combination of @ref RCC_Reset_Flag + */ +uint32_t HAL_RCC_GetResetSource(void) +{ + uint32_t reset; + + /* Get all reset flags */ + reset = RCC->CSR & RCC_RESET_FLAG_ALL; + + /* Clear Reset flags */ + RCC->CSR |= RCC_CSR_RMVF; + + return reset; +} + +/** + * @brief Enable the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. + * @note The Clock Security System can only be cleared by reset. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Handle the RCC Clock Security System interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF interrupt flag */ + if (__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + } +} + +/** + * @brief RCC Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback should be implemented in the user file + */ +} + +/** + * @} + */ +/** @defgroup RCC_Exported_Functions_Group3 Attributes management functions + * @brief Attributes management functions. + * +@verbatim + =============================================================================== + ##### RCC attributes functions ##### + =============================================================================== +@endverbatim + * @{ + */ +/** + * @brief Configure the RCC item attribute(s). + * @note Available attributes are to secure items and set RCC as privileged. + * @note As the privileged attributes concern either all secure or all + * non-secure RCC resources accesses and not each RCC individual items + * access attribute, the application must ensure that the privilege + * access attribute configurations are coherent amongst the security + * level set on RCC individual items so not to overwrite a previous + * more restricted access rule (consider either all secure and/or all + * non-secure RCC resources accesses by privileged-only transactions or + * privileged and unprivileged transactions). + * @param Item Item(s) to set attributes on. + * This parameter can be a one or a combination of @ref RCC_items + * @param Attributes specifies the RCC secure/privilege attributes. + * This parameter can be a value of @ref RCC_attributes + * @retval None + */ +void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes) +{ + /* Check the parameters */ + assert_param(IS_RCC_ITEM_ATTRIBUTES(Item)); + assert_param(IS_RCC_ATTRIBUTES(Attributes)); + + switch (Attributes) + { +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Secure Privilege attribute */ + case RCC_SEC_PRIV: + SET_BIT(RCC->SECCFGR, Item); + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); + break; + /* Secure Non-Privilege attribute */ + case RCC_SEC_NPRIV: + SET_BIT(RCC->SECCFGR, Item); + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); + break; + /* Non-secure Privilege attribute */ + case RCC_NSEC_PRIV: + CLEAR_BIT(RCC->SECCFGR, Item); + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); + break; + /* Non-secure Non-Privilege attribute */ + case RCC_NSEC_NPRIV: + CLEAR_BIT(RCC->SECCFGR, Item); + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); + break; +#else + /* Non-secure Privilege attribute */ + case RCC_NSEC_PRIV: + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); + break; + /* Non-secure Non-Privilege attribute */ + case RCC_NSEC_NPRIV: + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); + break; +#endif /* __ARM_FEATURE_CMSE */ + default: + /* Nothing to do */ + break; + } +} +/** + * @} + */ + +/** + * @brief Get the attribute of a RCC item. + * @note Secure and non-secure attributes are only available from secure state + * when the system implements the security (TZEN=1) + * @param Item Single item to get secure/non-secure and privilege/non-privilege attribute from. + * This parameter can be a one value of @ref RCC_items except RCC_ALL. + * @param pAttributes pointer to return the attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes) +{ + uint32_t attributes; + + /* Check null pointer */ + if (pAttributes == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_ITEM_ATTRIBUTES(Item)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + + /* Check item security */ + if ((RCC->SECCFGR & Item) == Item) + { + /* Get Secure privileges attribute */ + attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_SPRIV) == 0U) ? RCC_SEC_NPRIV : RCC_SEC_PRIV; + } + else + { + /* Get Non-Secure privileges attribute */ + attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_NSPRIV) == 0U) ? RCC_NSEC_NPRIV : RCC_NSEC_PRIV; + } +#else + /* Get Non-Secure privileges attribute */ + attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_NSPRIV) == 0U) ? RCC_NSEC_NPRIV : RCC_NSEC_PRIV; + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); + +#endif /* __ARM_FEATURE_CMSE */ + + /* return value */ + *pAttributes = attributes; + + return HAL_OK; +} +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup RCC_Private_Functions + * @{ + */ +/** + * @brief Update number of Flash wait states in line with MSI range and current + voltage range. + * @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_15 + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) +{ + uint32_t vos; + uint32_t latency; /* default value 0WS */ + + if (__HAL_RCC_PWR_IS_CLK_ENABLED()) + { + vos = HAL_PWREx_GetVoltageRange(); + } + else + { + __HAL_RCC_PWR_CLK_ENABLE(); + vos = HAL_PWREx_GetVoltageRange(); + __HAL_RCC_PWR_CLK_DISABLE(); + } + + if ((vos == PWR_REGULATOR_VOLTAGE_SCALE1) || (vos == PWR_REGULATOR_VOLTAGE_SCALE2)) + { + + if (msirange < RCC_MSIRANGE_1) + { + /* MSI = 48Mhz */ + latency = FLASH_LATENCY_1; /* 1WS */ + } + else + { + /* MSI < 48Mhz */ + latency = FLASH_LATENCY_0; /* 0WS */ + } + } + else + { + if (msirange < RCC_MSIRANGE_1) + { + /* MSI = 48Mhz */ + if (vos == PWR_REGULATOR_VOLTAGE_SCALE3) + { + latency = FLASH_LATENCY_3; /* 3WS */ + } + else + { + return HAL_ERROR; + } + } + else + { + if (msirange > RCC_MSIRANGE_2) + { + if (vos == PWR_REGULATOR_VOLTAGE_SCALE4) + { + if (msirange > RCC_MSIRANGE_3) + { + latency = FLASH_LATENCY_0; /* 1WS */ + } + else + { + latency = FLASH_LATENCY_1; /* 0WS */ + } + } + else + { + latency = FLASH_LATENCY_0; /* 0WS */ + } + } + else + { + if (msirange == RCC_MSIRANGE_1) + { + if (vos == PWR_REGULATOR_VOLTAGE_SCALE3) + { + latency = FLASH_LATENCY_1; /* 1WS */ + } + else + { + latency = FLASH_LATENCY_2; /* 2WS */ + } + } + else + { + latency = FLASH_LATENCY_1; /* 1WS */ + } + } + } + } + + __HAL_FLASH_SET_LATENCY(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if ((FLASH->ACR & FLASH_ACR_LATENCY) != latency) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @} + */ +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc_ex.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc_ex.c new file mode 100644 index 000000000..1b4e04338 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc_ex.c @@ -0,0 +1,4321 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extended peripheral: + * + Extended Peripheral Control functions + * + Extended Clock management functions + * + Extended Clock Recovery System Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx + * @brief RCC Extended HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Constants RCCEx Private Constants + * @{ + */ +#define PLL1_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ +#define PLL2_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ +#define PLL3_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ + +/* Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. */ +#if defined (STM32U585xx) || defined (STM32U575xx) +#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM23 /*!< External interrupt line 23 connected to the LSE CSS interrupt Line */ +#else +#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM24 /*!< External interrupt line 24 connected to the LSE CSS interrupt Line */ +#endif /* STM32U585xx || STM32U575xx */ + +/* Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. */ +#define RCC_EXTI_LINE_MSIPLLUNLCK EXTI_IMR1_IM23 /*!< External interrupt line 23 connected to the MSI PLL UNLOCK interrupt Line */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCCEx_Private_Macros + * @{ + */ + +#define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) ((0x00010000U <= (VALUE)) && ((VALUE) <= 0x00070000U)) + +#define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) ((0x00010000U <= (VALUE)) && ((VALUE) <= 0x00070000U)) + +#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) + +#define IS_RCC_MSIPLLMODE_SELECT(__SOURCE__) (((__SOURCE__) == RCC_MSISPLL_MODE_SEL) || \ + ((__SOURCE__) == RCC_MSIKPLL_MODE_SEL)) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != 0x00u) && \ + (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == 0x00u)) + +#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)) + +#if defined(USART2) +#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)) +#endif /* USART2 */ + +#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)) + +#define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE)) + +#define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE)) + +#if defined(USART6) +#define IS_RCC_USART6CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART6CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_LSE)) +#endif /* USART6 */ + +#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_MSIK)) + +#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)|| \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_MSIK)) + +#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)|| \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_MSIK)) + +#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK ) || \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI ) || \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_MSIK)) + +#define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)|| \ + ((__SOURCE__) == RCC_I2C4CLKSOURCE_MSIK)) + +#if defined(I2C5) +#define IS_RCC_I2C5CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C5CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C5CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C5CLKSOURCE_HSI)|| \ + ((__SOURCE__) == RCC_I2C5CLKSOURCE_MSIK)) +#endif /* I2C5 */ + +#if defined(I2C6) +#define IS_RCC_I2C6CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C6CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C6CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C6CLKSOURCE_HSI)|| \ + ((__SOURCE__) == RCC_I2C6CLKSOURCE_MSIK)) +#endif /* I2C6 */ + +#define IS_RCC_SAI1CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL1) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) + +#if defined(SAI2) +#define IS_RCC_SAI2CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL1) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI)) +#endif /* SAI2 */ + +#define IS_RCC_LPTIM1CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_MSIK) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) + +#define IS_RCC_LPTIM2CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) + +#define IS_RCC_LPTIM34CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM34CLKSOURCE_MSIK) || \ + ((__SOURCE__) == RCC_LPTIM34CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM34CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM34CLKSOURCE_LSE)) + +#define IS_RCC_FDCAN1CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_FDCAN1CLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_FDCAN1CLKSOURCE_PLL1) || \ + ((__SOURCE__) == RCC_FDCAN1CLKSOURCE_PLL2)) + +#define IS_RCC_SDMMCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SDMMCCLKSOURCE_CLK48) || \ + ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL1)) + +#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48_DIV2) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI)) + +#if defined(SAES) +#define IS_RCC_SAESCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SAESCLKSOURCE_SHSI) || \ + ((__SOURCE__) == RCC_SAESCLKSOURCE_SHSI_DIV2)) +#endif /* SAES */ + +#define IS_RCC_ADCDACCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ADCDACCLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_ADCDACCLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_ADCDACCLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_ADCDACCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_ADCDACCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_ADCDACCLKSOURCE_MSIK)) + +#define IS_RCC_MDF1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_MDF1CLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_MDF1CLKSOURCE_PLL1) || \ + ((__SOURCE__) == RCC_MDF1CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_MDF1CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_MDF1CLKSOURCE_MSIK)) + +#define IS_RCC_ADF1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ADF1CLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_ADF1CLKSOURCE_PLL1) || \ + ((__SOURCE__) == RCC_ADF1CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_ADF1CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_ADF1CLKSOURCE_MSIK)) + +#define IS_RCC_OSPICLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_MSIK) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL1) ||\ + ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2)) + +#if defined(HSPI1) +#define IS_RCC_HSPICLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_HSPICLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL1) || \ + ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL3)) +#endif /* HSPI1 */ + +#define IS_RCC_ICLKCLKSOURCE(__SOURCE__)\ + (((__SOURCE__) == RCC_ICLK_CLKSOURCE_HSI48)|| \ + ((__SOURCE__) == RCC_ICLK_CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_ICLK_CLKSOURCE_PLL1) || \ + ((__SOURCE__) == RCC_ICLK_CLKSOURCE_MSIK)) + +#define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI1CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_HSI)|| \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_MSIK)) + +#define IS_RCC_SPI2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_HSI)|| \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_MSIK)) + +#define IS_RCC_SPI3CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI3CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_HSI)|| \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_MSIK)) + +#define IS_RCC_DAC1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_DAC1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_DAC1CLKSOURCE_LSI)) + +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) + +#if defined(LTDC) + +#define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLL2)) + +#endif /* LTDC */ + +#if defined(DSI) + +#define IS_RCC_DSICLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_DSICLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY)) + +#endif /* DSI */ + +#if defined(USB_OTG_HS) + +#define IS_RCC_USBPHYCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USBPHYCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_USBPHYCLKSOURCE_HSE_DIV2) || \ + ((__SOURCE__) == RCC_USBPHYCLKSOURCE_PLL1) || \ + ((__SOURCE__) == RCC_USBPHYCLKSOURCE_PLL1_DIV2)) + +#endif /* USB_OTG_HS */ + +#if defined(CRS) + +#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) + +#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) + +#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ + ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) + +#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) + +#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) + +#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU)) + +#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ + ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) + +#endif /* CRS */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCCEx_Private_Functions RCCEx Private Functions + * @{ + */ +static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource); +static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *Pll2); +static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *Pll3); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) are set to their reset values. + +@endverbatim + * @{ + */ +/** + * @brief Initialize the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains a field PeriphClockSelection which can be a combination of the following values: + * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock + * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C5 I2C5 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C6 I2C6 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock + * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock + * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock + * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1 ADC2 ADC4 DAC1 peripheral clock + * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock + * @arg @ref RCC_PERIPHCLK_ADF1 ADF1 peripheral clock + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock + * @arg @ref RCC_PERIPHCLK_ICLK ICLK peripheral clock + * @arg @ref RCC_PERIPHCLK_SDMMC SDMMC1 peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock + * @arg @ref RCC_PERIPHCLK_OSPI OSPI peripheral clock + * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock + * @arg @ref RCC_PERIPHCLK_DAC1 DAC1 peripheral clock + * @arg @ref RCC_PERIPHCLK_HSPI HSPI peripheral clock + * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock + * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock + * @arg @ref RCC_PERIPHCLK_USBPHY USBPHY peripheral clock + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source: in this case the access to Backup domain is enabled. + * + * @retval HAL status + * + * (*) value not defined in all devices. + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPeriphClkInit) +{ + uint32_t tmpregister; + uint32_t tickstart; + HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + HAL_StatusTypeDef status = HAL_OK; /* Final status */ + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(pPeriphClkInit->PeriphClockSelection)); + + /*-------------------------- USART1 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(pPeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(pPeriphClkInit->Usart1ClockSelection); + } + +#if defined(USART2) + /*-------------------------- USART2 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(pPeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(pPeriphClkInit->Usart2ClockSelection); + } +#endif /* USART2 */ + + /*-------------------------- USART3 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(pPeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(pPeriphClkInit->Usart3ClockSelection); + } + + /*-------------------------- UART4 clock source configuration --------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) + { + /* Check the parameters */ + assert_param(IS_RCC_UART4CLKSOURCE(pPeriphClkInit->Uart4ClockSelection)); + + /* Configure the UART4 clock source */ + __HAL_RCC_UART4_CONFIG(pPeriphClkInit->Uart4ClockSelection); + } + + /*-------------------------- UART5 clock source configuration --------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) + { + /* Check the parameters */ + assert_param(IS_RCC_UART5CLKSOURCE(pPeriphClkInit->Uart5ClockSelection)); + + /* Configure the UART5 clock source */ + __HAL_RCC_UART5_CONFIG(pPeriphClkInit->Uart5ClockSelection); + } +#if defined(USART6) + /*-------------------------- USART6 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) + { + /* Check the parameters */ + assert_param(IS_RCC_USART6CLKSOURCE(pPeriphClkInit->Usart6ClockSelection)); + + /* Configure the USART6 clock source */ + __HAL_RCC_USART6_CONFIG(pPeriphClkInit->Usart6ClockSelection); + } +#endif /* USART6 */ + + /*-------------------------- LPUART1 clock source configuration ------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPUART1CLKSOURCE(pPeriphClkInit->Lpuart1ClockSelection)); + + /* Configure the LPUART1 clock source */ + __HAL_RCC_LPUART1_CONFIG(pPeriphClkInit->Lpuart1ClockSelection); + } + + /*-------------------------- I2C1 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(pPeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(pPeriphClkInit->I2c1ClockSelection); + } + + /*-------------------------- I2C2 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(pPeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(pPeriphClkInit->I2c2ClockSelection); + } + + /*-------------------------- I2C3 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(pPeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(pPeriphClkInit->I2c3ClockSelection); + } + + /*-------------------------- I2C4 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C4CLKSOURCE(pPeriphClkInit->I2c4ClockSelection)); + + /* Configure the I2C4 clock source */ + __HAL_RCC_I2C4_CONFIG(pPeriphClkInit->I2c4ClockSelection); + } + +#if defined(I2C5) + /*-------------------------- I2C5 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C5) == RCC_PERIPHCLK_I2C5) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C5CLKSOURCE(pPeriphClkInit->I2c5ClockSelection)); + + /* Configure the I2C5 clock source */ + __HAL_RCC_I2C5_CONFIG(pPeriphClkInit->I2c5ClockSelection); + } +#endif /* I2C5 */ + +#if defined(I2C6) + /*-------------------------- I2C6 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C6) == RCC_PERIPHCLK_I2C6) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C6CLKSOURCE(pPeriphClkInit->I2c6ClockSelection)); + + /* Configure the I2C6 clock source */ + __HAL_RCC_I2C6_CONFIG(pPeriphClkInit->I2c6ClockSelection); + } +#endif /* I2C6 */ + + /*-------------------------- LPTIM1 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) + { + assert_param(IS_RCC_LPTIM1CLK(pPeriphClkInit->Lptim1ClockSelection)); + __HAL_RCC_LPTIM1_CONFIG(pPeriphClkInit->Lptim1ClockSelection); + } + + /*-------------------------- LPTIM2 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) + { + assert_param(IS_RCC_LPTIM2CLK(pPeriphClkInit->Lptim2ClockSelection)); + __HAL_RCC_LPTIM2_CONFIG(pPeriphClkInit->Lptim2ClockSelection); + } + + /*-------------------------- LPTIM34 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM34) == (RCC_PERIPHCLK_LPTIM34)) + { + assert_param(IS_RCC_LPTIM34CLK(pPeriphClkInit->Lptim34ClockSelection)); + __HAL_RCC_LPTIM34_CONFIG(pPeriphClkInit->Lptim34ClockSelection); + } + + /*-------------------------- SAI1 clock source configuration ---------------------*/ + if ((((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLK(pPeriphClkInit->Sai1ClockSelection)); + + switch (pPeriphClkInit->Sai1ClockSelection) + { + case RCC_SAI1CLKSOURCE_PLL1: /* PLL is used as clock source for SAI1*/ + /* Enable SAI Clock output generated from System PLL */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); + /* SAI1 clock source config set later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ + /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* SAI1 clock source config set later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ + /* PLL3 P input clock, parameters M, N & P configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* SAI1 clock source config set later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/ + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_HSI: /* HSI is used as source of SAI1 clock*/ + /* SAI1 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI1 clock*/ + __HAL_RCC_SAI1_CONFIG(pPeriphClkInit->Sai1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(SAI2) + /*-------------------------- SAI2 clock source configuration ---------------------*/ + if ((((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI2CLK(pPeriphClkInit->Sai2ClockSelection)); + + switch (pPeriphClkInit->Sai2ClockSelection) + { + case RCC_SAI2CLKSOURCE_PLL1: /* PLL is used as clock source for SAI2*/ + /* Enable SAI Clock output generated from System PLL */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); + /* SAI2 clock source config set later after clock selection check */ + break; + + case RCC_SAI2CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ + /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* SAI2 clock source config set later after clock selection check */ + break; + + case RCC_SAI2CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ + /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* SAI2 clock source config set later after clock selection check */ + break; + + case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/ + /* SAI2 clock source configuration done later after clock selection check */ + break; + case RCC_SAI2CLKSOURCE_HSI: /* HSI is used as source of SAI2 clock*/ + /* SAI2 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI2 clock*/ + __HAL_RCC_SAI2_CONFIG(pPeriphClkInit->Sai2ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* SAI2 */ + + /*-------------------------- ADCDAC clock source configuration ----------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADCDAC) == RCC_PERIPHCLK_ADCDAC) + { + /* Check the parameters */ + assert_param(IS_RCC_ADCDACCLKSOURCE(pPeriphClkInit->AdcDacClockSelection)); + + switch (pPeriphClkInit->AdcDacClockSelection) + { + case RCC_ADCDACCLKSOURCE_PLL2: + /* PLL2 input clock, parameters M, N,P, & R configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + break; + + case RCC_ADCDACCLKSOURCE_SYSCLK: + case RCC_ADCDACCLKSOURCE_HCLK: + case RCC_ADCDACCLKSOURCE_HSE: + case RCC_ADCDACCLKSOURCE_HSI: + case RCC_ADCDACCLKSOURCE_MSIK: + break; + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Configure the ADC1 interface clock source */ + __HAL_RCC_ADCDAC_CONFIG(pPeriphClkInit->AdcDacClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- MDF1 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_MDF1) == RCC_PERIPHCLK_MDF1) + { + /* Check the parameters */ + assert_param(IS_RCC_MDF1CLKSOURCE(pPeriphClkInit->Mdf1ClockSelection)); + + switch (pPeriphClkInit->Mdf1ClockSelection) + { + case RCC_MDF1CLKSOURCE_PLL1: + /* Enable PLL1 Clock output generated from System PLL */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); + break; + case RCC_MDF1CLKSOURCE_PLL3: + /* PLL3 Q input clock, parameters M, N & Q configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + break; + case RCC_MDF1CLKSOURCE_HCLK: + break; + case RCC_MDF1CLKSOURCE_PIN: + break; + case RCC_MDF1CLKSOURCE_MSIK: + break; + default: + ret = HAL_ERROR; + break; + } + if (ret == HAL_OK) + { + /* Configure the MDF1 interface clock source */ + __HAL_RCC_MDF1_CONFIG(pPeriphClkInit->Mdf1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- ADF1 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADF1) == RCC_PERIPHCLK_ADF1) + { + /* Check the parameters */ + assert_param(IS_RCC_ADF1CLKSOURCE(pPeriphClkInit->Adf1ClockSelection)); + switch (pPeriphClkInit->Adf1ClockSelection) + { + case RCC_ADF1CLKSOURCE_PLL1: + /* Enable PLL1 Clock output generated from System PLL */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); + break; + case RCC_ADF1CLKSOURCE_PLL3: + /* PLL3 Q input clock, parameters M, N & Q configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + break; + case RCC_ADF1CLKSOURCE_HCLK: + break; + case RCC_ADF1CLKSOURCE_PIN: + break; + case RCC_ADF1CLKSOURCE_MSIK: + break; + default: + ret = HAL_ERROR; + break; + } + if (ret == HAL_OK) + { + /* Configure the ADF1 interface clock source */ + __HAL_RCC_ADF1_CONFIG(pPeriphClkInit->Adf1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- RTC clock source configuration ----------------------*/ + if ((pPeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + { + FlagStatus pwrclkchanged = RESET; + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(pPeriphClkInit->RTCClockSelection)); + /* Enable Power Clock */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + /* Enable write access to Backup domain */ + SET_BIT(PWR->DBPR, PWR_DBPR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + + if (ret == HAL_OK) + { + /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ + tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); + + if ((tmpregister != RCC_RTCCLKSOURCE_NO_CLK) && (tmpregister != pPeriphClkInit->RTCClockSelection)) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpregister; + } + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + } + + if (ret == HAL_OK) + { + /* Apply new RTC clock source selection */ + __HAL_RCC_RTC_CONFIG(pPeriphClkInit->RTCClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + else + { + /* set overall return value */ + status = ret; + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + + /*-------------------------------------- ICLK Configuration -----------------------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ICLK) == RCC_PERIPHCLK_ICLK) + { + /* Check the parameters */ + assert_param(IS_RCC_ICLKCLKSOURCE(pPeriphClkInit->IclkClockSelection)); + + switch (pPeriphClkInit->IclkClockSelection) + { + case RCC_ICLK_CLKSOURCE_PLL2: + /* PLL2 input clock, parameters M, N,P,Q & R configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + break; + case RCC_ICLK_CLKSOURCE_PLL1: + /* Enable ICLK Clock output generated from System PLL */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + break; + case RCC_ICLK_CLKSOURCE_HSI48: + break; + case RCC_ICLK_CLKSOURCE_MSIK: + break; + default: + ret = HAL_ERROR; + break; + } + if (ret == HAL_OK) + { + /* Configure the CLK48 source */ + __HAL_RCC_CLK48_CONFIG(pPeriphClkInit->IclkClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*------------------------------ RNG Configuration -------------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) + { + + /* Check the parameters */ + assert_param(IS_RCC_RNGCLKSOURCE(pPeriphClkInit->RngClockSelection)); + + switch (pPeriphClkInit->RngClockSelection) + { + case RCC_RNGCLKSOURCE_HSI48_DIV2: /* HSI48/2 is used as clock source for RNG*/ + /* RNG clock source configuration done later after clock selection check */ + break; + case RCC_RNGCLKSOURCE_HSI: /* HSI is used as clock source for RNG*/ + /* RNG clock source configuration done later after clock selection check */ + break; + case RCC_RNGCLKSOURCE_HSI48: + /* HSI48 oscillator is used as source of RNG clock */ + /* RNG clock source configuration done later after clock selection check */ + break; + default: + ret = HAL_ERROR; + break; + } + if (ret == HAL_OK) + { + /* Set the source of RNG clock*/ + __HAL_RCC_RNG_CONFIG(pPeriphClkInit->RngClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(SAES) + /*-------------------------- SAES clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAES) == RCC_PERIPHCLK_SAES) + { + /* Check the parameters */ + assert_param(IS_RCC_SAESCLKSOURCE(pPeriphClkInit->SaesClockSelection)); + + /* Configure the SAES clock source */ + __HAL_RCC_SAES_CONFIG(pPeriphClkInit->SaesClockSelection); + } +#endif /* SAES */ + + /*-------------------------- SDMMC1/2 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == (RCC_PERIPHCLK_SDMMC)) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMCCLKSOURCE(pPeriphClkInit->SdmmcClockSelection)); + + if (pPeriphClkInit->SdmmcClockSelection == RCC_SDMMCCLKSOURCE_PLL1) + { + /* Enable PLL1 P CLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); + } + + /* Configure the SDMMC1/2 clock source */ + __HAL_RCC_SDMMC_CONFIG(pPeriphClkInit->SdmmcClockSelection); + } + + /*-------------------------- SPI1 clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1) + { + /* Check the parameters */ + assert_param(IS_RCC_SPI1CLKSOURCE(pPeriphClkInit->Spi1ClockSelection)); + + /* Configure the SPI1 clock source */ + __HAL_RCC_SPI1_CONFIG(pPeriphClkInit->Spi1ClockSelection); + } + + /*-------------------------- SPI2 clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI2) == RCC_PERIPHCLK_SPI2) + { + /* Check the parameters */ + assert_param(IS_RCC_SPI2CLKSOURCE(pPeriphClkInit->Spi2ClockSelection)); + + /* Configure the SPI2 clock source */ + __HAL_RCC_SPI2_CONFIG(pPeriphClkInit->Spi2ClockSelection); + } + + /*-------------------------- SPI3 clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI3) == RCC_PERIPHCLK_SPI3) + { + /* Check the parameters */ + assert_param(IS_RCC_SPI3CLKSOURCE(pPeriphClkInit->Spi3ClockSelection)); + + /* Configure the SPI3 clock source */ + __HAL_RCC_SPI3_CONFIG(pPeriphClkInit->Spi3ClockSelection); + } + + /*-------------------------- OctoSPIx clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) + { + /* Check the parameters */ + assert_param(IS_RCC_OSPICLKSOURCE(pPeriphClkInit->OspiClockSelection)); + + if (pPeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL1) + { + /* Enable PLL1 Q CLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + } + if (pPeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL2) + { + /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + } + if (ret == HAL_OK) + { + /* Configure the OctoSPI clock source */ + __HAL_RCC_OSPI_CONFIG(pPeriphClkInit->OspiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(HSPI1) + /*-------------------------- HSPIx kernel clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HSPI) == RCC_PERIPHCLK_HSPI) + { + + /* Check the parameters */ + assert_param(IS_RCC_HSPICLKSOURCE(pPeriphClkInit->HspiClockSelection)); + + switch (pPeriphClkInit->HspiClockSelection) + { + case RCC_HSPICLKSOURCE_SYSCLK: /* SYSCLK is used as clock source for HSPI kernel clock*/ + /* HSPI kernel clock source config set later after clock selection check */ + break; + + case RCC_HSPICLKSOURCE_PLL1: /* PLL1 is used as clock source for HSPI kernel clock*/ + /* Enable 48M2 Clock output generated from System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + /* HSPI kernel clock source config set later after clock selection check */ + break; + + case RCC_HSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for HSPI kernel clock*/ + /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* HSPI kernel clock source config set later after clock selection check */ + break; + + case RCC_HSPICLKSOURCE_PLL3: /* PLL3 is used as clock source for HSPI kernel clock*/ + /* PLL3 input clock, parameters M, N & R configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* HSPI kernel clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of HSPI kernel clock*/ + __HAL_RCC_HSPI_CONFIG(pPeriphClkInit->HspiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* defined(HSPI1) */ + + /*-------------------------- FDCAN1 kernel clock source configuration -------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN1) == (RCC_PERIPHCLK_FDCAN1)) + { + assert_param(IS_RCC_FDCAN1CLK(pPeriphClkInit->Fdcan1ClockSelection)); + + switch (pPeriphClkInit->Fdcan1ClockSelection) + { + case RCC_FDCAN1CLKSOURCE_HSE: /* HSE is used as source of FDCAN1 kernel clock*/ + /* FDCAN1 kernel clock source config set later after clock selection check */ + break; + case RCC_FDCAN1CLKSOURCE_PLL1: /* PLL1 is used as clock source for FDCAN1 kernel clock*/ + /* Enable 48M2 Clock output generated from System PLL */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + /* FDCAN1 kernel clock source config set later after clock selection check */ + break; + case RCC_FDCAN1CLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN1 kernel clock*/ + /* PLL2 input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* FDCAN1 kernel clock source config set later after clock selection check */ + break; + default: + ret = HAL_ERROR; + break; + } + if (ret == HAL_OK) + { + /* Set the source of FDCAN1 kernel clock*/ + __HAL_RCC_FDCAN1_CONFIG(pPeriphClkInit->Fdcan1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- DAC1 clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DAC1) == RCC_PERIPHCLK_DAC1) + { + + /* Check the parameters */ + assert_param(IS_RCC_DAC1CLKSOURCE(pPeriphClkInit->Dac1ClockSelection)); + + /* Configure the DAC1 clock source */ + __HAL_RCC_DAC1_CONFIG(pPeriphClkInit->Dac1ClockSelection); + } + +#if defined(LTDC) + + /*-------------------------- LTDC clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + { + + /* Check the parameters */ + assert_param(IS_RCC_LTDCCLKSOURCE(pPeriphClkInit->LtdcClockSelection)); + + switch (pPeriphClkInit->LtdcClockSelection) + { + case RCC_LTDCCLKSOURCE_PLL2: /* PLL2 is used as clock source for LTDC clock*/ + /* PLL2 input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* LTDC clock source config set later after clock selection check */ + break; + + case RCC_LTDCCLKSOURCE_PLL3: /* PLL3 is used as clock source for LTDC clock*/ + /* PLL3 input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* LTDC clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LTDC clock*/ + __HAL_RCC_LTDC_CONFIG(pPeriphClkInit->LtdcClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#endif /* defined(LTDC) */ + +#if defined(DSI) + + /*-------------------------- DSI clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) + { + + /* Check the parameters */ + assert_param(IS_RCC_DSICLKSOURCE(pPeriphClkInit->DsiClockSelection)); + + if (pPeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLL3) + { + /* PLL3 is used as clock source for DSI clock*/ + /* PLL3 input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + } + + if (ret == HAL_OK) + { + /* Set the source of DSI clock*/ + __HAL_RCC_DSI_CONFIG(pPeriphClkInit->DsiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#endif /* defined(DSI) */ + +#if defined(USB_OTG_HS) + + /*-------------------------- USB PHY clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USBPHY) == RCC_PERIPHCLK_USBPHY) + { + + /* Check the parameters */ + assert_param(IS_RCC_USBPHYCLKSOURCE(pPeriphClkInit->UsbPhyClockSelection)); + + switch (pPeriphClkInit->UsbPhyClockSelection) + { + case RCC_USBPHYCLKSOURCE_HSE: /* HSE is used as clock source for USB PHY clock*/ + case RCC_USBPHYCLKSOURCE_HSE_DIV2: /* HSE div 2 is used as clock source for USB PHY clock*/ + /* USB-PHY clock source config set later after clock selection check */ + break; + + case RCC_USBPHYCLKSOURCE_PLL1: /* PLL1 P divider clock selected as USB PHY clock */ + case RCC_USBPHYCLKSOURCE_PLL1_DIV2: /* PLL1 P divider clock div 2 selected as USB PHY clock */ + /* Enable P Clock output generated from System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); + /* USB-PHY clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USBPHY clock*/ + __HAL_RCC_USBPHY_CONFIG(pPeriphClkInit->UsbPhyClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#endif /* defined(USB_OTG_HS) */ + + return status; +} + + +/** + * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. + * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals + * clocks(USART1, USART2, USART3, UART4, UART5, LPUART, I2C1, I2C2, I2C3, LPTIM1, LPTIM2, SAI1, SAI2, + * ADC1, ADC2, MDF1, MDF2, RTC, CLK48, SDMMC1, I2C4, SPI12, SPI3, OSPI, FDCAN1, DAC1). + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) +{ + /* Set all possible values for the extended clock type parameter------------*/ +#if (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx)) + pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \ + RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ + RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \ + RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_LTDC | \ + RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_USBPHY; +#elif (defined(STM32U595xx) || defined(STM32U5A5xx)) + pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \ + RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ + RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \ + RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_USBPHY; +#elif (defined(STM32U585xx) || defined(STM32U575xx)) + pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ + RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | \ + RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | \ + RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | \ + RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1; + +#else + pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ + RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | \ + RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | \ + RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_ICLK | \ + RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_I2C4 | \ + RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \ + RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1; +#endif /* (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx)) */ + +#if defined(SAES) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAES; +#endif /* SAES */ + + /* Get the PLL2 Clock configuration -----------------------------------------------*/ + pPeriphClkInit->PLL2.PLL2Source = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC) >> RCC_PLL2CFGR_PLL2SRC_Pos); + pPeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1U; + pPeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) >> RCC_PLL2DIVR_PLL2N_Pos) + 1U; + pPeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + 1U; + pPeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1U; + pPeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + 1U; + pPeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2RGE) >> RCC_PLL2CFGR_PLL2RGE_Pos); + pPeriphClkInit->PLL2.PLL2FRACN = (uint32_t)((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \ + RCC_PLL2FRACR_PLL2FRACN_Pos); + + /* Get the PLL3 Clock configuration -----------------------------------------------*/ + pPeriphClkInit->PLL3.PLL3Source = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC) >> RCC_PLL3CFGR_PLL3SRC_Pos); + pPeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos) + 1U; + pPeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) >> RCC_PLL3DIVR_PLL3N_Pos) + 1U; + pPeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + 1U; + pPeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + 1U; + pPeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + 1U; + pPeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3RGE) >> RCC_PLL3CFGR_PLL3RGE_Pos); + pPeriphClkInit->PLL3.PLL3FRACN = (uint32_t)((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \ + RCC_PLL3FRACR_PLL3FRACN_Pos); + + /* Get the USART1 clock source ---------------------------------------------*/ + pPeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + +#if defined(USART2) + /* Get the USART2 clock source ---------------------------------------------*/ + pPeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); +#endif /* USART2 */ + + /* Get the USART3 clock source ---------------------------------------------*/ + pPeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); + + /* Get the UART4 clock source ----------------------------------------------*/ + pPeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); + + /* Get the UART5 clock source ----------------------------------------------*/ + pPeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); + + /* Get the LPUART1 clock source --------------------------------------------*/ + pPeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); + +#if defined(USART6) + /* Get the UART6 clock source ---------------------------------------------*/ + pPeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); +#endif /* defined(USART6) */ + + /* Get the I2C1 clock source -----------------------------------------------*/ + pPeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + + /* Get the I2C2 clock source -----------------------------------------------*/ + pPeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); + + /* Get the I2C3 clock source -----------------------------------------------*/ + pPeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); + + /* Get the I2C4 clock source -----------------------------------------------*/ + pPeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); + +#if defined(I2C5) + /* Get the clock source ---------------------------------------------*/ + pPeriphClkInit->I2c5ClockSelection = __HAL_RCC_GET_I2C5_SOURCE(); +#endif /* defined(I2C5) */ + +#if defined(I2C6) + /* Get the clock source ---------------------------------------------*/ + pPeriphClkInit->I2c6ClockSelection = __HAL_RCC_GET_I2C6_SOURCE(); +#endif /* defined(I2C6) */ + + /* Get the LPTIM1 clock source ---------------------------------------------*/ + pPeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + + /* Get the LPTIM2 clock source ---------------------------------------------*/ + pPeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); + + /* Get the LPTIM34 clock source --------------------------------------------*/ + pPeriphClkInit->Lptim34ClockSelection = __HAL_RCC_GET_LPTIM34_SOURCE(); + + /* Get the FDCAN1 clock source ---------------------------------------------*/ + pPeriphClkInit->Fdcan1ClockSelection = __HAL_RCC_GET_FDCAN1_SOURCE(); + + /* Get the MDF1 clock source -----------------------------------------------*/ + pPeriphClkInit->Mdf1ClockSelection = __HAL_RCC_GET_MDF1_SOURCE(); + + /* Get the ADF1 clock source -----------------------------------------------*/ + pPeriphClkInit->Adf1ClockSelection = __HAL_RCC_GET_ADF1_SOURCE(); + +#if defined(SAES) + /* Get the SAES clock source -----------------------------------------------*/ + pPeriphClkInit->SaesClockSelection = __HAL_RCC_GET_SAES_SOURCE(); +#endif /* SAES */ + + /* Get the SAI1 clock source -----------------------------------------------*/ + pPeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); + +#if defined(SAI2) + /* Get the SAI2 clock source -----------------------------------------------*/ + pPeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); +#endif /* SAI2 */ + + /* Get the CLK48 clock source ----------------------------------------------*/ + pPeriphClkInit->IclkClockSelection = __HAL_RCC_GET_ICLK_SOURCE(); + + /* Get the SDMMC clock source ----------------------------------------------*/ + pPeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE(); + + /* Get the ADCDAC clock source ---------------------------------------------*/ + pPeriphClkInit->AdcDacClockSelection = __HAL_RCC_GET_ADCDAC_SOURCE(); + + /* Get the DAC1 clock source -----------------------------------------------*/ + pPeriphClkInit->Dac1ClockSelection = __HAL_RCC_GET_DAC1_SOURCE(); + + /* Get the OSPI clock source -----------------------------------------------*/ + pPeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE(); + + /* Get the SPI1 clock source -----------------------------------------------*/ + pPeriphClkInit->Spi1ClockSelection = __HAL_RCC_GET_SPI1_SOURCE(); + + /* Get the SPI2 clock source -----------------------------------------------*/ + pPeriphClkInit->Spi2ClockSelection = __HAL_RCC_GET_SPI2_SOURCE(); + + /* Get the SPI3 clock source -----------------------------------------------*/ + pPeriphClkInit->Spi3ClockSelection = __HAL_RCC_GET_SPI3_SOURCE(); + + /* Get the RTC clock source ------------------------------------------------*/ + pPeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); + + /* Get the RNG clock source ------------------------------------------------*/ + pPeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); + +#if defined(HSPI1) + /* Get the HSPI kernel clock source ------------------------------------------------*/ + pPeriphClkInit->HspiClockSelection = __HAL_RCC_GET_HSPI_SOURCE(); +#endif /* defined(HSPI1) */ + +#if defined(LTDC) + /* Get the LTDC clock source ------------------------------------------------*/ + pPeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE(); +#endif /* defined(LTDC) */ + +#if defined(DSI) + /* Get the DSI clock source ------------------------------------------------*/ + pPeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE(); +#endif /* defined(DSI) */ + +#if defined(USB_OTG_HS) + /* Get the USB PHY clock source ------------------------------------------------*/ + pPeriphClkInit->UsbPhyClockSelection = __HAL_RCC_GET_USBPHY_SOURCE(); +#endif /* defined(USB_OTG_HS) */ +} + +/** + * @brief Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency + * @note The PLL1 clock frequencies computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note The function returns values based on HSE_VALUE, HSI_VALUE or MSI Value multiplied/divided by the PLL + * factors. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time PLL1CLK changes, this function must be called to update the + * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect. + * @param PLL1_Clocks structure. + * @retval None + */ +void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) +{ + uint32_t pll1source; + uint32_t pll1m; + uint32_t pll1n; + uint32_t pll1fracen; + float_t fracn1; + float_t pll1vco; + + pll1n = (RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N); + pll1source = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); + pll1m = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; + pll1fracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \ + RCC_PLL1FRACR_PLL1FRACN_Pos)); + + switch (pll1source) + { + + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ + pll1vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll1m) * \ + ((float_t)pll1n + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + default: + pll1vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll1m) * \ + ((float_t)pll1n + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + } + + if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVP) != 0U) + { + PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \ + RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + \ + (float_t)1)); + } + else + { + PLL1_Clocks->PLL1_P_Frequency = 0U; + } + + if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVQ) != 0U) + { + PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \ + RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + \ + (float_t)1)); + } + else + { + PLL1_Clocks->PLL1_Q_Frequency = 0U; + } + + if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVR) != 0U) + { + PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \ + RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + \ + (float_t)1)); + } + else + { + PLL1_Clocks->PLL1_R_Frequency = 0U; + } + +} + +/** + * @brief Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency + * @note The PLL2 clock frequencies computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL + * factors. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time PLL2CLK changes, this function must be called to update the + * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. + * @param PLL2_Clocks structure. + * @retval None + */ +void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) +{ + uint32_t pll2source; + uint32_t pll2m; + uint32_t pll2n; + uint32_t pll2fracen; + float_t fracn2; + float_t pll2vco; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N + PLL2xCLK = PLL2_VCO / PLL2x */ + pll2n = (RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N); + pll2source = (RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC); + pll2m = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1U; + pll2fracen = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN) >> RCC_PLL2CFGR_PLL2FRACEN_Pos); + fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \ + RCC_PLL2FRACR_PLL2FRACN_Pos)); + + switch (pll2source) + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) + \ + (fracn2 / (float_t)0x2000) + (float_t)1); + break; + + case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ + pll2vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll2m) * \ + ((float_t)pll2n + (fracn2 / (float_t)0x2000) + (float_t)1); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) + \ + (fracn2 / (float_t)0x2000) + (float_t)1); + break; + + default: + pll2vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t) pll2m) \ + * ((float_t)pll2n + (fracn2 / (float_t)0x2000) + (float_t)1); + break; + } + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVP) != 0U) + { + PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \ + RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + \ + (float_t)1)); + } + else + { + PLL2_Clocks->PLL2_P_Frequency = 0U; + } + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVQ) != 0U) + { + PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \ + RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + \ + (float_t)1)); + } + else + { + PLL2_Clocks->PLL2_Q_Frequency = 0U; + } + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVR) != 0U) + { + PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \ + RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + \ + (float_t)1)); + } + else + { + PLL2_Clocks->PLL2_R_Frequency = 0U; + } +} + +/** + * @brief Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency + * @note The PLL3 clock frequencies computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL + * factors. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time PLL3CLK changes, this function must be called to update the + * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. + * @param PLL3_Clocks structure. + * @retval None + */ +void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) +{ + uint32_t pll3source; + uint32_t pll3m; + uint32_t pll3n; + uint32_t pll3fracen; + float_t fracn3; + float_t pll3vco; + + /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N + PLL3xCLK = PLL3_VCO / PLLxR + */ + + pll3n = (RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N); + pll3source = (RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC); + pll3m = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos) + 1U; + pll3fracen = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3FRACEN) >> RCC_PLL3CFGR_PLL3FRACEN_Pos); + fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \ + RCC_PLL3FRACR_PLL3FRACN_Pos)); + + switch (pll3source) + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) + \ + (fracn3 / (float_t)0x2000) + (float_t)1); + + break; + case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ + pll3vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll3m) * \ + ((float_t)pll3n + (fracn3 / (float_t)0x2000) + (float_t)1); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) + \ + (fracn3 / (float_t)0x2000) + (float_t)1); + break; + + default: + pll3vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll3m) * \ + ((float_t)pll3n + (fracn3 / (float_t)0x2000) + (float_t)1); + break; + } + + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVP) != 0U) + { + PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \ + RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + \ + (float_t)1)); + } + else + { + PLL3_Clocks->PLL3_P_Frequency = 0U; + } + + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVQ) != 0U) + { + PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \ + RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + \ + (float_t)1)); + } + else + { + PLL3_Clocks->PLL3_Q_Frequency = 0U; + } + + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVR) != 0U) + { + PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \ + RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + \ + (float_t)1)); + } + else + { + PLL3_Clocks->PLL3_R_Frequency = 0U; + } + +} + +/** + * @brief Return the peripheral clock frequency for peripherals + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock + * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock + * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock + * @arg @ref RCC_PERIPHCLK_ICLK ICLK peripheral clock + * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock + * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock + * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock + * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock + * @arg @ref RCC_PERIPHCLK_SDMMC SDMMC peripheral clock + * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_OSPI OSPI peripheral clock + * @arg @ref RCC_PERIPHCLK_HSPI HSPI peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_I2C5 I2C5 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_I2C6 I2C6 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_USBPHY USB_OTG_HS peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock + * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1 ADC2 ADC4 DAC1 peripheral clock + * @arg @ref RCC_PERIPHCLK_DAC1 DAC1 peripheral clock + * @arg @ref RCC_PERIPHCLK_ADF1 ADF1 peripheral clock + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @retval Frequency in Hz + * + * (*) value not defined in all devices. + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) +{ + PLL1_ClocksTypeDef pll1_clocks; + PLL2_ClocksTypeDef pll2_clocks; + PLL3_ClocksTypeDef pll3_clocks; + + uint32_t frequency; + uint32_t srcclk; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + + if (PeriphClk == RCC_PERIPHCLK_RTC) + { + /* Get the current RTC source */ + srcclk = __HAL_RCC_GET_RTC_SOURCE(); + + /* Check if LSE is ready and if RTC clock selection is LSE */ + if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Check if LSI is ready and if RTC clock selection is LSI */ + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI)) + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV)) + { + frequency = LSI_VALUE / 128U; + } + else + { + frequency = LSI_VALUE; + } + } + /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIV32)) + { + frequency = HSE_VALUE / 32U; + } + /* Clock not enabled for RTC*/ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_SAI1) + { + srcclk = __HAL_RCC_GET_SAI1_SOURCE(); + + switch (srcclk) + { + case RCC_SAI1CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */ + + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_P_Frequency; + break; + + case RCC_SAI1CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */ + + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; + + case RCC_SAI1CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */ + + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + break; + + case RCC_SAI1CLKSOURCE_PIN: + + frequency = EXTERNAL_SAI1_CLOCK_VALUE; + break; + + case RCC_SAI1CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */ + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + else + { + frequency = 0U; + } + break; + + default : + { + frequency = 0U; + break; + } + } + } +#if defined(SAI2) + else if (PeriphClk == RCC_PERIPHCLK_SAI2) + { + srcclk = __HAL_RCC_GET_SAI2_SOURCE(); + + switch (srcclk) + { + case RCC_SAI2CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */ + + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_P_Frequency; + break; + + case RCC_SAI2CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */ + + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; + + case RCC_SAI2CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */ + + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + break; + + case RCC_SAI2CLKSOURCE_PIN: + + frequency = EXTERNAL_SAI1_CLOCK_VALUE; + break; + + case RCC_SAI2CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */ + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + else + { + frequency = 0U; + } + break; + + default : + + frequency = 0U; + break; + } + } +#endif /* SAI2 */ +#if defined(SAES) + else if (PeriphClk == RCC_PERIPHCLK_SAES) + { + /* Get the current SAES source */ + srcclk = __HAL_RCC_GET_SAES_SOURCE(); + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI)) + { + frequency = HSI_VALUE; + } + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI_DIV2)) + { + frequency = HSI_VALUE >> 1U; + } + /* Clock not enabled for SAES */ + else + { + frequency = 0U; + } + } +#endif /* SAES */ + else if (PeriphClk == RCC_PERIPHCLK_ICLK) + { + srcclk = __HAL_RCC_GET_ICLK_SOURCE(); + + switch (srcclk) + { + case RCC_ICLK_CLKSOURCE_PLL1: /* PLL1Q */ + + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; + + case RCC_ICLK_CLKSOURCE_PLL2: /* PLL2Q */ + + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + break; + + case RCC_ICLK_CLKSOURCE_HSI48: /* HSI48 */ + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) + { + frequency = HSI48_VALUE; + } + else + { + frequency = 0U; + } + break; + + case RCC_ICLK_CLKSOURCE_MSIK: /* MSIK frequency range in HZ */ + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + break; + + default : + + frequency = 0U; + break; + } + } + else if (PeriphClk == RCC_PERIPHCLK_SDMMC) + { + srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); + if (srcclk == RCC_SDMMCCLKSOURCE_CLK48) + { + srcclk = __HAL_RCC_GET_ICLK_SOURCE(); + + switch (srcclk) + { + case RCC_ICLK_CLKSOURCE_PLL1: /* PLL1Q */ + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; + } + case RCC_ICLK_CLKSOURCE_PLL2: /* PLL2Q */ + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + break; + } + case RCC_ICLK_CLKSOURCE_HSI48: /* HSI48 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) + { + frequency = HSI48_VALUE; + } + else + { + frequency = 0U; + } + break; + } + case RCC_ICLK_CLKSOURCE_MSIK: /* MSIK frequency range in HZ */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + break; + } + default : + { + frequency = 0U; + break; + } + } + } + else if (srcclk == RCC_SDMMCCLKSOURCE_PLL1) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_P_Frequency; + } + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_USART1) + { + /* Get the current USART1 source */ + srcclk = __HAL_RCC_GET_USART1_SOURCE(); + + if (srcclk == RCC_USART1CLKSOURCE_PCLK2) + { + frequency = HAL_RCC_GetPCLK2Freq(); + } + else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART1 */ + else + { + frequency = 0U; + } + } +#if defined(USART2) + else if (PeriphClk == RCC_PERIPHCLK_USART2) + { + /* Get the current USART2 source */ + srcclk = __HAL_RCC_GET_USART2_SOURCE(); + + if (srcclk == RCC_USART2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART2 */ + else + { + frequency = 0U; + } + } +#endif /* USART2 */ + else if (PeriphClk == RCC_PERIPHCLK_USART3) + { + /* Get the current USART3 source */ + srcclk = __HAL_RCC_GET_USART3_SOURCE(); + + if (srcclk == RCC_USART3CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART3 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_UART4) + { + /* Get the current UART4 source */ + srcclk = __HAL_RCC_GET_UART4_SOURCE(); + + if (srcclk == RCC_UART4CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for UART4 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_UART5) + { + /* Get the current UART5 source */ + srcclk = __HAL_RCC_GET_UART5_SOURCE(); + + if (srcclk == RCC_UART5CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for UART5 */ + else + { + frequency = 0U; + } + } +#if defined(USART6) + else if (PeriphClk == RCC_PERIPHCLK_USART6) + { + /* Get the current USART6 source */ + srcclk = __HAL_RCC_GET_USART6_SOURCE(); + + if (srcclk == RCC_USART6CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_USART6CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART6CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART6CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for UART5 */ + else + { + frequency = 0U; + } + } +#endif /* USART6 */ + else if (PeriphClk == RCC_PERIPHCLK_LPUART1) + { + /* Get the current LPUART1 source */ + srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); + + if (srcclk == RCC_LPUART1CLKSOURCE_PCLK3) + { + frequency = HAL_RCC_GetPCLK3Freq(); + } + else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_MSIK)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + /* Clock not enabled for LPUART1 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_ADCDAC) + { + srcclk = __HAL_RCC_GET_ADCDAC_SOURCE(); + + if (srcclk == RCC_ADCDACCLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if (srcclk == RCC_ADCDACCLKSOURCE_PLL2) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; + } + else if (srcclk == RCC_ADCDACCLKSOURCE_HCLK) + { + frequency = HAL_RCC_GetHCLKFreq(); + } + else if (srcclk == RCC_ADCDACCLKSOURCE_MSIK) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSE)) + { + frequency = HSE_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + /* Clock not enabled for ADC */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_MDF1) + { + /* Get the current MDF1 source */ + srcclk = __HAL_RCC_GET_MDF1_SOURCE(); + + switch (srcclk) + { + case RCC_MDF1CLKSOURCE_PLL1: + + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_P_Frequency; + break; + + case RCC_MDF1CLKSOURCE_PLL3: + + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + break; + + case RCC_MDF1CLKSOURCE_HCLK: + + frequency = HAL_RCC_GetHCLKFreq(); + break; + + case RCC_MDF1CLKSOURCE_PIN: + + frequency = EXTERNAL_SAI1_CLOCK_VALUE; + break; + + case RCC_MDF1CLKSOURCE_MSIK: + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + break; + + default: + + frequency = 0U; + break; + } + } + else if (PeriphClk == RCC_PERIPHCLK_ADF1) + { + /* Get the current ADF1 source */ + srcclk = __HAL_RCC_GET_ADF1_SOURCE(); + + switch (srcclk) + { + case RCC_ADF1CLKSOURCE_PLL1: + + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_P_Frequency; + break; + + case RCC_ADF1CLKSOURCE_PLL3: + + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + break; + + case RCC_ADF1CLKSOURCE_HCLK: + + frequency = HAL_RCC_GetHCLKFreq(); + break; + + case RCC_ADF1CLKSOURCE_PIN: + + frequency = EXTERNAL_SAI1_CLOCK_VALUE; + break; + + case RCC_ADF1CLKSOURCE_MSIK: + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + break; + + default: + + frequency = 0U; + break; + } + } + else if (PeriphClk == RCC_PERIPHCLK_I2C1) + { + /* Get the current I2C1 source */ + srcclk = __HAL_RCC_GET_I2C1_SOURCE(); + + if (srcclk == RCC_I2C1CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C1CLKSOURCE_MSIK)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + /* Clock not enabled for I2C1 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_I2C2) + { + /* Get the current I2C2 source */ + srcclk = __HAL_RCC_GET_I2C2_SOURCE(); + + if (srcclk == RCC_I2C2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C2CLKSOURCE_MSIK)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + /* Clock not enabled for I2C2 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_I2C3) + { + /* Get the current I2C3 source */ + srcclk = __HAL_RCC_GET_I2C3_SOURCE(); + + switch (srcclk) + { + case RCC_I2C3CLKSOURCE_PCLK3: + { + frequency = HAL_RCC_GetPCLK3Freq(); + break; + } + case RCC_I2C3CLKSOURCE_HSI: + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + else + { + frequency = 0U; + } + break; + } + case RCC_I2C3CLKSOURCE_SYSCLK: + { + frequency = HAL_RCC_GetSysClockFreq(); + break; + } + case RCC_I2C3CLKSOURCE_MSIK: + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + break; + } + default: + { + frequency = 0U; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_I2C4) + { + /* Get the current I2C4 source */ + srcclk = __HAL_RCC_GET_I2C4_SOURCE(); + + if (srcclk == RCC_I2C4CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C4CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C4CLKSOURCE_MSIK)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + /* Clock not enabled for I2C4 */ + else + { + frequency = 0U; + } + } +#if defined (I2C5) + else if (PeriphClk == RCC_PERIPHCLK_I2C5) + { + /* Get the current I2C5 source */ + srcclk = __HAL_RCC_GET_I2C5_SOURCE(); + + if (srcclk == RCC_I2C5CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C5CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C5CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C5CLKSOURCE_MSIK)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + /* Clock not enabled for I2C5 */ + else + { + frequency = 0U; + } + } +#endif /* I2C5 */ +#if defined (I2C6) + else if (PeriphClk == RCC_PERIPHCLK_I2C6) + { + /* Get the current I2C6 source */ + srcclk = __HAL_RCC_GET_I2C6_SOURCE(); + + if (srcclk == RCC_I2C6CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C6CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C6CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C6CLKSOURCE_MSIK)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + /* Clock not enabled for I2C6 */ + else + { + frequency = 0U; + } + } +#endif /* I2C6 */ + else if (PeriphClk == RCC_PERIPHCLK_LPTIM34) + { + /* Get the current LPTIM34 source */ + srcclk = __HAL_RCC_GET_LPTIM34_SOURCE(); + + if (srcclk == RCC_LPTIM34CLKSOURCE_MSIK) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSI)) + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV)) + { + frequency = LSI_VALUE / 128U; + } + else + { + frequency = LSI_VALUE; + } + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for LPTIM34 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_LPTIM1) + { + /* Get the current LPTIM1 source */ + srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); + + if (srcclk == RCC_LPTIM1CLKSOURCE_MSIK) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI)) + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV)) + { + frequency = LSI_VALUE / 128U; + } + else + { + frequency = LSI_VALUE; + } + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for LPTIM1 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_LPTIM2) + { + /* Get the current LPTIM2 source */ + srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); + + if (srcclk == RCC_LPTIM2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSI)) + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV)) + { + frequency = LSI_VALUE / 128U; + } + else + { + frequency = LSI_VALUE; + } + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for LPTIM2 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_FDCAN1) + { + /* Get the current FDCAN1 kernel source */ + srcclk = __HAL_RCC_GET_FDCAN1_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCAN1CLKSOURCE_HSE)) + { + frequency = HSE_VALUE; + } + else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL1) /* PLL1 ? */ + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL2) /* PLL2 ? */ + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + /* Clock not enabled for FDCAN1 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_SPI1) + { + /* Get the current SPI1 kernel source */ + srcclk = __HAL_RCC_GET_SPI1_SOURCE(); + switch (srcclk) + { + case RCC_SPI1CLKSOURCE_PCLK2: + + frequency = HAL_RCC_GetPCLK2Freq(); + break; + + case RCC_SPI1CLKSOURCE_SYSCLK: + + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_SPI1CLKSOURCE_HSI: + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + else + { + frequency = 0U; + } + break; + + case RCC_SPI1CLKSOURCE_MSIK: + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + break; + + default: + + frequency = 0U; + break; + } + } + else if (PeriphClk == RCC_PERIPHCLK_SPI2) + { + /* Get the current SPI2 kernel source */ + srcclk = __HAL_RCC_GET_SPI2_SOURCE(); + switch (srcclk) + { + case RCC_SPI2CLKSOURCE_PCLK1: + + frequency = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_SPI2CLKSOURCE_SYSCLK: + + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_SPI2CLKSOURCE_HSI: + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + else + { + frequency = 0U; + } + break; + + case RCC_SPI2CLKSOURCE_MSIK: + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + break; + + default: + + frequency = 0U; + break; + } + } + else if (PeriphClk == RCC_PERIPHCLK_SPI3) + { + /* Get the current SPI3 kernel source */ + srcclk = __HAL_RCC_GET_SPI3_SOURCE(); + switch (srcclk) + { + case RCC_SPI3CLKSOURCE_PCLK3: + + frequency = HAL_RCC_GetPCLK3Freq(); + break; + + case RCC_SPI3CLKSOURCE_SYSCLK: + + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_SPI3CLKSOURCE_HSI: + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + else + { + frequency = 0U; + } + break; + + case RCC_SPI3CLKSOURCE_MSIK: + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + break; + + default: + + frequency = 0U; + break; + } + } + else if (PeriphClk == RCC_PERIPHCLK_OSPI) + { + /* Get the current OSPI kernel source */ + srcclk = __HAL_RCC_GET_OSPI_SOURCE(); + + switch (srcclk) + { + case RCC_OSPICLKSOURCE_PLL2: + + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + break; + + case RCC_OSPICLKSOURCE_PLL1: + + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; + + case RCC_OSPICLKSOURCE_SYSCLK: + + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_OSPICLKSOURCE_MSIK: + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + break; + + default: + + frequency = 0U; + break; + } + } +#if defined(HSPI1) + + else if (PeriphClk == RCC_PERIPHCLK_HSPI) + { + /* Get the current HSPI kernel source */ + srcclk = __HAL_RCC_GET_HSPI_SOURCE(); + + switch (srcclk) + { + case RCC_HSPICLKSOURCE_SYSCLK: + + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_HSPICLKSOURCE_PLL1: + + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; + + case RCC_HSPICLKSOURCE_PLL2: + + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + break; + case RCC_HSPICLKSOURCE_PLL3: + + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + break; + + default: + + frequency = 0U; + break; + } + } +#endif /* defined(HSPI1) */ + else if (PeriphClk == RCC_PERIPHCLK_DAC1) + { + /* Get the current DAC1 kernel source */ + srcclk = __HAL_RCC_GET_DAC1_SOURCE(); + + /* Check if LSE is ready and if DAC1 clock selection is LSE */ + if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Check if LSI is ready and if DAC1 clock selection is LSI */ + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSI)) + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV)) + { + frequency = LSI_VALUE / 128U; + } + else + { + frequency = LSI_VALUE; + } + } + /* Clock not enabled for DAC1*/ + else + { + frequency = 0U; + } + + } + else if (PeriphClk == RCC_PERIPHCLK_RNG) + { + /* Get the current RNG kernel source */ + srcclk = __HAL_RCC_GET_RNG_SOURCE(); + + /* Check if HSI48 is ready and if RNG clock selection is HSI48 */ + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48)) + { + frequency = HSI48_VALUE; + } + + /* Check if HSI48 is ready and if RNG clock selection is HSI48_DIV2 */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48_DIV2)) + { + frequency = HSI48_VALUE >> 1U ; + } + + /* Check if HSI is ready and if RNG clock selection is HSI */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + /* Clock not enabled for RNG */ + else + { + frequency = 0U; + } + } +#if defined(LTDC) + else if (PeriphClk == RCC_PERIPHCLK_LTDC) + { + /* Get the current LTDC kernel source */ + srcclk = __HAL_RCC_GET_LTDC_SOURCE(); + + switch (srcclk) + { + case RCC_LTDCCLKSOURCE_PLL3: /* PLL3R is the clock source for LTDC */ + + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + break; + + case RCC_LTDCCLKSOURCE_PLL2: /* PLL2R is the clock source for LTDC */ + + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; + break; + + default: + + frequency = 0U; + break; + } + } +#endif /* defined(LTDC) */ + +#if defined(USB_OTG_HS) + + else if (PeriphClk == RCC_PERIPHCLK_USBPHY) + { + /* Get the current USB_OTG_HS kernel source */ + srcclk = __HAL_RCC_GET_USBPHY_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_USBPHYCLKSOURCE_HSE)) + { + frequency = HSE_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_USBPHYCLKSOURCE_HSE_DIV2)) + { + frequency = HSE_VALUE >> 1U ; + } + else if (srcclk == RCC_USBPHYCLKSOURCE_PLL1) /* PLL1P */ + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_P_Frequency; + } + else if (srcclk == RCC_USBPHYCLKSOURCE_PLL1_DIV2) /* PLL1P_DIV2 */ + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = (pll1_clocks.PLL1_P_Frequency) / 2U; + } + /* Clock not enabled for USB_OTG_HS */ + else + { + frequency = 0U; + } + } +#endif /* defined(USB_OTG_HS) */ + + else + { + frequency = 0; + } + return (frequency); +} + + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions + * @brief Extended Clock management functions + * +@verbatim + =============================================================================== + ##### Extended clock management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the + activation or deactivation of MSI PLL-mode, PLL2, PLL3, LSE CSS, + Low speed clock output and clock after wake-up from STOP mode. +@endverbatim + * @{ + */ + +/** + * @brief Enable PLL2. + * @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that + * contains the configuration information for the PLL2 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(const RCC_PLL2InitTypeDef *PLL2Init) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + + /* check for PLL2 Parameters used to output PLL2CLK */ + assert_param(IS_RCC_PLLSOURCE(PLL2Init->PLL2Source)); + assert_param(IS_RCC_PLLM_VALUE(PLL2Init->PLL2M)); + assert_param(IS_RCC_PLLN_VALUE(PLL2Init->PLL2N)); + assert_param(IS_RCC_PLLP_VALUE(PLL2Init->PLL2P)); + assert_param(IS_RCC_PLLQ_VALUE(PLL2Init->PLL2Q)); + assert_param(IS_RCC_PLLR_VALUE(PLL2Init->PLL2R)); + assert_param(IS_RCC_PLL2CLOCKOUT_VALUE(PLL2Init->PLL2ClockOut)); + + /* Disable the PLL2 */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is ready to be updated */ + while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + break; + } + } + + if (status == HAL_OK) + { + /* Make sure PLL2Source is ready */ + status = RCCEx_PLLSource_Enable(PLL2Init->PLL2Source); + + if (status == HAL_OK) + { + /* Configure the PLL2 clock source, multiplication factor N, */ + /* and division factors M, P, Q and R */ + __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2Source, PLL2Init->PLL2M, PLL2Init->PLL2N, + PLL2Init->PLL2P, PLL2Init->PLL2Q, PLL2Init->PLL2R); + + /* Disable PLL2FRACN */ + __HAL_RCC_PLL2FRACN_DISABLE(); + + /* Configure PLL PLL2FRACN */ + __HAL_RCC_PLL2FRACN_CONFIG(PLL2Init->PLL2FRACN); + + /* Enable PLL2FRACN */ + __HAL_RCC_PLL2FRACN_ENABLE(); + + /* Select PLL2 input reference frequency range: VCI */ + __HAL_RCC_PLL2_VCIRANGE(PLL2Init->PLL2RGE); + + /* Configure the PLL2 Clock output(s) */ + __HAL_RCC_PLL2CLKOUT_ENABLE(PLL2Init->PLL2ClockOut); + + /* Enable the PLL2 again by setting PLL2ON to 1*/ + __HAL_RCC_PLL2_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + break; + } + } + } + } + + return status; +} + +/** + * @brief Disable PLL2. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + + /* Disable the PLL2 */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + break; + } + } + + /* To save power disable the PLL2 Source, FRACN and Clock outputs */ + CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN | RCC_PLL2CFGR_PLL2QEN | RCC_PLL2CFGR_PLL2REN | RCC_PLL2CFGR_PLL2SRC | \ + RCC_PLL2CFGR_PLL2FRACEN); + + return status; +} + +/** + * @brief Enable PLL3. + * @param PLL3Init pointer to an RCC_PLL3InitTypeDef structure that + * contains the configuration information for the PLL3 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(const RCC_PLL3InitTypeDef *PLL3Init) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + + /* check for PLL3 Parameters used to output PLL3CLK */ + assert_param(IS_RCC_PLLSOURCE(PLL3Init->PLL3Source)); + assert_param(IS_RCC_PLLM_VALUE(PLL3Init->PLL3M)); + assert_param(IS_RCC_PLLN_VALUE(PLL3Init->PLL3N)); + assert_param(IS_RCC_PLLP_VALUE(PLL3Init->PLL3P)); + assert_param(IS_RCC_PLL3CLOCKOUT_VALUE(PLL3Init->PLL3ClockOut)); + + /* Disable the PLL3 */ + __HAL_RCC_PLL3_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL3 is ready to be updated */ + while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + break; + } + } + + if (status == HAL_OK) + { + /* Make sure PLL3Source is ready */ + status = RCCEx_PLLSource_Enable(PLL3Init->PLL3Source); + + if (status == HAL_OK) + { + /* Configure the PLL3 clock source, multiplication factor N, */ + /* and division factors M and P */ + __HAL_RCC_PLL3_CONFIG(PLL3Init->PLL3Source, PLL3Init->PLL3M, PLL3Init->PLL3N, PLL3Init->PLL3P, PLL3Init->PLL3Q, \ + PLL3Init->PLL3R); + + /* Disable PLL3FRACN . */ + __HAL_RCC_PLL3FRACN_DISABLE(); + + /* Configure PLL PLL3FRACN */ + __HAL_RCC_PLL3FRACN_CONFIG(PLL3Init->PLL3FRACN); + + /* Enable PLL3FRACN . */ + __HAL_RCC_PLL3FRACN_ENABLE(); + + /* Select PLL3 input reference frequency range: VCI */ + __HAL_RCC_PLL3_VCIRANGE(PLL3Init->PLL3RGE); + + /* Configure the PLL3 Clock output(s) */ + __HAL_RCC_PLL3CLKOUT_ENABLE(PLL3Init->PLL3ClockOut); + + /* Enable the PLL3 again by setting PLL3ON to 1*/ + __HAL_RCC_PLL3_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL3 is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + break; + } + } + } + } + + return status; +} + +/** + * @brief Disable PLL3. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + + /* Disable the PLL3 */ + __HAL_RCC_PLL3_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL3 is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + break; + } + } + + /* To save power disable the PLL3 Source and Clock outputs */ + CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN | RCC_PLL3CFGR_PLL3QEN | RCC_PLL3CFGR_PLL3REN | RCC_PLL3CFGR_PLL3SRC | \ + RCC_PLL3CFGR_PLL3FRACEN); + + return status; +} + +/** + * @brief Select which MSI output clock uses the PLL mode. + * @note Prior to disable PLL-mode (MSIPLLEN = 0) before call HAL_RCCEx_EnableMSIPLLModeSelection. + * @note The MSI kernel clock output uses the same oscillator source than the MSI system + * clock output, then the PLL mode is applied to the both clocks outputs. + * @param MSIPLLModeSelection specifies which MSI output clock uses the PLL mode. + * This parameter can be one of the following values: + * @arg @ref RCC_MSISPLL_MODE_SEL PLL mode applied to MSIS (MSI system) clock output + * @arg @ref RCC_MSIKPLL_MODE_SEL PLL mode applied to MSIK (MSI kernel) clock output + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLModeSelection(uint32_t MSIPLLModeSelection) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + assert_param(IS_RCC_MSIPLLMODE_SELECT(MSIPLLModeSelection)); + if (READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == 0U) + { + /* This bit is used only if PLL mode is disabled (MSIPLLEN = 0) */ + if (MSIPLLModeSelection == RCC_MSISPLL_MODE_SEL) + { + SET_BIT(RCC->CR, RCC_CR_MSIPLLSEL); + } + else + { + CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLSEL); + } + status = HAL_OK; + } + + return status; +} + +/** + * @brief Enable the fast PLL mode start-up of the MSI clock + * @note Prior to enable PLL-mode (MSIPLLEN = 1) before call HAL_RCCEx_EnableMSIPLLFastStartup. + * @note The fast start-up feature is not active the first time the PLL mode is selected. The + * fast start-up is active when the MSI in PLL mode returns from switch off. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLFastStartup(void) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + if (READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == RCC_CR_MSIPLLEN) + { + /* This bit is used only if PLL mode is selected (MSIPLLEN = 1) */ + SET_BIT(RCC->CR, RCC_CR_MSIPLLFAST); + status = HAL_OK; + } + + return status; +} + +/** + * @brief Disable the fast PLL mode start-up of the MSI clock + * @note the MSI fast startup mode disabled only when PLL-mode is enabled + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisableMSIPLLFastStartup(void) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + if (READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == RCC_CR_MSIPLLEN) + { + /* This bit is used only if PLL mode is selected (MSIPLLEN = 1) */ + CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLFAST); + status = HAL_OK; + } + return status; +} + +/** + * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock. + * @param WakeUpClk Wakeup clock + * This parameter can be one of the following values: + * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI oscillator selection + * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection + * @note This function shall not be called after the Clock Security System on HSE has been + * enabled. + * @retval None + */ +void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) +{ + assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk)); + + __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk); +} + +/** + * @brief Configure the oscillator Kernel clock source for wakeup from Stop + * @param WakeUpClk: Kernel Wakeup clock + * This parameter can be one of the following values: + * @arg RCC_STOP_KERWAKEUPCLOCK_MSI: MSI oscillator selection + * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection + * @retval None + */ +void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk) +{ + assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk)); + + __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk); +} + +/** + * @brief Configure the MSI range after standby mode. + * @note After Standby its frequency can be selected between 3 possible values (1, 3.072 or 4 MHz). + * @param MSIRange MSI range + * This parameter can be one of the following values: + * @arg @ref RCC_MSIRANGE_4 Range 4 around 4 MHz (reset value) + * @arg @ref RCC_MSIRANGE_5 Range 5 around 2 MHz + * @arg @ref RCC_MSIRANGE_6 Range 6 around 1.33 MHz + * @arg @ref RCC_MSIRANGE_7 Range 7 around 1 MHz + * @arg @ref RCC_MSIRANGE_8 Range 8 around 3.072 MHz + * @retval None + */ +void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange) +{ + assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange)); + + __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange); +} + +/** + * @brief Configure the MSIK range after standby mode. + * @note After Standby its frequency can be selected between 5 possible values (1, 1.33, 2, 3.072 or 4 MHz). + * @param MSIKRange MSIK range + * This parameter can be one of the following values: + * @arg @ref RCC_MSIKRANGE_4 Range 4 around 4 MHz (reset value) + * @arg @ref RCC_MSIKRANGE_5 Range 5 around 2 MHz + * @arg @ref RCC_MSIKRANGE_6 Range 6 around 1.33 MHz + * @arg @ref RCC_MSIKRANGE_7 Range 7 around 1 MHz + * @arg @ref RCC_MSIKRANGE_8 Range 8 around 3.072 MHz + * @retval None + */ +void HAL_RCCEx_StandbyMSIKRangeConfig(uint32_t MSIKRange) +{ + assert_param(IS_RCC_MSIK_STANDBY_CLOCK_RANGE(MSIKRange)); + + __HAL_RCC_MSIK_STANDBY_RANGE_CONFIG(MSIKRange); +} + +/** + * @brief Enable the LSE Clock Security System. + * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled + * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC + * clock with HAL_RCCEx_PeriphCLKConfig(). + * @retval None + */ +void HAL_RCCEx_EnableLSECSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Disable the LSE Clock Security System. + * @note LSE Clock Security System can only be disabled after a LSE failure detection. + * @retval None + */ +void HAL_RCCEx_DisableLSECSS(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line. + * @note LSE Clock Security System Interrupt is mapped on EXTI line + * Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. + * @retval None + */ +void HAL_RCCEx_EnableLSECSS_IT(void) +{ + /* Enable LSE CSS */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; + + /* Enable IT on LSECSS EXTI Line */ + SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS); + /* Enable the RCC LSECSS EXTI Interrupt Rising Edge */ + SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS); +} + +/** + * @brief Handle the RCC LSE Clock Security System interrupt request. + * @note LSECSS EXTI is not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. + * @retval None + */ +void HAL_RCCEx_LSECSS_IRQHandler(void) +{ + uint32_t falling_edge_flag; + uint32_t rising_edge_flag; + + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) != 0U) + { + /* Read Falling Edge flag on LSECSS EXTI interrupt */ + falling_edge_flag = READ_BIT(EXTI->FPR1, RCC_EXTI_LINE_LSECSS); + + /* Read Rising Edge flag on LSECSS EXTI interrupt */ + rising_edge_flag = READ_BIT(EXTI->RPR1, RCC_EXTI_LINE_LSECSS); + + /* Check Rising/falling Edge flag on LSECSS EXTI interrupt */ + if ((falling_edge_flag == RCC_EXTI_LINE_LSECSS) || \ + (rising_edge_flag == RCC_EXTI_LINE_LSECSS)) + { + if (rising_edge_flag == RCC_EXTI_LINE_LSECSS) + { + /* Clear the RCC LSECSS EXTI Rising Edge flag */ + WRITE_REG(EXTI->RPR1, RCC_EXTI_LINE_LSECSS); + } + if (falling_edge_flag == RCC_EXTI_LINE_LSECSS) + { + /* Clear the RCC LSECSS EXTI Falling Edge flag */ + WRITE_REG(EXTI->FPR1, RCC_EXTI_LINE_LSECSS); + } + } + /* RCC LSECSS interrupt user callback */ + HAL_RCCEx_LSECSS_Callback(); + } +} + +/** + * @brief RCCEx LSE Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_LSECSS_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file + */ +} + +/** + * @brief Enable the MSI PLL Unlock Interrupt & corresponding EXTI line. + * @note MSI PLL Unlock Interrupt is mapped on EXTI line + * Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. + * @retval None + */ +void HAL_RCCEx_EnableMSIPLLUNLCK_IT(void) +{ + /* Enable IT on MSI PLL Unlock EXTI Line */ + SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_MSIPLLUNLCK); + /* Enable the RCC MSI PLL UNLOCK EXTI Interrupt Rising Edge */ + SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_MSIPLLUNLCK); +} + +/** + * @brief Handle the RCC MSI PLL Unlock interrupt request. + * @note Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. + * @retval None + */ +void HAL_RCCEx_MSIPLLUNLCK_IRQHandler(void) +{ + uint32_t rising_edge_flag = READ_BIT(EXTI->RPR1, RCC_EXTI_LINE_MSIPLLUNLCK); + uint32_t falling_edge_flag = READ_BIT(EXTI->FPR1, RCC_EXTI_LINE_MSIPLLUNLCK); + + /* Check Rising/falling Edge flag on MSI PLL UNLOCK EXTI interrupt */ + if ((rising_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK) || \ + (falling_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK)) + { + if (rising_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK) + { + /* Clear the RCC MSI PLL UNLOCK EXTI Rising Edge flag */ + WRITE_REG(EXTI->RPR1, RCC_EXTI_LINE_MSIPLLUNLCK); + } + if (falling_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK) + { + /* Clear the RCC MSI PLL UNLOCK EXTI Falling Edge flag */ + WRITE_REG(EXTI->FPR1, RCC_EXTI_LINE_MSIPLLUNLCK); + } + /* RCC MSI PLL Unlock interrupt user callback */ + HAL_RCCEx_MSIPLLUNLCK_Callback(); + } +} + +/** + * @brief RCCEx RCC MSI PLL Unlock interrupt callback. + * @note Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. + * @retval none + */ +__weak void HAL_RCCEx_MSIPLLUNLCK_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_MSIPLLUNLCK_Callback should be implemented in the user file + */ +} + +/** + * @brief Select the Low Speed clock source to output on LSCO pin (PA2). + * @param LSCOSource specifies the Low Speed clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source + * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source + * @retval None + */ +void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) +{ + FlagStatus pwrclkchanged = RESET; + FlagStatus backupchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); + + /* Update LSCOSEL clock source in Backup Domain control register */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) + { + HAL_PWR_EnableBkUpAccess(); + backupchanged = SET; + } + + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN); + + if (backupchanged == SET) + { + HAL_PWR_DisableBkUpAccess(); + } + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } +} + +/** + * @brief Disable the Low Speed clock output. + * @retval None + */ +void HAL_RCCEx_DisableLSCO(void) +{ + FlagStatus pwrclkchanged = RESET; + FlagStatus backupchanged = RESET; + + /* Update LSCOEN bit in Backup Domain control register */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) + { + /* Enable access to the backup domain */ + HAL_PWR_EnableBkUpAccess(); + backupchanged = SET; + } + + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); + + /* Restore previous configuration */ + if (backupchanged == SET) + { + /* Disable access to the backup domain */ + HAL_PWR_DisableBkUpAccess(); + } + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } +} + +/** + * @brief Enable the PLL-mode of the MSI. + * @note Prior to enable the PLL-mode of the MSI for automatic hardware + * calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig(). + * @retval None + */ +void HAL_RCCEx_EnableMSIPLLMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_MSIPLLEN); +} + +/** + * @brief Disable the PLL-mode of the MSI. + * @note PLL-mode of the MSI is automatically reset when LSE oscillator is disabled. + * @retval None + */ +void HAL_RCCEx_DisableMSIPLLMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN); +} +/** + * @} + */ + +#if defined(CRS) + +/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions + * @brief Extended Clock Recovery System Control functions + * +@verbatim + =============================================================================== + ##### Extended Clock Recovery System Control functions ##### + =============================================================================== + [..] + For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows: + + (#) In System clock config, HSI48 needs to be enabled + + (#) Enable CRS clock in IP MSP init which will use CRS functions + + (#) Call CRS functions as follows: + (##) Prepare synchronization configuration necessary for HSI48 calibration + (+++) Default values can be set for frequency Error Measurement (reload and error limit) + and also HSI48 oscillator smooth trimming. + (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate + directly reload value with target and synchronization frequencies values + (##) Call function HAL_RCCEx_CRSConfig which + (+++) Resets CRS registers to their default values. + (+++) Configures CRS registers with synchronization configuration + (+++) Enables automatic calibration and frequency error counter feature + Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the + periodic USB SOF will not be generated by the host. No SYNC signal will therefore be + provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock + precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs + should be used as SYNC signal. + + (##) A polling function is provided to wait for complete synchronization + (+++) Call function HAL_RCCEx_CRSWaitSynchronization() + (+++) According to CRS status, user can decide to adjust again the calibration or continue + application if synchronization is OK + + (#) User can retrieve information related to synchronization in calling function + HAL_RCCEx_CRSGetSynchronizationInfo() + + (#) Regarding synchronization status and synchronization information, user can try a new calibration + in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. + Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), + it means that the actual frequency is lower than the target (and so, that the TRIM value should be + incremented), while when it is detected during the upcounting phase it means that the actual frequency + is higher (and that the TRIM value should be decremented). + + (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go + through CRS Handler (CRS_IRQn/CRS_IRQHandler) + (++) Call function HAL_RCCEx_CRSConfig() + (++) Enable CRS_IRQn (thanks to NVIC functions) + (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) + (++) Implement CRS status management in the following user callbacks called from + HAL_RCCEx_CRS_IRQHandler(): + (+++) HAL_RCCEx_CRS_SyncOkCallback() + (+++) HAL_RCCEx_CRS_SyncWarnCallback() + (+++) HAL_RCCEx_CRS_ExpectedSyncCallback() + (+++) HAL_RCCEx_CRS_ErrorCallback() + + (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). + This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) + +@endverbatim + * @{ + */ + +/** + * @brief Start automatic synchronization for polling mode + * @param pInit Pointer on RCC_CRSInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *const pInit) +{ + uint32_t value; + + /* Check the parameters */ + assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); + assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); + assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); + assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); + assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); + assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); + + /* CONFIGURATION */ + + /* Before configuration, reset CRS registers to their default values*/ + __HAL_RCC_CRS_FORCE_RESET(); + __HAL_RCC_CRS_RELEASE_RESET(); + + /* Set the SYNCDIV[2:0] bits according to Prescaler value */ + /* Set the SYNCSRC[1:0] bits according to Source value */ + /* Set the SYNCSPOL bit according to Polarity value */ + value = (pInit->Prescaler | pInit->Source | pInit->Polarity); + /* Set the RELOAD[15:0] bits according to ReloadValue value */ + value |= pInit->ReloadValue; + /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ + value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); + WRITE_REG(CRS->CFGR, value); + + /* Adjust HSI48 oscillator smooth trimming */ + /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); + + /* START AUTOMATIC SYNCHRONIZATION*/ + + /* Enable Automatic trimming & Frequency error counter */ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); +} + +/** + * @brief Generate the software synchronization event + * @retval None + */ +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Return synchronization info + * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) +{ + /* Check the parameter */ + assert_param(pSynchroInfo != (void *) NULL); + + /* Get the reload value */ + pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); + + /* Get HSI48 oscillator smooth trimming */ + pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); + + /* Get Frequency error capture */ + pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); + + /* Get Frequency error direction */ + pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** + * @brief Wait for CRS Synchronization status. + * @param Timeout Duration of the timeout + * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization + * frequency. + * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. + * @retval Combination of Synchronization status + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_TIMEOUT + * @arg @ref RCC_CRS_SYNCOK + * @arg @ref RCC_CRS_SYNCWARN + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + */ +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) +{ + uint32_t crsstatus = RCC_CRS_NONE; + uint32_t tickstart; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait for CRS flag or timeout detection */ + do + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + crsstatus = RCC_CRS_TIMEOUT; + } + } + /* Check CRS SYNCOK flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) + { + /* CRS SYNC event OK */ + crsstatus |= RCC_CRS_SYNCOK; + + /* Clear CRS SYNC event OK bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); + } + + /* Check CRS SYNCWARN flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) + { + /* CRS SYNC warning */ + crsstatus |= RCC_CRS_SYNCWARN; + + /* Clear CRS SYNCWARN bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); + } + + /* Check CRS TRIM overflow flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_TRIMOVF; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); + } + + /* Check CRS Error flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_SYNCERR; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); + } + + /* Check CRS SYNC Missed flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) + { + /* CRS SYNC Missed */ + crsstatus |= RCC_CRS_SYNCMISS; + + /* Clear CRS SYNC Missed bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); + } + + /* Check CRS Expected SYNC flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) + { + /* frequency error counter reached a zero value */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); + } + } while (RCC_CRS_NONE == crsstatus); + + return crsstatus; +} + +/** + * @brief Handle the Clock Recovery System interrupt request. + * @retval None + */ +void HAL_RCCEx_CRS_IRQHandler(void) +{ + uint32_t crserror = RCC_CRS_NONE; + /* Get current IT flags and IT sources values */ + uint32_t itflags = READ_REG(CRS->ISR); + uint32_t itsources = READ_REG(CRS->CR); + + /* Check CRS SYNCOK flag */ + if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) + { + /* Clear CRS SYNC event OK flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); + + /* user callback */ + HAL_RCCEx_CRS_SyncOkCallback(); + } + /* Check CRS SYNCWARN flag */ + else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) + { + /* Clear CRS SYNCWARN flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); + + /* user callback */ + HAL_RCCEx_CRS_SyncWarnCallback(); + } + /* Check CRS Expected SYNC flag */ + else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U)) + { + /* frequency error counter reached a zero value */ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); + + /* user callback */ + HAL_RCCEx_CRS_ExpectedSyncCallback(); + } + /* Check CRS Error flags */ + else + { + if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U)) + { + if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) + { + crserror |= RCC_CRS_SYNCERR; + } + if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) + { + crserror |= RCC_CRS_SYNCMISS; + } + if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) + { + crserror |= RCC_CRS_TRIMOVF; + } + + /* Clear CRS Error flags */ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); + + /* user error callback */ + HAL_RCCEx_CRS_ErrorCallback(crserror); + } + } +} + +/** + * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncOkCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Error interrupt callback. + * @param Error Combination of Error status. + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + * @retval none + */ +__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Error); + + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file + */ +} + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/** @addtogroup RCCEx_Private_Functions + * @{ + */ +/** + * @brief Configure the PLL 1 source clock. + * @param PllSource PLL1 source clock it can be : + * RCC_PLLSOURCE_NONE + * RCC_PLLSOURCE_MSI + * RCC_PLLSOURCE_HSI + * RCC_PLLSOURCE_HSE + * + * @retval HAL status + */ +static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + + switch (PllSource) + { + case RCC_PLLSOURCE_MSI: + /* Check whether MSI in not ready and enable it */ + if (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U) + { + /* Enable the Internal Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till MSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + break; + } + } + } + break; + + case RCC_PLLSOURCE_HSI: + /* Check whether HSI in not ready and enable it */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + /* Enable the Internal High Speed oscillator (HSI) */ + __HAL_RCC_HSI_ENABLE(); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till MSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + break; + } + } + } + break; + + case RCC_PLLSOURCE_HSE: + /* Check whether HSE in not ready and enable it */ + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + /* Enable the External High Speed oscillator (HSE) */ + SET_BIT(RCC->CR, RCC_CR_HSEON); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + break; + } + } + } + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Configure the PLL2 VCI ranges, multiplication and division factors and enable it + * @param pll2: Pointer to an RCC_PLL2InitTypeDef structure that + * contains the configuration parameters as well as VCI clock ranges. + * @note PLL2 is temporary disabled to apply new parameters + * + * @retval HAL status + */ +static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2) +{ + + uint32_t tickstart; + assert_param(IS_RCC_PLLSOURCE(pll2->PLL2Source)); + assert_param(IS_RCC_PLLM_VALUE(pll2->PLL2M)); + assert_param(IS_RCC_PLLN_VALUE(pll2->PLL2N)); + assert_param(IS_RCC_PLLP_VALUE(pll2->PLL2P)); + assert_param(IS_RCC_PLLQ_VALUE(pll2->PLL2Q)); + assert_param(IS_RCC_PLLR_VALUE(pll2->PLL2R)); + + /* Disable PLL2 */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure PLL2 multiplication and division factors */ + __HAL_RCC_PLL2_CONFIG(pll2->PLL2Source, + pll2->PLL2M, + pll2->PLL2N, + pll2->PLL2P, + pll2->PLL2Q, + pll2->PLL2R); + + /* Select PLL2 input reference frequency range: VCI */ + __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE); + + /* Configure the PLL2 Clock output(s) */ + __HAL_RCC_PLL2CLKOUT_ENABLE(pll2->PLL2ClockOut); + + /* Disable PLL2FRACN */ + __HAL_RCC_PLL2FRACN_DISABLE(); + + /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ + __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); + + /* Enable PLL2FRACN */ + __HAL_RCC_PLL2FRACN_ENABLE(); + + /* Enable PLL2 */ + __HAL_RCC_PLL2_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; + +} + +/** + * @brief Configure the PLL3 VCI ranges, multiplication and division factors and enable it + * @param pll3: Pointer to an RCC_PLL3InitTypeDef structure that + * contains the configuration parameters as well as VCI clock ranges. + * @note PLL3 is temporary disabled to apply new parameters + * @retval HAL status + */ +static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3) +{ + uint32_t tickstart; + assert_param(IS_RCC_PLLSOURCE(pll3->PLL3Source)); + assert_param(IS_RCC_PLLM_VALUE(pll3->PLL3M)); + assert_param(IS_RCC_PLLN_VALUE(pll3->PLL3N)); + assert_param(IS_RCC_PLLP_VALUE(pll3->PLL3P)); + assert_param(IS_RCC_PLLQ_VALUE(pll3->PLL3Q)); + assert_param(IS_RCC_PLLR_VALUE(pll3->PLL3R)); + + /* Disable PLL3 */ + __HAL_RCC_PLL3_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure PLL3 multiplication and division factors */ + __HAL_RCC_PLL3_CONFIG(pll3->PLL3Source, + pll3->PLL3M, + pll3->PLL3N, + pll3->PLL3P, + pll3->PLL3Q, + pll3->PLL3R); + + /* Select PLL3 input reference frequency range: VCI */ + __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE); + + /* Configure the PLL3 Clock output(s) */ + __HAL_RCC_PLL3CLKOUT_ENABLE(pll3->PLL3ClockOut); + + /* Disable PLL3FRACN */ + __HAL_RCC_PLL3FRACN_DISABLE(); + + /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ + __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); + + /* Enable PLL3FRACN */ + __HAL_RCC_PLL3FRACN_ENABLE(); + + /* Enable PLL3 */ + __HAL_RCC_PLL3_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL3 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c new file mode 100644 index 000000000..3095a9f86 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c @@ -0,0 +1,1039 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_rng.c + * @author MCD Application Team + * @brief RNG HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Random Number Generator (RNG) peripheral: + * + Initialization and configuration functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The RNG HAL driver can be used as follows: + + (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro + in HAL_RNG_MspInit(). + (#) Activate the RNG peripheral using HAL_RNG_Init() function. + (#) Wait until the 32 bit Random Number Generator contains a valid + random data using (polling/interrupt) mode. + (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_RNG_RegisterCallback() to register a user callback. + Function HAL_RNG_RegisterCallback() allows to register following callbacks: + (+) ErrorCallback : RNG Error Callback. + (+) MspInitCallback : RNG MspInit. + (+) MspDeInitCallback : RNG MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default + weak (overridden) function. + HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) ErrorCallback : RNG Error Callback. + (+) MspInitCallback : RNG MspInit. + (+) MspDeInitCallback : RNG MspDeInit. + + [..] + For specific callback ReadyDataCallback, use dedicated register callbacks: + respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback(). + + [..] + By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET + all callbacks are set to the corresponding weak (overridden) functions: + example HAL_RNG_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (overridden) functions in the HAL_RNG_Init() + and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit() + or HAL_RNG_Init() function. + + [..] + When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (overridden) callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +#if defined (RNG) + +/** @addtogroup RNG + * @brief RNG HAL module driver. + * @{ + */ + +#ifdef HAL_RNG_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RNG_Private_Constants RNG Private Constants + * @{ + */ +#define RNG_TIMEOUT_VALUE 4U +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions prototypes ----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup RNG_Exported_Functions + * @{ + */ + +/** @addtogroup RNG_Exported_Functions_Group1 + * @brief Initialization and configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the RNG according to the specified parameters + in the RNG_InitTypeDef and create the associated handle + (+) DeInitialize the RNG peripheral + (+) Initialize the RNG MSP + (+) DeInitialize RNG MSP + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the RNG peripheral and creates the associated handle. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) +{ + uint32_t tickstart; + /* Check the RNG handle allocation */ + if (hrng == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ + assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance)); + assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection)); + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + if (hrng->State == HAL_RNG_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrng->Lock = HAL_UNLOCKED; + + hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */ + hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hrng->MspInitCallback == NULL) + { + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hrng->MspInitCallback(hrng); + } +#else + if (hrng->State == HAL_RNG_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrng->Lock = HAL_UNLOCKED; + + /* Init the low level hardware */ + HAL_RNG_MspInit(hrng); + } +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* Disable RNG */ + __HAL_RNG_DISABLE(hrng); + +#if defined(RNG_CR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + WRITE_REG(hrng->Instance->CR, RNG_CR_NIST_VALUE | RNG_CR_CONDRST | hrng->Init.ClockErrorDetection); +#else + /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ + MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST); +#endif /* RNG_CR_NIST_VALUE */ +#if defined(RNG_HTCR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + WRITE_REG(hrng->Instance->HTCR, RNG_HTCR_NIST_VALUE); +#endif /* RNG_HTCR_NIST_VALUE */ +#if defined(RNG_NSCR_NIST_VALUE) + WRITE_REG(hrng->Instance->NSCR, RNG_NSCR_NIST_VALUE); +#endif /* RNG_NSCR_NIST_VALUE */ + + /* Writing bit CONDRST=0 */ + CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for conditioning reset process to be completed */ + while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + return HAL_ERROR; + } + } + } + + /* Enable the RNG Peripheral */ + __HAL_RNG_ENABLE(hrng); + + /* verify that no seed error */ + if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + { + hrng->State = HAL_RNG_STATE_ERROR; + return HAL_ERROR; + } + /* Get tick */ + tickstart = HAL_GetTick(); + /* Check if data register contains valid random data */ + while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) + { + if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) + { + hrng->State = HAL_RNG_STATE_ERROR; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + return HAL_ERROR; + } + } + } + + /* Initialize the RNG state */ + hrng->State = HAL_RNG_STATE_READY; + + /* Initialise the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_NONE; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitializes the RNG peripheral. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) +{ + uint32_t tickstart; + + /* Check the RNG handle allocation */ + if (hrng == NULL) + { + return HAL_ERROR; + } + + /* Clear Clock Error Detection bit when CONDRT bit is set to 1 */ + MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, RNG_CED_ENABLE | RNG_CR_CONDRST); + + /* Writing bit CONDRST=0 */ + CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for conditioning reset process to be completed */ + while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } + } + } + + /* Disable the RNG Peripheral */ + CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN); + + /* Clear RNG interrupt status flags */ + CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS); + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + if (hrng->MspDeInitCallback == NULL) + { + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hrng->MspDeInitCallback(hrng); +#else + /* DeInit the low level hardware */ + HAL_RNG_MspDeInit(hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + + /* Update the RNG state */ + hrng->State = HAL_RNG_STATE_RESET; + + /* Initialise the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hrng); + + /* Return the function status */ + return HAL_OK; +} + +/** + * @brief Initializes the RNG MSP. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval None + */ +__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrng); + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_RNG_MspInit must be implemented in the user file. + */ +} + +/** + * @brief DeInitializes the RNG MSP. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval None + */ +__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrng); + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_RNG_MspDeInit must be implemented in the user file. + */ +} + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User RNG Callback + * To be used instead of the weak predefined callback + * @param hrng RNG handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID + * @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, + pRNG_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (HAL_RNG_STATE_READY == hrng->State) + { + switch (CallbackID) + { + case HAL_RNG_ERROR_CB_ID : + hrng->ErrorCallback = pCallback; + break; + + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = pCallback; + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_RNG_STATE_RESET == hrng->State) + { + switch (CallbackID) + { + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = pCallback; + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an RNG Callback + * RNG callback is redirected to the weak predefined callback + * @param hrng RNG handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID + * @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + + if (HAL_RNG_STATE_READY == hrng->State) + { + switch (CallbackID) + { + case HAL_RNG_ERROR_CB_ID : + hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_RNG_STATE_RESET == hrng->State) + { + switch (CallbackID) + { + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */ + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Data Ready RNG Callback + * To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback + * @param hrng RNG handle + * @param pCallback pointer to the Data Ready Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hrng); + + if (HAL_RNG_STATE_READY == hrng->State) + { + hrng->ReadyDataCallback = pCallback; + } + else + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrng); + return status; +} + +/** + * @brief UnRegister the Data Ready RNG Callback + * Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback + * @param hrng RNG handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hrng); + + if (HAL_RNG_STATE_READY == hrng->State) + { + hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */ + } + else + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrng); + return status; +} + +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup RNG_Exported_Functions_Group2 + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Get the 32 bit Random number + (+) Get the 32 bit Random number with interrupt enabled + (+) Handle RNG interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Generates a 32-bit random number. + * @note This function checks value of RNG_FLAG_DRDY flag to know if valid + * random number is available in the DR register (RNG_FLAG_DRDY flag set + * whenever a random number is available through the RNG_DR register). + * After transitioning from 0 to 1 (random number available), + * RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading + * four words from the RNG_DR register, i.e. further function calls + * will immediately return a new u32 random number (additional words are + * available and can be read by the application, till RNG_FLAG_DRDY flag remains high). + * @note When no more random number data is available in DR register, RNG_FLAG_DRDY + * flag is automatically cleared. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @param random32bit pointer to generated random number variable if successful. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hrng); + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + /* Check if there is a seed error */ + if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_SEED; + /* Reset from seed error */ + status = RNG_RecoverSeedError(hrng); + if (status == HAL_ERROR) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; + return status; + } + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if data register contains valid random data */ + while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } + } + } + + /* Get a 32bit Random number */ + hrng->RandomNumber = hrng->Instance->DR; + /* In case of seed error, the value available in the RNG_DR register must not + be used as it may not have enough entropy */ + if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + { + /* Update the error code and status */ + hrng->ErrorCode = HAL_RNG_ERROR_SEED; + status = HAL_ERROR; + } + else /* No seed error */ + { + *random32bit = hrng->RandomNumber; + } + hrng->State = HAL_RNG_STATE_READY; + } + else + { + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + + return status; +} + +/** + * @brief Generates a 32-bit random number in interrupt mode. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hrng); + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ + __HAL_RNG_ENABLE_IT(hrng); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Handles RNG interrupt request. + * @note In the case of a clock error, the RNG is no more able to generate + * random numbers because the PLL48CLK clock is not correct. User has + * to check that the clock controller is correctly configured to provide + * the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). + * The clock error has no impact on the previously generated + * random numbers, and the RNG_DR register contents can be used. + * @note In the case of a seed error, the generation of random numbers is + * interrupted as long as the SECS bit is '1'. If a number is + * available in the RNG_DR register, it must not be used because it may + * not have enough entropy. In this case, it is recommended to clear the + * SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable + * the RNG peripheral to reinitialize and restart the RNG. + * @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS + * or CEIS are set. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval None + + */ +void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) +{ + uint32_t rngclockerror = 0U; + uint32_t itflag = hrng->Instance->SR; + + /* RNG clock error interrupt occurred */ + if ((itflag & RNG_IT_CEI) == RNG_IT_CEI) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_CLOCK; + rngclockerror = 1U; + } + else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI) + { + /* Check if Seed Error Current Status (SECS) is set */ + if ((itflag & RNG_FLAG_SECS) != RNG_FLAG_SECS) + { + /* RNG IP performed the reset automatically (auto-reset) */ + /* Clear bit SEIS */ + CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI); + } + else + { + /* Seed Error has not been recovered : Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_SEED; + rngclockerror = 1U; + /* Disable the IT */ + __HAL_RNG_DISABLE_IT(hrng); + } + } + else + { + /* Nothing to do */ + } + + if (rngclockerror == 1U) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_ERROR; + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + /* Call registered Error callback */ + hrng->ErrorCallback(hrng); +#else + /* Call legacy weak Error callback */ + HAL_RNG_ErrorCallback(hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + + /* Clear the clock error flag */ + __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI); + + return; + } + + /* Check RNG data ready interrupt occurred */ + if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY) + { + /* Generate random number once, so disable the IT */ + __HAL_RNG_DISABLE_IT(hrng); + + /* Get the 32bit Random number (DRDY flag automatically cleared) */ + hrng->RandomNumber = hrng->Instance->DR; + + if (hrng->State != HAL_RNG_STATE_ERROR) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + /* Call registered Data Ready callback */ + hrng->ReadyDataCallback(hrng, hrng->RandomNumber); +#else + /* Call legacy weak Data Ready callback */ + HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Read latest generated random number. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval random value + */ +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng) +{ + return (hrng->RandomNumber); +} + +/** + * @brief Data Ready callback in non-blocking mode. + * @note When RNG_FLAG_DRDY flag value is set, first random number has been read + * from DR register in IRQ Handler and is provided as callback parameter. + * Depending on valid data available in the conditioning output buffer, + * additional words can be read by the application from DR register till + * DRDY bit remains high. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @param random32bit generated random number. + * @retval None + */ +__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrng); + UNUSED(random32bit); + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_RNG_ReadyDataCallback must be implemented in the user file. + */ +} + +/** + * @brief RNG error callbacks. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval None + */ +__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrng); + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_RNG_ErrorCallback must be implemented in the user file. + */ +} +/** + * @} + */ + + +/** @addtogroup RNG_Exported_Functions_Group3 + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the RNG state. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval HAL state + */ +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng) +{ + return hrng->State; +} + +/** + * @brief Return the RNG handle error code. + * @param hrng: pointer to a RNG_HandleTypeDef structure. + * @retval RNG Error Code + */ +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng) +{ + /* Return RNG Error Code */ + return hrng->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup RNG_Private_Functions + * @{ + */ + +/** + * @brief RNG sequence to recover from a seed error + * @param hrng pointer to a RNG_HandleTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng) +{ + __IO uint32_t count = 0U; + + /*Check if seed error current status (SECS)is set */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) == RESET) + { + /* RNG performed the reset automatically (auto-reset) */ + /* Clear bit SEIS */ + CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI); + } + else /* Sequence to fully recover from a seed error*/ + { + /* Writing bit CONDRST=1*/ + SET_BIT(hrng->Instance->CR, RNG_CR_CONDRST); + /* Writing bit CONDRST=0*/ + CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); + + /* Wait for conditioning reset process to be completed */ + count = RNG_TIMEOUT_VALUE; + do + { + count-- ; + if (count == 0U) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + /* Call registered Error callback */ + hrng->ErrorCallback(hrng); +#else + /* Call legacy weak Error callback */ + HAL_RNG_ErrorCallback(hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + return HAL_ERROR; + } + } while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)); + + if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + { + /* Clear bit SEIS */ + CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI); + } + + /* Wait for SECS to be cleared */ + count = RNG_TIMEOUT_VALUE; + do + { + count-- ; + if (count == 0U) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + /* Call registered Error callback */ + hrng->ErrorCallback(hrng); +#else + /* Call legacy weak Error callback */ + HAL_RNG_ErrorCallback(hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + return HAL_ERROR; + } + } while (HAL_IS_BIT_SET(hrng->Instance->SR, RNG_FLAG_SECS)); + } + /* Update the error code */ + hrng->ErrorCode &= ~ HAL_RNG_ERROR_SEED; + return HAL_OK; +} + +/** + * @} + */ + + +#endif /* HAL_RNG_MODULE_ENABLED */ +/** + * @} + */ + +#endif /* RNG */ + +/** + * @} + */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c new file mode 100644 index 000000000..d740553fb --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c @@ -0,0 +1,347 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_rng_ex.c + * @author MCD Application Team + * @brief Extended RNG HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Random Number Generator (RNG) peripheral: + * + Lock configuration functions + * + Reset the RNG + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +#if defined(RNG) + +/** @addtogroup RNGEx + * @brief RNG Extended HAL module driver. + * @{ + */ + +#ifdef HAL_RNG_MODULE_ENABLED +#if defined(RNG_CR_CONDRST) +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup RNGEx_Private_Constants + * @{ + */ +#define RNG_TIMEOUT_VALUE 2U +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions prototypes ----------------------------------------------*/ +/* Private functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions + * @{ + */ + +/** @defgroup RNGEx_Exported_Functions_Group1 Configuration and lock functions + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration and lock functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the RNG with the specified parameters in the RNG_ConfigTypeDef + (+) Lock RNG configuration Allows user to lock a configuration until next reset. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the RNG with the specified parameters in the + * RNG_ConfigTypeDef. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @param pConf pointer to a RNG_ConfigTypeDef structure that contains + * the configuration information for RNG module + + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf) +{ + uint32_t tickstart; + uint32_t cr_value; + HAL_StatusTypeDef status ; + + /* Check the RNG handle allocation */ + if ((hrng == NULL) || (pConf == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance)); + assert_param(IS_RNG_CLOCK_DIVIDER(pConf->ClockDivider)); + assert_param(IS_RNG_NIST_COMPLIANCE(pConf->NistCompliance)); + assert_param(IS_RNG_CONFIG1(pConf->Config1)); + assert_param(IS_RNG_CONFIG2(pConf->Config2)); + assert_param(IS_RNG_CONFIG3(pConf->Config3)); + assert_param(IS_RNG_ARDIS(pConf->AutoReset)); + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* Disable RNG */ + __HAL_RNG_DISABLE(hrng); + + /* RNG CR register configuration. Set value in CR register for : + - NIST Compliance setting + - Clock divider value + - Automatic reset to clear SECS bit + - CONFIG 1, CONFIG 2 and CONFIG 3 values */ + cr_value = (uint32_t)(pConf->ClockDivider | pConf->NistCompliance | pConf->AutoReset + | (pConf->Config1 << RNG_CR_RNG_CONFIG1_Pos) + | (pConf->Config2 << RNG_CR_RNG_CONFIG2_Pos) + | (pConf->Config3 << RNG_CR_RNG_CONFIG3_Pos)); + + MODIFY_REG(hrng->Instance->CR, RNG_CR_NISTC | RNG_CR_CLKDIV | RNG_CR_RNG_CONFIG1 + | RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3 | RNG_CR_ARDIS, + (uint32_t)(RNG_CR_CONDRST | cr_value)); + + /* RNG health test control in accordance with NIST */ + WRITE_REG(hrng->Instance->HTCR, pConf->HealthTest); + + /* RNG noise source control in accordance with NIST */ + WRITE_REG(hrng->Instance->NSCR, pConf->NoiseSource); + + /* Writing bit CONDRST=0*/ + CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for conditioning reset process to be completed */ + while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of prememption */ + if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + return HAL_ERROR; + } + } + } + + /* Enable RNG */ + __HAL_RNG_ENABLE(hrng); + + /* Initialize the RNG state */ + hrng->State = HAL_RNG_STATE_READY; + + /* function status */ + status = HAL_OK; + } + else + { + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Return the function status */ + return status; +} + +/** + * @brief Get the RNG Configuration and fill parameters in the + * RNG_ConfigTypeDef. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @param pConf pointer to a RNG_ConfigTypeDef structure that contains + * the configuration information for RNG module + + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf) +{ + + HAL_StatusTypeDef status ; + + /* Check the RNG handle allocation */ + if ((hrng == NULL) || (pConf == NULL)) + { + return HAL_ERROR; + } + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* Get RNG parameters */ + pConf->Config1 = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos) ; + pConf->Config2 = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos); + pConf->Config3 = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos); + pConf->ClockDivider = (hrng->Instance->CR & RNG_CR_CLKDIV); + pConf->NistCompliance = (hrng->Instance->CR & RNG_CR_NISTC); + pConf->AutoReset = (hrng->Instance->CR & RNG_CR_ARDIS); + pConf->HealthTest = (hrng->Instance->HTCR); + + /* Initialize the RNG state */ + hrng->State = HAL_RNG_STATE_READY; + + /* function status */ + status = HAL_OK; + } + else + { + hrng->ErrorCode |= HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Return the function status */ + return status; +} + +/** + * @brief RNG current configuration lock. + * @note This function allows to lock RNG peripheral configuration. + * Once locked, HW RNG reset has to be performed prior any further + * configuration update. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) +{ + HAL_StatusTypeDef status; + + /* Check the RNG handle allocation */ + if (hrng == NULL) + { + return HAL_ERROR; + } + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* Perform RNG configuration Lock */ + MODIFY_REG(hrng->Instance->CR, RNG_CR_CONFIGLOCK, RNG_CR_CONFIGLOCK); + + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_READY; + + /* function status */ + status = HAL_OK; + } + else + { + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Return the function status */ + return status; +} + + +/** + * @} + */ + +/** @defgroup RNGEx_Exported_Functions_Group2 Recover from seed error function + * @brief Recover from seed error function + * +@verbatim + =============================================================================== + ##### Recover from seed error function ##### + =============================================================================== + [..] This section provide function allowing to: + (+) Recover from a seed error + +@endverbatim + * @{ + */ + +/** + * @brief RNG sequence to recover from a seed error + * @param hrng: pointer to a RNG_HandleTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) +{ + HAL_StatusTypeDef status; + + /* Check the RNG handle allocation */ + if (hrng == NULL) + { + return HAL_ERROR; + } + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* sequence to fully recover from a seed error */ + status = RNG_RecoverSeedError(hrng); + if (status == HAL_ERROR) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; + } + } + else + { + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Return the function status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RNG_CR_CONDRST */ +#endif /* HAL_RNG_MODULE_ENABLED */ +/** + * @} + */ + +#endif /* RNG */ + +/** + * @} + */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c new file mode 100644 index 000000000..69e27c0c3 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c @@ -0,0 +1,4054 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_spi.c + * @author MCD Application Team + * @brief SPI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Serial Peripheral Interface (SPI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI HAL driver can be used as follows: + + (#) Declare a SPI_HandleTypeDef handle structure, for example: + SPI_HandleTypeDef hspi; + + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as alternate function push-pull + (##) NVIC configuration if you need to use interrupt process or DMA process + (+++) Configure the SPIx interrupt priority + (+++) Enable the NVIC SPI IRQ handle + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel + (+++) Enable the DMAx clock + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx Stream/Channel + (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx + or Rx Stream/Channel + + (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_SPI_MspInit() API. + [..] + Callback registration: + + (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1UL + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. + + Function HAL_SPI_RegisterCallback() allows to register following callbacks: + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) SuspendCallback : SPI Suspend callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + + (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default + weak function. + HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) SuspendCallback : SPI Suspend callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback + + By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() + or HAL_SPI_Init() function. + + When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or not defined, + the callback registering feature is not available and weak callbacks are used. + + SuspendCallback restriction: + SuspendCallback is called only when MasterReceiverAutoSusp is enabled and + EOT interrupt is activated. SuspendCallback is used in relation with functions + HAL_SPI_Transmit_IT, HAL_SPI_Receive_IT and HAL_SPI_TransmitReceive_IT. + + [..] + Circular mode restriction: + (+) The DMA circular mode cannot be used when the SPI is configured in these modes: + (++) Master 2Lines RxOnly + (++) Master 1Line Rx + (+) The CRC feature is not managed when the DMA circular mode is enabled + (+) The functions HAL_SPI_DMAPause()/ HAL_SPI_DMAResume() are not supported. Return always + HAL_ERROR with ErrorCode set to HAL_SPI_ERROR_NOT_SUPPORTED. + Those functions are maintained for backward compatibility reasons. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI HAL module driver + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_DEFAULT_TIMEOUT 100UL +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAError(DMA_HandleTypeDef *hdma); +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef *hspi, uint32_t Flag, + FlagStatus FlagStatus, uint32_t Timeout, uint32_t Tickstart); +static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi); +static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi); +static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi); +static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi); +static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi); +static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi); +static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi); +static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi); + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the SPIx peripheral: + + (+) User must implement HAL_SPI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_SPI_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + (++) CRC Length, used only with Data8 and Data16 + (++) FIFO reception threshold + (++) FIFO transmission threshold + + (+) Call the function HAL_SPI_DeInit() to restore the default configuration + of the selected SPIx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the SPI according to the specified parameters + * in the SPI_InitTypeDef and initialize the associated handle. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + uint32_t crc_length; + uint32_t packet_length; +#if (USE_SPI_CRC != 0UL) + uint32_t crc_poly_msb_mask; +#endif /* USE_SPI_CRC */ + + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_LIMITED_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); + } + else + { + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); + } + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + } +#if (USE_SPI_CRC != 0UL) + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_CRC_LENGTH(hspi->Init.CRCLength)); + } + else + { + assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); + } + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.TxCRCInitializationPattern)); + assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.RxCRCInitializationPattern)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; +#endif /* USE_SPI_CRC */ + + assert_param(IS_SPI_RDY_MASTER_MANAGEMENT(hspi->Init.ReadyMasterManagement)); + assert_param(IS_SPI_RDY_POLARITY(hspi->Init.ReadyPolarity)); + assert_param(IS_SPI_MASTER_RX_AUTOSUSP(hspi->Init.MasterReceiverAutoSusp)); + + /* Verify that the SPI instance supports Data Size higher than 16bits */ + if ((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (hspi->Init.DataSize > SPI_DATASIZE_16BIT)) + { + return HAL_ERROR; + } + + /* Verify that the SPI instance supports requested data packing */ + packet_length = SPI_GetPacketSize(hspi); + if (((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (packet_length > SPI_LOWEND_FIFO_SIZE)) || + ((IS_SPI_FULL_INSTANCE(hspi->Instance)) && (packet_length > SPI_HIGHEND_FIFO_SIZE))) + { + return HAL_ERROR; + } +#if (USE_SPI_CRC != 0UL) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Verify that the SPI instance supports CRC Length higher than 16bits */ + if ((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (hspi->Init.CRCLength > SPI_CRC_LENGTH_16BIT)) + { + return HAL_ERROR; + } + + /* Align the CRC Length on the data size */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) + { + crc_length = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) << SPI_CFG1_CRCSIZE_Pos; + } + else + { + crc_length = hspi->Init.CRCLength; + } + + /* Verify the correctness of polynom size */ + assert_param(IS_SPI_CRC_POLYNOMIAL_SIZE(hspi->Init.CRCPolynomial, crc_length)); + + /* Verify that the CRC Length is higher than DataSize */ + if ((hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) > (crc_length >> SPI_CFG1_CRCSIZE_Pos)) + { + return HAL_ERROR; + } + } + else + { + crc_length = hspi->Init.DataSize << SPI_CFG1_CRCSIZE_Pos; + } +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + /* Init the SPI Callback settings */ + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hspi->SuspendCallback = HAL_SPI_SuspendCallback; /* Legacy weak SuspendCallback */ + + if (hspi->MspInitCallback == NULL) + { + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + +#if (USE_SPI_CRC == 0) + /* Keep the default value of CRCSIZE in case of CRC is not used */ + crc_length = hspi->Instance->CFG1 & SPI_CFG1_CRCSIZE; +#endif /* USE_SPI_CRC */ + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, + Communication speed, First bit, CRC calculation state, CRC Length */ + + /* SPIx NSS Software Management Configuration */ + if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) && \ + (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) || \ + ((hspi->Init.Mode == SPI_MODE_SLAVE) && \ + (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_HIGH)))) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI); + } + + /* SPIx Master Rx Auto Suspend Configuration */ + if (((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER) && (hspi->Init.DataSize >= SPI_DATASIZE_8BIT)) + { + MODIFY_REG(hspi->Instance->CR1, SPI_CR1_MASRX, hspi->Init.MasterReceiverAutoSusp); + } + else + { + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_MASRX); + } + + /* SPIx CFG1 Configuration */ + WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_length | + hspi->Init.FifoThreshold | hspi->Init.DataSize)); + + /* SPIx CFG2 Configuration */ + WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode | hspi->Init.TIMode | + hspi->Init.NSSPolarity | hspi->Init.NSS | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | + hspi->Init.FirstBit | hspi->Init.Mode | + hspi->Init.MasterInterDataIdleness | hspi->Init.Direction | + hspi->Init.MasterSSIdleness | hspi->Init.IOSwap | + hspi->Init.ReadyMasterManagement | hspi->Init.ReadyPolarity)); + +#if (USE_SPI_CRC != 0UL) + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + /* Configure : CRC Polynomial */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Initialize TXCRC Pattern Initial Value */ + if (hspi->Init.TxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI); + } + else + { + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI); + } + + /* Initialize RXCRC Pattern Initial Value */ + if (hspi->Init.RxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI); + } + else + { + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI); + } + + /* Enable 33/17 bits CRC computation */ + if (((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_16BIT)) || + ((IS_SPI_FULL_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_32BIT))) + { + /* Set SPI_CR1_CRC33_17 bit */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17); + /* Write CRC polynomial in SPI Register */ + WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial); + } + else + { + /* Clear SPI_CR1_CRC33_17 bit */ + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17); + + /* Write CRC polynomial and set MSB bit at 1 in SPI Register */ + /* Set MSB is mandatory for a correct CRC computation */ + crc_poly_msb_mask = (0x1UL << ((crc_length >> SPI_CFG1_CRCSIZE_Pos) + 0x1U)); + WRITE_REG(hspi->Instance->CRCPOLY, (hspi->Init.CRCPolynomial) | crc_poly_msb_mask); + } + } +#endif /* USE_SPI_CRC */ + + /* Insure that Underrun configuration is managed only by Salve */ + if (hspi->Init.Mode == SPI_MODE_SLAVE) + { +#if (USE_SPI_CRC != 0UL) + MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG); +#endif /* USE_SPI_CRC */ + } + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif /* SPI_I2SCFGR_I2SMOD */ + + /* Insure that AFCNTR is managed only by Master */ + if ((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER) + { + /* Alternate function GPIOs control */ + MODIFY_REG(hspi->Instance->CFG2, SPI_CFG2_AFCNTR, (hspi->Init.MasterKeepIOState)); + } + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-Initialize the SPI peripheral. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check SPI Instance parameter */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the SPI Peripheral Clock */ + __HAL_SPI_DISABLE(hspi); + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + if (hspi->MspDeInitCallback == NULL) + { + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + hspi->MspDeInitCallback(hspi); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPI_MspDeInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Initialize the SPI MSP. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspInit should be implemented in the user file + */ +} + +/** + * @brief De-Initialize the SPI MSP. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspDeInit should be implemented in the user file + */ +} + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) +/** + * @brief Register a User SPI Callback + * To be used instead of the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be registered + * @param pCallback pointer to the Callback function + * @note The HAL_SPI_RegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET + * to register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = pCallback; + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = pCallback; + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = pCallback; + break; + + case HAL_SPI_SUSPEND_CB_ID : + hspi->SuspendCallback = pCallback; + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an SPI Callback + * SPI callback is redirected to the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be unregistered + * @note The HAL_SPI_UnRegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET + * to un-register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_SPI_SUSPEND_CB_ID : + hspi->SuspendCallback = HAL_SPI_SuspendCallback; /* Legacy weak SuspendCallback */ + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master and slave mode : + + (#) There are two modes of transfer: + (##) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (##) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData : pointer to data buffer + * @param Size : amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ +#if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); +#endif /* __GNUC__ */ + + uint32_t tickstart; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = (uint16_t) 0UL; + hspi->RxXferCount = (uint16_t) 0UL; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + else + { + SPI_2LINES_TX(hspi); + } + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Transmit data in 32 Bit mode */ + if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) + { + /* Transmit data in 32 Bit mode */ + while (hspi->TxXferCount > 0UL) + { + /* Wait until TXP flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + /* Transmit data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0UL) + { + /* Wait until TXP flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) + { + if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount -= (uint16_t)2UL; + } + else + { +#if defined (__GNUC__) + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + /* Transmit data in 8 Bit mode */ + else + { + while (hspi->TxXferCount > 0UL) + { + /* Wait until TXP flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) + { + if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount -= (uint16_t)4UL; + } + else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) + { +#if defined (__GNUC__) + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= (uint16_t)2UL; + } + else + { + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + } + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + + /* Wait for Tx (and CRC) data to be sent */ + if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData : pointer to data buffer + * @param Size : amount of data to be received + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t temp_sr_reg; + uint16_t init_max_data_in_fifo; + init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); +#if defined (__GNUC__) + __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); +#endif /* __GNUC__ */ + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = (uint16_t) 0UL; + hspi->TxXferCount = (uint16_t) 0UL; + hspi->RxISR = NULL; + hspi->TxISR = NULL; + + /* Configure communication direction: 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else + { + SPI_2LINES_RX(hspi); + } + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Receive data in 32 Bit mode */ + if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) + { + /* Transfer loop */ + while (hspi->RxXferCount > 0UL) + { + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + } + /* Check if transfer is locked because of a suspend */ + else if (HAL_IS_BIT_SET(temp_sr_reg, SPI_SR_SUSP)) + { + /* Verify suspend is triggered by hardware and not software */ + if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) + { + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + } + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + /* Receive data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Transfer loop */ + while (hspi->RxXferCount > 0UL) + { + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= (uint16_t)2UL; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((hspi->RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + } + /* Check if transfer is locked because of a suspend */ + else if (HAL_IS_BIT_SET(temp_sr_reg, SPI_SR_SUSP)) + { + /* Verify suspend is triggered by hardware and not software */ + if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) + { + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + } + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + /* Receive data in 8 Bit mode */ + else + { + /* Transfer loop */ + while (hspi->RxXferCount > 0UL) + { + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount -= (uint16_t)4UL; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((hspi->RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + } + /* Check if transfer is locked because of a suspend */ + else if (HAL_IS_BIT_SET(temp_sr_reg, SPI_SR_SUSP)) + { + /* Verify suspend is triggered by hardware and not software */ + if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) + { + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + } + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + +#if (USE_SPI_CRC != 0UL) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait for crc data to be received */ + if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + } +#endif /* USE_SPI_CRC */ + + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Transmit and Receive an amount of data in blocking mode. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @param Size : amount of data to be sent and received + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) +{ +#if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); + __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); +#endif /* __GNUC__ */ + + uint32_t tickstart; + uint32_t fifo_length; + uint32_t temp_sr_reg; + uint16_t initial_TxXferCount; + uint16_t initial_RxXferCount; + uint16_t init_max_data_in_fifo; + init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + initial_TxXferCount = Size; + initial_RxXferCount = Size; + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferCount = Size; + hspi->RxXferSize = Size; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferCount = Size; + hspi->TxXferSize = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + + /* Initialize FIFO length */ + if (IS_SPI_FULL_INSTANCE(hspi->Instance)) + { + fifo_length = SPI_HIGHEND_FIFO_SIZE; + } + else + { + fifo_length = SPI_LOWEND_FIFO_SIZE; + } + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + __HAL_SPI_ENABLE(hspi); + + if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Transmit and Receive data in 32 Bit mode */ + if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) + { + /* Adapt fifo length to 32bits data width */ + fifo_length = (fifo_length / 4UL); + + while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) + { + /* Check TXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && + (initial_RxXferCount < (initial_TxXferCount + fifo_length))) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount --; + initial_TxXferCount = hspi->TxXferCount; + } + + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + if (initial_RxXferCount > 0UL) + { + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + } + /* Transmit and Receive data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Adapt fifo length to 16bits data width */ + fifo_length = (fifo_length / 2UL); + + while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) + { + /* Check the TXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && + (initial_RxXferCount < (initial_TxXferCount + fifo_length))) + { +#if defined (__GNUC__) + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + initial_TxXferCount = hspi->TxXferCount; + } + + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + if (initial_RxXferCount > 0UL) + { + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= (uint16_t)2UL; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((initial_RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) + { + /* Check the TXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && + (initial_RxXferCount < (initial_TxXferCount + fifo_length))) + { + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + initial_TxXferCount = hspi->TxXferCount; + } + + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + if (initial_RxXferCount > 0UL) + { + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount -= (uint16_t)4UL; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((initial_RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + } + + /* Wait for Tx/Rx (and CRC) data to be sent/received */ + if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size : amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) +{ + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = (uint16_t) 0UL; + hspi->RxXferCount = (uint16_t) 0UL; + hspi->RxISR = NULL; + + /* Set the function for IT treatment */ + if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) + { + hspi->TxISR = SPI_TxISR_32BIT; + } + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->TxISR = SPI_TxISR_16BIT; + } + else + { + hspi->TxISR = SPI_TxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + else + { + SPI_2LINES_TX(hspi); + } + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + /* Enable EOT, TXP, FRE, MODF and UDR interrupts */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF)); + + if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size : amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = (uint16_t) 0UL; + hspi->TxXferCount = (uint16_t) 0UL; + hspi->TxISR = NULL; + + /* Set the function for IT treatment */ + if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) + { + hspi->RxISR = SPI_RxISR_32BIT; + } + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->RxISR = SPI_RxISR_16BIT; + } + else + { + hspi->RxISR = SPI_RxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else + { + SPI_2LINES_RX(hspi); + } + + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + /* Enable EOT, RXP, OVR, FRE and MODF interrupts */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); + + if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + return HAL_OK; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @param Size : amount of data to be sent and received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + uint32_t tmp_TxXferCount; +#if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); +#endif /* __GNUC__ */ + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + tmp_TxXferCount = hspi->TxXferCount; + + /* Set the function for IT treatment */ + if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) + { + hspi->TxISR = SPI_TxISR_32BIT; + hspi->RxISR = SPI_RxISR_32BIT; + } + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->RxISR = SPI_RxISR_16BIT; + hspi->TxISR = SPI_TxISR_16BIT; + } + else + { + hspi->RxISR = SPI_RxISR_8BIT; + hspi->TxISR = SPI_TxISR_8BIT; + } + + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + /* Fill in the TxFIFO */ + while ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (tmp_TxXferCount != 0UL)) + { + /* Transmit data in 32 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; + } + /* Transmit data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { +#if defined (__GNUC__) + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; + } + /* Transmit data in 8 Bit mode */ + else + { + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; + } + } + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + /* Enable EOT, DXP, UDR, OVR, FRE and MODF interrupts */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); + + if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Start Master transfer */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + return HAL_OK; +} + + + + +/** + * @brief Transmit an amount of data in non-blocking mode with DMA. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size : amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = NULL; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + hspi->RxXferSize = (uint16_t)0UL; + hspi->RxXferCount = (uint16_t)0UL; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + else + { + SPI_2LINES_TX(hspi); + } + + /* Packing mode management is enabled by the DMA settings */ + if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmatx->Init.SrcDataWidth != DMA_SRC_DATAWIDTH_WORD) && \ + (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \ + ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE))) + { + /* Restriction the DMA data received is not allowed in this mode */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Adjust XferCount according to DMA alignment / Data size */ + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL; + } + if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL; + } + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL; + } + } + else + { + /* Adjustment done */ + } + + /* Set the SPI TxDMA Half transfer complete callback */ + hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; + + /* Set the SPI TxDMA transfer complete callback */ + hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmatx->XferAbortCallback = NULL; + + /* Clear TXDMAEN bit*/ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); + + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + hspi->TxXferCount = Size; + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + hspi->TxXferCount = Size * 2U; + } + else + { + hspi->TxXferCount = Size * 4U; + } + + /* Enable the Tx DMA Stream/Channel */ + if ((hspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hspi->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->TxXferCount; + + /* Set DMA source address */ + hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hspi->pTxBuffPtr; + + /* Set DMA destination address */ + hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->TXDR; + + status = HAL_DMAEx_List_Start_IT(hspi->hdmatx); + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, + hspi->TxXferCount); + } + + /* Check status */ + if (status != HAL_OK) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + + /* Set the number of data at current transfer */ + if (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR) + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL); + } + else + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + } + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF)); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size : amount of data to be sent + * @note When the CRC feature is enabled the pData Length must be Size + 1. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + + if (hspi->State != HAL_SPI_STATE_READY) + { + __HAL_UNLOCK(hspi); + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0UL)) + { + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + hspi->TxXferSize = (uint16_t) 0UL; + hspi->TxXferCount = (uint16_t) 0UL; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else + { + SPI_2LINES_RX(hspi); + } + + /* Packing mode management is enabled by the DMA settings */ + if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) && \ + (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \ + ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE))) + { + /* Restriction the DMA data received is not allowed in this mode */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Clear RXDMAEN bit */ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); + + /* Adjust XferCount according to DMA alignment / Data size */ + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_HALFWORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL; + } + if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL; + } + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL; + } + } + else + { + /* Adjustment done */ + } + + /* Set the SPI RxDMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + /* Set the SPI Rx DMA transfer complete callback */ + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + hspi->RxXferCount = Size; + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + hspi->RxXferCount = Size * 2U; + } + else + { + hspi->RxXferCount = Size * 4U; + } + + /* Enable the Rx DMA Stream/Channel */ + if ((hspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hspi->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->RxXferCount; + + /* Set DMA source address */ + hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->RXDR; + + /* Set DMA destination address */ + hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hspi->pRxBuffPtr; + + status = HAL_DMAEx_List_Start_IT(hspi->hdmarx); + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount); + } + + /* Check status */ + if (status != HAL_OK) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + + /* Set the number of data at current transfer */ + if (hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL); + } + else + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + } + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @param Size : amount of data to be sent + * @note When the CRC feature is enabled the pRxData Length must be Size + 1 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + + /* Reset the Tx/Rx DMA bits */ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); + + /* Packing mode management is enabled by the DMA settings */ + if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && \ + ((hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) || \ + (hspi->hdmatx->Init.SrcDataWidth != DMA_SRC_DATAWIDTH_WORD)) && \ + (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \ + ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && \ + ((hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE) || \ + (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE)))) + { + /* Restriction the DMA data received is not allowed in this mode */ + /* Unlock the process */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Adjust XferCount according to DMA alignment / Data size */ + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL; + } + if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL; + } + if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_HALFWORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL; + } + if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL; + } + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL; + } + if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL; + } + } + else + { + /* Adjustment done */ + } + + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + hspi->RxXferCount = Size; + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + hspi->RxXferCount = Size * 2U; + } + else + { + hspi->RxXferCount = Size * 4U; + } + /* Enable the Rx DMA Stream/Channel */ + if ((hspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hspi->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->RxXferCount; + + /* Set DMA source address */ + hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->RXDR; + + /* Set DMA destination address */ + hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hspi->pRxBuffPtr; + + status = HAL_DMAEx_List_Start_IT(hspi->hdmarx); + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount); + } + + /* Check status */ + if (status != HAL_OK) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); + + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + hspi->hdmatx->XferHalfCpltCallback = NULL; + hspi->hdmatx->XferCpltCallback = NULL; + hspi->hdmatx->XferAbortCallback = NULL; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + hspi->TxXferCount = Size; + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + hspi->TxXferCount = Size * 2U; + } + else + { + hspi->TxXferCount = Size * 4U; + } + + /* Enable the Tx DMA Stream/Channel */ + if ((hspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hspi->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->TxXferCount; + + /* Set DMA source address */ + hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hspi->pTxBuffPtr; + + /* Set DMA destination address */ + hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->TXDR; + + status = HAL_DMAEx_List_Start_IT(hspi->hdmatx); + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, + hspi->TxXferCount); + } + + /* Check status */ + if (status != HAL_OK) + { + /* Abort Rx DMA Channel already started */ + (void)HAL_DMA_Abort(hspi->hdmarx); + + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + + if ((hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) && (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR)) + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL); + } + else + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + } + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF)); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfer (blocking mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * @note This procedure performs following operations : + * + Disable SPI Interrupts (depending of transfer direction) + * + Disable the DMA transfer in the peripheral register (if enabled) + * + Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * + Set handle State to READY. + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + + __IO uint32_t count; + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set hspi->state to aborting to avoid any interaction */ + hspi->State = HAL_SPI_STATE_ABORT; + + /* Initialized local variable */ + errorcode = HAL_OK; + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL); + + /* If master communication on going, make sure current frame is done before closing the connection */ + if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) + { + /* Disable EOT interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); + + /* Request a Suspend transfer */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + + /* Clear SUSP flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); + } + + /* Disable the SPI DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN)) + { + if (hspi->hdmatx != NULL) + { + /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ + hspi->hdmatx->XferAbortCallback = NULL; + + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } + } + } + + /* Disable the SPI DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)) + { + if (hspi->hdmarx != NULL) + { + /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } + } + } + + /* Proceed with abort procedure */ + SPI_AbortTransfer(hspi); + + /* Check error during Abort procedure */ + if (HAL_IS_BIT_SET(hspi->ErrorCode, HAL_SPI_ERROR_ABORT)) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Restore hspi->state to ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return errorcode; +} + +/** + * @brief Abort ongoing transfer (Interrupt mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * @note This procedure performs following operations : + * + Disable SPI Interrupts (depending of transfer direction) + * + Disable the DMA transfer in the peripheral register (if enabled) + * + Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * + Set handle State to READY + * + At abort completion, call user abort complete callback. + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + __IO uint32_t count; + uint32_t dma_tx_abort_done = 1UL; + uint32_t dma_rx_abort_done = 1UL; + + /* Set hspi->state to aborting to avoid any interaction */ + hspi->State = HAL_SPI_STATE_ABORT; + + /* Initialized local variable */ + errorcode = HAL_OK; + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL); + + /* If master communication on going, make sure current frame is done before closing the connection */ + if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) + { + /* Disable EOT interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); + + /* Request a Suspend transfer */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + + /* Clear SUSP flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); + } + + /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized + before any call to DMA Abort functions */ + + if (hspi->hdmarx != NULL) + { + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)) + { + /* Set DMA Abort Complete callback if SPI DMA Rx request if enabled */ + hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; + } + } + + if (hspi->hdmatx != NULL) + { + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN)) + { + /* Set DMA Abort Complete callback if SPI DMA Tx request if enabled */ + hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback; + + dma_tx_abort_done = 0UL; + + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_NO_XFER) + { + dma_tx_abort_done = 1UL; + hspi->hdmatx->XferAbortCallback = NULL; + } + } + } + else + { + hspi->hdmatx->XferAbortCallback = NULL; + } + } + + if (hspi->hdmarx != NULL) + { + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)) + { + /* Set DMA Abort Complete callback if SPI DMA Rx request if enabled */ + hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; + + dma_rx_abort_done = 0UL; + + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_NO_XFER) + { + dma_rx_abort_done = 1UL; + hspi->hdmarx->XferAbortCallback = NULL; + } + } + } + else + { + hspi->hdmarx->XferAbortCallback = NULL; + } + } + + /* If no running DMA transfer, finish cleanup and call callbacks */ + if ((dma_tx_abort_done == 1UL) && (dma_rx_abort_done == 1UL)) + { + /* Proceed with abort procedure */ + SPI_AbortTransfer(hspi); + + /* Check error during Abort procedure */ + if (HAL_IS_BIT_SET(hspi->ErrorCode, HAL_SPI_ERROR_ABORT)) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Restore hspi->state to ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + return errorcode; +} + +/** + * @brief Pause the DMA Transfer. + * This API is not supported, it is maintained for backward compatibility. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL_ERROR + */ +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +{ + /* Set error code to not supported */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED); + + return HAL_ERROR; +} + +/** + * @brief Resume the DMA Transfer. + * This API is not supported, it is maintained for backward compatibility. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL_ERROR + */ +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +{ + /* Set error code to not supported */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED); + + return HAL_ERROR; +} + +/** + * @brief Stop the DMA Transfer. + * This API is not supported, it is maintained for backward compatibility. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL_ERROR + */ +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +{ + /* Set error code to not supported */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED); + + return HAL_ERROR; +} + +/** + * @brief Handle SPI interrupt request. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval None + */ +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +{ + uint32_t itsource = hspi->Instance->IER; + uint32_t itflag = hspi->Instance->SR; + uint32_t trigger = itsource & itflag; + uint32_t cfg1 = hspi->Instance->CFG1; + uint32_t handled = 0UL; + + HAL_SPI_StateTypeDef State = hspi->State; +#if defined (__GNUC__) + __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); +#endif /* __GNUC__ */ + + /* SPI in SUSPEND mode ----------------------------------------------------*/ + if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT)) + { + /* Clear the Suspend flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + + /* Suspend on going, Call the Suspend callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->SuspendCallback(hspi); +#else + HAL_SPI_SuspendCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + + /* SPI in mode Transmitter and Receiver ------------------------------------*/ + if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && \ + HAL_IS_BIT_SET(trigger, SPI_FLAG_DXP)) + { + hspi->TxISR(hspi); + hspi->RxISR(hspi); + handled = 1UL; + } + + /* SPI in mode Receiver ----------------------------------------------------*/ + if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_RXP) && \ + HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP)) + { + hspi->RxISR(hspi); + handled = 1UL; + } + + /* SPI in mode Transmitter -------------------------------------------------*/ + if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_TXP) && \ + HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP)) + { + hspi->TxISR(hspi); + handled = 1UL; + } + + if (handled != 0UL) + { + return; + } + + /* SPI End Of Transfer: DMA or IT based transfer */ + if (HAL_IS_BIT_SET(trigger, SPI_FLAG_EOT)) + { + /* Clear EOT/TXTF/SUSP flag */ + __HAL_SPI_CLEAR_EOTFLAG(hspi); + __HAL_SPI_CLEAR_TXTFFLAG(hspi); + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + + /* Disable EOT interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); + + /* For the IT based receive extra polling maybe required for last packet */ + if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN)) + { + /* Pooling remaining data */ + while (hspi->RxXferCount != 0UL) + { + /* Receive data in 32 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + } + /* Receive data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + } + /* Receive data in 8 Bit mode */ + else + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + } + + hspi->RxXferCount--; + } + } + + /* Call SPI Standard close procedure */ + SPI_CloseTransfer(hspi); + + hspi->State = HAL_SPI_STATE_READY; + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + /* Call appropriate user callback */ + if (State == HAL_SPI_STATE_BUSY_TX_RX) + { + hspi->TxRxCpltCallback(hspi); + } + else if (State == HAL_SPI_STATE_BUSY_RX) + { + hspi->RxCpltCallback(hspi); + } + else if (State == HAL_SPI_STATE_BUSY_TX) + { + hspi->TxCpltCallback(hspi); + } +#else + /* Call appropriate user callback */ + if (State == HAL_SPI_STATE_BUSY_TX_RX) + { + HAL_SPI_TxRxCpltCallback(hspi); + } + else if (State == HAL_SPI_STATE_BUSY_RX) + { + HAL_SPI_RxCpltCallback(hspi); + } + else if (State == HAL_SPI_STATE_BUSY_TX) + { + HAL_SPI_TxCpltCallback(hspi); + } +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + else + { + /* End of the appropriate call */ + } + + return; + } + + /* SPI in Error Treatment --------------------------------------------------*/ + if ((trigger & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE | SPI_FLAG_UDR)) != 0UL) + { + /* SPI Overrun error interrupt occurred ----------------------------------*/ + if ((trigger & SPI_FLAG_OVR) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + /* SPI Mode Fault error interrupt occurred -------------------------------*/ + if ((trigger & SPI_FLAG_MODF) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Frame error interrupt occurred ------------------------------------*/ + if ((trigger & SPI_FLAG_FRE) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); + __HAL_SPI_CLEAR_FREFLAG(hspi); + } + + /* SPI Underrun error interrupt occurred ------------------------------------*/ + if ((trigger & SPI_FLAG_UDR) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR); + __HAL_SPI_CLEAR_UDRFLAG(hspi); + } + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable all interrupts */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_MODF | + SPI_IT_OVR | SPI_IT_FRE | SPI_IT_UDR)); + + /* Disable the SPI DMA requests if enabled */ + if (HAL_IS_BIT_SET(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN)) + { + /* Disable the SPI DMA requests */ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); + + /* Abort the SPI DMA Rx channel */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + /* Abort the SPI DMA Tx channel */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + } + else + { + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + } + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxHalfCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Half Transfer callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief SPI error callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_ErrorCallback should be implemented in the user file + */ + /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes + and user can use HAL_SPI_GetError() API to check the latest error occurred + */ +} + +/** + * @brief SPI Abort Complete callback. + * @param hspi SPI handle. + * @retval None + */ +__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief SPI Suspend callback. + * @param hspi SPI handle. + * @retval None + */ +__weak void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_SuspendCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SPI control functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral + (+) HAL_SPI_GetError() check in run-time Errors occurring during communication +@endverbatim + * @{ + */ + +/** + * @brief Return the SPI handle state. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI state + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) +{ + /* Return SPI handle state */ + return hspi->State; +} + +/** + * @brief Return the SPI error code. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI error code in bitmap format + */ +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) +{ + /* Return SPI ErrorCode */ + return hspi->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @brief Private functions + * @{ + */ + +/** + * @brief DMA SPI transmit process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hspi->State != HAL_SPI_STATE_ABORT) + { + if (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR) + { +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->TxCpltCallback(hspi); +#else + HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Enable EOT interrupt */ + __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT); + } + } +} + +/** + * @brief DMA SPI receive process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hspi->State != HAL_SPI_STATE_ABORT) + { + if (hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) + { +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Enable EOT interrupt */ + __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT); + } + } +} + +/** + * @brief DMA SPI transmit receive process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hspi->State != HAL_SPI_STATE_ABORT) + { + if ((hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) && + (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR)) + { +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->TxRxCpltCallback(hspi); +#else + HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Enable EOT interrupt */ + __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT); + } + } +} + +/** + * @brief DMA SPI half transmit process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) + ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->TxHalfCpltCallback(hspi); +#else + HAL_SPI_TxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) + ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->RxHalfCpltCallback(hspi); +#else + HAL_SPI_RxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half transmit receive process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) + ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->TxRxHalfCpltCallback(hspi); +#else + HAL_SPI_TxRxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI communication error callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* if DMA error is FIFO error ignore it */ + if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_NONE) + { + /* Call SPI standard close procedure */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA SPI communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + hspi->RxXferCount = (uint16_t) 0UL; + hspi->TxXferCount = (uint16_t) 0UL; + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hspi->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmarx != NULL) + { + if (hspi->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* Call the Abort procedure */ + SPI_AbortTransfer(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hspi->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmatx != NULL) + { + if (hspi->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* Call the Abort procedure */ + SPI_AbortTransfer(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief Manage the receive 8-bit in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi) +{ + /* Receive data in 8 Bit mode */ + *((uint8_t *)hspi->pRxBuffPtr) = (*(__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->RxXferCount == 0UL) + { + /* Disable RXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); + } +} + + +/** + * @brief Manage the 16-bit receive in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi) +{ + /* Receive data in 16 Bit mode */ +#if defined (__GNUC__) + __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); + + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = (*(__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->RxXferCount == 0UL) + { + /* Disable RXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); + } +} + + +/** + * @brief Manage the 32-bit receive in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi) +{ + /* Receive data in 32 Bit mode */ + *((uint32_t *)hspi->pRxBuffPtr) = (*(__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->RxXferCount == 0UL) + { + /* Disable RXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); + } +} + + +/** + * @brief Handle the data 8-bit transmit in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 8 Bit mode */ + if (hspi->TxXferCount != 0UL) + { + *(__IO uint8_t *)&hspi->Instance->TXDR = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + } + else + { + /* Disable IT if no more data expected */ + /* Disable TXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); + } +} + +/** + * @brief Handle the data 16-bit transmit in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + if (hspi->TxXferCount != 0UL) + { +#if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); + + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + else + { + /* Disable IT if no more data expected */ + /* Disable TXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); + } +} + +/** + * @brief Handle the data 32-bit transmit in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 32 Bit mode */ + if (hspi->TxXferCount != 0UL) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount--; + } + else + { + /* Disable IT if no more data expected */ + /* Disable TXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); + } +} + +/** + * @brief Abort Transfer and clear flags. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi) +{ + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable ITs */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \ + SPI_IT_FRE | SPI_IT_MODF)); + + /* Clear the Status flags in the SR register */ + __HAL_SPI_CLEAR_EOTFLAG(hspi); + __HAL_SPI_CLEAR_TXTFFLAG(hspi); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_UDRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + +#if (USE_SPI_CRC != 0U) + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); +#endif /* USE_SPI_CRC */ + + hspi->TxXferCount = (uint16_t)0UL; + hspi->RxXferCount = (uint16_t)0UL; +} + + +/** + * @brief Close Transfer and clear flags. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL_ERROR: if any error detected + * HAL_OK: if nothing detected + */ +static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi) +{ + uint32_t itflag = hspi->Instance->SR; + + __HAL_SPI_CLEAR_EOTFLAG(hspi); + __HAL_SPI_CLEAR_TXTFFLAG(hspi); + + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable ITs */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \ + SPI_IT_FRE | SPI_IT_MODF)); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); + + /* Report UnderRun error for non RX Only communication */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + if ((itflag & SPI_FLAG_UDR) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR); + __HAL_SPI_CLEAR_UDRFLAG(hspi); + } + } + + /* Report OverRun error for non TX Only communication */ + if (hspi->State != HAL_SPI_STATE_BUSY_TX) + { + if ((itflag & SPI_FLAG_OVR) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + +#if (USE_SPI_CRC != 0UL) + /* Check if CRC error occurred */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + if ((itflag & SPI_FLAG_CRCERR) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } +#endif /* USE_SPI_CRC */ + } + + /* SPI Mode Fault error interrupt occurred -------------------------------*/ + if ((itflag & SPI_FLAG_MODF) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Frame error interrupt occurred ------------------------------------*/ + if ((itflag & SPI_FLAG_FRE) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); + __HAL_SPI_CLEAR_FREFLAG(hspi); + } + + hspi->TxXferCount = (uint16_t)0UL; + hspi->RxXferCount = (uint16_t)0UL; +} + +/** + * @brief Handle SPI Communication Timeout. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Flag: SPI flag to check + * @param Status: flag state to check + * @param Timeout: Timeout duration + * @param Tickstart: Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) +{ + /* Wait until flag is set */ + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if ((((HAL_GetTick() - Tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Compute configured packet size from fifo perspective. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval Packet size occupied in the fifo + */ +static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi) +{ + uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL; + uint32_t data_size = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) + 1UL; + + /* Convert data size to Byte */ + data_size = (data_size + 7UL) / 8UL; + + return data_size * fifo_threashold; +} + +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c new file mode 100644 index 000000000..e26b02892 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c @@ -0,0 +1,345 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_spi_ex.c + * @author MCD Application Team + * @brief Extended SPI HAL module driver. + * This file provides firmware functions to manage the following + * SPI peripheral extended functionalities : + * + IO operation functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup SPIEx SPIEx + * @brief SPI Extended HAL module driver + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions + * @{ + */ + +/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of extended functions to manage the SPI + data transfers. + + (#) SPIEx function: + (++) HAL_SPIEx_FlushRxFifo() + (++) HAL_SPIEx_EnableLockConfiguration() + (++) HAL_SPIEx_ConfigureUnderrun() + +@endverbatim + * @{ + */ + +/** + * @brief Flush the RX fifo. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi) +{ + uint8_t count = 0; + uint32_t itflag = hspi->Instance->SR; + __IO uint32_t tmpreg; + + while (((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_RX_FIFO_0PACKET) || ((itflag & SPI_FLAG_RXWNE) != 0UL)) + { + count += (uint8_t)4UL; + tmpreg = hspi->Instance->RXDR; + UNUSED(tmpreg); /* To avoid GCC warning */ + + if (IS_SPI_FULL_INSTANCE(hspi->Instance)) + { + if (count > SPI_HIGHEND_FIFO_SIZE) + { + return HAL_TIMEOUT; + } + } + else + { + if (count > SPI_LOWEND_FIFO_SIZE) + { + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + + +/** + * @brief Enable the Lock for the AF configuration of associated IOs + * and write protect the Content of Configuration register 2 + * when SPI is enabled + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Check if the SPI is disabled to edit IOLOCK bit */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK); + } + else + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Configure the UNDERRUN condition and behavior of slave transmitter. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param UnderrunDetection : Detection of underrun condition at slave transmitter + * This parameter is not supported in this SPI version. + * It is kept in order to not break the compatibility. + * @param UnderrunBehaviour : Behavior of slave transmitter at underrun condition + * This parameter can be a value of @ref SPI_Underrun_Behaviour. + * @retval None + */ +HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, + uint32_t UnderrunBehaviour) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(UnderrunDetection); + + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Check State and Insure that Underrun configuration is managed only by Salve */ + if ((hspi->State != HAL_SPI_STATE_READY) || (hspi->Init.Mode != SPI_MODE_SLAVE)) + { + errorcode = HAL_BUSY; + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Check the parameters */ + assert_param(IS_SPI_UNDERRUN_BEHAVIOUR(UnderrunBehaviour)); + + /* Check if the SPI is disabled to edit CFG1 register */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Configure Underrun fields */ + MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour); + } + else + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Configure Underrun fields */ + MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Set Autonomous Mode configuration + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPIx peripheral. + * @param sConfig Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information of the autonomous mode for the specified SPIx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPIEx_SetConfigAutonomousMode(SPI_HandleTypeDef *hspi, + const SPI_AutonomousModeConfTypeDef *sConfig) +{ + if (hspi->State == HAL_SPI_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hspi); + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_SPI_AUTONOMOUS_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_TRIG_SOURCE(hspi->Instance, sConfig->TriggerSelection)); + assert_param(IS_SPI_AUTO_MODE_TRG_POL(sConfig->TriggerPolarity)); + + /* Disable the selected SPI peripheral to be able to configure AUTOCR */ + __HAL_SPI_DISABLE(hspi); + + /* SPIx AUTOCR Configuration */ + WRITE_REG(hspi->Instance->AUTOCR, (sConfig->TriggerState | ((sConfig->TriggerSelection) & SPI_AUTOCR_TRIGSEL_Msk) | + sConfig->TriggerPolarity)); + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Get Autonomous Mode configuration + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPIx peripheral. + * @param sConfig Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information of the autonomous mode for the specified SPIx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPIEx_GetConfigAutonomousMode(const SPI_HandleTypeDef *hspi, + SPI_AutonomousModeConfTypeDef *sConfig) +{ + uint32_t autocr_tmp; + + /* Check the parameters */ + assert_param(IS_SPI_AUTONOMOUS_INSTANCE(hspi->Instance)); + + autocr_tmp = hspi->Instance->AUTOCR; + + sConfig->TriggerState = (autocr_tmp & SPI_AUTOCR_TRIGEN); +#if defined(SPI_TRIG_GRP2) + if (IS_SPI_GRP2_INSTANCE(hspi->Instance)) + { + sConfig->TriggerSelection = ((autocr_tmp & SPI_AUTOCR_TRIGSEL) | SPI_TRIG_GRP2); + } + else + { + sConfig->TriggerSelection = ((autocr_tmp & SPI_AUTOCR_TRIGSEL) | SPI_TRIG_GRP1); + } +#else + sConfig->TriggerSelection = ((autocr_tmp & SPI_AUTOCR_TRIGSEL) | SPI_TRIG_GRP1); +#endif /* SPI_TRIG_GRP2 */ + sConfig->TriggerPolarity = (autocr_tmp & SPI_AUTOCR_TRIGPOL); + + return HAL_OK; +} + +/** + * @brief Clear Autonomous Mode configuration + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPIx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPIEx_ClearConfigAutonomousMode(SPI_HandleTypeDef *hspi) +{ + if (hspi->State == HAL_SPI_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hspi); + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_SPI_AUTONOMOUS_INSTANCE(hspi->Instance)); + + /* Disable the selected SPI peripheral to be able to clear AUTOCR */ + __HAL_SPI_DISABLE(hspi); + + CLEAR_REG(hspi->Instance->AUTOCR); + + /* Enable the selected SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c new file mode 100644 index 000000000..219acbf34 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c @@ -0,0 +1,4848 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_uart.c + * @author MCD Application Team + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The UART HAL driver can be used as follows: + + (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + (++) Enable the USARTx interface clock. + (++) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure these UART pins as alternate function pull-up. + (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + and HAL_UART_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (++) UART interrupts handling: + -@@- The specific UART interrupts (Transmission complete interrupt, + RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts) + are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() + inside the transmit and receive processes. + (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + and HAL_UART_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware + flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. + + (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) + in the huart handle AdvancedInit structure. + + (#) For the UART asynchronous mode, initialize the UART registers by calling + the HAL_UART_Init() API. + + (#) For the UART Half duplex mode, initialize the UART registers by calling + the HAL_HalfDuplex_Init() API. + + (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers + by calling the HAL_LIN_Init() API. + + (#) For the UART Multiprocessor mode, initialize the UART registers + by calling the HAL_MultiProcessor_Init() API. + + (#) For the UART RS485 Driver Enabled mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + [..] + (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), + also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by + calling the customized HAL_UART_MspInit() API. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_UART_RegisterCallback() to register a user callback. + Function HAL_UART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_UART_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + + [..] + For specific callback RxEventCallback, use dedicated registration/reset functions: + respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback(). + + [..] + By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak functions in the HAL_UART_Init() + and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() + or HAL_UART_Init() function. + + [..] + When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak callbacks are used. + + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief HAL UART module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \ + USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ + +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \ + USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ + +#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ +#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ + +#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ +#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions + * @{ + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +#if defined(HAL_DMA_MODULE_ENABLED) +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup UART_Private_variables + * @{ + */ +const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; +/** + * @} + */ + +/* Exported Constants --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API + follow respectively the UART asynchronous, UART Half duplex, UART LIN mode + and UART multiprocessor mode configuration procedures (details for the procedures + are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the UART mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + { + /* Check the parameters */ + assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + } + else + { + /* Check the parameters */ + assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Initialize the half-duplex mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check UART instance */ + assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In half-duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the LIN mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param BreakDetectLength Specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection + * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the LIN UART instance */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + /* Check the Break detection length parameter */ + assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + + /* LIN mode limited to 16-bit oversampling only */ + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + return HAL_ERROR; + } + /* LIN mode limited to 8-bit data length */ + if (huart->Init.WordLength != UART_WORDLENGTH_8B) + { + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In LIN mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + + /* Set the USART LIN Break detection length. */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the multiprocessor mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @param Address UART node address (4-, 6-, 7- or 8-bit long). + * @param WakeUpMethod Specifies the UART wakeup method. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection + * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark + * @note If the user resorts to idle line detection wake up, the Address parameter + * is useless and ignored by the initialization function. + * @note If the user resorts to address mark wake up, the address length detection + * is configured by default to 4 bits only. For the UART to be able to + * manage 6-, 7- or 8-bit long addresses detection, the API + * HAL_MultiProcessorEx_AddressLength_Set() must be called after + * HAL_MultiProcessor_Init(). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the wake up method parameter */ + assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In multiprocessor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) + { + /* If address mark wake up method is chosen, set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); + } + + /* Set the wake up method by setting the WAKE bit in the CR1 register */ + MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief DeInitialize the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + huart->Instance->CR1 = 0x0U; + huart->Instance->CR2 = 0x0U; + huart->Instance->CR3 = 0x0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + if (huart->MspDeInitCallback == NULL) + { + huart->MspDeInitCallback = HAL_UART_MspDeInit; + } + /* DeInit the low level hardware */ + huart->MspDeInitCallback(huart); +#else + /* DeInit the low level hardware */ + HAL_UART_MspDeInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Initialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User UART Callback + * To be used to override the weak predefined callback + * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_READY) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = pCallback; + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = pCallback; + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = pCallback; + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = pCallback; + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = pCallback; + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_UART_RX_FIFO_FULL_CB_ID : + huart->RxFifoFullCallback = pCallback; + break; + + case HAL_UART_TX_FIFO_EMPTY_CB_ID : + huart->TxFifoEmptyCallback = pCallback; + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (huart->gState == HAL_UART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_UART_STATE_READY == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ + break; + + case HAL_UART_RX_FIFO_FULL_CB_ID : + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + break; + + case HAL_UART_TX_FIFO_EMPTY_CB_ID : + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (HAL_UART_STATE_RESET == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register a User UART Rx Event Callback + * To be used instead of the weak predefined callback + * @param huart Uart handle + * @param pCallback Pointer to the Rx Event Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (huart->RxState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = pCallback; + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the UART Rx Event Callback + * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback + * @param huart Uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (huart->RxState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the UART asynchronous + and Half duplex data transfers. + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode API's are : + (++) HAL_UART_Transmit() + (++) HAL_UART_Receive() + + (#) Non-Blocking mode API's with Interrupt are : + (++) HAL_UART_Transmit_IT() + (++) HAL_UART_Receive_IT() + (++) HAL_UART_IRQHandler() + + (#) Non-Blocking mode API's with DMA are : + (++) HAL_UART_Transmit_DMA() + (++) HAL_UART_Receive_DMA() + (++) HAL_UART_DMAPause() + (++) HAL_UART_DMAResume() + (++) HAL_UART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (++) HAL_UART_TxHalfCpltCallback() + (++) HAL_UART_TxCpltCallback() + (++) HAL_UART_RxHalfCpltCallback() + (++) HAL_UART_RxCpltCallback() + (++) HAL_UART_ErrorCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (++) HAL_UART_Abort() + (++) HAL_UART_AbortTransmit() + (++) HAL_UART_AbortReceive() + (++) HAL_UART_Abort_IT() + (++) HAL_UART_AbortTransmit_IT() + (++) HAL_UART_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (++) HAL_UART_AbortCpltCallback() + (++) HAL_UART_AbortTransmitCpltCallback() + (++) HAL_UART_AbortReceiveCpltCallback() + + (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced + reception services: + (++) HAL_UARTEx_RxEventCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. + + -@- In the Half duplex communication, it is forbidden to run the transmit + and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @note When FIFO mode is enabled, writing a data in the TDR register adds one + * data to the TXFIFO. Write operations to the TDR register are performed + * when TXFNF flag is set. From hardware perspective, TXFNF flag and + * TXE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (const uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + while (huart->TxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; + } + else + { + huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; + } + huart->TxXferCount--; + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + huart->RxXferCount--; + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + huart->TxISR = NULL; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Configure Tx interrupt processing */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT_FIFOEN; + } + else + { + huart->TxISR = UART_TxISR_8BIT_FIFOEN; + } + + /* Enable the TX FIFO threshold interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + } + else + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT; + } + else + { + huart->TxISR = UART_TxISR_8BIT; + } + + /* Enable the Transmit Data Register Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + return (UART_Start_Receive_IT(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + uint16_t nbByte = Size; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + +#endif /* USART_DMAREQUESTS_SW_WA */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size * 2 */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + if ((huart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((huart->hdmatx->LinkedListQueue != NULL) && (huart->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)huart->pTxBuffPtr; + + /* Set DMA destination address */ + huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&huart->Instance->TDR; + + /* Enable the UART transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(huart->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the UART transmit DMA channel */ + status = HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, nbByte); + } + + if (status != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + +#endif /* USART_DMAREQUESTS_SW_WA */ + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + return (UART_Start_Receive_DMA(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pause the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + /* Suspend the UART DMA Tx channel : use blocking DMA Suspend API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + huart->hdmatx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + /* Suspend the UART DMA Rx channel : use blocking DMA Suspend API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Set the UART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + huart->hdmarx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + /* Resume the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + if (HAL_DMAEx_Resume(huart->hdmatx) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_ERROR; + } + } + } + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Resume the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + if (HAL_DMAEx_Resume(huart->hdmarx) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_ERROR; + } + } + } + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / + HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndRxTransfer(huart); + } + + return HAL_OK; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ + /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +{ + /* Disable TCIE, TXEIE and TXFTIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +{ + /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +{ + uint32_t abortcplt = 1U; + + /* Disable interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (huart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; + } + else + { + huart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (huart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; + } + else + { + huart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable DMA Tx at UART level */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* UART Tx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + huart->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* UART Rx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + huart->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ + huart->hdmatx->XferAbortCallback(huart->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Handle UART interrupt request. + * @param huart UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + if (errorflags == 0U) + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + return; + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver --------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + } + + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + errorcode = huart->ErrorCode; + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + && ((isrflags & USART_ISR_IDLE) != 0U) + && ((cr1its & USART_ISR_IDLE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + if ((nb_remaining_rx_data > 0U) + && (nb_remaining_rx_data < huart->RxXferSize)) + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (huart->hdmarx->Mode != DMA_LINKEDLIST_CIRCULAR) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (huart->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } + return; + } + else + { +#endif /* HAL_DMA_MODULE_ENABLED */ + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + if ((huart->RxXferCount > 0U) + && (nb_rx_data > 0U)) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; +#if defined(HAL_DMA_MODULE_ENABLED) + } +#endif /* HAL_DMA_MODULE_ENABLED */ + } + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) + { + if (huart->TxISR != NULL) + { + huart->TxISR(huart); + } + return; + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + { + UART_EndTransmit_IT(huart); + return; + } + + /* UART TX Fifo Empty occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + huart->TxFifoEmptyCallback(huart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ + HAL_UARTEx_TxFifoEmptyCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } + + /* UART RX Fifo Full occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + huart->RxFifoFullCallback(huart); +#else + /* Call legacy weak Rx Fifo Full Callback */ + HAL_UARTEx_RxFifoFullCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART error callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Receive Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). + * @param huart UART handle + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART. + (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly + (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature + (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature + (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode + (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode + (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode + (+) UART_SetConfig() API configures the UART peripheral + (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features + (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization + (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter + (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver + (+) HAL_LIN_SendBreak() API transmits the break characters +@endverbatim + * @{ + */ + +/** + * @brief Update on the fly the receiver timeout value in RTOR register. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout + * value must be less or equal to 0x0FFFFFFFF. + * @retval None + */ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); + MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); + } +} + +/** + * @brief Enable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Set the USART RTOEN bit */ + SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Disable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear the USART RTOEN bit */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable UART in mute mode (does not mean UART enters mute mode; + * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Enable USART mute mode by setting the MME bit in the CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Disable UART mute mode (does not mean the UART actually exits mute mode + * as it may not have been in mute mode at this very moment). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable USART mute mode by clearing the MME bit in the CR1 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Enter UART mute mode (means UART actually enters mute mode). + * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. + * @param huart UART handle. + * @retval None + */ +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); +} + +/** + * @brief Enable the UART transmitter and disable the UART receiver. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enable the UART receiver and disable the UART transmitter. + * @param huart UART handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + + +/** + * @brief Transmit break characters. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Send break characters */ + __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @brief UART Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Return the UART handle state. + (+) Return the UART handle error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the UART handle state. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval HAL state + */ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) +{ + uint32_t temp1; + uint32_t temp2; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the UART handle error code. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval UART Error Code + */ +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param huart UART handle. + * @retval none + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +{ + /* Init the UART Callback settings */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ + +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg; + uint16_t brrtemp; + uint32_t clocksource; + uint32_t usartdiv; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t lpuart_ker_ck_pres; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + if (UART_INSTANCE_LOWPOWER(huart)) + { + assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); + } + else + { + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); + } + + assert_param(IS_UART_PARITY(huart->Init.Parity)); + assert_param(IS_UART_MODE(huart->Init.Mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + + if (!(UART_INSTANCE_LOWPOWER(huart))) + { + tmpreg |= huart->Init.OneBitSampling; + } + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + + /*-------------------------- USART PRESC Configuration -----------------------*/ + /* Configure + * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ + MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + + /* Check LPUART instance */ + if (UART_INSTANCE_LOWPOWER(huart)) + { + /* Retrieve frequency clock */ + pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource); + + /* If proper clock source reported */ + if (pclk != 0U) + { + /* Compute clock after Prescaler */ + lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); + + /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ + if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || + (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) + { + ret = HAL_ERROR; + } + else + { + /* Check computed UsartDiv value is in allocated range + (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) + { + huart->Instance->BRR = usartdiv; + } + else + { + ret = HAL_ERROR; + } + } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || + (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ + } /* if (pclk != 0) */ + } + /* Check UART Over Sampling to set Baud Rate Register */ + else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource); + + /* USARTDIV must be greater than or equal to 0d16 */ + if (pclk != 0U) + { + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + huart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } + } + } + else + { + pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource); + + if (pclk != 0U) + { + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + huart->Instance->BRR = (uint16_t)usartdiv; + } + else + { + ret = HAL_ERROR; + } + } + } + + /* Initialize the number of data to process during RX/TX ISR execution */ + huart->NbTxDataToProcess = 1; + huart->NbRxDataToProcess = 1; + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + return ret; +} + +/** + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + } + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + } +} + +/** + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Disable TXE interrupt for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Check if the Receiver is enabled */ + if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->RxState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief This function handles UART Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param huart UART handle. + * @param Flag Specifies the UART flag to check + * @param Status The actual Flag status (SET or RESET) + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + + return HAL_TIMEOUT; + } + + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_ORE; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_RTO; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Start Receive operation in interrupt mode. + * @note This function could be called by all HAL UART API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + huart->RxISR = NULL; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Configure Rx interrupt processing */ + if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT_FIFOEN; + } + else + { + huart->RxISR = UART_RxISR_8BIT_FIFOEN; + } + + /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + } + else + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT; + } + else + { + huart->RxISR = UART_RxISR_8BIT; + } + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + return HAL_OK; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Start Receive operation in DMA mode. + * @note This function could be called by all HAL UART API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + uint16_t nbByte = Size; + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + if (huart->hdmarx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size * 2 */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + if ((huart->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((huart->hdmarx->LinkedListQueue != NULL) && (huart->hdmarx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)&huart->Instance->RDR; + + /* Set DMA destination address */ + huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)huart->pRxBuffPtr; + + /* Enable the UART receive DMA channel */ + status = HAL_DMAEx_List_Start_IT(huart->hdmarx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the UART receive DMA channel */ + status = HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, nbByte); + } + + if (status != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Restore huart->RxState to ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + + /* Enable the UART Parity Error Interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; +} + + +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE, TCIE, TXFT interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; +} + + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA UART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Check if DMA in circular mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + huart->TxXferCount = 0U; + +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + /* DMA Circular mode */ + else + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART transmit process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx Half complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx Half complete callback*/ + HAL_UART_TxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Check if DMA in circular mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + huart->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + huart->RxXferCount = 0; + + /* Check current nb of data still to be received on DMA side. + DMA Normal mode, remaining nb of data will be 0 + DMA Circular mode, remaining nb of data is reset to RxXferSize */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data < huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART receive process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + huart->RxXferCount = huart->RxXferSize / 2U; + + /* Check current nb of data still to be received on DMA side. */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data <= huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Half Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + huart->TxXferCount = 0U; + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + huart->RxXferCount = 0U; + UART_EndRxTransfer(huart); + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + huart->RxXferCount = 0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmarx != NULL) + { + if (huart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmatx != NULL) + { + if (huart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->TxXferCount = 0U; + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief TX interrupt handler for 7 or 8 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) +{ + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + } +} + +/** + * @brief TX interrupt handler for 9 bits data word length. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) +{ + const uint16_t *tmp; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + tmp = (const uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + } +} + +/** + * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (huart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + break; /* force exit loop */ + } + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + const uint16_t *tmp; + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (huart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + break; /* force exit loop */ + } + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) + { + tmp = (const uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief RX interrupt handler for 7 or 8 bits data word length . + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 9 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t *) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + break; + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_8BIT; + + /* Enable the UART Data Register Not Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t *) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + break; + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_16BIT; + + /* Enable the UART Data Register Not Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c new file mode 100644 index 000000000..309ae76c5 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c @@ -0,0 +1,1158 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_uart_ex.c + * @author MCD Application Team + * @brief Extended UART HAL module driver. + * This file provides firmware functions to manage the following extended + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### UART peripheral extended features ##### + ============================================================================== + [..] + (#) Declare a UART_HandleTypeDef handle structure. + + (#) For the UART RS485 Driver Enable mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + + -@- When UART operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be + configured prior starting RX/TX transfers. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup UARTEx UARTEx + * @brief UART Extended HAL module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UARTEX_Private_Constants UARTEx Private Constants + * @{ + */ +/* UART RX FIFO depth */ +#define RX_FIFO_DEPTH 8U + +/* UART TX FIFO depth */ +#define TX_FIFO_DEPTH 8U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UARTEx_Private_Functions UARTEx Private Functions + * @{ + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions + * @{ + */ + +/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Extended Initialization and Configuration Functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration + procedures (details for the procedures are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the RS485 Driver enable feature according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param Polarity Select the driver enable polarity. + * This parameter can be one of the following values: + * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high + * @arg @ref UART_DE_POLARITY_LOW DE signal is active low + * @param AssertionTime Driver Enable assertion time: + * 5-bit value defining the time between the activation of the DE (Driver Enable) + * signal and the beginning of the start bit. It is expressed in sample time + * units (1/8 or 1/16 bit time, depending on the oversampling rate) + * @param DeassertionTime Driver Enable deassertion time: + * 5-bit value defining the time between the end of the last stop bit, in a + * transmitted message, and the de-activation of the DE (Driver Enable) signal. + * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the + * oversampling rate). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime) +{ + uint32_t temp; + + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + /* Check the Driver Enable UART instance */ + assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); + + /* Check the Driver Enable polarity */ + assert_param(IS_UART_DE_POLARITY(Polarity)); + + /* Check the Driver Enable assertion time */ + assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); + + /* Check the Driver Enable deassertion time */ + assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DEM); + + /* Set the Driver Enable polarity */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); + + /* Set the Driver Enable assertion and deassertion times */ + temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); + temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions + * @brief Extended functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of Wakeup and FIFO mode related callback functions. + (#) TX/RX Fifos Callbacks: + (++) HAL_UARTEx_RxFifoFullCallback() + (++) HAL_UARTEx_TxFifoEmptyCallback() +@endverbatim + * @{ + */ + +/** + * @brief UART RX Fifo full callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief UART TX Fifo empty callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides the following functions: + (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address + detection length to more than 4 bits for multiprocessor address mark wake up. + (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode + trigger: address match, Start Bit detection or RXNE bit status. + (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode + (+) HAL_UARTEx_DisableStopMode() API disables the above functionality + (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold + + [..] This subsection also provides a set of additional functions providing enhanced reception + services to user. (For example, these functions allow application to handle use cases + where number of data to be received is unknown). + + (#) Compared to standard reception services which only consider number of received + data elements as reception completion criteria, these functions also consider additional events + as triggers for updating reception status to caller : + (++) Detection of inactivity period (RX line has not been active for a given period). + (+++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + for 1 frame time, after last received byte. + (+++) RX inactivity detected by RTO, i.e. line has been in idle state + for a programmable time, after last received byte. + (++) Detection that a specific character has been received. + + (#) There are two modes of transfer: + (++) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + or till IDLE event occurs. Reception is handled only during function execution. + When function exits, no data reception could occur. HAL status and number of actually received data elements, + are returned by function after finishing transfer. + (++) Non-Blocking mode: The reception is performed using Interrupts or DMA. + These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. + The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. + + (#) Blocking mode API: + (++) HAL_UARTEx_ReceiveToIdle() + + (#) Non-Blocking mode API with Interrupt: + (++) HAL_UARTEx_ReceiveToIdle_IT() + + (#) Non-Blocking mode API with DMA: + (++) HAL_UARTEx_ReceiveToIdle_DMA() + +@endverbatim + * @{ + */ + +/** + * @brief By default in multiprocessor mode, when the wake up method is set + * to address mark, the UART handles only 4-bit long addresses detection; + * this API allows to enable longer addresses detection (6-, 7- or 8-bit + * long). + * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, + * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. + * @param huart UART handle. + * @param AddressLength This parameter can be one of the following values: + * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address + * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the address length parameter */ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Set Wakeup from Stop mode interrupt flag selection. + * @note It is the application responsibility to enable the interrupt used as + * usart_wkup interrupt source before entering low-power mode. + * @param huart UART handle. + * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUP_ON_ADDRESS + * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* check the wake-up from stop mode UART instance */ + assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); + /* check the wake-up selection parameter */ + assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) + { + UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); + } + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + status = HAL_TIMEOUT; + } + else + { + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Enable UART Stop Mode. + * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Set UESM bit */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable UART Stop Mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Clear UESM bit */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + huart->FifoMode = UART_FIFOMODE_ENABLE; + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Disable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + huart->FifoMode = UART_FIFOMODE_DISABLE; + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Set the TXFIFO threshold. + * @param huart UART handle. + * @param Threshold TX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref UART_TXFIFO_THRESHOLD_1_8 + * @arg @ref UART_TXFIFO_THRESHOLD_1_4 + * @arg @ref UART_TXFIFO_THRESHOLD_1_2 + * @arg @ref UART_TXFIFO_THRESHOLD_3_4 + * @arg @ref UART_TXFIFO_THRESHOLD_7_8 + * @arg @ref UART_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Update TX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Set the RXFIFO threshold. + * @param huart UART handle. + * @param Threshold RX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref UART_RXFIFO_THRESHOLD_1_8 + * @arg @ref UART_RXFIFO_THRESHOLD_1_4 + * @arg @ref UART_RXFIFO_THRESHOLD_1_2 + * @arg @ref UART_RXFIFO_THRESHOLD_3_4 + * @arg @ref UART_RXFIFO_THRESHOLD_7_8 + * @arg @ref UART_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check the parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Update RX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in blocking mode till either the expected number of data + * is received or an IDLE event occurs. + * @note HAL_OK is returned if reception is completed (expected number of data has been received) + * or if reception is stopped after IDLE event (less than the expected number of data has been received) + * In this case, RxLen output parameter indicates number of data available in reception buffer. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @param RxLen Number of data elements finally received + * (could be lower than Size, in case reception ends on IDLE event) + * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* Initialize output number of received elements */ + *RxLen = 0U; + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* If Set, but no data ever received, clear flag without exiting loop */ + /* If Set, and data has already been received, this means Idle Event is valid : End reception */ + if (*RxLen > 0U) + { + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + } + + /* Check if RXNE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) + { + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + /* Increment number of received elements */ + *RxLen += 1U; + huart->RxXferCount--; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Set number of received elements in output parameter : RxLen */ + *RxLen = huart->RxXferSize - huart->RxXferCount; + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode till either the expected number of data + * is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + (void)UART_Start_Receive_IT(huart, pData, Size); + + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Receive an amount of data in DMA mode till either the expected number + * of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + status = UART_Start_Receive_DMA(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Provide Rx Event type that has lead to RxEvent callback execution. + * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress + * of reception process is provided to application through calls of Rx Event callback (either default one + * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, + * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead + * to Rx Event callback execution. + * @note This function is expected to be called within the user implementation of Rx Event Callback, + * in order to provide the accurate value. + * @note In Interrupt Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received. + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA mode, RxEvent callback could be called several times; + * When DMA is configured in Normal Mode, HT event does not stop Reception process; + * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; + * @param huart UART handle. + * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) + */ +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart) +{ + /* Return Rx Event type value, as stored in UART handle */ + return (huart->RxEventType); +} + +/** + * @brief Set autonomous mode Configuration. + * @param huart UART handle. + * @param sConfig Autonomous mode structure parameters. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart, + const UART_AutonomousModeConfTypeDef *sConfig) +{ + uint32_t tmpreg; + + if (huart->gState == HAL_UART_STATE_READY) + { + /* Check the parameters */ + assert_param(IS_UART_TRIGGER_POLARITY(sConfig->TriggerPolarity)); + assert_param(IS_UART_IDLE_FRAME_TRANSMIT(sConfig->IdleFrame)); + assert_param(IS_UART_TX_DATA_SIZE(sConfig->DataSize)); + if (IS_LPUART_INSTANCE(huart->Instance)) + { + assert_param(IS_LPUART_TRIGGER_SELECTION(sConfig->TriggerSelection)); + } + else + { + assert_param(IS_UART_TRIGGER_SELECTION(sConfig->TriggerSelection)); + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Disable Transmitter */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TE); + + /* Clear AUTOCR register */ + CLEAR_REG(huart->Instance->AUTOCR); + + /* UART AUTOCR Configuration */ + tmpreg = ((sConfig->DataSize << USART_AUTOCR_TDN_Pos) | (sConfig->TriggerPolarity) | \ + (sConfig->AutonomousModeState) | (sConfig->IdleFrame) | \ + (sConfig->TriggerSelection << USART_AUTOCR_TRIGSEL_Pos)); + + WRITE_REG(huart->Instance->AUTOCR, tmpreg); + + /* Enable UART */ + __HAL_UART_ENABLE(huart); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Get autonomous mode Configuration. + * @param huart UART handle. + * @param sConfig Autonomous mode structure parameters. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(const UART_HandleTypeDef *huart, + UART_AutonomousModeConfTypeDef *sConfig) +{ + uint32_t tmpreg; + + /* Read AUTOCR register */ + tmpreg = READ_REG(huart->Instance->AUTOCR); + + /* Fill Autonomous structure parameter */ + sConfig->AutonomousModeState = (tmpreg & USART_AUTOCR_TRIGEN); + sConfig->TriggerSelection = ((tmpreg & USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos); + sConfig->TriggerPolarity = (tmpreg & USART_AUTOCR_TRIGPOL); + sConfig->IdleFrame = (tmpreg & USART_AUTOCR_IDLEDIS); + sConfig->DataSize = (tmpreg & USART_AUTOCR_TDN); + + return HAL_OK; +} + +/** + * @brief Clear autonomous mode Configuration. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Clear AUTOCR register */ + CLEAR_REG(huart->Instance->AUTOCR); + + /* Enable UART */ + __HAL_UART_ENABLE(huart); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UARTEx_Private_Functions + * @{ + */ + +/** + * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. + * @param huart UART handle. + * @param WakeUpSelection UART wake up from stop mode parameters. + * @retval None + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); + + /* Set the USART address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); + + /* Set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); +} + +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @note The RX FIFO depth and the TX FIFO depth is extracted from + * the UART configuration registers. + * @param huart UART handle. + * @retval None + */ +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + + if (huart->FifoMode == UART_FIFOMODE_DISABLE) + { + huart->NbTxDataToProcess = 1U; + huart->NbRxDataToProcess = 1U; + } + else + { + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; + rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; + } +} +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart.c new file mode 100644 index 000000000..fb4d7c219 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart.c @@ -0,0 +1,4017 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_usart.c + * @author MCD Application Team + * @brief USART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter + * Peripheral (USART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Error functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The USART HAL driver can be used as follows: + + (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart). + (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API: + (++) Enable the USARTx interface clock. + (++) USART pins configuration: + (+++) Enable the clock for the USART GPIOs. + (+++) Configure these USART pins as alternate function pull-up. + (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(), + HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (++) USART interrupts handling: + -@@- The specific USART interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process. + (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA() + HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer + complete interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode + (Receiver/Transmitter) in the husart handle Init structure. + + (#) Initialize the USART registers by calling the HAL_USART_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_USART_MspInit(&husart) API. + + [..] + (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's + HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and + HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_USART_RegisterCallback() to register a user callback. + Function HAL_USART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) TxRxCpltCallback : Tx Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : USART MspInit. + (+) MspDeInitCallback : USART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_USART_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) TxRxCpltCallback : Tx Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : USART MspInit. + (+) MspDeInitCallback : USART MspDeInit. + + [..] + By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak functions in the HAL_USART_Init() + and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_USART_RegisterCallback() before calling HAL_USART_DeInit() + or HAL_USART_Init() function. + + [..] + When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak callbacks are used. + + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup USART USART + * @brief HAL USART Synchronous SPI module driver + * @{ + */ + +#ifdef HAL_USART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup USART_Private_Constants USART Private Constants + * @{ + */ +#define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */ +#define USART_TEACK_REACK_TIMEOUT 1000U /*!< USART TX or RX enable acknowledge time-out value */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 | \ + USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by USART_SetConfig API */ + +#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \ + USART_CR2_LBCL | USART_CR2_STOP | USART_CR2_SLVEN | \ + USART_CR2_DIS_NSS)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */ + +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART or USART CR3 fields of parameters set by USART_SetConfig API */ + +#define USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */ +#define USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup USART_Private_Functions + * @{ + */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +static void USART_EndTransfer(USART_HandleTypeDef *husart); +#if defined(HAL_DMA_MODULE_ENABLED) +static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void USART_DMAError(DMA_HandleTypeDef *hdma); +static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart); +static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart); +static void USART_TxISR_8BIT(USART_HandleTypeDef *husart); +static void USART_TxISR_16BIT(USART_HandleTypeDef *husart); +static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart); +static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); +static void USART_EndTransmit_IT(USART_HandleTypeDef *husart); +static void USART_RxISR_8BIT(USART_HandleTypeDef *husart); +static void USART_RxISR_16BIT(USART_HandleTypeDef *husart); +static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart); +static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USART_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USART + in synchronous SPI master/slave mode. + (+) For the synchronous SPI mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) USART polarity + (++) USART phase + (++) USART LastBit + (++) Receiver/transmitter modes + + [..] + The HAL_USART_Init() function follows the USART synchronous SPI configuration + procedure (details for the procedure are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible USART formats are listed in the + following table. + + Table 1. USART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | USART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the USART mode according to the specified + * parameters in the USART_InitTypeDef and initialize the associated handle. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) +{ + /* Check the USART handle allocation */ + if (husart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_USART_INSTANCE(husart->Instance)); + + if (husart->State == HAL_USART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + husart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + USART_InitCallbacksToDefault(husart); + + if (husart->MspInitCallback == NULL) + { + husart->MspInitCallback = HAL_USART_MspInit; + } + + /* Init the low level hardware */ + husart->MspInitCallback(husart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_USART_MspInit(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + + husart->State = HAL_USART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_USART_DISABLE(husart); + + /* Set the Usart Communication parameters */ + if (USART_SetConfig(husart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In Synchronous SPI mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register + - HDSEL, SCEN and IREN bits in the USART_CR3 register. + */ + husart->Instance->CR2 &= ~USART_CR2_LINEN; + husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); + + /* Enable the Peripheral */ + __HAL_USART_ENABLE(husart); + + /* TEACK and/or REACK to check before moving husart->State to Ready */ + return (USART_CheckIdleState(husart)); +} + +/** + * @brief DeInitialize the USART peripheral. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) +{ + /* Check the USART handle allocation */ + if (husart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_USART_INSTANCE(husart->Instance)); + + husart->State = HAL_USART_STATE_BUSY; + + husart->Instance->CR1 = 0x0U; + husart->Instance->CR2 = 0x0U; + husart->Instance->CR3 = 0x0U; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + if (husart->MspDeInitCallback == NULL) + { + husart->MspDeInitCallback = HAL_USART_MspDeInit; + } + /* DeInit the low level hardware */ + husart->MspDeInitCallback(husart); +#else + /* DeInit the low level hardware */ + HAL_USART_MspDeInit(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_RESET; + + /* Process Unlock */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Initialize the USART MSP. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the USART MSP. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User USART Callback + * To be used to override the weak predefined callback + * @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID + * @param husart usart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status ++ */ +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (husart->State == HAL_USART_STATE_READY) + { + switch (CallbackID) + { + case HAL_USART_TX_HALFCOMPLETE_CB_ID : + husart->TxHalfCpltCallback = pCallback; + break; + + case HAL_USART_TX_COMPLETE_CB_ID : + husart->TxCpltCallback = pCallback; + break; + + case HAL_USART_RX_HALFCOMPLETE_CB_ID : + husart->RxHalfCpltCallback = pCallback; + break; + + case HAL_USART_RX_COMPLETE_CB_ID : + husart->RxCpltCallback = pCallback; + break; + + case HAL_USART_TX_RX_COMPLETE_CB_ID : + husart->TxRxCpltCallback = pCallback; + break; + + case HAL_USART_ERROR_CB_ID : + husart->ErrorCallback = pCallback; + break; + + case HAL_USART_ABORT_COMPLETE_CB_ID : + husart->AbortCpltCallback = pCallback; + break; + + case HAL_USART_RX_FIFO_FULL_CB_ID : + husart->RxFifoFullCallback = pCallback; + break; + + case HAL_USART_TX_FIFO_EMPTY_CB_ID : + husart->TxFifoEmptyCallback = pCallback; + break; + + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = pCallback; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (husart->State == HAL_USART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = pCallback; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an USART Callback + * USART callaback is redirected to the weak predefined callback + * @note The HAL_USART_UnRegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to un-register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID + * @param husart usart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_USART_STATE_READY == husart->State) + { + switch (CallbackID) + { + case HAL_USART_TX_HALFCOMPLETE_CB_ID : + husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_USART_TX_COMPLETE_CB_ID : + husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_USART_RX_HALFCOMPLETE_CB_ID : + husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_USART_RX_COMPLETE_CB_ID : + husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_USART_TX_RX_COMPLETE_CB_ID : + husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_USART_ERROR_CB_ID : + husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_USART_ABORT_COMPLETE_CB_ID : + husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_USART_RX_FIFO_FULL_CB_ID : + husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + break; + + case HAL_USART_TX_FIFO_EMPTY_CB_ID : + husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + break; + + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_USART_STATE_RESET == husart->State) + { + switch (CallbackID) + { + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = HAL_USART_MspInit; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = HAL_USART_MspDeInit; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions_Group2 IO operation functions + * @brief USART Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USART synchronous SPI + data transfers. + + [..] The USART Synchronous SPI supports master and slave modes (SCLK as output or input). + + [..] + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated USART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode API's are : + (++) HAL_USART_Transmit() in simplex mode + (++) HAL_USART_Receive() in full duplex receive only + (++) HAL_USART_TransmitReceive() in full duplex mode + + (#) Non-Blocking mode API's with Interrupt are : + (++) HAL_USART_Transmit_IT() in simplex mode + (++) HAL_USART_Receive_IT() in full duplex receive only + (++) HAL_USART_TransmitReceive_IT() in full duplex mode + (++) HAL_USART_IRQHandler() + + (#) No-Blocking mode API's with DMA are : + (++) HAL_USART_Transmit_DMA() in simplex mode + (++) HAL_USART_Receive_DMA() in full duplex receive only + (++) HAL_USART_TransmitReceive_DMA() in full duplex mode + (++) HAL_USART_DMAPause() + (++) HAL_USART_DMAResume() + (++) HAL_USART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (++) HAL_USART_TxCpltCallback() + (++) HAL_USART_RxCpltCallback() + (++) HAL_USART_TxHalfCpltCallback() + (++) HAL_USART_RxHalfCpltCallback() + (++) HAL_USART_ErrorCallback() + (++) HAL_USART_TxRxCpltCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (++) HAL_USART_Abort() + (++) HAL_USART_Abort_IT() + + (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided: + (++) HAL_USART_AbortCpltCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, + Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify + error type, and HAL_USART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on USART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, + and HAL_USART_ErrorCallback() user callback is executed. + +@endverbatim + * @{ + */ + +/** + * @brief Simplex send an amount of data in blocking mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. + * @param husart USART handle. + * @param pTxData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, + uint32_t Timeout) +{ + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; + uint32_t tickstart; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pTxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + ptxdata8bits = NULL; + ptxdata16bits = (const uint16_t *) pTxData; + } + else + { + ptxdata8bits = pTxData; + ptxdata16bits = NULL; + } + + /* Check the remaining data to be sent */ + while (husart->TxXferCount > 0U) + { + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (ptxdata8bits == NULL) + { + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & 0x01FFU); + ptxdata16bits++; + } + else + { + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & 0xFFU); + ptxdata8bits++; + } + + husart->TxXferCount--; + } + + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear Transmission Complete Flag */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + + /* Clear overrun flag and discard the received data */ + __HAL_USART_CLEAR_OREFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + + /* At end of Tx process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. + * @param husart USART handle. + * @param pRxData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *prxdata8bits; + uint16_t *prxdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + husart->RxXferSize = Size; + husart->RxXferCount = Size; + + /* Computation of USART mask to apply to RDR register */ + USART_MASK_COMPUTATION(husart); + uhMask = husart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + prxdata8bits = NULL; + prxdata16bits = (uint16_t *) pRxData; + } + else + { + prxdata8bits = pRxData; + prxdata16bits = NULL; + } + + /* as long as data have to be received */ + while (husart->RxXferCount > 0U) + { + if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) + { + /* Wait until TXE flag is set to send dummy byte in order to generate the + * clock for the slave to send data. + * Whatever the frame length (7, 8 or 9-bit long), the same dummy value + * can be written for all the cases. */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF); + } + + /* Wait for RXNE Flag */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (prxdata8bits == NULL) + { + *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask); + prxdata16bits++; + } + else + { + *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU)); + prxdata8bits++; + } + + husart->RxXferCount--; + + } + + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* At end of Rx process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Send and Receive an amount of data in blocking mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. + * @param husart USART handle. + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) +{ + uint8_t *prxdata8bits; + uint16_t *prxdata16bits; + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; + uint16_t uhMask; + uint16_t rxdatacount; + uint32_t tickstart; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + } + + /* Disable the USART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + husart->RxXferSize = Size; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + husart->RxXferCount = Size; + + /* Computation of USART mask to apply to RDR register */ + USART_MASK_COMPUTATION(husart); + uhMask = husart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + prxdata8bits = NULL; + ptxdata8bits = NULL; + ptxdata16bits = (const uint16_t *) pTxData; + prxdata16bits = (uint16_t *) pRxData; + } + else + { + prxdata8bits = pRxData; + ptxdata8bits = pTxData; + ptxdata16bits = NULL; + prxdata16bits = NULL; + } + + if ((husart->TxXferCount == 0x01U) || (husart->SlaveMode == USART_SLAVEMODE_ENABLE)) + { + /* Wait until TXE flag is set to send data */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (ptxdata8bits == NULL) + { + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask); + ptxdata16bits++; + } + else + { + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU)); + ptxdata8bits++; + } + + husart->TxXferCount--; + } + + /* Check the remain data to be sent */ + /* rxdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + rxdatacount = husart->RxXferCount; + while ((husart->TxXferCount > 0U) || (rxdatacount > 0U)) + { + if (husart->TxXferCount > 0U) + { + /* Wait until TXE flag is set to send data */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (ptxdata8bits == NULL) + { + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask); + ptxdata16bits++; + } + else + { + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU)); + ptxdata8bits++; + } + + husart->TxXferCount--; + } + + if (husart->RxXferCount > 0U) + { + /* Wait for RXNE Flag */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (prxdata8bits == NULL) + { + *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask); + prxdata16bits++; + } + else + { + *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU)); + prxdata8bits++; + } + + husart->RxXferCount--; + } + rxdatacount = husart->RxXferCount; + } + + /* At end of TxRx process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. + * @param husart USART handle. + * @param pTxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) +{ + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + husart->TxISR = NULL; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + /* The USART Error Interrupts: (Frame error, noise error, overrun error) + are not managed by the USART Transmit Process to avoid the overrun interrupt + when the usart mode is configured for transmit and receive "USART_MODE_TX_RX" + to benefit for the frame error and noise interrupts the usart mode should be + configured only for transmit "USART_MODE_TX" */ + + /* Configure Tx interrupt processing */ + if (husart->FifoMode == USART_FIFOMODE_ENABLE) + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT_FIFOEN; + } + else + { + husart->TxISR = USART_TxISR_8BIT_FIFOEN; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the TX FIFO threshold interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TXFT); + } + else + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT; + } + else + { + husart->TxISR = USART_TxISR_8BIT; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Transmit Data Register Empty Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. + * @param husart USART handle. + * @param pRxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) +{ + uint16_t nb_dummy_data; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->RxXferCount = Size; + husart->RxISR = NULL; + + USART_MASK_COMPUTATION(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Configure Rx interrupt processing */ + if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->RxISR = USART_RxISR_16BIT_FIFOEN; + } + else + { + husart->RxISR = USART_RxISR_8BIT_FIFOEN; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */ + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); + } + else + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->RxISR = USART_RxISR_16BIT; + } + else + { + husart->RxISR = USART_RxISR_8BIT; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Parity Error and Data Register not empty Interrupts */ + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + + if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) + { + /* Send dummy data in order to generate the clock for the Slave to send the next data. + When FIFO mode is disabled only one data must be transferred. + When FIFO mode is enabled data must be transmitted until the RX FIFO reaches its threshold. + */ + if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) + { + for (nb_dummy_data = husart->NbRxDataToProcess ; nb_dummy_data > 0U ; nb_dummy_data--) + { + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + else + { + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. + * @param husart USART handle. + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + } + + /* Disable the USART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->RxXferCount = Size; + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + /* Computation of USART mask to apply to RDR register */ + USART_MASK_COMPUTATION(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX_RX; + + /* Configure TxRx interrupt processing */ + if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT_FIFOEN; + husart->RxISR = USART_RxISR_16BIT_FIFOEN; + } + else + { + husart->TxISR = USART_TxISR_8BIT_FIFOEN; + husart->RxISR = USART_RxISR_8BIT_FIFOEN; + } + + /* Process Locked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the TX and RX FIFO Threshold interrupts */ + SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE)); + } + else + { + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT; + husart->RxISR = USART_RxISR_16BIT; + } + else + { + husart->TxISR = USART_TxISR_8BIT; + husart->RxISR = USART_RxISR_8BIT; + } + + /* Process Locked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Enable the USART Parity Error and USART Data Register not empty Interrupts */ + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + + /* Enable the USART Transmit Data Register Empty Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Send an amount of data in DMA mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. + * @param husart USART handle. + * @param pTxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + const uint32_t *tmp; + uint16_t nbByte = Size; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + if (husart->hdmatx != NULL) + { + /* Set the USART DMA transfer complete callback */ + husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; + + /* Set the DMA error callback */ + husart->hdmatx->XferErrorCallback = USART_DMAError; + + /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + tmp = (const uint32_t *)&pTxData; + + /* Check linked list mode */ + if ((husart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((husart->hdmatx->LinkedListQueue != NULL) && (husart->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(const uint32_t *)tmp; + + /* Set DMA destination address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&husart->Instance->TDR; + + /* Enable the USART transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(husart->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the USART transmit DMA channel */ + status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte); + } + } + + if (status == HAL_OK) + { + /* Clear the TC flag in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @note When the USART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. + * @param husart USART handle. + * @param pRxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t *tmp = (uint32_t *)&pRxData; + uint16_t nbByte = Size; + + /* Check that a Rx process is not already ongoing */ + if (husart->State == HAL_USART_STATE_READY) + { + if ((pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->pTxBuffPtr = pRxData; + husart->TxXferSize = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + if (husart->hdmarx != NULL) + { + /* Set the USART DMA Rx transfer complete callback */ + husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; + + /* Set the USART DMA Rx transfer error callback */ + husart->hdmarx->XferErrorCallback = USART_DMAError; + + /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + if ((husart->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((husart->hdmarx->LinkedListQueue != NULL) && (husart->hdmarx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)&husart->Instance->RDR; + + /* Set DMA destination address */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = *(uint32_t *)tmp; + + /* Enable the USART receive DMA channel */ + status = HAL_DMAEx_List_Start_IT(husart->hdmarx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the USART receive DMA channel */ + status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, nbByte); + } + } + + if ((status == HAL_OK) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Enable the USART transmit DMA channel: the transmit channel is used in order + to generate in the non-blocking mode the clock to the slave device, + this mode isn't a simplex receive mode but a full-duplex receive mode */ + + /* Set the USART DMA Tx Complete and Error callback to Null */ + if (husart->hdmatx != NULL) + { + husart->hdmatx->XferErrorCallback = NULL; + husart->hdmatx->XferHalfCpltCallback = NULL; + husart->hdmatx->XferCpltCallback = NULL; + + /* Check linked list mode */ + if ((husart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((husart->hdmatx->LinkedListQueue != NULL) && (husart->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(uint32_t *)tmp; + + /* Set DMA destination address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&husart->Instance->TDR; + + /* Enable the USART transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(husart->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte); + } + } + } + + if (status == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + if ((husart->hdmarx != NULL) && ((husart->hdmarx->Mode & DMA_LINKEDLIST) != DMA_LINKEDLIST)) + { + status = HAL_DMA_Abort(husart->hdmarx); + } + + /* No need to check on error code */ + UNUSED(status); + + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. + * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. + * @param husart USART handle. + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received/sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + HAL_StatusTypeDef status; + const uint32_t *tmp; + uint16_t nbByte = Size; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX_RX; + + if ((husart->hdmarx != NULL) && (husart->hdmatx != NULL)) + { + /* Set the USART DMA Rx transfer complete callback */ + husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; + + /* Set the USART DMA Tx transfer complete callback */ + husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; + + /* Set the USART DMA Tx transfer error callback */ + husart->hdmatx->XferErrorCallback = USART_DMAError; + + /* Set the USART DMA Rx transfer error callback */ + husart->hdmarx->XferErrorCallback = USART_DMAError; + + /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + tmp = (uint32_t *)&pRxData; + if ((husart->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((husart->hdmarx->LinkedListQueue != NULL) && (husart->hdmarx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)&husart->Instance->RDR; + + /* Set DMA destination address */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = *(const uint32_t *)tmp; + + /* Enable the USART receive DMA channel */ + status = HAL_DMAEx_List_Start_IT(husart->hdmarx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the USART receive DMA channel */ + status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(const uint32_t *)tmp, nbByte); + } + + /* Enable the USART transmit DMA channel */ + if (status == HAL_OK) + { + tmp = (const uint32_t *)&pTxData; + + /* Check linked list mode */ + if ((husart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((husart->hdmatx->LinkedListQueue != NULL) && (husart->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(const uint32_t *)tmp; + + /* Set DMA destination address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&husart->Instance->TDR; + + /* Enable the USART transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(husart->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte); + } + } + } + else + { + status = HAL_ERROR; + } + + if (status == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Clear the TC flag in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + if ((husart->hdmarx != NULL) && ((husart->hdmarx->Mode & DMA_LINKEDLIST) != DMA_LINKEDLIST)) + { + status = HAL_DMA_Abort(husart->hdmarx); + } + + /* No need to check on error code */ + UNUSED(status); + + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pause the DMA Transfer. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + + /* Process Locked */ + __HAL_LOCK(husart); + + if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) && + (state == HAL_USART_STATE_BUSY_TX)) + { + /* Suspend the USART DMA Tx channel : use blocking DMA Suspend API (no callback) */ + if (husart->hdmatx != NULL) + { + /* Set the USART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + husart->hdmatx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Set the USART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + husart->hdmarx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(husart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + + if (state == HAL_USART_STATE_BUSY_TX_RX) + { + /* Set the USART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + husart->hdmatx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + + /* Process Locked */ + __HAL_LOCK(husart); + + if (state == HAL_USART_STATE_BUSY_TX) + { + /* Resume the USART DMA Tx channel */ + if (husart->hdmatx != NULL) + { + if (HAL_DMAEx_Resume(husart->hdmatx) != HAL_OK) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_ERROR; + } + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + /* Clear the Overrun flag before resuming the Rx transfer*/ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); + + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Resume the USART DMA Rx channel */ + if (husart->hdmarx != NULL) + { + if (HAL_DMAEx_Resume(husart->hdmarx) != HAL_OK) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_ERROR; + } + } + + if (state == HAL_USART_STATE_BUSY_TX_RX) + { + /* Resume the USART DMA Tx channel */ + if (husart->hdmatx != NULL) + { + if (HAL_DMAEx_Resume(husart->hdmatx) != HAL_OK) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_ERROR; + } + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() / + HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + /* Disable the USART Tx/Rx DMA requests */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the USART DMA tx channel */ + if (husart->hdmatx != NULL) + { + if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + /* Abort the USART DMA rx channel */ + if (husart->hdmarx != NULL) + { + if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + USART_EndTransfer(husart); + husart->State = HAL_USART_STATE_READY; + + return HAL_OK; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param husart USART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable USART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) +{ + /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the USART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (husart->hdmatx != NULL) + { + /* Set the USART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + husart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Abort the USART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Rx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (husart->hdmarx != NULL) + { + /* Set the USART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + husart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx and Rx transfer counters */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (husart->FifoMode == USART_FIFOMODE_ENABLE) + { + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Reset Handle ErrorCode to No Error */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param husart USART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable USART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) +{ + uint32_t abortcplt = 1U; + + /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (husart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if USART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback; + } + else + { + husart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (husart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if USART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback; + } + else + { + husart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Abort the USART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable DMA Tx at USART level */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (husart->hdmatx != NULL) + { + /* USART Tx DMA Abort callback has already been initialised : + will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK) + { + husart->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Abort the USART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Rx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (husart->hdmarx != NULL) + { + /* USART Rx DMA Abort callback has already been initialised : + will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) + { + husart->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (husart->FifoMode == USART_FIFOMODE_ENABLE) + { + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ + HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Handle USART interrupt request. + * @param husart USART handle. + * @retval None + */ +void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) +{ + uint32_t isrflags = READ_REG(husart->Instance->ISR); + uint32_t cr1its = READ_REG(husart->Instance->CR1); + uint32_t cr3its = READ_REG(husart->Instance->CR3); + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF | + USART_ISR_UDR)); + if (errorflags == 0U) + { + /* USART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (husart->RxISR != NULL) + { + husart->RxISR(husart); + } + return; + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + && (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))) + { + /* USART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF); + + husart->ErrorCode |= HAL_USART_ERROR_PE; + } + + /* USART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF); + + husart->ErrorCode |= HAL_USART_ERROR_FE; + } + + /* USART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF); + + husart->ErrorCode |= HAL_USART_ERROR_NE; + } + + /* USART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); + + husart->ErrorCode |= HAL_USART_ERROR_ORE; + } + + /* USART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF); + + husart->ErrorCode |= HAL_USART_ERROR_RTO; + } + + /* USART SPI slave underrun error interrupt occurred -------------------------*/ + if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + /* Ignore SPI slave underrun errors when reception is going on */ + if (husart->State == HAL_USART_STATE_BUSY_RX) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + return; + } + else + { + __HAL_USART_CLEAR_UDRFLAG(husart); + husart->ErrorCode |= HAL_USART_ERROR_UDR; + } + } + + /* Call USART Error Call back function if need be --------------------------*/ + if (husart->ErrorCode != HAL_USART_ERROR_NONE) + { + /* USART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (husart->RxISR != NULL) + { + husart->RxISR(husart); + } + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + errorcode = husart->ErrorCode & HAL_USART_ERROR_ORE; + if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) || + (errorcode != 0U)) + { + /* Blocking error : transfer is aborted + Set the USART state ready to be able to start again the process, + Disable Interrupts, and disable DMA requests, if ongoing */ + USART_EndTransfer(husart); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the USART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Rx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the USART DMA Tx channel */ + if (husart->hdmatx != NULL) + { + /* Set the USART Tx DMA Abort callback to NULL : no callback + executed at end of DMA abort procedure */ + husart->hdmatx->XferAbortCallback = NULL; + + /* Abort DMA TX */ + (void)HAL_DMA_Abort_IT(husart->hdmatx); + } + + /* Abort the USART DMA Rx channel */ + if (husart->hdmarx != NULL) + { + /* Set the USART Rx DMA Abort callback : + will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */ + husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) + { + /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */ + husart->hdmarx->XferAbortCallback(husart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Call user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + + /* USART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) + { + if (husart->TxISR != NULL) + { + husart->TxISR(husart); + } + return; + } + + /* USART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + { + USART_EndTransmit_IT(husart); + return; + } + + /* USART TX Fifo Empty occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + husart->TxFifoEmptyCallback(husart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ + HAL_USARTEx_TxFifoEmptyCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + return; + } + + /* USART RX Fifo Full occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + husart->RxFifoFullCallback(husart); +#else + /* Call legacy weak Rx Fifo Full Callback */ + HAL_USARTEx_RxFifoFullCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_USART_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_USART_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_RxHalfCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Tx/Rx Transfers completed callback for the non-blocking process. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_TxRxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief USART error callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief USART Abort Complete callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions + * @brief USART Peripheral State and Error functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Return the USART handle state + (+) Return the USART handle error code + +@endverbatim + * @{ + */ + + +/** + * @brief Return the USART handle state. + * @param husart pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART. + * @retval USART handle state + */ +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart) +{ + return husart->State; +} + +/** + * @brief Return the USART error code. + * @param husart pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART. + * @retval USART handle Error Code + */ +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart) +{ + return husart->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Functions USART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param husart USART handle. + * @retval none + */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart) +{ + /* Init the USART Callback settings */ + husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ + husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ +} +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** + * @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion). + * @param husart USART handle. + * @retval None + */ +static void USART_EndTransfer(USART_HandleTypeDef *husart) +{ + /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + + /* At end of process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA USART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + /* Check if DMA in circular mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + husart->TxXferCount = 0U; + + if (husart->State == HAL_USART_STATE_BUSY_TX) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the USART CR3 register */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + } + } + /* DMA Circular mode */ + else + { + if (husart->State == HAL_USART_STATE_BUSY_TX) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Complete Callback */ + husart->TxCpltCallback(husart); +#else + /* Call legacy weak Tx Complete Callback */ + HAL_USART_TxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief DMA USART transmit process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Half Complete Callback */ + husart->TxHalfCpltCallback(husart); +#else + /* Call legacy weak Tx Half Complete Callback */ + HAL_USART_TxHalfCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART receive process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + /* Check if DMA in circular mode*/ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + husart->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit + in USART CR3 register */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + /* similarly, disable the DMA TX transfer that was started to provide the + clock to the slave device */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + if (husart->State == HAL_USART_STATE_BUSY_RX) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ + else + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + husart->State = HAL_USART_STATE_READY; + } + /* DMA circular mode */ + else + { + if (husart->State == HAL_USART_STATE_BUSY_RX) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ + else + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief DMA USART receive process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Half Complete Callback */ + husart->RxHalfCpltCallback(husart); +#else + /* Call legacy weak Rx Half Complete Callback */ + HAL_USART_RxHalfCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMAError(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + husart->RxXferCount = 0U; + husart->TxXferCount = 0U; + USART_EndTransfer(husart); + + husart->ErrorCode |= HAL_USART_ERROR_DMA; + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + husart->RxXferCount = 0U; + husart->TxXferCount = 0U; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + husart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (husart->hdmarx != NULL) + { + if (husart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ + HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +} + + +/** + * @brief DMA USART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + husart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (husart->hdmatx != NULL) + { + if (husart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ + HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Handle USART Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param husart USART handle. + * @param Flag Specifies the USART flag to check. + * @param Status the actual Flag status (SET or RESET). + * @param Tickstart Tick start value + * @param Timeout timeout duration. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Configure the USART peripheral. + * @param husart USART handle. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) +{ + uint32_t tmpreg; + USART_ClockSourceTypeDef clocksource; + HAL_StatusTypeDef ret = HAL_OK; + uint16_t brrtemp; + uint32_t usartdiv = 0x00000000; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); + assert_param(IS_USART_PHASE(husart->Init.CLKPhase)); + assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit)); + assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate)); + assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength)); + assert_param(IS_USART_STOPBITS(husart->Init.StopBits)); + assert_param(IS_USART_PARITY(husart->Init.Parity)); + assert_param(IS_USART_MODE(husart->Init.Mode)); + assert_param(IS_USART_PRESCALER(husart->Init.ClockPrescaler)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE and RE bits and configure + * the USART Word Length, Parity and Mode: + * set the M bits according to husart->Init.WordLength value + * set PCE and PS bits according to husart->Init.Parity value + * set TE and RE bits according to husart->Init.Mode value + * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */ + tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8; + MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*---------------------------- USART CR2 Configuration ---------------------*/ + /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits: + * set CPOL bit according to husart->Init.CLKPolarity value + * set CPHA bit according to husart->Init.CLKPhase value + * set LBCL bit according to husart->Init.CLKLastBit value (used in USART Synchronous SPI master mode only) + * set STOP[13:12] bits according to husart->Init.StopBits value */ + tmpreg = (uint32_t)(USART_CLOCK_ENABLE); + tmpreg |= (uint32_t)husart->Init.CLKLastBit; + tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase); + tmpreg |= (uint32_t)husart->Init.StopBits; + MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg); + + /*-------------------------- USART PRESC Configuration -----------------------*/ + /* Configure + * - USART Clock Prescaler : set PRESCALER according to husart->Init.ClockPrescaler value */ + MODIFY_REG(husart->Instance->PRESC, USART_PRESC_PRESCALER, husart->Init.ClockPrescaler); + + /*-------------------------- USART BRR Configuration -----------------------*/ + /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */ + USART_GETCLOCKSOURCE(husart, clocksource); + + switch (clocksource) + { + case USART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + case USART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + case USART_CLOCKSOURCE_HSI: + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + case USART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + case USART_CLOCKSOURCE_LSE: + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + default: + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 and smaller than or equal to ffff */ + if ((usartdiv >= USART_BRR_MIN) && (usartdiv <= USART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + husart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } + + /* Initialize the number of data to process during RX/TX ISR execution */ + husart->NbTxDataToProcess = 1U; + husart->NbRxDataToProcess = 1U; + + /* Clear ISR function pointers */ + husart->RxISR = NULL; + husart->TxISR = NULL; + + return ret; +} + +/** + * @brief Check the USART Idle State. + * @param husart USART handle. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) +{ + uint32_t tickstart; + + /* Initialize the USART ErrorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + /* Check if the Receiver is enabled */ + if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Initialize the USART state*/ + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is less than 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_8BIT(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + + /* Check that a Tx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + if (husart->TxXferCount == 0U) + { + /* Disable the USART Transmit data register empty interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + } + else + { + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF); + husart->pTxBuffPtr++; + husart->TxXferCount--; + } + } +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + const uint16_t *tmp; + + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + if (husart->TxXferCount == 0U) + { + /* Disable the USART Transmit data register empty interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + } + else + { + tmp = (const uint16_t *) husart->pTxBuffPtr; + husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); + husart->pTxBuffPtr += 2U; + husart->TxXferCount--; + } + } +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is less than 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (husart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + + break; /* force exit loop */ + } + else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) + { + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF); + husart->pTxBuffPtr++; + husart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + const uint16_t *tmp; + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (husart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + + break; /* force exit loop */ + } + else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) + { + tmp = (const uint16_t *) husart->pTxBuffPtr; + husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); + husart->pTxBuffPtr += 2U; + husart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief Wraps up transmission in non-blocking mode. + * @param husart Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +static void USART_EndTransmit_IT(USART_HandleTypeDef *husart) +{ + /* Disable the USART Transmit Complete Interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TC); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + + /* Clear TxISR function pointer */ + husart->TxISR = NULL; + + if (husart->State == HAL_USART_STATE_BUSY_TX) + { + /* Clear overrun flag and discard the received data */ + __HAL_USART_CLEAR_OREFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + + /* Tx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Complete Callback */ + husart->TxCpltCallback(husart); +#else + /* Call legacy weak Tx Complete Callback */ + HAL_USART_TxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if (husart->RxXferCount == 0U) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } +} + + +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is less than 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t uhMask = husart->Mask; + uint32_t txftie; + + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + husart->pRxBuffPtr++; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) + { + /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) + { + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && + (txdatacount == 0U)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + else + { + /* Nothing to do */ + } + } +} + +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t *tmp; + uint16_t uhMask = husart->Mask; + uint32_t txftie; + + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + tmp = (uint16_t *) husart->pRxBuffPtr; + *tmp = (uint16_t)(husart->Instance->RDR & uhMask); + husart->pRxBuffPtr += 2U; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) + { + /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) + { + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && + (txdatacount == 0U)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + else + { + /* Nothing to do */ + } + } +} + +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is less than 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t rxdatacount; + uint16_t uhMask = husart->Mask; + uint16_t nb_rx_data; + uint32_t txftie; + + /* Check that a Rx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) + { + if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET) + { + *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU)); + husart->pRxBuffPtr++; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) + { + /* Disable the USART Parity Error Interrupt */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) + { + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + state = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && + (txdatacount == 0U)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + state = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + else + { + /* Nothing to do */ + } + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = husart->RxXferCount; + if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess)) + { + /* Disable the USART RXFT interrupt*/ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + husart->RxISR = USART_RxISR_8BIT; + + /* Enable the USART Data Register Not Empty interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + + if ((husart->TxXferCount == 0U) && + (state == HAL_USART_STATE_BUSY_TX_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t rxdatacount; + uint16_t *tmp; + uint16_t uhMask = husart->Mask; + uint16_t nb_rx_data; + uint32_t txftie; + + /* Check that a Tx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) + { + if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET) + { + tmp = (uint16_t *) husart->pRxBuffPtr; + *tmp = (uint16_t)(husart->Instance->RDR & uhMask); + husart->pRxBuffPtr += 2U; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) + { + /* Disable the USART Parity Error Interrupt */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) + { + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + state = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && + (txdatacount == 0U)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + state = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + else + { + /* Nothing to do */ + } + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = husart->RxXferCount; + if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess)) + { + /* Disable the USART RXFT interrupt*/ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + husart->RxISR = USART_RxISR_16BIT; + + /* Enable the USART Data Register Not Empty interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + + if ((husart->TxXferCount == 0U) && + (state == HAL_USART_STATE_BUSY_TX_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @} + */ + +#endif /* HAL_USART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart_ex.c b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart_ex.c new file mode 100644 index 000000000..76535fd0d --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/Vendor/STM32CubeU5/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart_ex.c @@ -0,0 +1,657 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_usart_ex.c + * @author MCD Application Team + * @brief Extended USART HAL module driver. + * This file provides firmware functions to manage the following extended + * functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### USART peripheral extended features ##### + ============================================================================== + + (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + + -@- When USART operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be + configured prior starting RX/TX transfers. + + (#) Slave mode enabling/disabling and NSS pin configuration. + + -@- When USART operates in Slave mode, Slave mode must be enabled prior + starting RX/TX transfers. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup USARTEx USARTEx + * @brief USART Extended HAL module driver + * @{ + */ + +#ifdef HAL_USART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/** @defgroup USARTEx_Private_Constants USARTEx Private Constants + * @{ + */ +/* USART RX FIFO depth */ +#define RX_FIFO_DEPTH 8U + +/* USART TX FIFO depth */ +#define TX_FIFO_DEPTH 8U +/** + * @} + */ + +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup USARTEx_Private_Functions USARTEx Private Functions + * @{ + */ +static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USARTEx_Exported_Functions USARTEx Exported Functions + * @{ + */ + +/** @defgroup USARTEx_Exported_Functions_Group1 IO operation functions + * @brief Extended USART Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of FIFO mode related callback functions. + + (#) TX/RX Fifos Callbacks: + (+) HAL_USARTEx_RxFifoFullCallback() + (+) HAL_USARTEx_TxFifoEmptyCallback() + +@endverbatim + * @{ + */ + +/** + * @brief USART RX Fifo full callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USARTEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief USART TX Fifo empty callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USARTEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup USARTEx_Exported_Functions_Group2 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides the following functions: + (+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode + (+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode + (+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS) + (+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold + + +@endverbatim + * @{ + */ + +/** + * @brief Enable the SPI slave mode. + * @note When the USART operates in SPI slave mode, it handles data flow using + * the serial interface clock derived from the external SCLK signal + * provided by the external master SPI device. + * @note In SPI slave mode, the USART must be enabled before starting the master + * communications (or between frames while the clock is stable). Otherwise, + * if the USART slave is enabled while the master is in the middle of a + * frame, it will become desynchronized with the master. + * @note The data register of the slave needs to be ready before the first edge + * of the communication clock or before the end of the ongoing communication, + * otherwise the SPI slave will transmit zeros. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* In SPI slave mode mode, the following bits must be kept cleared: + - LINEN and CLKEN bit in the USART_CR2 register + - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + /* Enable SPI slave mode */ + SET_BIT(husart->Instance->CR2, USART_CR2_SLVEN); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->SlaveMode = USART_SLAVEMODE_ENABLE; + + husart->State = HAL_USART_STATE_READY; + + /* Enable USART */ + __HAL_USART_ENABLE(husart); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Disable the SPI slave mode. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Disable SPI slave mode */ + CLEAR_BIT(husart->Instance->CR2, USART_CR2_SLVEN); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->SlaveMode = USART_SLAVEMODE_DISABLE; + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Configure the Slave Select input pin (NSS). + * @note Software NSS management: SPI slave will always be selected and NSS + * input pin will be ignored. + * @note Hardware NSS management: the SPI slave selection depends on NSS + * input pin. The slave is selected when NSS is low and deselected when + * NSS is high. + * @param husart USART handle. + * @param NSSConfig NSS configuration. + * This parameter can be one of the following values: + * @arg @ref USART_NSS_HARD + * @arg @ref USART_NSS_SOFT + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); + assert_param(IS_USART_NSS(NSSConfig)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Program DIS_NSS bit in the USART_CR2 register */ + MODIFY_REG(husart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Enable the FIFO mode. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + husart->FifoMode = USART_FIFOMODE_ENABLE; + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + /* Determine the number of data to process during RX/TX ISR execution */ + USARTEx_SetNbDataToProcess(husart); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Disable the FIFO mode. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Disable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + husart->FifoMode = USART_FIFOMODE_DISABLE; + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Set the TXFIFO threshold. + * @param husart USART handle. + * @param Threshold TX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref USART_TXFIFO_THRESHOLD_1_8 + * @arg @ref USART_TXFIFO_THRESHOLD_1_4 + * @arg @ref USART_TXFIFO_THRESHOLD_1_2 + * @arg @ref USART_TXFIFO_THRESHOLD_3_4 + * @arg @ref USART_TXFIFO_THRESHOLD_7_8 + * @arg @ref USART_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + assert_param(IS_USART_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Update TX threshold configuration */ + MODIFY_REG(husart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + USARTEx_SetNbDataToProcess(husart); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Set the RXFIFO threshold. + * @param husart USART handle. + * @param Threshold RX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref USART_RXFIFO_THRESHOLD_1_8 + * @arg @ref USART_RXFIFO_THRESHOLD_1_4 + * @arg @ref USART_RXFIFO_THRESHOLD_1_2 + * @arg @ref USART_RXFIFO_THRESHOLD_3_4 + * @arg @ref USART_RXFIFO_THRESHOLD_7_8 + * @arg @ref USART_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check the parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + assert_param(IS_USART_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Update RX threshold configuration */ + MODIFY_REG(husart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + USARTEx_SetNbDataToProcess(husart); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Set autonomous mode Configuration. + * @param husart USART handle. + * @param sConfig Autonomous mode structure parameters. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_SetConfigAutonomousMode(USART_HandleTypeDef *husart, + const USART_AutonomousModeConfTypeDef *sConfig) +{ + uint32_t tmpreg; + + if (husart->State == HAL_USART_STATE_READY) + { + /* Check the parameters */ + assert_param(IS_USART_TRIGGER_POLARITY(sConfig->TriggerPolarity)); + assert_param(IS_USART_IDLE_FRAME_TRANSMIT(sConfig->IdleFrame)); + assert_param(IS_USART_TX_DATA_SIZE(sConfig->DataSize)); + assert_param(IS_USART_TRIGGER_SELECTION(sConfig->TriggerSelection)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Disable Transmitter */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_TE); + + /* Clear AUTOCR register */ + CLEAR_REG(husart->Instance->AUTOCR); + + /* USART AUTOCR Configuration */ + tmpreg = ((sConfig->DataSize << USART_AUTOCR_TDN_Pos) | (sConfig->TriggerPolarity) | + (sConfig->AutonomousModeState) | (sConfig->IdleFrame) | + (sConfig->TriggerSelection << USART_AUTOCR_TRIGSEL_Pos)); + + WRITE_REG(husart->Instance->AUTOCR, tmpreg); + + /* Enable USART */ + __HAL_USART_ENABLE(husart); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Get autonomous mode Configuration. + * @param husart USART handle. + * @param sConfig Autonomous mode structure parameters. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_GetConfigAutonomousMode(const USART_HandleTypeDef *husart, + USART_AutonomousModeConfTypeDef *sConfig) +{ + uint32_t tmpreg; + + /* Read AUTOCR register */ + tmpreg = READ_REG(husart->Instance->AUTOCR); + + /* Fill Autonomous structure parameter */ + sConfig->AutonomousModeState = (tmpreg & USART_AUTOCR_TRIGEN); + sConfig->TriggerSelection = ((tmpreg & USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos); + sConfig->TriggerPolarity = (tmpreg & USART_AUTOCR_TRIGPOL); + sConfig->IdleFrame = (tmpreg & USART_AUTOCR_IDLEDIS); + sConfig->DataSize = (tmpreg & USART_AUTOCR_TDN); + + return HAL_OK; +} + +/** + * @brief Clear autonomous mode Configuration. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_ClearConfigAutonomousMode(USART_HandleTypeDef *husart) +{ + if (husart->State == HAL_USART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Clear AUTOCR register */ + CLEAR_REG(husart->Instance->AUTOCR); + + /* Enable USART */ + __HAL_USART_ENABLE(husart); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup USARTEx_Private_Functions + * @{ + */ + +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @note The RX FIFO depth and the TX FIFO depth is extracted from + * the USART configuration registers. + * @param husart USART handle. + * @retval None + */ +static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + + if (husart->FifoMode == USART_FIFOMODE_DISABLE) + { + husart->NbTxDataToProcess = 1U; + husart->NbRxDataToProcess = 1U; + } + else + { + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; + rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, + USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU); + tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, + USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU); + husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; + } +} +/** + * @} + */ + +#endif /* HAL_USART_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/tests/functional/stm32/nucleo_u545re_q/nucleo-u5xx.cfg b/tests/functional/stm32/nucleo_u545re_q/nucleo-u5xx.cfg new file mode 100644 index 000000000..7afa1fbc4 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/nucleo-u5xx.cfg @@ -0,0 +1,15 @@ +# Interface: Use the DAP version for ST-LINK/V3 (Critical for U5) +source [find interface/stlink.cfg] + +# Transport: Use DAP Direct SWD (Replaces hla_swd) +transport select swd + +# Target: Use the built-in script from xPack +# (It contains the correct flash driver settings for U5 automatically) +source [find target/stm32u5x.cfg] + +# Reset Config: Connect under reset to prevent locking up +reset_config srst_only srst_nogate connect_assert_srst + +# Optional: If you want to force a lower speed to be safe +adapter speed 4000 \ No newline at end of file diff --git a/tests/functional/stm32/nucleo_u545re_q/run_test.sh b/tests/functional/stm32/nucleo_u545re_q/run_test.sh new file mode 100755 index 000000000..6f3009339 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/run_test.sh @@ -0,0 +1,123 @@ +#!/usr/bin/env bash + +BINARY_PATH="$1" +STLINK_SERIAL_NUMBER="$2" + +# Get the directory where this script is located. +SCRIPT_DIR=$(cd -- "$(dirname -- "$0")" &> /dev/null && pwd) + +if [ -z "$BINARY_PATH" ]; then + echo "libtropic u545re_q script for flashing and running tests" + echo "usage: ./run_test.sh PATH_TO_BINARY [STLINK_SERIAL_NUMBER]" + exit 1 +fi + +if [ -z "$STLINK_SERIAL_NUMBER" ]; then + echo "No STLink serial number provided, trying to autodiscover STLink UART..." + DEV=$(find /dev/serial/by-id/ -type l -iname "usb-STMicroelectronics_STM32_STLink_*" | head -n1) + + if [ $? -ne 0 ]; then + echo "No STLinks discovered. Please provide path manually." + exit 1 + fi + + echo "Using autodiscovered STLink UART: $DEV" +else + echo "Using STLink serial number: $STLINK_SERIAL_NUMBER" + echo "Looking for corresponding UART device..." + + # We are looking for either link (usually on bare metal, link points to /dev/ttyX) or a character device + # (usually in Docker when the device connected to host is passed through). + DEV=$(find /dev/serial/by-id/ \( -type l -o -type c \) -iname "*${STLINK_SERIAL_NUMBER}*" | head -n1) + + if ! ls "$DEV"; then + echo "Cannot open UART of ST-Link with serial number $STLINK_SERIAL_NUMBER, terminating." + exit 1 + fi + + echo "Using UART device: $DEV" +fi + +BAUD="115200" +SENTINEL_OK="TEST FINISHED" +SENTINEL_FAIL_1="ASSERT FAIL" +SENTINEL_FAIL_2="WARNING" +SENTINEL_FAIL_3="ERROR" + +set -euo pipefail + +# Configure serial port +stty -F "$DEV" "$BAUD" \ + cs8 -cstopb -parenb \ + -ixon -ixoff -crtscts \ + -icanon -echo -echoe -echok -echoctl -echoke \ + -icrnl -inlcr -igncr -opost min 1 time 0 + +serial_reader() { + GOT_ERROR=0 + exec 3<"$DEV" + while IFS= read -t 60 -r -u 3 line; do + printf 'STM32: %s\n' "$line" + + if [[ "$line" == *"$SENTINEL_FAIL_1"* ]] \ + || [[ "$line" == *"$SENTINEL_FAIL_2"* ]] \ + || [[ "$line" == *"$SENTINEL_FAIL_3"* ]]; then + GOT_ERROR=1 + elif [[ "$line" == *"$SENTINEL_OK"* ]]; then + return $GOT_ERROR + fi + done + return 2 # Timeout or serial read error +} + +# Start serial reading in background +serial_reader & +READER_PID=$! + +# Ensure the background serial reader is killed on script termination +cleanup() { + if [ -n "${READER_PID:-}" ]; then + if kill -0 "$READER_PID" 2>/dev/null; then + kill "$READER_PID" 2>/dev/null || true + wait "$READER_PID" 2>/dev/null || true + fi + fi +} + +# On Ctrl+C or TERM, kill the reader and exit with 130. Always run cleanup on EXIT. +trap 'cleanup; exit 130' INT TERM +trap 'cleanup' EXIT + +# ---- Flash the device ---- +if [ -z "$STLINK_SERIAL_NUMBER" ]; then + echo "OpenOCD will autodiscover STLink programming interface." + openocd -f "$SCRIPT_DIR/nucleo-u5xx.cfg" \ + -c "gdb_port disabled" \ + -c "telnet_port disabled" \ + -c "tcl_port disabled" \ + -c "program $BINARY_PATH verify reset exit" +else + echo "OpenOCD will use STLink serial number $STLINK_SERIAL_NUMBER for programming." + openocd -f "$SCRIPT_DIR/nucleo-u5xx.cfg" \ + -c "gdb_port disabled" \ + -c "telnet_port disabled" \ + -c "tcl_port disabled" \ + -c "adapter serial $STLINK_SERIAL_NUMBER" \ + -c "program $BINARY_PATH verify reset exit" +fi + +# ---- Wait for serial reader to finish ---- +set +e +wait $READER_PID +EXIT_CODE=$? +set -e + +if [ $EXIT_CODE -eq 0 ]; then + echo "Test finished successfully." +elif [ $EXIT_CODE -eq 1 ]; then + echo "Test failed." +else + echo "Serial read error or timeout." +fi + +exit $EXIT_CODE diff --git a/tests/functional/stm32/nucleo_u545re_q/toolchain.cmake b/tests/functional/stm32/nucleo_u545re_q/toolchain.cmake new file mode 100644 index 000000000..c25db3310 --- /dev/null +++ b/tests/functional/stm32/nucleo_u545re_q/toolchain.cmake @@ -0,0 +1,31 @@ +# Name of the target +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR cortex-m33) + +set(MCPU_FLAGS "-mthumb -mcpu=cortex-m33") +set(VFP_FLAGS "") + +# Toolchain settings +set(CMAKE_C_COMPILER arm-none-eabi-gcc) +set(CMAKE_CXX_COMPILER arm-none-eabi-g++) +set(AS arm-none-eabi-as) +set(AR arm-none-eabi-ar) +set(OBJCOPY arm-none-eabi-objcopy) +set(OBJDUMP arm-none-eabi-objdump) +set(SIZE arm-none-eabi-size) + +set(CMAKE_C_FLAGS "-O2 ${MCPU_FLAGS} ${VFP_FLAGS} -Wall -fno-builtin -g -std=gnu11 -fdata-sections -ffunction-sections" CACHE INTERNAL "c compiler flags") +set(CMAKE_CXX_FLAGS "${MCPU_FLAGS} ${VFP_FLAGS} -Wall -fno-builtin -fdata-sections -ffunction-sections" CACHE INTERNAL "cxx compiler flags") +set(CMAKE_ASM_FLAGS "${MCPU_FLAGS} -x assembler-with-cpp" CACHE INTERNAL "asm compiler flags") + +SET(CMAKE_C_FLAGS_DEBUG "-O0 -g -ggdb3" CACHE INTERNAL "c debug compiler flags") +SET(CMAKE_CXX_FLAGS_DEBUG "-O0 -g -ggdb3" CACHE INTERNAL "cxx debug compiler flags") +SET(CMAKE_ASM_FLAGS_DEBUG "-g -ggdb3" CACHE INTERNAL "asm debug compiler flags") + +SET(CMAKE_C_FLAGS_RELEASE "-O2 -g -ggdb3" CACHE INTERNAL "c release compiler flags") +SET(CMAKE_CXX_FLAGS_RELEASE "-O2 -g -ggdb3" CACHE INTERNAL "cxx release compiler flags") +SET(CMAKE_ASM_FLAGS_RELEASE "" CACHE INTERNAL "asm release compiler flags") + +# omit -nostartfiles when using __libc_init_array +set(LD_FLAGS "-T ${LINKER_SCRIPT}") +set(CMAKE_EXE_LINKER_FLAGS "${MCPU_FLAGS} ${LD_FLAGS} -Wl,--gc-sections" CACHE INTERNAL "exe link flags") diff --git a/tests/functional_mock/CMakeLists.txt b/tests/functional_mock/CMakeLists.txt index 9f63c8f85..662733dfe 100644 --- a/tests/functional_mock/CMakeLists.txt +++ b/tests/functional_mock/CMakeLists.txt @@ -116,6 +116,7 @@ set(LIBTROPIC_MOCK_TEST_LIST lt_test_mock_attrs lt_test_mock_invalid_in_crc lt_test_mock_hardware_fail + lt_test_mock_invalid_app_fw_init ) ########################################################################### diff --git a/tests/functional_mock/helpers/lt_mock_helpers.c b/tests/functional_mock/helpers/lt_mock_helpers.c index f0b4c40b2..c49731d0d 100644 --- a/tests/functional_mock/helpers/lt_mock_helpers.c +++ b/tests/functional_mock/helpers/lt_mock_helpers.c @@ -3,7 +3,7 @@ * @brief Helper functions for functional mock tests. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include "lt_mock_helpers.h" @@ -26,7 +26,8 @@ void add_resp_crc(void *resp_buf) uint8_t *resp_buf_bytes = (uint8_t *)resp_buf; // CRC is calculated from STATUS, RSP_LEN and RSP_DATA, skipping CHIP_STATUS. - uint16_t resp_len = TR01_L2_STATUS_SIZE + TR01_L2_REQ_RSP_LEN_SIZE + resp_buf_bytes[TR01_L2_RSP_LEN_OFFSET]; + uint16_t resp_len = TR01_L2_STATUS_SIZE + TR01_L2_REQ_RSP_LEN_SIZE + + resp_buf_bytes[TR01_L2_RSP_LEN_OFFSET]; uint16_t crc = crc16(resp_buf_bytes + TR01_L1_CHIP_STATUS_SIZE, resp_len); // Append CRC at the end of the response buffer. @@ -39,8 +40,8 @@ size_t calc_mocked_resp_len(const void *resp_buf) const uint8_t *resp_buf_bytes = (const uint8_t *)resp_buf; // Total length is CHIP_STATUS + STATUS + RSP_LEN + RSP_DATA + CRC - return TR01_L1_CHIP_STATUS_SIZE + TR01_L2_STATUS_SIZE + TR01_L2_REQ_RSP_LEN_SIZE - + resp_buf_bytes[TR01_L2_RSP_LEN_OFFSET] + TR01_L2_REQ_RSP_CRC_SIZE; + return TR01_L1_CHIP_STATUS_SIZE + TR01_L2_STATUS_SIZE + TR01_L2_REQ_RSP_LEN_SIZE + + resp_buf_bytes[TR01_L2_RSP_LEN_OFFSET] + TR01_L2_REQ_RSP_CRC_SIZE; } lt_ret_t mock_init_communication(lt_handle_t *h, const uint8_t riscv_fw_ver[4]) @@ -65,8 +66,8 @@ lt_ret_t mock_init_communication(lt_handle_t *h, const uint8_t riscv_fw_ver[4]) add_resp_crc(&get_info_resp); // Mock response data for Get_Info, for both L2 Response. - if (LT_OK - != lt_mock_hal_enqueue_response(&h->l2, (uint8_t *)&get_info_resp, calc_mocked_resp_len(&get_info_resp))) { + if (LT_OK != lt_mock_hal_enqueue_response(&h->l2, (uint8_t *)&get_info_resp, + calc_mocked_resp_len(&get_info_resp))) { return LT_FAIL; } @@ -77,8 +78,8 @@ lt_ret_t mock_session_start(lt_handle_t *h, const uint8_t kcmd[TR01_AES256_KEY_L const uint8_t kres[TR01_AES256_KEY_LEN]) { // Check if kcmd and kres are equal. - // This is needed so we can reuse AES-GCM functions currently provided by CAL and not having to reinitialize AES - // with swapped encryption and decryption keys every time. + // This is needed so we can reuse AES-GCM functions currently provided by CAL and not having to + // reinitialize AES with swapped encryption and decryption keys every time. if (memcmp(kcmd, kres, TR01_AES256_KEY_LEN) != 0) { LT_LOG_ERROR("kcmd and kres have to match for L3 mocking to work (simplification)."); return LT_PARAM_ERR; @@ -110,22 +111,26 @@ lt_ret_t mock_session_abort(lt_handle_t *h) return LT_OK; } -lt_ret_t mock_l3_result(lt_handle_t *h, const uint8_t *result_plaintext, const size_t result_plaintext_size) +lt_ret_t mock_l3_result(lt_handle_t *h, const uint8_t *result_plaintext, + const size_t result_plaintext_size) { uint8_t l2_frame[TR01_L2_MAX_FRAME_SIZE]; size_t packet_size = TR01_L3_SIZE_SIZE + result_plaintext_size + TR01_L3_TAG_SIZE; - size_t frame_size = TR01_L1_CHIP_STATUS_SIZE + TR01_L2_STATUS_SIZE + TR01_L2_REQ_RSP_LEN_SIZE + packet_size - + TR01_L2_REQ_RSP_CRC_SIZE; + size_t frame_size = TR01_L1_CHIP_STATUS_SIZE + TR01_L2_STATUS_SIZE + TR01_L2_REQ_RSP_LEN_SIZE + + packet_size + TR01_L2_REQ_RSP_CRC_SIZE; if (packet_size > TR01_L2_CHUNK_MAX_DATA_SIZE) { - LT_LOG_ERROR("Payloads >%u B not supported due to chunking not implemented.", TR01_L2_CHUNK_MAX_DATA_SIZE); + LT_LOG_ERROR("Payloads >%u B not supported due to chunking not implemented.", + TR01_L2_CHUNK_MAX_DATA_SIZE); return LT_PARAM_ERR; } // This will happen only if the internal macros are implemented incorrectly. if (frame_size > TR01_L2_MAX_FRAME_SIZE) { - LT_LOG_ERROR("Implementation error! Total frame size won't fit to the buffer. Need at least: %zu", frame_size); + LT_LOG_ERROR( + "Implementation error! Total frame size won't fit to the buffer. Need at least: %zu", + frame_size); return LT_FAIL; } @@ -136,20 +141,19 @@ lt_ret_t mock_l3_result(lt_handle_t *h, const uint8_t *result_plaintext, const s l2_frame[TR01_L2_RSP_DATA_RSP_CRC_OFFSET] = result_plaintext_size; l2_frame[TR01_L2_RSP_DATA_RSP_CRC_OFFSET + 1] = 0x00; - lt_ret_t ret; - if (LT_OK - != (ret - = lt_aesgcm_encrypt(h->l3.crypto_ctx, h->l3.decryption_IV, TR01_L3_IV_SIZE, NULL, 0, result_plaintext, - result_plaintext_size, &l2_frame[TR01_L2_RSP_DATA_RSP_CRC_OFFSET + TR01_L3_SIZE_SIZE], - result_plaintext_size + TR01_L3_TAG_SIZE))) { + lt_ret_t ret = lt_aesgcm_encrypt(h->l3.crypto_ctx, h->l3.decryption_IV, TR01_L3_IV_SIZE, NULL, 0, + result_plaintext, result_plaintext_size, + &l2_frame[TR01_L2_RSP_DATA_RSP_CRC_OFFSET + TR01_L3_SIZE_SIZE], + result_plaintext_size + TR01_L3_TAG_SIZE); + if (LT_OK != ret) { LT_LOG_ERROR("Encryption failed! ret=%d", ret); return ret; } - // As the mock helpers share CAL interface with Libtropic (simplification), IV is handled in the Libtropic itself -> - // no need to increment here. + // As the mock helpers share CAL interface with Libtropic (simplification), IV is handled in the + // Libtropic itself -> no need to increment here. - uint16_t crc - = crc16(&l2_frame[TR01_L2_STATUS_OFFSET], TR01_L2_STATUS_SIZE + TR01_L2_REQ_RSP_LEN_SIZE + packet_size); + uint16_t crc = crc16(&l2_frame[TR01_L2_STATUS_OFFSET], + TR01_L2_STATUS_SIZE + TR01_L2_REQ_RSP_LEN_SIZE + packet_size); size_t crc_offset = TR01_L2_RSP_DATA_RSP_CRC_OFFSET + packet_size; l2_frame[crc_offset] = crc >> 8; l2_frame[crc_offset + 1] = crc & 0x00FF; diff --git a/tests/functional_mock/helpers/lt_mock_helpers.h b/tests/functional_mock/helpers/lt_mock_helpers.h index 5b544b336..2c20403e4 100644 --- a/tests/functional_mock/helpers/lt_mock_helpers.h +++ b/tests/functional_mock/helpers/lt_mock_helpers.h @@ -6,7 +6,7 @@ * @brief Helper functions for functional mock tests. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -20,14 +20,14 @@ extern "C" { /** * @brief Adds CRC16 to the end of the mocked response buffer. * - * @param resp_buf Pointer to the response buffer where CRC will be appended. The buffer must have enough space for the - * CRC (2 bytes). + * @param resp_buf Pointer to the response buffer where CRC will be appended. The buffer must have + * enough space for the CRC (2 bytes). */ void add_resp_crc(void *resp_buf); /** - * @brief Calculates the total length of a mocked response buffer, including CHIP_STATUS, STATUS, RSP_LEN, RSP_DATA, and - * CRC. + * @brief Calculates the total length of a mocked response buffer, including CHIP_STATUS, STATUS, + * RSP_LEN, RSP_DATA, and CRC. * * @param resp_buf Pointer to the response buffer. * @return size_t Total length of the mocked response buffer. @@ -37,10 +37,10 @@ size_t calc_mocked_resp_len(const void *resp_buf); /** * @brief Mock all data required to initialize Libtropic with lt_init(). * - * @details Currently, lt_init() initializes attributes based on the Application FW version running on TROPIC01. - * The version is obtained from the chip. This function mocks the necessary responses to simulate a specific FW version. - * As this operation needs to be done in each test that does any communication, this helper function is provided to - * simplify the process. + * @details Currently, lt_init() initializes attributes based on the Application FW version running on + * TROPIC01. The version is obtained from the chip. This function mocks the necessary responses to + * simulate a specific FW version. As this operation needs to be done in each test that does any + * communication, this helper function is provided to simplify the process. * * @param h Pointer to the lt_handle_t structure. * @param riscv_fw_ver Array representing the desired RISC-V FW version to mock. @@ -96,14 +96,17 @@ lt_ret_t mock_session_abort(lt_handle_t *h); * * @return LT_OK on success, or an appropriate lt_ret_t error code on failure. */ -lt_ret_t mock_l3_result(lt_handle_t *h, const uint8_t *result_plaintext, const size_t result_plaintext_size); +lt_ret_t mock_l3_result(lt_handle_t *h, const uint8_t *result_plaintext, + const size_t result_plaintext_size); /** * @brief Mock replies to a L3 Command. * * There are two types of replies from TROPIC01 to each L3 Command chunk: - * 1. reply to writing the chunk (using Encrypted_Cmd_Req L2 Request) -> only CHIP_READY (as to other L2 Requests) - * 2. reply to Get_Response -> L2 Response with status REQ_OK (last chunk) or REQ_CONT (not the last chunk) + * 1. reply to writing the chunk (using Encrypted_Cmd_Req L2 Request) -> only CHIP_READY (as to other + * L2 Requests) + * 2. reply to Get_Response -> L2 Response with status REQ_OK (last chunk) or REQ_CONT (not the last + * chunk) * * @param h Pointer to an lt_handle_t to use (for encryption and enqueuing). * @param chunk_count Count of the L3 Command chunks. Only single chunk supported now. diff --git a/tests/functional_mock/lt_functional_mock_tests.h b/tests/functional_mock/lt_functional_mock_tests.h index a4f632065..f877d2ce9 100644 --- a/tests/functional_mock/lt_functional_mock_tests.h +++ b/tests/functional_mock/lt_functional_mock_tests.h @@ -6,7 +6,7 @@ * @brief Declaration of functional mock test functions. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include "libtropic_common.h" @@ -46,15 +46,27 @@ void lt_test_mock_invalid_in_crc(lt_handle_t *h); * * Test steps: * 1. Mock Secure Session initialization. - * 2. For each of Pairing_Key_Write, Pairing_Key_Invalidate, R_Config_Write, I_Config_Write, R_Mem_Data_Write: - * a. Mock L3 Result with RESULT=HARDWARE_FAIL. - * b. Call Libtropic function corresponding to the L3 Command and verify that Libtropic returns LT_L3_HARDWARE_FAIL. + * 2. For each of Pairing_Key_Write, Pairing_Key_Invalidate, R_Config_Write, I_Config_Write, + * R_Mem_Data_Write: a. Mock L3 Result with RESULT=HARDWARE_FAIL. b. Call Libtropic function + * corresponding to the L3 Command and verify that Libtropic returns LT_L3_HARDWARE_FAIL. * 3. Mock Secure Session deinitialization. * * @param h Handle for communication with TROPIC01 */ void lt_test_mock_hardware_fail(lt_handle_t *h); +/** + * @brief Test for checking that lt_init suceeds if Application FW cannot be booted. + * + * Test steps: + * 1. Mock responses to simulate a scenario where Application FW cannot be booted, i.e. TROPIC01 stays + * in Start-up Mode. + * 2. Call lt_init and verify that it succeeds. + * + * @param h Handle for communication with TROPIC01 + */ +void lt_test_mock_invalid_app_fw_init(lt_handle_t *h); + #ifdef __cplusplus } #endif diff --git a/tests/functional_mock/lt_test_mock_attrs.c b/tests/functional_mock/lt_test_mock_attrs.c index bdd586390..8c6f3e262 100644 --- a/tests/functional_mock/lt_test_mock_attrs.c +++ b/tests/functional_mock/lt_test_mock_attrs.c @@ -3,7 +3,7 @@ * @brief Test for checking if TROPIC01 attributes are set correctly based on RISC-V FW version. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -38,8 +38,10 @@ void lt_test_mock_attrs(lt_handle_t *h) }; for (size_t i = 0; i < sizeof(riscv_fw_ver_resp) / sizeof(riscv_fw_ver_resp[0]); i++) { - LT_LOG_INFO("Testing with mocked RISC-V FW version: %" PRIu8 ".%" PRIu8 ".%" PRIu8 ".%" PRIu8 "", - riscv_fw_ver_resp[i][3], riscv_fw_ver_resp[i][2], riscv_fw_ver_resp[i][1], riscv_fw_ver_resp[i][0]); + LT_LOG_INFO("Testing with mocked RISC-V FW version: %" PRIu8 ".%" PRIu8 ".%" PRIu8 ".%" PRIu8 + "", + riscv_fw_ver_resp[i][3], riscv_fw_ver_resp[i][2], riscv_fw_ver_resp[i][1], + riscv_fw_ver_resp[i][0]); lt_mock_hal_reset(&h->l2); LT_LOG_INFO("Mocking initialization..."); diff --git a/tests/functional_mock/lt_test_mock_hardware_fail.c b/tests/functional_mock/lt_test_mock_hardware_fail.c index bea002b39..41270c6dc 100644 --- a/tests/functional_mock/lt_test_mock_hardware_fail.c +++ b/tests/functional_mock/lt_test_mock_hardware_fail.c @@ -3,7 +3,7 @@ * @brief Test HARDWARE_FAIL L3 Result handling. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include @@ -59,7 +59,8 @@ void lt_test_mock_hardware_fail(lt_handle_t *h) uint8_t pairing_key_write_plaintext[] = { TR01_L3_RESULT_HARDWARE_FAIL, }; - LT_TEST_ASSERT(LT_OK, mock_l3_result(h, pairing_key_write_plaintext, sizeof(pairing_key_write_plaintext))); + LT_TEST_ASSERT(LT_OK, mock_l3_result(h, pairing_key_write_plaintext, + sizeof(pairing_key_write_plaintext))); LT_TEST_ASSERT(LT_OK, lt_random_bytes(h, dummy_key, sizeof(dummy_key))); LT_TEST_ASSERT(LT_L3_HARDWARE_FAIL, lt_pairing_key_write(h, dummy_key, slot)); @@ -77,8 +78,8 @@ void lt_test_mock_hardware_fail(lt_handle_t *h) uint8_t pairing_key_invalidate_plaintext[] = { TR01_L3_RESULT_HARDWARE_FAIL, }; - LT_TEST_ASSERT(LT_OK, - mock_l3_result(h, pairing_key_invalidate_plaintext, sizeof(pairing_key_invalidate_plaintext))); + LT_TEST_ASSERT(LT_OK, mock_l3_result(h, pairing_key_invalidate_plaintext, + sizeof(pairing_key_invalidate_plaintext))); LT_TEST_ASSERT(LT_L3_HARDWARE_FAIL, lt_pairing_key_invalidate(h, slot)); } @@ -92,8 +93,10 @@ void lt_test_mock_hardware_fail(lt_handle_t *h) uint8_t r_config_write_plaintext[] = { TR01_L3_RESULT_HARDWARE_FAIL, }; - LT_TEST_ASSERT(LT_OK, mock_l3_result(h, r_config_write_plaintext, sizeof(r_config_write_plaintext))); - LT_TEST_ASSERT(LT_L3_HARDWARE_FAIL, lt_r_config_write(h, TR01_CFG_START_UP_ADDR, 0x00)); // Dummy object + LT_TEST_ASSERT(LT_OK, + mock_l3_result(h, r_config_write_plaintext, sizeof(r_config_write_plaintext))); + LT_TEST_ASSERT(LT_L3_HARDWARE_FAIL, + lt_r_config_write(h, TR01_CFG_START_UP_ADDR, 0x00)); // Dummy object // ---------------------------------------------------------------------------------------------------------- @@ -105,8 +108,10 @@ void lt_test_mock_hardware_fail(lt_handle_t *h) uint8_t i_config_write_plaintext[] = { TR01_L3_RESULT_HARDWARE_FAIL, }; - LT_TEST_ASSERT(LT_OK, mock_l3_result(h, i_config_write_plaintext, sizeof(i_config_write_plaintext))); - LT_TEST_ASSERT(LT_L3_HARDWARE_FAIL, lt_i_config_write(h, TR01_CFG_START_UP_ADDR, 0x00)); // Dummy object + LT_TEST_ASSERT(LT_OK, + mock_l3_result(h, i_config_write_plaintext, sizeof(i_config_write_plaintext))); + LT_TEST_ASSERT(LT_L3_HARDWARE_FAIL, + lt_i_config_write(h, TR01_CFG_START_UP_ADDR, 0x00)); // Dummy object // ---------------------------------------------------------------------------------------------------------- @@ -118,15 +123,17 @@ void lt_test_mock_hardware_fail(lt_handle_t *h) uint8_t r_mem_data_write_plaintext[] = { TR01_L3_RESULT_HARDWARE_FAIL, }; - LT_TEST_ASSERT(LT_OK, mock_l3_result(h, r_mem_data_write_plaintext, sizeof(r_mem_data_write_plaintext))); + LT_TEST_ASSERT(LT_OK, + mock_l3_result(h, r_mem_data_write_plaintext, sizeof(r_mem_data_write_plaintext))); uint16_t random_r_mem_slot; LT_TEST_ASSERT(LT_OK, lt_random_bytes(h, &random_r_mem_slot, sizeof(random_r_mem_slot))); random_r_mem_slot %= TR01_R_MEM_DATA_SLOT_MAX + 1; - uint8_t random_r_mem_data[16]; // Arbitrary size. Exact number not important, we just need some dummy data. + uint8_t random_r_mem_data[16]; // Arbitrary size. Exact number not important, we just need some + // dummy data. LT_TEST_ASSERT(LT_OK, lt_random_bytes(h, random_r_mem_data, sizeof(random_r_mem_data))); - LT_TEST_ASSERT(LT_L3_HARDWARE_FAIL, - lt_r_mem_data_write(h, random_r_mem_slot, random_r_mem_data, sizeof(random_r_mem_data))); + LT_TEST_ASSERT(LT_L3_HARDWARE_FAIL, lt_r_mem_data_write(h, random_r_mem_slot, random_r_mem_data, + sizeof(random_r_mem_data))); // ---------------------------------------------------------------------------------------------------------- diff --git a/tests/functional_mock/lt_test_mock_invalid_app_fw_init.c b/tests/functional_mock/lt_test_mock_invalid_app_fw_init.c new file mode 100644 index 000000000..aebcab506 --- /dev/null +++ b/tests/functional_mock/lt_test_mock_invalid_app_fw_init.c @@ -0,0 +1,62 @@ +/** + * @file lt_test_mock_invalid_app_fw_init.c + * @brief Test for checking that lt_init suceeds if Application FW cannot be booted. + * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. + * + * @license For the license see LICENSE.md in the root directory of this source tree. + */ + +#include "libtropic.h" +#include "libtropic_common.h" +#include "libtropic_logging.h" +#include "libtropic_port_mock.h" +#include "lt_functional_mock_tests.h" +#include "lt_l1.h" +#include "lt_l2_api_structs.h" +#include "lt_l2_frame_check.h" +#include "lt_mock_helpers.h" +#include "lt_test_common.h" + +void lt_test_mock_invalid_app_fw_init(lt_handle_t *h) +{ + LT_LOG_INFO("----------------------------------------------"); + LT_LOG_INFO("lt_test_mock_invalid_app_fw_init()"); + LT_LOG_INFO("----------------------------------------------"); + + const uint8_t chip_startup_mode = (TR01_L1_CHIP_MODE_READY_bit | TR01_L1_CHIP_MODE_STARTUP_bit); + const uint8_t lt_get_tr01_mode_mocked_response[] = {chip_startup_mode, TR01_L2_STATUS_NO_RESP}; + + lt_mock_hal_reset(&h->l2); + + // 1. Mock lt_init() -> lt_get_tr01_mode() response. + LT_LOG_INFO("Mocking Get_Response response..."); + LT_TEST_ASSERT(LT_OK, lt_mock_hal_enqueue_response(&h->l2, lt_get_tr01_mode_mocked_response, + sizeof(lt_get_tr01_mode_mocked_response))); + + // 2. Mock lt_init() -> lt_reboot() response. + LT_LOG_INFO("Mocking Startup_Req response..."); + struct lt_l2_startup_rsp_t startup_req_resp = { + .chip_status = (TR01_L1_CHIP_MODE_READY_bit | TR01_L1_CHIP_MODE_STARTUP_bit), // Start-up Mode + .status = TR01_L2_STATUS_REQUEST_OK, + .rsp_len = TR01_L2_STARTUP_RSP_LEN, + .crc = {0} // CRC added below. + }; + // Add CRC to the Startup_Req response. + add_resp_crc(&startup_req_resp); + + LT_TEST_ASSERT( + LT_OK, lt_mock_hal_enqueue_response(&h->l2, &chip_startup_mode, sizeof(chip_startup_mode))); + LT_TEST_ASSERT(LT_OK, lt_mock_hal_enqueue_response(&h->l2, (uint8_t *)&startup_req_resp, + calc_mocked_resp_len(&startup_req_resp))); + + // 3. Mock lt_init() -> lt_reboot() -> lt_get_tr01_mode() response. + LT_LOG_INFO("Mocking Get_Response response..."); + LT_TEST_ASSERT(LT_OK, lt_mock_hal_enqueue_response(&h->l2, lt_get_tr01_mode_mocked_response, + sizeof(lt_get_tr01_mode_mocked_response))); + + LT_LOG_INFO("Initializing handle"); + LT_TEST_ASSERT(LT_OK, lt_init(h)); + + LT_LOG_INFO("Deinitializing handle"); + LT_TEST_ASSERT(LT_OK, lt_deinit(h)); +} \ No newline at end of file diff --git a/tests/functional_mock/lt_test_mock_invalid_in_crc.c b/tests/functional_mock/lt_test_mock_invalid_in_crc.c index 391d84207..3f4760acc 100644 --- a/tests/functional_mock/lt_test_mock_invalid_in_crc.c +++ b/tests/functional_mock/lt_test_mock_invalid_in_crc.c @@ -3,7 +3,7 @@ * @brief Test for handling invalid CRC in TROPIC01 responses. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include "libtropic.h" @@ -25,7 +25,8 @@ void lt_test_mock_invalid_in_crc(lt_handle_t *h) lt_mock_hal_reset(&h->l2); LT_LOG_INFO("Mocking initialization..."); - LT_TEST_ASSERT(LT_OK, mock_init_communication(h, (uint8_t[]){0x00, 0x00, 0x00, 0x02})); // Version 2.0.0 + LT_TEST_ASSERT(LT_OK, + mock_init_communication(h, (uint8_t[]){0x00, 0x00, 0x00, 0x02})); // Version 2.0.0 LT_LOG_INFO("Initializing handle"); LT_TEST_ASSERT(LT_OK, lt_init(h)); @@ -38,8 +39,8 @@ void lt_test_mock_invalid_in_crc(lt_handle_t *h) .rsp_len = TR01_L2_GET_INFO_RISCV_FW_SIZE, .object = {0x00, 0x00, 0x00, 0x02, 0xFF, 0xFF} // dummy data with invalid CRC appended }; - LT_TEST_ASSERT( - LT_OK, lt_mock_hal_enqueue_response(&h->l2, (uint8_t *)&get_info_resp, calc_mocked_resp_len(&get_info_resp))); + LT_TEST_ASSERT(LT_OK, lt_mock_hal_enqueue_response(&h->l2, (uint8_t *)&get_info_resp, + calc_mocked_resp_len(&get_info_resp))); LT_LOG_INFO("Sending Get_Info request with invalid CRC in response..."); uint8_t dummy_out[TR01_L2_GET_INFO_RISCV_FW_SIZE]; diff --git a/tests/functional_mock/main.c.in b/tests/functional_mock/main.c.in index 10a991393..c16336d11 100644 --- a/tests/functional_mock/main.c.in +++ b/tests/functional_mock/main.c.in @@ -3,7 +3,7 @@ * @brief Main file for running functional mock tests. * @copyright Copyright (c) 2020-2026 Tropic Square s.r.o. * - * @license For the license see file LICENSE.txt file in the root directory of this source tree. + * @license For the license see LICENSE.md in the root directory of this source tree. */ #include diff --git a/ts_sw_setup.yml b/ts_sw_setup.yml index 8efcf7707..804d366db 100644 --- a/ts_sw_setup.yml +++ b/ts_sw_setup.yml @@ -5,7 +5,7 @@ texlive 2022 doxygen 1.10.0 # RISC-V tools -openocd v0.12.0 +openocd 2026_02_13_b4518ab cmake 3.23.2 # cppcheck 2.6 # cppcheck is not working for now